system stringclasses 7 values | input stringlengths 10 94.5k | output stringlengths 14 55.5k |
|---|---|---|
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | /******************************************************************************
*cr
*cr (C) Copyright 2010 The Board of Trustees of the
*cr University of Illinois
*cr All Rights Reserved
*cr
******************************************************************************/
#include <hip/hip_runtime.h>
#include <stdio.h>
__global__ void mysgemm(int m, int n, int k, const float *A, const float *B, float* C) {
/********************************************************************
*
* Compute C = A x B
* where A is a (m x k) matrix
* where B is a (k x n) matrix
* where C is a (m x n) matrix
*
********************************************************************/
// INSERT KERNEL CODE HERE
//Compute matrix C
int ROW = blockIdx.y * blockDim.y + threadIdx.y;
int COL = blockIdx.x * blockDim.x + threadIdx.x;
float SUM = 0;
if (COL < n && ROW < m)
{
for(unsigned int i = 0; i < k; ++i)
{
SUM += A[ROW * k + i] * B[i * n + COL];
}
C[ROW * n + COL] = SUM;
}
}
void basicSgemm(char transa, char transb, int m, int n, int k, float alpha, const float *A, int lda, const float *B, int ldb, float beta, float *C, int ldc)
{
if ((transa != 'N') && (transa != 'n')) {
printf("unsupported value of 'transa'\n");
return;
}
if ((transb != 'N') && (transb != 'n')) {
printf("unsupported value of 'transb'\n");
return;
}
if ((alpha - 1.0f > 1e-10) || (alpha - 1.0f < -1e-10)) {
printf("unsupported value of alpha\n");
return;
}
if ((beta - 0.0f > 1e-10) || (beta - 0.0f < -1e-10)) {
printf("unsupported value of beta\n");
return;
}
// Initialize thread block and kernel grid dimensions ---------------------
const unsigned int BLOCK_SIZE = 16; // Use 16x16 thread blocks
//INSERT CODE HERE
unsigned int gridrows = ceil((m + BLOCK_SIZE - 1) / BLOCK_SIZE);
unsigned int gridcols = ceil((n + BLOCK_SIZE - 1) / BLOCK_SIZE);
dim3 dimBlock(BLOCK_SIZE, BLOCK_SIZE);
dim3 dimGrid(gridcols, gridrows);
// Invoke CUDA kernel -----------------------------------------------------
//INSERT CODE HERE
mysgemm<<<dimGrid, dimBlock>>>(m, n, k, A, B, C);
} | .text
.file "kernel.hip"
.globl _Z22__device_stub__mysgemmiiiPKfS0_Pf # -- Begin function _Z22__device_stub__mysgemmiiiPKfS0_Pf
.p2align 4, 0x90
.type _Z22__device_stub__mysgemmiiiPKfS0_Pf,@function
_Z22__device_stub__mysgemmiiiPKfS0_Pf: # @_Z22__device_stub__mysgemmiiiPKfS0_Pf
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 20(%rsp)
movl %esi, 16(%rsp)
movl %edx, 12(%rsp)
movq %rcx, 88(%rsp)
movq %r8, 80(%rsp)
movq %r9, 72(%rsp)
leaq 20(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 88(%rsp), %rax
movq %rax, 120(%rsp)
leaq 80(%rsp), %rax
movq %rax, 128(%rsp)
leaq 72(%rsp), %rax
movq %rax, 136(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z7mysgemmiiiPKfS0_Pf, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z22__device_stub__mysgemmiiiPKfS0_Pf, .Lfunc_end0-_Z22__device_stub__mysgemmiiiPKfS0_Pf
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z10basicSgemmcciiifPKfiS0_ifPfi
.LCPI1_0:
.long 0xbf800000 # float -1
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0
.LCPI1_1:
.quad 0x3ddb7cdfd9d7bdbb # double 1.0E-10
.LCPI1_2:
.quad 0xbddb7cdfd9d7bdbb # double -1.0E-10
.text
.globl _Z10basicSgemmcciiifPKfiS0_ifPfi
.p2align 4, 0x90
.type _Z10basicSgemmcciiifPKfiS0_ifPfi,@function
_Z10basicSgemmcciiifPKfiS0_ifPfi: # @_Z10basicSgemmcciiifPKfiS0_ifPfi
.cfi_startproc
# %bb.0:
andb $-33, %dil
cmpb $78, %dil
jne .LBB1_9
# %bb.1:
andb $-33, %sil
cmpb $78, %sil
jne .LBB1_10
# %bb.2:
addss .LCPI1_0(%rip), %xmm0
cvtss2sd %xmm0, %xmm2
ucomisd .LCPI1_1(%rip), %xmm2
ja .LBB1_11
# %bb.3:
movsd .LCPI1_2(%rip), %xmm0 # xmm0 = mem[0],zero
ucomisd %xmm2, %xmm0
ja .LBB1_11
# %bb.4:
cvtss2sd %xmm1, %xmm1
ucomisd .LCPI1_1(%rip), %xmm1
ja .LBB1_12
# %bb.5:
ucomisd %xmm1, %xmm0
ja .LBB1_12
# %bb.6:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $152, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %ecx, %ebx
movl %edx, %r14d
movl %r8d, %ebp
movq %r9, %r12
movq 232(%rsp), %r15
movq 216(%rsp), %r13
leal 15(%r14), %edi
shrl $4, %edi
leal 15(%rbx), %eax
shrl $4, %eax
shlq $32, %rdi
orq %rax, %rdi
movabsq $68719476752, %rdx # imm = 0x1000000010
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_8
# %bb.7:
movl %r14d, 20(%rsp)
movl %ebx, 16(%rsp)
movl %ebp, 12(%rsp)
movq %r12, 88(%rsp)
movq %r13, 80(%rsp)
movq %r15, 72(%rsp)
leaq 20(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 88(%rsp), %rax
movq %rax, 120(%rsp)
leaq 80(%rsp), %rax
movq %rax, 128(%rsp)
leaq 72(%rsp), %rax
movq %rax, 136(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z7mysgemmiiiPKfS0_Pf, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_8:
addq $152, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_9:
.cfi_restore %rbx
.cfi_restore %rbp
.cfi_restore %r12
.cfi_restore %r13
.cfi_restore %r14
.cfi_restore %r15
movl $.Lstr.3, %edi
jmp puts@PLT # TAILCALL
.LBB1_10:
movl $.Lstr.2, %edi
jmp puts@PLT # TAILCALL
.LBB1_11:
movl $.Lstr.1, %edi
jmp puts@PLT # TAILCALL
.LBB1_12:
movl $.Lstr, %edi
jmp puts@PLT # TAILCALL
.Lfunc_end1:
.size _Z10basicSgemmcciiifPKfiS0_ifPfi, .Lfunc_end1-_Z10basicSgemmcciiifPKfiS0_ifPfi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7mysgemmiiiPKfS0_Pf, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z7mysgemmiiiPKfS0_Pf,@object # @_Z7mysgemmiiiPKfS0_Pf
.section .rodata,"a",@progbits
.globl _Z7mysgemmiiiPKfS0_Pf
.p2align 3, 0x0
_Z7mysgemmiiiPKfS0_Pf:
.quad _Z22__device_stub__mysgemmiiiPKfS0_Pf
.size _Z7mysgemmiiiPKfS0_Pf, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z7mysgemmiiiPKfS0_Pf"
.size .L__unnamed_1, 22
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "unsupported value of beta"
.size .Lstr, 26
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "unsupported value of alpha"
.size .Lstr.1, 27
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "unsupported value of 'transb'"
.size .Lstr.2, 30
.type .Lstr.3,@object # @str.3
.Lstr.3:
.asciz "unsupported value of 'transa'"
.size .Lstr.3, 30
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__mysgemmiiiPKfS0_Pf
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7mysgemmiiiPKfS0_Pf
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z7mysgemmiiiPKfS0_Pf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e280000002500 */
/*0020*/ S2R R26, SR_TID.X ; /* 0x00000000001a7919 */
/* 0x000e280000002100 */
/*0030*/ S2R R17, SR_CTAID.Y ; /* 0x0000000000117919 */
/* 0x000e680000002600 */
/*0040*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e620000002200 */
/*0050*/ IMAD R0, R3, c[0x0][0x0], R26 ; /* 0x0000000003007a24 */
/* 0x001fca00078e021a */
/*0060*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x164], PT ; /* 0x0000590000007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R17, R17, c[0x0][0x4], R2 ; /* 0x0000010011117a24 */
/* 0x002fca00078e0202 */
/*0080*/ ISETP.GE.OR P0, PT, R17, c[0x0][0x160], P0 ; /* 0x0000580011007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ ISETP.NE.AND P0, PT, RZ, c[0x0][0x168], PT ; /* 0x00005a00ff007a0c */
/* 0x000fe20003f05270 */
/*00b0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00c0*/ HFMA2.MMA R25, -RZ, RZ, 0, 0 ; /* 0x00000000ff197435 */
/* 0x000fd600000001ff */
/*00d0*/ @!P0 BRA 0x4f0 ; /* 0x0000041000008947 */
/* 0x000fea0003800000 */
/*00e0*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff027624 */
/* 0x000fe200078e00ff */
/*00f0*/ MOV R25, RZ ; /* 0x000000ff00197202 */
/* 0x000fe20000000f00 */
/*0100*/ IMAD.MOV.U32 R19, RZ, RZ, RZ ; /* 0x000000ffff137224 */
/* 0x000fc600078e00ff */
/*0110*/ IADD3 R4, R2.reuse, -0x1, RZ ; /* 0xffffffff02047810 */
/* 0x040fe40007ffe0ff */
/*0120*/ LOP3.LUT R18, R2, 0x3, RZ, 0xc0, !PT ; /* 0x0000000302127812 */
/* 0x000fe400078ec0ff */
/*0130*/ ISETP.GE.U32.AND P1, PT, R4, 0x3, PT ; /* 0x000000030400780c */
/* 0x000fe40003f26070 */
/*0140*/ ISETP.NE.AND P0, PT, R18, RZ, PT ; /* 0x000000ff1200720c */
/* 0x000fd60003f05270 */
/*0150*/ @!P1 BRA 0x410 ; /* 0x000002b000009947 */
/* 0x000fea0003800000 */
/*0160*/ IADD3 R26, R26, c[0x0][0x164], RZ ; /* 0x000059001a1a7a10 */
/* 0x000fe20007ffe0ff */
/*0170*/ HFMA2.MMA R19, -RZ, RZ, 0, 0 ; /* 0x00000000ff137435 */
/* 0x000fe200000001ff */
/*0180*/ MOV R21, c[0x0][0x164] ; /* 0x0000590000157a02 */
/* 0x000fe20000000f00 */
/*0190*/ IMAD R23, R17, R2, 0x3 ; /* 0x0000000311177424 */
/* 0x000fe200078e0202 */
/*01a0*/ IADD3 R22, R18, -c[0x0][0x168], RZ ; /* 0x80005a0012167a10 */
/* 0x000fe20007ffe0ff */
/*01b0*/ IMAD R26, R3, c[0x0][0x0], R26 ; /* 0x00000000031a7a24 */
/* 0x000fe200078e021a */
/*01c0*/ MOV R24, R0 ; /* 0x0000000000187202 */
/* 0x000fe20000000f00 */
/*01d0*/ IMAD.MOV.U32 R25, RZ, RZ, RZ ; /* 0x000000ffff197224 */
/* 0x000fe400078e00ff */
/*01e0*/ IMAD R16, R21.reuse, 0x2, R0.reuse ; /* 0x0000000215107824 */
/* 0x140fe400078e0200 */
/*01f0*/ IMAD R20, R21, 0x3, R0 ; /* 0x0000000315147824 */
/* 0x000fc400078e0200 */
/*0200*/ IADD3 R28, R23, -0x3, RZ ; /* 0xfffffffd171c7810 */
/* 0x000fe40007ffe0ff */
/*0210*/ MOV R13, 0x4 ; /* 0x00000004000d7802 */
/* 0x000fc40000000f00 */
/*0220*/ IADD3 R4, R23.reuse, -0x2, RZ ; /* 0xfffffffe17047810 */
/* 0x040fe40007ffe0ff */
/*0230*/ IADD3 R8, R23, -0x1, RZ ; /* 0xffffffff17087810 */
/* 0x000fe20007ffe0ff */
/*0240*/ IMAD.WIDE.U32 R28, R28, R13, c[0x0][0x170] ; /* 0x00005c001c1c7625 */
/* 0x000fc800078e000d */
/*0250*/ IMAD.WIDE.U32 R14, R24, R13.reuse, c[0x0][0x178] ; /* 0x00005e00180e7625 */
/* 0x080fe400078e000d */
/*0260*/ LDG.E R28, [R28.64] ; /* 0x000000041c1c7981 */
/* 0x000ea4000c1e1900 */
/*0270*/ IMAD.WIDE.U32 R4, R4, R13.reuse, c[0x0][0x170] ; /* 0x00005c0004047625 */
/* 0x080fe400078e000d */
/*0280*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000ea4000c1e1900 */
/*0290*/ IMAD.WIDE.U32 R6, R26, R13.reuse, c[0x0][0x178] ; /* 0x00005e001a067625 */
/* 0x080fe400078e000d */
/*02a0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ee4000c1e1900 */
/*02b0*/ IMAD.WIDE.U32 R8, R8, R13, c[0x0][0x170] ; /* 0x00005c0008087625 */
/* 0x000fc400078e000d */
/*02c0*/ LDG.E R7, [R6.64] ; /* 0x0000000406077981 */
/* 0x000ee4000c1e1900 */
/*02d0*/ IMAD.WIDE.U32 R2, R16, R13.reuse, c[0x0][0x178] ; /* 0x00005e0010027625 */
/* 0x080fe400078e000d */
/*02e0*/ LDG.E R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x000f24000c1e1900 */
/*02f0*/ IMAD.WIDE.U32 R10, R23, R13.reuse, c[0x0][0x170] ; /* 0x00005c00170a7625 */
/* 0x080fe400078e000d */
/*0300*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000f24000c1e1900 */
/*0310*/ IMAD.WIDE.U32 R12, R20, R13, c[0x0][0x178] ; /* 0x00005e00140c7625 */
/* 0x000fc400078e000d */
/*0320*/ LDG.E R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x000f68000c1e1900 */
/*0330*/ LDG.E R12, [R12.64] ; /* 0x000000040c0c7981 */
/* 0x000f62000c1e1900 */
/*0340*/ IADD3 R19, R19, 0x4, RZ ; /* 0x0000000413137810 */
/* 0x000fe20007ffe0ff */
/*0350*/ IMAD R26, R21.reuse, 0x4, R26 ; /* 0x00000004151a7824 */
/* 0x040fe200078e021a */
/*0360*/ LEA R16, R21.reuse, R16, 0x2 ; /* 0x0000001015107211 */
/* 0x040fe200078e10ff */
/*0370*/ IMAD R20, R21.reuse, 0x4, R20 ; /* 0x0000000415147824 */
/* 0x040fe200078e0214 */
/*0380*/ LEA R24, R21, R24, 0x2 ; /* 0x0000001815187211 */
/* 0x000fe400078e10ff */
/*0390*/ IADD3 R23, R23, 0x4, RZ ; /* 0x0000000417177810 */
/* 0x000fe20007ffe0ff */
/*03a0*/ FFMA R14, R14, R28, R25 ; /* 0x0000001c0e0e7223 */
/* 0x004fc80000000019 */
/*03b0*/ FFMA R5, R7, R4, R14 ; /* 0x0000000407057223 */
/* 0x008fe2000000000e */
/*03c0*/ IADD3 R4, R22, R19, RZ ; /* 0x0000001316047210 */
/* 0x000fc80007ffe0ff */
/*03d0*/ ISETP.NE.AND P1, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fe20003f25270 */
/*03e0*/ FFMA R5, R2, R8, R5 ; /* 0x0000000802057223 */
/* 0x010fc80000000005 */
/*03f0*/ FFMA R25, R12, R10, R5 ; /* 0x0000000a0c197223 */
/* 0x020fd00000000005 */
/*0400*/ @P1 BRA 0x200 ; /* 0xfffffdf000001947 */
/* 0x000fea000383ffff */
/*0410*/ @!P0 BRA 0x4f0 ; /* 0x000000d000008947 */
/* 0x000fea0003800000 */
/*0420*/ IMAD R6, R19, c[0x0][0x164], R0 ; /* 0x0000590013067a24 */
/* 0x000fe400078e0200 */
/*0430*/ IMAD R19, R17, c[0x0][0x168], R19 ; /* 0x00005a0011137a24 */
/* 0x000fe400078e0213 */
/*0440*/ HFMA2.MMA R4, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff047435 */
/* 0x000fd400000001ff */
/*0450*/ IMAD.WIDE.U32 R2, R19, R4, c[0x0][0x170] ; /* 0x00005c0013027625 */
/* 0x000fc800078e0004 */
/*0460*/ IMAD.WIDE.U32 R4, R6, R4, c[0x0][0x178] ; /* 0x00005e0006047625 */
/* 0x000fe400078e0004 */
/*0470*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*0480*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea2000c1e1900 */
/*0490*/ IADD3 R18, R18, -0x1, RZ ; /* 0xffffffff12127810 */
/* 0x000fe40007ffe0ff */
/*04a0*/ IADD3 R19, R19, 0x1, RZ ; /* 0x0000000113137810 */
/* 0x000fe40007ffe0ff */
/*04b0*/ ISETP.NE.AND P0, PT, R18, RZ, PT ; /* 0x000000ff1200720c */
/* 0x000fc40003f05270 */
/*04c0*/ IADD3 R6, R6, c[0x0][0x164], RZ ; /* 0x0000590006067a10 */
/* 0x000fe20007ffe0ff */
/*04d0*/ FFMA R25, R4, R2, R25 ; /* 0x0000000204197223 */
/* 0x004fd40000000019 */
/*04e0*/ @P0 BRA 0x440 ; /* 0xffffff5000000947 */
/* 0x000fea000383ffff */
/*04f0*/ MOV R3, 0x4 ; /* 0x0000000400037802 */
/* 0x000fe20000000f00 */
/*0500*/ IMAD R2, R17, c[0x0][0x164], R0 ; /* 0x0000590011027a24 */
/* 0x000fc800078e0200 */
/*0510*/ IMAD.WIDE R2, R2, R3, c[0x0][0x180] ; /* 0x0000600002027625 */
/* 0x000fca00078e0203 */
/*0520*/ STG.E [R2.64], R25 ; /* 0x0000001902007986 */
/* 0x000fe2000c101904 */
/*0530*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0540*/ BRA 0x540; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0550*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0560*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0570*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0580*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0590*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z7mysgemmiiiPKfS0_Pf
.globl _Z7mysgemmiiiPKfS0_Pf
.p2align 8
.type _Z7mysgemmiiiPKfS0_Pf,@function
_Z7mysgemmiiiPKfS0_Pf:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x34
s_load_b64 s[2:3], s[0:1], 0x0
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_lshr_b32 s5, s4, 16
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[0:1], null, s14, s4, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s5, v[3:4]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_gt_i32_e32 vcc_lo, s3, v0
v_cmp_gt_i32_e64 s2, s2, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, s2, vcc_lo
s_and_saveexec_b32 s4, s2
s_cbranch_execz .LBB0_6
s_load_b32 s2, s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_cmp_eq_u32 s2, 0
s_cbranch_scc1 .LBB0_4
s_load_b128 s[4:7], s[0:1], 0x10
v_mul_lo_u32 v2, v1, s2
v_mov_b32_e32 v6, 0
v_mov_b32_e32 v4, v0
.p2align 6
.LBB0_3:
v_mov_b32_e32 v3, 0
s_add_i32 s2, s2, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_cmp_eq_u32 s2, 0
v_mov_b32_e32 v5, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[9:10], 2, v[4:5]
v_add_nc_u32_e32 v4, s3, v4
v_lshlrev_b64 v[7:8], 2, v[2:3]
v_add_nc_u32_e32 v2, 1, v2
s_waitcnt lgkmcnt(0)
v_add_co_u32 v7, vcc_lo, s4, v7
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v8, vcc_lo, s5, v8, vcc_lo
v_add_co_u32 v9, vcc_lo, s6, v9
v_add_co_ci_u32_e32 v10, vcc_lo, s7, v10, vcc_lo
global_load_b32 v3, v[7:8], off
global_load_b32 v5, v[9:10], off
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v6, v3, v5
s_cbranch_scc0 .LBB0_3
s_branch .LBB0_5
.LBB0_4:
v_mov_b32_e32 v6, 0
.LBB0_5:
s_load_b64 s[0:1], s[0:1], 0x20
v_mad_u64_u32 v[2:3], null, v1, s3, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[0:1], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v6, off
.LBB0_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7mysgemmiiiPKfS0_Pf
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 11
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z7mysgemmiiiPKfS0_Pf, .Lfunc_end0-_Z7mysgemmiiiPKfS0_Pf
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .offset: 8
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7mysgemmiiiPKfS0_Pf
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z7mysgemmiiiPKfS0_Pf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 11
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0014c1fc_00000000-6_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z35__device_stub__Z7mysgemmiiiPKfS0_PfiiiPKfS0_Pf
.type _Z35__device_stub__Z7mysgemmiiiPKfS0_PfiiiPKfS0_Pf, @function
_Z35__device_stub__Z7mysgemmiiiPKfS0_PfiiiPKfS0_Pf:
.LFB2082:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movl %edi, 44(%rsp)
movl %esi, 40(%rsp)
movl %edx, 36(%rsp)
movq %rcx, 24(%rsp)
movq %r8, 16(%rsp)
movq %r9, 8(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 44(%rsp), %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rax
movq %rax, 120(%rsp)
leaq 36(%rsp), %rax
movq %rax, 128(%rsp)
leaq 24(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z7mysgemmiiiPKfS0_Pf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z35__device_stub__Z7mysgemmiiiPKfS0_PfiiiPKfS0_Pf, .-_Z35__device_stub__Z7mysgemmiiiPKfS0_PfiiiPKfS0_Pf
.globl _Z7mysgemmiiiPKfS0_Pf
.type _Z7mysgemmiiiPKfS0_Pf, @function
_Z7mysgemmiiiPKfS0_Pf:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z7mysgemmiiiPKfS0_PfiiiPKfS0_Pf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z7mysgemmiiiPKfS0_Pf, .-_Z7mysgemmiiiPKfS0_Pf
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "unsupported value of 'transa'\n"
.align 8
.LC1:
.string "unsupported value of 'transb'\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC5:
.string "unsupported value of alpha\n"
.LC6:
.string "unsupported value of beta\n"
.text
.globl _Z10basicSgemmcciiifPKfiS0_ifPfi
.type _Z10basicSgemmcciiifPKfiS0_ifPfi, @function
_Z10basicSgemmcciiifPKfiS0_ifPfi:
.LFB2057:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $40, %rsp
.cfi_def_cfa_offset 80
andl $-33, %edi
cmpb $78, %dil
jne .L26
movl %edx, %ebx
movl %ecx, %ebp
movl %r8d, %r12d
movq %r9, %r13
andl $-33, %esi
cmpb $78, %sil
jne .L27
subss .LC2(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
comisd .LC3(%rip), %xmm0
ja .L15
movsd .LC4(%rip), %xmm2
comisd %xmm0, %xmm2
ja .L15
cvtss2sd %xmm1, %xmm1
comisd .LC3(%rip), %xmm1
ja .L18
movsd .LC4(%rip), %xmm0
comisd %xmm1, %xmm0
jbe .L24
.L18:
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L11
.L26:
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L11
.L27:
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L11
.L15:
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L11:
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L24:
.cfi_restore_state
movl $16, 8(%rsp)
movl $16, 12(%rsp)
leal 15(%rcx), %eax
shrl $4, %eax
movl %eax, 20(%rsp)
leal 15(%rdx), %eax
shrl $4, %eax
movl %eax, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 8(%rsp), %rdx
movl $1, %ecx
movq 20(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L11
movq 104(%rsp), %r9
movq 88(%rsp), %r8
movq %r13, %rcx
movl %r12d, %edx
movl %ebp, %esi
movl %ebx, %edi
call _Z35__device_stub__Z7mysgemmiiiPKfS0_PfiiiPKfS0_Pf
jmp .L11
.cfi_endproc
.LFE2057:
.size _Z10basicSgemmcciiifPKfiS0_ifPfi, .-_Z10basicSgemmcciiifPKfiS0_ifPfi
.section .rodata.str1.1
.LC7:
.string "_Z7mysgemmiiiPKfS0_Pf"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _Z7mysgemmiiiPKfS0_Pf(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC2:
.long 1065353216
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC3:
.long -640172613
.long 1037794527
.align 8
.LC4:
.long -640172613
.long -1109689121
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "kernel.hip"
.globl _Z22__device_stub__mysgemmiiiPKfS0_Pf # -- Begin function _Z22__device_stub__mysgemmiiiPKfS0_Pf
.p2align 4, 0x90
.type _Z22__device_stub__mysgemmiiiPKfS0_Pf,@function
_Z22__device_stub__mysgemmiiiPKfS0_Pf: # @_Z22__device_stub__mysgemmiiiPKfS0_Pf
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 20(%rsp)
movl %esi, 16(%rsp)
movl %edx, 12(%rsp)
movq %rcx, 88(%rsp)
movq %r8, 80(%rsp)
movq %r9, 72(%rsp)
leaq 20(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 88(%rsp), %rax
movq %rax, 120(%rsp)
leaq 80(%rsp), %rax
movq %rax, 128(%rsp)
leaq 72(%rsp), %rax
movq %rax, 136(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z7mysgemmiiiPKfS0_Pf, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z22__device_stub__mysgemmiiiPKfS0_Pf, .Lfunc_end0-_Z22__device_stub__mysgemmiiiPKfS0_Pf
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z10basicSgemmcciiifPKfiS0_ifPfi
.LCPI1_0:
.long 0xbf800000 # float -1
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0
.LCPI1_1:
.quad 0x3ddb7cdfd9d7bdbb # double 1.0E-10
.LCPI1_2:
.quad 0xbddb7cdfd9d7bdbb # double -1.0E-10
.text
.globl _Z10basicSgemmcciiifPKfiS0_ifPfi
.p2align 4, 0x90
.type _Z10basicSgemmcciiifPKfiS0_ifPfi,@function
_Z10basicSgemmcciiifPKfiS0_ifPfi: # @_Z10basicSgemmcciiifPKfiS0_ifPfi
.cfi_startproc
# %bb.0:
andb $-33, %dil
cmpb $78, %dil
jne .LBB1_9
# %bb.1:
andb $-33, %sil
cmpb $78, %sil
jne .LBB1_10
# %bb.2:
addss .LCPI1_0(%rip), %xmm0
cvtss2sd %xmm0, %xmm2
ucomisd .LCPI1_1(%rip), %xmm2
ja .LBB1_11
# %bb.3:
movsd .LCPI1_2(%rip), %xmm0 # xmm0 = mem[0],zero
ucomisd %xmm2, %xmm0
ja .LBB1_11
# %bb.4:
cvtss2sd %xmm1, %xmm1
ucomisd .LCPI1_1(%rip), %xmm1
ja .LBB1_12
# %bb.5:
ucomisd %xmm1, %xmm0
ja .LBB1_12
# %bb.6:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $152, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %ecx, %ebx
movl %edx, %r14d
movl %r8d, %ebp
movq %r9, %r12
movq 232(%rsp), %r15
movq 216(%rsp), %r13
leal 15(%r14), %edi
shrl $4, %edi
leal 15(%rbx), %eax
shrl $4, %eax
shlq $32, %rdi
orq %rax, %rdi
movabsq $68719476752, %rdx # imm = 0x1000000010
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_8
# %bb.7:
movl %r14d, 20(%rsp)
movl %ebx, 16(%rsp)
movl %ebp, 12(%rsp)
movq %r12, 88(%rsp)
movq %r13, 80(%rsp)
movq %r15, 72(%rsp)
leaq 20(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 88(%rsp), %rax
movq %rax, 120(%rsp)
leaq 80(%rsp), %rax
movq %rax, 128(%rsp)
leaq 72(%rsp), %rax
movq %rax, 136(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z7mysgemmiiiPKfS0_Pf, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_8:
addq $152, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_9:
.cfi_restore %rbx
.cfi_restore %rbp
.cfi_restore %r12
.cfi_restore %r13
.cfi_restore %r14
.cfi_restore %r15
movl $.Lstr.3, %edi
jmp puts@PLT # TAILCALL
.LBB1_10:
movl $.Lstr.2, %edi
jmp puts@PLT # TAILCALL
.LBB1_11:
movl $.Lstr.1, %edi
jmp puts@PLT # TAILCALL
.LBB1_12:
movl $.Lstr, %edi
jmp puts@PLT # TAILCALL
.Lfunc_end1:
.size _Z10basicSgemmcciiifPKfiS0_ifPfi, .Lfunc_end1-_Z10basicSgemmcciiifPKfiS0_ifPfi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7mysgemmiiiPKfS0_Pf, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z7mysgemmiiiPKfS0_Pf,@object # @_Z7mysgemmiiiPKfS0_Pf
.section .rodata,"a",@progbits
.globl _Z7mysgemmiiiPKfS0_Pf
.p2align 3, 0x0
_Z7mysgemmiiiPKfS0_Pf:
.quad _Z22__device_stub__mysgemmiiiPKfS0_Pf
.size _Z7mysgemmiiiPKfS0_Pf, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z7mysgemmiiiPKfS0_Pf"
.size .L__unnamed_1, 22
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "unsupported value of beta"
.size .Lstr, 26
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "unsupported value of alpha"
.size .Lstr.1, 27
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "unsupported value of 'transb'"
.size .Lstr.2, 30
.type .Lstr.3,@object # @str.3
.Lstr.3:
.asciz "unsupported value of 'transa'"
.size .Lstr.3, 30
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__mysgemmiiiPKfS0_Pf
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7mysgemmiiiPKfS0_Pf
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include<stdio.h>
#include<cuda.h>
__global__ void oddeven(int* x,int I,int n)
{
int id=blockIdx.x;
if(I==0 && ((id*2+1)< n)){
if(x[id*2]>x[id*2+1]){
int X=x[id*2];
x[id*2]=x[id*2+1];
x[id*2+1]=X;
}
}
if(I==1 && ((id*2+2)< n)){
if(x[id*2+1]>x[id*2+2]){
int X=x[id*2+1];
x[id*2+1]=x[id*2+2];
x[id*2+2]=X;
}
}
}
int main()
{
int a[100],n,c[100],i;
int *d;
printf("Enter how many elements of first array:");
scanf("%d",&n);
printf("Enter No.\n");
for(i=0; i<n; i++)
{
scanf("%d",&a[i]);
}
cudaMalloc((void**)&d, n*sizeof(int));
cudaMemcpy(d,a,n*sizeof(int),cudaMemcpyHostToDevice);
for(i=0;i<n;i++){
//int size=n/2;
oddeven<<<n/2,1>>>(d,i%2,n);
}
printf("\n");
cudaMemcpy(c,d,n*sizeof(int), cudaMemcpyDeviceToHost);
printf("Sorted Array is:\t");
for(i=0; i<n; i++)
{
printf("%d\t",c[i]);
}
cudaFree(d);
return 0;
} | code for sm_80
Function : _Z7oddevenPiii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e220000002500 */
/*0020*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff047624 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ IMAD.SHL.U32 R2, R2, 0x2, RZ ; /* 0x0000000202027824 */
/* 0x001fca00078e00ff */
/*0050*/ IADD3 R0, R2.reuse, 0x1, RZ ; /* 0x0000000102007810 */
/* 0x040fe40007ffe0ff */
/*0060*/ IADD3 R3, R2, 0x2, RZ ; /* 0x0000000202037810 */
/* 0x000fe40007ffe0ff */
/*0070*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x16c], PT ; /* 0x00005b0000007a0c */
/* 0x000fe40003f06270 */
/*0080*/ ISETP.GE.AND P1, PT, R3, c[0x0][0x16c], PT ; /* 0x00005b0003007a0c */
/* 0x000fe20003f26270 */
/*0090*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fe200078e00ff */
/*00a0*/ ISETP.NE.OR P0, PT, RZ, c[0x0][0x168], P0 ; /* 0x00005a00ff007a0c */
/* 0x000fe40000705670 */
/*00b0*/ ISETP.NE.OR P1, PT, R4, 0x1, P1 ; /* 0x000000010400780c */
/* 0x000fe20000f25670 */
/*00c0*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fd400078e0203 */
/*00d0*/ @P0 BRA 0x130 ; /* 0x0000005000000947 */
/* 0x000fea0003800000 */
/*00e0*/ LDG.E R5, [R2.64] ; /* 0x0000000402057981 */
/* 0x000ea8000c1e1900 */
/*00f0*/ LDG.E R0, [R2.64+0x4] ; /* 0x0000040402007981 */
/* 0x000ea4000c1e1900 */
/*0100*/ ISETP.GT.AND P0, PT, R5, R0, PT ; /* 0x000000000500720c */
/* 0x004fda0003f04270 */
/*0110*/ @P0 STG.E [R2.64], R0 ; /* 0x0000000002000986 */
/* 0x0001e8000c101904 */
/*0120*/ @P0 STG.E [R2.64+0x4], R5 ; /* 0x0000040502000986 */
/* 0x0001e4000c101904 */
/*0130*/ @P1 EXIT ; /* 0x000000000000194d */
/* 0x000fea0003800000 */
/*0140*/ LDG.E R5, [R2.64+0x8] ; /* 0x0000080402057981 */
/* 0x001ea8000c1e1900 */
/*0150*/ LDG.E R0, [R2.64+0x4] ; /* 0x0000040402007981 */
/* 0x000ea4000c1e1900 */
/*0160*/ ISETP.GT.AND P0, PT, R0, R5, PT ; /* 0x000000050000720c */
/* 0x004fda0003f04270 */
/*0170*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0180*/ STG.E [R2.64+0x4], R5 ; /* 0x0000040502007986 */
/* 0x000fe8000c101904 */
/*0190*/ STG.E [R2.64+0x8], R0 ; /* 0x0000080002007986 */
/* 0x000fe2000c101904 */
/*01a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01b0*/ BRA 0x1b0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include<stdio.h>
#include<cuda.h>
__global__ void oddeven(int* x,int I,int n)
{
int id=blockIdx.x;
if(I==0 && ((id*2+1)< n)){
if(x[id*2]>x[id*2+1]){
int X=x[id*2];
x[id*2]=x[id*2+1];
x[id*2+1]=X;
}
}
if(I==1 && ((id*2+2)< n)){
if(x[id*2+1]>x[id*2+2]){
int X=x[id*2+1];
x[id*2+1]=x[id*2+2];
x[id*2+2]=X;
}
}
}
int main()
{
int a[100],n,c[100],i;
int *d;
printf("Enter how many elements of first array:");
scanf("%d",&n);
printf("Enter No.\n");
for(i=0; i<n; i++)
{
scanf("%d",&a[i]);
}
cudaMalloc((void**)&d, n*sizeof(int));
cudaMemcpy(d,a,n*sizeof(int),cudaMemcpyHostToDevice);
for(i=0;i<n;i++){
//int size=n/2;
oddeven<<<n/2,1>>>(d,i%2,n);
}
printf("\n");
cudaMemcpy(c,d,n*sizeof(int), cudaMemcpyDeviceToHost);
printf("Sorted Array is:\t");
for(i=0; i<n; i++)
{
printf("%d\t",c[i]);
}
cudaFree(d);
return 0;
} | .file "tmpxft_00119c76_00000000-6_oddeven.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z28__device_stub__Z7oddevenPiiiPiii
.type _Z28__device_stub__Z7oddevenPiiiPiii, @function
_Z28__device_stub__Z7oddevenPiiiPiii:
.LFB2082:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z7oddevenPiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z28__device_stub__Z7oddevenPiiiPiii, .-_Z28__device_stub__Z7oddevenPiiiPiii
.globl _Z7oddevenPiii
.type _Z7oddevenPiii, @function
_Z7oddevenPiii:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z28__device_stub__Z7oddevenPiiiPiii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z7oddevenPiii, .-_Z7oddevenPiii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "Enter how many elements of first array:"
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "%d"
.LC2:
.string "Enter No.\n"
.LC3:
.string "\n"
.LC4:
.string "Sorted Array is:\t"
.LC5:
.string "%d\t"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $864, %rsp
.cfi_def_cfa_offset 896
movq %fs:40, %rax
movq %rax, 856(%rsp)
xorl %eax, %eax
leaq .LC0(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
leaq 12(%rsp), %rsi
leaq .LC1(%rip), %rdi
movl $0, %eax
call __isoc23_scanf@PLT
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 12(%rsp), %esi
testl %esi, %esi
jle .L12
leaq 48(%rsp), %rbp
movl $0, %ebx
leaq .LC1(%rip), %r12
.L13:
movq %rbp, %rsi
movq %r12, %rdi
movl $0, %eax
call __isoc23_scanf@PLT
addl $1, %ebx
movl 12(%rsp), %esi
addq $4, %rbp
cmpl %ebx, %esi
jg .L13
.L12:
movslq %esi, %rsi
salq $2, %rsi
leaq 16(%rsp), %rdi
call cudaMalloc@PLT
movslq 12(%rsp), %rdx
salq $2, %rdx
leaq 48(%rsp), %rsi
movl $1, %ecx
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl 12(%rsp), %edx
testl %edx, %edx
jle .L14
movl $0, %ebx
jmp .L16
.L15:
addl $1, %ebx
movl 12(%rsp), %edx
cmpl %ebx, %edx
jle .L14
.L16:
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl %edx, %eax
shrl $31, %eax
addl %edx, %eax
sarl %eax
movl %eax, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L15
movl %ebx, %eax
shrl $31, %eax
leal (%rbx,%rax), %esi
andl $1, %esi
subl %eax, %esi
movl 12(%rsp), %edx
movq 16(%rsp), %rdi
call _Z28__device_stub__Z7oddevenPiiiPiii
jmp .L15
.L14:
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movslq 12(%rsp), %rdx
salq $2, %rdx
leaq 448(%rsp), %rdi
movl $2, %ecx
movq 16(%rsp), %rsi
call cudaMemcpy@PLT
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
cmpl $0, 12(%rsp)
jle .L17
movl $0, %ebx
leaq .LC5(%rip), %rbp
.L18:
movl 448(%rsp,%rbx,4), %edx
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpl %ebx, 12(%rsp)
jg .L18
.L17:
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 856(%rsp), %rax
subq %fs:40, %rax
jne .L24
movl $0, %eax
addq $864, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L24:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC6:
.string "_Z7oddevenPiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _Z7oddevenPiii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include<stdio.h>
#include<cuda.h>
__global__ void oddeven(int* x,int I,int n)
{
int id=blockIdx.x;
if(I==0 && ((id*2+1)< n)){
if(x[id*2]>x[id*2+1]){
int X=x[id*2];
x[id*2]=x[id*2+1];
x[id*2+1]=X;
}
}
if(I==1 && ((id*2+2)< n)){
if(x[id*2+1]>x[id*2+2]){
int X=x[id*2+1];
x[id*2+1]=x[id*2+2];
x[id*2+2]=X;
}
}
}
int main()
{
int a[100],n,c[100],i;
int *d;
printf("Enter how many elements of first array:");
scanf("%d",&n);
printf("Enter No.\n");
for(i=0; i<n; i++)
{
scanf("%d",&a[i]);
}
cudaMalloc((void**)&d, n*sizeof(int));
cudaMemcpy(d,a,n*sizeof(int),cudaMemcpyHostToDevice);
for(i=0;i<n;i++){
//int size=n/2;
oddeven<<<n/2,1>>>(d,i%2,n);
}
printf("\n");
cudaMemcpy(c,d,n*sizeof(int), cudaMemcpyDeviceToHost);
printf("Sorted Array is:\t");
for(i=0; i<n; i++)
{
printf("%d\t",c[i]);
}
cudaFree(d);
return 0;
} | #include<stdio.h>
#include<hip/hip_runtime.h>
__global__ void oddeven(int* x,int I,int n)
{
int id=blockIdx.x;
if(I==0 && ((id*2+1)< n)){
if(x[id*2]>x[id*2+1]){
int X=x[id*2];
x[id*2]=x[id*2+1];
x[id*2+1]=X;
}
}
if(I==1 && ((id*2+2)< n)){
if(x[id*2+1]>x[id*2+2]){
int X=x[id*2+1];
x[id*2+1]=x[id*2+2];
x[id*2+2]=X;
}
}
}
int main()
{
int a[100],n,c[100],i;
int *d;
printf("Enter how many elements of first array:");
scanf("%d",&n);
printf("Enter No.\n");
for(i=0; i<n; i++)
{
scanf("%d",&a[i]);
}
hipMalloc((void**)&d, n*sizeof(int));
hipMemcpy(d,a,n*sizeof(int),hipMemcpyHostToDevice);
for(i=0;i<n;i++){
//int size=n/2;
oddeven<<<n/2,1>>>(d,i%2,n);
}
printf("\n");
hipMemcpy(c,d,n*sizeof(int), hipMemcpyDeviceToHost);
printf("Sorted Array is:\t");
for(i=0; i<n; i++)
{
printf("%d\t",c[i]);
}
hipFree(d);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include<stdio.h>
#include<hip/hip_runtime.h>
__global__ void oddeven(int* x,int I,int n)
{
int id=blockIdx.x;
if(I==0 && ((id*2+1)< n)){
if(x[id*2]>x[id*2+1]){
int X=x[id*2];
x[id*2]=x[id*2+1];
x[id*2+1]=X;
}
}
if(I==1 && ((id*2+2)< n)){
if(x[id*2+1]>x[id*2+2]){
int X=x[id*2+1];
x[id*2+1]=x[id*2+2];
x[id*2+2]=X;
}
}
}
int main()
{
int a[100],n,c[100],i;
int *d;
printf("Enter how many elements of first array:");
scanf("%d",&n);
printf("Enter No.\n");
for(i=0; i<n; i++)
{
scanf("%d",&a[i]);
}
hipMalloc((void**)&d, n*sizeof(int));
hipMemcpy(d,a,n*sizeof(int),hipMemcpyHostToDevice);
for(i=0;i<n;i++){
//int size=n/2;
oddeven<<<n/2,1>>>(d,i%2,n);
}
printf("\n");
hipMemcpy(c,d,n*sizeof(int), hipMemcpyDeviceToHost);
printf("Sorted Array is:\t");
for(i=0; i<n; i++)
{
printf("%d\t",c[i]);
}
hipFree(d);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z7oddevenPiii
.globl _Z7oddevenPiii
.p2align 8
.type _Z7oddevenPiii,@function
_Z7oddevenPiii:
s_clause 0x1
s_load_b32 s7, s[0:1], 0x8
s_load_b64 s[2:3], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s7, 1
s_cbranch_scc1 .LBB0_2
s_cmp_eq_u32 s7, 1
s_mov_b32 s5, 0
s_cselect_b32 s4, -1, 0
s_branch .LBB0_3
.LBB0_2:
s_mov_b32 s5, -1
s_mov_b32 s4, 0
.LBB0_3:
s_load_b32 s6, s[0:1], 0xc
s_and_not1_b32 vcc_lo, exec_lo, s5
s_cbranch_vccnz .LBB0_5
s_cmp_eq_u32 s7, 0
s_cbranch_scc1 .LBB0_9
.LBB0_5:
s_and_b32 vcc_lo, exec_lo, s4
s_cbranch_vccz .LBB0_13
.LBB0_6:
s_lshl_b32 s0, s15, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_add_i32 s4, s0, 2
s_waitcnt lgkmcnt(0)
s_cmp_ge_i32 s4, s6
s_cbranch_scc1 .LBB0_13
s_or_b32 s0, s0, 1
v_mov_b32_e32 v0, 0
s_ashr_i32 s1, s0, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_lshl_b64 s[0:1], s[0:1], 2
s_add_u32 s0, s2, s0
s_addc_u32 s1, s3, s1
s_ashr_i32 s5, s4, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_lshl_b64 s[4:5], s[4:5], 2
s_add_u32 s2, s2, s4
s_addc_u32 s3, s3, s5
s_clause 0x1
global_load_b32 v1, v0, s[0:1]
global_load_b32 v2, v0, s[2:3]
s_waitcnt vmcnt(0)
v_cmp_le_i32_e32 vcc_lo, v1, v2
s_cbranch_vccnz .LBB0_13
s_clause 0x1
global_store_b32 v0, v2, s[0:1]
global_store_b32 v0, v1, s[2:3]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.LBB0_9:
s_lshl_b32 s0, s15, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 s4, s0, 1
s_waitcnt lgkmcnt(0)
s_cmp_ge_i32 s4, s6
s_cbranch_scc1 .LBB0_12
s_ashr_i32 s1, s0, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_lshl_b64 s[0:1], s[0:1], 2
s_add_u32 s0, s2, s0
s_addc_u32 s1, s3, s1
s_ashr_i32 s5, s4, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_lshl_b64 s[4:5], s[4:5], 2
s_add_u32 s4, s2, s4
s_addc_u32 s5, s3, s5
s_clause 0x1
s_load_b32 s8, s[0:1], 0x0
s_load_b32 s9, s[4:5], 0x0
s_waitcnt lgkmcnt(0)
s_cmp_le_i32 s8, s9
s_cbranch_scc1 .LBB0_12
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s9
v_mov_b32_e32 v2, s8
s_clause 0x1
global_store_b32 v0, v1, s[0:1]
global_store_b32 v0, v2, s[4:5]
.LBB0_12:
s_cmp_eq_u32 s7, 1
s_cselect_b32 s4, -1, 0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 vcc_lo, exec_lo, s4
s_cbranch_vccnz .LBB0_6
.LBB0_13:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7oddevenPiii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 16
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z7oddevenPiii, .Lfunc_end0-_Z7oddevenPiii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 16
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7oddevenPiii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z7oddevenPiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include<stdio.h>
#include<hip/hip_runtime.h>
__global__ void oddeven(int* x,int I,int n)
{
int id=blockIdx.x;
if(I==0 && ((id*2+1)< n)){
if(x[id*2]>x[id*2+1]){
int X=x[id*2];
x[id*2]=x[id*2+1];
x[id*2+1]=X;
}
}
if(I==1 && ((id*2+2)< n)){
if(x[id*2+1]>x[id*2+2]){
int X=x[id*2+1];
x[id*2+1]=x[id*2+2];
x[id*2+2]=X;
}
}
}
int main()
{
int a[100],n,c[100],i;
int *d;
printf("Enter how many elements of first array:");
scanf("%d",&n);
printf("Enter No.\n");
for(i=0; i<n; i++)
{
scanf("%d",&a[i]);
}
hipMalloc((void**)&d, n*sizeof(int));
hipMemcpy(d,a,n*sizeof(int),hipMemcpyHostToDevice);
for(i=0;i<n;i++){
//int size=n/2;
oddeven<<<n/2,1>>>(d,i%2,n);
}
printf("\n");
hipMemcpy(c,d,n*sizeof(int), hipMemcpyDeviceToHost);
printf("Sorted Array is:\t");
for(i=0; i<n; i++)
{
printf("%d\t",c[i]);
}
hipFree(d);
return 0;
} | .text
.file "oddeven.hip"
.globl _Z22__device_stub__oddevenPiii # -- Begin function _Z22__device_stub__oddevenPiii
.p2align 4, 0x90
.type _Z22__device_stub__oddevenPiii,@function
_Z22__device_stub__oddevenPiii: # @_Z22__device_stub__oddevenPiii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z7oddevenPiii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z22__device_stub__oddevenPiii, .Lfunc_end0-_Z22__device_stub__oddevenPiii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $888, %rsp # imm = 0x378
.cfi_def_cfa_offset 944
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $.L.str, %edi
xorl %eax, %eax
callq printf
leaq 4(%rsp), %rsi
movl $.L.str.1, %edi
xorl %eax, %eax
callq __isoc23_scanf
movl $.Lstr, %edi
callq puts@PLT
movl 4(%rsp), %eax
testl %eax, %eax
jle .LBB1_3
# %bb.1: # %.lr.ph.preheader
leaq 480(%rsp), %rbx
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl $.L.str.1, %edi
movq %rbx, %rsi
xorl %eax, %eax
callq __isoc23_scanf
incq %r14
movslq 4(%rsp), %rax
addq $4, %rbx
cmpq %rax, %r14
jl .LBB1_2
.LBB1_3: # %._crit_edge
movslq %eax, %rsi
shlq $2, %rsi
leaq 8(%rsp), %rdi
callq hipMalloc
movq 8(%rsp), %rdi
movslq 4(%rsp), %rdx
shlq $2, %rdx
leaq 480(%rsp), %rsi
movl $1, %ecx
callq hipMemcpy
movl 4(%rsp), %eax
testl %eax, %eax
jle .LBB1_8
# %bb.4: # %.lr.ph19
xorl %r14d, %r14d
movabsq $4294967296, %r15 # imm = 0x100000000
leaq 1(%r15), %rbx
leaq 32(%rsp), %r12
leaq 24(%rsp), %r13
leaq 80(%rsp), %rbp
jmp .LBB1_5
.p2align 4, 0x90
.LBB1_7: # in Loop: Header=BB1_5 Depth=1
incl %r14d
movl 4(%rsp), %eax
cmpl %eax, %r14d
jge .LBB1_8
.LBB1_5: # =>This Inner Loop Header: Depth=1
movl %eax, %edi
shrl $31, %edi
addl %eax, %edi
sarl %edi
orq %r15, %rdi
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_7
# %bb.6: # in Loop: Header=BB1_5 Depth=1
movq 8(%rsp), %rax
movl %r14d, %ecx
andl $1, %ecx
movl 4(%rsp), %edx
movq %rax, 72(%rsp)
movl %ecx, 20(%rsp)
movl %edx, 16(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 20(%rsp), %rax
movq %rax, 88(%rsp)
leaq 16(%rsp), %rax
movq %rax, 96(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
movq %r12, %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
movl $_Z7oddevenPiii, %edi
movq %rbp, %r9
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB1_7
.LBB1_8: # %._crit_edge20
movl $10, %edi
callq putchar@PLT
movq 8(%rsp), %rsi
movslq 4(%rsp), %rdx
shlq $2, %rdx
leaq 80(%rsp), %rdi
movl $2, %ecx
callq hipMemcpy
movl $.L.str.4, %edi
xorl %eax, %eax
callq printf
cmpl $0, 4(%rsp)
jle .LBB1_11
# %bb.9: # %.lr.ph23.preheader
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_10: # %.lr.ph23
# =>This Inner Loop Header: Depth=1
movl 80(%rsp,%rbx,4), %esi
movl $.L.str.5, %edi
xorl %eax, %eax
callq printf
incq %rbx
movslq 4(%rsp), %rax
cmpq %rax, %rbx
jl .LBB1_10
.LBB1_11: # %._crit_edge24
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $888, %rsp # imm = 0x378
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7oddevenPiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z7oddevenPiii,@object # @_Z7oddevenPiii
.section .rodata,"a",@progbits
.globl _Z7oddevenPiii
.p2align 3, 0x0
_Z7oddevenPiii:
.quad _Z22__device_stub__oddevenPiii
.size _Z7oddevenPiii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Enter how many elements of first array:"
.size .L.str, 40
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "%d"
.size .L.str.1, 3
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Sorted Array is:\t"
.size .L.str.4, 18
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "%d\t"
.size .L.str.5, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z7oddevenPiii"
.size .L__unnamed_1, 15
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Enter No."
.size .Lstr, 10
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__oddevenPiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7oddevenPiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z7oddevenPiii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e220000002500 */
/*0020*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff047624 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ IMAD.SHL.U32 R2, R2, 0x2, RZ ; /* 0x0000000202027824 */
/* 0x001fca00078e00ff */
/*0050*/ IADD3 R0, R2.reuse, 0x1, RZ ; /* 0x0000000102007810 */
/* 0x040fe40007ffe0ff */
/*0060*/ IADD3 R3, R2, 0x2, RZ ; /* 0x0000000202037810 */
/* 0x000fe40007ffe0ff */
/*0070*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x16c], PT ; /* 0x00005b0000007a0c */
/* 0x000fe40003f06270 */
/*0080*/ ISETP.GE.AND P1, PT, R3, c[0x0][0x16c], PT ; /* 0x00005b0003007a0c */
/* 0x000fe20003f26270 */
/*0090*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fe200078e00ff */
/*00a0*/ ISETP.NE.OR P0, PT, RZ, c[0x0][0x168], P0 ; /* 0x00005a00ff007a0c */
/* 0x000fe40000705670 */
/*00b0*/ ISETP.NE.OR P1, PT, R4, 0x1, P1 ; /* 0x000000010400780c */
/* 0x000fe20000f25670 */
/*00c0*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fd400078e0203 */
/*00d0*/ @P0 BRA 0x130 ; /* 0x0000005000000947 */
/* 0x000fea0003800000 */
/*00e0*/ LDG.E R5, [R2.64] ; /* 0x0000000402057981 */
/* 0x000ea8000c1e1900 */
/*00f0*/ LDG.E R0, [R2.64+0x4] ; /* 0x0000040402007981 */
/* 0x000ea4000c1e1900 */
/*0100*/ ISETP.GT.AND P0, PT, R5, R0, PT ; /* 0x000000000500720c */
/* 0x004fda0003f04270 */
/*0110*/ @P0 STG.E [R2.64], R0 ; /* 0x0000000002000986 */
/* 0x0001e8000c101904 */
/*0120*/ @P0 STG.E [R2.64+0x4], R5 ; /* 0x0000040502000986 */
/* 0x0001e4000c101904 */
/*0130*/ @P1 EXIT ; /* 0x000000000000194d */
/* 0x000fea0003800000 */
/*0140*/ LDG.E R5, [R2.64+0x8] ; /* 0x0000080402057981 */
/* 0x001ea8000c1e1900 */
/*0150*/ LDG.E R0, [R2.64+0x4] ; /* 0x0000040402007981 */
/* 0x000ea4000c1e1900 */
/*0160*/ ISETP.GT.AND P0, PT, R0, R5, PT ; /* 0x000000050000720c */
/* 0x004fda0003f04270 */
/*0170*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0180*/ STG.E [R2.64+0x4], R5 ; /* 0x0000040502007986 */
/* 0x000fe8000c101904 */
/*0190*/ STG.E [R2.64+0x8], R0 ; /* 0x0000080002007986 */
/* 0x000fe2000c101904 */
/*01a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01b0*/ BRA 0x1b0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z7oddevenPiii
.globl _Z7oddevenPiii
.p2align 8
.type _Z7oddevenPiii,@function
_Z7oddevenPiii:
s_clause 0x1
s_load_b32 s7, s[0:1], 0x8
s_load_b64 s[2:3], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s7, 1
s_cbranch_scc1 .LBB0_2
s_cmp_eq_u32 s7, 1
s_mov_b32 s5, 0
s_cselect_b32 s4, -1, 0
s_branch .LBB0_3
.LBB0_2:
s_mov_b32 s5, -1
s_mov_b32 s4, 0
.LBB0_3:
s_load_b32 s6, s[0:1], 0xc
s_and_not1_b32 vcc_lo, exec_lo, s5
s_cbranch_vccnz .LBB0_5
s_cmp_eq_u32 s7, 0
s_cbranch_scc1 .LBB0_9
.LBB0_5:
s_and_b32 vcc_lo, exec_lo, s4
s_cbranch_vccz .LBB0_13
.LBB0_6:
s_lshl_b32 s0, s15, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_add_i32 s4, s0, 2
s_waitcnt lgkmcnt(0)
s_cmp_ge_i32 s4, s6
s_cbranch_scc1 .LBB0_13
s_or_b32 s0, s0, 1
v_mov_b32_e32 v0, 0
s_ashr_i32 s1, s0, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_lshl_b64 s[0:1], s[0:1], 2
s_add_u32 s0, s2, s0
s_addc_u32 s1, s3, s1
s_ashr_i32 s5, s4, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_lshl_b64 s[4:5], s[4:5], 2
s_add_u32 s2, s2, s4
s_addc_u32 s3, s3, s5
s_clause 0x1
global_load_b32 v1, v0, s[0:1]
global_load_b32 v2, v0, s[2:3]
s_waitcnt vmcnt(0)
v_cmp_le_i32_e32 vcc_lo, v1, v2
s_cbranch_vccnz .LBB0_13
s_clause 0x1
global_store_b32 v0, v2, s[0:1]
global_store_b32 v0, v1, s[2:3]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.LBB0_9:
s_lshl_b32 s0, s15, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 s4, s0, 1
s_waitcnt lgkmcnt(0)
s_cmp_ge_i32 s4, s6
s_cbranch_scc1 .LBB0_12
s_ashr_i32 s1, s0, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_lshl_b64 s[0:1], s[0:1], 2
s_add_u32 s0, s2, s0
s_addc_u32 s1, s3, s1
s_ashr_i32 s5, s4, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_lshl_b64 s[4:5], s[4:5], 2
s_add_u32 s4, s2, s4
s_addc_u32 s5, s3, s5
s_clause 0x1
s_load_b32 s8, s[0:1], 0x0
s_load_b32 s9, s[4:5], 0x0
s_waitcnt lgkmcnt(0)
s_cmp_le_i32 s8, s9
s_cbranch_scc1 .LBB0_12
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s9
v_mov_b32_e32 v2, s8
s_clause 0x1
global_store_b32 v0, v1, s[0:1]
global_store_b32 v0, v2, s[4:5]
.LBB0_12:
s_cmp_eq_u32 s7, 1
s_cselect_b32 s4, -1, 0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 vcc_lo, exec_lo, s4
s_cbranch_vccnz .LBB0_6
.LBB0_13:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7oddevenPiii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 16
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z7oddevenPiii, .Lfunc_end0-_Z7oddevenPiii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 16
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7oddevenPiii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z7oddevenPiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00119c76_00000000-6_oddeven.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z28__device_stub__Z7oddevenPiiiPiii
.type _Z28__device_stub__Z7oddevenPiiiPiii, @function
_Z28__device_stub__Z7oddevenPiiiPiii:
.LFB2082:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z7oddevenPiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z28__device_stub__Z7oddevenPiiiPiii, .-_Z28__device_stub__Z7oddevenPiiiPiii
.globl _Z7oddevenPiii
.type _Z7oddevenPiii, @function
_Z7oddevenPiii:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z28__device_stub__Z7oddevenPiiiPiii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z7oddevenPiii, .-_Z7oddevenPiii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "Enter how many elements of first array:"
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "%d"
.LC2:
.string "Enter No.\n"
.LC3:
.string "\n"
.LC4:
.string "Sorted Array is:\t"
.LC5:
.string "%d\t"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $864, %rsp
.cfi_def_cfa_offset 896
movq %fs:40, %rax
movq %rax, 856(%rsp)
xorl %eax, %eax
leaq .LC0(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
leaq 12(%rsp), %rsi
leaq .LC1(%rip), %rdi
movl $0, %eax
call __isoc23_scanf@PLT
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 12(%rsp), %esi
testl %esi, %esi
jle .L12
leaq 48(%rsp), %rbp
movl $0, %ebx
leaq .LC1(%rip), %r12
.L13:
movq %rbp, %rsi
movq %r12, %rdi
movl $0, %eax
call __isoc23_scanf@PLT
addl $1, %ebx
movl 12(%rsp), %esi
addq $4, %rbp
cmpl %ebx, %esi
jg .L13
.L12:
movslq %esi, %rsi
salq $2, %rsi
leaq 16(%rsp), %rdi
call cudaMalloc@PLT
movslq 12(%rsp), %rdx
salq $2, %rdx
leaq 48(%rsp), %rsi
movl $1, %ecx
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl 12(%rsp), %edx
testl %edx, %edx
jle .L14
movl $0, %ebx
jmp .L16
.L15:
addl $1, %ebx
movl 12(%rsp), %edx
cmpl %ebx, %edx
jle .L14
.L16:
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl %edx, %eax
shrl $31, %eax
addl %edx, %eax
sarl %eax
movl %eax, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L15
movl %ebx, %eax
shrl $31, %eax
leal (%rbx,%rax), %esi
andl $1, %esi
subl %eax, %esi
movl 12(%rsp), %edx
movq 16(%rsp), %rdi
call _Z28__device_stub__Z7oddevenPiiiPiii
jmp .L15
.L14:
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movslq 12(%rsp), %rdx
salq $2, %rdx
leaq 448(%rsp), %rdi
movl $2, %ecx
movq 16(%rsp), %rsi
call cudaMemcpy@PLT
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
cmpl $0, 12(%rsp)
jle .L17
movl $0, %ebx
leaq .LC5(%rip), %rbp
.L18:
movl 448(%rsp,%rbx,4), %edx
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpl %ebx, 12(%rsp)
jg .L18
.L17:
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 856(%rsp), %rax
subq %fs:40, %rax
jne .L24
movl $0, %eax
addq $864, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L24:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC6:
.string "_Z7oddevenPiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _Z7oddevenPiii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "oddeven.hip"
.globl _Z22__device_stub__oddevenPiii # -- Begin function _Z22__device_stub__oddevenPiii
.p2align 4, 0x90
.type _Z22__device_stub__oddevenPiii,@function
_Z22__device_stub__oddevenPiii: # @_Z22__device_stub__oddevenPiii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z7oddevenPiii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z22__device_stub__oddevenPiii, .Lfunc_end0-_Z22__device_stub__oddevenPiii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $888, %rsp # imm = 0x378
.cfi_def_cfa_offset 944
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $.L.str, %edi
xorl %eax, %eax
callq printf
leaq 4(%rsp), %rsi
movl $.L.str.1, %edi
xorl %eax, %eax
callq __isoc23_scanf
movl $.Lstr, %edi
callq puts@PLT
movl 4(%rsp), %eax
testl %eax, %eax
jle .LBB1_3
# %bb.1: # %.lr.ph.preheader
leaq 480(%rsp), %rbx
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl $.L.str.1, %edi
movq %rbx, %rsi
xorl %eax, %eax
callq __isoc23_scanf
incq %r14
movslq 4(%rsp), %rax
addq $4, %rbx
cmpq %rax, %r14
jl .LBB1_2
.LBB1_3: # %._crit_edge
movslq %eax, %rsi
shlq $2, %rsi
leaq 8(%rsp), %rdi
callq hipMalloc
movq 8(%rsp), %rdi
movslq 4(%rsp), %rdx
shlq $2, %rdx
leaq 480(%rsp), %rsi
movl $1, %ecx
callq hipMemcpy
movl 4(%rsp), %eax
testl %eax, %eax
jle .LBB1_8
# %bb.4: # %.lr.ph19
xorl %r14d, %r14d
movabsq $4294967296, %r15 # imm = 0x100000000
leaq 1(%r15), %rbx
leaq 32(%rsp), %r12
leaq 24(%rsp), %r13
leaq 80(%rsp), %rbp
jmp .LBB1_5
.p2align 4, 0x90
.LBB1_7: # in Loop: Header=BB1_5 Depth=1
incl %r14d
movl 4(%rsp), %eax
cmpl %eax, %r14d
jge .LBB1_8
.LBB1_5: # =>This Inner Loop Header: Depth=1
movl %eax, %edi
shrl $31, %edi
addl %eax, %edi
sarl %edi
orq %r15, %rdi
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_7
# %bb.6: # in Loop: Header=BB1_5 Depth=1
movq 8(%rsp), %rax
movl %r14d, %ecx
andl $1, %ecx
movl 4(%rsp), %edx
movq %rax, 72(%rsp)
movl %ecx, 20(%rsp)
movl %edx, 16(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 20(%rsp), %rax
movq %rax, 88(%rsp)
leaq 16(%rsp), %rax
movq %rax, 96(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
movq %r12, %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
movl $_Z7oddevenPiii, %edi
movq %rbp, %r9
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB1_7
.LBB1_8: # %._crit_edge20
movl $10, %edi
callq putchar@PLT
movq 8(%rsp), %rsi
movslq 4(%rsp), %rdx
shlq $2, %rdx
leaq 80(%rsp), %rdi
movl $2, %ecx
callq hipMemcpy
movl $.L.str.4, %edi
xorl %eax, %eax
callq printf
cmpl $0, 4(%rsp)
jle .LBB1_11
# %bb.9: # %.lr.ph23.preheader
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_10: # %.lr.ph23
# =>This Inner Loop Header: Depth=1
movl 80(%rsp,%rbx,4), %esi
movl $.L.str.5, %edi
xorl %eax, %eax
callq printf
incq %rbx
movslq 4(%rsp), %rax
cmpq %rax, %rbx
jl .LBB1_10
.LBB1_11: # %._crit_edge24
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $888, %rsp # imm = 0x378
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7oddevenPiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z7oddevenPiii,@object # @_Z7oddevenPiii
.section .rodata,"a",@progbits
.globl _Z7oddevenPiii
.p2align 3, 0x0
_Z7oddevenPiii:
.quad _Z22__device_stub__oddevenPiii
.size _Z7oddevenPiii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Enter how many elements of first array:"
.size .L.str, 40
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "%d"
.size .L.str.1, 3
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Sorted Array is:\t"
.size .L.str.4, 18
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "%d\t"
.size .L.str.5, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z7oddevenPiii"
.size .L__unnamed_1, 15
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Enter No."
.size .Lstr, 10
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__oddevenPiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7oddevenPiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | /*********************************************************************
* Copyright © 2011-2014,
* Marwan Abdellah: <abdellah.marwan@gmail.com>
*
* This library (cufftShift) is free software; you can redistribute it
* and/or modify it under the terms of the GNU Lesser General Public
* License as published by the Free Software Foundation.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public
* License along with this library; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
* MA 02110-1301, USA.
********************************************************************/
#ifndef CUFFTSHIFT_1D_CU
#define CUFFTSHIFT_1D_CU
#include <cuda.h>
// #include <cutil_inline.h>
template <typename T>
__global__
void cufftShift_1D_kernel(T* input, T* output, int NX)
{
int threadIdxX = threadIdx.x;
int blockDimX = blockDim.x;
int blockIdxX = blockIdx.x;
int index = ((blockIdxX * blockDimX) + threadIdxX);
if (index < (NX / 2))
output[index] = (T) input[index + (NX / 2)];
else
output[index] = (T) input[index - (NX / 2)];
}
#endif // CUFFTSHIFT_1D_CU | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /*********************************************************************
* Copyright © 2011-2014,
* Marwan Abdellah: <abdellah.marwan@gmail.com>
*
* This library (cufftShift) is free software; you can redistribute it
* and/or modify it under the terms of the GNU Lesser General Public
* License as published by the Free Software Foundation.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public
* License along with this library; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
* MA 02110-1301, USA.
********************************************************************/
#ifndef CUFFTSHIFT_1D_CU
#define CUFFTSHIFT_1D_CU
#include <cuda.h>
// #include <cutil_inline.h>
template <typename T>
__global__
void cufftShift_1D_kernel(T* input, T* output, int NX)
{
int threadIdxX = threadIdx.x;
int blockDimX = blockDim.x;
int blockIdxX = blockIdx.x;
int index = ((blockIdxX * blockDimX) + threadIdxX);
if (index < (NX / 2))
output[index] = (T) input[index + (NX / 2)];
else
output[index] = (T) input[index - (NX / 2)];
}
#endif // CUFFTSHIFT_1D_CU | .file "tmpxft_00045251_00000000-6_cufftShift_1D_OP.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2031:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2031:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /*********************************************************************
* Copyright © 2011-2014,
* Marwan Abdellah: <abdellah.marwan@gmail.com>
*
* This library (cufftShift) is free software; you can redistribute it
* and/or modify it under the terms of the GNU Lesser General Public
* License as published by the Free Software Foundation.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public
* License along with this library; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
* MA 02110-1301, USA.
********************************************************************/
#ifndef CUFFTSHIFT_1D_CU
#define CUFFTSHIFT_1D_CU
#include <cuda.h>
// #include <cutil_inline.h>
template <typename T>
__global__
void cufftShift_1D_kernel(T* input, T* output, int NX)
{
int threadIdxX = threadIdx.x;
int blockDimX = blockDim.x;
int blockIdxX = blockIdx.x;
int index = ((blockIdxX * blockDimX) + threadIdxX);
if (index < (NX / 2))
output[index] = (T) input[index + (NX / 2)];
else
output[index] = (T) input[index - (NX / 2)];
}
#endif // CUFFTSHIFT_1D_CU | /*********************************************************************
* Copyright © 2011-2014,
* Marwan Abdellah: <abdellah.marwan@gmail.com>
*
* This library (cufftShift) is free software; you can redistribute it
* and/or modify it under the terms of the GNU Lesser General Public
* License as published by the Free Software Foundation.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public
* License along with this library; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
* MA 02110-1301, USA.
********************************************************************/
#ifndef CUFFTSHIFT_1D_CU
#define CUFFTSHIFT_1D_CU
#include <hip/hip_runtime.h>
// #include <cutil_inline.h>
template <typename T>
__global__
void cufftShift_1D_kernel(T* input, T* output, int NX)
{
int threadIdxX = threadIdx.x;
int blockDimX = blockDim.x;
int blockIdxX = blockIdx.x;
int index = ((blockIdxX * blockDimX) + threadIdxX);
if (index < (NX / 2))
output[index] = (T) input[index + (NX / 2)];
else
output[index] = (T) input[index - (NX / 2)];
}
#endif // CUFFTSHIFT_1D_CU |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | /*********************************************************************
* Copyright © 2011-2014,
* Marwan Abdellah: <abdellah.marwan@gmail.com>
*
* This library (cufftShift) is free software; you can redistribute it
* and/or modify it under the terms of the GNU Lesser General Public
* License as published by the Free Software Foundation.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public
* License along with this library; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
* MA 02110-1301, USA.
********************************************************************/
#ifndef CUFFTSHIFT_1D_CU
#define CUFFTSHIFT_1D_CU
#include <hip/hip_runtime.h>
// #include <cutil_inline.h>
template <typename T>
__global__
void cufftShift_1D_kernel(T* input, T* output, int NX)
{
int threadIdxX = threadIdx.x;
int blockDimX = blockDim.x;
int blockIdxX = blockIdx.x;
int index = ((blockIdxX * blockDimX) + threadIdxX);
if (index < (NX / 2))
output[index] = (T) input[index + (NX / 2)];
else
output[index] = (T) input[index - (NX / 2)];
}
#endif // CUFFTSHIFT_1D_CU | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | /*********************************************************************
* Copyright © 2011-2014,
* Marwan Abdellah: <abdellah.marwan@gmail.com>
*
* This library (cufftShift) is free software; you can redistribute it
* and/or modify it under the terms of the GNU Lesser General Public
* License as published by the Free Software Foundation.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public
* License along with this library; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
* MA 02110-1301, USA.
********************************************************************/
#ifndef CUFFTSHIFT_1D_CU
#define CUFFTSHIFT_1D_CU
#include <hip/hip_runtime.h>
// #include <cutil_inline.h>
template <typename T>
__global__
void cufftShift_1D_kernel(T* input, T* output, int NX)
{
int threadIdxX = threadIdx.x;
int blockDimX = blockDim.x;
int blockIdxX = blockIdx.x;
int index = ((blockIdxX * blockDimX) + threadIdxX);
if (index < (NX / 2))
output[index] = (T) input[index + (NX / 2)];
else
output[index] = (T) input[index - (NX / 2)];
}
#endif // CUFFTSHIFT_1D_CU | .text
.file "cufftShift_1D_OP.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00045251_00000000-6_cufftShift_1D_OP.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2031:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2031:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "cufftShift_1D_OP.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void predicate(int *d_array, int d_numberOfElements,int *d_predicateArray)
{
int index = blockIdx.x * blockDim.x + threadIdx.x;
if(index <d_numberOfElements)
{
if(d_array[index]%32== 0)
{
d_predicateArray[index] =1;
}
else
{
d_predicateArray[index] = 0;
}
}
} | code for sm_80
Function : _Z9predicatePiiS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R4, R4, c[0x0][0x0], R3 ; /* 0x0000000004047a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R4, c[0x0][0x168], PT ; /* 0x00005a0004007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R2, R4, R5, c[0x0][0x160] ; /* 0x0000580004027625 */
/* 0x000fcc00078e0205 */
/*0090*/ LDG.E.U8 R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1100 */
/*00a0*/ IMAD.WIDE R4, R4, R5, c[0x0][0x170] ; /* 0x00005c0004047625 */
/* 0x000fe200078e0205 */
/*00b0*/ LOP3.LUT P0, RZ, R2, 0x1f, RZ, 0xc0, !PT ; /* 0x0000001f02ff7812 */
/* 0x004fda000780c0ff */
/*00c0*/ @P0 STG.E [R4.64], RZ ; /* 0x000000ff04000986 */
/* 0x0001e2000c101904 */
/*00d0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00e0*/ MOV R3, 0x1 ; /* 0x0000000100037802 */
/* 0x000fca0000000f00 */
/*00f0*/ STG.E [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x000fe2000c101904 */
/*0100*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0110*/ BRA 0x110; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void predicate(int *d_array, int d_numberOfElements,int *d_predicateArray)
{
int index = blockIdx.x * blockDim.x + threadIdx.x;
if(index <d_numberOfElements)
{
if(d_array[index]%32== 0)
{
d_predicateArray[index] =1;
}
else
{
d_predicateArray[index] = 0;
}
}
} | .file "tmpxft_00009fcc_00000000-6_predicate.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z31__device_stub__Z9predicatePiiS_PiiS_
.type _Z31__device_stub__Z9predicatePiiS_PiiS_, @function
_Z31__device_stub__Z9predicatePiiS_PiiS_:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9predicatePiiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z31__device_stub__Z9predicatePiiS_PiiS_, .-_Z31__device_stub__Z9predicatePiiS_PiiS_
.globl _Z9predicatePiiS_
.type _Z9predicatePiiS_, @function
_Z9predicatePiiS_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z9predicatePiiS_PiiS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z9predicatePiiS_, .-_Z9predicatePiiS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z9predicatePiiS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z9predicatePiiS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void predicate(int *d_array, int d_numberOfElements,int *d_predicateArray)
{
int index = blockIdx.x * blockDim.x + threadIdx.x;
if(index <d_numberOfElements)
{
if(d_array[index]%32== 0)
{
d_predicateArray[index] =1;
}
else
{
d_predicateArray[index] = 0;
}
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void predicate(int *d_array, int d_numberOfElements,int *d_predicateArray)
{
int index = blockIdx.x * blockDim.x + threadIdx.x;
if(index <d_numberOfElements)
{
if(d_array[index]%32== 0)
{
d_predicateArray[index] =1;
}
else
{
d_predicateArray[index] = 0;
}
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void predicate(int *d_array, int d_numberOfElements,int *d_predicateArray)
{
int index = blockIdx.x * blockDim.x + threadIdx.x;
if(index <d_numberOfElements)
{
if(d_array[index]%32== 0)
{
d_predicateArray[index] =1;
}
else
{
d_predicateArray[index] = 0;
}
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9predicatePiiS_
.globl _Z9predicatePiiS_
.p2align 8
.type _Z9predicatePiiS_,@function
_Z9predicatePiiS_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b64 s[2:3], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(0)
v_and_b32_e32 v2, 31, v2
s_delay_alu instid0(VALU_DEP_1)
v_cmp_eq_u32_e32 vcc_lo, 0, v2
v_cndmask_b32_e64 v2, 0, 1, vcc_lo
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9predicatePiiS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9predicatePiiS_, .Lfunc_end0-_Z9predicatePiiS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9predicatePiiS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9predicatePiiS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void predicate(int *d_array, int d_numberOfElements,int *d_predicateArray)
{
int index = blockIdx.x * blockDim.x + threadIdx.x;
if(index <d_numberOfElements)
{
if(d_array[index]%32== 0)
{
d_predicateArray[index] =1;
}
else
{
d_predicateArray[index] = 0;
}
}
} | .text
.file "predicate.hip"
.globl _Z24__device_stub__predicatePiiS_ # -- Begin function _Z24__device_stub__predicatePiiS_
.p2align 4, 0x90
.type _Z24__device_stub__predicatePiiS_,@function
_Z24__device_stub__predicatePiiS_: # @_Z24__device_stub__predicatePiiS_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movl %esi, 12(%rsp)
movq %rdx, 64(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9predicatePiiS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z24__device_stub__predicatePiiS_, .Lfunc_end0-_Z24__device_stub__predicatePiiS_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9predicatePiiS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9predicatePiiS_,@object # @_Z9predicatePiiS_
.section .rodata,"a",@progbits
.globl _Z9predicatePiiS_
.p2align 3, 0x0
_Z9predicatePiiS_:
.quad _Z24__device_stub__predicatePiiS_
.size _Z9predicatePiiS_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z9predicatePiiS_"
.size .L__unnamed_1, 18
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__predicatePiiS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9predicatePiiS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z9predicatePiiS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R4, R4, c[0x0][0x0], R3 ; /* 0x0000000004047a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R4, c[0x0][0x168], PT ; /* 0x00005a0004007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R2, R4, R5, c[0x0][0x160] ; /* 0x0000580004027625 */
/* 0x000fcc00078e0205 */
/*0090*/ LDG.E.U8 R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1100 */
/*00a0*/ IMAD.WIDE R4, R4, R5, c[0x0][0x170] ; /* 0x00005c0004047625 */
/* 0x000fe200078e0205 */
/*00b0*/ LOP3.LUT P0, RZ, R2, 0x1f, RZ, 0xc0, !PT ; /* 0x0000001f02ff7812 */
/* 0x004fda000780c0ff */
/*00c0*/ @P0 STG.E [R4.64], RZ ; /* 0x000000ff04000986 */
/* 0x0001e2000c101904 */
/*00d0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00e0*/ MOV R3, 0x1 ; /* 0x0000000100037802 */
/* 0x000fca0000000f00 */
/*00f0*/ STG.E [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x000fe2000c101904 */
/*0100*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0110*/ BRA 0x110; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9predicatePiiS_
.globl _Z9predicatePiiS_
.p2align 8
.type _Z9predicatePiiS_,@function
_Z9predicatePiiS_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b64 s[2:3], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(0)
v_and_b32_e32 v2, 31, v2
s_delay_alu instid0(VALU_DEP_1)
v_cmp_eq_u32_e32 vcc_lo, 0, v2
v_cndmask_b32_e64 v2, 0, 1, vcc_lo
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9predicatePiiS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9predicatePiiS_, .Lfunc_end0-_Z9predicatePiiS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9predicatePiiS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9predicatePiiS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00009fcc_00000000-6_predicate.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z31__device_stub__Z9predicatePiiS_PiiS_
.type _Z31__device_stub__Z9predicatePiiS_PiiS_, @function
_Z31__device_stub__Z9predicatePiiS_PiiS_:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9predicatePiiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z31__device_stub__Z9predicatePiiS_PiiS_, .-_Z31__device_stub__Z9predicatePiiS_PiiS_
.globl _Z9predicatePiiS_
.type _Z9predicatePiiS_, @function
_Z9predicatePiiS_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z9predicatePiiS_PiiS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z9predicatePiiS_, .-_Z9predicatePiiS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z9predicatePiiS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z9predicatePiiS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "predicate.hip"
.globl _Z24__device_stub__predicatePiiS_ # -- Begin function _Z24__device_stub__predicatePiiS_
.p2align 4, 0x90
.type _Z24__device_stub__predicatePiiS_,@function
_Z24__device_stub__predicatePiiS_: # @_Z24__device_stub__predicatePiiS_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movl %esi, 12(%rsp)
movq %rdx, 64(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9predicatePiiS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z24__device_stub__predicatePiiS_, .Lfunc_end0-_Z24__device_stub__predicatePiiS_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9predicatePiiS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9predicatePiiS_,@object # @_Z9predicatePiiS_
.section .rodata,"a",@progbits
.globl _Z9predicatePiiS_
.p2align 3, 0x0
_Z9predicatePiiS_:
.quad _Z24__device_stub__predicatePiiS_
.size _Z9predicatePiiS_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z9predicatePiiS_"
.size .L__unnamed_1, 18
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__predicatePiiS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9predicatePiiS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <stdio.h>
int main()
{
int devcount;
cudaGetDeviceCount(&devcount);
printf("%i device(s) found...", devcount);
return 0;
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <stdio.h>
int main()
{
int devcount;
cudaGetDeviceCount(&devcount);
printf("%i device(s) found...", devcount);
return 0;
} | .file "tmpxft_00123440_00000000-6_cuda_01.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%i device(s) found..."
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $24, %rsp
.cfi_def_cfa_offset 32
movq %fs:40, %rax
movq %rax, 8(%rsp)
xorl %eax, %eax
leaq 4(%rsp), %rdi
call cudaGetDeviceCount@PLT
movl 4(%rsp), %edx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 8(%rsp), %rax
subq %fs:40, %rax
jne .L6
movl $0, %eax
addq $24, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L6:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <stdio.h>
int main()
{
int devcount;
cudaGetDeviceCount(&devcount);
printf("%i device(s) found...", devcount);
return 0;
} | #include "hip/hip_runtime.h"
#include <stdio.h>
int main()
{
int devcount;
hipGetDeviceCount(&devcount);
printf("%i device(s) found...", devcount);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include "hip/hip_runtime.h"
#include <stdio.h>
int main()
{
int devcount;
hipGetDeviceCount(&devcount);
printf("%i device(s) found...", devcount);
return 0;
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include "hip/hip_runtime.h"
#include <stdio.h>
int main()
{
int devcount;
hipGetDeviceCount(&devcount);
printf("%i device(s) found...", devcount);
return 0;
} | .text
.file "cuda_01.hip"
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
leaq 4(%rsp), %rdi
callq hipGetDeviceCount
movl 4(%rsp), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
xorl %eax, %eax
popq %rcx
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%i device(s) found..."
.size .L.str, 22
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00123440_00000000-6_cuda_01.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%i device(s) found..."
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $24, %rsp
.cfi_def_cfa_offset 32
movq %fs:40, %rax
movq %rax, 8(%rsp)
xorl %eax, %eax
leaq 4(%rsp), %rdi
call cudaGetDeviceCount@PLT
movl 4(%rsp), %edx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 8(%rsp), %rax
subq %fs:40, %rax
jne .L6
movl $0, %eax
addq $24, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L6:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "cuda_01.hip"
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
leaq 4(%rsp), %rdi
callq hipGetDeviceCount
movl 4(%rsp), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
xorl %eax, %eax
popq %rcx
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%i device(s) found..."
.size .L.str, 22
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void imageBNKernel(unsigned char* d_image, int h, int w)
{
int Row = blockIdx.y * blockDim.y + threadIdx.y;
int Col = blockIdx.x * blockDim.x + threadIdx.x;
int r, g, b;
if((Row < h) && (Col < w)){
r = d_image[4 * w * Row + 4 * Col + 0];
g = d_image[4 * w * Row + 4 * Col + 1];
b = d_image[4 * w * Row + 4 * Col + 2];
d_image[4 * w * Row + 4 * Col + 0] = 0;
d_image[4 * w * Row + 4 * Col + 1] = 0;
d_image[4 * w * Row + 4 * Col + 2] = 0;
d_image[4 * w * Row + 4 * Col + 3] = (int)(r*0.21 + g*0.71 + b*0.07);
}
} | code for sm_80
Function : _Z13imageBNKernelPhii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e280000002500 */
/*0020*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e280000002100 */
/*0030*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e680000002600 */
/*0040*/ S2R R3, SR_TID.Y ; /* 0x0000000000037919 */
/* 0x000e620000002200 */
/*0050*/ IMAD R2, R2, c[0x0][0x0], R5 ; /* 0x0000000002027a24 */
/* 0x001fca00078e0205 */
/*0060*/ ISETP.GE.AND P0, PT, R2, c[0x0][0x16c], PT ; /* 0x00005b0002007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R0, R0, c[0x0][0x4], R3 ; /* 0x0000010000007a24 */
/* 0x002fca00078e0203 */
/*0080*/ ISETP.GE.OR P0, PT, R0, c[0x0][0x168], P0 ; /* 0x00005a0000007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ SHF.L.U32 R0, R0, 0x2, RZ ; /* 0x0000000200007819 */
/* 0x000fe200000006ff */
/*00b0*/ IMAD.SHL.U32 R3, R2, 0x4, RZ ; /* 0x0000000402037824 */
/* 0x000fe200078e00ff */
/*00c0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*00d0*/ IMAD R0, R0, c[0x0][0x16c], R3 ; /* 0x00005b0000007a24 */
/* 0x000fca00078e0203 */
/*00e0*/ IADD3 R2, P0, R0, c[0x0][0x160], RZ ; /* 0x0000580000027a10 */
/* 0x000fc80007f1e0ff */
/*00f0*/ LEA.HI.X.SX32 R3, R0, c[0x0][0x164], 0x1, P0 ; /* 0x0000590000037a11 */
/* 0x000fca00000f0eff */
/*0100*/ LDG.E.U8 R10, [R2.64+0x1] ; /* 0x00000104020a7981 */
/* 0x000ea8000c1e1100 */
/*0110*/ LDG.E.U8 R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ee8000c1e1100 */
/*0120*/ LDG.E.U8 R8, [R2.64+0x2] ; /* 0x0000020402087981 */
/* 0x000f28000c1e1100 */
/*0130*/ STG.E.U8 [R2.64], RZ ; /* 0x000000ff02007986 */
/* 0x000fe8000c101104 */
/*0140*/ STG.E.U8 [R2.64+0x1], RZ ; /* 0x000001ff02007986 */
/* 0x000fe8000c101104 */
/*0150*/ STG.E.U8 [R2.64+0x2], RZ ; /* 0x000002ff02007986 */
/* 0x000fe2000c101104 */
/*0160*/ I2F.F64.U16 R6, R10 ; /* 0x0000000a00067312 */
/* 0x004e300000101800 */
/*0170*/ I2F.F64.U16 R4, R0 ; /* 0x0000000000047312 */
/* 0x008e700000101800 */
/*0180*/ I2F.F64.U16 R8, R8 ; /* 0x0000000800087312 */
/* 0x010ea20000101800 */
/*0190*/ DMUL R6, R6, c[0x2][0x0] ; /* 0x0080000006067a28 */
/* 0x001e4c0000000000 */
/*01a0*/ DFMA R4, R4, c[0x2][0x8], R6 ; /* 0x0080020004047a2b */
/* 0x002e8c0000000006 */
/*01b0*/ DFMA R4, R8, c[0x2][0x10], R4 ; /* 0x0080040008047a2b */
/* 0x004e140000000004 */
/*01c0*/ F2I.F64.TRUNC R5, R4 ; /* 0x0000000400057311 */
/* 0x001e24000030d100 */
/*01d0*/ STG.E.U8 [R2.64+0x3], R5 ; /* 0x0000030502007986 */
/* 0x001fe2000c101104 */
/*01e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01f0*/ BRA 0x1f0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void imageBNKernel(unsigned char* d_image, int h, int w)
{
int Row = blockIdx.y * blockDim.y + threadIdx.y;
int Col = blockIdx.x * blockDim.x + threadIdx.x;
int r, g, b;
if((Row < h) && (Col < w)){
r = d_image[4 * w * Row + 4 * Col + 0];
g = d_image[4 * w * Row + 4 * Col + 1];
b = d_image[4 * w * Row + 4 * Col + 2];
d_image[4 * w * Row + 4 * Col + 0] = 0;
d_image[4 * w * Row + 4 * Col + 1] = 0;
d_image[4 * w * Row + 4 * Col + 2] = 0;
d_image[4 * w * Row + 4 * Col + 3] = (int)(r*0.21 + g*0.71 + b*0.07);
}
} | .file "tmpxft_0016c119_00000000-6_imageBNKernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z35__device_stub__Z13imageBNKernelPhiiPhii
.type _Z35__device_stub__Z13imageBNKernelPhiiPhii, @function
_Z35__device_stub__Z13imageBNKernelPhiiPhii:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z13imageBNKernelPhii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z35__device_stub__Z13imageBNKernelPhiiPhii, .-_Z35__device_stub__Z13imageBNKernelPhiiPhii
.globl _Z13imageBNKernelPhii
.type _Z13imageBNKernelPhii, @function
_Z13imageBNKernelPhii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z13imageBNKernelPhiiPhii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z13imageBNKernelPhii, .-_Z13imageBNKernelPhii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z13imageBNKernelPhii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z13imageBNKernelPhii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void imageBNKernel(unsigned char* d_image, int h, int w)
{
int Row = blockIdx.y * blockDim.y + threadIdx.y;
int Col = blockIdx.x * blockDim.x + threadIdx.x;
int r, g, b;
if((Row < h) && (Col < w)){
r = d_image[4 * w * Row + 4 * Col + 0];
g = d_image[4 * w * Row + 4 * Col + 1];
b = d_image[4 * w * Row + 4 * Col + 2];
d_image[4 * w * Row + 4 * Col + 0] = 0;
d_image[4 * w * Row + 4 * Col + 1] = 0;
d_image[4 * w * Row + 4 * Col + 2] = 0;
d_image[4 * w * Row + 4 * Col + 3] = (int)(r*0.21 + g*0.71 + b*0.07);
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void imageBNKernel(unsigned char* d_image, int h, int w)
{
int Row = blockIdx.y * blockDim.y + threadIdx.y;
int Col = blockIdx.x * blockDim.x + threadIdx.x;
int r, g, b;
if((Row < h) && (Col < w)){
r = d_image[4 * w * Row + 4 * Col + 0];
g = d_image[4 * w * Row + 4 * Col + 1];
b = d_image[4 * w * Row + 4 * Col + 2];
d_image[4 * w * Row + 4 * Col + 0] = 0;
d_image[4 * w * Row + 4 * Col + 1] = 0;
d_image[4 * w * Row + 4 * Col + 2] = 0;
d_image[4 * w * Row + 4 * Col + 3] = (int)(r*0.21 + g*0.71 + b*0.07);
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void imageBNKernel(unsigned char* d_image, int h, int w)
{
int Row = blockIdx.y * blockDim.y + threadIdx.y;
int Col = blockIdx.x * blockDim.x + threadIdx.x;
int r, g, b;
if((Row < h) && (Col < w)){
r = d_image[4 * w * Row + 4 * Col + 0];
g = d_image[4 * w * Row + 4 * Col + 1];
b = d_image[4 * w * Row + 4 * Col + 2];
d_image[4 * w * Row + 4 * Col + 0] = 0;
d_image[4 * w * Row + 4 * Col + 1] = 0;
d_image[4 * w * Row + 4 * Col + 2] = 0;
d_image[4 * w * Row + 4 * Col + 3] = (int)(r*0.21 + g*0.71 + b*0.07);
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z13imageBNKernelPhii
.globl _Z13imageBNKernelPhii
.p2align 8
.type _Z13imageBNKernelPhii,@function
_Z13imageBNKernelPhii:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x1c
s_load_b64 s[2:3], s[0:1], 0x8
v_bfe_u32 v1, v0, 10, 10
v_and_b32_e32 v4, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s5, s4, 16
s_and_b32 s4, s4, 0xffff
v_mad_u64_u32 v[2:3], null, s15, s5, v[1:2]
v_mad_u64_u32 v[0:1], null, s14, s4, v[4:5]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_gt_i32_e32 vcc_lo, s2, v2
v_cmp_gt_i32_e64 s2, s3, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, vcc_lo, s2
s_and_saveexec_b32 s4, s2
s_cbranch_execz .LBB0_2
v_mul_lo_u32 v1, s3, v2
s_load_b64 s[0:1], s[0:1], 0x0
s_mov_b32 s3, 0x3fe6b851
s_mov_b32 s2, 0xeb851eb8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b32_e32 v1, 2, v1
v_lshl_add_u32 v10, v0, 2, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_or_b32_e32 v0, 1, v10
v_ashrrev_i32_e32 v3, 31, v10
v_or_b32_e32 v4, 2, v10
v_ashrrev_i32_e32 v1, 31, v0
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_ashrrev_i32_e32 v5, 31, v4
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
v_add_co_u32 v2, vcc_lo, s0, v10
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
global_load_u8 v6, v[0:1], off
v_add_co_u32 v4, vcc_lo, s0, v4
global_load_u8 v8, v[2:3], off
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v5, vcc_lo
global_load_u8 v11, v[4:5], off
s_waitcnt vmcnt(2)
v_cvt_f64_u32_e32 v[6:7], v6
s_waitcnt vmcnt(1)
v_cvt_f64_u32_e32 v[8:9], v8
s_delay_alu instid0(VALU_DEP_2)
v_mul_f64 v[6:7], v[6:7], s[2:3]
s_mov_b32 s3, 0x3fcae147
s_mov_b32 s2, 0xae147ae1
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fma_f64 v[6:7], v[8:9], s[2:3], v[6:7]
s_waitcnt vmcnt(0)
v_cvt_f64_u32_e32 v[8:9], v11
s_mov_b32 s3, 0x3fb1eb85
s_mov_b32 s2, 0x1eb851ec
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fma_f64 v[6:7], v[8:9], s[2:3], v[6:7]
v_mov_b32_e32 v9, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cvt_i32_f64_e32 v8, v[6:7]
v_or_b32_e32 v6, 3, v10
v_ashrrev_i32_e32 v7, 31, v6
v_add_co_u32 v6, vcc_lo, s0, v6
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v7, vcc_lo, s1, v7, vcc_lo
s_clause 0x3
global_store_b8 v[2:3], v9, off
global_store_b8 v[0:1], v9, off
global_store_b8 v[4:5], v9, off
global_store_b8 v[6:7], v8, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13imageBNKernelPhii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 12
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z13imageBNKernelPhii, .Lfunc_end0-_Z13imageBNKernelPhii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13imageBNKernelPhii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z13imageBNKernelPhii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 12
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void imageBNKernel(unsigned char* d_image, int h, int w)
{
int Row = blockIdx.y * blockDim.y + threadIdx.y;
int Col = blockIdx.x * blockDim.x + threadIdx.x;
int r, g, b;
if((Row < h) && (Col < w)){
r = d_image[4 * w * Row + 4 * Col + 0];
g = d_image[4 * w * Row + 4 * Col + 1];
b = d_image[4 * w * Row + 4 * Col + 2];
d_image[4 * w * Row + 4 * Col + 0] = 0;
d_image[4 * w * Row + 4 * Col + 1] = 0;
d_image[4 * w * Row + 4 * Col + 2] = 0;
d_image[4 * w * Row + 4 * Col + 3] = (int)(r*0.21 + g*0.71 + b*0.07);
}
} | .text
.file "imageBNKernel.hip"
.globl _Z28__device_stub__imageBNKernelPhii # -- Begin function _Z28__device_stub__imageBNKernelPhii
.p2align 4, 0x90
.type _Z28__device_stub__imageBNKernelPhii,@function
_Z28__device_stub__imageBNKernelPhii: # @_Z28__device_stub__imageBNKernelPhii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z13imageBNKernelPhii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z28__device_stub__imageBNKernelPhii, .Lfunc_end0-_Z28__device_stub__imageBNKernelPhii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13imageBNKernelPhii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z13imageBNKernelPhii,@object # @_Z13imageBNKernelPhii
.section .rodata,"a",@progbits
.globl _Z13imageBNKernelPhii
.p2align 3, 0x0
_Z13imageBNKernelPhii:
.quad _Z28__device_stub__imageBNKernelPhii
.size _Z13imageBNKernelPhii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z13imageBNKernelPhii"
.size .L__unnamed_1, 22
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__imageBNKernelPhii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z13imageBNKernelPhii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z13imageBNKernelPhii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e280000002500 */
/*0020*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e280000002100 */
/*0030*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e680000002600 */
/*0040*/ S2R R3, SR_TID.Y ; /* 0x0000000000037919 */
/* 0x000e620000002200 */
/*0050*/ IMAD R2, R2, c[0x0][0x0], R5 ; /* 0x0000000002027a24 */
/* 0x001fca00078e0205 */
/*0060*/ ISETP.GE.AND P0, PT, R2, c[0x0][0x16c], PT ; /* 0x00005b0002007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R0, R0, c[0x0][0x4], R3 ; /* 0x0000010000007a24 */
/* 0x002fca00078e0203 */
/*0080*/ ISETP.GE.OR P0, PT, R0, c[0x0][0x168], P0 ; /* 0x00005a0000007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ SHF.L.U32 R0, R0, 0x2, RZ ; /* 0x0000000200007819 */
/* 0x000fe200000006ff */
/*00b0*/ IMAD.SHL.U32 R3, R2, 0x4, RZ ; /* 0x0000000402037824 */
/* 0x000fe200078e00ff */
/*00c0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*00d0*/ IMAD R0, R0, c[0x0][0x16c], R3 ; /* 0x00005b0000007a24 */
/* 0x000fca00078e0203 */
/*00e0*/ IADD3 R2, P0, R0, c[0x0][0x160], RZ ; /* 0x0000580000027a10 */
/* 0x000fc80007f1e0ff */
/*00f0*/ LEA.HI.X.SX32 R3, R0, c[0x0][0x164], 0x1, P0 ; /* 0x0000590000037a11 */
/* 0x000fca00000f0eff */
/*0100*/ LDG.E.U8 R10, [R2.64+0x1] ; /* 0x00000104020a7981 */
/* 0x000ea8000c1e1100 */
/*0110*/ LDG.E.U8 R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ee8000c1e1100 */
/*0120*/ LDG.E.U8 R8, [R2.64+0x2] ; /* 0x0000020402087981 */
/* 0x000f28000c1e1100 */
/*0130*/ STG.E.U8 [R2.64], RZ ; /* 0x000000ff02007986 */
/* 0x000fe8000c101104 */
/*0140*/ STG.E.U8 [R2.64+0x1], RZ ; /* 0x000001ff02007986 */
/* 0x000fe8000c101104 */
/*0150*/ STG.E.U8 [R2.64+0x2], RZ ; /* 0x000002ff02007986 */
/* 0x000fe2000c101104 */
/*0160*/ I2F.F64.U16 R6, R10 ; /* 0x0000000a00067312 */
/* 0x004e300000101800 */
/*0170*/ I2F.F64.U16 R4, R0 ; /* 0x0000000000047312 */
/* 0x008e700000101800 */
/*0180*/ I2F.F64.U16 R8, R8 ; /* 0x0000000800087312 */
/* 0x010ea20000101800 */
/*0190*/ DMUL R6, R6, c[0x2][0x0] ; /* 0x0080000006067a28 */
/* 0x001e4c0000000000 */
/*01a0*/ DFMA R4, R4, c[0x2][0x8], R6 ; /* 0x0080020004047a2b */
/* 0x002e8c0000000006 */
/*01b0*/ DFMA R4, R8, c[0x2][0x10], R4 ; /* 0x0080040008047a2b */
/* 0x004e140000000004 */
/*01c0*/ F2I.F64.TRUNC R5, R4 ; /* 0x0000000400057311 */
/* 0x001e24000030d100 */
/*01d0*/ STG.E.U8 [R2.64+0x3], R5 ; /* 0x0000030502007986 */
/* 0x001fe2000c101104 */
/*01e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01f0*/ BRA 0x1f0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z13imageBNKernelPhii
.globl _Z13imageBNKernelPhii
.p2align 8
.type _Z13imageBNKernelPhii,@function
_Z13imageBNKernelPhii:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x1c
s_load_b64 s[2:3], s[0:1], 0x8
v_bfe_u32 v1, v0, 10, 10
v_and_b32_e32 v4, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s5, s4, 16
s_and_b32 s4, s4, 0xffff
v_mad_u64_u32 v[2:3], null, s15, s5, v[1:2]
v_mad_u64_u32 v[0:1], null, s14, s4, v[4:5]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_gt_i32_e32 vcc_lo, s2, v2
v_cmp_gt_i32_e64 s2, s3, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, vcc_lo, s2
s_and_saveexec_b32 s4, s2
s_cbranch_execz .LBB0_2
v_mul_lo_u32 v1, s3, v2
s_load_b64 s[0:1], s[0:1], 0x0
s_mov_b32 s3, 0x3fe6b851
s_mov_b32 s2, 0xeb851eb8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b32_e32 v1, 2, v1
v_lshl_add_u32 v10, v0, 2, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_or_b32_e32 v0, 1, v10
v_ashrrev_i32_e32 v3, 31, v10
v_or_b32_e32 v4, 2, v10
v_ashrrev_i32_e32 v1, 31, v0
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_ashrrev_i32_e32 v5, 31, v4
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
v_add_co_u32 v2, vcc_lo, s0, v10
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
global_load_u8 v6, v[0:1], off
v_add_co_u32 v4, vcc_lo, s0, v4
global_load_u8 v8, v[2:3], off
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v5, vcc_lo
global_load_u8 v11, v[4:5], off
s_waitcnt vmcnt(2)
v_cvt_f64_u32_e32 v[6:7], v6
s_waitcnt vmcnt(1)
v_cvt_f64_u32_e32 v[8:9], v8
s_delay_alu instid0(VALU_DEP_2)
v_mul_f64 v[6:7], v[6:7], s[2:3]
s_mov_b32 s3, 0x3fcae147
s_mov_b32 s2, 0xae147ae1
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fma_f64 v[6:7], v[8:9], s[2:3], v[6:7]
s_waitcnt vmcnt(0)
v_cvt_f64_u32_e32 v[8:9], v11
s_mov_b32 s3, 0x3fb1eb85
s_mov_b32 s2, 0x1eb851ec
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fma_f64 v[6:7], v[8:9], s[2:3], v[6:7]
v_mov_b32_e32 v9, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cvt_i32_f64_e32 v8, v[6:7]
v_or_b32_e32 v6, 3, v10
v_ashrrev_i32_e32 v7, 31, v6
v_add_co_u32 v6, vcc_lo, s0, v6
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v7, vcc_lo, s1, v7, vcc_lo
s_clause 0x3
global_store_b8 v[2:3], v9, off
global_store_b8 v[0:1], v9, off
global_store_b8 v[4:5], v9, off
global_store_b8 v[6:7], v8, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13imageBNKernelPhii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 12
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z13imageBNKernelPhii, .Lfunc_end0-_Z13imageBNKernelPhii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13imageBNKernelPhii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z13imageBNKernelPhii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 12
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0016c119_00000000-6_imageBNKernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z35__device_stub__Z13imageBNKernelPhiiPhii
.type _Z35__device_stub__Z13imageBNKernelPhiiPhii, @function
_Z35__device_stub__Z13imageBNKernelPhiiPhii:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z13imageBNKernelPhii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z35__device_stub__Z13imageBNKernelPhiiPhii, .-_Z35__device_stub__Z13imageBNKernelPhiiPhii
.globl _Z13imageBNKernelPhii
.type _Z13imageBNKernelPhii, @function
_Z13imageBNKernelPhii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z13imageBNKernelPhiiPhii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z13imageBNKernelPhii, .-_Z13imageBNKernelPhii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z13imageBNKernelPhii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z13imageBNKernelPhii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "imageBNKernel.hip"
.globl _Z28__device_stub__imageBNKernelPhii # -- Begin function _Z28__device_stub__imageBNKernelPhii
.p2align 4, 0x90
.type _Z28__device_stub__imageBNKernelPhii,@function
_Z28__device_stub__imageBNKernelPhii: # @_Z28__device_stub__imageBNKernelPhii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z13imageBNKernelPhii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z28__device_stub__imageBNKernelPhii, .Lfunc_end0-_Z28__device_stub__imageBNKernelPhii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13imageBNKernelPhii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z13imageBNKernelPhii,@object # @_Z13imageBNKernelPhii
.section .rodata,"a",@progbits
.globl _Z13imageBNKernelPhii
.p2align 3, 0x0
_Z13imageBNKernelPhii:
.quad _Z28__device_stub__imageBNKernelPhii
.size _Z13imageBNKernelPhii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z13imageBNKernelPhii"
.size .L__unnamed_1, 22
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__imageBNKernelPhii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z13imageBNKernelPhii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void Match5(float *d_pts1, float *d_pts2, float *d_score, int *d_index)
{
__shared__ float4 buffer1[M5W*(NDIM/4 + 1)];
__shared__ float4 buffer2[M5H*NDIM/4];
__shared__ float scores[M5W*M5H];
int tx = threadIdx.x;
int ty = threadIdx.y;
int bp1 = M5W*blockIdx.x;
if (ty<M5W)
for (int d=tx;d<NDIM/4;d+=M5W)
for (int j=ty;j<M5W;j+=M5H)
buffer1[j*(NDIM/4 + 1) + d] = ((float4*)d_pts1)[(bp1 + j)*(NDIM/4) + d];
__syncthreads();
float max_score = 0.0f;
int index = -1;
for (int bp2=0;bp2<NPTS;bp2+=M5H) {
for (int d=tx;d<NDIM/4;d+=M5W)
buffer2[ty*NDIM/4 + d] = ((float4*)d_pts2)[(bp2 + ty)*(NDIM/4) + d];
__syncthreads();
if (ty<M5H/M5R) { //%%%%
float score[M5R]; //%%%%
for (int dy=0;dy<M5R;dy++)
score[dy] = 0.0f;
for (int d=0;d<NDIM/4;d++) {
float4 v1 = buffer1[tx*(NDIM/4 + 1) + d];
for (int dy=0;dy<M5R;dy++) {
float4 v2 = buffer2[(M5R*ty + dy)*(NDIM/4) + d]; //%%%%
score[dy] += v1.x*v2.x; score[dy] += v1.y*v2.y;
score[dy] += v1.z*v2.z; score[dy] += v1.w*v2.w;
}
}
for (int dy=0;dy<M5R;dy++)
scores[tx + M5W*(M5R*ty + dy)] = score[dy];
}
__syncthreads();
if (ty==0) {
for (int i=0;i<M5H;i++) {
if (scores[i*M2W + tx]>max_score) {
max_score = scores[i*M5W + tx];
index = bp2 + i;
}
}
}
__syncthreads();
}
if (ty==0) {
d_score[bp1 + tx] = max_score;
d_index[bp1 + tx] = index;
}
} | .file "tmpxft_00006ab3_00000000-6_Match5.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z31__device_stub__Z6Match5PfS_S_PiPfS_S_Pi
.type _Z31__device_stub__Z6Match5PfS_S_PiPfS_S_Pi, @function
_Z31__device_stub__Z6Match5PfS_S_PiPfS_S_Pi:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6Match5PfS_S_Pi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z31__device_stub__Z6Match5PfS_S_PiPfS_S_Pi, .-_Z31__device_stub__Z6Match5PfS_S_PiPfS_S_Pi
.globl _Z6Match5PfS_S_Pi
.type _Z6Match5PfS_S_Pi, @function
_Z6Match5PfS_S_Pi:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z6Match5PfS_S_PiPfS_S_Pi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z6Match5PfS_S_Pi, .-_Z6Match5PfS_S_Pi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z6Match5PfS_S_Pi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z6Match5PfS_S_Pi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void Match5(float *d_pts1, float *d_pts2, float *d_score, int *d_index)
{
__shared__ float4 buffer1[M5W*(NDIM/4 + 1)];
__shared__ float4 buffer2[M5H*NDIM/4];
__shared__ float scores[M5W*M5H];
int tx = threadIdx.x;
int ty = threadIdx.y;
int bp1 = M5W*blockIdx.x;
if (ty<M5W)
for (int d=tx;d<NDIM/4;d+=M5W)
for (int j=ty;j<M5W;j+=M5H)
buffer1[j*(NDIM/4 + 1) + d] = ((float4*)d_pts1)[(bp1 + j)*(NDIM/4) + d];
__syncthreads();
float max_score = 0.0f;
int index = -1;
for (int bp2=0;bp2<NPTS;bp2+=M5H) {
for (int d=tx;d<NDIM/4;d+=M5W)
buffer2[ty*NDIM/4 + d] = ((float4*)d_pts2)[(bp2 + ty)*(NDIM/4) + d];
__syncthreads();
if (ty<M5H/M5R) { //%%%%
float score[M5R]; //%%%%
for (int dy=0;dy<M5R;dy++)
score[dy] = 0.0f;
for (int d=0;d<NDIM/4;d++) {
float4 v1 = buffer1[tx*(NDIM/4 + 1) + d];
for (int dy=0;dy<M5R;dy++) {
float4 v2 = buffer2[(M5R*ty + dy)*(NDIM/4) + d]; //%%%%
score[dy] += v1.x*v2.x; score[dy] += v1.y*v2.y;
score[dy] += v1.z*v2.z; score[dy] += v1.w*v2.w;
}
}
for (int dy=0;dy<M5R;dy++)
scores[tx + M5W*(M5R*ty + dy)] = score[dy];
}
__syncthreads();
if (ty==0) {
for (int i=0;i<M5H;i++) {
if (scores[i*M2W + tx]>max_score) {
max_score = scores[i*M5W + tx];
index = bp2 + i;
}
}
}
__syncthreads();
}
if (ty==0) {
d_score[bp1 + tx] = max_score;
d_index[bp1 + tx] = index;
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void Match5(float *d_pts1, float *d_pts2, float *d_score, int *d_index)
{
__shared__ float4 buffer1[M5W*(NDIM/4 + 1)];
__shared__ float4 buffer2[M5H*NDIM/4];
__shared__ float scores[M5W*M5H];
int tx = threadIdx.x;
int ty = threadIdx.y;
int bp1 = M5W*blockIdx.x;
if (ty<M5W)
for (int d=tx;d<NDIM/4;d+=M5W)
for (int j=ty;j<M5W;j+=M5H)
buffer1[j*(NDIM/4 + 1) + d] = ((float4*)d_pts1)[(bp1 + j)*(NDIM/4) + d];
__syncthreads();
float max_score = 0.0f;
int index = -1;
for (int bp2=0;bp2<NPTS;bp2+=M5H) {
for (int d=tx;d<NDIM/4;d+=M5W)
buffer2[ty*NDIM/4 + d] = ((float4*)d_pts2)[(bp2 + ty)*(NDIM/4) + d];
__syncthreads();
if (ty<M5H/M5R) { //%%%%
float score[M5R]; //%%%%
for (int dy=0;dy<M5R;dy++)
score[dy] = 0.0f;
for (int d=0;d<NDIM/4;d++) {
float4 v1 = buffer1[tx*(NDIM/4 + 1) + d];
for (int dy=0;dy<M5R;dy++) {
float4 v2 = buffer2[(M5R*ty + dy)*(NDIM/4) + d]; //%%%%
score[dy] += v1.x*v2.x; score[dy] += v1.y*v2.y;
score[dy] += v1.z*v2.z; score[dy] += v1.w*v2.w;
}
}
for (int dy=0;dy<M5R;dy++)
scores[tx + M5W*(M5R*ty + dy)] = score[dy];
}
__syncthreads();
if (ty==0) {
for (int i=0;i<M5H;i++) {
if (scores[i*M2W + tx]>max_score) {
max_score = scores[i*M5W + tx];
index = bp2 + i;
}
}
}
__syncthreads();
}
if (ty==0) {
d_score[bp1 + tx] = max_score;
d_index[bp1 + tx] = index;
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void Match5(float *d_pts1, float *d_pts2, float *d_score, int *d_index)
{
__shared__ float4 buffer1[M5W*(NDIM/4 + 1)];
__shared__ float4 buffer2[M5H*NDIM/4];
__shared__ float scores[M5W*M5H];
int tx = threadIdx.x;
int ty = threadIdx.y;
int bp1 = M5W*blockIdx.x;
if (ty<M5W)
for (int d=tx;d<NDIM/4;d+=M5W)
for (int j=ty;j<M5W;j+=M5H)
buffer1[j*(NDIM/4 + 1) + d] = ((float4*)d_pts1)[(bp1 + j)*(NDIM/4) + d];
__syncthreads();
float max_score = 0.0f;
int index = -1;
for (int bp2=0;bp2<NPTS;bp2+=M5H) {
for (int d=tx;d<NDIM/4;d+=M5W)
buffer2[ty*NDIM/4 + d] = ((float4*)d_pts2)[(bp2 + ty)*(NDIM/4) + d];
__syncthreads();
if (ty<M5H/M5R) { //%%%%
float score[M5R]; //%%%%
for (int dy=0;dy<M5R;dy++)
score[dy] = 0.0f;
for (int d=0;d<NDIM/4;d++) {
float4 v1 = buffer1[tx*(NDIM/4 + 1) + d];
for (int dy=0;dy<M5R;dy++) {
float4 v2 = buffer2[(M5R*ty + dy)*(NDIM/4) + d]; //%%%%
score[dy] += v1.x*v2.x; score[dy] += v1.y*v2.y;
score[dy] += v1.z*v2.z; score[dy] += v1.w*v2.w;
}
}
for (int dy=0;dy<M5R;dy++)
scores[tx + M5W*(M5R*ty + dy)] = score[dy];
}
__syncthreads();
if (ty==0) {
for (int i=0;i<M5H;i++) {
if (scores[i*M2W + tx]>max_score) {
max_score = scores[i*M5W + tx];
index = bp2 + i;
}
}
}
__syncthreads();
}
if (ty==0) {
d_score[bp1 + tx] = max_score;
d_index[bp1 + tx] = index;
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6Match5PfS_S_Pi
.globl _Z6Match5PfS_S_Pi
.p2align 8
.type _Z6Match5PfS_S_Pi,@function
_Z6Match5PfS_S_Pi:
v_bfe_u32 v11, v0, 10, 10
v_and_b32_e32 v10, 0x3ff, v0
s_lshl_b32 s10, s15, 4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_gt_u32_e32 vcc_lo, 16, v11
v_cmp_gt_u32_e64 s2, 32, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, vcc_lo, s2
s_and_saveexec_b32 s4, s2
s_cbranch_execz .LBB0_3
s_load_b64 s[2:3], s[0:1], 0x0
v_mul_u32_u24_e32 v1, 33, v11
v_add_lshl_u32 v0, v11, s10, 5
v_mov_b32_e32 v2, v10
s_mov_b32 s5, 0
s_delay_alu instid0(VALU_DEP_3)
v_add_lshl_u32 v1, v1, v10, 4
.p2align 6
.LBB0_2:
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v7, 16, v2
v_add_nc_u32_e32 v3, v0, v2
v_ashrrev_i32_e32 v4, 31, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 4, v[3:4]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, vcc_lo, s2, v3
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v4, vcc_lo
v_cmp_lt_u32_e32 vcc_lo, 15, v2
v_mov_b32_e32 v2, v7
global_load_b128 v[3:6], v[3:4], off
s_or_b32 s5, vcc_lo, s5
s_waitcnt vmcnt(0)
ds_store_b128 v1, v[3:6]
v_add_nc_u32_e32 v1, 0x100, v1
s_and_not1_b32 exec_lo, exec_lo, s5
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s4
s_load_b64 s[4:5], s[0:1], 0x8
v_dual_mov_b32 v13, -1 :: v_dual_lshlrev_b32 v0, 5, v11
v_lshlrev_b32_e32 v1, 9, v11
v_lshlrev_b32_e32 v2, 4, v10
v_lshl_add_u32 v16, v10, 2, 0x4100
s_delay_alu instid0(VALU_DEP_4)
v_add_lshl_u32 v0, v10, v0, 4
v_cmp_gt_u32_e32 vcc_lo, 32, v10
v_cmp_gt_u32_e64 s2, 4, v11
v_cmp_eq_u32_e64 s3, 0, v11
v_mul_u32_u24_e32 v14, 33, v10
v_dual_mov_b32 v12, 0 :: v_dual_add_nc_u32 v15, -16, v10
v_lshl_add_u32 v17, v11, 11, 0x2100
v_add3_u32 v18, v1, v2, 0x2100
v_lshl_add_u32 v19, v11, 8, v16
s_mov_b32 s11, 0
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_add_co_u32 v4, s4, s4, v0
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v5, null, s5, 0, s4
s_and_saveexec_b32 s5, vcc_lo
s_cbranch_execz .LBB0_6
.LBB0_4:
s_delay_alu instid0(VALU_DEP_1)
v_dual_mov_b32 v8, v18 :: v_dual_mov_b32 v7, v5
v_dual_mov_b32 v6, v4 :: v_dual_mov_b32 v9, v15
s_mov_b32 s6, 0
.p2align 6
.LBB0_5:
global_load_b128 v[20:23], v[6:7], off
v_add_co_u32 v6, s4, v6, 0x100
v_add_co_u32 v9, s7, v9, 16
v_add_co_ci_u32_e64 v7, s4, 0, v7, s4
s_xor_b32 s4, s7, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s4, exec_lo, s4
s_or_b32 s6, s4, s6
s_waitcnt vmcnt(0)
ds_store_b128 v8, v[20:23]
v_add_nc_u32_e32 v8, 0x100, v8
s_and_not1_b32 exec_lo, exec_lo, s6
s_cbranch_execnz .LBB0_5
.LBB0_6:
s_or_b32 exec_lo, exec_lo, s5
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_and_saveexec_b32 s12, s2
s_cbranch_execz .LBB0_15
s_mov_b64 s[6:7], 0
.p2align 6
.LBB0_8:
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lg_u32 s6, 3
s_cselect_b32 s4, -1, 0
s_cmp_lg_u32 s6, 2
v_cndmask_b32_e64 v3, 0, v3, s4
s_cselect_b32 s4, -1, 0
s_cmp_lg_u32 s6, 1
v_cndmask_b32_e64 v2, 0, v2, s4
s_cselect_b32 s4, -1, 0
s_cmp_lg_u32 s6, 0
v_cndmask_b32_e64 v1, 0, v1, s4
s_cselect_b32 s4, -1, 0
s_add_u32 s6, s6, 1
v_cndmask_b32_e64 v0, 0, v0, s4
s_addc_u32 s7, s7, 0
s_cmp_lg_u32 s6, 4
s_cbranch_scc1 .LBB0_8
v_mov_b32_e32 v20, v17
s_mov_b32 s13, 0
s_set_inst_prefetch_distance 0x1
.p2align 6
.LBB0_10:
v_add_lshl_u32 v8, s13, v14, 4
s_delay_alu instid0(VALU_DEP_2)
v_mov_b32_e32 v21, v20
s_mov_b64 s[8:9], 0
ds_load_2addr_b32 v[6:7], v8 offset1:1
ds_load_2addr_b32 v[8:9], v8 offset0:2 offset1:3
.p2align 6
.LBB0_11:
ds_load_2addr_b32 v[22:23], v21 offset1:1
ds_load_2addr_b32 v[24:25], v21 offset0:2 offset1:3
s_cmp_eq_u32 s8, 1
v_add_nc_u32_e32 v21, 0x200, v21
s_cselect_b32 s4, -1, 0
s_cmp_eq_u32 s8, 2
v_cndmask_b32_e64 v26, v0, v1, s4
s_cselect_b32 s5, -1, 0
s_cmp_eq_u32 s8, 3
s_cselect_b32 s6, -1, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_cndmask_b32_e64 v26, v26, v2, s5
s_cmp_eq_u32 s8, 0
s_cselect_b32 s7, -1, 0
s_add_u32 s8, s8, 1
v_cndmask_b32_e64 v26, v26, v3, s6
s_addc_u32 s9, s9, 0
s_cmp_eq_u32 s8, 4
s_waitcnt lgkmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v26, v6, v22
v_fmac_f32_e32 v26, v7, v23
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v26, v8, v24
v_fmac_f32_e32 v26, v9, v25
s_delay_alu instid0(VALU_DEP_1)
v_cndmask_b32_e64 v3, v3, v26, s6
v_cndmask_b32_e64 v2, v2, v26, s5
v_cndmask_b32_e64 v1, v1, v26, s4
v_cndmask_b32_e64 v0, v0, v26, s7
s_cbranch_scc0 .LBB0_11
v_add_nc_u32_e32 v20, 16, v20
s_add_i32 s13, s13, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lg_u32 s13, 32
s_cbranch_scc1 .LBB0_10
s_set_inst_prefetch_distance 0x2
v_mov_b32_e32 v6, v19
s_mov_b64 s[6:7], 0
.p2align 6
.LBB0_14:
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s6, 1
s_cselect_b32 s4, -1, 0
s_cmp_eq_u32 s6, 2
v_cndmask_b32_e64 v7, v0, v1, s4
s_cselect_b32 s4, -1, 0
s_cmp_eq_u32 s6, 3
s_delay_alu instid0(VALU_DEP_1)
v_cndmask_b32_e64 v7, v7, v2, s4
s_cselect_b32 s4, -1, 0
s_add_u32 s6, s6, 1
s_addc_u32 s7, s7, 0
s_cmp_lg_u32 s6, 4
v_cndmask_b32_e64 v7, v7, v3, s4
ds_store_b32 v6, v7
v_add_nc_u32_e32 v6, 64, v6
s_cbranch_scc1 .LBB0_14
.LBB0_15:
s_or_b32 exec_lo, exec_lo, s12
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_and_saveexec_b32 s5, s3
s_cbranch_execz .LBB0_18
v_mov_b32_e32 v6, v16
s_mov_b32 s6, 0
.LBB0_17:
ds_load_b32 v7, v6
s_add_i32 s7, s11, s6
v_add_nc_u32_e32 v6, 64, v6
s_add_i32 s6, s6, 1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
s_cmp_lg_u32 s6, 16
s_waitcnt lgkmcnt(0)
v_cmp_gt_f32_e64 s4, v7, v12
v_cndmask_b32_e64 v13, v13, s7, s4
v_cndmask_b32_e64 v12, v12, v7, s4
s_cbranch_scc1 .LBB0_17
.LBB0_18:
s_or_b32 exec_lo, exec_lo, s5
v_add_co_u32 v4, s4, v4, 0x2000
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v5, s4, 0, v5, s4
s_add_i32 s4, s11, 16
s_cmpk_gt_u32 s11, 0x3fef
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_20
s_mov_b32 s11, s4
s_and_saveexec_b32 s5, vcc_lo
s_cbranch_execnz .LBB0_4
s_branch .LBB0_6
.LBB0_20:
s_mov_b32 s2, exec_lo
v_cmpx_eq_u32_e32 0, v11
s_cbranch_execz .LBB0_22
s_load_b128 s[0:3], s[0:1], 0x10
v_add_nc_u32_e32 v0, s10, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_store_b32 v[2:3], v12, off
global_store_b32 v[0:1], v13, off
.LBB0_22:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6Match5PfS_S_Pi
.amdhsa_group_segment_fixed_size 17664
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 32
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 27
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6Match5PfS_S_Pi, .Lfunc_end0-_Z6Match5PfS_S_Pi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 17664
.kernarg_segment_align: 8
.kernarg_segment_size: 32
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6Match5PfS_S_Pi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6Match5PfS_S_Pi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 27
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void Match5(float *d_pts1, float *d_pts2, float *d_score, int *d_index)
{
__shared__ float4 buffer1[M5W*(NDIM/4 + 1)];
__shared__ float4 buffer2[M5H*NDIM/4];
__shared__ float scores[M5W*M5H];
int tx = threadIdx.x;
int ty = threadIdx.y;
int bp1 = M5W*blockIdx.x;
if (ty<M5W)
for (int d=tx;d<NDIM/4;d+=M5W)
for (int j=ty;j<M5W;j+=M5H)
buffer1[j*(NDIM/4 + 1) + d] = ((float4*)d_pts1)[(bp1 + j)*(NDIM/4) + d];
__syncthreads();
float max_score = 0.0f;
int index = -1;
for (int bp2=0;bp2<NPTS;bp2+=M5H) {
for (int d=tx;d<NDIM/4;d+=M5W)
buffer2[ty*NDIM/4 + d] = ((float4*)d_pts2)[(bp2 + ty)*(NDIM/4) + d];
__syncthreads();
if (ty<M5H/M5R) { //%%%%
float score[M5R]; //%%%%
for (int dy=0;dy<M5R;dy++)
score[dy] = 0.0f;
for (int d=0;d<NDIM/4;d++) {
float4 v1 = buffer1[tx*(NDIM/4 + 1) + d];
for (int dy=0;dy<M5R;dy++) {
float4 v2 = buffer2[(M5R*ty + dy)*(NDIM/4) + d]; //%%%%
score[dy] += v1.x*v2.x; score[dy] += v1.y*v2.y;
score[dy] += v1.z*v2.z; score[dy] += v1.w*v2.w;
}
}
for (int dy=0;dy<M5R;dy++)
scores[tx + M5W*(M5R*ty + dy)] = score[dy];
}
__syncthreads();
if (ty==0) {
for (int i=0;i<M5H;i++) {
if (scores[i*M2W + tx]>max_score) {
max_score = scores[i*M5W + tx];
index = bp2 + i;
}
}
}
__syncthreads();
}
if (ty==0) {
d_score[bp1 + tx] = max_score;
d_index[bp1 + tx] = index;
}
} | .text
.file "Match5.hip"
.globl _Z21__device_stub__Match5PfS_S_Pi # -- Begin function _Z21__device_stub__Match5PfS_S_Pi
.p2align 4, 0x90
.type _Z21__device_stub__Match5PfS_S_Pi,@function
_Z21__device_stub__Match5PfS_S_Pi: # @_Z21__device_stub__Match5PfS_S_Pi
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movq %rcx, 48(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rax
movq %rax, 104(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6Match5PfS_S_Pi, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z21__device_stub__Match5PfS_S_Pi, .Lfunc_end0-_Z21__device_stub__Match5PfS_S_Pi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6Match5PfS_S_Pi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6Match5PfS_S_Pi,@object # @_Z6Match5PfS_S_Pi
.section .rodata,"a",@progbits
.globl _Z6Match5PfS_S_Pi
.p2align 3, 0x0
_Z6Match5PfS_S_Pi:
.quad _Z21__device_stub__Match5PfS_S_Pi
.size _Z6Match5PfS_S_Pi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z6Match5PfS_S_Pi"
.size .L__unnamed_1, 18
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__Match5PfS_S_Pi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6Match5PfS_S_Pi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00006ab3_00000000-6_Match5.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z31__device_stub__Z6Match5PfS_S_PiPfS_S_Pi
.type _Z31__device_stub__Z6Match5PfS_S_PiPfS_S_Pi, @function
_Z31__device_stub__Z6Match5PfS_S_PiPfS_S_Pi:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6Match5PfS_S_Pi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z31__device_stub__Z6Match5PfS_S_PiPfS_S_Pi, .-_Z31__device_stub__Z6Match5PfS_S_PiPfS_S_Pi
.globl _Z6Match5PfS_S_Pi
.type _Z6Match5PfS_S_Pi, @function
_Z6Match5PfS_S_Pi:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z6Match5PfS_S_PiPfS_S_Pi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z6Match5PfS_S_Pi, .-_Z6Match5PfS_S_Pi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z6Match5PfS_S_Pi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z6Match5PfS_S_Pi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "Match5.hip"
.globl _Z21__device_stub__Match5PfS_S_Pi # -- Begin function _Z21__device_stub__Match5PfS_S_Pi
.p2align 4, 0x90
.type _Z21__device_stub__Match5PfS_S_Pi,@function
_Z21__device_stub__Match5PfS_S_Pi: # @_Z21__device_stub__Match5PfS_S_Pi
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movq %rcx, 48(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rax
movq %rax, 104(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6Match5PfS_S_Pi, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z21__device_stub__Match5PfS_S_Pi, .Lfunc_end0-_Z21__device_stub__Match5PfS_S_Pi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6Match5PfS_S_Pi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6Match5PfS_S_Pi,@object # @_Z6Match5PfS_S_Pi
.section .rodata,"a",@progbits
.globl _Z6Match5PfS_S_Pi
.p2align 3, 0x0
_Z6Match5PfS_S_Pi:
.quad _Z21__device_stub__Match5PfS_S_Pi
.size _Z6Match5PfS_S_Pi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z6Match5PfS_S_Pi"
.size .L__unnamed_1, 18
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__Match5PfS_S_Pi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6Match5PfS_S_Pi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void kernel_mul(char* newB, char* first, char* second, int size_first, int size_second, int * size_newB) {
int i = threadIdx.x;
int j = threadIdx.y;
int tid = j * gridDim.x * blockDim.x + i ;
if(j!=0 && i!=0){
newB[tid] = first[i] * second[j];
}
if(j==0 && i==0){
if(first[j] != second[i])
newB[0]='-';
else
newB[0]='+';
}
} | code for sm_80
Function : _Z10kernel_mulPcS_S_iiPi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R8, SR_TID.Y ; /* 0x0000000000087919 */
/* 0x000e220000002200 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0030*/ BSSY B0, 0x160 ; /* 0x0000012000007945 */
/* 0x000fe40003800000 */
/*0040*/ S2R R11, SR_TID.X ; /* 0x00000000000b7919 */
/* 0x000e620000002100 */
/*0050*/ ISETP.NE.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x001fc80003f05270 */
/*0060*/ ISETP.EQ.OR P0, PT, R11, RZ, !P0 ; /* 0x000000ff0b00720c */
/* 0x002fe40004702670 */
/*0070*/ LOP3.LUT P1, RZ, R8, R11, RZ, 0xfc, !PT ; /* 0x0000000b08ff7212 */
/* 0x000fd6000782fcff */
/*0080*/ @P0 BRA 0x150 ; /* 0x000000c000000947 */
/* 0x000fea0003800000 */
/*0090*/ IADD3 R4, P0, R11.reuse, c[0x0][0x168], RZ ; /* 0x00005a000b047a10 */
/* 0x040fe40007f1e0ff */
/*00a0*/ IADD3 R2, P2, R8.reuse, c[0x0][0x170], RZ ; /* 0x00005c0008027a10 */
/* 0x040fe40007f5e0ff */
/*00b0*/ LEA.HI.X.SX32 R5, R11, c[0x0][0x16c], 0x1, P0 ; /* 0x00005b000b057a11 */
/* 0x000fe400000f0eff */
/*00c0*/ LEA.HI.X.SX32 R3, R8, c[0x0][0x174], 0x1, P2 ; /* 0x00005d0008037a11 */
/* 0x000fc800010f0eff */
/*00d0*/ LDG.E.U8 R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea8000c1e1100 */
/*00e0*/ LDG.E.U8 R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1100 */
/*00f0*/ IMAD R0, R8, c[0x0][0xc], RZ ; /* 0x0000030008007a24 */
/* 0x000fc800078e02ff */
/*0100*/ IMAD R0, R0, c[0x0][0x0], R11 ; /* 0x0000000000007a24 */
/* 0x000fca00078e020b */
/*0110*/ IADD3 R6, P0, R0, c[0x0][0x160], RZ ; /* 0x0000580000067a10 */
/* 0x000fc80007f1e0ff */
/*0120*/ LEA.HI.X.SX32 R7, R0, c[0x0][0x164], 0x1, P0 ; /* 0x0000590000077a11 */
/* 0x000fe200000f0eff */
/*0130*/ IMAD R9, R2, R5, RZ ; /* 0x0000000502097224 */
/* 0x004fca00078e02ff */
/*0140*/ STG.E.U8 [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x0001e6000c101104 */
/*0150*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0160*/ @P1 EXIT ; /* 0x000000000000194d */
/* 0x000fea0003800000 */
/*0170*/ IADD3 R6, P0, R8.reuse, c[0x0][0x168], RZ ; /* 0x00005a0008067a10 */
/* 0x041fe40007f1e0ff */
/*0180*/ IADD3 R4, P1, R11.reuse, c[0x0][0x170], RZ ; /* 0x00005c000b047a10 */
/* 0x040fe40007f3e0ff */
/*0190*/ LEA.HI.X.SX32 R7, R8, c[0x0][0x16c], 0x1, P0 ; /* 0x00005b0008077a11 */
/* 0x000fe400000f0eff */
/*01a0*/ LEA.HI.X.SX32 R5, R11, c[0x0][0x174], 0x1, P1 ; /* 0x00005d000b057a11 */
/* 0x000fc800008f0eff */
/*01b0*/ LDG.E.U8 R7, [R6.64] ; /* 0x0000000406077981 */
/* 0x000ea8000c1e1100 */
/*01c0*/ LDG.E.U8 R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea2000c1e1100 */
/*01d0*/ IMAD.MOV.U32 R0, RZ, RZ, 0x2d ; /* 0x0000002dff007424 */
/* 0x000fe400078e00ff */
/*01e0*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff027624 */
/* 0x000fe400078e00ff */
/*01f0*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff037624 */
/* 0x000fe200078e00ff */
/*0200*/ ISETP.NE.AND P0, PT, R7, R4, PT ; /* 0x000000040700720c */
/* 0x004fda0003f05270 */
/*0210*/ @P0 STG.E.U8 [R2.64], R0 ; /* 0x0000000002000986 */
/* 0x0001e2000c101104 */
/*0220*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0230*/ IMAD.MOV.U32 R0, RZ, RZ, 0x2b ; /* 0x0000002bff007424 */
/* 0x001fca00078e00ff */
/*0240*/ STG.E.U8 [R2.64], R0 ; /* 0x0000000002007986 */
/* 0x000fe2000c101104 */
/*0250*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0260*/ BRA 0x260; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void kernel_mul(char* newB, char* first, char* second, int size_first, int size_second, int * size_newB) {
int i = threadIdx.x;
int j = threadIdx.y;
int tid = j * gridDim.x * blockDim.x + i ;
if(j!=0 && i!=0){
newB[tid] = first[i] * second[j];
}
if(j==0 && i==0){
if(first[j] != second[i])
newB[0]='-';
else
newB[0]='+';
}
} | .file "tmpxft_0003f9d3_00000000-6_kernel_mul.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z38__device_stub__Z10kernel_mulPcS_S_iiPiPcS_S_iiPi
.type _Z38__device_stub__Z10kernel_mulPcS_S_iiPiPcS_S_iiPi, @function
_Z38__device_stub__Z10kernel_mulPcS_S_iiPiPcS_S_iiPi:
.LFB2051:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movq %r9, 8(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z10kernel_mulPcS_S_iiPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z38__device_stub__Z10kernel_mulPcS_S_iiPiPcS_S_iiPi, .-_Z38__device_stub__Z10kernel_mulPcS_S_iiPiPcS_S_iiPi
.globl _Z10kernel_mulPcS_S_iiPi
.type _Z10kernel_mulPcS_S_iiPi, @function
_Z10kernel_mulPcS_S_iiPi:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z38__device_stub__Z10kernel_mulPcS_S_iiPiPcS_S_iiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z10kernel_mulPcS_S_iiPi, .-_Z10kernel_mulPcS_S_iiPi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z10kernel_mulPcS_S_iiPi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z10kernel_mulPcS_S_iiPi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void kernel_mul(char* newB, char* first, char* second, int size_first, int size_second, int * size_newB) {
int i = threadIdx.x;
int j = threadIdx.y;
int tid = j * gridDim.x * blockDim.x + i ;
if(j!=0 && i!=0){
newB[tid] = first[i] * second[j];
}
if(j==0 && i==0){
if(first[j] != second[i])
newB[0]='-';
else
newB[0]='+';
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void kernel_mul(char* newB, char* first, char* second, int size_first, int size_second, int * size_newB) {
int i = threadIdx.x;
int j = threadIdx.y;
int tid = j * gridDim.x * blockDim.x + i ;
if(j!=0 && i!=0){
newB[tid] = first[i] * second[j];
}
if(j==0 && i==0){
if(first[j] != second[i])
newB[0]='-';
else
newB[0]='+';
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void kernel_mul(char* newB, char* first, char* second, int size_first, int size_second, int * size_newB) {
int i = threadIdx.x;
int j = threadIdx.y;
int tid = j * gridDim.x * blockDim.x + i ;
if(j!=0 && i!=0){
newB[tid] = first[i] * second[j];
}
if(j==0 && i==0){
if(first[j] != second[i])
newB[0]='-';
else
newB[0]='+';
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10kernel_mulPcS_S_iiPi
.globl _Z10kernel_mulPcS_S_iiPi
.p2align 8
.type _Z10kernel_mulPcS_S_iiPi,@function
_Z10kernel_mulPcS_S_iiPi:
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[8:9], s[0:1], 0x10
v_bfe_u32 v1, v0, 10, 10
v_and_b32_e32 v0, 0x3ff, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_ne_u32_e32 vcc_lo, 0, v1
v_cmp_ne_u32_e64 s2, 0, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s3, vcc_lo, s2
s_and_saveexec_b32 s2, s3
s_cbranch_execz .LBB0_2
s_waitcnt lgkmcnt(0)
global_load_u8 v4, v0, s[6:7]
global_load_u8 v5, v1, s[8:9]
s_clause 0x1
s_load_b32 s3, s[0:1], 0x28
s_load_b32 s0, s[0:1], 0x34
s_waitcnt lgkmcnt(0)
v_mul_lo_u32 v6, s3, v1
s_and_b32 s0, s0, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[2:3], null, v6, s0, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v3, 31, v2
v_add_co_u32 v2, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
s_waitcnt vmcnt(0)
v_mul_lo_u16 v4, v5, v4
global_store_b8 v[2:3], v4, off
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s2
v_or_b32_e32 v0, v1, v0
s_mov_b32 s0, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_4
v_mov_b32_e32 v0, 0
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_load_u8 v1, v0, s[6:7]
global_load_u8 v2, v0, s[8:9]
s_waitcnt vmcnt(0)
v_cmp_eq_u32_e32 vcc_lo, v1, v2
v_cndmask_b32_e64 v1, 45, 43, vcc_lo
global_store_b8 v0, v1, s[4:5]
.LBB0_4:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10kernel_mulPcS_S_iiPi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 10
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10kernel_mulPcS_S_iiPi, .Lfunc_end0-_Z10kernel_mulPcS_S_iiPi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10kernel_mulPcS_S_iiPi
.private_segment_fixed_size: 0
.sgpr_count: 12
.sgpr_spill_count: 0
.symbol: _Z10kernel_mulPcS_S_iiPi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void kernel_mul(char* newB, char* first, char* second, int size_first, int size_second, int * size_newB) {
int i = threadIdx.x;
int j = threadIdx.y;
int tid = j * gridDim.x * blockDim.x + i ;
if(j!=0 && i!=0){
newB[tid] = first[i] * second[j];
}
if(j==0 && i==0){
if(first[j] != second[i])
newB[0]='-';
else
newB[0]='+';
}
} | .text
.file "kernel_mul.hip"
.globl _Z25__device_stub__kernel_mulPcS_S_iiPi # -- Begin function _Z25__device_stub__kernel_mulPcS_S_iiPi
.p2align 4, 0x90
.type _Z25__device_stub__kernel_mulPcS_S_iiPi,@function
_Z25__device_stub__kernel_mulPcS_S_iiPi: # @_Z25__device_stub__kernel_mulPcS_S_iiPi
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 12(%rsp)
movl %r8d, 8(%rsp)
movq %r9, 64(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
leaq 8(%rsp), %rax
movq %rax, 128(%rsp)
leaq 64(%rsp), %rax
movq %rax, 136(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z10kernel_mulPcS_S_iiPi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z25__device_stub__kernel_mulPcS_S_iiPi, .Lfunc_end0-_Z25__device_stub__kernel_mulPcS_S_iiPi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10kernel_mulPcS_S_iiPi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10kernel_mulPcS_S_iiPi,@object # @_Z10kernel_mulPcS_S_iiPi
.section .rodata,"a",@progbits
.globl _Z10kernel_mulPcS_S_iiPi
.p2align 3, 0x0
_Z10kernel_mulPcS_S_iiPi:
.quad _Z25__device_stub__kernel_mulPcS_S_iiPi
.size _Z10kernel_mulPcS_S_iiPi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z10kernel_mulPcS_S_iiPi"
.size .L__unnamed_1, 25
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__kernel_mulPcS_S_iiPi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10kernel_mulPcS_S_iiPi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z10kernel_mulPcS_S_iiPi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R8, SR_TID.Y ; /* 0x0000000000087919 */
/* 0x000e220000002200 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0030*/ BSSY B0, 0x160 ; /* 0x0000012000007945 */
/* 0x000fe40003800000 */
/*0040*/ S2R R11, SR_TID.X ; /* 0x00000000000b7919 */
/* 0x000e620000002100 */
/*0050*/ ISETP.NE.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x001fc80003f05270 */
/*0060*/ ISETP.EQ.OR P0, PT, R11, RZ, !P0 ; /* 0x000000ff0b00720c */
/* 0x002fe40004702670 */
/*0070*/ LOP3.LUT P1, RZ, R8, R11, RZ, 0xfc, !PT ; /* 0x0000000b08ff7212 */
/* 0x000fd6000782fcff */
/*0080*/ @P0 BRA 0x150 ; /* 0x000000c000000947 */
/* 0x000fea0003800000 */
/*0090*/ IADD3 R4, P0, R11.reuse, c[0x0][0x168], RZ ; /* 0x00005a000b047a10 */
/* 0x040fe40007f1e0ff */
/*00a0*/ IADD3 R2, P2, R8.reuse, c[0x0][0x170], RZ ; /* 0x00005c0008027a10 */
/* 0x040fe40007f5e0ff */
/*00b0*/ LEA.HI.X.SX32 R5, R11, c[0x0][0x16c], 0x1, P0 ; /* 0x00005b000b057a11 */
/* 0x000fe400000f0eff */
/*00c0*/ LEA.HI.X.SX32 R3, R8, c[0x0][0x174], 0x1, P2 ; /* 0x00005d0008037a11 */
/* 0x000fc800010f0eff */
/*00d0*/ LDG.E.U8 R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea8000c1e1100 */
/*00e0*/ LDG.E.U8 R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1100 */
/*00f0*/ IMAD R0, R8, c[0x0][0xc], RZ ; /* 0x0000030008007a24 */
/* 0x000fc800078e02ff */
/*0100*/ IMAD R0, R0, c[0x0][0x0], R11 ; /* 0x0000000000007a24 */
/* 0x000fca00078e020b */
/*0110*/ IADD3 R6, P0, R0, c[0x0][0x160], RZ ; /* 0x0000580000067a10 */
/* 0x000fc80007f1e0ff */
/*0120*/ LEA.HI.X.SX32 R7, R0, c[0x0][0x164], 0x1, P0 ; /* 0x0000590000077a11 */
/* 0x000fe200000f0eff */
/*0130*/ IMAD R9, R2, R5, RZ ; /* 0x0000000502097224 */
/* 0x004fca00078e02ff */
/*0140*/ STG.E.U8 [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x0001e6000c101104 */
/*0150*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0160*/ @P1 EXIT ; /* 0x000000000000194d */
/* 0x000fea0003800000 */
/*0170*/ IADD3 R6, P0, R8.reuse, c[0x0][0x168], RZ ; /* 0x00005a0008067a10 */
/* 0x041fe40007f1e0ff */
/*0180*/ IADD3 R4, P1, R11.reuse, c[0x0][0x170], RZ ; /* 0x00005c000b047a10 */
/* 0x040fe40007f3e0ff */
/*0190*/ LEA.HI.X.SX32 R7, R8, c[0x0][0x16c], 0x1, P0 ; /* 0x00005b0008077a11 */
/* 0x000fe400000f0eff */
/*01a0*/ LEA.HI.X.SX32 R5, R11, c[0x0][0x174], 0x1, P1 ; /* 0x00005d000b057a11 */
/* 0x000fc800008f0eff */
/*01b0*/ LDG.E.U8 R7, [R6.64] ; /* 0x0000000406077981 */
/* 0x000ea8000c1e1100 */
/*01c0*/ LDG.E.U8 R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea2000c1e1100 */
/*01d0*/ IMAD.MOV.U32 R0, RZ, RZ, 0x2d ; /* 0x0000002dff007424 */
/* 0x000fe400078e00ff */
/*01e0*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff027624 */
/* 0x000fe400078e00ff */
/*01f0*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff037624 */
/* 0x000fe200078e00ff */
/*0200*/ ISETP.NE.AND P0, PT, R7, R4, PT ; /* 0x000000040700720c */
/* 0x004fda0003f05270 */
/*0210*/ @P0 STG.E.U8 [R2.64], R0 ; /* 0x0000000002000986 */
/* 0x0001e2000c101104 */
/*0220*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0230*/ IMAD.MOV.U32 R0, RZ, RZ, 0x2b ; /* 0x0000002bff007424 */
/* 0x001fca00078e00ff */
/*0240*/ STG.E.U8 [R2.64], R0 ; /* 0x0000000002007986 */
/* 0x000fe2000c101104 */
/*0250*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0260*/ BRA 0x260; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10kernel_mulPcS_S_iiPi
.globl _Z10kernel_mulPcS_S_iiPi
.p2align 8
.type _Z10kernel_mulPcS_S_iiPi,@function
_Z10kernel_mulPcS_S_iiPi:
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[8:9], s[0:1], 0x10
v_bfe_u32 v1, v0, 10, 10
v_and_b32_e32 v0, 0x3ff, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_ne_u32_e32 vcc_lo, 0, v1
v_cmp_ne_u32_e64 s2, 0, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s3, vcc_lo, s2
s_and_saveexec_b32 s2, s3
s_cbranch_execz .LBB0_2
s_waitcnt lgkmcnt(0)
global_load_u8 v4, v0, s[6:7]
global_load_u8 v5, v1, s[8:9]
s_clause 0x1
s_load_b32 s3, s[0:1], 0x28
s_load_b32 s0, s[0:1], 0x34
s_waitcnt lgkmcnt(0)
v_mul_lo_u32 v6, s3, v1
s_and_b32 s0, s0, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[2:3], null, v6, s0, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v3, 31, v2
v_add_co_u32 v2, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
s_waitcnt vmcnt(0)
v_mul_lo_u16 v4, v5, v4
global_store_b8 v[2:3], v4, off
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s2
v_or_b32_e32 v0, v1, v0
s_mov_b32 s0, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_4
v_mov_b32_e32 v0, 0
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_load_u8 v1, v0, s[6:7]
global_load_u8 v2, v0, s[8:9]
s_waitcnt vmcnt(0)
v_cmp_eq_u32_e32 vcc_lo, v1, v2
v_cndmask_b32_e64 v1, 45, 43, vcc_lo
global_store_b8 v0, v1, s[4:5]
.LBB0_4:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10kernel_mulPcS_S_iiPi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 10
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10kernel_mulPcS_S_iiPi, .Lfunc_end0-_Z10kernel_mulPcS_S_iiPi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10kernel_mulPcS_S_iiPi
.private_segment_fixed_size: 0
.sgpr_count: 12
.sgpr_spill_count: 0
.symbol: _Z10kernel_mulPcS_S_iiPi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0003f9d3_00000000-6_kernel_mul.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z38__device_stub__Z10kernel_mulPcS_S_iiPiPcS_S_iiPi
.type _Z38__device_stub__Z10kernel_mulPcS_S_iiPiPcS_S_iiPi, @function
_Z38__device_stub__Z10kernel_mulPcS_S_iiPiPcS_S_iiPi:
.LFB2051:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movq %r9, 8(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z10kernel_mulPcS_S_iiPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z38__device_stub__Z10kernel_mulPcS_S_iiPiPcS_S_iiPi, .-_Z38__device_stub__Z10kernel_mulPcS_S_iiPiPcS_S_iiPi
.globl _Z10kernel_mulPcS_S_iiPi
.type _Z10kernel_mulPcS_S_iiPi, @function
_Z10kernel_mulPcS_S_iiPi:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z38__device_stub__Z10kernel_mulPcS_S_iiPiPcS_S_iiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z10kernel_mulPcS_S_iiPi, .-_Z10kernel_mulPcS_S_iiPi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z10kernel_mulPcS_S_iiPi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z10kernel_mulPcS_S_iiPi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "kernel_mul.hip"
.globl _Z25__device_stub__kernel_mulPcS_S_iiPi # -- Begin function _Z25__device_stub__kernel_mulPcS_S_iiPi
.p2align 4, 0x90
.type _Z25__device_stub__kernel_mulPcS_S_iiPi,@function
_Z25__device_stub__kernel_mulPcS_S_iiPi: # @_Z25__device_stub__kernel_mulPcS_S_iiPi
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 12(%rsp)
movl %r8d, 8(%rsp)
movq %r9, 64(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
leaq 8(%rsp), %rax
movq %rax, 128(%rsp)
leaq 64(%rsp), %rax
movq %rax, 136(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z10kernel_mulPcS_S_iiPi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z25__device_stub__kernel_mulPcS_S_iiPi, .Lfunc_end0-_Z25__device_stub__kernel_mulPcS_S_iiPi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10kernel_mulPcS_S_iiPi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10kernel_mulPcS_S_iiPi,@object # @_Z10kernel_mulPcS_S_iiPi
.section .rodata,"a",@progbits
.globl _Z10kernel_mulPcS_S_iiPi
.p2align 3, 0x0
_Z10kernel_mulPcS_S_iiPi:
.quad _Z25__device_stub__kernel_mulPcS_S_iiPi
.size _Z10kernel_mulPcS_S_iiPi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z10kernel_mulPcS_S_iiPi"
.size .L__unnamed_1, 25
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__kernel_mulPcS_S_iiPi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10kernel_mulPcS_S_iiPi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /*
* FileName: RayTracer_Kernel.cu
*
* Programmer: Jiayin Cao
*/
//the sum for scan
int* g_ScanSum[2];
//some helper functions
__device__ void d_normalize( float4* v )
{
float s = v->x * v->x + v->y * v->y + v->z * v->z;
s = sqrt(s);
v->x /= s;
v->y /= s;
v->z /= s;
}
//cross product
__device__ float4 d_cross( const float4& v1 , const float4& v2 )
{
float4 r;
r.x = v1.y * v2.z - v1.z * v2.y;
r.y = v1.z * v2.x - v1.x * v2.z;
r.z = v1.x * v2.y - v1.y * v2.x;
r.w = 0.0f;
return r;
}
//clamp the value
__device__ float d_clamp( const float v )
{
if( v > 1.0f )
return 1.0f;
if( v < 0.0f )
return 0.0f;
return v;
}
//clamp the float4
__device__ float4 d_saturate( const float4& v )
{
return make_float4( d_clamp( v.x ) , d_clamp( v.y ) , d_clamp( v.z ) , d_clamp( v.w ) );
}
//dot product
__device__ float d_dot( const float4& v1 , const float4& v2 )
{
return v1.x * v2.x + v1.y * v2.y + v1.z * v2.z ;
}
//the length of the vector
__device__ float d_length( const float4& v )
{
return sqrt( v.x * v.x + v.y * v.y + v.z * v.z );
}
//define some useful operators for float4
__device__ float4 operator+ ( const float4& v1 , const float4& v2 )
{
return make_float4( v1.x + v2.x , v1.y + v2.y , v1.z + v2.z , v1.w + v2.w );
}
__device__ float4 operator- ( const float4& v1 , const float4& v2 )
{
return make_float4( v1.x - v2.x , v1.y - v2.y , v1.z - v2.z , v1.w - v2.w );
}
__device__ float4 operator* ( const float4& v , const float d )
{
return make_float4( v.x * d , v.y * d , v.z * d , v.w * d );
}
__device__ float4 operator* ( const float d , const float4& v )
{
return make_float4( v.x * d , v.y * d , v.z * d , v.w * d );
}
__device__ float4 operator* ( const float4& v1 , const float4& v2 )
{
return make_float4( v1.x * v2.x , v1.y * v2.y , v1.z * v2.z , v1.w * v2.w );
}
__device__ float4 operator+= ( float4& v1 , const float4& v2 )
{
v1 = v1 + v2;
return v1;
}
__device__ float2 operator * ( const float d , const float2& v )
{
return make_float2( d * v.x , d * v.y );
}
__device__ float2 operator + ( const float2& v1 , const float2& v2 )
{
return make_float2( v1.x + v2.x , v1.y + v2.y );
}
__device__ float2 operator - ( const float2& v1 , const float2& v2 )
{
return make_float2( v1.x - v2.x , v1.y - v2.y );
}
__device__ float2 floor( const float2& v )
{
int x = (int) v.x ;
int y = (int) v.y ;
return make_float2( x , y );
}
//reflect direction
__device__ float4 d_reflect( const float4& dir , const float4& normal )
{
float dotProduct = ( -2.0f ) * d_dot( dir , normal );
float4 r = dir + dotProduct * normal;
return make_float4( r.x , r.y , r.z , 0.0f );
}
//refraction direction
__device__ float4 d_refract( const float4& dir , float4 normal , float rate )
{
float4 r;
if( d_dot( dir , normal ) > 0 )
{
normal = -1.0f * normal;
rate = 1.0f / rate;
}
float cos = -1.0f * d_dot( dir , normal );
float t = 1 - rate * rate * ( 1 - cos * cos );
if( t < 0 )
{
r = d_reflect( dir , normal );
}else
{
float cos2 = sqrt( t );
r = rate * dir + ( rate * cos - cos2 ) * normal ;
}
return r;
}
//check if the ray intersects with bounding box
__device__ float4 kernelIntersectBoundingBox( float4& ori , float4& dir , float4& min , float4& max , float length )
{
//the result
float4 result = make_float4( 0.0f , 9999999.0f , 0.0f , 0.0f );
//limit the maxium value
if( length > 0 )
result.y = length;
//the variables
float t1 , t2;
if( fabs( dir.x ) < 0.0000001f )
{
if( ori.x > max.x || ori.x < min.x )
return result;
}else
{
t1 = ( max.x - ori.x ) / dir.x;
t2 = ( min.x - ori.x ) / dir.x;
if( t1 > t2 ) { float t = t1; t1 = t2; t2 = t; }
//clamp
if( t1 > result.x ) result.x = t1;
if( t2 < result.y ) result.y = t2;
if( result.x > result.y )
return result;
}
if( fabs( dir.y ) < 0.0000001f )
{
if( ori.y > max.y || ori.y < min.y )
return result;
}else
{
t1 = ( max.y - ori.y ) / dir.y;
t2 = ( min.y - ori.y ) / dir.y;
if( t1 > t2 ) { float t = t1; t1 = t2; t2 = t; }
//clamp
if( t1 > result.x ) result.x = t1;
if( t2 < result.y ) result.y = t2;
if( result.x > result.y )
return result;
}
if( fabs( dir.y ) < 0.0000001f )
{
if( ori.z > max.z || ori.z < min.z )
return result;
}else
{
t1 = ( max.z - ori.z ) / dir.z;
t2 = ( min.z - ori.z ) / dir.z;
if( t1 > t2 ) { float t = t1; t1 = t2; t2 = t; }
//clamp
if( t1 > result.x ) result.x = t1;
if( t2 < result.y ) result.y = t2;
if( result.x > result.y )
return result;
}
//enable the intersected point
result.z = 1.0f;
return result;
}
//check if the ray intersects with a plane
__device__ float4 kernelIntersectPlane( const float4& v1 , const float4& v2 , const float4& v3 , const float4& ori , const float4& dir )
{
//w : >= 0 ( intersected point enable ) , < 0 ( disable )
float4 result = make_float4( 0.0f , 0.0f , 0.0f , 0.0f );
//get the normal of the plane
float4 normal = d_cross( v2 - v1 , v3 - v1 );
//get the factor
float t = d_dot( normal , ori - v1 ) / d_dot( normal , dir );
//set the result
result = ori - t * dir;
if( t <= 0.0f )
result.w = -t;
else
result.w = -1;
return result;
}
//check if the ray intersects with a triangle
__device__ float4 kernelIntersectTriangle( const float4& v1 , const float4& v2 , const float4& v3 , const float4& ori , const float4& dir )
{
//the result
float4 result = kernelIntersectPlane( v1 , v2 , v3 , ori , dir );
if( result.w < 0 )
return result;
//get the factor
float4 d1 = d_cross( result - v2 , v1 - v2 );
float4 d2 = d_cross( result - v3 , v2 - v3 );
float4 d3 = d_cross( result - v1 , v3 - v1 );
float f1 = d_dot( d1 , d2 );
float f2 = d_dot( d2 , d3 );
if( !( f1 >= -0.000000000000001f && f2 >= -0.000000000000001f ) )
result.w = -1.0f;
return result;
}
//check if the current point is in the bounding box
__device__ int kernelPointInBoundingBox( const float4& p , const float4& min , const float4& max )
{
float threshold = 0.00001f;
if( p.x < min.x - threshold || p.y < min.y - threshold || p.z < min.z - threshold ||
p.x > max.x + threshold || p.y > max.y + threshold || p.z > max.z + threshold )
return false;
return true;
}
//do interplotation
__device__ float4 kernelInterploted( const float4& v1 , const float4& v2 , const float4& v3 , const float4& intersected )
{
//get the vectors
float4 e1 = intersected - v1;
float4 e2 = intersected - v2;
float4 e3 = intersected - v3;
//compute the areas
float4 area;
area.x = d_length( d_cross( e2 , e3 ) );
area.y = d_length( d_cross( e3 , e1 ) );
area.z = d_length( d_cross( e1 , e2 ) );
float d = 1.0f / ( area.x + area.y + area.z );
return area * d;
}
//clear and initialize buffer
__global__ void kernelInitBuffer( float4* buffer ,
int* markedBuffer ,
int pixelNum )
{
//get the thread id
int tid = threadIdx.x + blockIdx.x * blockDim.x;
//limit the thread id
if( tid >= pixelNum )
return;
buffer[tid] = make_float4( 0.0f , 0.0f , 0.0f , 0.0f );
markedBuffer[tid] = tid;
}
//generate primary ray intersected result
__global__ void kernelGenerateIntersectedPoint( float4* rayOri ,
float4* rayDir ,
float4* vertexBuffer ,
int rayNum ,
int* index ,
float4* result )
{
//get the thread id
int tid = threadIdx.x + blockIdx.x * blockDim.x;
//limit the thread id
if( tid >= rayNum )
return;
//Load the vertex
int triId = index[tid];
//get the vertex
int id = 3 * triId;
float4 v1 = vertexBuffer[id];
float4 v2 = vertexBuffer[id+1];
float4 v3 = vertexBuffer[id+2];
//ray ori and dir
float4 ori = rayOri[tid];
float4 dir = rayDir[tid];
//get the intersected result
result[tid] = kernelIntersectPlane( v1 , v2 , v3 , ori , dir );
result[tid].w = triId;
}
//Generate primary rays
__global__ void kernelGeneratePrimaryRays( float4 viewInfo ,
float* invViewMatrix ,
float4* rayOri ,
float4* rayDir )
{
//get the thread id
int tid = threadIdx.x + blockIdx.x * blockDim.x;
//limit the thread id
if( tid >= (int)viewInfo.x * (int)viewInfo.y )
return;
// get the pixel coorindate first
uint2 coord;
coord.x = tid % (int) viewInfo.x;
coord.y = tid / (int)viewInfo.x;
// compute the vector of the ray in screen space
float2 v;
v.x = ( ( ( 2.0f * coord.x ) / viewInfo.x ) - 1.0f ) / viewInfo.z;
v.y = -1.0f * ( ( ( 2.0f * coord.y ) / viewInfo.y ) - 1.0f ) / viewInfo.w;
//copy the original point of the rays
rayOri[tid] = make_float4( invViewMatrix[12] , invViewMatrix[13] , invViewMatrix[14] , tid );
//compute the direction of the ray
float4 dir;
dir.x = ( v.x * invViewMatrix[0] + v.y * invViewMatrix[4] + invViewMatrix[8] );
dir.y = ( v.x * invViewMatrix[1] + v.y * invViewMatrix[5] + invViewMatrix[9] );
dir.z = ( v.x * invViewMatrix[2] + v.y * invViewMatrix[6] + invViewMatrix[10] );
dir.w = 0.0f;
d_normalize( &dir );
rayDir[tid] = make_float4( dir.x , dir.y , dir.z , 1.0f );
}
//traverse the ray through kd-tree
__device__ float4 kernelTraverseRay( float4* kdTree ,
int* indexMap ,
int* offsetBuffer ,
float4* vertexBuffer ,
float4& rayOri ,
float4& rayDir ,
float length )
{
//the intersected result
float4 result = make_float4( 0.0f , 0.0f , 0.0f , -1.0f );
//tree node information
float4 header;
float4 splitInfo;
//the bounding box
float4 minBB = kdTree[2];
float4 maxBB = kdTree[3];
//check if the ray intersects with the current bounding box of the root
result = kernelIntersectBoundingBox( rayOri , rayDir , minBB , maxBB , length );
//if the ray doesn't cross the kd-tree , just return
if( result.z < 0.5f )
{
result = make_float4( 0.0f , 0.0f , 0.0f , -1.0f );
return result;
}
//current traversing node
int currentNodeIndex = 0;
//the mask to mark the traversed node
unsigned int mask = 0;
//current traverse depth
int currentTraverseDepth = 0;
//current inPonit when traversing the node
float4 inPoint = rayOri + result.x * rayDir ;
while( currentTraverseDepth >= 0 )
{
//traverse the current node
do
{
//the current node offset
int currentNodeOffset = currentNodeIndex * 4;
//get the current node information
header = kdTree[ currentNodeOffset ];
splitInfo = kdTree[currentNodeOffset + 1 ];
//check if it's a leaf node
if( splitInfo.x < 0 )
break;
//get the split axis
int splitAxis = (int) splitInfo.x;
//get the pointer of the inPoint
float sPos = 0.0f;
if( splitAxis == 0 )
sPos = inPoint.x;
else if( splitAxis == 1 )
sPos = inPoint.y;
else if( splitAxis == 2 )
sPos = inPoint.z;
//update the virtual stack and traverse the node
if( splitInfo.y > sPos )
currentNodeIndex = (int)header.y;
else
currentNodeIndex = (int)header.z;
//increase the current traverse depth
currentTraverseDepth++;
}while( true );
//get the offset and triangle number
int triOffset = offsetBuffer[currentNodeIndex];
int triNumber = (int)header.w;
//min value
float minFactor = 9999999.0f;
if( length > 0 )
minFactor = length;
//triangle index
int oriTriIndex = -1;
//the bounding box
minBB = kdTree[currentNodeIndex*4+2];
maxBB = kdTree[currentNodeIndex*4+3];
//intersect with the current triangles
for( int i = 0 ; i < triNumber ; i++ )
{
//get the triangles
int triIndex = indexMap[triOffset+i];
//get the vertex
float4 v1 = vertexBuffer[3*triIndex];
float4 v2 = vertexBuffer[3*triIndex+1];
float4 v3 = vertexBuffer[3*triIndex+2];
//get the intersected point
result = kernelIntersectTriangle( v1 , v2 , v3 , rayOri , rayDir );
//limit the factor
if( result.w > 0.0f && result.w < minFactor )
{
if( kernelPointInBoundingBox( result , minBB , maxBB ) )
{
minFactor = result.w;
oriTriIndex = triIndex;
if( length > 0 )
break;
}
}
}
if( oriTriIndex >= 0 )
{
result = rayOri + minFactor * rayDir;
result.w = (float)oriTriIndex;
return result;
}
//back track here
while( currentTraverseDepth >= 0 )
{
if( currentTraverseDepth == 0 )
return make_float4( 0 , 0 , 0 , -1.0f );
//get the current mask
if( mask & ( 0x00000001 << currentTraverseDepth ) )
{
//update the mask
mask &= ~(0x00000001 << currentTraverseDepth );
//decrease the current depth;
currentTraverseDepth--;
//get to the father node
currentNodeIndex = (int)kdTree[ 4 * currentNodeIndex ].x;
//continue to next level
continue;
}
//check the other node
int otherNode = currentNodeIndex + 1;
if( currentNodeIndex % 2 == 0 )
otherNode -= 2;
//get the bounding box of the other node
int otherNodeOffset = 4 * otherNode;
minBB = kdTree[ otherNodeOffset + 2 ];
maxBB = kdTree[ otherNodeOffset + 3 ];
//get the intersected result
float4 bi = kernelIntersectBoundingBox( rayOri , rayDir , minBB , maxBB , length );
if( bi.z > 0.5f )
{
//update the current traverse node
currentNodeIndex = otherNode;
//update the inPoint
inPoint = rayOri + bi.x * rayDir ;
//update the mask
mask |= 0x00000001 << currentTraverseDepth;
break;
}else
{
//update the mask
mask &= ~( 0x00000001 << currentTraverseDepth );
//decrease current depth
currentTraverseDepth--;
//get to the father node
currentNodeIndex = (int) kdTree[ 4 * currentNodeIndex ].x;
}
}
}
result.w = -1.0f;
return result;
}
//get the interseced point
__global__ void kernelGetIntersectedPoint( float4* rayOri ,
float4* rayDir ,
float4* kdTree ,
int* indexMap ,
int* offsetBuffer ,
float4* vertexBuffer ,
int rayNumber ,
float4* result )
{
//get the thread id
int tid = threadIdx.x + blockIdx.x * blockDim.x;
//limit the thread id
if( tid >= rayNumber )
return;
//get the triangle
result[tid] = kernelTraverseRay( kdTree , indexMap , offsetBuffer , vertexBuffer , rayOri[tid] , rayDir[tid] , -1.0f );
}
//do pixel shader here
__global__ void kernelPixelShader( float4* intersected ,
float4* vertexBuffer ,
float4* normalBuffer ,
float2* texCoordinateBuffer ,
float4* kdTree ,
int* indexMap ,
int* offsetIndexBuffer,
float4* lightBuffer ,
int* attributeBuffer ,
float4* materialBuffer ,
int* textureOffset ,
float4* customTexture ,
int pixelNum ,
float4* rayDir ,
int* offsetBuffer ,
float4* destNormalBuffer ,
float4* imageBuffer )
{
//get the thread id
int tid = threadIdx.x + blockIdx.x * blockDim.x;
//limit the thread id
if( tid >= pixelNum )
return;
//get the triangle index
int triIndex = (int)intersected[tid].w;
int triOffset = 3 * triIndex;
float4 color = make_float4( 0.0f , 0.0f , 0.0f , 0.0f );
//load the density of the pixel
if( triIndex < 0 )
return;
//get the material index
int matIndex = attributeBuffer[triIndex];
//the material buffer
float4 ambient = materialBuffer[ 4 * matIndex ];
float4 diffuse = materialBuffer[ 4 * matIndex + 1 ];
float4 specular = materialBuffer[ 4 * matIndex + 2 ];
float4 matprop = materialBuffer[ 4 * matIndex + 3 ];
//load the vertex
float4 v1 = vertexBuffer[ triOffset ];
float4 v2 = vertexBuffer[ triOffset + 1 ];
float4 v3 = vertexBuffer[ triOffset + 2 ];
//get the interploted
float4 interploted = kernelInterploted( v1 , v2 , v3 , intersected[tid] );
//get the normal
float4 n1 = normalBuffer[ triOffset ];
float4 n2 = normalBuffer[ triOffset + 1 ];
float4 n3 = normalBuffer[ triOffset + 2 ];
float4 normal = n1 * interploted.x + n2 * interploted.y + n3 * interploted.z;
d_normalize( &normal );
//update the normal buffer
destNormalBuffer[tid] = normal;
destNormalBuffer[tid].w = matIndex;
//the density for the pixel
float density = rayDir[tid].w;
if( matprop.x > -0.5f )
{
//load the texture coordinate
float2 t1 = texCoordinateBuffer[ triOffset ];
float2 t2 = texCoordinateBuffer[ triOffset + 1 ];
float2 t3 = texCoordinateBuffer[ triOffset + 2 ];
float2 texCoord = interploted.x * t1 + interploted.y * t2 + interploted.z * t3;
texCoord = texCoord - floor( texCoord );
if( texCoord.x < 0.0f ) texCoord.x += 1.0f;
if( texCoord.y < 0.0f ) texCoord.y += 1.0f;
//load the texture
float4* imgData = customTexture + textureOffset[(int)matprop.x];
int x = imgData[0].y * texCoord.x ;
int y = imgData[0].z * texCoord.y ;
int texOffset = y * imgData[0].y + x + 1;
diffuse = diffuse * (*(imgData + texOffset)) ;
}
//initialize the image buffer
color = ambient;
//shade the pixels
for( int i = 0 ; i < 2 ; i++ )
{
if( lightBuffer[i].w < 0.01f )
continue;
//the light direction
float4 lightDir = intersected[tid] - lightBuffer[i];
//check if the point is in the shadow
float shadowLen = 0.98f * d_length(lightDir);
d_normalize( &lightDir );
//the dot product
float dotProduct = d_dot( lightDir , normal );
if( dotProduct > 0.0f )
continue;
{
float4 shadowFactor = kernelTraverseRay( kdTree , indexMap , offsetIndexBuffer , vertexBuffer , lightBuffer[i] , lightDir , shadowLen );
if( shadowFactor.w >= 0.0f )
continue;
}
//the light density
float lightDensity = d_clamp( -1.0f * dotProduct ) * lightBuffer[i].w;
//load the density of current pixel
color += diffuse * lightDensity ;
//add specular if possible
if( specular.w > 0 )
{
//reflect direction
float4 reflectDir = d_reflect( lightDir , normal );
d_normalize( &reflectDir );
//get the dot product
float d = d_clamp(-d_dot( reflectDir , rayDir[tid] ));
if( d > 0 )
color += pow( d , specular.w ) * specular;
}
}
int offset = offsetBuffer[tid];
imageBuffer[offset] = d_saturate( imageBuffer[offset] + d_saturate( color * density ) );
}
//generate next level rays
__global__ void kernelGenerateNextLevelRays( float4* materialInfo ,
float4* intersected ,
float4* backNormalBuffer ,
float4* rayOri ,
float4* rayDir ,
int rayNumber ,
float4* destRayOri ,
float4* destRayDir ,
int* markedBuffer )
{
//get the thread id
int tid = threadIdx.x + blockIdx.x * blockDim.x;
//limit the thread id
if( tid >= rayNumber )
return;
//set marked buffer zero
markedBuffer[tid] = 0;
//load the intersected point
float4 intersectedPoint = intersected[tid];
//get the intersected triangle index
int triIndex = (int)intersectedPoint.w;
if( triIndex < 0 )
return;
//load the normal
float4 normal = backNormalBuffer[tid];
//get the material index
int matIndex = (int)normal.w;
//get the material
float4 matInfo = materialInfo[4*matIndex+3];
//load the ray direction
float4 ori = rayOri[tid];
float4 dir = rayDir[tid];
//if there is reflection , mark result as true
if( matInfo.y > 0 )
{
float4 reflectDir = d_reflect( dir , normal );
d_normalize( &reflectDir );
reflectDir.w = dir.w * matInfo.y;
destRayDir[tid] = reflectDir;
destRayOri[tid] = intersectedPoint + reflectDir * 0.1f;
destRayOri[tid].w = ori.w;
markedBuffer[tid] = 1;
}else if( matInfo.z > 0 )
{
float4 refractDir = d_refract( dir , normal , 1.0f / matInfo.w );
d_normalize( &refractDir );
refractDir.w = dir.w * matInfo.z;
destRayDir[tid] = refractDir;
destRayOri[tid] = intersectedPoint + refractDir * 0.02f;
destRayOri[tid].w = ori.w;
markedBuffer[tid] = 1;
}
}
//copy new rays
__global__ void kernelCopyNewRays( float4* srcRayOri ,
float4* srcRayDir ,
int* scanResult ,
int rayNumber ,
float4* destRayOri ,
float4* destRayDir ,
int* offsets )
{
//get the thread id
int tid = threadIdx.x + blockIdx.x * blockDim.x;
//limit the thread id
if( tid >= rayNumber )
return;
//load the offset
int offset = scanResult[tid];
if( offset != scanResult[tid+1] )
{
//set the result
destRayOri[offset] = srcRayOri[tid];
destRayDir[offset] = srcRayDir[tid];
offsets[offset] = (int)srcRayOri[tid].w;
}
}
//Do scan on GPU
__global__ void kernelScan( int* data , int number , int oBlockRes , int* blockRes )
{
//the shared memory
__shared__ int sharedMem[512];
//get the thread id
int ltid = threadIdx.x;
int gtid = ltid + blockDim.x * blockIdx.x;
//the block sum
int blocksum = 0;
//zero the rest of the memory
if( 2 * gtid >= number )
{
data[ 2 * gtid ] = 0;
data[ 2 * gtid + 1 ] = 0;
}else if( 2 * gtid == number - 1 )
data[ 2 * gtid + 1 ] = 0;
//Load the data into the shared memory
sharedMem[2*ltid] = data[2*gtid];
sharedMem[2*ltid+1] = data[2*gtid+1];
//the offset
int offset = 1;
for( int d = 256 ; d > 1 ; d >>= 1 )
{
//sync the threads in a group
__syncthreads();
if( ltid < d )
{
int ai = offset * ( 2 * ltid + 1 ) - 1;
int bi = ai + offset;
sharedMem[bi] += sharedMem[ai];
}
offset *= 2;
}
//the block sum
blocksum = sharedMem[511] + sharedMem[255];
//clear the last element
if( ltid == 0 )
{
sharedMem[511] = sharedMem[255];
sharedMem[255] = 0;
}
for( int d = 2 ; d < 512 ; d *= 2 )
{
__syncthreads();
offset >>= 1;
if( ltid < d )
{
int ai = offset * ( 2 * ltid + 1 ) - 1 ;
int bi = ai + offset ;
int t = sharedMem[ai];
sharedMem[ai] = sharedMem[bi];
sharedMem[bi] += t;
}
}
__syncthreads();
data[ 2 * gtid ] = sharedMem[ 2 * ltid ];
data[ 2 * gtid + 1 ] = sharedMem[ 2 * ltid + 1 ];
//Output Block Result
if( oBlockRes > 0 )
{
if( ltid == 0 )
{
//copy the result
blockRes[blockIdx.x] = blocksum;
}
}
}
//Add the block result to the segmented scan result
__global__ void kernelUniformAdd( int* data , int* blockResult )
{
//get the thread id
int ltid = threadIdx.x;
int gtid = ltid + blockDim.x * blockIdx.x;
//add the result
data[gtid] += blockResult[gtid/512];
}
//clear the noise of the image
__global__ void kernelClearNoise( float4* imgData ,
int width ,
int height ,
float4* targetData )
{
//get the thread id
int tid = threadIdx.x + blockIdx.x * blockDim.x;
//limit the thread id
if( tid >= width * height )
return;
//threshold
float threshold = 0.4f;
//the difference
int difference = 0;
//current index
int currentIndex = tid;
int leftIndex = tid - 1;
int rightIndex = tid + 1;
int upIndex = tid - width ;
int downIndex = tid + width ;
//the coordinate
int i = tid % width;
int j = tid / width;
//current color
float4 color = imgData[currentIndex];
float4 sum = make_float4( 0 , 0 , 0 , 0 );
if( i > 0 )
{
if( d_length( color - imgData[leftIndex] ) > threshold )
difference++;
sum += imgData[leftIndex];
}
if( i < width - 1 )
{
if( d_length( color - imgData[rightIndex] ) > threshold )
difference++;
sum += imgData[rightIndex];
}
if( j > 0 )
{
if( d_length( color - imgData[upIndex] ) > threshold )
difference++;
sum += imgData[upIndex];
}
if( j < height - 1 )
{
if( d_length( color - imgData[downIndex] ) > threshold )
difference++;
sum += imgData[downIndex];
}
if( difference >= 2 )
color = sum * 0.25f;
targetData[tid] = color;
}
////////////////////////////////////////////////////////////////////////////////////////////////////
//initialize buffer
extern "C" void cudaInitBuffer( float4* buffer ,
int* markedBuffer ,
int pixelNum )
{
//the block number
int threadNum = 256;
int blockNum = ( pixelNum + threadNum - 1 ) / threadNum;
//call the kenrel
kernelInitBuffer<<<blockNum,threadNum>>>( buffer , markedBuffer , pixelNum );
}
//generate primary ray intersected result
extern "C" void cudaGenerateIntersectedPoint( float4* rayOri ,
float4* rayDir ,
float4* vertexBuffer ,
int rayNum ,
int* index ,
float4* result )
{
//the block number
int threadNum = 256;
int blockNum = ( rayNum + threadNum - 1 ) / threadNum;
//call the kernel
kernelGenerateIntersectedPoint<<<blockNum , threadNum>>>( rayOri , rayDir , vertexBuffer , rayNum , index , result );
}
//Generate primary rays
extern "C" void cudaGeneratePrimaryRays( float4 viewInfo ,
float* invViewMatrix ,
float4* rayOri ,
float4* rayDir )
{
//get the number of data
int rayNum = (int)( viewInfo.x * viewInfo.y );
//the block number
int threadNum = 256;
int blockNum = ( rayNum + threadNum - 1 ) / threadNum;
//call the kernel
kernelGeneratePrimaryRays<<<blockNum , threadNum>>>( viewInfo , invViewMatrix , rayOri , rayDir );
}
//get intersected point
extern "C" void cudaGetIntersectedPoint( float4* rayOri ,
float4* rayDir ,
float4* kdTree ,
int* indexMap ,
int* offsetBuffer ,
float4* vertexBuffer ,
int rayNumber ,
float4* result )
{
//the block and thread number
int threadNum = 256;
int blockNum = ( rayNumber + threadNum - 1 ) / threadNum ;
//call the kernel
kernelGetIntersectedPoint<<<blockNum , threadNum>>>( rayOri , rayDir , kdTree , indexMap , offsetBuffer , vertexBuffer , rayNumber , result );
}
//do pixel shader
extern "C" void cudaPixelShader( float4* interseced ,
float4* vertexBuffer ,
float4* normalBuffer ,
float2* texCoordinateBuffer ,
float4* kdTree ,
int* indexMap ,
int* offsetIndexBuffer ,
float4* lightBuffer ,
int* attributeBuffer ,
float4* materialBuffer ,
int* textureOffset ,
float4* customTexture ,
int pixelNum ,
float4* rayDir ,
int* offsetBuffer ,
float4* destNormalBuffer ,
float4* imageBuffer )
{
//the block and thread number
int threadNum = 256;
int blockNum = ( pixelNum + threadNum - 1 ) / threadNum ;
//call the kernel
kernelPixelShader<<<blockNum , threadNum>>>( interseced , vertexBuffer , normalBuffer , texCoordinateBuffer ,
kdTree , indexMap , offsetIndexBuffer , lightBuffer , attributeBuffer , materialBuffer ,
textureOffset , customTexture , pixelNum , rayDir , offsetBuffer , destNormalBuffer , imageBuffer );
}
//generate next level rays
extern "C" void cudaGenerateNextLevelRays( float4* materialInfo ,
float4* intersected ,
float4* backNormalBuffer ,
float4* rayOri ,
float4* rayDir ,
int rayNumber ,
float4* destRayOri ,
float4* destRayDir ,
int* markedBuffer )
{
//the block and thread number
int threadNum = 256;
int blockNum = ( rayNumber + threadNum - 1 ) / threadNum ;
//call the kernel
kernelGenerateNextLevelRays<<<blockNum , threadNum>>>( materialInfo , intersected , backNormalBuffer , rayOri , rayDir ,
rayNumber , destRayOri , destRayDir , markedBuffer );
}
//do scan on gpu
extern "C" void cudaScan( int* data , int num , int level )
{
/* //allocate the number of data
int* cpuData = new int[num];
//pass the data from gpu to cpu
cudaMemcpy( cpuData , data , sizeof( int ) * ( num - 1 ) , cudaMemcpyDeviceToHost );
int last = 0;
for( int i = 0 ; i < num ; i++ )
{
int oldLast = last;
last += cpuData[i];
cpuData[i] = oldLast;
}
//pass the data back from cpu to gpu
cudaMemcpy( data , cpuData , sizeof( int ) * num , cudaMemcpyHostToDevice );
//delete the data
delete[] cpuData;*/
//the dimension of the kernel
dim3 threads( 256 );
dim3 blocks( ( num + 511 ) / 512 );
//call the kernel
kernelScan<<<blocks , threads>>>( data , num , 1 , g_ScanSum[level] );
//scan the block Result
if( num <= 262144 )
kernelScan<<<1 , threads>>>( g_ScanSum[level] , blocks.x , -1 , data );
else
cudaScan( g_ScanSum[level] , blocks.x , level + 1 );
//add the offset
threads.x = 512;
kernelUniformAdd<<< blocks , threads >>> ( data , g_ScanSum[level] );
}
//copy new rays
extern "C" void cudaCopyNewRays( float4* srcRayOri ,
float4* srcRayDir ,
int* scanResult ,
int rayNumber ,
float4* destRayOri ,
float4* destRayDir ,
int* offsets )
{
//the block and thread number
int threadNum = 256;
int blockNum = ( rayNumber + threadNum - 1 ) / threadNum ;
//call the kernel
kernelCopyNewRays<<<blockNum , threadNum>>>( srcRayOri , srcRayDir , scanResult , rayNumber , destRayOri , destRayDir , offsets );
}
//clear the noise of the image
extern "C" void cudaClearNoise( float4* imgData ,
int width ,
int height ,
float4* targetData )
{
//the block and thread number
int threadNum = 256;
int blockNum = ( width * height + 255 ) / 256;
//call the kernel
kernelClearNoise<<<blockNum , threadNum>>>( imgData , width , height , targetData );
} | #include <hip/hip_runtime.h>
/*
* FileName: RayTracer_Kernel.cu
*
* Programmer: Jiayin Cao
*/
//the sum for scan
int* g_ScanSum[2];
//some helper functions
__device__ void d_normalize( float4* v )
{
float s = v->x * v->x + v->y * v->y + v->z * v->z;
s = sqrt(s);
v->x /= s;
v->y /= s;
v->z /= s;
}
//cross product
__device__ float4 d_cross( const float4& v1 , const float4& v2 )
{
float4 r;
r.x = v1.y * v2.z - v1.z * v2.y;
r.y = v1.z * v2.x - v1.x * v2.z;
r.z = v1.x * v2.y - v1.y * v2.x;
r.w = 0.0f;
return r;
}
//clamp the value
__device__ float d_clamp( const float v )
{
if( v > 1.0f )
return 1.0f;
if( v < 0.0f )
return 0.0f;
return v;
}
//clamp the float4
__device__ float4 d_saturate( const float4& v )
{
return make_float4( d_clamp( v.x ) , d_clamp( v.y ) , d_clamp( v.z ) , d_clamp( v.w ) );
}
//dot product
__device__ float d_dot( const float4& v1 , const float4& v2 )
{
return v1.x * v2.x + v1.y * v2.y + v1.z * v2.z ;
}
//the length of the vector
__device__ float d_length( const float4& v )
{
return sqrt( v.x * v.x + v.y * v.y + v.z * v.z );
}
//define some useful operators for float4
__device__ float4 operator+ ( const float4& v1 , const float4& v2 )
{
return make_float4( v1.x + v2.x , v1.y + v2.y , v1.z + v2.z , v1.w + v2.w );
}
__device__ float4 operator- ( const float4& v1 , const float4& v2 )
{
return make_float4( v1.x - v2.x , v1.y - v2.y , v1.z - v2.z , v1.w - v2.w );
}
__device__ float4 operator* ( const float4& v , const float d )
{
return make_float4( v.x * d , v.y * d , v.z * d , v.w * d );
}
__device__ float4 operator* ( const float d , const float4& v )
{
return make_float4( v.x * d , v.y * d , v.z * d , v.w * d );
}
__device__ float4 operator* ( const float4& v1 , const float4& v2 )
{
return make_float4( v1.x * v2.x , v1.y * v2.y , v1.z * v2.z , v1.w * v2.w );
}
__device__ float4 operator+= ( float4& v1 , const float4& v2 )
{
v1 = v1 + v2;
return v1;
}
__device__ float2 operator * ( const float d , const float2& v )
{
return make_float2( d * v.x , d * v.y );
}
__device__ float2 operator + ( const float2& v1 , const float2& v2 )
{
return make_float2( v1.x + v2.x , v1.y + v2.y );
}
__device__ float2 operator - ( const float2& v1 , const float2& v2 )
{
return make_float2( v1.x - v2.x , v1.y - v2.y );
}
__device__ float2 floor( const float2& v )
{
int x = (int) v.x ;
int y = (int) v.y ;
return make_float2( x , y );
}
//reflect direction
__device__ float4 d_reflect( const float4& dir , const float4& normal )
{
float dotProduct = ( -2.0f ) * d_dot( dir , normal );
float4 r = dir + dotProduct * normal;
return make_float4( r.x , r.y , r.z , 0.0f );
}
//refraction direction
__device__ float4 d_refract( const float4& dir , float4 normal , float rate )
{
float4 r;
if( d_dot( dir , normal ) > 0 )
{
normal = -1.0f * normal;
rate = 1.0f / rate;
}
float cos = -1.0f * d_dot( dir , normal );
float t = 1 - rate * rate * ( 1 - cos * cos );
if( t < 0 )
{
r = d_reflect( dir , normal );
}else
{
float cos2 = sqrt( t );
r = rate * dir + ( rate * cos - cos2 ) * normal ;
}
return r;
}
//check if the ray intersects with bounding box
__device__ float4 kernelIntersectBoundingBox( float4& ori , float4& dir , float4& min , float4& max , float length )
{
//the result
float4 result = make_float4( 0.0f , 9999999.0f , 0.0f , 0.0f );
//limit the maxium value
if( length > 0 )
result.y = length;
//the variables
float t1 , t2;
if( fabs( dir.x ) < 0.0000001f )
{
if( ori.x > max.x || ori.x < min.x )
return result;
}else
{
t1 = ( max.x - ori.x ) / dir.x;
t2 = ( min.x - ori.x ) / dir.x;
if( t1 > t2 ) { float t = t1; t1 = t2; t2 = t; }
//clamp
if( t1 > result.x ) result.x = t1;
if( t2 < result.y ) result.y = t2;
if( result.x > result.y )
return result;
}
if( fabs( dir.y ) < 0.0000001f )
{
if( ori.y > max.y || ori.y < min.y )
return result;
}else
{
t1 = ( max.y - ori.y ) / dir.y;
t2 = ( min.y - ori.y ) / dir.y;
if( t1 > t2 ) { float t = t1; t1 = t2; t2 = t; }
//clamp
if( t1 > result.x ) result.x = t1;
if( t2 < result.y ) result.y = t2;
if( result.x > result.y )
return result;
}
if( fabs( dir.y ) < 0.0000001f )
{
if( ori.z > max.z || ori.z < min.z )
return result;
}else
{
t1 = ( max.z - ori.z ) / dir.z;
t2 = ( min.z - ori.z ) / dir.z;
if( t1 > t2 ) { float t = t1; t1 = t2; t2 = t; }
//clamp
if( t1 > result.x ) result.x = t1;
if( t2 < result.y ) result.y = t2;
if( result.x > result.y )
return result;
}
//enable the intersected point
result.z = 1.0f;
return result;
}
//check if the ray intersects with a plane
__device__ float4 kernelIntersectPlane( const float4& v1 , const float4& v2 , const float4& v3 , const float4& ori , const float4& dir )
{
//w : >= 0 ( intersected point enable ) , < 0 ( disable )
float4 result = make_float4( 0.0f , 0.0f , 0.0f , 0.0f );
//get the normal of the plane
float4 normal = d_cross( v2 - v1 , v3 - v1 );
//get the factor
float t = d_dot( normal , ori - v1 ) / d_dot( normal , dir );
//set the result
result = ori - t * dir;
if( t <= 0.0f )
result.w = -t;
else
result.w = -1;
return result;
}
//check if the ray intersects with a triangle
__device__ float4 kernelIntersectTriangle( const float4& v1 , const float4& v2 , const float4& v3 , const float4& ori , const float4& dir )
{
//the result
float4 result = kernelIntersectPlane( v1 , v2 , v3 , ori , dir );
if( result.w < 0 )
return result;
//get the factor
float4 d1 = d_cross( result - v2 , v1 - v2 );
float4 d2 = d_cross( result - v3 , v2 - v3 );
float4 d3 = d_cross( result - v1 , v3 - v1 );
float f1 = d_dot( d1 , d2 );
float f2 = d_dot( d2 , d3 );
if( !( f1 >= -0.000000000000001f && f2 >= -0.000000000000001f ) )
result.w = -1.0f;
return result;
}
//check if the current point is in the bounding box
__device__ int kernelPointInBoundingBox( const float4& p , const float4& min , const float4& max )
{
float threshold = 0.00001f;
if( p.x < min.x - threshold || p.y < min.y - threshold || p.z < min.z - threshold ||
p.x > max.x + threshold || p.y > max.y + threshold || p.z > max.z + threshold )
return false;
return true;
}
//do interplotation
__device__ float4 kernelInterploted( const float4& v1 , const float4& v2 , const float4& v3 , const float4& intersected )
{
//get the vectors
float4 e1 = intersected - v1;
float4 e2 = intersected - v2;
float4 e3 = intersected - v3;
//compute the areas
float4 area;
area.x = d_length( d_cross( e2 , e3 ) );
area.y = d_length( d_cross( e3 , e1 ) );
area.z = d_length( d_cross( e1 , e2 ) );
float d = 1.0f / ( area.x + area.y + area.z );
return area * d;
}
//clear and initialize buffer
__global__ void kernelInitBuffer( float4* buffer ,
int* markedBuffer ,
int pixelNum )
{
//get the thread id
int tid = threadIdx.x + blockIdx.x * blockDim.x;
//limit the thread id
if( tid >= pixelNum )
return;
buffer[tid] = make_float4( 0.0f , 0.0f , 0.0f , 0.0f );
markedBuffer[tid] = tid;
}
//generate primary ray intersected result
__global__ void kernelGenerateIntersectedPoint( float4* rayOri ,
float4* rayDir ,
float4* vertexBuffer ,
int rayNum ,
int* index ,
float4* result )
{
//get the thread id
int tid = threadIdx.x + blockIdx.x * blockDim.x;
//limit the thread id
if( tid >= rayNum )
return;
//Load the vertex
int triId = index[tid];
//get the vertex
int id = 3 * triId;
float4 v1 = vertexBuffer[id];
float4 v2 = vertexBuffer[id+1];
float4 v3 = vertexBuffer[id+2];
//ray ori and dir
float4 ori = rayOri[tid];
float4 dir = rayDir[tid];
//get the intersected result
result[tid] = kernelIntersectPlane( v1 , v2 , v3 , ori , dir );
result[tid].w = triId;
}
//Generate primary rays
__global__ void kernelGeneratePrimaryRays( float4 viewInfo ,
float* invViewMatrix ,
float4* rayOri ,
float4* rayDir )
{
//get the thread id
int tid = threadIdx.x + blockIdx.x * blockDim.x;
//limit the thread id
if( tid >= (int)viewInfo.x * (int)viewInfo.y )
return;
// get the pixel coorindate first
uint2 coord;
coord.x = tid % (int) viewInfo.x;
coord.y = tid / (int)viewInfo.x;
// compute the vector of the ray in screen space
float2 v;
v.x = ( ( ( 2.0f * coord.x ) / viewInfo.x ) - 1.0f ) / viewInfo.z;
v.y = -1.0f * ( ( ( 2.0f * coord.y ) / viewInfo.y ) - 1.0f ) / viewInfo.w;
//copy the original point of the rays
rayOri[tid] = make_float4( invViewMatrix[12] , invViewMatrix[13] , invViewMatrix[14] , tid );
//compute the direction of the ray
float4 dir;
dir.x = ( v.x * invViewMatrix[0] + v.y * invViewMatrix[4] + invViewMatrix[8] );
dir.y = ( v.x * invViewMatrix[1] + v.y * invViewMatrix[5] + invViewMatrix[9] );
dir.z = ( v.x * invViewMatrix[2] + v.y * invViewMatrix[6] + invViewMatrix[10] );
dir.w = 0.0f;
d_normalize( &dir );
rayDir[tid] = make_float4( dir.x , dir.y , dir.z , 1.0f );
}
//traverse the ray through kd-tree
__device__ float4 kernelTraverseRay( float4* kdTree ,
int* indexMap ,
int* offsetBuffer ,
float4* vertexBuffer ,
float4& rayOri ,
float4& rayDir ,
float length )
{
//the intersected result
float4 result = make_float4( 0.0f , 0.0f , 0.0f , -1.0f );
//tree node information
float4 header;
float4 splitInfo;
//the bounding box
float4 minBB = kdTree[2];
float4 maxBB = kdTree[3];
//check if the ray intersects with the current bounding box of the root
result = kernelIntersectBoundingBox( rayOri , rayDir , minBB , maxBB , length );
//if the ray doesn't cross the kd-tree , just return
if( result.z < 0.5f )
{
result = make_float4( 0.0f , 0.0f , 0.0f , -1.0f );
return result;
}
//current traversing node
int currentNodeIndex = 0;
//the mask to mark the traversed node
unsigned int mask = 0;
//current traverse depth
int currentTraverseDepth = 0;
//current inPonit when traversing the node
float4 inPoint = rayOri + result.x * rayDir ;
while( currentTraverseDepth >= 0 )
{
//traverse the current node
do
{
//the current node offset
int currentNodeOffset = currentNodeIndex * 4;
//get the current node information
header = kdTree[ currentNodeOffset ];
splitInfo = kdTree[currentNodeOffset + 1 ];
//check if it's a leaf node
if( splitInfo.x < 0 )
break;
//get the split axis
int splitAxis = (int) splitInfo.x;
//get the pointer of the inPoint
float sPos = 0.0f;
if( splitAxis == 0 )
sPos = inPoint.x;
else if( splitAxis == 1 )
sPos = inPoint.y;
else if( splitAxis == 2 )
sPos = inPoint.z;
//update the virtual stack and traverse the node
if( splitInfo.y > sPos )
currentNodeIndex = (int)header.y;
else
currentNodeIndex = (int)header.z;
//increase the current traverse depth
currentTraverseDepth++;
}while( true );
//get the offset and triangle number
int triOffset = offsetBuffer[currentNodeIndex];
int triNumber = (int)header.w;
//min value
float minFactor = 9999999.0f;
if( length > 0 )
minFactor = length;
//triangle index
int oriTriIndex = -1;
//the bounding box
minBB = kdTree[currentNodeIndex*4+2];
maxBB = kdTree[currentNodeIndex*4+3];
//intersect with the current triangles
for( int i = 0 ; i < triNumber ; i++ )
{
//get the triangles
int triIndex = indexMap[triOffset+i];
//get the vertex
float4 v1 = vertexBuffer[3*triIndex];
float4 v2 = vertexBuffer[3*triIndex+1];
float4 v3 = vertexBuffer[3*triIndex+2];
//get the intersected point
result = kernelIntersectTriangle( v1 , v2 , v3 , rayOri , rayDir );
//limit the factor
if( result.w > 0.0f && result.w < minFactor )
{
if( kernelPointInBoundingBox( result , minBB , maxBB ) )
{
minFactor = result.w;
oriTriIndex = triIndex;
if( length > 0 )
break;
}
}
}
if( oriTriIndex >= 0 )
{
result = rayOri + minFactor * rayDir;
result.w = (float)oriTriIndex;
return result;
}
//back track here
while( currentTraverseDepth >= 0 )
{
if( currentTraverseDepth == 0 )
return make_float4( 0 , 0 , 0 , -1.0f );
//get the current mask
if( mask & ( 0x00000001 << currentTraverseDepth ) )
{
//update the mask
mask &= ~(0x00000001 << currentTraverseDepth );
//decrease the current depth;
currentTraverseDepth--;
//get to the father node
currentNodeIndex = (int)kdTree[ 4 * currentNodeIndex ].x;
//continue to next level
continue;
}
//check the other node
int otherNode = currentNodeIndex + 1;
if( currentNodeIndex % 2 == 0 )
otherNode -= 2;
//get the bounding box of the other node
int otherNodeOffset = 4 * otherNode;
minBB = kdTree[ otherNodeOffset + 2 ];
maxBB = kdTree[ otherNodeOffset + 3 ];
//get the intersected result
float4 bi = kernelIntersectBoundingBox( rayOri , rayDir , minBB , maxBB , length );
if( bi.z > 0.5f )
{
//update the current traverse node
currentNodeIndex = otherNode;
//update the inPoint
inPoint = rayOri + bi.x * rayDir ;
//update the mask
mask |= 0x00000001 << currentTraverseDepth;
break;
}else
{
//update the mask
mask &= ~( 0x00000001 << currentTraverseDepth );
//decrease current depth
currentTraverseDepth--;
//get to the father node
currentNodeIndex = (int) kdTree[ 4 * currentNodeIndex ].x;
}
}
}
result.w = -1.0f;
return result;
}
//get the interseced point
__global__ void kernelGetIntersectedPoint( float4* rayOri ,
float4* rayDir ,
float4* kdTree ,
int* indexMap ,
int* offsetBuffer ,
float4* vertexBuffer ,
int rayNumber ,
float4* result )
{
//get the thread id
int tid = threadIdx.x + blockIdx.x * blockDim.x;
//limit the thread id
if( tid >= rayNumber )
return;
//get the triangle
result[tid] = kernelTraverseRay( kdTree , indexMap , offsetBuffer , vertexBuffer , rayOri[tid] , rayDir[tid] , -1.0f );
}
//do pixel shader here
__global__ void kernelPixelShader( float4* intersected ,
float4* vertexBuffer ,
float4* normalBuffer ,
float2* texCoordinateBuffer ,
float4* kdTree ,
int* indexMap ,
int* offsetIndexBuffer,
float4* lightBuffer ,
int* attributeBuffer ,
float4* materialBuffer ,
int* textureOffset ,
float4* customTexture ,
int pixelNum ,
float4* rayDir ,
int* offsetBuffer ,
float4* destNormalBuffer ,
float4* imageBuffer )
{
//get the thread id
int tid = threadIdx.x + blockIdx.x * blockDim.x;
//limit the thread id
if( tid >= pixelNum )
return;
//get the triangle index
int triIndex = (int)intersected[tid].w;
int triOffset = 3 * triIndex;
float4 color = make_float4( 0.0f , 0.0f , 0.0f , 0.0f );
//load the density of the pixel
if( triIndex < 0 )
return;
//get the material index
int matIndex = attributeBuffer[triIndex];
//the material buffer
float4 ambient = materialBuffer[ 4 * matIndex ];
float4 diffuse = materialBuffer[ 4 * matIndex + 1 ];
float4 specular = materialBuffer[ 4 * matIndex + 2 ];
float4 matprop = materialBuffer[ 4 * matIndex + 3 ];
//load the vertex
float4 v1 = vertexBuffer[ triOffset ];
float4 v2 = vertexBuffer[ triOffset + 1 ];
float4 v3 = vertexBuffer[ triOffset + 2 ];
//get the interploted
float4 interploted = kernelInterploted( v1 , v2 , v3 , intersected[tid] );
//get the normal
float4 n1 = normalBuffer[ triOffset ];
float4 n2 = normalBuffer[ triOffset + 1 ];
float4 n3 = normalBuffer[ triOffset + 2 ];
float4 normal = n1 * interploted.x + n2 * interploted.y + n3 * interploted.z;
d_normalize( &normal );
//update the normal buffer
destNormalBuffer[tid] = normal;
destNormalBuffer[tid].w = matIndex;
//the density for the pixel
float density = rayDir[tid].w;
if( matprop.x > -0.5f )
{
//load the texture coordinate
float2 t1 = texCoordinateBuffer[ triOffset ];
float2 t2 = texCoordinateBuffer[ triOffset + 1 ];
float2 t3 = texCoordinateBuffer[ triOffset + 2 ];
float2 texCoord = interploted.x * t1 + interploted.y * t2 + interploted.z * t3;
texCoord = texCoord - floor( texCoord );
if( texCoord.x < 0.0f ) texCoord.x += 1.0f;
if( texCoord.y < 0.0f ) texCoord.y += 1.0f;
//load the texture
float4* imgData = customTexture + textureOffset[(int)matprop.x];
int x = imgData[0].y * texCoord.x ;
int y = imgData[0].z * texCoord.y ;
int texOffset = y * imgData[0].y + x + 1;
diffuse = diffuse * (*(imgData + texOffset)) ;
}
//initialize the image buffer
color = ambient;
//shade the pixels
for( int i = 0 ; i < 2 ; i++ )
{
if( lightBuffer[i].w < 0.01f )
continue;
//the light direction
float4 lightDir = intersected[tid] - lightBuffer[i];
//check if the point is in the shadow
float shadowLen = 0.98f * d_length(lightDir);
d_normalize( &lightDir );
//the dot product
float dotProduct = d_dot( lightDir , normal );
if( dotProduct > 0.0f )
continue;
{
float4 shadowFactor = kernelTraverseRay( kdTree , indexMap , offsetIndexBuffer , vertexBuffer , lightBuffer[i] , lightDir , shadowLen );
if( shadowFactor.w >= 0.0f )
continue;
}
//the light density
float lightDensity = d_clamp( -1.0f * dotProduct ) * lightBuffer[i].w;
//load the density of current pixel
color += diffuse * lightDensity ;
//add specular if possible
if( specular.w > 0 )
{
//reflect direction
float4 reflectDir = d_reflect( lightDir , normal );
d_normalize( &reflectDir );
//get the dot product
float d = d_clamp(-d_dot( reflectDir , rayDir[tid] ));
if( d > 0 )
color += pow( d , specular.w ) * specular;
}
}
int offset = offsetBuffer[tid];
imageBuffer[offset] = d_saturate( imageBuffer[offset] + d_saturate( color * density ) );
}
//generate next level rays
__global__ void kernelGenerateNextLevelRays( float4* materialInfo ,
float4* intersected ,
float4* backNormalBuffer ,
float4* rayOri ,
float4* rayDir ,
int rayNumber ,
float4* destRayOri ,
float4* destRayDir ,
int* markedBuffer )
{
//get the thread id
int tid = threadIdx.x + blockIdx.x * blockDim.x;
//limit the thread id
if( tid >= rayNumber )
return;
//set marked buffer zero
markedBuffer[tid] = 0;
//load the intersected point
float4 intersectedPoint = intersected[tid];
//get the intersected triangle index
int triIndex = (int)intersectedPoint.w;
if( triIndex < 0 )
return;
//load the normal
float4 normal = backNormalBuffer[tid];
//get the material index
int matIndex = (int)normal.w;
//get the material
float4 matInfo = materialInfo[4*matIndex+3];
//load the ray direction
float4 ori = rayOri[tid];
float4 dir = rayDir[tid];
//if there is reflection , mark result as true
if( matInfo.y > 0 )
{
float4 reflectDir = d_reflect( dir , normal );
d_normalize( &reflectDir );
reflectDir.w = dir.w * matInfo.y;
destRayDir[tid] = reflectDir;
destRayOri[tid] = intersectedPoint + reflectDir * 0.1f;
destRayOri[tid].w = ori.w;
markedBuffer[tid] = 1;
}else if( matInfo.z > 0 )
{
float4 refractDir = d_refract( dir , normal , 1.0f / matInfo.w );
d_normalize( &refractDir );
refractDir.w = dir.w * matInfo.z;
destRayDir[tid] = refractDir;
destRayOri[tid] = intersectedPoint + refractDir * 0.02f;
destRayOri[tid].w = ori.w;
markedBuffer[tid] = 1;
}
}
//copy new rays
__global__ void kernelCopyNewRays( float4* srcRayOri ,
float4* srcRayDir ,
int* scanResult ,
int rayNumber ,
float4* destRayOri ,
float4* destRayDir ,
int* offsets )
{
//get the thread id
int tid = threadIdx.x + blockIdx.x * blockDim.x;
//limit the thread id
if( tid >= rayNumber )
return;
//load the offset
int offset = scanResult[tid];
if( offset != scanResult[tid+1] )
{
//set the result
destRayOri[offset] = srcRayOri[tid];
destRayDir[offset] = srcRayDir[tid];
offsets[offset] = (int)srcRayOri[tid].w;
}
}
//Do scan on GPU
__global__ void kernelScan( int* data , int number , int oBlockRes , int* blockRes )
{
//the shared memory
__shared__ int sharedMem[512];
//get the thread id
int ltid = threadIdx.x;
int gtid = ltid + blockDim.x * blockIdx.x;
//the block sum
int blocksum = 0;
//zero the rest of the memory
if( 2 * gtid >= number )
{
data[ 2 * gtid ] = 0;
data[ 2 * gtid + 1 ] = 0;
}else if( 2 * gtid == number - 1 )
data[ 2 * gtid + 1 ] = 0;
//Load the data into the shared memory
sharedMem[2*ltid] = data[2*gtid];
sharedMem[2*ltid+1] = data[2*gtid+1];
//the offset
int offset = 1;
for( int d = 256 ; d > 1 ; d >>= 1 )
{
//sync the threads in a group
__syncthreads();
if( ltid < d )
{
int ai = offset * ( 2 * ltid + 1 ) - 1;
int bi = ai + offset;
sharedMem[bi] += sharedMem[ai];
}
offset *= 2;
}
//the block sum
blocksum = sharedMem[511] + sharedMem[255];
//clear the last element
if( ltid == 0 )
{
sharedMem[511] = sharedMem[255];
sharedMem[255] = 0;
}
for( int d = 2 ; d < 512 ; d *= 2 )
{
__syncthreads();
offset >>= 1;
if( ltid < d )
{
int ai = offset * ( 2 * ltid + 1 ) - 1 ;
int bi = ai + offset ;
int t = sharedMem[ai];
sharedMem[ai] = sharedMem[bi];
sharedMem[bi] += t;
}
}
__syncthreads();
data[ 2 * gtid ] = sharedMem[ 2 * ltid ];
data[ 2 * gtid + 1 ] = sharedMem[ 2 * ltid + 1 ];
//Output Block Result
if( oBlockRes > 0 )
{
if( ltid == 0 )
{
//copy the result
blockRes[blockIdx.x] = blocksum;
}
}
}
//Add the block result to the segmented scan result
__global__ void kernelUniformAdd( int* data , int* blockResult )
{
//get the thread id
int ltid = threadIdx.x;
int gtid = ltid + blockDim.x * blockIdx.x;
//add the result
data[gtid] += blockResult[gtid/512];
}
//clear the noise of the image
__global__ void kernelClearNoise( float4* imgData ,
int width ,
int height ,
float4* targetData )
{
//get the thread id
int tid = threadIdx.x + blockIdx.x * blockDim.x;
//limit the thread id
if( tid >= width * height )
return;
//threshold
float threshold = 0.4f;
//the difference
int difference = 0;
//current index
int currentIndex = tid;
int leftIndex = tid - 1;
int rightIndex = tid + 1;
int upIndex = tid - width ;
int downIndex = tid + width ;
//the coordinate
int i = tid % width;
int j = tid / width;
//current color
float4 color = imgData[currentIndex];
float4 sum = make_float4( 0 , 0 , 0 , 0 );
if( i > 0 )
{
if( d_length( color - imgData[leftIndex] ) > threshold )
difference++;
sum += imgData[leftIndex];
}
if( i < width - 1 )
{
if( d_length( color - imgData[rightIndex] ) > threshold )
difference++;
sum += imgData[rightIndex];
}
if( j > 0 )
{
if( d_length( color - imgData[upIndex] ) > threshold )
difference++;
sum += imgData[upIndex];
}
if( j < height - 1 )
{
if( d_length( color - imgData[downIndex] ) > threshold )
difference++;
sum += imgData[downIndex];
}
if( difference >= 2 )
color = sum * 0.25f;
targetData[tid] = color;
}
////////////////////////////////////////////////////////////////////////////////////////////////////
//initialize buffer
extern "C" void cudaInitBuffer( float4* buffer ,
int* markedBuffer ,
int pixelNum )
{
//the block number
int threadNum = 256;
int blockNum = ( pixelNum + threadNum - 1 ) / threadNum;
//call the kenrel
kernelInitBuffer<<<blockNum,threadNum>>>( buffer , markedBuffer , pixelNum );
}
//generate primary ray intersected result
extern "C" void cudaGenerateIntersectedPoint( float4* rayOri ,
float4* rayDir ,
float4* vertexBuffer ,
int rayNum ,
int* index ,
float4* result )
{
//the block number
int threadNum = 256;
int blockNum = ( rayNum + threadNum - 1 ) / threadNum;
//call the kernel
kernelGenerateIntersectedPoint<<<blockNum , threadNum>>>( rayOri , rayDir , vertexBuffer , rayNum , index , result );
}
//Generate primary rays
extern "C" void cudaGeneratePrimaryRays( float4 viewInfo ,
float* invViewMatrix ,
float4* rayOri ,
float4* rayDir )
{
//get the number of data
int rayNum = (int)( viewInfo.x * viewInfo.y );
//the block number
int threadNum = 256;
int blockNum = ( rayNum + threadNum - 1 ) / threadNum;
//call the kernel
kernelGeneratePrimaryRays<<<blockNum , threadNum>>>( viewInfo , invViewMatrix , rayOri , rayDir );
}
//get intersected point
extern "C" void cudaGetIntersectedPoint( float4* rayOri ,
float4* rayDir ,
float4* kdTree ,
int* indexMap ,
int* offsetBuffer ,
float4* vertexBuffer ,
int rayNumber ,
float4* result )
{
//the block and thread number
int threadNum = 256;
int blockNum = ( rayNumber + threadNum - 1 ) / threadNum ;
//call the kernel
kernelGetIntersectedPoint<<<blockNum , threadNum>>>( rayOri , rayDir , kdTree , indexMap , offsetBuffer , vertexBuffer , rayNumber , result );
}
//do pixel shader
extern "C" void cudaPixelShader( float4* interseced ,
float4* vertexBuffer ,
float4* normalBuffer ,
float2* texCoordinateBuffer ,
float4* kdTree ,
int* indexMap ,
int* offsetIndexBuffer ,
float4* lightBuffer ,
int* attributeBuffer ,
float4* materialBuffer ,
int* textureOffset ,
float4* customTexture ,
int pixelNum ,
float4* rayDir ,
int* offsetBuffer ,
float4* destNormalBuffer ,
float4* imageBuffer )
{
//the block and thread number
int threadNum = 256;
int blockNum = ( pixelNum + threadNum - 1 ) / threadNum ;
//call the kernel
kernelPixelShader<<<blockNum , threadNum>>>( interseced , vertexBuffer , normalBuffer , texCoordinateBuffer ,
kdTree , indexMap , offsetIndexBuffer , lightBuffer , attributeBuffer , materialBuffer ,
textureOffset , customTexture , pixelNum , rayDir , offsetBuffer , destNormalBuffer , imageBuffer );
}
//generate next level rays
extern "C" void cudaGenerateNextLevelRays( float4* materialInfo ,
float4* intersected ,
float4* backNormalBuffer ,
float4* rayOri ,
float4* rayDir ,
int rayNumber ,
float4* destRayOri ,
float4* destRayDir ,
int* markedBuffer )
{
//the block and thread number
int threadNum = 256;
int blockNum = ( rayNumber + threadNum - 1 ) / threadNum ;
//call the kernel
kernelGenerateNextLevelRays<<<blockNum , threadNum>>>( materialInfo , intersected , backNormalBuffer , rayOri , rayDir ,
rayNumber , destRayOri , destRayDir , markedBuffer );
}
//do scan on gpu
extern "C" void cudaScan( int* data , int num , int level )
{
/* //allocate the number of data
int* cpuData = new int[num];
//pass the data from gpu to cpu
cudaMemcpy( cpuData , data , sizeof( int ) * ( num - 1 ) , cudaMemcpyDeviceToHost );
int last = 0;
for( int i = 0 ; i < num ; i++ )
{
int oldLast = last;
last += cpuData[i];
cpuData[i] = oldLast;
}
//pass the data back from cpu to gpu
cudaMemcpy( data , cpuData , sizeof( int ) * num , cudaMemcpyHostToDevice );
//delete the data
delete[] cpuData;*/
//the dimension of the kernel
dim3 threads( 256 );
dim3 blocks( ( num + 511 ) / 512 );
//call the kernel
kernelScan<<<blocks , threads>>>( data , num , 1 , g_ScanSum[level] );
//scan the block Result
if( num <= 262144 )
kernelScan<<<1 , threads>>>( g_ScanSum[level] , blocks.x , -1 , data );
else
cudaScan( g_ScanSum[level] , blocks.x , level + 1 );
//add the offset
threads.x = 512;
kernelUniformAdd<<< blocks , threads >>> ( data , g_ScanSum[level] );
}
//copy new rays
extern "C" void cudaCopyNewRays( float4* srcRayOri ,
float4* srcRayDir ,
int* scanResult ,
int rayNumber ,
float4* destRayOri ,
float4* destRayDir ,
int* offsets )
{
//the block and thread number
int threadNum = 256;
int blockNum = ( rayNumber + threadNum - 1 ) / threadNum ;
//call the kernel
kernelCopyNewRays<<<blockNum , threadNum>>>( srcRayOri , srcRayDir , scanResult , rayNumber , destRayOri , destRayDir , offsets );
}
//clear the noise of the image
extern "C" void cudaClearNoise( float4* imgData ,
int width ,
int height ,
float4* targetData )
{
//the block and thread number
int threadNum = 256;
int blockNum = ( width * height + 255 ) / 256;
//call the kernel
kernelClearNoise<<<blockNum , threadNum>>>( imgData , width , height , targetData );
} |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void split_kernel(float *d_output, float *d_input, float *d_predicates, float *d_scanned, int length)
{
int idx = blockDim.x * blockIdx.x + threadIdx.x;
if (idx >= length) return;
if (d_predicates[idx] != 0.f)
{
// address
int address = d_scanned[idx] - 1;
// split
d_output[idx] = d_input[address];
}
} | code for sm_80
Function : _Z12split_kernelPfS_S_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x180], PT ; /* 0x0000600000007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ IMAD.MOV.U32 R9, RZ, RZ, 0x4 ; /* 0x00000004ff097424 */
/* 0x000fe200078e00ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0080*/ IMAD.WIDE R2, R0, R9, c[0x0][0x170] ; /* 0x00005c0000027625 */
/* 0x000fcc00078e0209 */
/*0090*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea4000c1e1900 */
/*00a0*/ FSETP.NEU.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720b */
/* 0x004fda0003f0d000 */
/*00b0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*00c0*/ IMAD.SHL.U32 R6, R0, 0x4, RZ ; /* 0x0000000400067824 */
/* 0x000fe200078e00ff */
/*00d0*/ SHF.R.S32.HI R3, RZ, 0x1f, R0 ; /* 0x0000001fff037819 */
/* 0x000fc80000011400 */
/*00e0*/ SHF.L.U64.HI R7, R0, 0x2, R3 ; /* 0x0000000200077819 */
/* 0x000fe40000010203 */
/*00f0*/ IADD3 R4, P0, R6, c[0x0][0x178], RZ ; /* 0x00005e0006047a10 */
/* 0x000fc80007f1e0ff */
/*0100*/ IADD3.X R5, R7, c[0x0][0x17c], RZ, P0, !PT ; /* 0x00005f0007057a10 */
/* 0x000fca00007fe4ff */
/*0110*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea4000c1e1900 */
/*0120*/ FADD R0, R4, -1 ; /* 0xbf80000004007421 */
/* 0x004fcc0000000000 */
/*0130*/ F2I.TRUNC.NTZ R0, R0 ; /* 0x0000000000007305 */
/* 0x000e24000020f100 */
/*0140*/ IMAD.WIDE R2, R0, R9, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x001fcc00078e0209 */
/*0150*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*0160*/ IADD3 R6, P0, R6, c[0x0][0x160], RZ ; /* 0x0000580006067a10 */
/* 0x000fc80007f1e0ff */
/*0170*/ IADD3.X R7, R7, c[0x0][0x164], RZ, P0, !PT ; /* 0x0000590007077a10 */
/* 0x000fca00007fe4ff */
/*0180*/ STG.E [R6.64], R3 ; /* 0x0000000306007986 */
/* 0x004fe2000c101904 */
/*0190*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01a0*/ BRA 0x1a0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void split_kernel(float *d_output, float *d_input, float *d_predicates, float *d_scanned, int length)
{
int idx = blockDim.x * blockIdx.x + threadIdx.x;
if (idx >= length) return;
if (d_predicates[idx] != 0.f)
{
// address
int address = d_scanned[idx] - 1;
// split
d_output[idx] = d_input[address];
}
} | .file "tmpxft_0013c02a_00000000-6_split_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z39__device_stub__Z12split_kernelPfS_S_S_iPfS_S_S_i
.type _Z39__device_stub__Z12split_kernelPfS_S_S_iPfS_S_S_i, @function
_Z39__device_stub__Z12split_kernelPfS_S_S_iPfS_S_S_i:
.LFB2051:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movl %r8d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 12(%rsp), %rax
movq %rax, 144(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 184
pushq 56(%rsp)
.cfi_def_cfa_offset 192
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z12split_kernelPfS_S_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z39__device_stub__Z12split_kernelPfS_S_S_iPfS_S_S_i, .-_Z39__device_stub__Z12split_kernelPfS_S_S_iPfS_S_S_i
.globl _Z12split_kernelPfS_S_S_i
.type _Z12split_kernelPfS_S_S_i, @function
_Z12split_kernelPfS_S_S_i:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z39__device_stub__Z12split_kernelPfS_S_S_iPfS_S_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z12split_kernelPfS_S_S_i, .-_Z12split_kernelPfS_S_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z12split_kernelPfS_S_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z12split_kernelPfS_S_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void split_kernel(float *d_output, float *d_input, float *d_predicates, float *d_scanned, int length)
{
int idx = blockDim.x * blockIdx.x + threadIdx.x;
if (idx >= length) return;
if (d_predicates[idx] != 0.f)
{
// address
int address = d_scanned[idx] - 1;
// split
d_output[idx] = d_input[address];
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void split_kernel(float *d_output, float *d_input, float *d_predicates, float *d_scanned, int length)
{
int idx = blockDim.x * blockIdx.x + threadIdx.x;
if (idx >= length) return;
if (d_predicates[idx] != 0.f)
{
// address
int address = d_scanned[idx] - 1;
// split
d_output[idx] = d_input[address];
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void split_kernel(float *d_output, float *d_input, float *d_predicates, float *d_scanned, int length)
{
int idx = blockDim.x * blockIdx.x + threadIdx.x;
if (idx >= length) return;
if (d_predicates[idx] != 0.f)
{
// address
int address = d_scanned[idx] - 1;
// split
d_output[idx] = d_input[address];
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z12split_kernelPfS_S_S_i
.globl _Z12split_kernelPfS_S_S_i
.p2align 8
.type _Z12split_kernelPfS_S_S_i,@function
_Z12split_kernelPfS_S_S_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x34
s_load_b32 s3, s[0:1], 0x20
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_3
s_load_b64 s[2:3], s[0:1], 0x10
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v1, vcc_lo
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(0)
v_cmp_neq_f32_e32 vcc_lo, 0, v2
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_3
s_load_b64 s[2:3], s[0:1], 0x18
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v1, vcc_lo
s_load_b128 s[0:3], s[0:1], 0x0
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, -1.0, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_i32_f32_e32 v2, v2
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s2, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(0)
global_store_b32 v[0:1], v2, off
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12split_kernelPfS_S_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z12split_kernelPfS_S_S_i, .Lfunc_end0-_Z12split_kernelPfS_S_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12split_kernelPfS_S_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z12split_kernelPfS_S_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void split_kernel(float *d_output, float *d_input, float *d_predicates, float *d_scanned, int length)
{
int idx = blockDim.x * blockIdx.x + threadIdx.x;
if (idx >= length) return;
if (d_predicates[idx] != 0.f)
{
// address
int address = d_scanned[idx] - 1;
// split
d_output[idx] = d_input[address];
}
} | .text
.file "split_kernel.hip"
.globl _Z27__device_stub__split_kernelPfS_S_S_i # -- Begin function _Z27__device_stub__split_kernelPfS_S_S_i
.p2align 4, 0x90
.type _Z27__device_stub__split_kernelPfS_S_S_i,@function
_Z27__device_stub__split_kernelPfS_S_S_i: # @_Z27__device_stub__split_kernelPfS_S_S_i
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movl %r8d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 12(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z12split_kernelPfS_S_S_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end0:
.size _Z27__device_stub__split_kernelPfS_S_S_i, .Lfunc_end0-_Z27__device_stub__split_kernelPfS_S_S_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12split_kernelPfS_S_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z12split_kernelPfS_S_S_i,@object # @_Z12split_kernelPfS_S_S_i
.section .rodata,"a",@progbits
.globl _Z12split_kernelPfS_S_S_i
.p2align 3, 0x0
_Z12split_kernelPfS_S_S_i:
.quad _Z27__device_stub__split_kernelPfS_S_S_i
.size _Z12split_kernelPfS_S_S_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z12split_kernelPfS_S_S_i"
.size .L__unnamed_1, 26
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__split_kernelPfS_S_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12split_kernelPfS_S_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z12split_kernelPfS_S_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x180], PT ; /* 0x0000600000007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ IMAD.MOV.U32 R9, RZ, RZ, 0x4 ; /* 0x00000004ff097424 */
/* 0x000fe200078e00ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0080*/ IMAD.WIDE R2, R0, R9, c[0x0][0x170] ; /* 0x00005c0000027625 */
/* 0x000fcc00078e0209 */
/*0090*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea4000c1e1900 */
/*00a0*/ FSETP.NEU.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720b */
/* 0x004fda0003f0d000 */
/*00b0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*00c0*/ IMAD.SHL.U32 R6, R0, 0x4, RZ ; /* 0x0000000400067824 */
/* 0x000fe200078e00ff */
/*00d0*/ SHF.R.S32.HI R3, RZ, 0x1f, R0 ; /* 0x0000001fff037819 */
/* 0x000fc80000011400 */
/*00e0*/ SHF.L.U64.HI R7, R0, 0x2, R3 ; /* 0x0000000200077819 */
/* 0x000fe40000010203 */
/*00f0*/ IADD3 R4, P0, R6, c[0x0][0x178], RZ ; /* 0x00005e0006047a10 */
/* 0x000fc80007f1e0ff */
/*0100*/ IADD3.X R5, R7, c[0x0][0x17c], RZ, P0, !PT ; /* 0x00005f0007057a10 */
/* 0x000fca00007fe4ff */
/*0110*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea4000c1e1900 */
/*0120*/ FADD R0, R4, -1 ; /* 0xbf80000004007421 */
/* 0x004fcc0000000000 */
/*0130*/ F2I.TRUNC.NTZ R0, R0 ; /* 0x0000000000007305 */
/* 0x000e24000020f100 */
/*0140*/ IMAD.WIDE R2, R0, R9, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x001fcc00078e0209 */
/*0150*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*0160*/ IADD3 R6, P0, R6, c[0x0][0x160], RZ ; /* 0x0000580006067a10 */
/* 0x000fc80007f1e0ff */
/*0170*/ IADD3.X R7, R7, c[0x0][0x164], RZ, P0, !PT ; /* 0x0000590007077a10 */
/* 0x000fca00007fe4ff */
/*0180*/ STG.E [R6.64], R3 ; /* 0x0000000306007986 */
/* 0x004fe2000c101904 */
/*0190*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01a0*/ BRA 0x1a0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z12split_kernelPfS_S_S_i
.globl _Z12split_kernelPfS_S_S_i
.p2align 8
.type _Z12split_kernelPfS_S_S_i,@function
_Z12split_kernelPfS_S_S_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x34
s_load_b32 s3, s[0:1], 0x20
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_3
s_load_b64 s[2:3], s[0:1], 0x10
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v1, vcc_lo
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(0)
v_cmp_neq_f32_e32 vcc_lo, 0, v2
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_3
s_load_b64 s[2:3], s[0:1], 0x18
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v1, vcc_lo
s_load_b128 s[0:3], s[0:1], 0x0
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, -1.0, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_i32_f32_e32 v2, v2
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s2, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(0)
global_store_b32 v[0:1], v2, off
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12split_kernelPfS_S_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z12split_kernelPfS_S_S_i, .Lfunc_end0-_Z12split_kernelPfS_S_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12split_kernelPfS_S_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z12split_kernelPfS_S_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0013c02a_00000000-6_split_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z39__device_stub__Z12split_kernelPfS_S_S_iPfS_S_S_i
.type _Z39__device_stub__Z12split_kernelPfS_S_S_iPfS_S_S_i, @function
_Z39__device_stub__Z12split_kernelPfS_S_S_iPfS_S_S_i:
.LFB2051:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movl %r8d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 12(%rsp), %rax
movq %rax, 144(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 184
pushq 56(%rsp)
.cfi_def_cfa_offset 192
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z12split_kernelPfS_S_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z39__device_stub__Z12split_kernelPfS_S_S_iPfS_S_S_i, .-_Z39__device_stub__Z12split_kernelPfS_S_S_iPfS_S_S_i
.globl _Z12split_kernelPfS_S_S_i
.type _Z12split_kernelPfS_S_S_i, @function
_Z12split_kernelPfS_S_S_i:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z39__device_stub__Z12split_kernelPfS_S_S_iPfS_S_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z12split_kernelPfS_S_S_i, .-_Z12split_kernelPfS_S_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z12split_kernelPfS_S_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z12split_kernelPfS_S_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "split_kernel.hip"
.globl _Z27__device_stub__split_kernelPfS_S_S_i # -- Begin function _Z27__device_stub__split_kernelPfS_S_S_i
.p2align 4, 0x90
.type _Z27__device_stub__split_kernelPfS_S_S_i,@function
_Z27__device_stub__split_kernelPfS_S_S_i: # @_Z27__device_stub__split_kernelPfS_S_S_i
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movl %r8d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 12(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z12split_kernelPfS_S_S_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end0:
.size _Z27__device_stub__split_kernelPfS_S_S_i, .Lfunc_end0-_Z27__device_stub__split_kernelPfS_S_S_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12split_kernelPfS_S_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z12split_kernelPfS_S_S_i,@object # @_Z12split_kernelPfS_S_S_i
.section .rodata,"a",@progbits
.globl _Z12split_kernelPfS_S_S_i
.p2align 3, 0x0
_Z12split_kernelPfS_S_S_i:
.quad _Z27__device_stub__split_kernelPfS_S_S_i
.size _Z12split_kernelPfS_S_S_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z12split_kernelPfS_S_S_i"
.size .L__unnamed_1, 26
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__split_kernelPfS_S_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12split_kernelPfS_S_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void kBiggerThan(float* gMat1, float* gMat2, float* gMatTarget, unsigned int numElements) {
const unsigned int idx = blockIdx.x * blockDim.x + threadIdx.x;
if (idx < numElements)
gMatTarget[idx] = gMat1[idx] > gMat2[idx];
} | code for sm_80
Function : _Z11kBiggerThanPfS_S_j
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R6, R6, c[0x0][0x0], R3 ; /* 0x0000000006067a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.U32.AND P0, PT, R6, c[0x0][0x178], PT ; /* 0x00005e0006007a0c */
/* 0x000fda0003f06070 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE.U32 R4, R6, R7, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x000fc800078e0007 */
/*0090*/ IMAD.WIDE.U32 R2, R6.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x0c0fe400078e0007 */
/*00a0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ IMAD.WIDE.U32 R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fe200078e0007 */
/*00d0*/ FSET.BF.GT.AND R9, R3, R4, PT ; /* 0x000000040309720a */
/* 0x004fca0003804000 */
/*00e0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void kBiggerThan(float* gMat1, float* gMat2, float* gMatTarget, unsigned int numElements) {
const unsigned int idx = blockIdx.x * blockDim.x + threadIdx.x;
if (idx < numElements)
gMatTarget[idx] = gMat1[idx] > gMat2[idx];
} | .file "tmpxft_001423a2_00000000-6_kBiggerThan.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z36__device_stub__Z11kBiggerThanPfS_S_jPfS_S_j
.type _Z36__device_stub__Z11kBiggerThanPfS_S_jPfS_S_j, @function
_Z36__device_stub__Z11kBiggerThanPfS_S_jPfS_S_j:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z11kBiggerThanPfS_S_j(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z36__device_stub__Z11kBiggerThanPfS_S_jPfS_S_j, .-_Z36__device_stub__Z11kBiggerThanPfS_S_jPfS_S_j
.globl _Z11kBiggerThanPfS_S_j
.type _Z11kBiggerThanPfS_S_j, @function
_Z11kBiggerThanPfS_S_j:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z36__device_stub__Z11kBiggerThanPfS_S_jPfS_S_j
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z11kBiggerThanPfS_S_j, .-_Z11kBiggerThanPfS_S_j
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z11kBiggerThanPfS_S_j"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z11kBiggerThanPfS_S_j(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void kBiggerThan(float* gMat1, float* gMat2, float* gMatTarget, unsigned int numElements) {
const unsigned int idx = blockIdx.x * blockDim.x + threadIdx.x;
if (idx < numElements)
gMatTarget[idx] = gMat1[idx] > gMat2[idx];
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void kBiggerThan(float* gMat1, float* gMat2, float* gMatTarget, unsigned int numElements) {
const unsigned int idx = blockIdx.x * blockDim.x + threadIdx.x;
if (idx < numElements)
gMatTarget[idx] = gMat1[idx] > gMat2[idx];
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void kBiggerThan(float* gMat1, float* gMat2, float* gMatTarget, unsigned int numElements) {
const unsigned int idx = blockIdx.x * blockDim.x + threadIdx.x;
if (idx < numElements)
gMatTarget[idx] = gMat1[idx] > gMat2[idx];
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11kBiggerThanPfS_S_j
.globl _Z11kBiggerThanPfS_S_j
.p2align 8
.type _Z11kBiggerThanPfS_S_j,@function
_Z11kBiggerThanPfS_S_j:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_u32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_mov_b32_e32 v2, 0
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
s_waitcnt vmcnt(0)
v_cmp_gt_f32_e32 vcc_lo, v2, v3
v_cndmask_b32_e64 v2, 0, 1.0, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11kBiggerThanPfS_S_j
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z11kBiggerThanPfS_S_j, .Lfunc_end0-_Z11kBiggerThanPfS_S_j
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11kBiggerThanPfS_S_j
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z11kBiggerThanPfS_S_j.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void kBiggerThan(float* gMat1, float* gMat2, float* gMatTarget, unsigned int numElements) {
const unsigned int idx = blockIdx.x * blockDim.x + threadIdx.x;
if (idx < numElements)
gMatTarget[idx] = gMat1[idx] > gMat2[idx];
} | .text
.file "kBiggerThan.hip"
.globl _Z26__device_stub__kBiggerThanPfS_S_j # -- Begin function _Z26__device_stub__kBiggerThanPfS_S_j
.p2align 4, 0x90
.type _Z26__device_stub__kBiggerThanPfS_S_j,@function
_Z26__device_stub__kBiggerThanPfS_S_j: # @_Z26__device_stub__kBiggerThanPfS_S_j
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z11kBiggerThanPfS_S_j, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z26__device_stub__kBiggerThanPfS_S_j, .Lfunc_end0-_Z26__device_stub__kBiggerThanPfS_S_j
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11kBiggerThanPfS_S_j, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z11kBiggerThanPfS_S_j,@object # @_Z11kBiggerThanPfS_S_j
.section .rodata,"a",@progbits
.globl _Z11kBiggerThanPfS_S_j
.p2align 3, 0x0
_Z11kBiggerThanPfS_S_j:
.quad _Z26__device_stub__kBiggerThanPfS_S_j
.size _Z11kBiggerThanPfS_S_j, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z11kBiggerThanPfS_S_j"
.size .L__unnamed_1, 23
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__kBiggerThanPfS_S_j
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11kBiggerThanPfS_S_j
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z11kBiggerThanPfS_S_j
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R6, R6, c[0x0][0x0], R3 ; /* 0x0000000006067a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.U32.AND P0, PT, R6, c[0x0][0x178], PT ; /* 0x00005e0006007a0c */
/* 0x000fda0003f06070 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE.U32 R4, R6, R7, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x000fc800078e0007 */
/*0090*/ IMAD.WIDE.U32 R2, R6.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x0c0fe400078e0007 */
/*00a0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ IMAD.WIDE.U32 R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fe200078e0007 */
/*00d0*/ FSET.BF.GT.AND R9, R3, R4, PT ; /* 0x000000040309720a */
/* 0x004fca0003804000 */
/*00e0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11kBiggerThanPfS_S_j
.globl _Z11kBiggerThanPfS_S_j
.p2align 8
.type _Z11kBiggerThanPfS_S_j,@function
_Z11kBiggerThanPfS_S_j:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_u32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_mov_b32_e32 v2, 0
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
s_waitcnt vmcnt(0)
v_cmp_gt_f32_e32 vcc_lo, v2, v3
v_cndmask_b32_e64 v2, 0, 1.0, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11kBiggerThanPfS_S_j
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z11kBiggerThanPfS_S_j, .Lfunc_end0-_Z11kBiggerThanPfS_S_j
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11kBiggerThanPfS_S_j
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z11kBiggerThanPfS_S_j.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001423a2_00000000-6_kBiggerThan.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z36__device_stub__Z11kBiggerThanPfS_S_jPfS_S_j
.type _Z36__device_stub__Z11kBiggerThanPfS_S_jPfS_S_j, @function
_Z36__device_stub__Z11kBiggerThanPfS_S_jPfS_S_j:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z11kBiggerThanPfS_S_j(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z36__device_stub__Z11kBiggerThanPfS_S_jPfS_S_j, .-_Z36__device_stub__Z11kBiggerThanPfS_S_jPfS_S_j
.globl _Z11kBiggerThanPfS_S_j
.type _Z11kBiggerThanPfS_S_j, @function
_Z11kBiggerThanPfS_S_j:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z36__device_stub__Z11kBiggerThanPfS_S_jPfS_S_j
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z11kBiggerThanPfS_S_j, .-_Z11kBiggerThanPfS_S_j
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z11kBiggerThanPfS_S_j"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z11kBiggerThanPfS_S_j(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "kBiggerThan.hip"
.globl _Z26__device_stub__kBiggerThanPfS_S_j # -- Begin function _Z26__device_stub__kBiggerThanPfS_S_j
.p2align 4, 0x90
.type _Z26__device_stub__kBiggerThanPfS_S_j,@function
_Z26__device_stub__kBiggerThanPfS_S_j: # @_Z26__device_stub__kBiggerThanPfS_S_j
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z11kBiggerThanPfS_S_j, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z26__device_stub__kBiggerThanPfS_S_j, .Lfunc_end0-_Z26__device_stub__kBiggerThanPfS_S_j
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11kBiggerThanPfS_S_j, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z11kBiggerThanPfS_S_j,@object # @_Z11kBiggerThanPfS_S_j
.section .rodata,"a",@progbits
.globl _Z11kBiggerThanPfS_S_j
.p2align 3, 0x0
_Z11kBiggerThanPfS_S_j:
.quad _Z26__device_stub__kBiggerThanPfS_S_j
.size _Z11kBiggerThanPfS_S_j, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z11kBiggerThanPfS_S_j"
.size .L__unnamed_1, 23
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__kBiggerThanPfS_S_j
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11kBiggerThanPfS_S_j
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #define CUDA_BLOCK_X 128
#define CUDA_BLOCK_Y 1
#define CUDA_BLOCK_Z 1
__global__ void _auto_kernel_0(int a[100][2])
{
int thread_x_id;thread_x_id = blockIdx.x * blockDim.x + threadIdx.x;
int thread_y_id;thread_y_id = blockIdx.y * blockDim.y + threadIdx.y;
if (thread_x_id && thread_y_id)
if (thread_x_id <= 100 && thread_y_id <= 2) {
a[2 * thread_x_id + -2][2 * thread_y_id + -2] = a[2 * thread_x_id + -1][2 * thread_y_id + -1];
}
}
int main()
{
int a[100][2];
int i;
int j;
i = 0;
{
{
/* Auto-generated code for call to _auto_kernel_0 */
typedef int _narray_a[2];
_narray_a *d_a;
cudaMalloc((void **) &d_a, sizeof(int ) * 100 * 2);
cudaMemcpy(d_a, a, sizeof(int ) * 100 * 2, cudaMemcpyHostToDevice);
int CUDA_GRID_X;
CUDA_GRID_X = (100 + CUDA_BLOCK_X - 1)/CUDA_BLOCK_X;
int CUDA_GRID_Y;
CUDA_GRID_Y = (2 + CUDA_BLOCK_Y - 1)/CUDA_BLOCK_Y;
int CUDA_GRID_Z;
CUDA_GRID_Z = (1 + CUDA_BLOCK_Z - 1)/CUDA_BLOCK_Z;
const dim3 CUDA_blockSize(CUDA_BLOCK_X, CUDA_BLOCK_Y, CUDA_BLOCK_Z);
const dim3 CUDA_gridSize(CUDA_GRID_X, CUDA_GRID_Y, CUDA_GRID_Z);
_auto_kernel_0<<<CUDA_gridSize,CUDA_blockSize>>>(d_a);
cudaMemcpy(a, d_a, sizeof(int ) * 100 * 2, cudaMemcpyDeviceToHost);
}
}
return 2;
} | code for sm_80
Function : _Z14_auto_kernel_0PA2_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e280000002100 */
/*0030*/ S2R R4, SR_CTAID.Y ; /* 0x0000000000047919 */
/* 0x000e680000002600 */
/*0040*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e620000002200 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0060*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe20003f05270 */
/*0070*/ IMAD R4, R4, c[0x0][0x4], R5 ; /* 0x0000010004047a24 */
/* 0x002fca00078e0205 */
/*0080*/ ISETP.EQ.OR P0, PT, R4, RZ, !P0 ; /* 0x000000ff0400720c */
/* 0x000fda0004702670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ ISETP.GT.AND P0, PT, R4, 0x2, PT ; /* 0x000000020400780c */
/* 0x000fc80003f04270 */
/*00b0*/ ISETP.GT.OR P0, PT, R0, 0x64, P0 ; /* 0x000000640000780c */
/* 0x000fda0000704670 */
/*00c0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00d0*/ HFMA2.MMA R3, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff037435 */
/* 0x000fe200000001ff */
/*00e0*/ IMAD.SHL.U32 R2, R0, 0x2, RZ ; /* 0x0000000200027824 */
/* 0x000fe200078e00ff */
/*00f0*/ SHF.L.U32 R5, R4, 0x1, RZ ; /* 0x0000000104057819 */
/* 0x000fe200000006ff */
/*0100*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fce0000000a00 */
/*0110*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fcc00078e0203 */
/*0120*/ IMAD.WIDE R2, R5, 0x4, R2 ; /* 0x0000000405027825 */
/* 0x000fca00078e0202 */
/*0130*/ LDG.E R5, [R2.64+-0xc] ; /* 0xfffff40402057981 */
/* 0x000ea8000c1e1900 */
/*0140*/ STG.E [R2.64+-0x18], R5 ; /* 0xffffe80502007986 */
/* 0x004fe2000c101904 */
/*0150*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0160*/ BRA 0x160; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #define CUDA_BLOCK_X 128
#define CUDA_BLOCK_Y 1
#define CUDA_BLOCK_Z 1
__global__ void _auto_kernel_0(int a[100][2])
{
int thread_x_id;thread_x_id = blockIdx.x * blockDim.x + threadIdx.x;
int thread_y_id;thread_y_id = blockIdx.y * blockDim.y + threadIdx.y;
if (thread_x_id && thread_y_id)
if (thread_x_id <= 100 && thread_y_id <= 2) {
a[2 * thread_x_id + -2][2 * thread_y_id + -2] = a[2 * thread_x_id + -1][2 * thread_y_id + -1];
}
}
int main()
{
int a[100][2];
int i;
int j;
i = 0;
{
{
/* Auto-generated code for call to _auto_kernel_0 */
typedef int _narray_a[2];
_narray_a *d_a;
cudaMalloc((void **) &d_a, sizeof(int ) * 100 * 2);
cudaMemcpy(d_a, a, sizeof(int ) * 100 * 2, cudaMemcpyHostToDevice);
int CUDA_GRID_X;
CUDA_GRID_X = (100 + CUDA_BLOCK_X - 1)/CUDA_BLOCK_X;
int CUDA_GRID_Y;
CUDA_GRID_Y = (2 + CUDA_BLOCK_Y - 1)/CUDA_BLOCK_Y;
int CUDA_GRID_Z;
CUDA_GRID_Z = (1 + CUDA_BLOCK_Z - 1)/CUDA_BLOCK_Z;
const dim3 CUDA_blockSize(CUDA_BLOCK_X, CUDA_BLOCK_Y, CUDA_BLOCK_Z);
const dim3 CUDA_gridSize(CUDA_GRID_X, CUDA_GRID_Y, CUDA_GRID_Z);
_auto_kernel_0<<<CUDA_gridSize,CUDA_blockSize>>>(d_a);
cudaMemcpy(a, d_a, sizeof(int ) * 100 * 2, cudaMemcpyDeviceToHost);
}
}
return 2;
} | .file "tmpxft_0003349d_00000000-6_pre1.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z37__device_stub__Z14_auto_kernel_0PA2_iPA2_i
.type _Z37__device_stub__Z14_auto_kernel_0PA2_iPA2_i, @function
_Z37__device_stub__Z14_auto_kernel_0PA2_iPA2_i:
.LFB2052:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z14_auto_kernel_0PA2_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2052:
.size _Z37__device_stub__Z14_auto_kernel_0PA2_iPA2_i, .-_Z37__device_stub__Z14_auto_kernel_0PA2_iPA2_i
.globl _Z14_auto_kernel_0PA2_i
.type _Z14_auto_kernel_0PA2_i, @function
_Z14_auto_kernel_0PA2_i:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z37__device_stub__Z14_auto_kernel_0PA2_iPA2_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _Z14_auto_kernel_0PA2_i, .-_Z14_auto_kernel_0PA2_i
.globl main
.type main, @function
main:
.LFB2027:
.cfi_startproc
endbr64
subq $856, %rsp
.cfi_def_cfa_offset 864
movq %fs:40, %rax
movq %rax, 840(%rsp)
xorl %eax, %eax
movq %rsp, %rdi
movl $800, %esi
call cudaMalloc@PLT
leaq 32(%rsp), %rsi
movl $1, %ecx
movl $800, %edx
movq (%rsp), %rdi
call cudaMemcpy@PLT
movl $128, 8(%rsp)
movl $1, 12(%rsp)
movl $1, 20(%rsp)
movl $2, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 8(%rsp), %rdx
movl $1, %ecx
movq 20(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L15
.L12:
leaq 32(%rsp), %rdi
movl $2, %ecx
movl $800, %edx
movq (%rsp), %rsi
call cudaMemcpy@PLT
movq 840(%rsp), %rax
subq %fs:40, %rax
jne .L16
movl $2, %eax
addq $856, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
movq (%rsp), %rdi
call _Z37__device_stub__Z14_auto_kernel_0PA2_iPA2_i
jmp .L12
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2027:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z14_auto_kernel_0PA2_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z14_auto_kernel_0PA2_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #define CUDA_BLOCK_X 128
#define CUDA_BLOCK_Y 1
#define CUDA_BLOCK_Z 1
__global__ void _auto_kernel_0(int a[100][2])
{
int thread_x_id;thread_x_id = blockIdx.x * blockDim.x + threadIdx.x;
int thread_y_id;thread_y_id = blockIdx.y * blockDim.y + threadIdx.y;
if (thread_x_id && thread_y_id)
if (thread_x_id <= 100 && thread_y_id <= 2) {
a[2 * thread_x_id + -2][2 * thread_y_id + -2] = a[2 * thread_x_id + -1][2 * thread_y_id + -1];
}
}
int main()
{
int a[100][2];
int i;
int j;
i = 0;
{
{
/* Auto-generated code for call to _auto_kernel_0 */
typedef int _narray_a[2];
_narray_a *d_a;
cudaMalloc((void **) &d_a, sizeof(int ) * 100 * 2);
cudaMemcpy(d_a, a, sizeof(int ) * 100 * 2, cudaMemcpyHostToDevice);
int CUDA_GRID_X;
CUDA_GRID_X = (100 + CUDA_BLOCK_X - 1)/CUDA_BLOCK_X;
int CUDA_GRID_Y;
CUDA_GRID_Y = (2 + CUDA_BLOCK_Y - 1)/CUDA_BLOCK_Y;
int CUDA_GRID_Z;
CUDA_GRID_Z = (1 + CUDA_BLOCK_Z - 1)/CUDA_BLOCK_Z;
const dim3 CUDA_blockSize(CUDA_BLOCK_X, CUDA_BLOCK_Y, CUDA_BLOCK_Z);
const dim3 CUDA_gridSize(CUDA_GRID_X, CUDA_GRID_Y, CUDA_GRID_Z);
_auto_kernel_0<<<CUDA_gridSize,CUDA_blockSize>>>(d_a);
cudaMemcpy(a, d_a, sizeof(int ) * 100 * 2, cudaMemcpyDeviceToHost);
}
}
return 2;
} | #include <hip/hip_runtime.h>
#define CUDA_BLOCK_X 128
#define CUDA_BLOCK_Y 1
#define CUDA_BLOCK_Z 1
__global__ void _auto_kernel_0(int a[100][2])
{
int thread_x_id;thread_x_id = blockIdx.x * blockDim.x + threadIdx.x;
int thread_y_id;thread_y_id = blockIdx.y * blockDim.y + threadIdx.y;
if (thread_x_id && thread_y_id)
if (thread_x_id <= 100 && thread_y_id <= 2) {
a[2 * thread_x_id + -2][2 * thread_y_id + -2] = a[2 * thread_x_id + -1][2 * thread_y_id + -1];
}
}
int main()
{
int a[100][2];
int i;
int j;
i = 0;
{
{
/* Auto-generated code for call to _auto_kernel_0 */
typedef int _narray_a[2];
_narray_a *d_a;
hipMalloc((void **) &d_a, sizeof(int ) * 100 * 2);
hipMemcpy(d_a, a, sizeof(int ) * 100 * 2, hipMemcpyHostToDevice);
int CUDA_GRID_X;
CUDA_GRID_X = (100 + CUDA_BLOCK_X - 1)/CUDA_BLOCK_X;
int CUDA_GRID_Y;
CUDA_GRID_Y = (2 + CUDA_BLOCK_Y - 1)/CUDA_BLOCK_Y;
int CUDA_GRID_Z;
CUDA_GRID_Z = (1 + CUDA_BLOCK_Z - 1)/CUDA_BLOCK_Z;
const dim3 CUDA_blockSize(CUDA_BLOCK_X, CUDA_BLOCK_Y, CUDA_BLOCK_Z);
const dim3 CUDA_gridSize(CUDA_GRID_X, CUDA_GRID_Y, CUDA_GRID_Z);
_auto_kernel_0<<<CUDA_gridSize,CUDA_blockSize>>>(d_a);
hipMemcpy(a, d_a, sizeof(int ) * 100 * 2, hipMemcpyDeviceToHost);
}
}
return 2;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#define CUDA_BLOCK_X 128
#define CUDA_BLOCK_Y 1
#define CUDA_BLOCK_Z 1
__global__ void _auto_kernel_0(int a[100][2])
{
int thread_x_id;thread_x_id = blockIdx.x * blockDim.x + threadIdx.x;
int thread_y_id;thread_y_id = blockIdx.y * blockDim.y + threadIdx.y;
if (thread_x_id && thread_y_id)
if (thread_x_id <= 100 && thread_y_id <= 2) {
a[2 * thread_x_id + -2][2 * thread_y_id + -2] = a[2 * thread_x_id + -1][2 * thread_y_id + -1];
}
}
int main()
{
int a[100][2];
int i;
int j;
i = 0;
{
{
/* Auto-generated code for call to _auto_kernel_0 */
typedef int _narray_a[2];
_narray_a *d_a;
hipMalloc((void **) &d_a, sizeof(int ) * 100 * 2);
hipMemcpy(d_a, a, sizeof(int ) * 100 * 2, hipMemcpyHostToDevice);
int CUDA_GRID_X;
CUDA_GRID_X = (100 + CUDA_BLOCK_X - 1)/CUDA_BLOCK_X;
int CUDA_GRID_Y;
CUDA_GRID_Y = (2 + CUDA_BLOCK_Y - 1)/CUDA_BLOCK_Y;
int CUDA_GRID_Z;
CUDA_GRID_Z = (1 + CUDA_BLOCK_Z - 1)/CUDA_BLOCK_Z;
const dim3 CUDA_blockSize(CUDA_BLOCK_X, CUDA_BLOCK_Y, CUDA_BLOCK_Z);
const dim3 CUDA_gridSize(CUDA_GRID_X, CUDA_GRID_Y, CUDA_GRID_Z);
_auto_kernel_0<<<CUDA_gridSize,CUDA_blockSize>>>(d_a);
hipMemcpy(a, d_a, sizeof(int ) * 100 * 2, hipMemcpyDeviceToHost);
}
}
return 2;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z14_auto_kernel_0PA2_i
.globl _Z14_auto_kernel_0PA2_i
.p2align 8
.type _Z14_auto_kernel_0PA2_i,@function
_Z14_auto_kernel_0PA2_i:
s_load_b32 s2, s[0:1], 0x14
v_and_b32_e32 v1, 0x3ff, v0
v_bfe_u32 v4, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_lshr_b32 s2, s2, 16
v_mad_u64_u32 v[2:3], null, s14, s3, v[1:2]
v_mad_u64_u32 v[0:1], null, s15, s2, v[4:5]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_cmp_ne_u32_e32 vcc_lo, 0, v2
v_cmp_gt_i32_e64 s3, 0x65, v2
v_cmp_ne_u32_e64 s2, 0, v0
v_cmp_gt_i32_e64 s4, 3, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
s_and_b32 s2, vcc_lo, s2
s_and_b32 s3, s3, s4
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, s2, s3
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_2
s_load_b64 s[0:1], s[0:1], 0x0
v_lshlrev_b32_e32 v1, 1, v2
v_lshlrev_b32_e32 v3, 1, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v2, 31, v1
v_ashrrev_i32_e32 v4, 31, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[0:1], 3, v[1:2]
v_lshlrev_b64 v[2:3], 2, v[3:4]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v0, v2
v_add_co_ci_u32_e32 v1, vcc_lo, v1, v3, vcc_lo
global_load_b32 v2, v[0:1], off offset:-12
s_waitcnt vmcnt(0)
global_store_b32 v[0:1], v2, off offset:-24
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z14_auto_kernel_0PA2_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 264
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z14_auto_kernel_0PA2_i, .Lfunc_end0-_Z14_auto_kernel_0PA2_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: hidden_block_count_x
- .offset: 12
.size: 4
.value_kind: hidden_block_count_y
- .offset: 16
.size: 4
.value_kind: hidden_block_count_z
- .offset: 20
.size: 2
.value_kind: hidden_group_size_x
- .offset: 22
.size: 2
.value_kind: hidden_group_size_y
- .offset: 24
.size: 2
.value_kind: hidden_group_size_z
- .offset: 26
.size: 2
.value_kind: hidden_remainder_x
- .offset: 28
.size: 2
.value_kind: hidden_remainder_y
- .offset: 30
.size: 2
.value_kind: hidden_remainder_z
- .offset: 48
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 72
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 264
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z14_auto_kernel_0PA2_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z14_auto_kernel_0PA2_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#define CUDA_BLOCK_X 128
#define CUDA_BLOCK_Y 1
#define CUDA_BLOCK_Z 1
__global__ void _auto_kernel_0(int a[100][2])
{
int thread_x_id;thread_x_id = blockIdx.x * blockDim.x + threadIdx.x;
int thread_y_id;thread_y_id = blockIdx.y * blockDim.y + threadIdx.y;
if (thread_x_id && thread_y_id)
if (thread_x_id <= 100 && thread_y_id <= 2) {
a[2 * thread_x_id + -2][2 * thread_y_id + -2] = a[2 * thread_x_id + -1][2 * thread_y_id + -1];
}
}
int main()
{
int a[100][2];
int i;
int j;
i = 0;
{
{
/* Auto-generated code for call to _auto_kernel_0 */
typedef int _narray_a[2];
_narray_a *d_a;
hipMalloc((void **) &d_a, sizeof(int ) * 100 * 2);
hipMemcpy(d_a, a, sizeof(int ) * 100 * 2, hipMemcpyHostToDevice);
int CUDA_GRID_X;
CUDA_GRID_X = (100 + CUDA_BLOCK_X - 1)/CUDA_BLOCK_X;
int CUDA_GRID_Y;
CUDA_GRID_Y = (2 + CUDA_BLOCK_Y - 1)/CUDA_BLOCK_Y;
int CUDA_GRID_Z;
CUDA_GRID_Z = (1 + CUDA_BLOCK_Z - 1)/CUDA_BLOCK_Z;
const dim3 CUDA_blockSize(CUDA_BLOCK_X, CUDA_BLOCK_Y, CUDA_BLOCK_Z);
const dim3 CUDA_gridSize(CUDA_GRID_X, CUDA_GRID_Y, CUDA_GRID_Z);
_auto_kernel_0<<<CUDA_gridSize,CUDA_blockSize>>>(d_a);
hipMemcpy(a, d_a, sizeof(int ) * 100 * 2, hipMemcpyDeviceToHost);
}
}
return 2;
} | .text
.file "pre1.hip"
.globl _Z29__device_stub___auto_kernel_0PA2_i # -- Begin function _Z29__device_stub___auto_kernel_0PA2_i
.p2align 4, 0x90
.type _Z29__device_stub___auto_kernel_0PA2_i,@function
_Z29__device_stub___auto_kernel_0PA2_i: # @_Z29__device_stub___auto_kernel_0PA2_i
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z14_auto_kernel_0PA2_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size _Z29__device_stub___auto_kernel_0PA2_i, .Lfunc_end0-_Z29__device_stub___auto_kernel_0PA2_i
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $888, %rsp # imm = 0x378
.cfi_def_cfa_offset 896
leaq 8(%rsp), %rdi
movl $800, %esi # imm = 0x320
callq hipMalloc
movq 8(%rsp), %rdi
leaq 80(%rsp), %rsi
movl $800, %edx # imm = 0x320
movl $1, %ecx
callq hipMemcpy
movabsq $8589934593, %rdi # imm = 0x200000001
movabsq $4294967424, %rdx # imm = 0x100000080
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq 8(%rsp), %rax
movq %rax, 72(%rsp)
leaq 72(%rsp), %rax
movq %rax, 16(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z14_auto_kernel_0PA2_i, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
movq 8(%rsp), %rsi
leaq 80(%rsp), %rdi
movl $800, %edx # imm = 0x320
movl $2, %ecx
callq hipMemcpy
movl $2, %eax
addq $888, %rsp # imm = 0x378
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14_auto_kernel_0PA2_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z14_auto_kernel_0PA2_i,@object # @_Z14_auto_kernel_0PA2_i
.section .rodata,"a",@progbits
.globl _Z14_auto_kernel_0PA2_i
.p2align 3, 0x0
_Z14_auto_kernel_0PA2_i:
.quad _Z29__device_stub___auto_kernel_0PA2_i
.size _Z14_auto_kernel_0PA2_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z14_auto_kernel_0PA2_i"
.size .L__unnamed_1, 24
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z29__device_stub___auto_kernel_0PA2_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z14_auto_kernel_0PA2_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z14_auto_kernel_0PA2_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e280000002100 */
/*0030*/ S2R R4, SR_CTAID.Y ; /* 0x0000000000047919 */
/* 0x000e680000002600 */
/*0040*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e620000002200 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0060*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe20003f05270 */
/*0070*/ IMAD R4, R4, c[0x0][0x4], R5 ; /* 0x0000010004047a24 */
/* 0x002fca00078e0205 */
/*0080*/ ISETP.EQ.OR P0, PT, R4, RZ, !P0 ; /* 0x000000ff0400720c */
/* 0x000fda0004702670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ ISETP.GT.AND P0, PT, R4, 0x2, PT ; /* 0x000000020400780c */
/* 0x000fc80003f04270 */
/*00b0*/ ISETP.GT.OR P0, PT, R0, 0x64, P0 ; /* 0x000000640000780c */
/* 0x000fda0000704670 */
/*00c0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00d0*/ HFMA2.MMA R3, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff037435 */
/* 0x000fe200000001ff */
/*00e0*/ IMAD.SHL.U32 R2, R0, 0x2, RZ ; /* 0x0000000200027824 */
/* 0x000fe200078e00ff */
/*00f0*/ SHF.L.U32 R5, R4, 0x1, RZ ; /* 0x0000000104057819 */
/* 0x000fe200000006ff */
/*0100*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fce0000000a00 */
/*0110*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fcc00078e0203 */
/*0120*/ IMAD.WIDE R2, R5, 0x4, R2 ; /* 0x0000000405027825 */
/* 0x000fca00078e0202 */
/*0130*/ LDG.E R5, [R2.64+-0xc] ; /* 0xfffff40402057981 */
/* 0x000ea8000c1e1900 */
/*0140*/ STG.E [R2.64+-0x18], R5 ; /* 0xffffe80502007986 */
/* 0x004fe2000c101904 */
/*0150*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0160*/ BRA 0x160; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z14_auto_kernel_0PA2_i
.globl _Z14_auto_kernel_0PA2_i
.p2align 8
.type _Z14_auto_kernel_0PA2_i,@function
_Z14_auto_kernel_0PA2_i:
s_load_b32 s2, s[0:1], 0x14
v_and_b32_e32 v1, 0x3ff, v0
v_bfe_u32 v4, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_lshr_b32 s2, s2, 16
v_mad_u64_u32 v[2:3], null, s14, s3, v[1:2]
v_mad_u64_u32 v[0:1], null, s15, s2, v[4:5]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_cmp_ne_u32_e32 vcc_lo, 0, v2
v_cmp_gt_i32_e64 s3, 0x65, v2
v_cmp_ne_u32_e64 s2, 0, v0
v_cmp_gt_i32_e64 s4, 3, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
s_and_b32 s2, vcc_lo, s2
s_and_b32 s3, s3, s4
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, s2, s3
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_2
s_load_b64 s[0:1], s[0:1], 0x0
v_lshlrev_b32_e32 v1, 1, v2
v_lshlrev_b32_e32 v3, 1, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v2, 31, v1
v_ashrrev_i32_e32 v4, 31, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[0:1], 3, v[1:2]
v_lshlrev_b64 v[2:3], 2, v[3:4]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v0, v2
v_add_co_ci_u32_e32 v1, vcc_lo, v1, v3, vcc_lo
global_load_b32 v2, v[0:1], off offset:-12
s_waitcnt vmcnt(0)
global_store_b32 v[0:1], v2, off offset:-24
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z14_auto_kernel_0PA2_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 264
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z14_auto_kernel_0PA2_i, .Lfunc_end0-_Z14_auto_kernel_0PA2_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: hidden_block_count_x
- .offset: 12
.size: 4
.value_kind: hidden_block_count_y
- .offset: 16
.size: 4
.value_kind: hidden_block_count_z
- .offset: 20
.size: 2
.value_kind: hidden_group_size_x
- .offset: 22
.size: 2
.value_kind: hidden_group_size_y
- .offset: 24
.size: 2
.value_kind: hidden_group_size_z
- .offset: 26
.size: 2
.value_kind: hidden_remainder_x
- .offset: 28
.size: 2
.value_kind: hidden_remainder_y
- .offset: 30
.size: 2
.value_kind: hidden_remainder_z
- .offset: 48
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 72
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 264
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z14_auto_kernel_0PA2_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z14_auto_kernel_0PA2_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0003349d_00000000-6_pre1.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z37__device_stub__Z14_auto_kernel_0PA2_iPA2_i
.type _Z37__device_stub__Z14_auto_kernel_0PA2_iPA2_i, @function
_Z37__device_stub__Z14_auto_kernel_0PA2_iPA2_i:
.LFB2052:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z14_auto_kernel_0PA2_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2052:
.size _Z37__device_stub__Z14_auto_kernel_0PA2_iPA2_i, .-_Z37__device_stub__Z14_auto_kernel_0PA2_iPA2_i
.globl _Z14_auto_kernel_0PA2_i
.type _Z14_auto_kernel_0PA2_i, @function
_Z14_auto_kernel_0PA2_i:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z37__device_stub__Z14_auto_kernel_0PA2_iPA2_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _Z14_auto_kernel_0PA2_i, .-_Z14_auto_kernel_0PA2_i
.globl main
.type main, @function
main:
.LFB2027:
.cfi_startproc
endbr64
subq $856, %rsp
.cfi_def_cfa_offset 864
movq %fs:40, %rax
movq %rax, 840(%rsp)
xorl %eax, %eax
movq %rsp, %rdi
movl $800, %esi
call cudaMalloc@PLT
leaq 32(%rsp), %rsi
movl $1, %ecx
movl $800, %edx
movq (%rsp), %rdi
call cudaMemcpy@PLT
movl $128, 8(%rsp)
movl $1, 12(%rsp)
movl $1, 20(%rsp)
movl $2, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 8(%rsp), %rdx
movl $1, %ecx
movq 20(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L15
.L12:
leaq 32(%rsp), %rdi
movl $2, %ecx
movl $800, %edx
movq (%rsp), %rsi
call cudaMemcpy@PLT
movq 840(%rsp), %rax
subq %fs:40, %rax
jne .L16
movl $2, %eax
addq $856, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
movq (%rsp), %rdi
call _Z37__device_stub__Z14_auto_kernel_0PA2_iPA2_i
jmp .L12
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2027:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z14_auto_kernel_0PA2_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z14_auto_kernel_0PA2_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "pre1.hip"
.globl _Z29__device_stub___auto_kernel_0PA2_i # -- Begin function _Z29__device_stub___auto_kernel_0PA2_i
.p2align 4, 0x90
.type _Z29__device_stub___auto_kernel_0PA2_i,@function
_Z29__device_stub___auto_kernel_0PA2_i: # @_Z29__device_stub___auto_kernel_0PA2_i
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z14_auto_kernel_0PA2_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size _Z29__device_stub___auto_kernel_0PA2_i, .Lfunc_end0-_Z29__device_stub___auto_kernel_0PA2_i
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $888, %rsp # imm = 0x378
.cfi_def_cfa_offset 896
leaq 8(%rsp), %rdi
movl $800, %esi # imm = 0x320
callq hipMalloc
movq 8(%rsp), %rdi
leaq 80(%rsp), %rsi
movl $800, %edx # imm = 0x320
movl $1, %ecx
callq hipMemcpy
movabsq $8589934593, %rdi # imm = 0x200000001
movabsq $4294967424, %rdx # imm = 0x100000080
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq 8(%rsp), %rax
movq %rax, 72(%rsp)
leaq 72(%rsp), %rax
movq %rax, 16(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z14_auto_kernel_0PA2_i, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
movq 8(%rsp), %rsi
leaq 80(%rsp), %rdi
movl $800, %edx # imm = 0x320
movl $2, %ecx
callq hipMemcpy
movl $2, %eax
addq $888, %rsp # imm = 0x378
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14_auto_kernel_0PA2_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z14_auto_kernel_0PA2_i,@object # @_Z14_auto_kernel_0PA2_i
.section .rodata,"a",@progbits
.globl _Z14_auto_kernel_0PA2_i
.p2align 3, 0x0
_Z14_auto_kernel_0PA2_i:
.quad _Z29__device_stub___auto_kernel_0PA2_i
.size _Z14_auto_kernel_0PA2_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z14_auto_kernel_0PA2_i"
.size .L__unnamed_1, 24
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z29__device_stub___auto_kernel_0PA2_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z14_auto_kernel_0PA2_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "mse.hh"
#include <cassert>
#include <stdexcept>
#include "graph.hh"
#include "mse-grad.hh"
#include "ops-builder.hh"
#include "../runtime/node.hh"
#include "../memory/alloc.hh"
namespace ops
{
MSE::MSE(Op* y, Op* y_hat)
: Op("mse", Shape{}, {y, y_hat})
{}
void MSE::compile()
{
auto& g = Graph::instance();
auto& cy = g.compiled(preds()[0]);
auto& cy_hat = g.compiled(preds()[1]);
std::size_t rows = cy.out_shape[0];
std::size_t cols = cy.out_shape[1];
Shape out_shape {};
dbl_t* out_data = tensor_alloc(1);
auto out_node = rt::Node::op_mse(cy.out_data, cy_hat.out_data, out_data,
rows, cols,
{cy.out_node, cy_hat.out_node});
g.add_compiled(this, {out_node}, {out_data}, out_node, out_shape, out_data);
}
Op* MSE::child_grad(std::size_t index, Op* dout)
{
assert(index < 2);
if (index == 0)
throw std::runtime_error {"Can't compute gradient of MSE for y"};
if (dout != nullptr)
throw std::runtime_error {"MSE must be the final node of the gradient"};
auto& builder = OpsBuilder::instance();
return builder.mse_grad(preds()[0] , preds()[1]);
}
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "mse.hh"
#include <cassert>
#include <stdexcept>
#include "graph.hh"
#include "mse-grad.hh"
#include "ops-builder.hh"
#include "../runtime/node.hh"
#include "../memory/alloc.hh"
namespace ops
{
MSE::MSE(Op* y, Op* y_hat)
: Op("mse", Shape{}, {y, y_hat})
{}
void MSE::compile()
{
auto& g = Graph::instance();
auto& cy = g.compiled(preds()[0]);
auto& cy_hat = g.compiled(preds()[1]);
std::size_t rows = cy.out_shape[0];
std::size_t cols = cy.out_shape[1];
Shape out_shape {};
dbl_t* out_data = tensor_alloc(1);
auto out_node = rt::Node::op_mse(cy.out_data, cy_hat.out_data, out_data,
rows, cols,
{cy.out_node, cy_hat.out_node});
g.add_compiled(this, {out_node}, {out_data}, out_node, out_shape, out_data);
}
Op* MSE::child_grad(std::size_t index, Op* dout)
{
assert(index < 2);
if (index == 0)
throw std::runtime_error {"Can't compute gradient of MSE for y"};
if (dout != nullptr)
throw std::runtime_error {"MSE must be the final node of the gradient"};
auto& builder = OpsBuilder::instance();
return builder.mse_grad(preds()[0] , preds()[1]);
}
} | .file "tmpxft_000944fe_00000000-6_mse.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB4630:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4630:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .text._ZN3ops3MSED2Ev,"axG",@progbits,_ZN3ops3MSED5Ev,comdat
.align 2
.weak _ZN3ops3MSED2Ev
.type _ZN3ops3MSED2Ev, @function
_ZN3ops3MSED2Ev:
.LFB5648:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movq %rdi, %rbx
leaq 16+_ZTVN3ops2OpE(%rip), %rax
movq %rax, (%rdi)
movq 88(%rdi), %rdi
testq %rdi, %rdi
je .L4
movq 104(%rbx), %rsi
subq %rdi, %rsi
call _ZdlPvm@PLT
.L4:
movq 64(%rbx), %rdi
testq %rdi, %rdi
je .L5
movq 80(%rbx), %rsi
subq %rdi, %rsi
call _ZdlPvm@PLT
.L5:
movq 40(%rbx), %rdi
testq %rdi, %rdi
je .L6
movq 56(%rbx), %rsi
subq %rdi, %rsi
call _ZdlPvm@PLT
.L6:
movq 8(%rbx), %rdi
leaq 24(%rbx), %rax
cmpq %rax, %rdi
je .L3
movq 24(%rbx), %rsi
addq $1, %rsi
call _ZdlPvm@PLT
.L3:
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE5648:
.size _ZN3ops3MSED2Ev, .-_ZN3ops3MSED2Ev
.weak _ZN3ops3MSED1Ev
.set _ZN3ops3MSED1Ev,_ZN3ops3MSED2Ev
.section .text._ZN3ops3MSED0Ev,"axG",@progbits,_ZN3ops3MSED5Ev,comdat
.align 2
.weak _ZN3ops3MSED0Ev
.type _ZN3ops3MSED0Ev, @function
_ZN3ops3MSED0Ev:
.LFB5650:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movq %rdi, %rbx
leaq 16+_ZTVN3ops2OpE(%rip), %rax
movq %rax, (%rdi)
movq 88(%rdi), %rdi
testq %rdi, %rdi
je .L10
movq 104(%rbx), %rsi
subq %rdi, %rsi
call _ZdlPvm@PLT
.L10:
movq 64(%rbx), %rdi
testq %rdi, %rdi
je .L11
movq 80(%rbx), %rsi
subq %rdi, %rsi
call _ZdlPvm@PLT
.L11:
movq 40(%rbx), %rdi
testq %rdi, %rdi
je .L12
movq 56(%rbx), %rsi
subq %rdi, %rsi
call _ZdlPvm@PLT
.L12:
movq 8(%rbx), %rdi
leaq 24(%rbx), %rax
cmpq %rax, %rdi
je .L13
movq 24(%rbx), %rax
leaq 1(%rax), %rsi
call _ZdlPvm@PLT
.L13:
movl $112, %esi
movq %rbx, %rdi
call _ZdlPvm@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE5650:
.size _ZN3ops3MSED0Ev, .-_ZN3ops3MSED0Ev
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB4653:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4653:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .text._ZNSt6vectorIPN2rt4NodeESaIS2_EED2Ev,"axG",@progbits,_ZNSt6vectorIPN2rt4NodeESaIS2_EED5Ev,comdat
.align 2
.weak _ZNSt6vectorIPN2rt4NodeESaIS2_EED2Ev
.type _ZNSt6vectorIPN2rt4NodeESaIS2_EED2Ev, @function
_ZNSt6vectorIPN2rt4NodeESaIS2_EED2Ev:
.LFB4957:
.cfi_startproc
endbr64
movq (%rdi), %rax
testq %rax, %rax
je .L20
subq $8, %rsp
.cfi_def_cfa_offset 16
movq 16(%rdi), %rsi
subq %rax, %rsi
movq %rax, %rdi
call _ZdlPvm@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.L20:
ret
.cfi_endproc
.LFE4957:
.size _ZNSt6vectorIPN2rt4NodeESaIS2_EED2Ev, .-_ZNSt6vectorIPN2rt4NodeESaIS2_EED2Ev
.weak _ZNSt6vectorIPN2rt4NodeESaIS2_EED1Ev
.set _ZNSt6vectorIPN2rt4NodeESaIS2_EED1Ev,_ZNSt6vectorIPN2rt4NodeESaIS2_EED2Ev
.section .text._ZNSt6vectorIiSaIiEED2Ev,"axG",@progbits,_ZNSt6vectorIiSaIiEED5Ev,comdat
.align 2
.weak _ZNSt6vectorIiSaIiEED2Ev
.type _ZNSt6vectorIiSaIiEED2Ev, @function
_ZNSt6vectorIiSaIiEED2Ev:
.LFB4969:
.cfi_startproc
endbr64
movq (%rdi), %rax
testq %rax, %rax
je .L26
subq $8, %rsp
.cfi_def_cfa_offset 16
movq 16(%rdi), %rsi
subq %rax, %rsi
movq %rax, %rdi
call _ZdlPvm@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.L26:
ret
.cfi_endproc
.LFE4969:
.size _ZNSt6vectorIiSaIiEED2Ev, .-_ZNSt6vectorIiSaIiEED2Ev
.weak _ZNSt6vectorIiSaIiEED1Ev
.set _ZNSt6vectorIiSaIiEED1Ev,_ZNSt6vectorIiSaIiEED2Ev
.section .text._ZNSt6vectorIPN3ops2OpESaIS2_EED2Ev,"axG",@progbits,_ZNSt6vectorIPN3ops2OpESaIS2_EED5Ev,comdat
.align 2
.weak _ZNSt6vectorIPN3ops2OpESaIS2_EED2Ev
.type _ZNSt6vectorIPN3ops2OpESaIS2_EED2Ev, @function
_ZNSt6vectorIPN3ops2OpESaIS2_EED2Ev:
.LFB5001:
.cfi_startproc
endbr64
movq (%rdi), %rax
testq %rax, %rax
je .L32
subq $8, %rsp
.cfi_def_cfa_offset 16
movq 16(%rdi), %rsi
subq %rax, %rsi
movq %rax, %rdi
call _ZdlPvm@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.L32:
ret
.cfi_endproc
.LFE5001:
.size _ZNSt6vectorIPN3ops2OpESaIS2_EED2Ev, .-_ZNSt6vectorIPN3ops2OpESaIS2_EED2Ev
.weak _ZNSt6vectorIPN3ops2OpESaIS2_EED1Ev
.set _ZNSt6vectorIPN3ops2OpESaIS2_EED1Ev,_ZNSt6vectorIPN3ops2OpESaIS2_EED2Ev
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "Can't compute gradient of MSE for y"
.align 8
.LC1:
.string "MSE must be the final node of the gradient"
.text
.align 2
.globl _ZN3ops3MSE10child_gradEmPNS_2OpE
.type _ZN3ops3MSE10child_gradEmPNS_2OpE, @function
_ZN3ops3MSE10child_gradEmPNS_2OpE:
.LFB4627:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA4627
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $64, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
testq %rsi, %rsi
je .L55
movq %rdi, %rbx
testq %rdx, %rdx
jne .L56
.LEHB0:
call _ZN3ops10OpsBuilder8instanceEv@PLT
movq %rax, %rbp
leaq 32(%rsp), %rdi
movq %rbx, %rsi
call _ZN3ops2Op5predsEv@PLT
.LEHE0:
movq 32(%rsp), %rax
movq 8(%rax), %r12
movq %rsp, %rdi
movq %rbx, %rsi
.LEHB1:
call _ZN3ops2Op5predsEv@PLT
.LEHE1:
jmp .L57
.L55:
movl $16, %edi
call __cxa_allocate_exception@PLT
movq %rax, %rbx
leaq .LC0(%rip), %rsi
movq %rax, %rdi
.LEHB2:
call _ZNSt13runtime_errorC1EPKc@PLT
.LEHE2:
movq 56(%rsp), %rax
subq %fs:40, %rax
je .L37
call __stack_chk_fail@PLT
.L37:
movq _ZNSt13runtime_errorD1Ev@GOTPCREL(%rip), %rdx
leaq _ZTISt13runtime_error(%rip), %rsi
movq %rbx, %rdi
.LEHB3:
call __cxa_throw@PLT
.LEHE3:
.L56:
movl $16, %edi
call __cxa_allocate_exception@PLT
movq %rax, %rbx
leaq .LC1(%rip), %rsi
movq %rax, %rdi
.LEHB4:
call _ZNSt13runtime_errorC1EPKc@PLT
.LEHE4:
movq 56(%rsp), %rax
subq %fs:40, %rax
je .L39
call __stack_chk_fail@PLT
.L39:
movq _ZNSt13runtime_errorD1Ev@GOTPCREL(%rip), %rdx
leaq _ZTISt13runtime_error(%rip), %rsi
movq %rbx, %rdi
.LEHB5:
call __cxa_throw@PLT
.LEHE5:
.L57:
movq (%rsp), %rax
movq (%rax), %rsi
movq %r12, %rdx
movq %rbp, %rdi
.LEHB6:
call _ZN3ops10OpsBuilder8mse_gradEPNS_2OpES2_@PLT
.LEHE6:
movq %rax, %rbx
movq (%rsp), %rdi
testq %rdi, %rdi
je .L40
movq 16(%rsp), %rsi
subq %rdi, %rsi
call _ZdlPvm@PLT
.L40:
movq 32(%rsp), %rdi
testq %rdi, %rdi
je .L35
movq 48(%rsp), %rsi
subq %rdi, %rsi
call _ZdlPvm@PLT
.L35:
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L58
movq %rbx, %rax
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L50:
.cfi_restore_state
endbr64
movq %rax, %rbp
movq %rbx, %rdi
call __cxa_free_exception@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
je .L43
call __stack_chk_fail@PLT
.L43:
movq %rbp, %rdi
.LEHB7:
call _Unwind_Resume@PLT
.L51:
endbr64
movq %rax, %rbp
movq %rbx, %rdi
call __cxa_free_exception@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
je .L45
call __stack_chk_fail@PLT
.L45:
movq %rbp, %rdi
call _Unwind_Resume@PLT
.L53:
endbr64
movq %rax, %rbx
movq %rsp, %rdi
call _ZNSt6vectorIPN3ops2OpESaIS2_EED1Ev
.L47:
leaq 32(%rsp), %rdi
call _ZNSt6vectorIPN3ops2OpESaIS2_EED1Ev
movq 56(%rsp), %rax
subq %fs:40, %rax
je .L48
call __stack_chk_fail@PLT
.L52:
endbr64
movq %rax, %rbx
jmp .L47
.L48:
movq %rbx, %rdi
call _Unwind_Resume@PLT
.LEHE7:
.L58:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4627:
.globl __gxx_personality_v0
.section .gcc_except_table,"a",@progbits
.LLSDA4627:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE4627-.LLSDACSB4627
.LLSDACSB4627:
.uleb128 .LEHB0-.LFB4627
.uleb128 .LEHE0-.LEHB0
.uleb128 0
.uleb128 0
.uleb128 .LEHB1-.LFB4627
.uleb128 .LEHE1-.LEHB1
.uleb128 .L52-.LFB4627
.uleb128 0
.uleb128 .LEHB2-.LFB4627
.uleb128 .LEHE2-.LEHB2
.uleb128 .L50-.LFB4627
.uleb128 0
.uleb128 .LEHB3-.LFB4627
.uleb128 .LEHE3-.LEHB3
.uleb128 0
.uleb128 0
.uleb128 .LEHB4-.LFB4627
.uleb128 .LEHE4-.LEHB4
.uleb128 .L51-.LFB4627
.uleb128 0
.uleb128 .LEHB5-.LFB4627
.uleb128 .LEHE5-.LEHB5
.uleb128 0
.uleb128 0
.uleb128 .LEHB6-.LFB4627
.uleb128 .LEHE6-.LEHB6
.uleb128 .L53-.LFB4627
.uleb128 0
.uleb128 .LEHB7-.LFB4627
.uleb128 .LEHE7-.LEHB7
.uleb128 0
.uleb128 0
.LLSDACSE4627:
.text
.size _ZN3ops3MSE10child_gradEmPNS_2OpE, .-_ZN3ops3MSE10child_gradEmPNS_2OpE
.align 2
.globl _ZN3ops3MSEC2EPNS_2OpES2_
.type _ZN3ops3MSEC2EPNS_2OpES2_, @function
_ZN3ops3MSEC2EPNS_2OpES2_:
.LFB4624:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA4624
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $176, %rsp
.cfi_def_cfa_offset 208
movq %rdi, %rbx
movq %rsi, %r12
movq %rdx, %rbp
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
movq $0, 96(%rsp)
movq $0, 104(%rsp)
movq $0, 112(%rsp)
movq $0, 64(%rsp)
movq $0, 72(%rsp)
movq $0, 80(%rsp)
movl $16, %edi
.LEHB8:
call _Znwm@PLT
.LEHE8:
movq %rax, 64(%rsp)
leaq 16(%rax), %rdx
movq %rdx, 80(%rsp)
movq %r12, (%rax)
movq %rbp, 8(%rax)
movq %rdx, 72(%rsp)
movq $0, 32(%rsp)
movq $0, 40(%rsp)
movq $0, 48(%rsp)
leaq 32(%rsp), %rsi
movq %rsp, %rdi
.LEHB9:
call _ZN3ops5ShapeC1ERKSt6vectorIiSaIiEE@PLT
.LEHE9:
jmp .L79
.L75:
endbr64
movq %rax, %rbx
movq 64(%rsp), %rdi
movq 80(%rsp), %rsi
subq %rdi, %rsi
testq %rdi, %rdi
je .L63
call _ZdlPvm@PLT
.L63:
leaq 96(%rsp), %rdi
call _ZNSt6vectorIPN3ops2OpESaIS2_EED1Ev
movq 168(%rsp), %rax
subq %fs:40, %rax
je .L71
call __stack_chk_fail@PLT
.L79:
leaq 128(%rsp), %rsi
leaq 144(%rsp), %rax
movq %rax, 128(%rsp)
movw $29549, 144(%rsp)
movb $101, 146(%rsp)
movq $3, 136(%rsp)
movb $0, 147(%rsp)
leaq 64(%rsp), %rcx
movq %rsp, %rdx
leaq 96(%rsp), %r8
movq %rbx, %rdi
.LEHB10:
call _ZN3ops2OpC2ERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEERKNS_5ShapeESt6vectorIPS0_SaISD_EESF_@PLT
.LEHE10:
movq 128(%rsp), %rdi
leaq 144(%rsp), %rax
cmpq %rax, %rdi
je .L64
movq 144(%rsp), %rax
leaq 1(%rax), %rsi
call _ZdlPvm@PLT
.L64:
movq (%rsp), %rdi
testq %rdi, %rdi
je .L65
movq 16(%rsp), %rsi
subq %rdi, %rsi
call _ZdlPvm@PLT
.L65:
movq 32(%rsp), %rdi
testq %rdi, %rdi
je .L66
movq 48(%rsp), %rsi
subq %rdi, %rsi
call _ZdlPvm@PLT
.L66:
movq 64(%rsp), %rdi
testq %rdi, %rdi
je .L67
movq 80(%rsp), %rsi
subq %rdi, %rsi
call _ZdlPvm@PLT
.L67:
movq 96(%rsp), %rdi
testq %rdi, %rdi
je .L68
movq 112(%rsp), %rsi
subq %rdi, %rsi
call _ZdlPvm@PLT
.L68:
leaq 16+_ZTVN3ops3MSEE(%rip), %rax
movq %rax, (%rbx)
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L80
addq $176, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L74:
.cfi_restore_state
endbr64
movq %rax, %rbx
leaq 128(%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
movq %rsp, %rdi
call _ZNSt6vectorIiSaIiEED1Ev
.L70:
leaq 32(%rsp), %rdi
call _ZNSt6vectorIiSaIiEED1Ev
leaq 64(%rsp), %rdi
call _ZNSt6vectorIPN3ops2OpESaIS2_EED1Ev
jmp .L63
.L73:
endbr64
movq %rax, %rbx
jmp .L70
.L71:
movq %rbx, %rdi
.LEHB11:
call _Unwind_Resume@PLT
.LEHE11:
.L80:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4624:
.section .gcc_except_table
.LLSDA4624:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE4624-.LLSDACSB4624
.LLSDACSB4624:
.uleb128 .LEHB8-.LFB4624
.uleb128 .LEHE8-.LEHB8
.uleb128 .L75-.LFB4624
.uleb128 0
.uleb128 .LEHB9-.LFB4624
.uleb128 .LEHE9-.LEHB9
.uleb128 .L73-.LFB4624
.uleb128 0
.uleb128 .LEHB10-.LFB4624
.uleb128 .LEHE10-.LEHB10
.uleb128 .L74-.LFB4624
.uleb128 0
.uleb128 .LEHB11-.LFB4624
.uleb128 .LEHE11-.LEHB11
.uleb128 0
.uleb128 0
.LLSDACSE4624:
.text
.size _ZN3ops3MSEC2EPNS_2OpES2_, .-_ZN3ops3MSEC2EPNS_2OpES2_
.globl _ZN3ops3MSEC1EPNS_2OpES2_
.set _ZN3ops3MSEC1EPNS_2OpES2_,_ZN3ops3MSEC2EPNS_2OpES2_
.section .text._ZNSt12_Vector_baseIPN2rt4NodeESaIS2_EED2Ev,"axG",@progbits,_ZNSt12_Vector_baseIPN2rt4NodeESaIS2_EED5Ev,comdat
.align 2
.weak _ZNSt12_Vector_baseIPN2rt4NodeESaIS2_EED2Ev
.type _ZNSt12_Vector_baseIPN2rt4NodeESaIS2_EED2Ev, @function
_ZNSt12_Vector_baseIPN2rt4NodeESaIS2_EED2Ev:
.LFB5181:
.cfi_startproc
endbr64
movq (%rdi), %rax
testq %rax, %rax
je .L84
subq $8, %rsp
.cfi_def_cfa_offset 16
movq 16(%rdi), %rsi
subq %rax, %rsi
movq %rax, %rdi
call _ZdlPvm@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.L84:
ret
.cfi_endproc
.LFE5181:
.size _ZNSt12_Vector_baseIPN2rt4NodeESaIS2_EED2Ev, .-_ZNSt12_Vector_baseIPN2rt4NodeESaIS2_EED2Ev
.weak _ZNSt12_Vector_baseIPN2rt4NodeESaIS2_EED1Ev
.set _ZNSt12_Vector_baseIPN2rt4NodeESaIS2_EED1Ev,_ZNSt12_Vector_baseIPN2rt4NodeESaIS2_EED2Ev
.text
.align 2
.globl _ZN3ops3MSE7compileEv
.type _ZN3ops3MSE7compileEv, @function
_ZN3ops3MSE7compileEv:
.LFB4626:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA4626
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
movq %rsp, %rbp
.cfi_def_cfa_register 6
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $136, %rsp
.cfi_offset 15, -24
.cfi_offset 14, -32
.cfi_offset 13, -40
.cfi_offset 12, -48
.cfi_offset 3, -56
movq %rdi, %r12
movq %fs:40, %rax
movq %rax, -56(%rbp)
xorl %eax, %eax
.LEHB12:
call _ZN3ops5Graph8instanceEv@PLT
movq %rax, %rbx
movq %rax, -152(%rbp)
leaq -80(%rbp), %rdi
movq %r12, %rsi
call _ZN3ops2Op5predsEv@PLT
.LEHE12:
movq -80(%rbp), %rax
movq (%rax), %rsi
movq %rbx, %rdi
.LEHB13:
call _ZN3ops5Graph8compiledEPNS_2OpE@PLT
.LEHE13:
movq %rax, %rbx
movq -80(%rbp), %rdi
testq %rdi, %rdi
je .L88
movq -64(%rbp), %rsi
subq %rdi, %rsi
call _ZdlPvm@PLT
.L88:
leaq -80(%rbp), %rdi
movq %r12, %rsi
.LEHB14:
call _ZN3ops2Op5predsEv@PLT
.LEHE14:
movq -80(%rbp), %rax
movq 8(%rax), %rsi
movq -152(%rbp), %rdi
.LEHB15:
call _ZN3ops5Graph8compiledEPNS_2OpE@PLT
.LEHE15:
movq %rax, %r14
movq -80(%rbp), %rdi
testq %rdi, %rdi
je .L89
movq -64(%rbp), %rsi
subq %rdi, %rsi
call _ZdlPvm@PLT
.L89:
leaq 64(%rbx), %r13
movl $0, %esi
movq %r13, %rdi
.LEHB16:
call _ZNK3ops5ShapeixEm@PLT
cltq
movq %rax, -160(%rbp)
movl $1, %esi
movq %r13, %rdi
call _ZNK3ops5ShapeixEm@PLT
.LEHE16:
cltq
movq %rax, -168(%rbp)
movq $0, -80(%rbp)
movq $0, -72(%rbp)
movq $0, -64(%rbp)
leaq -80(%rbp), %rsi
leaq -144(%rbp), %rdi
.LEHB17:
call _ZN3ops5ShapeC1ERKSt6vectorIiSaIiEE@PLT
.LEHE17:
movq -80(%rbp), %rdi
testq %rdi, %rdi
je .L90
movq -64(%rbp), %rsi
subq %rdi, %rsi
call _ZdlPvm@PLT
.L90:
movl $1, %edi
.LEHB18:
call _Z12tensor_allocm@PLT
.LEHE18:
movq %rax, %r13
movq 56(%rbx), %rax
movq %rax, -176(%rbp)
movq 56(%r14), %r15
movq $0, -80(%rbp)
movq $0, -72(%rbp)
movq $0, -64(%rbp)
movl $16, %edi
.LEHB19:
call _Znwm@PLT
.LEHE19:
movq %rax, -80(%rbp)
leaq 16(%rax), %rdx
movq %rdx, -64(%rbp)
movq -176(%rbp), %rcx
movq %rcx, (%rax)
movq %r15, 8(%rax)
movq %rdx, -72(%rbp)
movq 88(%r14), %rsi
movq 88(%rbx), %rdi
leaq -80(%rbp), %r9
movq -168(%rbp), %r8
movq -160(%rbp), %rcx
movq %r13, %rdx
.LEHB20:
call _ZN2rt4Node6op_mseEPKfS2_PfmmRKSt6vectorIPS0_SaIS5_EE@PLT
.LEHE20:
movq %rax, %rbx
movq -80(%rbp), %rdi
testq %rdi, %rdi
je .L94
movq -64(%rbp), %rsi
subq %rdi, %rsi
call _ZdlPvm@PLT
.L94:
movq $0, -80(%rbp)
movq $0, -72(%rbp)
movq $0, -64(%rbp)
movl $8, %edi
.LEHB21:
call _Znwm@PLT
.LEHE21:
jmp .L128
.L121:
endbr64
movq %rax, %rbx
leaq -80(%rbp), %rdi
call _ZNSt12_Vector_baseIPN2rt4NodeESaIS2_EED2Ev
.L93:
leaq -144(%rbp), %rdi
call _ZNSt6vectorIiSaIiEED1Ev
movq -56(%rbp), %rax
subq %fs:40, %rax
je .L113
call __stack_chk_fail@PLT
.L128:
movq %rax, -80(%rbp)
leaq 8(%rax), %rdx
movq %rdx, -64(%rbp)
movq %r13, (%rax)
movq %rdx, -72(%rbp)
movq $0, -112(%rbp)
movq $0, -104(%rbp)
movq $0, -96(%rbp)
movl $8, %edi
.LEHB22:
call _Znwm@PLT
.LEHE22:
movq %rax, -112(%rbp)
leaq 8(%rax), %rdx
movq %rdx, -96(%rbp)
movq %rbx, (%rax)
movq %rdx, -104(%rbp)
leaq -80(%rbp), %rcx
leaq -112(%rbp), %rdx
subq $8, %rsp
pushq %r13
leaq -144(%rbp), %r9
movq %rbx, %r8
movq %r12, %rsi
movq -152(%rbp), %rdi
.LEHB23:
.cfi_escape 0x2e,0x10
call _ZN3ops5Graph12add_compiledEPNS_2OpESt6vectorIPN2rt4NodeESaIS6_EES3_IPfSaIS9_EES6_RKNS_5ShapeES9_@PLT
.LEHE23:
jmp .L129
.L122:
endbr64
movq %rax, %rbx
movq -80(%rbp), %rdi
movq -64(%rbp), %rsi
subq %rdi, %rsi
testq %rdi, %rdi
je .L93
call _ZdlPvm@PLT
jmp .L93
.L129:
addq $16, %rsp
movq -112(%rbp), %rdi
testq %rdi, %rdi
je .L101
movq -96(%rbp), %rsi
subq %rdi, %rsi
call _ZdlPvm@PLT
.L101:
movq -80(%rbp), %rdi
testq %rdi, %rdi
je .L102
movq -64(%rbp), %rsi
subq %rdi, %rsi
call _ZdlPvm@PLT
.L102:
movq -144(%rbp), %rdi
testq %rdi, %rdi
je .L87
movq -128(%rbp), %rsi
subq %rdi, %rsi
call _ZdlPvm@PLT
.L87:
movq -56(%rbp), %rax
subq %fs:40, %rax
jne .L130
leaq -40(%rbp), %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
.cfi_remember_state
.cfi_def_cfa 7, 8
ret
.L123:
.cfi_restore_state
endbr64
movq %rax, %rbx
leaq -112(%rbp), %rdi
call _ZNSt12_Vector_baseIPN2rt4NodeESaIS2_EED2Ev
.L100:
movq -80(%rbp), %rdi
movq -64(%rbp), %rsi
subq %rdi, %rsi
testq %rdi, %rdi
je .L93
call _ZdlPvm@PLT
jmp .L93
.L115:
endbr64
movq %rax, %rbx
leaq -80(%rbp), %rdi
call _ZNSt6vectorIPN3ops2OpESaIS2_EED1Ev
movq -56(%rbp), %rax
subq %fs:40, %rax
je .L105
call __stack_chk_fail@PLT
.L105:
movq %rbx, %rdi
.LEHB24:
call _Unwind_Resume@PLT
.L116:
endbr64
movq %rax, %rbx
leaq -80(%rbp), %rdi
call _ZNSt6vectorIPN3ops2OpESaIS2_EED1Ev
movq -56(%rbp), %rax
subq %fs:40, %rax
je .L107
call __stack_chk_fail@PLT
.L107:
movq %rbx, %rdi
call _Unwind_Resume@PLT
.L117:
endbr64
movq %rax, %rbx
leaq -80(%rbp), %rdi
call _ZNSt6vectorIiSaIiEED1Ev
movq -56(%rbp), %rax
subq %fs:40, %rax
je .L109
call __stack_chk_fail@PLT
.L109:
movq %rbx, %rdi
call _Unwind_Resume@PLT
.L119:
endbr64
movq %rax, %rbx
leaq -80(%rbp), %rdi
call _ZNSt6vectorIPN2rt4NodeESaIS2_EED1Ev
jmp .L93
.L120:
endbr64
movq %rax, %rbx
leaq -112(%rbp), %rdi
call _ZNSt6vectorIPN2rt4NodeESaIS2_EED1Ev
jmp .L100
.L118:
endbr64
movq %rax, %rbx
jmp .L93
.L113:
movq %rbx, %rdi
call _Unwind_Resume@PLT
.LEHE24:
.L130:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4626:
.section .gcc_except_table
.LLSDA4626:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE4626-.LLSDACSB4626
.LLSDACSB4626:
.uleb128 .LEHB12-.LFB4626
.uleb128 .LEHE12-.LEHB12
.uleb128 0
.uleb128 0
.uleb128 .LEHB13-.LFB4626
.uleb128 .LEHE13-.LEHB13
.uleb128 .L115-.LFB4626
.uleb128 0
.uleb128 .LEHB14-.LFB4626
.uleb128 .LEHE14-.LEHB14
.uleb128 0
.uleb128 0
.uleb128 .LEHB15-.LFB4626
.uleb128 .LEHE15-.LEHB15
.uleb128 .L116-.LFB4626
.uleb128 0
.uleb128 .LEHB16-.LFB4626
.uleb128 .LEHE16-.LEHB16
.uleb128 0
.uleb128 0
.uleb128 .LEHB17-.LFB4626
.uleb128 .LEHE17-.LEHB17
.uleb128 .L117-.LFB4626
.uleb128 0
.uleb128 .LEHB18-.LFB4626
.uleb128 .LEHE18-.LEHB18
.uleb128 .L118-.LFB4626
.uleb128 0
.uleb128 .LEHB19-.LFB4626
.uleb128 .LEHE19-.LEHB19
.uleb128 .L121-.LFB4626
.uleb128 0
.uleb128 .LEHB20-.LFB4626
.uleb128 .LEHE20-.LEHB20
.uleb128 .L119-.LFB4626
.uleb128 0
.uleb128 .LEHB21-.LFB4626
.uleb128 .LEHE21-.LEHB21
.uleb128 .L122-.LFB4626
.uleb128 0
.uleb128 .LEHB22-.LFB4626
.uleb128 .LEHE22-.LEHB22
.uleb128 .L123-.LFB4626
.uleb128 0
.uleb128 .LEHB23-.LFB4626
.uleb128 .LEHE23-.LEHB23
.uleb128 .L120-.LFB4626
.uleb128 0
.uleb128 .LEHB24-.LFB4626
.uleb128 .LEHE24-.LEHB24
.uleb128 0
.uleb128 0
.LLSDACSE4626:
.text
.size _ZN3ops3MSE7compileEv, .-_ZN3ops3MSE7compileEv
.weak _ZTSN3ops3MSEE
.section .rodata._ZTSN3ops3MSEE,"aG",@progbits,_ZTSN3ops3MSEE,comdat
.align 8
.type _ZTSN3ops3MSEE, @object
.size _ZTSN3ops3MSEE, 11
_ZTSN3ops3MSEE:
.string "N3ops3MSEE"
.weak _ZTIN3ops3MSEE
.section .data.rel.ro._ZTIN3ops3MSEE,"awG",@progbits,_ZTIN3ops3MSEE,comdat
.align 8
.type _ZTIN3ops3MSEE, @object
.size _ZTIN3ops3MSEE, 24
_ZTIN3ops3MSEE:
.quad _ZTVN10__cxxabiv120__si_class_type_infoE+16
.quad _ZTSN3ops3MSEE
.quad _ZTIN3ops2OpE
.weak _ZTVN3ops3MSEE
.section .data.rel.ro.local._ZTVN3ops3MSEE,"awG",@progbits,_ZTVN3ops3MSEE,comdat
.align 8
.type _ZTVN3ops3MSEE, @object
.size _ZTVN3ops3MSEE, 48
_ZTVN3ops3MSEE:
.quad 0
.quad _ZTIN3ops3MSEE
.quad _ZN3ops3MSED1Ev
.quad _ZN3ops3MSED0Ev
.quad _ZN3ops3MSE7compileEv
.quad _ZN3ops3MSE10child_gradEmPNS_2OpE
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.hidden DW.ref.__gxx_personality_v0
.weak DW.ref.__gxx_personality_v0
.section .data.rel.local.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat
.align 8
.type DW.ref.__gxx_personality_v0, @object
.size DW.ref.__gxx_personality_v0, 8
DW.ref.__gxx_personality_v0:
.quad __gxx_personality_v0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "mse.hh"
#include <cassert>
#include <stdexcept>
#include "graph.hh"
#include "mse-grad.hh"
#include "ops-builder.hh"
#include "../runtime/node.hh"
#include "../memory/alloc.hh"
namespace ops
{
MSE::MSE(Op* y, Op* y_hat)
: Op("mse", Shape{}, {y, y_hat})
{}
void MSE::compile()
{
auto& g = Graph::instance();
auto& cy = g.compiled(preds()[0]);
auto& cy_hat = g.compiled(preds()[1]);
std::size_t rows = cy.out_shape[0];
std::size_t cols = cy.out_shape[1];
Shape out_shape {};
dbl_t* out_data = tensor_alloc(1);
auto out_node = rt::Node::op_mse(cy.out_data, cy_hat.out_data, out_data,
rows, cols,
{cy.out_node, cy_hat.out_node});
g.add_compiled(this, {out_node}, {out_data}, out_node, out_shape, out_data);
}
Op* MSE::child_grad(std::size_t index, Op* dout)
{
assert(index < 2);
if (index == 0)
throw std::runtime_error {"Can't compute gradient of MSE for y"};
if (dout != nullptr)
throw std::runtime_error {"MSE must be the final node of the gradient"};
auto& builder = OpsBuilder::instance();
return builder.mse_grad(preds()[0] , preds()[1]);
}
} | #include <hip/hip_runtime.h>
#include "mse.hh"
#include <cassert>
#include <stdexcept>
#include "graph.hh"
#include "mse-grad.hh"
#include "ops-builder.hh"
#include "../runtime/node.hh"
#include "../memory/alloc.hh"
namespace ops
{
MSE::MSE(Op* y, Op* y_hat)
: Op("mse", Shape{}, {y, y_hat})
{}
void MSE::compile()
{
auto& g = Graph::instance();
auto& cy = g.compiled(preds()[0]);
auto& cy_hat = g.compiled(preds()[1]);
std::size_t rows = cy.out_shape[0];
std::size_t cols = cy.out_shape[1];
Shape out_shape {};
dbl_t* out_data = tensor_alloc(1);
auto out_node = rt::Node::op_mse(cy.out_data, cy_hat.out_data, out_data,
rows, cols,
{cy.out_node, cy_hat.out_node});
g.add_compiled(this, {out_node}, {out_data}, out_node, out_shape, out_data);
}
Op* MSE::child_grad(std::size_t index, Op* dout)
{
assert(index < 2);
if (index == 0)
throw std::runtime_error {"Can't compute gradient of MSE for y"};
if (dout != nullptr)
throw std::runtime_error {"MSE must be the final node of the gradient"};
auto& builder = OpsBuilder::instance();
return builder.mse_grad(preds()[0] , preds()[1]);
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "mse.hh"
#include <cassert>
#include <stdexcept>
#include "graph.hh"
#include "mse-grad.hh"
#include "ops-builder.hh"
#include "../runtime/node.hh"
#include "../memory/alloc.hh"
namespace ops
{
MSE::MSE(Op* y, Op* y_hat)
: Op("mse", Shape{}, {y, y_hat})
{}
void MSE::compile()
{
auto& g = Graph::instance();
auto& cy = g.compiled(preds()[0]);
auto& cy_hat = g.compiled(preds()[1]);
std::size_t rows = cy.out_shape[0];
std::size_t cols = cy.out_shape[1];
Shape out_shape {};
dbl_t* out_data = tensor_alloc(1);
auto out_node = rt::Node::op_mse(cy.out_data, cy_hat.out_data, out_data,
rows, cols,
{cy.out_node, cy_hat.out_node});
g.add_compiled(this, {out_node}, {out_data}, out_node, out_shape, out_data);
}
Op* MSE::child_grad(std::size_t index, Op* dout)
{
assert(index < 2);
if (index == 0)
throw std::runtime_error {"Can't compute gradient of MSE for y"};
if (dout != nullptr)
throw std::runtime_error {"MSE must be the final node of the gradient"};
auto& builder = OpsBuilder::instance();
return builder.mse_grad(preds()[0] , preds()[1]);
}
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "mse.hh"
#include <cassert>
#include <stdexcept>
#include "graph.hh"
#include "mse-grad.hh"
#include "ops-builder.hh"
#include "../runtime/node.hh"
#include "../memory/alloc.hh"
namespace ops
{
MSE::MSE(Op* y, Op* y_hat)
: Op("mse", Shape{}, {y, y_hat})
{}
void MSE::compile()
{
auto& g = Graph::instance();
auto& cy = g.compiled(preds()[0]);
auto& cy_hat = g.compiled(preds()[1]);
std::size_t rows = cy.out_shape[0];
std::size_t cols = cy.out_shape[1];
Shape out_shape {};
dbl_t* out_data = tensor_alloc(1);
auto out_node = rt::Node::op_mse(cy.out_data, cy_hat.out_data, out_data,
rows, cols,
{cy.out_node, cy_hat.out_node});
g.add_compiled(this, {out_node}, {out_data}, out_node, out_shape, out_data);
}
Op* MSE::child_grad(std::size_t index, Op* dout)
{
assert(index < 2);
if (index == 0)
throw std::runtime_error {"Can't compute gradient of MSE for y"};
if (dout != nullptr)
throw std::runtime_error {"MSE must be the final node of the gradient"};
auto& builder = OpsBuilder::instance();
return builder.mse_grad(preds()[0] , preds()[1]);
}
} | .text
.file "mse.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function _ZN3ops3MSEC2EPNS_2OpES2_
.LCPI0_0:
.zero 16
.text
.globl _ZN3ops3MSEC2EPNS_2OpES2_
.p2align 4, 0x90
.type _ZN3ops3MSEC2EPNS_2OpES2_,@function
_ZN3ops3MSEC2EPNS_2OpES2_: # @_ZN3ops3MSEC2EPNS_2OpES2_
.Lfunc_begin0:
.cfi_startproc
.cfi_personality 3, __gxx_personality_v0
.cfi_lsda 3, .Lexception0
# %bb.0: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_.exit
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $152, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdx, %r14
movq %rsi, %r15
movq %rdi, %rbx
leaq 48(%rsp), %r12
movq %r12, 32(%rsp)
movl $6648685, 48(%rsp) # imm = 0x65736D
movq $3, 40(%rsp)
xorps %xmm0, %xmm0
movaps %xmm0, 96(%rsp)
movq $0, 112(%rsp)
.Ltmp0:
leaq 128(%rsp), %rdi
leaq 96(%rsp), %rsi
callq _ZN3ops5ShapeC1ERKSt6vectorIiSaIiEE
.Ltmp1:
# %bb.1:
xorps %xmm0, %xmm0
movaps %xmm0, (%rsp)
movq $0, 16(%rsp)
.Ltmp3:
movl $16, %edi
callq _Znwm
.Ltmp4:
# %bb.2: # %_ZNSt6vectorIPN3ops2OpESaIS2_EEC2ESt16initializer_listIS2_ERKS3_.exit
movq %rax, (%rsp)
movq %rax, %rcx
addq $16, %rcx
movq %rcx, 16(%rsp)
movq %r15, (%rax)
movq %r14, 8(%rax)
movq %rcx, 8(%rsp)
xorps %xmm0, %xmm0
movaps %xmm0, 64(%rsp)
movq $0, 80(%rsp)
.Ltmp6:
leaq 32(%rsp), %rsi
leaq 128(%rsp), %rdx
movq %rsp, %rcx
leaq 64(%rsp), %r8
movq %rbx, %rdi
callq _ZN3ops2OpC2ERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEERKNS_5ShapeESt6vectorIPS0_SaISD_EESF_
.Ltmp7:
# %bb.3:
movq 64(%rsp), %rdi
testq %rdi, %rdi
je .LBB0_5
# %bb.4:
callq _ZdlPv
.LBB0_5: # %_ZNSt6vectorIPN3ops2OpESaIS2_EED2Ev.exit
movq (%rsp), %rdi
testq %rdi, %rdi
je .LBB0_7
# %bb.6:
callq _ZdlPv
.LBB0_7: # %_ZNSt6vectorIPN3ops2OpESaIS2_EED2Ev.exit15
movq 128(%rsp), %rdi
testq %rdi, %rdi
je .LBB0_9
# %bb.8:
callq _ZdlPv
.LBB0_9: # %_ZN3ops5ShapeD2Ev.exit
movq 96(%rsp), %rdi
testq %rdi, %rdi
je .LBB0_11
# %bb.10:
callq _ZdlPv
.LBB0_11: # %_ZNSt6vectorIiSaIiEED2Ev.exit
movq 32(%rsp), %rdi
cmpq %r12, %rdi
je .LBB0_13
# %bb.12: # %.critedge.i.i
callq _ZdlPv
.LBB0_13: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit
movq $_ZTVN3ops3MSEE+16, (%rbx)
addq $152, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB0_15:
.cfi_def_cfa_offset 192
.Ltmp8:
movq %rax, %rbx
movq 64(%rsp), %rdi
testq %rdi, %rdi
je .LBB0_17
# %bb.16:
callq _ZdlPv
jmp .LBB0_17
.LBB0_26:
.Ltmp5:
movq %rax, %rbx
.LBB0_17: # %_ZNSt6vectorIPN3ops2OpESaIS2_EED2Ev.exit19
movq (%rsp), %rdi
testq %rdi, %rdi
je .LBB0_19
# %bb.18: # %.body.sink.split
callq _ZdlPv
.LBB0_19: # %.body
movq 128(%rsp), %rdi
testq %rdi, %rdi
je .LBB0_21
# %bb.20:
callq _ZdlPv
jmp .LBB0_21
.LBB0_14:
.Ltmp2:
movq %rax, %rbx
.LBB0_21: # %_ZN3ops5ShapeD2Ev.exit24
movq 96(%rsp), %rdi
testq %rdi, %rdi
je .LBB0_23
# %bb.22:
callq _ZdlPv
.LBB0_23: # %_ZNSt6vectorIiSaIiEED2Ev.exit26
movq 32(%rsp), %rdi
cmpq %r12, %rdi
je .LBB0_25
# %bb.24: # %.critedge.i.i27
callq _ZdlPv
.LBB0_25: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit29
movq %rbx, %rdi
callq _Unwind_Resume@PLT
.Lfunc_end0:
.size _ZN3ops3MSEC2EPNS_2OpES2_, .Lfunc_end0-_ZN3ops3MSEC2EPNS_2OpES2_
.cfi_endproc
.section .gcc_except_table,"a",@progbits
.p2align 2, 0x0
GCC_except_table0:
.Lexception0:
.byte 255 # @LPStart Encoding = omit
.byte 255 # @TType Encoding = omit
.byte 1 # Call site Encoding = uleb128
.uleb128 .Lcst_end0-.Lcst_begin0
.Lcst_begin0:
.uleb128 .Ltmp0-.Lfunc_begin0 # >> Call Site 1 <<
.uleb128 .Ltmp1-.Ltmp0 # Call between .Ltmp0 and .Ltmp1
.uleb128 .Ltmp2-.Lfunc_begin0 # jumps to .Ltmp2
.byte 0 # On action: cleanup
.uleb128 .Ltmp3-.Lfunc_begin0 # >> Call Site 2 <<
.uleb128 .Ltmp4-.Ltmp3 # Call between .Ltmp3 and .Ltmp4
.uleb128 .Ltmp5-.Lfunc_begin0 # jumps to .Ltmp5
.byte 0 # On action: cleanup
.uleb128 .Ltmp6-.Lfunc_begin0 # >> Call Site 3 <<
.uleb128 .Ltmp7-.Ltmp6 # Call between .Ltmp6 and .Ltmp7
.uleb128 .Ltmp8-.Lfunc_begin0 # jumps to .Ltmp8
.byte 0 # On action: cleanup
.uleb128 .Ltmp7-.Lfunc_begin0 # >> Call Site 4 <<
.uleb128 .Lfunc_end0-.Ltmp7 # Call between .Ltmp7 and .Lfunc_end0
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.Lcst_end0:
.p2align 2, 0x0
# -- End function
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function _ZN3ops3MSE7compileEv
.LCPI1_0:
.zero 16
.text
.globl _ZN3ops3MSE7compileEv
.p2align 4, 0x90
.type _ZN3ops3MSE7compileEv,@function
_ZN3ops3MSE7compileEv: # @_ZN3ops3MSE7compileEv
.Lfunc_begin1:
.cfi_startproc
.cfi_personality 3, __gxx_personality_v0
.cfi_lsda 3, .Lexception1
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $152, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rdi, %r14
callq _ZN3ops5Graph8instanceEv
movq %rax, %rbx
leaq 40(%rsp), %rdi
movq %r14, %rsi
callq _ZN3ops2Op5predsEv
movq 40(%rsp), %rax
movq (%rax), %rsi
.Ltmp9:
movq %rbx, %rdi
callq _ZN3ops5Graph8compiledEPNS_2OpE
.Ltmp10:
# %bb.1:
movq %rax, %r12
movq 40(%rsp), %rdi
testq %rdi, %rdi
je .LBB1_3
# %bb.2:
callq _ZdlPv
.LBB1_3: # %_ZNSt6vectorIPN3ops2OpESaIS2_EED2Ev.exit
leaq 40(%rsp), %rdi
movq %r14, %rsi
callq _ZN3ops2Op5predsEv
movq 40(%rsp), %rax
movq 8(%rax), %rsi
.Ltmp12:
movq %rbx, %rdi
callq _ZN3ops5Graph8compiledEPNS_2OpE
.Ltmp13:
# %bb.4:
movq %rax, %r13
movq %rbx, 128(%rsp) # 8-byte Spill
movq 40(%rsp), %rdi
testq %rdi, %rdi
je .LBB1_6
# %bb.5:
callq _ZdlPv
.LBB1_6: # %_ZNSt6vectorIPN3ops2OpESaIS2_EED2Ev.exit40
leaq 64(%r12), %rbx
movq %rbx, %rdi
xorl %esi, %esi
callq _ZNK3ops5ShapeixEm
movl %eax, %ebp
movl $1, %esi
movq %rbx, %rdi
callq _ZNK3ops5ShapeixEm
movl %eax, %ebx
xorps %xmm0, %xmm0
movaps %xmm0, 16(%rsp)
movq $0, 32(%rsp)
.Ltmp15:
leaq 40(%rsp), %rdi
leaq 16(%rsp), %rsi
callq _ZN3ops5ShapeC1ERKSt6vectorIiSaIiEE
.Ltmp16:
# %bb.7:
movq 16(%rsp), %rdi
testq %rdi, %rdi
je .LBB1_9
# %bb.8:
callq _ZdlPv
.LBB1_9: # %_ZNSt6vectorIiSaIiEED2Ev.exit
.Ltmp18:
movq %r14, 136(%rsp) # 8-byte Spill
movl $1, %edi
callq _Z12tensor_allocm
movq %rax, 144(%rsp) # 8-byte Spill
.Ltmp19:
# %bb.10:
movq 88(%r12), %r14
movq 88(%r13), %r15
movq 56(%r12), %r12
movq 56(%r13), %r13
xorps %xmm0, %xmm0
movaps %xmm0, 16(%rsp)
movq $0, 32(%rsp)
.Ltmp21:
movl $16, %edi
callq _Znwm
.Ltmp22:
# %bb.11: # %_ZNSt6vectorIPN2rt4NodeESaIS2_EEC2ESt16initializer_listIS2_ERKS3_.exit
movslq %ebp, %rcx
movslq %ebx, %r8
movq %rax, 16(%rsp)
movq %rax, %rdx
addq $16, %rdx
movq %rdx, 32(%rsp)
movq %r12, (%rax)
movq %r13, 8(%rax)
movq %rdx, 24(%rsp)
.Ltmp24:
leaq 16(%rsp), %r9
movq %r14, %rdi
movq %r15, %rsi
movq 144(%rsp), %r14 # 8-byte Reload
movq %r14, %rdx
callq _ZN2rt4Node6op_mseEPKfS2_PfmmRKSt6vectorIPS0_SaIS5_EE
.Ltmp25:
# %bb.12:
movq %rax, %r12
movq 16(%rsp), %rdi
testq %rdi, %rdi
movq 136(%rsp), %rbx # 8-byte Reload
je .LBB1_14
# %bb.13:
callq _ZdlPv
.LBB1_14: # %_ZNSt6vectorIPN2rt4NodeESaIS2_EED2Ev.exit
xorps %xmm0, %xmm0
movaps %xmm0, 96(%rsp)
movq $0, 112(%rsp)
.Ltmp27:
movl $8, %edi
callq _Znwm
.Ltmp28:
# %bb.15: # %_ZNSt6vectorIPN2rt4NodeESaIS2_EEC2ESt16initializer_listIS2_ERKS3_.exit48
movq %rax, 96(%rsp)
movq %rax, %rcx
addq $8, %rcx
movq %rcx, 112(%rsp)
movq %r12, (%rax)
movq %rcx, 104(%rsp)
xorps %xmm0, %xmm0
movaps %xmm0, 64(%rsp)
movq $0, 80(%rsp)
.Ltmp30:
movl $8, %edi
callq _Znwm
.Ltmp31:
# %bb.16: # %_ZNSt6vectorIPfSaIS0_EEC2ESt16initializer_listIS0_ERKS1_.exit
movq %rax, 64(%rsp)
movq %rax, %rcx
addq $8, %rcx
movq %rcx, 80(%rsp)
movq %r14, (%rax)
movq %rcx, 72(%rsp)
.Ltmp33:
movq %r14, (%rsp)
leaq 96(%rsp), %rdx
leaq 64(%rsp), %rcx
leaq 40(%rsp), %r9
movq 128(%rsp), %rdi # 8-byte Reload
movq %rbx, %rsi
movq %r12, %r8
callq _ZN3ops5Graph12add_compiledEPNS_2OpESt6vectorIPN2rt4NodeESaIS6_EES3_IPfSaIS9_EES6_RKNS_5ShapeES9_
.Ltmp34:
# %bb.17:
movq 64(%rsp), %rdi
testq %rdi, %rdi
je .LBB1_19
# %bb.18:
callq _ZdlPv
.LBB1_19: # %_ZNSt6vectorIPfSaIS0_EED2Ev.exit
movq 96(%rsp), %rdi
testq %rdi, %rdi
je .LBB1_21
# %bb.20:
callq _ZdlPv
.LBB1_21: # %_ZNSt6vectorIPN2rt4NodeESaIS2_EED2Ev.exit56
movq 40(%rsp), %rdi
testq %rdi, %rdi
je .LBB1_23
# %bb.22:
callq _ZdlPv
.LBB1_23: # %_ZN3ops5ShapeD2Ev.exit
addq $152, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_24:
.cfi_def_cfa_offset 208
.Ltmp35:
jmp .LBB1_26
.LBB1_25:
.Ltmp32:
.LBB1_26:
movq %rax, %rbx
movq 64(%rsp), %rdi
testq %rdi, %rdi
je .LBB1_29
# %bb.27: # %.body50.sink.split
callq _ZdlPv
jmp .LBB1_29
.LBB1_28:
.Ltmp29:
movq %rax, %rbx
.LBB1_29: # %.body50
movq 96(%rsp), %rdi
jmp .LBB1_33
.LBB1_30:
.Ltmp26:
jmp .LBB1_32
.LBB1_31:
.Ltmp23:
.LBB1_32:
movq %rax, %rbx
movq 16(%rsp), %rdi
.LBB1_33: # %.body50
testq %rdi, %rdi
je .LBB1_40
# %bb.34:
callq _ZdlPv
jmp .LBB1_40
.LBB1_35:
.Ltmp20:
jmp .LBB1_39
.LBB1_36:
.Ltmp17:
movq %rax, %rbx
movq 16(%rsp), %rdi
jmp .LBB1_41
.LBB1_37:
.Ltmp14:
jmp .LBB1_39
.LBB1_38:
.Ltmp11:
.LBB1_39: # %.body46
movq %rax, %rbx
.LBB1_40: # %.body46
movq 40(%rsp), %rdi
.LBB1_41: # %.body46
testq %rdi, %rdi
je .LBB1_43
# %bb.42:
callq _ZdlPv
.LBB1_43:
movq %rbx, %rdi
callq _Unwind_Resume@PLT
.Lfunc_end1:
.size _ZN3ops3MSE7compileEv, .Lfunc_end1-_ZN3ops3MSE7compileEv
.cfi_endproc
.section .gcc_except_table,"a",@progbits
.p2align 2, 0x0
GCC_except_table1:
.Lexception1:
.byte 255 # @LPStart Encoding = omit
.byte 255 # @TType Encoding = omit
.byte 1 # Call site Encoding = uleb128
.uleb128 .Lcst_end1-.Lcst_begin1
.Lcst_begin1:
.uleb128 .Lfunc_begin1-.Lfunc_begin1 # >> Call Site 1 <<
.uleb128 .Ltmp9-.Lfunc_begin1 # Call between .Lfunc_begin1 and .Ltmp9
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp9-.Lfunc_begin1 # >> Call Site 2 <<
.uleb128 .Ltmp10-.Ltmp9 # Call between .Ltmp9 and .Ltmp10
.uleb128 .Ltmp11-.Lfunc_begin1 # jumps to .Ltmp11
.byte 0 # On action: cleanup
.uleb128 .Ltmp10-.Lfunc_begin1 # >> Call Site 3 <<
.uleb128 .Ltmp12-.Ltmp10 # Call between .Ltmp10 and .Ltmp12
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp12-.Lfunc_begin1 # >> Call Site 4 <<
.uleb128 .Ltmp13-.Ltmp12 # Call between .Ltmp12 and .Ltmp13
.uleb128 .Ltmp14-.Lfunc_begin1 # jumps to .Ltmp14
.byte 0 # On action: cleanup
.uleb128 .Ltmp13-.Lfunc_begin1 # >> Call Site 5 <<
.uleb128 .Ltmp15-.Ltmp13 # Call between .Ltmp13 and .Ltmp15
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp15-.Lfunc_begin1 # >> Call Site 6 <<
.uleb128 .Ltmp16-.Ltmp15 # Call between .Ltmp15 and .Ltmp16
.uleb128 .Ltmp17-.Lfunc_begin1 # jumps to .Ltmp17
.byte 0 # On action: cleanup
.uleb128 .Ltmp18-.Lfunc_begin1 # >> Call Site 7 <<
.uleb128 .Ltmp19-.Ltmp18 # Call between .Ltmp18 and .Ltmp19
.uleb128 .Ltmp20-.Lfunc_begin1 # jumps to .Ltmp20
.byte 0 # On action: cleanup
.uleb128 .Ltmp21-.Lfunc_begin1 # >> Call Site 8 <<
.uleb128 .Ltmp22-.Ltmp21 # Call between .Ltmp21 and .Ltmp22
.uleb128 .Ltmp23-.Lfunc_begin1 # jumps to .Ltmp23
.byte 0 # On action: cleanup
.uleb128 .Ltmp24-.Lfunc_begin1 # >> Call Site 9 <<
.uleb128 .Ltmp25-.Ltmp24 # Call between .Ltmp24 and .Ltmp25
.uleb128 .Ltmp26-.Lfunc_begin1 # jumps to .Ltmp26
.byte 0 # On action: cleanup
.uleb128 .Ltmp27-.Lfunc_begin1 # >> Call Site 10 <<
.uleb128 .Ltmp28-.Ltmp27 # Call between .Ltmp27 and .Ltmp28
.uleb128 .Ltmp29-.Lfunc_begin1 # jumps to .Ltmp29
.byte 0 # On action: cleanup
.uleb128 .Ltmp30-.Lfunc_begin1 # >> Call Site 11 <<
.uleb128 .Ltmp31-.Ltmp30 # Call between .Ltmp30 and .Ltmp31
.uleb128 .Ltmp32-.Lfunc_begin1 # jumps to .Ltmp32
.byte 0 # On action: cleanup
.uleb128 .Ltmp33-.Lfunc_begin1 # >> Call Site 12 <<
.uleb128 .Ltmp34-.Ltmp33 # Call between .Ltmp33 and .Ltmp34
.uleb128 .Ltmp35-.Lfunc_begin1 # jumps to .Ltmp35
.byte 0 # On action: cleanup
.uleb128 .Ltmp34-.Lfunc_begin1 # >> Call Site 13 <<
.uleb128 .Lfunc_end1-.Ltmp34 # Call between .Ltmp34 and .Lfunc_end1
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.Lcst_end1:
.p2align 2, 0x0
# -- End function
.text
.globl _ZN3ops3MSE10child_gradEmPNS_2OpE # -- Begin function _ZN3ops3MSE10child_gradEmPNS_2OpE
.p2align 4, 0x90
.type _ZN3ops3MSE10child_gradEmPNS_2OpE,@function
_ZN3ops3MSE10child_gradEmPNS_2OpE: # @_ZN3ops3MSE10child_gradEmPNS_2OpE
.Lfunc_begin2:
.cfi_startproc
.cfi_personality 3, __gxx_personality_v0
.cfi_lsda 3, .Lexception2
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $48, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
testq %rsi, %rsi
je .LBB2_1
# %bb.5:
testq %rdx, %rdx
jne .LBB2_6
# %bb.8:
movq %rdi, %rbx
callq _ZN3ops10OpsBuilder8instanceEv
movq %rax, %r14
leaq 24(%rsp), %rdi
movq %rbx, %rsi
callq _ZN3ops2Op5predsEv
movq 24(%rsp), %rax
movq (%rax), %r15
.Ltmp39:
movq %rsp, %rdi
movq %rbx, %rsi
callq _ZN3ops2Op5predsEv
.Ltmp40:
# %bb.9:
movq (%rsp), %rax
movq 8(%rax), %rdx
.Ltmp42:
movq %r14, %rdi
movq %r15, %rsi
callq _ZN3ops10OpsBuilder8mse_gradEPNS_2OpES2_
.Ltmp43:
# %bb.10:
movq %rax, %rbx
movq (%rsp), %rdi
testq %rdi, %rdi
je .LBB2_12
# %bb.11:
callq _ZdlPv
.LBB2_12: # %_ZNSt6vectorIPN3ops2OpESaIS2_EED2Ev.exit
movq 24(%rsp), %rdi
testq %rdi, %rdi
je .LBB2_14
# %bb.13:
callq _ZdlPv
.LBB2_14: # %_ZNSt6vectorIPN3ops2OpESaIS2_EED2Ev.exit11
movq %rbx, %rax
addq $48, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB2_1:
.cfi_def_cfa_offset 80
movl $16, %edi
callq __cxa_allocate_exception
movq %rax, %r14
.Ltmp45:
movl $.L.str.1, %esi
movq %rax, %rdi
callq _ZNSt13runtime_errorC1EPKc
.Ltmp46:
jmp .LBB2_2
.LBB2_6:
movl $16, %edi
callq __cxa_allocate_exception
movq %rax, %r14
.Ltmp36:
movl $.L.str.2, %esi
movq %rax, %rdi
callq _ZNSt13runtime_errorC1EPKc
.Ltmp37:
.LBB2_2:
movl $_ZTISt13runtime_error, %esi
movl $_ZNSt13runtime_errorD1Ev, %edx
movq %r14, %rdi
callq __cxa_throw
.LBB2_7:
.Ltmp38:
jmp .LBB2_4
.LBB2_3:
.Ltmp47:
.LBB2_4:
movq %rax, %rbx
movq %r14, %rdi
callq __cxa_free_exception
movq %rbx, %rdi
callq _Unwind_Resume@PLT
.LBB2_16:
.Ltmp44:
movq %rax, %rbx
movq (%rsp), %rdi
testq %rdi, %rdi
je .LBB2_18
# %bb.17:
callq _ZdlPv
jmp .LBB2_18
.LBB2_15:
.Ltmp41:
movq %rax, %rbx
.LBB2_18: # %_ZNSt6vectorIPN3ops2OpESaIS2_EED2Ev.exit13
movq 24(%rsp), %rdi
testq %rdi, %rdi
je .LBB2_20
# %bb.19:
callq _ZdlPv
.LBB2_20:
movq %rbx, %rdi
callq _Unwind_Resume@PLT
.Lfunc_end2:
.size _ZN3ops3MSE10child_gradEmPNS_2OpE, .Lfunc_end2-_ZN3ops3MSE10child_gradEmPNS_2OpE
.cfi_endproc
.section .gcc_except_table,"a",@progbits
.p2align 2, 0x0
GCC_except_table2:
.Lexception2:
.byte 255 # @LPStart Encoding = omit
.byte 255 # @TType Encoding = omit
.byte 1 # Call site Encoding = uleb128
.uleb128 .Lcst_end2-.Lcst_begin2
.Lcst_begin2:
.uleb128 .Lfunc_begin2-.Lfunc_begin2 # >> Call Site 1 <<
.uleb128 .Ltmp39-.Lfunc_begin2 # Call between .Lfunc_begin2 and .Ltmp39
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp39-.Lfunc_begin2 # >> Call Site 2 <<
.uleb128 .Ltmp40-.Ltmp39 # Call between .Ltmp39 and .Ltmp40
.uleb128 .Ltmp41-.Lfunc_begin2 # jumps to .Ltmp41
.byte 0 # On action: cleanup
.uleb128 .Ltmp42-.Lfunc_begin2 # >> Call Site 3 <<
.uleb128 .Ltmp43-.Ltmp42 # Call between .Ltmp42 and .Ltmp43
.uleb128 .Ltmp44-.Lfunc_begin2 # jumps to .Ltmp44
.byte 0 # On action: cleanup
.uleb128 .Ltmp43-.Lfunc_begin2 # >> Call Site 4 <<
.uleb128 .Ltmp45-.Ltmp43 # Call between .Ltmp43 and .Ltmp45
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp45-.Lfunc_begin2 # >> Call Site 5 <<
.uleb128 .Ltmp46-.Ltmp45 # Call between .Ltmp45 and .Ltmp46
.uleb128 .Ltmp47-.Lfunc_begin2 # jumps to .Ltmp47
.byte 0 # On action: cleanup
.uleb128 .Ltmp46-.Lfunc_begin2 # >> Call Site 6 <<
.uleb128 .Ltmp36-.Ltmp46 # Call between .Ltmp46 and .Ltmp36
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp36-.Lfunc_begin2 # >> Call Site 7 <<
.uleb128 .Ltmp37-.Ltmp36 # Call between .Ltmp36 and .Ltmp37
.uleb128 .Ltmp38-.Lfunc_begin2 # jumps to .Ltmp38
.byte 0 # On action: cleanup
.uleb128 .Ltmp37-.Lfunc_begin2 # >> Call Site 8 <<
.uleb128 .Lfunc_end2-.Ltmp37 # Call between .Ltmp37 and .Lfunc_end2
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.Lcst_end2:
.p2align 2, 0x0
# -- End function
.section .text._ZN3ops2OpD2Ev,"axG",@progbits,_ZN3ops2OpD2Ev,comdat
.weak _ZN3ops2OpD2Ev # -- Begin function _ZN3ops2OpD2Ev
.p2align 4, 0x90
.type _ZN3ops2OpD2Ev,@function
_ZN3ops2OpD2Ev: # @_ZN3ops2OpD2Ev
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
movq %rdi, %rbx
movq $_ZTVN3ops2OpE+16, (%rdi)
movq 88(%rdi), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
callq _ZdlPv
.LBB3_2: # %_ZNSt6vectorIPN3ops2OpESaIS2_EED2Ev.exit
movq 64(%rbx), %rdi
testq %rdi, %rdi
je .LBB3_4
# %bb.3:
callq _ZdlPv
.LBB3_4: # %_ZNSt6vectorIPN3ops2OpESaIS2_EED2Ev.exit2
movq 40(%rbx), %rdi
testq %rdi, %rdi
je .LBB3_6
# %bb.5:
callq _ZdlPv
.LBB3_6: # %_ZN3ops5ShapeD2Ev.exit
movq 8(%rbx), %rdi
addq $24, %rbx
cmpq %rbx, %rdi
je .LBB3_7
# %bb.8: # %.critedge.i.i
popq %rbx
.cfi_def_cfa_offset 8
jmp _ZdlPv # TAILCALL
.LBB3_7: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size _ZN3ops2OpD2Ev, .Lfunc_end3-_ZN3ops2OpD2Ev
.cfi_endproc
# -- End function
.section .text._ZN3ops3MSED0Ev,"axG",@progbits,_ZN3ops3MSED0Ev,comdat
.weak _ZN3ops3MSED0Ev # -- Begin function _ZN3ops3MSED0Ev
.p2align 4, 0x90
.type _ZN3ops3MSED0Ev,@function
_ZN3ops3MSED0Ev: # @_ZN3ops3MSED0Ev
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
movq %rdi, %rbx
movq $_ZTVN3ops2OpE+16, (%rdi)
movq 88(%rdi), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
callq _ZdlPv
.LBB4_2: # %_ZNSt6vectorIPN3ops2OpESaIS2_EED2Ev.exit.i
movq 64(%rbx), %rdi
testq %rdi, %rdi
je .LBB4_4
# %bb.3:
callq _ZdlPv
.LBB4_4: # %_ZNSt6vectorIPN3ops2OpESaIS2_EED2Ev.exit2.i
movq 40(%rbx), %rdi
testq %rdi, %rdi
je .LBB4_6
# %bb.5:
callq _ZdlPv
.LBB4_6: # %_ZN3ops5ShapeD2Ev.exit.i
movq 8(%rbx), %rdi
leaq 24(%rbx), %rax
cmpq %rax, %rdi
je .LBB4_8
# %bb.7: # %.critedge.i.i.i
callq _ZdlPv
.LBB4_8: # %_ZN3ops2OpD2Ev.exit
movq %rbx, %rdi
popq %rbx
.cfi_def_cfa_offset 8
jmp _ZdlPv # TAILCALL
.Lfunc_end4:
.size _ZN3ops3MSED0Ev, .Lfunc_end4-_ZN3ops3MSED0Ev
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "mse"
.size .L.str, 4
.type _ZTVN3ops3MSEE,@object # @_ZTVN3ops3MSEE
.section .rodata,"a",@progbits
.globl _ZTVN3ops3MSEE
.p2align 3, 0x0
_ZTVN3ops3MSEE:
.quad 0
.quad _ZTIN3ops3MSEE
.quad _ZN3ops2OpD2Ev
.quad _ZN3ops3MSED0Ev
.quad _ZN3ops3MSE7compileEv
.quad _ZN3ops3MSE10child_gradEmPNS_2OpE
.size _ZTVN3ops3MSEE, 48
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "Can't compute gradient of MSE for y"
.size .L.str.1, 36
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "MSE must be the final node of the gradient"
.size .L.str.2, 43
.type _ZTSN3ops3MSEE,@object # @_ZTSN3ops3MSEE
.section .rodata,"a",@progbits
.globl _ZTSN3ops3MSEE
_ZTSN3ops3MSEE:
.asciz "N3ops3MSEE"
.size _ZTSN3ops3MSEE, 11
.type _ZTIN3ops3MSEE,@object # @_ZTIN3ops3MSEE
.globl _ZTIN3ops3MSEE
.p2align 3, 0x0
_ZTIN3ops3MSEE:
.quad _ZTVN10__cxxabiv120__si_class_type_infoE+16
.quad _ZTSN3ops3MSEE
.quad _ZTIN3ops2OpE
.size _ZTIN3ops3MSEE, 24
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.globl _ZN3ops3MSEC1EPNS_2OpES2_
.type _ZN3ops3MSEC1EPNS_2OpES2_,@function
.set _ZN3ops3MSEC1EPNS_2OpES2_, _ZN3ops3MSEC2EPNS_2OpES2_
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __gxx_personality_v0
.addrsig_sym _Unwind_Resume
.addrsig_sym _ZTISt13runtime_error
.addrsig_sym _ZTVN10__cxxabiv120__si_class_type_infoE
.addrsig_sym _ZTSN3ops3MSEE
.addrsig_sym _ZTIN3ops2OpE
.addrsig_sym _ZTIN3ops3MSEE
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
// Use this as the random seed in the pseudorandom function (see instructions)
#define SEED 20210418
// Pseudo-random number generator. This provides consistent reproducible results so that
// you can test your program.
__device__ float pseudorandom( uint x ) {
uint value = x;
value = (value ^ 61) ^ (value>>16);
value *= 9;
value ^= value << 4;
value *= 0x27d4eb2d;
value ^= value >> 15;
return (float) value / (float) INT_MAX;
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
// Use this as the random seed in the pseudorandom function (see instructions)
#define SEED 20210418
// Pseudo-random number generator. This provides consistent reproducible results so that
// you can test your program.
__device__ float pseudorandom( uint x ) {
uint value = x;
value = (value ^ 61) ^ (value>>16);
value *= 9;
value ^= value << 4;
value *= 0x27d4eb2d;
value ^= value >> 15;
return (float) value / (float) INT_MAX;
} | .file "tmpxft_000ba2cc_00000000-6_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z12pseudorandomj
.type _Z12pseudorandomj, @function
_Z12pseudorandomj:
.LFB2057:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size _Z12pseudorandomj, .-_Z12pseudorandomj
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
// Use this as the random seed in the pseudorandom function (see instructions)
#define SEED 20210418
// Pseudo-random number generator. This provides consistent reproducible results so that
// you can test your program.
__device__ float pseudorandom( uint x ) {
uint value = x;
value = (value ^ 61) ^ (value>>16);
value *= 9;
value ^= value << 4;
value *= 0x27d4eb2d;
value ^= value >> 15;
return (float) value / (float) INT_MAX;
} | #include <hip/hip_runtime.h>
#include <stdio.h>
// Use this as the random seed in the pseudorandom function (see instructions)
#define SEED 20210418
// Pseudo-random number generator. This provides consistent reproducible results so that
// you can test your program.
__device__ float pseudorandom( uint x ) {
uint value = x;
value = (value ^ 61) ^ (value>>16);
value *= 9;
value ^= value << 4;
value *= 0x27d4eb2d;
value ^= value >> 15;
return (float) value / (float) INT_MAX;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
// Use this as the random seed in the pseudorandom function (see instructions)
#define SEED 20210418
// Pseudo-random number generator. This provides consistent reproducible results so that
// you can test your program.
__device__ float pseudorandom( uint x ) {
uint value = x;
value = (value ^ 61) ^ (value>>16);
value *= 9;
value ^= value << 4;
value *= 0x27d4eb2d;
value ^= value >> 15;
return (float) value / (float) INT_MAX;
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
// Use this as the random seed in the pseudorandom function (see instructions)
#define SEED 20210418
// Pseudo-random number generator. This provides consistent reproducible results so that
// you can test your program.
__device__ float pseudorandom( uint x ) {
uint value = x;
value = (value ^ 61) ^ (value>>16);
value *= 9;
value ^= value << 4;
value *= 0x27d4eb2d;
value ^= value >> 15;
return (float) value / (float) INT_MAX;
} | .text
.file "kernel.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000ba2cc_00000000-6_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z12pseudorandomj
.type _Z12pseudorandomj, @function
_Z12pseudorandomj:
.LFB2057:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size _Z12pseudorandomj, .-_Z12pseudorandomj
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "kernel.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void uniformAdd(int *g_data, int *uniforms, int n, int blockOffset, int baseIndex)
{
__shared__ int uni;
if (threadIdx.x == 0)
uni = uniforms[blockIdx.x + blockOffset];
unsigned int address = __mul24(blockIdx.x, (blockDim.x << 1)) + baseIndex + threadIdx.x;
__syncthreads();
// note two adds per thread
g_data[address] += uni;
g_data[address + blockDim.x] += (threadIdx.x + blockDim.x < n) * uni;
} | code for sm_80
Function : _Z10uniformAddPiS_iii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R11, SR_TID.X ; /* 0x00000000000b7919 */
/* 0x000e220000002100 */
/*0020*/ IMAD.MOV.U32 R13, RZ, RZ, 0x4 ; /* 0x00000004ff0d7424 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e620000002500 */
/*0050*/ ISETP.NE.AND P0, PT, R11, RZ, PT ; /* 0x000000ff0b00720c */
/* 0x001fda0003f05270 */
/*0060*/ @!P0 IADD3 R2, R4, c[0x0][0x174], RZ ; /* 0x00005d0004028a10 */
/* 0x002fca0007ffe0ff */
/*0070*/ @!P0 IMAD.WIDE.U32 R2, R2, R13, c[0x0][0x168] ; /* 0x00005a0002028625 */
/* 0x000fca00078e000d */
/*0080*/ @!P0 LDG.E R0, [R2.64] ; /* 0x0000000602008981 */
/* 0x000ea2000c1e1900 */
/*0090*/ ULDC UR4, c[0x0][0x0] ; /* 0x0000000000047ab9 */
/* 0x000fe20000000800 */
/*00a0*/ SHF.L.U32 R4, R4, 0x8, RZ ; /* 0x0000000804047819 */
/* 0x000fe200000006ff */
/*00b0*/ USHF.L.U32 UR4, UR4, 0x9, URZ ; /* 0x0000000904047899 */
/* 0x000fc6000800063f */
/*00c0*/ SHF.R.S32.HI R4, RZ, 0x8, R4 ; /* 0x00000008ff047819 */
/* 0x000fe20000011404 */
/*00d0*/ USHF.R.S32.HI UR4, URZ, 0x8, UR4 ; /* 0x000000083f047899 */
/* 0x000fcc0008011404 */
/*00e0*/ IMAD R4, R4, UR4, R11 ; /* 0x0000000404047c24 */
/* 0x000fca000f8e020b */
/*00f0*/ IADD3 R6, R4, c[0x0][0x178], RZ ; /* 0x00005e0004067a10 */
/* 0x000fca0007ffe0ff */
/*0100*/ IMAD.WIDE.U32 R4, R6.reuse, R13, c[0x0][0x160] ; /* 0x0000580006047625 */
/* 0x040fe200078e000d */
/*0110*/ @!P0 STS [RZ], R0 ; /* 0x00000000ff008388 */
/* 0x004fe80000000800 */
/*0120*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0130*/ LDG.E R2, [R4.64] ; /* 0x0000000604027981 */
/* 0x000ea2000c1e1900 */
/*0140*/ IADD3 R3, R6, c[0x0][0x0], RZ ; /* 0x0000000006037a10 */
/* 0x000fc60007ffe0ff */
/*0150*/ LDS R7, [RZ] ; /* 0x00000000ff077984 */
/* 0x000ea20000000800 */
/*0160*/ IADD3 R6, R11, c[0x0][0x0], RZ ; /* 0x000000000b067a10 */
/* 0x000fe20007ffe0ff */
/*0170*/ IMAD.IADD R9, R2, 0x1, R7 ; /* 0x0000000102097824 */
/* 0x004fe400078e0207 */
/*0180*/ IMAD.WIDE.U32 R2, R3, R13, c[0x0][0x160] ; /* 0x0000580003027625 */
/* 0x000fc600078e000d */
/*0190*/ STG.E [R4.64], R9 ; /* 0x0000000904007986 */
/* 0x000fe8000c101906 */
/*01a0*/ LDG.E R8, [R2.64] ; /* 0x0000000602087981 */
/* 0x000ea2000c1e1900 */
/*01b0*/ ISETP.GE.U32.AND P0, PT, R6, c[0x0][0x170], PT ; /* 0x00005c0006007a0c */
/* 0x000fc80003f06070 */
/*01c0*/ SEL R7, R7, RZ, !P0 ; /* 0x000000ff07077207 */
/* 0x000fc80004000000 */
/*01d0*/ IADD3 R7, R7, R8, RZ ; /* 0x0000000807077210 */
/* 0x004fca0007ffe0ff */
/*01e0*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x000fe2000c101906 */
/*01f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0200*/ BRA 0x200; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void uniformAdd(int *g_data, int *uniforms, int n, int blockOffset, int baseIndex)
{
__shared__ int uni;
if (threadIdx.x == 0)
uni = uniforms[blockIdx.x + blockOffset];
unsigned int address = __mul24(blockIdx.x, (blockDim.x << 1)) + baseIndex + threadIdx.x;
__syncthreads();
// note two adds per thread
g_data[address] += uni;
g_data[address + blockDim.x] += (threadIdx.x + blockDim.x < n) * uni;
} | .file "tmpxft_001487f5_00000000-6_uniformAdd.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z35__device_stub__Z10uniformAddPiS_iiiPiS_iii
.type _Z35__device_stub__Z10uniformAddPiS_iiiPiS_iii, @function
_Z35__device_stub__Z10uniformAddPiS_iiiPiS_iii:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z10uniformAddPiS_iii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z35__device_stub__Z10uniformAddPiS_iiiPiS_iii, .-_Z35__device_stub__Z10uniformAddPiS_iiiPiS_iii
.globl _Z10uniformAddPiS_iii
.type _Z10uniformAddPiS_iii, @function
_Z10uniformAddPiS_iii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z10uniformAddPiS_iiiPiS_iii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z10uniformAddPiS_iii, .-_Z10uniformAddPiS_iii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z10uniformAddPiS_iii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z10uniformAddPiS_iii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void uniformAdd(int *g_data, int *uniforms, int n, int blockOffset, int baseIndex)
{
__shared__ int uni;
if (threadIdx.x == 0)
uni = uniforms[blockIdx.x + blockOffset];
unsigned int address = __mul24(blockIdx.x, (blockDim.x << 1)) + baseIndex + threadIdx.x;
__syncthreads();
// note two adds per thread
g_data[address] += uni;
g_data[address + blockDim.x] += (threadIdx.x + blockDim.x < n) * uni;
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void uniformAdd(int *g_data, int *uniforms, int n, int blockOffset, int baseIndex)
{
__shared__ int uni;
if (threadIdx.x == 0)
uni = uniforms[blockIdx.x + blockOffset];
unsigned int address = __mul24(blockIdx.x, (blockDim.x << 1)) + baseIndex + threadIdx.x;
__syncthreads();
// note two adds per thread
g_data[address] += uni;
g_data[address + blockDim.x] += (threadIdx.x + blockDim.x < n) * uni;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void uniformAdd(int *g_data, int *uniforms, int n, int blockOffset, int baseIndex)
{
__shared__ int uni;
if (threadIdx.x == 0)
uni = uniforms[blockIdx.x + blockOffset];
unsigned int address = __mul24(blockIdx.x, (blockDim.x << 1)) + baseIndex + threadIdx.x;
__syncthreads();
// note two adds per thread
g_data[address] += uni;
g_data[address + blockDim.x] += (threadIdx.x + blockDim.x < n) * uni;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10uniformAddPiS_iii
.globl _Z10uniformAddPiS_iii
.p2align 8
.type _Z10uniformAddPiS_iii,@function
_Z10uniformAddPiS_iii:
s_mov_b32 s3, 0
s_mov_b32 s4, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_2
s_clause 0x1
s_load_b32 s2, s[0:1], 0x14
s_load_b64 s[6:7], s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_add_i32 s2, s15, s2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_lshl_b64 s[2:3], s[2:3], 2
s_add_u32 s2, s6, s2
s_addc_u32 s3, s7, s3
s_load_b32 s2, s[2:3], 0x0
s_waitcnt lgkmcnt(0)
v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v2, s2
ds_store_b32 v1, v2
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s4
s_clause 0x2
s_load_b32 s4, s[0:1], 0x2c
s_load_b32 s5, s[0:1], 0x18
s_load_b64 s[2:3], s[0:1], 0x0
s_lshl_b32 s6, s15, 8
s_waitcnt lgkmcnt(0)
s_ashr_i32 s6, s6, 7
s_barrier
buffer_gl0_inv
v_mov_b32_e32 v6, 0
s_load_b32 s0, s[0:1], 0x10
ds_load_b32 v6, v6
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s6, s6, s4
v_add3_u32 v1, s6, s5, v0
v_mov_b32_e32 v2, 0
v_add_nc_u32_e32 v0, s4, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[1:2]
v_add_nc_u32_e32 v1, s4, v1
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v3, vcc_lo, s2, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_3)
v_add_co_u32 v1, vcc_lo, s2, v1
global_load_b32 v5, v[3:4], off
v_add_co_ci_u32_e32 v2, vcc_lo, s3, v2, vcc_lo
s_waitcnt lgkmcnt(0)
v_cmp_gt_u32_e32 vcc_lo, s0, v0
v_cndmask_b32_e32 v0, 0, v6, vcc_lo
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v5, v5, v6
global_store_b32 v[3:4], v5, off
global_load_b32 v3, v[1:2], off
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v0, v3, v0
global_store_b32 v[1:2], v0, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10uniformAddPiS_iii
.amdhsa_group_segment_fixed_size 4
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10uniformAddPiS_iii, .Lfunc_end0-_Z10uniformAddPiS_iii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 4
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10uniformAddPiS_iii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z10uniformAddPiS_iii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void uniformAdd(int *g_data, int *uniforms, int n, int blockOffset, int baseIndex)
{
__shared__ int uni;
if (threadIdx.x == 0)
uni = uniforms[blockIdx.x + blockOffset];
unsigned int address = __mul24(blockIdx.x, (blockDim.x << 1)) + baseIndex + threadIdx.x;
__syncthreads();
// note two adds per thread
g_data[address] += uni;
g_data[address + blockDim.x] += (threadIdx.x + blockDim.x < n) * uni;
} | .text
.file "uniformAdd.hip"
.globl _Z25__device_stub__uniformAddPiS_iii # -- Begin function _Z25__device_stub__uniformAddPiS_iii
.p2align 4, 0x90
.type _Z25__device_stub__uniformAddPiS_iii,@function
_Z25__device_stub__uniformAddPiS_iii: # @_Z25__device_stub__uniformAddPiS_iii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10uniformAddPiS_iii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z25__device_stub__uniformAddPiS_iii, .Lfunc_end0-_Z25__device_stub__uniformAddPiS_iii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10uniformAddPiS_iii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10uniformAddPiS_iii,@object # @_Z10uniformAddPiS_iii
.section .rodata,"a",@progbits
.globl _Z10uniformAddPiS_iii
.p2align 3, 0x0
_Z10uniformAddPiS_iii:
.quad _Z25__device_stub__uniformAddPiS_iii
.size _Z10uniformAddPiS_iii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z10uniformAddPiS_iii"
.size .L__unnamed_1, 22
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__uniformAddPiS_iii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10uniformAddPiS_iii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z10uniformAddPiS_iii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R11, SR_TID.X ; /* 0x00000000000b7919 */
/* 0x000e220000002100 */
/*0020*/ IMAD.MOV.U32 R13, RZ, RZ, 0x4 ; /* 0x00000004ff0d7424 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e620000002500 */
/*0050*/ ISETP.NE.AND P0, PT, R11, RZ, PT ; /* 0x000000ff0b00720c */
/* 0x001fda0003f05270 */
/*0060*/ @!P0 IADD3 R2, R4, c[0x0][0x174], RZ ; /* 0x00005d0004028a10 */
/* 0x002fca0007ffe0ff */
/*0070*/ @!P0 IMAD.WIDE.U32 R2, R2, R13, c[0x0][0x168] ; /* 0x00005a0002028625 */
/* 0x000fca00078e000d */
/*0080*/ @!P0 LDG.E R0, [R2.64] ; /* 0x0000000602008981 */
/* 0x000ea2000c1e1900 */
/*0090*/ ULDC UR4, c[0x0][0x0] ; /* 0x0000000000047ab9 */
/* 0x000fe20000000800 */
/*00a0*/ SHF.L.U32 R4, R4, 0x8, RZ ; /* 0x0000000804047819 */
/* 0x000fe200000006ff */
/*00b0*/ USHF.L.U32 UR4, UR4, 0x9, URZ ; /* 0x0000000904047899 */
/* 0x000fc6000800063f */
/*00c0*/ SHF.R.S32.HI R4, RZ, 0x8, R4 ; /* 0x00000008ff047819 */
/* 0x000fe20000011404 */
/*00d0*/ USHF.R.S32.HI UR4, URZ, 0x8, UR4 ; /* 0x000000083f047899 */
/* 0x000fcc0008011404 */
/*00e0*/ IMAD R4, R4, UR4, R11 ; /* 0x0000000404047c24 */
/* 0x000fca000f8e020b */
/*00f0*/ IADD3 R6, R4, c[0x0][0x178], RZ ; /* 0x00005e0004067a10 */
/* 0x000fca0007ffe0ff */
/*0100*/ IMAD.WIDE.U32 R4, R6.reuse, R13, c[0x0][0x160] ; /* 0x0000580006047625 */
/* 0x040fe200078e000d */
/*0110*/ @!P0 STS [RZ], R0 ; /* 0x00000000ff008388 */
/* 0x004fe80000000800 */
/*0120*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0130*/ LDG.E R2, [R4.64] ; /* 0x0000000604027981 */
/* 0x000ea2000c1e1900 */
/*0140*/ IADD3 R3, R6, c[0x0][0x0], RZ ; /* 0x0000000006037a10 */
/* 0x000fc60007ffe0ff */
/*0150*/ LDS R7, [RZ] ; /* 0x00000000ff077984 */
/* 0x000ea20000000800 */
/*0160*/ IADD3 R6, R11, c[0x0][0x0], RZ ; /* 0x000000000b067a10 */
/* 0x000fe20007ffe0ff */
/*0170*/ IMAD.IADD R9, R2, 0x1, R7 ; /* 0x0000000102097824 */
/* 0x004fe400078e0207 */
/*0180*/ IMAD.WIDE.U32 R2, R3, R13, c[0x0][0x160] ; /* 0x0000580003027625 */
/* 0x000fc600078e000d */
/*0190*/ STG.E [R4.64], R9 ; /* 0x0000000904007986 */
/* 0x000fe8000c101906 */
/*01a0*/ LDG.E R8, [R2.64] ; /* 0x0000000602087981 */
/* 0x000ea2000c1e1900 */
/*01b0*/ ISETP.GE.U32.AND P0, PT, R6, c[0x0][0x170], PT ; /* 0x00005c0006007a0c */
/* 0x000fc80003f06070 */
/*01c0*/ SEL R7, R7, RZ, !P0 ; /* 0x000000ff07077207 */
/* 0x000fc80004000000 */
/*01d0*/ IADD3 R7, R7, R8, RZ ; /* 0x0000000807077210 */
/* 0x004fca0007ffe0ff */
/*01e0*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x000fe2000c101906 */
/*01f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0200*/ BRA 0x200; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10uniformAddPiS_iii
.globl _Z10uniformAddPiS_iii
.p2align 8
.type _Z10uniformAddPiS_iii,@function
_Z10uniformAddPiS_iii:
s_mov_b32 s3, 0
s_mov_b32 s4, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_2
s_clause 0x1
s_load_b32 s2, s[0:1], 0x14
s_load_b64 s[6:7], s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_add_i32 s2, s15, s2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_lshl_b64 s[2:3], s[2:3], 2
s_add_u32 s2, s6, s2
s_addc_u32 s3, s7, s3
s_load_b32 s2, s[2:3], 0x0
s_waitcnt lgkmcnt(0)
v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v2, s2
ds_store_b32 v1, v2
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s4
s_clause 0x2
s_load_b32 s4, s[0:1], 0x2c
s_load_b32 s5, s[0:1], 0x18
s_load_b64 s[2:3], s[0:1], 0x0
s_lshl_b32 s6, s15, 8
s_waitcnt lgkmcnt(0)
s_ashr_i32 s6, s6, 7
s_barrier
buffer_gl0_inv
v_mov_b32_e32 v6, 0
s_load_b32 s0, s[0:1], 0x10
ds_load_b32 v6, v6
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s6, s6, s4
v_add3_u32 v1, s6, s5, v0
v_mov_b32_e32 v2, 0
v_add_nc_u32_e32 v0, s4, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[1:2]
v_add_nc_u32_e32 v1, s4, v1
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v3, vcc_lo, s2, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_3)
v_add_co_u32 v1, vcc_lo, s2, v1
global_load_b32 v5, v[3:4], off
v_add_co_ci_u32_e32 v2, vcc_lo, s3, v2, vcc_lo
s_waitcnt lgkmcnt(0)
v_cmp_gt_u32_e32 vcc_lo, s0, v0
v_cndmask_b32_e32 v0, 0, v6, vcc_lo
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v5, v5, v6
global_store_b32 v[3:4], v5, off
global_load_b32 v3, v[1:2], off
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v0, v3, v0
global_store_b32 v[1:2], v0, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10uniformAddPiS_iii
.amdhsa_group_segment_fixed_size 4
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10uniformAddPiS_iii, .Lfunc_end0-_Z10uniformAddPiS_iii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 4
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10uniformAddPiS_iii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z10uniformAddPiS_iii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001487f5_00000000-6_uniformAdd.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z35__device_stub__Z10uniformAddPiS_iiiPiS_iii
.type _Z35__device_stub__Z10uniformAddPiS_iiiPiS_iii, @function
_Z35__device_stub__Z10uniformAddPiS_iiiPiS_iii:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z10uniformAddPiS_iii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z35__device_stub__Z10uniformAddPiS_iiiPiS_iii, .-_Z35__device_stub__Z10uniformAddPiS_iiiPiS_iii
.globl _Z10uniformAddPiS_iii
.type _Z10uniformAddPiS_iii, @function
_Z10uniformAddPiS_iii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z10uniformAddPiS_iiiPiS_iii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z10uniformAddPiS_iii, .-_Z10uniformAddPiS_iii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z10uniformAddPiS_iii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z10uniformAddPiS_iii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "uniformAdd.hip"
.globl _Z25__device_stub__uniformAddPiS_iii # -- Begin function _Z25__device_stub__uniformAddPiS_iii
.p2align 4, 0x90
.type _Z25__device_stub__uniformAddPiS_iii,@function
_Z25__device_stub__uniformAddPiS_iii: # @_Z25__device_stub__uniformAddPiS_iii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10uniformAddPiS_iii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z25__device_stub__uniformAddPiS_iii, .Lfunc_end0-_Z25__device_stub__uniformAddPiS_iii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10uniformAddPiS_iii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10uniformAddPiS_iii,@object # @_Z10uniformAddPiS_iii
.section .rodata,"a",@progbits
.globl _Z10uniformAddPiS_iii
.p2align 3, 0x0
_Z10uniformAddPiS_iii:
.quad _Z25__device_stub__uniformAddPiS_iii
.size _Z10uniformAddPiS_iii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z10uniformAddPiS_iii"
.size .L__unnamed_1, 22
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__uniformAddPiS_iii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10uniformAddPiS_iii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
/* 1-98番目までのテキスト。__ の部分を今の数字に、 ## の部分をひとつ減らした数字に置き換える */
__device__ char text[] = "__ bottles of beer on the wall, __ bottles of beer!\n"
"Take one down, and pass it around, ## bottles of beer on the wall!\n\n";
/* 99番目のテキスト。そのまま表示する */
__device__ char end[] =
"01 bottle of beer on the wall, 01 bottle of beer.\n"
"Take one down and pass it around, no more bottles of beer on the wall.\n"
"\n"
"No more bottles of beer on the wall, no more bottles of beer.\n"
"Go to the store and buy some more, 99 bottles of beer on the wall.";
#define SIZE_TEXT (sizeof(text)-1) /* 98番目までのテキストの長さ */
#define SIZE_END (sizeof(end)-1) /* 99番目のテキストの長さ */
__global__
void bottle99(char *addr)
{
/* スレッド ID(threadIdx.x) の取得 */
int x = threadIdx.x;
/* 結果の格納アドレスを求める */
addr += x * SIZE_TEXT;
/* 残りのボトル数を求める */
int bottle = 99 - x;
if (bottle == 1) {
/* 99番目, ボトルが無くなったのでendを表示 */
for (int i=0; i<SIZE_END; i++) {
addr[i] = end[i];
}
addr[SIZE_END] = '\0';
} else {
/* 1-98番目 */
/* 残りのボトル数のASCII表現 */
char c1 = (bottle/10) + '0';
char c2 = (bottle%10) + '0';
/* ひとつ減ったあとのボトル数のASCII表現 */
char d1 = ((bottle-1)/10) + '0';
char d2 = ((bottle-1)%10) + '0';
for (int i=0; i<SIZE_TEXT; i++) {
int c = text[i];
if (c == '_') {
/* '__' の置き換え */
addr[i] = c1;
addr[i+1] = c2;
i++;
} else if (c == '#') {
/* '##' の置き換え */
addr[i] = d1;
addr[i+1] = d2;
i++;
} else {
/* 文字列のコピー */
addr[i] = text[i];
}
}
}
}
int main()
{
char *buffer;
char *d_buffer;
/* 必要な領域を計算する */
int size = SIZE_TEXT * 98 + SIZE_END + 1;
buffer = new char[size];
cudaMalloc((void**)&d_buffer, size);
/* 99 bottles of beer を求めるために99個のスレッドを起動する */
bottle99<<<1, 99>>>(d_buffer);
/* 結果を取得 */
cudaMemcpy(buffer, d_buffer, size, cudaMemcpyDeviceToHost);
cudaFree(d_buffer);
/* 表示 */
puts(buffer);
free(buffer);
} | code for sm_80
Function : _Z8bottle99Pc
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R17, SR_TID.X ; /* 0x0000000000117919 */
/* 0x000e220000002100 */
/*0020*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*0030*/ IADD3 R0, -R17, 0x63, RZ ; /* 0x0000006311007810 */
/* 0x001fc80007ffe1ff */
/*0040*/ ISETP.NE.AND P0, PT, R0, 0x1, PT ; /* 0x000000010000780c */
/* 0x000fda0003f05270 */
/*0050*/ @!P0 BRA 0x2b0 ; /* 0x0000025000008947 */
/* 0x000fea0003800000 */
/*0060*/ IADD3 R4, R0.reuse, -0x1, RZ ; /* 0xffffffff00047810 */
/* 0x040fe20007ffe0ff */
/*0070*/ IMAD.HI R2, R0, 0x66666667, RZ ; /* 0x6666666700027827 */
/* 0x000fc800078e02ff */
/*0080*/ IMAD.HI R5, R4, 0x66666667, RZ ; /* 0x6666666704057827 */
/* 0x000fe200078e02ff */
/*0090*/ SHF.R.U32.HI R3, RZ, 0x1f, R2 ; /* 0x0000001fff037819 */
/* 0x000fc60000011602 */
/*00a0*/ IMAD.MOV.U32 R15, RZ, RZ, RZ ; /* 0x000000ffff0f7224 */
/* 0x000fe200078e00ff */
/*00b0*/ SHF.R.U32.HI R6, RZ, 0x1f, R5 ; /* 0x0000001fff067819 */
/* 0x000fe40000011605 */
/*00c0*/ LEA.HI.SX32 R3, R2, R3, 0x1e ; /* 0x0000000302037211 */
/* 0x000fe400078ff2ff */
/*00d0*/ LEA.HI.SX32 R5, R5, R6, 0x1e ; /* 0x0000000605057211 */
/* 0x000fe400078ff2ff */
/*00e0*/ IADD3 R7, R3.reuse, 0x30, RZ ; /* 0x0000003003077810 */
/* 0x040fe20007ffe0ff */
/*00f0*/ IMAD R0, R3, -0xa, R0 ; /* 0xfffffff603007824 */
/* 0x000fe200078e0200 */
/*0100*/ IADD3 R11, R5.reuse, 0x30, RZ ; /* 0x00000030050b7810 */
/* 0x040fe20007ffe0ff */
/*0110*/ IMAD R4, R5, -0xa, R4 ; /* 0xfffffff605047824 */
/* 0x000fc600078e0204 */
/*0120*/ IADD3 R9, R0, 0x30, RZ ; /* 0x0000003000097810 */
/* 0x000fe40007ffe0ff */
/*0130*/ IADD3 R13, R4, 0x30, RZ ; /* 0x00000030040d7810 */
/* 0x000fe40007ffe0ff */
/*0140*/ SHF.R.S32.HI R3, RZ, 0x1f, R15 ; /* 0x0000001fff037819 */
/* 0x001fe4000001140f */
/*0150*/ IADD3 R4, P0, R15, c[0x4][0x0], RZ ; /* 0x010000000f047a10 */
/* 0x000fc80007f1e0ff */
/*0160*/ IADD3.X R5, R3, c[0x4][0x4], RZ, P0, !PT ; /* 0x0100010003057a10 */
/* 0x000fcc00007fe4ff */
/*0170*/ LDG.E.U8 R5, [R4.64] ; /* 0x0000000604057981 */
/* 0x000ea2000c1e1100 */
/*0180*/ IMAD.MOV.U32 R2, RZ, RZ, R15 ; /* 0x000000ffff027224 */
/* 0x000fc800078e000f */
/*0190*/ IMAD.WIDE R2, R17, 0x78, R2 ; /* 0x0000007811027825 */
/* 0x000fca00078e0202 */
/*01a0*/ IADD3 R2, P1, R2, c[0x0][0x160], RZ ; /* 0x0000580002027a10 */
/* 0x000fc80007f3e0ff */
/*01b0*/ IADD3.X R3, R3, c[0x0][0x164], RZ, P1, !PT ; /* 0x0000590003037a10 */
/* 0x000fe40000ffe4ff */
/*01c0*/ ISETP.NE.AND P0, PT, R5, 0x5f, PT ; /* 0x0000005f0500780c */
/* 0x004fda0003f05270 */
/*01d0*/ @!P0 BRA 0x240 ; /* 0x0000006000008947 */
/* 0x000fea0003800000 */
/*01e0*/ ISETP.NE.AND P0, PT, R5, 0x23, PT ; /* 0x000000230500780c */
/* 0x000fda0003f05270 */
/*01f0*/ @P0 STG.E.U8 [R2.64], R5 ; /* 0x0000000502000986 */
/* 0x0001e2000c101106 */
/*0200*/ @!P0 IADD3 R15, R15, 0x1, RZ ; /* 0x000000010f0f8810 */
/* 0x000fc60007ffe0ff */
/*0210*/ @!P0 STG.E.U8 [R2.64+0x1], R13 ; /* 0x0000010d02008986 */
/* 0x0001e8000c101106 */
/*0220*/ @!P0 STG.E.U8 [R2.64], R11 ; /* 0x0000000b02008986 */
/* 0x0001e2000c101106 */
/*0230*/ BRA 0x270 ; /* 0x0000003000007947 */
/* 0x000fea0003800000 */
/*0240*/ STG.E.U8 [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x0001e2000c101106 */
/*0250*/ IADD3 R15, R15, 0x1, RZ ; /* 0x000000010f0f7810 */
/* 0x000fc60007ffe0ff */
/*0260*/ STG.E.U8 [R2.64+0x1], R9 ; /* 0x0000010902007986 */
/* 0x0001e8000c101106 */
/*0270*/ IADD3 R15, R15, 0x1, RZ ; /* 0x000000010f0f7810 */
/* 0x000fc80007ffe0ff */
/*0280*/ ISETP.GE.U32.AND P0, PT, R15, 0x78, PT ; /* 0x000000780f00780c */
/* 0x000fda0003f06070 */
/*0290*/ @!P0 BRA 0x140 ; /* 0xfffffea000008947 */
/* 0x000fea000383ffff */
/*02a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*02b0*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x8] ; /* 0x01000200ff047624 */
/* 0x000fe200078e00ff */
/*02c0*/ ULDC.64 UR4, c[0x4][0x8] ; /* 0x0100020000047ab9 */
/* 0x000fe20000000a00 */
/*02d0*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0xc] ; /* 0x01000300ff057624 */
/* 0x000fca00078e00ff */
/*02e0*/ LDG.E.U8 R7, [R4.64] ; /* 0x0000000604077981 */
/* 0x000ea2000c1e1100 */
/*02f0*/ IMAD.MOV.U32 R2, RZ, RZ, 0x78 ; /* 0x00000078ff027424 */
/* 0x000fc800078e00ff */
/*0300*/ IMAD.WIDE R2, R17, R2, c[0x0][0x160] ; /* 0x0000580011027625 */
/* 0x000fca00078e0202 */
/*0310*/ STG.E.U8 [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x0041e8000c101106 */
/*0320*/ LDG.E.U8 R9, [R4.64+0x1] ; /* 0x0000010604097981 */
/* 0x000ea2000c1e1100 */
/*0330*/ UIADD3 UR4, UP0, UR4, 0x2, URZ ; /* 0x0000000204047890 */
/* 0x000fe2000ff1e03f */
/*0340*/ IADD3 R10, P0, R2, 0x3, RZ ; /* 0x00000003020a7810 */
/* 0x000fe20007f1e0ff */
/*0350*/ IMAD.MOV.U32 R0, RZ, RZ, 0x2 ; /* 0x00000002ff007424 */
/* 0x000fe400078e00ff */
/*0360*/ UIADD3.X UR5, URZ, UR5, URZ, UP0, !UPT ; /* 0x000000053f057290 */
/* 0x000fe400087fe43f */
/*0370*/ IMAD.U32 R8, RZ, RZ, UR4 ; /* 0x00000004ff087e24 */
/* 0x000fc4000f8e00ff */
/*0380*/ IMAD.X R15, RZ, RZ, R3, P0 ; /* 0x000000ffff0f7224 */
/* 0x000fe400000e0603 */
/*0390*/ IMAD.U32 R13, RZ, RZ, UR5 ; /* 0x00000005ff0d7e24 */
/* 0x000fe2000f8e00ff */
/*03a0*/ STG.E.U8 [R2.64+0x1], R9 ; /* 0x0000010902007986 */
/* 0x0041e8000c101106 */
/*03b0*/ IMAD.MOV.U32 R4, RZ, RZ, R8 ; /* 0x000000ffff047224 */
/* 0x000fe400078e0008 */
/*03c0*/ IMAD.MOV.U32 R5, RZ, RZ, R13 ; /* 0x000000ffff057224 */
/* 0x000fca00078e000d */
/*03d0*/ LDG.E.U8 R9, [R4.64] ; /* 0x0000000604097981 */
/* 0x009ea2000c1e1100 */
/*03e0*/ IMAD.MOV.U32 R6, RZ, RZ, R10 ; /* 0x000000ffff067224 */
/* 0x000fe400078e000a */
/*03f0*/ IMAD.MOV.U32 R7, RZ, RZ, R15 ; /* 0x000000ffff077224 */
/* 0x000fca00078e000f */
/*0400*/ STG.E.U8 [R6.64+-0x1], R9 ; /* 0xffffff0906007986 */
/* 0x0041e8000c101106 */
/*0410*/ LDG.E.U8 R11, [R4.64+0x1] ; /* 0x00000106040b7981 */
/* 0x000ea8000c1e1100 */
/*0420*/ STG.E.U8 [R6.64], R11 ; /* 0x0000000b06007986 */
/* 0x0043e8000c101106 */
/*0430*/ LDG.E.U8 R13, [R4.64+0x2] ; /* 0x00000206040d7981 */
/* 0x000ea8000c1e1100 */
/*0440*/ STG.E.U8 [R6.64+0x1], R13 ; /* 0x0000010d06007986 */
/* 0x0045e8000c101106 */
/*0450*/ LDG.E.U8 R15, [R4.64+0x3] ; /* 0x00000306040f7981 */
/* 0x000ee8000c1e1100 */
/*0460*/ STG.E.U8 [R6.64+0x2], R15 ; /* 0x0000020f06007986 */
/* 0x0087e8000c101106 */
/*0470*/ LDG.E.U8 R17, [R4.64+0x4] ; /* 0x0000040604117981 */
/* 0x000f28000c1e1100 */
/*0480*/ STG.E.U8 [R6.64+0x3], R17 ; /* 0x0000031106007986 */
/* 0x0109e8000c101106 */
/*0490*/ LDG.E.U8 R19, [R4.64+0x5] ; /* 0x0000050604137981 */
/* 0x000f68000c1e1100 */
/*04a0*/ STG.E.U8 [R6.64+0x4], R19 ; /* 0x0000041306007986 */
/* 0x020be8000c101106 */
/*04b0*/ LDG.E.U8 R9, [R4.64+0x6] ; /* 0x0000060604097981 */
/* 0x001ea8000c1e1100 */
/*04c0*/ STG.E.U8 [R6.64+0x5], R9 ; /* 0x0000050906007986 */
/* 0x0041e8000c101106 */
/*04d0*/ LDG.E.U8 R11, [R4.64+0x7] ; /* 0x00000706040b7981 */
/* 0x002ea8000c1e1100 */
/*04e0*/ STG.E.U8 [R6.64+0x6], R11 ; /* 0x0000060b06007986 */
/* 0x0043e8000c101106 */
/*04f0*/ LDG.E.U8 R13, [R4.64+0x8] ; /* 0x00000806040d7981 */
/* 0x000ea8000c1e1100 */
/*0500*/ STG.E.U8 [R6.64+0x7], R13 ; /* 0x0000070d06007986 */
/* 0x0045e8000c101106 */
/*0510*/ LDG.E.U8 R15, [R4.64+0x9] ; /* 0x00000906040f7981 */
/* 0x008ee8000c1e1100 */
/*0520*/ STG.E.U8 [R6.64+0x8], R15 ; /* 0x0000080f06007986 */
/* 0x0087e8000c101106 */
/*0530*/ LDG.E.U8 R17, [R4.64+0xa] ; /* 0x00000a0604117981 */
/* 0x010f28000c1e1100 */
/*0540*/ STG.E.U8 [R6.64+0x9], R17 ; /* 0x0000091106007986 */
/* 0x0109e8000c101106 */
/*0550*/ LDG.E.U8 R19, [R4.64+0xb] ; /* 0x00000b0604137981 */
/* 0x020f68000c1e1100 */
/*0560*/ STG.E.U8 [R6.64+0xa], R19 ; /* 0x00000a1306007986 */
/* 0x020be8000c101106 */
/*0570*/ LDG.E.U8 R9, [R4.64+0xc] ; /* 0x00000c0604097981 */
/* 0x001ea8000c1e1100 */
/*0580*/ STG.E.U8 [R6.64+0xb], R9 ; /* 0x00000b0906007986 */
/* 0x0041e8000c101106 */
/*0590*/ LDG.E.U8 R11, [R4.64+0xd] ; /* 0x00000d06040b7981 */
/* 0x002ea8000c1e1100 */
/*05a0*/ STG.E.U8 [R6.64+0xc], R11 ; /* 0x00000c0b06007986 */
/* 0x0043e8000c101106 */
/*05b0*/ LDG.E.U8 R13, [R4.64+0xe] ; /* 0x00000e06040d7981 */
/* 0x000ea8000c1e1100 */
/*05c0*/ STG.E.U8 [R6.64+0xd], R13 ; /* 0x00000d0d06007986 */
/* 0x0045e8000c101106 */
/*05d0*/ LDG.E.U8 R15, [R4.64+0xf] ; /* 0x00000f06040f7981 */
/* 0x008ee8000c1e1100 */
/*05e0*/ STG.E.U8 [R6.64+0xe], R15 ; /* 0x00000e0f06007986 */
/* 0x0087e8000c101106 */
/*05f0*/ LDG.E.U8 R17, [R4.64+0x10] ; /* 0x0000100604117981 */
/* 0x010f28000c1e1100 */
/*0600*/ STG.E.U8 [R6.64+0xf], R17 ; /* 0x00000f1106007986 */
/* 0x0109e8000c101106 */
/*0610*/ LDG.E.U8 R19, [R4.64+0x11] ; /* 0x0000110604137981 */
/* 0x020f68000c1e1100 */
/*0620*/ STG.E.U8 [R6.64+0x10], R19 ; /* 0x0000101306007986 */
/* 0x020be8000c101106 */
/*0630*/ LDG.E.U8 R9, [R4.64+0x12] ; /* 0x0000120604097981 */
/* 0x001ea8000c1e1100 */
/*0640*/ STG.E.U8 [R6.64+0x11], R9 ; /* 0x0000110906007986 */
/* 0x0041e8000c101106 */
/*0650*/ LDG.E.U8 R11, [R4.64+0x13] ; /* 0x00001306040b7981 */
/* 0x002ea8000c1e1100 */
/*0660*/ STG.E.U8 [R6.64+0x12], R11 ; /* 0x0000120b06007986 */
/* 0x0043e8000c101106 */
/*0670*/ LDG.E.U8 R13, [R4.64+0x14] ; /* 0x00001406040d7981 */
/* 0x000ea8000c1e1100 */
/*0680*/ STG.E.U8 [R6.64+0x13], R13 ; /* 0x0000130d06007986 */
/* 0x0045e8000c101106 */
/*0690*/ LDG.E.U8 R15, [R4.64+0x15] ; /* 0x00001506040f7981 */
/* 0x008ee8000c1e1100 */
/*06a0*/ STG.E.U8 [R6.64+0x14], R15 ; /* 0x0000140f06007986 */
/* 0x0087e8000c101106 */
/*06b0*/ LDG.E.U8 R17, [R4.64+0x16] ; /* 0x0000160604117981 */
/* 0x010f28000c1e1100 */
/*06c0*/ STG.E.U8 [R6.64+0x15], R17 ; /* 0x0000151106007986 */
/* 0x0109e8000c101106 */
/*06d0*/ LDG.E.U8 R19, [R4.64+0x17] ; /* 0x0000170604137981 */
/* 0x020f68000c1e1100 */
/*06e0*/ STG.E.U8 [R6.64+0x16], R19 ; /* 0x0000161306007986 */
/* 0x020be8000c101106 */
/*06f0*/ LDG.E.U8 R9, [R4.64+0x18] ; /* 0x0000180604097981 */
/* 0x001ea8000c1e1100 */
/*0700*/ STG.E.U8 [R6.64+0x17], R9 ; /* 0x0000170906007986 */
/* 0x0041e8000c101106 */
/*0710*/ LDG.E.U8 R11, [R4.64+0x19] ; /* 0x00001906040b7981 */
/* 0x002ea8000c1e1100 */
/*0720*/ STG.E.U8 [R6.64+0x18], R11 ; /* 0x0000180b06007986 */
/* 0x0043e8000c101106 */
/*0730*/ LDG.E.U8 R13, [R4.64+0x1a] ; /* 0x00001a06040d7981 */
/* 0x000ea8000c1e1100 */
/*0740*/ STG.E.U8 [R6.64+0x19], R13 ; /* 0x0000190d06007986 */
/* 0x0045e8000c101106 */
/*0750*/ LDG.E.U8 R15, [R4.64+0x1b] ; /* 0x00001b06040f7981 */
/* 0x008ee8000c1e1100 */
/*0760*/ STG.E.U8 [R6.64+0x1a], R15 ; /* 0x00001a0f06007986 */
/* 0x0087e8000c101106 */
/*0770*/ LDG.E.U8 R17, [R4.64+0x1c] ; /* 0x00001c0604117981 */
/* 0x010f28000c1e1100 */
/*0780*/ STG.E.U8 [R6.64+0x1b], R17 ; /* 0x00001b1106007986 */
/* 0x0109e8000c101106 */
/*0790*/ LDG.E.U8 R19, [R4.64+0x1d] ; /* 0x00001d0604137981 */
/* 0x020f68000c1e1100 */
/*07a0*/ STG.E.U8 [R6.64+0x1c], R19 ; /* 0x00001c1306007986 */
/* 0x020be8000c101106 */
/*07b0*/ LDG.E.U8 R9, [R4.64+0x1e] ; /* 0x00001e0604097981 */
/* 0x001ea8000c1e1100 */
/*07c0*/ STG.E.U8 [R6.64+0x1d], R9 ; /* 0x00001d0906007986 */
/* 0x0041e8000c101106 */
/*07d0*/ LDG.E.U8 R11, [R4.64+0x1f] ; /* 0x00001f06040b7981 */
/* 0x002ea8000c1e1100 */
/*07e0*/ STG.E.U8 [R6.64+0x1e], R11 ; /* 0x00001e0b06007986 */
/* 0x0043e8000c101106 */
/*07f0*/ LDG.E.U8 R13, [R4.64+0x20] ; /* 0x00002006040d7981 */
/* 0x000ea8000c1e1100 */
/*0800*/ STG.E.U8 [R6.64+0x1f], R13 ; /* 0x00001f0d06007986 */
/* 0x0045e8000c101106 */
/*0810*/ LDG.E.U8 R15, [R4.64+0x21] ; /* 0x00002106040f7981 */
/* 0x008ee8000c1e1100 */
/*0820*/ STG.E.U8 [R6.64+0x20], R15 ; /* 0x0000200f06007986 */
/* 0x0087e8000c101106 */
/*0830*/ LDG.E.U8 R17, [R4.64+0x22] ; /* 0x0000220604117981 */
/* 0x010f28000c1e1100 */
/*0840*/ STG.E.U8 [R6.64+0x21], R17 ; /* 0x0000211106007986 */
/* 0x0109e8000c101106 */
/*0850*/ LDG.E.U8 R19, [R4.64+0x23] ; /* 0x0000230604137981 */
/* 0x020f68000c1e1100 */
/*0860*/ STG.E.U8 [R6.64+0x22], R19 ; /* 0x0000221306007986 */
/* 0x020be8000c101106 */
/*0870*/ LDG.E.U8 R9, [R4.64+0x24] ; /* 0x0000240604097981 */
/* 0x001ea8000c1e1100 */
/*0880*/ STG.E.U8 [R6.64+0x23], R9 ; /* 0x0000230906007986 */
/* 0x0041e8000c101106 */
/*0890*/ LDG.E.U8 R11, [R4.64+0x25] ; /* 0x00002506040b7981 */
/* 0x002ea8000c1e1100 */
/*08a0*/ STG.E.U8 [R6.64+0x24], R11 ; /* 0x0000240b06007986 */
/* 0x0043e8000c101106 */
/*08b0*/ LDG.E.U8 R13, [R4.64+0x26] ; /* 0x00002606040d7981 */
/* 0x000ea8000c1e1100 */
/*08c0*/ STG.E.U8 [R6.64+0x25], R13 ; /* 0x0000250d06007986 */
/* 0x0045e8000c101106 */
/*08d0*/ LDG.E.U8 R15, [R4.64+0x27] ; /* 0x00002706040f7981 */
/* 0x008ee8000c1e1100 */
/*08e0*/ STG.E.U8 [R6.64+0x26], R15 ; /* 0x0000260f06007986 */
/* 0x0087e8000c101106 */
/*08f0*/ LDG.E.U8 R17, [R4.64+0x28] ; /* 0x0000280604117981 */
/* 0x010f28000c1e1100 */
/*0900*/ STG.E.U8 [R6.64+0x27], R17 ; /* 0x0000271106007986 */
/* 0x0109e8000c101106 */
/*0910*/ LDG.E.U8 R19, [R4.64+0x29] ; /* 0x0000290604137981 */
/* 0x020f68000c1e1100 */
/*0920*/ STG.E.U8 [R6.64+0x28], R19 ; /* 0x0000281306007986 */
/* 0x020be8000c101106 */
/*0930*/ LDG.E.U8 R9, [R4.64+0x2a] ; /* 0x00002a0604097981 */
/* 0x001ea8000c1e1100 */
/*0940*/ STG.E.U8 [R6.64+0x29], R9 ; /* 0x0000290906007986 */
/* 0x0041e8000c101106 */
/*0950*/ LDG.E.U8 R11, [R4.64+0x2b] ; /* 0x00002b06040b7981 */
/* 0x002ea8000c1e1100 */
/*0960*/ STG.E.U8 [R6.64+0x2a], R11 ; /* 0x00002a0b06007986 */
/* 0x0043e8000c101106 */
/*0970*/ LDG.E.U8 R13, [R4.64+0x2c] ; /* 0x00002c06040d7981 */
/* 0x000ea8000c1e1100 */
/*0980*/ STG.E.U8 [R6.64+0x2b], R13 ; /* 0x00002b0d06007986 */
/* 0x0045e8000c101106 */
/*0990*/ LDG.E.U8 R15, [R4.64+0x2d] ; /* 0x00002d06040f7981 */
/* 0x008ee8000c1e1100 */
/*09a0*/ STG.E.U8 [R6.64+0x2c], R15 ; /* 0x00002c0f06007986 */
/* 0x0087e8000c101106 */
/*09b0*/ LDG.E.U8 R17, [R4.64+0x2e] ; /* 0x00002e0604117981 */
/* 0x010f28000c1e1100 */
/*09c0*/ STG.E.U8 [R6.64+0x2d], R17 ; /* 0x00002d1106007986 */
/* 0x0109e8000c101106 */
/*09d0*/ LDG.E.U8 R19, [R4.64+0x2f] ; /* 0x00002f0604137981 */
/* 0x020f68000c1e1100 */
/*09e0*/ STG.E.U8 [R6.64+0x2e], R19 ; /* 0x00002e1306007986 */
/* 0x020be8000c101106 */
/*09f0*/ LDG.E.U8 R9, [R4.64+0x30] ; /* 0x0000300604097981 */
/* 0x001ea8000c1e1100 */
/*0a00*/ STG.E.U8 [R6.64+0x2f], R9 ; /* 0x00002f0906007986 */
/* 0x0041e8000c101106 */
/*0a10*/ LDG.E.U8 R11, [R4.64+0x31] ; /* 0x00003106040b7981 */
/* 0x002ea8000c1e1100 */
/*0a20*/ STG.E.U8 [R6.64+0x30], R11 ; /* 0x0000300b06007986 */
/* 0x0043e8000c101106 */
/*0a30*/ LDG.E.U8 R13, [R4.64+0x32] ; /* 0x00003206040d7981 */
/* 0x000ea8000c1e1100 */
/*0a40*/ STG.E.U8 [R6.64+0x31], R13 ; /* 0x0000310d06007986 */
/* 0x0045e8000c101106 */
/*0a50*/ LDG.E.U8 R15, [R4.64+0x33] ; /* 0x00003306040f7981 */
/* 0x008ee8000c1e1100 */
/*0a60*/ STG.E.U8 [R6.64+0x32], R15 ; /* 0x0000320f06007986 */
/* 0x0087e8000c101106 */
/*0a70*/ LDG.E.U8 R17, [R4.64+0x34] ; /* 0x0000340604117981 */
/* 0x010f28000c1e1100 */
/*0a80*/ STG.E.U8 [R6.64+0x33], R17 ; /* 0x0000331106007986 */
/* 0x0109e8000c101106 */
/*0a90*/ LDG.E.U8 R19, [R4.64+0x35] ; /* 0x0000350604137981 */
/* 0x020f68000c1e1100 */
/*0aa0*/ STG.E.U8 [R6.64+0x34], R19 ; /* 0x0000341306007986 */
/* 0x020be8000c101106 */
/*0ab0*/ LDG.E.U8 R9, [R4.64+0x36] ; /* 0x0000360604097981 */
/* 0x001ea8000c1e1100 */
/*0ac0*/ STG.E.U8 [R6.64+0x35], R9 ; /* 0x0000350906007986 */
/* 0x0041e8000c101106 */
/*0ad0*/ LDG.E.U8 R11, [R4.64+0x37] ; /* 0x00003706040b7981 */
/* 0x002ea8000c1e1100 */
/*0ae0*/ STG.E.U8 [R6.64+0x36], R11 ; /* 0x0000360b06007986 */
/* 0x0043e8000c101106 */
/*0af0*/ LDG.E.U8 R13, [R4.64+0x38] ; /* 0x00003806040d7981 */
/* 0x000ea8000c1e1100 */
/*0b00*/ STG.E.U8 [R6.64+0x37], R13 ; /* 0x0000370d06007986 */
/* 0x004fe8000c101106 */
/*0b10*/ LDG.E.U8 R15, [R4.64+0x39] ; /* 0x00003906040f7981 */
/* 0x008ea8000c1e1100 */
/*0b20*/ STG.E.U8 [R6.64+0x38], R15 ; /* 0x0000380f06007986 */
/* 0x0045e8000c101106 */
/*0b30*/ LDG.E.U8 R17, [R4.64+0x3a] ; /* 0x00003a0604117981 */
/* 0x010ee8000c1e1100 */
/*0b40*/ STG.E.U8 [R6.64+0x39], R17 ; /* 0x0000391106007986 */
/* 0x0087e8000c101106 */
/*0b50*/ LDG.E.U8 R19, [R4.64+0x3b] ; /* 0x00003b0604137981 */
/* 0x020f28000c1e1100 */
/*0b60*/ STG.E.U8 [R6.64+0x3a], R19 ; /* 0x00003a1306007986 */
/* 0x0107e8000c101106 */
/*0b70*/ LDG.E.U8 R9, [R4.64+0x3c] ; /* 0x00003c0604097981 */
/* 0x001f28000c1e1100 */
/*0b80*/ STG.E.U8 [R6.64+0x3b], R9 ; /* 0x00003b0906007986 */
/* 0x0107e8000c101106 */
/*0b90*/ LDG.E.U8 R11, [R4.64+0x3d] ; /* 0x00003d06040b7981 */
/* 0x002f22000c1e1100 */
/*0ba0*/ IADD3 R0, R0, 0x3e, RZ ; /* 0x0000003e00007810 */
/* 0x000fc40007ffe0ff */
/*0bb0*/ IADD3 R10, P1, R6, 0x3e, RZ ; /* 0x0000003e060a7810 */
/* 0x000fe40007f3e0ff */
/*0bc0*/ ISETP.NE.AND P0, PT, R0, 0xfa, PT ; /* 0x000000fa0000780c */
/* 0x000fe40003f05270 */
/*0bd0*/ IADD3 R8, P2, R4, 0x3e, RZ ; /* 0x0000003e04087810 */
/* 0x000fe20007f5e0ff */
/*0be0*/ IMAD.X R15, RZ, RZ, R7, P1 ; /* 0x000000ffff0f7224 */
/* 0x004fc800008e0607 */
/*0bf0*/ IMAD.X R13, RZ, RZ, R5, P2 ; /* 0x000000ffff0d7224 */
/* 0x000fe200010e0605 */
/*0c00*/ STG.E.U8 [R6.64+0x3c], R11 ; /* 0x00003c0b06007986 */
/* 0x0107ea000c101106 */
/*0c10*/ @P0 BRA 0x3b0 ; /* 0xfffff79000000947 */
/* 0x000fea000383ffff */
/*0c20*/ STG.E.U8 [R2.64+0xfa], RZ ; /* 0x0000faff02007986 */
/* 0x000fe2000c101106 */
/*0c30*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0c40*/ BRA 0xc40; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0c50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ca0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ce0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
/* 1-98番目までのテキスト。__ の部分を今の数字に、 ## の部分をひとつ減らした数字に置き換える */
__device__ char text[] = "__ bottles of beer on the wall, __ bottles of beer!\n"
"Take one down, and pass it around, ## bottles of beer on the wall!\n\n";
/* 99番目のテキスト。そのまま表示する */
__device__ char end[] =
"01 bottle of beer on the wall, 01 bottle of beer.\n"
"Take one down and pass it around, no more bottles of beer on the wall.\n"
"\n"
"No more bottles of beer on the wall, no more bottles of beer.\n"
"Go to the store and buy some more, 99 bottles of beer on the wall.";
#define SIZE_TEXT (sizeof(text)-1) /* 98番目までのテキストの長さ */
#define SIZE_END (sizeof(end)-1) /* 99番目のテキストの長さ */
__global__
void bottle99(char *addr)
{
/* スレッド ID(threadIdx.x) の取得 */
int x = threadIdx.x;
/* 結果の格納アドレスを求める */
addr += x * SIZE_TEXT;
/* 残りのボトル数を求める */
int bottle = 99 - x;
if (bottle == 1) {
/* 99番目, ボトルが無くなったのでendを表示 */
for (int i=0; i<SIZE_END; i++) {
addr[i] = end[i];
}
addr[SIZE_END] = '\0';
} else {
/* 1-98番目 */
/* 残りのボトル数のASCII表現 */
char c1 = (bottle/10) + '0';
char c2 = (bottle%10) + '0';
/* ひとつ減ったあとのボトル数のASCII表現 */
char d1 = ((bottle-1)/10) + '0';
char d2 = ((bottle-1)%10) + '0';
for (int i=0; i<SIZE_TEXT; i++) {
int c = text[i];
if (c == '_') {
/* '__' の置き換え */
addr[i] = c1;
addr[i+1] = c2;
i++;
} else if (c == '#') {
/* '##' の置き換え */
addr[i] = d1;
addr[i+1] = d2;
i++;
} else {
/* 文字列のコピー */
addr[i] = text[i];
}
}
}
}
int main()
{
char *buffer;
char *d_buffer;
/* 必要な領域を計算する */
int size = SIZE_TEXT * 98 + SIZE_END + 1;
buffer = new char[size];
cudaMalloc((void**)&d_buffer, size);
/* 99 bottles of beer を求めるために99個のスレッドを起動する */
bottle99<<<1, 99>>>(d_buffer);
/* 結果を取得 */
cudaMemcpy(buffer, d_buffer, size, cudaMemcpyDeviceToHost);
cudaFree(d_buffer);
/* 表示 */
puts(buffer);
free(buffer);
} | .file "tmpxft_000c038e_00000000-6_99bear.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z27__device_stub__Z8bottle99PcPc
.type _Z27__device_stub__Z8bottle99PcPc, @function
_Z27__device_stub__Z8bottle99PcPc:
.LFB2082:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z8bottle99Pc(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z27__device_stub__Z8bottle99PcPc, .-_Z27__device_stub__Z8bottle99PcPc
.globl _Z8bottle99Pc
.type _Z8bottle99Pc, @function
_Z8bottle99Pc:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z27__device_stub__Z8bottle99PcPc
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z8bottle99Pc, .-_Z8bottle99Pc
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $48, %rsp
.cfi_def_cfa_offset 64
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movl $12011, %edi
call _Znam@PLT
movq %rax, %rbx
leaq 8(%rsp), %rdi
movl $12011, %esi
call cudaMalloc@PLT
movl $99, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L15
.L12:
movl $2, %ecx
movl $12011, %edx
movq 8(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq %rbx, %rdi
call puts@PLT
movq %rbx, %rdi
call free@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L16
movl $0, %eax
addq $48, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
movq 8(%rsp), %rdi
call _Z27__device_stub__Z8bottle99PcPc
jmp .L12
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z8bottle99Pc"
.LC1:
.string "text"
.LC2:
.string "end"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z8bottle99Pc(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $121, %r9d
movl $0, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _ZL4text(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $251, %r9d
movl $0, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _ZL3end(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL3end
.comm _ZL3end,251,32
.local _ZL4text
.comm _ZL4text,121,32
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
/* 1-98番目までのテキスト。__ の部分を今の数字に、 ## の部分をひとつ減らした数字に置き換える */
__device__ char text[] = "__ bottles of beer on the wall, __ bottles of beer!\n"
"Take one down, and pass it around, ## bottles of beer on the wall!\n\n";
/* 99番目のテキスト。そのまま表示する */
__device__ char end[] =
"01 bottle of beer on the wall, 01 bottle of beer.\n"
"Take one down and pass it around, no more bottles of beer on the wall.\n"
"\n"
"No more bottles of beer on the wall, no more bottles of beer.\n"
"Go to the store and buy some more, 99 bottles of beer on the wall.";
#define SIZE_TEXT (sizeof(text)-1) /* 98番目までのテキストの長さ */
#define SIZE_END (sizeof(end)-1) /* 99番目のテキストの長さ */
__global__
void bottle99(char *addr)
{
/* スレッド ID(threadIdx.x) の取得 */
int x = threadIdx.x;
/* 結果の格納アドレスを求める */
addr += x * SIZE_TEXT;
/* 残りのボトル数を求める */
int bottle = 99 - x;
if (bottle == 1) {
/* 99番目, ボトルが無くなったのでendを表示 */
for (int i=0; i<SIZE_END; i++) {
addr[i] = end[i];
}
addr[SIZE_END] = '\0';
} else {
/* 1-98番目 */
/* 残りのボトル数のASCII表現 */
char c1 = (bottle/10) + '0';
char c2 = (bottle%10) + '0';
/* ひとつ減ったあとのボトル数のASCII表現 */
char d1 = ((bottle-1)/10) + '0';
char d2 = ((bottle-1)%10) + '0';
for (int i=0; i<SIZE_TEXT; i++) {
int c = text[i];
if (c == '_') {
/* '__' の置き換え */
addr[i] = c1;
addr[i+1] = c2;
i++;
} else if (c == '#') {
/* '##' の置き換え */
addr[i] = d1;
addr[i+1] = d2;
i++;
} else {
/* 文字列のコピー */
addr[i] = text[i];
}
}
}
}
int main()
{
char *buffer;
char *d_buffer;
/* 必要な領域を計算する */
int size = SIZE_TEXT * 98 + SIZE_END + 1;
buffer = new char[size];
cudaMalloc((void**)&d_buffer, size);
/* 99 bottles of beer を求めるために99個のスレッドを起動する */
bottle99<<<1, 99>>>(d_buffer);
/* 結果を取得 */
cudaMemcpy(buffer, d_buffer, size, cudaMemcpyDeviceToHost);
cudaFree(d_buffer);
/* 表示 */
puts(buffer);
free(buffer);
} | #include <hip/hip_runtime.h>
#include <stdio.h>
/* 1-98番目までのテキスト。__ の部分を今の数字に、 ## の部分をひとつ減らした数字に置き換える */
__device__ char text[] = "__ bottles of beer on the wall, __ bottles of beer!\n"
"Take one down, and pass it around, ## bottles of beer on the wall!\n\n";
/* 99番目のテキスト。そのまま表示する */
__device__ char end[] =
"01 bottle of beer on the wall, 01 bottle of beer.\n"
"Take one down and pass it around, no more bottles of beer on the wall.\n"
"\n"
"No more bottles of beer on the wall, no more bottles of beer.\n"
"Go to the store and buy some more, 99 bottles of beer on the wall.";
#define SIZE_TEXT (sizeof(text)-1) /* 98番目までのテキストの長さ */
#define SIZE_END (sizeof(end)-1) /* 99番目のテキストの長さ */
__global__
void bottle99(char *addr)
{
/* スレッド ID(threadIdx.x) の取得 */
int x = threadIdx.x;
/* 結果の格納アドレスを求める */
addr += x * SIZE_TEXT;
/* 残りのボトル数を求める */
int bottle = 99 - x;
if (bottle == 1) {
/* 99番目, ボトルが無くなったのでendを表示 */
for (int i=0; i<SIZE_END; i++) {
addr[i] = end[i];
}
addr[SIZE_END] = '\0';
} else {
/* 1-98番目 */
/* 残りのボトル数のASCII表現 */
char c1 = (bottle/10) + '0';
char c2 = (bottle%10) + '0';
/* ひとつ減ったあとのボトル数のASCII表現 */
char d1 = ((bottle-1)/10) + '0';
char d2 = ((bottle-1)%10) + '0';
for (int i=0; i<SIZE_TEXT; i++) {
int c = text[i];
if (c == '_') {
/* '__' の置き換え */
addr[i] = c1;
addr[i+1] = c2;
i++;
} else if (c == '#') {
/* '##' の置き換え */
addr[i] = d1;
addr[i+1] = d2;
i++;
} else {
/* 文字列のコピー */
addr[i] = text[i];
}
}
}
}
int main()
{
char *buffer;
char *d_buffer;
/* 必要な領域を計算する */
int size = SIZE_TEXT * 98 + SIZE_END + 1;
buffer = new char[size];
hipMalloc((void**)&d_buffer, size);
/* 99 bottles of beer を求めるために99個のスレッドを起動する */
bottle99<<<1, 99>>>(d_buffer);
/* 結果を取得 */
hipMemcpy(buffer, d_buffer, size, hipMemcpyDeviceToHost);
hipFree(d_buffer);
/* 表示 */
puts(buffer);
free(buffer);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
/* 1-98番目までのテキスト。__ の部分を今の数字に、 ## の部分をひとつ減らした数字に置き換える */
__device__ char text[] = "__ bottles of beer on the wall, __ bottles of beer!\n"
"Take one down, and pass it around, ## bottles of beer on the wall!\n\n";
/* 99番目のテキスト。そのまま表示する */
__device__ char end[] =
"01 bottle of beer on the wall, 01 bottle of beer.\n"
"Take one down and pass it around, no more bottles of beer on the wall.\n"
"\n"
"No more bottles of beer on the wall, no more bottles of beer.\n"
"Go to the store and buy some more, 99 bottles of beer on the wall.";
#define SIZE_TEXT (sizeof(text)-1) /* 98番目までのテキストの長さ */
#define SIZE_END (sizeof(end)-1) /* 99番目のテキストの長さ */
__global__
void bottle99(char *addr)
{
/* スレッド ID(threadIdx.x) の取得 */
int x = threadIdx.x;
/* 結果の格納アドレスを求める */
addr += x * SIZE_TEXT;
/* 残りのボトル数を求める */
int bottle = 99 - x;
if (bottle == 1) {
/* 99番目, ボトルが無くなったのでendを表示 */
for (int i=0; i<SIZE_END; i++) {
addr[i] = end[i];
}
addr[SIZE_END] = '\0';
} else {
/* 1-98番目 */
/* 残りのボトル数のASCII表現 */
char c1 = (bottle/10) + '0';
char c2 = (bottle%10) + '0';
/* ひとつ減ったあとのボトル数のASCII表現 */
char d1 = ((bottle-1)/10) + '0';
char d2 = ((bottle-1)%10) + '0';
for (int i=0; i<SIZE_TEXT; i++) {
int c = text[i];
if (c == '_') {
/* '__' の置き換え */
addr[i] = c1;
addr[i+1] = c2;
i++;
} else if (c == '#') {
/* '##' の置き換え */
addr[i] = d1;
addr[i+1] = d2;
i++;
} else {
/* 文字列のコピー */
addr[i] = text[i];
}
}
}
}
int main()
{
char *buffer;
char *d_buffer;
/* 必要な領域を計算する */
int size = SIZE_TEXT * 98 + SIZE_END + 1;
buffer = new char[size];
hipMalloc((void**)&d_buffer, size);
/* 99 bottles of beer を求めるために99個のスレッドを起動する */
bottle99<<<1, 99>>>(d_buffer);
/* 結果を取得 */
hipMemcpy(buffer, d_buffer, size, hipMemcpyDeviceToHost);
hipFree(d_buffer);
/* 表示 */
puts(buffer);
free(buffer);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z8bottle99Pc
.globl _Z8bottle99Pc
.p2align 8
.type _Z8bottle99Pc,@function
_Z8bottle99Pc:
s_load_b64 s[0:1], s[0:1], 0x0
v_mul_u32_u24_e32 v1, 0x78, v0
v_mov_b32_e32 v5, 0
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v1, s0, s0, v1
v_add_co_ci_u32_e64 v2, null, s1, 0, s0
s_mov_b32 s0, exec_lo
v_cmpx_ne_u32_e32 0x62, v0
s_xor_b32 s2, exec_lo, s0
s_cbranch_execz .LBB0_13
v_sub_nc_u32_e32 v3, 0x63, v0
v_sub_nc_u32_e32 v0, 0x62, v0
s_mov_b32 s3, 0
s_mov_b64 s[0:1], 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_hi_i32 v4, v3, 0x66666667
v_mul_hi_i32 v6, v0, 0x66666667
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_lshrrev_b32_e32 v7, 31, v4
v_ashrrev_i32_e32 v4, 2, v4
v_lshrrev_b32_e32 v8, 31, v6
v_ashrrev_i32_e32 v6, 2, v6
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v4, v4, v7
v_add_nc_u32_e32 v6, v6, v8
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_lo_u32 v7, v4, 10
v_mul_lo_u32 v8, v6, 10
v_add_nc_u16 v6, v6, 48
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_sub_nc_u32_e32 v3, v3, v7
v_sub_nc_u32_e32 v8, v0, v8
v_add_nc_u16 v0, v4, 48
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_nc_u16 v7, v3, 48
v_add_nc_u16 v8, v8, 48
s_branch .LBB0_3
.LBB0_2:
s_add_i32 s0, s0, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_ashr_i32 s1, s0, 31
s_cmpk_lt_u32 s0, 0x78
s_mov_b32 s3, s0
s_cbranch_scc0 .LBB0_13
.LBB0_3:
s_getpc_b64 s[4:5]
s_add_u32 s4, s4, text@rel32@lo+4
s_addc_u32 s5, s5, text@rel32@hi+12
s_add_u32 s4, s0, s4
s_addc_u32 s5, s1, s5
v_add_co_u32 v3, s0, v1, s0
global_load_u8 v9, v5, s[4:5]
v_add_co_ci_u32_e64 v4, s0, s1, v2, s0
s_mov_b32 s5, -1
s_mov_b32 s1, 0
s_mov_b32 s4, 0
s_waitcnt vmcnt(0)
v_cmp_gt_i16_e32 vcc_lo, 0x5f, v9
s_cbranch_vccz .LBB0_7
s_and_b32 vcc_lo, exec_lo, s5
s_cbranch_vccnz .LBB0_10
.LBB0_5:
s_and_not1_b32 vcc_lo, exec_lo, s4
s_cbranch_vccz .LBB0_11
.LBB0_6:
s_and_not1_b32 vcc_lo, exec_lo, s1
s_cbranch_vccnz .LBB0_2
s_branch .LBB0_12
.LBB0_7:
v_cmp_eq_u16_e32 vcc_lo, 0x5f, v9
s_mov_b32 s4, -1
s_cbranch_vccz .LBB0_9
s_add_i32 s0, s3, 1
global_store_b8 v[3:4], v0, off
v_add_co_u32 v10, vcc_lo, v1, s0
v_add_co_ci_u32_e32 v11, vcc_lo, 0, v2, vcc_lo
s_mov_b32 s4, 0
global_store_b8 v[10:11], v7, off
.LBB0_9:
s_branch .LBB0_5
.LBB0_10:
v_cmp_ne_u16_e64 s4, 35, v9
s_mov_b32 s1, -1
s_delay_alu instid0(VALU_DEP_1)
s_and_not1_b32 vcc_lo, exec_lo, s4
s_cbranch_vccnz .LBB0_6
.LBB0_11:
s_mov_b32 s0, s3
global_store_b8 v[3:4], v9, off
s_cbranch_execnz .LBB0_2
.LBB0_12:
s_add_i32 s0, s3, 1
s_delay_alu instid0(SALU_CYCLE_1)
v_add_co_u32 v9, vcc_lo, v1, s0
v_add_co_ci_u32_e32 v10, vcc_lo, 0, v2, vcc_lo
s_clause 0x1
global_store_b8 v[3:4], v6, off
global_store_b8 v[9:10], v8, off
s_branch .LBB0_2
.LBB0_13:
s_and_not1_saveexec_b32 s0, s2
s_cbranch_execz .LBB0_17
v_mov_b32_e32 v0, 0
s_mov_b64 s[0:1], 0
.p2align 6
.LBB0_15:
s_getpc_b64 s[2:3]
s_add_u32 s2, s2, end@rel32@lo+4
s_addc_u32 s3, s3, end@rel32@hi+12
s_add_u32 s2, s0, s2
s_addc_u32 s3, s1, s3
v_add_co_u32 v3, vcc_lo, v1, s0
global_load_u8 v5, v0, s[2:3]
v_add_co_ci_u32_e32 v4, vcc_lo, s1, v2, vcc_lo
s_add_u32 s0, s0, 1
s_addc_u32 s1, s1, 0
s_cmpk_eq_i32 s0, 0xfa
s_waitcnt vmcnt(0)
global_store_b8 v[3:4], v5, off
s_cbranch_scc0 .LBB0_15
v_mov_b32_e32 v0, 0
global_store_b8 v[1:2], v0, off offset:250
.LBB0_17:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8bottle99Pc
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 8
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 12
.amdhsa_next_free_sgpr 6
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z8bottle99Pc, .Lfunc_end0-_Z8bottle99Pc
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.protected text
.type text,@object
.data
.globl text
.p2align 4, 0x0
text:
.asciz "__ bottles of beer on the wall, __ bottles of beer!\nTake one down, and pass it around, ## bottles of beer on the wall!\n\n"
.size text, 121
.protected end
.type end,@object
.globl end
.p2align 4, 0x0
end:
.asciz "01 bottle of beer on the wall, 01 bottle of beer.\nTake one down and pass it around, no more bottles of beer on the wall.\n\nNo more bottles of beer on the wall, no more bottles of beer.\nGo to the store and buy some more, 99 bottles of beer on the wall."
.size end, 251
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym text
.addrsig_sym end
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 8
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8bottle99Pc
.private_segment_fixed_size: 0
.sgpr_count: 8
.sgpr_spill_count: 0
.symbol: _Z8bottle99Pc.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 12
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
/* 1-98番目までのテキスト。__ の部分を今の数字に、 ## の部分をひとつ減らした数字に置き換える */
__device__ char text[] = "__ bottles of beer on the wall, __ bottles of beer!\n"
"Take one down, and pass it around, ## bottles of beer on the wall!\n\n";
/* 99番目のテキスト。そのまま表示する */
__device__ char end[] =
"01 bottle of beer on the wall, 01 bottle of beer.\n"
"Take one down and pass it around, no more bottles of beer on the wall.\n"
"\n"
"No more bottles of beer on the wall, no more bottles of beer.\n"
"Go to the store and buy some more, 99 bottles of beer on the wall.";
#define SIZE_TEXT (sizeof(text)-1) /* 98番目までのテキストの長さ */
#define SIZE_END (sizeof(end)-1) /* 99番目のテキストの長さ */
__global__
void bottle99(char *addr)
{
/* スレッド ID(threadIdx.x) の取得 */
int x = threadIdx.x;
/* 結果の格納アドレスを求める */
addr += x * SIZE_TEXT;
/* 残りのボトル数を求める */
int bottle = 99 - x;
if (bottle == 1) {
/* 99番目, ボトルが無くなったのでendを表示 */
for (int i=0; i<SIZE_END; i++) {
addr[i] = end[i];
}
addr[SIZE_END] = '\0';
} else {
/* 1-98番目 */
/* 残りのボトル数のASCII表現 */
char c1 = (bottle/10) + '0';
char c2 = (bottle%10) + '0';
/* ひとつ減ったあとのボトル数のASCII表現 */
char d1 = ((bottle-1)/10) + '0';
char d2 = ((bottle-1)%10) + '0';
for (int i=0; i<SIZE_TEXT; i++) {
int c = text[i];
if (c == '_') {
/* '__' の置き換え */
addr[i] = c1;
addr[i+1] = c2;
i++;
} else if (c == '#') {
/* '##' の置き換え */
addr[i] = d1;
addr[i+1] = d2;
i++;
} else {
/* 文字列のコピー */
addr[i] = text[i];
}
}
}
}
int main()
{
char *buffer;
char *d_buffer;
/* 必要な領域を計算する */
int size = SIZE_TEXT * 98 + SIZE_END + 1;
buffer = new char[size];
hipMalloc((void**)&d_buffer, size);
/* 99 bottles of beer を求めるために99個のスレッドを起動する */
bottle99<<<1, 99>>>(d_buffer);
/* 結果を取得 */
hipMemcpy(buffer, d_buffer, size, hipMemcpyDeviceToHost);
hipFree(d_buffer);
/* 表示 */
puts(buffer);
free(buffer);
} | .text
.file "99bear.hip"
.globl _Z23__device_stub__bottle99Pc # -- Begin function _Z23__device_stub__bottle99Pc
.p2align 4, 0x90
.type _Z23__device_stub__bottle99Pc,@function
_Z23__device_stub__bottle99Pc: # @_Z23__device_stub__bottle99Pc
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z8bottle99Pc, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size _Z23__device_stub__bottle99Pc, .Lfunc_end0-_Z23__device_stub__bottle99Pc
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $80, %rsp
.cfi_def_cfa_offset 96
.cfi_offset %rbx, -16
movl $12011, %edi # imm = 0x2EEB
callq _Znam
movq %rax, %rbx
leaq 8(%rsp), %rdi
movl $12011, %esi # imm = 0x2EEB
callq hipMalloc
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 98(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq 8(%rsp), %rax
movq %rax, 72(%rsp)
leaq 72(%rsp), %rax
movq %rax, 16(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z8bottle99Pc, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
movq 8(%rsp), %rsi
movl $12011, %edx # imm = 0x2EEB
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq puts
movq %rbx, %rdi
callq free
xorl %eax, %eax
addq $80, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rbx
subq $32, %rsp
.cfi_adjust_cfa_offset 32
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8bottle99Pc, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
addq $32, %rsp
.cfi_adjust_cfa_offset -32
movl $text, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movl $121, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
pushq $0
.cfi_adjust_cfa_offset 8
pushq $0
.cfi_adjust_cfa_offset 8
callq __hipRegisterVar
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movl $end, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movl $251, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
pushq $0
.cfi_adjust_cfa_offset 8
pushq $0
.cfi_adjust_cfa_offset 8
callq __hipRegisterVar
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movl $__hip_module_dtor, %edi
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type text,@object # @text
.local text
.comm text,121,16
.type end,@object # @end
.local end
.comm end,251,16
.type _Z8bottle99Pc,@object # @_Z8bottle99Pc
.section .rodata,"a",@progbits
.globl _Z8bottle99Pc
.p2align 3, 0x0
_Z8bottle99Pc:
.quad _Z23__device_stub__bottle99Pc
.size _Z8bottle99Pc, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z8bottle99Pc"
.size .L__unnamed_1, 14
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "text"
.size .L__unnamed_2, 5
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "end"
.size .L__unnamed_3, 4
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__bottle99Pc
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym text
.addrsig_sym end
.addrsig_sym _Z8bottle99Pc
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z8bottle99Pc
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R17, SR_TID.X ; /* 0x0000000000117919 */
/* 0x000e220000002100 */
/*0020*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*0030*/ IADD3 R0, -R17, 0x63, RZ ; /* 0x0000006311007810 */
/* 0x001fc80007ffe1ff */
/*0040*/ ISETP.NE.AND P0, PT, R0, 0x1, PT ; /* 0x000000010000780c */
/* 0x000fda0003f05270 */
/*0050*/ @!P0 BRA 0x2b0 ; /* 0x0000025000008947 */
/* 0x000fea0003800000 */
/*0060*/ IADD3 R4, R0.reuse, -0x1, RZ ; /* 0xffffffff00047810 */
/* 0x040fe20007ffe0ff */
/*0070*/ IMAD.HI R2, R0, 0x66666667, RZ ; /* 0x6666666700027827 */
/* 0x000fc800078e02ff */
/*0080*/ IMAD.HI R5, R4, 0x66666667, RZ ; /* 0x6666666704057827 */
/* 0x000fe200078e02ff */
/*0090*/ SHF.R.U32.HI R3, RZ, 0x1f, R2 ; /* 0x0000001fff037819 */
/* 0x000fc60000011602 */
/*00a0*/ IMAD.MOV.U32 R15, RZ, RZ, RZ ; /* 0x000000ffff0f7224 */
/* 0x000fe200078e00ff */
/*00b0*/ SHF.R.U32.HI R6, RZ, 0x1f, R5 ; /* 0x0000001fff067819 */
/* 0x000fe40000011605 */
/*00c0*/ LEA.HI.SX32 R3, R2, R3, 0x1e ; /* 0x0000000302037211 */
/* 0x000fe400078ff2ff */
/*00d0*/ LEA.HI.SX32 R5, R5, R6, 0x1e ; /* 0x0000000605057211 */
/* 0x000fe400078ff2ff */
/*00e0*/ IADD3 R7, R3.reuse, 0x30, RZ ; /* 0x0000003003077810 */
/* 0x040fe20007ffe0ff */
/*00f0*/ IMAD R0, R3, -0xa, R0 ; /* 0xfffffff603007824 */
/* 0x000fe200078e0200 */
/*0100*/ IADD3 R11, R5.reuse, 0x30, RZ ; /* 0x00000030050b7810 */
/* 0x040fe20007ffe0ff */
/*0110*/ IMAD R4, R5, -0xa, R4 ; /* 0xfffffff605047824 */
/* 0x000fc600078e0204 */
/*0120*/ IADD3 R9, R0, 0x30, RZ ; /* 0x0000003000097810 */
/* 0x000fe40007ffe0ff */
/*0130*/ IADD3 R13, R4, 0x30, RZ ; /* 0x00000030040d7810 */
/* 0x000fe40007ffe0ff */
/*0140*/ SHF.R.S32.HI R3, RZ, 0x1f, R15 ; /* 0x0000001fff037819 */
/* 0x001fe4000001140f */
/*0150*/ IADD3 R4, P0, R15, c[0x4][0x0], RZ ; /* 0x010000000f047a10 */
/* 0x000fc80007f1e0ff */
/*0160*/ IADD3.X R5, R3, c[0x4][0x4], RZ, P0, !PT ; /* 0x0100010003057a10 */
/* 0x000fcc00007fe4ff */
/*0170*/ LDG.E.U8 R5, [R4.64] ; /* 0x0000000604057981 */
/* 0x000ea2000c1e1100 */
/*0180*/ IMAD.MOV.U32 R2, RZ, RZ, R15 ; /* 0x000000ffff027224 */
/* 0x000fc800078e000f */
/*0190*/ IMAD.WIDE R2, R17, 0x78, R2 ; /* 0x0000007811027825 */
/* 0x000fca00078e0202 */
/*01a0*/ IADD3 R2, P1, R2, c[0x0][0x160], RZ ; /* 0x0000580002027a10 */
/* 0x000fc80007f3e0ff */
/*01b0*/ IADD3.X R3, R3, c[0x0][0x164], RZ, P1, !PT ; /* 0x0000590003037a10 */
/* 0x000fe40000ffe4ff */
/*01c0*/ ISETP.NE.AND P0, PT, R5, 0x5f, PT ; /* 0x0000005f0500780c */
/* 0x004fda0003f05270 */
/*01d0*/ @!P0 BRA 0x240 ; /* 0x0000006000008947 */
/* 0x000fea0003800000 */
/*01e0*/ ISETP.NE.AND P0, PT, R5, 0x23, PT ; /* 0x000000230500780c */
/* 0x000fda0003f05270 */
/*01f0*/ @P0 STG.E.U8 [R2.64], R5 ; /* 0x0000000502000986 */
/* 0x0001e2000c101106 */
/*0200*/ @!P0 IADD3 R15, R15, 0x1, RZ ; /* 0x000000010f0f8810 */
/* 0x000fc60007ffe0ff */
/*0210*/ @!P0 STG.E.U8 [R2.64+0x1], R13 ; /* 0x0000010d02008986 */
/* 0x0001e8000c101106 */
/*0220*/ @!P0 STG.E.U8 [R2.64], R11 ; /* 0x0000000b02008986 */
/* 0x0001e2000c101106 */
/*0230*/ BRA 0x270 ; /* 0x0000003000007947 */
/* 0x000fea0003800000 */
/*0240*/ STG.E.U8 [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x0001e2000c101106 */
/*0250*/ IADD3 R15, R15, 0x1, RZ ; /* 0x000000010f0f7810 */
/* 0x000fc60007ffe0ff */
/*0260*/ STG.E.U8 [R2.64+0x1], R9 ; /* 0x0000010902007986 */
/* 0x0001e8000c101106 */
/*0270*/ IADD3 R15, R15, 0x1, RZ ; /* 0x000000010f0f7810 */
/* 0x000fc80007ffe0ff */
/*0280*/ ISETP.GE.U32.AND P0, PT, R15, 0x78, PT ; /* 0x000000780f00780c */
/* 0x000fda0003f06070 */
/*0290*/ @!P0 BRA 0x140 ; /* 0xfffffea000008947 */
/* 0x000fea000383ffff */
/*02a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*02b0*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x8] ; /* 0x01000200ff047624 */
/* 0x000fe200078e00ff */
/*02c0*/ ULDC.64 UR4, c[0x4][0x8] ; /* 0x0100020000047ab9 */
/* 0x000fe20000000a00 */
/*02d0*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0xc] ; /* 0x01000300ff057624 */
/* 0x000fca00078e00ff */
/*02e0*/ LDG.E.U8 R7, [R4.64] ; /* 0x0000000604077981 */
/* 0x000ea2000c1e1100 */
/*02f0*/ IMAD.MOV.U32 R2, RZ, RZ, 0x78 ; /* 0x00000078ff027424 */
/* 0x000fc800078e00ff */
/*0300*/ IMAD.WIDE R2, R17, R2, c[0x0][0x160] ; /* 0x0000580011027625 */
/* 0x000fca00078e0202 */
/*0310*/ STG.E.U8 [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x0041e8000c101106 */
/*0320*/ LDG.E.U8 R9, [R4.64+0x1] ; /* 0x0000010604097981 */
/* 0x000ea2000c1e1100 */
/*0330*/ UIADD3 UR4, UP0, UR4, 0x2, URZ ; /* 0x0000000204047890 */
/* 0x000fe2000ff1e03f */
/*0340*/ IADD3 R10, P0, R2, 0x3, RZ ; /* 0x00000003020a7810 */
/* 0x000fe20007f1e0ff */
/*0350*/ IMAD.MOV.U32 R0, RZ, RZ, 0x2 ; /* 0x00000002ff007424 */
/* 0x000fe400078e00ff */
/*0360*/ UIADD3.X UR5, URZ, UR5, URZ, UP0, !UPT ; /* 0x000000053f057290 */
/* 0x000fe400087fe43f */
/*0370*/ IMAD.U32 R8, RZ, RZ, UR4 ; /* 0x00000004ff087e24 */
/* 0x000fc4000f8e00ff */
/*0380*/ IMAD.X R15, RZ, RZ, R3, P0 ; /* 0x000000ffff0f7224 */
/* 0x000fe400000e0603 */
/*0390*/ IMAD.U32 R13, RZ, RZ, UR5 ; /* 0x00000005ff0d7e24 */
/* 0x000fe2000f8e00ff */
/*03a0*/ STG.E.U8 [R2.64+0x1], R9 ; /* 0x0000010902007986 */
/* 0x0041e8000c101106 */
/*03b0*/ IMAD.MOV.U32 R4, RZ, RZ, R8 ; /* 0x000000ffff047224 */
/* 0x000fe400078e0008 */
/*03c0*/ IMAD.MOV.U32 R5, RZ, RZ, R13 ; /* 0x000000ffff057224 */
/* 0x000fca00078e000d */
/*03d0*/ LDG.E.U8 R9, [R4.64] ; /* 0x0000000604097981 */
/* 0x009ea2000c1e1100 */
/*03e0*/ IMAD.MOV.U32 R6, RZ, RZ, R10 ; /* 0x000000ffff067224 */
/* 0x000fe400078e000a */
/*03f0*/ IMAD.MOV.U32 R7, RZ, RZ, R15 ; /* 0x000000ffff077224 */
/* 0x000fca00078e000f */
/*0400*/ STG.E.U8 [R6.64+-0x1], R9 ; /* 0xffffff0906007986 */
/* 0x0041e8000c101106 */
/*0410*/ LDG.E.U8 R11, [R4.64+0x1] ; /* 0x00000106040b7981 */
/* 0x000ea8000c1e1100 */
/*0420*/ STG.E.U8 [R6.64], R11 ; /* 0x0000000b06007986 */
/* 0x0043e8000c101106 */
/*0430*/ LDG.E.U8 R13, [R4.64+0x2] ; /* 0x00000206040d7981 */
/* 0x000ea8000c1e1100 */
/*0440*/ STG.E.U8 [R6.64+0x1], R13 ; /* 0x0000010d06007986 */
/* 0x0045e8000c101106 */
/*0450*/ LDG.E.U8 R15, [R4.64+0x3] ; /* 0x00000306040f7981 */
/* 0x000ee8000c1e1100 */
/*0460*/ STG.E.U8 [R6.64+0x2], R15 ; /* 0x0000020f06007986 */
/* 0x0087e8000c101106 */
/*0470*/ LDG.E.U8 R17, [R4.64+0x4] ; /* 0x0000040604117981 */
/* 0x000f28000c1e1100 */
/*0480*/ STG.E.U8 [R6.64+0x3], R17 ; /* 0x0000031106007986 */
/* 0x0109e8000c101106 */
/*0490*/ LDG.E.U8 R19, [R4.64+0x5] ; /* 0x0000050604137981 */
/* 0x000f68000c1e1100 */
/*04a0*/ STG.E.U8 [R6.64+0x4], R19 ; /* 0x0000041306007986 */
/* 0x020be8000c101106 */
/*04b0*/ LDG.E.U8 R9, [R4.64+0x6] ; /* 0x0000060604097981 */
/* 0x001ea8000c1e1100 */
/*04c0*/ STG.E.U8 [R6.64+0x5], R9 ; /* 0x0000050906007986 */
/* 0x0041e8000c101106 */
/*04d0*/ LDG.E.U8 R11, [R4.64+0x7] ; /* 0x00000706040b7981 */
/* 0x002ea8000c1e1100 */
/*04e0*/ STG.E.U8 [R6.64+0x6], R11 ; /* 0x0000060b06007986 */
/* 0x0043e8000c101106 */
/*04f0*/ LDG.E.U8 R13, [R4.64+0x8] ; /* 0x00000806040d7981 */
/* 0x000ea8000c1e1100 */
/*0500*/ STG.E.U8 [R6.64+0x7], R13 ; /* 0x0000070d06007986 */
/* 0x0045e8000c101106 */
/*0510*/ LDG.E.U8 R15, [R4.64+0x9] ; /* 0x00000906040f7981 */
/* 0x008ee8000c1e1100 */
/*0520*/ STG.E.U8 [R6.64+0x8], R15 ; /* 0x0000080f06007986 */
/* 0x0087e8000c101106 */
/*0530*/ LDG.E.U8 R17, [R4.64+0xa] ; /* 0x00000a0604117981 */
/* 0x010f28000c1e1100 */
/*0540*/ STG.E.U8 [R6.64+0x9], R17 ; /* 0x0000091106007986 */
/* 0x0109e8000c101106 */
/*0550*/ LDG.E.U8 R19, [R4.64+0xb] ; /* 0x00000b0604137981 */
/* 0x020f68000c1e1100 */
/*0560*/ STG.E.U8 [R6.64+0xa], R19 ; /* 0x00000a1306007986 */
/* 0x020be8000c101106 */
/*0570*/ LDG.E.U8 R9, [R4.64+0xc] ; /* 0x00000c0604097981 */
/* 0x001ea8000c1e1100 */
/*0580*/ STG.E.U8 [R6.64+0xb], R9 ; /* 0x00000b0906007986 */
/* 0x0041e8000c101106 */
/*0590*/ LDG.E.U8 R11, [R4.64+0xd] ; /* 0x00000d06040b7981 */
/* 0x002ea8000c1e1100 */
/*05a0*/ STG.E.U8 [R6.64+0xc], R11 ; /* 0x00000c0b06007986 */
/* 0x0043e8000c101106 */
/*05b0*/ LDG.E.U8 R13, [R4.64+0xe] ; /* 0x00000e06040d7981 */
/* 0x000ea8000c1e1100 */
/*05c0*/ STG.E.U8 [R6.64+0xd], R13 ; /* 0x00000d0d06007986 */
/* 0x0045e8000c101106 */
/*05d0*/ LDG.E.U8 R15, [R4.64+0xf] ; /* 0x00000f06040f7981 */
/* 0x008ee8000c1e1100 */
/*05e0*/ STG.E.U8 [R6.64+0xe], R15 ; /* 0x00000e0f06007986 */
/* 0x0087e8000c101106 */
/*05f0*/ LDG.E.U8 R17, [R4.64+0x10] ; /* 0x0000100604117981 */
/* 0x010f28000c1e1100 */
/*0600*/ STG.E.U8 [R6.64+0xf], R17 ; /* 0x00000f1106007986 */
/* 0x0109e8000c101106 */
/*0610*/ LDG.E.U8 R19, [R4.64+0x11] ; /* 0x0000110604137981 */
/* 0x020f68000c1e1100 */
/*0620*/ STG.E.U8 [R6.64+0x10], R19 ; /* 0x0000101306007986 */
/* 0x020be8000c101106 */
/*0630*/ LDG.E.U8 R9, [R4.64+0x12] ; /* 0x0000120604097981 */
/* 0x001ea8000c1e1100 */
/*0640*/ STG.E.U8 [R6.64+0x11], R9 ; /* 0x0000110906007986 */
/* 0x0041e8000c101106 */
/*0650*/ LDG.E.U8 R11, [R4.64+0x13] ; /* 0x00001306040b7981 */
/* 0x002ea8000c1e1100 */
/*0660*/ STG.E.U8 [R6.64+0x12], R11 ; /* 0x0000120b06007986 */
/* 0x0043e8000c101106 */
/*0670*/ LDG.E.U8 R13, [R4.64+0x14] ; /* 0x00001406040d7981 */
/* 0x000ea8000c1e1100 */
/*0680*/ STG.E.U8 [R6.64+0x13], R13 ; /* 0x0000130d06007986 */
/* 0x0045e8000c101106 */
/*0690*/ LDG.E.U8 R15, [R4.64+0x15] ; /* 0x00001506040f7981 */
/* 0x008ee8000c1e1100 */
/*06a0*/ STG.E.U8 [R6.64+0x14], R15 ; /* 0x0000140f06007986 */
/* 0x0087e8000c101106 */
/*06b0*/ LDG.E.U8 R17, [R4.64+0x16] ; /* 0x0000160604117981 */
/* 0x010f28000c1e1100 */
/*06c0*/ STG.E.U8 [R6.64+0x15], R17 ; /* 0x0000151106007986 */
/* 0x0109e8000c101106 */
/*06d0*/ LDG.E.U8 R19, [R4.64+0x17] ; /* 0x0000170604137981 */
/* 0x020f68000c1e1100 */
/*06e0*/ STG.E.U8 [R6.64+0x16], R19 ; /* 0x0000161306007986 */
/* 0x020be8000c101106 */
/*06f0*/ LDG.E.U8 R9, [R4.64+0x18] ; /* 0x0000180604097981 */
/* 0x001ea8000c1e1100 */
/*0700*/ STG.E.U8 [R6.64+0x17], R9 ; /* 0x0000170906007986 */
/* 0x0041e8000c101106 */
/*0710*/ LDG.E.U8 R11, [R4.64+0x19] ; /* 0x00001906040b7981 */
/* 0x002ea8000c1e1100 */
/*0720*/ STG.E.U8 [R6.64+0x18], R11 ; /* 0x0000180b06007986 */
/* 0x0043e8000c101106 */
/*0730*/ LDG.E.U8 R13, [R4.64+0x1a] ; /* 0x00001a06040d7981 */
/* 0x000ea8000c1e1100 */
/*0740*/ STG.E.U8 [R6.64+0x19], R13 ; /* 0x0000190d06007986 */
/* 0x0045e8000c101106 */
/*0750*/ LDG.E.U8 R15, [R4.64+0x1b] ; /* 0x00001b06040f7981 */
/* 0x008ee8000c1e1100 */
/*0760*/ STG.E.U8 [R6.64+0x1a], R15 ; /* 0x00001a0f06007986 */
/* 0x0087e8000c101106 */
/*0770*/ LDG.E.U8 R17, [R4.64+0x1c] ; /* 0x00001c0604117981 */
/* 0x010f28000c1e1100 */
/*0780*/ STG.E.U8 [R6.64+0x1b], R17 ; /* 0x00001b1106007986 */
/* 0x0109e8000c101106 */
/*0790*/ LDG.E.U8 R19, [R4.64+0x1d] ; /* 0x00001d0604137981 */
/* 0x020f68000c1e1100 */
/*07a0*/ STG.E.U8 [R6.64+0x1c], R19 ; /* 0x00001c1306007986 */
/* 0x020be8000c101106 */
/*07b0*/ LDG.E.U8 R9, [R4.64+0x1e] ; /* 0x00001e0604097981 */
/* 0x001ea8000c1e1100 */
/*07c0*/ STG.E.U8 [R6.64+0x1d], R9 ; /* 0x00001d0906007986 */
/* 0x0041e8000c101106 */
/*07d0*/ LDG.E.U8 R11, [R4.64+0x1f] ; /* 0x00001f06040b7981 */
/* 0x002ea8000c1e1100 */
/*07e0*/ STG.E.U8 [R6.64+0x1e], R11 ; /* 0x00001e0b06007986 */
/* 0x0043e8000c101106 */
/*07f0*/ LDG.E.U8 R13, [R4.64+0x20] ; /* 0x00002006040d7981 */
/* 0x000ea8000c1e1100 */
/*0800*/ STG.E.U8 [R6.64+0x1f], R13 ; /* 0x00001f0d06007986 */
/* 0x0045e8000c101106 */
/*0810*/ LDG.E.U8 R15, [R4.64+0x21] ; /* 0x00002106040f7981 */
/* 0x008ee8000c1e1100 */
/*0820*/ STG.E.U8 [R6.64+0x20], R15 ; /* 0x0000200f06007986 */
/* 0x0087e8000c101106 */
/*0830*/ LDG.E.U8 R17, [R4.64+0x22] ; /* 0x0000220604117981 */
/* 0x010f28000c1e1100 */
/*0840*/ STG.E.U8 [R6.64+0x21], R17 ; /* 0x0000211106007986 */
/* 0x0109e8000c101106 */
/*0850*/ LDG.E.U8 R19, [R4.64+0x23] ; /* 0x0000230604137981 */
/* 0x020f68000c1e1100 */
/*0860*/ STG.E.U8 [R6.64+0x22], R19 ; /* 0x0000221306007986 */
/* 0x020be8000c101106 */
/*0870*/ LDG.E.U8 R9, [R4.64+0x24] ; /* 0x0000240604097981 */
/* 0x001ea8000c1e1100 */
/*0880*/ STG.E.U8 [R6.64+0x23], R9 ; /* 0x0000230906007986 */
/* 0x0041e8000c101106 */
/*0890*/ LDG.E.U8 R11, [R4.64+0x25] ; /* 0x00002506040b7981 */
/* 0x002ea8000c1e1100 */
/*08a0*/ STG.E.U8 [R6.64+0x24], R11 ; /* 0x0000240b06007986 */
/* 0x0043e8000c101106 */
/*08b0*/ LDG.E.U8 R13, [R4.64+0x26] ; /* 0x00002606040d7981 */
/* 0x000ea8000c1e1100 */
/*08c0*/ STG.E.U8 [R6.64+0x25], R13 ; /* 0x0000250d06007986 */
/* 0x0045e8000c101106 */
/*08d0*/ LDG.E.U8 R15, [R4.64+0x27] ; /* 0x00002706040f7981 */
/* 0x008ee8000c1e1100 */
/*08e0*/ STG.E.U8 [R6.64+0x26], R15 ; /* 0x0000260f06007986 */
/* 0x0087e8000c101106 */
/*08f0*/ LDG.E.U8 R17, [R4.64+0x28] ; /* 0x0000280604117981 */
/* 0x010f28000c1e1100 */
/*0900*/ STG.E.U8 [R6.64+0x27], R17 ; /* 0x0000271106007986 */
/* 0x0109e8000c101106 */
/*0910*/ LDG.E.U8 R19, [R4.64+0x29] ; /* 0x0000290604137981 */
/* 0x020f68000c1e1100 */
/*0920*/ STG.E.U8 [R6.64+0x28], R19 ; /* 0x0000281306007986 */
/* 0x020be8000c101106 */
/*0930*/ LDG.E.U8 R9, [R4.64+0x2a] ; /* 0x00002a0604097981 */
/* 0x001ea8000c1e1100 */
/*0940*/ STG.E.U8 [R6.64+0x29], R9 ; /* 0x0000290906007986 */
/* 0x0041e8000c101106 */
/*0950*/ LDG.E.U8 R11, [R4.64+0x2b] ; /* 0x00002b06040b7981 */
/* 0x002ea8000c1e1100 */
/*0960*/ STG.E.U8 [R6.64+0x2a], R11 ; /* 0x00002a0b06007986 */
/* 0x0043e8000c101106 */
/*0970*/ LDG.E.U8 R13, [R4.64+0x2c] ; /* 0x00002c06040d7981 */
/* 0x000ea8000c1e1100 */
/*0980*/ STG.E.U8 [R6.64+0x2b], R13 ; /* 0x00002b0d06007986 */
/* 0x0045e8000c101106 */
/*0990*/ LDG.E.U8 R15, [R4.64+0x2d] ; /* 0x00002d06040f7981 */
/* 0x008ee8000c1e1100 */
/*09a0*/ STG.E.U8 [R6.64+0x2c], R15 ; /* 0x00002c0f06007986 */
/* 0x0087e8000c101106 */
/*09b0*/ LDG.E.U8 R17, [R4.64+0x2e] ; /* 0x00002e0604117981 */
/* 0x010f28000c1e1100 */
/*09c0*/ STG.E.U8 [R6.64+0x2d], R17 ; /* 0x00002d1106007986 */
/* 0x0109e8000c101106 */
/*09d0*/ LDG.E.U8 R19, [R4.64+0x2f] ; /* 0x00002f0604137981 */
/* 0x020f68000c1e1100 */
/*09e0*/ STG.E.U8 [R6.64+0x2e], R19 ; /* 0x00002e1306007986 */
/* 0x020be8000c101106 */
/*09f0*/ LDG.E.U8 R9, [R4.64+0x30] ; /* 0x0000300604097981 */
/* 0x001ea8000c1e1100 */
/*0a00*/ STG.E.U8 [R6.64+0x2f], R9 ; /* 0x00002f0906007986 */
/* 0x0041e8000c101106 */
/*0a10*/ LDG.E.U8 R11, [R4.64+0x31] ; /* 0x00003106040b7981 */
/* 0x002ea8000c1e1100 */
/*0a20*/ STG.E.U8 [R6.64+0x30], R11 ; /* 0x0000300b06007986 */
/* 0x0043e8000c101106 */
/*0a30*/ LDG.E.U8 R13, [R4.64+0x32] ; /* 0x00003206040d7981 */
/* 0x000ea8000c1e1100 */
/*0a40*/ STG.E.U8 [R6.64+0x31], R13 ; /* 0x0000310d06007986 */
/* 0x0045e8000c101106 */
/*0a50*/ LDG.E.U8 R15, [R4.64+0x33] ; /* 0x00003306040f7981 */
/* 0x008ee8000c1e1100 */
/*0a60*/ STG.E.U8 [R6.64+0x32], R15 ; /* 0x0000320f06007986 */
/* 0x0087e8000c101106 */
/*0a70*/ LDG.E.U8 R17, [R4.64+0x34] ; /* 0x0000340604117981 */
/* 0x010f28000c1e1100 */
/*0a80*/ STG.E.U8 [R6.64+0x33], R17 ; /* 0x0000331106007986 */
/* 0x0109e8000c101106 */
/*0a90*/ LDG.E.U8 R19, [R4.64+0x35] ; /* 0x0000350604137981 */
/* 0x020f68000c1e1100 */
/*0aa0*/ STG.E.U8 [R6.64+0x34], R19 ; /* 0x0000341306007986 */
/* 0x020be8000c101106 */
/*0ab0*/ LDG.E.U8 R9, [R4.64+0x36] ; /* 0x0000360604097981 */
/* 0x001ea8000c1e1100 */
/*0ac0*/ STG.E.U8 [R6.64+0x35], R9 ; /* 0x0000350906007986 */
/* 0x0041e8000c101106 */
/*0ad0*/ LDG.E.U8 R11, [R4.64+0x37] ; /* 0x00003706040b7981 */
/* 0x002ea8000c1e1100 */
/*0ae0*/ STG.E.U8 [R6.64+0x36], R11 ; /* 0x0000360b06007986 */
/* 0x0043e8000c101106 */
/*0af0*/ LDG.E.U8 R13, [R4.64+0x38] ; /* 0x00003806040d7981 */
/* 0x000ea8000c1e1100 */
/*0b00*/ STG.E.U8 [R6.64+0x37], R13 ; /* 0x0000370d06007986 */
/* 0x004fe8000c101106 */
/*0b10*/ LDG.E.U8 R15, [R4.64+0x39] ; /* 0x00003906040f7981 */
/* 0x008ea8000c1e1100 */
/*0b20*/ STG.E.U8 [R6.64+0x38], R15 ; /* 0x0000380f06007986 */
/* 0x0045e8000c101106 */
/*0b30*/ LDG.E.U8 R17, [R4.64+0x3a] ; /* 0x00003a0604117981 */
/* 0x010ee8000c1e1100 */
/*0b40*/ STG.E.U8 [R6.64+0x39], R17 ; /* 0x0000391106007986 */
/* 0x0087e8000c101106 */
/*0b50*/ LDG.E.U8 R19, [R4.64+0x3b] ; /* 0x00003b0604137981 */
/* 0x020f28000c1e1100 */
/*0b60*/ STG.E.U8 [R6.64+0x3a], R19 ; /* 0x00003a1306007986 */
/* 0x0107e8000c101106 */
/*0b70*/ LDG.E.U8 R9, [R4.64+0x3c] ; /* 0x00003c0604097981 */
/* 0x001f28000c1e1100 */
/*0b80*/ STG.E.U8 [R6.64+0x3b], R9 ; /* 0x00003b0906007986 */
/* 0x0107e8000c101106 */
/*0b90*/ LDG.E.U8 R11, [R4.64+0x3d] ; /* 0x00003d06040b7981 */
/* 0x002f22000c1e1100 */
/*0ba0*/ IADD3 R0, R0, 0x3e, RZ ; /* 0x0000003e00007810 */
/* 0x000fc40007ffe0ff */
/*0bb0*/ IADD3 R10, P1, R6, 0x3e, RZ ; /* 0x0000003e060a7810 */
/* 0x000fe40007f3e0ff */
/*0bc0*/ ISETP.NE.AND P0, PT, R0, 0xfa, PT ; /* 0x000000fa0000780c */
/* 0x000fe40003f05270 */
/*0bd0*/ IADD3 R8, P2, R4, 0x3e, RZ ; /* 0x0000003e04087810 */
/* 0x000fe20007f5e0ff */
/*0be0*/ IMAD.X R15, RZ, RZ, R7, P1 ; /* 0x000000ffff0f7224 */
/* 0x004fc800008e0607 */
/*0bf0*/ IMAD.X R13, RZ, RZ, R5, P2 ; /* 0x000000ffff0d7224 */
/* 0x000fe200010e0605 */
/*0c00*/ STG.E.U8 [R6.64+0x3c], R11 ; /* 0x00003c0b06007986 */
/* 0x0107ea000c101106 */
/*0c10*/ @P0 BRA 0x3b0 ; /* 0xfffff79000000947 */
/* 0x000fea000383ffff */
/*0c20*/ STG.E.U8 [R2.64+0xfa], RZ ; /* 0x0000faff02007986 */
/* 0x000fe2000c101106 */
/*0c30*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0c40*/ BRA 0xc40; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0c50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ca0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ce0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z8bottle99Pc
.globl _Z8bottle99Pc
.p2align 8
.type _Z8bottle99Pc,@function
_Z8bottle99Pc:
s_load_b64 s[0:1], s[0:1], 0x0
v_mul_u32_u24_e32 v1, 0x78, v0
v_mov_b32_e32 v5, 0
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v1, s0, s0, v1
v_add_co_ci_u32_e64 v2, null, s1, 0, s0
s_mov_b32 s0, exec_lo
v_cmpx_ne_u32_e32 0x62, v0
s_xor_b32 s2, exec_lo, s0
s_cbranch_execz .LBB0_13
v_sub_nc_u32_e32 v3, 0x63, v0
v_sub_nc_u32_e32 v0, 0x62, v0
s_mov_b32 s3, 0
s_mov_b64 s[0:1], 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_hi_i32 v4, v3, 0x66666667
v_mul_hi_i32 v6, v0, 0x66666667
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_lshrrev_b32_e32 v7, 31, v4
v_ashrrev_i32_e32 v4, 2, v4
v_lshrrev_b32_e32 v8, 31, v6
v_ashrrev_i32_e32 v6, 2, v6
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v4, v4, v7
v_add_nc_u32_e32 v6, v6, v8
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_lo_u32 v7, v4, 10
v_mul_lo_u32 v8, v6, 10
v_add_nc_u16 v6, v6, 48
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_sub_nc_u32_e32 v3, v3, v7
v_sub_nc_u32_e32 v8, v0, v8
v_add_nc_u16 v0, v4, 48
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_nc_u16 v7, v3, 48
v_add_nc_u16 v8, v8, 48
s_branch .LBB0_3
.LBB0_2:
s_add_i32 s0, s0, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_ashr_i32 s1, s0, 31
s_cmpk_lt_u32 s0, 0x78
s_mov_b32 s3, s0
s_cbranch_scc0 .LBB0_13
.LBB0_3:
s_getpc_b64 s[4:5]
s_add_u32 s4, s4, text@rel32@lo+4
s_addc_u32 s5, s5, text@rel32@hi+12
s_add_u32 s4, s0, s4
s_addc_u32 s5, s1, s5
v_add_co_u32 v3, s0, v1, s0
global_load_u8 v9, v5, s[4:5]
v_add_co_ci_u32_e64 v4, s0, s1, v2, s0
s_mov_b32 s5, -1
s_mov_b32 s1, 0
s_mov_b32 s4, 0
s_waitcnt vmcnt(0)
v_cmp_gt_i16_e32 vcc_lo, 0x5f, v9
s_cbranch_vccz .LBB0_7
s_and_b32 vcc_lo, exec_lo, s5
s_cbranch_vccnz .LBB0_10
.LBB0_5:
s_and_not1_b32 vcc_lo, exec_lo, s4
s_cbranch_vccz .LBB0_11
.LBB0_6:
s_and_not1_b32 vcc_lo, exec_lo, s1
s_cbranch_vccnz .LBB0_2
s_branch .LBB0_12
.LBB0_7:
v_cmp_eq_u16_e32 vcc_lo, 0x5f, v9
s_mov_b32 s4, -1
s_cbranch_vccz .LBB0_9
s_add_i32 s0, s3, 1
global_store_b8 v[3:4], v0, off
v_add_co_u32 v10, vcc_lo, v1, s0
v_add_co_ci_u32_e32 v11, vcc_lo, 0, v2, vcc_lo
s_mov_b32 s4, 0
global_store_b8 v[10:11], v7, off
.LBB0_9:
s_branch .LBB0_5
.LBB0_10:
v_cmp_ne_u16_e64 s4, 35, v9
s_mov_b32 s1, -1
s_delay_alu instid0(VALU_DEP_1)
s_and_not1_b32 vcc_lo, exec_lo, s4
s_cbranch_vccnz .LBB0_6
.LBB0_11:
s_mov_b32 s0, s3
global_store_b8 v[3:4], v9, off
s_cbranch_execnz .LBB0_2
.LBB0_12:
s_add_i32 s0, s3, 1
s_delay_alu instid0(SALU_CYCLE_1)
v_add_co_u32 v9, vcc_lo, v1, s0
v_add_co_ci_u32_e32 v10, vcc_lo, 0, v2, vcc_lo
s_clause 0x1
global_store_b8 v[3:4], v6, off
global_store_b8 v[9:10], v8, off
s_branch .LBB0_2
.LBB0_13:
s_and_not1_saveexec_b32 s0, s2
s_cbranch_execz .LBB0_17
v_mov_b32_e32 v0, 0
s_mov_b64 s[0:1], 0
.p2align 6
.LBB0_15:
s_getpc_b64 s[2:3]
s_add_u32 s2, s2, end@rel32@lo+4
s_addc_u32 s3, s3, end@rel32@hi+12
s_add_u32 s2, s0, s2
s_addc_u32 s3, s1, s3
v_add_co_u32 v3, vcc_lo, v1, s0
global_load_u8 v5, v0, s[2:3]
v_add_co_ci_u32_e32 v4, vcc_lo, s1, v2, vcc_lo
s_add_u32 s0, s0, 1
s_addc_u32 s1, s1, 0
s_cmpk_eq_i32 s0, 0xfa
s_waitcnt vmcnt(0)
global_store_b8 v[3:4], v5, off
s_cbranch_scc0 .LBB0_15
v_mov_b32_e32 v0, 0
global_store_b8 v[1:2], v0, off offset:250
.LBB0_17:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8bottle99Pc
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 8
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 12
.amdhsa_next_free_sgpr 6
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z8bottle99Pc, .Lfunc_end0-_Z8bottle99Pc
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.protected text
.type text,@object
.data
.globl text
.p2align 4, 0x0
text:
.asciz "__ bottles of beer on the wall, __ bottles of beer!\nTake one down, and pass it around, ## bottles of beer on the wall!\n\n"
.size text, 121
.protected end
.type end,@object
.globl end
.p2align 4, 0x0
end:
.asciz "01 bottle of beer on the wall, 01 bottle of beer.\nTake one down and pass it around, no more bottles of beer on the wall.\n\nNo more bottles of beer on the wall, no more bottles of beer.\nGo to the store and buy some more, 99 bottles of beer on the wall."
.size end, 251
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym text
.addrsig_sym end
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 8
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8bottle99Pc
.private_segment_fixed_size: 0
.sgpr_count: 8
.sgpr_spill_count: 0
.symbol: _Z8bottle99Pc.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 12
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000c038e_00000000-6_99bear.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z27__device_stub__Z8bottle99PcPc
.type _Z27__device_stub__Z8bottle99PcPc, @function
_Z27__device_stub__Z8bottle99PcPc:
.LFB2082:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z8bottle99Pc(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z27__device_stub__Z8bottle99PcPc, .-_Z27__device_stub__Z8bottle99PcPc
.globl _Z8bottle99Pc
.type _Z8bottle99Pc, @function
_Z8bottle99Pc:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z27__device_stub__Z8bottle99PcPc
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z8bottle99Pc, .-_Z8bottle99Pc
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $48, %rsp
.cfi_def_cfa_offset 64
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movl $12011, %edi
call _Znam@PLT
movq %rax, %rbx
leaq 8(%rsp), %rdi
movl $12011, %esi
call cudaMalloc@PLT
movl $99, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L15
.L12:
movl $2, %ecx
movl $12011, %edx
movq 8(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq %rbx, %rdi
call puts@PLT
movq %rbx, %rdi
call free@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L16
movl $0, %eax
addq $48, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
movq 8(%rsp), %rdi
call _Z27__device_stub__Z8bottle99PcPc
jmp .L12
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z8bottle99Pc"
.LC1:
.string "text"
.LC2:
.string "end"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z8bottle99Pc(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $121, %r9d
movl $0, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _ZL4text(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $251, %r9d
movl $0, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _ZL3end(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL3end
.comm _ZL3end,251,32
.local _ZL4text
.comm _ZL4text,121,32
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "99bear.hip"
.globl _Z23__device_stub__bottle99Pc # -- Begin function _Z23__device_stub__bottle99Pc
.p2align 4, 0x90
.type _Z23__device_stub__bottle99Pc,@function
_Z23__device_stub__bottle99Pc: # @_Z23__device_stub__bottle99Pc
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z8bottle99Pc, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size _Z23__device_stub__bottle99Pc, .Lfunc_end0-_Z23__device_stub__bottle99Pc
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $80, %rsp
.cfi_def_cfa_offset 96
.cfi_offset %rbx, -16
movl $12011, %edi # imm = 0x2EEB
callq _Znam
movq %rax, %rbx
leaq 8(%rsp), %rdi
movl $12011, %esi # imm = 0x2EEB
callq hipMalloc
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 98(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq 8(%rsp), %rax
movq %rax, 72(%rsp)
leaq 72(%rsp), %rax
movq %rax, 16(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z8bottle99Pc, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
movq 8(%rsp), %rsi
movl $12011, %edx # imm = 0x2EEB
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq puts
movq %rbx, %rdi
callq free
xorl %eax, %eax
addq $80, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rbx
subq $32, %rsp
.cfi_adjust_cfa_offset 32
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8bottle99Pc, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
addq $32, %rsp
.cfi_adjust_cfa_offset -32
movl $text, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movl $121, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
pushq $0
.cfi_adjust_cfa_offset 8
pushq $0
.cfi_adjust_cfa_offset 8
callq __hipRegisterVar
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movl $end, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movl $251, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
pushq $0
.cfi_adjust_cfa_offset 8
pushq $0
.cfi_adjust_cfa_offset 8
callq __hipRegisterVar
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movl $__hip_module_dtor, %edi
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type text,@object # @text
.local text
.comm text,121,16
.type end,@object # @end
.local end
.comm end,251,16
.type _Z8bottle99Pc,@object # @_Z8bottle99Pc
.section .rodata,"a",@progbits
.globl _Z8bottle99Pc
.p2align 3, 0x0
_Z8bottle99Pc:
.quad _Z23__device_stub__bottle99Pc
.size _Z8bottle99Pc, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z8bottle99Pc"
.size .L__unnamed_1, 14
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "text"
.size .L__unnamed_2, 5
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "end"
.size .L__unnamed_3, 4
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__bottle99Pc
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym text
.addrsig_sym end
.addrsig_sym _Z8bottle99Pc
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | //hello.cu
#include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <stdio.h>
int main(void) {
printf("Hello CUDA \n");
return 0;
} | code for sm_80 |
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