system stringclasses 7 values | input stringlengths 10 94.5k | output stringlengths 14 55.5k |
|---|---|---|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | //hello.cu
#include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <stdio.h>
int main(void) {
printf("Hello CUDA \n");
return 0;
} | .file "tmpxft_0014ddc7_00000000-6_hello.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Hello CUDA \n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %eax
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | //hello.cu
#include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <stdio.h>
int main(void) {
printf("Hello CUDA \n");
return 0;
} | //hello.cu
#include "hip/hip_runtime.h"
#include <stdio.h>
int main(void) {
printf("Hello CUDA \n");
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | //hello.cu
#include "hip/hip_runtime.h"
#include <stdio.h>
int main(void) {
printf("Hello CUDA \n");
return 0;
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | //hello.cu
#include "hip/hip_runtime.h"
#include <stdio.h>
int main(void) {
printf("Hello CUDA \n");
return 0;
} | .text
.file "hello.hip"
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
movl $.Lstr, %edi
callq puts@PLT
xorl %eax, %eax
popq %rcx
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Hello CUDA "
.size .Lstr, 12
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0014ddc7_00000000-6_hello.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Hello CUDA \n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %eax
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "hello.hip"
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
movl $.Lstr, %edi
callq puts@PLT
xorl %eax, %eax
popq %rcx
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Hello CUDA "
.size .Lstr, 12
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | // from quantity_ext.c
__global__ void update(
int N,
double timestep,
double * centroid_values,
double * explicit_update,
double * semi_implicit_update)
{
const int k =
threadIdx.x+threadIdx.y*blockDim.x+
(blockIdx.x+blockIdx.y*gridDim.x)*blockDim.x*blockDim.y;
double denominator, x;
if (k >= N)
return;
// Divide semi_implicit update by conserved quantity
//for (k=0; k<N; k++) {
x = centroid_values[k];
if (x == 0.0) {
semi_implicit_update[k] = 0.0;
} else {
semi_implicit_update[k] /= x;
}
//}
// Explicit updates
//for (k=0; k<N; k++) {
centroid_values[k] += timestep*explicit_update[k];
//}
// Semi implicit updates
//for (k=0; k<N; k++) {
denominator = 1.0 - timestep*semi_implicit_update[k];
if (denominator <= 0.0) {
return;
} else {
//Update conserved_quantities from semi implicit updates
centroid_values[k] /= denominator;
}
//}
// Reset semi_implicit_update here ready for next time step
//memset(semi_implicit_update, 0, N*sizeof(double));
} | code for sm_80
Function : _Z6updateidPdS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e280000002600 */
/*0020*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e280000002500 */
/*0030*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e680000002200 */
/*0040*/ S2R R7, SR_TID.X ; /* 0x0000000000077919 */
/* 0x000ea20000002100 */
/*0050*/ IMAD R0, R0, c[0x0][0xc], R3 ; /* 0x0000030000007a24 */
/* 0x001fc800078e0203 */
/*0060*/ IMAD R0, R0, c[0x0][0x4], R5 ; /* 0x0000010000007a24 */
/* 0x002fc800078e0205 */
/*0070*/ IMAD R20, R0, c[0x0][0x0], R7 ; /* 0x0000000000147a24 */
/* 0x004fca00078e0207 */
/*0080*/ ISETP.GE.AND P0, PT, R20, c[0x0][0x160], PT ; /* 0x0000580014007a0c */
/* 0x000fda0003f06270 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ IMAD.MOV.U32 R9, RZ, RZ, 0x8 ; /* 0x00000008ff097424 */
/* 0x000fe200078e00ff */
/*00b0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*00c0*/ IMAD.WIDE R6, R20, R9, c[0x0][0x170] ; /* 0x00005c0014067625 */
/* 0x000fca00078e0209 */
/*00d0*/ LDG.E.64 R2, [R6.64] ; /* 0x0000000406027981 */
/* 0x000ea2000c1e1b00 */
/*00e0*/ BSSY B0, 0x2b0 ; /* 0x000001c000007945 */
/* 0x000fe20003800000 */
/*00f0*/ SHF.R.S32.HI R21, RZ, 0x1f, R20 ; /* 0x0000001fff157819 */
/* 0x000fe20000011414 */
/*0100*/ CS2R R10, SRZ ; /* 0x00000000000a7805 */
/* 0x000fe2000001ff00 */
/*0110*/ IMAD.WIDE R8, R20, R9, c[0x0][0x180] ; /* 0x0000600014087625 */
/* 0x000fe200078e0209 */
/*0120*/ DSETP.NEU.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200722a */
/* 0x004e1c0003f0d000 */
/*0130*/ @!P0 BRA 0x2a0 ; /* 0x0000016000008947 */
/* 0x001fea0003800000 */
/*0140*/ LDG.E.64 R4, [R8.64] ; /* 0x0000000408047981 */
/* 0x000ea2000c1e1b00 */
/*0150*/ MUFU.RCP64H R11, R3 ; /* 0x00000003000b7308 */
/* 0x000e220000001800 */
/*0160*/ IMAD.MOV.U32 R10, RZ, RZ, 0x1 ; /* 0x00000001ff0a7424 */
/* 0x000fe200078e00ff */
/*0170*/ BSSY B1, 0x2a0 ; /* 0x0000012000017945 */
/* 0x000fea0003800000 */
/*0180*/ DFMA R12, -R2, R10, 1 ; /* 0x3ff00000020c742b */
/* 0x001e0c000000010a */
/*0190*/ DFMA R12, R12, R12, R12 ; /* 0x0000000c0c0c722b */
/* 0x001e0c000000000c */
/*01a0*/ DFMA R12, R10, R12, R10 ; /* 0x0000000c0a0c722b */
/* 0x001e0c000000000a */
/*01b0*/ DFMA R10, -R2, R12, 1 ; /* 0x3ff00000020a742b */
/* 0x001e0c000000010c */
/*01c0*/ DFMA R10, R12, R10, R12 ; /* 0x0000000a0c0a722b */
/* 0x001e8c000000000c */
/*01d0*/ DMUL R12, R4, R10 ; /* 0x0000000a040c7228 */
/* 0x004e220000000000 */
/*01e0*/ FSETP.GEU.AND P1, PT, |R5|, 6.5827683646048100446e-37, PT ; /* 0x036000000500780b */
/* 0x000fca0003f2e200 */
/*01f0*/ DFMA R14, -R2, R12, R4 ; /* 0x0000000c020e722b */
/* 0x001e0c0000000104 */
/*0200*/ DFMA R10, R10, R14, R12 ; /* 0x0000000e0a0a722b */
/* 0x001e14000000000c */
/*0210*/ FFMA R0, RZ, R3, R11 ; /* 0x00000003ff007223 */
/* 0x001fca000000000b */
/*0220*/ FSETP.GT.AND P0, PT, |R0|, 1.469367938527859385e-39, PT ; /* 0x001000000000780b */
/* 0x000fda0003f04200 */
/*0230*/ @P0 BRA P1, 0x290 ; /* 0x0000005000000947 */
/* 0x000fea0000800000 */
/*0240*/ IMAD.MOV.U32 R14, RZ, RZ, R4 ; /* 0x000000ffff0e7224 */
/* 0x000fe200078e0004 */
/*0250*/ MOV R0, 0x290 ; /* 0x0000029000007802 */
/* 0x000fe20000000f00 */
/*0260*/ IMAD.MOV.U32 R15, RZ, RZ, R5 ; /* 0x000000ffff0f7224 */
/* 0x000fe400078e0005 */
/*0270*/ IMAD.MOV.U32 R13, RZ, RZ, R3 ; /* 0x000000ffff0d7224 */
/* 0x000fe400078e0003 */
/*0280*/ CALL.REL.NOINC 0x520 ; /* 0x0000029000007944 */
/* 0x000fea0003c00000 */
/*0290*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*02a0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*02b0*/ LEA R12, P0, R20.reuse, c[0x0][0x178], 0x3 ; /* 0x00005e00140c7a11 */
/* 0x040fe200078018ff */
/*02c0*/ STG.E.64 [R8.64], R10 ; /* 0x0000000a08007986 */
/* 0x0001e6000c101b04 */
/*02d0*/ LEA.HI.X R13, R20, c[0x0][0x17c], R21, 0x3, P0 ; /* 0x00005f00140d7a11 */
/* 0x000fe200000f1c15 */
/*02e0*/ LDG.E.64 R4, [R6.64] ; /* 0x0000000406047981 */
/* 0x000ea8000c1e1b00 */
/*02f0*/ LDG.E.64 R2, [R12.64] ; /* 0x000000040c027981 */
/* 0x000ea4000c1e1b00 */
/*0300*/ DFMA R2, R2, c[0x0][0x168], R4 ; /* 0x00005a0002027a2b */
/* 0x004e8e0000000004 */
/*0310*/ STG.E.64 [R6.64], R2 ; /* 0x0000000206007986 */
/* 0x0041e8000c101b04 */
/*0320*/ LDG.E.64 R4, [R8.64] ; /* 0x0000000408047981 */
/* 0x000ea2000c1e1b00 */
/*0330*/ IMAD.MOV.U32 R14, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff0e7624 */
/* 0x000fe400078e00ff */
/*0340*/ IMAD.MOV.U32 R15, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff0f7624 */
/* 0x000fcc00078e00ff */
/*0350*/ DFMA R4, -R4, R14, 1 ; /* 0x3ff000000404742b */
/* 0x004e8c000000010e */
/*0360*/ DSETP.GTU.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400722a */
/* 0x004e9c0003f0c000 */
/*0370*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x004fea0003800000 */
/*0380*/ MUFU.RCP64H R9, R5 ; /* 0x0000000500097308 */
/* 0x001e220000001800 */
/*0390*/ IMAD.MOV.U32 R8, RZ, RZ, 0x1 ; /* 0x00000001ff087424 */
/* 0x000fe200078e00ff */
/*03a0*/ FSETP.GEU.AND P1, PT, |R3|, 6.5827683646048100446e-37, PT ; /* 0x036000000300780b */
/* 0x000fe20003f2e200 */
/*03b0*/ BSSY B0, 0x500 ; /* 0x0000014000007945 */
/* 0x000fe80003800000 */
/*03c0*/ DFMA R10, -R4, R8, 1 ; /* 0x3ff00000040a742b */
/* 0x001e0c0000000108 */
/*03d0*/ DFMA R10, R10, R10, R10 ; /* 0x0000000a0a0a722b */
/* 0x001e0c000000000a */
/*03e0*/ DFMA R10, R8, R10, R8 ; /* 0x0000000a080a722b */
/* 0x001e0c0000000008 */
/*03f0*/ DFMA R8, -R4, R10, 1 ; /* 0x3ff000000408742b */
/* 0x001e0c000000010a */
/*0400*/ DFMA R8, R10, R8, R10 ; /* 0x000000080a08722b */
/* 0x001e0c000000000a */
/*0410*/ DMUL R10, R2, R8 ; /* 0x00000008020a7228 */
/* 0x001e0c0000000000 */
/*0420*/ DFMA R12, -R4, R10, R2 ; /* 0x0000000a040c722b */
/* 0x001e0c0000000102 */
/*0430*/ DFMA R8, R8, R12, R10 ; /* 0x0000000c0808722b */
/* 0x001e14000000000a */
/*0440*/ FFMA R0, RZ, R5, R9 ; /* 0x00000005ff007223 */
/* 0x001fca0000000009 */
/*0450*/ FSETP.GT.AND P0, PT, |R0|, 1.469367938527859385e-39, PT ; /* 0x001000000000780b */
/* 0x000fda0003f04200 */
/*0460*/ @P0 BRA P1, 0x4f0 ; /* 0x0000008000000947 */
/* 0x000fea0000800000 */
/*0470*/ IMAD.MOV.U32 R14, RZ, RZ, R2 ; /* 0x000000ffff0e7224 */
/* 0x000fe200078e0002 */
/*0480*/ MOV R0, 0x4d0 ; /* 0x000004d000007802 */
/* 0x000fe20000000f00 */
/*0490*/ IMAD.MOV.U32 R15, RZ, RZ, R3 ; /* 0x000000ffff0f7224 */
/* 0x000fe400078e0003 */
/*04a0*/ IMAD.MOV.U32 R2, RZ, RZ, R4 ; /* 0x000000ffff027224 */
/* 0x000fe400078e0004 */
/*04b0*/ IMAD.MOV.U32 R13, RZ, RZ, R5 ; /* 0x000000ffff0d7224 */
/* 0x000fe400078e0005 */
/*04c0*/ CALL.REL.NOINC 0x520 ; /* 0x0000005000007944 */
/* 0x002fea0003c00000 */
/*04d0*/ IMAD.MOV.U32 R8, RZ, RZ, R10 ; /* 0x000000ffff087224 */
/* 0x000fe400078e000a */
/*04e0*/ IMAD.MOV.U32 R9, RZ, RZ, R11 ; /* 0x000000ffff097224 */
/* 0x000fe400078e000b */
/*04f0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0500*/ STG.E.64 [R6.64], R8 ; /* 0x0000000806007986 */
/* 0x000fe2000c101b04 */
/*0510*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0520*/ FSETP.GEU.AND P0, PT, |R13|.reuse, 1.469367938527859385e-39, PT ; /* 0x001000000d00780b */
/* 0x040fe20003f0e200 */
/*0530*/ IMAD.MOV.U32 R12, RZ, RZ, R2.reuse ; /* 0x000000ffff0c7224 */
/* 0x100fe200078e0002 */
/*0540*/ LOP3.LUT R10, R13, 0x800fffff, RZ, 0xc0, !PT ; /* 0x800fffff0d0a7812 */
/* 0x000fe200078ec0ff */
/*0550*/ IMAD.MOV.U32 R23, RZ, RZ, 0x1ca00000 ; /* 0x1ca00000ff177424 */
/* 0x000fe200078e00ff */
/*0560*/ FSETP.GEU.AND P2, PT, |R15|.reuse, 1.469367938527859385e-39, PT ; /* 0x001000000f00780b */
/* 0x040fe20003f4e200 */
/*0570*/ IMAD.MOV.U32 R4, RZ, RZ, 0x1 ; /* 0x00000001ff047424 */
/* 0x000fe200078e00ff */
/*0580*/ LOP3.LUT R11, R10, 0x3ff00000, RZ, 0xfc, !PT ; /* 0x3ff000000a0b7812 */
/* 0x000fe200078efcff */
/*0590*/ IMAD.MOV.U32 R10, RZ, RZ, R2 ; /* 0x000000ffff0a7224 */
/* 0x000fe200078e0002 */
/*05a0*/ LOP3.LUT R22, R15, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff000000f167812 */
/* 0x000fe200078ec0ff */
/*05b0*/ IMAD.MOV.U32 R2, RZ, RZ, R14 ; /* 0x000000ffff027224 */
/* 0x000fe200078e000e */
/*05c0*/ LOP3.LUT R25, R13, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff000000d197812 */
/* 0x000fe200078ec0ff */
/*05d0*/ BSSY B2, 0xac0 ; /* 0x000004e000027945 */
/* 0x000fe40003800000 */
/*05e0*/ @!P0 DMUL R10, R12, 8.98846567431157953865e+307 ; /* 0x7fe000000c0a8828 */
/* 0x000e220000000000 */
/*05f0*/ ISETP.GE.U32.AND P1, PT, R22, R25, PT ; /* 0x000000191600720c */
/* 0x000fe20003f26070 */
/*0600*/ IMAD.MOV.U32 R24, RZ, RZ, R22 ; /* 0x000000ffff187224 */
/* 0x000fc400078e0016 */
/*0610*/ @!P2 LOP3.LUT R3, R13, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff000000d03a812 */
/* 0x000fe200078ec0ff */
/*0620*/ @!P2 IMAD.MOV.U32 R18, RZ, RZ, RZ ; /* 0x000000ffff12a224 */
/* 0x000fe200078e00ff */
/*0630*/ MUFU.RCP64H R5, R11 ; /* 0x0000000b00057308 */
/* 0x001e240000001800 */
/*0640*/ @!P2 ISETP.GE.U32.AND P3, PT, R22, R3, PT ; /* 0x000000031600a20c */
/* 0x000fe40003f66070 */
/*0650*/ SEL R3, R23.reuse, 0x63400000, !P1 ; /* 0x6340000017037807 */
/* 0x040fe40004800000 */
/*0660*/ @!P2 SEL R19, R23, 0x63400000, !P3 ; /* 0x634000001713a807 */
/* 0x000fe40005800000 */
/*0670*/ LOP3.LUT R3, R3, 0x800fffff, R15, 0xf8, !PT ; /* 0x800fffff03037812 */
/* 0x000fc400078ef80f */
/*0680*/ @!P2 LOP3.LUT R19, R19, 0x80000000, R15, 0xf8, !PT ; /* 0x800000001313a812 */
/* 0x000fe400078ef80f */
/*0690*/ @!P0 LOP3.LUT R25, R11, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff000000b198812 */
/* 0x000fe400078ec0ff */
/*06a0*/ @!P2 LOP3.LUT R19, R19, 0x100000, RZ, 0xfc, !PT ; /* 0x001000001313a812 */
/* 0x000fe200078efcff */
/*06b0*/ DFMA R16, R4, -R10, 1 ; /* 0x3ff000000410742b */
/* 0x001e22000000080a */
/*06c0*/ IADD3 R26, R25, -0x1, RZ ; /* 0xffffffff191a7810 */
/* 0x000fc80007ffe0ff */
/*06d0*/ @!P2 DFMA R2, R2, 2, -R18 ; /* 0x400000000202a82b */
/* 0x000fc80000000812 */
/*06e0*/ DFMA R16, R16, R16, R16 ; /* 0x000000101010722b */
/* 0x001e0c0000000010 */
/*06f0*/ DFMA R16, R4, R16, R4 ; /* 0x000000100410722b */
/* 0x001e220000000004 */
/*0700*/ @!P2 LOP3.LUT R24, R3, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff000000318a812 */
/* 0x000fc800078ec0ff */
/*0710*/ IADD3 R18, R24, -0x1, RZ ; /* 0xffffffff18127810 */
/* 0x000fe20007ffe0ff */
/*0720*/ DFMA R4, R16, -R10, 1 ; /* 0x3ff000001004742b */
/* 0x001e06000000080a */
/*0730*/ ISETP.GT.U32.AND P0, PT, R18, 0x7feffffe, PT ; /* 0x7feffffe1200780c */
/* 0x000fc60003f04070 */
/*0740*/ DFMA R16, R16, R4, R16 ; /* 0x000000041010722b */
/* 0x001e220000000010 */
/*0750*/ ISETP.GT.U32.OR P0, PT, R26, 0x7feffffe, P0 ; /* 0x7feffffe1a00780c */
/* 0x000fca0000704470 */
/*0760*/ DMUL R4, R16, R2 ; /* 0x0000000210047228 */
/* 0x001e0c0000000000 */
/*0770*/ DFMA R18, R4, -R10, R2 ; /* 0x8000000a0412722b */
/* 0x001e0c0000000002 */
/*0780*/ DFMA R18, R16, R18, R4 ; /* 0x000000121012722b */
/* 0x0010620000000004 */
/*0790*/ @P0 BRA 0x960 ; /* 0x000001c000000947 */
/* 0x000fea0003800000 */
/*07a0*/ LOP3.LUT R5, R13, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff000000d057812 */
/* 0x001fe200078ec0ff */
/*07b0*/ IMAD.MOV.U32 R16, RZ, RZ, RZ ; /* 0x000000ffff107224 */
/* 0x000fc600078e00ff */
/*07c0*/ ISETP.GE.U32.AND P0, PT, R22.reuse, R5, PT ; /* 0x000000051600720c */
/* 0x040fe20003f06070 */
/*07d0*/ IMAD.IADD R4, R22, 0x1, -R5 ; /* 0x0000000116047824 */
/* 0x000fc600078e0a05 */
/*07e0*/ SEL R23, R23, 0x63400000, !P0 ; /* 0x6340000017177807 */
/* 0x000fe40004000000 */
/*07f0*/ IMNMX R4, R4, -0x46a00000, !PT ; /* 0xb960000004047817 */
/* 0x000fc80007800200 */
/*0800*/ IMNMX R4, R4, 0x46a00000, PT ; /* 0x46a0000004047817 */
/* 0x000fca0003800200 */
/*0810*/ IMAD.IADD R14, R4, 0x1, -R23 ; /* 0x00000001040e7824 */
/* 0x000fca00078e0a17 */
/*0820*/ IADD3 R17, R14, 0x7fe00000, RZ ; /* 0x7fe000000e117810 */
/* 0x000fcc0007ffe0ff */
/*0830*/ DMUL R4, R18, R16 ; /* 0x0000001012047228 */
/* 0x002e140000000000 */
/*0840*/ FSETP.GTU.AND P0, PT, |R5|, 1.469367938527859385e-39, PT ; /* 0x001000000500780b */
/* 0x001fda0003f0c200 */
/*0850*/ @P0 BRA 0xab0 ; /* 0x0000025000000947 */
/* 0x000fea0003800000 */
/*0860*/ DFMA R2, R18, -R10, R2 ; /* 0x8000000a1202722b */
/* 0x000e220000000002 */
/*0870*/ IMAD.MOV.U32 R16, RZ, RZ, RZ ; /* 0x000000ffff107224 */
/* 0x000fd200078e00ff */
/*0880*/ FSETP.NEU.AND P0, PT, R3.reuse, RZ, PT ; /* 0x000000ff0300720b */
/* 0x041fe40003f0d000 */
/*0890*/ LOP3.LUT R13, R3, 0x80000000, R13, 0x48, !PT ; /* 0x80000000030d7812 */
/* 0x000fc800078e480d */
/*08a0*/ LOP3.LUT R17, R13, R17, RZ, 0xfc, !PT ; /* 0x000000110d117212 */
/* 0x000fce00078efcff */
/*08b0*/ @!P0 BRA 0xab0 ; /* 0x000001f000008947 */
/* 0x000fea0003800000 */
/*08c0*/ IMAD.MOV R3, RZ, RZ, -R14 ; /* 0x000000ffff037224 */
/* 0x000fe200078e0a0e */
/*08d0*/ DMUL.RP R16, R18, R16 ; /* 0x0000001012107228 */
/* 0x000e220000008000 */
/*08e0*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x000fcc00078e00ff */
/*08f0*/ DFMA R2, R4, -R2, R18 ; /* 0x800000020402722b */
/* 0x000e460000000012 */
/*0900*/ LOP3.LUT R13, R17, R13, RZ, 0x3c, !PT ; /* 0x0000000d110d7212 */
/* 0x001fc600078e3cff */
/*0910*/ IADD3 R2, -R14, -0x43300000, RZ ; /* 0xbcd000000e027810 */
/* 0x002fc80007ffe1ff */
/*0920*/ FSETP.NEU.AND P0, PT, |R3|, R2, PT ; /* 0x000000020300720b */
/* 0x000fc80003f0d200 */
/*0930*/ FSEL R4, R16, R4, !P0 ; /* 0x0000000410047208 */
/* 0x000fe40004000000 */
/*0940*/ FSEL R5, R13, R5, !P0 ; /* 0x000000050d057208 */
/* 0x000fe20004000000 */
/*0950*/ BRA 0xab0 ; /* 0x0000015000007947 */
/* 0x000fea0003800000 */
/*0960*/ DSETP.NAN.AND P0, PT, R14, R14, PT ; /* 0x0000000e0e00722a */
/* 0x000e9c0003f08000 */
/*0970*/ @P0 BRA 0xa90 ; /* 0x0000011000000947 */
/* 0x004fea0003800000 */
/*0980*/ DSETP.NAN.AND P0, PT, R12, R12, PT ; /* 0x0000000c0c00722a */
/* 0x000e9c0003f08000 */
/*0990*/ @P0 BRA 0xa60 ; /* 0x000000c000000947 */
/* 0x004fea0003800000 */
/*09a0*/ ISETP.NE.AND P0, PT, R24, R25, PT ; /* 0x000000191800720c */
/* 0x000fe20003f05270 */
/*09b0*/ IMAD.MOV.U32 R4, RZ, RZ, 0x0 ; /* 0x00000000ff047424 */
/* 0x001fe400078e00ff */
/*09c0*/ IMAD.MOV.U32 R5, RZ, RZ, -0x80000 ; /* 0xfff80000ff057424 */
/* 0x000fd400078e00ff */
/*09d0*/ @!P0 BRA 0xab0 ; /* 0x000000d000008947 */
/* 0x000fea0003800000 */
/*09e0*/ ISETP.NE.AND P0, PT, R24, 0x7ff00000, PT ; /* 0x7ff000001800780c */
/* 0x000fe40003f05270 */
/*09f0*/ LOP3.LUT R5, R15, 0x80000000, R13, 0x48, !PT ; /* 0x800000000f057812 */
/* 0x000fe400078e480d */
/*0a00*/ ISETP.EQ.OR P0, PT, R25, RZ, !P0 ; /* 0x000000ff1900720c */
/* 0x000fda0004702670 */
/*0a10*/ @P0 LOP3.LUT R2, R5, 0x7ff00000, RZ, 0xfc, !PT ; /* 0x7ff0000005020812 */
/* 0x000fe200078efcff */
/*0a20*/ @!P0 IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff048224 */
/* 0x000fe400078e00ff */
/*0a30*/ @P0 IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff040224 */
/* 0x000fe400078e00ff */
/*0a40*/ @P0 IMAD.MOV.U32 R5, RZ, RZ, R2 ; /* 0x000000ffff050224 */
/* 0x000fe200078e0002 */
/*0a50*/ BRA 0xab0 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*0a60*/ LOP3.LUT R5, R13, 0x80000, RZ, 0xfc, !PT ; /* 0x000800000d057812 */
/* 0x001fe200078efcff */
/*0a70*/ IMAD.MOV.U32 R4, RZ, RZ, R12 ; /* 0x000000ffff047224 */
/* 0x000fe200078e000c */
/*0a80*/ BRA 0xab0 ; /* 0x0000002000007947 */
/* 0x000fea0003800000 */
/*0a90*/ LOP3.LUT R5, R15, 0x80000, RZ, 0xfc, !PT ; /* 0x000800000f057812 */
/* 0x001fe200078efcff */
/*0aa0*/ IMAD.MOV.U32 R4, RZ, RZ, R14 ; /* 0x000000ffff047224 */
/* 0x000fe400078e000e */
/*0ab0*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*0ac0*/ IMAD.MOV.U32 R2, RZ, RZ, R0 ; /* 0x000000ffff027224 */
/* 0x000fe400078e0000 */
/*0ad0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x0 ; /* 0x00000000ff037424 */
/* 0x000fc400078e00ff */
/*0ae0*/ IMAD.MOV.U32 R10, RZ, RZ, R4 ; /* 0x000000ffff0a7224 */
/* 0x000fe400078e0004 */
/*0af0*/ IMAD.MOV.U32 R11, RZ, RZ, R5 ; /* 0x000000ffff0b7224 */
/* 0x000fe200078e0005 */
/*0b00*/ RET.REL.NODEC R2 0x0 ; /* 0xfffff4f002007950 */
/* 0x000fec0003c3ffff */
/*0b10*/ BRA 0xb10; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0b20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ba0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0be0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | // from quantity_ext.c
__global__ void update(
int N,
double timestep,
double * centroid_values,
double * explicit_update,
double * semi_implicit_update)
{
const int k =
threadIdx.x+threadIdx.y*blockDim.x+
(blockIdx.x+blockIdx.y*gridDim.x)*blockDim.x*blockDim.y;
double denominator, x;
if (k >= N)
return;
// Divide semi_implicit update by conserved quantity
//for (k=0; k<N; k++) {
x = centroid_values[k];
if (x == 0.0) {
semi_implicit_update[k] = 0.0;
} else {
semi_implicit_update[k] /= x;
}
//}
// Explicit updates
//for (k=0; k<N; k++) {
centroid_values[k] += timestep*explicit_update[k];
//}
// Semi implicit updates
//for (k=0; k<N; k++) {
denominator = 1.0 - timestep*semi_implicit_update[k];
if (denominator <= 0.0) {
return;
} else {
//Update conserved_quantities from semi implicit updates
centroid_values[k] /= denominator;
}
//}
// Reset semi_implicit_update here ready for next time step
//memset(semi_implicit_update, 0, N*sizeof(double));
} | .file "tmpxft_00030b3f_00000000-6_update.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z31__device_stub__Z6updateidPdS_S_idPdS_S_
.type _Z31__device_stub__Z6updateidPdS_S_idPdS_S_, @function
_Z31__device_stub__Z6updateidPdS_S_idPdS_S_:
.LFB2051:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movl %edi, 44(%rsp)
movsd %xmm0, 32(%rsp)
movq %rsi, 24(%rsp)
movq %rdx, 16(%rsp)
movq %rcx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 44(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 184
pushq 56(%rsp)
.cfi_def_cfa_offset 192
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z6updateidPdS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z31__device_stub__Z6updateidPdS_S_idPdS_S_, .-_Z31__device_stub__Z6updateidPdS_S_idPdS_S_
.globl _Z6updateidPdS_S_
.type _Z6updateidPdS_S_, @function
_Z6updateidPdS_S_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z6updateidPdS_S_idPdS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z6updateidPdS_S_, .-_Z6updateidPdS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z6updateidPdS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z6updateidPdS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | // from quantity_ext.c
__global__ void update(
int N,
double timestep,
double * centroid_values,
double * explicit_update,
double * semi_implicit_update)
{
const int k =
threadIdx.x+threadIdx.y*blockDim.x+
(blockIdx.x+blockIdx.y*gridDim.x)*blockDim.x*blockDim.y;
double denominator, x;
if (k >= N)
return;
// Divide semi_implicit update by conserved quantity
//for (k=0; k<N; k++) {
x = centroid_values[k];
if (x == 0.0) {
semi_implicit_update[k] = 0.0;
} else {
semi_implicit_update[k] /= x;
}
//}
// Explicit updates
//for (k=0; k<N; k++) {
centroid_values[k] += timestep*explicit_update[k];
//}
// Semi implicit updates
//for (k=0; k<N; k++) {
denominator = 1.0 - timestep*semi_implicit_update[k];
if (denominator <= 0.0) {
return;
} else {
//Update conserved_quantities from semi implicit updates
centroid_values[k] /= denominator;
}
//}
// Reset semi_implicit_update here ready for next time step
//memset(semi_implicit_update, 0, N*sizeof(double));
} | #include <hip/hip_runtime.h>
// from quantity_ext.c
__global__ void update(
int N,
double timestep,
double * centroid_values,
double * explicit_update,
double * semi_implicit_update)
{
const int k =
threadIdx.x+threadIdx.y*blockDim.x+
(blockIdx.x+blockIdx.y*gridDim.x)*blockDim.x*blockDim.y;
double denominator, x;
if (k >= N)
return;
// Divide semi_implicit update by conserved quantity
//for (k=0; k<N; k++) {
x = centroid_values[k];
if (x == 0.0) {
semi_implicit_update[k] = 0.0;
} else {
semi_implicit_update[k] /= x;
}
//}
// Explicit updates
//for (k=0; k<N; k++) {
centroid_values[k] += timestep*explicit_update[k];
//}
// Semi implicit updates
//for (k=0; k<N; k++) {
denominator = 1.0 - timestep*semi_implicit_update[k];
if (denominator <= 0.0) {
return;
} else {
//Update conserved_quantities from semi implicit updates
centroid_values[k] /= denominator;
}
//}
// Reset semi_implicit_update here ready for next time step
//memset(semi_implicit_update, 0, N*sizeof(double));
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
// from quantity_ext.c
__global__ void update(
int N,
double timestep,
double * centroid_values,
double * explicit_update,
double * semi_implicit_update)
{
const int k =
threadIdx.x+threadIdx.y*blockDim.x+
(blockIdx.x+blockIdx.y*gridDim.x)*blockDim.x*blockDim.y;
double denominator, x;
if (k >= N)
return;
// Divide semi_implicit update by conserved quantity
//for (k=0; k<N; k++) {
x = centroid_values[k];
if (x == 0.0) {
semi_implicit_update[k] = 0.0;
} else {
semi_implicit_update[k] /= x;
}
//}
// Explicit updates
//for (k=0; k<N; k++) {
centroid_values[k] += timestep*explicit_update[k];
//}
// Semi implicit updates
//for (k=0; k<N; k++) {
denominator = 1.0 - timestep*semi_implicit_update[k];
if (denominator <= 0.0) {
return;
} else {
//Update conserved_quantities from semi implicit updates
centroid_values[k] /= denominator;
}
//}
// Reset semi_implicit_update here ready for next time step
//memset(semi_implicit_update, 0, N*sizeof(double));
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6updateidPdS_S_
.globl _Z6updateidPdS_S_
.p2align 8
.type _Z6updateidPdS_S_,@function
_Z6updateidPdS_S_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x28
s_load_b32 s3, s[0:1], 0x34
v_bfe_u32 v1, v0, 10, 10
s_load_b32 s4, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_mul_i32 s2, s2, s15
s_lshr_b32 s5, s3, 16
s_add_i32 s2, s2, s14
s_delay_alu instid0(SALU_CYCLE_1)
v_mad_u64_u32 v[2:3], null, s2, s5, v[1:2]
v_and_b32_e32 v3, 0x3ff, v0
s_and_b32 s2, s3, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[0:1], null, v2, s2, v[3:4]
s_mov_b32 s2, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s4, v0
s_cbranch_execz .LBB0_5
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x10
s_load_b64 s[4:5], s[0:1], 0x20
v_ashrrev_i32_e32 v1, 31, v0
v_mov_b32_e32 v8, 0
v_mov_b32_e32 v9, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 3, v[0:1]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s2, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v3, vcc_lo
v_add_co_u32 v4, s2, s4, v2
v_add_co_ci_u32_e64 v5, s2, s5, v3, s2
global_load_b64 v[6:7], v[0:1], off
s_mov_b32 s2, exec_lo
s_waitcnt vmcnt(0)
v_cmpx_neq_f64_e32 0, v[6:7]
s_cbranch_execz .LBB0_3
global_load_b64 v[8:9], v[4:5], off
s_waitcnt vmcnt(0)
v_div_scale_f64 v[10:11], null, v[6:7], v[6:7], v[8:9]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f64_e32 v[12:13], v[10:11]
s_waitcnt_depctr 0xfff
v_fma_f64 v[14:15], -v[10:11], v[12:13], 1.0
v_fma_f64 v[12:13], v[12:13], v[14:15], v[12:13]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[14:15], -v[10:11], v[12:13], 1.0
v_fma_f64 v[12:13], v[12:13], v[14:15], v[12:13]
v_div_scale_f64 v[14:15], vcc_lo, v[8:9], v[6:7], v[8:9]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[16:17], v[14:15], v[12:13]
v_fma_f64 v[10:11], -v[10:11], v[16:17], v[14:15]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fmas_f64 v[10:11], v[10:11], v[12:13], v[16:17]
v_div_fixup_f64 v[8:9], v[10:11], v[6:7], v[8:9]
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s2
s_load_b64 s[2:3], s[0:1], 0x18
global_store_b64 v[4:5], v[8:9], off
s_load_b64 s[0:1], s[0:1], 0x8
s_waitcnt lgkmcnt(0)
v_add_co_u32 v6, vcc_lo, s2, v2
v_add_co_ci_u32_e32 v7, vcc_lo, s3, v3, vcc_lo
v_add_co_u32 v2, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
global_load_b64 v[4:5], v[6:7], off
global_load_b64 v[6:7], v[0:1], off
s_waitcnt vmcnt(0)
v_fma_f64 v[4:5], v[4:5], s[0:1], v[6:7]
global_store_b64 v[0:1], v[4:5], off
global_load_b64 v[2:3], v[2:3], off
s_waitcnt vmcnt(0)
v_fma_f64 v[2:3], -v[2:3], s[0:1], 1.0
s_delay_alu instid0(VALU_DEP_1)
v_cmp_nge_f64_e32 vcc_lo, 0, v[2:3]
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_5
v_div_scale_f64 v[6:7], null, v[2:3], v[2:3], v[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f64_e32 v[8:9], v[6:7]
s_waitcnt_depctr 0xfff
v_fma_f64 v[10:11], -v[6:7], v[8:9], 1.0
v_fma_f64 v[8:9], v[8:9], v[10:11], v[8:9]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[10:11], -v[6:7], v[8:9], 1.0
v_fma_f64 v[8:9], v[8:9], v[10:11], v[8:9]
v_div_scale_f64 v[10:11], vcc_lo, v[4:5], v[2:3], v[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[12:13], v[10:11], v[8:9]
v_fma_f64 v[6:7], -v[6:7], v[12:13], v[10:11]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fmas_f64 v[6:7], v[6:7], v[8:9], v[12:13]
v_div_fixup_f64 v[2:3], v[6:7], v[2:3], v[4:5]
global_store_b64 v[0:1], v[2:3], off
.LBB0_5:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6updateidPdS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 18
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6updateidPdS_S_, .Lfunc_end0-_Z6updateidPdS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 8
.size: 8
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6updateidPdS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6updateidPdS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 18
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
// from quantity_ext.c
__global__ void update(
int N,
double timestep,
double * centroid_values,
double * explicit_update,
double * semi_implicit_update)
{
const int k =
threadIdx.x+threadIdx.y*blockDim.x+
(blockIdx.x+blockIdx.y*gridDim.x)*blockDim.x*blockDim.y;
double denominator, x;
if (k >= N)
return;
// Divide semi_implicit update by conserved quantity
//for (k=0; k<N; k++) {
x = centroid_values[k];
if (x == 0.0) {
semi_implicit_update[k] = 0.0;
} else {
semi_implicit_update[k] /= x;
}
//}
// Explicit updates
//for (k=0; k<N; k++) {
centroid_values[k] += timestep*explicit_update[k];
//}
// Semi implicit updates
//for (k=0; k<N; k++) {
denominator = 1.0 - timestep*semi_implicit_update[k];
if (denominator <= 0.0) {
return;
} else {
//Update conserved_quantities from semi implicit updates
centroid_values[k] /= denominator;
}
//}
// Reset semi_implicit_update here ready for next time step
//memset(semi_implicit_update, 0, N*sizeof(double));
} | .text
.file "update.hip"
.globl _Z21__device_stub__updateidPdS_S_ # -- Begin function _Z21__device_stub__updateidPdS_S_
.p2align 4, 0x90
.type _Z21__device_stub__updateidPdS_S_,@function
_Z21__device_stub__updateidPdS_S_: # @_Z21__device_stub__updateidPdS_S_
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movl %edi, 12(%rsp)
movsd %xmm0, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 88(%rsp), %rax
movq %rax, 104(%rsp)
leaq 80(%rsp), %rax
movq %rax, 112(%rsp)
leaq 72(%rsp), %rax
movq %rax, 120(%rsp)
leaq 64(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z6updateidPdS_S_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end0:
.size _Z21__device_stub__updateidPdS_S_, .Lfunc_end0-_Z21__device_stub__updateidPdS_S_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6updateidPdS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6updateidPdS_S_,@object # @_Z6updateidPdS_S_
.section .rodata,"a",@progbits
.globl _Z6updateidPdS_S_
.p2align 3, 0x0
_Z6updateidPdS_S_:
.quad _Z21__device_stub__updateidPdS_S_
.size _Z6updateidPdS_S_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z6updateidPdS_S_"
.size .L__unnamed_1, 18
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__updateidPdS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6updateidPdS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z6updateidPdS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e280000002600 */
/*0020*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e280000002500 */
/*0030*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e680000002200 */
/*0040*/ S2R R7, SR_TID.X ; /* 0x0000000000077919 */
/* 0x000ea20000002100 */
/*0050*/ IMAD R0, R0, c[0x0][0xc], R3 ; /* 0x0000030000007a24 */
/* 0x001fc800078e0203 */
/*0060*/ IMAD R0, R0, c[0x0][0x4], R5 ; /* 0x0000010000007a24 */
/* 0x002fc800078e0205 */
/*0070*/ IMAD R20, R0, c[0x0][0x0], R7 ; /* 0x0000000000147a24 */
/* 0x004fca00078e0207 */
/*0080*/ ISETP.GE.AND P0, PT, R20, c[0x0][0x160], PT ; /* 0x0000580014007a0c */
/* 0x000fda0003f06270 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ IMAD.MOV.U32 R9, RZ, RZ, 0x8 ; /* 0x00000008ff097424 */
/* 0x000fe200078e00ff */
/*00b0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*00c0*/ IMAD.WIDE R6, R20, R9, c[0x0][0x170] ; /* 0x00005c0014067625 */
/* 0x000fca00078e0209 */
/*00d0*/ LDG.E.64 R2, [R6.64] ; /* 0x0000000406027981 */
/* 0x000ea2000c1e1b00 */
/*00e0*/ BSSY B0, 0x2b0 ; /* 0x000001c000007945 */
/* 0x000fe20003800000 */
/*00f0*/ SHF.R.S32.HI R21, RZ, 0x1f, R20 ; /* 0x0000001fff157819 */
/* 0x000fe20000011414 */
/*0100*/ CS2R R10, SRZ ; /* 0x00000000000a7805 */
/* 0x000fe2000001ff00 */
/*0110*/ IMAD.WIDE R8, R20, R9, c[0x0][0x180] ; /* 0x0000600014087625 */
/* 0x000fe200078e0209 */
/*0120*/ DSETP.NEU.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200722a */
/* 0x004e1c0003f0d000 */
/*0130*/ @!P0 BRA 0x2a0 ; /* 0x0000016000008947 */
/* 0x001fea0003800000 */
/*0140*/ LDG.E.64 R4, [R8.64] ; /* 0x0000000408047981 */
/* 0x000ea2000c1e1b00 */
/*0150*/ MUFU.RCP64H R11, R3 ; /* 0x00000003000b7308 */
/* 0x000e220000001800 */
/*0160*/ IMAD.MOV.U32 R10, RZ, RZ, 0x1 ; /* 0x00000001ff0a7424 */
/* 0x000fe200078e00ff */
/*0170*/ BSSY B1, 0x2a0 ; /* 0x0000012000017945 */
/* 0x000fea0003800000 */
/*0180*/ DFMA R12, -R2, R10, 1 ; /* 0x3ff00000020c742b */
/* 0x001e0c000000010a */
/*0190*/ DFMA R12, R12, R12, R12 ; /* 0x0000000c0c0c722b */
/* 0x001e0c000000000c */
/*01a0*/ DFMA R12, R10, R12, R10 ; /* 0x0000000c0a0c722b */
/* 0x001e0c000000000a */
/*01b0*/ DFMA R10, -R2, R12, 1 ; /* 0x3ff00000020a742b */
/* 0x001e0c000000010c */
/*01c0*/ DFMA R10, R12, R10, R12 ; /* 0x0000000a0c0a722b */
/* 0x001e8c000000000c */
/*01d0*/ DMUL R12, R4, R10 ; /* 0x0000000a040c7228 */
/* 0x004e220000000000 */
/*01e0*/ FSETP.GEU.AND P1, PT, |R5|, 6.5827683646048100446e-37, PT ; /* 0x036000000500780b */
/* 0x000fca0003f2e200 */
/*01f0*/ DFMA R14, -R2, R12, R4 ; /* 0x0000000c020e722b */
/* 0x001e0c0000000104 */
/*0200*/ DFMA R10, R10, R14, R12 ; /* 0x0000000e0a0a722b */
/* 0x001e14000000000c */
/*0210*/ FFMA R0, RZ, R3, R11 ; /* 0x00000003ff007223 */
/* 0x001fca000000000b */
/*0220*/ FSETP.GT.AND P0, PT, |R0|, 1.469367938527859385e-39, PT ; /* 0x001000000000780b */
/* 0x000fda0003f04200 */
/*0230*/ @P0 BRA P1, 0x290 ; /* 0x0000005000000947 */
/* 0x000fea0000800000 */
/*0240*/ IMAD.MOV.U32 R14, RZ, RZ, R4 ; /* 0x000000ffff0e7224 */
/* 0x000fe200078e0004 */
/*0250*/ MOV R0, 0x290 ; /* 0x0000029000007802 */
/* 0x000fe20000000f00 */
/*0260*/ IMAD.MOV.U32 R15, RZ, RZ, R5 ; /* 0x000000ffff0f7224 */
/* 0x000fe400078e0005 */
/*0270*/ IMAD.MOV.U32 R13, RZ, RZ, R3 ; /* 0x000000ffff0d7224 */
/* 0x000fe400078e0003 */
/*0280*/ CALL.REL.NOINC 0x520 ; /* 0x0000029000007944 */
/* 0x000fea0003c00000 */
/*0290*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*02a0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*02b0*/ LEA R12, P0, R20.reuse, c[0x0][0x178], 0x3 ; /* 0x00005e00140c7a11 */
/* 0x040fe200078018ff */
/*02c0*/ STG.E.64 [R8.64], R10 ; /* 0x0000000a08007986 */
/* 0x0001e6000c101b04 */
/*02d0*/ LEA.HI.X R13, R20, c[0x0][0x17c], R21, 0x3, P0 ; /* 0x00005f00140d7a11 */
/* 0x000fe200000f1c15 */
/*02e0*/ LDG.E.64 R4, [R6.64] ; /* 0x0000000406047981 */
/* 0x000ea8000c1e1b00 */
/*02f0*/ LDG.E.64 R2, [R12.64] ; /* 0x000000040c027981 */
/* 0x000ea4000c1e1b00 */
/*0300*/ DFMA R2, R2, c[0x0][0x168], R4 ; /* 0x00005a0002027a2b */
/* 0x004e8e0000000004 */
/*0310*/ STG.E.64 [R6.64], R2 ; /* 0x0000000206007986 */
/* 0x0041e8000c101b04 */
/*0320*/ LDG.E.64 R4, [R8.64] ; /* 0x0000000408047981 */
/* 0x000ea2000c1e1b00 */
/*0330*/ IMAD.MOV.U32 R14, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff0e7624 */
/* 0x000fe400078e00ff */
/*0340*/ IMAD.MOV.U32 R15, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff0f7624 */
/* 0x000fcc00078e00ff */
/*0350*/ DFMA R4, -R4, R14, 1 ; /* 0x3ff000000404742b */
/* 0x004e8c000000010e */
/*0360*/ DSETP.GTU.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400722a */
/* 0x004e9c0003f0c000 */
/*0370*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x004fea0003800000 */
/*0380*/ MUFU.RCP64H R9, R5 ; /* 0x0000000500097308 */
/* 0x001e220000001800 */
/*0390*/ IMAD.MOV.U32 R8, RZ, RZ, 0x1 ; /* 0x00000001ff087424 */
/* 0x000fe200078e00ff */
/*03a0*/ FSETP.GEU.AND P1, PT, |R3|, 6.5827683646048100446e-37, PT ; /* 0x036000000300780b */
/* 0x000fe20003f2e200 */
/*03b0*/ BSSY B0, 0x500 ; /* 0x0000014000007945 */
/* 0x000fe80003800000 */
/*03c0*/ DFMA R10, -R4, R8, 1 ; /* 0x3ff00000040a742b */
/* 0x001e0c0000000108 */
/*03d0*/ DFMA R10, R10, R10, R10 ; /* 0x0000000a0a0a722b */
/* 0x001e0c000000000a */
/*03e0*/ DFMA R10, R8, R10, R8 ; /* 0x0000000a080a722b */
/* 0x001e0c0000000008 */
/*03f0*/ DFMA R8, -R4, R10, 1 ; /* 0x3ff000000408742b */
/* 0x001e0c000000010a */
/*0400*/ DFMA R8, R10, R8, R10 ; /* 0x000000080a08722b */
/* 0x001e0c000000000a */
/*0410*/ DMUL R10, R2, R8 ; /* 0x00000008020a7228 */
/* 0x001e0c0000000000 */
/*0420*/ DFMA R12, -R4, R10, R2 ; /* 0x0000000a040c722b */
/* 0x001e0c0000000102 */
/*0430*/ DFMA R8, R8, R12, R10 ; /* 0x0000000c0808722b */
/* 0x001e14000000000a */
/*0440*/ FFMA R0, RZ, R5, R9 ; /* 0x00000005ff007223 */
/* 0x001fca0000000009 */
/*0450*/ FSETP.GT.AND P0, PT, |R0|, 1.469367938527859385e-39, PT ; /* 0x001000000000780b */
/* 0x000fda0003f04200 */
/*0460*/ @P0 BRA P1, 0x4f0 ; /* 0x0000008000000947 */
/* 0x000fea0000800000 */
/*0470*/ IMAD.MOV.U32 R14, RZ, RZ, R2 ; /* 0x000000ffff0e7224 */
/* 0x000fe200078e0002 */
/*0480*/ MOV R0, 0x4d0 ; /* 0x000004d000007802 */
/* 0x000fe20000000f00 */
/*0490*/ IMAD.MOV.U32 R15, RZ, RZ, R3 ; /* 0x000000ffff0f7224 */
/* 0x000fe400078e0003 */
/*04a0*/ IMAD.MOV.U32 R2, RZ, RZ, R4 ; /* 0x000000ffff027224 */
/* 0x000fe400078e0004 */
/*04b0*/ IMAD.MOV.U32 R13, RZ, RZ, R5 ; /* 0x000000ffff0d7224 */
/* 0x000fe400078e0005 */
/*04c0*/ CALL.REL.NOINC 0x520 ; /* 0x0000005000007944 */
/* 0x002fea0003c00000 */
/*04d0*/ IMAD.MOV.U32 R8, RZ, RZ, R10 ; /* 0x000000ffff087224 */
/* 0x000fe400078e000a */
/*04e0*/ IMAD.MOV.U32 R9, RZ, RZ, R11 ; /* 0x000000ffff097224 */
/* 0x000fe400078e000b */
/*04f0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0500*/ STG.E.64 [R6.64], R8 ; /* 0x0000000806007986 */
/* 0x000fe2000c101b04 */
/*0510*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0520*/ FSETP.GEU.AND P0, PT, |R13|.reuse, 1.469367938527859385e-39, PT ; /* 0x001000000d00780b */
/* 0x040fe20003f0e200 */
/*0530*/ IMAD.MOV.U32 R12, RZ, RZ, R2.reuse ; /* 0x000000ffff0c7224 */
/* 0x100fe200078e0002 */
/*0540*/ LOP3.LUT R10, R13, 0x800fffff, RZ, 0xc0, !PT ; /* 0x800fffff0d0a7812 */
/* 0x000fe200078ec0ff */
/*0550*/ IMAD.MOV.U32 R23, RZ, RZ, 0x1ca00000 ; /* 0x1ca00000ff177424 */
/* 0x000fe200078e00ff */
/*0560*/ FSETP.GEU.AND P2, PT, |R15|.reuse, 1.469367938527859385e-39, PT ; /* 0x001000000f00780b */
/* 0x040fe20003f4e200 */
/*0570*/ IMAD.MOV.U32 R4, RZ, RZ, 0x1 ; /* 0x00000001ff047424 */
/* 0x000fe200078e00ff */
/*0580*/ LOP3.LUT R11, R10, 0x3ff00000, RZ, 0xfc, !PT ; /* 0x3ff000000a0b7812 */
/* 0x000fe200078efcff */
/*0590*/ IMAD.MOV.U32 R10, RZ, RZ, R2 ; /* 0x000000ffff0a7224 */
/* 0x000fe200078e0002 */
/*05a0*/ LOP3.LUT R22, R15, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff000000f167812 */
/* 0x000fe200078ec0ff */
/*05b0*/ IMAD.MOV.U32 R2, RZ, RZ, R14 ; /* 0x000000ffff027224 */
/* 0x000fe200078e000e */
/*05c0*/ LOP3.LUT R25, R13, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff000000d197812 */
/* 0x000fe200078ec0ff */
/*05d0*/ BSSY B2, 0xac0 ; /* 0x000004e000027945 */
/* 0x000fe40003800000 */
/*05e0*/ @!P0 DMUL R10, R12, 8.98846567431157953865e+307 ; /* 0x7fe000000c0a8828 */
/* 0x000e220000000000 */
/*05f0*/ ISETP.GE.U32.AND P1, PT, R22, R25, PT ; /* 0x000000191600720c */
/* 0x000fe20003f26070 */
/*0600*/ IMAD.MOV.U32 R24, RZ, RZ, R22 ; /* 0x000000ffff187224 */
/* 0x000fc400078e0016 */
/*0610*/ @!P2 LOP3.LUT R3, R13, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff000000d03a812 */
/* 0x000fe200078ec0ff */
/*0620*/ @!P2 IMAD.MOV.U32 R18, RZ, RZ, RZ ; /* 0x000000ffff12a224 */
/* 0x000fe200078e00ff */
/*0630*/ MUFU.RCP64H R5, R11 ; /* 0x0000000b00057308 */
/* 0x001e240000001800 */
/*0640*/ @!P2 ISETP.GE.U32.AND P3, PT, R22, R3, PT ; /* 0x000000031600a20c */
/* 0x000fe40003f66070 */
/*0650*/ SEL R3, R23.reuse, 0x63400000, !P1 ; /* 0x6340000017037807 */
/* 0x040fe40004800000 */
/*0660*/ @!P2 SEL R19, R23, 0x63400000, !P3 ; /* 0x634000001713a807 */
/* 0x000fe40005800000 */
/*0670*/ LOP3.LUT R3, R3, 0x800fffff, R15, 0xf8, !PT ; /* 0x800fffff03037812 */
/* 0x000fc400078ef80f */
/*0680*/ @!P2 LOP3.LUT R19, R19, 0x80000000, R15, 0xf8, !PT ; /* 0x800000001313a812 */
/* 0x000fe400078ef80f */
/*0690*/ @!P0 LOP3.LUT R25, R11, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff000000b198812 */
/* 0x000fe400078ec0ff */
/*06a0*/ @!P2 LOP3.LUT R19, R19, 0x100000, RZ, 0xfc, !PT ; /* 0x001000001313a812 */
/* 0x000fe200078efcff */
/*06b0*/ DFMA R16, R4, -R10, 1 ; /* 0x3ff000000410742b */
/* 0x001e22000000080a */
/*06c0*/ IADD3 R26, R25, -0x1, RZ ; /* 0xffffffff191a7810 */
/* 0x000fc80007ffe0ff */
/*06d0*/ @!P2 DFMA R2, R2, 2, -R18 ; /* 0x400000000202a82b */
/* 0x000fc80000000812 */
/*06e0*/ DFMA R16, R16, R16, R16 ; /* 0x000000101010722b */
/* 0x001e0c0000000010 */
/*06f0*/ DFMA R16, R4, R16, R4 ; /* 0x000000100410722b */
/* 0x001e220000000004 */
/*0700*/ @!P2 LOP3.LUT R24, R3, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff000000318a812 */
/* 0x000fc800078ec0ff */
/*0710*/ IADD3 R18, R24, -0x1, RZ ; /* 0xffffffff18127810 */
/* 0x000fe20007ffe0ff */
/*0720*/ DFMA R4, R16, -R10, 1 ; /* 0x3ff000001004742b */
/* 0x001e06000000080a */
/*0730*/ ISETP.GT.U32.AND P0, PT, R18, 0x7feffffe, PT ; /* 0x7feffffe1200780c */
/* 0x000fc60003f04070 */
/*0740*/ DFMA R16, R16, R4, R16 ; /* 0x000000041010722b */
/* 0x001e220000000010 */
/*0750*/ ISETP.GT.U32.OR P0, PT, R26, 0x7feffffe, P0 ; /* 0x7feffffe1a00780c */
/* 0x000fca0000704470 */
/*0760*/ DMUL R4, R16, R2 ; /* 0x0000000210047228 */
/* 0x001e0c0000000000 */
/*0770*/ DFMA R18, R4, -R10, R2 ; /* 0x8000000a0412722b */
/* 0x001e0c0000000002 */
/*0780*/ DFMA R18, R16, R18, R4 ; /* 0x000000121012722b */
/* 0x0010620000000004 */
/*0790*/ @P0 BRA 0x960 ; /* 0x000001c000000947 */
/* 0x000fea0003800000 */
/*07a0*/ LOP3.LUT R5, R13, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff000000d057812 */
/* 0x001fe200078ec0ff */
/*07b0*/ IMAD.MOV.U32 R16, RZ, RZ, RZ ; /* 0x000000ffff107224 */
/* 0x000fc600078e00ff */
/*07c0*/ ISETP.GE.U32.AND P0, PT, R22.reuse, R5, PT ; /* 0x000000051600720c */
/* 0x040fe20003f06070 */
/*07d0*/ IMAD.IADD R4, R22, 0x1, -R5 ; /* 0x0000000116047824 */
/* 0x000fc600078e0a05 */
/*07e0*/ SEL R23, R23, 0x63400000, !P0 ; /* 0x6340000017177807 */
/* 0x000fe40004000000 */
/*07f0*/ IMNMX R4, R4, -0x46a00000, !PT ; /* 0xb960000004047817 */
/* 0x000fc80007800200 */
/*0800*/ IMNMX R4, R4, 0x46a00000, PT ; /* 0x46a0000004047817 */
/* 0x000fca0003800200 */
/*0810*/ IMAD.IADD R14, R4, 0x1, -R23 ; /* 0x00000001040e7824 */
/* 0x000fca00078e0a17 */
/*0820*/ IADD3 R17, R14, 0x7fe00000, RZ ; /* 0x7fe000000e117810 */
/* 0x000fcc0007ffe0ff */
/*0830*/ DMUL R4, R18, R16 ; /* 0x0000001012047228 */
/* 0x002e140000000000 */
/*0840*/ FSETP.GTU.AND P0, PT, |R5|, 1.469367938527859385e-39, PT ; /* 0x001000000500780b */
/* 0x001fda0003f0c200 */
/*0850*/ @P0 BRA 0xab0 ; /* 0x0000025000000947 */
/* 0x000fea0003800000 */
/*0860*/ DFMA R2, R18, -R10, R2 ; /* 0x8000000a1202722b */
/* 0x000e220000000002 */
/*0870*/ IMAD.MOV.U32 R16, RZ, RZ, RZ ; /* 0x000000ffff107224 */
/* 0x000fd200078e00ff */
/*0880*/ FSETP.NEU.AND P0, PT, R3.reuse, RZ, PT ; /* 0x000000ff0300720b */
/* 0x041fe40003f0d000 */
/*0890*/ LOP3.LUT R13, R3, 0x80000000, R13, 0x48, !PT ; /* 0x80000000030d7812 */
/* 0x000fc800078e480d */
/*08a0*/ LOP3.LUT R17, R13, R17, RZ, 0xfc, !PT ; /* 0x000000110d117212 */
/* 0x000fce00078efcff */
/*08b0*/ @!P0 BRA 0xab0 ; /* 0x000001f000008947 */
/* 0x000fea0003800000 */
/*08c0*/ IMAD.MOV R3, RZ, RZ, -R14 ; /* 0x000000ffff037224 */
/* 0x000fe200078e0a0e */
/*08d0*/ DMUL.RP R16, R18, R16 ; /* 0x0000001012107228 */
/* 0x000e220000008000 */
/*08e0*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x000fcc00078e00ff */
/*08f0*/ DFMA R2, R4, -R2, R18 ; /* 0x800000020402722b */
/* 0x000e460000000012 */
/*0900*/ LOP3.LUT R13, R17, R13, RZ, 0x3c, !PT ; /* 0x0000000d110d7212 */
/* 0x001fc600078e3cff */
/*0910*/ IADD3 R2, -R14, -0x43300000, RZ ; /* 0xbcd000000e027810 */
/* 0x002fc80007ffe1ff */
/*0920*/ FSETP.NEU.AND P0, PT, |R3|, R2, PT ; /* 0x000000020300720b */
/* 0x000fc80003f0d200 */
/*0930*/ FSEL R4, R16, R4, !P0 ; /* 0x0000000410047208 */
/* 0x000fe40004000000 */
/*0940*/ FSEL R5, R13, R5, !P0 ; /* 0x000000050d057208 */
/* 0x000fe20004000000 */
/*0950*/ BRA 0xab0 ; /* 0x0000015000007947 */
/* 0x000fea0003800000 */
/*0960*/ DSETP.NAN.AND P0, PT, R14, R14, PT ; /* 0x0000000e0e00722a */
/* 0x000e9c0003f08000 */
/*0970*/ @P0 BRA 0xa90 ; /* 0x0000011000000947 */
/* 0x004fea0003800000 */
/*0980*/ DSETP.NAN.AND P0, PT, R12, R12, PT ; /* 0x0000000c0c00722a */
/* 0x000e9c0003f08000 */
/*0990*/ @P0 BRA 0xa60 ; /* 0x000000c000000947 */
/* 0x004fea0003800000 */
/*09a0*/ ISETP.NE.AND P0, PT, R24, R25, PT ; /* 0x000000191800720c */
/* 0x000fe20003f05270 */
/*09b0*/ IMAD.MOV.U32 R4, RZ, RZ, 0x0 ; /* 0x00000000ff047424 */
/* 0x001fe400078e00ff */
/*09c0*/ IMAD.MOV.U32 R5, RZ, RZ, -0x80000 ; /* 0xfff80000ff057424 */
/* 0x000fd400078e00ff */
/*09d0*/ @!P0 BRA 0xab0 ; /* 0x000000d000008947 */
/* 0x000fea0003800000 */
/*09e0*/ ISETP.NE.AND P0, PT, R24, 0x7ff00000, PT ; /* 0x7ff000001800780c */
/* 0x000fe40003f05270 */
/*09f0*/ LOP3.LUT R5, R15, 0x80000000, R13, 0x48, !PT ; /* 0x800000000f057812 */
/* 0x000fe400078e480d */
/*0a00*/ ISETP.EQ.OR P0, PT, R25, RZ, !P0 ; /* 0x000000ff1900720c */
/* 0x000fda0004702670 */
/*0a10*/ @P0 LOP3.LUT R2, R5, 0x7ff00000, RZ, 0xfc, !PT ; /* 0x7ff0000005020812 */
/* 0x000fe200078efcff */
/*0a20*/ @!P0 IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff048224 */
/* 0x000fe400078e00ff */
/*0a30*/ @P0 IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff040224 */
/* 0x000fe400078e00ff */
/*0a40*/ @P0 IMAD.MOV.U32 R5, RZ, RZ, R2 ; /* 0x000000ffff050224 */
/* 0x000fe200078e0002 */
/*0a50*/ BRA 0xab0 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*0a60*/ LOP3.LUT R5, R13, 0x80000, RZ, 0xfc, !PT ; /* 0x000800000d057812 */
/* 0x001fe200078efcff */
/*0a70*/ IMAD.MOV.U32 R4, RZ, RZ, R12 ; /* 0x000000ffff047224 */
/* 0x000fe200078e000c */
/*0a80*/ BRA 0xab0 ; /* 0x0000002000007947 */
/* 0x000fea0003800000 */
/*0a90*/ LOP3.LUT R5, R15, 0x80000, RZ, 0xfc, !PT ; /* 0x000800000f057812 */
/* 0x001fe200078efcff */
/*0aa0*/ IMAD.MOV.U32 R4, RZ, RZ, R14 ; /* 0x000000ffff047224 */
/* 0x000fe400078e000e */
/*0ab0*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*0ac0*/ IMAD.MOV.U32 R2, RZ, RZ, R0 ; /* 0x000000ffff027224 */
/* 0x000fe400078e0000 */
/*0ad0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x0 ; /* 0x00000000ff037424 */
/* 0x000fc400078e00ff */
/*0ae0*/ IMAD.MOV.U32 R10, RZ, RZ, R4 ; /* 0x000000ffff0a7224 */
/* 0x000fe400078e0004 */
/*0af0*/ IMAD.MOV.U32 R11, RZ, RZ, R5 ; /* 0x000000ffff0b7224 */
/* 0x000fe200078e0005 */
/*0b00*/ RET.REL.NODEC R2 0x0 ; /* 0xfffff4f002007950 */
/* 0x000fec0003c3ffff */
/*0b10*/ BRA 0xb10; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0b20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ba0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0be0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6updateidPdS_S_
.globl _Z6updateidPdS_S_
.p2align 8
.type _Z6updateidPdS_S_,@function
_Z6updateidPdS_S_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x28
s_load_b32 s3, s[0:1], 0x34
v_bfe_u32 v1, v0, 10, 10
s_load_b32 s4, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_mul_i32 s2, s2, s15
s_lshr_b32 s5, s3, 16
s_add_i32 s2, s2, s14
s_delay_alu instid0(SALU_CYCLE_1)
v_mad_u64_u32 v[2:3], null, s2, s5, v[1:2]
v_and_b32_e32 v3, 0x3ff, v0
s_and_b32 s2, s3, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[0:1], null, v2, s2, v[3:4]
s_mov_b32 s2, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s4, v0
s_cbranch_execz .LBB0_5
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x10
s_load_b64 s[4:5], s[0:1], 0x20
v_ashrrev_i32_e32 v1, 31, v0
v_mov_b32_e32 v8, 0
v_mov_b32_e32 v9, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 3, v[0:1]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s2, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v3, vcc_lo
v_add_co_u32 v4, s2, s4, v2
v_add_co_ci_u32_e64 v5, s2, s5, v3, s2
global_load_b64 v[6:7], v[0:1], off
s_mov_b32 s2, exec_lo
s_waitcnt vmcnt(0)
v_cmpx_neq_f64_e32 0, v[6:7]
s_cbranch_execz .LBB0_3
global_load_b64 v[8:9], v[4:5], off
s_waitcnt vmcnt(0)
v_div_scale_f64 v[10:11], null, v[6:7], v[6:7], v[8:9]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f64_e32 v[12:13], v[10:11]
s_waitcnt_depctr 0xfff
v_fma_f64 v[14:15], -v[10:11], v[12:13], 1.0
v_fma_f64 v[12:13], v[12:13], v[14:15], v[12:13]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[14:15], -v[10:11], v[12:13], 1.0
v_fma_f64 v[12:13], v[12:13], v[14:15], v[12:13]
v_div_scale_f64 v[14:15], vcc_lo, v[8:9], v[6:7], v[8:9]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[16:17], v[14:15], v[12:13]
v_fma_f64 v[10:11], -v[10:11], v[16:17], v[14:15]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fmas_f64 v[10:11], v[10:11], v[12:13], v[16:17]
v_div_fixup_f64 v[8:9], v[10:11], v[6:7], v[8:9]
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s2
s_load_b64 s[2:3], s[0:1], 0x18
global_store_b64 v[4:5], v[8:9], off
s_load_b64 s[0:1], s[0:1], 0x8
s_waitcnt lgkmcnt(0)
v_add_co_u32 v6, vcc_lo, s2, v2
v_add_co_ci_u32_e32 v7, vcc_lo, s3, v3, vcc_lo
v_add_co_u32 v2, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
global_load_b64 v[4:5], v[6:7], off
global_load_b64 v[6:7], v[0:1], off
s_waitcnt vmcnt(0)
v_fma_f64 v[4:5], v[4:5], s[0:1], v[6:7]
global_store_b64 v[0:1], v[4:5], off
global_load_b64 v[2:3], v[2:3], off
s_waitcnt vmcnt(0)
v_fma_f64 v[2:3], -v[2:3], s[0:1], 1.0
s_delay_alu instid0(VALU_DEP_1)
v_cmp_nge_f64_e32 vcc_lo, 0, v[2:3]
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_5
v_div_scale_f64 v[6:7], null, v[2:3], v[2:3], v[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f64_e32 v[8:9], v[6:7]
s_waitcnt_depctr 0xfff
v_fma_f64 v[10:11], -v[6:7], v[8:9], 1.0
v_fma_f64 v[8:9], v[8:9], v[10:11], v[8:9]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[10:11], -v[6:7], v[8:9], 1.0
v_fma_f64 v[8:9], v[8:9], v[10:11], v[8:9]
v_div_scale_f64 v[10:11], vcc_lo, v[4:5], v[2:3], v[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[12:13], v[10:11], v[8:9]
v_fma_f64 v[6:7], -v[6:7], v[12:13], v[10:11]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fmas_f64 v[6:7], v[6:7], v[8:9], v[12:13]
v_div_fixup_f64 v[2:3], v[6:7], v[2:3], v[4:5]
global_store_b64 v[0:1], v[2:3], off
.LBB0_5:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6updateidPdS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 18
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6updateidPdS_S_, .Lfunc_end0-_Z6updateidPdS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 8
.size: 8
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6updateidPdS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6updateidPdS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 18
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00030b3f_00000000-6_update.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z31__device_stub__Z6updateidPdS_S_idPdS_S_
.type _Z31__device_stub__Z6updateidPdS_S_idPdS_S_, @function
_Z31__device_stub__Z6updateidPdS_S_idPdS_S_:
.LFB2051:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movl %edi, 44(%rsp)
movsd %xmm0, 32(%rsp)
movq %rsi, 24(%rsp)
movq %rdx, 16(%rsp)
movq %rcx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 44(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 184
pushq 56(%rsp)
.cfi_def_cfa_offset 192
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z6updateidPdS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z31__device_stub__Z6updateidPdS_S_idPdS_S_, .-_Z31__device_stub__Z6updateidPdS_S_idPdS_S_
.globl _Z6updateidPdS_S_
.type _Z6updateidPdS_S_, @function
_Z6updateidPdS_S_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z6updateidPdS_S_idPdS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z6updateidPdS_S_, .-_Z6updateidPdS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z6updateidPdS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z6updateidPdS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "update.hip"
.globl _Z21__device_stub__updateidPdS_S_ # -- Begin function _Z21__device_stub__updateidPdS_S_
.p2align 4, 0x90
.type _Z21__device_stub__updateidPdS_S_,@function
_Z21__device_stub__updateidPdS_S_: # @_Z21__device_stub__updateidPdS_S_
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movl %edi, 12(%rsp)
movsd %xmm0, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 88(%rsp), %rax
movq %rax, 104(%rsp)
leaq 80(%rsp), %rax
movq %rax, 112(%rsp)
leaq 72(%rsp), %rax
movq %rax, 120(%rsp)
leaq 64(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z6updateidPdS_S_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end0:
.size _Z21__device_stub__updateidPdS_S_, .Lfunc_end0-_Z21__device_stub__updateidPdS_S_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6updateidPdS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6updateidPdS_S_,@object # @_Z6updateidPdS_S_
.section .rodata,"a",@progbits
.globl _Z6updateidPdS_S_
.p2align 3, 0x0
_Z6updateidPdS_S_:
.quad _Z21__device_stub__updateidPdS_S_
.size _Z6updateidPdS_S_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z6updateidPdS_S_"
.size .L__unnamed_1, 18
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__updateidPdS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6updateidPdS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <iostream>
#define BLOCKSIZE 1024
__global__ void StupidSumArray(int* array, int* result) {
int tid = blockDim.x * blockIdx.x + threadIdx.x;
result[tid] = 0;
for (int i = tid * 1024; i < (tid + 1) * 1024; ++i) {
result[tid] += array[i];
}
}
int main() {
int N = 1 << 20;
int *h_x = new int[N];
for (int i = 0; i < N; ++i) {
h_x[i] = 1;
}
int *d_x;
int size = sizeof(int) * N;
cudaMalloc(&d_x, size);
int* h_result = new int[1024];
for (int i = 0; i < BLOCKSIZE; ++i) {
h_result[i] = 0;
}
int *d_result;
cudaMalloc(&d_result, sizeof(int) * 1024);
cudaMemcpy(d_x, h_x, size, cudaMemcpyHostToDevice);
cudaMemcpy(d_result, h_result, size, cudaMemcpyHostToDevice);
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaEventRecord(start);
StupidSumArray<<<1, 1024>>>(d_x, d_result);
cudaEventRecord(stop);
cudaMemcpy(h_result, d_result, sizeof(int) * 1024, cudaMemcpyDeviceToHost);
cudaEventSynchronize(stop);
float ms;
cudaEventElapsedTime(&ms, start, stop);
for (int i = 0; i < 1024; ++i) {
std::cout << i << " " << h_result[i] << std::endl;
}
std::cout << ms << std::endl;
cudaFree(d_x);
cudaFree(d_result);
delete[] h_result;
delete[] h_x;
} | code for sm_80
Function : _Z14StupidSumArrayPiS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e220000002500 */
/*0020*/ IMAD.MOV.U32 R11, RZ, RZ, 0x4 ; /* 0x00000004ff0b7424 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R2, R2, c[0x0][0x0], R3 ; /* 0x0000000002027a24 */
/* 0x001fc800078e0203 */
/*0060*/ IMAD.SHL.U32 R6, R2.reuse, 0x400, RZ ; /* 0x0000040002067824 */
/* 0x040fe400078e00ff */
/*0070*/ IMAD.WIDE R2, R2, R11, c[0x0][0x168] ; /* 0x00005a0002027625 */
/* 0x000fc600078e020b */
/*0080*/ ISETP.NE.AND P0, PT, R6, 0x7ffffc00, PT ; /* 0x7ffffc000600780c */
/* 0x000fe40003f05270 */
/*0090*/ STG.E [R2.64], RZ ; /* 0x000000ff02007986 */
/* 0x0001f6000c101904 */
/*00a0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*00b0*/ IADD3 R0, R6.reuse, 0x400, RZ ; /* 0x0000040006007810 */
/* 0x041fe20007ffe0ff */
/*00c0*/ BSSY B0, 0x250 ; /* 0x0000018000007945 */
/* 0x000fe20003800000 */
/*00d0*/ IADD3 R5, R6, 0x1, RZ ; /* 0x0000000106057810 */
/* 0x000fc40007ffe0ff */
/*00e0*/ LOP3.LUT R4, RZ, R6, RZ, 0x33, !PT ; /* 0x00000006ff047212 */
/* 0x000fe400078e33ff */
/*00f0*/ IMNMX R5, R0, R5, !PT ; /* 0x0000000500057217 */
/* 0x000fc80007800200 */
/*0100*/ LOP3.LUT R7, R5.reuse, 0x1, RZ, 0xc0, !PT ; /* 0x0000000105077812 */
/* 0x040fe400078ec0ff */
/*0110*/ IADD3 R4, R5, R4, RZ ; /* 0x0000000405047210 */
/* 0x000fe40007ffe0ff */
/*0120*/ ISETP.NE.U32.AND P1, PT, R7, 0x1, PT ; /* 0x000000010700780c */
/* 0x000fe20003f25070 */
/*0130*/ IMAD.MOV.U32 R7, RZ, RZ, RZ ; /* 0x000000ffff077224 */
/* 0x000fe200078e00ff */
/*0140*/ ISETP.GE.U32.AND P0, PT, R4, 0x3, PT ; /* 0x000000030400780c */
/* 0x000fd60003f06070 */
/*0150*/ @P1 BRA 0x240 ; /* 0x000000e000001947 */
/* 0x000fea0003800000 */
/*0160*/ IMAD.WIDE R4, R6, R11, c[0x0][0x160] ; /* 0x0000580006047625 */
/* 0x000fe200078e020b */
/*0170*/ HFMA2.MMA R7, -RZ, RZ, 0, 0 ; /* 0x00000000ff077435 */
/* 0x000fc600000001ff */
/*0180*/ IMAD.MOV.U32 R9, RZ, RZ, R4 ; /* 0x000000ffff097224 */
/* 0x000fe400078e0004 */
/*0190*/ IMAD.MOV.U32 R8, RZ, RZ, RZ ; /* 0x000000ffff087224 */
/* 0x000fe400078e00ff */
/*01a0*/ IMAD.MOV.U32 R4, RZ, RZ, R9 ; /* 0x000000ffff047224 */
/* 0x000fcc00078e0009 */
/*01b0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x0010a2000c1e1900 */
/*01c0*/ IADD3 R8, R8, -0x4, RZ ; /* 0xfffffffc08087810 */
/* 0x000fe40007ffe0ff */
/*01d0*/ IADD3 R9, P2, R9, 0x4, RZ ; /* 0x0000000409097810 */
/* 0x000fe40007f5e0ff */
/*01e0*/ ISETP.NE.AND P1, PT, R8, -0x4, PT ; /* 0xfffffffc0800780c */
/* 0x000fe40003f25270 */
/*01f0*/ IADD3 R6, R6, 0x1, RZ ; /* 0x0000000106067810 */
/* 0x000fe20007ffe0ff */
/*0200*/ IMAD.X R5, RZ, RZ, R5, P2 ; /* 0x000000ffff057224 */
/* 0x001fe400010e0605 */
/*0210*/ IMAD.IADD R7, R4, 0x1, R7 ; /* 0x0000000104077824 */
/* 0x004fca00078e0207 */
/*0220*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x0001e6000c101904 */
/*0230*/ @P1 BRA 0x1a0 ; /* 0xffffff6000001947 */
/* 0x000fea000383ffff */
/*0240*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0250*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0260*/ IMAD.WIDE R4, R6, R11, c[0x0][0x160] ; /* 0x0000580006047625 */
/* 0x000fca00078e020b */
/*0270*/ IADD3 R8, P0, R4, 0x8, RZ ; /* 0x0000000804087810 */
/* 0x000fc80007f1e0ff */
/*0280*/ IADD3.X R9, RZ, R5, RZ, P0, !PT ; /* 0x00000005ff097210 */
/* 0x000fc600007fe4ff */
/*0290*/ IMAD.MOV.U32 R4, RZ, RZ, R8 ; /* 0x000000ffff047224 */
/* 0x000fe400078e0008 */
/*02a0*/ IMAD.MOV.U32 R5, RZ, RZ, R9 ; /* 0x000000ffff057224 */
/* 0x000fca00078e0009 */
/*02b0*/ LDG.E R8, [R4.64+-0x8] ; /* 0xfffff80404087981 */
/* 0x004ea4000c1e1900 */
/*02c0*/ IADD3 R9, R8, R7, RZ ; /* 0x0000000708097210 */
/* 0x004fca0007ffe0ff */
/*02d0*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x0003e8000c101904 */
/*02e0*/ LDG.E R8, [R4.64+-0x4] ; /* 0xfffffc0404087981 */
/* 0x000ea4000c1e1900 */
/*02f0*/ IMAD.IADD R11, R9, 0x1, R8 ; /* 0x00000001090b7824 */
/* 0x004fca00078e0208 */
/*0300*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x0005e8000c101904 */
/*0310*/ LDG.E R8, [R4.64] ; /* 0x0000000404087981 */
/* 0x000ee4000c1e1900 */
/*0320*/ IMAD.IADD R13, R11, 0x1, R8 ; /* 0x000000010b0d7824 */
/* 0x008fca00078e0208 */
/*0330*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x0005e8000c101904 */
/*0340*/ LDG.E R8, [R4.64+0x4] ; /* 0x0000040404087981 */
/* 0x000ee2000c1e1900 */
/*0350*/ IADD3 R6, R6, 0x4, RZ ; /* 0x0000000406067810 */
/* 0x000fc80007ffe0ff */
/*0360*/ ISETP.GE.AND P0, PT, R6, R0, PT ; /* 0x000000000600720c */
/* 0x000fe40003f06270 */
/*0370*/ IADD3 R7, R13, R8, RZ ; /* 0x000000080d077210 */
/* 0x009fe40007ffe0ff */
/*0380*/ IADD3 R8, P1, R4, 0x10, RZ ; /* 0x0000001004087810 */
/* 0x000fc60007f3e0ff */
/*0390*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x0005e4000c101904 */
/*03a0*/ IMAD.X R9, RZ, RZ, R5, P1 ; /* 0x000000ffff097224 */
/* 0x002fc800008e0605 */
/*03b0*/ @!P0 BRA 0x290 ; /* 0xfffffed000008947 */
/* 0x000fea000383ffff */
/*03c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*03d0*/ BRA 0x3d0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*03e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0400*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0410*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0420*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0430*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0440*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0450*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0460*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0470*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <iostream>
#define BLOCKSIZE 1024
__global__ void StupidSumArray(int* array, int* result) {
int tid = blockDim.x * blockIdx.x + threadIdx.x;
result[tid] = 0;
for (int i = tid * 1024; i < (tid + 1) * 1024; ++i) {
result[tid] += array[i];
}
}
int main() {
int N = 1 << 20;
int *h_x = new int[N];
for (int i = 0; i < N; ++i) {
h_x[i] = 1;
}
int *d_x;
int size = sizeof(int) * N;
cudaMalloc(&d_x, size);
int* h_result = new int[1024];
for (int i = 0; i < BLOCKSIZE; ++i) {
h_result[i] = 0;
}
int *d_result;
cudaMalloc(&d_result, sizeof(int) * 1024);
cudaMemcpy(d_x, h_x, size, cudaMemcpyHostToDevice);
cudaMemcpy(d_result, h_result, size, cudaMemcpyHostToDevice);
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaEventRecord(start);
StupidSumArray<<<1, 1024>>>(d_x, d_result);
cudaEventRecord(stop);
cudaMemcpy(h_result, d_result, sizeof(int) * 1024, cudaMemcpyDeviceToHost);
cudaEventSynchronize(stop);
float ms;
cudaEventElapsedTime(&ms, start, stop);
for (int i = 0; i < 1024; ++i) {
std::cout << i << " " << h_result[i] << std::endl;
}
std::cout << ms << std::endl;
cudaFree(d_x);
cudaFree(d_result);
delete[] h_result;
delete[] h_x;
} | .file "tmpxft_0016601a_00000000-6_main.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z36__device_stub__Z14StupidSumArrayPiS_PiS_
.type _Z36__device_stub__Z14StupidSumArrayPiS_PiS_, @function
_Z36__device_stub__Z14StupidSumArrayPiS_PiS_:
.LFB3694:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z14StupidSumArrayPiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3694:
.size _Z36__device_stub__Z14StupidSumArrayPiS_PiS_, .-_Z36__device_stub__Z14StupidSumArrayPiS_PiS_
.globl _Z14StupidSumArrayPiS_
.type _Z14StupidSumArrayPiS_, @function
_Z14StupidSumArrayPiS_:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z36__device_stub__Z14StupidSumArrayPiS_PiS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _Z14StupidSumArrayPiS_, .-_Z14StupidSumArrayPiS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string " "
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $88, %rsp
.cfi_def_cfa_offset 144
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $4194304, %edi
call _Znam@PLT
movq %rax, 8(%rsp)
leaq 4194304(%rax), %rdx
.L12:
movl $1, (%rax)
addq $4, %rax
cmpq %rax, %rdx
jne .L12
leaq 16(%rsp), %rdi
movl $4194304, %esi
call cudaMalloc@PLT
movl $4096, %edi
call _Znam@PLT
movq %rax, %r13
leaq 4096(%rax), %rdx
.L13:
movl $0, (%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L13
leaq 24(%rsp), %rdi
movl $4096, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $4194304, %edx
movq 8(%rsp), %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $4194304, %edx
movq %r13, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
leaq 32(%rsp), %rdi
call cudaEventCreate@PLT
leaq 40(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 32(%rsp), %rdi
call cudaEventRecord@PLT
movl $1024, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movl $1, %ecx
movq 48(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L25
.L14:
movl $0, %esi
movq 40(%rsp), %rdi
call cudaEventRecord@PLT
movl $2, %ecx
movl $4096, %edx
movq 24(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
movq 40(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 60(%rsp), %rdi
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
call cudaEventElapsedTime@PLT
movl $0, %ebp
leaq _ZSt4cout(%rip), %r15
leaq .LC0(%rip), %r14
jmp .L19
.L25:
movq 24(%rsp), %rsi
movq 16(%rsp), %rdi
call _Z36__device_stub__Z14StupidSumArrayPiS_PiS_
jmp .L14
.L28:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L26
call _ZSt16__throw_bad_castv@PLT
.L26:
call __stack_chk_fail@PLT
.L17:
movq %r12, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r12), %rax
movl $10, %esi
movq %r12, %rdi
call *48(%rax)
movl %eax, %esi
.L18:
movsbl %sil, %esi
movq %rbx, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
addq $1, %rbp
cmpq $1024, %rbp
je .L27
.L19:
movl %ebp, %esi
movq %r15, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbx
movl $1, %edx
movq %r14, %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl 0(%r13,%rbp,4), %esi
movq %rbx, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbx
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r12
testq %r12, %r12
je .L28
cmpb $0, 56(%r12)
je .L17
movzbl 67(%r12), %esi
jmp .L18
.L27:
pxor %xmm0, %xmm0
cvtss2sd 60(%rsp), %xmm0
leaq _ZSt4cout(%rip), %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq %r13, %rdi
call _ZdaPv@PLT
movq 8(%rsp), %rdi
call _ZdaPv@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L29
movl $0, %eax
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L29:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z14StupidSumArrayPiS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z14StupidSumArrayPiS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <iostream>
#define BLOCKSIZE 1024
__global__ void StupidSumArray(int* array, int* result) {
int tid = blockDim.x * blockIdx.x + threadIdx.x;
result[tid] = 0;
for (int i = tid * 1024; i < (tid + 1) * 1024; ++i) {
result[tid] += array[i];
}
}
int main() {
int N = 1 << 20;
int *h_x = new int[N];
for (int i = 0; i < N; ++i) {
h_x[i] = 1;
}
int *d_x;
int size = sizeof(int) * N;
cudaMalloc(&d_x, size);
int* h_result = new int[1024];
for (int i = 0; i < BLOCKSIZE; ++i) {
h_result[i] = 0;
}
int *d_result;
cudaMalloc(&d_result, sizeof(int) * 1024);
cudaMemcpy(d_x, h_x, size, cudaMemcpyHostToDevice);
cudaMemcpy(d_result, h_result, size, cudaMemcpyHostToDevice);
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaEventRecord(start);
StupidSumArray<<<1, 1024>>>(d_x, d_result);
cudaEventRecord(stop);
cudaMemcpy(h_result, d_result, sizeof(int) * 1024, cudaMemcpyDeviceToHost);
cudaEventSynchronize(stop);
float ms;
cudaEventElapsedTime(&ms, start, stop);
for (int i = 0; i < 1024; ++i) {
std::cout << i << " " << h_result[i] << std::endl;
}
std::cout << ms << std::endl;
cudaFree(d_x);
cudaFree(d_result);
delete[] h_result;
delete[] h_x;
} | #include <hip/hip_runtime.h>
#include <iostream>
#define BLOCKSIZE 1024
__global__ void StupidSumArray(int* array, int* result) {
int tid = blockDim.x * blockIdx.x + threadIdx.x;
result[tid] = 0;
for (int i = tid * 1024; i < (tid + 1) * 1024; ++i) {
result[tid] += array[i];
}
}
int main() {
int N = 1 << 20;
int *h_x = new int[N];
for (int i = 0; i < N; ++i) {
h_x[i] = 1;
}
int *d_x;
int size = sizeof(int) * N;
hipMalloc(&d_x, size);
int* h_result = new int[1024];
for (int i = 0; i < BLOCKSIZE; ++i) {
h_result[i] = 0;
}
int *d_result;
hipMalloc(&d_result, sizeof(int) * 1024);
hipMemcpy(d_x, h_x, size, hipMemcpyHostToDevice);
hipMemcpy(d_result, h_result, size, hipMemcpyHostToDevice);
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
hipEventRecord(start);
StupidSumArray<<<1, 1024>>>(d_x, d_result);
hipEventRecord(stop);
hipMemcpy(h_result, d_result, sizeof(int) * 1024, hipMemcpyDeviceToHost);
hipEventSynchronize(stop);
float ms;
hipEventElapsedTime(&ms, start, stop);
for (int i = 0; i < 1024; ++i) {
std::cout << i << " " << h_result[i] << std::endl;
}
std::cout << ms << std::endl;
hipFree(d_x);
hipFree(d_result);
delete[] h_result;
delete[] h_x;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <iostream>
#define BLOCKSIZE 1024
__global__ void StupidSumArray(int* array, int* result) {
int tid = blockDim.x * blockIdx.x + threadIdx.x;
result[tid] = 0;
for (int i = tid * 1024; i < (tid + 1) * 1024; ++i) {
result[tid] += array[i];
}
}
int main() {
int N = 1 << 20;
int *h_x = new int[N];
for (int i = 0; i < N; ++i) {
h_x[i] = 1;
}
int *d_x;
int size = sizeof(int) * N;
hipMalloc(&d_x, size);
int* h_result = new int[1024];
for (int i = 0; i < BLOCKSIZE; ++i) {
h_result[i] = 0;
}
int *d_result;
hipMalloc(&d_result, sizeof(int) * 1024);
hipMemcpy(d_x, h_x, size, hipMemcpyHostToDevice);
hipMemcpy(d_result, h_result, size, hipMemcpyHostToDevice);
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
hipEventRecord(start);
StupidSumArray<<<1, 1024>>>(d_x, d_result);
hipEventRecord(stop);
hipMemcpy(h_result, d_result, sizeof(int) * 1024, hipMemcpyDeviceToHost);
hipEventSynchronize(stop);
float ms;
hipEventElapsedTime(&ms, start, stop);
for (int i = 0; i < 1024; ++i) {
std::cout << i << " " << h_result[i] << std::endl;
}
std::cout << ms << std::endl;
hipFree(d_x);
hipFree(d_result);
delete[] h_result;
delete[] h_x;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z14StupidSumArrayPiS_
.globl _Z14StupidSumArrayPiS_
.p2align 8
.type _Z14StupidSumArrayPiS_,@function
_Z14StupidSumArrayPiS_:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x1c
s_load_b64 s[2:3], s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b32_e32 v0, 10, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[2:3], 2, v[1:2]
v_mov_b32_e32 v1, 0
v_add_co_u32 v2, vcc_lo, s2, v2
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
s_mov_b32 s2, exec_lo
global_store_b32 v[2:3], v1, off
v_cmpx_ne_u32_e32 0x7ffffc00, v0
s_cbranch_execz .LBB0_3
global_load_b32 v6, v[2:3], off
s_load_b64 s[0:1], s[0:1], 0x0
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[4:5], 2, v[0:1]
v_add_nc_u32_e32 v1, 0x400, v0
s_waitcnt lgkmcnt(0)
v_add_co_u32 v4, vcc_lo, s0, v4
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v5, vcc_lo
s_mov_b32 s1, 0
.LBB0_2:
global_load_b32 v7, v[4:5], off
v_add_nc_u32_e32 v0, 1, v0
v_add_co_u32 v4, vcc_lo, v4, 4
v_add_co_ci_u32_e32 v5, vcc_lo, 0, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_ge_i32_e64 s0, v0, v1
s_or_b32 s1, s0, s1
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v6, v6, v7
global_store_b32 v[2:3], v6, off
s_and_not1_b32 exec_lo, exec_lo, s1
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z14StupidSumArrayPiS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z14StupidSumArrayPiS_, .Lfunc_end0-_Z14StupidSumArrayPiS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z14StupidSumArrayPiS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z14StupidSumArrayPiS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <iostream>
#define BLOCKSIZE 1024
__global__ void StupidSumArray(int* array, int* result) {
int tid = blockDim.x * blockIdx.x + threadIdx.x;
result[tid] = 0;
for (int i = tid * 1024; i < (tid + 1) * 1024; ++i) {
result[tid] += array[i];
}
}
int main() {
int N = 1 << 20;
int *h_x = new int[N];
for (int i = 0; i < N; ++i) {
h_x[i] = 1;
}
int *d_x;
int size = sizeof(int) * N;
hipMalloc(&d_x, size);
int* h_result = new int[1024];
for (int i = 0; i < BLOCKSIZE; ++i) {
h_result[i] = 0;
}
int *d_result;
hipMalloc(&d_result, sizeof(int) * 1024);
hipMemcpy(d_x, h_x, size, hipMemcpyHostToDevice);
hipMemcpy(d_result, h_result, size, hipMemcpyHostToDevice);
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
hipEventRecord(start);
StupidSumArray<<<1, 1024>>>(d_x, d_result);
hipEventRecord(stop);
hipMemcpy(h_result, d_result, sizeof(int) * 1024, hipMemcpyDeviceToHost);
hipEventSynchronize(stop);
float ms;
hipEventElapsedTime(&ms, start, stop);
for (int i = 0; i < 1024; ++i) {
std::cout << i << " " << h_result[i] << std::endl;
}
std::cout << ms << std::endl;
hipFree(d_x);
hipFree(d_result);
delete[] h_result;
delete[] h_x;
} | .text
.file "main.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z29__device_stub__StupidSumArrayPiS_ # -- Begin function _Z29__device_stub__StupidSumArrayPiS_
.p2align 4, 0x90
.type _Z29__device_stub__StupidSumArrayPiS_,@function
_Z29__device_stub__StupidSumArrayPiS_: # @_Z29__device_stub__StupidSumArrayPiS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z14StupidSumArrayPiS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z29__device_stub__StupidSumArrayPiS_, .Lfunc_end0-_Z29__device_stub__StupidSumArrayPiS_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $112, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $4194304, %edi # imm = 0x400000
callq _Znam
movq %rax, %rbx
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movl $1, (%rbx,%rax,4)
incq %rax
cmpq $1048576, %rax # imm = 0x100000
jne .LBB1_1
# %bb.2:
leaq 16(%rsp), %rdi
movl $4194304, %esi # imm = 0x400000
callq hipMalloc
movl $4096, %edi # imm = 0x1000
callq _Znam
movq %rax, %r14
movl $4096, %edx # imm = 0x1000
movq %rax, %rdi
xorl %esi, %esi
callq memset@PLT
movq %rsp, %rdi
movl $4096, %esi # imm = 0x1000
callq hipMalloc
movq 16(%rsp), %rdi
movl $4194304, %edx # imm = 0x400000
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq (%rsp), %rdi
movl $4194304, %edx # imm = 0x400000
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
leaq 24(%rsp), %rdi
callq hipEventCreate
leaq 8(%rsp), %rdi
callq hipEventCreate
movq 24(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 1023(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 16(%rsp), %rax
movq (%rsp), %rcx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
leaq 104(%rsp), %rax
movq %rax, 32(%rsp)
leaq 96(%rsp), %rax
movq %rax, 40(%rsp)
leaq 80(%rsp), %rdi
leaq 64(%rsp), %rsi
leaq 56(%rsp), %rdx
leaq 48(%rsp), %rcx
callq __hipPopCallConfiguration
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
movq 64(%rsp), %rcx
movl 72(%rsp), %r8d
leaq 32(%rsp), %r9
movl $_Z14StupidSumArrayPiS_, %edi
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
movq 8(%rsp), %rdi
xorl %r15d, %r15d
xorl %esi, %esi
callq hipEventRecord
movq (%rsp), %rsi
movl $4096, %edx # imm = 0x1000
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
callq hipEventSynchronize
movq 24(%rsp), %rsi
movq 8(%rsp), %rdx
leaq 32(%rsp), %rdi
callq hipEventElapsedTime
jmp .LBB1_5
.p2align 4, 0x90
.LBB1_13: # in Loop: Header=BB1_5 Depth=1
movq %r12, %rdi
movq %rax, %r13
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r12), %rax
movq %r12, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r13, %rax
.LBB1_14: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit32
# in Loop: Header=BB1_5 Depth=1
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
incq %r15
cmpq $1024, %r15 # imm = 0x400
je .LBB1_8
.LBB1_5: # =>This Inner Loop Header: Depth=1
movl $_ZSt4cout, %edi
movl %r15d, %esi
callq _ZNSolsEi
movq %rax, %r12
movl $.L.str, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl (%r14,%r15,4), %esi
movq %r12, %rdi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r12
testq %r12, %r12
je .LBB1_15
# %bb.6: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i29
# in Loop: Header=BB1_5 Depth=1
cmpb $0, 56(%r12)
je .LBB1_13
# %bb.7: # in Loop: Header=BB1_5 Depth=1
movzbl 67(%r12), %ecx
jmp .LBB1_14
.LBB1_8:
movss 32(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r15
testq %r15, %r15
je .LBB1_15
# %bb.9: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%r15)
je .LBB1_11
# %bb.10:
movzbl 67(%r15), %ecx
jmp .LBB1_12
.LBB1_11:
movq %r15, %rdi
movq %rax, %r12
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r12, %rax
.LBB1_12: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq 16(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
movq %r14, %rdi
callq _ZdaPv
movq %rbx, %rdi
callq _ZdaPv
xorl %eax, %eax
addq $112, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB1_15:
.cfi_def_cfa_offset 160
callq _ZSt16__throw_bad_castv
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14StupidSumArrayPiS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z14StupidSumArrayPiS_,@object # @_Z14StupidSumArrayPiS_
.section .rodata,"a",@progbits
.globl _Z14StupidSumArrayPiS_
.p2align 3, 0x0
_Z14StupidSumArrayPiS_:
.quad _Z29__device_stub__StupidSumArrayPiS_
.size _Z14StupidSumArrayPiS_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz " "
.size .L.str, 2
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z14StupidSumArrayPiS_"
.size .L__unnamed_1, 23
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z29__device_stub__StupidSumArrayPiS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z14StupidSumArrayPiS_
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z14StupidSumArrayPiS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e220000002500 */
/*0020*/ IMAD.MOV.U32 R11, RZ, RZ, 0x4 ; /* 0x00000004ff0b7424 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R2, R2, c[0x0][0x0], R3 ; /* 0x0000000002027a24 */
/* 0x001fc800078e0203 */
/*0060*/ IMAD.SHL.U32 R6, R2.reuse, 0x400, RZ ; /* 0x0000040002067824 */
/* 0x040fe400078e00ff */
/*0070*/ IMAD.WIDE R2, R2, R11, c[0x0][0x168] ; /* 0x00005a0002027625 */
/* 0x000fc600078e020b */
/*0080*/ ISETP.NE.AND P0, PT, R6, 0x7ffffc00, PT ; /* 0x7ffffc000600780c */
/* 0x000fe40003f05270 */
/*0090*/ STG.E [R2.64], RZ ; /* 0x000000ff02007986 */
/* 0x0001f6000c101904 */
/*00a0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*00b0*/ IADD3 R0, R6.reuse, 0x400, RZ ; /* 0x0000040006007810 */
/* 0x041fe20007ffe0ff */
/*00c0*/ BSSY B0, 0x250 ; /* 0x0000018000007945 */
/* 0x000fe20003800000 */
/*00d0*/ IADD3 R5, R6, 0x1, RZ ; /* 0x0000000106057810 */
/* 0x000fc40007ffe0ff */
/*00e0*/ LOP3.LUT R4, RZ, R6, RZ, 0x33, !PT ; /* 0x00000006ff047212 */
/* 0x000fe400078e33ff */
/*00f0*/ IMNMX R5, R0, R5, !PT ; /* 0x0000000500057217 */
/* 0x000fc80007800200 */
/*0100*/ LOP3.LUT R7, R5.reuse, 0x1, RZ, 0xc0, !PT ; /* 0x0000000105077812 */
/* 0x040fe400078ec0ff */
/*0110*/ IADD3 R4, R5, R4, RZ ; /* 0x0000000405047210 */
/* 0x000fe40007ffe0ff */
/*0120*/ ISETP.NE.U32.AND P1, PT, R7, 0x1, PT ; /* 0x000000010700780c */
/* 0x000fe20003f25070 */
/*0130*/ IMAD.MOV.U32 R7, RZ, RZ, RZ ; /* 0x000000ffff077224 */
/* 0x000fe200078e00ff */
/*0140*/ ISETP.GE.U32.AND P0, PT, R4, 0x3, PT ; /* 0x000000030400780c */
/* 0x000fd60003f06070 */
/*0150*/ @P1 BRA 0x240 ; /* 0x000000e000001947 */
/* 0x000fea0003800000 */
/*0160*/ IMAD.WIDE R4, R6, R11, c[0x0][0x160] ; /* 0x0000580006047625 */
/* 0x000fe200078e020b */
/*0170*/ HFMA2.MMA R7, -RZ, RZ, 0, 0 ; /* 0x00000000ff077435 */
/* 0x000fc600000001ff */
/*0180*/ IMAD.MOV.U32 R9, RZ, RZ, R4 ; /* 0x000000ffff097224 */
/* 0x000fe400078e0004 */
/*0190*/ IMAD.MOV.U32 R8, RZ, RZ, RZ ; /* 0x000000ffff087224 */
/* 0x000fe400078e00ff */
/*01a0*/ IMAD.MOV.U32 R4, RZ, RZ, R9 ; /* 0x000000ffff047224 */
/* 0x000fcc00078e0009 */
/*01b0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x0010a2000c1e1900 */
/*01c0*/ IADD3 R8, R8, -0x4, RZ ; /* 0xfffffffc08087810 */
/* 0x000fe40007ffe0ff */
/*01d0*/ IADD3 R9, P2, R9, 0x4, RZ ; /* 0x0000000409097810 */
/* 0x000fe40007f5e0ff */
/*01e0*/ ISETP.NE.AND P1, PT, R8, -0x4, PT ; /* 0xfffffffc0800780c */
/* 0x000fe40003f25270 */
/*01f0*/ IADD3 R6, R6, 0x1, RZ ; /* 0x0000000106067810 */
/* 0x000fe20007ffe0ff */
/*0200*/ IMAD.X R5, RZ, RZ, R5, P2 ; /* 0x000000ffff057224 */
/* 0x001fe400010e0605 */
/*0210*/ IMAD.IADD R7, R4, 0x1, R7 ; /* 0x0000000104077824 */
/* 0x004fca00078e0207 */
/*0220*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x0001e6000c101904 */
/*0230*/ @P1 BRA 0x1a0 ; /* 0xffffff6000001947 */
/* 0x000fea000383ffff */
/*0240*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0250*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0260*/ IMAD.WIDE R4, R6, R11, c[0x0][0x160] ; /* 0x0000580006047625 */
/* 0x000fca00078e020b */
/*0270*/ IADD3 R8, P0, R4, 0x8, RZ ; /* 0x0000000804087810 */
/* 0x000fc80007f1e0ff */
/*0280*/ IADD3.X R9, RZ, R5, RZ, P0, !PT ; /* 0x00000005ff097210 */
/* 0x000fc600007fe4ff */
/*0290*/ IMAD.MOV.U32 R4, RZ, RZ, R8 ; /* 0x000000ffff047224 */
/* 0x000fe400078e0008 */
/*02a0*/ IMAD.MOV.U32 R5, RZ, RZ, R9 ; /* 0x000000ffff057224 */
/* 0x000fca00078e0009 */
/*02b0*/ LDG.E R8, [R4.64+-0x8] ; /* 0xfffff80404087981 */
/* 0x004ea4000c1e1900 */
/*02c0*/ IADD3 R9, R8, R7, RZ ; /* 0x0000000708097210 */
/* 0x004fca0007ffe0ff */
/*02d0*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x0003e8000c101904 */
/*02e0*/ LDG.E R8, [R4.64+-0x4] ; /* 0xfffffc0404087981 */
/* 0x000ea4000c1e1900 */
/*02f0*/ IMAD.IADD R11, R9, 0x1, R8 ; /* 0x00000001090b7824 */
/* 0x004fca00078e0208 */
/*0300*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x0005e8000c101904 */
/*0310*/ LDG.E R8, [R4.64] ; /* 0x0000000404087981 */
/* 0x000ee4000c1e1900 */
/*0320*/ IMAD.IADD R13, R11, 0x1, R8 ; /* 0x000000010b0d7824 */
/* 0x008fca00078e0208 */
/*0330*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x0005e8000c101904 */
/*0340*/ LDG.E R8, [R4.64+0x4] ; /* 0x0000040404087981 */
/* 0x000ee2000c1e1900 */
/*0350*/ IADD3 R6, R6, 0x4, RZ ; /* 0x0000000406067810 */
/* 0x000fc80007ffe0ff */
/*0360*/ ISETP.GE.AND P0, PT, R6, R0, PT ; /* 0x000000000600720c */
/* 0x000fe40003f06270 */
/*0370*/ IADD3 R7, R13, R8, RZ ; /* 0x000000080d077210 */
/* 0x009fe40007ffe0ff */
/*0380*/ IADD3 R8, P1, R4, 0x10, RZ ; /* 0x0000001004087810 */
/* 0x000fc60007f3e0ff */
/*0390*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x0005e4000c101904 */
/*03a0*/ IMAD.X R9, RZ, RZ, R5, P1 ; /* 0x000000ffff097224 */
/* 0x002fc800008e0605 */
/*03b0*/ @!P0 BRA 0x290 ; /* 0xfffffed000008947 */
/* 0x000fea000383ffff */
/*03c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*03d0*/ BRA 0x3d0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*03e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0400*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0410*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0420*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0430*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0440*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0450*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0460*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0470*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z14StupidSumArrayPiS_
.globl _Z14StupidSumArrayPiS_
.p2align 8
.type _Z14StupidSumArrayPiS_,@function
_Z14StupidSumArrayPiS_:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x1c
s_load_b64 s[2:3], s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b32_e32 v0, 10, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[2:3], 2, v[1:2]
v_mov_b32_e32 v1, 0
v_add_co_u32 v2, vcc_lo, s2, v2
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
s_mov_b32 s2, exec_lo
global_store_b32 v[2:3], v1, off
v_cmpx_ne_u32_e32 0x7ffffc00, v0
s_cbranch_execz .LBB0_3
global_load_b32 v6, v[2:3], off
s_load_b64 s[0:1], s[0:1], 0x0
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[4:5], 2, v[0:1]
v_add_nc_u32_e32 v1, 0x400, v0
s_waitcnt lgkmcnt(0)
v_add_co_u32 v4, vcc_lo, s0, v4
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v5, vcc_lo
s_mov_b32 s1, 0
.LBB0_2:
global_load_b32 v7, v[4:5], off
v_add_nc_u32_e32 v0, 1, v0
v_add_co_u32 v4, vcc_lo, v4, 4
v_add_co_ci_u32_e32 v5, vcc_lo, 0, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_ge_i32_e64 s0, v0, v1
s_or_b32 s1, s0, s1
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v6, v6, v7
global_store_b32 v[2:3], v6, off
s_and_not1_b32 exec_lo, exec_lo, s1
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z14StupidSumArrayPiS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z14StupidSumArrayPiS_, .Lfunc_end0-_Z14StupidSumArrayPiS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z14StupidSumArrayPiS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z14StupidSumArrayPiS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0016601a_00000000-6_main.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z36__device_stub__Z14StupidSumArrayPiS_PiS_
.type _Z36__device_stub__Z14StupidSumArrayPiS_PiS_, @function
_Z36__device_stub__Z14StupidSumArrayPiS_PiS_:
.LFB3694:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z14StupidSumArrayPiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3694:
.size _Z36__device_stub__Z14StupidSumArrayPiS_PiS_, .-_Z36__device_stub__Z14StupidSumArrayPiS_PiS_
.globl _Z14StupidSumArrayPiS_
.type _Z14StupidSumArrayPiS_, @function
_Z14StupidSumArrayPiS_:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z36__device_stub__Z14StupidSumArrayPiS_PiS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _Z14StupidSumArrayPiS_, .-_Z14StupidSumArrayPiS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string " "
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $88, %rsp
.cfi_def_cfa_offset 144
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $4194304, %edi
call _Znam@PLT
movq %rax, 8(%rsp)
leaq 4194304(%rax), %rdx
.L12:
movl $1, (%rax)
addq $4, %rax
cmpq %rax, %rdx
jne .L12
leaq 16(%rsp), %rdi
movl $4194304, %esi
call cudaMalloc@PLT
movl $4096, %edi
call _Znam@PLT
movq %rax, %r13
leaq 4096(%rax), %rdx
.L13:
movl $0, (%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L13
leaq 24(%rsp), %rdi
movl $4096, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $4194304, %edx
movq 8(%rsp), %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $4194304, %edx
movq %r13, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
leaq 32(%rsp), %rdi
call cudaEventCreate@PLT
leaq 40(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 32(%rsp), %rdi
call cudaEventRecord@PLT
movl $1024, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movl $1, %ecx
movq 48(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L25
.L14:
movl $0, %esi
movq 40(%rsp), %rdi
call cudaEventRecord@PLT
movl $2, %ecx
movl $4096, %edx
movq 24(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
movq 40(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 60(%rsp), %rdi
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
call cudaEventElapsedTime@PLT
movl $0, %ebp
leaq _ZSt4cout(%rip), %r15
leaq .LC0(%rip), %r14
jmp .L19
.L25:
movq 24(%rsp), %rsi
movq 16(%rsp), %rdi
call _Z36__device_stub__Z14StupidSumArrayPiS_PiS_
jmp .L14
.L28:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L26
call _ZSt16__throw_bad_castv@PLT
.L26:
call __stack_chk_fail@PLT
.L17:
movq %r12, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r12), %rax
movl $10, %esi
movq %r12, %rdi
call *48(%rax)
movl %eax, %esi
.L18:
movsbl %sil, %esi
movq %rbx, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
addq $1, %rbp
cmpq $1024, %rbp
je .L27
.L19:
movl %ebp, %esi
movq %r15, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbx
movl $1, %edx
movq %r14, %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl 0(%r13,%rbp,4), %esi
movq %rbx, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbx
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r12
testq %r12, %r12
je .L28
cmpb $0, 56(%r12)
je .L17
movzbl 67(%r12), %esi
jmp .L18
.L27:
pxor %xmm0, %xmm0
cvtss2sd 60(%rsp), %xmm0
leaq _ZSt4cout(%rip), %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq %r13, %rdi
call _ZdaPv@PLT
movq 8(%rsp), %rdi
call _ZdaPv@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L29
movl $0, %eax
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L29:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z14StupidSumArrayPiS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z14StupidSumArrayPiS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "main.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z29__device_stub__StupidSumArrayPiS_ # -- Begin function _Z29__device_stub__StupidSumArrayPiS_
.p2align 4, 0x90
.type _Z29__device_stub__StupidSumArrayPiS_,@function
_Z29__device_stub__StupidSumArrayPiS_: # @_Z29__device_stub__StupidSumArrayPiS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z14StupidSumArrayPiS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z29__device_stub__StupidSumArrayPiS_, .Lfunc_end0-_Z29__device_stub__StupidSumArrayPiS_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $112, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $4194304, %edi # imm = 0x400000
callq _Znam
movq %rax, %rbx
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movl $1, (%rbx,%rax,4)
incq %rax
cmpq $1048576, %rax # imm = 0x100000
jne .LBB1_1
# %bb.2:
leaq 16(%rsp), %rdi
movl $4194304, %esi # imm = 0x400000
callq hipMalloc
movl $4096, %edi # imm = 0x1000
callq _Znam
movq %rax, %r14
movl $4096, %edx # imm = 0x1000
movq %rax, %rdi
xorl %esi, %esi
callq memset@PLT
movq %rsp, %rdi
movl $4096, %esi # imm = 0x1000
callq hipMalloc
movq 16(%rsp), %rdi
movl $4194304, %edx # imm = 0x400000
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq (%rsp), %rdi
movl $4194304, %edx # imm = 0x400000
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
leaq 24(%rsp), %rdi
callq hipEventCreate
leaq 8(%rsp), %rdi
callq hipEventCreate
movq 24(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 1023(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 16(%rsp), %rax
movq (%rsp), %rcx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
leaq 104(%rsp), %rax
movq %rax, 32(%rsp)
leaq 96(%rsp), %rax
movq %rax, 40(%rsp)
leaq 80(%rsp), %rdi
leaq 64(%rsp), %rsi
leaq 56(%rsp), %rdx
leaq 48(%rsp), %rcx
callq __hipPopCallConfiguration
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
movq 64(%rsp), %rcx
movl 72(%rsp), %r8d
leaq 32(%rsp), %r9
movl $_Z14StupidSumArrayPiS_, %edi
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
movq 8(%rsp), %rdi
xorl %r15d, %r15d
xorl %esi, %esi
callq hipEventRecord
movq (%rsp), %rsi
movl $4096, %edx # imm = 0x1000
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
callq hipEventSynchronize
movq 24(%rsp), %rsi
movq 8(%rsp), %rdx
leaq 32(%rsp), %rdi
callq hipEventElapsedTime
jmp .LBB1_5
.p2align 4, 0x90
.LBB1_13: # in Loop: Header=BB1_5 Depth=1
movq %r12, %rdi
movq %rax, %r13
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r12), %rax
movq %r12, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r13, %rax
.LBB1_14: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit32
# in Loop: Header=BB1_5 Depth=1
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
incq %r15
cmpq $1024, %r15 # imm = 0x400
je .LBB1_8
.LBB1_5: # =>This Inner Loop Header: Depth=1
movl $_ZSt4cout, %edi
movl %r15d, %esi
callq _ZNSolsEi
movq %rax, %r12
movl $.L.str, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl (%r14,%r15,4), %esi
movq %r12, %rdi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r12
testq %r12, %r12
je .LBB1_15
# %bb.6: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i29
# in Loop: Header=BB1_5 Depth=1
cmpb $0, 56(%r12)
je .LBB1_13
# %bb.7: # in Loop: Header=BB1_5 Depth=1
movzbl 67(%r12), %ecx
jmp .LBB1_14
.LBB1_8:
movss 32(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r15
testq %r15, %r15
je .LBB1_15
# %bb.9: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%r15)
je .LBB1_11
# %bb.10:
movzbl 67(%r15), %ecx
jmp .LBB1_12
.LBB1_11:
movq %r15, %rdi
movq %rax, %r12
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r12, %rax
.LBB1_12: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq 16(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
movq %r14, %rdi
callq _ZdaPv
movq %rbx, %rdi
callq _ZdaPv
xorl %eax, %eax
addq $112, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB1_15:
.cfi_def_cfa_offset 160
callq _ZSt16__throw_bad_castv
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14StupidSumArrayPiS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z14StupidSumArrayPiS_,@object # @_Z14StupidSumArrayPiS_
.section .rodata,"a",@progbits
.globl _Z14StupidSumArrayPiS_
.p2align 3, 0x0
_Z14StupidSumArrayPiS_:
.quad _Z29__device_stub__StupidSumArrayPiS_
.size _Z14StupidSumArrayPiS_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz " "
.size .L.str, 2
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z14StupidSumArrayPiS_"
.size .L__unnamed_1, 23
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z29__device_stub__StupidSumArrayPiS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z14StupidSumArrayPiS_
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
//indicates a function that runs on the divice
// and also is colled from host code (du global)
//ad a single integer
__global__ void add(int *a, int *b, int *c){
*c = *a + *b; //ver si funciona sin lo sastericos
int d = *c + 1;
printf("kernel %d\n", d);
}
int main(void){
int a, b, c; //host copies of a,b,c
int *d_a, *d_b, *d_c; //device copies of a, b,c
int size = sizeof(int);
//allocate space for device copies of a,b,c
cudaMalloc(&d_a, size); //cuando va??? (void **), como ir a cuda Managed, agregar check error.
cudaMalloc(&d_b, size);
cudaMalloc(&d_c, size);
a = 1;
b = 1;
//copy inputs to device
cudaMemcpy(d_a, &a, size, cudaMemcpyHostToDevice);
cudaMemcpy(d_b, &b, size, cudaMemcpyHostToDevice);
//launch add() kernel on GPU
add<<<1,1>>>(d_a,d_b,d_c);
//copy result back to host
cudaMemcpy(&c,d_c,size,cudaMemcpyDeviceToHost);
printf("fuera del kernel %i\n", c);
//cleanup
cudaFree(d_a); cudaFree(d_b); cudaFree(d_c);
return 0;
} | code for sm_80
Function : _Z3addPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R11, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff0b7624 */
/* 0x000fe200078e00ff */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0030*/ IMAD.MOV.U32 R8, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff087624 */
/* 0x000fe200078e00ff */
/*0040*/ IADD3 R1, R1, -0x8, RZ ; /* 0xfffffff801017810 */
/* 0x000fe20007ffe0ff */
/*0050*/ IMAD.MOV.U32 R9, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff097624 */
/* 0x000fe400078e00ff */
/*0060*/ IMAD.MOV.U32 R10, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff0a7624 */
/* 0x000fc600078e00ff */
/*0070*/ LDG.E R0, [R8.64] ; /* 0x0000000408007981 */
/* 0x000ea8000c1e1900 */
/*0080*/ LDG.E R11, [R10.64] ; /* 0x000000040a0b7981 */
/* 0x000ea2000c1e1900 */
/*0090*/ MOV R2, 0x0 ; /* 0x0000000000027802 */
/* 0x000fe20000000f00 */
/*00a0*/ IMAD.MOV.U32 R12, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff0c7624 */
/* 0x000fe200078e00ff */
/*00b0*/ IADD3 R6, P0, R1, c[0x0][0x20], RZ ; /* 0x0000080001067a10 */
/* 0x000fe20007f1e0ff */
/*00c0*/ IMAD.MOV.U32 R13, RZ, RZ, c[0x0][0x174] ; /* 0x00005d00ff0d7624 */
/* 0x000fe200078e00ff */
/*00d0*/ MOV R5, c[0x4][0xc] ; /* 0x0100030000057a02 */
/* 0x000fe20000000f00 */
/*00e0*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x8] ; /* 0x01000200ff047624 */
/* 0x000fe200078e00ff */
/*00f0*/ LDC.64 R2, c[0x4][R2] ; /* 0x0100000002027b82 */
/* 0x000e220000000a00 */
/*0100*/ IMAD.X R7, RZ, RZ, c[0x0][0x24], P0 ; /* 0x00000900ff077624 */
/* 0x000fe200000e06ff */
/*0110*/ IADD3 R0, R0, R11, RZ ; /* 0x0000000b00007210 */
/* 0x004fc80007ffe0ff */
/*0120*/ IADD3 R14, R0, 0x1, RZ ; /* 0x00000001000e7810 */
/* 0x000fe20007ffe0ff */
/*0130*/ STG.E [R12.64], R0 ; /* 0x000000000c007986 */
/* 0x0003e8000c101904 */
/*0140*/ STL [R1], R14 ; /* 0x0000000e01007387 */
/* 0x0003e40000100800 */
/*0150*/ LEPC R8 ; /* 0x000000000008734e */
/* 0x001fe40000000000 */
/*0160*/ MOV R11, 0x1d0 ; /* 0x000001d0000b7802 */
/* 0x000fe40000000f00 */
/*0170*/ MOV R20, 0x150 ; /* 0x0000015000147802 */
/* 0x000fe40000000f00 */
/*0180*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*0190*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x002fc40000000f00 */
/*01a0*/ IADD3 R20, P0, P1, -R20, R11, R8 ; /* 0x0000000b14147210 */
/* 0x000fc8000791e108 */
/*01b0*/ IADD3.X R21, ~R0, R21, R9, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2509 */
/*01c0*/ CALL.ABS.NOINC R2 ; /* 0x0000000002007343 */
/* 0x000fea0003c00000 */
/*01d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01e0*/ BRA 0x1e0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
//indicates a function that runs on the divice
// and also is colled from host code (du global)
//ad a single integer
__global__ void add(int *a, int *b, int *c){
*c = *a + *b; //ver si funciona sin lo sastericos
int d = *c + 1;
printf("kernel %d\n", d);
}
int main(void){
int a, b, c; //host copies of a,b,c
int *d_a, *d_b, *d_c; //device copies of a, b,c
int size = sizeof(int);
//allocate space for device copies of a,b,c
cudaMalloc(&d_a, size); //cuando va??? (void **), como ir a cuda Managed, agregar check error.
cudaMalloc(&d_b, size);
cudaMalloc(&d_c, size);
a = 1;
b = 1;
//copy inputs to device
cudaMemcpy(d_a, &a, size, cudaMemcpyHostToDevice);
cudaMemcpy(d_b, &b, size, cudaMemcpyHostToDevice);
//launch add() kernel on GPU
add<<<1,1>>>(d_a,d_b,d_c);
//copy result back to host
cudaMemcpy(&c,d_c,size,cudaMemcpyDeviceToHost);
printf("fuera del kernel %i\n", c);
//cleanup
cudaFree(d_a); cudaFree(d_b); cudaFree(d_c);
return 0;
} | .file "tmpxft_0004895d_00000000-6_suma.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z26__device_stub__Z3addPiS_S_PiS_S_
.type _Z26__device_stub__Z3addPiS_S_PiS_S_, @function
_Z26__device_stub__Z3addPiS_S_PiS_S_:
.LFB2082:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3addPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z26__device_stub__Z3addPiS_S_PiS_S_, .-_Z26__device_stub__Z3addPiS_S_PiS_S_
.globl _Z3addPiS_S_
.type _Z3addPiS_S_, @function
_Z3addPiS_S_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z3addPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z3addPiS_S_, .-_Z3addPiS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "fuera del kernel %i\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
movl $1, (%rsp)
movl $1, 4(%rsp)
movq %rsp, %rsi
movl $1, %ecx
movl $4, %edx
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
leaq 4(%rsp), %rsi
movl $1, %ecx
movl $4, %edx
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L15
.L12:
leaq 44(%rsp), %rdi
movl $2, %ecx
movl $4, %edx
movq 24(%rsp), %rsi
call cudaMemcpy@PLT
movl 44(%rsp), %edx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L16
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z26__device_stub__Z3addPiS_S_PiS_S_
jmp .L12
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z3addPiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z3addPiS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
//indicates a function that runs on the divice
// and also is colled from host code (du global)
//ad a single integer
__global__ void add(int *a, int *b, int *c){
*c = *a + *b; //ver si funciona sin lo sastericos
int d = *c + 1;
printf("kernel %d\n", d);
}
int main(void){
int a, b, c; //host copies of a,b,c
int *d_a, *d_b, *d_c; //device copies of a, b,c
int size = sizeof(int);
//allocate space for device copies of a,b,c
cudaMalloc(&d_a, size); //cuando va??? (void **), como ir a cuda Managed, agregar check error.
cudaMalloc(&d_b, size);
cudaMalloc(&d_c, size);
a = 1;
b = 1;
//copy inputs to device
cudaMemcpy(d_a, &a, size, cudaMemcpyHostToDevice);
cudaMemcpy(d_b, &b, size, cudaMemcpyHostToDevice);
//launch add() kernel on GPU
add<<<1,1>>>(d_a,d_b,d_c);
//copy result back to host
cudaMemcpy(&c,d_c,size,cudaMemcpyDeviceToHost);
printf("fuera del kernel %i\n", c);
//cleanup
cudaFree(d_a); cudaFree(d_b); cudaFree(d_c);
return 0;
} | #include <hip/hip_runtime.h>
#include <stdio.h>
//indicates a function that runs on the divice
// and also is colled from host code (du global)
//ad a single integer
__global__ void add(int *a, int *b, int *c){
*c = *a + *b; //ver si funciona sin lo sastericos
int d = *c + 1;
printf("kernel %d\n", d);
}
int main(void){
int a, b, c; //host copies of a,b,c
int *d_a, *d_b, *d_c; //device copies of a, b,c
int size = sizeof(int);
//allocate space for device copies of a,b,c
hipMalloc(&d_a, size); //cuando va??? (void **), como ir a cuda Managed, agregar check error.
hipMalloc(&d_b, size);
hipMalloc(&d_c, size);
a = 1;
b = 1;
//copy inputs to device
hipMemcpy(d_a, &a, size, hipMemcpyHostToDevice);
hipMemcpy(d_b, &b, size, hipMemcpyHostToDevice);
//launch add() kernel on GPU
add<<<1,1>>>(d_a,d_b,d_c);
//copy result back to host
hipMemcpy(&c,d_c,size,hipMemcpyDeviceToHost);
printf("fuera del kernel %i\n", c);
//cleanup
hipFree(d_a); hipFree(d_b); hipFree(d_c);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
//indicates a function that runs on the divice
// and also is colled from host code (du global)
//ad a single integer
__global__ void add(int *a, int *b, int *c){
*c = *a + *b; //ver si funciona sin lo sastericos
int d = *c + 1;
printf("kernel %d\n", d);
}
int main(void){
int a, b, c; //host copies of a,b,c
int *d_a, *d_b, *d_c; //device copies of a, b,c
int size = sizeof(int);
//allocate space for device copies of a,b,c
hipMalloc(&d_a, size); //cuando va??? (void **), como ir a cuda Managed, agregar check error.
hipMalloc(&d_b, size);
hipMalloc(&d_c, size);
a = 1;
b = 1;
//copy inputs to device
hipMemcpy(d_a, &a, size, hipMemcpyHostToDevice);
hipMemcpy(d_b, &b, size, hipMemcpyHostToDevice);
//launch add() kernel on GPU
add<<<1,1>>>(d_a,d_b,d_c);
//copy result back to host
hipMemcpy(&c,d_c,size,hipMemcpyDeviceToHost);
printf("fuera del kernel %i\n", c);
//cleanup
hipFree(d_a); hipFree(d_b); hipFree(d_c);
return 0;
} | .text
.file "suma.hip"
.globl _Z18__device_stub__addPiS_S_ # -- Begin function _Z18__device_stub__addPiS_S_
.p2align 4, 0x90
.type _Z18__device_stub__addPiS_S_,@function
_Z18__device_stub__addPiS_S_: # @_Z18__device_stub__addPiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3addPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z18__device_stub__addPiS_S_, .Lfunc_end0-_Z18__device_stub__addPiS_S_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
leaq 16(%rsp), %rdi
movl $4, %esi
callq hipMalloc
leaq 8(%rsp), %rdi
movl $4, %esi
callq hipMalloc
movq %rsp, %rdi
movl $4, %esi
callq hipMalloc
movl $1, 28(%rsp)
movl $1, 24(%rsp)
movq 16(%rsp), %rdi
leaq 28(%rsp), %rsi
movl $4, %edx
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
leaq 24(%rsp), %rsi
movl $4, %edx
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq (%rsp), %rdx
movq %rax, 128(%rsp)
movq %rcx, 120(%rsp)
movq %rdx, 112(%rsp)
leaq 128(%rsp), %rax
movq %rax, 32(%rsp)
leaq 120(%rsp), %rax
movq %rax, 40(%rsp)
leaq 112(%rsp), %rax
movq %rax, 48(%rsp)
leaq 96(%rsp), %rdi
leaq 80(%rsp), %rsi
leaq 72(%rsp), %rdx
leaq 64(%rsp), %rcx
callq __hipPopCallConfiguration
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
movq 80(%rsp), %rcx
movl 88(%rsp), %r8d
leaq 32(%rsp), %r9
movl $_Z3addPiS_S_, %edi
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
pushq 80(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
movq (%rsp), %rsi
leaq 32(%rsp), %rdi
movl $4, %edx
movl $2, %ecx
callq hipMemcpy
movl 32(%rsp), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $136, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3addPiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3addPiS_S_,@object # @_Z3addPiS_S_
.section .rodata,"a",@progbits
.globl _Z3addPiS_S_
.p2align 3, 0x0
_Z3addPiS_S_:
.quad _Z18__device_stub__addPiS_S_
.size _Z3addPiS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "fuera del kernel %i\n"
.size .L.str, 21
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z3addPiS_S_"
.size .L__unnamed_1, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__addPiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3addPiS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0004895d_00000000-6_suma.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z26__device_stub__Z3addPiS_S_PiS_S_
.type _Z26__device_stub__Z3addPiS_S_PiS_S_, @function
_Z26__device_stub__Z3addPiS_S_PiS_S_:
.LFB2082:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3addPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z26__device_stub__Z3addPiS_S_PiS_S_, .-_Z26__device_stub__Z3addPiS_S_PiS_S_
.globl _Z3addPiS_S_
.type _Z3addPiS_S_, @function
_Z3addPiS_S_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z3addPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z3addPiS_S_, .-_Z3addPiS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "fuera del kernel %i\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
movl $1, (%rsp)
movl $1, 4(%rsp)
movq %rsp, %rsi
movl $1, %ecx
movl $4, %edx
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
leaq 4(%rsp), %rsi
movl $1, %ecx
movl $4, %edx
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L15
.L12:
leaq 44(%rsp), %rdi
movl $2, %ecx
movl $4, %edx
movq 24(%rsp), %rsi
call cudaMemcpy@PLT
movl 44(%rsp), %edx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L16
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z26__device_stub__Z3addPiS_S_PiS_S_
jmp .L12
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z3addPiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z3addPiS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "suma.hip"
.globl _Z18__device_stub__addPiS_S_ # -- Begin function _Z18__device_stub__addPiS_S_
.p2align 4, 0x90
.type _Z18__device_stub__addPiS_S_,@function
_Z18__device_stub__addPiS_S_: # @_Z18__device_stub__addPiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3addPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z18__device_stub__addPiS_S_, .Lfunc_end0-_Z18__device_stub__addPiS_S_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
leaq 16(%rsp), %rdi
movl $4, %esi
callq hipMalloc
leaq 8(%rsp), %rdi
movl $4, %esi
callq hipMalloc
movq %rsp, %rdi
movl $4, %esi
callq hipMalloc
movl $1, 28(%rsp)
movl $1, 24(%rsp)
movq 16(%rsp), %rdi
leaq 28(%rsp), %rsi
movl $4, %edx
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
leaq 24(%rsp), %rsi
movl $4, %edx
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq (%rsp), %rdx
movq %rax, 128(%rsp)
movq %rcx, 120(%rsp)
movq %rdx, 112(%rsp)
leaq 128(%rsp), %rax
movq %rax, 32(%rsp)
leaq 120(%rsp), %rax
movq %rax, 40(%rsp)
leaq 112(%rsp), %rax
movq %rax, 48(%rsp)
leaq 96(%rsp), %rdi
leaq 80(%rsp), %rsi
leaq 72(%rsp), %rdx
leaq 64(%rsp), %rcx
callq __hipPopCallConfiguration
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
movq 80(%rsp), %rcx
movl 88(%rsp), %r8d
leaq 32(%rsp), %r9
movl $_Z3addPiS_S_, %edi
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
pushq 80(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
movq (%rsp), %rsi
leaq 32(%rsp), %rdi
movl $4, %edx
movl $2, %ecx
callq hipMemcpy
movl 32(%rsp), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $136, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3addPiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3addPiS_S_,@object # @_Z3addPiS_S_
.section .rodata,"a",@progbits
.globl _Z3addPiS_S_
.p2align 3, 0x0
_Z3addPiS_S_:
.quad _Z18__device_stub__addPiS_S_
.size _Z3addPiS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "fuera del kernel %i\n"
.size .L.str, 21
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z3addPiS_S_"
.size .L__unnamed_1, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__addPiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3addPiS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <math.h>
#include <fstream>
#include <array>
#include <cuda.h>
#include <cuda_runtime.h>
#include <iostream>
#include <assert.h>
using namespace std;
#define DEBUG
bool readFile(int16_t* read, const char* filePath);
bool saveFile(int16_t* write, const char* filePath);
float max_distance = 0;
int HEIGHT = 240;
int WIDTH = 288;
timespec diff(timespec start, timespec end)
{
timespec temp;
if ((end.tv_nsec-start.tv_nsec)<0) {
temp.tv_sec = end.tv_sec-start.tv_sec-1;
temp.tv_nsec = 1000000000+end.tv_nsec-start.tv_nsec;
} else {
temp.tv_sec = end.tv_sec-start.tv_sec;
temp.tv_nsec = end.tv_nsec-start.tv_nsec;
}
return temp;
}
inline
cudaError_t checkCuda(cudaError_t result)
{
#if defined(DEBUG) || defined(_DEBUG)
if (result != cudaSuccess) {
fprintf(stderr, "CUDA Runtime Error: %s\n", cudaGetErrorString(result));
assert(result == cudaSuccess);
}
#endif
return result;
}
__global__
void calculate_atan2_cu(int16_t* phase1_cu, int16_t* phase2_cu,
int16_t* phase3_cu, int16_t* phase4_cu,
int16_t* depth_out_cu, int16_t* confidence_out_cu,int N){
const int index = blockIdx.x*blockDim.x + threadIdx.x;
if(index < N){
int16_t phase_1 = *(phase1_cu + index);
int16_t phase_2 = *(phase2_cu + index);
int16_t phase_3 = *(phase3_cu + index);
int16_t phase_4 = *(phase4_cu + index);
//printf("%d,%d,%d,%d\n",phase_1,phase_2,phase_3,phase_4);
auto phase1_t = phase_1 >> 4;
auto phase2_t = phase_2 >> 4;
auto phase3_t = phase_3 >> 4;
auto phase4_t = phase_4 >> 4;
int16_t I = phase1_t - phase3_t;
int16_t Q = phase2_t - phase4_t;
int out_index = index;
confidence_out_cu[out_index] = sqrt(float(I*I + Q*Q));
//printf("rsqrt(%d) confidence_out_cu[%d]=%d",I*I+Q*Q,index,confidence_out_cu[index]);
float angle = atan(-(float)Q/(float)I);
depth_out_cu[out_index] = (angle + M_PI) * 3.7474 * 1000 / (2 * M_PI);
}
}
int main(int argc, char *argv[])
{
const char *path=NULL;
printf("\n");
printf("Usage: %s relative-path-for-phase-data\n",argv[0]);
printf("depth_cu and confidence2_cu are put in the same path with %s\n",argv[0]);
printf("****Be noticed that the calculation will be done for 1000 times****\n");
printf("If you want to profile %s, try ",argv[0]);
printf("sudo /usr/local/cuda/bin/nvprof %s\n",argv[0]);
printf("otherwise, just run %s\n",argv[0]);
printf("\n");
if(argc == 1){
printf("Now loading phase data from ./data/originalData/\n");
path = "./data/originalData/";
}
else{
printf("now loading phase data from %s\n",argv[1]);
path = argv[1];
}
const int nStreams = 4;
timespec time1, time2;
cudaStream_t stream[nStreams];
for (int i = 0; i < nStreams; ++i)
checkCuda( cudaStreamCreate(&stream[i]) );
cudaEvent_t startEvent, stopEvent, dummyEvent;
checkCuda( cudaEventCreate(&startEvent) );
checkCuda( cudaEventCreate(&stopEvent) );
checkCuda( cudaEventCreate(&dummyEvent) );
int fmod = 40;
max_distance = 0.5*299792458/(double)fmod/1000;
int16_t* phase1;
int16_t* phase2;
int16_t* phase3;
int16_t* phase4;
int16_t* depth1_out;
int16_t* confidence1_out;
#ifndef PINNED
phase1 = new int16_t[WIDTH*HEIGHT];
phase2 = new int16_t[WIDTH*HEIGHT];
phase3 = new int16_t[WIDTH*HEIGHT];
phase4 = new int16_t[WIDTH*HEIGHT];
depth1_out = new int16_t[WIDTH*HEIGHT];
confidence1_out = new int16_t[WIDTH*HEIGHT];
#else
checkCuda( cudaMallocHost((void**)&phase1, sizeof(int16_t)*WIDTH*HEIGHT) ); // host pinned
checkCuda( cudaMallocHost((void**)&phase2, sizeof(int16_t)*WIDTH*HEIGHT) ); // host pinned
checkCuda( cudaMallocHost((void**)&phase3, sizeof(int16_t)*WIDTH*HEIGHT) ); // host pinned
checkCuda( cudaMallocHost((void**)&phase4, sizeof(int16_t)*WIDTH*HEIGHT) ); // host pinned
checkCuda( cudaMallocHost((void**)&depth1_out, sizeof(int16_t)* WIDTH*HEIGHT) ); // host pinned
checkCuda( cudaMallocHost((void**)&confidence1_out, sizeof(int16_t)* WIDTH*HEIGHT) ); // host pinned
#endif
int16_t *phase1_cu[nStreams],*phase2_cu[nStreams],*phase3_cu[nStreams],*phase4_cu[nStreams],*depth1_out_cu[nStreams],*confidence1_out_cu[nStreams];
for(int i=0;i<nStreams;i++){
checkCuda(cudaMalloc((void**)&phase1_cu[i], sizeof(int16_t) * WIDTH * HEIGHT));
checkCuda(cudaMalloc((void**)&phase2_cu[i], sizeof(int16_t) * WIDTH * HEIGHT));
checkCuda(cudaMalloc((void**)&phase3_cu[i], sizeof(int16_t) * WIDTH * HEIGHT));
checkCuda(cudaMalloc((void**)&phase4_cu[i], sizeof(int16_t) * WIDTH * HEIGHT));
checkCuda(cudaMalloc((void**)&depth1_out_cu[i], sizeof(int16_t) * WIDTH * HEIGHT));
checkCuda(cudaMalloc((void**)&confidence1_out_cu[i], sizeof(int16_t) * WIDTH * HEIGHT));
}
char *file = new char[ strlen(path)+ 10];
memset(file,0,strlen(path)+ 10);
strcat(file,path);
if(!readFile(phase1, strcat(file,"phase0")) || (*(file+strlen(path)) = '\0')||
!readFile(phase2, strcat(file,"phase90")) ||(*(file+strlen(path)) = '\0')||
!readFile(phase3, strcat(file,"phase180")) ||(*(file+strlen(path)) = '\0')||
!readFile(phase4, strcat(file,"phase270")) )
{
printf("read failed!\n");
return 0;
}
printf("calculation is started\n");
float ms; // elapsed time in milliseconds
#ifdef STREAM
checkCuda( cudaEventRecord(startEvent,stream[nStreams-1]) );
clock_gettime(CLOCK_MONOTONIC, &time1);
for(int i=0;i<1000;i+=nStreams){
// Transfer data from host to device memory
for(int j=0;j<nStreams;j++){
checkCuda(cudaMemcpyAsync(phase1_cu[j],phase1, sizeof(int16_t) * WIDTH * HEIGHT, cudaMemcpyHostToDevice,stream[j]));
checkCuda(cudaMemcpyAsync(phase2_cu[j],phase2, sizeof(int16_t) * WIDTH * HEIGHT, cudaMemcpyHostToDevice,stream[j]));
checkCuda(cudaMemcpyAsync(phase3_cu[j],phase3, sizeof(int16_t) * WIDTH * HEIGHT, cudaMemcpyHostToDevice,stream[j]));
checkCuda(cudaMemcpyAsync(phase4_cu[j],phase4, sizeof(int16_t) * WIDTH * HEIGHT, cudaMemcpyHostToDevice,stream[j]));
}
for(int j=0;j<nStreams;j++){
calculate_atan2_cu<<<540,128,0,stream[j]>>>(phase1_cu[j],phase2_cu[j],phase3_cu[j],phase4_cu[j],depth1_out_cu[j],confidence1_out_cu[j], WIDTH*HEIGHT);
}
for(int j=0;j<nStreams;j++){
checkCuda(cudaMemcpyAsync(depth1_out, depth1_out_cu[j],sizeof(int16_t) * WIDTH * HEIGHT, cudaMemcpyDeviceToHost,stream[j]));
checkCuda(cudaMemcpyAsync(confidence1_out,confidence1_out_cu[j], sizeof(int16_t) * WIDTH * HEIGHT, cudaMemcpyDeviceToHost,stream[j]));
}
}
checkCuda( cudaEventRecord(stopEvent, stream[nStreams-1]) );
checkCuda( cudaEventSynchronize(stopEvent) );
checkCuda( cudaEventElapsedTime(&ms, startEvent, stopEvent) );
cudaDeviceSynchronize();
clock_gettime(CLOCK_MONOTONIC, &time2);
printf("Time for multiple stream transfer and execute (ms): %f ", ms);
cout<<diff(time1,time2).tv_sec<<":"<<diff(time1,time2).tv_nsec<<endl;
printf("stream with %d calculation is done\n",nStreams);
#endif
#ifdef NULLSTREAM
clock_gettime(CLOCK_MONOTONIC, &time1);
checkCuda( cudaEventRecord(startEvent,0) );
for(int i=0;i<1000;i++){
// Transfer data from host to device memory
cudaMemcpy(phase1_cu[0],phase1, sizeof(int16_t) * WIDTH * HEIGHT, cudaMemcpyHostToDevice);
cudaMemcpy(phase2_cu[0],phase2, sizeof(int16_t) * WIDTH * HEIGHT, cudaMemcpyHostToDevice);
cudaMemcpy(phase3_cu[0],phase3, sizeof(int16_t) * WIDTH * HEIGHT, cudaMemcpyHostToDevice);
cudaMemcpy(phase4_cu[0],phase4, sizeof(int16_t) * WIDTH * HEIGHT, cudaMemcpyHostToDevice);
calculate_atan2_cu<<<540,128>>>(phase1_cu[0],phase2_cu[0],phase3_cu[0],phase4_cu[0],depth1_out_cu[0],confidence1_out_cu[0], WIDTH*HEIGHT);
cudaMemcpy(depth1_out, depth1_out_cu[0],sizeof(int16_t) * WIDTH * HEIGHT, cudaMemcpyDeviceToHost);
cudaMemcpy(confidence1_out,confidence1_out_cu[0], sizeof(int16_t) * WIDTH * HEIGHT, cudaMemcpyDeviceToHost);
}
checkCuda( cudaEventRecord(stopEvent, 0) );
checkCuda( cudaEventSynchronize(stopEvent) );
checkCuda( cudaEventElapsedTime(&ms, startEvent, stopEvent) );
cudaDeviceSynchronize();
clock_gettime(CLOCK_MONOTONIC, &time2);
printf("Time for NULL stream transfer and execute (ms): %f ", ms);
cout<<diff(time1,time2).tv_sec<<":"<<diff(time1,time2).tv_nsec<<endl;
#endif
printf("Calculation is done and saving depth and confidence!\n");
saveFile(depth1_out, "depth_cu");
saveFile(confidence1_out, "confidence2_cu");
printf("\n");
return 0;
}
bool readFile(int16_t* read, const char* filePath)
{
// printf("filePath=%s\n",filePath);
std::ifstream infile;
infile.open(filePath);
if(!infile)
{
printf("can not open file :%s\n",filePath);
return false;
}
while(!infile.eof())
{
infile>>*read;
read++;
}
infile.close();
return true;
}
bool saveFile(int16_t* write, const char* filePath)
{
std::ofstream fout(filePath);
for(auto j=0; j < HEIGHT; ++j)
{
for(auto i =0; i < WIDTH; i++)
{
fout << write[j*WIDTH+i] << "\t" ;
}
fout << "\n";
}
fout.close();
} | .file "tmpxft_00044b87_00000000-6_main.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3847:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3847:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z4diff8timespecS_
.type _Z4diff8timespecS_, @function
_Z4diff8timespecS_:
.LFB3840:
.cfi_startproc
endbr64
movq %rdx, %rax
subq %rdi, %rax
movq %rcx, %r8
subq %rsi, %r8
js .L6
.L5:
movq %r8, %rdx
ret
.L6:
leaq -1(%rax), %rax
leaq 1000000000(%rcx), %r8
subq %rsi, %r8
jmp .L5
.cfi_endproc
.LFE3840:
.size _Z4diff8timespecS_, .-_Z4diff8timespecS_
.section .rodata._Z9checkCuda9cudaError.str1.1,"aMS",@progbits,1
.LC0:
.string "CUDA Runtime Error: %s\n"
.section .text._Z9checkCuda9cudaError,"axG",@progbits,_Z9checkCuda9cudaError,comdat
.weak _Z9checkCuda9cudaError
.type _Z9checkCuda9cudaError, @function
_Z9checkCuda9cudaError:
.LFB3841:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movl %edi, %ebx
testl %edi, %edi
jne .L10
.L8:
movl %ebx, %eax
popq %rbx
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L10:
.cfi_restore_state
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L8
.cfi_endproc
.LFE3841:
.size _Z9checkCuda9cudaError, .-_Z9checkCuda9cudaError
.text
.globl _Z49__device_stub__Z18calculate_atan2_cuPsS_S_S_S_S_iPsS_S_S_S_S_i
.type _Z49__device_stub__Z18calculate_atan2_cuPsS_S_S_S_S_iPsS_S_S_S_S_i, @function
_Z49__device_stub__Z18calculate_atan2_cuPsS_S_S_S_S_iPsS_S_S_S_S_i:
.LFB3869:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movq %r8, 8(%rsp)
movq %r9, (%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
movq %rsp, %rax
movq %rax, 152(%rsp)
leaq 192(%rsp), %rax
movq %rax, 160(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z18calculate_atan2_cuPsS_S_S_S_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3869:
.size _Z49__device_stub__Z18calculate_atan2_cuPsS_S_S_S_S_iPsS_S_S_S_S_i, .-_Z49__device_stub__Z18calculate_atan2_cuPsS_S_S_S_S_iPsS_S_S_S_S_i
.globl _Z18calculate_atan2_cuPsS_S_S_S_S_i
.type _Z18calculate_atan2_cuPsS_S_S_S_S_i, @function
_Z18calculate_atan2_cuPsS_S_S_S_S_i:
.LFB3870:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
call _Z49__device_stub__Z18calculate_atan2_cuPsS_S_S_S_S_iPsS_S_S_S_S_i
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3870:
.size _Z18calculate_atan2_cuPsS_S_S_S_S_i, .-_Z18calculate_atan2_cuPsS_S_S_S_S_i
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "_Z18calculate_atan2_cuPsS_S_S_S_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3872:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z18calculate_atan2_cuPsS_S_S_S_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3872:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "\t"
.LC3:
.string "\n"
.text
.globl _Z8saveFilePsPKc
.type _Z8saveFilePsPKc, @function
_Z8saveFilePsPKc:
.LFB3844:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA3844
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $536, %rsp
.cfi_def_cfa_offset 592
movq %rdi, %r13
movq %fs:40, %rax
movq %rax, 520(%rsp)
xorl %eax, %eax
movq %rsp, %rdi
movl $16, %edx
.LEHB0:
call _ZNSt14basic_ofstreamIcSt11char_traitsIcEEC1EPKcSt13_Ios_Openmode@PLT
.LEHE0:
cmpl $0, HEIGHT(%rip)
jle .L23
movl $0, %ebp
leaq .LC2(%rip), %r14
movq %rsp, %r12
leaq .LC3(%rip), %r15
jmp .L22
.L35:
movq %rax, %rdi
movl $1, %edx
movq %r14, %rsi
.LEHB1:
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
addl $1, %ebx
movl WIDTH(%rip), %eax
cmpl %ebx, %eax
jle .L25
.L24:
imull %ebp, %eax
addl %ebx, %eax
cltq
movswl 0(%r13,%rax,2), %esi
movq %r12, %rdi
call _ZNSolsEs@PLT
jmp .L35
.L36:
addl $1, %ebp
cmpl %ebp, HEIGHT(%rip)
jle .L23
.L22:
movl WIDTH(%rip), %eax
movl $0, %ebx
testl %eax, %eax
jg .L24
.L25:
movl $1, %edx
movq %r15, %rsi
movq %r12, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
jmp .L36
.L23:
movq %rsp, %rdi
call _ZNSt14basic_ofstreamIcSt11char_traitsIcEE5closeEv@PLT
.LEHE1:
movq %rsp, %rdi
call _ZNSt14basic_ofstreamIcSt11char_traitsIcEED1Ev@PLT
.L31:
endbr64
movq %rax, %rbx
movq %rsp, %rdi
call _ZNSt14basic_ofstreamIcSt11char_traitsIcEED1Ev@PLT
movq 520(%rsp), %rax
subq %fs:40, %rax
je .L27
call __stack_chk_fail@PLT
.L27:
movq %rbx, %rdi
.LEHB2:
call _Unwind_Resume@PLT
.LEHE2:
.cfi_endproc
.LFE3844:
.globl __gxx_personality_v0
.section .gcc_except_table,"a",@progbits
.LLSDA3844:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE3844-.LLSDACSB3844
.LLSDACSB3844:
.uleb128 .LEHB0-.LFB3844
.uleb128 .LEHE0-.LEHB0
.uleb128 0
.uleb128 0
.uleb128 .LEHB1-.LFB3844
.uleb128 .LEHE1-.LEHB1
.uleb128 .L31-.LFB3844
.uleb128 0
.uleb128 .LEHB2-.LFB3844
.uleb128 .LEHE2-.LEHB2
.uleb128 0
.uleb128 0
.LLSDACSE3844:
.text
.size _Z8saveFilePsPKc, .-_Z8saveFilePsPKc
.section .rodata.str1.1
.LC4:
.string "can not open file :%s\n"
.text
.globl _Z8readFilePsPKc
.type _Z8readFilePsPKc, @function
_Z8readFilePsPKc:
.LFB3843:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA3843
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $528, %rsp
.cfi_def_cfa_offset 576
movq %rdi, %rbx
movq %rsi, %rbp
movq %fs:40, %rax
movq %rax, 520(%rsp)
xorl %eax, %eax
movq %rsp, %r13
leaq 256(%rsp), %rdi
call _ZNSt8ios_baseC2Ev@PLT
leaq 16+_ZTVSt9basic_iosIcSt11char_traitsIcEE(%rip), %rax
movq %rax, 256(%rsp)
movq $0, 472(%rsp)
movb $0, 480(%rsp)
movb $0, 481(%rsp)
movq $0, 488(%rsp)
movq $0, 496(%rsp)
movq $0, 504(%rsp)
movq $0, 512(%rsp)
movq 8+_ZTTSt14basic_ifstreamIcSt11char_traitsIcEE(%rip), %r12
movq %r12, (%rsp)
movq 16+_ZTTSt14basic_ifstreamIcSt11char_traitsIcEE(%rip), %r14
movq -24(%r12), %rax
movq %r14, (%rsp,%rax)
movq $0, 8(%rsp)
movq (%rsp), %rax
movq %r13, %rdi
addq -24(%rax), %rdi
movl $0, %esi
.LEHB3:
call _ZNSt9basic_iosIcSt11char_traitsIcEE4initEPSt15basic_streambufIcS1_E@PLT
.LEHE3:
leaq 24+_ZTVSt14basic_ifstreamIcSt11char_traitsIcEE(%rip), %rax
movq %rax, (%rsp)
leaq 40(%rax), %rax
movq %rax, 256(%rsp)
leaq 16(%rsp), %rdi
.LEHB4:
call _ZNSt13basic_filebufIcSt11char_traitsIcEEC1Ev@PLT
.LEHE4:
leaq 16(%rsp), %rsi
leaq 256(%rsp), %rdi
.LEHB5:
call _ZNSt9basic_iosIcSt11char_traitsIcEE4initEPSt15basic_streambufIcS1_E@PLT
.LEHE5:
jmp .L67
.L59:
endbr64
movq %rax, %rbx
leaq 16(%rsp), %rdi
call _ZNSt13basic_filebufIcSt11char_traitsIcEED1Ev@PLT
.L40:
movq %r12, (%rsp)
movq -24(%r12), %rax
movq %r14, (%rsp,%rax)
movq $0, 8(%rsp)
.L41:
leaq 16+_ZTVSt9basic_iosIcSt11char_traitsIcEE(%rip), %rax
movq %rax, 256(%rsp)
leaq 256(%rsp), %rdi
call _ZNSt8ios_baseD2Ev@PLT
movq 520(%rsp), %rax
subq %fs:40, %rax
je .L42
call __stack_chk_fail@PLT
.L58:
endbr64
movq %rax, %rbx
jmp .L40
.L57:
endbr64
movq %rax, %rbx
jmp .L41
.L42:
movq %rbx, %rdi
.LEHB6:
call _Unwind_Resume@PLT
.LEHE6:
.L67:
leaq 16(%rsp), %rdi
movl $8, %edx
movq %rbp, %rsi
.LEHB7:
call _ZNSt13basic_filebufIcSt11char_traitsIcEE4openEPKcSt13_Ios_Openmode@PLT
testq %rax, %rax
je .L68
movq (%rsp), %rax
movq -24(%rax), %rax
leaq (%rsp,%rax), %rdi
movl $0, %esi
call _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate@PLT
jmp .L44
.L68:
movq (%rsp), %rax
movq -24(%rax), %rax
leaq (%rsp,%rax), %rdi
movl 32(%rdi), %esi
orl $4, %esi
call _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate@PLT
.L44:
movl 288(%rsp), %eax
testb $5, %al
jne .L45
movq %rsp, %rbp
testb $2, %al
je .L46
.L47:
leaq 16(%rsp), %rdi
call _ZNSt13basic_filebufIcSt11char_traitsIcEE5closeEv@PLT
jmp .L69
.L45:
movq %rbp, %rdx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L70
.L71:
addq $2, %rbx
testb $2, 288(%rsp)
jne .L47
.L46:
movq %rbx, %rsi
movq %rbp, %rdi
call _ZNSirsERs@PLT
.LEHE7:
jmp .L71
.L69:
movl $1, %ebx
testq %rax, %rax
je .L72
.L48:
leaq 24+_ZTVSt14basic_ifstreamIcSt11char_traitsIcEE(%rip), %rax
movq %rax, (%rsp)
leaq 40(%rax), %rax
movq %rax, 256(%rsp)
leaq 16+_ZTVSt13basic_filebufIcSt11char_traitsIcEE(%rip), %rax
movq %rax, 16(%rsp)
leaq 16(%rsp), %rdi
.LEHB8:
call _ZNSt13basic_filebufIcSt11char_traitsIcEE5closeEv@PLT
.LEHE8:
jmp .L50
.L72:
movq (%rsp), %rax
movq -24(%rax), %rax
leaq (%rsp,%rax), %rdi
movl 32(%rdi), %esi
orl $4, %esi
.LEHB9:
call _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate@PLT
.LEHE9:
jmp .L48
.L70:
movl $0, %ebx
jmp .L48
.L60:
endbr64
movq %rax, %rdi
call __cxa_begin_catch@PLT
call __cxa_end_catch@PLT
.L50:
leaq 120(%rsp), %rdi
call _ZNSt12__basic_fileIcED1Ev@PLT
leaq 16+_ZTVSt15basic_streambufIcSt11char_traitsIcEE(%rip), %rax
movq %rax, 16(%rsp)
leaq 72(%rsp), %rdi
call _ZNSt6localeD1Ev@PLT
movq %r12, (%rsp)
movq -24(%r12), %rax
movq %r14, (%rsp,%rax)
movq $0, 8(%rsp)
leaq 16+_ZTVSt9basic_iosIcSt11char_traitsIcEE(%rip), %rax
movq %rax, 256(%rsp)
leaq 256(%rsp), %rdi
call _ZNSt8ios_baseD2Ev@PLT
movq 520(%rsp), %rax
subq %fs:40, %rax
jne .L73
movl %ebx, %eax
addq $528, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L56:
.cfi_restore_state
endbr64
movq %rax, %rbx
movq %rsp, %rdi
call _ZNSt14basic_ifstreamIcSt11char_traitsIcEED1Ev@PLT
movq 520(%rsp), %rax
subq %fs:40, %rax
je .L52
call __stack_chk_fail@PLT
.L52:
movq %rbx, %rdi
.LEHB10:
call _Unwind_Resume@PLT
.LEHE10:
.L73:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3843:
.section .gcc_except_table
.align 4
.LLSDA3843:
.byte 0xff
.byte 0x9b
.uleb128 .LLSDATT3843-.LLSDATTD3843
.LLSDATTD3843:
.byte 0x1
.uleb128 .LLSDACSE3843-.LLSDACSB3843
.LLSDACSB3843:
.uleb128 .LEHB3-.LFB3843
.uleb128 .LEHE3-.LEHB3
.uleb128 .L57-.LFB3843
.uleb128 0
.uleb128 .LEHB4-.LFB3843
.uleb128 .LEHE4-.LEHB4
.uleb128 .L58-.LFB3843
.uleb128 0
.uleb128 .LEHB5-.LFB3843
.uleb128 .LEHE5-.LEHB5
.uleb128 .L59-.LFB3843
.uleb128 0
.uleb128 .LEHB6-.LFB3843
.uleb128 .LEHE6-.LEHB6
.uleb128 0
.uleb128 0
.uleb128 .LEHB7-.LFB3843
.uleb128 .LEHE7-.LEHB7
.uleb128 .L56-.LFB3843
.uleb128 0
.uleb128 .LEHB8-.LFB3843
.uleb128 .LEHE8-.LEHB8
.uleb128 .L60-.LFB3843
.uleb128 0x1
.uleb128 .LEHB9-.LFB3843
.uleb128 .LEHE9-.LEHB9
.uleb128 .L56-.LFB3843
.uleb128 0
.uleb128 .LEHB10-.LFB3843
.uleb128 .LEHE10-.LEHB10
.uleb128 0
.uleb128 0
.LLSDACSE3843:
.byte 0x1
.byte 0
.align 4
.long 0
.LLSDATT3843:
.text
.size _Z8readFilePsPKc, .-_Z8readFilePsPKc
.section .rodata.str1.1
.LC5:
.string "./data/originalData/"
.section .rodata.str1.8
.align 8
.LC6:
.string "Usage: %s relative-path-for-phase-data\n"
.align 8
.LC7:
.string "depth_cu and confidence2_cu are put in the same path with %s\n"
.align 8
.LC8:
.string "****Be noticed that the calculation will be done for 1000 times****\n"
.align 8
.LC9:
.string "If you want to profile %s, try "
.align 8
.LC10:
.string "sudo /usr/local/cuda/bin/nvprof %s\n"
.section .rodata.str1.1
.LC11:
.string "otherwise, just run %s\n"
.section .rodata.str1.8
.align 8
.LC12:
.string "Now loading phase data from ./data/originalData/\n"
.align 8
.LC13:
.string "now loading phase data from %s\n"
.section .rodata.str1.1
.LC15:
.string "phase0"
.LC16:
.string "phase90"
.LC17:
.string "phase180"
.LC18:
.string "phase270"
.LC19:
.string "read failed!\n"
.LC20:
.string "calculation is started\n"
.section .rodata.str1.8
.align 8
.LC21:
.string "Calculation is done and saving depth and confidence!\n"
.section .rodata.str1.1
.LC22:
.string "depth_cu"
.text
.globl main
.type main, @function
main:
.LFB3842:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $296, %rsp
.cfi_def_cfa_offset 352
movl %edi, %ebp
movq %rsi, %rbx
movq %fs:40, %rax
movq %rax, 280(%rsp)
xorl %eax, %eax
leaq .LC3(%rip), %r12
movq %r12, %rsi
movl $2, %edi
call __printf_chk@PLT
movq (%rbx), %rdx
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq (%rbx), %rdx
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq (%rbx), %rdx
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq (%rbx), %rdx
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq (%rbx), %rdx
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
cmpl $1, %ebp
je .L116
movq 8(%rbx), %rdx
leaq .LC13(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 8(%rbx), %r12
.L76:
leaq 48(%rsp), %rbx
leaq 80(%rsp), %rbp
leaq .LC0(%rip), %r13
jmp .L78
.L116:
leaq .LC12(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC5(%rip), %r12
jmp .L76
.L77:
addq $8, %rbx
cmpq %rbp, %rbx
je .L117
.L78:
movq %rbx, %rdi
call cudaStreamCreate@PLT
testl %eax, %eax
je .L77
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movq %r13, %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L77
.L117:
leaq 24(%rsp), %rdi
call cudaEventCreate@PLT
movl %eax, %edi
call _Z9checkCuda9cudaError
leaq 32(%rsp), %rdi
call cudaEventCreate@PLT
movl %eax, %edi
call _Z9checkCuda9cudaError
leaq 40(%rsp), %rdi
call cudaEventCreate@PLT
movl %eax, %edi
call _Z9checkCuda9cudaError
movl $0x456a367e, max_distance(%rip)
movl WIDTH(%rip), %edi
imull HEIGHT(%rip), %edi
movslq %edi, %rdi
movabsq $4611686018427387900, %rax
cmpq %rdi, %rax
jb .L79
addq %rdi, %rdi
call _Znam@PLT
movq %rax, %r13
movl WIDTH(%rip), %edi
imull HEIGHT(%rip), %edi
movslq %edi, %rdi
movabsq $4611686018427387900, %rax
cmpq %rdi, %rax
jb .L118
addq %rdi, %rdi
call _Znam@PLT
movq %rax, %r14
movl WIDTH(%rip), %edi
imull HEIGHT(%rip), %edi
movslq %edi, %rdi
movabsq $4611686018427387900, %rax
cmpq %rdi, %rax
jb .L119
addq %rdi, %rdi
call _Znam@PLT
movq %rax, %r15
movl WIDTH(%rip), %edi
imull HEIGHT(%rip), %edi
movslq %edi, %rdi
movabsq $4611686018427387900, %rax
cmpq %rdi, %rax
jb .L120
addq %rdi, %rdi
call _Znam@PLT
movq %rax, (%rsp)
movl WIDTH(%rip), %edi
imull HEIGHT(%rip), %edi
movslq %edi, %rdi
movabsq $4611686018427387900, %rax
cmpq %rdi, %rax
jb .L121
addq %rdi, %rdi
call _Znam@PLT
movq %rax, 8(%rsp)
movl WIDTH(%rip), %eax
imull HEIGHT(%rip), %eax
cltq
movabsq $4611686018427387900, %rdx
cmpq %rax, %rdx
jb .L122
movl $0, %ebx
leaq .LC0(%rip), %rbp
jmp .L92
.L79:
movq 280(%rsp), %rax
subq %fs:40, %rax
je .L82
call __stack_chk_fail@PLT
.L82:
call __cxa_throw_bad_array_new_length@PLT
.L118:
movq 280(%rsp), %rax
subq %fs:40, %rax
je .L85
call __stack_chk_fail@PLT
.L85:
call __cxa_throw_bad_array_new_length@PLT
.L119:
movq 280(%rsp), %rax
subq %fs:40, %rax
je .L88
call __stack_chk_fail@PLT
.L88:
call __cxa_throw_bad_array_new_length@PLT
.L120:
movq 280(%rsp), %rax
subq %fs:40, %rax
je .L91
call __stack_chk_fail@PLT
.L91:
call __cxa_throw_bad_array_new_length@PLT
.L121:
movq 280(%rsp), %rax
subq %fs:40, %rax
je .L94
call __stack_chk_fail@PLT
.L94:
call __cxa_throw_bad_array_new_length@PLT
.L122:
movq 280(%rsp), %rax
subq %fs:40, %rax
je .L95
call __stack_chk_fail@PLT
.L95:
call __cxa_throw_bad_array_new_length@PLT
.L124:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movq %rbp, %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L96
.L125:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movq %rbp, %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L97
.L126:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movq %rbp, %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L98
.L127:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movq %rbp, %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L99
.L128:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movq %rbp, %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L100
.L101:
addq $8, %rbx
cmpq $32, %rbx
je .L123
.L92:
movslq WIDTH(%rip), %rsi
movslq HEIGHT(%rip), %rax
imulq %rax, %rsi
addq %rsi, %rsi
leaq 80(%rsp,%rbx), %rdi
call cudaMalloc@PLT
testl %eax, %eax
jne .L124
.L96:
movslq WIDTH(%rip), %rsi
movslq HEIGHT(%rip), %rax
imulq %rax, %rsi
addq %rsi, %rsi
leaq 112(%rsp,%rbx), %rdi
call cudaMalloc@PLT
testl %eax, %eax
jne .L125
.L97:
movslq WIDTH(%rip), %rsi
movslq HEIGHT(%rip), %rax
imulq %rax, %rsi
addq %rsi, %rsi
leaq 144(%rsp,%rbx), %rdi
call cudaMalloc@PLT
testl %eax, %eax
jne .L126
.L98:
movslq WIDTH(%rip), %rsi
movslq HEIGHT(%rip), %rax
imulq %rax, %rsi
addq %rsi, %rsi
leaq 176(%rsp,%rbx), %rdi
call cudaMalloc@PLT
testl %eax, %eax
jne .L127
.L99:
movslq WIDTH(%rip), %rsi
movslq HEIGHT(%rip), %rax
imulq %rax, %rsi
addq %rsi, %rsi
leaq 208(%rsp,%rbx), %rdi
call cudaMalloc@PLT
testl %eax, %eax
jne .L128
.L100:
movslq WIDTH(%rip), %rsi
movslq HEIGHT(%rip), %rax
imulq %rax, %rsi
addq %rsi, %rsi
leaq 240(%rsp,%rbx), %rdi
call cudaMalloc@PLT
testl %eax, %eax
je .L101
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movq %rbp, %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L101
.L123:
movq %r12, %rdi
call strlen@PLT
leaq 10(%rax), %rbp
movq %rbp, %rdi
call _Znam@PLT
movq %rax, %rbx
movq %r12, %rdi
call strlen@PLT
leaq 10(%rax), %rdx
movq %rbp, %rcx
movl $0, %esi
movq %rbx, %rdi
call __memset_chk@PLT
movq %rbp, %rdx
movq %r12, %rsi
movq %rbx, %rdi
call __strcat_chk@PLT
movq %rbp, %rdx
leaq .LC15(%rip), %rsi
movq %rbx, %rdi
call __strcat_chk@PLT
movq %rbx, %rsi
movq %r13, %rdi
call _Z8readFilePsPKc
testb %al, %al
je .L102
movq %r12, %rdi
call strlen@PLT
movb $0, (%rbx,%rax)
movq %rbp, %rdx
leaq .LC16(%rip), %rsi
movq %rbx, %rdi
call __strcat_chk@PLT
movq %rbx, %rsi
movq %r14, %rdi
call _Z8readFilePsPKc
testb %al, %al
jne .L129
.L102:
leaq .LC19(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 280(%rsp), %rax
subq %fs:40, %rax
jne .L130
movl $0, %eax
addq $296, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L129:
.cfi_restore_state
movq %r12, %rdi
call strlen@PLT
movb $0, (%rbx,%rax)
movq %rbp, %rdx
leaq .LC17(%rip), %rsi
movq %rbx, %rdi
call __strcat_chk@PLT
movq %rbx, %rsi
movq %r15, %rdi
call _Z8readFilePsPKc
testb %al, %al
je .L102
movq %r12, %rdi
call strlen@PLT
movb $0, (%rbx,%rax)
movq %rbp, %rdx
leaq .LC18(%rip), %rsi
movq %rbx, %rdi
call __strcat_chk@PLT
movq %rbx, %rsi
movq (%rsp), %rdi
call _Z8readFilePsPKc
testb %al, %al
je .L102
leaq .LC20(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC21(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 280(%rsp), %rax
subq %fs:40, %rax
jne .L131
leaq .LC22(%rip), %rsi
movq 8(%rsp), %rdi
call _Z8saveFilePsPKc
.L131:
call __stack_chk_fail@PLT
.L130:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3842:
.size main, .-main
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl WIDTH
.data
.align 4
.type WIDTH, @object
.size WIDTH, 4
WIDTH:
.long 288
.globl HEIGHT
.align 4
.type HEIGHT, @object
.size HEIGHT, 4
HEIGHT:
.long 240
.globl max_distance
.bss
.align 4
.type max_distance, @object
.size max_distance, 4
max_distance:
.zero 4
.hidden DW.ref.__gxx_personality_v0
.weak DW.ref.__gxx_personality_v0
.section .data.rel.local.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat
.align 8
.type DW.ref.__gxx_personality_v0, @object
.size DW.ref.__gxx_personality_v0, 8
DW.ref.__gxx_personality_v0:
.quad __gxx_personality_v0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <math.h>
#include <fstream>
#include <array>
#include <cuda.h>
#include <cuda_runtime.h>
#include <iostream>
#include <assert.h>
using namespace std;
#define DEBUG
bool readFile(int16_t* read, const char* filePath);
bool saveFile(int16_t* write, const char* filePath);
float max_distance = 0;
int HEIGHT = 240;
int WIDTH = 288;
timespec diff(timespec start, timespec end)
{
timespec temp;
if ((end.tv_nsec-start.tv_nsec)<0) {
temp.tv_sec = end.tv_sec-start.tv_sec-1;
temp.tv_nsec = 1000000000+end.tv_nsec-start.tv_nsec;
} else {
temp.tv_sec = end.tv_sec-start.tv_sec;
temp.tv_nsec = end.tv_nsec-start.tv_nsec;
}
return temp;
}
inline
cudaError_t checkCuda(cudaError_t result)
{
#if defined(DEBUG) || defined(_DEBUG)
if (result != cudaSuccess) {
fprintf(stderr, "CUDA Runtime Error: %s\n", cudaGetErrorString(result));
assert(result == cudaSuccess);
}
#endif
return result;
}
__global__
void calculate_atan2_cu(int16_t* phase1_cu, int16_t* phase2_cu,
int16_t* phase3_cu, int16_t* phase4_cu,
int16_t* depth_out_cu, int16_t* confidence_out_cu,int N){
const int index = blockIdx.x*blockDim.x + threadIdx.x;
if(index < N){
int16_t phase_1 = *(phase1_cu + index);
int16_t phase_2 = *(phase2_cu + index);
int16_t phase_3 = *(phase3_cu + index);
int16_t phase_4 = *(phase4_cu + index);
//printf("%d,%d,%d,%d\n",phase_1,phase_2,phase_3,phase_4);
auto phase1_t = phase_1 >> 4;
auto phase2_t = phase_2 >> 4;
auto phase3_t = phase_3 >> 4;
auto phase4_t = phase_4 >> 4;
int16_t I = phase1_t - phase3_t;
int16_t Q = phase2_t - phase4_t;
int out_index = index;
confidence_out_cu[out_index] = sqrt(float(I*I + Q*Q));
//printf("rsqrt(%d) confidence_out_cu[%d]=%d",I*I+Q*Q,index,confidence_out_cu[index]);
float angle = atan(-(float)Q/(float)I);
depth_out_cu[out_index] = (angle + M_PI) * 3.7474 * 1000 / (2 * M_PI);
}
}
int main(int argc, char *argv[])
{
const char *path=NULL;
printf("\n");
printf("Usage: %s relative-path-for-phase-data\n",argv[0]);
printf("depth_cu and confidence2_cu are put in the same path with %s\n",argv[0]);
printf("****Be noticed that the calculation will be done for 1000 times****\n");
printf("If you want to profile %s, try ",argv[0]);
printf("sudo /usr/local/cuda/bin/nvprof %s\n",argv[0]);
printf("otherwise, just run %s\n",argv[0]);
printf("\n");
if(argc == 1){
printf("Now loading phase data from ./data/originalData/\n");
path = "./data/originalData/";
}
else{
printf("now loading phase data from %s\n",argv[1]);
path = argv[1];
}
const int nStreams = 4;
timespec time1, time2;
cudaStream_t stream[nStreams];
for (int i = 0; i < nStreams; ++i)
checkCuda( cudaStreamCreate(&stream[i]) );
cudaEvent_t startEvent, stopEvent, dummyEvent;
checkCuda( cudaEventCreate(&startEvent) );
checkCuda( cudaEventCreate(&stopEvent) );
checkCuda( cudaEventCreate(&dummyEvent) );
int fmod = 40;
max_distance = 0.5*299792458/(double)fmod/1000;
int16_t* phase1;
int16_t* phase2;
int16_t* phase3;
int16_t* phase4;
int16_t* depth1_out;
int16_t* confidence1_out;
#ifndef PINNED
phase1 = new int16_t[WIDTH*HEIGHT];
phase2 = new int16_t[WIDTH*HEIGHT];
phase3 = new int16_t[WIDTH*HEIGHT];
phase4 = new int16_t[WIDTH*HEIGHT];
depth1_out = new int16_t[WIDTH*HEIGHT];
confidence1_out = new int16_t[WIDTH*HEIGHT];
#else
checkCuda( cudaMallocHost((void**)&phase1, sizeof(int16_t)*WIDTH*HEIGHT) ); // host pinned
checkCuda( cudaMallocHost((void**)&phase2, sizeof(int16_t)*WIDTH*HEIGHT) ); // host pinned
checkCuda( cudaMallocHost((void**)&phase3, sizeof(int16_t)*WIDTH*HEIGHT) ); // host pinned
checkCuda( cudaMallocHost((void**)&phase4, sizeof(int16_t)*WIDTH*HEIGHT) ); // host pinned
checkCuda( cudaMallocHost((void**)&depth1_out, sizeof(int16_t)* WIDTH*HEIGHT) ); // host pinned
checkCuda( cudaMallocHost((void**)&confidence1_out, sizeof(int16_t)* WIDTH*HEIGHT) ); // host pinned
#endif
int16_t *phase1_cu[nStreams],*phase2_cu[nStreams],*phase3_cu[nStreams],*phase4_cu[nStreams],*depth1_out_cu[nStreams],*confidence1_out_cu[nStreams];
for(int i=0;i<nStreams;i++){
checkCuda(cudaMalloc((void**)&phase1_cu[i], sizeof(int16_t) * WIDTH * HEIGHT));
checkCuda(cudaMalloc((void**)&phase2_cu[i], sizeof(int16_t) * WIDTH * HEIGHT));
checkCuda(cudaMalloc((void**)&phase3_cu[i], sizeof(int16_t) * WIDTH * HEIGHT));
checkCuda(cudaMalloc((void**)&phase4_cu[i], sizeof(int16_t) * WIDTH * HEIGHT));
checkCuda(cudaMalloc((void**)&depth1_out_cu[i], sizeof(int16_t) * WIDTH * HEIGHT));
checkCuda(cudaMalloc((void**)&confidence1_out_cu[i], sizeof(int16_t) * WIDTH * HEIGHT));
}
char *file = new char[ strlen(path)+ 10];
memset(file,0,strlen(path)+ 10);
strcat(file,path);
if(!readFile(phase1, strcat(file,"phase0")) || (*(file+strlen(path)) = '\0')||
!readFile(phase2, strcat(file,"phase90")) ||(*(file+strlen(path)) = '\0')||
!readFile(phase3, strcat(file,"phase180")) ||(*(file+strlen(path)) = '\0')||
!readFile(phase4, strcat(file,"phase270")) )
{
printf("read failed!\n");
return 0;
}
printf("calculation is started\n");
float ms; // elapsed time in milliseconds
#ifdef STREAM
checkCuda( cudaEventRecord(startEvent,stream[nStreams-1]) );
clock_gettime(CLOCK_MONOTONIC, &time1);
for(int i=0;i<1000;i+=nStreams){
// Transfer data from host to device memory
for(int j=0;j<nStreams;j++){
checkCuda(cudaMemcpyAsync(phase1_cu[j],phase1, sizeof(int16_t) * WIDTH * HEIGHT, cudaMemcpyHostToDevice,stream[j]));
checkCuda(cudaMemcpyAsync(phase2_cu[j],phase2, sizeof(int16_t) * WIDTH * HEIGHT, cudaMemcpyHostToDevice,stream[j]));
checkCuda(cudaMemcpyAsync(phase3_cu[j],phase3, sizeof(int16_t) * WIDTH * HEIGHT, cudaMemcpyHostToDevice,stream[j]));
checkCuda(cudaMemcpyAsync(phase4_cu[j],phase4, sizeof(int16_t) * WIDTH * HEIGHT, cudaMemcpyHostToDevice,stream[j]));
}
for(int j=0;j<nStreams;j++){
calculate_atan2_cu<<<540,128,0,stream[j]>>>(phase1_cu[j],phase2_cu[j],phase3_cu[j],phase4_cu[j],depth1_out_cu[j],confidence1_out_cu[j], WIDTH*HEIGHT);
}
for(int j=0;j<nStreams;j++){
checkCuda(cudaMemcpyAsync(depth1_out, depth1_out_cu[j],sizeof(int16_t) * WIDTH * HEIGHT, cudaMemcpyDeviceToHost,stream[j]));
checkCuda(cudaMemcpyAsync(confidence1_out,confidence1_out_cu[j], sizeof(int16_t) * WIDTH * HEIGHT, cudaMemcpyDeviceToHost,stream[j]));
}
}
checkCuda( cudaEventRecord(stopEvent, stream[nStreams-1]) );
checkCuda( cudaEventSynchronize(stopEvent) );
checkCuda( cudaEventElapsedTime(&ms, startEvent, stopEvent) );
cudaDeviceSynchronize();
clock_gettime(CLOCK_MONOTONIC, &time2);
printf("Time for multiple stream transfer and execute (ms): %f ", ms);
cout<<diff(time1,time2).tv_sec<<":"<<diff(time1,time2).tv_nsec<<endl;
printf("stream with %d calculation is done\n",nStreams);
#endif
#ifdef NULLSTREAM
clock_gettime(CLOCK_MONOTONIC, &time1);
checkCuda( cudaEventRecord(startEvent,0) );
for(int i=0;i<1000;i++){
// Transfer data from host to device memory
cudaMemcpy(phase1_cu[0],phase1, sizeof(int16_t) * WIDTH * HEIGHT, cudaMemcpyHostToDevice);
cudaMemcpy(phase2_cu[0],phase2, sizeof(int16_t) * WIDTH * HEIGHT, cudaMemcpyHostToDevice);
cudaMemcpy(phase3_cu[0],phase3, sizeof(int16_t) * WIDTH * HEIGHT, cudaMemcpyHostToDevice);
cudaMemcpy(phase4_cu[0],phase4, sizeof(int16_t) * WIDTH * HEIGHT, cudaMemcpyHostToDevice);
calculate_atan2_cu<<<540,128>>>(phase1_cu[0],phase2_cu[0],phase3_cu[0],phase4_cu[0],depth1_out_cu[0],confidence1_out_cu[0], WIDTH*HEIGHT);
cudaMemcpy(depth1_out, depth1_out_cu[0],sizeof(int16_t) * WIDTH * HEIGHT, cudaMemcpyDeviceToHost);
cudaMemcpy(confidence1_out,confidence1_out_cu[0], sizeof(int16_t) * WIDTH * HEIGHT, cudaMemcpyDeviceToHost);
}
checkCuda( cudaEventRecord(stopEvent, 0) );
checkCuda( cudaEventSynchronize(stopEvent) );
checkCuda( cudaEventElapsedTime(&ms, startEvent, stopEvent) );
cudaDeviceSynchronize();
clock_gettime(CLOCK_MONOTONIC, &time2);
printf("Time for NULL stream transfer and execute (ms): %f ", ms);
cout<<diff(time1,time2).tv_sec<<":"<<diff(time1,time2).tv_nsec<<endl;
#endif
printf("Calculation is done and saving depth and confidence!\n");
saveFile(depth1_out, "depth_cu");
saveFile(confidence1_out, "confidence2_cu");
printf("\n");
return 0;
}
bool readFile(int16_t* read, const char* filePath)
{
// printf("filePath=%s\n",filePath);
std::ifstream infile;
infile.open(filePath);
if(!infile)
{
printf("can not open file :%s\n",filePath);
return false;
}
while(!infile.eof())
{
infile>>*read;
read++;
}
infile.close();
return true;
}
bool saveFile(int16_t* write, const char* filePath)
{
std::ofstream fout(filePath);
for(auto j=0; j < HEIGHT; ++j)
{
for(auto i =0; i < WIDTH; i++)
{
fout << write[j*WIDTH+i] << "\t" ;
}
fout << "\n";
}
fout.close();
} | #include <math.h>
#include <fstream>
#include <array>
#include <hip/hip_runtime.h>
#include <iostream>
#include <assert.h>
using namespace std;
#define DEBUG
bool readFile(int16_t* read, const char* filePath);
bool saveFile(int16_t* write, const char* filePath);
float max_distance = 0;
int HEIGHT = 240;
int WIDTH = 288;
timespec diff(timespec start, timespec end)
{
timespec temp;
if ((end.tv_nsec-start.tv_nsec)<0) {
temp.tv_sec = end.tv_sec-start.tv_sec-1;
temp.tv_nsec = 1000000000+end.tv_nsec-start.tv_nsec;
} else {
temp.tv_sec = end.tv_sec-start.tv_sec;
temp.tv_nsec = end.tv_nsec-start.tv_nsec;
}
return temp;
}
inline
hipError_t checkCuda(hipError_t result)
{
#if defined(DEBUG) || defined(_DEBUG)
if (result != hipSuccess) {
fprintf(stderr, "CUDA Runtime Error: %s\n", hipGetErrorString(result));
assert(result == hipSuccess);
}
#endif
return result;
}
__global__
void calculate_atan2_cu(int16_t* phase1_cu, int16_t* phase2_cu,
int16_t* phase3_cu, int16_t* phase4_cu,
int16_t* depth_out_cu, int16_t* confidence_out_cu,int N){
const int index = blockIdx.x*blockDim.x + threadIdx.x;
if(index < N){
int16_t phase_1 = *(phase1_cu + index);
int16_t phase_2 = *(phase2_cu + index);
int16_t phase_3 = *(phase3_cu + index);
int16_t phase_4 = *(phase4_cu + index);
//printf("%d,%d,%d,%d\n",phase_1,phase_2,phase_3,phase_4);
auto phase1_t = phase_1 >> 4;
auto phase2_t = phase_2 >> 4;
auto phase3_t = phase_3 >> 4;
auto phase4_t = phase_4 >> 4;
int16_t I = phase1_t - phase3_t;
int16_t Q = phase2_t - phase4_t;
int out_index = index;
confidence_out_cu[out_index] = sqrt(float(I*I + Q*Q));
//printf("rsqrt(%d) confidence_out_cu[%d]=%d",I*I+Q*Q,index,confidence_out_cu[index]);
float angle = atan(-(float)Q/(float)I);
depth_out_cu[out_index] = (angle + M_PI) * 3.7474 * 1000 / (2 * M_PI);
}
}
int main(int argc, char *argv[])
{
const char *path=NULL;
printf("\n");
printf("Usage: %s relative-path-for-phase-data\n",argv[0]);
printf("depth_cu and confidence2_cu are put in the same path with %s\n",argv[0]);
printf("****Be noticed that the calculation will be done for 1000 times****\n");
printf("If you want to profile %s, try ",argv[0]);
printf("sudo /usr/local/cuda/bin/nvprof %s\n",argv[0]);
printf("otherwise, just run %s\n",argv[0]);
printf("\n");
if(argc == 1){
printf("Now loading phase data from ./data/originalData/\n");
path = "./data/originalData/";
}
else{
printf("now loading phase data from %s\n",argv[1]);
path = argv[1];
}
const int nStreams = 4;
timespec time1, time2;
hipStream_t stream[nStreams];
for (int i = 0; i < nStreams; ++i)
checkCuda( hipStreamCreate(&stream[i]) );
hipEvent_t startEvent, stopEvent, dummyEvent;
checkCuda( hipEventCreate(&startEvent) );
checkCuda( hipEventCreate(&stopEvent) );
checkCuda( hipEventCreate(&dummyEvent) );
int fmod = 40;
max_distance = 0.5*299792458/(double)fmod/1000;
int16_t* phase1;
int16_t* phase2;
int16_t* phase3;
int16_t* phase4;
int16_t* depth1_out;
int16_t* confidence1_out;
#ifndef PINNED
phase1 = new int16_t[WIDTH*HEIGHT];
phase2 = new int16_t[WIDTH*HEIGHT];
phase3 = new int16_t[WIDTH*HEIGHT];
phase4 = new int16_t[WIDTH*HEIGHT];
depth1_out = new int16_t[WIDTH*HEIGHT];
confidence1_out = new int16_t[WIDTH*HEIGHT];
#else
checkCuda( hipHostMalloc((void**)&phase1, sizeof(int16_t)*WIDTH*HEIGHT, hipHostMallocDefault) ); // host pinned
checkCuda( hipHostMalloc((void**)&phase2, sizeof(int16_t)*WIDTH*HEIGHT, hipHostMallocDefault) ); // host pinned
checkCuda( hipHostMalloc((void**)&phase3, sizeof(int16_t)*WIDTH*HEIGHT, hipHostMallocDefault) ); // host pinned
checkCuda( hipHostMalloc((void**)&phase4, sizeof(int16_t)*WIDTH*HEIGHT, hipHostMallocDefault) ); // host pinned
checkCuda( hipHostMalloc((void**)&depth1_out, sizeof(int16_t)* WIDTH*HEIGHT, hipHostMallocDefault) ); // host pinned
checkCuda( hipHostMalloc((void**)&confidence1_out, sizeof(int16_t)* WIDTH*HEIGHT, hipHostMallocDefault) ); // host pinned
#endif
int16_t *phase1_cu[nStreams],*phase2_cu[nStreams],*phase3_cu[nStreams],*phase4_cu[nStreams],*depth1_out_cu[nStreams],*confidence1_out_cu[nStreams];
for(int i=0;i<nStreams;i++){
checkCuda(hipMalloc((void**)&phase1_cu[i], sizeof(int16_t) * WIDTH * HEIGHT));
checkCuda(hipMalloc((void**)&phase2_cu[i], sizeof(int16_t) * WIDTH * HEIGHT));
checkCuda(hipMalloc((void**)&phase3_cu[i], sizeof(int16_t) * WIDTH * HEIGHT));
checkCuda(hipMalloc((void**)&phase4_cu[i], sizeof(int16_t) * WIDTH * HEIGHT));
checkCuda(hipMalloc((void**)&depth1_out_cu[i], sizeof(int16_t) * WIDTH * HEIGHT));
checkCuda(hipMalloc((void**)&confidence1_out_cu[i], sizeof(int16_t) * WIDTH * HEIGHT));
}
char *file = new char[ strlen(path)+ 10];
memset(file,0,strlen(path)+ 10);
strcat(file,path);
if(!readFile(phase1, strcat(file,"phase0")) || (*(file+strlen(path)) = '\0')||
!readFile(phase2, strcat(file,"phase90")) ||(*(file+strlen(path)) = '\0')||
!readFile(phase3, strcat(file,"phase180")) ||(*(file+strlen(path)) = '\0')||
!readFile(phase4, strcat(file,"phase270")) )
{
printf("read failed!\n");
return 0;
}
printf("calculation is started\n");
float ms; // elapsed time in milliseconds
#ifdef STREAM
checkCuda( hipEventRecord(startEvent,stream[nStreams-1]) );
clock_gettime(CLOCK_MONOTONIC, &time1);
for(int i=0;i<1000;i+=nStreams){
// Transfer data from host to device memory
for(int j=0;j<nStreams;j++){
checkCuda(hipMemcpyAsync(phase1_cu[j],phase1, sizeof(int16_t) * WIDTH * HEIGHT, hipMemcpyHostToDevice,stream[j]));
checkCuda(hipMemcpyAsync(phase2_cu[j],phase2, sizeof(int16_t) * WIDTH * HEIGHT, hipMemcpyHostToDevice,stream[j]));
checkCuda(hipMemcpyAsync(phase3_cu[j],phase3, sizeof(int16_t) * WIDTH * HEIGHT, hipMemcpyHostToDevice,stream[j]));
checkCuda(hipMemcpyAsync(phase4_cu[j],phase4, sizeof(int16_t) * WIDTH * HEIGHT, hipMemcpyHostToDevice,stream[j]));
}
for(int j=0;j<nStreams;j++){
calculate_atan2_cu<<<540,128,0,stream[j]>>>(phase1_cu[j],phase2_cu[j],phase3_cu[j],phase4_cu[j],depth1_out_cu[j],confidence1_out_cu[j], WIDTH*HEIGHT);
}
for(int j=0;j<nStreams;j++){
checkCuda(hipMemcpyAsync(depth1_out, depth1_out_cu[j],sizeof(int16_t) * WIDTH * HEIGHT, hipMemcpyDeviceToHost,stream[j]));
checkCuda(hipMemcpyAsync(confidence1_out,confidence1_out_cu[j], sizeof(int16_t) * WIDTH * HEIGHT, hipMemcpyDeviceToHost,stream[j]));
}
}
checkCuda( hipEventRecord(stopEvent, stream[nStreams-1]) );
checkCuda( hipEventSynchronize(stopEvent) );
checkCuda( hipEventElapsedTime(&ms, startEvent, stopEvent) );
hipDeviceSynchronize();
clock_gettime(CLOCK_MONOTONIC, &time2);
printf("Time for multiple stream transfer and execute (ms): %f ", ms);
cout<<diff(time1,time2).tv_sec<<":"<<diff(time1,time2).tv_nsec<<endl;
printf("stream with %d calculation is done\n",nStreams);
#endif
#ifdef NULLSTREAM
clock_gettime(CLOCK_MONOTONIC, &time1);
checkCuda( hipEventRecord(startEvent,0) );
for(int i=0;i<1000;i++){
// Transfer data from host to device memory
hipMemcpy(phase1_cu[0],phase1, sizeof(int16_t) * WIDTH * HEIGHT, hipMemcpyHostToDevice);
hipMemcpy(phase2_cu[0],phase2, sizeof(int16_t) * WIDTH * HEIGHT, hipMemcpyHostToDevice);
hipMemcpy(phase3_cu[0],phase3, sizeof(int16_t) * WIDTH * HEIGHT, hipMemcpyHostToDevice);
hipMemcpy(phase4_cu[0],phase4, sizeof(int16_t) * WIDTH * HEIGHT, hipMemcpyHostToDevice);
calculate_atan2_cu<<<540,128>>>(phase1_cu[0],phase2_cu[0],phase3_cu[0],phase4_cu[0],depth1_out_cu[0],confidence1_out_cu[0], WIDTH*HEIGHT);
hipMemcpy(depth1_out, depth1_out_cu[0],sizeof(int16_t) * WIDTH * HEIGHT, hipMemcpyDeviceToHost);
hipMemcpy(confidence1_out,confidence1_out_cu[0], sizeof(int16_t) * WIDTH * HEIGHT, hipMemcpyDeviceToHost);
}
checkCuda( hipEventRecord(stopEvent, 0) );
checkCuda( hipEventSynchronize(stopEvent) );
checkCuda( hipEventElapsedTime(&ms, startEvent, stopEvent) );
hipDeviceSynchronize();
clock_gettime(CLOCK_MONOTONIC, &time2);
printf("Time for NULL stream transfer and execute (ms): %f ", ms);
cout<<diff(time1,time2).tv_sec<<":"<<diff(time1,time2).tv_nsec<<endl;
#endif
printf("Calculation is done and saving depth and confidence!\n");
saveFile(depth1_out, "depth_cu");
saveFile(confidence1_out, "confidence2_cu");
printf("\n");
return 0;
}
bool readFile(int16_t* read, const char* filePath)
{
// printf("filePath=%s\n",filePath);
std::ifstream infile;
infile.open(filePath);
if(!infile)
{
printf("can not open file :%s\n",filePath);
return false;
}
while(!infile.eof())
{
infile>>*read;
read++;
}
infile.close();
return true;
}
bool saveFile(int16_t* write, const char* filePath)
{
std::ofstream fout(filePath);
for(auto j=0; j < HEIGHT; ++j)
{
for(auto i =0; i < WIDTH; i++)
{
fout << write[j*WIDTH+i] << "\t" ;
}
fout << "\n";
}
fout.close();
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <math.h>
#include <fstream>
#include <array>
#include <hip/hip_runtime.h>
#include <iostream>
#include <assert.h>
using namespace std;
#define DEBUG
bool readFile(int16_t* read, const char* filePath);
bool saveFile(int16_t* write, const char* filePath);
float max_distance = 0;
int HEIGHT = 240;
int WIDTH = 288;
timespec diff(timespec start, timespec end)
{
timespec temp;
if ((end.tv_nsec-start.tv_nsec)<0) {
temp.tv_sec = end.tv_sec-start.tv_sec-1;
temp.tv_nsec = 1000000000+end.tv_nsec-start.tv_nsec;
} else {
temp.tv_sec = end.tv_sec-start.tv_sec;
temp.tv_nsec = end.tv_nsec-start.tv_nsec;
}
return temp;
}
inline
hipError_t checkCuda(hipError_t result)
{
#if defined(DEBUG) || defined(_DEBUG)
if (result != hipSuccess) {
fprintf(stderr, "CUDA Runtime Error: %s\n", hipGetErrorString(result));
assert(result == hipSuccess);
}
#endif
return result;
}
__global__
void calculate_atan2_cu(int16_t* phase1_cu, int16_t* phase2_cu,
int16_t* phase3_cu, int16_t* phase4_cu,
int16_t* depth_out_cu, int16_t* confidence_out_cu,int N){
const int index = blockIdx.x*blockDim.x + threadIdx.x;
if(index < N){
int16_t phase_1 = *(phase1_cu + index);
int16_t phase_2 = *(phase2_cu + index);
int16_t phase_3 = *(phase3_cu + index);
int16_t phase_4 = *(phase4_cu + index);
//printf("%d,%d,%d,%d\n",phase_1,phase_2,phase_3,phase_4);
auto phase1_t = phase_1 >> 4;
auto phase2_t = phase_2 >> 4;
auto phase3_t = phase_3 >> 4;
auto phase4_t = phase_4 >> 4;
int16_t I = phase1_t - phase3_t;
int16_t Q = phase2_t - phase4_t;
int out_index = index;
confidence_out_cu[out_index] = sqrt(float(I*I + Q*Q));
//printf("rsqrt(%d) confidence_out_cu[%d]=%d",I*I+Q*Q,index,confidence_out_cu[index]);
float angle = atan(-(float)Q/(float)I);
depth_out_cu[out_index] = (angle + M_PI) * 3.7474 * 1000 / (2 * M_PI);
}
}
int main(int argc, char *argv[])
{
const char *path=NULL;
printf("\n");
printf("Usage: %s relative-path-for-phase-data\n",argv[0]);
printf("depth_cu and confidence2_cu are put in the same path with %s\n",argv[0]);
printf("****Be noticed that the calculation will be done for 1000 times****\n");
printf("If you want to profile %s, try ",argv[0]);
printf("sudo /usr/local/cuda/bin/nvprof %s\n",argv[0]);
printf("otherwise, just run %s\n",argv[0]);
printf("\n");
if(argc == 1){
printf("Now loading phase data from ./data/originalData/\n");
path = "./data/originalData/";
}
else{
printf("now loading phase data from %s\n",argv[1]);
path = argv[1];
}
const int nStreams = 4;
timespec time1, time2;
hipStream_t stream[nStreams];
for (int i = 0; i < nStreams; ++i)
checkCuda( hipStreamCreate(&stream[i]) );
hipEvent_t startEvent, stopEvent, dummyEvent;
checkCuda( hipEventCreate(&startEvent) );
checkCuda( hipEventCreate(&stopEvent) );
checkCuda( hipEventCreate(&dummyEvent) );
int fmod = 40;
max_distance = 0.5*299792458/(double)fmod/1000;
int16_t* phase1;
int16_t* phase2;
int16_t* phase3;
int16_t* phase4;
int16_t* depth1_out;
int16_t* confidence1_out;
#ifndef PINNED
phase1 = new int16_t[WIDTH*HEIGHT];
phase2 = new int16_t[WIDTH*HEIGHT];
phase3 = new int16_t[WIDTH*HEIGHT];
phase4 = new int16_t[WIDTH*HEIGHT];
depth1_out = new int16_t[WIDTH*HEIGHT];
confidence1_out = new int16_t[WIDTH*HEIGHT];
#else
checkCuda( hipHostMalloc((void**)&phase1, sizeof(int16_t)*WIDTH*HEIGHT, hipHostMallocDefault) ); // host pinned
checkCuda( hipHostMalloc((void**)&phase2, sizeof(int16_t)*WIDTH*HEIGHT, hipHostMallocDefault) ); // host pinned
checkCuda( hipHostMalloc((void**)&phase3, sizeof(int16_t)*WIDTH*HEIGHT, hipHostMallocDefault) ); // host pinned
checkCuda( hipHostMalloc((void**)&phase4, sizeof(int16_t)*WIDTH*HEIGHT, hipHostMallocDefault) ); // host pinned
checkCuda( hipHostMalloc((void**)&depth1_out, sizeof(int16_t)* WIDTH*HEIGHT, hipHostMallocDefault) ); // host pinned
checkCuda( hipHostMalloc((void**)&confidence1_out, sizeof(int16_t)* WIDTH*HEIGHT, hipHostMallocDefault) ); // host pinned
#endif
int16_t *phase1_cu[nStreams],*phase2_cu[nStreams],*phase3_cu[nStreams],*phase4_cu[nStreams],*depth1_out_cu[nStreams],*confidence1_out_cu[nStreams];
for(int i=0;i<nStreams;i++){
checkCuda(hipMalloc((void**)&phase1_cu[i], sizeof(int16_t) * WIDTH * HEIGHT));
checkCuda(hipMalloc((void**)&phase2_cu[i], sizeof(int16_t) * WIDTH * HEIGHT));
checkCuda(hipMalloc((void**)&phase3_cu[i], sizeof(int16_t) * WIDTH * HEIGHT));
checkCuda(hipMalloc((void**)&phase4_cu[i], sizeof(int16_t) * WIDTH * HEIGHT));
checkCuda(hipMalloc((void**)&depth1_out_cu[i], sizeof(int16_t) * WIDTH * HEIGHT));
checkCuda(hipMalloc((void**)&confidence1_out_cu[i], sizeof(int16_t) * WIDTH * HEIGHT));
}
char *file = new char[ strlen(path)+ 10];
memset(file,0,strlen(path)+ 10);
strcat(file,path);
if(!readFile(phase1, strcat(file,"phase0")) || (*(file+strlen(path)) = '\0')||
!readFile(phase2, strcat(file,"phase90")) ||(*(file+strlen(path)) = '\0')||
!readFile(phase3, strcat(file,"phase180")) ||(*(file+strlen(path)) = '\0')||
!readFile(phase4, strcat(file,"phase270")) )
{
printf("read failed!\n");
return 0;
}
printf("calculation is started\n");
float ms; // elapsed time in milliseconds
#ifdef STREAM
checkCuda( hipEventRecord(startEvent,stream[nStreams-1]) );
clock_gettime(CLOCK_MONOTONIC, &time1);
for(int i=0;i<1000;i+=nStreams){
// Transfer data from host to device memory
for(int j=0;j<nStreams;j++){
checkCuda(hipMemcpyAsync(phase1_cu[j],phase1, sizeof(int16_t) * WIDTH * HEIGHT, hipMemcpyHostToDevice,stream[j]));
checkCuda(hipMemcpyAsync(phase2_cu[j],phase2, sizeof(int16_t) * WIDTH * HEIGHT, hipMemcpyHostToDevice,stream[j]));
checkCuda(hipMemcpyAsync(phase3_cu[j],phase3, sizeof(int16_t) * WIDTH * HEIGHT, hipMemcpyHostToDevice,stream[j]));
checkCuda(hipMemcpyAsync(phase4_cu[j],phase4, sizeof(int16_t) * WIDTH * HEIGHT, hipMemcpyHostToDevice,stream[j]));
}
for(int j=0;j<nStreams;j++){
calculate_atan2_cu<<<540,128,0,stream[j]>>>(phase1_cu[j],phase2_cu[j],phase3_cu[j],phase4_cu[j],depth1_out_cu[j],confidence1_out_cu[j], WIDTH*HEIGHT);
}
for(int j=0;j<nStreams;j++){
checkCuda(hipMemcpyAsync(depth1_out, depth1_out_cu[j],sizeof(int16_t) * WIDTH * HEIGHT, hipMemcpyDeviceToHost,stream[j]));
checkCuda(hipMemcpyAsync(confidence1_out,confidence1_out_cu[j], sizeof(int16_t) * WIDTH * HEIGHT, hipMemcpyDeviceToHost,stream[j]));
}
}
checkCuda( hipEventRecord(stopEvent, stream[nStreams-1]) );
checkCuda( hipEventSynchronize(stopEvent) );
checkCuda( hipEventElapsedTime(&ms, startEvent, stopEvent) );
hipDeviceSynchronize();
clock_gettime(CLOCK_MONOTONIC, &time2);
printf("Time for multiple stream transfer and execute (ms): %f ", ms);
cout<<diff(time1,time2).tv_sec<<":"<<diff(time1,time2).tv_nsec<<endl;
printf("stream with %d calculation is done\n",nStreams);
#endif
#ifdef NULLSTREAM
clock_gettime(CLOCK_MONOTONIC, &time1);
checkCuda( hipEventRecord(startEvent,0) );
for(int i=0;i<1000;i++){
// Transfer data from host to device memory
hipMemcpy(phase1_cu[0],phase1, sizeof(int16_t) * WIDTH * HEIGHT, hipMemcpyHostToDevice);
hipMemcpy(phase2_cu[0],phase2, sizeof(int16_t) * WIDTH * HEIGHT, hipMemcpyHostToDevice);
hipMemcpy(phase3_cu[0],phase3, sizeof(int16_t) * WIDTH * HEIGHT, hipMemcpyHostToDevice);
hipMemcpy(phase4_cu[0],phase4, sizeof(int16_t) * WIDTH * HEIGHT, hipMemcpyHostToDevice);
calculate_atan2_cu<<<540,128>>>(phase1_cu[0],phase2_cu[0],phase3_cu[0],phase4_cu[0],depth1_out_cu[0],confidence1_out_cu[0], WIDTH*HEIGHT);
hipMemcpy(depth1_out, depth1_out_cu[0],sizeof(int16_t) * WIDTH * HEIGHT, hipMemcpyDeviceToHost);
hipMemcpy(confidence1_out,confidence1_out_cu[0], sizeof(int16_t) * WIDTH * HEIGHT, hipMemcpyDeviceToHost);
}
checkCuda( hipEventRecord(stopEvent, 0) );
checkCuda( hipEventSynchronize(stopEvent) );
checkCuda( hipEventElapsedTime(&ms, startEvent, stopEvent) );
hipDeviceSynchronize();
clock_gettime(CLOCK_MONOTONIC, &time2);
printf("Time for NULL stream transfer and execute (ms): %f ", ms);
cout<<diff(time1,time2).tv_sec<<":"<<diff(time1,time2).tv_nsec<<endl;
#endif
printf("Calculation is done and saving depth and confidence!\n");
saveFile(depth1_out, "depth_cu");
saveFile(confidence1_out, "confidence2_cu");
printf("\n");
return 0;
}
bool readFile(int16_t* read, const char* filePath)
{
// printf("filePath=%s\n",filePath);
std::ifstream infile;
infile.open(filePath);
if(!infile)
{
printf("can not open file :%s\n",filePath);
return false;
}
while(!infile.eof())
{
infile>>*read;
read++;
}
infile.close();
return true;
}
bool saveFile(int16_t* write, const char* filePath)
{
std::ofstream fout(filePath);
for(auto j=0; j < HEIGHT; ++j)
{
for(auto i =0; i < WIDTH; i++)
{
fout << write[j*WIDTH+i] << "\t" ;
}
fout << "\n";
}
fout.close();
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z18calculate_atan2_cuPsS_S_S_S_S_i
.globl _Z18calculate_atan2_cuPsS_S_S_S_S_i
.p2align 8
.type _Z18calculate_atan2_cuPsS_S_S_S_S_i,@function
_Z18calculate_atan2_cuPsS_S_S_S_S_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x44
s_load_b32 s3, s[0:1], 0x30
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b256 s[4:11], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_mov_b32 s2, 0x3b2d2a58
s_mov_b32 s3, 0x400921fb
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 1, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v6, vcc_lo, s10, v0
v_add_co_ci_u32_e32 v7, vcc_lo, s11, v1, vcc_lo
v_add_co_u32 v8, vcc_lo, s8, v0
v_add_co_ci_u32_e32 v9, vcc_lo, s9, v1, vcc_lo
global_load_u16 v2, v[2:3], off
global_load_u16 v3, v[4:5], off
global_load_u16 v4, v[6:7], off
global_load_u16 v5, v[8:9], off
s_mov_b32 s5, 0x400dfaac
s_mov_b32 s4, 0xd9e83e42
s_waitcnt vmcnt(3)
v_ashrrev_i16 v2, 4, v2
s_waitcnt vmcnt(2)
v_ashrrev_i16 v3, 4, v3
s_waitcnt vmcnt(1)
v_ashrrev_i16 v4, 4, v4
s_waitcnt vmcnt(0)
v_ashrrev_i16 v5, 4, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_nc_u16 v3, v3, v4
v_sub_nc_u16 v2, v2, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_bfe_i32 v12, v3, 0, 16
v_bfe_i32 v13, v2, 0, 16
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cvt_f32_i32_e32 v2, v12
v_cvt_f32_i32_e32 v3, v13
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_div_scale_f32 v4, null, v3, v3, -v2
v_div_scale_f32 v7, vcc_lo, -v2, v3, -v2
v_rcp_f32_e32 v5, v4
s_waitcnt_depctr 0xfff
v_fma_f32 v6, -v4, v5, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v5, v6, v5
v_mul_f32_e32 v6, v7, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v8, -v4, v6, v7
v_fmac_f32_e32 v6, v8, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v4, -v4, v6, v7
v_div_fmas_f32 v4, v4, v5, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fixup_f32 v2, v4, v3, -v2
v_rcp_f32_e64 v3, |v2|
v_cmp_gt_f32_e64 vcc_lo, |v2|, 1.0
s_waitcnt_depctr 0xfff
v_cndmask_b32_e64 v3, |v2|, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v4, v3, v3
v_fmaak_f32 v5, s2, v4, 0xbc7a590c
s_mov_b32 s2, 0x54442d18
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmaak_f32 v5, v4, v5, 0x3d29fb3f
v_fmaak_f32 v5, v4, v5, 0xbd97d4d7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmaak_f32 v5, v4, v5, 0x3dd931b2
v_fmaak_f32 v5, v4, v5, 0xbe1160e6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmaak_f32 v5, v4, v5, 0x3e4cb8bf
v_fmaak_f32 v5, v4, v5, 0xbeaaaa62
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v4, v4, v5
v_fmac_f32_e32 v3, v3, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_f32_e32 v4, 0x3fc90fdb, v3
v_cndmask_b32_e32 v3, v3, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_bfi_b32 v2, 0x7fffffff, v3, v2
v_cvt_f64_f32_e32 v[2:3], v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_f64 v[2:3], v[2:3], s[2:3]
s_mov_b32 s3, 0x401921fb
v_mul_f64 v[2:3], v[2:3], s[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[2:3], v[2:3], 0x408f4000
v_div_scale_f64 v[4:5], null, s[2:3], s[2:3], v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f64_e32 v[6:7], v[4:5]
s_waitcnt_depctr 0xfff
v_fma_f64 v[8:9], -v[4:5], v[6:7], 1.0
v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[8:9], -v[4:5], v[6:7], 1.0
v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7]
v_div_scale_f64 v[8:9], vcc_lo, v[2:3], s[2:3], v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[10:11], v[8:9], v[6:7]
v_fma_f64 v[4:5], -v[4:5], v[10:11], v[8:9]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_div_fmas_f64 v[4:5], v[4:5], v[6:7], v[10:11]
v_mul_i32_i24_e32 v6, v13, v13
v_mad_i32_i24 v6, v12, v12, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_f32_i32_e32 v6, v6
v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v6
v_div_fixup_f64 v[2:3], v[4:5], s[2:3], v[2:3]
v_mul_f32_e32 v4, 0x4f800000, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v4, v6, v4, vcc_lo
v_sqrt_f32_e32 v5, v4
s_waitcnt_depctr 0xfff
v_add_nc_u32_e32 v6, -1, v5
v_add_nc_u32_e32 v8, 1, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v7, -v6, v5, v4
v_cmp_ge_f32_e64 s2, 0, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
v_cndmask_b32_e64 v6, v5, v6, s2
v_fma_f32 v5, -v8, v5, v4
v_cvt_i32_f64_e32 v7, v[2:3]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_lt_f32_e64 s2, 0, v5
v_cndmask_b32_e64 v2, v6, v8, s2
s_load_b128 s[0:3], s[0:1], 0x20
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v3, 0x37800000, v2
v_cndmask_b32_e32 v2, v2, v3, vcc_lo
v_cmp_class_f32_e64 vcc_lo, v4, 0x260
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v2, v2, v4, vcc_lo
v_cvt_i32_f32_e32 v4, v2
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b16 v[2:3], v4, off
global_store_b16 v[0:1], v7, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z18calculate_atan2_cuPsS_S_S_S_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 312
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 14
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z18calculate_atan2_cuPsS_S_S_S_S_i, .Lfunc_end0-_Z18calculate_atan2_cuPsS_S_S_S_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
- .offset: 48
.size: 4
.value_kind: by_value
- .offset: 56
.size: 4
.value_kind: hidden_block_count_x
- .offset: 60
.size: 4
.value_kind: hidden_block_count_y
- .offset: 64
.size: 4
.value_kind: hidden_block_count_z
- .offset: 68
.size: 2
.value_kind: hidden_group_size_x
- .offset: 70
.size: 2
.value_kind: hidden_group_size_y
- .offset: 72
.size: 2
.value_kind: hidden_group_size_z
- .offset: 74
.size: 2
.value_kind: hidden_remainder_x
- .offset: 76
.size: 2
.value_kind: hidden_remainder_y
- .offset: 78
.size: 2
.value_kind: hidden_remainder_z
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 112
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 120
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 312
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z18calculate_atan2_cuPsS_S_S_S_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z18calculate_atan2_cuPsS_S_S_S_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 14
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <math.h>
#include <fstream>
#include <array>
#include <hip/hip_runtime.h>
#include <iostream>
#include <assert.h>
using namespace std;
#define DEBUG
bool readFile(int16_t* read, const char* filePath);
bool saveFile(int16_t* write, const char* filePath);
float max_distance = 0;
int HEIGHT = 240;
int WIDTH = 288;
timespec diff(timespec start, timespec end)
{
timespec temp;
if ((end.tv_nsec-start.tv_nsec)<0) {
temp.tv_sec = end.tv_sec-start.tv_sec-1;
temp.tv_nsec = 1000000000+end.tv_nsec-start.tv_nsec;
} else {
temp.tv_sec = end.tv_sec-start.tv_sec;
temp.tv_nsec = end.tv_nsec-start.tv_nsec;
}
return temp;
}
inline
hipError_t checkCuda(hipError_t result)
{
#if defined(DEBUG) || defined(_DEBUG)
if (result != hipSuccess) {
fprintf(stderr, "CUDA Runtime Error: %s\n", hipGetErrorString(result));
assert(result == hipSuccess);
}
#endif
return result;
}
__global__
void calculate_atan2_cu(int16_t* phase1_cu, int16_t* phase2_cu,
int16_t* phase3_cu, int16_t* phase4_cu,
int16_t* depth_out_cu, int16_t* confidence_out_cu,int N){
const int index = blockIdx.x*blockDim.x + threadIdx.x;
if(index < N){
int16_t phase_1 = *(phase1_cu + index);
int16_t phase_2 = *(phase2_cu + index);
int16_t phase_3 = *(phase3_cu + index);
int16_t phase_4 = *(phase4_cu + index);
//printf("%d,%d,%d,%d\n",phase_1,phase_2,phase_3,phase_4);
auto phase1_t = phase_1 >> 4;
auto phase2_t = phase_2 >> 4;
auto phase3_t = phase_3 >> 4;
auto phase4_t = phase_4 >> 4;
int16_t I = phase1_t - phase3_t;
int16_t Q = phase2_t - phase4_t;
int out_index = index;
confidence_out_cu[out_index] = sqrt(float(I*I + Q*Q));
//printf("rsqrt(%d) confidence_out_cu[%d]=%d",I*I+Q*Q,index,confidence_out_cu[index]);
float angle = atan(-(float)Q/(float)I);
depth_out_cu[out_index] = (angle + M_PI) * 3.7474 * 1000 / (2 * M_PI);
}
}
int main(int argc, char *argv[])
{
const char *path=NULL;
printf("\n");
printf("Usage: %s relative-path-for-phase-data\n",argv[0]);
printf("depth_cu and confidence2_cu are put in the same path with %s\n",argv[0]);
printf("****Be noticed that the calculation will be done for 1000 times****\n");
printf("If you want to profile %s, try ",argv[0]);
printf("sudo /usr/local/cuda/bin/nvprof %s\n",argv[0]);
printf("otherwise, just run %s\n",argv[0]);
printf("\n");
if(argc == 1){
printf("Now loading phase data from ./data/originalData/\n");
path = "./data/originalData/";
}
else{
printf("now loading phase data from %s\n",argv[1]);
path = argv[1];
}
const int nStreams = 4;
timespec time1, time2;
hipStream_t stream[nStreams];
for (int i = 0; i < nStreams; ++i)
checkCuda( hipStreamCreate(&stream[i]) );
hipEvent_t startEvent, stopEvent, dummyEvent;
checkCuda( hipEventCreate(&startEvent) );
checkCuda( hipEventCreate(&stopEvent) );
checkCuda( hipEventCreate(&dummyEvent) );
int fmod = 40;
max_distance = 0.5*299792458/(double)fmod/1000;
int16_t* phase1;
int16_t* phase2;
int16_t* phase3;
int16_t* phase4;
int16_t* depth1_out;
int16_t* confidence1_out;
#ifndef PINNED
phase1 = new int16_t[WIDTH*HEIGHT];
phase2 = new int16_t[WIDTH*HEIGHT];
phase3 = new int16_t[WIDTH*HEIGHT];
phase4 = new int16_t[WIDTH*HEIGHT];
depth1_out = new int16_t[WIDTH*HEIGHT];
confidence1_out = new int16_t[WIDTH*HEIGHT];
#else
checkCuda( hipHostMalloc((void**)&phase1, sizeof(int16_t)*WIDTH*HEIGHT, hipHostMallocDefault) ); // host pinned
checkCuda( hipHostMalloc((void**)&phase2, sizeof(int16_t)*WIDTH*HEIGHT, hipHostMallocDefault) ); // host pinned
checkCuda( hipHostMalloc((void**)&phase3, sizeof(int16_t)*WIDTH*HEIGHT, hipHostMallocDefault) ); // host pinned
checkCuda( hipHostMalloc((void**)&phase4, sizeof(int16_t)*WIDTH*HEIGHT, hipHostMallocDefault) ); // host pinned
checkCuda( hipHostMalloc((void**)&depth1_out, sizeof(int16_t)* WIDTH*HEIGHT, hipHostMallocDefault) ); // host pinned
checkCuda( hipHostMalloc((void**)&confidence1_out, sizeof(int16_t)* WIDTH*HEIGHT, hipHostMallocDefault) ); // host pinned
#endif
int16_t *phase1_cu[nStreams],*phase2_cu[nStreams],*phase3_cu[nStreams],*phase4_cu[nStreams],*depth1_out_cu[nStreams],*confidence1_out_cu[nStreams];
for(int i=0;i<nStreams;i++){
checkCuda(hipMalloc((void**)&phase1_cu[i], sizeof(int16_t) * WIDTH * HEIGHT));
checkCuda(hipMalloc((void**)&phase2_cu[i], sizeof(int16_t) * WIDTH * HEIGHT));
checkCuda(hipMalloc((void**)&phase3_cu[i], sizeof(int16_t) * WIDTH * HEIGHT));
checkCuda(hipMalloc((void**)&phase4_cu[i], sizeof(int16_t) * WIDTH * HEIGHT));
checkCuda(hipMalloc((void**)&depth1_out_cu[i], sizeof(int16_t) * WIDTH * HEIGHT));
checkCuda(hipMalloc((void**)&confidence1_out_cu[i], sizeof(int16_t) * WIDTH * HEIGHT));
}
char *file = new char[ strlen(path)+ 10];
memset(file,0,strlen(path)+ 10);
strcat(file,path);
if(!readFile(phase1, strcat(file,"phase0")) || (*(file+strlen(path)) = '\0')||
!readFile(phase2, strcat(file,"phase90")) ||(*(file+strlen(path)) = '\0')||
!readFile(phase3, strcat(file,"phase180")) ||(*(file+strlen(path)) = '\0')||
!readFile(phase4, strcat(file,"phase270")) )
{
printf("read failed!\n");
return 0;
}
printf("calculation is started\n");
float ms; // elapsed time in milliseconds
#ifdef STREAM
checkCuda( hipEventRecord(startEvent,stream[nStreams-1]) );
clock_gettime(CLOCK_MONOTONIC, &time1);
for(int i=0;i<1000;i+=nStreams){
// Transfer data from host to device memory
for(int j=0;j<nStreams;j++){
checkCuda(hipMemcpyAsync(phase1_cu[j],phase1, sizeof(int16_t) * WIDTH * HEIGHT, hipMemcpyHostToDevice,stream[j]));
checkCuda(hipMemcpyAsync(phase2_cu[j],phase2, sizeof(int16_t) * WIDTH * HEIGHT, hipMemcpyHostToDevice,stream[j]));
checkCuda(hipMemcpyAsync(phase3_cu[j],phase3, sizeof(int16_t) * WIDTH * HEIGHT, hipMemcpyHostToDevice,stream[j]));
checkCuda(hipMemcpyAsync(phase4_cu[j],phase4, sizeof(int16_t) * WIDTH * HEIGHT, hipMemcpyHostToDevice,stream[j]));
}
for(int j=0;j<nStreams;j++){
calculate_atan2_cu<<<540,128,0,stream[j]>>>(phase1_cu[j],phase2_cu[j],phase3_cu[j],phase4_cu[j],depth1_out_cu[j],confidence1_out_cu[j], WIDTH*HEIGHT);
}
for(int j=0;j<nStreams;j++){
checkCuda(hipMemcpyAsync(depth1_out, depth1_out_cu[j],sizeof(int16_t) * WIDTH * HEIGHT, hipMemcpyDeviceToHost,stream[j]));
checkCuda(hipMemcpyAsync(confidence1_out,confidence1_out_cu[j], sizeof(int16_t) * WIDTH * HEIGHT, hipMemcpyDeviceToHost,stream[j]));
}
}
checkCuda( hipEventRecord(stopEvent, stream[nStreams-1]) );
checkCuda( hipEventSynchronize(stopEvent) );
checkCuda( hipEventElapsedTime(&ms, startEvent, stopEvent) );
hipDeviceSynchronize();
clock_gettime(CLOCK_MONOTONIC, &time2);
printf("Time for multiple stream transfer and execute (ms): %f ", ms);
cout<<diff(time1,time2).tv_sec<<":"<<diff(time1,time2).tv_nsec<<endl;
printf("stream with %d calculation is done\n",nStreams);
#endif
#ifdef NULLSTREAM
clock_gettime(CLOCK_MONOTONIC, &time1);
checkCuda( hipEventRecord(startEvent,0) );
for(int i=0;i<1000;i++){
// Transfer data from host to device memory
hipMemcpy(phase1_cu[0],phase1, sizeof(int16_t) * WIDTH * HEIGHT, hipMemcpyHostToDevice);
hipMemcpy(phase2_cu[0],phase2, sizeof(int16_t) * WIDTH * HEIGHT, hipMemcpyHostToDevice);
hipMemcpy(phase3_cu[0],phase3, sizeof(int16_t) * WIDTH * HEIGHT, hipMemcpyHostToDevice);
hipMemcpy(phase4_cu[0],phase4, sizeof(int16_t) * WIDTH * HEIGHT, hipMemcpyHostToDevice);
calculate_atan2_cu<<<540,128>>>(phase1_cu[0],phase2_cu[0],phase3_cu[0],phase4_cu[0],depth1_out_cu[0],confidence1_out_cu[0], WIDTH*HEIGHT);
hipMemcpy(depth1_out, depth1_out_cu[0],sizeof(int16_t) * WIDTH * HEIGHT, hipMemcpyDeviceToHost);
hipMemcpy(confidence1_out,confidence1_out_cu[0], sizeof(int16_t) * WIDTH * HEIGHT, hipMemcpyDeviceToHost);
}
checkCuda( hipEventRecord(stopEvent, 0) );
checkCuda( hipEventSynchronize(stopEvent) );
checkCuda( hipEventElapsedTime(&ms, startEvent, stopEvent) );
hipDeviceSynchronize();
clock_gettime(CLOCK_MONOTONIC, &time2);
printf("Time for NULL stream transfer and execute (ms): %f ", ms);
cout<<diff(time1,time2).tv_sec<<":"<<diff(time1,time2).tv_nsec<<endl;
#endif
printf("Calculation is done and saving depth and confidence!\n");
saveFile(depth1_out, "depth_cu");
saveFile(confidence1_out, "confidence2_cu");
printf("\n");
return 0;
}
bool readFile(int16_t* read, const char* filePath)
{
// printf("filePath=%s\n",filePath);
std::ifstream infile;
infile.open(filePath);
if(!infile)
{
printf("can not open file :%s\n",filePath);
return false;
}
while(!infile.eof())
{
infile>>*read;
read++;
}
infile.close();
return true;
}
bool saveFile(int16_t* write, const char* filePath)
{
std::ofstream fout(filePath);
for(auto j=0; j < HEIGHT; ++j)
{
for(auto i =0; i < WIDTH; i++)
{
fout << write[j*WIDTH+i] << "\t" ;
}
fout << "\n";
}
fout.close();
} | .text
.file "main.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z4diff8timespecS_ # -- Begin function _Z4diff8timespecS_
.p2align 4, 0x90
.type _Z4diff8timespecS_,@function
_Z4diff8timespecS_: # @_Z4diff8timespecS_
.cfi_startproc
# %bb.0:
movq %rdx, %r8
movq %rdi, %rax
movq %rcx, %rdx
subq %rsi, %rdx
js .LBB0_1
# %bb.2:
subq %rax, %r8
movq %r8, %rax
retq
.LBB0_1:
notq %rax
addq %r8, %rax
subq %rsi, %rcx
addq $1000000000, %rcx # imm = 0x3B9ACA00
movq %rcx, %rdx
retq
.Lfunc_end0:
.size _Z4diff8timespecS_, .Lfunc_end0-_Z4diff8timespecS_
.cfi_endproc
# -- End function
.globl _Z33__device_stub__calculate_atan2_cuPsS_S_S_S_S_i # -- Begin function _Z33__device_stub__calculate_atan2_cuPsS_S_S_S_S_i
.p2align 4, 0x90
.type _Z33__device_stub__calculate_atan2_cuPsS_S_S_S_S_i,@function
_Z33__device_stub__calculate_atan2_cuPsS_S_S_S_S_i: # @_Z33__device_stub__calculate_atan2_cuPsS_S_S_S_S_i
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
movq %r9, 48(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 160(%rsp), %rax
movq %rax, 144(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z18calculate_atan2_cuPsS_S_S_S_S_i, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end1:
.size _Z33__device_stub__calculate_atan2_cuPsS_S_S_S_S_i, .Lfunc_end1-_Z33__device_stub__calculate_atan2_cuPsS_S_S_S_S_i
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $280, %rsp # imm = 0x118
.cfi_def_cfa_offset 336
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %rbx
movl %edi, %ebp
movl $10, %edi
callq putchar@PLT
movq (%rbx), %rsi
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
movq (%rbx), %rsi
movl $.L.str.2, %edi
xorl %eax, %eax
callq printf
movl $.Lstr, %edi
callq puts@PLT
movq (%rbx), %rsi
movl $.L.str.4, %edi
xorl %eax, %eax
callq printf
movq (%rbx), %rsi
movl $.L.str.5, %edi
xorl %eax, %eax
callq printf
movq (%rbx), %rsi
movl $.L.str.6, %edi
xorl %eax, %eax
callq printf
movl $10, %edi
callq putchar@PLT
cmpl $1, %ebp
jne .LBB2_2
# %bb.1:
movl $.Lstr.1, %edi
callq puts@PLT
movl $.L.str.8, %ebx
jmp .LBB2_3
.LBB2_2:
movq 8(%rbx), %rsi
movl $.L.str.9, %edi
xorl %eax, %eax
callq printf
movq 8(%rbx), %rbx
.LBB2_3:
xorl %r15d, %r15d
jmp .LBB2_4
.p2align 4, 0x90
.LBB2_6: # %_Z9checkCuda10hipError_t.exit61
# in Loop: Header=BB2_4 Depth=1
addq $8, %r15
cmpq $32, %r15
je .LBB2_7
.LBB2_4: # =>This Inner Loop Header: Depth=1
leaq (%rsp,%r15), %rdi
addq $240, %rdi
callq hipStreamCreate
testl %eax, %eax
je .LBB2_6
# %bb.5: # in Loop: Header=BB2_4 Depth=1
movq stderr(%rip), %r14
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.21, %esi
movq %r14, %rdi
movq %rax, %rdx
xorl %eax, %eax
callq fprintf
jmp .LBB2_6
.LBB2_7:
leaq 40(%rsp), %rdi
callq hipEventCreate
testl %eax, %eax
jne .LBB2_8
.LBB2_9: # %_Z9checkCuda10hipError_t.exit
leaq 32(%rsp), %rdi
callq hipEventCreate
testl %eax, %eax
jne .LBB2_10
.LBB2_11: # %_Z9checkCuda10hipError_t.exit57
leaq 24(%rsp), %rdi
callq hipEventCreate
testl %eax, %eax
jne .LBB2_12
.LBB2_13: # %_Z9checkCuda10hipError_t.exit59
movl $1164588670, max_distance(%rip) # imm = 0x456A367E
movslq WIDTH(%rip), %rax
movslq HEIGHT(%rip), %rcx
imulq %rax, %rcx
movq %rcx, %rax
addq %rcx, %rax
testl %ecx, %ecx
movq $-1, %r14
cmovnsq %rax, %r14
movq %r14, %rdi
callq _Znam
movq %rax, %rbp
movq %r14, %rdi
callq _Znam
movq %rax, %r13
movq %r14, %rdi
callq _Znam
movq %rax, %r12
movq %r14, %rdi
callq _Znam
movq %rax, 16(%rsp) # 8-byte Spill
movq %r14, %rdi
callq _Znam
movq %rax, 8(%rsp) # 8-byte Spill
xorl %r15d, %r15d
jmp .LBB2_14
.p2align 4, 0x90
.LBB2_26: # %_Z9checkCuda10hipError_t.exit73
# in Loop: Header=BB2_14 Depth=1
addq $8, %r15
cmpq $32, %r15
je .LBB2_27
.LBB2_14: # =>This Inner Loop Header: Depth=1
leaq (%rsp,%r15), %rdi
addq $208, %rdi
movslq WIDTH(%rip), %rax
movslq HEIGHT(%rip), %rsi
imulq %rax, %rsi
addq %rsi, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB2_15
.LBB2_16: # %_Z9checkCuda10hipError_t.exit63
# in Loop: Header=BB2_14 Depth=1
leaq (%rsp,%r15), %rdi
addq $176, %rdi
movslq WIDTH(%rip), %rax
movslq HEIGHT(%rip), %rsi
imulq %rax, %rsi
addq %rsi, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB2_17
.LBB2_18: # %_Z9checkCuda10hipError_t.exit65
# in Loop: Header=BB2_14 Depth=1
leaq (%rsp,%r15), %rdi
addq $144, %rdi
movslq WIDTH(%rip), %rax
movslq HEIGHT(%rip), %rsi
imulq %rax, %rsi
addq %rsi, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB2_19
.LBB2_20: # %_Z9checkCuda10hipError_t.exit67
# in Loop: Header=BB2_14 Depth=1
leaq (%rsp,%r15), %rdi
addq $112, %rdi
movslq WIDTH(%rip), %rax
movslq HEIGHT(%rip), %rsi
imulq %rax, %rsi
addq %rsi, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB2_21
.LBB2_22: # %_Z9checkCuda10hipError_t.exit69
# in Loop: Header=BB2_14 Depth=1
leaq (%rsp,%r15), %rdi
addq $80, %rdi
movslq WIDTH(%rip), %rax
movslq HEIGHT(%rip), %rsi
imulq %rax, %rsi
addq %rsi, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB2_23
.LBB2_24: # %_Z9checkCuda10hipError_t.exit71
# in Loop: Header=BB2_14 Depth=1
leaq (%rsp,%r15), %rdi
addq $48, %rdi
movslq WIDTH(%rip), %rax
movslq HEIGHT(%rip), %rsi
imulq %rax, %rsi
addq %rsi, %rsi
callq hipMalloc
testl %eax, %eax
je .LBB2_26
# %bb.25: # in Loop: Header=BB2_14 Depth=1
movq stderr(%rip), %r14
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.21, %esi
movq %r14, %rdi
movq %rax, %rdx
xorl %eax, %eax
callq fprintf
jmp .LBB2_26
.LBB2_15: # in Loop: Header=BB2_14 Depth=1
movq stderr(%rip), %r14
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.21, %esi
movq %r14, %rdi
movq %rax, %rdx
xorl %eax, %eax
callq fprintf
jmp .LBB2_16
.LBB2_17: # in Loop: Header=BB2_14 Depth=1
movq stderr(%rip), %r14
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.21, %esi
movq %r14, %rdi
movq %rax, %rdx
xorl %eax, %eax
callq fprintf
jmp .LBB2_18
.LBB2_19: # in Loop: Header=BB2_14 Depth=1
movq stderr(%rip), %r14
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.21, %esi
movq %r14, %rdi
movq %rax, %rdx
xorl %eax, %eax
callq fprintf
jmp .LBB2_20
.LBB2_21: # in Loop: Header=BB2_14 Depth=1
movq stderr(%rip), %r14
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.21, %esi
movq %r14, %rdi
movq %rax, %rdx
xorl %eax, %eax
callq fprintf
jmp .LBB2_22
.LBB2_23: # in Loop: Header=BB2_14 Depth=1
movq stderr(%rip), %r14
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.21, %esi
movq %r14, %rdi
movq %rax, %rdx
xorl %eax, %eax
callq fprintf
jmp .LBB2_24
.LBB2_27:
movq %rbx, %rdi
callq strlen
leaq 10(%rax), %rdi
callq _Znam
movq %rax, %r14
movq %rbx, %rdi
callq strlen
leaq 10(%rax), %rdx
movq %r14, %rdi
xorl %esi, %esi
callq memset@PLT
movq %r14, %rdi
movq %rbx, %rsi
callq strcat
movq %r14, %rdi
callq strlen
movl $1935763568, (%r14,%rax) # imm = 0x73616870
movl $3171699, 3(%r14,%rax) # imm = 0x306573
movq %rbp, %rdi
movq %r14, %rsi
callq _Z8readFilePsPKc
testb %al, %al
je .LBB2_31
# %bb.28:
movq %rbx, %rdi
callq strlen
movb $0, (%r14,%rax)
movq %r14, %rdi
callq strlen
movabsq $13573906772355184, %rcx # imm = 0x30396573616870
movq %rcx, (%r14,%rax)
movq %r13, %rdi
movq %r14, %rsi
callq _Z8readFilePsPKc
testb %al, %al
je .LBB2_31
# %bb.29:
movq %rbx, %rdi
callq strlen
movb $0, (%r14,%rax)
movq %r14, %rdi
callq strlen
movabsq $3474581424313559152, %rcx # imm = 0x3038316573616870
movq %rcx, (%r14,%rax)
movb $0, 8(%r14,%rax)
movq %r12, %rdi
movq %r14, %rsi
callq _Z8readFilePsPKc
testb %al, %al
je .LBB2_31
# %bb.30:
movq %rbx, %rdi
callq strlen
movb $0, (%r14,%rax)
movq %r14, %rdi
callq strlen
movabsq $3474301048848476272, %rcx # imm = 0x3037326573616870
movq %rcx, (%r14,%rax)
movb $0, 8(%r14,%rax)
movq 16(%rsp), %rdi # 8-byte Reload
movq %r14, %rsi
callq _Z8readFilePsPKc
testb %al, %al
jne .LBB2_32
.LBB2_31:
movl $.Lstr.2, %edi
callq puts@PLT
xorl %eax, %eax
addq $280, %rsp # imm = 0x118
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB2_8:
.cfi_def_cfa_offset 336
movq stderr(%rip), %r14
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.21, %esi
movq %r14, %rdi
movq %rax, %rdx
xorl %eax, %eax
callq fprintf
jmp .LBB2_9
.LBB2_10:
movq stderr(%rip), %r14
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.21, %esi
movq %r14, %rdi
movq %rax, %rdx
xorl %eax, %eax
callq fprintf
jmp .LBB2_11
.LBB2_12:
movq stderr(%rip), %r14
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.21, %esi
movq %r14, %rdi
movq %rax, %rdx
xorl %eax, %eax
callq fprintf
jmp .LBB2_13
.LBB2_32:
movl $.Lstr.3, %edi
callq puts@PLT
movl $.Lstr.4, %edi
callq puts@PLT
movl $.L.str.17, %esi
movq 8(%rsp), %rdi # 8-byte Reload
callq _Z8saveFilePsPKc
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.globl _Z8readFilePsPKc # -- Begin function _Z8readFilePsPKc
.p2align 4, 0x90
.type _Z8readFilePsPKc,@function
_Z8readFilePsPKc: # @_Z8readFilePsPKc
.Lfunc_begin0:
.cfi_startproc
.cfi_personality 3, __gxx_personality_v0
.cfi_lsda 3, .Lexception0
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $528, %rsp # imm = 0x210
.cfi_def_cfa_offset 576
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %r15
movq %rdi, %rbx
leaq 8(%rsp), %r12
movq %r12, %rdi
callq _ZNSt14basic_ifstreamIcSt11char_traitsIcEEC1Ev
leaq 24(%rsp), %r14
.Ltmp0:
movq %r14, %rdi
movq %r15, %rsi
movl $8, %edx
callq _ZNSt13basic_filebufIcSt11char_traitsIcEE4openEPKcSt13_Ios_Openmode
.Ltmp1:
# %bb.1: # %.noexc
movq 8(%rsp), %rcx
addq -24(%rcx), %r12
xorl %esi, %esi
testq %rax, %rax
jne .LBB3_3
# %bb.2:
movl 32(%r12), %esi
orl $4, %esi
.LBB3_3: # %.invoke
.Ltmp2:
movq %r12, %rdi
callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate
.Ltmp3:
# %bb.4: # %_ZNSt14basic_ifstreamIcSt11char_traitsIcEE4openEPKcSt13_Ios_Openmode.exit
movq 8(%rsp), %rax
movq -24(%rax), %rax
movl 40(%rsp,%rax), %ebp
testb $5, %bpl
je .LBB3_5
# %bb.12:
movl $.L.str.19, %edi
movq %r15, %rsi
xorl %eax, %eax
callq printf
jmp .LBB3_13
.LBB3_5: # %.preheader
movq 8(%rsp), %rax
movq -24(%rax), %rax
testb $2, 40(%rsp,%rax)
jne .LBB3_9
# %bb.6:
leaq 8(%rsp), %r15
.p2align 4, 0x90
.LBB3_7: # %.lr.ph
# =>This Inner Loop Header: Depth=1
.Ltmp4:
movq %r15, %rdi
movq %rbx, %rsi
callq _ZNSirsERs
.Ltmp5:
# %bb.8: # in Loop: Header=BB3_7 Depth=1
addq $2, %rbx
movq 8(%rsp), %rax
movq -24(%rax), %rax
testb $2, 40(%rsp,%rax)
je .LBB3_7
.LBB3_9: # %._crit_edge
.Ltmp7:
movq %r14, %rdi
callq _ZNSt13basic_filebufIcSt11char_traitsIcEE5closeEv
.Ltmp8:
# %bb.10: # %.noexc10
testq %rax, %rax
jne .LBB3_13
# %bb.11:
movq 8(%rsp), %rax
movq -24(%rax), %rax
leaq (%rsp,%rax), %rdi
addq $8, %rdi
movl 40(%rsp,%rax), %esi
orl $4, %esi
.Ltmp9:
callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate
.Ltmp10:
.LBB3_13: # %_ZNSt14basic_ifstreamIcSt11char_traitsIcEE5closeEv.exit
testb $5, %bpl
sete %bl
leaq 8(%rsp), %rdi
movl $_ZTTSt14basic_ifstreamIcSt11char_traitsIcEE, %esi
callq _ZNSt14basic_ifstreamIcSt11char_traitsIcEED2Ev
leaq 264(%rsp), %rdi
callq _ZNSt8ios_baseD2Ev
movl %ebx, %eax
addq $528, %rsp # imm = 0x210
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB3_15: # %.loopexit.split-lp
.cfi_def_cfa_offset 576
.Ltmp11:
jmp .LBB3_16
.LBB3_14: # %.loopexit
.Ltmp6:
.LBB3_16:
movq %rax, %rbx
leaq 8(%rsp), %rdi
movl $_ZTTSt14basic_ifstreamIcSt11char_traitsIcEE, %esi
callq _ZNSt14basic_ifstreamIcSt11char_traitsIcEED2Ev
leaq 264(%rsp), %rdi
callq _ZNSt8ios_baseD2Ev
movq %rbx, %rdi
callq _Unwind_Resume@PLT
.Lfunc_end3:
.size _Z8readFilePsPKc, .Lfunc_end3-_Z8readFilePsPKc
.cfi_endproc
.section .gcc_except_table,"a",@progbits
.p2align 2, 0x0
GCC_except_table3:
.Lexception0:
.byte 255 # @LPStart Encoding = omit
.byte 255 # @TType Encoding = omit
.byte 1 # Call site Encoding = uleb128
.uleb128 .Lcst_end0-.Lcst_begin0
.Lcst_begin0:
.uleb128 .Lfunc_begin0-.Lfunc_begin0 # >> Call Site 1 <<
.uleb128 .Ltmp0-.Lfunc_begin0 # Call between .Lfunc_begin0 and .Ltmp0
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp0-.Lfunc_begin0 # >> Call Site 2 <<
.uleb128 .Ltmp3-.Ltmp0 # Call between .Ltmp0 and .Ltmp3
.uleb128 .Ltmp11-.Lfunc_begin0 # jumps to .Ltmp11
.byte 0 # On action: cleanup
.uleb128 .Ltmp4-.Lfunc_begin0 # >> Call Site 3 <<
.uleb128 .Ltmp5-.Ltmp4 # Call between .Ltmp4 and .Ltmp5
.uleb128 .Ltmp6-.Lfunc_begin0 # jumps to .Ltmp6
.byte 0 # On action: cleanup
.uleb128 .Ltmp7-.Lfunc_begin0 # >> Call Site 4 <<
.uleb128 .Ltmp10-.Ltmp7 # Call between .Ltmp7 and .Ltmp10
.uleb128 .Ltmp11-.Lfunc_begin0 # jumps to .Ltmp11
.byte 0 # On action: cleanup
.uleb128 .Ltmp10-.Lfunc_begin0 # >> Call Site 5 <<
.uleb128 .Lfunc_end3-.Ltmp10 # Call between .Ltmp10 and .Lfunc_end3
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.Lcst_end0:
.p2align 2, 0x0
# -- End function
.text
.globl _Z8saveFilePsPKc # -- Begin function _Z8saveFilePsPKc
.p2align 4, 0x90
.type _Z8saveFilePsPKc,@function
_Z8saveFilePsPKc: # @_Z8saveFilePsPKc
.Lfunc_begin1:
.cfi_startproc
.cfi_personality 3, __gxx_personality_v0
.cfi_lsda 3, .Lexception1
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $520, %rsp # imm = 0x208
.cfi_def_cfa_offset 560
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdi, %rbx
leaq 8(%rsp), %rdi
movl $16, %edx
callq _ZNSt14basic_ofstreamIcSt11char_traitsIcEEC1EPKcSt13_Ios_Openmode
cmpl $0, HEIGHT(%rip)
jle .LBB4_9
# %bb.1: # %.preheader.preheader
xorl %r15d, %r15d
leaq 8(%rsp), %r14
.p2align 4, 0x90
.LBB4_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB4_4 Depth 2
movl WIDTH(%rip), %eax
testl %eax, %eax
jle .LBB4_7
# %bb.3: # %.lr.ph.preheader
# in Loop: Header=BB4_2 Depth=1
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB4_4: # %.lr.ph
# Parent Loop BB4_2 Depth=1
# => This Inner Loop Header: Depth=2
imull %r15d, %eax
cltq
addq %r12, %rax
movswl (%rbx,%rax,2), %esi
.Ltmp12:
movq %r14, %rdi
callq _ZNSolsEs
.Ltmp13:
# %bb.5: # in Loop: Header=BB4_4 Depth=2
.Ltmp14:
movl $.L.str.20, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp15:
# %bb.6: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit16
# in Loop: Header=BB4_4 Depth=2
movl WIDTH(%rip), %eax
incq %r12
cmpl %eax, %r12d
jl .LBB4_4
.LBB4_7: # %._crit_edge
# in Loop: Header=BB4_2 Depth=1
.Ltmp17:
movl $.L.str, %esi
movl $1, %edx
movq %r14, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp18:
# %bb.8: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit
# in Loop: Header=BB4_2 Depth=1
incl %r15d
cmpl HEIGHT(%rip), %r15d
jl .LBB4_2
.LBB4_9: # %._crit_edge19
.Ltmp20:
leaq 8(%rsp), %rdi
callq _ZNSt14basic_ofstreamIcSt11char_traitsIcEE5closeEv
.Ltmp21:
# %bb.10:
.LBB4_14:
.Ltmp19:
jmp .LBB4_12
.LBB4_13:
.Ltmp16:
jmp .LBB4_12
.LBB4_11:
.Ltmp22:
.LBB4_12:
movq %rax, %rbx
leaq 8(%rsp), %rdi
callq _ZNSt14basic_ofstreamIcSt11char_traitsIcEED1Ev
movq %rbx, %rdi
callq _Unwind_Resume@PLT
.Lfunc_end4:
.size _Z8saveFilePsPKc, .Lfunc_end4-_Z8saveFilePsPKc
.cfi_endproc
.section .gcc_except_table,"a",@progbits
.p2align 2, 0x0
GCC_except_table4:
.Lexception1:
.byte 255 # @LPStart Encoding = omit
.byte 255 # @TType Encoding = omit
.byte 1 # Call site Encoding = uleb128
.uleb128 .Lcst_end1-.Lcst_begin1
.Lcst_begin1:
.uleb128 .Lfunc_begin1-.Lfunc_begin1 # >> Call Site 1 <<
.uleb128 .Ltmp12-.Lfunc_begin1 # Call between .Lfunc_begin1 and .Ltmp12
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp12-.Lfunc_begin1 # >> Call Site 2 <<
.uleb128 .Ltmp15-.Ltmp12 # Call between .Ltmp12 and .Ltmp15
.uleb128 .Ltmp16-.Lfunc_begin1 # jumps to .Ltmp16
.byte 0 # On action: cleanup
.uleb128 .Ltmp17-.Lfunc_begin1 # >> Call Site 3 <<
.uleb128 .Ltmp18-.Ltmp17 # Call between .Ltmp17 and .Ltmp18
.uleb128 .Ltmp19-.Lfunc_begin1 # jumps to .Ltmp19
.byte 0 # On action: cleanup
.uleb128 .Ltmp20-.Lfunc_begin1 # >> Call Site 4 <<
.uleb128 .Ltmp21-.Ltmp20 # Call between .Ltmp20 and .Ltmp21
.uleb128 .Ltmp22-.Lfunc_begin1 # jumps to .Ltmp22
.byte 0 # On action: cleanup
.uleb128 .Ltmp21-.Lfunc_begin1 # >> Call Site 5 <<
.uleb128 .Lfunc_end4-.Ltmp21 # Call between .Ltmp21 and .Lfunc_end4
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.Lcst_end1:
.p2align 2, 0x0
# -- End function
.text
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z18calculate_atan2_cuPsS_S_S_S_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type max_distance,@object # @max_distance
.bss
.globl max_distance
.p2align 2, 0x0
max_distance:
.long 0x00000000 # float 0
.size max_distance, 4
.type HEIGHT,@object # @HEIGHT
.data
.globl HEIGHT
.p2align 2, 0x0
HEIGHT:
.long 240 # 0xf0
.size HEIGHT, 4
.type WIDTH,@object # @WIDTH
.globl WIDTH
.p2align 2, 0x0
WIDTH:
.long 288 # 0x120
.size WIDTH, 4
.type _Z18calculate_atan2_cuPsS_S_S_S_S_i,@object # @_Z18calculate_atan2_cuPsS_S_S_S_S_i
.section .rodata,"a",@progbits
.globl _Z18calculate_atan2_cuPsS_S_S_S_S_i
.p2align 3, 0x0
_Z18calculate_atan2_cuPsS_S_S_S_S_i:
.quad _Z33__device_stub__calculate_atan2_cuPsS_S_S_S_S_i
.size _Z18calculate_atan2_cuPsS_S_S_S_S_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "\n"
.size .L.str, 2
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Usage: %s relative-path-for-phase-data\n"
.size .L.str.1, 40
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "depth_cu and confidence2_cu are put in the same path with %s\n"
.size .L.str.2, 62
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "If you want to profile %s, try "
.size .L.str.4, 32
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "sudo /usr/local/cuda/bin/nvprof %s\n"
.size .L.str.5, 36
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "otherwise, just run %s\n"
.size .L.str.6, 24
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "./data/originalData/"
.size .L.str.8, 21
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "now loading phase data from %s\n"
.size .L.str.9, 32
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "phase0"
.size .L.str.10, 7
.type .L.str.12,@object # @.str.12
.L.str.12:
.asciz "phase180"
.size .L.str.12, 9
.type .L.str.13,@object # @.str.13
.L.str.13:
.asciz "phase270"
.size .L.str.13, 9
.type .L.str.17,@object # @.str.17
.L.str.17:
.asciz "depth_cu"
.size .L.str.17, 9
.type .L.str.19,@object # @.str.19
.L.str.19:
.asciz "can not open file :%s\n"
.size .L.str.19, 23
.type .L.str.20,@object # @.str.20
.L.str.20:
.asciz "\t"
.size .L.str.20, 2
.type .L.str.21,@object # @.str.21
.L.str.21:
.asciz "CUDA Runtime Error: %s\n"
.size .L.str.21, 24
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z18calculate_atan2_cuPsS_S_S_S_S_i"
.size .L__unnamed_1, 36
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "****Be noticed that the calculation will be done for 1000 times****"
.size .Lstr, 68
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "Now loading phase data from ./data/originalData/"
.size .Lstr.1, 49
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "read failed!"
.size .Lstr.2, 13
.type .Lstr.3,@object # @str.3
.Lstr.3:
.asciz "calculation is started"
.size .Lstr.3, 23
.type .Lstr.4,@object # @str.4
.Lstr.4:
.asciz "Calculation is done and saving depth and confidence!"
.size .Lstr.4, 53
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z33__device_stub__calculate_atan2_cuPsS_S_S_S_S_i
.addrsig_sym __gxx_personality_v0
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Unwind_Resume
.addrsig_sym _Z18calculate_atan2_cuPsS_S_S_S_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <cuda.h>
#include <cuda_runtime.h>
#include "stdio.h"
#define TILE_SIZE 64
#define WARP_SIZE 32
extern "C" void CSR_matvec(int N, int nnz, int* start, int* indices, float* data, float* x, float *y, bool bVectorized);
extern "C" void CSR_create(int N, int nnz, int* start, int * indices, float * data , float * x , float * y, int** start_d, int **indices_d, float **data_d, float **x_d, float **y_d);
extern "C" void CSR_kernel(int N, int nnz, int* start_d, int * indices_d, float * data_d , float * x_d , float * y_d, bool bVectorized);
extern "C" void CSR_destroy(int* start_d, int* indices_d, float* data_d, float* x_d, float* y_d);
extern "C" void ELL_create(int N, int num_cols_per_row, int * indices, float * data , float * x , float * y, int **indices_d, float **data_d, float **x_d, float **y_d);
extern "C" void ELL_kernel(int N, int num_cols_per_row , int * indices_d, float * data_d , float * x_d , float * y_d);
extern "C" void ELL_destroy(int* indices_d, float* data_d, float* x_d, float* y_d);
extern "C" void band_create(int N, int num_cols_per_row, float * data , float * x , float * y, float **data_d, float **x_d, float **y_d);
extern "C" void band_kernel(int N, int num_cols_per_row , float * data_d , float * x_d , float * y_d);
extern "C" void band_destroy(float* data_d, float* x_d, float* y_d);
/**
* Custom CUDA error check wrapper.
*/
#define checkCUDAError() do { \
cudaError_t error = cudaGetLastError(); \
if (error != cudaSuccess) { \
printf("(CUDA) %s", cudaGetErrorString(error)); \
printf(" (" __FILE__ ":%d)\n", __LINE__); \
}\
} while (0)
/**
* Cuda kernel for: CSR_s(A)x = y
*/
__global__ void k_csr_mat_vec_mm(const int N, int *start, int* indices, float *data, float *x, float* y) {
int row = blockDim.x * blockIdx.x + threadIdx.x ;
if ( row < N ){
float dot = 0;
int row_start = start [ row ];
int row_end = start [ row+1];
for ( int jj = row_start ; jj < row_end ; jj ++) {
dot += data [ jj ] * x [ indices [ jj ]];
}
y[row] = dot ;
}
}
/**
* Cuda kernel for: CSR_v(A)x = y
*/
__global__ void k_csr2_mat_vec_mm(const int N, int *start, int* indices, float *data, float *x, float* y) {
__shared__ float vals[TILE_SIZE];
int thread_id = blockDim.x * blockIdx.x + threadIdx.x;
int warp_id = thread_id / WARP_SIZE;
int lane = thread_id & (WARP_SIZE - 1);
int row = warp_id;
if (row < N) {
int row_start = start[row];
int row_end = start[row + 1];
// compute running sum per thread
vals[threadIdx.x] = 0;
for (int jj = row_start + lane; jj < row_end; jj += WARP_SIZE) {
vals[threadIdx.x] += data[jj] * x[indices[jj]];
}
// parallel reduction in shared memory
for (int d = WARP_SIZE >> 1; d >= 1; d >>= 1) {
if (lane < d) vals[threadIdx.x] += vals[threadIdx.x + d];
}
// first thread in a warp writes the result
if (lane == 0) {
y[row] = vals[threadIdx.x];
}
}
}
/**
* Cuda kernel for: ELL(A)x = y
*/
__global__ void k_ell_mat_vec_mm ( const int N, const int num_cols_per_row , int * indices,
float * data , float * x , float * y ) {
int row = blockDim.x * blockIdx.x + threadIdx.x ;
if ( row < N ){
float dot = 0;
for ( int n = 0; n < num_cols_per_row ; n ++){
int col = indices [ N * n + row ];
float val = data [ N * n + row ];
if ( val != 0)
dot += val * x [ col ];
}
y [ row ] = dot ;
}
}
/**
* Cuda kernel for: Band(A)x = y
*/
__global__ void band_matvec(int N, int k_max,
float* a, float* x, float* y) {
int i = TILE_SIZE * blockIdx.x + threadIdx.x;
if (i < N) {
float dot = 0;
for (int k = 0; k < 2 * k_max + 1; k++) {
float val = a[N * k + i];
int j = i + k - k_max;
if (val != 0) dot += val * x[j];
}
y[i] = dot;
}
}
/**
* Perform: CSR(A)x = y
*/
void CSR_matvec(const int N, const int nnz, int* start, int * indices, float * data , float * x , float * y, const bool bVectorized) {
int *start_d, *indices_d;
float *data_d, *x_d, *y_d;
CSR_create(N, nnz, start, indices, data, x, y, &start_d, &indices_d, &data_d, &x_d, &y_d);
CSR_kernel(N, nnz, start_d, indices_d, data_d, x_d, y_d, bVectorized);
cudaMemcpy(y, y_d, N * sizeof(float), cudaMemcpyDeviceToHost);
checkCUDAError();
CSR_destroy(start_d, indices_d, data_d, x_d, y_d);
}
/**
* Create CSR matrix
*/
void CSR_create(const int N, const int nnz,
int * start, int * indices, float * data , float * x , float * y,
int ** start_d, int ** indices_d, float **data_d, float **x_d, float **y_d) {
/************************/
/* copy to device */
/************************/
cudaMalloc((void **) start_d, (N+1) * sizeof(int));
checkCUDAError();
cudaMemcpy(*start_d, start, (N+1) * sizeof(int), cudaMemcpyHostToDevice);
checkCUDAError();
cudaMalloc((void **) indices_d, nnz * sizeof(int));
checkCUDAError();
cudaMemcpy(*indices_d, indices, nnz * sizeof(int), cudaMemcpyHostToDevice);
checkCUDAError();
cudaMalloc((void **) data_d, nnz * sizeof(float));
checkCUDAError();
cudaMemcpy(*data_d, data, nnz * sizeof(float), cudaMemcpyHostToDevice);
checkCUDAError();
cudaMalloc((void **) x_d, N * sizeof(float));
checkCUDAError();
cudaMemcpy(*x_d, x, N * sizeof(float), cudaMemcpyHostToDevice);
checkCUDAError();
cudaMalloc((void **) y_d, N * sizeof(float));
checkCUDAError();
cudaMemcpy(*y_d, y, N * sizeof(float) , cudaMemcpyHostToDevice);
checkCUDAError();
}
/**
* Perform: CSR(A)x = y
*/
void CSR_kernel(const int N, const int nnz, int * start_d , int * indices_d, float * data_d , float * x_d , float * y_d, const bool bVectorized) {
if (bVectorized) {
//#threads = #rows * #threads per row (= N * WARP_SIZE)
dim3 grid((N * WARP_SIZE + TILE_SIZE - 1)/TILE_SIZE, 1, 1);
dim3 block(TILE_SIZE, 1, 1);
k_csr2_mat_vec_mm <<< grid, block >>> (N, start_d, indices_d, data_d, x_d, y_d);
} else {
//#threads = #rows (= N)
dim3 grid((N + TILE_SIZE - 1)/TILE_SIZE, 1, 1);
dim3 block(TILE_SIZE, 1, 1);
k_csr_mat_vec_mm <<< grid, block >>> (N, start_d, indices_d, data_d, x_d, y_d);
}
checkCUDAError();
}
/**
* Destroy CSR matrix
*/
void CSR_destroy(int* start_d, int* indices_d, float* data_d, float* x_d, float* y_d) {
cudaFree(start_d);
cudaFree(indices_d);
cudaFree(data_d);
cudaFree(x_d);
cudaFree(y_d);
}
/**
* Create band matrix
*/
void band_create(const int N, const int num_cols_per_row,
float * data , float * x , float * y,
float **data_d, float **x_d, float **y_d) {
cudaMalloc((void **) data_d, N * num_cols_per_row * sizeof(float));
checkCUDAError();
cudaMemcpy(*data_d, data, N * num_cols_per_row * sizeof(float), cudaMemcpyHostToDevice);
checkCUDAError();
cudaMalloc((void **) x_d, N * sizeof(float));
checkCUDAError();
cudaMemcpy(*x_d, x, N * sizeof(float), cudaMemcpyHostToDevice);
checkCUDAError();
cudaMalloc((void **) y_d, N * sizeof(float));
checkCUDAError();
cudaMemcpy(*y_d, y, N * sizeof(float), cudaMemcpyHostToDevice);
checkCUDAError();
}
/**
* Perform: band(A)x = y
*/
void band_kernel(int N, int k_max , float * data_d , float * x_d , float * y_d) {
//#threads = #rows (= N)
dim3 grid((N + TILE_SIZE - 1)/TILE_SIZE, 1, 1);
dim3 block(TILE_SIZE, 1, 1);
band_matvec <<< grid, block >>> (N, k_max, data_d , x_d, y_d);
checkCUDAError();
}
/**
* Destroy ELL matrix
*/
void band_destroy(float* data_d, float* x_d, float* y_d) {
cudaFree(data_d);
cudaFree(x_d);
cudaFree(y_d);
}
/**
* Create ELL matrix
*/
void ELL_create(const int N, const int num_cols_per_row,
int * indices, float * data , float * x , float * y,
int ** indices_d, float **data_d, float **x_d, float **y_d) {
cudaMalloc((void **) indices_d, N * num_cols_per_row * sizeof(int));
checkCUDAError();
cudaMemcpy(*indices_d, indices, N * num_cols_per_row * sizeof(int), cudaMemcpyHostToDevice);
checkCUDAError();
cudaMalloc((void **) data_d, N * num_cols_per_row * sizeof(float));
checkCUDAError();
cudaMemcpy(*data_d, data, N * num_cols_per_row * sizeof(float), cudaMemcpyHostToDevice);
checkCUDAError();
cudaMalloc((void **) x_d, N * sizeof(float));
checkCUDAError();
cudaMemcpy(*x_d, x, N * sizeof(float), cudaMemcpyHostToDevice);
checkCUDAError();
cudaMalloc((void **) y_d, N * sizeof(float));
checkCUDAError();
cudaMemcpy(*y_d, y, N * sizeof(float), cudaMemcpyHostToDevice);
checkCUDAError();
}
/**
* Perform: ELL(A)x = y
*/
void ELL_kernel(int N, int num_cols_per_row , int * indices_d, float * data_d , float * x_d , float * y_d) {
//round grid size N/TILE_SIZE up
dim3 grid((N + TILE_SIZE - 1)/TILE_SIZE, 1, 1);
dim3 block(TILE_SIZE, 1, 1);
k_ell_mat_vec_mm <<< grid, block >>> (N, num_cols_per_row, indices_d, data_d , x_d, y_d);
checkCUDAError();
}
/**
* Destroy ELL matrix
*/
void ELL_destroy(int* indices_d, float* data_d, float* x_d, float* y_d) {
cudaFree(indices_d);
cudaFree(data_d);
cudaFree(x_d);
cudaFree(y_d);
} | .file "tmpxft_000d00f3_00000000-6_kernels.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2069:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2069:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "(CUDA) %s"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string " (/home/ubuntu/Datasets/stackv2/train-structured/PhuNH/hpc-aa/master/t4/kernels.cu:%d)\n"
.text
.globl CSR_create
.type CSR_create, @function
CSR_create:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $8, %rsp
.cfi_def_cfa_offset 64
movl %esi, %ebp
movq %rdx, %r15
movq %rcx, %r14
movq %r8, %r13
movq %r9, %r12
leal 1(%rdi), %ebx
movslq %ebx, %rbx
salq $2, %rbx
movq %rbx, %rsi
movq 72(%rsp), %rdi
call cudaMalloc@PLT
call cudaGetLastError@PLT
testl %eax, %eax
jne .L15
.L4:
movq 72(%rsp), %rax
movq (%rax), %rdi
movl $1, %ecx
movq %rbx, %rdx
movq %r15, %rsi
call cudaMemcpy@PLT
call cudaGetLastError@PLT
testl %eax, %eax
jne .L16
.L5:
movslq %ebp, %rbp
salq $2, %rbp
movq %rbp, %rsi
movq 80(%rsp), %rdi
call cudaMalloc@PLT
call cudaGetLastError@PLT
testl %eax, %eax
jne .L17
.L6:
movq 80(%rsp), %rax
movq (%rax), %rdi
movl $1, %ecx
movq %rbp, %rdx
movq %r14, %rsi
call cudaMemcpy@PLT
call cudaGetLastError@PLT
testl %eax, %eax
jne .L18
.L7:
movq %rbp, %rsi
movq 88(%rsp), %rdi
call cudaMalloc@PLT
call cudaGetLastError@PLT
testl %eax, %eax
jne .L19
.L8:
movq 88(%rsp), %rax
movq (%rax), %rdi
movl $1, %ecx
movq %rbp, %rdx
movq %r13, %rsi
call cudaMemcpy@PLT
call cudaGetLastError@PLT
testl %eax, %eax
jne .L20
.L9:
subq $4, %rbx
movq %rbx, %rsi
movq 96(%rsp), %rdi
call cudaMalloc@PLT
call cudaGetLastError@PLT
testl %eax, %eax
jne .L21
.L10:
movq 96(%rsp), %rax
movq (%rax), %rdi
movl $1, %ecx
movq %rbx, %rdx
movq %r12, %rsi
call cudaMemcpy@PLT
call cudaGetLastError@PLT
testl %eax, %eax
jne .L22
.L11:
movq %rbx, %rsi
movq 104(%rsp), %rdi
call cudaMalloc@PLT
call cudaGetLastError@PLT
testl %eax, %eax
jne .L23
.L12:
movq 104(%rsp), %rax
movq (%rax), %rdi
movl $1, %ecx
movq %rbx, %rdx
movq 64(%rsp), %rsi
call cudaMemcpy@PLT
call cudaGetLastError@PLT
testl %eax, %eax
jne .L24
.L3:
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $156, %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L4
.L16:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $158, %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L5
.L17:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $161, %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L6
.L18:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $163, %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L7
.L19:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $166, %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L8
.L20:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $168, %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L9
.L21:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $171, %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L10
.L22:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $173, %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L11
.L23:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $176, %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L12
.L24:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $178, %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L3
.cfi_endproc
.LFE2058:
.size CSR_create, .-CSR_create
.globl CSR_destroy
.type CSR_destroy, @function
CSR_destroy:
.LFB2060:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $8, %rsp
.cfi_def_cfa_offset 48
movq %rsi, %r13
movq %rdx, %r12
movq %rcx, %rbp
movq %r8, %rbx
call cudaFree@PLT
movq %r13, %rdi
call cudaFree@PLT
movq %r12, %rdi
call cudaFree@PLT
movq %rbp, %rdi
call cudaFree@PLT
movq %rbx, %rdi
call cudaFree@PLT
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size CSR_destroy, .-CSR_destroy
.globl band_create
.type band_create, @function
band_create:
.LFB2061:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $8, %rsp
.cfi_def_cfa_offset 64
movl %edi, %ebx
movq %rdx, %r15
movq %rcx, %r14
movq %r8, %r13
movq %r9, %r12
imull %edi, %esi
movslq %esi, %rbp
salq $2, %rbp
movq %rbp, %rsi
movq %r9, %rdi
call cudaMalloc@PLT
call cudaGetLastError@PLT
testl %eax, %eax
jne .L35
.L28:
movq (%r12), %rdi
movl $1, %ecx
movq %rbp, %rdx
movq %r15, %rsi
call cudaMemcpy@PLT
call cudaGetLastError@PLT
testl %eax, %eax
jne .L36
.L29:
movslq %ebx, %rbx
salq $2, %rbx
movq %rbx, %rsi
movq 64(%rsp), %rdi
call cudaMalloc@PLT
call cudaGetLastError@PLT
testl %eax, %eax
jne .L37
.L30:
movq 64(%rsp), %rax
movq (%rax), %rdi
movl $1, %ecx
movq %rbx, %rdx
movq %r14, %rsi
call cudaMemcpy@PLT
call cudaGetLastError@PLT
testl %eax, %eax
jne .L38
.L31:
movq %rbx, %rsi
movq 72(%rsp), %rdi
call cudaMalloc@PLT
call cudaGetLastError@PLT
testl %eax, %eax
jne .L39
.L32:
movq 72(%rsp), %rax
movq (%rax), %rdi
movl $1, %ecx
movq %rbx, %rdx
movq %r13, %rsi
call cudaMemcpy@PLT
call cudaGetLastError@PLT
testl %eax, %eax
jne .L40
.L27:
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L35:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $221, %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L28
.L36:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $223, %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L29
.L37:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $226, %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L30
.L38:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $228, %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L31
.L39:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $231, %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L32
.L40:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $233, %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L27
.cfi_endproc
.LFE2061:
.size band_create, .-band_create
.globl band_destroy
.type band_destroy, @function
band_destroy:
.LFB2063:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movq %rsi, %rbp
movq %rdx, %rbx
call cudaFree@PLT
movq %rbp, %rdi
call cudaFree@PLT
movq %rbx, %rdi
call cudaFree@PLT
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2063:
.size band_destroy, .-band_destroy
.globl ELL_create
.type ELL_create, @function
ELL_create:
.LFB2064:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $8, %rsp
.cfi_def_cfa_offset 64
movl %edi, %ebx
movq %rdx, %r15
movq %rcx, %r14
movq %r8, %r13
movq %r9, %r12
imull %edi, %esi
movslq %esi, %rbp
salq $2, %rbp
movq %rbp, %rsi
movq 64(%rsp), %rdi
call cudaMalloc@PLT
call cudaGetLastError@PLT
testl %eax, %eax
jne .L53
.L44:
movq 64(%rsp), %rax
movq (%rax), %rdi
movl $1, %ecx
movq %rbp, %rdx
movq %r15, %rsi
call cudaMemcpy@PLT
call cudaGetLastError@PLT
testl %eax, %eax
jne .L54
.L45:
movq %rbp, %rsi
movq 72(%rsp), %rdi
call cudaMalloc@PLT
call cudaGetLastError@PLT
testl %eax, %eax
jne .L55
.L46:
movq 72(%rsp), %rax
movq (%rax), %rdi
movl $1, %ecx
movq %rbp, %rdx
movq %r14, %rsi
call cudaMemcpy@PLT
call cudaGetLastError@PLT
testl %eax, %eax
jne .L56
.L47:
movslq %ebx, %rbx
salq $2, %rbx
movq %rbx, %rsi
movq 80(%rsp), %rdi
call cudaMalloc@PLT
call cudaGetLastError@PLT
testl %eax, %eax
jne .L57
.L48:
movq 80(%rsp), %rax
movq (%rax), %rdi
movl $1, %ecx
movq %rbx, %rdx
movq %r13, %rsi
call cudaMemcpy@PLT
call cudaGetLastError@PLT
testl %eax, %eax
jne .L58
.L49:
movq %rbx, %rsi
movq 88(%rsp), %rdi
call cudaMalloc@PLT
call cudaGetLastError@PLT
testl %eax, %eax
jne .L59
.L50:
movq 88(%rsp), %rax
movq (%rax), %rdi
movl $1, %ecx
movq %rbx, %rdx
movq %r12, %rsi
call cudaMemcpy@PLT
call cudaGetLastError@PLT
testl %eax, %eax
jne .L60
.L43:
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L53:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $268, %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L44
.L54:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $270, %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L45
.L55:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $273, %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L46
.L56:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $275, %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L47
.L57:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $278, %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L48
.L58:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $280, %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L49
.L59:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $283, %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L50
.L60:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $285, %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L43
.cfi_endproc
.LFE2064:
.size ELL_create, .-ELL_create
.globl ELL_destroy
.type ELL_destroy, @function
ELL_destroy:
.LFB2066:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
movq %rsi, %r12
movq %rdx, %rbp
movq %rcx, %rbx
call cudaFree@PLT
movq %r12, %rdi
call cudaFree@PLT
movq %rbp, %rdi
call cudaFree@PLT
movq %rbx, %rdi
call cudaFree@PLT
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2066:
.size ELL_destroy, .-ELL_destroy
.globl _Z47__device_stub__Z16k_csr_mat_vec_mmiPiS_PfS0_S0_iPiS_PfS0_S0_
.type _Z47__device_stub__Z16k_csr_mat_vec_mmiPiS_PfS0_S0_iPiS_PfS0_S0_, @function
_Z47__device_stub__Z16k_csr_mat_vec_mmiPiS_PfS0_S0_iPiS_PfS0_S0_:
.LFB2091:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movl %edi, 44(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movq %r8, 8(%rsp)
movq %r9, (%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 44(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
movq %rsp, %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L67
.L63:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L68
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L67:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z16k_csr_mat_vec_mmiPiS_PfS0_S0_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L63
.L68:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2091:
.size _Z47__device_stub__Z16k_csr_mat_vec_mmiPiS_PfS0_S0_iPiS_PfS0_S0_, .-_Z47__device_stub__Z16k_csr_mat_vec_mmiPiS_PfS0_S0_iPiS_PfS0_S0_
.globl _Z16k_csr_mat_vec_mmiPiS_PfS0_S0_
.type _Z16k_csr_mat_vec_mmiPiS_PfS0_S0_, @function
_Z16k_csr_mat_vec_mmiPiS_PfS0_S0_:
.LFB2092:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z47__device_stub__Z16k_csr_mat_vec_mmiPiS_PfS0_S0_iPiS_PfS0_S0_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2092:
.size _Z16k_csr_mat_vec_mmiPiS_PfS0_S0_, .-_Z16k_csr_mat_vec_mmiPiS_PfS0_S0_
.globl _Z48__device_stub__Z17k_csr2_mat_vec_mmiPiS_PfS0_S0_iPiS_PfS0_S0_
.type _Z48__device_stub__Z17k_csr2_mat_vec_mmiPiS_PfS0_S0_iPiS_PfS0_S0_, @function
_Z48__device_stub__Z17k_csr2_mat_vec_mmiPiS_PfS0_S0_iPiS_PfS0_S0_:
.LFB2093:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movl %edi, 44(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movq %r8, 8(%rsp)
movq %r9, (%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 44(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
movq %rsp, %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L75
.L71:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L76
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L75:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z17k_csr2_mat_vec_mmiPiS_PfS0_S0_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L71
.L76:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2093:
.size _Z48__device_stub__Z17k_csr2_mat_vec_mmiPiS_PfS0_S0_iPiS_PfS0_S0_, .-_Z48__device_stub__Z17k_csr2_mat_vec_mmiPiS_PfS0_S0_iPiS_PfS0_S0_
.globl _Z17k_csr2_mat_vec_mmiPiS_PfS0_S0_
.type _Z17k_csr2_mat_vec_mmiPiS_PfS0_S0_, @function
_Z17k_csr2_mat_vec_mmiPiS_PfS0_S0_:
.LFB2094:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z48__device_stub__Z17k_csr2_mat_vec_mmiPiS_PfS0_S0_iPiS_PfS0_S0_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2094:
.size _Z17k_csr2_mat_vec_mmiPiS_PfS0_S0_, .-_Z17k_csr2_mat_vec_mmiPiS_PfS0_S0_
.globl CSR_kernel
.type CSR_kernel, @function
CSR_kernel:
.LFB2059:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $32, %rsp
.cfi_def_cfa_offset 80
movl %edi, %ebx
movq %rdx, %rbp
movq %rcx, %r12
movq %r8, %r13
movq %r9, %r14
cmpb $0, 88(%rsp)
je .L80
leal 2(%rdi), %eax
sall $5, %eax
leal 62(%rax), %edx
subl $1, %eax
cmovs %edx, %eax
sarl $6, %eax
movl %eax, 8(%rsp)
movl $1, 12(%rsp)
movl $1, 16(%rsp)
movl $64, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L86
.L82:
call cudaGetLastError@PLT
testl %eax, %eax
jne .L87
.L79:
addq $32, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L86:
.cfi_restore_state
movq 80(%rsp), %r9
movq %r14, %r8
movq %r13, %rcx
movq %r12, %rdx
movq %rbp, %rsi
movl %ebx, %edi
call _Z48__device_stub__Z17k_csr2_mat_vec_mmiPiS_PfS0_S0_iPiS_PfS0_S0_
jmp .L82
.L80:
leal 126(%rdi), %eax
movl %edi, %edx
addl $63, %edx
cmovns %edx, %eax
sarl $6, %eax
movl %eax, 8(%rsp)
movl $1, 12(%rsp)
movl $1, 16(%rsp)
movl $64, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L82
movq 80(%rsp), %r9
movq %r14, %r8
movq %r13, %rcx
movq %r12, %rdx
movq %rbp, %rsi
movl %ebx, %edi
call _Z47__device_stub__Z16k_csr_mat_vec_mmiPiS_PfS0_S0_iPiS_PfS0_S0_
jmp .L82
.L87:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $199, %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L79
.cfi_endproc
.LFE2059:
.size CSR_kernel, .-CSR_kernel
.globl CSR_matvec
.type CSR_matvec, @function
CSR_matvec:
.LFB2057:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $56, %rsp
.cfi_def_cfa_offset 96
movl %edi, %ebx
movl %esi, %ebp
movq 96(%rsp), %r13
movl 104(%rsp), %r12d
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
leaq 32(%rsp), %rax
pushq %rax
.cfi_def_cfa_offset 104
leaq 32(%rsp), %rax
pushq %rax
.cfi_def_cfa_offset 112
leaq 32(%rsp), %rax
pushq %rax
.cfi_def_cfa_offset 120
leaq 32(%rsp), %rax
pushq %rax
.cfi_def_cfa_offset 128
leaq 32(%rsp), %rax
pushq %rax
.cfi_def_cfa_offset 136
pushq %r13
.cfi_def_cfa_offset 144
call CSR_create
addq $48, %rsp
.cfi_def_cfa_offset 96
movzbl %r12b, %r12d
pushq %r12
.cfi_def_cfa_offset 104
pushq 40(%rsp)
.cfi_def_cfa_offset 112
movq 40(%rsp), %r9
movq 32(%rsp), %r8
movq 24(%rsp), %rcx
movq 16(%rsp), %rdx
movl %ebp, %esi
movl %ebx, %edi
call CSR_kernel
addq $16, %rsp
.cfi_def_cfa_offset 96
movslq %ebx, %rdx
salq $2, %rdx
movl $2, %ecx
movq 32(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
call cudaGetLastError@PLT
testl %eax, %eax
jne .L92
.L89:
movq 32(%rsp), %r8
movq 24(%rsp), %rcx
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call CSR_destroy
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L93
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L92:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $138, %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L89
.L93:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size CSR_matvec, .-CSR_matvec
.globl _Z46__device_stub__Z16k_ell_mat_vec_mmiiPiPfS0_S0_iiPiPfS0_S0_
.type _Z46__device_stub__Z16k_ell_mat_vec_mmiiPiPfS0_S0_iiPiPfS0_S0_, @function
_Z46__device_stub__Z16k_ell_mat_vec_mmiiPiPfS0_S0_iiPiPfS0_S0_:
.LFB2095:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movl %edi, 44(%rsp)
movl %esi, 40(%rsp)
movq %rdx, 32(%rsp)
movq %rcx, 24(%rsp)
movq %r8, 16(%rsp)
movq %r9, 8(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 44(%rsp), %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rax
movq %rax, 120(%rsp)
leaq 32(%rsp), %rax
movq %rax, 128(%rsp)
leaq 24(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L98
.L94:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L99
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L98:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z16k_ell_mat_vec_mmiiPiPfS0_S0_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L94
.L99:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2095:
.size _Z46__device_stub__Z16k_ell_mat_vec_mmiiPiPfS0_S0_iiPiPfS0_S0_, .-_Z46__device_stub__Z16k_ell_mat_vec_mmiiPiPfS0_S0_iiPiPfS0_S0_
.globl _Z16k_ell_mat_vec_mmiiPiPfS0_S0_
.type _Z16k_ell_mat_vec_mmiiPiPfS0_S0_, @function
_Z16k_ell_mat_vec_mmiiPiPfS0_S0_:
.LFB2096:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z46__device_stub__Z16k_ell_mat_vec_mmiiPiPfS0_S0_iiPiPfS0_S0_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2096:
.size _Z16k_ell_mat_vec_mmiiPiPfS0_S0_, .-_Z16k_ell_mat_vec_mmiiPiPfS0_S0_
.globl ELL_kernel
.type ELL_kernel, @function
ELL_kernel:
.LFB2065:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $40, %rsp
.cfi_def_cfa_offset 96
movl %edi, %ebx
movl %esi, %ebp
movq %rdx, %r12
movq %rcx, %r13
movq %r8, %r14
movq %r9, %r15
leal 126(%rdi), %eax
movl %edi, %edx
addl $63, %edx
cmovns %edx, %eax
sarl $6, %eax
movl %eax, 8(%rsp)
movl $1, 12(%rsp)
movl $64, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L106
.L103:
call cudaGetLastError@PLT
testl %eax, %eax
jne .L107
.L102:
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L106:
.cfi_restore_state
movq %r15, %r9
movq %r14, %r8
movq %r13, %rcx
movq %r12, %rdx
movl %ebp, %esi
movl %ebx, %edi
call _Z46__device_stub__Z16k_ell_mat_vec_mmiiPiPfS0_S0_iiPiPfS0_S0_
jmp .L103
.L107:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $297, %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L102
.cfi_endproc
.LFE2065:
.size ELL_kernel, .-ELL_kernel
.globl _Z37__device_stub__Z11band_matveciiPfS_S_iiPfS_S_
.type _Z37__device_stub__Z11band_matveciiPfS_S_iiPfS_S_, @function
_Z37__device_stub__Z11band_matveciiPfS_S_iiPfS_S_:
.LFB2097:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movl %esi, 24(%rsp)
movq %rdx, 16(%rsp)
movq %rcx, 8(%rsp)
movq %r8, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L112
.L108:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L113
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L112:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z11band_matveciiPfS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L108
.L113:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2097:
.size _Z37__device_stub__Z11band_matveciiPfS_S_iiPfS_S_, .-_Z37__device_stub__Z11band_matveciiPfS_S_iiPfS_S_
.globl _Z11band_matveciiPfS_S_
.type _Z11band_matveciiPfS_S_, @function
_Z11band_matveciiPfS_S_:
.LFB2098:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z37__device_stub__Z11band_matveciiPfS_S_iiPfS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2098:
.size _Z11band_matveciiPfS_S_, .-_Z11band_matveciiPfS_S_
.globl band_kernel
.type band_kernel, @function
band_kernel:
.LFB2062:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $32, %rsp
.cfi_def_cfa_offset 80
movl %edi, %ebx
movl %esi, %ebp
movq %rdx, %r12
movq %rcx, %r13
movq %r8, %r14
leal 126(%rdi), %eax
movl %edi, %edx
addl $63, %edx
cmovns %edx, %eax
sarl $6, %eax
movl %eax, 8(%rsp)
movl $1, 12(%rsp)
movl $64, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L120
.L117:
call cudaGetLastError@PLT
testl %eax, %eax
jne .L121
.L116:
addq $32, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L120:
.cfi_restore_state
movq %r14, %r8
movq %r13, %rcx
movq %r12, %rdx
movl %ebp, %esi
movl %ebx, %edi
call _Z37__device_stub__Z11band_matveciiPfS_S_iiPfS_S_
jmp .L117
.L121:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $247, %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L116
.cfi_endproc
.LFE2062:
.size band_kernel, .-band_kernel
.section .rodata.str1.1
.LC2:
.string "_Z11band_matveciiPfS_S_"
.section .rodata.str1.8
.align 8
.LC3:
.string "_Z16k_ell_mat_vec_mmiiPiPfS0_S0_"
.align 8
.LC4:
.string "_Z17k_csr2_mat_vec_mmiPiS_PfS0_S0_"
.align 8
.LC5:
.string "_Z16k_csr_mat_vec_mmiPiS_PfS0_S0_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2100:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z11band_matveciiPfS_S_(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z16k_ell_mat_vec_mmiiPiPfS0_S0_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z17k_csr2_mat_vec_mmiPiS_PfS0_S0_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z16k_csr_mat_vec_mmiPiS_PfS0_S0_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2100:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <cuda.h>
#include <cuda_runtime.h>
#include "stdio.h"
#define TILE_SIZE 64
#define WARP_SIZE 32
extern "C" void CSR_matvec(int N, int nnz, int* start, int* indices, float* data, float* x, float *y, bool bVectorized);
extern "C" void CSR_create(int N, int nnz, int* start, int * indices, float * data , float * x , float * y, int** start_d, int **indices_d, float **data_d, float **x_d, float **y_d);
extern "C" void CSR_kernel(int N, int nnz, int* start_d, int * indices_d, float * data_d , float * x_d , float * y_d, bool bVectorized);
extern "C" void CSR_destroy(int* start_d, int* indices_d, float* data_d, float* x_d, float* y_d);
extern "C" void ELL_create(int N, int num_cols_per_row, int * indices, float * data , float * x , float * y, int **indices_d, float **data_d, float **x_d, float **y_d);
extern "C" void ELL_kernel(int N, int num_cols_per_row , int * indices_d, float * data_d , float * x_d , float * y_d);
extern "C" void ELL_destroy(int* indices_d, float* data_d, float* x_d, float* y_d);
extern "C" void band_create(int N, int num_cols_per_row, float * data , float * x , float * y, float **data_d, float **x_d, float **y_d);
extern "C" void band_kernel(int N, int num_cols_per_row , float * data_d , float * x_d , float * y_d);
extern "C" void band_destroy(float* data_d, float* x_d, float* y_d);
/**
* Custom CUDA error check wrapper.
*/
#define checkCUDAError() do { \
cudaError_t error = cudaGetLastError(); \
if (error != cudaSuccess) { \
printf("(CUDA) %s", cudaGetErrorString(error)); \
printf(" (" __FILE__ ":%d)\n", __LINE__); \
}\
} while (0)
/**
* Cuda kernel for: CSR_s(A)x = y
*/
__global__ void k_csr_mat_vec_mm(const int N, int *start, int* indices, float *data, float *x, float* y) {
int row = blockDim.x * blockIdx.x + threadIdx.x ;
if ( row < N ){
float dot = 0;
int row_start = start [ row ];
int row_end = start [ row+1];
for ( int jj = row_start ; jj < row_end ; jj ++) {
dot += data [ jj ] * x [ indices [ jj ]];
}
y[row] = dot ;
}
}
/**
* Cuda kernel for: CSR_v(A)x = y
*/
__global__ void k_csr2_mat_vec_mm(const int N, int *start, int* indices, float *data, float *x, float* y) {
__shared__ float vals[TILE_SIZE];
int thread_id = blockDim.x * blockIdx.x + threadIdx.x;
int warp_id = thread_id / WARP_SIZE;
int lane = thread_id & (WARP_SIZE - 1);
int row = warp_id;
if (row < N) {
int row_start = start[row];
int row_end = start[row + 1];
// compute running sum per thread
vals[threadIdx.x] = 0;
for (int jj = row_start + lane; jj < row_end; jj += WARP_SIZE) {
vals[threadIdx.x] += data[jj] * x[indices[jj]];
}
// parallel reduction in shared memory
for (int d = WARP_SIZE >> 1; d >= 1; d >>= 1) {
if (lane < d) vals[threadIdx.x] += vals[threadIdx.x + d];
}
// first thread in a warp writes the result
if (lane == 0) {
y[row] = vals[threadIdx.x];
}
}
}
/**
* Cuda kernel for: ELL(A)x = y
*/
__global__ void k_ell_mat_vec_mm ( const int N, const int num_cols_per_row , int * indices,
float * data , float * x , float * y ) {
int row = blockDim.x * blockIdx.x + threadIdx.x ;
if ( row < N ){
float dot = 0;
for ( int n = 0; n < num_cols_per_row ; n ++){
int col = indices [ N * n + row ];
float val = data [ N * n + row ];
if ( val != 0)
dot += val * x [ col ];
}
y [ row ] = dot ;
}
}
/**
* Cuda kernel for: Band(A)x = y
*/
__global__ void band_matvec(int N, int k_max,
float* a, float* x, float* y) {
int i = TILE_SIZE * blockIdx.x + threadIdx.x;
if (i < N) {
float dot = 0;
for (int k = 0; k < 2 * k_max + 1; k++) {
float val = a[N * k + i];
int j = i + k - k_max;
if (val != 0) dot += val * x[j];
}
y[i] = dot;
}
}
/**
* Perform: CSR(A)x = y
*/
void CSR_matvec(const int N, const int nnz, int* start, int * indices, float * data , float * x , float * y, const bool bVectorized) {
int *start_d, *indices_d;
float *data_d, *x_d, *y_d;
CSR_create(N, nnz, start, indices, data, x, y, &start_d, &indices_d, &data_d, &x_d, &y_d);
CSR_kernel(N, nnz, start_d, indices_d, data_d, x_d, y_d, bVectorized);
cudaMemcpy(y, y_d, N * sizeof(float), cudaMemcpyDeviceToHost);
checkCUDAError();
CSR_destroy(start_d, indices_d, data_d, x_d, y_d);
}
/**
* Create CSR matrix
*/
void CSR_create(const int N, const int nnz,
int * start, int * indices, float * data , float * x , float * y,
int ** start_d, int ** indices_d, float **data_d, float **x_d, float **y_d) {
/************************/
/* copy to device */
/************************/
cudaMalloc((void **) start_d, (N+1) * sizeof(int));
checkCUDAError();
cudaMemcpy(*start_d, start, (N+1) * sizeof(int), cudaMemcpyHostToDevice);
checkCUDAError();
cudaMalloc((void **) indices_d, nnz * sizeof(int));
checkCUDAError();
cudaMemcpy(*indices_d, indices, nnz * sizeof(int), cudaMemcpyHostToDevice);
checkCUDAError();
cudaMalloc((void **) data_d, nnz * sizeof(float));
checkCUDAError();
cudaMemcpy(*data_d, data, nnz * sizeof(float), cudaMemcpyHostToDevice);
checkCUDAError();
cudaMalloc((void **) x_d, N * sizeof(float));
checkCUDAError();
cudaMemcpy(*x_d, x, N * sizeof(float), cudaMemcpyHostToDevice);
checkCUDAError();
cudaMalloc((void **) y_d, N * sizeof(float));
checkCUDAError();
cudaMemcpy(*y_d, y, N * sizeof(float) , cudaMemcpyHostToDevice);
checkCUDAError();
}
/**
* Perform: CSR(A)x = y
*/
void CSR_kernel(const int N, const int nnz, int * start_d , int * indices_d, float * data_d , float * x_d , float * y_d, const bool bVectorized) {
if (bVectorized) {
//#threads = #rows * #threads per row (= N * WARP_SIZE)
dim3 grid((N * WARP_SIZE + TILE_SIZE - 1)/TILE_SIZE, 1, 1);
dim3 block(TILE_SIZE, 1, 1);
k_csr2_mat_vec_mm <<< grid, block >>> (N, start_d, indices_d, data_d, x_d, y_d);
} else {
//#threads = #rows (= N)
dim3 grid((N + TILE_SIZE - 1)/TILE_SIZE, 1, 1);
dim3 block(TILE_SIZE, 1, 1);
k_csr_mat_vec_mm <<< grid, block >>> (N, start_d, indices_d, data_d, x_d, y_d);
}
checkCUDAError();
}
/**
* Destroy CSR matrix
*/
void CSR_destroy(int* start_d, int* indices_d, float* data_d, float* x_d, float* y_d) {
cudaFree(start_d);
cudaFree(indices_d);
cudaFree(data_d);
cudaFree(x_d);
cudaFree(y_d);
}
/**
* Create band matrix
*/
void band_create(const int N, const int num_cols_per_row,
float * data , float * x , float * y,
float **data_d, float **x_d, float **y_d) {
cudaMalloc((void **) data_d, N * num_cols_per_row * sizeof(float));
checkCUDAError();
cudaMemcpy(*data_d, data, N * num_cols_per_row * sizeof(float), cudaMemcpyHostToDevice);
checkCUDAError();
cudaMalloc((void **) x_d, N * sizeof(float));
checkCUDAError();
cudaMemcpy(*x_d, x, N * sizeof(float), cudaMemcpyHostToDevice);
checkCUDAError();
cudaMalloc((void **) y_d, N * sizeof(float));
checkCUDAError();
cudaMemcpy(*y_d, y, N * sizeof(float), cudaMemcpyHostToDevice);
checkCUDAError();
}
/**
* Perform: band(A)x = y
*/
void band_kernel(int N, int k_max , float * data_d , float * x_d , float * y_d) {
//#threads = #rows (= N)
dim3 grid((N + TILE_SIZE - 1)/TILE_SIZE, 1, 1);
dim3 block(TILE_SIZE, 1, 1);
band_matvec <<< grid, block >>> (N, k_max, data_d , x_d, y_d);
checkCUDAError();
}
/**
* Destroy ELL matrix
*/
void band_destroy(float* data_d, float* x_d, float* y_d) {
cudaFree(data_d);
cudaFree(x_d);
cudaFree(y_d);
}
/**
* Create ELL matrix
*/
void ELL_create(const int N, const int num_cols_per_row,
int * indices, float * data , float * x , float * y,
int ** indices_d, float **data_d, float **x_d, float **y_d) {
cudaMalloc((void **) indices_d, N * num_cols_per_row * sizeof(int));
checkCUDAError();
cudaMemcpy(*indices_d, indices, N * num_cols_per_row * sizeof(int), cudaMemcpyHostToDevice);
checkCUDAError();
cudaMalloc((void **) data_d, N * num_cols_per_row * sizeof(float));
checkCUDAError();
cudaMemcpy(*data_d, data, N * num_cols_per_row * sizeof(float), cudaMemcpyHostToDevice);
checkCUDAError();
cudaMalloc((void **) x_d, N * sizeof(float));
checkCUDAError();
cudaMemcpy(*x_d, x, N * sizeof(float), cudaMemcpyHostToDevice);
checkCUDAError();
cudaMalloc((void **) y_d, N * sizeof(float));
checkCUDAError();
cudaMemcpy(*y_d, y, N * sizeof(float), cudaMemcpyHostToDevice);
checkCUDAError();
}
/**
* Perform: ELL(A)x = y
*/
void ELL_kernel(int N, int num_cols_per_row , int * indices_d, float * data_d , float * x_d , float * y_d) {
//round grid size N/TILE_SIZE up
dim3 grid((N + TILE_SIZE - 1)/TILE_SIZE, 1, 1);
dim3 block(TILE_SIZE, 1, 1);
k_ell_mat_vec_mm <<< grid, block >>> (N, num_cols_per_row, indices_d, data_d , x_d, y_d);
checkCUDAError();
}
/**
* Destroy ELL matrix
*/
void ELL_destroy(int* indices_d, float* data_d, float* x_d, float* y_d) {
cudaFree(indices_d);
cudaFree(data_d);
cudaFree(x_d);
cudaFree(y_d);
} | #include <hip/hip_runtime.h>
#include "stdio.h"
#define TILE_SIZE 64
#define WARP_SIZE 32
extern "C" void CSR_matvec(int N, int nnz, int* start, int* indices, float* data, float* x, float *y, bool bVectorized);
extern "C" void CSR_create(int N, int nnz, int* start, int * indices, float * data , float * x , float * y, int** start_d, int **indices_d, float **data_d, float **x_d, float **y_d);
extern "C" void CSR_kernel(int N, int nnz, int* start_d, int * indices_d, float * data_d , float * x_d , float * y_d, bool bVectorized);
extern "C" void CSR_destroy(int* start_d, int* indices_d, float* data_d, float* x_d, float* y_d);
extern "C" void ELL_create(int N, int num_cols_per_row, int * indices, float * data , float * x , float * y, int **indices_d, float **data_d, float **x_d, float **y_d);
extern "C" void ELL_kernel(int N, int num_cols_per_row , int * indices_d, float * data_d , float * x_d , float * y_d);
extern "C" void ELL_destroy(int* indices_d, float* data_d, float* x_d, float* y_d);
extern "C" void band_create(int N, int num_cols_per_row, float * data , float * x , float * y, float **data_d, float **x_d, float **y_d);
extern "C" void band_kernel(int N, int num_cols_per_row , float * data_d , float * x_d , float * y_d);
extern "C" void band_destroy(float* data_d, float* x_d, float* y_d);
/**
* Custom CUDA error check wrapper.
*/
#define checkCUDAError() do { \
hipError_t error = hipGetLastError(); \
if (error != hipSuccess) { \
printf("(CUDA) %s", hipGetErrorString(error)); \
printf(" (" __FILE__ ":%d)\n", __LINE__); \
}\
} while (0)
/**
* Cuda kernel for: CSR_s(A)x = y
*/
__global__ void k_csr_mat_vec_mm(const int N, int *start, int* indices, float *data, float *x, float* y) {
int row = blockDim.x * blockIdx.x + threadIdx.x ;
if ( row < N ){
float dot = 0;
int row_start = start [ row ];
int row_end = start [ row+1];
for ( int jj = row_start ; jj < row_end ; jj ++) {
dot += data [ jj ] * x [ indices [ jj ]];
}
y[row] = dot ;
}
}
/**
* Cuda kernel for: CSR_v(A)x = y
*/
__global__ void k_csr2_mat_vec_mm(const int N, int *start, int* indices, float *data, float *x, float* y) {
__shared__ float vals[TILE_SIZE];
int thread_id = blockDim.x * blockIdx.x + threadIdx.x;
int warp_id = thread_id / WARP_SIZE;
int lane = thread_id & (WARP_SIZE - 1);
int row = warp_id;
if (row < N) {
int row_start = start[row];
int row_end = start[row + 1];
// compute running sum per thread
vals[threadIdx.x] = 0;
for (int jj = row_start + lane; jj < row_end; jj += WARP_SIZE) {
vals[threadIdx.x] += data[jj] * x[indices[jj]];
}
// parallel reduction in shared memory
for (int d = WARP_SIZE >> 1; d >= 1; d >>= 1) {
if (lane < d) vals[threadIdx.x] += vals[threadIdx.x + d];
}
// first thread in a warp writes the result
if (lane == 0) {
y[row] = vals[threadIdx.x];
}
}
}
/**
* Cuda kernel for: ELL(A)x = y
*/
__global__ void k_ell_mat_vec_mm ( const int N, const int num_cols_per_row , int * indices,
float * data , float * x , float * y ) {
int row = blockDim.x * blockIdx.x + threadIdx.x ;
if ( row < N ){
float dot = 0;
for ( int n = 0; n < num_cols_per_row ; n ++){
int col = indices [ N * n + row ];
float val = data [ N * n + row ];
if ( val != 0)
dot += val * x [ col ];
}
y [ row ] = dot ;
}
}
/**
* Cuda kernel for: Band(A)x = y
*/
__global__ void band_matvec(int N, int k_max,
float* a, float* x, float* y) {
int i = TILE_SIZE * blockIdx.x + threadIdx.x;
if (i < N) {
float dot = 0;
for (int k = 0; k < 2 * k_max + 1; k++) {
float val = a[N * k + i];
int j = i + k - k_max;
if (val != 0) dot += val * x[j];
}
y[i] = dot;
}
}
/**
* Perform: CSR(A)x = y
*/
void CSR_matvec(const int N, const int nnz, int* start, int * indices, float * data , float * x , float * y, const bool bVectorized) {
int *start_d, *indices_d;
float *data_d, *x_d, *y_d;
CSR_create(N, nnz, start, indices, data, x, y, &start_d, &indices_d, &data_d, &x_d, &y_d);
CSR_kernel(N, nnz, start_d, indices_d, data_d, x_d, y_d, bVectorized);
hipMemcpy(y, y_d, N * sizeof(float), hipMemcpyDeviceToHost);
checkCUDAError();
CSR_destroy(start_d, indices_d, data_d, x_d, y_d);
}
/**
* Create CSR matrix
*/
void CSR_create(const int N, const int nnz,
int * start, int * indices, float * data , float * x , float * y,
int ** start_d, int ** indices_d, float **data_d, float **x_d, float **y_d) {
/************************/
/* copy to device */
/************************/
hipMalloc((void **) start_d, (N+1) * sizeof(int));
checkCUDAError();
hipMemcpy(*start_d, start, (N+1) * sizeof(int), hipMemcpyHostToDevice);
checkCUDAError();
hipMalloc((void **) indices_d, nnz * sizeof(int));
checkCUDAError();
hipMemcpy(*indices_d, indices, nnz * sizeof(int), hipMemcpyHostToDevice);
checkCUDAError();
hipMalloc((void **) data_d, nnz * sizeof(float));
checkCUDAError();
hipMemcpy(*data_d, data, nnz * sizeof(float), hipMemcpyHostToDevice);
checkCUDAError();
hipMalloc((void **) x_d, N * sizeof(float));
checkCUDAError();
hipMemcpy(*x_d, x, N * sizeof(float), hipMemcpyHostToDevice);
checkCUDAError();
hipMalloc((void **) y_d, N * sizeof(float));
checkCUDAError();
hipMemcpy(*y_d, y, N * sizeof(float) , hipMemcpyHostToDevice);
checkCUDAError();
}
/**
* Perform: CSR(A)x = y
*/
void CSR_kernel(const int N, const int nnz, int * start_d , int * indices_d, float * data_d , float * x_d , float * y_d, const bool bVectorized) {
if (bVectorized) {
//#threads = #rows * #threads per row (= N * WARP_SIZE)
dim3 grid((N * WARP_SIZE + TILE_SIZE - 1)/TILE_SIZE, 1, 1);
dim3 block(TILE_SIZE, 1, 1);
k_csr2_mat_vec_mm <<< grid, block >>> (N, start_d, indices_d, data_d, x_d, y_d);
} else {
//#threads = #rows (= N)
dim3 grid((N + TILE_SIZE - 1)/TILE_SIZE, 1, 1);
dim3 block(TILE_SIZE, 1, 1);
k_csr_mat_vec_mm <<< grid, block >>> (N, start_d, indices_d, data_d, x_d, y_d);
}
checkCUDAError();
}
/**
* Destroy CSR matrix
*/
void CSR_destroy(int* start_d, int* indices_d, float* data_d, float* x_d, float* y_d) {
hipFree(start_d);
hipFree(indices_d);
hipFree(data_d);
hipFree(x_d);
hipFree(y_d);
}
/**
* Create band matrix
*/
void band_create(const int N, const int num_cols_per_row,
float * data , float * x , float * y,
float **data_d, float **x_d, float **y_d) {
hipMalloc((void **) data_d, N * num_cols_per_row * sizeof(float));
checkCUDAError();
hipMemcpy(*data_d, data, N * num_cols_per_row * sizeof(float), hipMemcpyHostToDevice);
checkCUDAError();
hipMalloc((void **) x_d, N * sizeof(float));
checkCUDAError();
hipMemcpy(*x_d, x, N * sizeof(float), hipMemcpyHostToDevice);
checkCUDAError();
hipMalloc((void **) y_d, N * sizeof(float));
checkCUDAError();
hipMemcpy(*y_d, y, N * sizeof(float), hipMemcpyHostToDevice);
checkCUDAError();
}
/**
* Perform: band(A)x = y
*/
void band_kernel(int N, int k_max , float * data_d , float * x_d , float * y_d) {
//#threads = #rows (= N)
dim3 grid((N + TILE_SIZE - 1)/TILE_SIZE, 1, 1);
dim3 block(TILE_SIZE, 1, 1);
band_matvec <<< grid, block >>> (N, k_max, data_d , x_d, y_d);
checkCUDAError();
}
/**
* Destroy ELL matrix
*/
void band_destroy(float* data_d, float* x_d, float* y_d) {
hipFree(data_d);
hipFree(x_d);
hipFree(y_d);
}
/**
* Create ELL matrix
*/
void ELL_create(const int N, const int num_cols_per_row,
int * indices, float * data , float * x , float * y,
int ** indices_d, float **data_d, float **x_d, float **y_d) {
hipMalloc((void **) indices_d, N * num_cols_per_row * sizeof(int));
checkCUDAError();
hipMemcpy(*indices_d, indices, N * num_cols_per_row * sizeof(int), hipMemcpyHostToDevice);
checkCUDAError();
hipMalloc((void **) data_d, N * num_cols_per_row * sizeof(float));
checkCUDAError();
hipMemcpy(*data_d, data, N * num_cols_per_row * sizeof(float), hipMemcpyHostToDevice);
checkCUDAError();
hipMalloc((void **) x_d, N * sizeof(float));
checkCUDAError();
hipMemcpy(*x_d, x, N * sizeof(float), hipMemcpyHostToDevice);
checkCUDAError();
hipMalloc((void **) y_d, N * sizeof(float));
checkCUDAError();
hipMemcpy(*y_d, y, N * sizeof(float), hipMemcpyHostToDevice);
checkCUDAError();
}
/**
* Perform: ELL(A)x = y
*/
void ELL_kernel(int N, int num_cols_per_row , int * indices_d, float * data_d , float * x_d , float * y_d) {
//round grid size N/TILE_SIZE up
dim3 grid((N + TILE_SIZE - 1)/TILE_SIZE, 1, 1);
dim3 block(TILE_SIZE, 1, 1);
k_ell_mat_vec_mm <<< grid, block >>> (N, num_cols_per_row, indices_d, data_d , x_d, y_d);
checkCUDAError();
}
/**
* Destroy ELL matrix
*/
void ELL_destroy(int* indices_d, float* data_d, float* x_d, float* y_d) {
hipFree(indices_d);
hipFree(data_d);
hipFree(x_d);
hipFree(y_d);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "stdio.h"
#define TILE_SIZE 64
#define WARP_SIZE 32
extern "C" void CSR_matvec(int N, int nnz, int* start, int* indices, float* data, float* x, float *y, bool bVectorized);
extern "C" void CSR_create(int N, int nnz, int* start, int * indices, float * data , float * x , float * y, int** start_d, int **indices_d, float **data_d, float **x_d, float **y_d);
extern "C" void CSR_kernel(int N, int nnz, int* start_d, int * indices_d, float * data_d , float * x_d , float * y_d, bool bVectorized);
extern "C" void CSR_destroy(int* start_d, int* indices_d, float* data_d, float* x_d, float* y_d);
extern "C" void ELL_create(int N, int num_cols_per_row, int * indices, float * data , float * x , float * y, int **indices_d, float **data_d, float **x_d, float **y_d);
extern "C" void ELL_kernel(int N, int num_cols_per_row , int * indices_d, float * data_d , float * x_d , float * y_d);
extern "C" void ELL_destroy(int* indices_d, float* data_d, float* x_d, float* y_d);
extern "C" void band_create(int N, int num_cols_per_row, float * data , float * x , float * y, float **data_d, float **x_d, float **y_d);
extern "C" void band_kernel(int N, int num_cols_per_row , float * data_d , float * x_d , float * y_d);
extern "C" void band_destroy(float* data_d, float* x_d, float* y_d);
/**
* Custom CUDA error check wrapper.
*/
#define checkCUDAError() do { \
hipError_t error = hipGetLastError(); \
if (error != hipSuccess) { \
printf("(CUDA) %s", hipGetErrorString(error)); \
printf(" (" __FILE__ ":%d)\n", __LINE__); \
}\
} while (0)
/**
* Cuda kernel for: CSR_s(A)x = y
*/
__global__ void k_csr_mat_vec_mm(const int N, int *start, int* indices, float *data, float *x, float* y) {
int row = blockDim.x * blockIdx.x + threadIdx.x ;
if ( row < N ){
float dot = 0;
int row_start = start [ row ];
int row_end = start [ row+1];
for ( int jj = row_start ; jj < row_end ; jj ++) {
dot += data [ jj ] * x [ indices [ jj ]];
}
y[row] = dot ;
}
}
/**
* Cuda kernel for: CSR_v(A)x = y
*/
__global__ void k_csr2_mat_vec_mm(const int N, int *start, int* indices, float *data, float *x, float* y) {
__shared__ float vals[TILE_SIZE];
int thread_id = blockDim.x * blockIdx.x + threadIdx.x;
int warp_id = thread_id / WARP_SIZE;
int lane = thread_id & (WARP_SIZE - 1);
int row = warp_id;
if (row < N) {
int row_start = start[row];
int row_end = start[row + 1];
// compute running sum per thread
vals[threadIdx.x] = 0;
for (int jj = row_start + lane; jj < row_end; jj += WARP_SIZE) {
vals[threadIdx.x] += data[jj] * x[indices[jj]];
}
// parallel reduction in shared memory
for (int d = WARP_SIZE >> 1; d >= 1; d >>= 1) {
if (lane < d) vals[threadIdx.x] += vals[threadIdx.x + d];
}
// first thread in a warp writes the result
if (lane == 0) {
y[row] = vals[threadIdx.x];
}
}
}
/**
* Cuda kernel for: ELL(A)x = y
*/
__global__ void k_ell_mat_vec_mm ( const int N, const int num_cols_per_row , int * indices,
float * data , float * x , float * y ) {
int row = blockDim.x * blockIdx.x + threadIdx.x ;
if ( row < N ){
float dot = 0;
for ( int n = 0; n < num_cols_per_row ; n ++){
int col = indices [ N * n + row ];
float val = data [ N * n + row ];
if ( val != 0)
dot += val * x [ col ];
}
y [ row ] = dot ;
}
}
/**
* Cuda kernel for: Band(A)x = y
*/
__global__ void band_matvec(int N, int k_max,
float* a, float* x, float* y) {
int i = TILE_SIZE * blockIdx.x + threadIdx.x;
if (i < N) {
float dot = 0;
for (int k = 0; k < 2 * k_max + 1; k++) {
float val = a[N * k + i];
int j = i + k - k_max;
if (val != 0) dot += val * x[j];
}
y[i] = dot;
}
}
/**
* Perform: CSR(A)x = y
*/
void CSR_matvec(const int N, const int nnz, int* start, int * indices, float * data , float * x , float * y, const bool bVectorized) {
int *start_d, *indices_d;
float *data_d, *x_d, *y_d;
CSR_create(N, nnz, start, indices, data, x, y, &start_d, &indices_d, &data_d, &x_d, &y_d);
CSR_kernel(N, nnz, start_d, indices_d, data_d, x_d, y_d, bVectorized);
hipMemcpy(y, y_d, N * sizeof(float), hipMemcpyDeviceToHost);
checkCUDAError();
CSR_destroy(start_d, indices_d, data_d, x_d, y_d);
}
/**
* Create CSR matrix
*/
void CSR_create(const int N, const int nnz,
int * start, int * indices, float * data , float * x , float * y,
int ** start_d, int ** indices_d, float **data_d, float **x_d, float **y_d) {
/************************/
/* copy to device */
/************************/
hipMalloc((void **) start_d, (N+1) * sizeof(int));
checkCUDAError();
hipMemcpy(*start_d, start, (N+1) * sizeof(int), hipMemcpyHostToDevice);
checkCUDAError();
hipMalloc((void **) indices_d, nnz * sizeof(int));
checkCUDAError();
hipMemcpy(*indices_d, indices, nnz * sizeof(int), hipMemcpyHostToDevice);
checkCUDAError();
hipMalloc((void **) data_d, nnz * sizeof(float));
checkCUDAError();
hipMemcpy(*data_d, data, nnz * sizeof(float), hipMemcpyHostToDevice);
checkCUDAError();
hipMalloc((void **) x_d, N * sizeof(float));
checkCUDAError();
hipMemcpy(*x_d, x, N * sizeof(float), hipMemcpyHostToDevice);
checkCUDAError();
hipMalloc((void **) y_d, N * sizeof(float));
checkCUDAError();
hipMemcpy(*y_d, y, N * sizeof(float) , hipMemcpyHostToDevice);
checkCUDAError();
}
/**
* Perform: CSR(A)x = y
*/
void CSR_kernel(const int N, const int nnz, int * start_d , int * indices_d, float * data_d , float * x_d , float * y_d, const bool bVectorized) {
if (bVectorized) {
//#threads = #rows * #threads per row (= N * WARP_SIZE)
dim3 grid((N * WARP_SIZE + TILE_SIZE - 1)/TILE_SIZE, 1, 1);
dim3 block(TILE_SIZE, 1, 1);
k_csr2_mat_vec_mm <<< grid, block >>> (N, start_d, indices_d, data_d, x_d, y_d);
} else {
//#threads = #rows (= N)
dim3 grid((N + TILE_SIZE - 1)/TILE_SIZE, 1, 1);
dim3 block(TILE_SIZE, 1, 1);
k_csr_mat_vec_mm <<< grid, block >>> (N, start_d, indices_d, data_d, x_d, y_d);
}
checkCUDAError();
}
/**
* Destroy CSR matrix
*/
void CSR_destroy(int* start_d, int* indices_d, float* data_d, float* x_d, float* y_d) {
hipFree(start_d);
hipFree(indices_d);
hipFree(data_d);
hipFree(x_d);
hipFree(y_d);
}
/**
* Create band matrix
*/
void band_create(const int N, const int num_cols_per_row,
float * data , float * x , float * y,
float **data_d, float **x_d, float **y_d) {
hipMalloc((void **) data_d, N * num_cols_per_row * sizeof(float));
checkCUDAError();
hipMemcpy(*data_d, data, N * num_cols_per_row * sizeof(float), hipMemcpyHostToDevice);
checkCUDAError();
hipMalloc((void **) x_d, N * sizeof(float));
checkCUDAError();
hipMemcpy(*x_d, x, N * sizeof(float), hipMemcpyHostToDevice);
checkCUDAError();
hipMalloc((void **) y_d, N * sizeof(float));
checkCUDAError();
hipMemcpy(*y_d, y, N * sizeof(float), hipMemcpyHostToDevice);
checkCUDAError();
}
/**
* Perform: band(A)x = y
*/
void band_kernel(int N, int k_max , float * data_d , float * x_d , float * y_d) {
//#threads = #rows (= N)
dim3 grid((N + TILE_SIZE - 1)/TILE_SIZE, 1, 1);
dim3 block(TILE_SIZE, 1, 1);
band_matvec <<< grid, block >>> (N, k_max, data_d , x_d, y_d);
checkCUDAError();
}
/**
* Destroy ELL matrix
*/
void band_destroy(float* data_d, float* x_d, float* y_d) {
hipFree(data_d);
hipFree(x_d);
hipFree(y_d);
}
/**
* Create ELL matrix
*/
void ELL_create(const int N, const int num_cols_per_row,
int * indices, float * data , float * x , float * y,
int ** indices_d, float **data_d, float **x_d, float **y_d) {
hipMalloc((void **) indices_d, N * num_cols_per_row * sizeof(int));
checkCUDAError();
hipMemcpy(*indices_d, indices, N * num_cols_per_row * sizeof(int), hipMemcpyHostToDevice);
checkCUDAError();
hipMalloc((void **) data_d, N * num_cols_per_row * sizeof(float));
checkCUDAError();
hipMemcpy(*data_d, data, N * num_cols_per_row * sizeof(float), hipMemcpyHostToDevice);
checkCUDAError();
hipMalloc((void **) x_d, N * sizeof(float));
checkCUDAError();
hipMemcpy(*x_d, x, N * sizeof(float), hipMemcpyHostToDevice);
checkCUDAError();
hipMalloc((void **) y_d, N * sizeof(float));
checkCUDAError();
hipMemcpy(*y_d, y, N * sizeof(float), hipMemcpyHostToDevice);
checkCUDAError();
}
/**
* Perform: ELL(A)x = y
*/
void ELL_kernel(int N, int num_cols_per_row , int * indices_d, float * data_d , float * x_d , float * y_d) {
//round grid size N/TILE_SIZE up
dim3 grid((N + TILE_SIZE - 1)/TILE_SIZE, 1, 1);
dim3 block(TILE_SIZE, 1, 1);
k_ell_mat_vec_mm <<< grid, block >>> (N, num_cols_per_row, indices_d, data_d , x_d, y_d);
checkCUDAError();
}
/**
* Destroy ELL matrix
*/
void ELL_destroy(int* indices_d, float* data_d, float* x_d, float* y_d) {
hipFree(indices_d);
hipFree(data_d);
hipFree(x_d);
hipFree(y_d);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z16k_csr_mat_vec_mmiPiS_PfS0_S0_
.globl _Z16k_csr_mat_vec_mmiPiS_PfS0_S0_
.p2align 8
.type _Z16k_csr_mat_vec_mmiPiS_PfS0_S0_,@function
_Z16k_csr_mat_vec_mmiPiS_PfS0_S0_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x3c
s_load_b32 s3, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_6
s_load_b64 s[2:3], s[0:1], 0x8
v_ashrrev_i32_e32 v2, 31, v1
v_mov_b32_e32 v0, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, vcc_lo, s2, v3
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v4, vcc_lo
s_mov_b32 s3, exec_lo
global_load_b64 v[3:4], v[3:4], off
s_waitcnt vmcnt(0)
v_cmpx_lt_i32_e64 v3, v4
s_cbranch_execz .LBB0_5
s_clause 0x1
s_load_b128 s[8:11], s[0:1], 0x10
s_load_b64 s[4:5], s[0:1], 0x20
v_ashrrev_i32_e32 v6, 31, v3
v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v0, 0
s_mov_b32 s6, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[7:8], 2, v[5:6]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v5, vcc_lo, s10, v7
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v6, vcc_lo, s11, v8, vcc_lo
v_add_co_u32 v7, vcc_lo, s8, v7
v_add_co_ci_u32_e32 v8, vcc_lo, s9, v8, vcc_lo
.p2align 6
.LBB0_3:
global_load_b32 v9, v[7:8], off
s_waitcnt vmcnt(0)
v_ashrrev_i32_e32 v10, 31, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[9:10], 2, v[9:10]
v_add_co_u32 v9, vcc_lo, s4, v9
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v10, vcc_lo, s5, v10, vcc_lo
global_load_b32 v11, v[5:6], off
global_load_b32 v9, v[9:10], off
v_add_nc_u32_e32 v3, 1, v3
v_add_co_u32 v5, vcc_lo, v5, 4
v_add_co_ci_u32_e32 v6, vcc_lo, 0, v6, vcc_lo
v_add_co_u32 v7, vcc_lo, v7, 4
v_add_co_ci_u32_e32 v8, vcc_lo, 0, v8, vcc_lo
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v0, v11, v9
v_cmp_ge_i32_e64 s2, v3, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_or_b32 s6, s2, s6
s_and_not1_b32 exec_lo, exec_lo, s6
s_cbranch_execnz .LBB0_3
s_or_b32 exec_lo, exec_lo, s6
.LBB0_5:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
s_or_b32 exec_lo, exec_lo, s3
s_load_b64 s[0:1], s[0:1], 0x28
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v1, vcc_lo, s0, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
global_store_b32 v[1:2], v0, off
.LBB0_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z16k_csr_mat_vec_mmiPiS_PfS0_S0_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 304
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 12
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z16k_csr_mat_vec_mmiPiS_PfS0_S0_, .Lfunc_end0-_Z16k_csr_mat_vec_mmiPiS_PfS0_S0_
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z17k_csr2_mat_vec_mmiPiS_PfS0_S0_
.globl _Z17k_csr2_mat_vec_mmiPiS_PfS0_S0_
.p2align 8
.type _Z17k_csr2_mat_vec_mmiPiS_PfS0_S0_,@function
_Z17k_csr2_mat_vec_mmiPiS_PfS0_S0_:
s_load_b32 s2, s[0:1], 0x3c
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[5:6], null, s15, s3, v[0:1]
s_load_b32 s3, s[0:1], 0x0
v_ashrrev_i32_e32 v1, 31, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshrrev_b32_e32 v1, 27, v1
v_add_nc_u32_e32 v1, v5, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v1, 5, v1
s_waitcnt lgkmcnt(0)
v_cmp_gt_i32_e32 vcc_lo, s3, v1
s_and_saveexec_b32 s3, vcc_lo
s_cbranch_execz .LBB1_11
s_load_b64 s[4:5], s[0:1], 0x8
v_ashrrev_i32_e32 v2, 31, v1
v_dual_mov_b32 v5, 0 :: v_dual_and_b32 v10, 31, v5
v_lshlrev_b32_e32 v9, 2, v0
s_mov_b32 s3, exec_lo
s_delay_alu instid0(VALU_DEP_3)
v_lshlrev_b64 v[3:4], 2, v[1:2]
ds_store_b32 v9, v5
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, vcc_lo, s4, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
global_load_b64 v[3:4], v[3:4], off
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v11, v3, v10
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_lt_i32_e64 v11, v4
s_cbranch_execz .LBB1_5
v_mad_u16 v5, s15, s2, v0
s_clause 0x1
s_load_b128 s[8:11], s[0:1], 0x10
s_load_b64 s[4:5], s[0:1], 0x20
v_ashrrev_i32_e32 v6, 31, v3
s_mov_b32 s6, 0
v_and_b32_e32 v5, 31, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v5, vcc_lo, v3, v5
v_add_co_ci_u32_e32 v6, vcc_lo, 0, v6, vcc_lo
ds_load_b32 v3, v9
v_lshlrev_b64 v[7:8], 2, v[5:6]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v5, vcc_lo, s10, v7
v_add_co_ci_u32_e32 v6, vcc_lo, s11, v8, vcc_lo
v_add_co_u32 v7, vcc_lo, s8, v7
v_add_co_ci_u32_e32 v8, vcc_lo, s9, v8, vcc_lo
.p2align 6
.LBB1_3:
global_load_b32 v12, v[7:8], off
v_add_nc_u32_e32 v11, 32, v11
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_ge_i32_e64 s2, v11, v4
s_or_b32 s6, s2, s6
s_waitcnt vmcnt(0)
v_ashrrev_i32_e32 v13, 31, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[12:13], 2, v[12:13]
v_add_co_u32 v12, vcc_lo, s4, v12
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v13, vcc_lo, s5, v13, vcc_lo
global_load_b32 v14, v[5:6], off
global_load_b32 v12, v[12:13], off
v_add_co_u32 v5, vcc_lo, v5, 0x80
v_add_co_ci_u32_e32 v6, vcc_lo, 0, v6, vcc_lo
v_add_co_u32 v7, vcc_lo, v7, 0x80
v_add_co_ci_u32_e32 v8, vcc_lo, 0, v8, vcc_lo
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v3, v14, v12
s_and_not1_b32 exec_lo, exec_lo, s6
s_cbranch_execnz .LBB1_3
s_or_b32 exec_lo, exec_lo, s6
ds_store_b32 v9, v3
.LBB1_5:
s_or_b32 exec_lo, exec_lo, s3
s_mov_b32 s2, 16
s_branch .LBB1_7
.p2align 6
.LBB1_6:
s_or_b32 exec_lo, exec_lo, s3
s_lshr_b32 s3, s2, 1
s_cmp_lt_u32 s2, 2
s_mov_b32 s2, s3
s_cbranch_scc1 .LBB1_9
.LBB1_7:
s_mov_b32 s3, exec_lo
v_cmpx_gt_u32_e64 s2, v10
s_cbranch_execz .LBB1_6
v_add_lshl_u32 v3, s2, v0, 2
ds_load_b32 v3, v3
ds_load_b32 v4, v9
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v3, v3, v4
ds_store_b32 v9, v3
s_branch .LBB1_6
.LBB1_9:
v_cmp_eq_u32_e32 vcc_lo, 0, v10
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB1_11
s_load_b64 s[0:1], s[0:1], 0x28
ds_load_b32 v3, v9
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v3, off
.LBB1_11:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z17k_csr2_mat_vec_mmiPiS_PfS0_S0_
.amdhsa_group_segment_fixed_size 256
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 304
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 15
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z17k_csr2_mat_vec_mmiPiS_PfS0_S0_, .Lfunc_end1-_Z17k_csr2_mat_vec_mmiPiS_PfS0_S0_
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z16k_ell_mat_vec_mmiiPiPfS0_S0_
.globl _Z16k_ell_mat_vec_mmiiPiPfS0_S0_
.p2align 8
.type _Z16k_ell_mat_vec_mmiiPiPfS0_S0_,@function
_Z16k_ell_mat_vec_mmiiPiPfS0_S0_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x34
s_load_b32 s8, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s8, v1
s_cbranch_execz .LBB2_8
s_load_b32 s9, s[0:1], 0x4
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s9, 1
s_cbranch_scc1 .LBB2_6
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x8
s_load_b64 s[2:3], s[0:1], 0x18
v_mov_b32_e32 v0, 0
v_mov_b32_e32 v2, v1
s_set_inst_prefetch_distance 0x1
s_branch .LBB2_4
.p2align 6
.LBB2_3:
s_or_b32 exec_lo, exec_lo, s10
v_add_nc_u32_e32 v2, s8, v2
s_add_i32 s9, s9, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s9, 0
s_cbranch_scc1 .LBB2_7
.LBB2_4:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
s_mov_b32 s10, exec_lo
v_lshlrev_b64 v[3:4], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v5, vcc_lo, s6, v3
v_add_co_ci_u32_e32 v6, vcc_lo, s7, v4, vcc_lo
global_load_b32 v5, v[5:6], off
s_waitcnt vmcnt(0)
v_cmpx_neq_f32_e32 0, v5
s_cbranch_execz .LBB2_3
v_add_co_u32 v3, vcc_lo, s4, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
global_load_b32 v3, v[3:4], off
s_waitcnt vmcnt(0)
v_ashrrev_i32_e32 v4, 31, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[3:4]
v_add_co_u32 v3, vcc_lo, s2, v3
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v4, vcc_lo
global_load_b32 v3, v[3:4], off
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v0, v5, v3
s_branch .LBB2_3
.LBB2_6:
v_mov_b32_e32 v0, 0
.LBB2_7:
s_set_inst_prefetch_distance 0x2
s_load_b64 s[0:1], s[0:1], 0x20
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v1, vcc_lo, s0, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
global_store_b32 v[1:2], v0, off
.LBB2_8:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z16k_ell_mat_vec_mmiiPiPfS0_S0_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end2:
.size _Z16k_ell_mat_vec_mmiiPiPfS0_S0_, .Lfunc_end2-_Z16k_ell_mat_vec_mmiiPiPfS0_S0_
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z11band_matveciiPfS_S_
.globl _Z11band_matveciiPfS_S_
.p2align 8
.type _Z11band_matveciiPfS_S_,@function
_Z11band_matveciiPfS_S_:
s_load_b32 s2, s[0:1], 0x0
s_lshl_b32 s3, s15, 6
s_mov_b32 s4, exec_lo
v_add_nc_u32_e32 v1, s3, v0
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s2, v1
s_cbranch_execz .LBB3_7
s_load_b32 s8, s[0:1], 0x4
v_mov_b32_e32 v6, 0
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s8, 0
s_cbranch_scc1 .LBB3_6
s_load_b128 s[4:7], s[0:1], 0x8
v_add_nc_u32_e32 v0, s3, v0
s_lshl_b32 s3, s8, 1
v_mov_b32_e32 v6, 0
v_mov_b32_e32 v4, v1
s_max_i32 s3, s3, 0
v_subrev_nc_u32_e32 v2, s8, v0
s_or_b32 s3, s3, 1
s_set_inst_prefetch_distance 0x1
s_branch .LBB3_4
.p2align 6
.LBB3_3:
s_or_b32 exec_lo, exec_lo, s8
v_add_nc_u32_e32 v4, s2, v4
v_add_nc_u32_e32 v2, 1, v2
s_add_i32 s3, s3, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s3, 0
s_cbranch_scc1 .LBB3_6
.LBB3_4:
v_ashrrev_i32_e32 v5, 31, v4
s_mov_b32 s8, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[7:8], 2, v[4:5]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v7, vcc_lo, s4, v7
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v8, vcc_lo, s5, v8, vcc_lo
global_load_b32 v0, v[7:8], off
s_waitcnt vmcnt(0)
v_cmpx_neq_f32_e32 0, v0
s_cbranch_execz .LBB3_3
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[7:8], 2, v[2:3]
v_add_co_u32 v7, vcc_lo, s6, v7
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v8, vcc_lo, s7, v8, vcc_lo
global_load_b32 v3, v[7:8], off
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v6, v0, v3
s_branch .LBB3_3
.LBB3_6:
s_set_inst_prefetch_distance 0x2
s_load_b64 s[0:1], s[0:1], 0x18
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v6, off
.LBB3_7:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11band_matveciiPfS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 32
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end3:
.size _Z11band_matveciiPfS_S_, .Lfunc_end3-_Z11band_matveciiPfS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
- .offset: 48
.size: 4
.value_kind: hidden_block_count_x
- .offset: 52
.size: 4
.value_kind: hidden_block_count_y
- .offset: 56
.size: 4
.value_kind: hidden_block_count_z
- .offset: 60
.size: 2
.value_kind: hidden_group_size_x
- .offset: 62
.size: 2
.value_kind: hidden_group_size_y
- .offset: 64
.size: 2
.value_kind: hidden_group_size_z
- .offset: 66
.size: 2
.value_kind: hidden_remainder_x
- .offset: 68
.size: 2
.value_kind: hidden_remainder_y
- .offset: 70
.size: 2
.value_kind: hidden_remainder_z
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 112
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 304
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z16k_csr_mat_vec_mmiPiS_PfS0_S0_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z16k_csr_mat_vec_mmiPiS_PfS0_S0_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 12
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
- .offset: 48
.size: 4
.value_kind: hidden_block_count_x
- .offset: 52
.size: 4
.value_kind: hidden_block_count_y
- .offset: 56
.size: 4
.value_kind: hidden_block_count_z
- .offset: 60
.size: 2
.value_kind: hidden_group_size_x
- .offset: 62
.size: 2
.value_kind: hidden_group_size_y
- .offset: 64
.size: 2
.value_kind: hidden_group_size_z
- .offset: 66
.size: 2
.value_kind: hidden_remainder_x
- .offset: 68
.size: 2
.value_kind: hidden_remainder_y
- .offset: 70
.size: 2
.value_kind: hidden_remainder_z
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 112
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 256
.kernarg_segment_align: 8
.kernarg_segment_size: 304
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z17k_csr2_mat_vec_mmiPiS_PfS0_S0_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z17k_csr2_mat_vec_mmiPiS_PfS0_S0_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 15
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
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- .address_space: global
.offset: 16
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- .address_space: global
.offset: 24
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.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
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- .offset: 60
.size: 2
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- .offset: 62
.size: 2
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- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z16k_ell_mat_vec_mmiiPiPfS0_S0_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z16k_ell_mat_vec_mmiiPiPfS0_S0_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 32
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11band_matveciiPfS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z11band_matveciiPfS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "stdio.h"
#define TILE_SIZE 64
#define WARP_SIZE 32
extern "C" void CSR_matvec(int N, int nnz, int* start, int* indices, float* data, float* x, float *y, bool bVectorized);
extern "C" void CSR_create(int N, int nnz, int* start, int * indices, float * data , float * x , float * y, int** start_d, int **indices_d, float **data_d, float **x_d, float **y_d);
extern "C" void CSR_kernel(int N, int nnz, int* start_d, int * indices_d, float * data_d , float * x_d , float * y_d, bool bVectorized);
extern "C" void CSR_destroy(int* start_d, int* indices_d, float* data_d, float* x_d, float* y_d);
extern "C" void ELL_create(int N, int num_cols_per_row, int * indices, float * data , float * x , float * y, int **indices_d, float **data_d, float **x_d, float **y_d);
extern "C" void ELL_kernel(int N, int num_cols_per_row , int * indices_d, float * data_d , float * x_d , float * y_d);
extern "C" void ELL_destroy(int* indices_d, float* data_d, float* x_d, float* y_d);
extern "C" void band_create(int N, int num_cols_per_row, float * data , float * x , float * y, float **data_d, float **x_d, float **y_d);
extern "C" void band_kernel(int N, int num_cols_per_row , float * data_d , float * x_d , float * y_d);
extern "C" void band_destroy(float* data_d, float* x_d, float* y_d);
/**
* Custom CUDA error check wrapper.
*/
#define checkCUDAError() do { \
hipError_t error = hipGetLastError(); \
if (error != hipSuccess) { \
printf("(CUDA) %s", hipGetErrorString(error)); \
printf(" (" __FILE__ ":%d)\n", __LINE__); \
}\
} while (0)
/**
* Cuda kernel for: CSR_s(A)x = y
*/
__global__ void k_csr_mat_vec_mm(const int N, int *start, int* indices, float *data, float *x, float* y) {
int row = blockDim.x * blockIdx.x + threadIdx.x ;
if ( row < N ){
float dot = 0;
int row_start = start [ row ];
int row_end = start [ row+1];
for ( int jj = row_start ; jj < row_end ; jj ++) {
dot += data [ jj ] * x [ indices [ jj ]];
}
y[row] = dot ;
}
}
/**
* Cuda kernel for: CSR_v(A)x = y
*/
__global__ void k_csr2_mat_vec_mm(const int N, int *start, int* indices, float *data, float *x, float* y) {
__shared__ float vals[TILE_SIZE];
int thread_id = blockDim.x * blockIdx.x + threadIdx.x;
int warp_id = thread_id / WARP_SIZE;
int lane = thread_id & (WARP_SIZE - 1);
int row = warp_id;
if (row < N) {
int row_start = start[row];
int row_end = start[row + 1];
// compute running sum per thread
vals[threadIdx.x] = 0;
for (int jj = row_start + lane; jj < row_end; jj += WARP_SIZE) {
vals[threadIdx.x] += data[jj] * x[indices[jj]];
}
// parallel reduction in shared memory
for (int d = WARP_SIZE >> 1; d >= 1; d >>= 1) {
if (lane < d) vals[threadIdx.x] += vals[threadIdx.x + d];
}
// first thread in a warp writes the result
if (lane == 0) {
y[row] = vals[threadIdx.x];
}
}
}
/**
* Cuda kernel for: ELL(A)x = y
*/
__global__ void k_ell_mat_vec_mm ( const int N, const int num_cols_per_row , int * indices,
float * data , float * x , float * y ) {
int row = blockDim.x * blockIdx.x + threadIdx.x ;
if ( row < N ){
float dot = 0;
for ( int n = 0; n < num_cols_per_row ; n ++){
int col = indices [ N * n + row ];
float val = data [ N * n + row ];
if ( val != 0)
dot += val * x [ col ];
}
y [ row ] = dot ;
}
}
/**
* Cuda kernel for: Band(A)x = y
*/
__global__ void band_matvec(int N, int k_max,
float* a, float* x, float* y) {
int i = TILE_SIZE * blockIdx.x + threadIdx.x;
if (i < N) {
float dot = 0;
for (int k = 0; k < 2 * k_max + 1; k++) {
float val = a[N * k + i];
int j = i + k - k_max;
if (val != 0) dot += val * x[j];
}
y[i] = dot;
}
}
/**
* Perform: CSR(A)x = y
*/
void CSR_matvec(const int N, const int nnz, int* start, int * indices, float * data , float * x , float * y, const bool bVectorized) {
int *start_d, *indices_d;
float *data_d, *x_d, *y_d;
CSR_create(N, nnz, start, indices, data, x, y, &start_d, &indices_d, &data_d, &x_d, &y_d);
CSR_kernel(N, nnz, start_d, indices_d, data_d, x_d, y_d, bVectorized);
hipMemcpy(y, y_d, N * sizeof(float), hipMemcpyDeviceToHost);
checkCUDAError();
CSR_destroy(start_d, indices_d, data_d, x_d, y_d);
}
/**
* Create CSR matrix
*/
void CSR_create(const int N, const int nnz,
int * start, int * indices, float * data , float * x , float * y,
int ** start_d, int ** indices_d, float **data_d, float **x_d, float **y_d) {
/************************/
/* copy to device */
/************************/
hipMalloc((void **) start_d, (N+1) * sizeof(int));
checkCUDAError();
hipMemcpy(*start_d, start, (N+1) * sizeof(int), hipMemcpyHostToDevice);
checkCUDAError();
hipMalloc((void **) indices_d, nnz * sizeof(int));
checkCUDAError();
hipMemcpy(*indices_d, indices, nnz * sizeof(int), hipMemcpyHostToDevice);
checkCUDAError();
hipMalloc((void **) data_d, nnz * sizeof(float));
checkCUDAError();
hipMemcpy(*data_d, data, nnz * sizeof(float), hipMemcpyHostToDevice);
checkCUDAError();
hipMalloc((void **) x_d, N * sizeof(float));
checkCUDAError();
hipMemcpy(*x_d, x, N * sizeof(float), hipMemcpyHostToDevice);
checkCUDAError();
hipMalloc((void **) y_d, N * sizeof(float));
checkCUDAError();
hipMemcpy(*y_d, y, N * sizeof(float) , hipMemcpyHostToDevice);
checkCUDAError();
}
/**
* Perform: CSR(A)x = y
*/
void CSR_kernel(const int N, const int nnz, int * start_d , int * indices_d, float * data_d , float * x_d , float * y_d, const bool bVectorized) {
if (bVectorized) {
//#threads = #rows * #threads per row (= N * WARP_SIZE)
dim3 grid((N * WARP_SIZE + TILE_SIZE - 1)/TILE_SIZE, 1, 1);
dim3 block(TILE_SIZE, 1, 1);
k_csr2_mat_vec_mm <<< grid, block >>> (N, start_d, indices_d, data_d, x_d, y_d);
} else {
//#threads = #rows (= N)
dim3 grid((N + TILE_SIZE - 1)/TILE_SIZE, 1, 1);
dim3 block(TILE_SIZE, 1, 1);
k_csr_mat_vec_mm <<< grid, block >>> (N, start_d, indices_d, data_d, x_d, y_d);
}
checkCUDAError();
}
/**
* Destroy CSR matrix
*/
void CSR_destroy(int* start_d, int* indices_d, float* data_d, float* x_d, float* y_d) {
hipFree(start_d);
hipFree(indices_d);
hipFree(data_d);
hipFree(x_d);
hipFree(y_d);
}
/**
* Create band matrix
*/
void band_create(const int N, const int num_cols_per_row,
float * data , float * x , float * y,
float **data_d, float **x_d, float **y_d) {
hipMalloc((void **) data_d, N * num_cols_per_row * sizeof(float));
checkCUDAError();
hipMemcpy(*data_d, data, N * num_cols_per_row * sizeof(float), hipMemcpyHostToDevice);
checkCUDAError();
hipMalloc((void **) x_d, N * sizeof(float));
checkCUDAError();
hipMemcpy(*x_d, x, N * sizeof(float), hipMemcpyHostToDevice);
checkCUDAError();
hipMalloc((void **) y_d, N * sizeof(float));
checkCUDAError();
hipMemcpy(*y_d, y, N * sizeof(float), hipMemcpyHostToDevice);
checkCUDAError();
}
/**
* Perform: band(A)x = y
*/
void band_kernel(int N, int k_max , float * data_d , float * x_d , float * y_d) {
//#threads = #rows (= N)
dim3 grid((N + TILE_SIZE - 1)/TILE_SIZE, 1, 1);
dim3 block(TILE_SIZE, 1, 1);
band_matvec <<< grid, block >>> (N, k_max, data_d , x_d, y_d);
checkCUDAError();
}
/**
* Destroy ELL matrix
*/
void band_destroy(float* data_d, float* x_d, float* y_d) {
hipFree(data_d);
hipFree(x_d);
hipFree(y_d);
}
/**
* Create ELL matrix
*/
void ELL_create(const int N, const int num_cols_per_row,
int * indices, float * data , float * x , float * y,
int ** indices_d, float **data_d, float **x_d, float **y_d) {
hipMalloc((void **) indices_d, N * num_cols_per_row * sizeof(int));
checkCUDAError();
hipMemcpy(*indices_d, indices, N * num_cols_per_row * sizeof(int), hipMemcpyHostToDevice);
checkCUDAError();
hipMalloc((void **) data_d, N * num_cols_per_row * sizeof(float));
checkCUDAError();
hipMemcpy(*data_d, data, N * num_cols_per_row * sizeof(float), hipMemcpyHostToDevice);
checkCUDAError();
hipMalloc((void **) x_d, N * sizeof(float));
checkCUDAError();
hipMemcpy(*x_d, x, N * sizeof(float), hipMemcpyHostToDevice);
checkCUDAError();
hipMalloc((void **) y_d, N * sizeof(float));
checkCUDAError();
hipMemcpy(*y_d, y, N * sizeof(float), hipMemcpyHostToDevice);
checkCUDAError();
}
/**
* Perform: ELL(A)x = y
*/
void ELL_kernel(int N, int num_cols_per_row , int * indices_d, float * data_d , float * x_d , float * y_d) {
//round grid size N/TILE_SIZE up
dim3 grid((N + TILE_SIZE - 1)/TILE_SIZE, 1, 1);
dim3 block(TILE_SIZE, 1, 1);
k_ell_mat_vec_mm <<< grid, block >>> (N, num_cols_per_row, indices_d, data_d , x_d, y_d);
checkCUDAError();
}
/**
* Destroy ELL matrix
*/
void ELL_destroy(int* indices_d, float* data_d, float* x_d, float* y_d) {
hipFree(indices_d);
hipFree(data_d);
hipFree(x_d);
hipFree(y_d);
} | .text
.file "kernels.hip"
.globl _Z31__device_stub__k_csr_mat_vec_mmiPiS_PfS0_S0_ # -- Begin function _Z31__device_stub__k_csr_mat_vec_mmiPiS_PfS0_S0_
.p2align 4, 0x90
.type _Z31__device_stub__k_csr_mat_vec_mmiPiS_PfS0_S0_,@function
_Z31__device_stub__k_csr_mat_vec_mmiPiS_PfS0_S0_: # @_Z31__device_stub__k_csr_mat_vec_mmiPiS_PfS0_S0_
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 4(%rsp)
movq %rsi, 88(%rsp)
movq %rdx, 80(%rsp)
movq %rcx, 72(%rsp)
movq %r8, 64(%rsp)
movq %r9, 56(%rsp)
leaq 4(%rsp), %rax
movq %rax, 96(%rsp)
leaq 88(%rsp), %rax
movq %rax, 104(%rsp)
leaq 80(%rsp), %rax
movq %rax, 112(%rsp)
leaq 72(%rsp), %rax
movq %rax, 120(%rsp)
leaq 64(%rsp), %rax
movq %rax, 128(%rsp)
leaq 56(%rsp), %rax
movq %rax, 136(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z16k_csr_mat_vec_mmiPiS_PfS0_S0_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z31__device_stub__k_csr_mat_vec_mmiPiS_PfS0_S0_, .Lfunc_end0-_Z31__device_stub__k_csr_mat_vec_mmiPiS_PfS0_S0_
.cfi_endproc
# -- End function
.globl _Z32__device_stub__k_csr2_mat_vec_mmiPiS_PfS0_S0_ # -- Begin function _Z32__device_stub__k_csr2_mat_vec_mmiPiS_PfS0_S0_
.p2align 4, 0x90
.type _Z32__device_stub__k_csr2_mat_vec_mmiPiS_PfS0_S0_,@function
_Z32__device_stub__k_csr2_mat_vec_mmiPiS_PfS0_S0_: # @_Z32__device_stub__k_csr2_mat_vec_mmiPiS_PfS0_S0_
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 4(%rsp)
movq %rsi, 88(%rsp)
movq %rdx, 80(%rsp)
movq %rcx, 72(%rsp)
movq %r8, 64(%rsp)
movq %r9, 56(%rsp)
leaq 4(%rsp), %rax
movq %rax, 96(%rsp)
leaq 88(%rsp), %rax
movq %rax, 104(%rsp)
leaq 80(%rsp), %rax
movq %rax, 112(%rsp)
leaq 72(%rsp), %rax
movq %rax, 120(%rsp)
leaq 64(%rsp), %rax
movq %rax, 128(%rsp)
leaq 56(%rsp), %rax
movq %rax, 136(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z17k_csr2_mat_vec_mmiPiS_PfS0_S0_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end1:
.size _Z32__device_stub__k_csr2_mat_vec_mmiPiS_PfS0_S0_, .Lfunc_end1-_Z32__device_stub__k_csr2_mat_vec_mmiPiS_PfS0_S0_
.cfi_endproc
# -- End function
.globl _Z31__device_stub__k_ell_mat_vec_mmiiPiPfS0_S0_ # -- Begin function _Z31__device_stub__k_ell_mat_vec_mmiiPiPfS0_S0_
.p2align 4, 0x90
.type _Z31__device_stub__k_ell_mat_vec_mmiiPiPfS0_S0_,@function
_Z31__device_stub__k_ell_mat_vec_mmiiPiPfS0_S0_: # @_Z31__device_stub__k_ell_mat_vec_mmiiPiPfS0_S0_
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 12(%rsp)
movl %esi, 8(%rsp)
movq %rdx, 88(%rsp)
movq %rcx, 80(%rsp)
movq %r8, 72(%rsp)
movq %r9, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 88(%rsp), %rax
movq %rax, 112(%rsp)
leaq 80(%rsp), %rax
movq %rax, 120(%rsp)
leaq 72(%rsp), %rax
movq %rax, 128(%rsp)
leaq 64(%rsp), %rax
movq %rax, 136(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z16k_ell_mat_vec_mmiiPiPfS0_S0_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end2:
.size _Z31__device_stub__k_ell_mat_vec_mmiiPiPfS0_S0_, .Lfunc_end2-_Z31__device_stub__k_ell_mat_vec_mmiiPiPfS0_S0_
.cfi_endproc
# -- End function
.globl _Z26__device_stub__band_matveciiPfS_S_ # -- Begin function _Z26__device_stub__band_matveciiPfS_S_
.p2align 4, 0x90
.type _Z26__device_stub__band_matveciiPfS_S_,@function
_Z26__device_stub__band_matveciiPfS_S_: # @_Z26__device_stub__band_matveciiPfS_S_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 4(%rsp)
movl %esi, (%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
leaq 4(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
leaq 72(%rsp), %rax
movq %rax, 96(%rsp)
leaq 64(%rsp), %rax
movq %rax, 104(%rsp)
leaq 56(%rsp), %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z11band_matveciiPfS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end3:
.size _Z26__device_stub__band_matveciiPfS_S_, .Lfunc_end3-_Z26__device_stub__band_matveciiPfS_S_
.cfi_endproc
# -- End function
.globl CSR_matvec # -- Begin function CSR_matvec
.p2align 4, 0x90
.type CSR_matvec,@function
CSR_matvec: # @CSR_matvec
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $48, %rsp
.cfi_def_cfa_offset 96
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %edi, %ebp
movzbl 104(%rsp), %r14d
movq 96(%rsp), %rbx
leaq 8(%rsp), %rax
leaq 16(%rsp), %r10
leaq 24(%rsp), %r11
leaq 32(%rsp), %r15
leaq 40(%rsp), %r12
pushq %rax
.cfi_adjust_cfa_offset 8
pushq %r10
.cfi_adjust_cfa_offset 8
pushq %r11
.cfi_adjust_cfa_offset 8
pushq %r15
.cfi_adjust_cfa_offset 8
pushq %r12
.cfi_adjust_cfa_offset 8
pushq %rbx
.cfi_adjust_cfa_offset 8
callq CSR_create
addq $48, %rsp
.cfi_adjust_cfa_offset -48
movq 40(%rsp), %rdx
movq 32(%rsp), %rcx
movq 24(%rsp), %r8
movq 16(%rsp), %r9
movzbl %r14b, %eax
movl %ebp, %edi
pushq %rax
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq CSR_kernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movq 8(%rsp), %rsi
movslq %ebp, %rdx
shlq $2, %rdx
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
callq hipGetLastError
testl %eax, %eax
je .LBB4_2
# %bb.1:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
movl $.L.str.1, %edi
movl $138, %esi
xorl %eax, %eax
callq printf
.LBB4_2:
movq 40(%rsp), %rdi
movq 32(%rsp), %rbx
movq 24(%rsp), %r14
movq 16(%rsp), %r15
movq 8(%rsp), %r12
callq hipFree
movq %rbx, %rdi
callq hipFree
movq %r14, %rdi
callq hipFree
movq %r15, %rdi
callq hipFree
movq %r12, %rdi
callq hipFree
addq $48, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end4:
.size CSR_matvec, .Lfunc_end4-CSR_matvec
.cfi_endproc
# -- End function
.globl CSR_create # -- Begin function CSR_create
.p2align 4, 0x90
.type CSR_create,@function
CSR_create: # @CSR_create
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $56, %rsp
.cfi_def_cfa_offset 112
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %r9, 32(%rsp) # 8-byte Spill
movq %r8, 16(%rsp) # 8-byte Spill
movq %rcx, (%rsp) # 8-byte Spill
movq %rdx, %r13
movl %esi, %ebp
movq 152(%rsp), %rax
movq %rax, 48(%rsp) # 8-byte Spill
movq 144(%rsp), %rax
movq %rax, 24(%rsp) # 8-byte Spill
movq 136(%rsp), %rax
movq %rax, 8(%rsp) # 8-byte Spill
movq 128(%rsp), %rbx
movq 120(%rsp), %r15
movq 112(%rsp), %rax
movq %rax, 40(%rsp) # 8-byte Spill
movslq %edi, %r14
leaq 4(,%r14,4), %r12
movq %r15, %rdi
movq %r12, %rsi
callq hipMalloc
callq hipGetLastError
testl %eax, %eax
je .LBB5_2
# %bb.1:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
movl $.L.str.1, %edi
movl $156, %esi
xorl %eax, %eax
callq printf
.LBB5_2:
movq (%r15), %rdi
movq %r13, %rsi
movq %r12, %rdx
movl $1, %ecx
callq hipMemcpy
callq hipGetLastError
testl %eax, %eax
je .LBB5_4
# %bb.3:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
movl $.L.str.1, %edi
movl $158, %esi
xorl %eax, %eax
callq printf
.LBB5_4:
movslq %ebp, %rbp
shlq $2, %rbp
movq %rbx, %rdi
movq %rbp, %rsi
callq hipMalloc
callq hipGetLastError
testl %eax, %eax
movq 24(%rsp), %r15 # 8-byte Reload
movq 8(%rsp), %r12 # 8-byte Reload
je .LBB5_6
# %bb.5:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
movl $.L.str.1, %edi
movl $161, %esi
xorl %eax, %eax
callq printf
.LBB5_6:
movq (%rbx), %rdi
movq (%rsp), %rsi # 8-byte Reload
movq %rbp, %rdx
movl $1, %ecx
callq hipMemcpy
callq hipGetLastError
testl %eax, %eax
je .LBB5_8
# %bb.7:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
movl $.L.str.1, %edi
movl $163, %esi
xorl %eax, %eax
callq printf
.LBB5_8:
movq %r12, %rdi
movq %rbp, %rsi
callq hipMalloc
callq hipGetLastError
testl %eax, %eax
movq 48(%rsp), %rbx # 8-byte Reload
je .LBB5_10
# %bb.9:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
movl $.L.str.1, %edi
movl $166, %esi
xorl %eax, %eax
callq printf
.LBB5_10:
movq (%r12), %rdi
movq 16(%rsp), %rsi # 8-byte Reload
movq %rbp, %rdx
movl $1, %ecx
callq hipMemcpy
callq hipGetLastError
testl %eax, %eax
je .LBB5_12
# %bb.11:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
movl $.L.str.1, %edi
movl $168, %esi
xorl %eax, %eax
callq printf
.LBB5_12:
shlq $2, %r14
movq %r15, %rdi
movq %r14, %rsi
callq hipMalloc
callq hipGetLastError
testl %eax, %eax
je .LBB5_14
# %bb.13:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
movl $.L.str.1, %edi
movl $171, %esi
xorl %eax, %eax
callq printf
.LBB5_14:
movq (%r15), %rdi
movq 32(%rsp), %rsi # 8-byte Reload
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
callq hipGetLastError
testl %eax, %eax
je .LBB5_16
# %bb.15:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
movl $.L.str.1, %edi
movl $173, %esi
xorl %eax, %eax
callq printf
.LBB5_16:
movq %rbx, %rdi
movq %r14, %rsi
callq hipMalloc
callq hipGetLastError
testl %eax, %eax
je .LBB5_18
# %bb.17:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
movl $.L.str.1, %edi
movl $176, %esi
xorl %eax, %eax
callq printf
.LBB5_18:
movq (%rbx), %rdi
movq 40(%rsp), %rsi # 8-byte Reload
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
callq hipGetLastError
testl %eax, %eax
je .LBB5_19
# %bb.20:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
movl $.L.str.1, %edi
movl $178, %esi
xorl %eax, %eax
addq $56, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
jmp printf # TAILCALL
.LBB5_19:
.cfi_def_cfa_offset 112
addq $56, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end5:
.size CSR_create, .Lfunc_end5-CSR_create
.cfi_endproc
# -- End function
.globl CSR_kernel # -- Begin function CSR_kernel
.p2align 4, 0x90
.type CSR_kernel,@function
CSR_kernel: # @CSR_kernel
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $152, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %r9, %rbx
movq %r8, %r14
movq %rcx, %r15
movq %rdx, %r12
movl %edi, %r13d
movq 208(%rsp), %rbp
movabsq $4294967296, %rdx # imm = 0x100000000
cmpb $0, 216(%rsp)
je .LBB6_3
# %bb.1:
movl %r13d, %edi
shll $5, %edi
leal 63(%rdi), %eax
addl $126, %edi
testl %eax, %eax
cmovnsl %eax, %edi
sarl $6, %edi
orq %rdx, %rdi
addq $64, %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB6_6
# %bb.2:
movl %r13d, 4(%rsp)
movq %r12, 88(%rsp)
movq %r15, 80(%rsp)
movq %r14, 72(%rsp)
movq %rbx, 64(%rsp)
movq %rbp, 56(%rsp)
leaq 4(%rsp), %rax
movq %rax, 96(%rsp)
leaq 88(%rsp), %rax
movq %rax, 104(%rsp)
leaq 80(%rsp), %rax
movq %rax, 112(%rsp)
leaq 72(%rsp), %rax
movq %rax, 120(%rsp)
leaq 64(%rsp), %rax
movq %rax, 128(%rsp)
leaq 56(%rsp), %rax
movq %rax, 136(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z17k_csr2_mat_vec_mmiPiS_PfS0_S0_, %edi
jmp .LBB6_5
.LBB6_3:
leal 63(%r13), %eax
leal 126(%r13), %edi
testl %eax, %eax
cmovnsl %eax, %edi
sarl $6, %edi
orq %rdx, %rdi
addq $64, %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB6_6
# %bb.4:
movl %r13d, 4(%rsp)
movq %r12, 88(%rsp)
movq %r15, 80(%rsp)
movq %r14, 72(%rsp)
movq %rbx, 64(%rsp)
movq %rbp, 56(%rsp)
leaq 4(%rsp), %rax
movq %rax, 96(%rsp)
leaq 88(%rsp), %rax
movq %rax, 104(%rsp)
leaq 80(%rsp), %rax
movq %rax, 112(%rsp)
leaq 72(%rsp), %rax
movq %rax, 120(%rsp)
leaq 64(%rsp), %rax
movq %rax, 128(%rsp)
leaq 56(%rsp), %rax
movq %rax, 136(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z16k_csr_mat_vec_mmiPiS_PfS0_S0_, %edi
.LBB6_5:
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB6_6:
callq hipGetLastError
testl %eax, %eax
je .LBB6_8
# %bb.7:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
movl $.L.str.1, %edi
movl $199, %esi
xorl %eax, %eax
callq printf
.LBB6_8:
addq $152, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end6:
.size CSR_kernel, .Lfunc_end6-CSR_kernel
.cfi_endproc
# -- End function
.globl CSR_destroy # -- Begin function CSR_destroy
.p2align 4, 0x90
.type CSR_destroy,@function
CSR_destroy: # @CSR_destroy
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
pushq %rax
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %r8, %rbx
movq %rcx, %r14
movq %rdx, %r15
movq %rsi, %r12
callq hipFree
movq %r12, %rdi
callq hipFree
movq %r15, %rdi
callq hipFree
movq %r14, %rdi
callq hipFree
movq %rbx, %rdi
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
jmp hipFree # TAILCALL
.Lfunc_end7:
.size CSR_destroy, .Lfunc_end7-CSR_destroy
.cfi_endproc
# -- End function
.globl band_create # -- Begin function band_create
.p2align 4, 0x90
.type band_create,@function
band_create: # @band_create
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $24, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %r9, %rbx
movq %r8, 16(%rsp) # 8-byte Spill
movq %rcx, 8(%rsp) # 8-byte Spill
movq %rdx, %r13
movl %edi, %ebp
movq 88(%rsp), %r14
movq 80(%rsp), %r12
imull %edi, %esi
movslq %esi, %r15
shlq $2, %r15
movq %r9, %rdi
movq %r15, %rsi
callq hipMalloc
callq hipGetLastError
testl %eax, %eax
je .LBB8_2
# %bb.1:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
movl $.L.str.1, %edi
movl $221, %esi
xorl %eax, %eax
callq printf
.LBB8_2:
movq (%rbx), %rdi
movq %r13, %rsi
movq %r15, %rdx
movl $1, %ecx
callq hipMemcpy
callq hipGetLastError
testl %eax, %eax
je .LBB8_4
# %bb.3:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
movl $.L.str.1, %edi
movl $223, %esi
xorl %eax, %eax
callq printf
.LBB8_4:
movslq %ebp, %r13
shlq $2, %r13
movq %r12, %rdi
movq %r13, %rsi
callq hipMalloc
callq hipGetLastError
testl %eax, %eax
je .LBB8_6
# %bb.5:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
movl $.L.str.1, %edi
movl $226, %esi
xorl %eax, %eax
callq printf
.LBB8_6:
movq (%r12), %rdi
movq 8(%rsp), %rsi # 8-byte Reload
movq %r13, %rdx
movl $1, %ecx
callq hipMemcpy
callq hipGetLastError
testl %eax, %eax
je .LBB8_8
# %bb.7:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
movl $.L.str.1, %edi
movl $228, %esi
xorl %eax, %eax
callq printf
.LBB8_8:
movq %r14, %rdi
movq %r13, %rsi
callq hipMalloc
callq hipGetLastError
testl %eax, %eax
je .LBB8_10
# %bb.9:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
movl $.L.str.1, %edi
movl $231, %esi
xorl %eax, %eax
callq printf
.LBB8_10:
movq (%r14), %rdi
movq 16(%rsp), %rsi # 8-byte Reload
movq %r13, %rdx
movl $1, %ecx
callq hipMemcpy
callq hipGetLastError
testl %eax, %eax
je .LBB8_11
# %bb.12:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
movl $.L.str.1, %edi
movl $233, %esi
xorl %eax, %eax
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
jmp printf # TAILCALL
.LBB8_11:
.cfi_def_cfa_offset 80
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end8:
.size band_create, .Lfunc_end8-band_create
.cfi_endproc
# -- End function
.globl band_kernel # -- Begin function band_kernel
.p2align 4, 0x90
.type band_kernel,@function
band_kernel: # @band_kernel
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $128, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %r8, %rbx
movq %rcx, %r14
movq %rdx, %r15
movl %esi, %ebp
movl %edi, %r12d
leal 63(%r12), %eax
leal 126(%r12), %edi
testl %eax, %eax
cmovnsl %eax, %edi
sarl $6, %edi
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %rdi
orq $64, %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB9_2
# %bb.1:
movl %r12d, 4(%rsp)
movl %ebp, (%rsp)
movq %r15, 72(%rsp)
movq %r14, 64(%rsp)
movq %rbx, 56(%rsp)
leaq 4(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
leaq 72(%rsp), %rax
movq %rax, 96(%rsp)
leaq 64(%rsp), %rax
movq %rax, 104(%rsp)
leaq 56(%rsp), %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z11band_matveciiPfS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB9_2:
callq hipGetLastError
testl %eax, %eax
je .LBB9_4
# %bb.3:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
movl $.L.str.1, %edi
movl $247, %esi
xorl %eax, %eax
callq printf
.LBB9_4:
addq $128, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end9:
.size band_kernel, .Lfunc_end9-band_kernel
.cfi_endproc
# -- End function
.globl band_destroy # -- Begin function band_destroy
.p2align 4, 0x90
.type band_destroy,@function
band_destroy: # @band_destroy
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movq %rdx, %rbx
movq %rsi, %r14
callq hipFree
movq %r14, %rdi
callq hipFree
movq %rbx, %rdi
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
jmp hipFree # TAILCALL
.Lfunc_end10:
.size band_destroy, .Lfunc_end10-band_destroy
.cfi_endproc
# -- End function
.globl ELL_create # -- Begin function ELL_create
.p2align 4, 0x90
.type ELL_create,@function
ELL_create: # @ELL_create
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $40, %rsp
.cfi_def_cfa_offset 96
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %r9, 32(%rsp) # 8-byte Spill
movq %r8, 24(%rsp) # 8-byte Spill
movq %rcx, 8(%rsp) # 8-byte Spill
movq %rdx, %r14
movl %edi, %ebp
movq 120(%rsp), %r12
movq 112(%rsp), %rax
movq %rax, 16(%rsp) # 8-byte Spill
movq 104(%rsp), %r15
movq 96(%rsp), %r13
imull %edi, %esi
movslq %esi, %rbx
shlq $2, %rbx
movq %r13, %rdi
movq %rbx, %rsi
callq hipMalloc
callq hipGetLastError
testl %eax, %eax
je .LBB11_2
# %bb.1:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
movl $.L.str.1, %edi
movl $268, %esi # imm = 0x10C
xorl %eax, %eax
callq printf
.LBB11_2:
movq (%r13), %rdi
movq %r14, %rsi
movq %rbx, %rdx
movl $1, %ecx
callq hipMemcpy
callq hipGetLastError
testl %eax, %eax
je .LBB11_4
# %bb.3:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
movl $.L.str.1, %edi
movl $270, %esi # imm = 0x10E
xorl %eax, %eax
callq printf
.LBB11_4:
movq %r15, %rdi
movq %rbx, %rsi
callq hipMalloc
callq hipGetLastError
testl %eax, %eax
je .LBB11_6
# %bb.5:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
movl $.L.str.1, %edi
movl $273, %esi # imm = 0x111
xorl %eax, %eax
callq printf
.LBB11_6:
movq (%r15), %rdi
movq 8(%rsp), %rsi # 8-byte Reload
movq %rbx, %rdx
movl $1, %ecx
callq hipMemcpy
callq hipGetLastError
testl %eax, %eax
je .LBB11_8
# %bb.7:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
movl $.L.str.1, %edi
movl $275, %esi # imm = 0x113
xorl %eax, %eax
callq printf
.LBB11_8:
movslq %ebp, %rbx
shlq $2, %rbx
movq 16(%rsp), %r15 # 8-byte Reload
movq %r15, %rdi
movq %rbx, %rsi
callq hipMalloc
callq hipGetLastError
testl %eax, %eax
je .LBB11_10
# %bb.9:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
movl $.L.str.1, %edi
movl $278, %esi # imm = 0x116
xorl %eax, %eax
callq printf
.LBB11_10:
movq (%r15), %rdi
movq 24(%rsp), %rsi # 8-byte Reload
movq %rbx, %rdx
movl $1, %ecx
callq hipMemcpy
callq hipGetLastError
testl %eax, %eax
je .LBB11_12
# %bb.11:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
movl $.L.str.1, %edi
movl $280, %esi # imm = 0x118
xorl %eax, %eax
callq printf
.LBB11_12:
movq %r12, %rdi
movq %rbx, %rsi
callq hipMalloc
callq hipGetLastError
testl %eax, %eax
je .LBB11_14
# %bb.13:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
movl $.L.str.1, %edi
movl $283, %esi # imm = 0x11B
xorl %eax, %eax
callq printf
.LBB11_14:
movq (%r12), %rdi
movq 32(%rsp), %rsi # 8-byte Reload
movq %rbx, %rdx
movl $1, %ecx
callq hipMemcpy
callq hipGetLastError
testl %eax, %eax
je .LBB11_15
# %bb.16:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
movl $.L.str.1, %edi
movl $285, %esi # imm = 0x11D
xorl %eax, %eax
addq $40, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
jmp printf # TAILCALL
.LBB11_15:
.cfi_def_cfa_offset 96
addq $40, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end11:
.size ELL_create, .Lfunc_end11-ELL_create
.cfi_endproc
# -- End function
.globl ELL_kernel # -- Begin function ELL_kernel
.p2align 4, 0x90
.type ELL_kernel,@function
ELL_kernel: # @ELL_kernel
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $152, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %r9, %rbx
movq %r8, %r14
movq %rcx, %r15
movq %rdx, %r12
movl %esi, %ebp
movl %edi, %r13d
leal 63(%r13), %eax
leal 126(%r13), %edi
testl %eax, %eax
cmovnsl %eax, %edi
sarl $6, %edi
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %rdi
orq $64, %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB12_2
# %bb.1:
movl %r13d, 12(%rsp)
movl %ebp, 8(%rsp)
movq %r12, 88(%rsp)
movq %r15, 80(%rsp)
movq %r14, 72(%rsp)
movq %rbx, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 88(%rsp), %rax
movq %rax, 112(%rsp)
leaq 80(%rsp), %rax
movq %rax, 120(%rsp)
leaq 72(%rsp), %rax
movq %rax, 128(%rsp)
leaq 64(%rsp), %rax
movq %rax, 136(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z16k_ell_mat_vec_mmiiPiPfS0_S0_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB12_2:
callq hipGetLastError
testl %eax, %eax
je .LBB12_4
# %bb.3:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
movl $.L.str.1, %edi
movl $297, %esi # imm = 0x129
xorl %eax, %eax
callq printf
.LBB12_4:
addq $152, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end12:
.size ELL_kernel, .Lfunc_end12-ELL_kernel
.cfi_endproc
# -- End function
.globl ELL_destroy # -- Begin function ELL_destroy
.p2align 4, 0x90
.type ELL_destroy,@function
ELL_destroy: # @ELL_destroy
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rcx, %rbx
movq %rdx, %r14
movq %rsi, %r15
callq hipFree
movq %r15, %rdi
callq hipFree
movq %r14, %rdi
callq hipFree
movq %rbx, %rdi
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
jmp hipFree # TAILCALL
.Lfunc_end13:
.size ELL_destroy, .Lfunc_end13-ELL_destroy
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB14_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB14_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z16k_csr_mat_vec_mmiPiS_PfS0_S0_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z17k_csr2_mat_vec_mmiPiS_PfS0_S0_, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z16k_ell_mat_vec_mmiiPiPfS0_S0_, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11band_matveciiPfS_S_, %esi
movl $.L__unnamed_4, %edx
movl $.L__unnamed_4, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end14:
.size __hip_module_ctor, .Lfunc_end14-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB15_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB15_2:
retq
.Lfunc_end15:
.size __hip_module_dtor, .Lfunc_end15-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z16k_csr_mat_vec_mmiPiS_PfS0_S0_,@object # @_Z16k_csr_mat_vec_mmiPiS_PfS0_S0_
.section .rodata,"a",@progbits
.globl _Z16k_csr_mat_vec_mmiPiS_PfS0_S0_
.p2align 3, 0x0
_Z16k_csr_mat_vec_mmiPiS_PfS0_S0_:
.quad _Z31__device_stub__k_csr_mat_vec_mmiPiS_PfS0_S0_
.size _Z16k_csr_mat_vec_mmiPiS_PfS0_S0_, 8
.type _Z17k_csr2_mat_vec_mmiPiS_PfS0_S0_,@object # @_Z17k_csr2_mat_vec_mmiPiS_PfS0_S0_
.globl _Z17k_csr2_mat_vec_mmiPiS_PfS0_S0_
.p2align 3, 0x0
_Z17k_csr2_mat_vec_mmiPiS_PfS0_S0_:
.quad _Z32__device_stub__k_csr2_mat_vec_mmiPiS_PfS0_S0_
.size _Z17k_csr2_mat_vec_mmiPiS_PfS0_S0_, 8
.type _Z16k_ell_mat_vec_mmiiPiPfS0_S0_,@object # @_Z16k_ell_mat_vec_mmiiPiPfS0_S0_
.globl _Z16k_ell_mat_vec_mmiiPiPfS0_S0_
.p2align 3, 0x0
_Z16k_ell_mat_vec_mmiiPiPfS0_S0_:
.quad _Z31__device_stub__k_ell_mat_vec_mmiiPiPfS0_S0_
.size _Z16k_ell_mat_vec_mmiiPiPfS0_S0_, 8
.type _Z11band_matveciiPfS_S_,@object # @_Z11band_matveciiPfS_S_
.globl _Z11band_matveciiPfS_S_
.p2align 3, 0x0
_Z11band_matveciiPfS_S_:
.quad _Z26__device_stub__band_matveciiPfS_S_
.size _Z11band_matveciiPfS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "(CUDA) %s"
.size .L.str, 10
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz " (/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/PhuNH/hpc-aa/master/t4/kernels.hip:%d)\n"
.size .L.str.1, 99
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z16k_csr_mat_vec_mmiPiS_PfS0_S0_"
.size .L__unnamed_1, 34
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z17k_csr2_mat_vec_mmiPiS_PfS0_S0_"
.size .L__unnamed_2, 35
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z16k_ell_mat_vec_mmiiPiPfS0_S0_"
.size .L__unnamed_3, 33
.type .L__unnamed_4,@object # @3
.L__unnamed_4:
.asciz "_Z11band_matveciiPfS_S_"
.size .L__unnamed_4, 24
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z31__device_stub__k_csr_mat_vec_mmiPiS_PfS0_S0_
.addrsig_sym _Z32__device_stub__k_csr2_mat_vec_mmiPiS_PfS0_S0_
.addrsig_sym _Z31__device_stub__k_ell_mat_vec_mmiiPiPfS0_S0_
.addrsig_sym _Z26__device_stub__band_matveciiPfS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z16k_csr_mat_vec_mmiPiS_PfS0_S0_
.addrsig_sym _Z17k_csr2_mat_vec_mmiPiS_PfS0_S0_
.addrsig_sym _Z16k_ell_mat_vec_mmiiPiPfS0_S0_
.addrsig_sym _Z11band_matveciiPfS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#define BLOCK_SIZE_X 128
__global__
void warmUp(float* out, float* in, int count) {
float* local_array = in + (blockIdx.x * blockDim.x);
if (threadIdx.x == 0) { out[blockIdx.x] = local_array[0]; }
}
__global__
void sumUnrollGlobal(float* out, float* in, int count) {
if ((blockIdx.x * blockDim.x) + threadIdx.x > count) return;
float* local_array = in + (blockIdx.x * blockDim.x);
if (blockDim.x >= 1024 && threadIdx.x < 512) { local_array[threadIdx.x] += local_array[threadIdx.x + 512]; }
__syncthreads();
if (blockDim.x >= 512 && threadIdx.x < 256) { local_array[threadIdx.x] += local_array[threadIdx.x + 256]; }
__syncthreads();
if (blockDim.x >= 256 && threadIdx.x < 128) { local_array[threadIdx.x] += local_array[threadIdx.x + 128]; }
__syncthreads();
if (blockDim.x >= 128 && threadIdx.x < 64) { local_array[threadIdx.x] += local_array[threadIdx.x + 64]; }
__syncthreads();
if (threadIdx.x < 32) {
volatile float* v_local_array = local_array;
v_local_array[threadIdx.x] += v_local_array[threadIdx.x + 32];
v_local_array[threadIdx.x] += v_local_array[threadIdx.x + 16];
v_local_array[threadIdx.x] += v_local_array[threadIdx.x + 8];
v_local_array[threadIdx.x] += v_local_array[threadIdx.x + 4];
v_local_array[threadIdx.x] += v_local_array[threadIdx.x + 2];
v_local_array[threadIdx.x] += v_local_array[threadIdx.x + 1];
}
if (threadIdx.x == 0) { out[blockIdx.x] = local_array[0]; }
}
__global__
void sumUnrollShared(float* out, float* in, int count) {
if ((blockIdx.x * blockDim.x) + threadIdx.x > count) return;
float* local_array = in + (blockIdx.x * blockDim.x);
__shared__ float shared_array[BLOCK_SIZE_X];
shared_array[threadIdx.x] = local_array[threadIdx.x];
__syncthreads();
if (blockDim.x >= 1024 && threadIdx.x < 512) { shared_array[threadIdx.x] += shared_array[threadIdx.x + 512]; }
__syncthreads();
if (blockDim.x >= 512 && threadIdx.x < 256) { shared_array[threadIdx.x] += shared_array[threadIdx.x + 256]; }
__syncthreads();
if (blockDim.x >= 256 && threadIdx.x < 128) { shared_array[threadIdx.x] += shared_array[threadIdx.x + 128]; }
__syncthreads();
if (blockDim.x >= 128 && threadIdx.x < 64) { shared_array[threadIdx.x] += shared_array[threadIdx.x + 64]; }
__syncthreads();
if (threadIdx.x < 32) {
volatile float* v_local_array = shared_array;
v_local_array[threadIdx.x] += v_local_array[threadIdx.x + 32];
v_local_array[threadIdx.x] += v_local_array[threadIdx.x + 16];
v_local_array[threadIdx.x] += v_local_array[threadIdx.x + 8];
v_local_array[threadIdx.x] += v_local_array[threadIdx.x + 4];
v_local_array[threadIdx.x] += v_local_array[threadIdx.x + 2];
v_local_array[threadIdx.x] += v_local_array[threadIdx.x + 1];
}
if (threadIdx.x == 0) { out[blockIdx.x] = shared_array[0]; }
}
int main(void) {
int count = 1 << 16;
dim3 block(BLOCK_SIZE_X);
dim3 grid((count + block.x - 1) / block.x);
float* host_array = (float*)malloc(count*sizeof(float));
for (int x = 0; x < count; x++) { host_array[x] = x; }
float* host_result_array = (float*)malloc(grid.x*sizeof(float));
float *device_array, *device_result_array;
cudaMalloc((float**)&device_array, count*sizeof(float));
cudaMemcpy(device_array, host_array, count*sizeof(float), cudaMemcpyHostToDevice);
cudaMalloc((float**)&device_result_array, grid.x*sizeof(float));
warmUp<<<grid,block>>>(device_result_array, device_array, count);
sumUnrollGlobal<<<grid,block>>>(device_result_array, device_array, count);
cudaDeviceSynchronize();
cudaMemcpy(host_result_array, device_result_array, grid.x*sizeof(float), cudaMemcpyDeviceToHost);
sumUnrollShared<<<grid,block>>>(device_result_array, device_array, count);
cudaDeviceSynchronize();
cudaMemcpy(host_result_array, device_result_array, grid.x*sizeof(float), cudaMemcpyDeviceToHost);
free(host_array);
free(host_result_array);
cudaFree(device_array);
cudaFree(device_result_array);
cudaDeviceReset();
return 0;
} | code for sm_80
Function : _Z15sumUnrollSharedPfS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e620000002100 */
/*0030*/ IMAD R3, R0, c[0x0][0x0], RZ ; /* 0x0000000000037a24 */
/* 0x001fca00078e02ff */
/*0040*/ IADD3 R4, R3, R2, RZ ; /* 0x0000000203047210 */
/* 0x002fc80007ffe0ff */
/*0050*/ ISETP.GT.U32.AND P0, PT, R4, c[0x0][0x170], PT ; /* 0x00005c0004007a0c */
/* 0x000fda0003f04070 */
/*0060*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0070*/ IADD3 R3, P0, R3, R2, RZ ; /* 0x0000000203037210 */
/* 0x000fe20007f1e0ff */
/*0080*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc80000000a00 */
/*0090*/ IMAD.X R6, RZ, RZ, RZ, P0 ; /* 0x000000ffff067224 */
/* 0x000fe200000e06ff */
/*00a0*/ LEA R4, P0, R3, c[0x0][0x168], 0x2 ; /* 0x00005a0003047a11 */
/* 0x000fc800078010ff */
/*00b0*/ LEA.HI.X R5, R3, c[0x0][0x16c], R6, 0x2, P0 ; /* 0x00005b0003057a11 */
/* 0x000fcc00000f1406 */
/*00c0*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*00d0*/ ISETP.GT.U32.AND P0, PT, R2.reuse, 0x1ff, PT ; /* 0x000001ff0200780c */
/* 0x040fe20003f04070 */
/*00e0*/ BSSY B0, 0x490 ; /* 0x000003a000007945 */
/* 0x000fe20003800000 */
/*00f0*/ MOV R8, c[0x0][0x0] ; /* 0x0000000000087a02 */
/* 0x000fe40000000f00 */
/*0100*/ ISETP.NE.AND P2, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fe40003f45270 */
/*0110*/ ISETP.LT.U32.OR P1, PT, R8, 0x400, P0 ; /* 0x000004000800780c */
/* 0x000fe40000721470 */
/*0120*/ ISETP.GT.U32.AND P0, PT, R2, 0xff, PT ; /* 0x000000ff0200780c */
/* 0x000fc80003f04070 */
/*0130*/ ISETP.LT.U32.OR P0, PT, R8, 0x200, P0 ; /* 0x000002000800780c */
/* 0x000fe20000701470 */
/*0140*/ STS [R2.X4], R5 ; /* 0x0000000502007388 */
/* 0x004fe80000004800 */
/*0150*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0160*/ @!P1 LDS R3, [R2.X4] ; /* 0x0000000002039984 */
/* 0x000fe80000004800 */
/*0170*/ @!P1 LDS R6, [R2.X4+0x800] ; /* 0x0008000002069984 */
/* 0x000e240000004800 */
/*0180*/ @!P1 FADD R3, R3, R6 ; /* 0x0000000603039221 */
/* 0x001fca0000000000 */
/*0190*/ @!P1 STS [R2.X4], R3 ; /* 0x0000000302009388 */
/* 0x000fe80000004800 */
/*01a0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*01b0*/ ISETP.GT.U32.AND P1, PT, R2, 0x7f, PT ; /* 0x0000007f0200780c */
/* 0x000fc80003f24070 */
/*01c0*/ ISETP.LT.U32.OR P1, PT, R8, 0x100, P1 ; /* 0x000001000800780c */
/* 0x000fe20000f21470 */
/*01d0*/ @!P0 LDS R4, [R2.X4] ; /* 0x0000000002048984 */
/* 0x000fe80000004800 */
/*01e0*/ @!P0 LDS R7, [R2.X4+0x400] ; /* 0x0004000002078984 */
/* 0x000e240000004800 */
/*01f0*/ @!P0 FADD R7, R4, R7 ; /* 0x0000000704078221 */
/* 0x001fca0000000000 */
/*0200*/ @!P0 STS [R2.X4], R7 ; /* 0x0000000702008388 */
/* 0x000fe80000004800 */
/*0210*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0220*/ ISETP.GT.U32.AND P0, PT, R2, 0x3f, PT ; /* 0x0000003f0200780c */
/* 0x000fc80003f04070 */
/*0230*/ ISETP.LT.U32.OR P0, PT, R8, 0x80, P0 ; /* 0x000000800800780c */
/* 0x000fe20000701470 */
/*0240*/ @!P1 LDS R4, [R2.X4] ; /* 0x0000000002049984 */
/* 0x000fe80000004800 */
/*0250*/ @!P1 LDS R5, [R2.X4+0x200] ; /* 0x0002000002059984 */
/* 0x000e240000004800 */
/*0260*/ @!P1 FADD R5, R4, R5 ; /* 0x0000000504059221 */
/* 0x001fca0000000000 */
/*0270*/ @!P1 STS [R2.X4], R5 ; /* 0x0000000502009388 */
/* 0x000fe80000004800 */
/*0280*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0290*/ ISETP.GT.U32.AND P1, PT, R2, 0x1f, PT ; /* 0x0000001f0200780c */
/* 0x000fca0003f24070 */
/*02a0*/ @!P0 LDS R3, [R2.X4] ; /* 0x0000000002038984 */
/* 0x000fe80000004800 */
/*02b0*/ @!P0 LDS R4, [R2.X4+0x100] ; /* 0x0001000002048984 */
/* 0x000e240000004800 */
/*02c0*/ @!P0 FADD R3, R3, R4 ; /* 0x0000000403038221 */
/* 0x001fca0000000000 */
/*02d0*/ @!P0 STS [R2.X4], R3 ; /* 0x0000000302008388 */
/* 0x0001e80000004800 */
/*02e0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*02f0*/ @P1 BRA 0x480 ; /* 0x0000018000001947 */
/* 0x000fea0003800000 */
/*0300*/ LDS R3, [R2.X4] ; /* 0x0000000002037984 */
/* 0x001fe80000004800 */
/*0310*/ LDS R4, [R2.X4+0x80] ; /* 0x0000800002047984 */
/* 0x000e240000004800 */
/*0320*/ FADD R3, R3, R4 ; /* 0x0000000403037221 */
/* 0x001fca0000000000 */
/*0330*/ STS [R2.X4], R3 ; /* 0x0000000302007388 */
/* 0x000fe80000004800 */
/*0340*/ LDS R4, [R2.X4] ; /* 0x0000000002047984 */
/* 0x000fe80000004800 */
/*0350*/ LDS R5, [R2.X4+0x40] ; /* 0x0000400002057984 */
/* 0x000e240000004800 */
/*0360*/ FADD R5, R4, R5 ; /* 0x0000000504057221 */
/* 0x001fca0000000000 */
/*0370*/ STS [R2.X4], R5 ; /* 0x0000000502007388 */
/* 0x000fe80000004800 */
/*0380*/ LDS R4, [R2.X4] ; /* 0x0000000002047984 */
/* 0x000fe80000004800 */
/*0390*/ LDS R7, [R2.X4+0x20] ; /* 0x0000200002077984 */
/* 0x000e240000004800 */
/*03a0*/ FADD R7, R4, R7 ; /* 0x0000000704077221 */
/* 0x001fca0000000000 */
/*03b0*/ STS [R2.X4], R7 ; /* 0x0000000702007388 */
/* 0x000fe80000004800 */
/*03c0*/ LDS R4, [R2.X4] ; /* 0x0000000002047984 */
/* 0x000fe80000004800 */
/*03d0*/ LDS R9, [R2.X4+0x10] ; /* 0x0000100002097984 */
/* 0x000e240000004800 */
/*03e0*/ FADD R9, R4, R9 ; /* 0x0000000904097221 */
/* 0x001fca0000000000 */
/*03f0*/ STS [R2.X4], R9 ; /* 0x0000000902007388 */
/* 0x000fe80000004800 */
/*0400*/ LDS R3, [R2.X4] ; /* 0x0000000002037984 */
/* 0x000fe80000004800 */
/*0410*/ LDS R4, [R2.X4+0x8] ; /* 0x0000080002047984 */
/* 0x000e240000004800 */
/*0420*/ FADD R3, R3, R4 ; /* 0x0000000403037221 */
/* 0x001fca0000000000 */
/*0430*/ STS [R2.X4], R3 ; /* 0x0000000302007388 */
/* 0x000fe80000004800 */
/*0440*/ LDS R4, [R2.X4] ; /* 0x0000000002047984 */
/* 0x000fe80000004800 */
/*0450*/ LDS R5, [R2.X4+0x4] ; /* 0x0000040002057984 */
/* 0x000e240000004800 */
/*0460*/ FADD R5, R4, R5 ; /* 0x0000000504057221 */
/* 0x001fca0000000000 */
/*0470*/ STS [R2.X4], R5 ; /* 0x0000000502007388 */
/* 0x0001e40000004800 */
/*0480*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x001fea0003800000 */
/*0490*/ @P2 EXIT ; /* 0x000000000000294d */
/* 0x000fea0003800000 */
/*04a0*/ LDS R5, [RZ] ; /* 0x00000000ff057984 */
/* 0x000e220000000800 */
/*04b0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fc800078e00ff */
/*04c0*/ IMAD.WIDE.U32 R2, R0, R3, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fca00078e0003 */
/*04d0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x001fe2000c101904 */
/*04e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*04f0*/ BRA 0x4f0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0500*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0510*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0520*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0530*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0540*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0550*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0560*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0570*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z15sumUnrollGlobalPfS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0030*/ IMAD R2, R0, c[0x0][0x0], RZ ; /* 0x0000000000027a24 */
/* 0x001fca00078e02ff */
/*0040*/ IADD3 R3, R2, R5, RZ ; /* 0x0000000502037210 */
/* 0x002fc80007ffe0ff */
/*0050*/ ISETP.GT.U32.AND P0, PT, R3, c[0x0][0x170], PT ; /* 0x00005c0003007a0c */
/* 0x000fda0003f04070 */
/*0060*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0070*/ ISETP.GT.U32.AND P1, PT, R5.reuse, 0x1ff, PT ; /* 0x000001ff0500780c */
/* 0x040fe20003f24070 */
/*0080*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0090*/ MOV R3, c[0x0][0x0] ; /* 0x0000000000037a02 */
/* 0x000fe20000000f00 */
/*00a0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00b0*/ ISETP.GT.U32.AND P2, PT, R5, 0xff, PT ; /* 0x000000ff0500780c */
/* 0x000fe20003f44070 */
/*00c0*/ BSSY B0, 0x1d0 ; /* 0x0000010000007945 */
/* 0x000fe20003800000 */
/*00d0*/ ISETP.LT.U32.OR P1, PT, R3, 0x400, P1 ; /* 0x000004000300780c */
/* 0x000fe40000f21470 */
/*00e0*/ ISETP.GT.U32.AND P3, PT, R5.reuse, 0x7f, PT ; /* 0x0000007f0500780c */
/* 0x040fe40003f64070 */
/*00f0*/ ISETP.GT.U32.AND P0, PT, R5, 0x3f, PT ; /* 0x0000003f0500780c */
/* 0x000fc40003f04070 */
/*0100*/ ISETP.LT.U32.OR P2, PT, R3.reuse, 0x200, P2 ; /* 0x000002000300780c */
/* 0x040fe40001741470 */
/*0110*/ ISETP.LT.U32.OR P3, PT, R3.reuse, 0x100, P3 ; /* 0x000001000300780c */
/* 0x040fe40001f61470 */
/*0120*/ ISETP.LT.U32.OR P0, PT, R3, 0x80, P0 ; /* 0x000000800300780c */
/* 0x000fe20000701470 */
/*0130*/ IMAD.WIDE.U32 R2, R2, R7, c[0x0][0x168] ; /* 0x00005a0002027625 */
/* 0x000fe200078e0007 */
/*0140*/ ISETP.GT.U32.AND P4, PT, R5.reuse, 0x1f, PT ; /* 0x0000001f0500780c */
/* 0x040fe40003f84070 */
/*0150*/ ISETP.NE.AND P5, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fc60003fa5270 */
/*0160*/ IMAD.WIDE.U32 R4, R5, 0x4, R2 ; /* 0x0000000405047825 */
/* 0x000fe200078e0002 */
/*0170*/ @P1 BRA 0x1c0 ; /* 0x0000004000001947 */
/* 0x000fea0003800000 */
/*0180*/ LDG.E R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000ea8000c1e1900 */
/*0190*/ LDG.E R9, [R4.64+0x800] ; /* 0x0008000404097981 */
/* 0x000ea4000c1e1900 */
/*01a0*/ FADD R9, R6, R9 ; /* 0x0000000906097221 */
/* 0x004fca0000000000 */
/*01b0*/ STG.E [R4.64], R9 ; /* 0x0000000904007986 */
/* 0x0001e4000c101904 */
/*01c0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*01d0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*01e0*/ BSSY B0, 0x250 ; /* 0x0000006000007945 */
/* 0x000fe20003800000 */
/*01f0*/ @P2 BRA 0x240 ; /* 0x0000004000002947 */
/* 0x000fea0003800000 */
/*0200*/ LDG.E R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000ea8000c1e1900 */
/*0210*/ LDG.E R9, [R4.64+0x400] ; /* 0x0004000404097981 */
/* 0x001ea4000c1e1900 */
/*0220*/ FADD R9, R6, R9 ; /* 0x0000000906097221 */
/* 0x004fca0000000000 */
/*0230*/ STG.E [R4.64], R9 ; /* 0x0000000904007986 */
/* 0x0001e4000c101904 */
/*0240*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0250*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0260*/ BSSY B0, 0x2d0 ; /* 0x0000006000007945 */
/* 0x000fe20003800000 */
/*0270*/ @P3 BRA 0x2c0 ; /* 0x0000004000003947 */
/* 0x000fea0003800000 */
/*0280*/ LDG.E R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000ea8000c1e1900 */
/*0290*/ LDG.E R9, [R4.64+0x200] ; /* 0x0002000404097981 */
/* 0x001ea4000c1e1900 */
/*02a0*/ FADD R9, R6, R9 ; /* 0x0000000906097221 */
/* 0x004fca0000000000 */
/*02b0*/ STG.E [R4.64], R9 ; /* 0x0000000904007986 */
/* 0x0001e4000c101904 */
/*02c0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*02d0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*02e0*/ BSSY B0, 0x350 ; /* 0x0000006000007945 */
/* 0x000fe20003800000 */
/*02f0*/ @P0 BRA 0x340 ; /* 0x0000004000000947 */
/* 0x000fea0003800000 */
/*0300*/ LDG.E R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000ea8000c1e1900 */
/*0310*/ LDG.E R9, [R4.64+0x100] ; /* 0x0001000404097981 */
/* 0x001ea4000c1e1900 */
/*0320*/ FADD R9, R6, R9 ; /* 0x0000000906097221 */
/* 0x004fca0000000000 */
/*0330*/ STG.E [R4.64], R9 ; /* 0x0000000904007986 */
/* 0x0001e4000c101904 */
/*0340*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0350*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0360*/ BSSY B0, 0x510 ; /* 0x000001a000007945 */
/* 0x000fe20003800000 */
/*0370*/ @P4 BRA 0x500 ; /* 0x0000018000004947 */
/* 0x000fea0003800000 */
/*0380*/ LDG.E.STRONG.SYS R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000ea8000c1f5900 */
/*0390*/ LDG.E.STRONG.SYS R9, [R4.64+0x80] ; /* 0x0000800404097981 */
/* 0x001ea4000c1f5900 */
/*03a0*/ FADD R9, R6, R9 ; /* 0x0000000906097221 */
/* 0x004fca0000000000 */
/*03b0*/ STG.E.STRONG.SYS [R4.64], R9 ; /* 0x0000000904007986 */
/* 0x0001e8000c115904 */
/*03c0*/ LDG.E.STRONG.SYS R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000ea8000c1f5900 */
/*03d0*/ LDG.E.STRONG.SYS R11, [R4.64+0x40] ; /* 0x00004004040b7981 */
/* 0x000ea4000c1f5900 */
/*03e0*/ FADD R11, R6, R11 ; /* 0x0000000b060b7221 */
/* 0x004fca0000000000 */
/*03f0*/ STG.E.STRONG.SYS [R4.64], R11 ; /* 0x0000000b04007986 */
/* 0x0003e8000c115904 */
/*0400*/ LDG.E.STRONG.SYS R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000ea8000c1f5900 */
/*0410*/ LDG.E.STRONG.SYS R13, [R4.64+0x20] ; /* 0x00002004040d7981 */
/* 0x000ea4000c1f5900 */
/*0420*/ FADD R13, R6, R13 ; /* 0x0000000d060d7221 */
/* 0x004fca0000000000 */
/*0430*/ STG.E.STRONG.SYS [R4.64], R13 ; /* 0x0000000d04007986 */
/* 0x0005e8000c115904 */
/*0440*/ LDG.E.STRONG.SYS R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000ee8000c1f5900 */
/*0450*/ LDG.E.STRONG.SYS R15, [R4.64+0x10] ; /* 0x00001004040f7981 */
/* 0x000ee4000c1f5900 */
/*0460*/ FADD R15, R6, R15 ; /* 0x0000000f060f7221 */
/* 0x008fca0000000000 */
/*0470*/ STG.E.STRONG.SYS [R4.64], R15 ; /* 0x0000000f04007986 */
/* 0x0005e8000c115904 */
/*0480*/ LDG.E.STRONG.SYS R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000ee8000c1f5900 */
/*0490*/ LDG.E.STRONG.SYS R9, [R4.64+0x8] ; /* 0x0000080404097981 */
/* 0x001ee4000c1f5900 */
/*04a0*/ FADD R9, R6, R9 ; /* 0x0000000906097221 */
/* 0x008fca0000000000 */
/*04b0*/ STG.E.STRONG.SYS [R4.64], R9 ; /* 0x0000000904007986 */
/* 0x0005e8000c115904 */
/*04c0*/ LDG.E.STRONG.SYS R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000ee8000c1f5900 */
/*04d0*/ LDG.E.STRONG.SYS R11, [R4.64+0x4] ; /* 0x00000404040b7981 */
/* 0x002ee4000c1f5900 */
/*04e0*/ FADD R11, R6, R11 ; /* 0x0000000b060b7221 */
/* 0x008fca0000000000 */
/*04f0*/ STG.E.STRONG.SYS [R4.64], R11 ; /* 0x0000000b04007986 */
/* 0x0005e4000c115904 */
/*0500*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0510*/ @P5 EXIT ; /* 0x000000000000594d */
/* 0x000fea0003800000 */
/*0520*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ee2000c1e1900 */
/*0530*/ IMAD.WIDE.U32 R4, R0, R7, c[0x0][0x160] ; /* 0x0000580000047625 */
/* 0x005fca00078e0007 */
/*0540*/ STG.E [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x008fe2000c101904 */
/*0550*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0560*/ BRA 0x560; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0570*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0580*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0590*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z6warmUpPfS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e240000002100 */
/*0020*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x001fda0003f05270 */
/*0030*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0040*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e220000002500 */
/*0050*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0060*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0070*/ IMAD R2, R4, c[0x0][0x0], RZ ; /* 0x0000000004027a24 */
/* 0x001fd000078e02ff */
/*0080*/ IMAD.WIDE.U32 R2, R2, R5, c[0x0][0x168] ; /* 0x00005a0002027625 */
/* 0x000fcc00078e0005 */
/*0090*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ IMAD.WIDE.U32 R4, R4, R5, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fca00078e0005 */
/*00b0*/ STG.E [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x004fe2000c101904 */
/*00c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00d0*/ BRA 0xd0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#define BLOCK_SIZE_X 128
__global__
void warmUp(float* out, float* in, int count) {
float* local_array = in + (blockIdx.x * blockDim.x);
if (threadIdx.x == 0) { out[blockIdx.x] = local_array[0]; }
}
__global__
void sumUnrollGlobal(float* out, float* in, int count) {
if ((blockIdx.x * blockDim.x) + threadIdx.x > count) return;
float* local_array = in + (blockIdx.x * blockDim.x);
if (blockDim.x >= 1024 && threadIdx.x < 512) { local_array[threadIdx.x] += local_array[threadIdx.x + 512]; }
__syncthreads();
if (blockDim.x >= 512 && threadIdx.x < 256) { local_array[threadIdx.x] += local_array[threadIdx.x + 256]; }
__syncthreads();
if (blockDim.x >= 256 && threadIdx.x < 128) { local_array[threadIdx.x] += local_array[threadIdx.x + 128]; }
__syncthreads();
if (blockDim.x >= 128 && threadIdx.x < 64) { local_array[threadIdx.x] += local_array[threadIdx.x + 64]; }
__syncthreads();
if (threadIdx.x < 32) {
volatile float* v_local_array = local_array;
v_local_array[threadIdx.x] += v_local_array[threadIdx.x + 32];
v_local_array[threadIdx.x] += v_local_array[threadIdx.x + 16];
v_local_array[threadIdx.x] += v_local_array[threadIdx.x + 8];
v_local_array[threadIdx.x] += v_local_array[threadIdx.x + 4];
v_local_array[threadIdx.x] += v_local_array[threadIdx.x + 2];
v_local_array[threadIdx.x] += v_local_array[threadIdx.x + 1];
}
if (threadIdx.x == 0) { out[blockIdx.x] = local_array[0]; }
}
__global__
void sumUnrollShared(float* out, float* in, int count) {
if ((blockIdx.x * blockDim.x) + threadIdx.x > count) return;
float* local_array = in + (blockIdx.x * blockDim.x);
__shared__ float shared_array[BLOCK_SIZE_X];
shared_array[threadIdx.x] = local_array[threadIdx.x];
__syncthreads();
if (blockDim.x >= 1024 && threadIdx.x < 512) { shared_array[threadIdx.x] += shared_array[threadIdx.x + 512]; }
__syncthreads();
if (blockDim.x >= 512 && threadIdx.x < 256) { shared_array[threadIdx.x] += shared_array[threadIdx.x + 256]; }
__syncthreads();
if (blockDim.x >= 256 && threadIdx.x < 128) { shared_array[threadIdx.x] += shared_array[threadIdx.x + 128]; }
__syncthreads();
if (blockDim.x >= 128 && threadIdx.x < 64) { shared_array[threadIdx.x] += shared_array[threadIdx.x + 64]; }
__syncthreads();
if (threadIdx.x < 32) {
volatile float* v_local_array = shared_array;
v_local_array[threadIdx.x] += v_local_array[threadIdx.x + 32];
v_local_array[threadIdx.x] += v_local_array[threadIdx.x + 16];
v_local_array[threadIdx.x] += v_local_array[threadIdx.x + 8];
v_local_array[threadIdx.x] += v_local_array[threadIdx.x + 4];
v_local_array[threadIdx.x] += v_local_array[threadIdx.x + 2];
v_local_array[threadIdx.x] += v_local_array[threadIdx.x + 1];
}
if (threadIdx.x == 0) { out[blockIdx.x] = shared_array[0]; }
}
int main(void) {
int count = 1 << 16;
dim3 block(BLOCK_SIZE_X);
dim3 grid((count + block.x - 1) / block.x);
float* host_array = (float*)malloc(count*sizeof(float));
for (int x = 0; x < count; x++) { host_array[x] = x; }
float* host_result_array = (float*)malloc(grid.x*sizeof(float));
float *device_array, *device_result_array;
cudaMalloc((float**)&device_array, count*sizeof(float));
cudaMemcpy(device_array, host_array, count*sizeof(float), cudaMemcpyHostToDevice);
cudaMalloc((float**)&device_result_array, grid.x*sizeof(float));
warmUp<<<grid,block>>>(device_result_array, device_array, count);
sumUnrollGlobal<<<grid,block>>>(device_result_array, device_array, count);
cudaDeviceSynchronize();
cudaMemcpy(host_result_array, device_result_array, grid.x*sizeof(float), cudaMemcpyDeviceToHost);
sumUnrollShared<<<grid,block>>>(device_result_array, device_array, count);
cudaDeviceSynchronize();
cudaMemcpy(host_result_array, device_result_array, grid.x*sizeof(float), cudaMemcpyDeviceToHost);
free(host_array);
free(host_result_array);
cudaFree(device_array);
cudaFree(device_result_array);
cudaDeviceReset();
return 0;
} | .file "tmpxft_0003ecda_00000000-6_array_sum_shared.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z28__device_stub__Z6warmUpPfS_iPfS_i
.type _Z28__device_stub__Z6warmUpPfS_iPfS_i, @function
_Z28__device_stub__Z6warmUpPfS_iPfS_i:
.LFB2082:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6warmUpPfS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z28__device_stub__Z6warmUpPfS_iPfS_i, .-_Z28__device_stub__Z6warmUpPfS_iPfS_i
.globl _Z6warmUpPfS_i
.type _Z6warmUpPfS_i, @function
_Z6warmUpPfS_i:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z28__device_stub__Z6warmUpPfS_iPfS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z6warmUpPfS_i, .-_Z6warmUpPfS_i
.globl _Z38__device_stub__Z15sumUnrollGlobalPfS_iPfS_i
.type _Z38__device_stub__Z15sumUnrollGlobalPfS_iPfS_i, @function
_Z38__device_stub__Z15sumUnrollGlobalPfS_iPfS_i:
.LFB2084:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z15sumUnrollGlobalPfS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z38__device_stub__Z15sumUnrollGlobalPfS_iPfS_i, .-_Z38__device_stub__Z15sumUnrollGlobalPfS_iPfS_i
.globl _Z15sumUnrollGlobalPfS_i
.type _Z15sumUnrollGlobalPfS_i, @function
_Z15sumUnrollGlobalPfS_i:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z38__device_stub__Z15sumUnrollGlobalPfS_iPfS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z15sumUnrollGlobalPfS_i, .-_Z15sumUnrollGlobalPfS_i
.globl _Z38__device_stub__Z15sumUnrollSharedPfS_iPfS_i
.type _Z38__device_stub__Z15sumUnrollSharedPfS_iPfS_i, @function
_Z38__device_stub__Z15sumUnrollSharedPfS_iPfS_i:
.LFB2086:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L23
.L19:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L24
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z15sumUnrollSharedPfS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L19
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2086:
.size _Z38__device_stub__Z15sumUnrollSharedPfS_iPfS_i, .-_Z38__device_stub__Z15sumUnrollSharedPfS_iPfS_i
.globl _Z15sumUnrollSharedPfS_i
.type _Z15sumUnrollSharedPfS_i, @function
_Z15sumUnrollSharedPfS_i:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z38__device_stub__Z15sumUnrollSharedPfS_iPfS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _Z15sumUnrollSharedPfS_i, .-_Z15sumUnrollSharedPfS_i
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $56, %rsp
.cfi_def_cfa_offset 80
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $262144, %edi
call malloc@PLT
movq %rax, %rbx
movl $0, %eax
.L28:
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, (%rbx,%rax,4)
addq $1, %rax
cmpq $65536, %rax
jne .L28
movl $2048, %edi
call malloc@PLT
movq %rax, %rbp
movq %rsp, %rdi
movl $262144, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $262144, %edx
movq %rbx, %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
leaq 8(%rsp), %rdi
movl $2048, %esi
call cudaMalloc@PLT
movl $512, 28(%rsp)
movl $128, 16(%rsp)
movl 24(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 16(%rsp), %rdx
movq 28(%rsp), %rdi
movl 36(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L35
.L29:
movl 24(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 16(%rsp), %rdx
movq 28(%rsp), %rdi
movl 36(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L36
.L30:
call cudaDeviceSynchronize@PLT
movl $2, %ecx
movl $2048, %edx
movq 8(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
movl 24(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 16(%rsp), %rdx
movq 28(%rsp), %rdi
movl 36(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L37
.L31:
call cudaDeviceSynchronize@PLT
movl $2, %ecx
movl $2048, %edx
movq 8(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
movq %rbx, %rdi
call free@PLT
movq %rbp, %rdi
call free@PLT
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
call cudaDeviceReset@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L38
movl $0, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L35:
.cfi_restore_state
movl $65536, %edx
movq (%rsp), %rsi
movq 8(%rsp), %rdi
call _Z28__device_stub__Z6warmUpPfS_iPfS_i
jmp .L29
.L36:
movl $65536, %edx
movq (%rsp), %rsi
movq 8(%rsp), %rdi
call _Z38__device_stub__Z15sumUnrollGlobalPfS_iPfS_i
jmp .L30
.L37:
movl $65536, %edx
movq (%rsp), %rsi
movq 8(%rsp), %rdi
call _Z38__device_stub__Z15sumUnrollSharedPfS_iPfS_i
jmp .L31
.L38:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z15sumUnrollSharedPfS_i"
.LC1:
.string "_Z15sumUnrollGlobalPfS_i"
.LC2:
.string "_Z6warmUpPfS_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2089:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z15sumUnrollSharedPfS_i(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z15sumUnrollGlobalPfS_i(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z6warmUpPfS_i(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2089:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#define BLOCK_SIZE_X 128
__global__
void warmUp(float* out, float* in, int count) {
float* local_array = in + (blockIdx.x * blockDim.x);
if (threadIdx.x == 0) { out[blockIdx.x] = local_array[0]; }
}
__global__
void sumUnrollGlobal(float* out, float* in, int count) {
if ((blockIdx.x * blockDim.x) + threadIdx.x > count) return;
float* local_array = in + (blockIdx.x * blockDim.x);
if (blockDim.x >= 1024 && threadIdx.x < 512) { local_array[threadIdx.x] += local_array[threadIdx.x + 512]; }
__syncthreads();
if (blockDim.x >= 512 && threadIdx.x < 256) { local_array[threadIdx.x] += local_array[threadIdx.x + 256]; }
__syncthreads();
if (blockDim.x >= 256 && threadIdx.x < 128) { local_array[threadIdx.x] += local_array[threadIdx.x + 128]; }
__syncthreads();
if (blockDim.x >= 128 && threadIdx.x < 64) { local_array[threadIdx.x] += local_array[threadIdx.x + 64]; }
__syncthreads();
if (threadIdx.x < 32) {
volatile float* v_local_array = local_array;
v_local_array[threadIdx.x] += v_local_array[threadIdx.x + 32];
v_local_array[threadIdx.x] += v_local_array[threadIdx.x + 16];
v_local_array[threadIdx.x] += v_local_array[threadIdx.x + 8];
v_local_array[threadIdx.x] += v_local_array[threadIdx.x + 4];
v_local_array[threadIdx.x] += v_local_array[threadIdx.x + 2];
v_local_array[threadIdx.x] += v_local_array[threadIdx.x + 1];
}
if (threadIdx.x == 0) { out[blockIdx.x] = local_array[0]; }
}
__global__
void sumUnrollShared(float* out, float* in, int count) {
if ((blockIdx.x * blockDim.x) + threadIdx.x > count) return;
float* local_array = in + (blockIdx.x * blockDim.x);
__shared__ float shared_array[BLOCK_SIZE_X];
shared_array[threadIdx.x] = local_array[threadIdx.x];
__syncthreads();
if (blockDim.x >= 1024 && threadIdx.x < 512) { shared_array[threadIdx.x] += shared_array[threadIdx.x + 512]; }
__syncthreads();
if (blockDim.x >= 512 && threadIdx.x < 256) { shared_array[threadIdx.x] += shared_array[threadIdx.x + 256]; }
__syncthreads();
if (blockDim.x >= 256 && threadIdx.x < 128) { shared_array[threadIdx.x] += shared_array[threadIdx.x + 128]; }
__syncthreads();
if (blockDim.x >= 128 && threadIdx.x < 64) { shared_array[threadIdx.x] += shared_array[threadIdx.x + 64]; }
__syncthreads();
if (threadIdx.x < 32) {
volatile float* v_local_array = shared_array;
v_local_array[threadIdx.x] += v_local_array[threadIdx.x + 32];
v_local_array[threadIdx.x] += v_local_array[threadIdx.x + 16];
v_local_array[threadIdx.x] += v_local_array[threadIdx.x + 8];
v_local_array[threadIdx.x] += v_local_array[threadIdx.x + 4];
v_local_array[threadIdx.x] += v_local_array[threadIdx.x + 2];
v_local_array[threadIdx.x] += v_local_array[threadIdx.x + 1];
}
if (threadIdx.x == 0) { out[blockIdx.x] = shared_array[0]; }
}
int main(void) {
int count = 1 << 16;
dim3 block(BLOCK_SIZE_X);
dim3 grid((count + block.x - 1) / block.x);
float* host_array = (float*)malloc(count*sizeof(float));
for (int x = 0; x < count; x++) { host_array[x] = x; }
float* host_result_array = (float*)malloc(grid.x*sizeof(float));
float *device_array, *device_result_array;
cudaMalloc((float**)&device_array, count*sizeof(float));
cudaMemcpy(device_array, host_array, count*sizeof(float), cudaMemcpyHostToDevice);
cudaMalloc((float**)&device_result_array, grid.x*sizeof(float));
warmUp<<<grid,block>>>(device_result_array, device_array, count);
sumUnrollGlobal<<<grid,block>>>(device_result_array, device_array, count);
cudaDeviceSynchronize();
cudaMemcpy(host_result_array, device_result_array, grid.x*sizeof(float), cudaMemcpyDeviceToHost);
sumUnrollShared<<<grid,block>>>(device_result_array, device_array, count);
cudaDeviceSynchronize();
cudaMemcpy(host_result_array, device_result_array, grid.x*sizeof(float), cudaMemcpyDeviceToHost);
free(host_array);
free(host_result_array);
cudaFree(device_array);
cudaFree(device_result_array);
cudaDeviceReset();
return 0;
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#define BLOCK_SIZE_X 128
__global__
void warmUp(float* out, float* in, int count) {
float* local_array = in + (blockIdx.x * blockDim.x);
if (threadIdx.x == 0) { out[blockIdx.x] = local_array[0]; }
}
__global__
void sumUnrollGlobal(float* out, float* in, int count) {
if ((blockIdx.x * blockDim.x) + threadIdx.x > count) return;
float* local_array = in + (blockIdx.x * blockDim.x);
if (blockDim.x >= 1024 && threadIdx.x < 512) { local_array[threadIdx.x] += local_array[threadIdx.x + 512]; }
__syncthreads();
if (blockDim.x >= 512 && threadIdx.x < 256) { local_array[threadIdx.x] += local_array[threadIdx.x + 256]; }
__syncthreads();
if (blockDim.x >= 256 && threadIdx.x < 128) { local_array[threadIdx.x] += local_array[threadIdx.x + 128]; }
__syncthreads();
if (blockDim.x >= 128 && threadIdx.x < 64) { local_array[threadIdx.x] += local_array[threadIdx.x + 64]; }
__syncthreads();
if (threadIdx.x < 32) {
volatile float* v_local_array = local_array;
v_local_array[threadIdx.x] += v_local_array[threadIdx.x + 32];
v_local_array[threadIdx.x] += v_local_array[threadIdx.x + 16];
v_local_array[threadIdx.x] += v_local_array[threadIdx.x + 8];
v_local_array[threadIdx.x] += v_local_array[threadIdx.x + 4];
v_local_array[threadIdx.x] += v_local_array[threadIdx.x + 2];
v_local_array[threadIdx.x] += v_local_array[threadIdx.x + 1];
}
if (threadIdx.x == 0) { out[blockIdx.x] = local_array[0]; }
}
__global__
void sumUnrollShared(float* out, float* in, int count) {
if ((blockIdx.x * blockDim.x) + threadIdx.x > count) return;
float* local_array = in + (blockIdx.x * blockDim.x);
__shared__ float shared_array[BLOCK_SIZE_X];
shared_array[threadIdx.x] = local_array[threadIdx.x];
__syncthreads();
if (blockDim.x >= 1024 && threadIdx.x < 512) { shared_array[threadIdx.x] += shared_array[threadIdx.x + 512]; }
__syncthreads();
if (blockDim.x >= 512 && threadIdx.x < 256) { shared_array[threadIdx.x] += shared_array[threadIdx.x + 256]; }
__syncthreads();
if (blockDim.x >= 256 && threadIdx.x < 128) { shared_array[threadIdx.x] += shared_array[threadIdx.x + 128]; }
__syncthreads();
if (blockDim.x >= 128 && threadIdx.x < 64) { shared_array[threadIdx.x] += shared_array[threadIdx.x + 64]; }
__syncthreads();
if (threadIdx.x < 32) {
volatile float* v_local_array = shared_array;
v_local_array[threadIdx.x] += v_local_array[threadIdx.x + 32];
v_local_array[threadIdx.x] += v_local_array[threadIdx.x + 16];
v_local_array[threadIdx.x] += v_local_array[threadIdx.x + 8];
v_local_array[threadIdx.x] += v_local_array[threadIdx.x + 4];
v_local_array[threadIdx.x] += v_local_array[threadIdx.x + 2];
v_local_array[threadIdx.x] += v_local_array[threadIdx.x + 1];
}
if (threadIdx.x == 0) { out[blockIdx.x] = shared_array[0]; }
}
int main(void) {
int count = 1 << 16;
dim3 block(BLOCK_SIZE_X);
dim3 grid((count + block.x - 1) / block.x);
float* host_array = (float*)malloc(count*sizeof(float));
for (int x = 0; x < count; x++) { host_array[x] = x; }
float* host_result_array = (float*)malloc(grid.x*sizeof(float));
float *device_array, *device_result_array;
hipMalloc((float**)&device_array, count*sizeof(float));
hipMemcpy(device_array, host_array, count*sizeof(float), hipMemcpyHostToDevice);
hipMalloc((float**)&device_result_array, grid.x*sizeof(float));
warmUp<<<grid,block>>>(device_result_array, device_array, count);
sumUnrollGlobal<<<grid,block>>>(device_result_array, device_array, count);
hipDeviceSynchronize();
hipMemcpy(host_result_array, device_result_array, grid.x*sizeof(float), hipMemcpyDeviceToHost);
sumUnrollShared<<<grid,block>>>(device_result_array, device_array, count);
hipDeviceSynchronize();
hipMemcpy(host_result_array, device_result_array, grid.x*sizeof(float), hipMemcpyDeviceToHost);
free(host_array);
free(host_result_array);
hipFree(device_array);
hipFree(device_result_array);
hipDeviceReset();
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#define BLOCK_SIZE_X 128
__global__
void warmUp(float* out, float* in, int count) {
float* local_array = in + (blockIdx.x * blockDim.x);
if (threadIdx.x == 0) { out[blockIdx.x] = local_array[0]; }
}
__global__
void sumUnrollGlobal(float* out, float* in, int count) {
if ((blockIdx.x * blockDim.x) + threadIdx.x > count) return;
float* local_array = in + (blockIdx.x * blockDim.x);
if (blockDim.x >= 1024 && threadIdx.x < 512) { local_array[threadIdx.x] += local_array[threadIdx.x + 512]; }
__syncthreads();
if (blockDim.x >= 512 && threadIdx.x < 256) { local_array[threadIdx.x] += local_array[threadIdx.x + 256]; }
__syncthreads();
if (blockDim.x >= 256 && threadIdx.x < 128) { local_array[threadIdx.x] += local_array[threadIdx.x + 128]; }
__syncthreads();
if (blockDim.x >= 128 && threadIdx.x < 64) { local_array[threadIdx.x] += local_array[threadIdx.x + 64]; }
__syncthreads();
if (threadIdx.x < 32) {
volatile float* v_local_array = local_array;
v_local_array[threadIdx.x] += v_local_array[threadIdx.x + 32];
v_local_array[threadIdx.x] += v_local_array[threadIdx.x + 16];
v_local_array[threadIdx.x] += v_local_array[threadIdx.x + 8];
v_local_array[threadIdx.x] += v_local_array[threadIdx.x + 4];
v_local_array[threadIdx.x] += v_local_array[threadIdx.x + 2];
v_local_array[threadIdx.x] += v_local_array[threadIdx.x + 1];
}
if (threadIdx.x == 0) { out[blockIdx.x] = local_array[0]; }
}
__global__
void sumUnrollShared(float* out, float* in, int count) {
if ((blockIdx.x * blockDim.x) + threadIdx.x > count) return;
float* local_array = in + (blockIdx.x * blockDim.x);
__shared__ float shared_array[BLOCK_SIZE_X];
shared_array[threadIdx.x] = local_array[threadIdx.x];
__syncthreads();
if (blockDim.x >= 1024 && threadIdx.x < 512) { shared_array[threadIdx.x] += shared_array[threadIdx.x + 512]; }
__syncthreads();
if (blockDim.x >= 512 && threadIdx.x < 256) { shared_array[threadIdx.x] += shared_array[threadIdx.x + 256]; }
__syncthreads();
if (blockDim.x >= 256 && threadIdx.x < 128) { shared_array[threadIdx.x] += shared_array[threadIdx.x + 128]; }
__syncthreads();
if (blockDim.x >= 128 && threadIdx.x < 64) { shared_array[threadIdx.x] += shared_array[threadIdx.x + 64]; }
__syncthreads();
if (threadIdx.x < 32) {
volatile float* v_local_array = shared_array;
v_local_array[threadIdx.x] += v_local_array[threadIdx.x + 32];
v_local_array[threadIdx.x] += v_local_array[threadIdx.x + 16];
v_local_array[threadIdx.x] += v_local_array[threadIdx.x + 8];
v_local_array[threadIdx.x] += v_local_array[threadIdx.x + 4];
v_local_array[threadIdx.x] += v_local_array[threadIdx.x + 2];
v_local_array[threadIdx.x] += v_local_array[threadIdx.x + 1];
}
if (threadIdx.x == 0) { out[blockIdx.x] = shared_array[0]; }
}
int main(void) {
int count = 1 << 16;
dim3 block(BLOCK_SIZE_X);
dim3 grid((count + block.x - 1) / block.x);
float* host_array = (float*)malloc(count*sizeof(float));
for (int x = 0; x < count; x++) { host_array[x] = x; }
float* host_result_array = (float*)malloc(grid.x*sizeof(float));
float *device_array, *device_result_array;
hipMalloc((float**)&device_array, count*sizeof(float));
hipMemcpy(device_array, host_array, count*sizeof(float), hipMemcpyHostToDevice);
hipMalloc((float**)&device_result_array, grid.x*sizeof(float));
warmUp<<<grid,block>>>(device_result_array, device_array, count);
sumUnrollGlobal<<<grid,block>>>(device_result_array, device_array, count);
hipDeviceSynchronize();
hipMemcpy(host_result_array, device_result_array, grid.x*sizeof(float), hipMemcpyDeviceToHost);
sumUnrollShared<<<grid,block>>>(device_result_array, device_array, count);
hipDeviceSynchronize();
hipMemcpy(host_result_array, device_result_array, grid.x*sizeof(float), hipMemcpyDeviceToHost);
free(host_array);
free(host_result_array);
hipFree(device_array);
hipFree(device_result_array);
hipDeviceReset();
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6warmUpPfS_i
.globl _Z6warmUpPfS_i
.p2align 8
.type _Z6warmUpPfS_i,@function
_Z6warmUpPfS_i:
s_mov_b32 s5, 0
s_mov_b32 s3, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_2
s_clause 0x1
s_load_b32 s3, s[0:1], 0x24
s_load_b128 s[8:11], s[0:1], 0x0
s_mov_b32 s2, s15
s_waitcnt lgkmcnt(0)
s_and_b32 s0, s3, 0xffff
s_mov_b32 s3, s5
s_mul_i32 s4, s15, s0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_lshl_b64 s[0:1], s[4:5], 2
s_add_u32 s0, s10, s0
s_addc_u32 s1, s11, s1
s_load_b32 s4, s[0:1], 0x0
s_lshl_b64 s[0:1], s[2:3], 2
v_mov_b32_e32 v0, 0
s_add_u32 s0, s8, s0
s_addc_u32 s1, s9, s1
s_waitcnt lgkmcnt(0)
v_mov_b32_e32 v1, s4
global_store_b32 v0, v1, s[0:1]
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6warmUpPfS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 16
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6warmUpPfS_i, .Lfunc_end0-_Z6warmUpPfS_i
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z15sumUnrollGlobalPfS_i
.globl _Z15sumUnrollGlobalPfS_i
.p2align 8
.type _Z15sumUnrollGlobalPfS_i,@function
_Z15sumUnrollGlobalPfS_i:
s_clause 0x1
s_load_b32 s6, s[0:1], 0x24
s_load_b32 s5, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s6, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s4, s15, s3
v_add_nc_u32_e32 v1, s4, v0
s_delay_alu instid0(VALU_DEP_1)
v_cmp_ge_u32_e32 vcc_lo, s5, v1
s_and_saveexec_b32 s5, vcc_lo
s_cbranch_execz .LBB1_13
s_load_b64 s[8:9], s[0:1], 0x8
s_mov_b32 s5, 0
v_cmp_lt_u16_e64 s7, 0x3ff, s6
v_cmp_gt_u32_e32 vcc_lo, 0x200, v0
s_lshl_b64 s[4:5], s[4:5], 2
s_mov_b32 s2, s15
s_waitcnt lgkmcnt(0)
s_add_u32 s4, s8, s4
s_addc_u32 s5, s9, s5
s_and_b32 s8, vcc_lo, s7
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s7, s8
s_cbranch_execz .LBB1_3
v_lshlrev_b32_e32 v1, 2, v0
s_clause 0x1
global_load_b32 v2, v1, s[4:5] offset:2048
global_load_b32 v3, v1, s[4:5]
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v2, v3
global_store_b32 v1, v2, s[4:5]
.LBB1_3:
s_or_b32 exec_lo, exec_lo, s7
v_cmp_lt_u16_e64 s7, 0x1ff, s6
v_cmp_gt_u32_e32 vcc_lo, 0x100, v0
s_and_b32 s6, 0xffff, s6
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
s_and_b32 s8, vcc_lo, s7
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s7, s8
s_cbranch_execz .LBB1_5
v_lshlrev_b32_e32 v1, 2, v0
s_clause 0x1
global_load_b32 v2, v1, s[4:5] offset:1024
global_load_b32 v3, v1, s[4:5]
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v2, v3
global_store_b32 v1, v2, s[4:5]
.LBB1_5:
s_or_b32 exec_lo, exec_lo, s7
v_cmp_gt_u32_e32 vcc_lo, 0x80, v0
s_cmpk_gt_u32 s6, 0xff
s_waitcnt_vscnt null, 0x0
s_cselect_b32 s6, -1, 0
s_barrier
s_and_b32 s7, vcc_lo, s6
buffer_gl0_inv
s_and_saveexec_b32 s6, s7
s_cbranch_execz .LBB1_7
v_lshlrev_b32_e32 v1, 2, v0
s_clause 0x1
global_load_b32 v2, v1, s[4:5] offset:512
global_load_b32 v3, v1, s[4:5]
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v2, v3
global_store_b32 v1, v2, s[4:5]
.LBB1_7:
s_or_b32 exec_lo, exec_lo, s6
v_cmp_gt_u32_e32 vcc_lo, 64, v0
s_cmpk_gt_u32 s3, 0x7f
s_waitcnt_vscnt null, 0x0
s_cselect_b32 s3, -1, 0
s_barrier
s_and_b32 s6, vcc_lo, s3
buffer_gl0_inv
s_and_saveexec_b32 s3, s6
s_cbranch_execz .LBB1_9
v_lshlrev_b32_e32 v1, 2, v0
s_clause 0x1
global_load_b32 v2, v1, s[4:5] offset:256
global_load_b32 v3, v1, s[4:5]
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v2, v3
global_store_b32 v1, v2, s[4:5]
.LBB1_9:
s_or_b32 exec_lo, exec_lo, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 s3, exec_lo
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
v_cmpx_gt_u32_e32 32, v0
s_cbranch_execz .LBB1_11
v_lshlrev_b32_e32 v1, 2, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v1, s6, s4, v1
v_add_co_ci_u32_e64 v2, null, s5, 0, s6
flat_load_b32 v3, v[1:2] offset:128 glc dlc
s_waitcnt vmcnt(0)
flat_load_b32 v4, v[1:2] glc dlc
s_waitcnt vmcnt(0) lgkmcnt(0)
v_add_f32_e32 v3, v3, v4
flat_store_b32 v[1:2], v3 dlc
s_waitcnt_vscnt null, 0x0
flat_load_b32 v3, v[1:2] offset:64 glc dlc
s_waitcnt vmcnt(0)
flat_load_b32 v4, v[1:2] glc dlc
s_waitcnt vmcnt(0) lgkmcnt(0)
v_add_f32_e32 v3, v3, v4
flat_store_b32 v[1:2], v3 dlc
s_waitcnt_vscnt null, 0x0
flat_load_b32 v3, v[1:2] offset:32 glc dlc
s_waitcnt vmcnt(0)
flat_load_b32 v4, v[1:2] glc dlc
s_waitcnt vmcnt(0) lgkmcnt(0)
v_add_f32_e32 v3, v3, v4
flat_store_b32 v[1:2], v3 dlc
s_waitcnt_vscnt null, 0x0
flat_load_b32 v3, v[1:2] offset:16 glc dlc
s_waitcnt vmcnt(0)
flat_load_b32 v4, v[1:2] glc dlc
s_waitcnt vmcnt(0) lgkmcnt(0)
v_add_f32_e32 v3, v3, v4
flat_store_b32 v[1:2], v3 dlc
s_waitcnt_vscnt null, 0x0
flat_load_b32 v3, v[1:2] offset:8 glc dlc
s_waitcnt vmcnt(0)
flat_load_b32 v4, v[1:2] glc dlc
s_waitcnt vmcnt(0) lgkmcnt(0)
v_add_f32_e32 v3, v3, v4
flat_store_b32 v[1:2], v3 dlc
s_waitcnt_vscnt null, 0x0
flat_load_b32 v3, v[1:2] offset:4 glc dlc
s_waitcnt vmcnt(0)
flat_load_b32 v4, v[1:2] glc dlc
s_waitcnt vmcnt(0) lgkmcnt(0)
v_add_f32_e32 v3, v3, v4
flat_store_b32 v[1:2], v3 dlc
s_waitcnt_vscnt null, 0x0
.LBB1_11:
s_or_b32 exec_lo, exec_lo, s3
v_cmp_eq_u32_e32 vcc_lo, 0, v0
s_mov_b32 s3, 0
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB1_13
v_mov_b32_e32 v0, 0
s_load_b64 s[0:1], s[0:1], 0x0
s_lshl_b64 s[2:3], s[2:3], 2
global_load_b32 v1, v0, s[4:5]
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
s_waitcnt vmcnt(0)
global_store_b32 v0, v1, s[0:1]
.LBB1_13:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z15sumUnrollGlobalPfS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z15sumUnrollGlobalPfS_i, .Lfunc_end1-_Z15sumUnrollGlobalPfS_i
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z15sumUnrollSharedPfS_i
.globl _Z15sumUnrollSharedPfS_i
.p2align 8
.type _Z15sumUnrollSharedPfS_i,@function
_Z15sumUnrollSharedPfS_i:
s_clause 0x1
s_load_b32 s6, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s5, s6, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s2, s15, s5
v_add_nc_u32_e32 v1, s2, v0
s_delay_alu instid0(VALU_DEP_1)
v_cmp_ge_u32_e32 vcc_lo, s3, v1
s_and_saveexec_b32 s3, vcc_lo
s_cbranch_execz .LBB2_13
s_load_b64 s[8:9], s[0:1], 0x8
s_mov_b32 s3, 0
v_lshlrev_b32_e32 v1, 2, v0
s_lshl_b64 s[2:3], s[2:3], 2
v_cmp_gt_u32_e32 vcc_lo, 0x200, v0
s_mov_b32 s4, s15
s_waitcnt lgkmcnt(0)
s_add_u32 s2, s8, s2
s_addc_u32 s3, s9, s3
global_load_b32 v2, v1, s[2:3]
v_cmp_lt_u16_e64 s2, 0x3ff, s6
s_delay_alu instid0(VALU_DEP_1)
s_and_b32 s3, vcc_lo, s2
s_waitcnt vmcnt(0)
ds_store_b32 v1, v2
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_and_saveexec_b32 s2, s3
s_cbranch_execz .LBB2_3
ds_load_2addr_stride64_b32 v[2:3], v1 offset1:8
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v2, v3, v2
ds_store_b32 v1, v2
.LBB2_3:
s_or_b32 exec_lo, exec_lo, s2
v_cmp_lt_u16_e64 s3, 0x1ff, s6
v_cmp_gt_u32_e32 vcc_lo, 0x100, v0
s_and_b32 s2, 0xffff, s6
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_and_b32 s6, vcc_lo, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s6
s_cbranch_execz .LBB2_5
v_lshlrev_b32_e32 v2, 2, v0
ds_load_b32 v2, v2 offset:1024
ds_load_b32 v3, v1
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v2, v2, v3
ds_store_b32 v1, v2
.LBB2_5:
s_or_b32 exec_lo, exec_lo, s3
v_cmp_gt_u32_e32 vcc_lo, 0x80, v0
s_cmpk_gt_u32 s2, 0xff
s_waitcnt lgkmcnt(0)
s_cselect_b32 s2, -1, 0
s_barrier
s_and_b32 s3, vcc_lo, s2
buffer_gl0_inv
s_and_saveexec_b32 s2, s3
s_cbranch_execz .LBB2_7
v_lshlrev_b32_e32 v2, 2, v0
ds_load_b32 v2, v2 offset:512
ds_load_b32 v3, v1
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v2, v2, v3
ds_store_b32 v1, v2
.LBB2_7:
s_or_b32 exec_lo, exec_lo, s2
v_cmp_gt_u32_e32 vcc_lo, 64, v0
s_cmpk_gt_u32 s5, 0x7f
s_waitcnt lgkmcnt(0)
s_cselect_b32 s2, -1, 0
s_barrier
s_and_b32 s3, vcc_lo, s2
buffer_gl0_inv
s_and_saveexec_b32 s2, s3
s_cbranch_execz .LBB2_9
v_lshlrev_b32_e32 v2, 2, v0
ds_load_b32 v2, v2 offset:256
ds_load_b32 v3, v1
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v2, v2, v3
ds_store_b32 v1, v2
.LBB2_9:
s_or_b32 exec_lo, exec_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 s3, exec_lo
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_gt_u32_e32 32, v0
s_cbranch_execz .LBB2_11
v_lshlrev_b32_e32 v5, 2, v0
s_mov_b64 s[6:7], src_shared_base
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v2, 0x80, v5
v_cmp_ne_u32_e64 s2, -1, v5
v_cmp_ne_u32_e32 vcc_lo, -1, v2
s_delay_alu instid0(VALU_DEP_2)
v_cndmask_b32_e64 v1, 0, v5, s2
v_cndmask_b32_e32 v3, 0, v2, vcc_lo
v_cndmask_b32_e64 v4, 0, s7, vcc_lo
v_cndmask_b32_e64 v2, 0, s7, s2
flat_load_b32 v4, v[3:4] glc dlc
s_waitcnt vmcnt(0)
flat_load_b32 v6, v[1:2] glc dlc
s_waitcnt vmcnt(0) lgkmcnt(0)
v_dual_add_f32 v6, v4, v6 :: v_dual_add_nc_u32 v3, 64, v5
flat_store_b32 v[1:2], v6 dlc
s_waitcnt_vscnt null, 0x0
v_cmp_ne_u32_e32 vcc_lo, -1, v3
v_cndmask_b32_e32 v3, 0, v3, vcc_lo
v_cndmask_b32_e64 v4, 0, s7, vcc_lo
flat_load_b32 v4, v[3:4] glc dlc
s_waitcnt vmcnt(0)
flat_load_b32 v6, v[1:2] glc dlc
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v3, 32, v5
s_delay_alu instid0(VALU_DEP_1)
v_cmp_ne_u32_e32 vcc_lo, -1, v3
s_waitcnt lgkmcnt(0)
v_dual_cndmask_b32 v3, 0, v3 :: v_dual_add_f32 v6, v4, v6
v_cndmask_b32_e64 v4, 0, s7, vcc_lo
flat_store_b32 v[1:2], v6 dlc
s_waitcnt_vscnt null, 0x0
flat_load_b32 v4, v[3:4] glc dlc
s_waitcnt vmcnt(0)
flat_load_b32 v6, v[1:2] glc dlc
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v3, 16, v5
s_delay_alu instid0(VALU_DEP_1)
v_cmp_ne_u32_e32 vcc_lo, -1, v3
s_waitcnt lgkmcnt(0)
v_dual_cndmask_b32 v3, 0, v3 :: v_dual_add_f32 v6, v4, v6
v_cndmask_b32_e64 v4, 0, s7, vcc_lo
flat_store_b32 v[1:2], v6 dlc
s_waitcnt_vscnt null, 0x0
flat_load_b32 v4, v[3:4] glc dlc
s_waitcnt vmcnt(0)
flat_load_b32 v6, v[1:2] glc dlc
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v3, 8, v5
s_delay_alu instid0(VALU_DEP_1)
v_cmp_ne_u32_e32 vcc_lo, -1, v3
s_waitcnt lgkmcnt(0)
v_dual_cndmask_b32 v3, 0, v3 :: v_dual_add_f32 v6, v4, v6
v_cndmask_b32_e64 v4, 0, s7, vcc_lo
flat_store_b32 v[1:2], v6 dlc
s_waitcnt_vscnt null, 0x0
flat_load_b32 v4, v[3:4] glc dlc
s_waitcnt vmcnt(0)
flat_load_b32 v6, v[1:2] glc dlc
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v3, 4, v5
s_delay_alu instid0(VALU_DEP_1)
v_cmp_ne_u32_e32 vcc_lo, -1, v3
v_cndmask_b32_e32 v3, 0, v3, vcc_lo
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v5, v4, v6
v_cndmask_b32_e64 v4, 0, s7, vcc_lo
flat_store_b32 v[1:2], v5 dlc
s_waitcnt_vscnt null, 0x0
flat_load_b32 v3, v[3:4] glc dlc
s_waitcnt vmcnt(0)
flat_load_b32 v4, v[1:2] glc dlc
s_waitcnt vmcnt(0) lgkmcnt(0)
v_add_f32_e32 v3, v3, v4
flat_store_b32 v[1:2], v3 dlc
s_waitcnt_vscnt null, 0x0
.LBB2_11:
s_or_b32 exec_lo, exec_lo, s3
v_cmp_eq_u32_e32 vcc_lo, 0, v0
s_mov_b32 s5, 0
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB2_13
v_mov_b32_e32 v0, 0
s_load_b64 s[0:1], s[0:1], 0x0
s_lshl_b64 s[2:3], s[4:5], 2
ds_load_b32 v1, v0
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
global_store_b32 v0, v1, s[0:1]
.LBB2_13:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z15sumUnrollSharedPfS_i
.amdhsa_group_segment_fixed_size 512
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end2:
.size _Z15sumUnrollSharedPfS_i, .Lfunc_end2-_Z15sumUnrollSharedPfS_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6warmUpPfS_i
.private_segment_fixed_size: 0
.sgpr_count: 16
.sgpr_spill_count: 0
.symbol: _Z6warmUpPfS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z15sumUnrollGlobalPfS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z15sumUnrollGlobalPfS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 512
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z15sumUnrollSharedPfS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z15sumUnrollSharedPfS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#define BLOCK_SIZE_X 128
__global__
void warmUp(float* out, float* in, int count) {
float* local_array = in + (blockIdx.x * blockDim.x);
if (threadIdx.x == 0) { out[blockIdx.x] = local_array[0]; }
}
__global__
void sumUnrollGlobal(float* out, float* in, int count) {
if ((blockIdx.x * blockDim.x) + threadIdx.x > count) return;
float* local_array = in + (blockIdx.x * blockDim.x);
if (blockDim.x >= 1024 && threadIdx.x < 512) { local_array[threadIdx.x] += local_array[threadIdx.x + 512]; }
__syncthreads();
if (blockDim.x >= 512 && threadIdx.x < 256) { local_array[threadIdx.x] += local_array[threadIdx.x + 256]; }
__syncthreads();
if (blockDim.x >= 256 && threadIdx.x < 128) { local_array[threadIdx.x] += local_array[threadIdx.x + 128]; }
__syncthreads();
if (blockDim.x >= 128 && threadIdx.x < 64) { local_array[threadIdx.x] += local_array[threadIdx.x + 64]; }
__syncthreads();
if (threadIdx.x < 32) {
volatile float* v_local_array = local_array;
v_local_array[threadIdx.x] += v_local_array[threadIdx.x + 32];
v_local_array[threadIdx.x] += v_local_array[threadIdx.x + 16];
v_local_array[threadIdx.x] += v_local_array[threadIdx.x + 8];
v_local_array[threadIdx.x] += v_local_array[threadIdx.x + 4];
v_local_array[threadIdx.x] += v_local_array[threadIdx.x + 2];
v_local_array[threadIdx.x] += v_local_array[threadIdx.x + 1];
}
if (threadIdx.x == 0) { out[blockIdx.x] = local_array[0]; }
}
__global__
void sumUnrollShared(float* out, float* in, int count) {
if ((blockIdx.x * blockDim.x) + threadIdx.x > count) return;
float* local_array = in + (blockIdx.x * blockDim.x);
__shared__ float shared_array[BLOCK_SIZE_X];
shared_array[threadIdx.x] = local_array[threadIdx.x];
__syncthreads();
if (blockDim.x >= 1024 && threadIdx.x < 512) { shared_array[threadIdx.x] += shared_array[threadIdx.x + 512]; }
__syncthreads();
if (blockDim.x >= 512 && threadIdx.x < 256) { shared_array[threadIdx.x] += shared_array[threadIdx.x + 256]; }
__syncthreads();
if (blockDim.x >= 256 && threadIdx.x < 128) { shared_array[threadIdx.x] += shared_array[threadIdx.x + 128]; }
__syncthreads();
if (blockDim.x >= 128 && threadIdx.x < 64) { shared_array[threadIdx.x] += shared_array[threadIdx.x + 64]; }
__syncthreads();
if (threadIdx.x < 32) {
volatile float* v_local_array = shared_array;
v_local_array[threadIdx.x] += v_local_array[threadIdx.x + 32];
v_local_array[threadIdx.x] += v_local_array[threadIdx.x + 16];
v_local_array[threadIdx.x] += v_local_array[threadIdx.x + 8];
v_local_array[threadIdx.x] += v_local_array[threadIdx.x + 4];
v_local_array[threadIdx.x] += v_local_array[threadIdx.x + 2];
v_local_array[threadIdx.x] += v_local_array[threadIdx.x + 1];
}
if (threadIdx.x == 0) { out[blockIdx.x] = shared_array[0]; }
}
int main(void) {
int count = 1 << 16;
dim3 block(BLOCK_SIZE_X);
dim3 grid((count + block.x - 1) / block.x);
float* host_array = (float*)malloc(count*sizeof(float));
for (int x = 0; x < count; x++) { host_array[x] = x; }
float* host_result_array = (float*)malloc(grid.x*sizeof(float));
float *device_array, *device_result_array;
hipMalloc((float**)&device_array, count*sizeof(float));
hipMemcpy(device_array, host_array, count*sizeof(float), hipMemcpyHostToDevice);
hipMalloc((float**)&device_result_array, grid.x*sizeof(float));
warmUp<<<grid,block>>>(device_result_array, device_array, count);
sumUnrollGlobal<<<grid,block>>>(device_result_array, device_array, count);
hipDeviceSynchronize();
hipMemcpy(host_result_array, device_result_array, grid.x*sizeof(float), hipMemcpyDeviceToHost);
sumUnrollShared<<<grid,block>>>(device_result_array, device_array, count);
hipDeviceSynchronize();
hipMemcpy(host_result_array, device_result_array, grid.x*sizeof(float), hipMemcpyDeviceToHost);
free(host_array);
free(host_result_array);
hipFree(device_array);
hipFree(device_result_array);
hipDeviceReset();
return 0;
} | .text
.file "array_sum_shared.hip"
.globl _Z21__device_stub__warmUpPfS_i # -- Begin function _Z21__device_stub__warmUpPfS_i
.p2align 4, 0x90
.type _Z21__device_stub__warmUpPfS_i,@function
_Z21__device_stub__warmUpPfS_i: # @_Z21__device_stub__warmUpPfS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6warmUpPfS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z21__device_stub__warmUpPfS_i, .Lfunc_end0-_Z21__device_stub__warmUpPfS_i
.cfi_endproc
# -- End function
.globl _Z30__device_stub__sumUnrollGlobalPfS_i # -- Begin function _Z30__device_stub__sumUnrollGlobalPfS_i
.p2align 4, 0x90
.type _Z30__device_stub__sumUnrollGlobalPfS_i,@function
_Z30__device_stub__sumUnrollGlobalPfS_i: # @_Z30__device_stub__sumUnrollGlobalPfS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z15sumUnrollGlobalPfS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end1:
.size _Z30__device_stub__sumUnrollGlobalPfS_i, .Lfunc_end1-_Z30__device_stub__sumUnrollGlobalPfS_i
.cfi_endproc
# -- End function
.globl _Z30__device_stub__sumUnrollSharedPfS_i # -- Begin function _Z30__device_stub__sumUnrollSharedPfS_i
.p2align 4, 0x90
.type _Z30__device_stub__sumUnrollSharedPfS_i,@function
_Z30__device_stub__sumUnrollSharedPfS_i: # @_Z30__device_stub__sumUnrollSharedPfS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z15sumUnrollSharedPfS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end2:
.size _Z30__device_stub__sumUnrollSharedPfS_i, .Lfunc_end2-_Z30__device_stub__sumUnrollSharedPfS_i
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $120, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $262144, %edi # imm = 0x40000
callq malloc
movq %rax, %rbx
xorl %eax, %eax
.p2align 4, 0x90
.LBB3_1: # =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, (%rbx,%rax,4)
incq %rax
cmpq $65536, %rax # imm = 0x10000
jne .LBB3_1
# %bb.2:
movabsq $4294967424, %r15 # imm = 0x100000080
movl $2048, %edi # imm = 0x800
callq malloc
movq %rax, %r14
leaq 24(%rsp), %rdi
movl $262144, %esi # imm = 0x40000
callq hipMalloc
movq 24(%rsp), %rdi
movl $262144, %edx # imm = 0x40000
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
leaq 16(%rsp), %rdi
movl $2048, %esi # imm = 0x800
callq hipMalloc
leaq 384(%r15), %r12
movq %r12, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_4
# %bb.3:
movq 16(%rsp), %rax
movq 24(%rsp), %rcx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movl $65536, 12(%rsp) # imm = 0x10000
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z6warmUpPfS_i, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_4:
movq %r12, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_6
# %bb.5:
movq 16(%rsp), %rax
movq 24(%rsp), %rcx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movl $65536, 12(%rsp) # imm = 0x10000
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z15sumUnrollGlobalPfS_i, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_6:
callq hipDeviceSynchronize
movq 16(%rsp), %rsi
movl $2048, %edx # imm = 0x800
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
movq %r12, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_8
# %bb.7:
movq 16(%rsp), %rax
movq 24(%rsp), %rcx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movl $65536, 12(%rsp) # imm = 0x10000
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z15sumUnrollSharedPfS_i, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_8:
callq hipDeviceSynchronize
movq 16(%rsp), %rsi
movl $2048, %edx # imm = 0x800
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
callq hipDeviceReset
xorl %eax, %eax
addq $120, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6warmUpPfS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15sumUnrollGlobalPfS_i, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15sumUnrollSharedPfS_i, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6warmUpPfS_i,@object # @_Z6warmUpPfS_i
.section .rodata,"a",@progbits
.globl _Z6warmUpPfS_i
.p2align 3, 0x0
_Z6warmUpPfS_i:
.quad _Z21__device_stub__warmUpPfS_i
.size _Z6warmUpPfS_i, 8
.type _Z15sumUnrollGlobalPfS_i,@object # @_Z15sumUnrollGlobalPfS_i
.globl _Z15sumUnrollGlobalPfS_i
.p2align 3, 0x0
_Z15sumUnrollGlobalPfS_i:
.quad _Z30__device_stub__sumUnrollGlobalPfS_i
.size _Z15sumUnrollGlobalPfS_i, 8
.type _Z15sumUnrollSharedPfS_i,@object # @_Z15sumUnrollSharedPfS_i
.globl _Z15sumUnrollSharedPfS_i
.p2align 3, 0x0
_Z15sumUnrollSharedPfS_i:
.quad _Z30__device_stub__sumUnrollSharedPfS_i
.size _Z15sumUnrollSharedPfS_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z6warmUpPfS_i"
.size .L__unnamed_1, 15
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z15sumUnrollGlobalPfS_i"
.size .L__unnamed_2, 25
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z15sumUnrollSharedPfS_i"
.size .L__unnamed_3, 25
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__warmUpPfS_i
.addrsig_sym _Z30__device_stub__sumUnrollGlobalPfS_i
.addrsig_sym _Z30__device_stub__sumUnrollSharedPfS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6warmUpPfS_i
.addrsig_sym _Z15sumUnrollGlobalPfS_i
.addrsig_sym _Z15sumUnrollSharedPfS_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0003ecda_00000000-6_array_sum_shared.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z28__device_stub__Z6warmUpPfS_iPfS_i
.type _Z28__device_stub__Z6warmUpPfS_iPfS_i, @function
_Z28__device_stub__Z6warmUpPfS_iPfS_i:
.LFB2082:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6warmUpPfS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z28__device_stub__Z6warmUpPfS_iPfS_i, .-_Z28__device_stub__Z6warmUpPfS_iPfS_i
.globl _Z6warmUpPfS_i
.type _Z6warmUpPfS_i, @function
_Z6warmUpPfS_i:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z28__device_stub__Z6warmUpPfS_iPfS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z6warmUpPfS_i, .-_Z6warmUpPfS_i
.globl _Z38__device_stub__Z15sumUnrollGlobalPfS_iPfS_i
.type _Z38__device_stub__Z15sumUnrollGlobalPfS_iPfS_i, @function
_Z38__device_stub__Z15sumUnrollGlobalPfS_iPfS_i:
.LFB2084:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z15sumUnrollGlobalPfS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z38__device_stub__Z15sumUnrollGlobalPfS_iPfS_i, .-_Z38__device_stub__Z15sumUnrollGlobalPfS_iPfS_i
.globl _Z15sumUnrollGlobalPfS_i
.type _Z15sumUnrollGlobalPfS_i, @function
_Z15sumUnrollGlobalPfS_i:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z38__device_stub__Z15sumUnrollGlobalPfS_iPfS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z15sumUnrollGlobalPfS_i, .-_Z15sumUnrollGlobalPfS_i
.globl _Z38__device_stub__Z15sumUnrollSharedPfS_iPfS_i
.type _Z38__device_stub__Z15sumUnrollSharedPfS_iPfS_i, @function
_Z38__device_stub__Z15sumUnrollSharedPfS_iPfS_i:
.LFB2086:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L23
.L19:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L24
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z15sumUnrollSharedPfS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L19
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2086:
.size _Z38__device_stub__Z15sumUnrollSharedPfS_iPfS_i, .-_Z38__device_stub__Z15sumUnrollSharedPfS_iPfS_i
.globl _Z15sumUnrollSharedPfS_i
.type _Z15sumUnrollSharedPfS_i, @function
_Z15sumUnrollSharedPfS_i:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z38__device_stub__Z15sumUnrollSharedPfS_iPfS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _Z15sumUnrollSharedPfS_i, .-_Z15sumUnrollSharedPfS_i
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $56, %rsp
.cfi_def_cfa_offset 80
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $262144, %edi
call malloc@PLT
movq %rax, %rbx
movl $0, %eax
.L28:
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, (%rbx,%rax,4)
addq $1, %rax
cmpq $65536, %rax
jne .L28
movl $2048, %edi
call malloc@PLT
movq %rax, %rbp
movq %rsp, %rdi
movl $262144, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $262144, %edx
movq %rbx, %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
leaq 8(%rsp), %rdi
movl $2048, %esi
call cudaMalloc@PLT
movl $512, 28(%rsp)
movl $128, 16(%rsp)
movl 24(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 16(%rsp), %rdx
movq 28(%rsp), %rdi
movl 36(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L35
.L29:
movl 24(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 16(%rsp), %rdx
movq 28(%rsp), %rdi
movl 36(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L36
.L30:
call cudaDeviceSynchronize@PLT
movl $2, %ecx
movl $2048, %edx
movq 8(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
movl 24(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 16(%rsp), %rdx
movq 28(%rsp), %rdi
movl 36(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L37
.L31:
call cudaDeviceSynchronize@PLT
movl $2, %ecx
movl $2048, %edx
movq 8(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
movq %rbx, %rdi
call free@PLT
movq %rbp, %rdi
call free@PLT
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
call cudaDeviceReset@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L38
movl $0, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L35:
.cfi_restore_state
movl $65536, %edx
movq (%rsp), %rsi
movq 8(%rsp), %rdi
call _Z28__device_stub__Z6warmUpPfS_iPfS_i
jmp .L29
.L36:
movl $65536, %edx
movq (%rsp), %rsi
movq 8(%rsp), %rdi
call _Z38__device_stub__Z15sumUnrollGlobalPfS_iPfS_i
jmp .L30
.L37:
movl $65536, %edx
movq (%rsp), %rsi
movq 8(%rsp), %rdi
call _Z38__device_stub__Z15sumUnrollSharedPfS_iPfS_i
jmp .L31
.L38:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z15sumUnrollSharedPfS_i"
.LC1:
.string "_Z15sumUnrollGlobalPfS_i"
.LC2:
.string "_Z6warmUpPfS_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2089:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z15sumUnrollSharedPfS_i(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z15sumUnrollGlobalPfS_i(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z6warmUpPfS_i(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2089:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "array_sum_shared.hip"
.globl _Z21__device_stub__warmUpPfS_i # -- Begin function _Z21__device_stub__warmUpPfS_i
.p2align 4, 0x90
.type _Z21__device_stub__warmUpPfS_i,@function
_Z21__device_stub__warmUpPfS_i: # @_Z21__device_stub__warmUpPfS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6warmUpPfS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z21__device_stub__warmUpPfS_i, .Lfunc_end0-_Z21__device_stub__warmUpPfS_i
.cfi_endproc
# -- End function
.globl _Z30__device_stub__sumUnrollGlobalPfS_i # -- Begin function _Z30__device_stub__sumUnrollGlobalPfS_i
.p2align 4, 0x90
.type _Z30__device_stub__sumUnrollGlobalPfS_i,@function
_Z30__device_stub__sumUnrollGlobalPfS_i: # @_Z30__device_stub__sumUnrollGlobalPfS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z15sumUnrollGlobalPfS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end1:
.size _Z30__device_stub__sumUnrollGlobalPfS_i, .Lfunc_end1-_Z30__device_stub__sumUnrollGlobalPfS_i
.cfi_endproc
# -- End function
.globl _Z30__device_stub__sumUnrollSharedPfS_i # -- Begin function _Z30__device_stub__sumUnrollSharedPfS_i
.p2align 4, 0x90
.type _Z30__device_stub__sumUnrollSharedPfS_i,@function
_Z30__device_stub__sumUnrollSharedPfS_i: # @_Z30__device_stub__sumUnrollSharedPfS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z15sumUnrollSharedPfS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end2:
.size _Z30__device_stub__sumUnrollSharedPfS_i, .Lfunc_end2-_Z30__device_stub__sumUnrollSharedPfS_i
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $120, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $262144, %edi # imm = 0x40000
callq malloc
movq %rax, %rbx
xorl %eax, %eax
.p2align 4, 0x90
.LBB3_1: # =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, (%rbx,%rax,4)
incq %rax
cmpq $65536, %rax # imm = 0x10000
jne .LBB3_1
# %bb.2:
movabsq $4294967424, %r15 # imm = 0x100000080
movl $2048, %edi # imm = 0x800
callq malloc
movq %rax, %r14
leaq 24(%rsp), %rdi
movl $262144, %esi # imm = 0x40000
callq hipMalloc
movq 24(%rsp), %rdi
movl $262144, %edx # imm = 0x40000
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
leaq 16(%rsp), %rdi
movl $2048, %esi # imm = 0x800
callq hipMalloc
leaq 384(%r15), %r12
movq %r12, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_4
# %bb.3:
movq 16(%rsp), %rax
movq 24(%rsp), %rcx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movl $65536, 12(%rsp) # imm = 0x10000
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z6warmUpPfS_i, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_4:
movq %r12, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_6
# %bb.5:
movq 16(%rsp), %rax
movq 24(%rsp), %rcx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movl $65536, 12(%rsp) # imm = 0x10000
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z15sumUnrollGlobalPfS_i, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_6:
callq hipDeviceSynchronize
movq 16(%rsp), %rsi
movl $2048, %edx # imm = 0x800
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
movq %r12, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_8
# %bb.7:
movq 16(%rsp), %rax
movq 24(%rsp), %rcx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movl $65536, 12(%rsp) # imm = 0x10000
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z15sumUnrollSharedPfS_i, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_8:
callq hipDeviceSynchronize
movq 16(%rsp), %rsi
movl $2048, %edx # imm = 0x800
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
callq hipDeviceReset
xorl %eax, %eax
addq $120, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6warmUpPfS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15sumUnrollGlobalPfS_i, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15sumUnrollSharedPfS_i, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6warmUpPfS_i,@object # @_Z6warmUpPfS_i
.section .rodata,"a",@progbits
.globl _Z6warmUpPfS_i
.p2align 3, 0x0
_Z6warmUpPfS_i:
.quad _Z21__device_stub__warmUpPfS_i
.size _Z6warmUpPfS_i, 8
.type _Z15sumUnrollGlobalPfS_i,@object # @_Z15sumUnrollGlobalPfS_i
.globl _Z15sumUnrollGlobalPfS_i
.p2align 3, 0x0
_Z15sumUnrollGlobalPfS_i:
.quad _Z30__device_stub__sumUnrollGlobalPfS_i
.size _Z15sumUnrollGlobalPfS_i, 8
.type _Z15sumUnrollSharedPfS_i,@object # @_Z15sumUnrollSharedPfS_i
.globl _Z15sumUnrollSharedPfS_i
.p2align 3, 0x0
_Z15sumUnrollSharedPfS_i:
.quad _Z30__device_stub__sumUnrollSharedPfS_i
.size _Z15sumUnrollSharedPfS_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z6warmUpPfS_i"
.size .L__unnamed_1, 15
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z15sumUnrollGlobalPfS_i"
.size .L__unnamed_2, 25
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z15sumUnrollSharedPfS_i"
.size .L__unnamed_3, 25
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__warmUpPfS_i
.addrsig_sym _Z30__device_stub__sumUnrollGlobalPfS_i
.addrsig_sym _Z30__device_stub__sumUnrollSharedPfS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6warmUpPfS_i
.addrsig_sym _Z15sumUnrollGlobalPfS_i
.addrsig_sym _Z15sumUnrollSharedPfS_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <stdio.h>
void CPU_kernel(int max_itemcount)
{
int i;
for (i = 0; i < max_itemcount; ++i)
{
printf("%i\n", i);
}
}
int main(void)
{
CPU_kernel(100);
printf("Finished execution!\n");
return 0;
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <stdio.h>
void CPU_kernel(int max_itemcount)
{
int i;
for (i = 0; i < max_itemcount; ++i)
{
printf("%i\n", i);
}
}
int main(void)
{
CPU_kernel(100);
printf("Finished execution!\n");
return 0;
} | .file "tmpxft_000dae05_00000000-6_cuda_03.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%i\n"
.text
.globl _Z10CPU_kerneli
.type _Z10CPU_kerneli, @function
_Z10CPU_kerneli:
.LFB2057:
.cfi_startproc
endbr64
testl %edi, %edi
jle .L8
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
movl %edi, %ebp
movl $0, %ebx
leaq .LC0(%rip), %r12
.L5:
movl %ebx, %edx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %ebx
cmpl %ebx, %ebp
jne .L5
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L8:
.cfi_restore 3
.cfi_restore 6
.cfi_restore 12
ret
.cfi_endproc
.LFE2057:
.size _Z10CPU_kerneli, .-_Z10CPU_kerneli
.section .rodata.str1.1
.LC1:
.string "Finished execution!\n"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl $100, %edi
call _Z10CPU_kerneli
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %eax
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <stdio.h>
void CPU_kernel(int max_itemcount)
{
int i;
for (i = 0; i < max_itemcount; ++i)
{
printf("%i\n", i);
}
}
int main(void)
{
CPU_kernel(100);
printf("Finished execution!\n");
return 0;
} | #include "hip/hip_runtime.h"
#include <stdio.h>
void CPU_kernel(int max_itemcount)
{
int i;
for (i = 0; i < max_itemcount; ++i)
{
printf("%i\n", i);
}
}
int main(void)
{
CPU_kernel(100);
printf("Finished execution!\n");
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include "hip/hip_runtime.h"
#include <stdio.h>
void CPU_kernel(int max_itemcount)
{
int i;
for (i = 0; i < max_itemcount; ++i)
{
printf("%i\n", i);
}
}
int main(void)
{
CPU_kernel(100);
printf("Finished execution!\n");
return 0;
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include "hip/hip_runtime.h"
#include <stdio.h>
void CPU_kernel(int max_itemcount)
{
int i;
for (i = 0; i < max_itemcount; ++i)
{
printf("%i\n", i);
}
}
int main(void)
{
CPU_kernel(100);
printf("Finished execution!\n");
return 0;
} | .text
.file "cuda_03.hip"
.globl _Z10CPU_kerneli # -- Begin function _Z10CPU_kerneli
.p2align 4, 0x90
.type _Z10CPU_kerneli,@function
_Z10CPU_kerneli: # @_Z10CPU_kerneli
.cfi_startproc
# %bb.0:
testl %edi, %edi
jle .LBB0_4
# %bb.1: # %.lr.ph.preheader
pushq %rbp
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %rbp, -16
movl %edi, %ebx
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB0_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl $.L.str, %edi
movl %ebp, %esi
xorl %eax, %eax
callq printf
incl %ebp
cmpl %ebp, %ebx
jne .LBB0_2
# %bb.3:
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %rbp
.LBB0_4: # %._crit_edge
retq
.Lfunc_end0:
.size _Z10CPU_kerneli, .Lfunc_end0-_Z10CPU_kerneli
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_1: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
movl $.L.str, %edi
movl %ebx, %esi
xorl %eax, %eax
callq printf
incl %ebx
cmpl $100, %ebx
jne .LBB1_1
# %bb.2: # %_Z10CPU_kerneli.exit
movl $.Lstr, %edi
callq puts@PLT
xorl %eax, %eax
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%i\n"
.size .L.str, 4
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Finished execution!"
.size .Lstr, 20
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000dae05_00000000-6_cuda_03.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%i\n"
.text
.globl _Z10CPU_kerneli
.type _Z10CPU_kerneli, @function
_Z10CPU_kerneli:
.LFB2057:
.cfi_startproc
endbr64
testl %edi, %edi
jle .L8
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
movl %edi, %ebp
movl $0, %ebx
leaq .LC0(%rip), %r12
.L5:
movl %ebx, %edx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %ebx
cmpl %ebx, %ebp
jne .L5
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L8:
.cfi_restore 3
.cfi_restore 6
.cfi_restore 12
ret
.cfi_endproc
.LFE2057:
.size _Z10CPU_kerneli, .-_Z10CPU_kerneli
.section .rodata.str1.1
.LC1:
.string "Finished execution!\n"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl $100, %edi
call _Z10CPU_kerneli
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %eax
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "cuda_03.hip"
.globl _Z10CPU_kerneli # -- Begin function _Z10CPU_kerneli
.p2align 4, 0x90
.type _Z10CPU_kerneli,@function
_Z10CPU_kerneli: # @_Z10CPU_kerneli
.cfi_startproc
# %bb.0:
testl %edi, %edi
jle .LBB0_4
# %bb.1: # %.lr.ph.preheader
pushq %rbp
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %rbp, -16
movl %edi, %ebx
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB0_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl $.L.str, %edi
movl %ebp, %esi
xorl %eax, %eax
callq printf
incl %ebp
cmpl %ebp, %ebx
jne .LBB0_2
# %bb.3:
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %rbp
.LBB0_4: # %._crit_edge
retq
.Lfunc_end0:
.size _Z10CPU_kerneli, .Lfunc_end0-_Z10CPU_kerneli
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_1: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
movl $.L.str, %edi
movl %ebx, %esi
xorl %eax, %eax
callq printf
incl %ebx
cmpl $100, %ebx
jne .LBB1_1
# %bb.2: # %_Z10CPU_kerneli.exit
movl $.Lstr, %edi
callq puts@PLT
xorl %eax, %eax
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%i\n"
.size .L.str, 4
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Finished execution!"
.size .Lstr, 20
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /* =======================================================
Student: Patricia Wilthew
The basic SDH algorithm implementation for 3D data
To compile: nvcc SDH.c -o SDH
=======================================================
*/
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <sys/time.h>
#define BOX_SIZE 23000
/*
Structure: atom.
Descriptors for single atom in the tree.
*/
typedef struct atomdesc
{
double x_pos;
double y_pos;
double z_pos;
} atom;
/*
Structure: bucket.
Size of the buckets.
*/
typedef struct hist_entry
{
long long d_cnt;
} bucket;
cudaError_t err;
long long PDH_acnt;
double PDH_res;
int num_buckets, PDH_threads;
bucket *histogram;
atom *atom_list;
struct timezone Idunno;
struct timeval startTime, endTime;
/*
Method: distance.
Distance of two points (x1, y1, z1) and (x2, y2, z2).
*/
__device__
double distance(double x1, double y1, double z1, double x2, double y2, double z2)
{
return sqrt((x1 - x2)*(x1-x2) + (y1 - y2)*(y1 - y2) + (z1 - z2)*(z1 - z2));
}
/*
Method: PDH_on_gpu.
SDH solution in GPU threads.
*/
__global__
void PDH_on_gpu(double *x, double *y, double *z, bucket *hist,
int PDH_acnt, double PDH_res, int num_buckets)
{
extern __shared__ unsigned int SHMOut[];
int t_id, b_id, t, s;
int i, h_pos;
double x1, y1, z1, x2, y2, z2, d;
t_id = threadIdx.x;
b_id = blockIdx.x;
t = b_id*blockDim.x + t_id;
// Initialize Shared Memory to Zero.
for (s = 0; s < (num_buckets + blockDim.x - 1)/blockDim.x; s++)
{
if (t_id + s*blockDim.x < num_buckets)
{
SHMOut[t_id + s*blockDim.x] = 0;
}
}
// The t-th datum of b-th input data block.
i = t + 1;
x1 = x[t];
y1 = y[t];
z1 = z[t];
for (i=t+1; i < PDH_acnt; i++)
{
x2 = x[i];
y2 = y[i];
z2 = z[i];
d = distance(x1, y1, z1, x2, y2, z2);
h_pos = (int) (d / PDH_res);
atomicAdd(&SHMOut[h_pos], 1);
}
__syncthreads();
// Write results to Global Memory.
for (s = 0; s < (num_buckets + blockDim.x - 1)/blockDim.x; s++)
{
if (t_id + s*blockDim.x < num_buckets)
{
atomicAdd((unsigned int *)&hist[t_id + s*blockDim.x].d_cnt,
SHMOut[t_id + s*blockDim.x]);
}
}
}
/*
Method: p2p_distance.
Distance of two points in the atom_list.
*/
double p2p_distance(atom *atom_list, int ind1, int ind2)
{
double x1 = atom_list[ind1].x_pos;
double x2 = atom_list[ind2].x_pos;
double y1 = atom_list[ind1].y_pos;
double y2 = atom_list[ind2].y_pos;
double z1 = atom_list[ind1].z_pos;
double z2 = atom_list[ind2].z_pos;
return sqrt((x1 - x2)*(x1-x2) + (y1 - y2)*(y1 - y2) + (z1 - z2)*(z1 - z2));
}
/*
Method: PDH_baseline.
Brute-force SDH solution in a single CPU thread.
*/
int PDH_baseline(atom *atom_list, bucket *histogram, long long PDH_acnt, double PDH_res)
{
int i, j, h_pos;
double dist;
for (i = 0; i < PDH_acnt; i++)
{
for (j = i+1; j < PDH_acnt; j++)
{
dist = p2p_distance(atom_list, i,j);
h_pos = (int) (dist / PDH_res);
histogram[h_pos].d_cnt++;
}
}
return 0;
}
/*
Method: report_running_time.
Set a checkpoint and show the (natural) running time in seconds.
*/
double report_running_time()
{
long sec_diff, usec_diff;
gettimeofday(&endTime, &Idunno);
sec_diff = endTime.tv_sec - startTime.tv_sec;
usec_diff= endTime.tv_usec-startTime.tv_usec;
if (usec_diff < 0)
{
sec_diff--;
usec_diff += 1000000;
}
printf("Running time: %ld.%06ld\n", sec_diff, usec_diff);
return (double)(sec_diff*1.0 + usec_diff/1000000.0);
}
/*
Method: output_histogram.
Print the counts in all buckets of the histogram.
*/
void output_histogram(bucket *histogram, int num_buckets)
{
int i;
long long total_cnt = 0;
for (i=0; i< num_buckets; i++)
{
if (i%5 == 0) // Print 5 buckets in a row.
printf("\n%02d: ", i);
printf("%15lld ", histogram[i].d_cnt);
total_cnt += histogram[i].d_cnt;
// Also want to make sure the total distance count is correct.
if (i == num_buckets - 1)
printf("\n T:%lld \n", total_cnt);
else printf("| ");
}
}
/*
Method: catch_error.
Prints any CUDA error to stdout.
*/
void catch_error(cudaError_t error)
{
if (error)
{
printf("Error: %s\n", cudaGetErrorString(err));
}
}
int main(int argc, char **argv)
{
if (argc <= 3)
{
printf("Usage: ./SDH {# Atoms} {# Buckets} {# Threads}\n");
exit(1);
}
if (atoi(argv[3]) < 32)
{
printf("Number of threads must be greater or equal to 32.\n");
exit(1);
}
PDH_acnt = atoi(argv[1]);
PDH_res = atof(argv[2]);
PDH_threads = atoi(argv[3]);
// Variables declaration;
float time = 0;
int i;
double *x, *y, *z, *d_x, *d_y, *d_z;
bucket *d_histogram, *h_histogram;
// bucket *difference_histogram;
// Variables initialization and mem allocation.
num_buckets = (int)(BOX_SIZE * 1.732 / PDH_res) + 1;
atom_list = (atom *)malloc(sizeof(atom) * PDH_acnt);
histogram = (bucket *)malloc(sizeof(bucket) * num_buckets);
x = (double *)malloc(sizeof(double)*PDH_acnt);
y = (double *)malloc(sizeof(double)*PDH_acnt);
z = (double *)malloc(sizeof(double)*PDH_acnt);
h_histogram = (bucket *)malloc(sizeof(bucket) * num_buckets);
// difference_histogram = (bucket *)malloc(sizeof(bucket) * num_buckets);
err = cudaSuccess;
srand(1);
// Generate data following a uniform distribution.
for (i = 0; i < PDH_acnt; i++)
{
x[i] = atom_list[i].x_pos = ((double)(rand()) / RAND_MAX) * BOX_SIZE;
y[i] = atom_list[i].y_pos = ((double)(rand()) / RAND_MAX) * BOX_SIZE;
z[i] = atom_list[i].z_pos = ((double)(rand()) / RAND_MAX) * BOX_SIZE;
}
/*
printf("----CPU----");
// Start counting time.
gettimeofday(&startTime, &Idunno);
// Call CPU single thread version to compute the histogram.
PDH_baseline(atom_list, histogram, PDH_acnt, PDH_res);
// Check the total running time.
report_running_time();
// Print out the histogram.
output_histogram(histogram, num_buckets);
*/
/* My part of the project */
// Initialize h_histogram with zeroes.
for (i = 0; i < num_buckets; i++)
{
h_histogram[i].d_cnt = 0;
}
// Allocate memory in device for single dim arrays.
err = cudaMalloc((void **)&d_x, PDH_acnt * sizeof(double)); catch_error(err);
err = cudaMalloc((void **)&d_y, PDH_acnt * sizeof(double)); catch_error(err);
err = cudaMalloc((void **)&d_z, PDH_acnt * sizeof(double)); catch_error(err);
// Allocate memory in device for histogram.
err = cudaMalloc(&d_histogram, num_buckets * sizeof(bucket)); catch_error(err);
// Copy single dim arrays to device.
err = cudaMemcpy(d_x, x, PDH_acnt * sizeof(double), cudaMemcpyHostToDevice); catch_error(err);
err = cudaMemcpy(d_y, y, PDH_acnt * sizeof(double), cudaMemcpyHostToDevice); catch_error(err);
err = cudaMemcpy(d_z, z, PDH_acnt * sizeof(double), cudaMemcpyHostToDevice); catch_error(err);
// Copy zeroed histogram from host to device.
err = cudaMemcpy(d_histogram, h_histogram, num_buckets * sizeof(bucket),
cudaMemcpyHostToDevice); catch_error(err);
// Recording variables.
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
// Start to record.
cudaEventRecord( start, 0);
// Call GPU version.
PDH_on_gpu<<<(PDH_acnt - 1 + PDH_threads)/PDH_threads,
PDH_threads,
num_buckets * sizeof(int)>>>(d_x, d_y, d_z,
d_histogram,
PDH_acnt,
PDH_res,
num_buckets);
// Stop recording.
cudaEventRecord(stop, 0);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&time, start, stop);
cudaEventDestroy(start);
cudaEventDestroy(stop);
// Copy histogram from device to host.
err = cudaMemcpy(h_histogram, d_histogram, num_buckets * sizeof(bucket),
cudaMemcpyDeviceToHost); catch_error(err);
// Print out the histogram.
output_histogram(h_histogram, num_buckets);
// Output the total running time.
printf("******** Total Running Time of Kernel = %.5f sec *******\n", time/1000.0);
/*
printf("\n----Difference between histograms:\n");
// Print the difference between the histograms.
for (i = 0; i < num_buckets; i++)
{
difference_histogram[i].d_cnt = abs(histogram[i].d_cnt - h_histogram[i].d_cnt);
}
// Print out the histograms' difference.
output_histogram(difference_histogram, num_buckets);
*/
// Free memory.
cudaFree(d_x);
cudaFree(d_y);
cudaFree(d_z);
cudaFree(d_histogram);
free(histogram);
free(h_histogram);
free(atom_list);
free(x);
free(y);
free(z);
return 0;
} | .file "tmpxft_00008be1_00000000-6_SDH.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2066:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2066:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z8distancedddddd
.type _Z8distancedddddd, @function
_Z8distancedddddd:
.LFB2057:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size _Z8distancedddddd, .-_Z8distancedddddd
.globl _Z12p2p_distanceP8atomdescii
.type _Z12p2p_distanceP8atomdescii, @function
_Z12p2p_distanceP8atomdescii:
.LFB2058:
.cfi_startproc
endbr64
movslq %esi, %rsi
leaq (%rsi,%rsi,2), %rax
leaq (%rdi,%rax,8), %rcx
movslq %edx, %rdx
leaq (%rdx,%rdx,2), %rax
leaq (%rdi,%rax,8), %rax
movsd (%rcx), %xmm1
subsd (%rax), %xmm1
movsd 8(%rcx), %xmm2
subsd 8(%rax), %xmm2
movsd 16(%rcx), %xmm0
subsd 16(%rax), %xmm0
mulsd %xmm1, %xmm1
mulsd %xmm2, %xmm2
addsd %xmm2, %xmm1
mulsd %xmm0, %xmm0
addsd %xmm1, %xmm0
sqrtsd %xmm0, %xmm0
ret
.cfi_endproc
.LFE2058:
.size _Z12p2p_distanceP8atomdescii, .-_Z12p2p_distanceP8atomdescii
.globl _Z12PDH_baselineP8atomdescP10hist_entryxd
.type _Z12PDH_baselineP8atomdescP10hist_entryxd, @function
_Z12PDH_baselineP8atomdescP10hist_entryxd:
.LFB2059:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $24, %rsp
.cfi_def_cfa_offset 80
movq %rdx, 16(%rsp)
movsd %xmm0, (%rsp)
testq %rdx, %rdx
jle .L7
movq %rdi, %r13
movq %rsi, %rbp
leaq -1(%rdx), %rcx
movq %rcx, 8(%rsp)
movl $0, %r15d
movl %edx, %r14d
.L9:
movl %r15d, %r12d
leal 1(%r15), %ebx
movq 8(%rsp), %rax
cmpq %rax, %r15
je .L7
.L8:
movl %ebx, %edx
movl %r12d, %esi
movq %r13, %rdi
call _Z12p2p_distanceP8atomdescii
divsd (%rsp), %xmm0
cvttsd2sil %xmm0, %eax
cltq
addq $1, 0(%rbp,%rax,8)
addl $1, %ebx
cmpl %ebx, %r14d
jne .L8
addq $1, %r15
movq 16(%rsp), %rax
cmpq %rax, %r15
jne .L9
.L7:
movl $0, %eax
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size _Z12PDH_baselineP8atomdescP10hist_entryxd, .-_Z12PDH_baselineP8atomdescP10hist_entryxd
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Running time: %ld.%06ld\n"
.text
.globl _Z19report_running_timev
.type _Z19report_running_timev, @function
_Z19report_running_timev:
.LFB2060:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
leaq Idunno(%rip), %rsi
leaq endTime(%rip), %rdi
call gettimeofday@PLT
movq endTime(%rip), %rbp
subq startTime(%rip), %rbp
movq 8+endTime(%rip), %rbx
subq 8+startTime(%rip), %rbx
js .L16
.L14:
movq %rbx, %rcx
movq %rbp, %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
pxor %xmm0, %xmm0
cvtsi2sdq %rbx, %xmm0
divsd .LC1(%rip), %xmm0
pxor %xmm1, %xmm1
cvtsi2sdq %rbp, %xmm1
addsd %xmm1, %xmm0
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L16:
.cfi_restore_state
subq $1, %rbp
addq $1000000, %rbx
jmp .L14
.cfi_endproc
.LFE2060:
.size _Z19report_running_timev, .-_Z19report_running_timev
.section .rodata.str1.1
.LC2:
.string "\n%02d: "
.LC3:
.string "%15lld "
.LC4:
.string "\n T:%lld \n"
.LC5:
.string "| "
.text
.globl _Z16output_histogramP10hist_entryi
.type _Z16output_histogramP10hist_entryi, @function
_Z16output_histogramP10hist_entryi:
.LFB2061:
.cfi_startproc
endbr64
testl %esi, %esi
jle .L25
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $8, %rsp
.cfi_def_cfa_offset 64
movq %rdi, %rbp
movl %esi, %r13d
movslq %esi, %r15
movl $0, %ebx
movl $0, %r12d
leaq .LC3(%rip), %r14
jmp .L22
.L19:
movq 0(%rbp,%rbx,8), %rdx
movq %r14, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %r12, %rdx
addq 0(%rbp,%rbx,8), %rdx
movq %rdx, %r12
leal -1(%r13), %eax
cmpl %ebx, %eax
je .L28
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L21:
addq $1, %rbx
cmpq %r15, %rbx
je .L29
.L22:
movslq %ebx, %rax
imulq $1717986919, %rax, %rax
sarq $33, %rax
movl %ebx, %edx
sarl $31, %edx
subl %edx, %eax
leal (%rax,%rax,4), %eax
cmpl %ebx, %eax
jne .L19
movl %ebx, %edx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L19
.L28:
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L21
.L29:
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L25:
.cfi_restore 3
.cfi_restore 6
.cfi_restore 12
.cfi_restore 13
.cfi_restore 14
.cfi_restore 15
ret
.cfi_endproc
.LFE2061:
.size _Z16output_histogramP10hist_entryi, .-_Z16output_histogramP10hist_entryi
.section .rodata.str1.1
.LC6:
.string "Error: %s\n"
.text
.globl _Z11catch_error9cudaError
.type _Z11catch_error9cudaError, @function
_Z11catch_error9cudaError:
.LFB2062:
.cfi_startproc
endbr64
testl %edi, %edi
jne .L36
ret
.L36:
subq $8, %rsp
.cfi_def_cfa_offset 16
movl err(%rip), %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _Z11catch_error9cudaError, .-_Z11catch_error9cudaError
.globl _Z50__device_stub__Z10PDH_on_gpuPdS_S_P10hist_entryidiPdS_S_P10hist_entryidi
.type _Z50__device_stub__Z10PDH_on_gpuPdS_S_P10hist_entryidiPdS_S_P10hist_entryidi, @function
_Z50__device_stub__Z10PDH_on_gpuPdS_S_P10hist_entryidiPdS_S_P10hist_entryidi:
.LFB2088:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movl %r8d, 12(%rsp)
movsd %xmm0, (%rsp)
movl %r9d, 8(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 12(%rsp), %rax
movq %rax, 144(%rsp)
movq %rsp, %rax
movq %rax, 152(%rsp)
leaq 8(%rsp), %rax
movq %rax, 160(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L41
.L37:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L42
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L41:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z10PDH_on_gpuPdS_S_P10hist_entryidi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L37
.L42:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2088:
.size _Z50__device_stub__Z10PDH_on_gpuPdS_S_P10hist_entryidiPdS_S_P10hist_entryidi, .-_Z50__device_stub__Z10PDH_on_gpuPdS_S_P10hist_entryidiPdS_S_P10hist_entryidi
.globl _Z10PDH_on_gpuPdS_S_P10hist_entryidi
.type _Z10PDH_on_gpuPdS_S_P10hist_entryidi, @function
_Z10PDH_on_gpuPdS_S_P10hist_entryidi:
.LFB2089:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z50__device_stub__Z10PDH_on_gpuPdS_S_P10hist_entryidiPdS_S_P10hist_entryidi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2089:
.size _Z10PDH_on_gpuPdS_S_P10hist_entryidi, .-_Z10PDH_on_gpuPdS_S_P10hist_entryidi
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC7:
.string "Usage: ./SDH {# Atoms} {# Buckets} {# Threads}\n"
.align 8
.LC8:
.string "Number of threads must be greater or equal to 32.\n"
.align 8
.LC14:
.string "******** Total Running Time of Kernel = %.5f sec *******\n"
.text
.globl main
.type main, @function
main:
.LFB2063:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $104, %rsp
.cfi_def_cfa_offset 160
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
cmpl $3, %edi
jle .L57
movq %rsi, %rbx
movq 24(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
cmpl $31, %eax
jle .L58
movq 8(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
cltq
movq %rax, PDH_acnt(%rip)
movq 16(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, PDH_res(%rip)
movq 24(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movl %eax, PDH_threads(%rip)
movl $0x00000000, 12(%rsp)
movsd .LC10(%rip), %xmm0
divsd PDH_res(%rip), %xmm0
cvttsd2sil %xmm0, %ebp
addl $1, %ebp
movl %ebp, num_buckets(%rip)
movq PDH_acnt(%rip), %rbx
leaq (%rbx,%rbx,2), %rdi
salq $3, %rdi
call malloc@PLT
movq %rax, atom_list(%rip)
movslq %ebp, %rbp
salq $3, %rbp
movq %rbp, %rdi
call malloc@PLT
movq %rax, histogram(%rip)
salq $3, %rbx
movq %rbx, %rdi
call malloc@PLT
movq %rax, %r14
movq %rbx, %rdi
call malloc@PLT
movq %rax, %r13
movq %rbx, %rdi
call malloc@PLT
movq %rax, %r12
movq %rbp, %rdi
call malloc@PLT
movq %rax, %r15
movl $0, err(%rip)
movl $1, %edi
call srand@PLT
movq PDH_acnt(%rip), %rsi
testq %rsi, %rsi
jle .L48
movl $0, %ebx
.L49:
call rand@PLT
movl %eax, %edx
leaq (%rbx,%rbx,2), %rax
leaq 0(,%rax,8), %rbp
pxor %xmm0, %xmm0
cvtsi2sdl %edx, %xmm0
divsd .LC11(%rip), %xmm0
mulsd .LC12(%rip), %xmm0
movq atom_list(%rip), %rdx
movsd %xmm0, (%rdx,%rax,8)
movsd %xmm0, (%r14,%rbx,8)
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
divsd .LC11(%rip), %xmm0
mulsd .LC12(%rip), %xmm0
movq atom_list(%rip), %rax
movsd %xmm0, 8(%rax,%rbp)
movsd %xmm0, 0(%r13,%rbx,8)
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
divsd .LC11(%rip), %xmm0
mulsd .LC12(%rip), %xmm0
movq atom_list(%rip), %rax
movsd %xmm0, 16(%rax,%rbp)
movsd %xmm0, (%r12,%rbx,8)
movq PDH_acnt(%rip), %rsi
addq $1, %rbx
cmpq %rbx, %rsi
jg .L49
.L48:
movl num_buckets(%rip), %edx
testl %edx, %edx
jle .L50
movq %r15, %rax
movslq %edx, %rdx
leaq (%r15,%rdx,8), %rdx
.L51:
movq $0, (%rax)
addq $8, %rax
cmpq %rdx, %rax
jne .L51
.L50:
salq $3, %rsi
leaq 16(%rsp), %rdi
call cudaMalloc@PLT
movl %eax, %edi
movl %eax, err(%rip)
call _Z11catch_error9cudaError
movq PDH_acnt(%rip), %rax
leaq 0(,%rax,8), %rsi
leaq 24(%rsp), %rdi
call cudaMalloc@PLT
movl %eax, %edi
movl %eax, err(%rip)
call _Z11catch_error9cudaError
movq PDH_acnt(%rip), %rax
leaq 0(,%rax,8), %rsi
leaq 32(%rsp), %rdi
call cudaMalloc@PLT
movl %eax, %edi
movl %eax, err(%rip)
call _Z11catch_error9cudaError
movslq num_buckets(%rip), %rsi
salq $3, %rsi
leaq 40(%rsp), %rdi
call cudaMalloc@PLT
movl %eax, %edi
movl %eax, err(%rip)
call _Z11catch_error9cudaError
movq PDH_acnt(%rip), %rax
leaq 0(,%rax,8), %rdx
movl $1, %ecx
movq %r14, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
movl %eax, err(%rip)
call _Z11catch_error9cudaError
movq PDH_acnt(%rip), %rax
leaq 0(,%rax,8), %rdx
movl $1, %ecx
movq %r13, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
movl %eax, err(%rip)
call _Z11catch_error9cudaError
movq PDH_acnt(%rip), %rax
leaq 0(,%rax,8), %rdx
movl $1, %ecx
movq %r12, %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
movl %eax, err(%rip)
call _Z11catch_error9cudaError
movslq num_buckets(%rip), %rdx
salq $3, %rdx
movl $1, %ecx
movq %r15, %rsi
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
movl %eax, err(%rip)
call _Z11catch_error9cudaError
leaq 48(%rsp), %rdi
call cudaEventCreate@PLT
leaq 56(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 48(%rsp), %rdi
call cudaEventRecord@PLT
movslq num_buckets(%rip), %rsi
movl PDH_threads(%rip), %ecx
movl %ecx, 76(%rsp)
movl $1, 80(%rsp)
movslq %ecx, %rcx
movq PDH_acnt(%rip), %rax
leaq -1(%rcx,%rax), %rax
cqto
idivq %rcx
movl %eax, 64(%rsp)
movl $1, 68(%rsp)
movl $0, %r9d
leaq 0(,%rsi,4), %r8
movq 76(%rsp), %rdx
movl $1, %ecx
movq 64(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L59
.L52:
movl $0, %esi
movq 56(%rsp), %rdi
call cudaEventRecord@PLT
movq 56(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 12(%rsp), %rdi
movq 56(%rsp), %rdx
movq 48(%rsp), %rsi
call cudaEventElapsedTime@PLT
movq 48(%rsp), %rdi
call cudaEventDestroy@PLT
movq 56(%rsp), %rdi
call cudaEventDestroy@PLT
movslq num_buckets(%rip), %rdx
salq $3, %rdx
movl $2, %ecx
movq 40(%rsp), %rsi
movq %r15, %rdi
call cudaMemcpy@PLT
movl %eax, %edi
movl %eax, err(%rip)
call _Z11catch_error9cudaError
movl num_buckets(%rip), %esi
movq %r15, %rdi
call _Z16output_histogramP10hist_entryi
pxor %xmm0, %xmm0
cvtss2sd 12(%rsp), %xmm0
divsd .LC13(%rip), %xmm0
leaq .LC14(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq histogram(%rip), %rdi
call free@PLT
movq %r15, %rdi
call free@PLT
movq atom_list(%rip), %rdi
call free@PLT
movq %r14, %rdi
call free@PLT
movq %r13, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L60
movl $0, %eax
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L57:
.cfi_restore_state
leaq .LC7(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L58:
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L59:
movl num_buckets(%rip), %r9d
movsd PDH_res(%rip), %xmm0
movl PDH_acnt(%rip), %r8d
movq 40(%rsp), %rcx
movq 32(%rsp), %rdx
movq 24(%rsp), %rsi
movq 16(%rsp), %rdi
call _Z50__device_stub__Z10PDH_on_gpuPdS_S_P10hist_entryidiPdS_S_P10hist_entryidi
jmp .L52
.L60:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2063:
.size main, .-main
.section .rodata.str1.8
.align 8
.LC15:
.string "_Z10PDH_on_gpuPdS_S_P10hist_entryidi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2091:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC15(%rip), %rdx
movq %rdx, %rcx
leaq _Z10PDH_on_gpuPdS_S_P10hist_entryidi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2091:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl endTime
.bss
.align 16
.type endTime, @object
.size endTime, 16
endTime:
.zero 16
.globl startTime
.align 16
.type startTime, @object
.size startTime, 16
startTime:
.zero 16
.globl Idunno
.align 8
.type Idunno, @object
.size Idunno, 8
Idunno:
.zero 8
.globl atom_list
.align 8
.type atom_list, @object
.size atom_list, 8
atom_list:
.zero 8
.globl histogram
.align 8
.type histogram, @object
.size histogram, 8
histogram:
.zero 8
.globl PDH_threads
.align 4
.type PDH_threads, @object
.size PDH_threads, 4
PDH_threads:
.zero 4
.globl num_buckets
.align 4
.type num_buckets, @object
.size num_buckets, 4
num_buckets:
.zero 4
.globl PDH_res
.align 8
.type PDH_res, @object
.size PDH_res, 8
PDH_res:
.zero 8
.globl PDH_acnt
.align 8
.type PDH_acnt, @object
.size PDH_acnt, 8
PDH_acnt:
.zero 8
.globl err
.align 4
.type err, @object
.size err, 4
err:
.zero 4
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC1:
.long 0
.long 1093567616
.align 8
.LC10:
.long 0
.long 1088648064
.align 8
.LC11:
.long -4194304
.long 1105199103
.align 8
.LC12:
.long 0
.long 1087796736
.align 8
.LC13:
.long 0
.long 1083129856
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /* =======================================================
Student: Patricia Wilthew
The basic SDH algorithm implementation for 3D data
To compile: nvcc SDH.c -o SDH
=======================================================
*/
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <sys/time.h>
#define BOX_SIZE 23000
/*
Structure: atom.
Descriptors for single atom in the tree.
*/
typedef struct atomdesc
{
double x_pos;
double y_pos;
double z_pos;
} atom;
/*
Structure: bucket.
Size of the buckets.
*/
typedef struct hist_entry
{
long long d_cnt;
} bucket;
cudaError_t err;
long long PDH_acnt;
double PDH_res;
int num_buckets, PDH_threads;
bucket *histogram;
atom *atom_list;
struct timezone Idunno;
struct timeval startTime, endTime;
/*
Method: distance.
Distance of two points (x1, y1, z1) and (x2, y2, z2).
*/
__device__
double distance(double x1, double y1, double z1, double x2, double y2, double z2)
{
return sqrt((x1 - x2)*(x1-x2) + (y1 - y2)*(y1 - y2) + (z1 - z2)*(z1 - z2));
}
/*
Method: PDH_on_gpu.
SDH solution in GPU threads.
*/
__global__
void PDH_on_gpu(double *x, double *y, double *z, bucket *hist,
int PDH_acnt, double PDH_res, int num_buckets)
{
extern __shared__ unsigned int SHMOut[];
int t_id, b_id, t, s;
int i, h_pos;
double x1, y1, z1, x2, y2, z2, d;
t_id = threadIdx.x;
b_id = blockIdx.x;
t = b_id*blockDim.x + t_id;
// Initialize Shared Memory to Zero.
for (s = 0; s < (num_buckets + blockDim.x - 1)/blockDim.x; s++)
{
if (t_id + s*blockDim.x < num_buckets)
{
SHMOut[t_id + s*blockDim.x] = 0;
}
}
// The t-th datum of b-th input data block.
i = t + 1;
x1 = x[t];
y1 = y[t];
z1 = z[t];
for (i=t+1; i < PDH_acnt; i++)
{
x2 = x[i];
y2 = y[i];
z2 = z[i];
d = distance(x1, y1, z1, x2, y2, z2);
h_pos = (int) (d / PDH_res);
atomicAdd(&SHMOut[h_pos], 1);
}
__syncthreads();
// Write results to Global Memory.
for (s = 0; s < (num_buckets + blockDim.x - 1)/blockDim.x; s++)
{
if (t_id + s*blockDim.x < num_buckets)
{
atomicAdd((unsigned int *)&hist[t_id + s*blockDim.x].d_cnt,
SHMOut[t_id + s*blockDim.x]);
}
}
}
/*
Method: p2p_distance.
Distance of two points in the atom_list.
*/
double p2p_distance(atom *atom_list, int ind1, int ind2)
{
double x1 = atom_list[ind1].x_pos;
double x2 = atom_list[ind2].x_pos;
double y1 = atom_list[ind1].y_pos;
double y2 = atom_list[ind2].y_pos;
double z1 = atom_list[ind1].z_pos;
double z2 = atom_list[ind2].z_pos;
return sqrt((x1 - x2)*(x1-x2) + (y1 - y2)*(y1 - y2) + (z1 - z2)*(z1 - z2));
}
/*
Method: PDH_baseline.
Brute-force SDH solution in a single CPU thread.
*/
int PDH_baseline(atom *atom_list, bucket *histogram, long long PDH_acnt, double PDH_res)
{
int i, j, h_pos;
double dist;
for (i = 0; i < PDH_acnt; i++)
{
for (j = i+1; j < PDH_acnt; j++)
{
dist = p2p_distance(atom_list, i,j);
h_pos = (int) (dist / PDH_res);
histogram[h_pos].d_cnt++;
}
}
return 0;
}
/*
Method: report_running_time.
Set a checkpoint and show the (natural) running time in seconds.
*/
double report_running_time()
{
long sec_diff, usec_diff;
gettimeofday(&endTime, &Idunno);
sec_diff = endTime.tv_sec - startTime.tv_sec;
usec_diff= endTime.tv_usec-startTime.tv_usec;
if (usec_diff < 0)
{
sec_diff--;
usec_diff += 1000000;
}
printf("Running time: %ld.%06ld\n", sec_diff, usec_diff);
return (double)(sec_diff*1.0 + usec_diff/1000000.0);
}
/*
Method: output_histogram.
Print the counts in all buckets of the histogram.
*/
void output_histogram(bucket *histogram, int num_buckets)
{
int i;
long long total_cnt = 0;
for (i=0; i< num_buckets; i++)
{
if (i%5 == 0) // Print 5 buckets in a row.
printf("\n%02d: ", i);
printf("%15lld ", histogram[i].d_cnt);
total_cnt += histogram[i].d_cnt;
// Also want to make sure the total distance count is correct.
if (i == num_buckets - 1)
printf("\n T:%lld \n", total_cnt);
else printf("| ");
}
}
/*
Method: catch_error.
Prints any CUDA error to stdout.
*/
void catch_error(cudaError_t error)
{
if (error)
{
printf("Error: %s\n", cudaGetErrorString(err));
}
}
int main(int argc, char **argv)
{
if (argc <= 3)
{
printf("Usage: ./SDH {# Atoms} {# Buckets} {# Threads}\n");
exit(1);
}
if (atoi(argv[3]) < 32)
{
printf("Number of threads must be greater or equal to 32.\n");
exit(1);
}
PDH_acnt = atoi(argv[1]);
PDH_res = atof(argv[2]);
PDH_threads = atoi(argv[3]);
// Variables declaration;
float time = 0;
int i;
double *x, *y, *z, *d_x, *d_y, *d_z;
bucket *d_histogram, *h_histogram;
// bucket *difference_histogram;
// Variables initialization and mem allocation.
num_buckets = (int)(BOX_SIZE * 1.732 / PDH_res) + 1;
atom_list = (atom *)malloc(sizeof(atom) * PDH_acnt);
histogram = (bucket *)malloc(sizeof(bucket) * num_buckets);
x = (double *)malloc(sizeof(double)*PDH_acnt);
y = (double *)malloc(sizeof(double)*PDH_acnt);
z = (double *)malloc(sizeof(double)*PDH_acnt);
h_histogram = (bucket *)malloc(sizeof(bucket) * num_buckets);
// difference_histogram = (bucket *)malloc(sizeof(bucket) * num_buckets);
err = cudaSuccess;
srand(1);
// Generate data following a uniform distribution.
for (i = 0; i < PDH_acnt; i++)
{
x[i] = atom_list[i].x_pos = ((double)(rand()) / RAND_MAX) * BOX_SIZE;
y[i] = atom_list[i].y_pos = ((double)(rand()) / RAND_MAX) * BOX_SIZE;
z[i] = atom_list[i].z_pos = ((double)(rand()) / RAND_MAX) * BOX_SIZE;
}
/*
printf("----CPU----");
// Start counting time.
gettimeofday(&startTime, &Idunno);
// Call CPU single thread version to compute the histogram.
PDH_baseline(atom_list, histogram, PDH_acnt, PDH_res);
// Check the total running time.
report_running_time();
// Print out the histogram.
output_histogram(histogram, num_buckets);
*/
/* My part of the project */
// Initialize h_histogram with zeroes.
for (i = 0; i < num_buckets; i++)
{
h_histogram[i].d_cnt = 0;
}
// Allocate memory in device for single dim arrays.
err = cudaMalloc((void **)&d_x, PDH_acnt * sizeof(double)); catch_error(err);
err = cudaMalloc((void **)&d_y, PDH_acnt * sizeof(double)); catch_error(err);
err = cudaMalloc((void **)&d_z, PDH_acnt * sizeof(double)); catch_error(err);
// Allocate memory in device for histogram.
err = cudaMalloc(&d_histogram, num_buckets * sizeof(bucket)); catch_error(err);
// Copy single dim arrays to device.
err = cudaMemcpy(d_x, x, PDH_acnt * sizeof(double), cudaMemcpyHostToDevice); catch_error(err);
err = cudaMemcpy(d_y, y, PDH_acnt * sizeof(double), cudaMemcpyHostToDevice); catch_error(err);
err = cudaMemcpy(d_z, z, PDH_acnt * sizeof(double), cudaMemcpyHostToDevice); catch_error(err);
// Copy zeroed histogram from host to device.
err = cudaMemcpy(d_histogram, h_histogram, num_buckets * sizeof(bucket),
cudaMemcpyHostToDevice); catch_error(err);
// Recording variables.
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
// Start to record.
cudaEventRecord( start, 0);
// Call GPU version.
PDH_on_gpu<<<(PDH_acnt - 1 + PDH_threads)/PDH_threads,
PDH_threads,
num_buckets * sizeof(int)>>>(d_x, d_y, d_z,
d_histogram,
PDH_acnt,
PDH_res,
num_buckets);
// Stop recording.
cudaEventRecord(stop, 0);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&time, start, stop);
cudaEventDestroy(start);
cudaEventDestroy(stop);
// Copy histogram from device to host.
err = cudaMemcpy(h_histogram, d_histogram, num_buckets * sizeof(bucket),
cudaMemcpyDeviceToHost); catch_error(err);
// Print out the histogram.
output_histogram(h_histogram, num_buckets);
// Output the total running time.
printf("******** Total Running Time of Kernel = %.5f sec *******\n", time/1000.0);
/*
printf("\n----Difference between histograms:\n");
// Print the difference between the histograms.
for (i = 0; i < num_buckets; i++)
{
difference_histogram[i].d_cnt = abs(histogram[i].d_cnt - h_histogram[i].d_cnt);
}
// Print out the histograms' difference.
output_histogram(difference_histogram, num_buckets);
*/
// Free memory.
cudaFree(d_x);
cudaFree(d_y);
cudaFree(d_z);
cudaFree(d_histogram);
free(histogram);
free(h_histogram);
free(atom_list);
free(x);
free(y);
free(z);
return 0;
} | /* =======================================================
Student: Patricia Wilthew
The basic SDH algorithm implementation for 3D data
To compile: nvcc SDH.c -o SDH
=======================================================
*/
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <sys/time.h>
#define BOX_SIZE 23000
/*
Structure: atom.
Descriptors for single atom in the tree.
*/
typedef struct atomdesc
{
double x_pos;
double y_pos;
double z_pos;
} atom;
/*
Structure: bucket.
Size of the buckets.
*/
typedef struct hist_entry
{
long long d_cnt;
} bucket;
hipError_t err;
long long PDH_acnt;
double PDH_res;
int num_buckets, PDH_threads;
bucket *histogram;
atom *atom_list;
struct timezone Idunno;
struct timeval startTime, endTime;
/*
Method: distance.
Distance of two points (x1, y1, z1) and (x2, y2, z2).
*/
__device__
double distance(double x1, double y1, double z1, double x2, double y2, double z2)
{
return sqrt((x1 - x2)*(x1-x2) + (y1 - y2)*(y1 - y2) + (z1 - z2)*(z1 - z2));
}
/*
Method: PDH_on_gpu.
SDH solution in GPU threads.
*/
__global__
void PDH_on_gpu(double *x, double *y, double *z, bucket *hist,
int PDH_acnt, double PDH_res, int num_buckets)
{
extern __shared__ unsigned int SHMOut[];
int t_id, b_id, t, s;
int i, h_pos;
double x1, y1, z1, x2, y2, z2, d;
t_id = threadIdx.x;
b_id = blockIdx.x;
t = b_id*blockDim.x + t_id;
// Initialize Shared Memory to Zero.
for (s = 0; s < (num_buckets + blockDim.x - 1)/blockDim.x; s++)
{
if (t_id + s*blockDim.x < num_buckets)
{
SHMOut[t_id + s*blockDim.x] = 0;
}
}
// The t-th datum of b-th input data block.
i = t + 1;
x1 = x[t];
y1 = y[t];
z1 = z[t];
for (i=t+1; i < PDH_acnt; i++)
{
x2 = x[i];
y2 = y[i];
z2 = z[i];
d = distance(x1, y1, z1, x2, y2, z2);
h_pos = (int) (d / PDH_res);
atomicAdd(&SHMOut[h_pos], 1);
}
__syncthreads();
// Write results to Global Memory.
for (s = 0; s < (num_buckets + blockDim.x - 1)/blockDim.x; s++)
{
if (t_id + s*blockDim.x < num_buckets)
{
atomicAdd((unsigned int *)&hist[t_id + s*blockDim.x].d_cnt,
SHMOut[t_id + s*blockDim.x]);
}
}
}
/*
Method: p2p_distance.
Distance of two points in the atom_list.
*/
double p2p_distance(atom *atom_list, int ind1, int ind2)
{
double x1 = atom_list[ind1].x_pos;
double x2 = atom_list[ind2].x_pos;
double y1 = atom_list[ind1].y_pos;
double y2 = atom_list[ind2].y_pos;
double z1 = atom_list[ind1].z_pos;
double z2 = atom_list[ind2].z_pos;
return sqrt((x1 - x2)*(x1-x2) + (y1 - y2)*(y1 - y2) + (z1 - z2)*(z1 - z2));
}
/*
Method: PDH_baseline.
Brute-force SDH solution in a single CPU thread.
*/
int PDH_baseline(atom *atom_list, bucket *histogram, long long PDH_acnt, double PDH_res)
{
int i, j, h_pos;
double dist;
for (i = 0; i < PDH_acnt; i++)
{
for (j = i+1; j < PDH_acnt; j++)
{
dist = p2p_distance(atom_list, i,j);
h_pos = (int) (dist / PDH_res);
histogram[h_pos].d_cnt++;
}
}
return 0;
}
/*
Method: report_running_time.
Set a checkpoint and show the (natural) running time in seconds.
*/
double report_running_time()
{
long sec_diff, usec_diff;
gettimeofday(&endTime, &Idunno);
sec_diff = endTime.tv_sec - startTime.tv_sec;
usec_diff= endTime.tv_usec-startTime.tv_usec;
if (usec_diff < 0)
{
sec_diff--;
usec_diff += 1000000;
}
printf("Running time: %ld.%06ld\n", sec_diff, usec_diff);
return (double)(sec_diff*1.0 + usec_diff/1000000.0);
}
/*
Method: output_histogram.
Print the counts in all buckets of the histogram.
*/
void output_histogram(bucket *histogram, int num_buckets)
{
int i;
long long total_cnt = 0;
for (i=0; i< num_buckets; i++)
{
if (i%5 == 0) // Print 5 buckets in a row.
printf("\n%02d: ", i);
printf("%15lld ", histogram[i].d_cnt);
total_cnt += histogram[i].d_cnt;
// Also want to make sure the total distance count is correct.
if (i == num_buckets - 1)
printf("\n T:%lld \n", total_cnt);
else printf("| ");
}
}
/*
Method: catch_error.
Prints any CUDA error to stdout.
*/
void catch_error(hipError_t error)
{
if (error)
{
printf("Error: %s\n", hipGetErrorString(err));
}
}
int main(int argc, char **argv)
{
if (argc <= 3)
{
printf("Usage: ./SDH {# Atoms} {# Buckets} {# Threads}\n");
exit(1);
}
if (atoi(argv[3]) < 32)
{
printf("Number of threads must be greater or equal to 32.\n");
exit(1);
}
PDH_acnt = atoi(argv[1]);
PDH_res = atof(argv[2]);
PDH_threads = atoi(argv[3]);
// Variables declaration;
float time = 0;
int i;
double *x, *y, *z, *d_x, *d_y, *d_z;
bucket *d_histogram, *h_histogram;
// bucket *difference_histogram;
// Variables initialization and mem allocation.
num_buckets = (int)(BOX_SIZE * 1.732 / PDH_res) + 1;
atom_list = (atom *)malloc(sizeof(atom) * PDH_acnt);
histogram = (bucket *)malloc(sizeof(bucket) * num_buckets);
x = (double *)malloc(sizeof(double)*PDH_acnt);
y = (double *)malloc(sizeof(double)*PDH_acnt);
z = (double *)malloc(sizeof(double)*PDH_acnt);
h_histogram = (bucket *)malloc(sizeof(bucket) * num_buckets);
// difference_histogram = (bucket *)malloc(sizeof(bucket) * num_buckets);
err = hipSuccess;
srand(1);
// Generate data following a uniform distribution.
for (i = 0; i < PDH_acnt; i++)
{
x[i] = atom_list[i].x_pos = ((double)(rand()) / RAND_MAX) * BOX_SIZE;
y[i] = atom_list[i].y_pos = ((double)(rand()) / RAND_MAX) * BOX_SIZE;
z[i] = atom_list[i].z_pos = ((double)(rand()) / RAND_MAX) * BOX_SIZE;
}
/*
printf("----CPU----");
// Start counting time.
gettimeofday(&startTime, &Idunno);
// Call CPU single thread version to compute the histogram.
PDH_baseline(atom_list, histogram, PDH_acnt, PDH_res);
// Check the total running time.
report_running_time();
// Print out the histogram.
output_histogram(histogram, num_buckets);
*/
/* My part of the project */
// Initialize h_histogram with zeroes.
for (i = 0; i < num_buckets; i++)
{
h_histogram[i].d_cnt = 0;
}
// Allocate memory in device for single dim arrays.
err = hipMalloc((void **)&d_x, PDH_acnt * sizeof(double)); catch_error(err);
err = hipMalloc((void **)&d_y, PDH_acnt * sizeof(double)); catch_error(err);
err = hipMalloc((void **)&d_z, PDH_acnt * sizeof(double)); catch_error(err);
// Allocate memory in device for histogram.
err = hipMalloc(&d_histogram, num_buckets * sizeof(bucket)); catch_error(err);
// Copy single dim arrays to device.
err = hipMemcpy(d_x, x, PDH_acnt * sizeof(double), hipMemcpyHostToDevice); catch_error(err);
err = hipMemcpy(d_y, y, PDH_acnt * sizeof(double), hipMemcpyHostToDevice); catch_error(err);
err = hipMemcpy(d_z, z, PDH_acnt * sizeof(double), hipMemcpyHostToDevice); catch_error(err);
// Copy zeroed histogram from host to device.
err = hipMemcpy(d_histogram, h_histogram, num_buckets * sizeof(bucket),
hipMemcpyHostToDevice); catch_error(err);
// Recording variables.
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
// Start to record.
hipEventRecord( start, 0);
// Call GPU version.
PDH_on_gpu<<<(PDH_acnt - 1 + PDH_threads)/PDH_threads,
PDH_threads,
num_buckets * sizeof(int)>>>(d_x, d_y, d_z,
d_histogram,
PDH_acnt,
PDH_res,
num_buckets);
// Stop recording.
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
hipEventElapsedTime(&time, start, stop);
hipEventDestroy(start);
hipEventDestroy(stop);
// Copy histogram from device to host.
err = hipMemcpy(h_histogram, d_histogram, num_buckets * sizeof(bucket),
hipMemcpyDeviceToHost); catch_error(err);
// Print out the histogram.
output_histogram(h_histogram, num_buckets);
// Output the total running time.
printf("******** Total Running Time of Kernel = %.5f sec *******\n", time/1000.0);
/*
printf("\n----Difference between histograms:\n");
// Print the difference between the histograms.
for (i = 0; i < num_buckets; i++)
{
difference_histogram[i].d_cnt = abs(histogram[i].d_cnt - h_histogram[i].d_cnt);
}
// Print out the histograms' difference.
output_histogram(difference_histogram, num_buckets);
*/
// Free memory.
hipFree(d_x);
hipFree(d_y);
hipFree(d_z);
hipFree(d_histogram);
free(histogram);
free(h_histogram);
free(atom_list);
free(x);
free(y);
free(z);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | /* =======================================================
Student: Patricia Wilthew
The basic SDH algorithm implementation for 3D data
To compile: nvcc SDH.c -o SDH
=======================================================
*/
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <sys/time.h>
#define BOX_SIZE 23000
/*
Structure: atom.
Descriptors for single atom in the tree.
*/
typedef struct atomdesc
{
double x_pos;
double y_pos;
double z_pos;
} atom;
/*
Structure: bucket.
Size of the buckets.
*/
typedef struct hist_entry
{
long long d_cnt;
} bucket;
hipError_t err;
long long PDH_acnt;
double PDH_res;
int num_buckets, PDH_threads;
bucket *histogram;
atom *atom_list;
struct timezone Idunno;
struct timeval startTime, endTime;
/*
Method: distance.
Distance of two points (x1, y1, z1) and (x2, y2, z2).
*/
__device__
double distance(double x1, double y1, double z1, double x2, double y2, double z2)
{
return sqrt((x1 - x2)*(x1-x2) + (y1 - y2)*(y1 - y2) + (z1 - z2)*(z1 - z2));
}
/*
Method: PDH_on_gpu.
SDH solution in GPU threads.
*/
__global__
void PDH_on_gpu(double *x, double *y, double *z, bucket *hist,
int PDH_acnt, double PDH_res, int num_buckets)
{
extern __shared__ unsigned int SHMOut[];
int t_id, b_id, t, s;
int i, h_pos;
double x1, y1, z1, x2, y2, z2, d;
t_id = threadIdx.x;
b_id = blockIdx.x;
t = b_id*blockDim.x + t_id;
// Initialize Shared Memory to Zero.
for (s = 0; s < (num_buckets + blockDim.x - 1)/blockDim.x; s++)
{
if (t_id + s*blockDim.x < num_buckets)
{
SHMOut[t_id + s*blockDim.x] = 0;
}
}
// The t-th datum of b-th input data block.
i = t + 1;
x1 = x[t];
y1 = y[t];
z1 = z[t];
for (i=t+1; i < PDH_acnt; i++)
{
x2 = x[i];
y2 = y[i];
z2 = z[i];
d = distance(x1, y1, z1, x2, y2, z2);
h_pos = (int) (d / PDH_res);
atomicAdd(&SHMOut[h_pos], 1);
}
__syncthreads();
// Write results to Global Memory.
for (s = 0; s < (num_buckets + blockDim.x - 1)/blockDim.x; s++)
{
if (t_id + s*blockDim.x < num_buckets)
{
atomicAdd((unsigned int *)&hist[t_id + s*blockDim.x].d_cnt,
SHMOut[t_id + s*blockDim.x]);
}
}
}
/*
Method: p2p_distance.
Distance of two points in the atom_list.
*/
double p2p_distance(atom *atom_list, int ind1, int ind2)
{
double x1 = atom_list[ind1].x_pos;
double x2 = atom_list[ind2].x_pos;
double y1 = atom_list[ind1].y_pos;
double y2 = atom_list[ind2].y_pos;
double z1 = atom_list[ind1].z_pos;
double z2 = atom_list[ind2].z_pos;
return sqrt((x1 - x2)*(x1-x2) + (y1 - y2)*(y1 - y2) + (z1 - z2)*(z1 - z2));
}
/*
Method: PDH_baseline.
Brute-force SDH solution in a single CPU thread.
*/
int PDH_baseline(atom *atom_list, bucket *histogram, long long PDH_acnt, double PDH_res)
{
int i, j, h_pos;
double dist;
for (i = 0; i < PDH_acnt; i++)
{
for (j = i+1; j < PDH_acnt; j++)
{
dist = p2p_distance(atom_list, i,j);
h_pos = (int) (dist / PDH_res);
histogram[h_pos].d_cnt++;
}
}
return 0;
}
/*
Method: report_running_time.
Set a checkpoint and show the (natural) running time in seconds.
*/
double report_running_time()
{
long sec_diff, usec_diff;
gettimeofday(&endTime, &Idunno);
sec_diff = endTime.tv_sec - startTime.tv_sec;
usec_diff= endTime.tv_usec-startTime.tv_usec;
if (usec_diff < 0)
{
sec_diff--;
usec_diff += 1000000;
}
printf("Running time: %ld.%06ld\n", sec_diff, usec_diff);
return (double)(sec_diff*1.0 + usec_diff/1000000.0);
}
/*
Method: output_histogram.
Print the counts in all buckets of the histogram.
*/
void output_histogram(bucket *histogram, int num_buckets)
{
int i;
long long total_cnt = 0;
for (i=0; i< num_buckets; i++)
{
if (i%5 == 0) // Print 5 buckets in a row.
printf("\n%02d: ", i);
printf("%15lld ", histogram[i].d_cnt);
total_cnt += histogram[i].d_cnt;
// Also want to make sure the total distance count is correct.
if (i == num_buckets - 1)
printf("\n T:%lld \n", total_cnt);
else printf("| ");
}
}
/*
Method: catch_error.
Prints any CUDA error to stdout.
*/
void catch_error(hipError_t error)
{
if (error)
{
printf("Error: %s\n", hipGetErrorString(err));
}
}
int main(int argc, char **argv)
{
if (argc <= 3)
{
printf("Usage: ./SDH {# Atoms} {# Buckets} {# Threads}\n");
exit(1);
}
if (atoi(argv[3]) < 32)
{
printf("Number of threads must be greater or equal to 32.\n");
exit(1);
}
PDH_acnt = atoi(argv[1]);
PDH_res = atof(argv[2]);
PDH_threads = atoi(argv[3]);
// Variables declaration;
float time = 0;
int i;
double *x, *y, *z, *d_x, *d_y, *d_z;
bucket *d_histogram, *h_histogram;
// bucket *difference_histogram;
// Variables initialization and mem allocation.
num_buckets = (int)(BOX_SIZE * 1.732 / PDH_res) + 1;
atom_list = (atom *)malloc(sizeof(atom) * PDH_acnt);
histogram = (bucket *)malloc(sizeof(bucket) * num_buckets);
x = (double *)malloc(sizeof(double)*PDH_acnt);
y = (double *)malloc(sizeof(double)*PDH_acnt);
z = (double *)malloc(sizeof(double)*PDH_acnt);
h_histogram = (bucket *)malloc(sizeof(bucket) * num_buckets);
// difference_histogram = (bucket *)malloc(sizeof(bucket) * num_buckets);
err = hipSuccess;
srand(1);
// Generate data following a uniform distribution.
for (i = 0; i < PDH_acnt; i++)
{
x[i] = atom_list[i].x_pos = ((double)(rand()) / RAND_MAX) * BOX_SIZE;
y[i] = atom_list[i].y_pos = ((double)(rand()) / RAND_MAX) * BOX_SIZE;
z[i] = atom_list[i].z_pos = ((double)(rand()) / RAND_MAX) * BOX_SIZE;
}
/*
printf("----CPU----");
// Start counting time.
gettimeofday(&startTime, &Idunno);
// Call CPU single thread version to compute the histogram.
PDH_baseline(atom_list, histogram, PDH_acnt, PDH_res);
// Check the total running time.
report_running_time();
// Print out the histogram.
output_histogram(histogram, num_buckets);
*/
/* My part of the project */
// Initialize h_histogram with zeroes.
for (i = 0; i < num_buckets; i++)
{
h_histogram[i].d_cnt = 0;
}
// Allocate memory in device for single dim arrays.
err = hipMalloc((void **)&d_x, PDH_acnt * sizeof(double)); catch_error(err);
err = hipMalloc((void **)&d_y, PDH_acnt * sizeof(double)); catch_error(err);
err = hipMalloc((void **)&d_z, PDH_acnt * sizeof(double)); catch_error(err);
// Allocate memory in device for histogram.
err = hipMalloc(&d_histogram, num_buckets * sizeof(bucket)); catch_error(err);
// Copy single dim arrays to device.
err = hipMemcpy(d_x, x, PDH_acnt * sizeof(double), hipMemcpyHostToDevice); catch_error(err);
err = hipMemcpy(d_y, y, PDH_acnt * sizeof(double), hipMemcpyHostToDevice); catch_error(err);
err = hipMemcpy(d_z, z, PDH_acnt * sizeof(double), hipMemcpyHostToDevice); catch_error(err);
// Copy zeroed histogram from host to device.
err = hipMemcpy(d_histogram, h_histogram, num_buckets * sizeof(bucket),
hipMemcpyHostToDevice); catch_error(err);
// Recording variables.
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
// Start to record.
hipEventRecord( start, 0);
// Call GPU version.
PDH_on_gpu<<<(PDH_acnt - 1 + PDH_threads)/PDH_threads,
PDH_threads,
num_buckets * sizeof(int)>>>(d_x, d_y, d_z,
d_histogram,
PDH_acnt,
PDH_res,
num_buckets);
// Stop recording.
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
hipEventElapsedTime(&time, start, stop);
hipEventDestroy(start);
hipEventDestroy(stop);
// Copy histogram from device to host.
err = hipMemcpy(h_histogram, d_histogram, num_buckets * sizeof(bucket),
hipMemcpyDeviceToHost); catch_error(err);
// Print out the histogram.
output_histogram(h_histogram, num_buckets);
// Output the total running time.
printf("******** Total Running Time of Kernel = %.5f sec *******\n", time/1000.0);
/*
printf("\n----Difference between histograms:\n");
// Print the difference between the histograms.
for (i = 0; i < num_buckets; i++)
{
difference_histogram[i].d_cnt = abs(histogram[i].d_cnt - h_histogram[i].d_cnt);
}
// Print out the histograms' difference.
output_histogram(difference_histogram, num_buckets);
*/
// Free memory.
hipFree(d_x);
hipFree(d_y);
hipFree(d_z);
hipFree(d_histogram);
free(histogram);
free(h_histogram);
free(atom_list);
free(x);
free(y);
free(z);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10PDH_on_gpuPdS_S_P10hist_entryidi
.globl _Z10PDH_on_gpuPdS_S_P10hist_entryidi
.p2align 8
.type _Z10PDH_on_gpuPdS_S_P10hist_entryidi,@function
_Z10PDH_on_gpuPdS_S_P10hist_entryidi:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x44
s_load_b32 s6, s[0:1], 0x30
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_add_i32 s2, s6, -1
v_cvt_f32_u32_e32 v1, s3
v_add_co_u32 v15, s2, s2, s3
s_sub_i32 s5, 0, s3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v1, v1
v_readfirstlane_b32 s7, v15
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v1, 0x4f7ffffe, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_u32_f32_e32 v1, v1
v_readfirstlane_b32 s4, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s5, s5, s4
s_mul_hi_u32 s5, s4, s5
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s4, s4, s5
s_mul_hi_u32 s4, s7, s4
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s5, s4, s3
s_sub_i32 s5, s7, s5
s_add_i32 s7, s4, 1
s_sub_i32 s8, s5, s3
s_cmp_ge_u32 s5, s3
s_cselect_b32 s4, s7, s4
s_cselect_b32 s5, s8, s5
s_add_i32 s7, s4, 1
s_cmp_ge_u32 s5, s3
s_cselect_b32 s7, s7, s4
s_and_b32 vcc_lo, exec_lo, s2
s_mov_b32 s2, 0
s_cbranch_vccnz .LBB0_5
v_lshl_add_u32 v1, v0, 2, 0
v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v3, v0
s_lshl_b32 s4, s3, 2
s_branch .LBB0_3
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s5
v_add_nc_u32_e32 v1, s4, v1
v_add_nc_u32_e32 v3, s3, v3
s_add_i32 s2, s2, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lt_u32 s2, s7
s_cbranch_scc0 .LBB0_5
.LBB0_3:
s_mov_b32 s5, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_u32_e64 s6, v3
s_cbranch_execz .LBB0_2
ds_store_b32 v1, v2
s_branch .LBB0_2
.LBB0_5:
s_load_b32 s8, s[0:1], 0x20
v_mad_u64_u32 v[2:3], null, s15, s3, v[0:1]
s_mov_b32 s9, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v1, 1, v2
s_waitcnt lgkmcnt(0)
v_cmpx_gt_i32_e64 s8, v1
s_cbranch_execz .LBB0_8
s_clause 0x1
s_load_b128 s[12:15], s[0:1], 0x0
s_load_b64 s[10:11], s[0:1], 0x10
v_ashrrev_i32_e32 v3, 31, v2
s_load_b64 s[4:5], s[0:1], 0x28
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 3, v[2:3]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v4, vcc_lo, s12, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v5, vcc_lo, s13, v3, vcc_lo
v_add_co_u32 v6, vcc_lo, s14, v2
v_add_co_ci_u32_e32 v7, vcc_lo, s15, v3, vcc_lo
v_add_co_u32 v8, vcc_lo, s10, v2
v_add_co_ci_u32_e32 v9, vcc_lo, s11, v3, vcc_lo
global_load_b64 v[3:4], v[4:5], off
global_load_b64 v[5:6], v[6:7], off
global_load_b64 v[7:8], v[8:9], off
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[13:14], 3, v[1:2]
v_mov_b32_e32 v2, 1
v_add_co_u32 v9, vcc_lo, s12, v13
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v10, vcc_lo, s13, v14, vcc_lo
v_add_co_u32 v11, vcc_lo, s14, v13
v_add_co_ci_u32_e32 v12, vcc_lo, s15, v14, vcc_lo
v_add_co_u32 v13, vcc_lo, s10, v13
v_add_co_ci_u32_e32 v14, vcc_lo, s11, v14, vcc_lo
s_mov_b32 s10, 0
.LBB0_7:
global_load_b64 v[16:17], v[11:12], off
global_load_b64 v[18:19], v[9:10], off
global_load_b64 v[20:21], v[13:14], off
v_add_co_u32 v13, s2, v13, 8
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v14, s2, 0, v14, s2
v_add_nc_u32_e32 v1, 1, v1
s_waitcnt vmcnt(2)
v_add_f64 v[16:17], v[5:6], -v[16:17]
s_waitcnt vmcnt(1)
v_add_f64 v[18:19], v[3:4], -v[18:19]
s_waitcnt vmcnt(0)
v_add_f64 v[20:21], v[7:8], -v[20:21]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[16:17], v[16:17], v[16:17]
v_fma_f64 v[16:17], v[18:19], v[18:19], v[16:17]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[16:17], v[20:21], v[20:21], v[16:17]
v_cmp_gt_f64_e32 vcc_lo, 0x10000000, v[16:17]
v_cndmask_b32_e64 v18, 0, 1, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b32_e32 v18, 8, v18
v_ldexp_f64 v[16:17], v[16:17], v18
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_rsq_f64_e32 v[18:19], v[16:17]
s_waitcnt_depctr 0xfff
v_mul_f64 v[20:21], v[16:17], v[18:19]
v_mul_f64 v[18:19], v[18:19], 0.5
v_fma_f64 v[22:23], -v[18:19], v[20:21], 0.5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_fma_f64 v[20:21], v[20:21], v[22:23], v[20:21]
v_fma_f64 v[18:19], v[18:19], v[22:23], v[18:19]
v_fma_f64 v[22:23], -v[20:21], v[20:21], v[16:17]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[20:21], v[22:23], v[18:19], v[20:21]
v_fma_f64 v[22:23], -v[20:21], v[20:21], v[16:17]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_fma_f64 v[18:19], v[22:23], v[18:19], v[20:21]
v_cndmask_b32_e64 v20, 0, 0xffffff80, vcc_lo
v_cmp_class_f64_e64 vcc_lo, v[16:17], 0x260
v_ldexp_f64 v[18:19], v[18:19], v20
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_cndmask_b32 v17, v19, v17 :: v_dual_cndmask_b32 v16, v18, v16
v_div_scale_f64 v[18:19], null, s[4:5], s[4:5], v[16:17]
v_div_scale_f64 v[24:25], vcc_lo, v[16:17], s[4:5], v[16:17]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f64_e32 v[20:21], v[18:19]
s_waitcnt_depctr 0xfff
v_fma_f64 v[22:23], -v[18:19], v[20:21], 1.0
v_fma_f64 v[20:21], v[20:21], v[22:23], v[20:21]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[22:23], -v[18:19], v[20:21], 1.0
v_fma_f64 v[20:21], v[20:21], v[22:23], v[20:21]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[22:23], v[24:25], v[20:21]
v_fma_f64 v[18:19], -v[18:19], v[22:23], v[24:25]
s_delay_alu instid0(VALU_DEP_1)
v_div_fmas_f64 v[18:19], v[18:19], v[20:21], v[22:23]
v_add_co_u32 v9, vcc_lo, v9, 8
v_add_co_ci_u32_e32 v10, vcc_lo, 0, v10, vcc_lo
v_add_co_u32 v11, vcc_lo, v11, 8
v_add_co_ci_u32_e32 v12, vcc_lo, 0, v12, vcc_lo
v_cmp_le_i32_e32 vcc_lo, s8, v1
s_or_b32 s10, vcc_lo, s10
v_div_fixup_f64 v[16:17], v[18:19], s[4:5], v[16:17]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_i32_f64_e32 v16, v[16:17]
v_lshl_add_u32 v16, v16, 2, 0
ds_add_u32 v16, v2
s_and_not1_b32 exec_lo, exec_lo, s10
s_cbranch_execnz .LBB0_7
.LBB0_8:
s_or_b32 exec_lo, exec_lo, s9
v_cmp_gt_u32_e32 vcc_lo, s3, v15
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_vccnz .LBB0_13
s_load_b64 s[0:1], s[0:1], 0x18
v_lshl_add_u32 v2, v0, 2, 0
v_mov_b32_e32 v1, 0
s_mov_b32 s2, 0
s_lshl_b32 s4, s3, 2
s_branch .LBB0_11
.p2align 6
.LBB0_10:
s_or_b32 exec_lo, exec_lo, s5
v_add_nc_u32_e32 v2, s4, v2
v_add_nc_u32_e32 v0, s3, v0
s_add_i32 s2, s2, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lt_u32 s2, s7
s_cbranch_scc0 .LBB0_13
.LBB0_11:
s_mov_b32 s5, exec_lo
v_cmpx_gt_u32_e64 s6, v0
s_cbranch_execz .LBB0_10
ds_load_b32 v5, v2
v_lshlrev_b64 v[3:4], 3, v[0:1]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v3, vcc_lo, s0, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
global_atomic_add_u32 v[3:4], v5, off
s_branch .LBB0_10
.LBB0_13:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10PDH_on_gpuPdS_S_P10hist_entryidi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 312
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 26
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10PDH_on_gpuPdS_S_P10hist_entryidi, .Lfunc_end0-_Z10PDH_on_gpuPdS_S_P10hist_entryidi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym SHMOut
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 40
.size: 8
.value_kind: by_value
- .offset: 48
.size: 4
.value_kind: by_value
- .offset: 56
.size: 4
.value_kind: hidden_block_count_x
- .offset: 60
.size: 4
.value_kind: hidden_block_count_y
- .offset: 64
.size: 4
.value_kind: hidden_block_count_z
- .offset: 68
.size: 2
.value_kind: hidden_group_size_x
- .offset: 70
.size: 2
.value_kind: hidden_group_size_y
- .offset: 72
.size: 2
.value_kind: hidden_group_size_z
- .offset: 74
.size: 2
.value_kind: hidden_remainder_x
- .offset: 76
.size: 2
.value_kind: hidden_remainder_y
- .offset: 78
.size: 2
.value_kind: hidden_remainder_z
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 112
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 120
.size: 2
.value_kind: hidden_grid_dims
- .offset: 176
.size: 4
.value_kind: hidden_dynamic_lds_size
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 312
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10PDH_on_gpuPdS_S_P10hist_entryidi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z10PDH_on_gpuPdS_S_P10hist_entryidi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 26
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | /* =======================================================
Student: Patricia Wilthew
The basic SDH algorithm implementation for 3D data
To compile: nvcc SDH.c -o SDH
=======================================================
*/
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <sys/time.h>
#define BOX_SIZE 23000
/*
Structure: atom.
Descriptors for single atom in the tree.
*/
typedef struct atomdesc
{
double x_pos;
double y_pos;
double z_pos;
} atom;
/*
Structure: bucket.
Size of the buckets.
*/
typedef struct hist_entry
{
long long d_cnt;
} bucket;
hipError_t err;
long long PDH_acnt;
double PDH_res;
int num_buckets, PDH_threads;
bucket *histogram;
atom *atom_list;
struct timezone Idunno;
struct timeval startTime, endTime;
/*
Method: distance.
Distance of two points (x1, y1, z1) and (x2, y2, z2).
*/
__device__
double distance(double x1, double y1, double z1, double x2, double y2, double z2)
{
return sqrt((x1 - x2)*(x1-x2) + (y1 - y2)*(y1 - y2) + (z1 - z2)*(z1 - z2));
}
/*
Method: PDH_on_gpu.
SDH solution in GPU threads.
*/
__global__
void PDH_on_gpu(double *x, double *y, double *z, bucket *hist,
int PDH_acnt, double PDH_res, int num_buckets)
{
extern __shared__ unsigned int SHMOut[];
int t_id, b_id, t, s;
int i, h_pos;
double x1, y1, z1, x2, y2, z2, d;
t_id = threadIdx.x;
b_id = blockIdx.x;
t = b_id*blockDim.x + t_id;
// Initialize Shared Memory to Zero.
for (s = 0; s < (num_buckets + blockDim.x - 1)/blockDim.x; s++)
{
if (t_id + s*blockDim.x < num_buckets)
{
SHMOut[t_id + s*blockDim.x] = 0;
}
}
// The t-th datum of b-th input data block.
i = t + 1;
x1 = x[t];
y1 = y[t];
z1 = z[t];
for (i=t+1; i < PDH_acnt; i++)
{
x2 = x[i];
y2 = y[i];
z2 = z[i];
d = distance(x1, y1, z1, x2, y2, z2);
h_pos = (int) (d / PDH_res);
atomicAdd(&SHMOut[h_pos], 1);
}
__syncthreads();
// Write results to Global Memory.
for (s = 0; s < (num_buckets + blockDim.x - 1)/blockDim.x; s++)
{
if (t_id + s*blockDim.x < num_buckets)
{
atomicAdd((unsigned int *)&hist[t_id + s*blockDim.x].d_cnt,
SHMOut[t_id + s*blockDim.x]);
}
}
}
/*
Method: p2p_distance.
Distance of two points in the atom_list.
*/
double p2p_distance(atom *atom_list, int ind1, int ind2)
{
double x1 = atom_list[ind1].x_pos;
double x2 = atom_list[ind2].x_pos;
double y1 = atom_list[ind1].y_pos;
double y2 = atom_list[ind2].y_pos;
double z1 = atom_list[ind1].z_pos;
double z2 = atom_list[ind2].z_pos;
return sqrt((x1 - x2)*(x1-x2) + (y1 - y2)*(y1 - y2) + (z1 - z2)*(z1 - z2));
}
/*
Method: PDH_baseline.
Brute-force SDH solution in a single CPU thread.
*/
int PDH_baseline(atom *atom_list, bucket *histogram, long long PDH_acnt, double PDH_res)
{
int i, j, h_pos;
double dist;
for (i = 0; i < PDH_acnt; i++)
{
for (j = i+1; j < PDH_acnt; j++)
{
dist = p2p_distance(atom_list, i,j);
h_pos = (int) (dist / PDH_res);
histogram[h_pos].d_cnt++;
}
}
return 0;
}
/*
Method: report_running_time.
Set a checkpoint and show the (natural) running time in seconds.
*/
double report_running_time()
{
long sec_diff, usec_diff;
gettimeofday(&endTime, &Idunno);
sec_diff = endTime.tv_sec - startTime.tv_sec;
usec_diff= endTime.tv_usec-startTime.tv_usec;
if (usec_diff < 0)
{
sec_diff--;
usec_diff += 1000000;
}
printf("Running time: %ld.%06ld\n", sec_diff, usec_diff);
return (double)(sec_diff*1.0 + usec_diff/1000000.0);
}
/*
Method: output_histogram.
Print the counts in all buckets of the histogram.
*/
void output_histogram(bucket *histogram, int num_buckets)
{
int i;
long long total_cnt = 0;
for (i=0; i< num_buckets; i++)
{
if (i%5 == 0) // Print 5 buckets in a row.
printf("\n%02d: ", i);
printf("%15lld ", histogram[i].d_cnt);
total_cnt += histogram[i].d_cnt;
// Also want to make sure the total distance count is correct.
if (i == num_buckets - 1)
printf("\n T:%lld \n", total_cnt);
else printf("| ");
}
}
/*
Method: catch_error.
Prints any CUDA error to stdout.
*/
void catch_error(hipError_t error)
{
if (error)
{
printf("Error: %s\n", hipGetErrorString(err));
}
}
int main(int argc, char **argv)
{
if (argc <= 3)
{
printf("Usage: ./SDH {# Atoms} {# Buckets} {# Threads}\n");
exit(1);
}
if (atoi(argv[3]) < 32)
{
printf("Number of threads must be greater or equal to 32.\n");
exit(1);
}
PDH_acnt = atoi(argv[1]);
PDH_res = atof(argv[2]);
PDH_threads = atoi(argv[3]);
// Variables declaration;
float time = 0;
int i;
double *x, *y, *z, *d_x, *d_y, *d_z;
bucket *d_histogram, *h_histogram;
// bucket *difference_histogram;
// Variables initialization and mem allocation.
num_buckets = (int)(BOX_SIZE * 1.732 / PDH_res) + 1;
atom_list = (atom *)malloc(sizeof(atom) * PDH_acnt);
histogram = (bucket *)malloc(sizeof(bucket) * num_buckets);
x = (double *)malloc(sizeof(double)*PDH_acnt);
y = (double *)malloc(sizeof(double)*PDH_acnt);
z = (double *)malloc(sizeof(double)*PDH_acnt);
h_histogram = (bucket *)malloc(sizeof(bucket) * num_buckets);
// difference_histogram = (bucket *)malloc(sizeof(bucket) * num_buckets);
err = hipSuccess;
srand(1);
// Generate data following a uniform distribution.
for (i = 0; i < PDH_acnt; i++)
{
x[i] = atom_list[i].x_pos = ((double)(rand()) / RAND_MAX) * BOX_SIZE;
y[i] = atom_list[i].y_pos = ((double)(rand()) / RAND_MAX) * BOX_SIZE;
z[i] = atom_list[i].z_pos = ((double)(rand()) / RAND_MAX) * BOX_SIZE;
}
/*
printf("----CPU----");
// Start counting time.
gettimeofday(&startTime, &Idunno);
// Call CPU single thread version to compute the histogram.
PDH_baseline(atom_list, histogram, PDH_acnt, PDH_res);
// Check the total running time.
report_running_time();
// Print out the histogram.
output_histogram(histogram, num_buckets);
*/
/* My part of the project */
// Initialize h_histogram with zeroes.
for (i = 0; i < num_buckets; i++)
{
h_histogram[i].d_cnt = 0;
}
// Allocate memory in device for single dim arrays.
err = hipMalloc((void **)&d_x, PDH_acnt * sizeof(double)); catch_error(err);
err = hipMalloc((void **)&d_y, PDH_acnt * sizeof(double)); catch_error(err);
err = hipMalloc((void **)&d_z, PDH_acnt * sizeof(double)); catch_error(err);
// Allocate memory in device for histogram.
err = hipMalloc(&d_histogram, num_buckets * sizeof(bucket)); catch_error(err);
// Copy single dim arrays to device.
err = hipMemcpy(d_x, x, PDH_acnt * sizeof(double), hipMemcpyHostToDevice); catch_error(err);
err = hipMemcpy(d_y, y, PDH_acnt * sizeof(double), hipMemcpyHostToDevice); catch_error(err);
err = hipMemcpy(d_z, z, PDH_acnt * sizeof(double), hipMemcpyHostToDevice); catch_error(err);
// Copy zeroed histogram from host to device.
err = hipMemcpy(d_histogram, h_histogram, num_buckets * sizeof(bucket),
hipMemcpyHostToDevice); catch_error(err);
// Recording variables.
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
// Start to record.
hipEventRecord( start, 0);
// Call GPU version.
PDH_on_gpu<<<(PDH_acnt - 1 + PDH_threads)/PDH_threads,
PDH_threads,
num_buckets * sizeof(int)>>>(d_x, d_y, d_z,
d_histogram,
PDH_acnt,
PDH_res,
num_buckets);
// Stop recording.
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
hipEventElapsedTime(&time, start, stop);
hipEventDestroy(start);
hipEventDestroy(stop);
// Copy histogram from device to host.
err = hipMemcpy(h_histogram, d_histogram, num_buckets * sizeof(bucket),
hipMemcpyDeviceToHost); catch_error(err);
// Print out the histogram.
output_histogram(h_histogram, num_buckets);
// Output the total running time.
printf("******** Total Running Time of Kernel = %.5f sec *******\n", time/1000.0);
/*
printf("\n----Difference between histograms:\n");
// Print the difference between the histograms.
for (i = 0; i < num_buckets; i++)
{
difference_histogram[i].d_cnt = abs(histogram[i].d_cnt - h_histogram[i].d_cnt);
}
// Print out the histograms' difference.
output_histogram(difference_histogram, num_buckets);
*/
// Free memory.
hipFree(d_x);
hipFree(d_y);
hipFree(d_z);
hipFree(d_histogram);
free(histogram);
free(h_histogram);
free(atom_list);
free(x);
free(y);
free(z);
return 0;
} | .text
.file "SDH.hip"
.globl _Z25__device_stub__PDH_on_gpuPdS_S_P10hist_entryidi # -- Begin function _Z25__device_stub__PDH_on_gpuPdS_S_P10hist_entryidi
.p2align 4, 0x90
.type _Z25__device_stub__PDH_on_gpuPdS_S_P10hist_entryidi,@function
_Z25__device_stub__PDH_on_gpuPdS_S_P10hist_entryidi: # @_Z25__device_stub__PDH_on_gpuPdS_S_P10hist_entryidi
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movl %r8d, 4(%rsp)
movsd %xmm0, 56(%rsp)
movl %r9d, (%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
leaq 56(%rsp), %rax
movq %rax, 136(%rsp)
movq %rsp, %rax
movq %rax, 144(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z10PDH_on_gpuPdS_S_P10hist_entryidi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z25__device_stub__PDH_on_gpuPdS_S_P10hist_entryidi, .Lfunc_end0-_Z25__device_stub__PDH_on_gpuPdS_S_P10hist_entryidi
.cfi_endproc
# -- End function
.globl _Z12p2p_distanceP8atomdescii # -- Begin function _Z12p2p_distanceP8atomdescii
.p2align 4, 0x90
.type _Z12p2p_distanceP8atomdescii,@function
_Z12p2p_distanceP8atomdescii: # @_Z12p2p_distanceP8atomdescii
.cfi_startproc
# %bb.0:
movslq %esi, %rax
leaq (%rax,%rax,2), %rax
movslq %edx, %rcx
leaq (%rcx,%rcx,2), %rcx
movsd (%rdi,%rax,8), %xmm1 # xmm1 = mem[0],zero
movsd 8(%rdi,%rax,8), %xmm2 # xmm2 = mem[0],zero
movsd 16(%rdi,%rax,8), %xmm0 # xmm0 = mem[0],zero
subsd (%rdi,%rcx,8), %xmm1
mulsd %xmm1, %xmm1
subsd 8(%rdi,%rcx,8), %xmm2
mulsd %xmm2, %xmm2
addsd %xmm1, %xmm2
subsd 16(%rdi,%rcx,8), %xmm0
mulsd %xmm0, %xmm0
addsd %xmm2, %xmm0
xorpd %xmm1, %xmm1
ucomisd %xmm1, %xmm0
jb sqrt # TAILCALL
# %bb.1: # %.split
sqrtsd %xmm0, %xmm0
retq
.Lfunc_end1:
.size _Z12p2p_distanceP8atomdescii, .Lfunc_end1-_Z12p2p_distanceP8atomdescii
.cfi_endproc
# -- End function
.globl _Z12PDH_baselineP8atomdescP10hist_entryxd # -- Begin function _Z12PDH_baselineP8atomdescP10hist_entryxd
.p2align 4, 0x90
.type _Z12PDH_baselineP8atomdescP10hist_entryxd,@function
_Z12PDH_baselineP8atomdescP10hist_entryxd: # @_Z12PDH_baselineP8atomdescP10hist_entryxd
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $40, %rsp
.cfi_def_cfa_offset 96
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rdi, 8(%rsp) # 8-byte Spill
testq %rdx, %rdx
jle .LBB2_9
# %bb.1: # %.lr.ph17.preheader
movapd %xmm0, %xmm3
movq %rdx, %rbx
movq %rsi, %r14
movq 8(%rsp), %rax # 8-byte Reload
addq $40, %rax
movq %rax, 16(%rsp) # 8-byte Spill
movl $1, %ebp
xorl %eax, %eax
xorpd %xmm4, %xmm4
movsd %xmm0, 32(%rsp) # 8-byte Spill
jmp .LBB2_3
.p2align 4, 0x90
.LBB2_2: # %.loopexit
# in Loop: Header=BB2_3 Depth=1
incq %rbp
addq $24, 16(%rsp) # 8-byte Folded Spill
movq 24(%rsp), %rax # 8-byte Reload
cmpq %rbx, %rax
je .LBB2_9
.LBB2_3: # %.lr.ph17
# =>This Loop Header: Depth=1
# Child Loop BB2_5 Depth 2
leaq 1(%rax), %rcx
movq %rcx, 24(%rsp) # 8-byte Spill
cmpq %rbx, %rcx
jge .LBB2_2
# %bb.4: # %.lr.ph
# in Loop: Header=BB2_3 Depth=1
leaq (%rax,%rax,2), %rax
movq 8(%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax,8), %r15
movq 16(%rsp), %r12 # 8-byte Reload
movq %rbp, %r13
jmp .LBB2_5
.p2align 4, 0x90
.LBB2_7: # %call.sqrt
# in Loop: Header=BB2_5 Depth=2
callq sqrt
xorpd %xmm4, %xmm4
movsd 32(%rsp), %xmm3 # 8-byte Reload
# xmm3 = mem[0],zero
.LBB2_8: # %.split
# in Loop: Header=BB2_5 Depth=2
divsd %xmm3, %xmm0
cvttsd2si %xmm0, %eax
cltq
incq (%r14,%rax,8)
incq %r13
addq $24, %r12
cmpq %rbx, %r13
jge .LBB2_2
.LBB2_5: # Parent Loop BB2_3 Depth=1
# => This Inner Loop Header: Depth=2
movsd (%r15), %xmm1 # xmm1 = mem[0],zero
movsd 8(%r15), %xmm2 # xmm2 = mem[0],zero
subsd -16(%r12), %xmm1
movsd 16(%r15), %xmm0 # xmm0 = mem[0],zero
mulsd %xmm1, %xmm1
subsd -8(%r12), %xmm2
mulsd %xmm2, %xmm2
addsd %xmm1, %xmm2
subsd (%r12), %xmm0
mulsd %xmm0, %xmm0
addsd %xmm2, %xmm0
ucomisd %xmm4, %xmm0
jb .LBB2_7
# %bb.6: # in Loop: Header=BB2_5 Depth=2
sqrtsd %xmm0, %xmm0
jmp .LBB2_8
.LBB2_9: # %._crit_edge
xorl %eax, %eax
addq $40, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z12PDH_baselineP8atomdescP10hist_entryxd, .Lfunc_end2-_Z12PDH_baselineP8atomdescP10hist_entryxd
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z19report_running_timev
.LCPI3_0:
.quad 0x412e848000000000 # double 1.0E+6
.text
.globl _Z19report_running_timev
.p2align 4, 0x90
.type _Z19report_running_timev,@function
_Z19report_running_timev: # @_Z19report_running_timev
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movl $endTime, %edi
movl $Idunno, %esi
callq gettimeofday
movq endTime(%rip), %rax
subq startTime(%rip), %rax
movq endTime+8(%rip), %rcx
subq startTime+8(%rip), %rcx
leaq 1000000(%rcx), %rbx
movq %rcx, %r14
sarq $63, %r14
addq %rax, %r14
testq %rcx, %rcx
cmovnsq %rcx, %rbx
movl $.L.str, %edi
movq %r14, %rsi
movq %rbx, %rdx
xorl %eax, %eax
callq printf
cvtsi2sd %r14, %xmm1
cvtsi2sd %rbx, %xmm0
divsd .LCPI3_0(%rip), %xmm0
addsd %xmm1, %xmm0
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size _Z19report_running_timev, .Lfunc_end3-_Z19report_running_timev
.cfi_endproc
# -- End function
.globl _Z16output_histogramP10hist_entryi # -- Begin function _Z16output_histogramP10hist_entryi
.p2align 4, 0x90
.type _Z16output_histogramP10hist_entryi,@function
_Z16output_histogramP10hist_entryi: # @_Z16output_histogramP10hist_entryi
.cfi_startproc
# %bb.0:
# kill: def $esi killed $esi def $rsi
testl %esi, %esi
jle .LBB4_9
# %bb.1: # %.lr.ph
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
pushq %rax
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rdi, %rbx
leal -1(%rsi), %r12d
movl %esi, %r13d
movl $3435973837, %ebp # imm = 0xCCCCCCCD
xorl %r14d, %r14d
xorl %r15d, %r15d
jmp .LBB4_2
.p2align 4, 0x90
.LBB4_5: # in Loop: Header=BB4_2 Depth=1
movl $.L.str.3, %edi
movq %r15, %rsi
xorl %eax, %eax
callq printf
.LBB4_7: # in Loop: Header=BB4_2 Depth=1
incq %r14
cmpq %r14, %r13
je .LBB4_8
.LBB4_2: # =>This Inner Loop Header: Depth=1
movl %r14d, %eax
imulq %rbp, %rax
shrq $34, %rax
leal (%rax,%rax,4), %eax
cmpl %eax, %r14d
jne .LBB4_4
# %bb.3: # in Loop: Header=BB4_2 Depth=1
movl $.L.str.1, %edi
movl %r14d, %esi
xorl %eax, %eax
callq printf
.LBB4_4: # in Loop: Header=BB4_2 Depth=1
movq (%rbx,%r14,8), %rsi
movl $.L.str.2, %edi
xorl %eax, %eax
callq printf
addq (%rbx,%r14,8), %r15
cmpq %r14, %r12
je .LBB4_5
# %bb.6: # in Loop: Header=BB4_2 Depth=1
movl $.L.str.4, %edi
xorl %eax, %eax
callq printf
jmp .LBB4_7
.LBB4_8:
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r12
.cfi_restore %r13
.cfi_restore %r14
.cfi_restore %r15
.cfi_restore %rbp
.LBB4_9: # %._crit_edge
retq
.Lfunc_end4:
.size _Z16output_histogramP10hist_entryi, .Lfunc_end4-_Z16output_histogramP10hist_entryi
.cfi_endproc
# -- End function
.globl _Z11catch_error10hipError_t # -- Begin function _Z11catch_error10hipError_t
.p2align 4, 0x90
.type _Z11catch_error10hipError_t,@function
_Z11catch_error10hipError_t: # @_Z11catch_error10hipError_t
.cfi_startproc
# %bb.0:
testl %edi, %edi
je .LBB5_1
# %bb.2:
pushq %rax
.cfi_def_cfa_offset 16
movl err(%rip), %edi
callq hipGetErrorString
movl $.L.str.5, %edi
movq %rax, %rsi
xorl %eax, %eax
popq %rcx
.cfi_def_cfa_offset 8
jmp printf # TAILCALL
.LBB5_1:
retq
.Lfunc_end5:
.size _Z11catch_error10hipError_t, .Lfunc_end5-_Z11catch_error10hipError_t
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI6_0:
.quad 0x40e3738000000000 # double 39836
.LCPI6_1:
.quad 0x41dfffffffc00000 # double 2147483647
.LCPI6_2:
.quad 0x40d6760000000000 # double 23000
.LCPI6_3:
.quad 0x408f400000000000 # double 1000
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $248, %rsp
.cfi_def_cfa_offset 304
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
cmpl $3, %edi
jle .LBB6_1
# %bb.3:
movq %rsi, %rbx
movq 24(%rsi), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
cmpl $31, %eax
jle .LBB6_4
# %bb.5:
movq 8(%rbx), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
cltq
movq %rax, PDH_acnt(%rip)
movq 16(%rbx), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, PDH_res(%rip)
movq 24(%rbx), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movl %eax, PDH_threads(%rip)
movsd .LCPI6_0(%rip), %xmm0 # xmm0 = mem[0],zero
divsd PDH_res(%rip), %xmm0
movl $0, 12(%rsp)
cvttsd2si %xmm0, %ebx
leal 1(%rbx), %eax
movl %eax, num_buckets(%rip)
movq PDH_acnt(%rip), %r15
shlq $3, %r15
leaq (%r15,%r15,2), %rdi
callq malloc
movq %rax, atom_list(%rip)
movslq %ebx, %rax
leaq 8(,%rax,8), %rbx
movq %rbx, %rdi
callq malloc
movq %rax, histogram(%rip)
movq %r15, %rdi
callq malloc
movq %rax, %r12
movq %r15, %rdi
callq malloc
movq %r15, %rdi
movq %rax, %r15
callq malloc
movq %rax, %rbp
movq %rbx, %rdi
callq malloc
movq %rax, 80(%rsp) # 8-byte Spill
movl $0, err(%rip)
movl $1, %edi
callq srand
movq PDH_acnt(%rip), %r13
testq %r13, %r13
jle .LBB6_8
# %bb.6: # %.lr.ph.preheader
xorl %ebx, %ebx
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB6_7: # %.lr.ph
# =>This Inner Loop Header: Depth=1
callq rand
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
movsd .LCPI6_1(%rip), %xmm1 # xmm1 = mem[0],zero
divsd %xmm1, %xmm0
movsd .LCPI6_2(%rip), %xmm1 # xmm1 = mem[0],zero
mulsd %xmm1, %xmm0
movq atom_list(%rip), %rax
movsd %xmm0, (%rax,%rbx)
movsd %xmm0, (%r12,%r14,8)
callq rand
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
divsd .LCPI6_1(%rip), %xmm0
mulsd .LCPI6_2(%rip), %xmm0
movq atom_list(%rip), %rax
movsd %xmm0, 8(%rax,%rbx)
movsd %xmm0, (%r15,%r14,8)
callq rand
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
divsd .LCPI6_1(%rip), %xmm0
mulsd .LCPI6_2(%rip), %xmm0
movq atom_list(%rip), %rax
movsd %xmm0, 16(%rax,%rbx)
movsd %xmm0, (%rbp,%r14,8)
incq %r14
movq PDH_acnt(%rip), %r13
addq $24, %rbx
cmpq %r14, %r13
jg .LBB6_7
.LBB6_8: # %.preheader
movq %r12, %r14
movq %rbp, 72(%rsp) # 8-byte Spill
movl num_buckets(%rip), %edx
testl %edx, %edx
movq 80(%rsp), %r12 # 8-byte Reload
jle .LBB6_10
# %bb.9: # %.lr.ph54.preheader
shlq $3, %rdx
movq %r12, %rdi
xorl %esi, %esi
callq memset@PLT
.LBB6_10: # %._crit_edge
shlq $3, %r13
leaq 56(%rsp), %rdi
movq %r13, %rsi
callq hipMalloc
movl %eax, err(%rip)
testl %eax, %eax
movq 72(%rsp), %rbx # 8-byte Reload
je .LBB6_12
# %bb.11:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.5, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
.LBB6_12: # %_Z11catch_error10hipError_t.exit
movq PDH_acnt(%rip), %rsi
shlq $3, %rsi
leaq 48(%rsp), %rdi
callq hipMalloc
movl %eax, err(%rip)
testl %eax, %eax
je .LBB6_14
# %bb.13:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.5, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
.LBB6_14: # %_Z11catch_error10hipError_t.exit34
movq PDH_acnt(%rip), %rsi
shlq $3, %rsi
leaq 40(%rsp), %rdi
callq hipMalloc
movl %eax, err(%rip)
testl %eax, %eax
je .LBB6_16
# %bb.15:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.5, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
.LBB6_16: # %_Z11catch_error10hipError_t.exit36
movslq num_buckets(%rip), %rsi
shlq $3, %rsi
leaq 24(%rsp), %rdi
callq hipMalloc
movl %eax, err(%rip)
testl %eax, %eax
je .LBB6_18
# %bb.17:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.5, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
.LBB6_18: # %_Z11catch_error10hipError_t.exit38
movq 56(%rsp), %rdi
movq PDH_acnt(%rip), %rdx
shlq $3, %rdx
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movl %eax, err(%rip)
testl %eax, %eax
je .LBB6_20
# %bb.19:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.5, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
.LBB6_20: # %_Z11catch_error10hipError_t.exit40
movq 48(%rsp), %rdi
movq PDH_acnt(%rip), %rdx
shlq $3, %rdx
movq %r15, %rsi
movl $1, %ecx
callq hipMemcpy
movl %eax, err(%rip)
testl %eax, %eax
je .LBB6_22
# %bb.21:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.5, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
.LBB6_22: # %_Z11catch_error10hipError_t.exit42
movq 40(%rsp), %rdi
movq PDH_acnt(%rip), %rdx
shlq $3, %rdx
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movl %eax, err(%rip)
testl %eax, %eax
je .LBB6_24
# %bb.23:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.5, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
.LBB6_24: # %_Z11catch_error10hipError_t.exit44
movq 24(%rsp), %rdi
movslq num_buckets(%rip), %rdx
shlq $3, %rdx
movq %r12, %rsi
movl $1, %ecx
callq hipMemcpy
movl %eax, err(%rip)
testl %eax, %eax
je .LBB6_26
# %bb.25:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.5, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
.LBB6_26: # %_Z11catch_error10hipError_t.exit46
movq %r15, 88(%rsp) # 8-byte Spill
movq %r14, 96(%rsp) # 8-byte Spill
leaq 32(%rsp), %rdi
callq hipEventCreate
leaq 16(%rsp), %rdi
callq hipEventCreate
movq 32(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq PDH_acnt(%rip), %rax
movl PDH_threads(%rip), %ecx
movslq %ecx, %rsi
addq %rsi, %rax
decq %rax
cqto
idivq %rsi
movslq num_buckets(%rip), %r8
shlq $2, %r8
movl %eax, %edi
movabsq $4294967296, %rax # imm = 0x100000000
orq %rax, %rdi
orq %rax, %rcx
movl $1, %esi
movq %rcx, %rdx
movl $1, %ecx
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB6_28
# %bb.27:
movq 56(%rsp), %rax
movq 48(%rsp), %rcx
movq 40(%rsp), %rdx
movq 24(%rsp), %rsi
movl PDH_acnt(%rip), %edi
movsd PDH_res(%rip), %xmm0 # xmm0 = mem[0],zero
movl num_buckets(%rip), %r8d
movq %rax, 184(%rsp)
movq %rcx, 176(%rsp)
movq %rdx, 168(%rsp)
movq %rsi, 160(%rsp)
movl %edi, 68(%rsp)
movsd %xmm0, 152(%rsp)
movl %r8d, 64(%rsp)
leaq 184(%rsp), %rax
movq %rax, 192(%rsp)
leaq 176(%rsp), %rax
movq %rax, 200(%rsp)
leaq 168(%rsp), %rax
movq %rax, 208(%rsp)
leaq 160(%rsp), %rax
movq %rax, 216(%rsp)
leaq 68(%rsp), %rax
movq %rax, 224(%rsp)
leaq 152(%rsp), %rax
movq %rax, 232(%rsp)
leaq 64(%rsp), %rax
movq %rax, 240(%rsp)
leaq 136(%rsp), %rdi
leaq 120(%rsp), %rsi
leaq 112(%rsp), %rdx
leaq 104(%rsp), %rcx
callq __hipPopCallConfiguration
movq 136(%rsp), %rsi
movl 144(%rsp), %edx
movq 120(%rsp), %rcx
movl 128(%rsp), %r8d
leaq 192(%rsp), %r9
movl $_Z10PDH_on_gpuPdS_S_P10hist_entryidi, %edi
pushq 104(%rsp)
.cfi_adjust_cfa_offset 8
pushq 120(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB6_28:
movq 16(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 16(%rsp), %rdi
callq hipEventSynchronize
movq 32(%rsp), %rsi
movq 16(%rsp), %rdx
leaq 12(%rsp), %rdi
callq hipEventElapsedTime
movq 32(%rsp), %rdi
callq hipEventDestroy
movq 16(%rsp), %rdi
callq hipEventDestroy
movq 24(%rsp), %rsi
movslq num_buckets(%rip), %rdx
shlq $3, %rdx
movq %r12, %rdi
movl $2, %ecx
callq hipMemcpy
movl %eax, err(%rip)
testl %eax, %eax
je .LBB6_30
# %bb.29:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.5, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
.LBB6_30: # %_Z11catch_error10hipError_t.exit48
movl num_buckets(%rip), %ebx
testl %ebx, %ebx
jle .LBB6_38
# %bb.31: # %.lr.ph.i
leal -1(%rbx), %r14d
movl $3435973837, %r15d # imm = 0xCCCCCCCD
xorl %r13d, %r13d
xorl %ebp, %ebp
jmp .LBB6_32
.p2align 4, 0x90
.LBB6_36: # in Loop: Header=BB6_32 Depth=1
movl $.L.str.4, %edi
xorl %eax, %eax
callq printf
.LBB6_37: # in Loop: Header=BB6_32 Depth=1
incq %r13
cmpq %r13, %rbx
je .LBB6_38
.LBB6_32: # =>This Inner Loop Header: Depth=1
movl %r13d, %eax
imulq %r15, %rax
shrq $34, %rax
leal (%rax,%rax,4), %eax
cmpl %eax, %r13d
jne .LBB6_34
# %bb.33: # in Loop: Header=BB6_32 Depth=1
movl $.L.str.1, %edi
movl %r13d, %esi
xorl %eax, %eax
callq printf
.LBB6_34: # in Loop: Header=BB6_32 Depth=1
movq (%r12,%r13,8), %rsi
movl $.L.str.2, %edi
xorl %eax, %eax
callq printf
addq (%r12,%r13,8), %rbp
cmpq %r13, %r14
jne .LBB6_36
# %bb.35: # in Loop: Header=BB6_32 Depth=1
movl $.L.str.3, %edi
movq %rbp, %rsi
xorl %eax, %eax
callq printf
jmp .LBB6_37
.LBB6_38: # %_Z16output_histogramP10hist_entryi.exit
movss 12(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
divsd .LCPI6_3(%rip), %xmm0
movl $.L.str.8, %edi
movb $1, %al
callq printf
movq 56(%rsp), %rdi
callq hipFree
movq 48(%rsp), %rdi
callq hipFree
movq 40(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
movq histogram(%rip), %rdi
callq free
movq %r12, %rdi
callq free
movq atom_list(%rip), %rdi
callq free
movq 96(%rsp), %rdi # 8-byte Reload
callq free
movq 88(%rsp), %rdi # 8-byte Reload
callq free
movq 72(%rsp), %rdi # 8-byte Reload
callq free
xorl %eax, %eax
addq $248, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB6_1:
.cfi_def_cfa_offset 304
movl $.Lstr.1, %edi
jmp .LBB6_2
.LBB6_4:
movl $.Lstr, %edi
.LBB6_2:
callq puts@PLT
movl $1, %edi
callq exit
.Lfunc_end6:
.size main, .Lfunc_end6-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB7_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB7_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10PDH_on_gpuPdS_S_P10hist_entryidi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end7:
.size __hip_module_ctor, .Lfunc_end7-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB8_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB8_2:
retq
.Lfunc_end8:
.size __hip_module_dtor, .Lfunc_end8-__hip_module_dtor
.cfi_endproc
# -- End function
.type err,@object # @err
.bss
.globl err
.p2align 2, 0x0
err:
.long 0 # 0x0
.size err, 4
.type PDH_acnt,@object # @PDH_acnt
.globl PDH_acnt
.p2align 3, 0x0
PDH_acnt:
.quad 0 # 0x0
.size PDH_acnt, 8
.type PDH_res,@object # @PDH_res
.globl PDH_res
.p2align 3, 0x0
PDH_res:
.quad 0x0000000000000000 # double 0
.size PDH_res, 8
.type num_buckets,@object # @num_buckets
.globl num_buckets
.p2align 2, 0x0
num_buckets:
.long 0 # 0x0
.size num_buckets, 4
.type PDH_threads,@object # @PDH_threads
.globl PDH_threads
.p2align 2, 0x0
PDH_threads:
.long 0 # 0x0
.size PDH_threads, 4
.type histogram,@object # @histogram
.globl histogram
.p2align 3, 0x0
histogram:
.quad 0
.size histogram, 8
.type atom_list,@object # @atom_list
.globl atom_list
.p2align 3, 0x0
atom_list:
.quad 0
.size atom_list, 8
.type Idunno,@object # @Idunno
.globl Idunno
.p2align 2, 0x0
Idunno:
.zero 8
.size Idunno, 8
.type startTime,@object # @startTime
.globl startTime
.p2align 3, 0x0
startTime:
.zero 16
.size startTime, 16
.type endTime,@object # @endTime
.globl endTime
.p2align 3, 0x0
endTime:
.zero 16
.size endTime, 16
.type _Z10PDH_on_gpuPdS_S_P10hist_entryidi,@object # @_Z10PDH_on_gpuPdS_S_P10hist_entryidi
.section .rodata,"a",@progbits
.globl _Z10PDH_on_gpuPdS_S_P10hist_entryidi
.p2align 3, 0x0
_Z10PDH_on_gpuPdS_S_P10hist_entryidi:
.quad _Z25__device_stub__PDH_on_gpuPdS_S_P10hist_entryidi
.size _Z10PDH_on_gpuPdS_S_P10hist_entryidi, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Running time: %ld.%06ld\n"
.size .L.str, 25
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "\n%02d: "
.size .L.str.1, 8
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "%15lld "
.size .L.str.2, 8
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "\n T:%lld \n"
.size .L.str.3, 11
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "| "
.size .L.str.4, 3
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Error: %s\n"
.size .L.str.5, 11
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "******** Total Running Time of Kernel = %.5f sec *******\n"
.size .L.str.8, 58
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z10PDH_on_gpuPdS_S_P10hist_entryidi"
.size .L__unnamed_1, 37
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Number of threads must be greater or equal to 32."
.size .Lstr, 50
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "Usage: ./SDH {# Atoms} {# Buckets} {# Threads}"
.size .Lstr.1, 47
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__PDH_on_gpuPdS_S_P10hist_entryidi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym Idunno
.addrsig_sym endTime
.addrsig_sym _Z10PDH_on_gpuPdS_S_P10hist_entryidi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00008be1_00000000-6_SDH.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2066:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2066:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z8distancedddddd
.type _Z8distancedddddd, @function
_Z8distancedddddd:
.LFB2057:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size _Z8distancedddddd, .-_Z8distancedddddd
.globl _Z12p2p_distanceP8atomdescii
.type _Z12p2p_distanceP8atomdescii, @function
_Z12p2p_distanceP8atomdescii:
.LFB2058:
.cfi_startproc
endbr64
movslq %esi, %rsi
leaq (%rsi,%rsi,2), %rax
leaq (%rdi,%rax,8), %rcx
movslq %edx, %rdx
leaq (%rdx,%rdx,2), %rax
leaq (%rdi,%rax,8), %rax
movsd (%rcx), %xmm1
subsd (%rax), %xmm1
movsd 8(%rcx), %xmm2
subsd 8(%rax), %xmm2
movsd 16(%rcx), %xmm0
subsd 16(%rax), %xmm0
mulsd %xmm1, %xmm1
mulsd %xmm2, %xmm2
addsd %xmm2, %xmm1
mulsd %xmm0, %xmm0
addsd %xmm1, %xmm0
sqrtsd %xmm0, %xmm0
ret
.cfi_endproc
.LFE2058:
.size _Z12p2p_distanceP8atomdescii, .-_Z12p2p_distanceP8atomdescii
.globl _Z12PDH_baselineP8atomdescP10hist_entryxd
.type _Z12PDH_baselineP8atomdescP10hist_entryxd, @function
_Z12PDH_baselineP8atomdescP10hist_entryxd:
.LFB2059:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $24, %rsp
.cfi_def_cfa_offset 80
movq %rdx, 16(%rsp)
movsd %xmm0, (%rsp)
testq %rdx, %rdx
jle .L7
movq %rdi, %r13
movq %rsi, %rbp
leaq -1(%rdx), %rcx
movq %rcx, 8(%rsp)
movl $0, %r15d
movl %edx, %r14d
.L9:
movl %r15d, %r12d
leal 1(%r15), %ebx
movq 8(%rsp), %rax
cmpq %rax, %r15
je .L7
.L8:
movl %ebx, %edx
movl %r12d, %esi
movq %r13, %rdi
call _Z12p2p_distanceP8atomdescii
divsd (%rsp), %xmm0
cvttsd2sil %xmm0, %eax
cltq
addq $1, 0(%rbp,%rax,8)
addl $1, %ebx
cmpl %ebx, %r14d
jne .L8
addq $1, %r15
movq 16(%rsp), %rax
cmpq %rax, %r15
jne .L9
.L7:
movl $0, %eax
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size _Z12PDH_baselineP8atomdescP10hist_entryxd, .-_Z12PDH_baselineP8atomdescP10hist_entryxd
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Running time: %ld.%06ld\n"
.text
.globl _Z19report_running_timev
.type _Z19report_running_timev, @function
_Z19report_running_timev:
.LFB2060:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
leaq Idunno(%rip), %rsi
leaq endTime(%rip), %rdi
call gettimeofday@PLT
movq endTime(%rip), %rbp
subq startTime(%rip), %rbp
movq 8+endTime(%rip), %rbx
subq 8+startTime(%rip), %rbx
js .L16
.L14:
movq %rbx, %rcx
movq %rbp, %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
pxor %xmm0, %xmm0
cvtsi2sdq %rbx, %xmm0
divsd .LC1(%rip), %xmm0
pxor %xmm1, %xmm1
cvtsi2sdq %rbp, %xmm1
addsd %xmm1, %xmm0
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L16:
.cfi_restore_state
subq $1, %rbp
addq $1000000, %rbx
jmp .L14
.cfi_endproc
.LFE2060:
.size _Z19report_running_timev, .-_Z19report_running_timev
.section .rodata.str1.1
.LC2:
.string "\n%02d: "
.LC3:
.string "%15lld "
.LC4:
.string "\n T:%lld \n"
.LC5:
.string "| "
.text
.globl _Z16output_histogramP10hist_entryi
.type _Z16output_histogramP10hist_entryi, @function
_Z16output_histogramP10hist_entryi:
.LFB2061:
.cfi_startproc
endbr64
testl %esi, %esi
jle .L25
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $8, %rsp
.cfi_def_cfa_offset 64
movq %rdi, %rbp
movl %esi, %r13d
movslq %esi, %r15
movl $0, %ebx
movl $0, %r12d
leaq .LC3(%rip), %r14
jmp .L22
.L19:
movq 0(%rbp,%rbx,8), %rdx
movq %r14, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %r12, %rdx
addq 0(%rbp,%rbx,8), %rdx
movq %rdx, %r12
leal -1(%r13), %eax
cmpl %ebx, %eax
je .L28
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L21:
addq $1, %rbx
cmpq %r15, %rbx
je .L29
.L22:
movslq %ebx, %rax
imulq $1717986919, %rax, %rax
sarq $33, %rax
movl %ebx, %edx
sarl $31, %edx
subl %edx, %eax
leal (%rax,%rax,4), %eax
cmpl %ebx, %eax
jne .L19
movl %ebx, %edx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L19
.L28:
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L21
.L29:
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L25:
.cfi_restore 3
.cfi_restore 6
.cfi_restore 12
.cfi_restore 13
.cfi_restore 14
.cfi_restore 15
ret
.cfi_endproc
.LFE2061:
.size _Z16output_histogramP10hist_entryi, .-_Z16output_histogramP10hist_entryi
.section .rodata.str1.1
.LC6:
.string "Error: %s\n"
.text
.globl _Z11catch_error9cudaError
.type _Z11catch_error9cudaError, @function
_Z11catch_error9cudaError:
.LFB2062:
.cfi_startproc
endbr64
testl %edi, %edi
jne .L36
ret
.L36:
subq $8, %rsp
.cfi_def_cfa_offset 16
movl err(%rip), %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _Z11catch_error9cudaError, .-_Z11catch_error9cudaError
.globl _Z50__device_stub__Z10PDH_on_gpuPdS_S_P10hist_entryidiPdS_S_P10hist_entryidi
.type _Z50__device_stub__Z10PDH_on_gpuPdS_S_P10hist_entryidiPdS_S_P10hist_entryidi, @function
_Z50__device_stub__Z10PDH_on_gpuPdS_S_P10hist_entryidiPdS_S_P10hist_entryidi:
.LFB2088:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movl %r8d, 12(%rsp)
movsd %xmm0, (%rsp)
movl %r9d, 8(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 12(%rsp), %rax
movq %rax, 144(%rsp)
movq %rsp, %rax
movq %rax, 152(%rsp)
leaq 8(%rsp), %rax
movq %rax, 160(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L41
.L37:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L42
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L41:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z10PDH_on_gpuPdS_S_P10hist_entryidi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L37
.L42:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2088:
.size _Z50__device_stub__Z10PDH_on_gpuPdS_S_P10hist_entryidiPdS_S_P10hist_entryidi, .-_Z50__device_stub__Z10PDH_on_gpuPdS_S_P10hist_entryidiPdS_S_P10hist_entryidi
.globl _Z10PDH_on_gpuPdS_S_P10hist_entryidi
.type _Z10PDH_on_gpuPdS_S_P10hist_entryidi, @function
_Z10PDH_on_gpuPdS_S_P10hist_entryidi:
.LFB2089:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z50__device_stub__Z10PDH_on_gpuPdS_S_P10hist_entryidiPdS_S_P10hist_entryidi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2089:
.size _Z10PDH_on_gpuPdS_S_P10hist_entryidi, .-_Z10PDH_on_gpuPdS_S_P10hist_entryidi
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC7:
.string "Usage: ./SDH {# Atoms} {# Buckets} {# Threads}\n"
.align 8
.LC8:
.string "Number of threads must be greater or equal to 32.\n"
.align 8
.LC14:
.string "******** Total Running Time of Kernel = %.5f sec *******\n"
.text
.globl main
.type main, @function
main:
.LFB2063:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $104, %rsp
.cfi_def_cfa_offset 160
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
cmpl $3, %edi
jle .L57
movq %rsi, %rbx
movq 24(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
cmpl $31, %eax
jle .L58
movq 8(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
cltq
movq %rax, PDH_acnt(%rip)
movq 16(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, PDH_res(%rip)
movq 24(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movl %eax, PDH_threads(%rip)
movl $0x00000000, 12(%rsp)
movsd .LC10(%rip), %xmm0
divsd PDH_res(%rip), %xmm0
cvttsd2sil %xmm0, %ebp
addl $1, %ebp
movl %ebp, num_buckets(%rip)
movq PDH_acnt(%rip), %rbx
leaq (%rbx,%rbx,2), %rdi
salq $3, %rdi
call malloc@PLT
movq %rax, atom_list(%rip)
movslq %ebp, %rbp
salq $3, %rbp
movq %rbp, %rdi
call malloc@PLT
movq %rax, histogram(%rip)
salq $3, %rbx
movq %rbx, %rdi
call malloc@PLT
movq %rax, %r14
movq %rbx, %rdi
call malloc@PLT
movq %rax, %r13
movq %rbx, %rdi
call malloc@PLT
movq %rax, %r12
movq %rbp, %rdi
call malloc@PLT
movq %rax, %r15
movl $0, err(%rip)
movl $1, %edi
call srand@PLT
movq PDH_acnt(%rip), %rsi
testq %rsi, %rsi
jle .L48
movl $0, %ebx
.L49:
call rand@PLT
movl %eax, %edx
leaq (%rbx,%rbx,2), %rax
leaq 0(,%rax,8), %rbp
pxor %xmm0, %xmm0
cvtsi2sdl %edx, %xmm0
divsd .LC11(%rip), %xmm0
mulsd .LC12(%rip), %xmm0
movq atom_list(%rip), %rdx
movsd %xmm0, (%rdx,%rax,8)
movsd %xmm0, (%r14,%rbx,8)
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
divsd .LC11(%rip), %xmm0
mulsd .LC12(%rip), %xmm0
movq atom_list(%rip), %rax
movsd %xmm0, 8(%rax,%rbp)
movsd %xmm0, 0(%r13,%rbx,8)
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
divsd .LC11(%rip), %xmm0
mulsd .LC12(%rip), %xmm0
movq atom_list(%rip), %rax
movsd %xmm0, 16(%rax,%rbp)
movsd %xmm0, (%r12,%rbx,8)
movq PDH_acnt(%rip), %rsi
addq $1, %rbx
cmpq %rbx, %rsi
jg .L49
.L48:
movl num_buckets(%rip), %edx
testl %edx, %edx
jle .L50
movq %r15, %rax
movslq %edx, %rdx
leaq (%r15,%rdx,8), %rdx
.L51:
movq $0, (%rax)
addq $8, %rax
cmpq %rdx, %rax
jne .L51
.L50:
salq $3, %rsi
leaq 16(%rsp), %rdi
call cudaMalloc@PLT
movl %eax, %edi
movl %eax, err(%rip)
call _Z11catch_error9cudaError
movq PDH_acnt(%rip), %rax
leaq 0(,%rax,8), %rsi
leaq 24(%rsp), %rdi
call cudaMalloc@PLT
movl %eax, %edi
movl %eax, err(%rip)
call _Z11catch_error9cudaError
movq PDH_acnt(%rip), %rax
leaq 0(,%rax,8), %rsi
leaq 32(%rsp), %rdi
call cudaMalloc@PLT
movl %eax, %edi
movl %eax, err(%rip)
call _Z11catch_error9cudaError
movslq num_buckets(%rip), %rsi
salq $3, %rsi
leaq 40(%rsp), %rdi
call cudaMalloc@PLT
movl %eax, %edi
movl %eax, err(%rip)
call _Z11catch_error9cudaError
movq PDH_acnt(%rip), %rax
leaq 0(,%rax,8), %rdx
movl $1, %ecx
movq %r14, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
movl %eax, err(%rip)
call _Z11catch_error9cudaError
movq PDH_acnt(%rip), %rax
leaq 0(,%rax,8), %rdx
movl $1, %ecx
movq %r13, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
movl %eax, err(%rip)
call _Z11catch_error9cudaError
movq PDH_acnt(%rip), %rax
leaq 0(,%rax,8), %rdx
movl $1, %ecx
movq %r12, %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
movl %eax, err(%rip)
call _Z11catch_error9cudaError
movslq num_buckets(%rip), %rdx
salq $3, %rdx
movl $1, %ecx
movq %r15, %rsi
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
movl %eax, err(%rip)
call _Z11catch_error9cudaError
leaq 48(%rsp), %rdi
call cudaEventCreate@PLT
leaq 56(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 48(%rsp), %rdi
call cudaEventRecord@PLT
movslq num_buckets(%rip), %rsi
movl PDH_threads(%rip), %ecx
movl %ecx, 76(%rsp)
movl $1, 80(%rsp)
movslq %ecx, %rcx
movq PDH_acnt(%rip), %rax
leaq -1(%rcx,%rax), %rax
cqto
idivq %rcx
movl %eax, 64(%rsp)
movl $1, 68(%rsp)
movl $0, %r9d
leaq 0(,%rsi,4), %r8
movq 76(%rsp), %rdx
movl $1, %ecx
movq 64(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L59
.L52:
movl $0, %esi
movq 56(%rsp), %rdi
call cudaEventRecord@PLT
movq 56(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 12(%rsp), %rdi
movq 56(%rsp), %rdx
movq 48(%rsp), %rsi
call cudaEventElapsedTime@PLT
movq 48(%rsp), %rdi
call cudaEventDestroy@PLT
movq 56(%rsp), %rdi
call cudaEventDestroy@PLT
movslq num_buckets(%rip), %rdx
salq $3, %rdx
movl $2, %ecx
movq 40(%rsp), %rsi
movq %r15, %rdi
call cudaMemcpy@PLT
movl %eax, %edi
movl %eax, err(%rip)
call _Z11catch_error9cudaError
movl num_buckets(%rip), %esi
movq %r15, %rdi
call _Z16output_histogramP10hist_entryi
pxor %xmm0, %xmm0
cvtss2sd 12(%rsp), %xmm0
divsd .LC13(%rip), %xmm0
leaq .LC14(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq histogram(%rip), %rdi
call free@PLT
movq %r15, %rdi
call free@PLT
movq atom_list(%rip), %rdi
call free@PLT
movq %r14, %rdi
call free@PLT
movq %r13, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L60
movl $0, %eax
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L57:
.cfi_restore_state
leaq .LC7(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L58:
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L59:
movl num_buckets(%rip), %r9d
movsd PDH_res(%rip), %xmm0
movl PDH_acnt(%rip), %r8d
movq 40(%rsp), %rcx
movq 32(%rsp), %rdx
movq 24(%rsp), %rsi
movq 16(%rsp), %rdi
call _Z50__device_stub__Z10PDH_on_gpuPdS_S_P10hist_entryidiPdS_S_P10hist_entryidi
jmp .L52
.L60:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2063:
.size main, .-main
.section .rodata.str1.8
.align 8
.LC15:
.string "_Z10PDH_on_gpuPdS_S_P10hist_entryidi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2091:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC15(%rip), %rdx
movq %rdx, %rcx
leaq _Z10PDH_on_gpuPdS_S_P10hist_entryidi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2091:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl endTime
.bss
.align 16
.type endTime, @object
.size endTime, 16
endTime:
.zero 16
.globl startTime
.align 16
.type startTime, @object
.size startTime, 16
startTime:
.zero 16
.globl Idunno
.align 8
.type Idunno, @object
.size Idunno, 8
Idunno:
.zero 8
.globl atom_list
.align 8
.type atom_list, @object
.size atom_list, 8
atom_list:
.zero 8
.globl histogram
.align 8
.type histogram, @object
.size histogram, 8
histogram:
.zero 8
.globl PDH_threads
.align 4
.type PDH_threads, @object
.size PDH_threads, 4
PDH_threads:
.zero 4
.globl num_buckets
.align 4
.type num_buckets, @object
.size num_buckets, 4
num_buckets:
.zero 4
.globl PDH_res
.align 8
.type PDH_res, @object
.size PDH_res, 8
PDH_res:
.zero 8
.globl PDH_acnt
.align 8
.type PDH_acnt, @object
.size PDH_acnt, 8
PDH_acnt:
.zero 8
.globl err
.align 4
.type err, @object
.size err, 4
err:
.zero 4
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC1:
.long 0
.long 1093567616
.align 8
.LC10:
.long 0
.long 1088648064
.align 8
.LC11:
.long -4194304
.long 1105199103
.align 8
.LC12:
.long 0
.long 1087796736
.align 8
.LC13:
.long 0
.long 1083129856
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "SDH.hip"
.globl _Z25__device_stub__PDH_on_gpuPdS_S_P10hist_entryidi # -- Begin function _Z25__device_stub__PDH_on_gpuPdS_S_P10hist_entryidi
.p2align 4, 0x90
.type _Z25__device_stub__PDH_on_gpuPdS_S_P10hist_entryidi,@function
_Z25__device_stub__PDH_on_gpuPdS_S_P10hist_entryidi: # @_Z25__device_stub__PDH_on_gpuPdS_S_P10hist_entryidi
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movl %r8d, 4(%rsp)
movsd %xmm0, 56(%rsp)
movl %r9d, (%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
leaq 56(%rsp), %rax
movq %rax, 136(%rsp)
movq %rsp, %rax
movq %rax, 144(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z10PDH_on_gpuPdS_S_P10hist_entryidi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z25__device_stub__PDH_on_gpuPdS_S_P10hist_entryidi, .Lfunc_end0-_Z25__device_stub__PDH_on_gpuPdS_S_P10hist_entryidi
.cfi_endproc
# -- End function
.globl _Z12p2p_distanceP8atomdescii # -- Begin function _Z12p2p_distanceP8atomdescii
.p2align 4, 0x90
.type _Z12p2p_distanceP8atomdescii,@function
_Z12p2p_distanceP8atomdescii: # @_Z12p2p_distanceP8atomdescii
.cfi_startproc
# %bb.0:
movslq %esi, %rax
leaq (%rax,%rax,2), %rax
movslq %edx, %rcx
leaq (%rcx,%rcx,2), %rcx
movsd (%rdi,%rax,8), %xmm1 # xmm1 = mem[0],zero
movsd 8(%rdi,%rax,8), %xmm2 # xmm2 = mem[0],zero
movsd 16(%rdi,%rax,8), %xmm0 # xmm0 = mem[0],zero
subsd (%rdi,%rcx,8), %xmm1
mulsd %xmm1, %xmm1
subsd 8(%rdi,%rcx,8), %xmm2
mulsd %xmm2, %xmm2
addsd %xmm1, %xmm2
subsd 16(%rdi,%rcx,8), %xmm0
mulsd %xmm0, %xmm0
addsd %xmm2, %xmm0
xorpd %xmm1, %xmm1
ucomisd %xmm1, %xmm0
jb sqrt # TAILCALL
# %bb.1: # %.split
sqrtsd %xmm0, %xmm0
retq
.Lfunc_end1:
.size _Z12p2p_distanceP8atomdescii, .Lfunc_end1-_Z12p2p_distanceP8atomdescii
.cfi_endproc
# -- End function
.globl _Z12PDH_baselineP8atomdescP10hist_entryxd # -- Begin function _Z12PDH_baselineP8atomdescP10hist_entryxd
.p2align 4, 0x90
.type _Z12PDH_baselineP8atomdescP10hist_entryxd,@function
_Z12PDH_baselineP8atomdescP10hist_entryxd: # @_Z12PDH_baselineP8atomdescP10hist_entryxd
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $40, %rsp
.cfi_def_cfa_offset 96
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rdi, 8(%rsp) # 8-byte Spill
testq %rdx, %rdx
jle .LBB2_9
# %bb.1: # %.lr.ph17.preheader
movapd %xmm0, %xmm3
movq %rdx, %rbx
movq %rsi, %r14
movq 8(%rsp), %rax # 8-byte Reload
addq $40, %rax
movq %rax, 16(%rsp) # 8-byte Spill
movl $1, %ebp
xorl %eax, %eax
xorpd %xmm4, %xmm4
movsd %xmm0, 32(%rsp) # 8-byte Spill
jmp .LBB2_3
.p2align 4, 0x90
.LBB2_2: # %.loopexit
# in Loop: Header=BB2_3 Depth=1
incq %rbp
addq $24, 16(%rsp) # 8-byte Folded Spill
movq 24(%rsp), %rax # 8-byte Reload
cmpq %rbx, %rax
je .LBB2_9
.LBB2_3: # %.lr.ph17
# =>This Loop Header: Depth=1
# Child Loop BB2_5 Depth 2
leaq 1(%rax), %rcx
movq %rcx, 24(%rsp) # 8-byte Spill
cmpq %rbx, %rcx
jge .LBB2_2
# %bb.4: # %.lr.ph
# in Loop: Header=BB2_3 Depth=1
leaq (%rax,%rax,2), %rax
movq 8(%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax,8), %r15
movq 16(%rsp), %r12 # 8-byte Reload
movq %rbp, %r13
jmp .LBB2_5
.p2align 4, 0x90
.LBB2_7: # %call.sqrt
# in Loop: Header=BB2_5 Depth=2
callq sqrt
xorpd %xmm4, %xmm4
movsd 32(%rsp), %xmm3 # 8-byte Reload
# xmm3 = mem[0],zero
.LBB2_8: # %.split
# in Loop: Header=BB2_5 Depth=2
divsd %xmm3, %xmm0
cvttsd2si %xmm0, %eax
cltq
incq (%r14,%rax,8)
incq %r13
addq $24, %r12
cmpq %rbx, %r13
jge .LBB2_2
.LBB2_5: # Parent Loop BB2_3 Depth=1
# => This Inner Loop Header: Depth=2
movsd (%r15), %xmm1 # xmm1 = mem[0],zero
movsd 8(%r15), %xmm2 # xmm2 = mem[0],zero
subsd -16(%r12), %xmm1
movsd 16(%r15), %xmm0 # xmm0 = mem[0],zero
mulsd %xmm1, %xmm1
subsd -8(%r12), %xmm2
mulsd %xmm2, %xmm2
addsd %xmm1, %xmm2
subsd (%r12), %xmm0
mulsd %xmm0, %xmm0
addsd %xmm2, %xmm0
ucomisd %xmm4, %xmm0
jb .LBB2_7
# %bb.6: # in Loop: Header=BB2_5 Depth=2
sqrtsd %xmm0, %xmm0
jmp .LBB2_8
.LBB2_9: # %._crit_edge
xorl %eax, %eax
addq $40, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z12PDH_baselineP8atomdescP10hist_entryxd, .Lfunc_end2-_Z12PDH_baselineP8atomdescP10hist_entryxd
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z19report_running_timev
.LCPI3_0:
.quad 0x412e848000000000 # double 1.0E+6
.text
.globl _Z19report_running_timev
.p2align 4, 0x90
.type _Z19report_running_timev,@function
_Z19report_running_timev: # @_Z19report_running_timev
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movl $endTime, %edi
movl $Idunno, %esi
callq gettimeofday
movq endTime(%rip), %rax
subq startTime(%rip), %rax
movq endTime+8(%rip), %rcx
subq startTime+8(%rip), %rcx
leaq 1000000(%rcx), %rbx
movq %rcx, %r14
sarq $63, %r14
addq %rax, %r14
testq %rcx, %rcx
cmovnsq %rcx, %rbx
movl $.L.str, %edi
movq %r14, %rsi
movq %rbx, %rdx
xorl %eax, %eax
callq printf
cvtsi2sd %r14, %xmm1
cvtsi2sd %rbx, %xmm0
divsd .LCPI3_0(%rip), %xmm0
addsd %xmm1, %xmm0
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size _Z19report_running_timev, .Lfunc_end3-_Z19report_running_timev
.cfi_endproc
# -- End function
.globl _Z16output_histogramP10hist_entryi # -- Begin function _Z16output_histogramP10hist_entryi
.p2align 4, 0x90
.type _Z16output_histogramP10hist_entryi,@function
_Z16output_histogramP10hist_entryi: # @_Z16output_histogramP10hist_entryi
.cfi_startproc
# %bb.0:
# kill: def $esi killed $esi def $rsi
testl %esi, %esi
jle .LBB4_9
# %bb.1: # %.lr.ph
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
pushq %rax
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rdi, %rbx
leal -1(%rsi), %r12d
movl %esi, %r13d
movl $3435973837, %ebp # imm = 0xCCCCCCCD
xorl %r14d, %r14d
xorl %r15d, %r15d
jmp .LBB4_2
.p2align 4, 0x90
.LBB4_5: # in Loop: Header=BB4_2 Depth=1
movl $.L.str.3, %edi
movq %r15, %rsi
xorl %eax, %eax
callq printf
.LBB4_7: # in Loop: Header=BB4_2 Depth=1
incq %r14
cmpq %r14, %r13
je .LBB4_8
.LBB4_2: # =>This Inner Loop Header: Depth=1
movl %r14d, %eax
imulq %rbp, %rax
shrq $34, %rax
leal (%rax,%rax,4), %eax
cmpl %eax, %r14d
jne .LBB4_4
# %bb.3: # in Loop: Header=BB4_2 Depth=1
movl $.L.str.1, %edi
movl %r14d, %esi
xorl %eax, %eax
callq printf
.LBB4_4: # in Loop: Header=BB4_2 Depth=1
movq (%rbx,%r14,8), %rsi
movl $.L.str.2, %edi
xorl %eax, %eax
callq printf
addq (%rbx,%r14,8), %r15
cmpq %r14, %r12
je .LBB4_5
# %bb.6: # in Loop: Header=BB4_2 Depth=1
movl $.L.str.4, %edi
xorl %eax, %eax
callq printf
jmp .LBB4_7
.LBB4_8:
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r12
.cfi_restore %r13
.cfi_restore %r14
.cfi_restore %r15
.cfi_restore %rbp
.LBB4_9: # %._crit_edge
retq
.Lfunc_end4:
.size _Z16output_histogramP10hist_entryi, .Lfunc_end4-_Z16output_histogramP10hist_entryi
.cfi_endproc
# -- End function
.globl _Z11catch_error10hipError_t # -- Begin function _Z11catch_error10hipError_t
.p2align 4, 0x90
.type _Z11catch_error10hipError_t,@function
_Z11catch_error10hipError_t: # @_Z11catch_error10hipError_t
.cfi_startproc
# %bb.0:
testl %edi, %edi
je .LBB5_1
# %bb.2:
pushq %rax
.cfi_def_cfa_offset 16
movl err(%rip), %edi
callq hipGetErrorString
movl $.L.str.5, %edi
movq %rax, %rsi
xorl %eax, %eax
popq %rcx
.cfi_def_cfa_offset 8
jmp printf # TAILCALL
.LBB5_1:
retq
.Lfunc_end5:
.size _Z11catch_error10hipError_t, .Lfunc_end5-_Z11catch_error10hipError_t
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI6_0:
.quad 0x40e3738000000000 # double 39836
.LCPI6_1:
.quad 0x41dfffffffc00000 # double 2147483647
.LCPI6_2:
.quad 0x40d6760000000000 # double 23000
.LCPI6_3:
.quad 0x408f400000000000 # double 1000
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $248, %rsp
.cfi_def_cfa_offset 304
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
cmpl $3, %edi
jle .LBB6_1
# %bb.3:
movq %rsi, %rbx
movq 24(%rsi), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
cmpl $31, %eax
jle .LBB6_4
# %bb.5:
movq 8(%rbx), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
cltq
movq %rax, PDH_acnt(%rip)
movq 16(%rbx), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, PDH_res(%rip)
movq 24(%rbx), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movl %eax, PDH_threads(%rip)
movsd .LCPI6_0(%rip), %xmm0 # xmm0 = mem[0],zero
divsd PDH_res(%rip), %xmm0
movl $0, 12(%rsp)
cvttsd2si %xmm0, %ebx
leal 1(%rbx), %eax
movl %eax, num_buckets(%rip)
movq PDH_acnt(%rip), %r15
shlq $3, %r15
leaq (%r15,%r15,2), %rdi
callq malloc
movq %rax, atom_list(%rip)
movslq %ebx, %rax
leaq 8(,%rax,8), %rbx
movq %rbx, %rdi
callq malloc
movq %rax, histogram(%rip)
movq %r15, %rdi
callq malloc
movq %rax, %r12
movq %r15, %rdi
callq malloc
movq %r15, %rdi
movq %rax, %r15
callq malloc
movq %rax, %rbp
movq %rbx, %rdi
callq malloc
movq %rax, 80(%rsp) # 8-byte Spill
movl $0, err(%rip)
movl $1, %edi
callq srand
movq PDH_acnt(%rip), %r13
testq %r13, %r13
jle .LBB6_8
# %bb.6: # %.lr.ph.preheader
xorl %ebx, %ebx
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB6_7: # %.lr.ph
# =>This Inner Loop Header: Depth=1
callq rand
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
movsd .LCPI6_1(%rip), %xmm1 # xmm1 = mem[0],zero
divsd %xmm1, %xmm0
movsd .LCPI6_2(%rip), %xmm1 # xmm1 = mem[0],zero
mulsd %xmm1, %xmm0
movq atom_list(%rip), %rax
movsd %xmm0, (%rax,%rbx)
movsd %xmm0, (%r12,%r14,8)
callq rand
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
divsd .LCPI6_1(%rip), %xmm0
mulsd .LCPI6_2(%rip), %xmm0
movq atom_list(%rip), %rax
movsd %xmm0, 8(%rax,%rbx)
movsd %xmm0, (%r15,%r14,8)
callq rand
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
divsd .LCPI6_1(%rip), %xmm0
mulsd .LCPI6_2(%rip), %xmm0
movq atom_list(%rip), %rax
movsd %xmm0, 16(%rax,%rbx)
movsd %xmm0, (%rbp,%r14,8)
incq %r14
movq PDH_acnt(%rip), %r13
addq $24, %rbx
cmpq %r14, %r13
jg .LBB6_7
.LBB6_8: # %.preheader
movq %r12, %r14
movq %rbp, 72(%rsp) # 8-byte Spill
movl num_buckets(%rip), %edx
testl %edx, %edx
movq 80(%rsp), %r12 # 8-byte Reload
jle .LBB6_10
# %bb.9: # %.lr.ph54.preheader
shlq $3, %rdx
movq %r12, %rdi
xorl %esi, %esi
callq memset@PLT
.LBB6_10: # %._crit_edge
shlq $3, %r13
leaq 56(%rsp), %rdi
movq %r13, %rsi
callq hipMalloc
movl %eax, err(%rip)
testl %eax, %eax
movq 72(%rsp), %rbx # 8-byte Reload
je .LBB6_12
# %bb.11:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.5, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
.LBB6_12: # %_Z11catch_error10hipError_t.exit
movq PDH_acnt(%rip), %rsi
shlq $3, %rsi
leaq 48(%rsp), %rdi
callq hipMalloc
movl %eax, err(%rip)
testl %eax, %eax
je .LBB6_14
# %bb.13:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.5, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
.LBB6_14: # %_Z11catch_error10hipError_t.exit34
movq PDH_acnt(%rip), %rsi
shlq $3, %rsi
leaq 40(%rsp), %rdi
callq hipMalloc
movl %eax, err(%rip)
testl %eax, %eax
je .LBB6_16
# %bb.15:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.5, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
.LBB6_16: # %_Z11catch_error10hipError_t.exit36
movslq num_buckets(%rip), %rsi
shlq $3, %rsi
leaq 24(%rsp), %rdi
callq hipMalloc
movl %eax, err(%rip)
testl %eax, %eax
je .LBB6_18
# %bb.17:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.5, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
.LBB6_18: # %_Z11catch_error10hipError_t.exit38
movq 56(%rsp), %rdi
movq PDH_acnt(%rip), %rdx
shlq $3, %rdx
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movl %eax, err(%rip)
testl %eax, %eax
je .LBB6_20
# %bb.19:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.5, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
.LBB6_20: # %_Z11catch_error10hipError_t.exit40
movq 48(%rsp), %rdi
movq PDH_acnt(%rip), %rdx
shlq $3, %rdx
movq %r15, %rsi
movl $1, %ecx
callq hipMemcpy
movl %eax, err(%rip)
testl %eax, %eax
je .LBB6_22
# %bb.21:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.5, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
.LBB6_22: # %_Z11catch_error10hipError_t.exit42
movq 40(%rsp), %rdi
movq PDH_acnt(%rip), %rdx
shlq $3, %rdx
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movl %eax, err(%rip)
testl %eax, %eax
je .LBB6_24
# %bb.23:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.5, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
.LBB6_24: # %_Z11catch_error10hipError_t.exit44
movq 24(%rsp), %rdi
movslq num_buckets(%rip), %rdx
shlq $3, %rdx
movq %r12, %rsi
movl $1, %ecx
callq hipMemcpy
movl %eax, err(%rip)
testl %eax, %eax
je .LBB6_26
# %bb.25:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.5, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
.LBB6_26: # %_Z11catch_error10hipError_t.exit46
movq %r15, 88(%rsp) # 8-byte Spill
movq %r14, 96(%rsp) # 8-byte Spill
leaq 32(%rsp), %rdi
callq hipEventCreate
leaq 16(%rsp), %rdi
callq hipEventCreate
movq 32(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq PDH_acnt(%rip), %rax
movl PDH_threads(%rip), %ecx
movslq %ecx, %rsi
addq %rsi, %rax
decq %rax
cqto
idivq %rsi
movslq num_buckets(%rip), %r8
shlq $2, %r8
movl %eax, %edi
movabsq $4294967296, %rax # imm = 0x100000000
orq %rax, %rdi
orq %rax, %rcx
movl $1, %esi
movq %rcx, %rdx
movl $1, %ecx
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB6_28
# %bb.27:
movq 56(%rsp), %rax
movq 48(%rsp), %rcx
movq 40(%rsp), %rdx
movq 24(%rsp), %rsi
movl PDH_acnt(%rip), %edi
movsd PDH_res(%rip), %xmm0 # xmm0 = mem[0],zero
movl num_buckets(%rip), %r8d
movq %rax, 184(%rsp)
movq %rcx, 176(%rsp)
movq %rdx, 168(%rsp)
movq %rsi, 160(%rsp)
movl %edi, 68(%rsp)
movsd %xmm0, 152(%rsp)
movl %r8d, 64(%rsp)
leaq 184(%rsp), %rax
movq %rax, 192(%rsp)
leaq 176(%rsp), %rax
movq %rax, 200(%rsp)
leaq 168(%rsp), %rax
movq %rax, 208(%rsp)
leaq 160(%rsp), %rax
movq %rax, 216(%rsp)
leaq 68(%rsp), %rax
movq %rax, 224(%rsp)
leaq 152(%rsp), %rax
movq %rax, 232(%rsp)
leaq 64(%rsp), %rax
movq %rax, 240(%rsp)
leaq 136(%rsp), %rdi
leaq 120(%rsp), %rsi
leaq 112(%rsp), %rdx
leaq 104(%rsp), %rcx
callq __hipPopCallConfiguration
movq 136(%rsp), %rsi
movl 144(%rsp), %edx
movq 120(%rsp), %rcx
movl 128(%rsp), %r8d
leaq 192(%rsp), %r9
movl $_Z10PDH_on_gpuPdS_S_P10hist_entryidi, %edi
pushq 104(%rsp)
.cfi_adjust_cfa_offset 8
pushq 120(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB6_28:
movq 16(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 16(%rsp), %rdi
callq hipEventSynchronize
movq 32(%rsp), %rsi
movq 16(%rsp), %rdx
leaq 12(%rsp), %rdi
callq hipEventElapsedTime
movq 32(%rsp), %rdi
callq hipEventDestroy
movq 16(%rsp), %rdi
callq hipEventDestroy
movq 24(%rsp), %rsi
movslq num_buckets(%rip), %rdx
shlq $3, %rdx
movq %r12, %rdi
movl $2, %ecx
callq hipMemcpy
movl %eax, err(%rip)
testl %eax, %eax
je .LBB6_30
# %bb.29:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.5, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
.LBB6_30: # %_Z11catch_error10hipError_t.exit48
movl num_buckets(%rip), %ebx
testl %ebx, %ebx
jle .LBB6_38
# %bb.31: # %.lr.ph.i
leal -1(%rbx), %r14d
movl $3435973837, %r15d # imm = 0xCCCCCCCD
xorl %r13d, %r13d
xorl %ebp, %ebp
jmp .LBB6_32
.p2align 4, 0x90
.LBB6_36: # in Loop: Header=BB6_32 Depth=1
movl $.L.str.4, %edi
xorl %eax, %eax
callq printf
.LBB6_37: # in Loop: Header=BB6_32 Depth=1
incq %r13
cmpq %r13, %rbx
je .LBB6_38
.LBB6_32: # =>This Inner Loop Header: Depth=1
movl %r13d, %eax
imulq %r15, %rax
shrq $34, %rax
leal (%rax,%rax,4), %eax
cmpl %eax, %r13d
jne .LBB6_34
# %bb.33: # in Loop: Header=BB6_32 Depth=1
movl $.L.str.1, %edi
movl %r13d, %esi
xorl %eax, %eax
callq printf
.LBB6_34: # in Loop: Header=BB6_32 Depth=1
movq (%r12,%r13,8), %rsi
movl $.L.str.2, %edi
xorl %eax, %eax
callq printf
addq (%r12,%r13,8), %rbp
cmpq %r13, %r14
jne .LBB6_36
# %bb.35: # in Loop: Header=BB6_32 Depth=1
movl $.L.str.3, %edi
movq %rbp, %rsi
xorl %eax, %eax
callq printf
jmp .LBB6_37
.LBB6_38: # %_Z16output_histogramP10hist_entryi.exit
movss 12(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
divsd .LCPI6_3(%rip), %xmm0
movl $.L.str.8, %edi
movb $1, %al
callq printf
movq 56(%rsp), %rdi
callq hipFree
movq 48(%rsp), %rdi
callq hipFree
movq 40(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
movq histogram(%rip), %rdi
callq free
movq %r12, %rdi
callq free
movq atom_list(%rip), %rdi
callq free
movq 96(%rsp), %rdi # 8-byte Reload
callq free
movq 88(%rsp), %rdi # 8-byte Reload
callq free
movq 72(%rsp), %rdi # 8-byte Reload
callq free
xorl %eax, %eax
addq $248, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB6_1:
.cfi_def_cfa_offset 304
movl $.Lstr.1, %edi
jmp .LBB6_2
.LBB6_4:
movl $.Lstr, %edi
.LBB6_2:
callq puts@PLT
movl $1, %edi
callq exit
.Lfunc_end6:
.size main, .Lfunc_end6-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB7_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB7_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10PDH_on_gpuPdS_S_P10hist_entryidi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end7:
.size __hip_module_ctor, .Lfunc_end7-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB8_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB8_2:
retq
.Lfunc_end8:
.size __hip_module_dtor, .Lfunc_end8-__hip_module_dtor
.cfi_endproc
# -- End function
.type err,@object # @err
.bss
.globl err
.p2align 2, 0x0
err:
.long 0 # 0x0
.size err, 4
.type PDH_acnt,@object # @PDH_acnt
.globl PDH_acnt
.p2align 3, 0x0
PDH_acnt:
.quad 0 # 0x0
.size PDH_acnt, 8
.type PDH_res,@object # @PDH_res
.globl PDH_res
.p2align 3, 0x0
PDH_res:
.quad 0x0000000000000000 # double 0
.size PDH_res, 8
.type num_buckets,@object # @num_buckets
.globl num_buckets
.p2align 2, 0x0
num_buckets:
.long 0 # 0x0
.size num_buckets, 4
.type PDH_threads,@object # @PDH_threads
.globl PDH_threads
.p2align 2, 0x0
PDH_threads:
.long 0 # 0x0
.size PDH_threads, 4
.type histogram,@object # @histogram
.globl histogram
.p2align 3, 0x0
histogram:
.quad 0
.size histogram, 8
.type atom_list,@object # @atom_list
.globl atom_list
.p2align 3, 0x0
atom_list:
.quad 0
.size atom_list, 8
.type Idunno,@object # @Idunno
.globl Idunno
.p2align 2, 0x0
Idunno:
.zero 8
.size Idunno, 8
.type startTime,@object # @startTime
.globl startTime
.p2align 3, 0x0
startTime:
.zero 16
.size startTime, 16
.type endTime,@object # @endTime
.globl endTime
.p2align 3, 0x0
endTime:
.zero 16
.size endTime, 16
.type _Z10PDH_on_gpuPdS_S_P10hist_entryidi,@object # @_Z10PDH_on_gpuPdS_S_P10hist_entryidi
.section .rodata,"a",@progbits
.globl _Z10PDH_on_gpuPdS_S_P10hist_entryidi
.p2align 3, 0x0
_Z10PDH_on_gpuPdS_S_P10hist_entryidi:
.quad _Z25__device_stub__PDH_on_gpuPdS_S_P10hist_entryidi
.size _Z10PDH_on_gpuPdS_S_P10hist_entryidi, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Running time: %ld.%06ld\n"
.size .L.str, 25
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "\n%02d: "
.size .L.str.1, 8
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "%15lld "
.size .L.str.2, 8
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "\n T:%lld \n"
.size .L.str.3, 11
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "| "
.size .L.str.4, 3
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Error: %s\n"
.size .L.str.5, 11
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "******** Total Running Time of Kernel = %.5f sec *******\n"
.size .L.str.8, 58
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z10PDH_on_gpuPdS_S_P10hist_entryidi"
.size .L__unnamed_1, 37
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Number of threads must be greater or equal to 32."
.size .Lstr, 50
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "Usage: ./SDH {# Atoms} {# Buckets} {# Threads}"
.size .Lstr.1, 47
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__PDH_on_gpuPdS_S_P10hist_entryidi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym Idunno
.addrsig_sym endTime
.addrsig_sym _Z10PDH_on_gpuPdS_S_P10hist_entryidi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void ComputeCubes2Kernel( float *pointsCoordinates, float *vertexData, int quadOffset, float cubeSide, float *cubeOperation, float *cubeTexCoordinates, int *activityFlag, float textureWidth, int maxCells )
{
int threadId = blockDim.x*blockIdx.y*gridDim.x //rows preceeding current row in grid
+ blockDim.x*blockIdx.x //blocks preceeding current block
+ threadIdx.x;
if(threadId < maxCells * 6)
{
int cellId = threadId / 6;
float fCellId = (float)cellId;
int sideId = threadId % 6;
float x = pointsCoordinates[cellId * 3];
float y = pointsCoordinates[cellId * 3 + 1];
float z = pointsCoordinates[cellId * 3 + 2];
float halfSide = (activityFlag[cellId] == 1) * 0.50f * cubeSide;
int textureOffset = quadOffset + maxCells * 4 * 6 * 3;
float textureAbsLength = (float)maxCells * textureWidth;
vertexData[quadOffset + cellId * 72 + 12*sideId] = x + operationMaskConstant[12*sideId] * halfSide;
vertexData[quadOffset + cellId * 72 + 12*sideId + 1] = y + operationMaskConstant[12*sideId + 1] * halfSide;
vertexData[quadOffset + cellId * 72 + 12*sideId + 2] = z + operationMaskConstant[12*sideId + 2] * halfSide;
vertexData[quadOffset + cellId * 72 + 12*sideId + 3] = x + operationMaskConstant[12*sideId + 3] * halfSide;
vertexData[quadOffset + cellId * 72 + 12*sideId + 4] = y + operationMaskConstant[12*sideId + 4] * halfSide;
vertexData[quadOffset + cellId * 72 + 12*sideId + 5] = z + operationMaskConstant[12*sideId + 5] * halfSide;
vertexData[quadOffset + cellId * 72 + 12*sideId + 6] = x + operationMaskConstant[12*sideId + 6] * halfSide;
vertexData[quadOffset + cellId * 72 + 12*sideId + 7] = y + operationMaskConstant[12*sideId + 7] * halfSide;
vertexData[quadOffset + cellId * 72 + 12*sideId + 8] = z + operationMaskConstant[12*sideId + 8] * halfSide;
vertexData[quadOffset + cellId * 72 + 12*sideId + 9] = x + operationMaskConstant[12*sideId + 9] * halfSide;
vertexData[quadOffset + cellId * 72 + 12*sideId + 10] = y + operationMaskConstant[12*sideId + 10] * halfSide;
vertexData[quadOffset + cellId * 72 + 12*sideId + 11] = z + operationMaskConstant[12*sideId + 11] * halfSide;
vertexData[textureOffset + cellId * 48 + 8 * sideId] = ((fCellId + cubeTexCoordinatesConstant[sideId * 8])* textureWidth) / textureAbsLength;
vertexData[textureOffset + cellId * 48 + 8 * sideId + 1] = cubeTexCoordinatesConstant[sideId * 8 + 1];
vertexData[textureOffset + cellId * 48 + 8 * sideId + 2] = ((fCellId + cubeTexCoordinatesConstant[sideId * 8 + 2]) * textureWidth) / textureAbsLength;
vertexData[textureOffset + cellId * 48 + 8 * sideId + 3] = cubeTexCoordinatesConstant[sideId * 8 + 3];
vertexData[textureOffset + cellId * 48 + 8 * sideId + 4] = ((fCellId + cubeTexCoordinatesConstant[sideId * 8 + 4]) * textureWidth) / textureAbsLength;
vertexData[textureOffset + cellId * 48 + 8 * sideId + 5] = cubeTexCoordinatesConstant[sideId * 8 + 5];
vertexData[textureOffset + cellId * 48 + 8 * sideId + 6] = ((fCellId + cubeTexCoordinatesConstant[sideId * 8 + 6]) * textureWidth) / textureAbsLength;
vertexData[textureOffset + cellId * 48 + 8 * sideId + 7] = cubeTexCoordinatesConstant[sideId * 8 + 7];
/*
vertexData[quadOffset + cellId * 72 + 12*sideId] = x + cubeOperation[12*sideId] * halfSide;
vertexData[quadOffset + cellId * 72 + 12*sideId + 1] = y + cubeOperation[12*sideId + 1] * halfSide;
vertexData[quadOffset + cellId * 72 + 12*sideId + 2] = z + cubeOperation[12*sideId + 2] * halfSide;
vertexData[quadOffset + cellId * 72 + 12*sideId + 3] = x + cubeOperation[12*sideId + 3] * halfSide;
vertexData[quadOffset + cellId * 72 + 12*sideId + 4] = y + cubeOperation[12*sideId + 4] * halfSide;
vertexData[quadOffset + cellId * 72 + 12*sideId + 5] = z + cubeOperation[12*sideId + 5] * halfSide;
vertexData[quadOffset + cellId * 72 + 12*sideId + 6] = x + cubeOperation[12*sideId + 6] * halfSide;
vertexData[quadOffset + cellId * 72 + 12*sideId + 7] = y + cubeOperation[12*sideId + 7] * halfSide;
vertexData[quadOffset + cellId * 72 + 12*sideId + 8] = z + cubeOperation[12*sideId + 8] * halfSide;
vertexData[quadOffset + cellId * 72 + 12*sideId + 9] = x + cubeOperation[12*sideId + 9] * halfSide;
vertexData[quadOffset + cellId * 72 + 12*sideId + 10] = y + cubeOperation[12*sideId + 10] * halfSide;
vertexData[quadOffset + cellId * 72 + 12*sideId + 11] = z + cubeOperation[12*sideId + 11] * halfSide;
vertexData[textureOffset + cellId * 48 + 8 * sideId] = ((fCellId + cubeTexCoordinates[sideId * 8])* textureWidth) / textureAbsLength;
vertexData[textureOffset + cellId * 48 + 8 * sideId + 1] = cubeTexCoordinates[sideId * 8 + 1];
vertexData[textureOffset + cellId * 48 + 8 * sideId + 2] = ((fCellId + cubeTexCoordinates[sideId * 8 + 2]) * textureWidth) / textureAbsLength;
vertexData[textureOffset + cellId * 48 + 8 * sideId + 3] = cubeTexCoordinates[sideId * 8 + 3];
vertexData[textureOffset + cellId * 48 + 8 * sideId + 4] = ((fCellId + cubeTexCoordinates[sideId * 8 + 4]) * textureWidth) / textureAbsLength;
vertexData[textureOffset + cellId * 48 + 8 * sideId + 5] = cubeTexCoordinates[sideId * 8 + 5];
vertexData[textureOffset + cellId * 48 + 8 * sideId + 6] = ((fCellId + cubeTexCoordinates[sideId * 8 + 6]) * textureWidth) / textureAbsLength;
vertexData[textureOffset + cellId * 48 + 8 * sideId + 7] = cubeTexCoordinates[sideId * 8 + 7];
*/
}
} | code for sm_80
Function : _Z19ComputeCubes2KernelPfS_ifS_S_Pifi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e220000002600 */
/*0020*/ ULDC UR4, c[0x0][0x194] ; /* 0x0000650000047ab9 */
/* 0x000fe40000000800 */
/*0030*/ UIMAD UR4, UR4, 0x6, URZ ; /* 0x00000006040478a4 */
/* 0x000fe2000f8e023f */
/*0040*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e280000002500 */
/*0050*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0060*/ IMAD R0, R0, c[0x0][0xc], R3 ; /* 0x0000030000007a24 */
/* 0x001fc800078e0203 */
/*0070*/ IMAD R3, R0, c[0x0][0x0], R5 ; /* 0x0000000000037a24 */
/* 0x002fca00078e0205 */
/*0080*/ ISETP.GE.AND P0, PT, R3, UR4, PT ; /* 0x0000000403007c0c */
/* 0x000fda000bf06270 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ IMAD.HI R18, R3, 0x2aaaaaab, RZ ; /* 0x2aaaaaab03127827 */
/* 0x000fe200078e02ff */
/*00b0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*00c0*/ IMAD.MOV.U32 R14, RZ, RZ, 0x4 ; /* 0x00000004ff0e7424 */
/* 0x000fe200078e00ff */
/*00d0*/ LEA.HI R18, R18, R18, RZ, 0x1 ; /* 0x0000001212127211 */
/* 0x000fca00078f08ff */
/*00e0*/ IMAD.WIDE R6, R18, R14, c[0x0][0x188] ; /* 0x0000620012067625 */
/* 0x000fca00078e020e */
/*00f0*/ LDG.E R15, [R6.64] ; /* 0x00000004060f7981 */
/* 0x0000a2000c1e1900 */
/*0100*/ IMAD R23, R18, 0x3, RZ ; /* 0x0000000312177824 */
/* 0x000fc800078e02ff */
/*0110*/ IMAD.WIDE R22, R23, R14, c[0x0][0x160] ; /* 0x0000580017167625 */
/* 0x000fca00078e020e */
/*0120*/ LDG.E R20, [R22.64+0x4] ; /* 0x0000040416147981 */
/* 0x0002e8000c1e1900 */
/*0130*/ LDG.E R19, [R22.64] ; /* 0x0000000416137981 */
/* 0x000328000c1e1900 */
/*0140*/ LDG.E R21, [R22.64+0x8] ; /* 0x0000080416157981 */
/* 0x000362000c1e1900 */
/*0150*/ IMAD R17, R18, -0x6, R3 ; /* 0xfffffffa12117824 */
/* 0x000fc800078e0203 */
/*0160*/ IMAD R25, R17, 0xc, RZ ; /* 0x0000000c11197824 */
/* 0x000fca00078e02ff */
/*0170*/ SHF.L.U32 R26, R25, 0x2, RZ ; /* 0x00000002191a7819 */
/* 0x000fc800000006ff */
/*0180*/ LDC.64 R2, c[0x3][R26] ; /* 0x00c000001a027b82 */
/* 0x000ee20000000a00 */
/*0190*/ IMAD.SHL.U32 R17, R17, 0x8, RZ ; /* 0x0000000811117824 */
/* 0x000fc800078e00ff */
/*01a0*/ IMAD R0, R17, R14, c[0x2][0x0] ; /* 0x0080000011007624 */
/* 0x000fc600078e020e */
/*01b0*/ LDC.64 R4, c[0x3][R26+0x8] ; /* 0x00c002001a047b82 */
/* 0x000f300000000a00 */
/*01c0*/ LDC.64 R6, c[0x3][R26+0x18] ; /* 0x00c006001a067b82 */
/* 0x001e300000000a00 */
/*01d0*/ LDC.64 R8, c[0x3][R26+0x20] ; /* 0x00c008001a087b82 */
/* 0x000e300000000a00 */
/*01e0*/ LDC R22, c[0x3][R0] ; /* 0x00c0000000167b82 */
/* 0x002e700000000800 */
/*01f0*/ LDC.64 R10, c[0x3][R26+0x10] ; /* 0x00c004001a0a7b82 */
/* 0x000e300000000a00 */
/*0200*/ LDC.64 R12, c[0x3][R26+0x28] ; /* 0x00c00a001a0c7b82 */
/* 0x000e220000000a00 */
/*0210*/ I2F R16, c[0x0][0x194] ; /* 0x0000650000107b06 */
/* 0x000e620000201400 */
/*0220*/ HFMA2.MMA R23, -RZ, RZ, 0, 4.291534423828125e-06 ; /* 0x00000048ff177435 */
/* 0x000fd400000001ff */
/*0230*/ IMAD R28, R18, R23, c[0x0][0x170] ; /* 0x00005c00121c7624 */
/* 0x000fe400078e0217 */
/*0240*/ FMUL R16, R16, c[0x0][0x190] ; /* 0x0000640010107a20 */
/* 0x002fc80000400000 */
/*0250*/ MUFU.RCP R23, R16 ; /* 0x0000001000177308 */
/* 0x000fe20000001000 */
/*0260*/ BSSY B0, 0x530 ; /* 0x000002c000007945 */
/* 0x000fe20003800000 */
/*0270*/ ISETP.NE.AND P0, PT, R15, 0x1, PT ; /* 0x000000010f00780c */
/* 0x004fc80003f05270 */
/*0280*/ FSEL R24, RZ, 0.5, P0 ; /* 0x3f000000ff187808 */
/* 0x000fca0000000000 */
/*0290*/ FMUL R24, R24, c[0x0][0x174] ; /* 0x00005d0018187a20 */
/* 0x000fc80000400000 */
/*02a0*/ FFMA R27, R24.reuse, R3, R20 ; /* 0x00000003181b7223 */
/* 0x048fe40000000014 */
/*02b0*/ I2F R3, R18 ; /* 0x0000001200037306 */
/* 0x000e620000201400 */
/*02c0*/ IMAD.IADD R15, R25, 0x1, R28 ; /* 0x00000001190f7824 */
/* 0x000fe400078e021c */
/*02d0*/ FFMA R5, R24, R5, R19 ; /* 0x0000000518057223 */
/* 0x010fe40000000013 */
/*02e0*/ IMAD.WIDE R14, R15, R14, c[0x0][0x168] ; /* 0x00005a000f0e7625 */
/* 0x000fc800078e020e */
/*02f0*/ FFMA R25, R24.reuse, R2, R19.reuse ; /* 0x0000000218197223 */
/* 0x140fe40000000013 */
/*0300*/ FFMA R6, R24.reuse, R6, R19.reuse ; /* 0x0000000618067223 */
/* 0x141fe40000000013 */
/*0310*/ FFMA R2, R24.reuse, R7, R20 ; /* 0x0000000718027223 */
/* 0x040fe40000000014 */
/*0320*/ FFMA R9, R24.reuse, R9, R19 ; /* 0x0000000918097223 */
/* 0x040fe40000000013 */
/*0330*/ FADD R22, R3, R22 ; /* 0x0000001603167221 */
/* 0x002fe40000000000 */
/*0340*/ FFMA R29, R24, R4, R21 ; /* 0x00000004181d7223 */
/* 0x020fc40000000015 */
/*0350*/ FFMA R8, R24.reuse, R8, R21.reuse ; /* 0x0000000818087223 */
/* 0x140fe40000000015 */
/*0360*/ FFMA R7, R24.reuse, R10, R20.reuse ; /* 0x0000000a18077223 */
/* 0x140fe40000000014 */
/*0370*/ FFMA R11, R24.reuse, R11, R21.reuse ; /* 0x0000000b180b7223 */
/* 0x140fe40000000015 */
/*0380*/ FFMA R19, R24.reuse, R12, R20 ; /* 0x0000000c18137223 */
/* 0x040fe40000000014 */
/*0390*/ FFMA R13, R24, R13, R21 ; /* 0x0000000d180d7223 */
/* 0x000fe20000000015 */
/*03a0*/ STG.E [R14.64+0xc], R5 ; /* 0x00000c050e007986 */
/* 0x0001e8000c101904 */
/*03b0*/ STG.E [R14.64], R25 ; /* 0x000000190e007986 */
/* 0x000fe8000c101904 */
/*03c0*/ STG.E [R14.64+0x4], R27 ; /* 0x0000041b0e007986 */
/* 0x000fe2000c101904 */
/*03d0*/ FMUL R5, R22, c[0x0][0x190] ; /* 0x0000640016057a20 */
/* 0x001fc60000400000 */
/*03e0*/ STG.E [R14.64+0x8], R29 ; /* 0x0000081d0e007986 */
/* 0x000fe8000c101904 */
/*03f0*/ STG.E [R14.64+0x18], R6 ; /* 0x000018060e007986 */
/* 0x000fe2000c101904 */
/*0400*/ FCHK P0, R5, R16 ; /* 0x0000001005007302 */
/* 0x000e260000000000 */
/*0410*/ STG.E [R14.64+0x20], R8 ; /* 0x000020080e007986 */
/* 0x000fe8000c101904 */
/*0420*/ STG.E [R14.64+0x24], R9 ; /* 0x000024090e007986 */
/* 0x000fe8000c101904 */
/*0430*/ STG.E [R14.64+0x10], R7 ; /* 0x000010070e007986 */
/* 0x000fe8000c101904 */
/*0440*/ STG.E [R14.64+0x14], R11 ; /* 0x0000140b0e007986 */
/* 0x000fe8000c101904 */
/*0450*/ STG.E [R14.64+0x28], R19 ; /* 0x000028130e007986 */
/* 0x000fe8000c101904 */
/*0460*/ STG.E [R14.64+0x2c], R13 ; /* 0x00002c0d0e007986 */
/* 0x000fe8000c101904 */
/*0470*/ STG.E [R14.64+0x1c], R2 ; /* 0x00001c020e007986 */
/* 0x0003e4000c101904 */
/*0480*/ FFMA R2, -R16, R23, 1 ; /* 0x3f80000010027423 */
/* 0x002fc80000000117 */
/*0490*/ FFMA R2, R23, R2, R23 ; /* 0x0000000217027223 */
/* 0x000fc80000000017 */
/*04a0*/ FFMA R21, R5, R2, RZ ; /* 0x0000000205157223 */
/* 0x000fc800000000ff */
/*04b0*/ FFMA R4, -R16, R21, R5 ; /* 0x0000001510047223 */
/* 0x000fc80000000105 */
/*04c0*/ FFMA R21, R2, R4, R21 ; /* 0x0000000402157223 */
/* 0x000fe20000000015 */
/*04d0*/ @!P0 BRA 0x520 ; /* 0x0000004000008947 */
/* 0x001fea0003800000 */
/*04e0*/ MOV R10, R5 ; /* 0x00000005000a7202 */
/* 0x000fe40000000f00 */
/*04f0*/ MOV R2, 0x510 ; /* 0x0000051000027802 */
/* 0x000fe40000000f00 */
/*0500*/ CALL.REL.NOINC 0x990 ; /* 0x0000048000007944 */
/* 0x000fea0003c00000 */
/*0510*/ IMAD.MOV.U32 R21, RZ, RZ, R9 ; /* 0x000000ffff157224 */
/* 0x000fe400078e0009 */
/*0520*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0530*/ LDC R2, c[0x3][R0+0x8] ; /* 0x00c0020000027b82 */
/* 0x000e220000000800 */
/*0540*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.86102294921875e-06 ; /* 0x00000030ff057435 */
/* 0x000fe200000001ff */
/*0550*/ MUFU.RCP R11, R16 ; /* 0x00000010000b7308 */
/* 0x000e620000001000 */
/*0560*/ MOV R9, 0x4 ; /* 0x0000000400097802 */
/* 0x000fe20000000f00 */
/*0570*/ BSSY B0, 0x6e0 ; /* 0x0000016000007945 */
/* 0x000fe80003800000 */
/*0580*/ LDC R7, c[0x3][R0+0x4] ; /* 0x00c0010000077b82 */
/* 0x000ea60000000800 */
/*0590*/ IMAD R18, R18, R5, c[0x0][0x170] ; /* 0x00005c0012127624 */
/* 0x000fc400078e0205 */
/*05a0*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x194] ; /* 0x00006500ff057624 */
/* 0x000fc600078e00ff */
/*05b0*/ IADD3 R18, R17, R18, RZ ; /* 0x0000001211127210 */
/* 0x000fe20007ffe0ff */
/*05c0*/ FFMA R6, -R16, R11, 1 ; /* 0x3f80000010067423 */
/* 0x002fc8000000010b */
/*05d0*/ IMAD R4, R5, 0x48, R18 ; /* 0x0000004805047824 */
/* 0x000fe400078e0212 */
/*05e0*/ FFMA R6, R11, R6, R11 ; /* 0x000000060b067223 */
/* 0x000fe4000000000b */
/*05f0*/ IMAD.WIDE R4, R4, R9, c[0x0][0x168] ; /* 0x00005a0004047625 */
/* 0x000fca00078e0209 */
/*0600*/ STG.E [R4.64], R21 ; /* 0x0000001504007986 */
/* 0x0003e2000c101904 */
/*0610*/ FADD R2, R3, R2 ; /* 0x0000000203027221 */
/* 0x001fc80000000000 */
/*0620*/ FMUL R9, R2, c[0x0][0x190] ; /* 0x0000640002097a20 */
/* 0x000fe20000400000 */
/*0630*/ STG.E [R4.64+0x4], R7 ; /* 0x0000040704007986 */
/* 0x0043e6000c101904 */
/*0640*/ FCHK P0, R9, R16 ; /* 0x0000001009007302 */
/* 0x000e220000000000 */
/*0650*/ FFMA R2, R6, R9, RZ ; /* 0x0000000906027223 */
/* 0x000fc800000000ff */
/*0660*/ FFMA R11, -R16, R2, R9 ; /* 0x00000002100b7223 */
/* 0x000fc80000000109 */
/*0670*/ FFMA R11, R6, R11, R2 ; /* 0x0000000b060b7223 */
/* 0x000fe20000000002 */
/*0680*/ @!P0 BRA 0x6d0 ; /* 0x0000004000008947 */
/* 0x001fea0003800000 */
/*0690*/ MOV R10, R9 ; /* 0x00000009000a7202 */
/* 0x002fe40000000f00 */
/*06a0*/ MOV R2, 0x6c0 ; /* 0x000006c000027802 */
/* 0x000fe40000000f00 */
/*06b0*/ CALL.REL.NOINC 0x990 ; /* 0x000002d000007944 */
/* 0x000fea0003c00000 */
/*06c0*/ IMAD.MOV.U32 R11, RZ, RZ, R9 ; /* 0x000000ffff0b7224 */
/* 0x000fe400078e0009 */
/*06d0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x002fea0003800000 */
/*06e0*/ LDC R2, c[0x3][R0+0x10] ; /* 0x00c0040000027b82 */
/* 0x000e220000000800 */
/*06f0*/ MUFU.RCP R13, R16 ; /* 0x00000010000d7308 */
/* 0x000e620000001000 */
/*0700*/ STG.E [R4.64+0x8], R11 ; /* 0x0000080b04007986 */
/* 0x0005e2000c101904 */
/*0710*/ BSSY B0, 0x820 ; /* 0x0000010000007945 */
/* 0x000fea0003800000 */
/*0720*/ LDC R7, c[0x3][R0+0xc] ; /* 0x00c0030000077b82 */
/* 0x000ee20000000800 */
/*0730*/ FFMA R6, -R16, R13, 1 ; /* 0x3f80000010067423 */
/* 0x002fc8000000010d */
/*0740*/ FFMA R6, R13, R6, R13 ; /* 0x000000060d067223 */
/* 0x000fe4000000000d */
/*0750*/ FADD R2, R3, R2 ; /* 0x0000000203027221 */
/* 0x001fc80000000000 */
/*0760*/ FMUL R9, R2, c[0x0][0x190] ; /* 0x0000640002097a20 */
/* 0x000fe20000400000 */
/*0770*/ STG.E [R4.64+0xc], R7 ; /* 0x00000c0704007986 */
/* 0x0085e6000c101904 */
/*0780*/ FCHK P0, R9, R16 ; /* 0x0000001009007302 */
/* 0x000e220000000000 */
/*0790*/ FFMA R2, R6, R9, RZ ; /* 0x0000000906027223 */
/* 0x000fc800000000ff */
/*07a0*/ FFMA R13, -R16, R2, R9 ; /* 0x00000002100d7223 */
/* 0x000fc80000000109 */
/*07b0*/ FFMA R13, R6, R13, R2 ; /* 0x0000000d060d7223 */
/* 0x000fe20000000002 */
/*07c0*/ @!P0 BRA 0x810 ; /* 0x0000004000008947 */
/* 0x001fea0003800000 */
/*07d0*/ MOV R10, R9 ; /* 0x00000009000a7202 */
/* 0x004fe40000000f00 */
/*07e0*/ MOV R2, 0x800 ; /* 0x0000080000027802 */
/* 0x000fe40000000f00 */
/*07f0*/ CALL.REL.NOINC 0x990 ; /* 0x0000019000007944 */
/* 0x000fea0003c00000 */
/*0800*/ MOV R13, R9 ; /* 0x00000009000d7202 */
/* 0x000fe40000000f00 */
/*0810*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x004fea0003800000 */
/*0820*/ LDC R2, c[0x3][R0+0x18] ; /* 0x00c0060000027b82 */
/* 0x000e220000000800 */
/*0830*/ MUFU.RCP R9, R16 ; /* 0x0000001000097308 */
/* 0x000e620000001000 */
/*0840*/ STG.E [R4.64+0x10], R13 ; /* 0x0000100d04007986 */
/* 0x0005e2000c101904 */
/*0850*/ BSSY B0, 0x950 ; /* 0x000000f000007945 */
/* 0x000fea0003800000 */
/*0860*/ LDC R7, c[0x3][R0+0x14] ; /* 0x00c0050000077b82 */
/* 0x000ee20000000800 */
/*0870*/ FFMA R6, -R16, R9, 1 ; /* 0x3f80000010067423 */
/* 0x002fc80000000109 */
/*0880*/ FFMA R6, R9, R6, R9 ; /* 0x0000000609067223 */
/* 0x000fe40000000009 */
/*0890*/ FADD R2, R3, R2 ; /* 0x0000000203027221 */
/* 0x001fc80000000000 */
/*08a0*/ FMUL R3, R2, c[0x0][0x190] ; /* 0x0000640002037a20 */
/* 0x000fe20000400000 */
/*08b0*/ STG.E [R4.64+0x14], R7 ; /* 0x0000140704007986 */
/* 0x0085e6000c101904 */
/*08c0*/ FCHK P0, R3, R16 ; /* 0x0000001003007302 */
/* 0x000e220000000000 */
/*08d0*/ FFMA R2, R6, R3, RZ ; /* 0x0000000306027223 */
/* 0x000fc800000000ff */
/*08e0*/ FFMA R9, -R16, R2, R3 ; /* 0x0000000210097223 */
/* 0x000fc80000000103 */
/*08f0*/ FFMA R9, R6, R9, R2 ; /* 0x0000000906097223 */
/* 0x000fe20000000002 */
/*0900*/ @!P0 BRA 0x940 ; /* 0x0000003000008947 */
/* 0x001fea0003800000 */
/*0910*/ IMAD.MOV.U32 R10, RZ, RZ, R3 ; /* 0x000000ffff0a7224 */
/* 0x004fe200078e0003 */
/*0920*/ MOV R2, 0x940 ; /* 0x0000094000027802 */
/* 0x000fe40000000f00 */
/*0930*/ CALL.REL.NOINC 0x990 ; /* 0x0000005000007944 */
/* 0x000fea0003c00000 */
/*0940*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x004fea0003800000 */
/*0950*/ LDC R3, c[0x3][R0+0x1c] ; /* 0x00c0070000037b82 */
/* 0x000e220000000800 */
/*0960*/ STG.E [R4.64+0x18], R9 ; /* 0x0000180904007986 */
/* 0x000fe8000c101904 */
/*0970*/ STG.E [R4.64+0x1c], R3 ; /* 0x00001c0304007986 */
/* 0x001fe2000c101904 */
/*0980*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0990*/ SHF.R.U32.HI R8, RZ, 0x17, R16 ; /* 0x00000017ff087819 */
/* 0x000fe20000011610 */
/*09a0*/ BSSY B1, 0xff0 ; /* 0x0000064000017945 */
/* 0x000fe20003800000 */
/*09b0*/ SHF.R.U32.HI R6, RZ, 0x17, R10 ; /* 0x00000017ff067819 */
/* 0x000fc4000001160a */
/*09c0*/ LOP3.LUT R8, R8, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff08087812 */
/* 0x000fe400078ec0ff */
/*09d0*/ LOP3.LUT R12, R6, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff060c7812 */
/* 0x000fe400078ec0ff */
/*09e0*/ IADD3 R13, R8, -0x1, RZ ; /* 0xffffffff080d7810 */
/* 0x000fe40007ffe0ff */
/*09f0*/ IADD3 R11, R12, -0x1, RZ ; /* 0xffffffff0c0b7810 */
/* 0x000fe40007ffe0ff */
/*0a00*/ ISETP.GT.U32.AND P0, PT, R13, 0xfd, PT ; /* 0x000000fd0d00780c */
/* 0x000fe40003f04070 */
/*0a10*/ MOV R6, R10 ; /* 0x0000000a00067202 */
/* 0x000fc40000000f00 */
/*0a20*/ ISETP.GT.U32.OR P0, PT, R11, 0xfd, P0 ; /* 0x000000fd0b00780c */
/* 0x000fe40000704470 */
/*0a30*/ MOV R9, R16 ; /* 0x0000001000097202 */
/* 0x000fd60000000f00 */
/*0a40*/ @!P0 IMAD.MOV.U32 R7, RZ, RZ, RZ ; /* 0x000000ffff078224 */
/* 0x000fe200078e00ff */
/*0a50*/ @!P0 BRA 0xbd0 ; /* 0x0000017000008947 */
/* 0x000fea0003800000 */
/*0a60*/ FSETP.GTU.FTZ.AND P0, PT, |R10|, +INF , PT ; /* 0x7f8000000a00780b */
/* 0x000fe40003f1c200 */
/*0a70*/ FSETP.GTU.FTZ.AND P1, PT, |R16|, +INF , PT ; /* 0x7f8000001000780b */
/* 0x000fc80003f3c200 */
/*0a80*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000703570 */
/*0a90*/ @P0 BRA 0xfd0 ; /* 0x0000053000000947 */
/* 0x000fea0003800000 */
/*0aa0*/ LOP3.LUT P0, RZ, R9, 0x7fffffff, R6, 0xc8, !PT ; /* 0x7fffffff09ff7812 */
/* 0x000fda000780c806 */
/*0ab0*/ @!P0 BRA 0xfb0 ; /* 0x000004f000008947 */
/* 0x000fea0003800000 */
/*0ac0*/ FSETP.NEU.FTZ.AND P2, PT, |R10|, +INF , PT ; /* 0x7f8000000a00780b */
/* 0x000fe40003f5d200 */
/*0ad0*/ FSETP.NEU.FTZ.AND P1, PT, |R16|, +INF , PT ; /* 0x7f8000001000780b */
/* 0x000fe40003f3d200 */
/*0ae0*/ FSETP.NEU.FTZ.AND P0, PT, |R10|, +INF , PT ; /* 0x7f8000000a00780b */
/* 0x000fd60003f1d200 */
/*0af0*/ @!P1 BRA !P2, 0xfb0 ; /* 0x000004b000009947 */
/* 0x000fea0005000000 */
/*0b00*/ LOP3.LUT P2, RZ, R6, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff06ff7812 */
/* 0x000fc8000784c0ff */
/*0b10*/ PLOP3.LUT P1, PT, P1, P2, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000f24572 */
/*0b20*/ @P1 BRA 0xf90 ; /* 0x0000046000001947 */
/* 0x000fea0003800000 */
/*0b30*/ LOP3.LUT P1, RZ, R9, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff09ff7812 */
/* 0x000fc8000782c0ff */
/*0b40*/ PLOP3.LUT P0, PT, P0, P1, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000702572 */
/*0b50*/ @P0 BRA 0xf60 ; /* 0x0000040000000947 */
/* 0x000fea0003800000 */
/*0b60*/ ISETP.GE.AND P0, PT, R11, RZ, PT ; /* 0x000000ff0b00720c */
/* 0x000fe40003f06270 */
/*0b70*/ ISETP.GE.AND P1, PT, R13, RZ, PT ; /* 0x000000ff0d00720c */
/* 0x000fd60003f26270 */
/*0b80*/ @P0 MOV R7, RZ ; /* 0x000000ff00070202 */
/* 0x000fe20000000f00 */
/*0b90*/ @!P0 FFMA R6, R10, 1.84467440737095516160e+19, RZ ; /* 0x5f8000000a068823 */
/* 0x000fe200000000ff */
/*0ba0*/ @!P0 MOV R7, 0xffffffc0 ; /* 0xffffffc000078802 */
/* 0x000fe20000000f00 */
/*0bb0*/ @!P1 FFMA R9, R16, 1.84467440737095516160e+19, RZ ; /* 0x5f80000010099823 */
/* 0x000fc600000000ff */
/*0bc0*/ @!P1 IADD3 R7, R7, 0x40, RZ ; /* 0x0000004007079810 */
/* 0x000fe40007ffe0ff */
/*0bd0*/ LEA R10, R8, 0xc0800000, 0x17 ; /* 0xc0800000080a7811 */
/* 0x000fe200078eb8ff */
/*0be0*/ BSSY B2, 0xf50 ; /* 0x0000036000027945 */
/* 0x000fe80003800000 */
/*0bf0*/ IMAD.IADD R10, R9, 0x1, -R10 ; /* 0x00000001090a7824 */
/* 0x000fe200078e0a0a */
/*0c00*/ IADD3 R9, R12, -0x7f, RZ ; /* 0xffffff810c097810 */
/* 0x000fc60007ffe0ff */
/*0c10*/ MUFU.RCP R11, R10 ; /* 0x0000000a000b7308 */
/* 0x0000620000001000 */
/*0c20*/ FADD.FTZ R13, -R10, -RZ ; /* 0x800000ff0a0d7221 */
/* 0x000fe40000010100 */
/*0c30*/ IMAD R6, R9.reuse, -0x800000, R6 ; /* 0xff80000009067824 */
/* 0x040fe200078e0206 */
/*0c40*/ IADD3 R10, R9, 0x7f, -R8 ; /* 0x0000007f090a7810 */
/* 0x001fc80007ffe808 */
/*0c50*/ IADD3 R7, R10, R7, RZ ; /* 0x000000070a077210 */
/* 0x000fe20007ffe0ff */
/*0c60*/ FFMA R12, R11, R13, 1 ; /* 0x3f8000000b0c7423 */
/* 0x002fc8000000000d */
/*0c70*/ FFMA R15, R11, R12, R11 ; /* 0x0000000c0b0f7223 */
/* 0x000fc8000000000b */
/*0c80*/ FFMA R11, R6, R15, RZ ; /* 0x0000000f060b7223 */
/* 0x000fc800000000ff */
/*0c90*/ FFMA R12, R13, R11, R6 ; /* 0x0000000b0d0c7223 */
/* 0x000fc80000000006 */
/*0ca0*/ FFMA R12, R15, R12, R11 ; /* 0x0000000c0f0c7223 */
/* 0x000fc8000000000b */
/*0cb0*/ FFMA R13, R13, R12, R6 ; /* 0x0000000c0d0d7223 */
/* 0x000fc80000000006 */
/*0cc0*/ FFMA R6, R15, R13, R12 ; /* 0x0000000d0f067223 */
/* 0x000fca000000000c */
/*0cd0*/ SHF.R.U32.HI R8, RZ, 0x17, R6 ; /* 0x00000017ff087819 */
/* 0x000fc80000011606 */
/*0ce0*/ LOP3.LUT R8, R8, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff08087812 */
/* 0x000fc800078ec0ff */
/*0cf0*/ IADD3 R11, R8, R7, RZ ; /* 0x00000007080b7210 */
/* 0x000fc80007ffe0ff */
/*0d00*/ IADD3 R8, R11, -0x1, RZ ; /* 0xffffffff0b087810 */
/* 0x000fc80007ffe0ff */
/*0d10*/ ISETP.GE.U32.AND P0, PT, R8, 0xfe, PT ; /* 0x000000fe0800780c */
/* 0x000fda0003f06070 */
/*0d20*/ @!P0 BRA 0xf30 ; /* 0x0000020000008947 */
/* 0x000fea0003800000 */
/*0d30*/ ISETP.GT.AND P0, PT, R11, 0xfe, PT ; /* 0x000000fe0b00780c */
/* 0x000fda0003f04270 */
/*0d40*/ @P0 BRA 0xf00 ; /* 0x000001b000000947 */
/* 0x000fea0003800000 */
/*0d50*/ ISETP.GE.AND P0, PT, R11, 0x1, PT ; /* 0x000000010b00780c */
/* 0x000fda0003f06270 */
/*0d60*/ @P0 BRA 0xf40 ; /* 0x000001d000000947 */
/* 0x000fea0003800000 */
/*0d70*/ ISETP.GE.AND P0, PT, R11, -0x18, PT ; /* 0xffffffe80b00780c */
/* 0x000fe40003f06270 */
/*0d80*/ LOP3.LUT R6, R6, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000006067812 */
/* 0x000fd600078ec0ff */
/*0d90*/ @!P0 BRA 0xf40 ; /* 0x000001a000008947 */
/* 0x000fea0003800000 */
/*0da0*/ FFMA.RZ R7, R15, R13.reuse, R12.reuse ; /* 0x0000000d0f077223 */
/* 0x180fe2000000c00c */
/*0db0*/ IADD3 R10, R11, 0x20, RZ ; /* 0x000000200b0a7810 */
/* 0x000fe20007ffe0ff */
/*0dc0*/ FFMA.RM R8, R15, R13.reuse, R12.reuse ; /* 0x0000000d0f087223 */
/* 0x180fe2000000400c */
/*0dd0*/ ISETP.NE.AND P2, PT, R11, RZ, PT ; /* 0x000000ff0b00720c */
/* 0x000fe40003f45270 */
/*0de0*/ LOP3.LUT R9, R7, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff07097812 */
/* 0x000fe200078ec0ff */
/*0df0*/ FFMA.RP R7, R15, R13, R12 ; /* 0x0000000d0f077223 */
/* 0x000fe2000000800c */
/*0e00*/ ISETP.NE.AND P1, PT, R11, RZ, PT ; /* 0x000000ff0b00720c */
/* 0x000fe20003f25270 */
/*0e10*/ IMAD.MOV R11, RZ, RZ, -R11 ; /* 0x000000ffff0b7224 */
/* 0x000fe200078e0a0b */
/*0e20*/ LOP3.LUT R9, R9, 0x800000, RZ, 0xfc, !PT ; /* 0x0080000009097812 */
/* 0x000fe400078efcff */
/*0e30*/ FSETP.NEU.FTZ.AND P0, PT, R7, R8, PT ; /* 0x000000080700720b */
/* 0x000fc40003f1d000 */
/*0e40*/ SHF.L.U32 R10, R9, R10, RZ ; /* 0x0000000a090a7219 */
/* 0x000fe400000006ff */
/*0e50*/ SEL R8, R11, RZ, P2 ; /* 0x000000ff0b087207 */
/* 0x000fe40001000000 */
/*0e60*/ ISETP.NE.AND P1, PT, R10, RZ, P1 ; /* 0x000000ff0a00720c */
/* 0x000fe40000f25270 */
/*0e70*/ SHF.R.U32.HI R8, RZ, R8, R9 ; /* 0x00000008ff087219 */
/* 0x000fe40000011609 */
/*0e80*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40000703570 */
/*0e90*/ SHF.R.U32.HI R10, RZ, 0x1, R8 ; /* 0x00000001ff0a7819 */
/* 0x000fc40000011608 */
/*0ea0*/ SEL R7, RZ, 0x1, !P0 ; /* 0x00000001ff077807 */
/* 0x000fc80004000000 */
/*0eb0*/ LOP3.LUT R7, R7, 0x1, R10, 0xf8, !PT ; /* 0x0000000107077812 */
/* 0x000fc800078ef80a */
/*0ec0*/ LOP3.LUT R7, R7, R8, RZ, 0xc0, !PT ; /* 0x0000000807077212 */
/* 0x000fc800078ec0ff */
/*0ed0*/ IADD3 R7, R10, R7, RZ ; /* 0x000000070a077210 */
/* 0x000fc80007ffe0ff */
/*0ee0*/ LOP3.LUT R6, R7, R6, RZ, 0xfc, !PT ; /* 0x0000000607067212 */
/* 0x000fe200078efcff */
/*0ef0*/ BRA 0xf40 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*0f00*/ LOP3.LUT R6, R6, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000006067812 */
/* 0x000fc800078ec0ff */
/*0f10*/ LOP3.LUT R6, R6, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000006067812 */
/* 0x000fe200078efcff */
/*0f20*/ BRA 0xf40 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0f30*/ LEA R6, R7, R6, 0x17 ; /* 0x0000000607067211 */
/* 0x000fe400078eb8ff */
/*0f40*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*0f50*/ BRA 0xfe0 ; /* 0x0000008000007947 */
/* 0x000fea0003800000 */
/*0f60*/ LOP3.LUT R6, R9, 0x80000000, R6, 0x48, !PT ; /* 0x8000000009067812 */
/* 0x000fc800078e4806 */
/*0f70*/ LOP3.LUT R6, R6, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000006067812 */
/* 0x000fe200078efcff */
/*0f80*/ BRA 0xfe0 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*0f90*/ LOP3.LUT R6, R9, 0x80000000, R6, 0x48, !PT ; /* 0x8000000009067812 */
/* 0x000fe200078e4806 */
/*0fa0*/ BRA 0xfe0 ; /* 0x0000003000007947 */
/* 0x000fea0003800000 */
/*0fb0*/ MUFU.RSQ R6, -QNAN ; /* 0xffc0000000067908 */
/* 0x000e220000001400 */
/*0fc0*/ BRA 0xfe0 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0fd0*/ FADD.FTZ R6, R10, R16 ; /* 0x000000100a067221 */
/* 0x000fe40000010000 */
/*0fe0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0ff0*/ HFMA2.MMA R7, -RZ, RZ, 0, 0 ; /* 0x00000000ff077435 */
/* 0x000fe200000001ff */
/*1000*/ IMAD.MOV.U32 R9, RZ, RZ, R6 ; /* 0x000000ffff097224 */
/* 0x001fe200078e0006 */
/*1010*/ MOV R6, R2 ; /* 0x0000000200067202 */
/* 0x000fc80000000f00 */
/*1020*/ RET.REL.NODEC R6 0x0 ; /* 0xffffefd006007950 */
/* 0x000fea0003c3ffff */
/*1030*/ BRA 0x1030; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*1040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*10a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*10b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*10c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*10d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*10e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*10f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void ComputeCubes2Kernel( float *pointsCoordinates, float *vertexData, int quadOffset, float cubeSide, float *cubeOperation, float *cubeTexCoordinates, int *activityFlag, float textureWidth, int maxCells )
{
int threadId = blockDim.x*blockIdx.y*gridDim.x //rows preceeding current row in grid
+ blockDim.x*blockIdx.x //blocks preceeding current block
+ threadIdx.x;
if(threadId < maxCells * 6)
{
int cellId = threadId / 6;
float fCellId = (float)cellId;
int sideId = threadId % 6;
float x = pointsCoordinates[cellId * 3];
float y = pointsCoordinates[cellId * 3 + 1];
float z = pointsCoordinates[cellId * 3 + 2];
float halfSide = (activityFlag[cellId] == 1) * 0.50f * cubeSide;
int textureOffset = quadOffset + maxCells * 4 * 6 * 3;
float textureAbsLength = (float)maxCells * textureWidth;
vertexData[quadOffset + cellId * 72 + 12*sideId] = x + operationMaskConstant[12*sideId] * halfSide;
vertexData[quadOffset + cellId * 72 + 12*sideId + 1] = y + operationMaskConstant[12*sideId + 1] * halfSide;
vertexData[quadOffset + cellId * 72 + 12*sideId + 2] = z + operationMaskConstant[12*sideId + 2] * halfSide;
vertexData[quadOffset + cellId * 72 + 12*sideId + 3] = x + operationMaskConstant[12*sideId + 3] * halfSide;
vertexData[quadOffset + cellId * 72 + 12*sideId + 4] = y + operationMaskConstant[12*sideId + 4] * halfSide;
vertexData[quadOffset + cellId * 72 + 12*sideId + 5] = z + operationMaskConstant[12*sideId + 5] * halfSide;
vertexData[quadOffset + cellId * 72 + 12*sideId + 6] = x + operationMaskConstant[12*sideId + 6] * halfSide;
vertexData[quadOffset + cellId * 72 + 12*sideId + 7] = y + operationMaskConstant[12*sideId + 7] * halfSide;
vertexData[quadOffset + cellId * 72 + 12*sideId + 8] = z + operationMaskConstant[12*sideId + 8] * halfSide;
vertexData[quadOffset + cellId * 72 + 12*sideId + 9] = x + operationMaskConstant[12*sideId + 9] * halfSide;
vertexData[quadOffset + cellId * 72 + 12*sideId + 10] = y + operationMaskConstant[12*sideId + 10] * halfSide;
vertexData[quadOffset + cellId * 72 + 12*sideId + 11] = z + operationMaskConstant[12*sideId + 11] * halfSide;
vertexData[textureOffset + cellId * 48 + 8 * sideId] = ((fCellId + cubeTexCoordinatesConstant[sideId * 8])* textureWidth) / textureAbsLength;
vertexData[textureOffset + cellId * 48 + 8 * sideId + 1] = cubeTexCoordinatesConstant[sideId * 8 + 1];
vertexData[textureOffset + cellId * 48 + 8 * sideId + 2] = ((fCellId + cubeTexCoordinatesConstant[sideId * 8 + 2]) * textureWidth) / textureAbsLength;
vertexData[textureOffset + cellId * 48 + 8 * sideId + 3] = cubeTexCoordinatesConstant[sideId * 8 + 3];
vertexData[textureOffset + cellId * 48 + 8 * sideId + 4] = ((fCellId + cubeTexCoordinatesConstant[sideId * 8 + 4]) * textureWidth) / textureAbsLength;
vertexData[textureOffset + cellId * 48 + 8 * sideId + 5] = cubeTexCoordinatesConstant[sideId * 8 + 5];
vertexData[textureOffset + cellId * 48 + 8 * sideId + 6] = ((fCellId + cubeTexCoordinatesConstant[sideId * 8 + 6]) * textureWidth) / textureAbsLength;
vertexData[textureOffset + cellId * 48 + 8 * sideId + 7] = cubeTexCoordinatesConstant[sideId * 8 + 7];
/*
vertexData[quadOffset + cellId * 72 + 12*sideId] = x + cubeOperation[12*sideId] * halfSide;
vertexData[quadOffset + cellId * 72 + 12*sideId + 1] = y + cubeOperation[12*sideId + 1] * halfSide;
vertexData[quadOffset + cellId * 72 + 12*sideId + 2] = z + cubeOperation[12*sideId + 2] * halfSide;
vertexData[quadOffset + cellId * 72 + 12*sideId + 3] = x + cubeOperation[12*sideId + 3] * halfSide;
vertexData[quadOffset + cellId * 72 + 12*sideId + 4] = y + cubeOperation[12*sideId + 4] * halfSide;
vertexData[quadOffset + cellId * 72 + 12*sideId + 5] = z + cubeOperation[12*sideId + 5] * halfSide;
vertexData[quadOffset + cellId * 72 + 12*sideId + 6] = x + cubeOperation[12*sideId + 6] * halfSide;
vertexData[quadOffset + cellId * 72 + 12*sideId + 7] = y + cubeOperation[12*sideId + 7] * halfSide;
vertexData[quadOffset + cellId * 72 + 12*sideId + 8] = z + cubeOperation[12*sideId + 8] * halfSide;
vertexData[quadOffset + cellId * 72 + 12*sideId + 9] = x + cubeOperation[12*sideId + 9] * halfSide;
vertexData[quadOffset + cellId * 72 + 12*sideId + 10] = y + cubeOperation[12*sideId + 10] * halfSide;
vertexData[quadOffset + cellId * 72 + 12*sideId + 11] = z + cubeOperation[12*sideId + 11] * halfSide;
vertexData[textureOffset + cellId * 48 + 8 * sideId] = ((fCellId + cubeTexCoordinates[sideId * 8])* textureWidth) / textureAbsLength;
vertexData[textureOffset + cellId * 48 + 8 * sideId + 1] = cubeTexCoordinates[sideId * 8 + 1];
vertexData[textureOffset + cellId * 48 + 8 * sideId + 2] = ((fCellId + cubeTexCoordinates[sideId * 8 + 2]) * textureWidth) / textureAbsLength;
vertexData[textureOffset + cellId * 48 + 8 * sideId + 3] = cubeTexCoordinates[sideId * 8 + 3];
vertexData[textureOffset + cellId * 48 + 8 * sideId + 4] = ((fCellId + cubeTexCoordinates[sideId * 8 + 4]) * textureWidth) / textureAbsLength;
vertexData[textureOffset + cellId * 48 + 8 * sideId + 5] = cubeTexCoordinates[sideId * 8 + 5];
vertexData[textureOffset + cellId * 48 + 8 * sideId + 6] = ((fCellId + cubeTexCoordinates[sideId * 8 + 6]) * textureWidth) / textureAbsLength;
vertexData[textureOffset + cellId * 48 + 8 * sideId + 7] = cubeTexCoordinates[sideId * 8 + 7];
*/
}
} | .file "tmpxft_000cccc1_00000000-6_ComputeCubes2Kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z51__device_stub__Z19ComputeCubes2KernelPfS_ifS_S_PifiPfS_ifS_S_Pifi
.type _Z51__device_stub__Z19ComputeCubes2KernelPfS_ifS_S_PifiPfS_ifS_S_Pifi, @function
_Z51__device_stub__Z19ComputeCubes2KernelPfS_ifS_S_PifiPfS_ifS_S_Pifi:
.LFB2051:
.cfi_startproc
endbr64
subq $216, %rsp
.cfi_def_cfa_offset 224
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
movl %edx, 44(%rsp)
movss %xmm0, 40(%rsp)
movq %rcx, 32(%rsp)
movq %r8, 24(%rsp)
movq %r9, 16(%rsp)
movss %xmm1, 12(%rsp)
movq %fs:40, %rax
movq %rax, 200(%rsp)
xorl %eax, %eax
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 44(%rsp), %rax
movq %rax, 144(%rsp)
leaq 40(%rsp), %rax
movq %rax, 152(%rsp)
leaq 32(%rsp), %rax
movq %rax, 160(%rsp)
leaq 24(%rsp), %rax
movq %rax, 168(%rsp)
leaq 16(%rsp), %rax
movq %rax, 176(%rsp)
leaq 12(%rsp), %rax
movq %rax, 184(%rsp)
leaq 224(%rsp), %rax
movq %rax, 192(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 200(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $216, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 232
pushq 72(%rsp)
.cfi_def_cfa_offset 240
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq _Z19ComputeCubes2KernelPfS_ifS_S_Pifi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 224
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z51__device_stub__Z19ComputeCubes2KernelPfS_ifS_S_PifiPfS_ifS_S_Pifi, .-_Z51__device_stub__Z19ComputeCubes2KernelPfS_ifS_S_PifiPfS_ifS_S_Pifi
.globl _Z19ComputeCubes2KernelPfS_ifS_S_Pifi
.type _Z19ComputeCubes2KernelPfS_ifS_S_Pifi, @function
_Z19ComputeCubes2KernelPfS_ifS_S_Pifi:
.LFB2052:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
call _Z51__device_stub__Z19ComputeCubes2KernelPfS_ifS_S_PifiPfS_ifS_S_Pifi
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z19ComputeCubes2KernelPfS_ifS_S_Pifi, .-_Z19ComputeCubes2KernelPfS_ifS_S_Pifi
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z19ComputeCubes2KernelPfS_ifS_S_Pifi"
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "operationMaskConstant"
.LC2:
.string "cubeTexCoordinatesConstant"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z19ComputeCubes2KernelPfS_ifS_S_Pifi(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $288, %r9d
movl $0, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _ZL21operationMaskConstant(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $192, %r9d
movl $0, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _ZL26cubeTexCoordinatesConstant(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL26cubeTexCoordinatesConstant
.comm _ZL26cubeTexCoordinatesConstant,192,32
.local _ZL21operationMaskConstant
.comm _ZL21operationMaskConstant,288,32
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void ComputeCubes2Kernel( float *pointsCoordinates, float *vertexData, int quadOffset, float cubeSide, float *cubeOperation, float *cubeTexCoordinates, int *activityFlag, float textureWidth, int maxCells )
{
int threadId = blockDim.x*blockIdx.y*gridDim.x //rows preceeding current row in grid
+ blockDim.x*blockIdx.x //blocks preceeding current block
+ threadIdx.x;
if(threadId < maxCells * 6)
{
int cellId = threadId / 6;
float fCellId = (float)cellId;
int sideId = threadId % 6;
float x = pointsCoordinates[cellId * 3];
float y = pointsCoordinates[cellId * 3 + 1];
float z = pointsCoordinates[cellId * 3 + 2];
float halfSide = (activityFlag[cellId] == 1) * 0.50f * cubeSide;
int textureOffset = quadOffset + maxCells * 4 * 6 * 3;
float textureAbsLength = (float)maxCells * textureWidth;
vertexData[quadOffset + cellId * 72 + 12*sideId] = x + operationMaskConstant[12*sideId] * halfSide;
vertexData[quadOffset + cellId * 72 + 12*sideId + 1] = y + operationMaskConstant[12*sideId + 1] * halfSide;
vertexData[quadOffset + cellId * 72 + 12*sideId + 2] = z + operationMaskConstant[12*sideId + 2] * halfSide;
vertexData[quadOffset + cellId * 72 + 12*sideId + 3] = x + operationMaskConstant[12*sideId + 3] * halfSide;
vertexData[quadOffset + cellId * 72 + 12*sideId + 4] = y + operationMaskConstant[12*sideId + 4] * halfSide;
vertexData[quadOffset + cellId * 72 + 12*sideId + 5] = z + operationMaskConstant[12*sideId + 5] * halfSide;
vertexData[quadOffset + cellId * 72 + 12*sideId + 6] = x + operationMaskConstant[12*sideId + 6] * halfSide;
vertexData[quadOffset + cellId * 72 + 12*sideId + 7] = y + operationMaskConstant[12*sideId + 7] * halfSide;
vertexData[quadOffset + cellId * 72 + 12*sideId + 8] = z + operationMaskConstant[12*sideId + 8] * halfSide;
vertexData[quadOffset + cellId * 72 + 12*sideId + 9] = x + operationMaskConstant[12*sideId + 9] * halfSide;
vertexData[quadOffset + cellId * 72 + 12*sideId + 10] = y + operationMaskConstant[12*sideId + 10] * halfSide;
vertexData[quadOffset + cellId * 72 + 12*sideId + 11] = z + operationMaskConstant[12*sideId + 11] * halfSide;
vertexData[textureOffset + cellId * 48 + 8 * sideId] = ((fCellId + cubeTexCoordinatesConstant[sideId * 8])* textureWidth) / textureAbsLength;
vertexData[textureOffset + cellId * 48 + 8 * sideId + 1] = cubeTexCoordinatesConstant[sideId * 8 + 1];
vertexData[textureOffset + cellId * 48 + 8 * sideId + 2] = ((fCellId + cubeTexCoordinatesConstant[sideId * 8 + 2]) * textureWidth) / textureAbsLength;
vertexData[textureOffset + cellId * 48 + 8 * sideId + 3] = cubeTexCoordinatesConstant[sideId * 8 + 3];
vertexData[textureOffset + cellId * 48 + 8 * sideId + 4] = ((fCellId + cubeTexCoordinatesConstant[sideId * 8 + 4]) * textureWidth) / textureAbsLength;
vertexData[textureOffset + cellId * 48 + 8 * sideId + 5] = cubeTexCoordinatesConstant[sideId * 8 + 5];
vertexData[textureOffset + cellId * 48 + 8 * sideId + 6] = ((fCellId + cubeTexCoordinatesConstant[sideId * 8 + 6]) * textureWidth) / textureAbsLength;
vertexData[textureOffset + cellId * 48 + 8 * sideId + 7] = cubeTexCoordinatesConstant[sideId * 8 + 7];
/*
vertexData[quadOffset + cellId * 72 + 12*sideId] = x + cubeOperation[12*sideId] * halfSide;
vertexData[quadOffset + cellId * 72 + 12*sideId + 1] = y + cubeOperation[12*sideId + 1] * halfSide;
vertexData[quadOffset + cellId * 72 + 12*sideId + 2] = z + cubeOperation[12*sideId + 2] * halfSide;
vertexData[quadOffset + cellId * 72 + 12*sideId + 3] = x + cubeOperation[12*sideId + 3] * halfSide;
vertexData[quadOffset + cellId * 72 + 12*sideId + 4] = y + cubeOperation[12*sideId + 4] * halfSide;
vertexData[quadOffset + cellId * 72 + 12*sideId + 5] = z + cubeOperation[12*sideId + 5] * halfSide;
vertexData[quadOffset + cellId * 72 + 12*sideId + 6] = x + cubeOperation[12*sideId + 6] * halfSide;
vertexData[quadOffset + cellId * 72 + 12*sideId + 7] = y + cubeOperation[12*sideId + 7] * halfSide;
vertexData[quadOffset + cellId * 72 + 12*sideId + 8] = z + cubeOperation[12*sideId + 8] * halfSide;
vertexData[quadOffset + cellId * 72 + 12*sideId + 9] = x + cubeOperation[12*sideId + 9] * halfSide;
vertexData[quadOffset + cellId * 72 + 12*sideId + 10] = y + cubeOperation[12*sideId + 10] * halfSide;
vertexData[quadOffset + cellId * 72 + 12*sideId + 11] = z + cubeOperation[12*sideId + 11] * halfSide;
vertexData[textureOffset + cellId * 48 + 8 * sideId] = ((fCellId + cubeTexCoordinates[sideId * 8])* textureWidth) / textureAbsLength;
vertexData[textureOffset + cellId * 48 + 8 * sideId + 1] = cubeTexCoordinates[sideId * 8 + 1];
vertexData[textureOffset + cellId * 48 + 8 * sideId + 2] = ((fCellId + cubeTexCoordinates[sideId * 8 + 2]) * textureWidth) / textureAbsLength;
vertexData[textureOffset + cellId * 48 + 8 * sideId + 3] = cubeTexCoordinates[sideId * 8 + 3];
vertexData[textureOffset + cellId * 48 + 8 * sideId + 4] = ((fCellId + cubeTexCoordinates[sideId * 8 + 4]) * textureWidth) / textureAbsLength;
vertexData[textureOffset + cellId * 48 + 8 * sideId + 5] = cubeTexCoordinates[sideId * 8 + 5];
vertexData[textureOffset + cellId * 48 + 8 * sideId + 6] = ((fCellId + cubeTexCoordinates[sideId * 8 + 6]) * textureWidth) / textureAbsLength;
vertexData[textureOffset + cellId * 48 + 8 * sideId + 7] = cubeTexCoordinates[sideId * 8 + 7];
*/
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void ComputeCubes2Kernel( float *pointsCoordinates, float *vertexData, int quadOffset, float cubeSide, float *cubeOperation, float *cubeTexCoordinates, int *activityFlag, float textureWidth, int maxCells )
{
int threadId = blockDim.x*blockIdx.y*gridDim.x //rows preceeding current row in grid
+ blockDim.x*blockIdx.x //blocks preceeding current block
+ threadIdx.x;
if(threadId < maxCells * 6)
{
int cellId = threadId / 6;
float fCellId = (float)cellId;
int sideId = threadId % 6;
float x = pointsCoordinates[cellId * 3];
float y = pointsCoordinates[cellId * 3 + 1];
float z = pointsCoordinates[cellId * 3 + 2];
float halfSide = (activityFlag[cellId] == 1) * 0.50f * cubeSide;
int textureOffset = quadOffset + maxCells * 4 * 6 * 3;
float textureAbsLength = (float)maxCells * textureWidth;
vertexData[quadOffset + cellId * 72 + 12*sideId] = x + operationMaskConstant[12*sideId] * halfSide;
vertexData[quadOffset + cellId * 72 + 12*sideId + 1] = y + operationMaskConstant[12*sideId + 1] * halfSide;
vertexData[quadOffset + cellId * 72 + 12*sideId + 2] = z + operationMaskConstant[12*sideId + 2] * halfSide;
vertexData[quadOffset + cellId * 72 + 12*sideId + 3] = x + operationMaskConstant[12*sideId + 3] * halfSide;
vertexData[quadOffset + cellId * 72 + 12*sideId + 4] = y + operationMaskConstant[12*sideId + 4] * halfSide;
vertexData[quadOffset + cellId * 72 + 12*sideId + 5] = z + operationMaskConstant[12*sideId + 5] * halfSide;
vertexData[quadOffset + cellId * 72 + 12*sideId + 6] = x + operationMaskConstant[12*sideId + 6] * halfSide;
vertexData[quadOffset + cellId * 72 + 12*sideId + 7] = y + operationMaskConstant[12*sideId + 7] * halfSide;
vertexData[quadOffset + cellId * 72 + 12*sideId + 8] = z + operationMaskConstant[12*sideId + 8] * halfSide;
vertexData[quadOffset + cellId * 72 + 12*sideId + 9] = x + operationMaskConstant[12*sideId + 9] * halfSide;
vertexData[quadOffset + cellId * 72 + 12*sideId + 10] = y + operationMaskConstant[12*sideId + 10] * halfSide;
vertexData[quadOffset + cellId * 72 + 12*sideId + 11] = z + operationMaskConstant[12*sideId + 11] * halfSide;
vertexData[textureOffset + cellId * 48 + 8 * sideId] = ((fCellId + cubeTexCoordinatesConstant[sideId * 8])* textureWidth) / textureAbsLength;
vertexData[textureOffset + cellId * 48 + 8 * sideId + 1] = cubeTexCoordinatesConstant[sideId * 8 + 1];
vertexData[textureOffset + cellId * 48 + 8 * sideId + 2] = ((fCellId + cubeTexCoordinatesConstant[sideId * 8 + 2]) * textureWidth) / textureAbsLength;
vertexData[textureOffset + cellId * 48 + 8 * sideId + 3] = cubeTexCoordinatesConstant[sideId * 8 + 3];
vertexData[textureOffset + cellId * 48 + 8 * sideId + 4] = ((fCellId + cubeTexCoordinatesConstant[sideId * 8 + 4]) * textureWidth) / textureAbsLength;
vertexData[textureOffset + cellId * 48 + 8 * sideId + 5] = cubeTexCoordinatesConstant[sideId * 8 + 5];
vertexData[textureOffset + cellId * 48 + 8 * sideId + 6] = ((fCellId + cubeTexCoordinatesConstant[sideId * 8 + 6]) * textureWidth) / textureAbsLength;
vertexData[textureOffset + cellId * 48 + 8 * sideId + 7] = cubeTexCoordinatesConstant[sideId * 8 + 7];
/*
vertexData[quadOffset + cellId * 72 + 12*sideId] = x + cubeOperation[12*sideId] * halfSide;
vertexData[quadOffset + cellId * 72 + 12*sideId + 1] = y + cubeOperation[12*sideId + 1] * halfSide;
vertexData[quadOffset + cellId * 72 + 12*sideId + 2] = z + cubeOperation[12*sideId + 2] * halfSide;
vertexData[quadOffset + cellId * 72 + 12*sideId + 3] = x + cubeOperation[12*sideId + 3] * halfSide;
vertexData[quadOffset + cellId * 72 + 12*sideId + 4] = y + cubeOperation[12*sideId + 4] * halfSide;
vertexData[quadOffset + cellId * 72 + 12*sideId + 5] = z + cubeOperation[12*sideId + 5] * halfSide;
vertexData[quadOffset + cellId * 72 + 12*sideId + 6] = x + cubeOperation[12*sideId + 6] * halfSide;
vertexData[quadOffset + cellId * 72 + 12*sideId + 7] = y + cubeOperation[12*sideId + 7] * halfSide;
vertexData[quadOffset + cellId * 72 + 12*sideId + 8] = z + cubeOperation[12*sideId + 8] * halfSide;
vertexData[quadOffset + cellId * 72 + 12*sideId + 9] = x + cubeOperation[12*sideId + 9] * halfSide;
vertexData[quadOffset + cellId * 72 + 12*sideId + 10] = y + cubeOperation[12*sideId + 10] * halfSide;
vertexData[quadOffset + cellId * 72 + 12*sideId + 11] = z + cubeOperation[12*sideId + 11] * halfSide;
vertexData[textureOffset + cellId * 48 + 8 * sideId] = ((fCellId + cubeTexCoordinates[sideId * 8])* textureWidth) / textureAbsLength;
vertexData[textureOffset + cellId * 48 + 8 * sideId + 1] = cubeTexCoordinates[sideId * 8 + 1];
vertexData[textureOffset + cellId * 48 + 8 * sideId + 2] = ((fCellId + cubeTexCoordinates[sideId * 8 + 2]) * textureWidth) / textureAbsLength;
vertexData[textureOffset + cellId * 48 + 8 * sideId + 3] = cubeTexCoordinates[sideId * 8 + 3];
vertexData[textureOffset + cellId * 48 + 8 * sideId + 4] = ((fCellId + cubeTexCoordinates[sideId * 8 + 4]) * textureWidth) / textureAbsLength;
vertexData[textureOffset + cellId * 48 + 8 * sideId + 5] = cubeTexCoordinates[sideId * 8 + 5];
vertexData[textureOffset + cellId * 48 + 8 * sideId + 6] = ((fCellId + cubeTexCoordinates[sideId * 8 + 6]) * textureWidth) / textureAbsLength;
vertexData[textureOffset + cellId * 48 + 8 * sideId + 7] = cubeTexCoordinates[sideId * 8 + 7];
*/
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void ComputeCubes2Kernel( float *pointsCoordinates, float *vertexData, int quadOffset, float cubeSide, float *cubeOperation, float *cubeTexCoordinates, int *activityFlag, float textureWidth, int maxCells )
{
int threadId = blockDim.x*blockIdx.y*gridDim.x //rows preceeding current row in grid
+ blockDim.x*blockIdx.x //blocks preceeding current block
+ threadIdx.x;
if(threadId < maxCells * 6)
{
int cellId = threadId / 6;
float fCellId = (float)cellId;
int sideId = threadId % 6;
float x = pointsCoordinates[cellId * 3];
float y = pointsCoordinates[cellId * 3 + 1];
float z = pointsCoordinates[cellId * 3 + 2];
float halfSide = (activityFlag[cellId] == 1) * 0.50f * cubeSide;
int textureOffset = quadOffset + maxCells * 4 * 6 * 3;
float textureAbsLength = (float)maxCells * textureWidth;
vertexData[quadOffset + cellId * 72 + 12*sideId] = x + operationMaskConstant[12*sideId] * halfSide;
vertexData[quadOffset + cellId * 72 + 12*sideId + 1] = y + operationMaskConstant[12*sideId + 1] * halfSide;
vertexData[quadOffset + cellId * 72 + 12*sideId + 2] = z + operationMaskConstant[12*sideId + 2] * halfSide;
vertexData[quadOffset + cellId * 72 + 12*sideId + 3] = x + operationMaskConstant[12*sideId + 3] * halfSide;
vertexData[quadOffset + cellId * 72 + 12*sideId + 4] = y + operationMaskConstant[12*sideId + 4] * halfSide;
vertexData[quadOffset + cellId * 72 + 12*sideId + 5] = z + operationMaskConstant[12*sideId + 5] * halfSide;
vertexData[quadOffset + cellId * 72 + 12*sideId + 6] = x + operationMaskConstant[12*sideId + 6] * halfSide;
vertexData[quadOffset + cellId * 72 + 12*sideId + 7] = y + operationMaskConstant[12*sideId + 7] * halfSide;
vertexData[quadOffset + cellId * 72 + 12*sideId + 8] = z + operationMaskConstant[12*sideId + 8] * halfSide;
vertexData[quadOffset + cellId * 72 + 12*sideId + 9] = x + operationMaskConstant[12*sideId + 9] * halfSide;
vertexData[quadOffset + cellId * 72 + 12*sideId + 10] = y + operationMaskConstant[12*sideId + 10] * halfSide;
vertexData[quadOffset + cellId * 72 + 12*sideId + 11] = z + operationMaskConstant[12*sideId + 11] * halfSide;
vertexData[textureOffset + cellId * 48 + 8 * sideId] = ((fCellId + cubeTexCoordinatesConstant[sideId * 8])* textureWidth) / textureAbsLength;
vertexData[textureOffset + cellId * 48 + 8 * sideId + 1] = cubeTexCoordinatesConstant[sideId * 8 + 1];
vertexData[textureOffset + cellId * 48 + 8 * sideId + 2] = ((fCellId + cubeTexCoordinatesConstant[sideId * 8 + 2]) * textureWidth) / textureAbsLength;
vertexData[textureOffset + cellId * 48 + 8 * sideId + 3] = cubeTexCoordinatesConstant[sideId * 8 + 3];
vertexData[textureOffset + cellId * 48 + 8 * sideId + 4] = ((fCellId + cubeTexCoordinatesConstant[sideId * 8 + 4]) * textureWidth) / textureAbsLength;
vertexData[textureOffset + cellId * 48 + 8 * sideId + 5] = cubeTexCoordinatesConstant[sideId * 8 + 5];
vertexData[textureOffset + cellId * 48 + 8 * sideId + 6] = ((fCellId + cubeTexCoordinatesConstant[sideId * 8 + 6]) * textureWidth) / textureAbsLength;
vertexData[textureOffset + cellId * 48 + 8 * sideId + 7] = cubeTexCoordinatesConstant[sideId * 8 + 7];
/*
vertexData[quadOffset + cellId * 72 + 12*sideId] = x + cubeOperation[12*sideId] * halfSide;
vertexData[quadOffset + cellId * 72 + 12*sideId + 1] = y + cubeOperation[12*sideId + 1] * halfSide;
vertexData[quadOffset + cellId * 72 + 12*sideId + 2] = z + cubeOperation[12*sideId + 2] * halfSide;
vertexData[quadOffset + cellId * 72 + 12*sideId + 3] = x + cubeOperation[12*sideId + 3] * halfSide;
vertexData[quadOffset + cellId * 72 + 12*sideId + 4] = y + cubeOperation[12*sideId + 4] * halfSide;
vertexData[quadOffset + cellId * 72 + 12*sideId + 5] = z + cubeOperation[12*sideId + 5] * halfSide;
vertexData[quadOffset + cellId * 72 + 12*sideId + 6] = x + cubeOperation[12*sideId + 6] * halfSide;
vertexData[quadOffset + cellId * 72 + 12*sideId + 7] = y + cubeOperation[12*sideId + 7] * halfSide;
vertexData[quadOffset + cellId * 72 + 12*sideId + 8] = z + cubeOperation[12*sideId + 8] * halfSide;
vertexData[quadOffset + cellId * 72 + 12*sideId + 9] = x + cubeOperation[12*sideId + 9] * halfSide;
vertexData[quadOffset + cellId * 72 + 12*sideId + 10] = y + cubeOperation[12*sideId + 10] * halfSide;
vertexData[quadOffset + cellId * 72 + 12*sideId + 11] = z + cubeOperation[12*sideId + 11] * halfSide;
vertexData[textureOffset + cellId * 48 + 8 * sideId] = ((fCellId + cubeTexCoordinates[sideId * 8])* textureWidth) / textureAbsLength;
vertexData[textureOffset + cellId * 48 + 8 * sideId + 1] = cubeTexCoordinates[sideId * 8 + 1];
vertexData[textureOffset + cellId * 48 + 8 * sideId + 2] = ((fCellId + cubeTexCoordinates[sideId * 8 + 2]) * textureWidth) / textureAbsLength;
vertexData[textureOffset + cellId * 48 + 8 * sideId + 3] = cubeTexCoordinates[sideId * 8 + 3];
vertexData[textureOffset + cellId * 48 + 8 * sideId + 4] = ((fCellId + cubeTexCoordinates[sideId * 8 + 4]) * textureWidth) / textureAbsLength;
vertexData[textureOffset + cellId * 48 + 8 * sideId + 5] = cubeTexCoordinates[sideId * 8 + 5];
vertexData[textureOffset + cellId * 48 + 8 * sideId + 6] = ((fCellId + cubeTexCoordinates[sideId * 8 + 6]) * textureWidth) / textureAbsLength;
vertexData[textureOffset + cellId * 48 + 8 * sideId + 7] = cubeTexCoordinates[sideId * 8 + 7];
*/
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z19ComputeCubes2KernelPfS_ifS_S_Pifi
.globl _Z19ComputeCubes2KernelPfS_ifS_S_Pifi
.p2align 8
.type _Z19ComputeCubes2KernelPfS_ifS_S_Pifi,@function
_Z19ComputeCubes2KernelPfS_ifS_S_Pifi:
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x34
s_load_b32 s4, s[0:1], 0x44
s_waitcnt lgkmcnt(0)
s_mul_i32 s3, s3, s15
s_and_b32 s4, s4, 0xffff
s_add_i32 s3, s3, s14
s_delay_alu instid0(SALU_CYCLE_1)
v_mad_u64_u32 v[1:2], null, s3, s4, v[0:1]
s_mul_i32 s3, s2, 6
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_cmp_gt_i32_e32 vcc_lo, s3, v1
s_and_saveexec_b32 s3, vcc_lo
s_cbranch_execz .LBB0_2
v_mul_hi_i32 v0, v1, 0x2aaaaaab
s_clause 0x2
s_load_b64 s[8:9], s[0:1], 0x28
s_load_b32 s3, s[0:1], 0x30
s_load_b128 s[4:7], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshrrev_b32_e32 v2, 31, v0
v_add_nc_u32_e32 v3, v0, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v4, 31, v3
v_mul_lo_u32 v0, v3, 6
v_lshlrev_b64 v[4:5], 2, v[3:4]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_sub_nc_u32_e32 v11, v1, v0
v_lshl_add_u32 v0, v3, 1, v3
s_waitcnt lgkmcnt(0)
v_add_co_u32 v4, vcc_lo, s8, v4
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v5, vcc_lo, s9, v5, vcc_lo
v_mul_lo_u32 v6, v11, 12
v_ashrrev_i32_e32 v1, 31, v0
s_load_b64 s[8:9], s[0:1], 0x10
global_load_b32 v12, v[4:5], off
s_getpc_b64 s[0:1]
s_add_u32 s0, s0, operationMaskConstant@rel32@lo+4
s_addc_u32 s1, s1, operationMaskConstant@rel32@hi+12
v_lshlrev_b64 v[0:1], 2, v[0:1]
v_ashrrev_i32_e32 v7, 31, v6
v_or_b32_e32 v9, 1, v6
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v0, vcc_lo, s4, v0
v_lshlrev_b64 v[4:5], 2, v[6:7]
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_ashrrev_i32_e32 v10, 31, v9
v_add_co_u32 v7, vcc_lo, v4, s0
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v8, vcc_lo, s1, v5, vcc_lo
global_load_b96 v[0:2], v[0:1], off
global_load_b32 v13, v[7:8], off
v_lshlrev_b64 v[9:10], 2, v[9:10]
s_waitcnt vmcnt(2)
v_cmp_eq_u32_e32 vcc_lo, 1, v12
v_cndmask_b32_e64 v12, 0, 0.5, vcc_lo
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mul_f32_e32 v12, s9, v12
v_mul_lo_u32 v7, v3, 0x48
v_add3_u32 v7, v7, s8, v6
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v13, v13, v12, v0
v_ashrrev_i32_e32 v8, 31, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[7:8], 2, v[7:8]
v_add_co_u32 v7, vcc_lo, s6, v7
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v8, vcc_lo, s7, v8, vcc_lo
v_add_co_u32 v9, vcc_lo, v9, s0
v_add_co_ci_u32_e32 v10, vcc_lo, s1, v10, vcc_lo
global_store_b32 v[7:8], v13, off
global_load_b32 v13, v[9:10], off
v_or_b32_e32 v9, 2, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v10, 31, v9
v_lshlrev_b64 v[9:10], 2, v[9:10]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v9, vcc_lo, v9, s0
v_add_co_ci_u32_e32 v10, vcc_lo, s1, v10, vcc_lo
s_waitcnt vmcnt(0)
v_fma_f32 v13, v13, v12, v1
global_store_b32 v[7:8], v13, off offset:4
global_load_b32 v13, v[9:10], off
v_or_b32_e32 v9, 3, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v10, 31, v9
v_lshlrev_b64 v[9:10], 2, v[9:10]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v9, vcc_lo, v9, s0
v_add_co_ci_u32_e32 v10, vcc_lo, s1, v10, vcc_lo
s_getpc_b64 s[0:1]
s_add_u32 s0, s0, operationMaskConstant@rel32@lo+20
s_addc_u32 s1, s1, operationMaskConstant@rel32@hi+28
s_waitcnt vmcnt(0)
v_fma_f32 v6, v12, v13, v2
global_store_b32 v[7:8], v6, off offset:8
global_load_b32 v6, v[9:10], off
v_add_co_u32 v9, vcc_lo, v4, s0
v_add_co_ci_u32_e32 v10, vcc_lo, s1, v5, vcc_lo
s_getpc_b64 s[0:1]
s_add_u32 s0, s0, operationMaskConstant@rel32@lo+24
s_addc_u32 s1, s1, operationMaskConstant@rel32@hi+32
s_waitcnt vmcnt(0)
v_fma_f32 v6, v12, v6, v0
global_store_b32 v[7:8], v6, off offset:12
global_load_b32 v6, v[9:10], off
v_add_co_u32 v9, vcc_lo, v4, s0
v_add_co_ci_u32_e32 v10, vcc_lo, s1, v5, vcc_lo
s_getpc_b64 s[0:1]
s_add_u32 s0, s0, operationMaskConstant@rel32@lo+28
s_addc_u32 s1, s1, operationMaskConstant@rel32@hi+36
s_waitcnt vmcnt(0)
v_fma_f32 v6, v12, v6, v1
global_store_b32 v[7:8], v6, off offset:16
global_load_b32 v6, v[9:10], off
v_add_co_u32 v9, vcc_lo, v4, s0
v_add_co_ci_u32_e32 v10, vcc_lo, s1, v5, vcc_lo
s_getpc_b64 s[0:1]
s_add_u32 s0, s0, operationMaskConstant@rel32@lo+32
s_addc_u32 s1, s1, operationMaskConstant@rel32@hi+40
s_waitcnt vmcnt(0)
v_fma_f32 v6, v12, v6, v2
global_store_b32 v[7:8], v6, off offset:20
global_load_b32 v6, v[9:10], off
v_add_co_u32 v9, vcc_lo, v4, s0
v_add_co_ci_u32_e32 v10, vcc_lo, s1, v5, vcc_lo
s_getpc_b64 s[0:1]
s_add_u32 s0, s0, operationMaskConstant@rel32@lo+36
s_addc_u32 s1, s1, operationMaskConstant@rel32@hi+44
s_waitcnt vmcnt(0)
v_fma_f32 v6, v12, v6, v0
global_store_b32 v[7:8], v6, off offset:24
global_load_b32 v6, v[9:10], off
v_add_co_u32 v9, vcc_lo, v4, s0
v_add_co_ci_u32_e32 v10, vcc_lo, s1, v5, vcc_lo
s_getpc_b64 s[0:1]
s_add_u32 s0, s0, operationMaskConstant@rel32@lo+40
s_addc_u32 s1, s1, operationMaskConstant@rel32@hi+48
s_waitcnt vmcnt(0)
v_fma_f32 v6, v12, v6, v1
global_store_b32 v[7:8], v6, off offset:28
global_load_b32 v6, v[9:10], off
v_add_co_u32 v9, vcc_lo, v4, s0
v_add_co_ci_u32_e32 v10, vcc_lo, s1, v5, vcc_lo
s_getpc_b64 s[0:1]
s_add_u32 s0, s0, operationMaskConstant@rel32@lo+44
s_addc_u32 s1, s1, operationMaskConstant@rel32@hi+52
s_waitcnt vmcnt(0)
v_fma_f32 v6, v12, v6, v2
global_store_b32 v[7:8], v6, off offset:32
global_load_b32 v6, v[9:10], off
v_add_co_u32 v9, vcc_lo, v4, s0
v_add_co_ci_u32_e32 v10, vcc_lo, s1, v5, vcc_lo
s_getpc_b64 s[0:1]
s_add_u32 s0, s0, operationMaskConstant@rel32@lo+48
s_addc_u32 s1, s1, operationMaskConstant@rel32@hi+56
s_waitcnt vmcnt(0)
v_fma_f32 v0, v12, v6, v0
global_store_b32 v[7:8], v0, off offset:36
global_load_b32 v0, v[9:10], off
s_waitcnt vmcnt(0)
v_fma_f32 v6, v12, v0, v1
v_add_co_u32 v0, vcc_lo, v4, s0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v5, vcc_lo
global_store_b32 v[7:8], v6, off offset:40
s_getpc_b64 s[0:1]
s_add_u32 s0, s0, cubeTexCoordinatesConstant@rel32@lo+4
s_addc_u32 s1, s1, cubeTexCoordinatesConstant@rel32@hi+12
global_load_b32 v6, v[0:1], off
v_lshlrev_b32_e32 v0, 3, v11
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[4:5], 2, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v4, vcc_lo, v4, s0
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v5, vcc_lo
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v2, v12, v6
global_store_b32 v[7:8], v2, off offset:44
global_load_b32 v1, v[4:5], off
v_cvt_f32_i32_e32 v5, v3
v_cvt_f32_i32_e32 v2, s2
s_mulk_i32 s2, 0x48
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
s_add_i32 s2, s2, s8
s_waitcnt vmcnt(0)
v_dual_mul_f32 v6, s3, v2 :: v_dual_add_f32 v1, v1, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v7, s3, v1
v_div_scale_f32 v8, null, v6, v6, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v9, v8
s_waitcnt_depctr 0xfff
v_fma_f32 v1, -v8, v9, 1.0
v_fmac_f32_e32 v9, v1, v9
v_div_scale_f32 v10, vcc_lo, v7, v6, v7
v_mul_lo_u32 v1, v3, 48
v_or_b32_e32 v3, 1, v0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_f32_e32 v11, v10, v9
v_ashrrev_i32_e32 v4, 31, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_fma_f32 v2, -v8, v11, v10
v_add3_u32 v1, s2, v1, v0
v_lshlrev_b64 v[3:4], 2, v[3:4]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fmac_f32_e32 v11, v2, v9
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v8, -v8, v11, v10
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_div_fmas_f32 v8, v8, v9, v11
v_add_co_u32 v1, vcc_lo, s6, v1
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_add_co_ci_u32_e32 v2, vcc_lo, s7, v2, vcc_lo
v_add_co_u32 v3, vcc_lo, v3, s0
v_div_fixup_f32 v7, v8, v6, v7
v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
global_store_b32 v[1:2], v7, off
global_load_b32 v7, v[3:4], off
v_or_b32_e32 v3, 2, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v4, 31, v3
v_lshlrev_b64 v[3:4], 2, v[3:4]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v3, vcc_lo, v3, s0
v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
s_waitcnt vmcnt(0)
global_store_b32 v[1:2], v7, off offset:4
global_load_b32 v3, v[3:4], off
s_waitcnt vmcnt(0)
v_add_f32_e32 v3, v3, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v7, s3, v3
v_div_scale_f32 v4, null, v6, v6, v7
v_div_scale_f32 v9, vcc_lo, v7, v6, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v8, v4
s_waitcnt_depctr 0xfff
v_fma_f32 v3, -v4, v8, 1.0
v_fmac_f32_e32 v8, v3, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v10, v9, v8
v_fma_f32 v3, -v4, v10, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_fmac_f32_e32 v10, v3, v8
v_or_b32_e32 v3, 3, v0
v_fma_f32 v9, -v4, v10, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v4, 31, v3
v_div_fmas_f32 v8, v9, v8, v10
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[3:4], 2, v[3:4]
v_div_fixup_f32 v7, v8, v6, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v3, vcc_lo, v3, s0
v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
global_store_b32 v[1:2], v7, off offset:8
global_load_b32 v7, v[3:4], off
v_or_b32_e32 v3, 4, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v4, 31, v3
v_lshlrev_b64 v[3:4], 2, v[3:4]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v3, vcc_lo, v3, s0
v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
s_waitcnt vmcnt(0)
global_store_b32 v[1:2], v7, off offset:12
global_load_b32 v3, v[3:4], off
s_waitcnt vmcnt(0)
v_add_f32_e32 v3, v3, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v7, s3, v3
v_div_scale_f32 v4, null, v6, v6, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v8, v4
s_waitcnt_depctr 0xfff
v_fma_f32 v3, -v4, v8, 1.0
v_fmac_f32_e32 v8, v3, v8
v_div_scale_f32 v9, vcc_lo, v7, v6, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v10, v9, v8
v_fma_f32 v3, -v4, v10, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_fmac_f32_e32 v10, v3, v8
v_or_b32_e32 v3, 5, v0
v_fma_f32 v9, -v4, v10, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v4, 31, v3
v_div_fmas_f32 v8, v9, v8, v10
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[3:4], 2, v[3:4]
v_div_fixup_f32 v7, v8, v6, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v3, vcc_lo, v3, s0
v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
global_store_b32 v[1:2], v7, off offset:16
global_load_b32 v7, v[3:4], off
v_or_b32_e32 v3, 6, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v4, 31, v3
v_lshlrev_b64 v[3:4], 2, v[3:4]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v3, vcc_lo, v3, s0
v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
s_waitcnt vmcnt(0)
global_store_b32 v[1:2], v7, off offset:20
global_load_b32 v3, v[3:4], off
s_waitcnt vmcnt(0)
v_add_f32_e32 v3, v3, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v5, s3, v3
v_div_scale_f32 v4, null, v6, v6, v5
v_div_scale_f32 v8, vcc_lo, v5, v6, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v7, v4
s_waitcnt_depctr 0xfff
v_fma_f32 v3, -v4, v7, 1.0
v_fmac_f32_e32 v7, v3, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v9, v8, v7
v_fma_f32 v3, -v4, v9, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_fmac_f32_e32 v9, v3, v7
v_or_b32_e32 v3, 7, v0
v_fma_f32 v0, -v4, v9, v8
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v4, 31, v3
v_div_fmas_f32 v0, v0, v7, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[3:4], 2, v[3:4]
v_div_fixup_f32 v0, v0, v6, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v3, vcc_lo, v3, s0
v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
global_store_b32 v[1:2], v0, off offset:24
global_load_b32 v0, v[3:4], off
s_waitcnt vmcnt(0)
global_store_b32 v[1:2], v0, off offset:28
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z19ComputeCubes2KernelPfS_ifS_S_Pifi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 312
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 14
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z19ComputeCubes2KernelPfS_ifS_S_Pifi, .Lfunc_end0-_Z19ComputeCubes2KernelPfS_ifS_S_Pifi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.protected operationMaskConstant
.type operationMaskConstant,@object
.section .bss,"aw",@nobits
.globl operationMaskConstant
.p2align 4, 0x0
operationMaskConstant:
.zero 288
.size operationMaskConstant, 288
.protected cubeTexCoordinatesConstant
.type cubeTexCoordinatesConstant,@object
.globl cubeTexCoordinatesConstant
.p2align 4, 0x0
cubeTexCoordinatesConstant:
.zero 192
.size cubeTexCoordinatesConstant, 192
.type __hip_cuid_,@object
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym operationMaskConstant
.addrsig_sym cubeTexCoordinatesConstant
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
- .offset: 48
.size: 4
.value_kind: by_value
- .offset: 52
.size: 4
.value_kind: by_value
- .offset: 56
.size: 4
.value_kind: hidden_block_count_x
- .offset: 60
.size: 4
.value_kind: hidden_block_count_y
- .offset: 64
.size: 4
.value_kind: hidden_block_count_z
- .offset: 68
.size: 2
.value_kind: hidden_group_size_x
- .offset: 70
.size: 2
.value_kind: hidden_group_size_y
- .offset: 72
.size: 2
.value_kind: hidden_group_size_z
- .offset: 74
.size: 2
.value_kind: hidden_remainder_x
- .offset: 76
.size: 2
.value_kind: hidden_remainder_y
- .offset: 78
.size: 2
.value_kind: hidden_remainder_z
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 112
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 120
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 312
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z19ComputeCubes2KernelPfS_ifS_S_Pifi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z19ComputeCubes2KernelPfS_ifS_S_Pifi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 14
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void ComputeCubes2Kernel( float *pointsCoordinates, float *vertexData, int quadOffset, float cubeSide, float *cubeOperation, float *cubeTexCoordinates, int *activityFlag, float textureWidth, int maxCells )
{
int threadId = blockDim.x*blockIdx.y*gridDim.x //rows preceeding current row in grid
+ blockDim.x*blockIdx.x //blocks preceeding current block
+ threadIdx.x;
if(threadId < maxCells * 6)
{
int cellId = threadId / 6;
float fCellId = (float)cellId;
int sideId = threadId % 6;
float x = pointsCoordinates[cellId * 3];
float y = pointsCoordinates[cellId * 3 + 1];
float z = pointsCoordinates[cellId * 3 + 2];
float halfSide = (activityFlag[cellId] == 1) * 0.50f * cubeSide;
int textureOffset = quadOffset + maxCells * 4 * 6 * 3;
float textureAbsLength = (float)maxCells * textureWidth;
vertexData[quadOffset + cellId * 72 + 12*sideId] = x + operationMaskConstant[12*sideId] * halfSide;
vertexData[quadOffset + cellId * 72 + 12*sideId + 1] = y + operationMaskConstant[12*sideId + 1] * halfSide;
vertexData[quadOffset + cellId * 72 + 12*sideId + 2] = z + operationMaskConstant[12*sideId + 2] * halfSide;
vertexData[quadOffset + cellId * 72 + 12*sideId + 3] = x + operationMaskConstant[12*sideId + 3] * halfSide;
vertexData[quadOffset + cellId * 72 + 12*sideId + 4] = y + operationMaskConstant[12*sideId + 4] * halfSide;
vertexData[quadOffset + cellId * 72 + 12*sideId + 5] = z + operationMaskConstant[12*sideId + 5] * halfSide;
vertexData[quadOffset + cellId * 72 + 12*sideId + 6] = x + operationMaskConstant[12*sideId + 6] * halfSide;
vertexData[quadOffset + cellId * 72 + 12*sideId + 7] = y + operationMaskConstant[12*sideId + 7] * halfSide;
vertexData[quadOffset + cellId * 72 + 12*sideId + 8] = z + operationMaskConstant[12*sideId + 8] * halfSide;
vertexData[quadOffset + cellId * 72 + 12*sideId + 9] = x + operationMaskConstant[12*sideId + 9] * halfSide;
vertexData[quadOffset + cellId * 72 + 12*sideId + 10] = y + operationMaskConstant[12*sideId + 10] * halfSide;
vertexData[quadOffset + cellId * 72 + 12*sideId + 11] = z + operationMaskConstant[12*sideId + 11] * halfSide;
vertexData[textureOffset + cellId * 48 + 8 * sideId] = ((fCellId + cubeTexCoordinatesConstant[sideId * 8])* textureWidth) / textureAbsLength;
vertexData[textureOffset + cellId * 48 + 8 * sideId + 1] = cubeTexCoordinatesConstant[sideId * 8 + 1];
vertexData[textureOffset + cellId * 48 + 8 * sideId + 2] = ((fCellId + cubeTexCoordinatesConstant[sideId * 8 + 2]) * textureWidth) / textureAbsLength;
vertexData[textureOffset + cellId * 48 + 8 * sideId + 3] = cubeTexCoordinatesConstant[sideId * 8 + 3];
vertexData[textureOffset + cellId * 48 + 8 * sideId + 4] = ((fCellId + cubeTexCoordinatesConstant[sideId * 8 + 4]) * textureWidth) / textureAbsLength;
vertexData[textureOffset + cellId * 48 + 8 * sideId + 5] = cubeTexCoordinatesConstant[sideId * 8 + 5];
vertexData[textureOffset + cellId * 48 + 8 * sideId + 6] = ((fCellId + cubeTexCoordinatesConstant[sideId * 8 + 6]) * textureWidth) / textureAbsLength;
vertexData[textureOffset + cellId * 48 + 8 * sideId + 7] = cubeTexCoordinatesConstant[sideId * 8 + 7];
/*
vertexData[quadOffset + cellId * 72 + 12*sideId] = x + cubeOperation[12*sideId] * halfSide;
vertexData[quadOffset + cellId * 72 + 12*sideId + 1] = y + cubeOperation[12*sideId + 1] * halfSide;
vertexData[quadOffset + cellId * 72 + 12*sideId + 2] = z + cubeOperation[12*sideId + 2] * halfSide;
vertexData[quadOffset + cellId * 72 + 12*sideId + 3] = x + cubeOperation[12*sideId + 3] * halfSide;
vertexData[quadOffset + cellId * 72 + 12*sideId + 4] = y + cubeOperation[12*sideId + 4] * halfSide;
vertexData[quadOffset + cellId * 72 + 12*sideId + 5] = z + cubeOperation[12*sideId + 5] * halfSide;
vertexData[quadOffset + cellId * 72 + 12*sideId + 6] = x + cubeOperation[12*sideId + 6] * halfSide;
vertexData[quadOffset + cellId * 72 + 12*sideId + 7] = y + cubeOperation[12*sideId + 7] * halfSide;
vertexData[quadOffset + cellId * 72 + 12*sideId + 8] = z + cubeOperation[12*sideId + 8] * halfSide;
vertexData[quadOffset + cellId * 72 + 12*sideId + 9] = x + cubeOperation[12*sideId + 9] * halfSide;
vertexData[quadOffset + cellId * 72 + 12*sideId + 10] = y + cubeOperation[12*sideId + 10] * halfSide;
vertexData[quadOffset + cellId * 72 + 12*sideId + 11] = z + cubeOperation[12*sideId + 11] * halfSide;
vertexData[textureOffset + cellId * 48 + 8 * sideId] = ((fCellId + cubeTexCoordinates[sideId * 8])* textureWidth) / textureAbsLength;
vertexData[textureOffset + cellId * 48 + 8 * sideId + 1] = cubeTexCoordinates[sideId * 8 + 1];
vertexData[textureOffset + cellId * 48 + 8 * sideId + 2] = ((fCellId + cubeTexCoordinates[sideId * 8 + 2]) * textureWidth) / textureAbsLength;
vertexData[textureOffset + cellId * 48 + 8 * sideId + 3] = cubeTexCoordinates[sideId * 8 + 3];
vertexData[textureOffset + cellId * 48 + 8 * sideId + 4] = ((fCellId + cubeTexCoordinates[sideId * 8 + 4]) * textureWidth) / textureAbsLength;
vertexData[textureOffset + cellId * 48 + 8 * sideId + 5] = cubeTexCoordinates[sideId * 8 + 5];
vertexData[textureOffset + cellId * 48 + 8 * sideId + 6] = ((fCellId + cubeTexCoordinates[sideId * 8 + 6]) * textureWidth) / textureAbsLength;
vertexData[textureOffset + cellId * 48 + 8 * sideId + 7] = cubeTexCoordinates[sideId * 8 + 7];
*/
}
} | .text
.file "ComputeCubes2Kernel.hip"
.globl _Z34__device_stub__ComputeCubes2KernelPfS_ifS_S_Pifi # -- Begin function _Z34__device_stub__ComputeCubes2KernelPfS_ifS_S_Pifi
.p2align 4, 0x90
.type _Z34__device_stub__ComputeCubes2KernelPfS_ifS_S_Pifi,@function
_Z34__device_stub__ComputeCubes2KernelPfS_ifS_S_Pifi: # @_Z34__device_stub__ComputeCubes2KernelPfS_ifS_S_Pifi
.cfi_startproc
# %bb.0:
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 104(%rsp)
movq %rsi, 96(%rsp)
movl %edx, 20(%rsp)
movss %xmm0, 16(%rsp)
movq %rcx, 88(%rsp)
movq %r8, 80(%rsp)
movq %r9, 72(%rsp)
movss %xmm1, 12(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 20(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 88(%rsp), %rax
movq %rax, 144(%rsp)
leaq 80(%rsp), %rax
movq %rax, 152(%rsp)
leaq 72(%rsp), %rax
movq %rax, 160(%rsp)
leaq 12(%rsp), %rax
movq %rax, 168(%rsp)
leaq 192(%rsp), %rax
movq %rax, 176(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z19ComputeCubes2KernelPfS_ifS_S_Pifi, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $200, %rsp
.cfi_adjust_cfa_offset -200
retq
.Lfunc_end0:
.size _Z34__device_stub__ComputeCubes2KernelPfS_ifS_S_Pifi, .Lfunc_end0-_Z34__device_stub__ComputeCubes2KernelPfS_ifS_S_Pifi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rbx
subq $32, %rsp
.cfi_adjust_cfa_offset 32
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z19ComputeCubes2KernelPfS_ifS_S_Pifi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
addq $32, %rsp
.cfi_adjust_cfa_offset -32
movl $operationMaskConstant, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movl $288, %r9d # imm = 0x120
movq %rbx, %rdi
xorl %r8d, %r8d
pushq $0
.cfi_adjust_cfa_offset 8
pushq $1
.cfi_adjust_cfa_offset 8
callq __hipRegisterVar
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movl $cubeTexCoordinatesConstant, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movl $192, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
pushq $0
.cfi_adjust_cfa_offset 8
pushq $1
.cfi_adjust_cfa_offset 8
callq __hipRegisterVar
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movl $__hip_module_dtor, %edi
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type operationMaskConstant,@object # @operationMaskConstant
.local operationMaskConstant
.comm operationMaskConstant,288,16
.type cubeTexCoordinatesConstant,@object # @cubeTexCoordinatesConstant
.local cubeTexCoordinatesConstant
.comm cubeTexCoordinatesConstant,192,16
.type _Z19ComputeCubes2KernelPfS_ifS_S_Pifi,@object # @_Z19ComputeCubes2KernelPfS_ifS_S_Pifi
.section .rodata,"a",@progbits
.globl _Z19ComputeCubes2KernelPfS_ifS_S_Pifi
.p2align 3, 0x0
_Z19ComputeCubes2KernelPfS_ifS_S_Pifi:
.quad _Z34__device_stub__ComputeCubes2KernelPfS_ifS_S_Pifi
.size _Z19ComputeCubes2KernelPfS_ifS_S_Pifi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z19ComputeCubes2KernelPfS_ifS_S_Pifi"
.size .L__unnamed_1, 38
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "operationMaskConstant"
.size .L__unnamed_2, 22
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "cubeTexCoordinatesConstant"
.size .L__unnamed_3, 27
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z34__device_stub__ComputeCubes2KernelPfS_ifS_S_Pifi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym operationMaskConstant
.addrsig_sym cubeTexCoordinatesConstant
.addrsig_sym _Z19ComputeCubes2KernelPfS_ifS_S_Pifi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000cccc1_00000000-6_ComputeCubes2Kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z51__device_stub__Z19ComputeCubes2KernelPfS_ifS_S_PifiPfS_ifS_S_Pifi
.type _Z51__device_stub__Z19ComputeCubes2KernelPfS_ifS_S_PifiPfS_ifS_S_Pifi, @function
_Z51__device_stub__Z19ComputeCubes2KernelPfS_ifS_S_PifiPfS_ifS_S_Pifi:
.LFB2051:
.cfi_startproc
endbr64
subq $216, %rsp
.cfi_def_cfa_offset 224
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
movl %edx, 44(%rsp)
movss %xmm0, 40(%rsp)
movq %rcx, 32(%rsp)
movq %r8, 24(%rsp)
movq %r9, 16(%rsp)
movss %xmm1, 12(%rsp)
movq %fs:40, %rax
movq %rax, 200(%rsp)
xorl %eax, %eax
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 44(%rsp), %rax
movq %rax, 144(%rsp)
leaq 40(%rsp), %rax
movq %rax, 152(%rsp)
leaq 32(%rsp), %rax
movq %rax, 160(%rsp)
leaq 24(%rsp), %rax
movq %rax, 168(%rsp)
leaq 16(%rsp), %rax
movq %rax, 176(%rsp)
leaq 12(%rsp), %rax
movq %rax, 184(%rsp)
leaq 224(%rsp), %rax
movq %rax, 192(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 200(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $216, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 232
pushq 72(%rsp)
.cfi_def_cfa_offset 240
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq _Z19ComputeCubes2KernelPfS_ifS_S_Pifi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 224
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z51__device_stub__Z19ComputeCubes2KernelPfS_ifS_S_PifiPfS_ifS_S_Pifi, .-_Z51__device_stub__Z19ComputeCubes2KernelPfS_ifS_S_PifiPfS_ifS_S_Pifi
.globl _Z19ComputeCubes2KernelPfS_ifS_S_Pifi
.type _Z19ComputeCubes2KernelPfS_ifS_S_Pifi, @function
_Z19ComputeCubes2KernelPfS_ifS_S_Pifi:
.LFB2052:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
call _Z51__device_stub__Z19ComputeCubes2KernelPfS_ifS_S_PifiPfS_ifS_S_Pifi
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z19ComputeCubes2KernelPfS_ifS_S_Pifi, .-_Z19ComputeCubes2KernelPfS_ifS_S_Pifi
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z19ComputeCubes2KernelPfS_ifS_S_Pifi"
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "operationMaskConstant"
.LC2:
.string "cubeTexCoordinatesConstant"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z19ComputeCubes2KernelPfS_ifS_S_Pifi(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $288, %r9d
movl $0, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _ZL21operationMaskConstant(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $192, %r9d
movl $0, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _ZL26cubeTexCoordinatesConstant(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL26cubeTexCoordinatesConstant
.comm _ZL26cubeTexCoordinatesConstant,192,32
.local _ZL21operationMaskConstant
.comm _ZL21operationMaskConstant,288,32
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "ComputeCubes2Kernel.hip"
.globl _Z34__device_stub__ComputeCubes2KernelPfS_ifS_S_Pifi # -- Begin function _Z34__device_stub__ComputeCubes2KernelPfS_ifS_S_Pifi
.p2align 4, 0x90
.type _Z34__device_stub__ComputeCubes2KernelPfS_ifS_S_Pifi,@function
_Z34__device_stub__ComputeCubes2KernelPfS_ifS_S_Pifi: # @_Z34__device_stub__ComputeCubes2KernelPfS_ifS_S_Pifi
.cfi_startproc
# %bb.0:
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 104(%rsp)
movq %rsi, 96(%rsp)
movl %edx, 20(%rsp)
movss %xmm0, 16(%rsp)
movq %rcx, 88(%rsp)
movq %r8, 80(%rsp)
movq %r9, 72(%rsp)
movss %xmm1, 12(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 20(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 88(%rsp), %rax
movq %rax, 144(%rsp)
leaq 80(%rsp), %rax
movq %rax, 152(%rsp)
leaq 72(%rsp), %rax
movq %rax, 160(%rsp)
leaq 12(%rsp), %rax
movq %rax, 168(%rsp)
leaq 192(%rsp), %rax
movq %rax, 176(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z19ComputeCubes2KernelPfS_ifS_S_Pifi, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $200, %rsp
.cfi_adjust_cfa_offset -200
retq
.Lfunc_end0:
.size _Z34__device_stub__ComputeCubes2KernelPfS_ifS_S_Pifi, .Lfunc_end0-_Z34__device_stub__ComputeCubes2KernelPfS_ifS_S_Pifi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rbx
subq $32, %rsp
.cfi_adjust_cfa_offset 32
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z19ComputeCubes2KernelPfS_ifS_S_Pifi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
addq $32, %rsp
.cfi_adjust_cfa_offset -32
movl $operationMaskConstant, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movl $288, %r9d # imm = 0x120
movq %rbx, %rdi
xorl %r8d, %r8d
pushq $0
.cfi_adjust_cfa_offset 8
pushq $1
.cfi_adjust_cfa_offset 8
callq __hipRegisterVar
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movl $cubeTexCoordinatesConstant, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movl $192, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
pushq $0
.cfi_adjust_cfa_offset 8
pushq $1
.cfi_adjust_cfa_offset 8
callq __hipRegisterVar
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movl $__hip_module_dtor, %edi
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type operationMaskConstant,@object # @operationMaskConstant
.local operationMaskConstant
.comm operationMaskConstant,288,16
.type cubeTexCoordinatesConstant,@object # @cubeTexCoordinatesConstant
.local cubeTexCoordinatesConstant
.comm cubeTexCoordinatesConstant,192,16
.type _Z19ComputeCubes2KernelPfS_ifS_S_Pifi,@object # @_Z19ComputeCubes2KernelPfS_ifS_S_Pifi
.section .rodata,"a",@progbits
.globl _Z19ComputeCubes2KernelPfS_ifS_S_Pifi
.p2align 3, 0x0
_Z19ComputeCubes2KernelPfS_ifS_S_Pifi:
.quad _Z34__device_stub__ComputeCubes2KernelPfS_ifS_S_Pifi
.size _Z19ComputeCubes2KernelPfS_ifS_S_Pifi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z19ComputeCubes2KernelPfS_ifS_S_Pifi"
.size .L__unnamed_1, 38
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "operationMaskConstant"
.size .L__unnamed_2, 22
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "cubeTexCoordinatesConstant"
.size .L__unnamed_3, 27
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z34__device_stub__ComputeCubes2KernelPfS_ifS_S_Pifi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym operationMaskConstant
.addrsig_sym cubeTexCoordinatesConstant
.addrsig_sym _Z19ComputeCubes2KernelPfS_ifS_S_Pifi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
extern "C"
extern "C"
__global__ void deltasBatch(float *inputs, float *outputs, float *weights, float *weightsDeltas, int noInputs, int inputSize){
int gid = blockIdx.x * blockDim.x + threadIdx.x;
float sum=0;
int offsetDeltas = (inputSize+1)*gid;
int offsetInput = noInputs*inputSize*gid;
int offsetOutputs = noInputs*gid;
for(int imageIndex=0;imageIndex<=inputSize;imageIndex++){
weightsDeltas[offsetDeltas+imageIndex]=0;
}
for (int i=0;i<noInputs;i++){
sum=0;
for(int imageIndex=0;imageIndex<inputSize;imageIndex++){
sum+=inputs[offsetInput+i*inputSize+imageIndex]*weights[imageIndex];
}
sum+=weights[inputSize];
if(sum>0) sum=1;
else sum=0;
sum=outputs[offsetOutputs+i]-sum;
if(sum!=0){
for(int imageIndex=0;imageIndex<inputSize;imageIndex++){
weightsDeltas[offsetDeltas+imageIndex]+=sum*inputs[offsetInput+i*inputSize+imageIndex];
}
weightsDeltas[offsetDeltas+inputSize]+=sum;
}
}
} | .file "tmpxft_000c03b5_00000000-6_deltasBatch.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z39__device_stub__Z11deltasBatchPfS_S_S_iiPfS_S_S_ii
.type _Z39__device_stub__Z11deltasBatchPfS_S_S_iiPfS_S_S_ii, @function
_Z39__device_stub__Z11deltasBatchPfS_S_S_iiPfS_S_S_ii:
.LFB2051:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movl %r8d, 12(%rsp)
movl %r9d, 8(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 12(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq deltasBatch(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z39__device_stub__Z11deltasBatchPfS_S_S_iiPfS_S_S_ii, .-_Z39__device_stub__Z11deltasBatchPfS_S_S_iiPfS_S_S_ii
.globl deltasBatch
.type deltasBatch, @function
deltasBatch:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z39__device_stub__Z11deltasBatchPfS_S_S_iiPfS_S_S_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size deltasBatch, .-deltasBatch
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "deltasBatch"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq deltasBatch(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
extern "C"
extern "C"
__global__ void deltasBatch(float *inputs, float *outputs, float *weights, float *weightsDeltas, int noInputs, int inputSize){
int gid = blockIdx.x * blockDim.x + threadIdx.x;
float sum=0;
int offsetDeltas = (inputSize+1)*gid;
int offsetInput = noInputs*inputSize*gid;
int offsetOutputs = noInputs*gid;
for(int imageIndex=0;imageIndex<=inputSize;imageIndex++){
weightsDeltas[offsetDeltas+imageIndex]=0;
}
for (int i=0;i<noInputs;i++){
sum=0;
for(int imageIndex=0;imageIndex<inputSize;imageIndex++){
sum+=inputs[offsetInput+i*inputSize+imageIndex]*weights[imageIndex];
}
sum+=weights[inputSize];
if(sum>0) sum=1;
else sum=0;
sum=outputs[offsetOutputs+i]-sum;
if(sum!=0){
for(int imageIndex=0;imageIndex<inputSize;imageIndex++){
weightsDeltas[offsetDeltas+imageIndex]+=sum*inputs[offsetInput+i*inputSize+imageIndex];
}
weightsDeltas[offsetDeltas+inputSize]+=sum;
}
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
extern "C"
extern "C"
__global__ void deltasBatch(float *inputs, float *outputs, float *weights, float *weightsDeltas, int noInputs, int inputSize){
int gid = blockIdx.x * blockDim.x + threadIdx.x;
float sum=0;
int offsetDeltas = (inputSize+1)*gid;
int offsetInput = noInputs*inputSize*gid;
int offsetOutputs = noInputs*gid;
for(int imageIndex=0;imageIndex<=inputSize;imageIndex++){
weightsDeltas[offsetDeltas+imageIndex]=0;
}
for (int i=0;i<noInputs;i++){
sum=0;
for(int imageIndex=0;imageIndex<inputSize;imageIndex++){
sum+=inputs[offsetInput+i*inputSize+imageIndex]*weights[imageIndex];
}
sum+=weights[inputSize];
if(sum>0) sum=1;
else sum=0;
sum=outputs[offsetOutputs+i]-sum;
if(sum!=0){
for(int imageIndex=0;imageIndex<inputSize;imageIndex++){
weightsDeltas[offsetDeltas+imageIndex]+=sum*inputs[offsetInput+i*inputSize+imageIndex];
}
weightsDeltas[offsetDeltas+inputSize]+=sum;
}
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
extern "C"
extern "C"
__global__ void deltasBatch(float *inputs, float *outputs, float *weights, float *weightsDeltas, int noInputs, int inputSize){
int gid = blockIdx.x * blockDim.x + threadIdx.x;
float sum=0;
int offsetDeltas = (inputSize+1)*gid;
int offsetInput = noInputs*inputSize*gid;
int offsetOutputs = noInputs*gid;
for(int imageIndex=0;imageIndex<=inputSize;imageIndex++){
weightsDeltas[offsetDeltas+imageIndex]=0;
}
for (int i=0;i<noInputs;i++){
sum=0;
for(int imageIndex=0;imageIndex<inputSize;imageIndex++){
sum+=inputs[offsetInput+i*inputSize+imageIndex]*weights[imageIndex];
}
sum+=weights[inputSize];
if(sum>0) sum=1;
else sum=0;
sum=outputs[offsetOutputs+i]-sum;
if(sum!=0){
for(int imageIndex=0;imageIndex<inputSize;imageIndex++){
weightsDeltas[offsetDeltas+imageIndex]+=sum*inputs[offsetInput+i*inputSize+imageIndex];
}
weightsDeltas[offsetDeltas+inputSize]+=sum;
}
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected deltasBatch
.globl deltasBatch
.p2align 8
.type deltasBatch,@function
deltasBatch:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x34
s_load_b32 s4, s[0:1], 0x24
s_load_b64 s[10:11], s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_add_i32 s2, s4, 1
s_cmp_lt_i32 s4, 0
v_mul_lo_u32 v2, v1, s2
s_cbranch_scc1 .LBB0_3
s_delay_alu instid0(VALU_DEP_1)
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v3, v2
.LBB0_2:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_ashrrev_i32_e32 v4, 31, v3
s_add_i32 s2, s2, -1
s_cmp_eq_u32 s2, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[4:5], 2, v[3:4]
v_add_nc_u32_e32 v3, 1, v3
v_add_co_u32 v4, vcc_lo, s10, v4
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v5, vcc_lo, s11, v5, vcc_lo
global_store_b32 v[4:5], v0, off
s_cbranch_scc0 .LBB0_2
.LBB0_3:
s_load_b32 s12, s[0:1], 0x20
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s12, 1
s_cbranch_scc1 .LBB0_14
s_load_b64 s[6:7], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_dual_mov_b32 v11, 0 :: v_dual_add_nc_u32 v4, s4, v2
v_ashrrev_i32_e32 v3, 31, v2
s_load_b128 s[0:3], s[0:1], 0x0
s_ashr_i32 s5, s4, 31
v_ashrrev_i32_e32 v5, 31, v4
s_mul_i32 s13, s4, s12
v_lshlrev_b64 v[2:3], 2, v[2:3]
v_mul_lo_u32 v10, v1, s12
s_lshl_b64 s[8:9], s[4:5], 2
v_lshlrev_b64 v[4:5], 2, v[4:5]
v_mul_lo_u32 v0, s13, v1
s_mov_b32 s13, 0
v_add_co_u32 v2, vcc_lo, s10, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s11, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_4)
v_add_co_u32 v4, vcc_lo, s10, v4
s_waitcnt lgkmcnt(0)
s_add_u32 s8, s6, s8
s_addc_u32 s9, s7, s9
v_add_co_ci_u32_e32 v5, vcc_lo, s11, v5, vcc_lo
s_cmp_gt_i32 s4, 0
s_cselect_b32 s5, -1, 0
s_branch .LBB0_7
.LBB0_5:
global_load_b32 v1, v[4:5], off
s_waitcnt vmcnt(0)
v_add_f32_e32 v1, v12, v1
global_store_b32 v[4:5], v1, off
.LBB0_6:
s_or_b32 exec_lo, exec_lo, s10
v_add_nc_u32_e32 v0, s4, v0
s_add_i32 s13, s13, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s13, s12
s_cbranch_scc1 .LBB0_14
.LBB0_7:
v_mov_b32_e32 v1, 0
s_and_not1_b32 vcc_lo, exec_lo, s5
s_cbranch_vccnz .LBB0_10
v_ashrrev_i32_e32 v1, 31, v0
s_mov_b64 s[10:11], s[6:7]
s_mov_b32 s14, s4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[6:7], 2, v[0:1]
v_mov_b32_e32 v1, 0
v_add_co_u32 v6, vcc_lo, s0, v6
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v7, vcc_lo, s1, v7, vcc_lo
.LBB0_9:
global_load_b32 v8, v[6:7], off
global_load_b32 v9, v11, s[10:11]
v_add_co_u32 v6, vcc_lo, v6, 4
s_add_i32 s14, s14, -1
v_add_co_ci_u32_e32 v7, vcc_lo, 0, v7, vcc_lo
s_add_u32 s10, s10, 4
s_addc_u32 s11, s11, 0
s_cmp_eq_u32 s14, 0
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v1, v8, v9
s_cbranch_scc0 .LBB0_9
.LBB0_10:
global_load_b32 v8, v11, s[8:9]
v_add_nc_u32_e32 v6, s13, v10
s_mov_b32 s10, exec_lo
s_waitcnt vmcnt(0)
v_add_f32_e32 v1, v1, v8
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v7, 31, v6
v_lshlrev_b64 v[6:7], 2, v[6:7]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v6, vcc_lo, s2, v6
v_add_co_ci_u32_e32 v7, vcc_lo, s3, v7, vcc_lo
v_cmp_lt_f32_e32 vcc_lo, 0, v1
global_load_b32 v6, v[6:7], off
v_cndmask_b32_e64 v1, 0, 1.0, vcc_lo
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_f32_e32 v12, v6, v1
v_cmpx_neq_f32_e32 0, v12
s_cbranch_execz .LBB0_6
s_and_not1_b32 vcc_lo, exec_lo, s5
s_cbranch_vccnz .LBB0_5
v_ashrrev_i32_e32 v1, 31, v0
v_dual_mov_b32 v9, v3 :: v_dual_mov_b32 v8, v2
s_mov_b32 s11, s4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[6:7], 2, v[0:1]
v_add_co_u32 v6, vcc_lo, s0, v6
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v7, vcc_lo, s1, v7, vcc_lo
.p2align 6
.LBB0_13:
global_load_b32 v1, v[6:7], off
global_load_b32 v13, v[8:9], off
s_add_i32 s11, s11, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s11, 0
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v13, v12, v1
global_store_b32 v[8:9], v13, off
v_add_co_u32 v8, vcc_lo, v8, 4
v_add_co_ci_u32_e32 v9, vcc_lo, 0, v9, vcc_lo
v_add_co_u32 v6, vcc_lo, v6, 4
v_add_co_ci_u32_e32 v7, vcc_lo, 0, v7, vcc_lo
s_cbranch_scc0 .LBB0_13
s_branch .LBB0_5
.LBB0_14:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel deltasBatch
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 14
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size deltasBatch, .Lfunc_end0-deltasBatch
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 36
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: deltasBatch
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: deltasBatch.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 14
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
extern "C"
extern "C"
__global__ void deltasBatch(float *inputs, float *outputs, float *weights, float *weightsDeltas, int noInputs, int inputSize){
int gid = blockIdx.x * blockDim.x + threadIdx.x;
float sum=0;
int offsetDeltas = (inputSize+1)*gid;
int offsetInput = noInputs*inputSize*gid;
int offsetOutputs = noInputs*gid;
for(int imageIndex=0;imageIndex<=inputSize;imageIndex++){
weightsDeltas[offsetDeltas+imageIndex]=0;
}
for (int i=0;i<noInputs;i++){
sum=0;
for(int imageIndex=0;imageIndex<inputSize;imageIndex++){
sum+=inputs[offsetInput+i*inputSize+imageIndex]*weights[imageIndex];
}
sum+=weights[inputSize];
if(sum>0) sum=1;
else sum=0;
sum=outputs[offsetOutputs+i]-sum;
if(sum!=0){
for(int imageIndex=0;imageIndex<inputSize;imageIndex++){
weightsDeltas[offsetDeltas+imageIndex]+=sum*inputs[offsetInput+i*inputSize+imageIndex];
}
weightsDeltas[offsetDeltas+inputSize]+=sum;
}
}
} | .text
.file "deltasBatch.hip"
.globl __device_stub__deltasBatch # -- Begin function __device_stub__deltasBatch
.p2align 4, 0x90
.type __device_stub__deltasBatch,@function
__device_stub__deltasBatch: # @__device_stub__deltasBatch
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movl %r8d, 12(%rsp)
movl %r9d, 8(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 12(%rsp), %rax
movq %rax, 128(%rsp)
leaq 8(%rsp), %rax
movq %rax, 136(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $deltasBatch, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size __device_stub__deltasBatch, .Lfunc_end0-__device_stub__deltasBatch
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $deltasBatch, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type deltasBatch,@object # @deltasBatch
.section .rodata,"a",@progbits
.globl deltasBatch
.p2align 3, 0x0
deltasBatch:
.quad __device_stub__deltasBatch
.size deltasBatch, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "deltasBatch"
.size .L__unnamed_1, 12
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub__deltasBatch
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym deltasBatch
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000c03b5_00000000-6_deltasBatch.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z39__device_stub__Z11deltasBatchPfS_S_S_iiPfS_S_S_ii
.type _Z39__device_stub__Z11deltasBatchPfS_S_S_iiPfS_S_S_ii, @function
_Z39__device_stub__Z11deltasBatchPfS_S_S_iiPfS_S_S_ii:
.LFB2051:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movl %r8d, 12(%rsp)
movl %r9d, 8(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 12(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq deltasBatch(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z39__device_stub__Z11deltasBatchPfS_S_S_iiPfS_S_S_ii, .-_Z39__device_stub__Z11deltasBatchPfS_S_S_iiPfS_S_S_ii
.globl deltasBatch
.type deltasBatch, @function
deltasBatch:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z39__device_stub__Z11deltasBatchPfS_S_S_iiPfS_S_S_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size deltasBatch, .-deltasBatch
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "deltasBatch"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq deltasBatch(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "deltasBatch.hip"
.globl __device_stub__deltasBatch # -- Begin function __device_stub__deltasBatch
.p2align 4, 0x90
.type __device_stub__deltasBatch,@function
__device_stub__deltasBatch: # @__device_stub__deltasBatch
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movl %r8d, 12(%rsp)
movl %r9d, 8(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 12(%rsp), %rax
movq %rax, 128(%rsp)
leaq 8(%rsp), %rax
movq %rax, 136(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $deltasBatch, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size __device_stub__deltasBatch, .Lfunc_end0-__device_stub__deltasBatch
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $deltasBatch, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type deltasBatch,@object # @deltasBatch
.section .rodata,"a",@progbits
.globl deltasBatch
.p2align 3, 0x0
deltasBatch:
.quad __device_stub__deltasBatch
.size deltasBatch, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "deltasBatch"
.size .L__unnamed_1, 12
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub__deltasBatch
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym deltasBatch
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
/*****************************************
Emitting C Generated Code
*******************************************/
/************* Functions **************/
/**************** Snippet ****************/
__global__ void x6(float* x7, float* x8, float* x9, int x10) {
int x11 = gridDim.x * blockDim.x;
int x12 = threadIdx.x + blockIdx.x * blockDim.x;
while (x12 < x10) {
int x13 = x12;
x9[x13] = x7[x13] + x8[x13];
x12 = x12 + x11;
}
} | code for sm_80
Function : _Z2x6PfS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e280000002500 */
/*0020*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R3, R3, c[0x0][0x0], R0 ; /* 0x0000000003037a24 */
/* 0x001fca00078e0200 */
/*0040*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x178], PT ; /* 0x00005e0003007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ MOV R0, c[0x0][0x0] ; /* 0x0000000000007a02 */
/* 0x000fe20000000f00 */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0080*/ BSSY B0, 0x340 ; /* 0x000002b000007945 */
/* 0x000fe60003800000 */
/*0090*/ IMAD R0, R0, c[0x0][0xc], RZ ; /* 0x0000030000007a24 */
/* 0x000fc800078e02ff */
/*00a0*/ I2F.U32.RP R6, R0 ; /* 0x0000000000067306 */
/* 0x000e220000209000 */
/*00b0*/ IADD3 R9, RZ, -R0, RZ ; /* 0x80000000ff097210 */
/* 0x000fe40007ffe0ff */
/*00c0*/ IADD3 R2, R0.reuse, R3, RZ ; /* 0x0000000300027210 */
/* 0x040fe40007ffe0ff */
/*00d0*/ ISETP.NE.U32.AND P2, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe40003f45070 */
/*00e0*/ LOP3.LUT R7, RZ, R2, RZ, 0x33, !PT ; /* 0x00000002ff077212 */
/* 0x000fc800078e33ff */
/*00f0*/ IADD3 R7, R7, c[0x0][0x178], R0 ; /* 0x00005e0007077a10 */
/* 0x000fe20007ffe000 */
/*0100*/ MUFU.RCP R6, R6 ; /* 0x0000000600067308 */
/* 0x001e240000001000 */
/*0110*/ IADD3 R4, R6, 0xffffffe, RZ ; /* 0x0ffffffe06047810 */
/* 0x001fcc0007ffe0ff */
/*0120*/ F2I.FTZ.U32.TRUNC.NTZ R5, R4 ; /* 0x0000000400057305 */
/* 0x000064000021f000 */
/*0130*/ HFMA2.MMA R4, -RZ, RZ, 0, 0 ; /* 0x00000000ff047435 */
/* 0x001fe200000001ff */
/*0140*/ IMAD R9, R9, R5, RZ ; /* 0x0000000509097224 */
/* 0x002fd200078e02ff */
/*0150*/ IMAD.HI.U32 R2, R5, R9, R4 ; /* 0x0000000905027227 */
/* 0x000fcc00078e0004 */
/*0160*/ IMAD.HI.U32 R2, R2, R7, RZ ; /* 0x0000000702027227 */
/* 0x000fca00078e00ff */
/*0170*/ IADD3 R4, -R2, RZ, RZ ; /* 0x000000ff02047210 */
/* 0x000fca0007ffe1ff */
/*0180*/ IMAD R7, R0, R4, R7 ; /* 0x0000000400077224 */
/* 0x000fca00078e0207 */
/*0190*/ ISETP.GE.U32.AND P0, PT, R7, R0, PT ; /* 0x000000000700720c */
/* 0x000fda0003f06070 */
/*01a0*/ @P0 IADD3 R7, -R0, R7, RZ ; /* 0x0000000700070210 */
/* 0x000fe40007ffe1ff */
/*01b0*/ @P0 IADD3 R2, R2, 0x1, RZ ; /* 0x0000000102020810 */
/* 0x000fe40007ffe0ff */
/*01c0*/ ISETP.GE.U32.AND P1, PT, R7, R0, PT ; /* 0x000000000700720c */
/* 0x000fda0003f26070 */
/*01d0*/ @P1 IADD3 R2, R2, 0x1, RZ ; /* 0x0000000102021810 */
/* 0x000fe40007ffe0ff */
/*01e0*/ @!P2 LOP3.LUT R2, RZ, R0, RZ, 0x33, !PT ; /* 0x00000000ff02a212 */
/* 0x000fc800078e33ff */
/*01f0*/ IADD3 R4, R2.reuse, 0x1, RZ ; /* 0x0000000102047810 */
/* 0x040fe40007ffe0ff */
/*0200*/ ISETP.GE.U32.AND P1, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fe40003f26070 */
/*0210*/ LOP3.LUT P0, R4, R4, 0x3, RZ, 0xc0, !PT ; /* 0x0000000304047812 */
/* 0x000fda000780c0ff */
/*0220*/ @!P0 BRA 0x330 ; /* 0x0000010000008947 */
/* 0x000fea0003800000 */
/*0230*/ MOV R8, 0x4 ; /* 0x0000000400087802 */
/* 0x000fe40000000f00 */
/*0240*/ MOV R2, R4 ; /* 0x0000000400027202 */
/* 0x000fc60000000f00 */
/*0250*/ IMAD.WIDE R4, R3, R8, c[0x0][0x170] ; /* 0x00005c0003047625 */
/* 0x000fc800078e0208 */
/*0260*/ IMAD.WIDE R6, R3, R8, c[0x0][0x168] ; /* 0x00005a0003067625 */
/* 0x000fc800078e0208 */
/*0270*/ IMAD.WIDE R8, R3, R8, c[0x0][0x160] ; /* 0x0000580003087625 */
/* 0x000fc800078e0208 */
/*0280*/ LDG.E R10, [R6.64] ; /* 0x00000004060a7981 */
/* 0x0000a8000c1e1900 */
/*0290*/ LDG.E R11, [R8.64] ; /* 0x00000004080b7981 */
/* 0x0002a2000c1e1900 */
/*02a0*/ IADD3 R2, R2, -0x1, RZ ; /* 0xffffffff02027810 */
/* 0x000fe40007ffe0ff */
/*02b0*/ IADD3 R3, R0, R3, RZ ; /* 0x0000000300037210 */
/* 0x000fe40007ffe0ff */
/*02c0*/ ISETP.NE.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fe20003f05270 */
/*02d0*/ IMAD.WIDE R6, R0, 0x4, R6 ; /* 0x0000000400067825 */
/* 0x001fc800078e0206 */
/*02e0*/ IMAD.WIDE R8, R0, 0x4, R8 ; /* 0x0000000400087825 */
/* 0x002fc800078e0208 */
/*02f0*/ FADD R11, R10, R11 ; /* 0x0000000b0a0b7221 */
/* 0x004fca0000000000 */
/*0300*/ STG.E [R4.64], R11 ; /* 0x0000000b04007986 */
/* 0x0001e4000c101904 */
/*0310*/ IMAD.WIDE R4, R0, 0x4, R4 ; /* 0x0000000400047825 */
/* 0x001fe200078e0204 */
/*0320*/ @P0 BRA 0x280 ; /* 0xffffff5000000947 */
/* 0x000fea000383ffff */
/*0330*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0340*/ @!P1 EXIT ; /* 0x000000000000994d */
/* 0x000fea0003800000 */
/*0350*/ HFMA2.MMA R8, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff087435 */
/* 0x000fd400000001ff */
/*0360*/ IMAD.WIDE R6, R3, R8, c[0x0][0x168] ; /* 0x00005a0003067625 */
/* 0x000fc800078e0208 */
/*0370*/ IMAD.WIDE R4, R3.reuse, R8.reuse, c[0x0][0x160] ; /* 0x0000580003047625 */
/* 0x0c0fe200078e0208 */
/*0380*/ LDG.E R2, [R6.64] ; /* 0x0000000406027981 */
/* 0x000ea8000c1e1900 */
/*0390*/ LDG.E R11, [R4.64] ; /* 0x00000004040b7981 */
/* 0x001ea2000c1e1900 */
/*03a0*/ IMAD.WIDE R8, R3, R8, c[0x0][0x170] ; /* 0x00005c0003087625 */
/* 0x000fc800078e0208 */
/*03b0*/ IMAD.WIDE R12, R0, 0x4, R6 ; /* 0x00000004000c7825 */
/* 0x000fc800078e0206 */
/*03c0*/ FADD R19, R2, R11 ; /* 0x0000000b02137221 */
/* 0x004fe40000000000 */
/*03d0*/ IMAD.WIDE R10, R0, 0x4, R4 ; /* 0x00000004000a7825 */
/* 0x000fc600078e0204 */
/*03e0*/ STG.E [R8.64], R19 ; /* 0x0000001308007986 */
/* 0x0001e8000c101904 */
/*03f0*/ LDG.E R2, [R12.64] ; /* 0x000000040c027981 */
/* 0x000ea8000c1e1900 */
/*0400*/ LDG.E R17, [R10.64] ; /* 0x000000040a117981 */
/* 0x000ea2000c1e1900 */
/*0410*/ IMAD.WIDE R14, R0, 0x4, R8 ; /* 0x00000004000e7825 */
/* 0x000fc800078e0208 */
/*0420*/ IMAD.WIDE R6, R0, 0x4, R12 ; /* 0x0000000400067825 */
/* 0x000fc800078e020c */
/*0430*/ IMAD.WIDE R4, R0, 0x4, R10 ; /* 0x0000000400047825 */
/* 0x000fc800078e020a */
/*0440*/ FADD R21, R2, R17 ; /* 0x0000001102157221 */
/* 0x004fca0000000000 */
/*0450*/ STG.E [R14.64], R21 ; /* 0x000000150e007986 */
/* 0x0003e8000c101904 */
/*0460*/ LDG.E R2, [R6.64] ; /* 0x0000000406027981 */
/* 0x000ea8000c1e1900 */
/*0470*/ LDG.E R23, [R4.64] ; /* 0x0000000404177981 */
/* 0x000ea2000c1e1900 */
/*0480*/ IMAD.WIDE R16, R0, 0x4, R14 ; /* 0x0000000400107825 */
/* 0x000fc800078e020e */
/*0490*/ IMAD.WIDE R12, R0, 0x4, R6 ; /* 0x00000004000c7825 */
/* 0x000fc800078e0206 */
/*04a0*/ IMAD.WIDE R8, R0, 0x4, R4 ; /* 0x0000000400087825 */
/* 0x001fc800078e0204 */
/*04b0*/ FADD R23, R2, R23 ; /* 0x0000001702177221 */
/* 0x004fca0000000000 */
/*04c0*/ STG.E [R16.64], R23 ; /* 0x0000001710007986 */
/* 0x0001e8000c101904 */
/*04d0*/ LDG.E R12, [R12.64] ; /* 0x000000040c0c7981 */
/* 0x000e68000c1e1900 */
/*04e0*/ LDG.E R9, [R8.64] ; /* 0x0000000408097981 */
/* 0x000e62000c1e1900 */
/*04f0*/ IMAD.WIDE R10, R0.reuse, 0x4, R16 ; /* 0x00000004000a7825 */
/* 0x040fe200078e0210 */
/*0500*/ IADD3 R3, R0, R3, R0 ; /* 0x0000000300037210 */
/* 0x000fc80007ffe000 */
/*0510*/ IADD3 R3, R0, R3, R0 ; /* 0x0000000300037210 */
/* 0x000fc80007ffe000 */
/*0520*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x178], PT ; /* 0x00005e0003007a0c */
/* 0x000fe20003f06270 */
/*0530*/ FADD R15, R12, R9 ; /* 0x000000090c0f7221 */
/* 0x002fca0000000000 */
/*0540*/ STG.E [R10.64], R15 ; /* 0x0000000f0a007986 */
/* 0x0001ee000c101904 */
/*0550*/ @!P0 BRA 0x350 ; /* 0xfffffdf000008947 */
/* 0x000fea000383ffff */
/*0560*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0570*/ BRA 0x570; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0580*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0590*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
/*****************************************
Emitting C Generated Code
*******************************************/
/************* Functions **************/
/**************** Snippet ****************/
__global__ void x6(float* x7, float* x8, float* x9, int x10) {
int x11 = gridDim.x * blockDim.x;
int x12 = threadIdx.x + blockIdx.x * blockDim.x;
while (x12 < x10) {
int x13 = x12;
x9[x13] = x7[x13] + x8[x13];
x12 = x12 + x11;
}
} | .file "tmpxft_0014a0d9_00000000-6_x6.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z26__device_stub__Z2x6PfS_S_iPfS_S_i
.type _Z26__device_stub__Z2x6PfS_S_iPfS_S_i, @function
_Z26__device_stub__Z2x6PfS_S_iPfS_S_i:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z2x6PfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z26__device_stub__Z2x6PfS_S_iPfS_S_i, .-_Z26__device_stub__Z2x6PfS_S_iPfS_S_i
.globl _Z2x6PfS_S_i
.type _Z2x6PfS_S_i, @function
_Z2x6PfS_S_i:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z2x6PfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z2x6PfS_S_i, .-_Z2x6PfS_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z2x6PfS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z2x6PfS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
/*****************************************
Emitting C Generated Code
*******************************************/
/************* Functions **************/
/**************** Snippet ****************/
__global__ void x6(float* x7, float* x8, float* x9, int x10) {
int x11 = gridDim.x * blockDim.x;
int x12 = threadIdx.x + blockIdx.x * blockDim.x;
while (x12 < x10) {
int x13 = x12;
x9[x13] = x7[x13] + x8[x13];
x12 = x12 + x11;
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
/*****************************************
Emitting C Generated Code
*******************************************/
/************* Functions **************/
/**************** Snippet ****************/
__global__ void x6(float* x7, float* x8, float* x9, int x10) {
int x11 = gridDim.x * blockDim.x;
int x12 = threadIdx.x + blockIdx.x * blockDim.x;
while (x12 < x10) {
int x13 = x12;
x9[x13] = x7[x13] + x8[x13];
x12 = x12 + x11;
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
/*****************************************
Emitting C Generated Code
*******************************************/
/************* Functions **************/
/**************** Snippet ****************/
__global__ void x6(float* x7, float* x8, float* x9, int x10) {
int x11 = gridDim.x * blockDim.x;
int x12 = threadIdx.x + blockIdx.x * blockDim.x;
while (x12 < x10) {
int x13 = x12;
x9[x13] = x7[x13] + x8[x13];
x12 = x12 + x11;
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z2x6PfS_S_i
.globl _Z2x6PfS_S_i
.p2align 8
.type _Z2x6PfS_S_i,@function
_Z2x6PfS_S_i:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x2c
s_load_b32 s12, s[0:1], 0x18
s_add_u32 s2, s0, 32
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s8, s4, 0xffff
s_mov_b32 s4, exec_lo
v_mad_u64_u32 v[1:2], null, s15, s8, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s12, v1
s_cbranch_execz .LBB0_3
s_load_b32 s9, s[2:3], 0x0
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[2:3], s[0:1], 0x10
v_ashrrev_i32_e32 v2, 31, v1
s_mov_b32 s1, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_mul_i32 s8, s9, s8
s_ashr_i32 s9, s8, 31
s_delay_alu instid0(SALU_CYCLE_1)
s_lshl_b64 s[10:11], s[8:9], 2
.p2align 6
.LBB0_2:
s_delay_alu instid0(VALU_DEP_1)
v_add_co_u32 v4, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v3, vcc_lo
v_add_co_u32 v6, vcc_lo, s6, v2
v_add_co_ci_u32_e32 v7, vcc_lo, s7, v3, vcc_lo
global_load_b32 v0, v[4:5], off
global_load_b32 v6, v[6:7], off
v_add_nc_u32_e32 v1, s8, v1
v_add_co_u32 v4, vcc_lo, s2, v2
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v3, vcc_lo
v_add_co_u32 v2, vcc_lo, v2, s10
v_add_co_ci_u32_e32 v3, vcc_lo, s11, v3, vcc_lo
s_waitcnt vmcnt(0)
v_add_f32_e32 v0, v0, v6
v_cmp_le_i32_e64 s0, s12, v1
global_store_b32 v[4:5], v0, off
s_or_b32 s1, s0, s1
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s1
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z2x6PfS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z2x6PfS_S_i, .Lfunc_end0-_Z2x6PfS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z2x6PfS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z2x6PfS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
/*****************************************
Emitting C Generated Code
*******************************************/
/************* Functions **************/
/**************** Snippet ****************/
__global__ void x6(float* x7, float* x8, float* x9, int x10) {
int x11 = gridDim.x * blockDim.x;
int x12 = threadIdx.x + blockIdx.x * blockDim.x;
while (x12 < x10) {
int x13 = x12;
x9[x13] = x7[x13] + x8[x13];
x12 = x12 + x11;
}
} | .text
.file "x6.hip"
.globl _Z17__device_stub__x6PfS_S_i # -- Begin function _Z17__device_stub__x6PfS_S_i
.p2align 4, 0x90
.type _Z17__device_stub__x6PfS_S_i,@function
_Z17__device_stub__x6PfS_S_i: # @_Z17__device_stub__x6PfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z2x6PfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z17__device_stub__x6PfS_S_i, .Lfunc_end0-_Z17__device_stub__x6PfS_S_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z2x6PfS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z2x6PfS_S_i,@object # @_Z2x6PfS_S_i
.section .rodata,"a",@progbits
.globl _Z2x6PfS_S_i
.p2align 3, 0x0
_Z2x6PfS_S_i:
.quad _Z17__device_stub__x6PfS_S_i
.size _Z2x6PfS_S_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z2x6PfS_S_i"
.size .L__unnamed_1, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z17__device_stub__x6PfS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z2x6PfS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z2x6PfS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e280000002500 */
/*0020*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R3, R3, c[0x0][0x0], R0 ; /* 0x0000000003037a24 */
/* 0x001fca00078e0200 */
/*0040*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x178], PT ; /* 0x00005e0003007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ MOV R0, c[0x0][0x0] ; /* 0x0000000000007a02 */
/* 0x000fe20000000f00 */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0080*/ BSSY B0, 0x340 ; /* 0x000002b000007945 */
/* 0x000fe60003800000 */
/*0090*/ IMAD R0, R0, c[0x0][0xc], RZ ; /* 0x0000030000007a24 */
/* 0x000fc800078e02ff */
/*00a0*/ I2F.U32.RP R6, R0 ; /* 0x0000000000067306 */
/* 0x000e220000209000 */
/*00b0*/ IADD3 R9, RZ, -R0, RZ ; /* 0x80000000ff097210 */
/* 0x000fe40007ffe0ff */
/*00c0*/ IADD3 R2, R0.reuse, R3, RZ ; /* 0x0000000300027210 */
/* 0x040fe40007ffe0ff */
/*00d0*/ ISETP.NE.U32.AND P2, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe40003f45070 */
/*00e0*/ LOP3.LUT R7, RZ, R2, RZ, 0x33, !PT ; /* 0x00000002ff077212 */
/* 0x000fc800078e33ff */
/*00f0*/ IADD3 R7, R7, c[0x0][0x178], R0 ; /* 0x00005e0007077a10 */
/* 0x000fe20007ffe000 */
/*0100*/ MUFU.RCP R6, R6 ; /* 0x0000000600067308 */
/* 0x001e240000001000 */
/*0110*/ IADD3 R4, R6, 0xffffffe, RZ ; /* 0x0ffffffe06047810 */
/* 0x001fcc0007ffe0ff */
/*0120*/ F2I.FTZ.U32.TRUNC.NTZ R5, R4 ; /* 0x0000000400057305 */
/* 0x000064000021f000 */
/*0130*/ HFMA2.MMA R4, -RZ, RZ, 0, 0 ; /* 0x00000000ff047435 */
/* 0x001fe200000001ff */
/*0140*/ IMAD R9, R9, R5, RZ ; /* 0x0000000509097224 */
/* 0x002fd200078e02ff */
/*0150*/ IMAD.HI.U32 R2, R5, R9, R4 ; /* 0x0000000905027227 */
/* 0x000fcc00078e0004 */
/*0160*/ IMAD.HI.U32 R2, R2, R7, RZ ; /* 0x0000000702027227 */
/* 0x000fca00078e00ff */
/*0170*/ IADD3 R4, -R2, RZ, RZ ; /* 0x000000ff02047210 */
/* 0x000fca0007ffe1ff */
/*0180*/ IMAD R7, R0, R4, R7 ; /* 0x0000000400077224 */
/* 0x000fca00078e0207 */
/*0190*/ ISETP.GE.U32.AND P0, PT, R7, R0, PT ; /* 0x000000000700720c */
/* 0x000fda0003f06070 */
/*01a0*/ @P0 IADD3 R7, -R0, R7, RZ ; /* 0x0000000700070210 */
/* 0x000fe40007ffe1ff */
/*01b0*/ @P0 IADD3 R2, R2, 0x1, RZ ; /* 0x0000000102020810 */
/* 0x000fe40007ffe0ff */
/*01c0*/ ISETP.GE.U32.AND P1, PT, R7, R0, PT ; /* 0x000000000700720c */
/* 0x000fda0003f26070 */
/*01d0*/ @P1 IADD3 R2, R2, 0x1, RZ ; /* 0x0000000102021810 */
/* 0x000fe40007ffe0ff */
/*01e0*/ @!P2 LOP3.LUT R2, RZ, R0, RZ, 0x33, !PT ; /* 0x00000000ff02a212 */
/* 0x000fc800078e33ff */
/*01f0*/ IADD3 R4, R2.reuse, 0x1, RZ ; /* 0x0000000102047810 */
/* 0x040fe40007ffe0ff */
/*0200*/ ISETP.GE.U32.AND P1, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fe40003f26070 */
/*0210*/ LOP3.LUT P0, R4, R4, 0x3, RZ, 0xc0, !PT ; /* 0x0000000304047812 */
/* 0x000fda000780c0ff */
/*0220*/ @!P0 BRA 0x330 ; /* 0x0000010000008947 */
/* 0x000fea0003800000 */
/*0230*/ MOV R8, 0x4 ; /* 0x0000000400087802 */
/* 0x000fe40000000f00 */
/*0240*/ MOV R2, R4 ; /* 0x0000000400027202 */
/* 0x000fc60000000f00 */
/*0250*/ IMAD.WIDE R4, R3, R8, c[0x0][0x170] ; /* 0x00005c0003047625 */
/* 0x000fc800078e0208 */
/*0260*/ IMAD.WIDE R6, R3, R8, c[0x0][0x168] ; /* 0x00005a0003067625 */
/* 0x000fc800078e0208 */
/*0270*/ IMAD.WIDE R8, R3, R8, c[0x0][0x160] ; /* 0x0000580003087625 */
/* 0x000fc800078e0208 */
/*0280*/ LDG.E R10, [R6.64] ; /* 0x00000004060a7981 */
/* 0x0000a8000c1e1900 */
/*0290*/ LDG.E R11, [R8.64] ; /* 0x00000004080b7981 */
/* 0x0002a2000c1e1900 */
/*02a0*/ IADD3 R2, R2, -0x1, RZ ; /* 0xffffffff02027810 */
/* 0x000fe40007ffe0ff */
/*02b0*/ IADD3 R3, R0, R3, RZ ; /* 0x0000000300037210 */
/* 0x000fe40007ffe0ff */
/*02c0*/ ISETP.NE.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fe20003f05270 */
/*02d0*/ IMAD.WIDE R6, R0, 0x4, R6 ; /* 0x0000000400067825 */
/* 0x001fc800078e0206 */
/*02e0*/ IMAD.WIDE R8, R0, 0x4, R8 ; /* 0x0000000400087825 */
/* 0x002fc800078e0208 */
/*02f0*/ FADD R11, R10, R11 ; /* 0x0000000b0a0b7221 */
/* 0x004fca0000000000 */
/*0300*/ STG.E [R4.64], R11 ; /* 0x0000000b04007986 */
/* 0x0001e4000c101904 */
/*0310*/ IMAD.WIDE R4, R0, 0x4, R4 ; /* 0x0000000400047825 */
/* 0x001fe200078e0204 */
/*0320*/ @P0 BRA 0x280 ; /* 0xffffff5000000947 */
/* 0x000fea000383ffff */
/*0330*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0340*/ @!P1 EXIT ; /* 0x000000000000994d */
/* 0x000fea0003800000 */
/*0350*/ HFMA2.MMA R8, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff087435 */
/* 0x000fd400000001ff */
/*0360*/ IMAD.WIDE R6, R3, R8, c[0x0][0x168] ; /* 0x00005a0003067625 */
/* 0x000fc800078e0208 */
/*0370*/ IMAD.WIDE R4, R3.reuse, R8.reuse, c[0x0][0x160] ; /* 0x0000580003047625 */
/* 0x0c0fe200078e0208 */
/*0380*/ LDG.E R2, [R6.64] ; /* 0x0000000406027981 */
/* 0x000ea8000c1e1900 */
/*0390*/ LDG.E R11, [R4.64] ; /* 0x00000004040b7981 */
/* 0x001ea2000c1e1900 */
/*03a0*/ IMAD.WIDE R8, R3, R8, c[0x0][0x170] ; /* 0x00005c0003087625 */
/* 0x000fc800078e0208 */
/*03b0*/ IMAD.WIDE R12, R0, 0x4, R6 ; /* 0x00000004000c7825 */
/* 0x000fc800078e0206 */
/*03c0*/ FADD R19, R2, R11 ; /* 0x0000000b02137221 */
/* 0x004fe40000000000 */
/*03d0*/ IMAD.WIDE R10, R0, 0x4, R4 ; /* 0x00000004000a7825 */
/* 0x000fc600078e0204 */
/*03e0*/ STG.E [R8.64], R19 ; /* 0x0000001308007986 */
/* 0x0001e8000c101904 */
/*03f0*/ LDG.E R2, [R12.64] ; /* 0x000000040c027981 */
/* 0x000ea8000c1e1900 */
/*0400*/ LDG.E R17, [R10.64] ; /* 0x000000040a117981 */
/* 0x000ea2000c1e1900 */
/*0410*/ IMAD.WIDE R14, R0, 0x4, R8 ; /* 0x00000004000e7825 */
/* 0x000fc800078e0208 */
/*0420*/ IMAD.WIDE R6, R0, 0x4, R12 ; /* 0x0000000400067825 */
/* 0x000fc800078e020c */
/*0430*/ IMAD.WIDE R4, R0, 0x4, R10 ; /* 0x0000000400047825 */
/* 0x000fc800078e020a */
/*0440*/ FADD R21, R2, R17 ; /* 0x0000001102157221 */
/* 0x004fca0000000000 */
/*0450*/ STG.E [R14.64], R21 ; /* 0x000000150e007986 */
/* 0x0003e8000c101904 */
/*0460*/ LDG.E R2, [R6.64] ; /* 0x0000000406027981 */
/* 0x000ea8000c1e1900 */
/*0470*/ LDG.E R23, [R4.64] ; /* 0x0000000404177981 */
/* 0x000ea2000c1e1900 */
/*0480*/ IMAD.WIDE R16, R0, 0x4, R14 ; /* 0x0000000400107825 */
/* 0x000fc800078e020e */
/*0490*/ IMAD.WIDE R12, R0, 0x4, R6 ; /* 0x00000004000c7825 */
/* 0x000fc800078e0206 */
/*04a0*/ IMAD.WIDE R8, R0, 0x4, R4 ; /* 0x0000000400087825 */
/* 0x001fc800078e0204 */
/*04b0*/ FADD R23, R2, R23 ; /* 0x0000001702177221 */
/* 0x004fca0000000000 */
/*04c0*/ STG.E [R16.64], R23 ; /* 0x0000001710007986 */
/* 0x0001e8000c101904 */
/*04d0*/ LDG.E R12, [R12.64] ; /* 0x000000040c0c7981 */
/* 0x000e68000c1e1900 */
/*04e0*/ LDG.E R9, [R8.64] ; /* 0x0000000408097981 */
/* 0x000e62000c1e1900 */
/*04f0*/ IMAD.WIDE R10, R0.reuse, 0x4, R16 ; /* 0x00000004000a7825 */
/* 0x040fe200078e0210 */
/*0500*/ IADD3 R3, R0, R3, R0 ; /* 0x0000000300037210 */
/* 0x000fc80007ffe000 */
/*0510*/ IADD3 R3, R0, R3, R0 ; /* 0x0000000300037210 */
/* 0x000fc80007ffe000 */
/*0520*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x178], PT ; /* 0x00005e0003007a0c */
/* 0x000fe20003f06270 */
/*0530*/ FADD R15, R12, R9 ; /* 0x000000090c0f7221 */
/* 0x002fca0000000000 */
/*0540*/ STG.E [R10.64], R15 ; /* 0x0000000f0a007986 */
/* 0x0001ee000c101904 */
/*0550*/ @!P0 BRA 0x350 ; /* 0xfffffdf000008947 */
/* 0x000fea000383ffff */
/*0560*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0570*/ BRA 0x570; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0580*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0590*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z2x6PfS_S_i
.globl _Z2x6PfS_S_i
.p2align 8
.type _Z2x6PfS_S_i,@function
_Z2x6PfS_S_i:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x2c
s_load_b32 s12, s[0:1], 0x18
s_add_u32 s2, s0, 32
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s8, s4, 0xffff
s_mov_b32 s4, exec_lo
v_mad_u64_u32 v[1:2], null, s15, s8, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s12, v1
s_cbranch_execz .LBB0_3
s_load_b32 s9, s[2:3], 0x0
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[2:3], s[0:1], 0x10
v_ashrrev_i32_e32 v2, 31, v1
s_mov_b32 s1, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_mul_i32 s8, s9, s8
s_ashr_i32 s9, s8, 31
s_delay_alu instid0(SALU_CYCLE_1)
s_lshl_b64 s[10:11], s[8:9], 2
.p2align 6
.LBB0_2:
s_delay_alu instid0(VALU_DEP_1)
v_add_co_u32 v4, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v3, vcc_lo
v_add_co_u32 v6, vcc_lo, s6, v2
v_add_co_ci_u32_e32 v7, vcc_lo, s7, v3, vcc_lo
global_load_b32 v0, v[4:5], off
global_load_b32 v6, v[6:7], off
v_add_nc_u32_e32 v1, s8, v1
v_add_co_u32 v4, vcc_lo, s2, v2
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v3, vcc_lo
v_add_co_u32 v2, vcc_lo, v2, s10
v_add_co_ci_u32_e32 v3, vcc_lo, s11, v3, vcc_lo
s_waitcnt vmcnt(0)
v_add_f32_e32 v0, v0, v6
v_cmp_le_i32_e64 s0, s12, v1
global_store_b32 v[4:5], v0, off
s_or_b32 s1, s0, s1
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s1
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z2x6PfS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z2x6PfS_S_i, .Lfunc_end0-_Z2x6PfS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z2x6PfS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z2x6PfS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0014a0d9_00000000-6_x6.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z26__device_stub__Z2x6PfS_S_iPfS_S_i
.type _Z26__device_stub__Z2x6PfS_S_iPfS_S_i, @function
_Z26__device_stub__Z2x6PfS_S_iPfS_S_i:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z2x6PfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z26__device_stub__Z2x6PfS_S_iPfS_S_i, .-_Z26__device_stub__Z2x6PfS_S_iPfS_S_i
.globl _Z2x6PfS_S_i
.type _Z2x6PfS_S_i, @function
_Z2x6PfS_S_i:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z2x6PfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z2x6PfS_S_i, .-_Z2x6PfS_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z2x6PfS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z2x6PfS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "x6.hip"
.globl _Z17__device_stub__x6PfS_S_i # -- Begin function _Z17__device_stub__x6PfS_S_i
.p2align 4, 0x90
.type _Z17__device_stub__x6PfS_S_i,@function
_Z17__device_stub__x6PfS_S_i: # @_Z17__device_stub__x6PfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z2x6PfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z17__device_stub__x6PfS_S_i, .Lfunc_end0-_Z17__device_stub__x6PfS_S_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z2x6PfS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z2x6PfS_S_i,@object # @_Z2x6PfS_S_i
.section .rodata,"a",@progbits
.globl _Z2x6PfS_S_i
.p2align 3, 0x0
_Z2x6PfS_S_i:
.quad _Z17__device_stub__x6PfS_S_i
.size _Z2x6PfS_S_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z2x6PfS_S_i"
.size .L__unnamed_1, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z17__device_stub__x6PfS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z2x6PfS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void cuda_graph_maxpool_bprop(float* gradInput, const float *gradOutput, const float* indices, const int nClusters, const int dim, const int nClustersPerThread) {
extern __shared__ float shared_mem[];
float* gradOutput_data = (float*)shared_mem;
float* indices_data = (float*)&gradOutput_data[nClusters];
const int tidx = threadIdx.x;
gradInput += blockIdx.x * dim;
gradOutput += blockIdx.x * nClusters;
indices += blockIdx.x * nClusters;
__syncthreads();
for (int i = 0; i < nClustersPerThread; ++i) {
int idx = tidx + i*blockDim.x;
if (idx < nClusters) {
gradOutput_data[idx] = gradOutput[idx];
indices_data[idx] = indices[idx];
}
}
__syncthreads();
//ouch...
if (tidx == 1) {
for (int i = 0; i < nClusters; ++i) {
gradInput[(int)indices_data[i]-1] += gradOutput[i];
}
}
//gradInput[(int)indices_data[tidx]-1] = gradOutput[tidx];
} | code for sm_80
Function : _Z24cuda_graph_maxpool_bpropPfPKfS1_iii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2UR UR6, SR_CTAID.X ; /* 0x00000000000679c3 */
/* 0x000e220000002500 */
/*0020*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e620000002100 */
/*0030*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x180] ; /* 0x00006000ff027624 */
/* 0x000fe200078e00ff */
/*0040*/ ULDC.64 UR4, c[0x0][0x178] ; /* 0x00005e0000047ab9 */
/* 0x000fe40000000a00 */
/*0050*/ ULDC.64 UR14, c[0x0][0x118] ; /* 0x00004600000e7ab9 */
/* 0x000fe20000000a00 */
/*0060*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0070*/ ISETP.GE.AND P0, PT, R2, 0x1, PT ; /* 0x000000010200780c */
/* 0x000fe20003f06270 */
/*0080*/ UIMAD UR5, UR6, UR5, URZ ; /* 0x00000005060572a4 */
/* 0x001fe4000f8e023f */
/*0090*/ UIMAD UR6, UR6, UR4, URZ ; /* 0x00000004060672a4 */
/* 0x000fd4000f8e023f */
/*00a0*/ @!P0 BRA 0x7d0 ; /* 0x0000072000008947 */
/* 0x000fea0003800000 */
/*00b0*/ IADD3 R3, R2.reuse, -0x1, RZ ; /* 0xffffffff02037810 */
/* 0x042fe20007ffe0ff */
/*00c0*/ IMAD.MOV.U32 R7, RZ, RZ, RZ ; /* 0x000000ffff077224 */
/* 0x000fe200078e00ff */
/*00d0*/ LOP3.LUT R2, R2, 0x3, RZ, 0xc0, !PT ; /* 0x0000000302027812 */
/* 0x000fe400078ec0ff */
/*00e0*/ ISETP.GE.U32.AND P1, PT, R3, 0x3, PT ; /* 0x000000030300780c */
/* 0x000fe40003f26070 */
/*00f0*/ ISETP.NE.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fd60003f05270 */
/*0100*/ @!P1 BRA 0x620 ; /* 0x0000051000009947 */
/* 0x000fea0003800000 */
/*0110*/ IMAD.SHL.U32 R4, R0.reuse, 0x4, RZ ; /* 0x0000000400047824 */
/* 0x040fe200078e00ff */
/*0120*/ IADD3 R5, R0, c[0x0][0x0], RZ ; /* 0x0000000000057a10 */
/* 0x000fe20007ffe0ff */
/*0130*/ IMAD.MOV.U32 R11, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff0b7624 */
/* 0x000fe200078e00ff */
/*0140*/ IADD3 R26, R2, -c[0x0][0x180], RZ ; /* 0x80006000021a7a10 */
/* 0x000fe20007ffe0ff */
/*0150*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fe200078e00ff */
/*0160*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*0170*/ IMAD R19, R11.reuse, 0x2, R0 ; /* 0x000000020b137824 */
/* 0x040fe400078e0200 */
/*0180*/ IMAD R9, R11.reuse, 0x8, R4 ; /* 0x000000080b097824 */
/* 0x040fe400078e0204 */
/*0190*/ IMAD R8, R11, 0x3, R0 ; /* 0x000000030b087824 */
/* 0x000fc400078e0200 */
/*01a0*/ IMAD R24, R3, c[0x0][0x0], R4.reuse ; /* 0x0000000003187a24 */
/* 0x100fe400078e0204 */
/*01b0*/ IMAD R11, R11, 0xc, R4.reuse ; /* 0x0000000c0b0b7824 */
/* 0x100fe400078e0204 */
/*01c0*/ IMAD R18, R3.reuse, c[0x0][0x178], R4 ; /* 0x00005e0003127a24 */
/* 0x040fe400078e0204 */
/*01d0*/ IMAD R24, R3.reuse, c[0x0][0x178], R24 ; /* 0x00005e0003187a24 */
/* 0x040fe400078e0218 */
/*01e0*/ IMAD R25, R3, c[0x0][0x178], R9 ; /* 0x00005e0003197a24 */
/* 0x000fe400078e0209 */
/*01f0*/ IMAD.MOV.U32 R7, RZ, RZ, RZ ; /* 0x000000ffff077224 */
/* 0x000fc400078e00ff */
/*0200*/ IMAD.MOV.U32 R10, RZ, RZ, R0 ; /* 0x000000ffff0a7224 */
/* 0x000fe400078e0000 */
/*0210*/ IMAD.MOV.U32 R6, RZ, RZ, R5 ; /* 0x000000ffff067224 */
/* 0x000fe400078e0005 */
/*0220*/ IMAD R3, R3, c[0x0][0x178], R11 ; /* 0x00005e0003037a24 */
/* 0x000fe400078e020b */
/*0230*/ ISETP.GE.AND P1, PT, R10, c[0x0][0x178], PT ; /* 0x00005e000a007a0c */
/* 0x000fe40003f26270 */
/*0240*/ ISETP.GE.AND P3, PT, R6, c[0x0][0x178], PT ; /* 0x00005e0006007a0c */
/* 0x000fe40003f66270 */
/*0250*/ ISETP.GE.AND P2, PT, R19, c[0x0][0x178], PT ; /* 0x00005e0013007a0c */
/* 0x000fd20003f46270 */
/*0260*/ @!P1 IADD3 R15, P4, R10, UR6, RZ ; /* 0x000000060a0f9c10 */
/* 0x000fe4000ff9e0ff */
/*0270*/ @!P3 IADD3 R12, P5, R6, UR6, RZ ; /* 0x00000006060cbc10 */
/* 0x000fe4000ffbe0ff */
/*0280*/ @!P1 LEA.HI.X.SX32 R14, R10, RZ, 0x1, P4 ; /* 0x000000ff0a0e9211 */
/* 0x001fe200020f0eff */
/*0290*/ @!P1 IMAD.SHL.U32 R22, R15.reuse, 0x4, RZ ; /* 0x000000040f169824 */
/* 0x040fe200078e00ff */
/*02a0*/ @!P3 LEA.HI.X.SX32 R13, R6, RZ, 0x1, P5 ; /* 0x000000ff060db211 */
/* 0x000fe400028f0eff */
/*02b0*/ @!P1 SHF.L.U64.HI R15, R15, 0x2, R14 ; /* 0x000000020f0f9819 */
/* 0x000fe4000001020e */
/*02c0*/ @!P3 SHF.L.U64.HI R13, R12.reuse, 0x2, R13 ; /* 0x000000020c0db819 */
/* 0x040fe2000001020d */
/*02d0*/ @!P3 IMAD.SHL.U32 R12, R12, 0x4, RZ ; /* 0x000000040c0cb824 */
/* 0x000fe200078e00ff */
/*02e0*/ @!P1 IADD3 R16, P4, R22, c[0x0][0x168], RZ ; /* 0x00005a0016109a10 */
/* 0x000fc40007f9e0ff */
/*02f0*/ @!P1 IADD3 R22, P5, R22, c[0x0][0x170], RZ ; /* 0x00005c0016169a10 */
/* 0x000fe40007fbe0ff */
/*0300*/ @!P1 IADD3.X R17, R15, c[0x0][0x16c], RZ, P4, !PT ; /* 0x00005b000f119a10 */
/* 0x000fe400027fe4ff */
/*0310*/ @!P2 IADD3 R14, P6, R19, UR6, RZ ; /* 0x00000006130eac10 */
/* 0x000fe4000ffde0ff */
/*0320*/ @!P3 IADD3 R20, P4, R12, c[0x0][0x168], RZ ; /* 0x00005a000c14ba10 */
/* 0x000fe20007f9e0ff */
/*0330*/ @!P1 LDG.E R27, [R16.64] ; /* 0x0000000e101b9981 */
/* 0x0000a2000c1e1900 */
/*0340*/ @!P1 IADD3.X R23, R15, c[0x0][0x174], RZ, P5, !PT ; /* 0x00005d000f179a10 */
/* 0x000fe40002ffe4ff */
/*0350*/ @!P2 LEA.HI.X.SX32 R15, R19, RZ, 0x1, P6 ; /* 0x000000ff130fa211 */
/* 0x000fc400030f0eff */
/*0360*/ @!P3 IADD3.X R21, R13, c[0x0][0x16c], RZ, P4, !PT ; /* 0x00005b000d15ba10 */
/* 0x000fe200027fe4ff */
/*0370*/ @!P1 LDG.E R29, [R22.64] ; /* 0x0000000e161d9981 */
/* 0x0002e2000c1e1900 */
/*0380*/ ISETP.GE.AND P4, PT, R8, c[0x0][0x178], PT ; /* 0x00005e0008007a0c */
/* 0x000fe40003f86270 */
/*0390*/ @!P2 SHF.L.U64.HI R17, R14.reuse, 0x2, R15 ; /* 0x000000020e11a819 */
/* 0x041fe2000001020f */
/*03a0*/ @!P2 IMAD.SHL.U32 R15, R14, 0x4, RZ ; /* 0x000000040e0fa824 */
/* 0x000fe200078e00ff */
/*03b0*/ @!P3 IADD3 R12, P6, R12, c[0x0][0x170], RZ ; /* 0x00005c000c0cba10 */
/* 0x000fe20007fde0ff */
/*03c0*/ @!P3 LDG.E R28, [R20.64] ; /* 0x0000000e141cb981 */
/* 0x000126000c1e1900 */
/*03d0*/ @!P2 IADD3 R14, P5, R15, c[0x0][0x168], RZ ; /* 0x00005a000f0eaa10 */
/* 0x000fc40007fbe0ff */
/*03e0*/ @!P3 IADD3.X R13, R13, c[0x0][0x174], RZ, P6, !PT ; /* 0x00005d000d0dba10 */
/* 0x000fe400037fe4ff */
/*03f0*/ @!P2 IADD3 R16, P6, R15, c[0x0][0x170], RZ ; /* 0x00005c000f10aa10 */
/* 0x000fe40007fde0ff */
/*0400*/ @!P2 IADD3.X R15, R17, c[0x0][0x16c], RZ, P5, !PT ; /* 0x00005b00110faa10 */
/* 0x000fe40002ffe4ff */
/*0410*/ @!P4 IADD3 R23, P5, R8.reuse, UR6, RZ ; /* 0x000000060817cc10 */
/* 0x042fe2000ffbe0ff */
/*0420*/ @!P3 LDG.E R13, [R12.64] ; /* 0x0000000e0c0db981 */
/* 0x000368000c1e1900 */
/*0430*/ @!P4 IMAD.SHL.U32 R22, R23, 0x4, RZ ; /* 0x000000041716c824 */
/* 0x000fe200078e00ff */
/*0440*/ @!P2 IADD3.X R17, R17, c[0x0][0x174], RZ, P6, !PT ; /* 0x00005d001111aa10 */
/* 0x000fe200037fe4ff */
/*0450*/ @!P2 LDG.E R14, [R14.64] ; /* 0x0000000e0e0ea981 */
/* 0x000162000c1e1900 */
/*0460*/ @!P4 LEA.HI.X.SX32 R12, R8, RZ, 0x1, P5 ; /* 0x000000ff080cc211 */
/* 0x002fc600028f0eff */
/*0470*/ @!P2 LDG.E R16, [R16.64] ; /* 0x0000000e1010a981 */
/* 0x000f62000c1e1900 */
/*0480*/ @!P4 IADD3 R20, P5, R22.reuse, c[0x0][0x168], RZ ; /* 0x00005a001614ca10 */
/* 0x041fe40007fbe0ff */
/*0490*/ @!P4 SHF.L.U64.HI R23, R23, 0x2, R12 ; /* 0x000000021717c819 */
/* 0x000fe4000001020c */
/*04a0*/ @!P4 IADD3 R22, P6, R22, c[0x0][0x170], RZ ; /* 0x00005c001616ca10 */
/* 0x000fe40007fde0ff */
/*04b0*/ @!P4 IADD3.X R21, R23.reuse, c[0x0][0x16c], RZ, P5, !PT ; /* 0x00005b001715ca10 */
/* 0x040fe40002ffe4ff */
/*04c0*/ @!P4 IADD3.X R23, R23, c[0x0][0x174], RZ, P6, !PT ; /* 0x00005d001717ca10 */
/* 0x000fc600037fe4ff */
/*04d0*/ @!P4 LDG.E R20, [R20.64] ; /* 0x0000000e1414c981 */
/* 0x000f68000c1e1900 */
/*04e0*/ @!P4 LDG.E R22, [R22.64] ; /* 0x0000000e1616c981 */
/* 0x000f62000c1e1900 */
/*04f0*/ IADD3 R26, R26, 0x4, RZ ; /* 0x000000041a1a7810 */
/* 0x000fe20007ffe0ff */
/*0500*/ ULDC UR7, c[0x0][0x0] ; /* 0x0000000000077ab9 */
/* 0x000fe20000000800 */
/*0510*/ IMAD.MOV.U32 R15, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff0f7624 */
/* 0x000fe200078e00ff */
/*0520*/ IADD3 R7, R7, 0x4, RZ ; /* 0x0000000407077810 */
/* 0x000fc60007ffe0ff */
/*0530*/ IMAD R6, R15.reuse, 0x4, R6 ; /* 0x000000040f067824 */
/* 0x040fe400078e0206 */
/*0540*/ IMAD R19, R15.reuse, 0x4, R19 ; /* 0x000000040f137824 */
/* 0x040fe400078e0213 */
/*0550*/ IMAD R8, R15.reuse, 0x4, R8 ; /* 0x000000040f087824 */
/* 0x040fe400078e0208 */
/*0560*/ IMAD R10, R15, 0x4, R10 ; /* 0x000000040f0a7824 */
/* 0x000fe200078e020a */
/*0570*/ @!P1 STS [R4+UR4], R27 ; /* 0x0000001b04009988 */
/* 0x0041e80008000804 */
/*0580*/ @!P1 STS [R18+UR4], R29 ; /* 0x0000001d12009988 */
/* 0x0081e20008000804 */
/*0590*/ ISETP.NE.AND P1, PT, R26, RZ, PT ; /* 0x000000ff1a00720c */
/* 0x000fc60003f25270 */
/*05a0*/ @!P3 STS [R5.X4+UR4], R28 ; /* 0x0000001c0500b988 */
/* 0x0101e80008004804 */
/*05b0*/ @!P3 STS [R24+UR4], R13 ; /* 0x0000000d1800b988 */
/* 0x0201e80008000804 */
/*05c0*/ @!P2 STS [R9+UR4], R14 ; /* 0x0000000e0900a988 */
/* 0x0001e80008000804 */
/*05d0*/ @!P2 STS [R25+UR4], R16 ; /* 0x000000101900a988 */
/* 0x0001e80008000804 */
/*05e0*/ @!P4 STS [R11+UR4], R20 ; /* 0x000000140b00c988 */
/* 0x0001e80008000804 */
/*05f0*/ @!P4 STS [R3+UR4], R22 ; /* 0x000000160300c988 */
/* 0x0001e20008000804 */
/*0600*/ ULEA UR4, UR7, UR4, 0x4 ; /* 0x0000000407047291 */
/* 0x000fe2000f8e203f */
/*0610*/ @P1 BRA 0x230 ; /* 0xfffffc1000001947 */
/* 0x000fea000383ffff */
/*0620*/ NOP ; /* 0x0000000000007918 */
/* 0x000fc20000000000 */
/*0630*/ @!P0 BRA 0x7d0 ; /* 0x0000019000008947 */
/* 0x000fea0003800000 */
/*0640*/ IADD3 R4, R0, c[0x0][0x178], RZ ; /* 0x00005e0000047a10 */
/* 0x001fe20007ffe0ff */
/*0650*/ IMAD R8, R7, c[0x0][0x0], R0 ; /* 0x0000000007087a24 */
/* 0x000fc800078e0200 */
/*0660*/ IMAD R4, R7, c[0x0][0x0], R4 ; /* 0x0000000007047a24 */
/* 0x000fe400078e0204 */
/*0670*/ IMAD.SHL.U32 R9, R8, 0x4, RZ ; /* 0x0000000408097824 */
/* 0x000fe400078e00ff */
/*0680*/ IMAD.SHL.U32 R3, R4, 0x4, RZ ; /* 0x0000000404037824 */
/* 0x000fe400078e00ff */
/*0690*/ ISETP.GE.AND P0, PT, R8, c[0x0][0x178], PT ; /* 0x00005e0008007a0c */
/* 0x000fda0003f06270 */
/*06a0*/ @!P0 IADD3 R7, P1, R8, UR6, RZ ; /* 0x0000000608078c10 */
/* 0x000fc8000ff3e0ff */
/*06b0*/ @!P0 LEA.HI.X.SX32 R4, R8, RZ, 0x1, P1 ; /* 0x000000ff08048211 */
/* 0x000fe200008f0eff */
/*06c0*/ @!P0 IMAD.SHL.U32 R6, R7, 0x4, RZ ; /* 0x0000000407068824 */
/* 0x000fc600078e00ff */
/*06d0*/ @!P0 SHF.L.U64.HI R7, R7, 0x2, R4 ; /* 0x0000000207078819 */
/* 0x000fe40000010204 */
/*06e0*/ @!P0 IADD3 R4, P1, R6.reuse, c[0x0][0x168], RZ ; /* 0x00005a0006048a10 */
/* 0x040fe40007f3e0ff */
/*06f0*/ @!P0 IADD3 R6, P2, R6, c[0x0][0x170], RZ ; /* 0x00005c0006068a10 */
/* 0x000fe40007f5e0ff */
/*0700*/ @!P0 IADD3.X R5, R7.reuse, c[0x0][0x16c], RZ, P1, !PT ; /* 0x00005b0007058a10 */
/* 0x040fe40000ffe4ff */
/*0710*/ @!P0 IADD3.X R7, R7, c[0x0][0x174], RZ, P2, !PT ; /* 0x00005d0007078a10 */
/* 0x000fc600017fe4ff */
/*0720*/ @!P0 LDG.E R4, [R4.64] ; /* 0x0000000e04048981 */
/* 0x000ea8000c1e1900 */
/*0730*/ @!P0 LDG.E R6, [R6.64] ; /* 0x0000000e06068981 */
/* 0x000ee2000c1e1900 */
/*0740*/ IADD3 R2, R2, -0x1, RZ ; /* 0xffffffff02027810 */
/* 0x000fe20007ffe0ff */
/*0750*/ IMAD.MOV.U32 R10, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff0a7624 */
/* 0x000fe200078e00ff */
/*0760*/ IADD3 R8, R8, c[0x0][0x0], RZ ; /* 0x0000000008087a10 */
/* 0x000fe20007ffe0ff */
/*0770*/ @!P0 STS [R9], R4 ; /* 0x0000000409008388 */
/* 0x0041e80000000800 */
/*0780*/ @!P0 STS [R3], R6 ; /* 0x0000000603008388 */
/* 0x0083e20000000800 */
/*0790*/ ISETP.NE.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fe20003f05270 */
/*07a0*/ IMAD R9, R10, 0x4, R9 ; /* 0x000000040a097824 */
/* 0x001fc400078e0209 */
/*07b0*/ IMAD R3, R10, 0x4, R3 ; /* 0x000000040a037824 */
/* 0x002fd400078e0203 */
/*07c0*/ @P0 BRA 0x690 ; /* 0xfffffec000000947 */
/* 0x000fea000383ffff */
/*07d0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x002fe20000010000 */
/*07e0*/ IMAD.MOV.U32 R2, RZ, RZ, 0x1 ; /* 0x00000001ff027424 */
/* 0x000fca00078e00ff */
/*07f0*/ ISETP.LE.AND P0, PT, R2, c[0x0][0x178], PT ; /* 0x00005e0002007a0c */
/* 0x000fc80003f03270 */
/*0800*/ ISETP.NE.OR P0, PT, R0, 0x1, !P0 ; /* 0x000000010000780c */
/* 0x000fda0004705670 */
/*0810*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0820*/ IMAD.MOV.U32 R0, RZ, RZ, 0x1 ; /* 0x00000001ff007424 */
/* 0x000fe200078e00ff */
/*0830*/ UMOV UR7, 0x3 ; /* 0x0000000300077882 */
/* 0x000fe40000000000 */
/*0840*/ ULDC UR8, c[0x0][0x178] ; /* 0x00005e0000087ab9 */
/* 0x000fe40000000800 */
/*0850*/ IADD3 R0, -R0, c[0x0][0x178], RZ ; /* 0x00005e0000007a10 */
/* 0x000fe20007ffe1ff */
/*0860*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe40008000000 */
/*0870*/ ULOP3.LUT UR7, UR7, UR8, URZ, 0xc0, !UPT ; /* 0x0000000807077292 */
/* 0x000fe2000f8ec03f */
/*0880*/ ISETP.GE.U32.AND P0, PT, R0, 0x3, PT ; /* 0x000000030000780c */
/* 0x000fda0003f06070 */
/*0890*/ @!P0 BRA 0xcb0 ; /* 0x0000041000008947 */
/* 0x000fea0003800000 */
/*08a0*/ ULDC.64 UR8, c[0x0][0x168] ; /* 0x00005a0000087ab9 */
/* 0x000fe40000000a00 */
/*08b0*/ ULEA UR4, UP0, UR6, UR8, 0x2 ; /* 0x0000000806047291 */
/* 0x000fe4000f80103f */
/*08c0*/ ULDC UR10, c[0x0][0x178] ; /* 0x00005e00000a7ab9 */
/* 0x000fe40000000800 */
/*08d0*/ ULEA.HI.X UR9, UR6, UR9, URZ, 0x2, UP0 ; /* 0x0000000906097291 */
/* 0x000fe400080f143f */
/*08e0*/ UIADD3 UR4, UP0, UR4, 0x8, URZ ; /* 0x0000000804047890 */
/* 0x000fe4000ff1e03f */
/*08f0*/ UMOV UR8, 0x4 ; /* 0x0000000400087882 */
/* 0x000fc40000000000 */
/*0900*/ UIADD3.X UR9, URZ, UR9, URZ, UP0, !UPT ; /* 0x000000093f097290 */
/* 0x000fe400087fe43f */
/*0910*/ IMAD.U32 R6, RZ, RZ, UR4 ; /* 0x00000004ff067e24 */
/* 0x000fe2000f8e00ff */
/*0920*/ UIADD3 UR11, -UR7, UR10, URZ ; /* 0x0000000a070b7290 */
/* 0x000fe4000fffe13f */
/*0930*/ UIMAD UR8, UR8, UR10, 0x8 ; /* 0x00000008080874a4 */
/* 0x000fe2000f8e020a */
/*0940*/ IMAD.U32 R13, RZ, RZ, UR9 ; /* 0x00000009ff0d7e24 */
/* 0x001fe2000f8e00ff */
/*0950*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fce0008000000 */
/*0960*/ LDS R0, [UR8+-0x8] ; /* 0xfffff808ff007984 */
/* 0x001e280008000800 */
/*0970*/ LDS R10, [UR8+-0x4] ; /* 0xfffffc08ff0a7984 */
/* 0x000e680008000800 */
/*0980*/ LDS R12, [UR8] ; /* 0x00000008ff0c7984 */
/* 0x000ea20008000800 */
/*0990*/ F2I.TRUNC.NTZ R0, R0 ; /* 0x0000000000007305 */
/* 0x001e24000020f100 */
/*09a0*/ IADD3 R2, R0, -0x1, RZ ; /* 0xffffffff00027810 */
/* 0x001fc80007ffe0ff */
/*09b0*/ IADD3 R3, P0, R2, UR5, RZ ; /* 0x0000000502037c10 */
/* 0x000fc8000ff1e0ff */
/*09c0*/ LEA.HI.X.SX32 R2, R2, RZ, 0x1, P0 ; /* 0x000000ff02027211 */
/* 0x000fe400000f0eff */
/*09d0*/ LEA R8, P0, R3, c[0x0][0x160], 0x2 ; /* 0x0000580003087a11 */
/* 0x000fc800078010ff */
/*09e0*/ LEA.HI.X R9, R3, c[0x0][0x164], R2, 0x2, P0 ; /* 0x0000590003097a11 */
/* 0x000fe200000f1402 */
/*09f0*/ IMAD.MOV.U32 R2, RZ, RZ, R6 ; /* 0x000000ffff027224 */
/* 0x000fe400078e0006 */
/*0a00*/ IMAD.MOV.U32 R3, RZ, RZ, R13 ; /* 0x000000ffff037224 */
/* 0x000fe400078e000d */
/*0a10*/ LDG.E R4, [R8.64] ; /* 0x0000000e08047981 */
/* 0x000ee8000c1e1900 */
/*0a20*/ LDG.E R5, [R2.64+-0x8] ; /* 0xfffff80e02057981 */
/* 0x000ee2000c1e1900 */
/*0a30*/ F2I.TRUNC.NTZ R10, R10 ; /* 0x0000000a000a7305 */
/* 0x002e24000020f100 */
/*0a40*/ IADD3 R0, R10, -0x1, RZ ; /* 0xffffffff0a007810 */
/* 0x001fc80007ffe0ff */
/*0a50*/ IADD3 R7, P0, R0, UR5, RZ ; /* 0x0000000500077c10 */
/* 0x000fc8000ff1e0ff */
/*0a60*/ LEA.HI.X.SX32 R0, R0, RZ, 0x1, P0 ; /* 0x000000ff00007211 */
/* 0x000fe400000f0eff */
/*0a70*/ LEA R6, P0, R7, c[0x0][0x160], 0x2 ; /* 0x0000580007067a11 */
/* 0x000fc800078010ff */
/*0a80*/ LEA.HI.X R7, R7, c[0x0][0x164], R0, 0x2, P0 ; /* 0x0000590007077a11 */
/* 0x000fe200000f1400 */
/*0a90*/ FADD R11, R4, R5 ; /* 0x00000005040b7221 */
/* 0x008fca0000000000 */
/*0aa0*/ STG.E [R8.64], R11 ; /* 0x0000000b08007986 */
/* 0x0001e8000c10190e */
/*0ab0*/ LDG.E R13, [R2.64+-0x4] ; /* 0xfffffc0e020d7981 */
/* 0x000ee8000c1e1900 */
/*0ac0*/ LDG.E R0, [R6.64] ; /* 0x0000000e06007981 */
/* 0x000ee2000c1e1900 */
/*0ad0*/ F2I.TRUNC.NTZ R12, R12 ; /* 0x0000000c000c7305 */
/* 0x004e64000020f100 */
/*0ae0*/ IADD3 R4, R12, -0x1, RZ ; /* 0xffffffff0c047810 */
/* 0x002fc80007ffe0ff */
/*0af0*/ IADD3 R5, P0, R4, UR5, RZ ; /* 0x0000000504057c10 */
/* 0x000fc8000ff1e0ff */
/*0b00*/ LEA.HI.X.SX32 R10, R4, RZ, 0x1, P0 ; /* 0x000000ff040a7211 */
/* 0x000fe400000f0eff */
/*0b10*/ LEA R4, P0, R5, c[0x0][0x160], 0x2 ; /* 0x0000580005047a11 */
/* 0x000fc800078010ff */
/*0b20*/ LEA.HI.X R5, R5, c[0x0][0x164], R10, 0x2, P0 ; /* 0x0000590005057a11 */
/* 0x000fe400000f140a */
/*0b30*/ LDS R10, [UR8+0x4] ; /* 0x00000408ff0a7984 */
/* 0x000e620008000800 */
/*0b40*/ FADD R13, R0, R13 ; /* 0x0000000d000d7221 */
/* 0x008fca0000000000 */
/*0b50*/ STG.E [R6.64], R13 ; /* 0x0000000d06007986 */
/* 0x0005e8000c10190e */
/*0b60*/ LDG.E R11, [R2.64] ; /* 0x0000000e020b7981 */
/* 0x001ee8000c1e1900 */
/*0b70*/ LDG.E R0, [R4.64] ; /* 0x0000000e04007981 */
/* 0x000ee2000c1e1900 */
/*0b80*/ F2I.TRUNC.NTZ R10, R10 ; /* 0x0000000a000a7305 */
/* 0x002e24000020f100 */
/*0b90*/ IADD3 R8, R10, -0x1, RZ ; /* 0xffffffff0a087810 */
/* 0x001fc80007ffe0ff */
/*0ba0*/ IADD3 R9, P0, R8, UR5, RZ ; /* 0x0000000508097c10 */
/* 0x000fc8000ff1e0ff */
/*0bb0*/ LEA.HI.X.SX32 R12, R8, RZ, 0x1, P0 ; /* 0x000000ff080c7211 */
/* 0x000fe400000f0eff */
/*0bc0*/ LEA R8, P0, R9, c[0x0][0x160], 0x2 ; /* 0x0000580009087a11 */
/* 0x000fc800078010ff */
/*0bd0*/ LEA.HI.X R9, R9, c[0x0][0x164], R12, 0x2, P0 ; /* 0x0000590009097a11 */
/* 0x000fe200000f140c */
/*0be0*/ FADD R11, R0, R11 ; /* 0x0000000b000b7221 */
/* 0x008fca0000000000 */
/*0bf0*/ STG.E [R4.64], R11 ; /* 0x0000000b04007986 */
/* 0x0001e8000c10190e */
/*0c00*/ LDG.E R7, [R2.64+0x4] ; /* 0x0000040e02077981 */
/* 0x004ea8000c1e1900 */
/*0c10*/ LDG.E R0, [R8.64] ; /* 0x0000000e08007981 */
/* 0x000ea2000c1e1900 */
/*0c20*/ UIADD3 UR11, UR11, -0x4, URZ ; /* 0xfffffffc0b0b7890 */
/* 0x000fcc000fffe03f */
/*0c30*/ ISETP.NE.AND P0, PT, RZ, UR11, PT ; /* 0x0000000bff007c0c */
/* 0x000fe4000bf05270 */
/*0c40*/ IADD3 R6, P1, R2, 0x10, RZ ; /* 0x0000001002067810 */
/* 0x000fe20007f3e0ff */
/*0c50*/ UIADD3 UR4, UR4, 0x4, URZ ; /* 0x0000000404047890 */
/* 0x000fe4000fffe03f */
/*0c60*/ UIADD3 UR8, UR8, 0x10, URZ ; /* 0x0000001008087890 */
/* 0x000fe4000fffe03f */
/*0c70*/ IMAD.X R13, RZ, RZ, R3, P1 ; /* 0x000000ffff0d7224 */
/* 0x000fe400008e0603 */
/*0c80*/ FADD R7, R0, R7 ; /* 0x0000000700077221 */
/* 0x004fca0000000000 */
/*0c90*/ STG.E [R8.64], R7 ; /* 0x0000000708007986 */
/* 0x0001e2000c10190e */
/*0ca0*/ @P0 BRA 0x960 ; /* 0xfffffcb000000947 */
/* 0x000fea000383ffff */
/*0cb0*/ ISETP.NE.AND P0, PT, RZ, UR7, PT ; /* 0x00000007ff007c0c */
/* 0x000fda000bf05270 */
/*0cc0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0cd0*/ UIADD3 UR9, UP0, UR6, UR4, URZ ; /* 0x0000000406097290 */
/* 0x000fe4000ff1e03f */
/*0ce0*/ ULDC UR11, c[0x0][0x178] ; /* 0x00005e00000b7ab9 */
/* 0x000fe40000000800 */
/*0cf0*/ ULDC.64 UR12, c[0x0][0x168] ; /* 0x00005a00000c7ab9 */
/* 0x000fe40000000a00 */
/*0d00*/ ULEA.HI.X.SX32 UR10, UR4, URZ, 0x1, UP0 ; /* 0x0000003f040a7291 */
/* 0x000fe400080f0e3f */
/*0d10*/ ULEA UR8, UP0, UR9, UR12, 0x2 ; /* 0x0000000c09087291 */
/* 0x000fe4000f80103f */
/*0d20*/ UIADD3 UR4, UR4, UR11, URZ ; /* 0x0000000b04047290 */
/* 0x000fc4000fffe03f */
/*0d30*/ ULEA.HI.X UR9, UR9, UR13, UR10, 0x2, UP0 ; /* 0x0000000d09097291 */
/* 0x000fe400080f140a */
/*0d40*/ USHF.L.U32 UR4, UR4, 0x2, URZ ; /* 0x0000000204047899 */
/* 0x000fd2000800063f */
/*0d50*/ LDS R0, [UR4] ; /* 0x00000004ff007984 */
/* 0x000e620008000800 */
/*0d60*/ IMAD.U32 R5, RZ, RZ, UR9 ; /* 0x00000009ff057e24 */
/* 0x001fe4000f8e00ff */
/*0d70*/ IMAD.U32 R4, RZ, RZ, UR8 ; /* 0x00000008ff047e24 */
/* 0x000fca000f8e00ff */
/*0d80*/ LDG.E R5, [R4.64] ; /* 0x0000000e04057981 */
/* 0x000ea2000c1e1900 */
/*0d90*/ F2I.TRUNC.NTZ R0, R0 ; /* 0x0000000000007305 */
/* 0x002e24000020f100 */
/*0da0*/ IADD3 R2, R0, -0x1, RZ ; /* 0xffffffff00027810 */
/* 0x001fc80007ffe0ff */
/*0db0*/ IADD3 R3, P0, R2, UR5, RZ ; /* 0x0000000502037c10 */
/* 0x000fc8000ff1e0ff */
/*0dc0*/ LEA.HI.X.SX32 R6, R2, RZ, 0x1, P0 ; /* 0x000000ff02067211 */
/* 0x000fe400000f0eff */
/*0dd0*/ LEA R2, P0, R3, c[0x0][0x160], 0x2 ; /* 0x0000580003027a11 */
/* 0x000fc800078010ff */
/*0de0*/ LEA.HI.X R3, R3, c[0x0][0x164], R6, 0x2, P0 ; /* 0x0000590003037a11 */
/* 0x000fca00000f1406 */
/*0df0*/ LDG.E R6, [R2.64] ; /* 0x0000000e02067981 */
/* 0x000ea2000c1e1900 */
/*0e00*/ UIADD3 UR7, UR7, -0x1, URZ ; /* 0xffffffff07077890 */
/* 0x000fcc000fffe03f */
/*0e10*/ ISETP.NE.AND P0, PT, RZ, UR7, PT ; /* 0x00000007ff007c0c */
/* 0x000fe2000bf05270 */
/*0e20*/ UIADD3 UR8, UP0, UR8, 0x4, URZ ; /* 0x0000000408087890 */
/* 0x000fe4000ff1e03f */
/*0e30*/ UIADD3 UR4, UR4, 0x4, URZ ; /* 0x0000000404047890 */
/* 0x000fe4000fffe03f */
/*0e40*/ UIADD3.X UR9, URZ, UR9, URZ, UP0, !UPT ; /* 0x000000093f097290 */
/* 0x000fe200087fe43f */
/*0e50*/ FADD R7, R6, R5 ; /* 0x0000000506077221 */
/* 0x004fca0000000000 */
/*0e60*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x0001e4000c10190e */
/*0e70*/ @P0 BRA 0xd50 ; /* 0xfffffed000000947 */
/* 0x000fea000383ffff */
/*0e80*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0e90*/ BRA 0xe90; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0ea0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0eb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ec0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ed0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ee0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ef0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void cuda_graph_maxpool_bprop(float* gradInput, const float *gradOutput, const float* indices, const int nClusters, const int dim, const int nClustersPerThread) {
extern __shared__ float shared_mem[];
float* gradOutput_data = (float*)shared_mem;
float* indices_data = (float*)&gradOutput_data[nClusters];
const int tidx = threadIdx.x;
gradInput += blockIdx.x * dim;
gradOutput += blockIdx.x * nClusters;
indices += blockIdx.x * nClusters;
__syncthreads();
for (int i = 0; i < nClustersPerThread; ++i) {
int idx = tidx + i*blockDim.x;
if (idx < nClusters) {
gradOutput_data[idx] = gradOutput[idx];
indices_data[idx] = indices[idx];
}
}
__syncthreads();
//ouch...
if (tidx == 1) {
for (int i = 0; i < nClusters; ++i) {
gradInput[(int)indices_data[i]-1] += gradOutput[i];
}
}
//gradInput[(int)indices_data[tidx]-1] = gradOutput[tidx];
} | .file "tmpxft_000e5bc8_00000000-6_cuda_graph_maxpool_bprop.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z53__device_stub__Z24cuda_graph_maxpool_bpropPfPKfS1_iiiPfPKfS1_iii
.type _Z53__device_stub__Z24cuda_graph_maxpool_bpropPfPKfS1_iiiPfPKfS1_iii, @function
_Z53__device_stub__Z24cuda_graph_maxpool_bpropPfPKfS1_iiiPfPKfS1_iii:
.LFB2051:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z24cuda_graph_maxpool_bpropPfPKfS1_iii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z53__device_stub__Z24cuda_graph_maxpool_bpropPfPKfS1_iiiPfPKfS1_iii, .-_Z53__device_stub__Z24cuda_graph_maxpool_bpropPfPKfS1_iiiPfPKfS1_iii
.globl _Z24cuda_graph_maxpool_bpropPfPKfS1_iii
.type _Z24cuda_graph_maxpool_bpropPfPKfS1_iii, @function
_Z24cuda_graph_maxpool_bpropPfPKfS1_iii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z53__device_stub__Z24cuda_graph_maxpool_bpropPfPKfS1_iiiPfPKfS1_iii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z24cuda_graph_maxpool_bpropPfPKfS1_iii, .-_Z24cuda_graph_maxpool_bpropPfPKfS1_iii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z24cuda_graph_maxpool_bpropPfPKfS1_iii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z24cuda_graph_maxpool_bpropPfPKfS1_iii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void cuda_graph_maxpool_bprop(float* gradInput, const float *gradOutput, const float* indices, const int nClusters, const int dim, const int nClustersPerThread) {
extern __shared__ float shared_mem[];
float* gradOutput_data = (float*)shared_mem;
float* indices_data = (float*)&gradOutput_data[nClusters];
const int tidx = threadIdx.x;
gradInput += blockIdx.x * dim;
gradOutput += blockIdx.x * nClusters;
indices += blockIdx.x * nClusters;
__syncthreads();
for (int i = 0; i < nClustersPerThread; ++i) {
int idx = tidx + i*blockDim.x;
if (idx < nClusters) {
gradOutput_data[idx] = gradOutput[idx];
indices_data[idx] = indices[idx];
}
}
__syncthreads();
//ouch...
if (tidx == 1) {
for (int i = 0; i < nClusters; ++i) {
gradInput[(int)indices_data[i]-1] += gradOutput[i];
}
}
//gradInput[(int)indices_data[tidx]-1] = gradOutput[tidx];
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void cuda_graph_maxpool_bprop(float* gradInput, const float *gradOutput, const float* indices, const int nClusters, const int dim, const int nClustersPerThread) {
extern __shared__ float shared_mem[];
float* gradOutput_data = (float*)shared_mem;
float* indices_data = (float*)&gradOutput_data[nClusters];
const int tidx = threadIdx.x;
gradInput += blockIdx.x * dim;
gradOutput += blockIdx.x * nClusters;
indices += blockIdx.x * nClusters;
__syncthreads();
for (int i = 0; i < nClustersPerThread; ++i) {
int idx = tidx + i*blockDim.x;
if (idx < nClusters) {
gradOutput_data[idx] = gradOutput[idx];
indices_data[idx] = indices[idx];
}
}
__syncthreads();
//ouch...
if (tidx == 1) {
for (int i = 0; i < nClusters; ++i) {
gradInput[(int)indices_data[i]-1] += gradOutput[i];
}
}
//gradInput[(int)indices_data[tidx]-1] = gradOutput[tidx];
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void cuda_graph_maxpool_bprop(float* gradInput, const float *gradOutput, const float* indices, const int nClusters, const int dim, const int nClustersPerThread) {
extern __shared__ float shared_mem[];
float* gradOutput_data = (float*)shared_mem;
float* indices_data = (float*)&gradOutput_data[nClusters];
const int tidx = threadIdx.x;
gradInput += blockIdx.x * dim;
gradOutput += blockIdx.x * nClusters;
indices += blockIdx.x * nClusters;
__syncthreads();
for (int i = 0; i < nClustersPerThread; ++i) {
int idx = tidx + i*blockDim.x;
if (idx < nClusters) {
gradOutput_data[idx] = gradOutput[idx];
indices_data[idx] = indices[idx];
}
}
__syncthreads();
//ouch...
if (tidx == 1) {
for (int i = 0; i < nClusters; ++i) {
gradInput[(int)indices_data[i]-1] += gradOutput[i];
}
}
//gradInput[(int)indices_data[tidx]-1] = gradOutput[tidx];
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z24cuda_graph_maxpool_bpropPfPKfS1_iii
.globl _Z24cuda_graph_maxpool_bpropPfPKfS1_iii
.p2align 8
.type _Z24cuda_graph_maxpool_bpropPfPKfS1_iii,@function
_Z24cuda_graph_maxpool_bpropPfPKfS1_iii:
s_clause 0x2
s_load_b32 s6, s[0:1], 0x18
s_load_b64 s[2:3], s[0:1], 0x8
s_load_b32 s7, s[0:1], 0x20
s_mov_b32 s5, 0
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_mul_i32 s4, s15, s6
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_lshl_b64 s[4:5], s[4:5], 2
s_add_u32 s2, s2, s4
s_addc_u32 s3, s3, s5
s_cmp_lt_i32 s7, 1
s_cbranch_scc1 .LBB0_5
s_clause 0x1
s_load_b64 s[8:9], s[0:1], 0x10
s_load_b32 s10, s[0:1], 0x34
v_lshl_add_u32 v3, v0, 2, 0
v_mov_b32_e32 v1, v0
s_waitcnt lgkmcnt(0)
s_add_u32 s4, s8, s4
s_addc_u32 s5, s9, s5
s_and_b32 s8, s10, 0xffff
s_lshl_b32 s9, s6, 2
s_lshl_b32 s10, s8, 2
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_3
.p2align 6
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s11
v_add_nc_u32_e32 v3, s10, v3
v_add_nc_u32_e32 v1, s8, v1
s_add_i32 s7, s7, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s7, 0
s_cbranch_scc1 .LBB0_5
.LBB0_3:
s_mov_b32 s11, exec_lo
v_cmpx_gt_i32_e64 s6, v1
s_cbranch_execz .LBB0_2
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[4:5], 2, v[1:2]
v_add_co_u32 v6, vcc_lo, s2, v4
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v7, vcc_lo, s3, v5, vcc_lo
v_add_co_u32 v4, vcc_lo, s4, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
global_load_b32 v2, v[6:7], off
global_load_b32 v4, v[4:5], off
v_add_nc_u32_e32 v5, s9, v3
s_waitcnt vmcnt(1)
ds_store_b32 v3, v2
s_waitcnt vmcnt(0)
ds_store_b32 v5, v4
s_branch .LBB0_2
.LBB0_5:
s_set_inst_prefetch_distance 0x2
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_mov_b32 s4, exec_lo
v_cmpx_eq_u32_e32 1, v0
s_cbranch_execz .LBB0_9
s_cmp_lt_i32 s6, 1
s_cbranch_scc1 .LBB0_9
s_clause 0x1
s_load_b32 s4, s[0:1], 0x1c
s_load_b64 s[0:1], s[0:1], 0x0
s_mov_b32 s5, 0
v_mov_b32_e32 v0, 0
s_waitcnt lgkmcnt(0)
s_mul_i32 s4, s15, s4
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_lshl_b64 s[4:5], s[4:5], 2
s_add_u32 s0, s0, s4
s_addc_u32 s1, s1, s5
s_add_u32 s0, s0, -4
s_addc_u32 s1, s1, -1
s_lshl_b32 s4, s6, 2
s_delay_alu instid0(SALU_CYCLE_1)
s_add_i32 s4, s4, 0
.p2align 6
.LBB0_8:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
v_mov_b32_e32 v1, s4
s_add_i32 s6, s6, -1
ds_load_b32 v1, v1
s_waitcnt lgkmcnt(0)
v_cvt_i32_f32_e32 v1, v1
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[1:2]
v_add_co_u32 v1, vcc_lo, s0, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
global_load_b32 v3, v0, s[2:3]
global_load_b32 v4, v[1:2], off
s_add_u32 s2, s2, 4
s_addc_u32 s3, s3, 0
s_add_i32 s4, s4, 4
s_cmp_lg_u32 s6, 0
s_waitcnt vmcnt(0)
v_add_f32_e32 v3, v3, v4
global_store_b32 v[1:2], v3, off
s_cbranch_scc1 .LBB0_8
.LBB0_9:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z24cuda_graph_maxpool_bpropPfPKfS1_iii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z24cuda_graph_maxpool_bpropPfPKfS1_iii, .Lfunc_end0-_Z24cuda_graph_maxpool_bpropPfPKfS1_iii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
- .offset: 160
.size: 4
.value_kind: hidden_dynamic_lds_size
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z24cuda_graph_maxpool_bpropPfPKfS1_iii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z24cuda_graph_maxpool_bpropPfPKfS1_iii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void cuda_graph_maxpool_bprop(float* gradInput, const float *gradOutput, const float* indices, const int nClusters, const int dim, const int nClustersPerThread) {
extern __shared__ float shared_mem[];
float* gradOutput_data = (float*)shared_mem;
float* indices_data = (float*)&gradOutput_data[nClusters];
const int tidx = threadIdx.x;
gradInput += blockIdx.x * dim;
gradOutput += blockIdx.x * nClusters;
indices += blockIdx.x * nClusters;
__syncthreads();
for (int i = 0; i < nClustersPerThread; ++i) {
int idx = tidx + i*blockDim.x;
if (idx < nClusters) {
gradOutput_data[idx] = gradOutput[idx];
indices_data[idx] = indices[idx];
}
}
__syncthreads();
//ouch...
if (tidx == 1) {
for (int i = 0; i < nClusters; ++i) {
gradInput[(int)indices_data[i]-1] += gradOutput[i];
}
}
//gradInput[(int)indices_data[tidx]-1] = gradOutput[tidx];
} | .text
.file "cuda_graph_maxpool_bprop.hip"
.globl _Z39__device_stub__cuda_graph_maxpool_bpropPfPKfS1_iii # -- Begin function _Z39__device_stub__cuda_graph_maxpool_bpropPfPKfS1_iii
.p2align 4, 0x90
.type _Z39__device_stub__cuda_graph_maxpool_bpropPfPKfS1_iii,@function
_Z39__device_stub__cuda_graph_maxpool_bpropPfPKfS1_iii: # @_Z39__device_stub__cuda_graph_maxpool_bpropPfPKfS1_iii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z24cuda_graph_maxpool_bpropPfPKfS1_iii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z39__device_stub__cuda_graph_maxpool_bpropPfPKfS1_iii, .Lfunc_end0-_Z39__device_stub__cuda_graph_maxpool_bpropPfPKfS1_iii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z24cuda_graph_maxpool_bpropPfPKfS1_iii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z24cuda_graph_maxpool_bpropPfPKfS1_iii,@object # @_Z24cuda_graph_maxpool_bpropPfPKfS1_iii
.section .rodata,"a",@progbits
.globl _Z24cuda_graph_maxpool_bpropPfPKfS1_iii
.p2align 3, 0x0
_Z24cuda_graph_maxpool_bpropPfPKfS1_iii:
.quad _Z39__device_stub__cuda_graph_maxpool_bpropPfPKfS1_iii
.size _Z24cuda_graph_maxpool_bpropPfPKfS1_iii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z24cuda_graph_maxpool_bpropPfPKfS1_iii"
.size .L__unnamed_1, 40
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z39__device_stub__cuda_graph_maxpool_bpropPfPKfS1_iii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z24cuda_graph_maxpool_bpropPfPKfS1_iii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z24cuda_graph_maxpool_bpropPfPKfS1_iii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2UR UR6, SR_CTAID.X ; /* 0x00000000000679c3 */
/* 0x000e220000002500 */
/*0020*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e620000002100 */
/*0030*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x180] ; /* 0x00006000ff027624 */
/* 0x000fe200078e00ff */
/*0040*/ ULDC.64 UR4, c[0x0][0x178] ; /* 0x00005e0000047ab9 */
/* 0x000fe40000000a00 */
/*0050*/ ULDC.64 UR14, c[0x0][0x118] ; /* 0x00004600000e7ab9 */
/* 0x000fe20000000a00 */
/*0060*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0070*/ ISETP.GE.AND P0, PT, R2, 0x1, PT ; /* 0x000000010200780c */
/* 0x000fe20003f06270 */
/*0080*/ UIMAD UR5, UR6, UR5, URZ ; /* 0x00000005060572a4 */
/* 0x001fe4000f8e023f */
/*0090*/ UIMAD UR6, UR6, UR4, URZ ; /* 0x00000004060672a4 */
/* 0x000fd4000f8e023f */
/*00a0*/ @!P0 BRA 0x7d0 ; /* 0x0000072000008947 */
/* 0x000fea0003800000 */
/*00b0*/ IADD3 R3, R2.reuse, -0x1, RZ ; /* 0xffffffff02037810 */
/* 0x042fe20007ffe0ff */
/*00c0*/ IMAD.MOV.U32 R7, RZ, RZ, RZ ; /* 0x000000ffff077224 */
/* 0x000fe200078e00ff */
/*00d0*/ LOP3.LUT R2, R2, 0x3, RZ, 0xc0, !PT ; /* 0x0000000302027812 */
/* 0x000fe400078ec0ff */
/*00e0*/ ISETP.GE.U32.AND P1, PT, R3, 0x3, PT ; /* 0x000000030300780c */
/* 0x000fe40003f26070 */
/*00f0*/ ISETP.NE.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fd60003f05270 */
/*0100*/ @!P1 BRA 0x620 ; /* 0x0000051000009947 */
/* 0x000fea0003800000 */
/*0110*/ IMAD.SHL.U32 R4, R0.reuse, 0x4, RZ ; /* 0x0000000400047824 */
/* 0x040fe200078e00ff */
/*0120*/ IADD3 R5, R0, c[0x0][0x0], RZ ; /* 0x0000000000057a10 */
/* 0x000fe20007ffe0ff */
/*0130*/ IMAD.MOV.U32 R11, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff0b7624 */
/* 0x000fe200078e00ff */
/*0140*/ IADD3 R26, R2, -c[0x0][0x180], RZ ; /* 0x80006000021a7a10 */
/* 0x000fe20007ffe0ff */
/*0150*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fe200078e00ff */
/*0160*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*0170*/ IMAD R19, R11.reuse, 0x2, R0 ; /* 0x000000020b137824 */
/* 0x040fe400078e0200 */
/*0180*/ IMAD R9, R11.reuse, 0x8, R4 ; /* 0x000000080b097824 */
/* 0x040fe400078e0204 */
/*0190*/ IMAD R8, R11, 0x3, R0 ; /* 0x000000030b087824 */
/* 0x000fc400078e0200 */
/*01a0*/ IMAD R24, R3, c[0x0][0x0], R4.reuse ; /* 0x0000000003187a24 */
/* 0x100fe400078e0204 */
/*01b0*/ IMAD R11, R11, 0xc, R4.reuse ; /* 0x0000000c0b0b7824 */
/* 0x100fe400078e0204 */
/*01c0*/ IMAD R18, R3.reuse, c[0x0][0x178], R4 ; /* 0x00005e0003127a24 */
/* 0x040fe400078e0204 */
/*01d0*/ IMAD R24, R3.reuse, c[0x0][0x178], R24 ; /* 0x00005e0003187a24 */
/* 0x040fe400078e0218 */
/*01e0*/ IMAD R25, R3, c[0x0][0x178], R9 ; /* 0x00005e0003197a24 */
/* 0x000fe400078e0209 */
/*01f0*/ IMAD.MOV.U32 R7, RZ, RZ, RZ ; /* 0x000000ffff077224 */
/* 0x000fc400078e00ff */
/*0200*/ IMAD.MOV.U32 R10, RZ, RZ, R0 ; /* 0x000000ffff0a7224 */
/* 0x000fe400078e0000 */
/*0210*/ IMAD.MOV.U32 R6, RZ, RZ, R5 ; /* 0x000000ffff067224 */
/* 0x000fe400078e0005 */
/*0220*/ IMAD R3, R3, c[0x0][0x178], R11 ; /* 0x00005e0003037a24 */
/* 0x000fe400078e020b */
/*0230*/ ISETP.GE.AND P1, PT, R10, c[0x0][0x178], PT ; /* 0x00005e000a007a0c */
/* 0x000fe40003f26270 */
/*0240*/ ISETP.GE.AND P3, PT, R6, c[0x0][0x178], PT ; /* 0x00005e0006007a0c */
/* 0x000fe40003f66270 */
/*0250*/ ISETP.GE.AND P2, PT, R19, c[0x0][0x178], PT ; /* 0x00005e0013007a0c */
/* 0x000fd20003f46270 */
/*0260*/ @!P1 IADD3 R15, P4, R10, UR6, RZ ; /* 0x000000060a0f9c10 */
/* 0x000fe4000ff9e0ff */
/*0270*/ @!P3 IADD3 R12, P5, R6, UR6, RZ ; /* 0x00000006060cbc10 */
/* 0x000fe4000ffbe0ff */
/*0280*/ @!P1 LEA.HI.X.SX32 R14, R10, RZ, 0x1, P4 ; /* 0x000000ff0a0e9211 */
/* 0x001fe200020f0eff */
/*0290*/ @!P1 IMAD.SHL.U32 R22, R15.reuse, 0x4, RZ ; /* 0x000000040f169824 */
/* 0x040fe200078e00ff */
/*02a0*/ @!P3 LEA.HI.X.SX32 R13, R6, RZ, 0x1, P5 ; /* 0x000000ff060db211 */
/* 0x000fe400028f0eff */
/*02b0*/ @!P1 SHF.L.U64.HI R15, R15, 0x2, R14 ; /* 0x000000020f0f9819 */
/* 0x000fe4000001020e */
/*02c0*/ @!P3 SHF.L.U64.HI R13, R12.reuse, 0x2, R13 ; /* 0x000000020c0db819 */
/* 0x040fe2000001020d */
/*02d0*/ @!P3 IMAD.SHL.U32 R12, R12, 0x4, RZ ; /* 0x000000040c0cb824 */
/* 0x000fe200078e00ff */
/*02e0*/ @!P1 IADD3 R16, P4, R22, c[0x0][0x168], RZ ; /* 0x00005a0016109a10 */
/* 0x000fc40007f9e0ff */
/*02f0*/ @!P1 IADD3 R22, P5, R22, c[0x0][0x170], RZ ; /* 0x00005c0016169a10 */
/* 0x000fe40007fbe0ff */
/*0300*/ @!P1 IADD3.X R17, R15, c[0x0][0x16c], RZ, P4, !PT ; /* 0x00005b000f119a10 */
/* 0x000fe400027fe4ff */
/*0310*/ @!P2 IADD3 R14, P6, R19, UR6, RZ ; /* 0x00000006130eac10 */
/* 0x000fe4000ffde0ff */
/*0320*/ @!P3 IADD3 R20, P4, R12, c[0x0][0x168], RZ ; /* 0x00005a000c14ba10 */
/* 0x000fe20007f9e0ff */
/*0330*/ @!P1 LDG.E R27, [R16.64] ; /* 0x0000000e101b9981 */
/* 0x0000a2000c1e1900 */
/*0340*/ @!P1 IADD3.X R23, R15, c[0x0][0x174], RZ, P5, !PT ; /* 0x00005d000f179a10 */
/* 0x000fe40002ffe4ff */
/*0350*/ @!P2 LEA.HI.X.SX32 R15, R19, RZ, 0x1, P6 ; /* 0x000000ff130fa211 */
/* 0x000fc400030f0eff */
/*0360*/ @!P3 IADD3.X R21, R13, c[0x0][0x16c], RZ, P4, !PT ; /* 0x00005b000d15ba10 */
/* 0x000fe200027fe4ff */
/*0370*/ @!P1 LDG.E R29, [R22.64] ; /* 0x0000000e161d9981 */
/* 0x0002e2000c1e1900 */
/*0380*/ ISETP.GE.AND P4, PT, R8, c[0x0][0x178], PT ; /* 0x00005e0008007a0c */
/* 0x000fe40003f86270 */
/*0390*/ @!P2 SHF.L.U64.HI R17, R14.reuse, 0x2, R15 ; /* 0x000000020e11a819 */
/* 0x041fe2000001020f */
/*03a0*/ @!P2 IMAD.SHL.U32 R15, R14, 0x4, RZ ; /* 0x000000040e0fa824 */
/* 0x000fe200078e00ff */
/*03b0*/ @!P3 IADD3 R12, P6, R12, c[0x0][0x170], RZ ; /* 0x00005c000c0cba10 */
/* 0x000fe20007fde0ff */
/*03c0*/ @!P3 LDG.E R28, [R20.64] ; /* 0x0000000e141cb981 */
/* 0x000126000c1e1900 */
/*03d0*/ @!P2 IADD3 R14, P5, R15, c[0x0][0x168], RZ ; /* 0x00005a000f0eaa10 */
/* 0x000fc40007fbe0ff */
/*03e0*/ @!P3 IADD3.X R13, R13, c[0x0][0x174], RZ, P6, !PT ; /* 0x00005d000d0dba10 */
/* 0x000fe400037fe4ff */
/*03f0*/ @!P2 IADD3 R16, P6, R15, c[0x0][0x170], RZ ; /* 0x00005c000f10aa10 */
/* 0x000fe40007fde0ff */
/*0400*/ @!P2 IADD3.X R15, R17, c[0x0][0x16c], RZ, P5, !PT ; /* 0x00005b00110faa10 */
/* 0x000fe40002ffe4ff */
/*0410*/ @!P4 IADD3 R23, P5, R8.reuse, UR6, RZ ; /* 0x000000060817cc10 */
/* 0x042fe2000ffbe0ff */
/*0420*/ @!P3 LDG.E R13, [R12.64] ; /* 0x0000000e0c0db981 */
/* 0x000368000c1e1900 */
/*0430*/ @!P4 IMAD.SHL.U32 R22, R23, 0x4, RZ ; /* 0x000000041716c824 */
/* 0x000fe200078e00ff */
/*0440*/ @!P2 IADD3.X R17, R17, c[0x0][0x174], RZ, P6, !PT ; /* 0x00005d001111aa10 */
/* 0x000fe200037fe4ff */
/*0450*/ @!P2 LDG.E R14, [R14.64] ; /* 0x0000000e0e0ea981 */
/* 0x000162000c1e1900 */
/*0460*/ @!P4 LEA.HI.X.SX32 R12, R8, RZ, 0x1, P5 ; /* 0x000000ff080cc211 */
/* 0x002fc600028f0eff */
/*0470*/ @!P2 LDG.E R16, [R16.64] ; /* 0x0000000e1010a981 */
/* 0x000f62000c1e1900 */
/*0480*/ @!P4 IADD3 R20, P5, R22.reuse, c[0x0][0x168], RZ ; /* 0x00005a001614ca10 */
/* 0x041fe40007fbe0ff */
/*0490*/ @!P4 SHF.L.U64.HI R23, R23, 0x2, R12 ; /* 0x000000021717c819 */
/* 0x000fe4000001020c */
/*04a0*/ @!P4 IADD3 R22, P6, R22, c[0x0][0x170], RZ ; /* 0x00005c001616ca10 */
/* 0x000fe40007fde0ff */
/*04b0*/ @!P4 IADD3.X R21, R23.reuse, c[0x0][0x16c], RZ, P5, !PT ; /* 0x00005b001715ca10 */
/* 0x040fe40002ffe4ff */
/*04c0*/ @!P4 IADD3.X R23, R23, c[0x0][0x174], RZ, P6, !PT ; /* 0x00005d001717ca10 */
/* 0x000fc600037fe4ff */
/*04d0*/ @!P4 LDG.E R20, [R20.64] ; /* 0x0000000e1414c981 */
/* 0x000f68000c1e1900 */
/*04e0*/ @!P4 LDG.E R22, [R22.64] ; /* 0x0000000e1616c981 */
/* 0x000f62000c1e1900 */
/*04f0*/ IADD3 R26, R26, 0x4, RZ ; /* 0x000000041a1a7810 */
/* 0x000fe20007ffe0ff */
/*0500*/ ULDC UR7, c[0x0][0x0] ; /* 0x0000000000077ab9 */
/* 0x000fe20000000800 */
/*0510*/ IMAD.MOV.U32 R15, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff0f7624 */
/* 0x000fe200078e00ff */
/*0520*/ IADD3 R7, R7, 0x4, RZ ; /* 0x0000000407077810 */
/* 0x000fc60007ffe0ff */
/*0530*/ IMAD R6, R15.reuse, 0x4, R6 ; /* 0x000000040f067824 */
/* 0x040fe400078e0206 */
/*0540*/ IMAD R19, R15.reuse, 0x4, R19 ; /* 0x000000040f137824 */
/* 0x040fe400078e0213 */
/*0550*/ IMAD R8, R15.reuse, 0x4, R8 ; /* 0x000000040f087824 */
/* 0x040fe400078e0208 */
/*0560*/ IMAD R10, R15, 0x4, R10 ; /* 0x000000040f0a7824 */
/* 0x000fe200078e020a */
/*0570*/ @!P1 STS [R4+UR4], R27 ; /* 0x0000001b04009988 */
/* 0x0041e80008000804 */
/*0580*/ @!P1 STS [R18+UR4], R29 ; /* 0x0000001d12009988 */
/* 0x0081e20008000804 */
/*0590*/ ISETP.NE.AND P1, PT, R26, RZ, PT ; /* 0x000000ff1a00720c */
/* 0x000fc60003f25270 */
/*05a0*/ @!P3 STS [R5.X4+UR4], R28 ; /* 0x0000001c0500b988 */
/* 0x0101e80008004804 */
/*05b0*/ @!P3 STS [R24+UR4], R13 ; /* 0x0000000d1800b988 */
/* 0x0201e80008000804 */
/*05c0*/ @!P2 STS [R9+UR4], R14 ; /* 0x0000000e0900a988 */
/* 0x0001e80008000804 */
/*05d0*/ @!P2 STS [R25+UR4], R16 ; /* 0x000000101900a988 */
/* 0x0001e80008000804 */
/*05e0*/ @!P4 STS [R11+UR4], R20 ; /* 0x000000140b00c988 */
/* 0x0001e80008000804 */
/*05f0*/ @!P4 STS [R3+UR4], R22 ; /* 0x000000160300c988 */
/* 0x0001e20008000804 */
/*0600*/ ULEA UR4, UR7, UR4, 0x4 ; /* 0x0000000407047291 */
/* 0x000fe2000f8e203f */
/*0610*/ @P1 BRA 0x230 ; /* 0xfffffc1000001947 */
/* 0x000fea000383ffff */
/*0620*/ NOP ; /* 0x0000000000007918 */
/* 0x000fc20000000000 */
/*0630*/ @!P0 BRA 0x7d0 ; /* 0x0000019000008947 */
/* 0x000fea0003800000 */
/*0640*/ IADD3 R4, R0, c[0x0][0x178], RZ ; /* 0x00005e0000047a10 */
/* 0x001fe20007ffe0ff */
/*0650*/ IMAD R8, R7, c[0x0][0x0], R0 ; /* 0x0000000007087a24 */
/* 0x000fc800078e0200 */
/*0660*/ IMAD R4, R7, c[0x0][0x0], R4 ; /* 0x0000000007047a24 */
/* 0x000fe400078e0204 */
/*0670*/ IMAD.SHL.U32 R9, R8, 0x4, RZ ; /* 0x0000000408097824 */
/* 0x000fe400078e00ff */
/*0680*/ IMAD.SHL.U32 R3, R4, 0x4, RZ ; /* 0x0000000404037824 */
/* 0x000fe400078e00ff */
/*0690*/ ISETP.GE.AND P0, PT, R8, c[0x0][0x178], PT ; /* 0x00005e0008007a0c */
/* 0x000fda0003f06270 */
/*06a0*/ @!P0 IADD3 R7, P1, R8, UR6, RZ ; /* 0x0000000608078c10 */
/* 0x000fc8000ff3e0ff */
/*06b0*/ @!P0 LEA.HI.X.SX32 R4, R8, RZ, 0x1, P1 ; /* 0x000000ff08048211 */
/* 0x000fe200008f0eff */
/*06c0*/ @!P0 IMAD.SHL.U32 R6, R7, 0x4, RZ ; /* 0x0000000407068824 */
/* 0x000fc600078e00ff */
/*06d0*/ @!P0 SHF.L.U64.HI R7, R7, 0x2, R4 ; /* 0x0000000207078819 */
/* 0x000fe40000010204 */
/*06e0*/ @!P0 IADD3 R4, P1, R6.reuse, c[0x0][0x168], RZ ; /* 0x00005a0006048a10 */
/* 0x040fe40007f3e0ff */
/*06f0*/ @!P0 IADD3 R6, P2, R6, c[0x0][0x170], RZ ; /* 0x00005c0006068a10 */
/* 0x000fe40007f5e0ff */
/*0700*/ @!P0 IADD3.X R5, R7.reuse, c[0x0][0x16c], RZ, P1, !PT ; /* 0x00005b0007058a10 */
/* 0x040fe40000ffe4ff */
/*0710*/ @!P0 IADD3.X R7, R7, c[0x0][0x174], RZ, P2, !PT ; /* 0x00005d0007078a10 */
/* 0x000fc600017fe4ff */
/*0720*/ @!P0 LDG.E R4, [R4.64] ; /* 0x0000000e04048981 */
/* 0x000ea8000c1e1900 */
/*0730*/ @!P0 LDG.E R6, [R6.64] ; /* 0x0000000e06068981 */
/* 0x000ee2000c1e1900 */
/*0740*/ IADD3 R2, R2, -0x1, RZ ; /* 0xffffffff02027810 */
/* 0x000fe20007ffe0ff */
/*0750*/ IMAD.MOV.U32 R10, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff0a7624 */
/* 0x000fe200078e00ff */
/*0760*/ IADD3 R8, R8, c[0x0][0x0], RZ ; /* 0x0000000008087a10 */
/* 0x000fe20007ffe0ff */
/*0770*/ @!P0 STS [R9], R4 ; /* 0x0000000409008388 */
/* 0x0041e80000000800 */
/*0780*/ @!P0 STS [R3], R6 ; /* 0x0000000603008388 */
/* 0x0083e20000000800 */
/*0790*/ ISETP.NE.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fe20003f05270 */
/*07a0*/ IMAD R9, R10, 0x4, R9 ; /* 0x000000040a097824 */
/* 0x001fc400078e0209 */
/*07b0*/ IMAD R3, R10, 0x4, R3 ; /* 0x000000040a037824 */
/* 0x002fd400078e0203 */
/*07c0*/ @P0 BRA 0x690 ; /* 0xfffffec000000947 */
/* 0x000fea000383ffff */
/*07d0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x002fe20000010000 */
/*07e0*/ IMAD.MOV.U32 R2, RZ, RZ, 0x1 ; /* 0x00000001ff027424 */
/* 0x000fca00078e00ff */
/*07f0*/ ISETP.LE.AND P0, PT, R2, c[0x0][0x178], PT ; /* 0x00005e0002007a0c */
/* 0x000fc80003f03270 */
/*0800*/ ISETP.NE.OR P0, PT, R0, 0x1, !P0 ; /* 0x000000010000780c */
/* 0x000fda0004705670 */
/*0810*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0820*/ IMAD.MOV.U32 R0, RZ, RZ, 0x1 ; /* 0x00000001ff007424 */
/* 0x000fe200078e00ff */
/*0830*/ UMOV UR7, 0x3 ; /* 0x0000000300077882 */
/* 0x000fe40000000000 */
/*0840*/ ULDC UR8, c[0x0][0x178] ; /* 0x00005e0000087ab9 */
/* 0x000fe40000000800 */
/*0850*/ IADD3 R0, -R0, c[0x0][0x178], RZ ; /* 0x00005e0000007a10 */
/* 0x000fe20007ffe1ff */
/*0860*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe40008000000 */
/*0870*/ ULOP3.LUT UR7, UR7, UR8, URZ, 0xc0, !UPT ; /* 0x0000000807077292 */
/* 0x000fe2000f8ec03f */
/*0880*/ ISETP.GE.U32.AND P0, PT, R0, 0x3, PT ; /* 0x000000030000780c */
/* 0x000fda0003f06070 */
/*0890*/ @!P0 BRA 0xcb0 ; /* 0x0000041000008947 */
/* 0x000fea0003800000 */
/*08a0*/ ULDC.64 UR8, c[0x0][0x168] ; /* 0x00005a0000087ab9 */
/* 0x000fe40000000a00 */
/*08b0*/ ULEA UR4, UP0, UR6, UR8, 0x2 ; /* 0x0000000806047291 */
/* 0x000fe4000f80103f */
/*08c0*/ ULDC UR10, c[0x0][0x178] ; /* 0x00005e00000a7ab9 */
/* 0x000fe40000000800 */
/*08d0*/ ULEA.HI.X UR9, UR6, UR9, URZ, 0x2, UP0 ; /* 0x0000000906097291 */
/* 0x000fe400080f143f */
/*08e0*/ UIADD3 UR4, UP0, UR4, 0x8, URZ ; /* 0x0000000804047890 */
/* 0x000fe4000ff1e03f */
/*08f0*/ UMOV UR8, 0x4 ; /* 0x0000000400087882 */
/* 0x000fc40000000000 */
/*0900*/ UIADD3.X UR9, URZ, UR9, URZ, UP0, !UPT ; /* 0x000000093f097290 */
/* 0x000fe400087fe43f */
/*0910*/ IMAD.U32 R6, RZ, RZ, UR4 ; /* 0x00000004ff067e24 */
/* 0x000fe2000f8e00ff */
/*0920*/ UIADD3 UR11, -UR7, UR10, URZ ; /* 0x0000000a070b7290 */
/* 0x000fe4000fffe13f */
/*0930*/ UIMAD UR8, UR8, UR10, 0x8 ; /* 0x00000008080874a4 */
/* 0x000fe2000f8e020a */
/*0940*/ IMAD.U32 R13, RZ, RZ, UR9 ; /* 0x00000009ff0d7e24 */
/* 0x001fe2000f8e00ff */
/*0950*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fce0008000000 */
/*0960*/ LDS R0, [UR8+-0x8] ; /* 0xfffff808ff007984 */
/* 0x001e280008000800 */
/*0970*/ LDS R10, [UR8+-0x4] ; /* 0xfffffc08ff0a7984 */
/* 0x000e680008000800 */
/*0980*/ LDS R12, [UR8] ; /* 0x00000008ff0c7984 */
/* 0x000ea20008000800 */
/*0990*/ F2I.TRUNC.NTZ R0, R0 ; /* 0x0000000000007305 */
/* 0x001e24000020f100 */
/*09a0*/ IADD3 R2, R0, -0x1, RZ ; /* 0xffffffff00027810 */
/* 0x001fc80007ffe0ff */
/*09b0*/ IADD3 R3, P0, R2, UR5, RZ ; /* 0x0000000502037c10 */
/* 0x000fc8000ff1e0ff */
/*09c0*/ LEA.HI.X.SX32 R2, R2, RZ, 0x1, P0 ; /* 0x000000ff02027211 */
/* 0x000fe400000f0eff */
/*09d0*/ LEA R8, P0, R3, c[0x0][0x160], 0x2 ; /* 0x0000580003087a11 */
/* 0x000fc800078010ff */
/*09e0*/ LEA.HI.X R9, R3, c[0x0][0x164], R2, 0x2, P0 ; /* 0x0000590003097a11 */
/* 0x000fe200000f1402 */
/*09f0*/ IMAD.MOV.U32 R2, RZ, RZ, R6 ; /* 0x000000ffff027224 */
/* 0x000fe400078e0006 */
/*0a00*/ IMAD.MOV.U32 R3, RZ, RZ, R13 ; /* 0x000000ffff037224 */
/* 0x000fe400078e000d */
/*0a10*/ LDG.E R4, [R8.64] ; /* 0x0000000e08047981 */
/* 0x000ee8000c1e1900 */
/*0a20*/ LDG.E R5, [R2.64+-0x8] ; /* 0xfffff80e02057981 */
/* 0x000ee2000c1e1900 */
/*0a30*/ F2I.TRUNC.NTZ R10, R10 ; /* 0x0000000a000a7305 */
/* 0x002e24000020f100 */
/*0a40*/ IADD3 R0, R10, -0x1, RZ ; /* 0xffffffff0a007810 */
/* 0x001fc80007ffe0ff */
/*0a50*/ IADD3 R7, P0, R0, UR5, RZ ; /* 0x0000000500077c10 */
/* 0x000fc8000ff1e0ff */
/*0a60*/ LEA.HI.X.SX32 R0, R0, RZ, 0x1, P0 ; /* 0x000000ff00007211 */
/* 0x000fe400000f0eff */
/*0a70*/ LEA R6, P0, R7, c[0x0][0x160], 0x2 ; /* 0x0000580007067a11 */
/* 0x000fc800078010ff */
/*0a80*/ LEA.HI.X R7, R7, c[0x0][0x164], R0, 0x2, P0 ; /* 0x0000590007077a11 */
/* 0x000fe200000f1400 */
/*0a90*/ FADD R11, R4, R5 ; /* 0x00000005040b7221 */
/* 0x008fca0000000000 */
/*0aa0*/ STG.E [R8.64], R11 ; /* 0x0000000b08007986 */
/* 0x0001e8000c10190e */
/*0ab0*/ LDG.E R13, [R2.64+-0x4] ; /* 0xfffffc0e020d7981 */
/* 0x000ee8000c1e1900 */
/*0ac0*/ LDG.E R0, [R6.64] ; /* 0x0000000e06007981 */
/* 0x000ee2000c1e1900 */
/*0ad0*/ F2I.TRUNC.NTZ R12, R12 ; /* 0x0000000c000c7305 */
/* 0x004e64000020f100 */
/*0ae0*/ IADD3 R4, R12, -0x1, RZ ; /* 0xffffffff0c047810 */
/* 0x002fc80007ffe0ff */
/*0af0*/ IADD3 R5, P0, R4, UR5, RZ ; /* 0x0000000504057c10 */
/* 0x000fc8000ff1e0ff */
/*0b00*/ LEA.HI.X.SX32 R10, R4, RZ, 0x1, P0 ; /* 0x000000ff040a7211 */
/* 0x000fe400000f0eff */
/*0b10*/ LEA R4, P0, R5, c[0x0][0x160], 0x2 ; /* 0x0000580005047a11 */
/* 0x000fc800078010ff */
/*0b20*/ LEA.HI.X R5, R5, c[0x0][0x164], R10, 0x2, P0 ; /* 0x0000590005057a11 */
/* 0x000fe400000f140a */
/*0b30*/ LDS R10, [UR8+0x4] ; /* 0x00000408ff0a7984 */
/* 0x000e620008000800 */
/*0b40*/ FADD R13, R0, R13 ; /* 0x0000000d000d7221 */
/* 0x008fca0000000000 */
/*0b50*/ STG.E [R6.64], R13 ; /* 0x0000000d06007986 */
/* 0x0005e8000c10190e */
/*0b60*/ LDG.E R11, [R2.64] ; /* 0x0000000e020b7981 */
/* 0x001ee8000c1e1900 */
/*0b70*/ LDG.E R0, [R4.64] ; /* 0x0000000e04007981 */
/* 0x000ee2000c1e1900 */
/*0b80*/ F2I.TRUNC.NTZ R10, R10 ; /* 0x0000000a000a7305 */
/* 0x002e24000020f100 */
/*0b90*/ IADD3 R8, R10, -0x1, RZ ; /* 0xffffffff0a087810 */
/* 0x001fc80007ffe0ff */
/*0ba0*/ IADD3 R9, P0, R8, UR5, RZ ; /* 0x0000000508097c10 */
/* 0x000fc8000ff1e0ff */
/*0bb0*/ LEA.HI.X.SX32 R12, R8, RZ, 0x1, P0 ; /* 0x000000ff080c7211 */
/* 0x000fe400000f0eff */
/*0bc0*/ LEA R8, P0, R9, c[0x0][0x160], 0x2 ; /* 0x0000580009087a11 */
/* 0x000fc800078010ff */
/*0bd0*/ LEA.HI.X R9, R9, c[0x0][0x164], R12, 0x2, P0 ; /* 0x0000590009097a11 */
/* 0x000fe200000f140c */
/*0be0*/ FADD R11, R0, R11 ; /* 0x0000000b000b7221 */
/* 0x008fca0000000000 */
/*0bf0*/ STG.E [R4.64], R11 ; /* 0x0000000b04007986 */
/* 0x0001e8000c10190e */
/*0c00*/ LDG.E R7, [R2.64+0x4] ; /* 0x0000040e02077981 */
/* 0x004ea8000c1e1900 */
/*0c10*/ LDG.E R0, [R8.64] ; /* 0x0000000e08007981 */
/* 0x000ea2000c1e1900 */
/*0c20*/ UIADD3 UR11, UR11, -0x4, URZ ; /* 0xfffffffc0b0b7890 */
/* 0x000fcc000fffe03f */
/*0c30*/ ISETP.NE.AND P0, PT, RZ, UR11, PT ; /* 0x0000000bff007c0c */
/* 0x000fe4000bf05270 */
/*0c40*/ IADD3 R6, P1, R2, 0x10, RZ ; /* 0x0000001002067810 */
/* 0x000fe20007f3e0ff */
/*0c50*/ UIADD3 UR4, UR4, 0x4, URZ ; /* 0x0000000404047890 */
/* 0x000fe4000fffe03f */
/*0c60*/ UIADD3 UR8, UR8, 0x10, URZ ; /* 0x0000001008087890 */
/* 0x000fe4000fffe03f */
/*0c70*/ IMAD.X R13, RZ, RZ, R3, P1 ; /* 0x000000ffff0d7224 */
/* 0x000fe400008e0603 */
/*0c80*/ FADD R7, R0, R7 ; /* 0x0000000700077221 */
/* 0x004fca0000000000 */
/*0c90*/ STG.E [R8.64], R7 ; /* 0x0000000708007986 */
/* 0x0001e2000c10190e */
/*0ca0*/ @P0 BRA 0x960 ; /* 0xfffffcb000000947 */
/* 0x000fea000383ffff */
/*0cb0*/ ISETP.NE.AND P0, PT, RZ, UR7, PT ; /* 0x00000007ff007c0c */
/* 0x000fda000bf05270 */
/*0cc0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0cd0*/ UIADD3 UR9, UP0, UR6, UR4, URZ ; /* 0x0000000406097290 */
/* 0x000fe4000ff1e03f */
/*0ce0*/ ULDC UR11, c[0x0][0x178] ; /* 0x00005e00000b7ab9 */
/* 0x000fe40000000800 */
/*0cf0*/ ULDC.64 UR12, c[0x0][0x168] ; /* 0x00005a00000c7ab9 */
/* 0x000fe40000000a00 */
/*0d00*/ ULEA.HI.X.SX32 UR10, UR4, URZ, 0x1, UP0 ; /* 0x0000003f040a7291 */
/* 0x000fe400080f0e3f */
/*0d10*/ ULEA UR8, UP0, UR9, UR12, 0x2 ; /* 0x0000000c09087291 */
/* 0x000fe4000f80103f */
/*0d20*/ UIADD3 UR4, UR4, UR11, URZ ; /* 0x0000000b04047290 */
/* 0x000fc4000fffe03f */
/*0d30*/ ULEA.HI.X UR9, UR9, UR13, UR10, 0x2, UP0 ; /* 0x0000000d09097291 */
/* 0x000fe400080f140a */
/*0d40*/ USHF.L.U32 UR4, UR4, 0x2, URZ ; /* 0x0000000204047899 */
/* 0x000fd2000800063f */
/*0d50*/ LDS R0, [UR4] ; /* 0x00000004ff007984 */
/* 0x000e620008000800 */
/*0d60*/ IMAD.U32 R5, RZ, RZ, UR9 ; /* 0x00000009ff057e24 */
/* 0x001fe4000f8e00ff */
/*0d70*/ IMAD.U32 R4, RZ, RZ, UR8 ; /* 0x00000008ff047e24 */
/* 0x000fca000f8e00ff */
/*0d80*/ LDG.E R5, [R4.64] ; /* 0x0000000e04057981 */
/* 0x000ea2000c1e1900 */
/*0d90*/ F2I.TRUNC.NTZ R0, R0 ; /* 0x0000000000007305 */
/* 0x002e24000020f100 */
/*0da0*/ IADD3 R2, R0, -0x1, RZ ; /* 0xffffffff00027810 */
/* 0x001fc80007ffe0ff */
/*0db0*/ IADD3 R3, P0, R2, UR5, RZ ; /* 0x0000000502037c10 */
/* 0x000fc8000ff1e0ff */
/*0dc0*/ LEA.HI.X.SX32 R6, R2, RZ, 0x1, P0 ; /* 0x000000ff02067211 */
/* 0x000fe400000f0eff */
/*0dd0*/ LEA R2, P0, R3, c[0x0][0x160], 0x2 ; /* 0x0000580003027a11 */
/* 0x000fc800078010ff */
/*0de0*/ LEA.HI.X R3, R3, c[0x0][0x164], R6, 0x2, P0 ; /* 0x0000590003037a11 */
/* 0x000fca00000f1406 */
/*0df0*/ LDG.E R6, [R2.64] ; /* 0x0000000e02067981 */
/* 0x000ea2000c1e1900 */
/*0e00*/ UIADD3 UR7, UR7, -0x1, URZ ; /* 0xffffffff07077890 */
/* 0x000fcc000fffe03f */
/*0e10*/ ISETP.NE.AND P0, PT, RZ, UR7, PT ; /* 0x00000007ff007c0c */
/* 0x000fe2000bf05270 */
/*0e20*/ UIADD3 UR8, UP0, UR8, 0x4, URZ ; /* 0x0000000408087890 */
/* 0x000fe4000ff1e03f */
/*0e30*/ UIADD3 UR4, UR4, 0x4, URZ ; /* 0x0000000404047890 */
/* 0x000fe4000fffe03f */
/*0e40*/ UIADD3.X UR9, URZ, UR9, URZ, UP0, !UPT ; /* 0x000000093f097290 */
/* 0x000fe200087fe43f */
/*0e50*/ FADD R7, R6, R5 ; /* 0x0000000506077221 */
/* 0x004fca0000000000 */
/*0e60*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x0001e4000c10190e */
/*0e70*/ @P0 BRA 0xd50 ; /* 0xfffffed000000947 */
/* 0x000fea000383ffff */
/*0e80*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0e90*/ BRA 0xe90; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0ea0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0eb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ec0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ed0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ee0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ef0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z24cuda_graph_maxpool_bpropPfPKfS1_iii
.globl _Z24cuda_graph_maxpool_bpropPfPKfS1_iii
.p2align 8
.type _Z24cuda_graph_maxpool_bpropPfPKfS1_iii,@function
_Z24cuda_graph_maxpool_bpropPfPKfS1_iii:
s_clause 0x2
s_load_b32 s6, s[0:1], 0x18
s_load_b64 s[2:3], s[0:1], 0x8
s_load_b32 s7, s[0:1], 0x20
s_mov_b32 s5, 0
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_mul_i32 s4, s15, s6
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_lshl_b64 s[4:5], s[4:5], 2
s_add_u32 s2, s2, s4
s_addc_u32 s3, s3, s5
s_cmp_lt_i32 s7, 1
s_cbranch_scc1 .LBB0_5
s_clause 0x1
s_load_b64 s[8:9], s[0:1], 0x10
s_load_b32 s10, s[0:1], 0x34
v_lshl_add_u32 v3, v0, 2, 0
v_mov_b32_e32 v1, v0
s_waitcnt lgkmcnt(0)
s_add_u32 s4, s8, s4
s_addc_u32 s5, s9, s5
s_and_b32 s8, s10, 0xffff
s_lshl_b32 s9, s6, 2
s_lshl_b32 s10, s8, 2
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_3
.p2align 6
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s11
v_add_nc_u32_e32 v3, s10, v3
v_add_nc_u32_e32 v1, s8, v1
s_add_i32 s7, s7, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s7, 0
s_cbranch_scc1 .LBB0_5
.LBB0_3:
s_mov_b32 s11, exec_lo
v_cmpx_gt_i32_e64 s6, v1
s_cbranch_execz .LBB0_2
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[4:5], 2, v[1:2]
v_add_co_u32 v6, vcc_lo, s2, v4
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v7, vcc_lo, s3, v5, vcc_lo
v_add_co_u32 v4, vcc_lo, s4, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
global_load_b32 v2, v[6:7], off
global_load_b32 v4, v[4:5], off
v_add_nc_u32_e32 v5, s9, v3
s_waitcnt vmcnt(1)
ds_store_b32 v3, v2
s_waitcnt vmcnt(0)
ds_store_b32 v5, v4
s_branch .LBB0_2
.LBB0_5:
s_set_inst_prefetch_distance 0x2
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_mov_b32 s4, exec_lo
v_cmpx_eq_u32_e32 1, v0
s_cbranch_execz .LBB0_9
s_cmp_lt_i32 s6, 1
s_cbranch_scc1 .LBB0_9
s_clause 0x1
s_load_b32 s4, s[0:1], 0x1c
s_load_b64 s[0:1], s[0:1], 0x0
s_mov_b32 s5, 0
v_mov_b32_e32 v0, 0
s_waitcnt lgkmcnt(0)
s_mul_i32 s4, s15, s4
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_lshl_b64 s[4:5], s[4:5], 2
s_add_u32 s0, s0, s4
s_addc_u32 s1, s1, s5
s_add_u32 s0, s0, -4
s_addc_u32 s1, s1, -1
s_lshl_b32 s4, s6, 2
s_delay_alu instid0(SALU_CYCLE_1)
s_add_i32 s4, s4, 0
.p2align 6
.LBB0_8:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
v_mov_b32_e32 v1, s4
s_add_i32 s6, s6, -1
ds_load_b32 v1, v1
s_waitcnt lgkmcnt(0)
v_cvt_i32_f32_e32 v1, v1
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[1:2]
v_add_co_u32 v1, vcc_lo, s0, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
global_load_b32 v3, v0, s[2:3]
global_load_b32 v4, v[1:2], off
s_add_u32 s2, s2, 4
s_addc_u32 s3, s3, 0
s_add_i32 s4, s4, 4
s_cmp_lg_u32 s6, 0
s_waitcnt vmcnt(0)
v_add_f32_e32 v3, v3, v4
global_store_b32 v[1:2], v3, off
s_cbranch_scc1 .LBB0_8
.LBB0_9:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z24cuda_graph_maxpool_bpropPfPKfS1_iii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z24cuda_graph_maxpool_bpropPfPKfS1_iii, .Lfunc_end0-_Z24cuda_graph_maxpool_bpropPfPKfS1_iii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
- .offset: 160
.size: 4
.value_kind: hidden_dynamic_lds_size
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z24cuda_graph_maxpool_bpropPfPKfS1_iii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z24cuda_graph_maxpool_bpropPfPKfS1_iii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000e5bc8_00000000-6_cuda_graph_maxpool_bprop.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z53__device_stub__Z24cuda_graph_maxpool_bpropPfPKfS1_iiiPfPKfS1_iii
.type _Z53__device_stub__Z24cuda_graph_maxpool_bpropPfPKfS1_iiiPfPKfS1_iii, @function
_Z53__device_stub__Z24cuda_graph_maxpool_bpropPfPKfS1_iiiPfPKfS1_iii:
.LFB2051:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z24cuda_graph_maxpool_bpropPfPKfS1_iii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z53__device_stub__Z24cuda_graph_maxpool_bpropPfPKfS1_iiiPfPKfS1_iii, .-_Z53__device_stub__Z24cuda_graph_maxpool_bpropPfPKfS1_iiiPfPKfS1_iii
.globl _Z24cuda_graph_maxpool_bpropPfPKfS1_iii
.type _Z24cuda_graph_maxpool_bpropPfPKfS1_iii, @function
_Z24cuda_graph_maxpool_bpropPfPKfS1_iii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z53__device_stub__Z24cuda_graph_maxpool_bpropPfPKfS1_iiiPfPKfS1_iii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z24cuda_graph_maxpool_bpropPfPKfS1_iii, .-_Z24cuda_graph_maxpool_bpropPfPKfS1_iii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z24cuda_graph_maxpool_bpropPfPKfS1_iii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z24cuda_graph_maxpool_bpropPfPKfS1_iii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "cuda_graph_maxpool_bprop.hip"
.globl _Z39__device_stub__cuda_graph_maxpool_bpropPfPKfS1_iii # -- Begin function _Z39__device_stub__cuda_graph_maxpool_bpropPfPKfS1_iii
.p2align 4, 0x90
.type _Z39__device_stub__cuda_graph_maxpool_bpropPfPKfS1_iii,@function
_Z39__device_stub__cuda_graph_maxpool_bpropPfPKfS1_iii: # @_Z39__device_stub__cuda_graph_maxpool_bpropPfPKfS1_iii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z24cuda_graph_maxpool_bpropPfPKfS1_iii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z39__device_stub__cuda_graph_maxpool_bpropPfPKfS1_iii, .Lfunc_end0-_Z39__device_stub__cuda_graph_maxpool_bpropPfPKfS1_iii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z24cuda_graph_maxpool_bpropPfPKfS1_iii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z24cuda_graph_maxpool_bpropPfPKfS1_iii,@object # @_Z24cuda_graph_maxpool_bpropPfPKfS1_iii
.section .rodata,"a",@progbits
.globl _Z24cuda_graph_maxpool_bpropPfPKfS1_iii
.p2align 3, 0x0
_Z24cuda_graph_maxpool_bpropPfPKfS1_iii:
.quad _Z39__device_stub__cuda_graph_maxpool_bpropPfPKfS1_iii
.size _Z24cuda_graph_maxpool_bpropPfPKfS1_iii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z24cuda_graph_maxpool_bpropPfPKfS1_iii"
.size .L__unnamed_1, 40
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z39__device_stub__cuda_graph_maxpool_bpropPfPKfS1_iii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z24cuda_graph_maxpool_bpropPfPKfS1_iii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
#define MAX_BUF 100000000
typedef unsigned int UINT;
UINT buffer[MAX_BUF];
// 核函数统一使用该命名，参数列表可自定义
__global__ void kernel()
{
} | code for sm_80
Function : _Z6kernelv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
#define MAX_BUF 100000000
typedef unsigned int UINT;
UINT buffer[MAX_BUF];
// 核函数统一使用该命名，参数列表可自定义
__global__ void kernel()
{
} | .file "tmpxft_00187321_00000000-6_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z24__device_stub__Z6kernelvv
.type _Z24__device_stub__Z6kernelvv, @function
_Z24__device_stub__Z6kernelvv:
.LFB2051:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z6kernelv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z24__device_stub__Z6kernelvv, .-_Z24__device_stub__Z6kernelvv
.globl _Z6kernelv
.type _Z6kernelv, @function
_Z6kernelv:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z24__device_stub__Z6kernelvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z6kernelv, .-_Z6kernelv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z6kernelv"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z6kernelv(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl buffer
.bss
.align 32
.type buffer, @object
.size buffer, 400000000
buffer:
.zero 400000000
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
#define MAX_BUF 100000000
typedef unsigned int UINT;
UINT buffer[MAX_BUF];
// 核函数统一使用该命名，参数列表可自定义
__global__ void kernel()
{
} | #include <hip/hip_runtime.h>
#include "includes.h"
#define MAX_BUF 100000000
typedef unsigned int UINT;
UINT buffer[MAX_BUF];
// 核函数统一使用该命名，参数列表可自定义
__global__ void kernel()
{
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
#define MAX_BUF 100000000
typedef unsigned int UINT;
UINT buffer[MAX_BUF];
// 核函数统一使用该命名，参数列表可自定义
__global__ void kernel()
{
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6kernelv
.globl _Z6kernelv
.p2align 8
.type _Z6kernelv,@function
_Z6kernelv:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6kernelv
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 0
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 0
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 1
.amdhsa_next_free_sgpr 1
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6kernelv, .Lfunc_end0-_Z6kernelv
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args: []
.group_segment_fixed_size: 0
.kernarg_segment_align: 4
.kernarg_segment_size: 0
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6kernelv
.private_segment_fixed_size: 0
.sgpr_count: 0
.sgpr_spill_count: 0
.symbol: _Z6kernelv.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 0
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
#define MAX_BUF 100000000
typedef unsigned int UINT;
UINT buffer[MAX_BUF];
// 核函数统一使用该命名，参数列表可自定义
__global__ void kernel()
{
} | .text
.file "kernel.hip"
.globl _Z21__device_stub__kernelv # -- Begin function _Z21__device_stub__kernelv
.p2align 4, 0x90
.type _Z21__device_stub__kernelv,@function
_Z21__device_stub__kernelv: # @_Z21__device_stub__kernelv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z6kernelv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z21__device_stub__kernelv, .Lfunc_end0-_Z21__device_stub__kernelv
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6kernelv, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type buffer,@object # @buffer
.bss
.globl buffer
.p2align 4, 0x0
buffer:
.zero 400000000
.size buffer, 400000000
.type _Z6kernelv,@object # @_Z6kernelv
.section .rodata,"a",@progbits
.globl _Z6kernelv
.p2align 3, 0x0
_Z6kernelv:
.quad _Z21__device_stub__kernelv
.size _Z6kernelv, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z6kernelv"
.size .L__unnamed_1, 11
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__kernelv
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6kernelv
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z6kernelv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6kernelv
.globl _Z6kernelv
.p2align 8
.type _Z6kernelv,@function
_Z6kernelv:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6kernelv
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 0
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 0
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 1
.amdhsa_next_free_sgpr 1
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6kernelv, .Lfunc_end0-_Z6kernelv
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args: []
.group_segment_fixed_size: 0
.kernarg_segment_align: 4
.kernarg_segment_size: 0
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6kernelv
.private_segment_fixed_size: 0
.sgpr_count: 0
.sgpr_spill_count: 0
.symbol: _Z6kernelv.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 0
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00187321_00000000-6_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z24__device_stub__Z6kernelvv
.type _Z24__device_stub__Z6kernelvv, @function
_Z24__device_stub__Z6kernelvv:
.LFB2051:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z6kernelv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z24__device_stub__Z6kernelvv, .-_Z24__device_stub__Z6kernelvv
.globl _Z6kernelv
.type _Z6kernelv, @function
_Z6kernelv:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z24__device_stub__Z6kernelvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z6kernelv, .-_Z6kernelv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z6kernelv"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z6kernelv(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl buffer
.bss
.align 32
.type buffer, @object
.size buffer, 400000000
buffer:
.zero 400000000
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "kernel.hip"
.globl _Z21__device_stub__kernelv # -- Begin function _Z21__device_stub__kernelv
.p2align 4, 0x90
.type _Z21__device_stub__kernelv,@function
_Z21__device_stub__kernelv: # @_Z21__device_stub__kernelv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z6kernelv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z21__device_stub__kernelv, .Lfunc_end0-_Z21__device_stub__kernelv
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6kernelv, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type buffer,@object # @buffer
.bss
.globl buffer
.p2align 4, 0x0
buffer:
.zero 400000000
.size buffer, 400000000
.type _Z6kernelv,@object # @_Z6kernelv
.section .rodata,"a",@progbits
.globl _Z6kernelv
.p2align 3, 0x0
_Z6kernelv:
.quad _Z21__device_stub__kernelv
.size _Z6kernelv, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z6kernelv"
.size .L__unnamed_1, 11
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__kernelv
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6kernelv
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void matrixAdd_A_Kernel(float* A, float* B, float* C, size_t pitch, int width){
//compute indexes
int row = blockIdx.x * blockDim.x + threadIdx.x;
int col = blockIdx.y * blockDim.y + threadIdx.y;
int rowWidthWithPad = pitch/sizeof(float);
if(row < width && col < width)
C[row * rowWidthWithPad + col] = A[row * rowWidthWithPad + col] + B[row * rowWidthWithPad + col];
} | code for sm_80
Function : _Z18matrixAdd_A_KernelPfS_S_mi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e280000002600 */
/*0020*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e280000002200 */
/*0030*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e680000002500 */
/*0040*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0050*/ IMAD R3, R3, c[0x0][0x4], R2 ; /* 0x0000010003037a24 */
/* 0x001fca00078e0202 */
/*0060*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x180], PT ; /* 0x0000600003007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R0, R0, c[0x0][0x0], R5 ; /* 0x0000000000007a24 */
/* 0x002fca00078e0205 */
/*0080*/ ISETP.GE.OR P0, PT, R0, c[0x0][0x180], P0 ; /* 0x0000600000007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ ULDC.64 UR4, c[0x0][0x178] ; /* 0x00005e0000047ab9 */
/* 0x000fe20000000a00 */
/*00b0*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*00c0*/ USHF.R.U64 UR4, UR4, 0x2, UR5 ; /* 0x0000000204047899 */
/* 0x000fcc0008001205 */
/*00d0*/ IMAD R0, R0, UR4, R3 ; /* 0x0000000400007c24 */
/* 0x000fe2000f8e0203 */
/*00e0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*00f0*/ IMAD.WIDE R4, R0, R7, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x000fc800078e0207 */
/*0100*/ IMAD.WIDE R2, R0.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x0c0fe400078e0207 */
/*0110*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*0120*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*0130*/ IMAD.WIDE R6, R0, R7, c[0x0][0x170] ; /* 0x00005c0000067625 */
/* 0x000fc800078e0207 */
/*0140*/ FADD R9, R4, R3 ; /* 0x0000000304097221 */
/* 0x004fca0000000000 */
/*0150*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*0160*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0170*/ BRA 0x170; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void matrixAdd_A_Kernel(float* A, float* B, float* C, size_t pitch, int width){
//compute indexes
int row = blockIdx.x * blockDim.x + threadIdx.x;
int col = blockIdx.y * blockDim.y + threadIdx.y;
int rowWidthWithPad = pitch/sizeof(float);
if(row < width && col < width)
C[row * rowWidthWithPad + col] = A[row * rowWidthWithPad + col] + B[row * rowWidthWithPad + col];
} | .file "tmpxft_0006e0a6_00000000-6_matrixAdd_A_Kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z44__device_stub__Z18matrixAdd_A_KernelPfS_S_miPfS_S_mi
.type _Z44__device_stub__Z18matrixAdd_A_KernelPfS_S_miPfS_S_mi, @function
_Z44__device_stub__Z18matrixAdd_A_KernelPfS_S_miPfS_S_mi:
.LFB2051:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movl %r8d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 12(%rsp), %rax
movq %rax, 144(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 184
pushq 56(%rsp)
.cfi_def_cfa_offset 192
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z18matrixAdd_A_KernelPfS_S_mi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z44__device_stub__Z18matrixAdd_A_KernelPfS_S_miPfS_S_mi, .-_Z44__device_stub__Z18matrixAdd_A_KernelPfS_S_miPfS_S_mi
.globl _Z18matrixAdd_A_KernelPfS_S_mi
.type _Z18matrixAdd_A_KernelPfS_S_mi, @function
_Z18matrixAdd_A_KernelPfS_S_mi:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z44__device_stub__Z18matrixAdd_A_KernelPfS_S_miPfS_S_mi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z18matrixAdd_A_KernelPfS_S_mi, .-_Z18matrixAdd_A_KernelPfS_S_mi
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z18matrixAdd_A_KernelPfS_S_mi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z18matrixAdd_A_KernelPfS_S_mi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void matrixAdd_A_Kernel(float* A, float* B, float* C, size_t pitch, int width){
//compute indexes
int row = blockIdx.x * blockDim.x + threadIdx.x;
int col = blockIdx.y * blockDim.y + threadIdx.y;
int rowWidthWithPad = pitch/sizeof(float);
if(row < width && col < width)
C[row * rowWidthWithPad + col] = A[row * rowWidthWithPad + col] + B[row * rowWidthWithPad + col];
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void matrixAdd_A_Kernel(float* A, float* B, float* C, size_t pitch, int width){
//compute indexes
int row = blockIdx.x * blockDim.x + threadIdx.x;
int col = blockIdx.y * blockDim.y + threadIdx.y;
int rowWidthWithPad = pitch/sizeof(float);
if(row < width && col < width)
C[row * rowWidthWithPad + col] = A[row * rowWidthWithPad + col] + B[row * rowWidthWithPad + col];
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void matrixAdd_A_Kernel(float* A, float* B, float* C, size_t pitch, int width){
//compute indexes
int row = blockIdx.x * blockDim.x + threadIdx.x;
int col = blockIdx.y * blockDim.y + threadIdx.y;
int rowWidthWithPad = pitch/sizeof(float);
if(row < width && col < width)
C[row * rowWidthWithPad + col] = A[row * rowWidthWithPad + col] + B[row * rowWidthWithPad + col];
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z18matrixAdd_A_KernelPfS_S_mi
.globl _Z18matrixAdd_A_KernelPfS_S_mi
.p2align 8
.type _Z18matrixAdd_A_KernelPfS_S_mi,@function
_Z18matrixAdd_A_KernelPfS_S_mi:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x34
s_load_b32 s3, s[0:1], 0x20
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s2, 0xffff
s_lshr_b32 s2, s2, 16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[0:1], null, s14, s4, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s2, v[3:4]
s_mov_b32 s2, exec_lo
v_max_i32_e32 v2, v0, v1
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s3, v2
s_cbranch_execz .LBB0_2
s_load_b256 s[0:7], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
v_alignbit_b32 v4, s7, s6, 2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, v0, v4, v[1:2]
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[2:3]
v_add_co_u32 v2, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s4, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v2, v3
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z18matrixAdd_A_KernelPfS_S_mi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z18matrixAdd_A_KernelPfS_S_mi, .Lfunc_end0-_Z18matrixAdd_A_KernelPfS_S_mi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 8
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z18matrixAdd_A_KernelPfS_S_mi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z18matrixAdd_A_KernelPfS_S_mi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void matrixAdd_A_Kernel(float* A, float* B, float* C, size_t pitch, int width){
//compute indexes
int row = blockIdx.x * blockDim.x + threadIdx.x;
int col = blockIdx.y * blockDim.y + threadIdx.y;
int rowWidthWithPad = pitch/sizeof(float);
if(row < width && col < width)
C[row * rowWidthWithPad + col] = A[row * rowWidthWithPad + col] + B[row * rowWidthWithPad + col];
} | .text
.file "matrixAdd_A_Kernel.hip"
.globl _Z33__device_stub__matrixAdd_A_KernelPfS_S_mi # -- Begin function _Z33__device_stub__matrixAdd_A_KernelPfS_S_mi
.p2align 4, 0x90
.type _Z33__device_stub__matrixAdd_A_KernelPfS_S_mi,@function
_Z33__device_stub__matrixAdd_A_KernelPfS_S_mi: # @_Z33__device_stub__matrixAdd_A_KernelPfS_S_mi
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movl %r8d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 12(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z18matrixAdd_A_KernelPfS_S_mi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end0:
.size _Z33__device_stub__matrixAdd_A_KernelPfS_S_mi, .Lfunc_end0-_Z33__device_stub__matrixAdd_A_KernelPfS_S_mi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z18matrixAdd_A_KernelPfS_S_mi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z18matrixAdd_A_KernelPfS_S_mi,@object # @_Z18matrixAdd_A_KernelPfS_S_mi
.section .rodata,"a",@progbits
.globl _Z18matrixAdd_A_KernelPfS_S_mi
.p2align 3, 0x0
_Z18matrixAdd_A_KernelPfS_S_mi:
.quad _Z33__device_stub__matrixAdd_A_KernelPfS_S_mi
.size _Z18matrixAdd_A_KernelPfS_S_mi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z18matrixAdd_A_KernelPfS_S_mi"
.size .L__unnamed_1, 31
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z33__device_stub__matrixAdd_A_KernelPfS_S_mi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z18matrixAdd_A_KernelPfS_S_mi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z18matrixAdd_A_KernelPfS_S_mi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e280000002600 */
/*0020*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e280000002200 */
/*0030*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e680000002500 */
/*0040*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0050*/ IMAD R3, R3, c[0x0][0x4], R2 ; /* 0x0000010003037a24 */
/* 0x001fca00078e0202 */
/*0060*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x180], PT ; /* 0x0000600003007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R0, R0, c[0x0][0x0], R5 ; /* 0x0000000000007a24 */
/* 0x002fca00078e0205 */
/*0080*/ ISETP.GE.OR P0, PT, R0, c[0x0][0x180], P0 ; /* 0x0000600000007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ ULDC.64 UR4, c[0x0][0x178] ; /* 0x00005e0000047ab9 */
/* 0x000fe20000000a00 */
/*00b0*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*00c0*/ USHF.R.U64 UR4, UR4, 0x2, UR5 ; /* 0x0000000204047899 */
/* 0x000fcc0008001205 */
/*00d0*/ IMAD R0, R0, UR4, R3 ; /* 0x0000000400007c24 */
/* 0x000fe2000f8e0203 */
/*00e0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*00f0*/ IMAD.WIDE R4, R0, R7, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x000fc800078e0207 */
/*0100*/ IMAD.WIDE R2, R0.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x0c0fe400078e0207 */
/*0110*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*0120*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*0130*/ IMAD.WIDE R6, R0, R7, c[0x0][0x170] ; /* 0x00005c0000067625 */
/* 0x000fc800078e0207 */
/*0140*/ FADD R9, R4, R3 ; /* 0x0000000304097221 */
/* 0x004fca0000000000 */
/*0150*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*0160*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0170*/ BRA 0x170; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z18matrixAdd_A_KernelPfS_S_mi
.globl _Z18matrixAdd_A_KernelPfS_S_mi
.p2align 8
.type _Z18matrixAdd_A_KernelPfS_S_mi,@function
_Z18matrixAdd_A_KernelPfS_S_mi:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x34
s_load_b32 s3, s[0:1], 0x20
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s2, 0xffff
s_lshr_b32 s2, s2, 16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[0:1], null, s14, s4, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s2, v[3:4]
s_mov_b32 s2, exec_lo
v_max_i32_e32 v2, v0, v1
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s3, v2
s_cbranch_execz .LBB0_2
s_load_b256 s[0:7], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
v_alignbit_b32 v4, s7, s6, 2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, v0, v4, v[1:2]
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[2:3]
v_add_co_u32 v2, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s4, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v2, v3
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z18matrixAdd_A_KernelPfS_S_mi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z18matrixAdd_A_KernelPfS_S_mi, .Lfunc_end0-_Z18matrixAdd_A_KernelPfS_S_mi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 8
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z18matrixAdd_A_KernelPfS_S_mi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z18matrixAdd_A_KernelPfS_S_mi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0006e0a6_00000000-6_matrixAdd_A_Kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z44__device_stub__Z18matrixAdd_A_KernelPfS_S_miPfS_S_mi
.type _Z44__device_stub__Z18matrixAdd_A_KernelPfS_S_miPfS_S_mi, @function
_Z44__device_stub__Z18matrixAdd_A_KernelPfS_S_miPfS_S_mi:
.LFB2051:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movl %r8d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 12(%rsp), %rax
movq %rax, 144(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 184
pushq 56(%rsp)
.cfi_def_cfa_offset 192
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z18matrixAdd_A_KernelPfS_S_mi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z44__device_stub__Z18matrixAdd_A_KernelPfS_S_miPfS_S_mi, .-_Z44__device_stub__Z18matrixAdd_A_KernelPfS_S_miPfS_S_mi
.globl _Z18matrixAdd_A_KernelPfS_S_mi
.type _Z18matrixAdd_A_KernelPfS_S_mi, @function
_Z18matrixAdd_A_KernelPfS_S_mi:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z44__device_stub__Z18matrixAdd_A_KernelPfS_S_miPfS_S_mi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z18matrixAdd_A_KernelPfS_S_mi, .-_Z18matrixAdd_A_KernelPfS_S_mi
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z18matrixAdd_A_KernelPfS_S_mi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z18matrixAdd_A_KernelPfS_S_mi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "matrixAdd_A_Kernel.hip"
.globl _Z33__device_stub__matrixAdd_A_KernelPfS_S_mi # -- Begin function _Z33__device_stub__matrixAdd_A_KernelPfS_S_mi
.p2align 4, 0x90
.type _Z33__device_stub__matrixAdd_A_KernelPfS_S_mi,@function
_Z33__device_stub__matrixAdd_A_KernelPfS_S_mi: # @_Z33__device_stub__matrixAdd_A_KernelPfS_S_mi
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movl %r8d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 12(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z18matrixAdd_A_KernelPfS_S_mi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end0:
.size _Z33__device_stub__matrixAdd_A_KernelPfS_S_mi, .Lfunc_end0-_Z33__device_stub__matrixAdd_A_KernelPfS_S_mi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z18matrixAdd_A_KernelPfS_S_mi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z18matrixAdd_A_KernelPfS_S_mi,@object # @_Z18matrixAdd_A_KernelPfS_S_mi
.section .rodata,"a",@progbits
.globl _Z18matrixAdd_A_KernelPfS_S_mi
.p2align 3, 0x0
_Z18matrixAdd_A_KernelPfS_S_mi:
.quad _Z33__device_stub__matrixAdd_A_KernelPfS_S_mi
.size _Z18matrixAdd_A_KernelPfS_S_mi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z18matrixAdd_A_KernelPfS_S_mi"
.size .L__unnamed_1, 31
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z33__device_stub__matrixAdd_A_KernelPfS_S_mi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z18matrixAdd_A_KernelPfS_S_mi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdlib.h>
#include <stdio.h>
#include <string.h>
#include <math.h>
#include <cuda.h>
#include <cuda_runtime.h>
#include <cuda.h>
#include <device_launch_parameters.h>
#define LIST_SIZE_GLOBAL 5000000
#define LIST_SIZE 10000
extern "C" __device__ unsigned long long load_store_index[LIST_SIZE];
extern "C" __device__ unsigned long long load_store_value[LIST_SIZE];
extern "C" __device__ double load_store_double[LIST_SIZE];
extern "C" __device__ unsigned long long load_store_double_index[LIST_SIZE];
extern "C" __device__ unsigned long long record_flag;
extern "C" __device__ unsigned long long call_count;
int memPro_kernel = 0;
void bambooLogRecordOff(){
long long local_record = 0;
cudaMemcpyToSymbol(record_flag, &local_record, sizeof(long long), 0, cudaMemcpyHostToDevice);
}
void bambooLogKernelBegin(long long i) {
cudaMemcpyToSymbol(call_count, &i, sizeof(long long), 0, cudaMemcpyHostToDevice);
i = 1;
cudaMemcpyToSymbol(record_flag, &i, sizeof(long long), 0, cudaMemcpyHostToDevice);
}
void bambooLogKernelEnd()
{
unsigned long long loadStoreIndex[LIST_SIZE] = {0};
unsigned long long loadStoreValue[LIST_SIZE] = {0};
unsigned long long loadStoreIndex_double[LIST_SIZE] = {0};
double loadStoreValue_double[LIST_SIZE] = {0};
FILE *profileFile = fopen("profile_mem_val_result.txt", "a");
for (int j=0; j < LIST_SIZE_GLOBAL; j+=LIST_SIZE)
{
cudaMemcpyFromSymbol(&loadStoreIndex, load_store_index, LIST_SIZE * sizeof(unsigned long long), j*sizeof(unsigned long long), cudaMemcpyDeviceToHost);
cudaMemcpyFromSymbol(&loadStoreValue, load_store_value, LIST_SIZE * sizeof(unsigned long long), j*sizeof(unsigned long long), cudaMemcpyDeviceToHost);
for(long long i=0; i < LIST_SIZE && loadStoreIndex[i] != 0; i++)
{
fprintf(profileFile, "%lld %lld\n", loadStoreIndex[i], loadStoreValue[i]);
}
}
for (int j=0; j < LIST_SIZE_GLOBAL; j+=LIST_SIZE)
{
cudaMemcpyFromSymbol(&loadStoreIndex_double, load_store_double_index, LIST_SIZE * sizeof(unsigned long long), j*sizeof(unsigned long long), cudaMemcpyDeviceToHost);
cudaMemcpyFromSymbol(&loadStoreValue_double, load_store_double, LIST_SIZE * sizeof(double), j*sizeof(double), cudaMemcpyDeviceToHost);
for(long long i=0; i < LIST_SIZE && loadStoreIndex_double[i] != 0; i++)
{
fprintf(profileFile, "%lld %.40f\n", loadStoreIndex_double[i], loadStoreValue_double[i]);
}
}
fclose(profileFile);
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdlib.h>
#include <stdio.h>
#include <string.h>
#include <math.h>
#include <cuda.h>
#include <cuda_runtime.h>
#include <cuda.h>
#include <device_launch_parameters.h>
#define LIST_SIZE_GLOBAL 5000000
#define LIST_SIZE 10000
extern "C" __device__ unsigned long long load_store_index[LIST_SIZE];
extern "C" __device__ unsigned long long load_store_value[LIST_SIZE];
extern "C" __device__ double load_store_double[LIST_SIZE];
extern "C" __device__ unsigned long long load_store_double_index[LIST_SIZE];
extern "C" __device__ unsigned long long record_flag;
extern "C" __device__ unsigned long long call_count;
int memPro_kernel = 0;
void bambooLogRecordOff(){
long long local_record = 0;
cudaMemcpyToSymbol(record_flag, &local_record, sizeof(long long), 0, cudaMemcpyHostToDevice);
}
void bambooLogKernelBegin(long long i) {
cudaMemcpyToSymbol(call_count, &i, sizeof(long long), 0, cudaMemcpyHostToDevice);
i = 1;
cudaMemcpyToSymbol(record_flag, &i, sizeof(long long), 0, cudaMemcpyHostToDevice);
}
void bambooLogKernelEnd()
{
unsigned long long loadStoreIndex[LIST_SIZE] = {0};
unsigned long long loadStoreValue[LIST_SIZE] = {0};
unsigned long long loadStoreIndex_double[LIST_SIZE] = {0};
double loadStoreValue_double[LIST_SIZE] = {0};
FILE *profileFile = fopen("profile_mem_val_result.txt", "a");
for (int j=0; j < LIST_SIZE_GLOBAL; j+=LIST_SIZE)
{
cudaMemcpyFromSymbol(&loadStoreIndex, load_store_index, LIST_SIZE * sizeof(unsigned long long), j*sizeof(unsigned long long), cudaMemcpyDeviceToHost);
cudaMemcpyFromSymbol(&loadStoreValue, load_store_value, LIST_SIZE * sizeof(unsigned long long), j*sizeof(unsigned long long), cudaMemcpyDeviceToHost);
for(long long i=0; i < LIST_SIZE && loadStoreIndex[i] != 0; i++)
{
fprintf(profileFile, "%lld %lld\n", loadStoreIndex[i], loadStoreValue[i]);
}
}
for (int j=0; j < LIST_SIZE_GLOBAL; j+=LIST_SIZE)
{
cudaMemcpyFromSymbol(&loadStoreIndex_double, load_store_double_index, LIST_SIZE * sizeof(unsigned long long), j*sizeof(unsigned long long), cudaMemcpyDeviceToHost);
cudaMemcpyFromSymbol(&loadStoreValue_double, load_store_double, LIST_SIZE * sizeof(double), j*sizeof(double), cudaMemcpyDeviceToHost);
for(long long i=0; i < LIST_SIZE && loadStoreIndex_double[i] != 0; i++)
{
fprintf(profileFile, "%lld %.40f\n", loadStoreIndex_double[i], loadStoreValue_double[i]);
}
}
fclose(profileFile);
} | .file "tmpxft_001432cf_00000000-6_record_data.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z18bambooLogRecordOffv
.type _Z18bambooLogRecordOffv, @function
_Z18bambooLogRecordOffv:
.LFB2057:
.cfi_startproc
endbr64
subq $24, %rsp
.cfi_def_cfa_offset 32
movq %fs:40, %rax
movq %rax, 8(%rsp)
xorl %eax, %eax
movq $0, (%rsp)
movq %rsp, %rsi
movl $1, %r8d
movl $0, %ecx
movl $8, %edx
leaq record_flag(%rip), %rdi
call cudaMemcpyToSymbol@PLT
movq 8(%rsp), %rax
subq %fs:40, %rax
jne .L6
addq $24, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L6:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size _Z18bambooLogRecordOffv, .-_Z18bambooLogRecordOffv
.globl _Z20bambooLogKernelBeginx
.type _Z20bambooLogKernelBeginx, @function
_Z20bambooLogKernelBeginx:
.LFB2058:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $16, %rsp
.cfi_def_cfa_offset 32
movq %rdi, 8(%rsp)
leaq 8(%rsp), %rbx
movl $1, %r8d
movl $0, %ecx
movl $8, %edx
movq %rbx, %rsi
leaq call_count(%rip), %rdi
call cudaMemcpyToSymbol@PLT
movq $1, 8(%rsp)
movl $1, %r8d
movl $0, %ecx
movl $8, %edx
movq %rbx, %rsi
leaq record_flag(%rip), %rdi
call cudaMemcpyToSymbol@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _Z20bambooLogKernelBeginx, .-_Z20bambooLogKernelBeginx
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "a"
.LC1:
.string "profile_mem_val_result.txt"
.LC2:
.string "%lld %lld\n"
.LC3:
.string "%lld %.40f\n"
.text
.globl _Z18bambooLogKernelEndv
.type _Z18bambooLogKernelEndv, @function
_Z18bambooLogKernelEndv:
.LFB2059:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
leaq -319488(%rsp), %r11
.cfi_def_cfa 11, 319544
.LPSRL0:
subq $4096, %rsp
orq $0, (%rsp)
cmpq %r11, %rsp
jne .LPSRL0
.cfi_def_cfa_register 7
subq $536, %rsp
.cfi_def_cfa_offset 320080
movq %fs:40, %rax
movq %rax, 320008(%rsp)
xorl %eax, %eax
movq %rsp, %rdi
movl $80000, %edx
movl $0, %esi
call memset@PLT
leaq 80000(%rsp), %rdi
movl $80000, %edx
movl $0, %esi
call memset@PLT
leaq 160000(%rsp), %rdi
movl $80000, %edx
movl $0, %esi
call memset@PLT
leaq 240000(%rsp), %rdi
movl $80000, %edx
movl $0, %esi
call memset@PLT
leaq .LC0(%rip), %rsi
leaq .LC1(%rip), %rdi
call fopen@PLT
movq %rax, %rbp
movl $0, %r14d
movq %rsp, %r12
leaq load_store_index(%rip), %r15
leaq .LC2(%rip), %r13
jmp .L13
.L11:
addq $80000, %r14
cmpq $40000000, %r14
je .L22
.L13:
movl $2, %r8d
movq %r14, %rcx
movl $80000, %edx
movq %r15, %rsi
movq %r12, %rdi
call cudaMemcpyFromSymbol@PLT
leaq 80000(%rsp), %rdi
movl $2, %r8d
movq %r14, %rcx
movl $80000, %edx
leaq load_store_value(%rip), %rsi
call cudaMemcpyFromSymbol@PLT
movl $0, %ebx
.L10:
movq (%r12,%rbx,8), %rcx
testq %rcx, %rcx
je .L11
movq 80000(%rsp,%rbx,8), %r8
movq %r13, %rdx
movl $2, %esi
movq %rbp, %rdi
movl $0, %eax
call __fprintf_chk@PLT
addq $1, %rbx
cmpq $10000, %rbx
jne .L10
jmp .L11
.L22:
movl $0, %r14d
leaq 160000(%rsp), %r12
leaq load_store_double_index(%rip), %r15
leaq .LC3(%rip), %r13
jmp .L17
.L15:
addq $80000, %r14
cmpq $40000000, %r14
je .L23
.L17:
movl $2, %r8d
movq %r14, %rcx
movl $80000, %edx
movq %r15, %rsi
movq %r12, %rdi
call cudaMemcpyFromSymbol@PLT
leaq 240000(%rsp), %rdi
movl $2, %r8d
movq %r14, %rcx
movl $80000, %edx
leaq load_store_double(%rip), %rsi
call cudaMemcpyFromSymbol@PLT
movl $0, %ebx
.L14:
movq (%r12,%rbx,8), %rcx
testq %rcx, %rcx
je .L15
movsd 240000(%rsp,%rbx,8), %xmm0
movq %r13, %rdx
movl $2, %esi
movq %rbp, %rdi
movl $1, %eax
call __fprintf_chk@PLT
addq $1, %rbx
cmpq $10000, %rbx
jne .L14
jmp .L15
.L23:
movq %rbp, %rdi
call fclose@PLT
movq 320008(%rsp), %rax
subq %fs:40, %rax
jne .L24
addq $320024, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L24:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size _Z18bambooLogKernelEndv, .-_Z18bambooLogKernelEndv
.section .rodata.str1.1
.LC4:
.string "load_store_index"
.LC5:
.string "load_store_value"
.LC6:
.string "load_store_double"
.LC7:
.string "load_store_double_index"
.LC8:
.string "record_flag"
.LC9:
.string "call_count"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $80000, %r9d
movl $1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq load_store_index(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $80000, %r9d
movl $1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq load_store_value(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $80000, %r9d
movl $1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq load_store_double(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $80000, %r9d
movl $1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq load_store_double_index(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $8, %r9d
movl $1, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq record_flag(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $8, %r9d
movl $1, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq call_count(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl memPro_kernel
.bss
.align 4
.type memPro_kernel, @object
.size memPro_kernel, 4
memPro_kernel:
.zero 4
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdlib.h>
#include <stdio.h>
#include <string.h>
#include <math.h>
#include <cuda.h>
#include <cuda_runtime.h>
#include <cuda.h>
#include <device_launch_parameters.h>
#define LIST_SIZE_GLOBAL 5000000
#define LIST_SIZE 10000
extern "C" __device__ unsigned long long load_store_index[LIST_SIZE];
extern "C" __device__ unsigned long long load_store_value[LIST_SIZE];
extern "C" __device__ double load_store_double[LIST_SIZE];
extern "C" __device__ unsigned long long load_store_double_index[LIST_SIZE];
extern "C" __device__ unsigned long long record_flag;
extern "C" __device__ unsigned long long call_count;
int memPro_kernel = 0;
void bambooLogRecordOff(){
long long local_record = 0;
cudaMemcpyToSymbol(record_flag, &local_record, sizeof(long long), 0, cudaMemcpyHostToDevice);
}
void bambooLogKernelBegin(long long i) {
cudaMemcpyToSymbol(call_count, &i, sizeof(long long), 0, cudaMemcpyHostToDevice);
i = 1;
cudaMemcpyToSymbol(record_flag, &i, sizeof(long long), 0, cudaMemcpyHostToDevice);
}
void bambooLogKernelEnd()
{
unsigned long long loadStoreIndex[LIST_SIZE] = {0};
unsigned long long loadStoreValue[LIST_SIZE] = {0};
unsigned long long loadStoreIndex_double[LIST_SIZE] = {0};
double loadStoreValue_double[LIST_SIZE] = {0};
FILE *profileFile = fopen("profile_mem_val_result.txt", "a");
for (int j=0; j < LIST_SIZE_GLOBAL; j+=LIST_SIZE)
{
cudaMemcpyFromSymbol(&loadStoreIndex, load_store_index, LIST_SIZE * sizeof(unsigned long long), j*sizeof(unsigned long long), cudaMemcpyDeviceToHost);
cudaMemcpyFromSymbol(&loadStoreValue, load_store_value, LIST_SIZE * sizeof(unsigned long long), j*sizeof(unsigned long long), cudaMemcpyDeviceToHost);
for(long long i=0; i < LIST_SIZE && loadStoreIndex[i] != 0; i++)
{
fprintf(profileFile, "%lld %lld\n", loadStoreIndex[i], loadStoreValue[i]);
}
}
for (int j=0; j < LIST_SIZE_GLOBAL; j+=LIST_SIZE)
{
cudaMemcpyFromSymbol(&loadStoreIndex_double, load_store_double_index, LIST_SIZE * sizeof(unsigned long long), j*sizeof(unsigned long long), cudaMemcpyDeviceToHost);
cudaMemcpyFromSymbol(&loadStoreValue_double, load_store_double, LIST_SIZE * sizeof(double), j*sizeof(double), cudaMemcpyDeviceToHost);
for(long long i=0; i < LIST_SIZE && loadStoreIndex_double[i] != 0; i++)
{
fprintf(profileFile, "%lld %.40f\n", loadStoreIndex_double[i], loadStoreValue_double[i]);
}
}
fclose(profileFile);
} | #include <stdlib.h>
#include <stdio.h>
#include <string.h>
#include <math.h>
#include <hip/hip_runtime.h>
#define LIST_SIZE_GLOBAL 5000000
#define LIST_SIZE 10000
extern "C" __device__ unsigned long long load_store_index[LIST_SIZE];
extern "C" __device__ unsigned long long load_store_value[LIST_SIZE];
extern "C" __device__ double load_store_double[LIST_SIZE];
extern "C" __device__ unsigned long long load_store_double_index[LIST_SIZE];
extern "C" __device__ unsigned long long record_flag;
extern "C" __device__ unsigned long long call_count;
int memPro_kernel = 0;
void bambooLogRecordOff(){
long long local_record = 0;
hipMemcpyToSymbol(HIP_SYMBOL(record_flag), &local_record, sizeof(long long), 0, hipMemcpyHostToDevice);
}
void bambooLogKernelBegin(long long i) {
hipMemcpyToSymbol(HIP_SYMBOL(call_count), &i, sizeof(long long), 0, hipMemcpyHostToDevice);
i = 1;
hipMemcpyToSymbol(HIP_SYMBOL(record_flag), &i, sizeof(long long), 0, hipMemcpyHostToDevice);
}
void bambooLogKernelEnd()
{
unsigned long long loadStoreIndex[LIST_SIZE] = {0};
unsigned long long loadStoreValue[LIST_SIZE] = {0};
unsigned long long loadStoreIndex_double[LIST_SIZE] = {0};
double loadStoreValue_double[LIST_SIZE] = {0};
FILE *profileFile = fopen("profile_mem_val_result.txt", "a");
for (int j=0; j < LIST_SIZE_GLOBAL; j+=LIST_SIZE)
{
hipMemcpyFromSymbol(&loadStoreIndex, HIP_SYMBOL(load_store_index), LIST_SIZE * sizeof(unsigned long long), j*sizeof(unsigned long long), hipMemcpyDeviceToHost);
hipMemcpyFromSymbol(&loadStoreValue, HIP_SYMBOL(load_store_value), LIST_SIZE * sizeof(unsigned long long), j*sizeof(unsigned long long), hipMemcpyDeviceToHost);
for(long long i=0; i < LIST_SIZE && loadStoreIndex[i] != 0; i++)
{
fprintf(profileFile, "%lld %lld\n", loadStoreIndex[i], loadStoreValue[i]);
}
}
for (int j=0; j < LIST_SIZE_GLOBAL; j+=LIST_SIZE)
{
hipMemcpyFromSymbol(&loadStoreIndex_double, HIP_SYMBOL(load_store_double_index), LIST_SIZE * sizeof(unsigned long long), j*sizeof(unsigned long long), hipMemcpyDeviceToHost);
hipMemcpyFromSymbol(&loadStoreValue_double, HIP_SYMBOL(load_store_double), LIST_SIZE * sizeof(double), j*sizeof(double), hipMemcpyDeviceToHost);
for(long long i=0; i < LIST_SIZE && loadStoreIndex_double[i] != 0; i++)
{
fprintf(profileFile, "%lld %.40f\n", loadStoreIndex_double[i], loadStoreValue_double[i]);
}
}
fclose(profileFile);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <stdlib.h>
#include <stdio.h>
#include <string.h>
#include <math.h>
#include <hip/hip_runtime.h>
#define LIST_SIZE_GLOBAL 5000000
#define LIST_SIZE 10000
extern "C" __device__ unsigned long long load_store_index[LIST_SIZE];
extern "C" __device__ unsigned long long load_store_value[LIST_SIZE];
extern "C" __device__ double load_store_double[LIST_SIZE];
extern "C" __device__ unsigned long long load_store_double_index[LIST_SIZE];
extern "C" __device__ unsigned long long record_flag;
extern "C" __device__ unsigned long long call_count;
int memPro_kernel = 0;
void bambooLogRecordOff(){
long long local_record = 0;
hipMemcpyToSymbol(HIP_SYMBOL(record_flag), &local_record, sizeof(long long), 0, hipMemcpyHostToDevice);
}
void bambooLogKernelBegin(long long i) {
hipMemcpyToSymbol(HIP_SYMBOL(call_count), &i, sizeof(long long), 0, hipMemcpyHostToDevice);
i = 1;
hipMemcpyToSymbol(HIP_SYMBOL(record_flag), &i, sizeof(long long), 0, hipMemcpyHostToDevice);
}
void bambooLogKernelEnd()
{
unsigned long long loadStoreIndex[LIST_SIZE] = {0};
unsigned long long loadStoreValue[LIST_SIZE] = {0};
unsigned long long loadStoreIndex_double[LIST_SIZE] = {0};
double loadStoreValue_double[LIST_SIZE] = {0};
FILE *profileFile = fopen("profile_mem_val_result.txt", "a");
for (int j=0; j < LIST_SIZE_GLOBAL; j+=LIST_SIZE)
{
hipMemcpyFromSymbol(&loadStoreIndex, HIP_SYMBOL(load_store_index), LIST_SIZE * sizeof(unsigned long long), j*sizeof(unsigned long long), hipMemcpyDeviceToHost);
hipMemcpyFromSymbol(&loadStoreValue, HIP_SYMBOL(load_store_value), LIST_SIZE * sizeof(unsigned long long), j*sizeof(unsigned long long), hipMemcpyDeviceToHost);
for(long long i=0; i < LIST_SIZE && loadStoreIndex[i] != 0; i++)
{
fprintf(profileFile, "%lld %lld\n", loadStoreIndex[i], loadStoreValue[i]);
}
}
for (int j=0; j < LIST_SIZE_GLOBAL; j+=LIST_SIZE)
{
hipMemcpyFromSymbol(&loadStoreIndex_double, HIP_SYMBOL(load_store_double_index), LIST_SIZE * sizeof(unsigned long long), j*sizeof(unsigned long long), hipMemcpyDeviceToHost);
hipMemcpyFromSymbol(&loadStoreValue_double, HIP_SYMBOL(load_store_double), LIST_SIZE * sizeof(double), j*sizeof(double), hipMemcpyDeviceToHost);
for(long long i=0; i < LIST_SIZE && loadStoreIndex_double[i] != 0; i++)
{
fprintf(profileFile, "%lld %.40f\n", loadStoreIndex_double[i], loadStoreValue_double[i]);
}
}
fclose(profileFile);
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.protected load_store_double_index
.type load_store_double_index,@object
.section .bss,"aw",@nobits
.globl load_store_double_index
.p2align 4, 0x0
load_store_double_index:
.zero 80000
.size load_store_double_index, 80000
.protected load_store_value
.type load_store_value,@object
.globl load_store_value
.p2align 4, 0x0
load_store_value:
.zero 80000
.size load_store_value, 80000
.protected record_flag
.type record_flag,@object
.globl record_flag
.p2align 3, 0x0
record_flag:
.quad 0
.size record_flag, 8
.protected load_store_double
.type load_store_double,@object
.globl load_store_double
.p2align 4, 0x0
load_store_double:
.zero 80000
.size load_store_double, 80000
.protected load_store_index
.type load_store_index,@object
.globl load_store_index
.p2align 4, 0x0
load_store_index:
.zero 80000
.size load_store_index, 80000
.protected call_count
.type call_count,@object
.globl call_count
.p2align 3, 0x0
call_count:
.quad 0
.size call_count, 8
.type __hip_cuid_,@object
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym load_store_double_index
.addrsig_sym load_store_value
.addrsig_sym record_flag
.addrsig_sym load_store_double
.addrsig_sym load_store_index
.addrsig_sym call_count
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <stdlib.h>
#include <stdio.h>
#include <string.h>
#include <math.h>
#include <hip/hip_runtime.h>
#define LIST_SIZE_GLOBAL 5000000
#define LIST_SIZE 10000
extern "C" __device__ unsigned long long load_store_index[LIST_SIZE];
extern "C" __device__ unsigned long long load_store_value[LIST_SIZE];
extern "C" __device__ double load_store_double[LIST_SIZE];
extern "C" __device__ unsigned long long load_store_double_index[LIST_SIZE];
extern "C" __device__ unsigned long long record_flag;
extern "C" __device__ unsigned long long call_count;
int memPro_kernel = 0;
void bambooLogRecordOff(){
long long local_record = 0;
hipMemcpyToSymbol(HIP_SYMBOL(record_flag), &local_record, sizeof(long long), 0, hipMemcpyHostToDevice);
}
void bambooLogKernelBegin(long long i) {
hipMemcpyToSymbol(HIP_SYMBOL(call_count), &i, sizeof(long long), 0, hipMemcpyHostToDevice);
i = 1;
hipMemcpyToSymbol(HIP_SYMBOL(record_flag), &i, sizeof(long long), 0, hipMemcpyHostToDevice);
}
void bambooLogKernelEnd()
{
unsigned long long loadStoreIndex[LIST_SIZE] = {0};
unsigned long long loadStoreValue[LIST_SIZE] = {0};
unsigned long long loadStoreIndex_double[LIST_SIZE] = {0};
double loadStoreValue_double[LIST_SIZE] = {0};
FILE *profileFile = fopen("profile_mem_val_result.txt", "a");
for (int j=0; j < LIST_SIZE_GLOBAL; j+=LIST_SIZE)
{
hipMemcpyFromSymbol(&loadStoreIndex, HIP_SYMBOL(load_store_index), LIST_SIZE * sizeof(unsigned long long), j*sizeof(unsigned long long), hipMemcpyDeviceToHost);
hipMemcpyFromSymbol(&loadStoreValue, HIP_SYMBOL(load_store_value), LIST_SIZE * sizeof(unsigned long long), j*sizeof(unsigned long long), hipMemcpyDeviceToHost);
for(long long i=0; i < LIST_SIZE && loadStoreIndex[i] != 0; i++)
{
fprintf(profileFile, "%lld %lld\n", loadStoreIndex[i], loadStoreValue[i]);
}
}
for (int j=0; j < LIST_SIZE_GLOBAL; j+=LIST_SIZE)
{
hipMemcpyFromSymbol(&loadStoreIndex_double, HIP_SYMBOL(load_store_double_index), LIST_SIZE * sizeof(unsigned long long), j*sizeof(unsigned long long), hipMemcpyDeviceToHost);
hipMemcpyFromSymbol(&loadStoreValue_double, HIP_SYMBOL(load_store_double), LIST_SIZE * sizeof(double), j*sizeof(double), hipMemcpyDeviceToHost);
for(long long i=0; i < LIST_SIZE && loadStoreIndex_double[i] != 0; i++)
{
fprintf(profileFile, "%lld %.40f\n", loadStoreIndex_double[i], loadStoreValue_double[i]);
}
}
fclose(profileFile);
} | .text
.file "record_data.hip"
.globl _Z18bambooLogRecordOffv # -- Begin function _Z18bambooLogRecordOffv
.p2align 4, 0x90
.type _Z18bambooLogRecordOffv,@function
_Z18bambooLogRecordOffv: # @_Z18bambooLogRecordOffv
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
movq $0, (%rsp)
movq %rsp, %rsi
movl $record_flag, %edi
movl $8, %edx
xorl %ecx, %ecx
movl $1, %r8d
callq hipMemcpyToSymbol
popq %rax
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z18bambooLogRecordOffv, .Lfunc_end0-_Z18bambooLogRecordOffv
.cfi_endproc
# -- End function
.globl _Z20bambooLogKernelBeginx # -- Begin function _Z20bambooLogKernelBeginx
.p2align 4, 0x90
.type _Z20bambooLogKernelBeginx,@function
_Z20bambooLogKernelBeginx: # @_Z20bambooLogKernelBeginx
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $16, %rsp
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -16
movq %rdi, 8(%rsp)
leaq 8(%rsp), %rbx
movl $call_count, %edi
movl $8, %edx
movq %rbx, %rsi
xorl %ecx, %ecx
movl $1, %r8d
callq hipMemcpyToSymbol
movq $1, 8(%rsp)
movl $record_flag, %edi
movl $8, %edx
movq %rbx, %rsi
xorl %ecx, %ecx
movl $1, %r8d
callq hipMemcpyToSymbol
addq $16, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z20bambooLogKernelBeginx, .Lfunc_end1-_Z20bambooLogKernelBeginx
.cfi_endproc
# -- End function
.globl _Z18bambooLogKernelEndv # -- Begin function _Z18bambooLogKernelEndv
.p2align 4, 0x90
.type _Z18bambooLogKernelEndv,@function
_Z18bambooLogKernelEndv: # @_Z18bambooLogKernelEndv
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $320000, %rsp # imm = 0x4E200
.cfi_def_cfa_offset 320048
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 240000(%rsp), %r14
movl $80000, %edx # imm = 0x13880
movq %r14, %rdi
xorl %esi, %esi
callq memset@PLT
leaq 160000(%rsp), %r15
movl $80000, %edx # imm = 0x13880
movq %r15, %rdi
xorl %esi, %esi
callq memset@PLT
leaq 80000(%rsp), %rdi
movl $80000, %edx # imm = 0x13880
xorl %esi, %esi
callq memset@PLT
movq %rsp, %rdi
movl $80000, %edx # imm = 0x13880
xorl %esi, %esi
callq memset@PLT
movl $.L.str, %edi
movl $.L.str.1, %esi
callq fopen
movq %rax, %rbx
xorl %r13d, %r13d
jmp .LBB2_1
.p2align 4, 0x90
.LBB2_3: # %.critedge
# in Loop: Header=BB2_1 Depth=1
leaq 10000(%r13), %rax
cmpq $4990000, %r13 # imm = 0x4C2430
movq %rax, %r13
jae .LBB2_4
.LBB2_1: # =>This Loop Header: Depth=1
# Child Loop BB2_2 Depth 2
leaq (,%r13,8), %r12
movl $load_store_index, %esi
movl $80000, %edx # imm = 0x13880
movq %r14, %rdi
movq %r12, %rcx
movl $2, %r8d
callq hipMemcpyFromSymbol
movl $load_store_value, %esi
movl $80000, %edx # imm = 0x13880
movq %r15, %rdi
movq %r12, %rcx
movl $2, %r8d
callq hipMemcpyFromSymbol
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB2_2: # Parent Loop BB2_1 Depth=1
# => This Inner Loop Header: Depth=2
movq 240000(%rsp,%r12,8), %rdx
testq %rdx, %rdx
je .LBB2_3
# %bb.9: # in Loop: Header=BB2_2 Depth=2
movq 160000(%rsp,%r12,8), %rcx
movl $.L.str.2, %esi
movq %rbx, %rdi
xorl %eax, %eax
callq fprintf
incq %r12
cmpq $10000, %r12 # imm = 0x2710
jne .LBB2_2
jmp .LBB2_3
.LBB2_4: # %.preheader.preheader
xorl %r13d, %r13d
leaq 80000(%rsp), %r14
movq %rsp, %r15
jmp .LBB2_5
.p2align 4, 0x90
.LBB2_7: # %.critedge2
# in Loop: Header=BB2_5 Depth=1
leaq 10000(%r13), %rax
cmpq $4990000, %r13 # imm = 0x4C2430
movq %rax, %r13
jae .LBB2_8
.LBB2_5: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB2_6 Depth 2
leaq (,%r13,8), %r12
movl $load_store_double_index, %esi
movl $80000, %edx # imm = 0x13880
movq %r14, %rdi
movq %r12, %rcx
movl $2, %r8d
callq hipMemcpyFromSymbol
movl $load_store_double, %esi
movl $80000, %edx # imm = 0x13880
movq %r15, %rdi
movq %r12, %rcx
movl $2, %r8d
callq hipMemcpyFromSymbol
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB2_6: # Parent Loop BB2_5 Depth=1
# => This Inner Loop Header: Depth=2
movq 80000(%rsp,%r12,8), %rdx
testq %rdx, %rdx
je .LBB2_7
# %bb.10: # in Loop: Header=BB2_6 Depth=2
movsd (%rsp,%r12,8), %xmm0 # xmm0 = mem[0],zero
movl $.L.str.3, %esi
movq %rbx, %rdi
movb $1, %al
callq fprintf
incq %r12
cmpq $10000, %r12 # imm = 0x2710
jne .LBB2_6
jmp .LBB2_7
.LBB2_8:
movq %rbx, %rdi
callq fclose
addq $320000, %rsp # imm = 0x4E200
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z18bambooLogKernelEndv, .Lfunc_end2-_Z18bambooLogKernelEndv
.cfi_endproc
# -- End function
.type memPro_kernel,@object # @memPro_kernel
.bss
.globl memPro_kernel
.p2align 2, 0x0
memPro_kernel:
.long 0 # 0x0
.size memPro_kernel, 4
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "profile_mem_val_result.txt"
.size .L.str, 27
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "a"
.size .L.str.1, 2
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "%lld %lld\n"
.size .L.str.2, 11
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "%lld %.40f\n"
.size .L.str.3, 12
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym record_flag
.addrsig_sym call_count
.addrsig_sym load_store_index
.addrsig_sym load_store_value
.addrsig_sym load_store_double_index
.addrsig_sym load_store_double
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.protected load_store_double_index
.type load_store_double_index,@object
.section .bss,"aw",@nobits
.globl load_store_double_index
.p2align 4, 0x0
load_store_double_index:
.zero 80000
.size load_store_double_index, 80000
.protected load_store_value
.type load_store_value,@object
.globl load_store_value
.p2align 4, 0x0
load_store_value:
.zero 80000
.size load_store_value, 80000
.protected record_flag
.type record_flag,@object
.globl record_flag
.p2align 3, 0x0
record_flag:
.quad 0
.size record_flag, 8
.protected load_store_double
.type load_store_double,@object
.globl load_store_double
.p2align 4, 0x0
load_store_double:
.zero 80000
.size load_store_double, 80000
.protected load_store_index
.type load_store_index,@object
.globl load_store_index
.p2align 4, 0x0
load_store_index:
.zero 80000
.size load_store_index, 80000
.protected call_count
.type call_count,@object
.globl call_count
.p2align 3, 0x0
call_count:
.quad 0
.size call_count, 8
.type __hip_cuid_,@object
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym load_store_double_index
.addrsig_sym load_store_value
.addrsig_sym record_flag
.addrsig_sym load_store_double
.addrsig_sym load_store_index
.addrsig_sym call_count
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001432cf_00000000-6_record_data.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z18bambooLogRecordOffv
.type _Z18bambooLogRecordOffv, @function
_Z18bambooLogRecordOffv:
.LFB2057:
.cfi_startproc
endbr64
subq $24, %rsp
.cfi_def_cfa_offset 32
movq %fs:40, %rax
movq %rax, 8(%rsp)
xorl %eax, %eax
movq $0, (%rsp)
movq %rsp, %rsi
movl $1, %r8d
movl $0, %ecx
movl $8, %edx
leaq record_flag(%rip), %rdi
call cudaMemcpyToSymbol@PLT
movq 8(%rsp), %rax
subq %fs:40, %rax
jne .L6
addq $24, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L6:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size _Z18bambooLogRecordOffv, .-_Z18bambooLogRecordOffv
.globl _Z20bambooLogKernelBeginx
.type _Z20bambooLogKernelBeginx, @function
_Z20bambooLogKernelBeginx:
.LFB2058:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $16, %rsp
.cfi_def_cfa_offset 32
movq %rdi, 8(%rsp)
leaq 8(%rsp), %rbx
movl $1, %r8d
movl $0, %ecx
movl $8, %edx
movq %rbx, %rsi
leaq call_count(%rip), %rdi
call cudaMemcpyToSymbol@PLT
movq $1, 8(%rsp)
movl $1, %r8d
movl $0, %ecx
movl $8, %edx
movq %rbx, %rsi
leaq record_flag(%rip), %rdi
call cudaMemcpyToSymbol@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _Z20bambooLogKernelBeginx, .-_Z20bambooLogKernelBeginx
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "a"
.LC1:
.string "profile_mem_val_result.txt"
.LC2:
.string "%lld %lld\n"
.LC3:
.string "%lld %.40f\n"
.text
.globl _Z18bambooLogKernelEndv
.type _Z18bambooLogKernelEndv, @function
_Z18bambooLogKernelEndv:
.LFB2059:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
leaq -319488(%rsp), %r11
.cfi_def_cfa 11, 319544
.LPSRL0:
subq $4096, %rsp
orq $0, (%rsp)
cmpq %r11, %rsp
jne .LPSRL0
.cfi_def_cfa_register 7
subq $536, %rsp
.cfi_def_cfa_offset 320080
movq %fs:40, %rax
movq %rax, 320008(%rsp)
xorl %eax, %eax
movq %rsp, %rdi
movl $80000, %edx
movl $0, %esi
call memset@PLT
leaq 80000(%rsp), %rdi
movl $80000, %edx
movl $0, %esi
call memset@PLT
leaq 160000(%rsp), %rdi
movl $80000, %edx
movl $0, %esi
call memset@PLT
leaq 240000(%rsp), %rdi
movl $80000, %edx
movl $0, %esi
call memset@PLT
leaq .LC0(%rip), %rsi
leaq .LC1(%rip), %rdi
call fopen@PLT
movq %rax, %rbp
movl $0, %r14d
movq %rsp, %r12
leaq load_store_index(%rip), %r15
leaq .LC2(%rip), %r13
jmp .L13
.L11:
addq $80000, %r14
cmpq $40000000, %r14
je .L22
.L13:
movl $2, %r8d
movq %r14, %rcx
movl $80000, %edx
movq %r15, %rsi
movq %r12, %rdi
call cudaMemcpyFromSymbol@PLT
leaq 80000(%rsp), %rdi
movl $2, %r8d
movq %r14, %rcx
movl $80000, %edx
leaq load_store_value(%rip), %rsi
call cudaMemcpyFromSymbol@PLT
movl $0, %ebx
.L10:
movq (%r12,%rbx,8), %rcx
testq %rcx, %rcx
je .L11
movq 80000(%rsp,%rbx,8), %r8
movq %r13, %rdx
movl $2, %esi
movq %rbp, %rdi
movl $0, %eax
call __fprintf_chk@PLT
addq $1, %rbx
cmpq $10000, %rbx
jne .L10
jmp .L11
.L22:
movl $0, %r14d
leaq 160000(%rsp), %r12
leaq load_store_double_index(%rip), %r15
leaq .LC3(%rip), %r13
jmp .L17
.L15:
addq $80000, %r14
cmpq $40000000, %r14
je .L23
.L17:
movl $2, %r8d
movq %r14, %rcx
movl $80000, %edx
movq %r15, %rsi
movq %r12, %rdi
call cudaMemcpyFromSymbol@PLT
leaq 240000(%rsp), %rdi
movl $2, %r8d
movq %r14, %rcx
movl $80000, %edx
leaq load_store_double(%rip), %rsi
call cudaMemcpyFromSymbol@PLT
movl $0, %ebx
.L14:
movq (%r12,%rbx,8), %rcx
testq %rcx, %rcx
je .L15
movsd 240000(%rsp,%rbx,8), %xmm0
movq %r13, %rdx
movl $2, %esi
movq %rbp, %rdi
movl $1, %eax
call __fprintf_chk@PLT
addq $1, %rbx
cmpq $10000, %rbx
jne .L14
jmp .L15
.L23:
movq %rbp, %rdi
call fclose@PLT
movq 320008(%rsp), %rax
subq %fs:40, %rax
jne .L24
addq $320024, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L24:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size _Z18bambooLogKernelEndv, .-_Z18bambooLogKernelEndv
.section .rodata.str1.1
.LC4:
.string "load_store_index"
.LC5:
.string "load_store_value"
.LC6:
.string "load_store_double"
.LC7:
.string "load_store_double_index"
.LC8:
.string "record_flag"
.LC9:
.string "call_count"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $80000, %r9d
movl $1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq load_store_index(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $80000, %r9d
movl $1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq load_store_value(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $80000, %r9d
movl $1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq load_store_double(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $80000, %r9d
movl $1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq load_store_double_index(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $8, %r9d
movl $1, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq record_flag(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $8, %r9d
movl $1, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq call_count(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl memPro_kernel
.bss
.align 4
.type memPro_kernel, @object
.size memPro_kernel, 4
memPro_kernel:
.zero 4
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "record_data.hip"
.globl _Z18bambooLogRecordOffv # -- Begin function _Z18bambooLogRecordOffv
.p2align 4, 0x90
.type _Z18bambooLogRecordOffv,@function
_Z18bambooLogRecordOffv: # @_Z18bambooLogRecordOffv
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
movq $0, (%rsp)
movq %rsp, %rsi
movl $record_flag, %edi
movl $8, %edx
xorl %ecx, %ecx
movl $1, %r8d
callq hipMemcpyToSymbol
popq %rax
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z18bambooLogRecordOffv, .Lfunc_end0-_Z18bambooLogRecordOffv
.cfi_endproc
# -- End function
.globl _Z20bambooLogKernelBeginx # -- Begin function _Z20bambooLogKernelBeginx
.p2align 4, 0x90
.type _Z20bambooLogKernelBeginx,@function
_Z20bambooLogKernelBeginx: # @_Z20bambooLogKernelBeginx
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $16, %rsp
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -16
movq %rdi, 8(%rsp)
leaq 8(%rsp), %rbx
movl $call_count, %edi
movl $8, %edx
movq %rbx, %rsi
xorl %ecx, %ecx
movl $1, %r8d
callq hipMemcpyToSymbol
movq $1, 8(%rsp)
movl $record_flag, %edi
movl $8, %edx
movq %rbx, %rsi
xorl %ecx, %ecx
movl $1, %r8d
callq hipMemcpyToSymbol
addq $16, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z20bambooLogKernelBeginx, .Lfunc_end1-_Z20bambooLogKernelBeginx
.cfi_endproc
# -- End function
.globl _Z18bambooLogKernelEndv # -- Begin function _Z18bambooLogKernelEndv
.p2align 4, 0x90
.type _Z18bambooLogKernelEndv,@function
_Z18bambooLogKernelEndv: # @_Z18bambooLogKernelEndv
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $320000, %rsp # imm = 0x4E200
.cfi_def_cfa_offset 320048
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 240000(%rsp), %r14
movl $80000, %edx # imm = 0x13880
movq %r14, %rdi
xorl %esi, %esi
callq memset@PLT
leaq 160000(%rsp), %r15
movl $80000, %edx # imm = 0x13880
movq %r15, %rdi
xorl %esi, %esi
callq memset@PLT
leaq 80000(%rsp), %rdi
movl $80000, %edx # imm = 0x13880
xorl %esi, %esi
callq memset@PLT
movq %rsp, %rdi
movl $80000, %edx # imm = 0x13880
xorl %esi, %esi
callq memset@PLT
movl $.L.str, %edi
movl $.L.str.1, %esi
callq fopen
movq %rax, %rbx
xorl %r13d, %r13d
jmp .LBB2_1
.p2align 4, 0x90
.LBB2_3: # %.critedge
# in Loop: Header=BB2_1 Depth=1
leaq 10000(%r13), %rax
cmpq $4990000, %r13 # imm = 0x4C2430
movq %rax, %r13
jae .LBB2_4
.LBB2_1: # =>This Loop Header: Depth=1
# Child Loop BB2_2 Depth 2
leaq (,%r13,8), %r12
movl $load_store_index, %esi
movl $80000, %edx # imm = 0x13880
movq %r14, %rdi
movq %r12, %rcx
movl $2, %r8d
callq hipMemcpyFromSymbol
movl $load_store_value, %esi
movl $80000, %edx # imm = 0x13880
movq %r15, %rdi
movq %r12, %rcx
movl $2, %r8d
callq hipMemcpyFromSymbol
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB2_2: # Parent Loop BB2_1 Depth=1
# => This Inner Loop Header: Depth=2
movq 240000(%rsp,%r12,8), %rdx
testq %rdx, %rdx
je .LBB2_3
# %bb.9: # in Loop: Header=BB2_2 Depth=2
movq 160000(%rsp,%r12,8), %rcx
movl $.L.str.2, %esi
movq %rbx, %rdi
xorl %eax, %eax
callq fprintf
incq %r12
cmpq $10000, %r12 # imm = 0x2710
jne .LBB2_2
jmp .LBB2_3
.LBB2_4: # %.preheader.preheader
xorl %r13d, %r13d
leaq 80000(%rsp), %r14
movq %rsp, %r15
jmp .LBB2_5
.p2align 4, 0x90
.LBB2_7: # %.critedge2
# in Loop: Header=BB2_5 Depth=1
leaq 10000(%r13), %rax
cmpq $4990000, %r13 # imm = 0x4C2430
movq %rax, %r13
jae .LBB2_8
.LBB2_5: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB2_6 Depth 2
leaq (,%r13,8), %r12
movl $load_store_double_index, %esi
movl $80000, %edx # imm = 0x13880
movq %r14, %rdi
movq %r12, %rcx
movl $2, %r8d
callq hipMemcpyFromSymbol
movl $load_store_double, %esi
movl $80000, %edx # imm = 0x13880
movq %r15, %rdi
movq %r12, %rcx
movl $2, %r8d
callq hipMemcpyFromSymbol
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB2_6: # Parent Loop BB2_5 Depth=1
# => This Inner Loop Header: Depth=2
movq 80000(%rsp,%r12,8), %rdx
testq %rdx, %rdx
je .LBB2_7
# %bb.10: # in Loop: Header=BB2_6 Depth=2
movsd (%rsp,%r12,8), %xmm0 # xmm0 = mem[0],zero
movl $.L.str.3, %esi
movq %rbx, %rdi
movb $1, %al
callq fprintf
incq %r12
cmpq $10000, %r12 # imm = 0x2710
jne .LBB2_6
jmp .LBB2_7
.LBB2_8:
movq %rbx, %rdi
callq fclose
addq $320000, %rsp # imm = 0x4E200
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z18bambooLogKernelEndv, .Lfunc_end2-_Z18bambooLogKernelEndv
.cfi_endproc
# -- End function
.type memPro_kernel,@object # @memPro_kernel
.bss
.globl memPro_kernel
.p2align 2, 0x0
memPro_kernel:
.long 0 # 0x0
.size memPro_kernel, 4
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "profile_mem_val_result.txt"
.size .L.str, 27
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "a"
.size .L.str.1, 2
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "%lld %lld\n"
.size .L.str.2, 11
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "%lld %.40f\n"
.size .L.str.3, 12
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym record_flag
.addrsig_sym call_count
.addrsig_sym load_store_index
.addrsig_sym load_store_value
.addrsig_sym load_store_double_index
.addrsig_sym load_store_double
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <curand_kernel.h>
#include <curand.h>
#include <chrono>
#include <iostream>
#include <string.h>
#include <math.h>
#include <time.h>
#include <stdio.h>
__global__ void setup_gpu_rng(long long n, curandState *rng_states, long long seed) {
long long i = blockIdx.x * blockDim.x + threadIdx.x;
if (i < n) curand_init(seed, i, 0, &rng_states[i]);
}
__global__ void gpu_estimate_pi(long long n, curandState *rng_states, long long samples, float *pi_estimates) {
long long i = blockIdx.x * blockDim.x + threadIdx.x, count = 0;
float x, y, z;
if (i < n) {
for (long long j = 0; j < samples; j++) {
x = curand_uniform(&rng_states[i]);
y = curand_uniform(&rng_states[i]);
z = sqrt((x*x) + (y*y));
if (z <= 1.0) count++;
}
pi_estimates[i] = 4.0 * (float)count / (float)samples;
//printf("i: %lld est: %.2f\n", i, pi_estimates[i]);
}
}
float cpu_estimate_pi(long long n) {
// Calculate PI following a Monte Carlo method
float x, y, z;
int count;
for (int iter = 0; iter < n; iter++) {
// Generate random (X,Y) points
x = (float)random() / (float)RAND_MAX;
y = (float)random() / (float)RAND_MAX;
z = sqrt((x*x) + (y*y));
// Check if point is in unit circle
if (z <= 1.0)
{
count++;
}
}
return ((float)count / (float)n) * 4.0;
}
int main(int argc, char* argv[]) {
long long samples = std::atoi(argv[1]), samples_per_thread = std::atoi(argv[2]), thread_per_block = std::atoi(argv[3]);
auto start = std::chrono::steady_clock::now();
float pi = cpu_estimate_pi(samples);
auto end = std::chrono::steady_clock::now();
std::cout << "CPU-PI: " << pi << std::endl;
std::cout << "CPU " << std::chrono::duration_cast<std::chrono::microseconds>(end - start).count() << std::endl;
long long blocks = (samples + thread_per_block - 1) / (thread_per_block * samples_per_thread) + 1;
long long total_threads = blocks * thread_per_block;
curandState *rng;
cudaMalloc(&rng, sizeof(curandState) * total_threads);
setup_gpu_rng<<<blocks, thread_per_block>>>(total_threads, rng, time(NULL));
float *device_pi_estimates, *host_pi_estimates;
cudaMalloc(&device_pi_estimates, sizeof(float) * total_threads);
host_pi_estimates = (float*)malloc(sizeof(float) * total_threads);
start = std::chrono::steady_clock::now();
gpu_estimate_pi<<<blocks, thread_per_block>>>(total_threads, rng, samples_per_thread, device_pi_estimates);
cudaMemcpy(host_pi_estimates, device_pi_estimates, sizeof(float) * total_threads, cudaMemcpyDeviceToHost);
float gpu_pi = 0;
for (long long i = 0; i < total_threads; i++) {
gpu_pi += host_pi_estimates[i];
}
gpu_pi /= (float)total_threads;
end = std::chrono::steady_clock::now();
std::cout << "GPU-PI: " << gpu_pi << std::endl;
std::cout << "GPU " << std::chrono::duration_cast<std::chrono::microseconds>(end - start).count() << std::endl;
return 0;
} | .file "tmpxft_000fd52e_00000000-6_exercise_4.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3988:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3988:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z15cpu_estimate_pix
.type _Z15cpu_estimate_pix, @function
_Z15cpu_estimate_pix:
.LFB3982:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $16, %rsp
.cfi_def_cfa_offset 48
movq %rdi, %r12
testq %rdi, %rdi
jle .L4
movl $0, %ebx
.L7:
call random@PLT
pxor %xmm0, %xmm0
cvtsi2ssq %rax, %xmm0
mulss .LC0(%rip), %xmm0
movss %xmm0, 12(%rsp)
call random@PLT
pxor %xmm1, %xmm1
cvtsi2ssq %rax, %xmm1
mulss .LC0(%rip), %xmm1
movss 12(%rsp), %xmm0
mulss %xmm0, %xmm0
mulss %xmm1, %xmm1
addss %xmm1, %xmm0
sqrtss %xmm0, %xmm0
movss .LC1(%rip), %xmm2
comiss %xmm0, %xmm2
sbbl $-1, %ebp
addq $1, %rbx
cmpq %r12, %rbx
jne .L7
.L4:
pxor %xmm0, %xmm0
cvtsi2ssl %ebp, %xmm0
pxor %xmm1, %xmm1
cvtsi2ssq %r12, %xmm1
divss %xmm1, %xmm0
mulss .LC2(%rip), %xmm0
addq $16, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3982:
.size _Z15cpu_estimate_pix, .-_Z15cpu_estimate_pix
.globl _Z53__device_stub__Z13setup_gpu_rngxP17curandStateXORWOWxxP17curandStateXORWOWx
.type _Z53__device_stub__Z13setup_gpu_rngxP17curandStateXORWOWxxP17curandStateXORWOWx, @function
_Z53__device_stub__Z13setup_gpu_rngxP17curandStateXORWOWxxP17curandStateXORWOWx:
.LFB4010:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z13setup_gpu_rngxP17curandStateXORWOWx(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4010:
.size _Z53__device_stub__Z13setup_gpu_rngxP17curandStateXORWOWxxP17curandStateXORWOWx, .-_Z53__device_stub__Z13setup_gpu_rngxP17curandStateXORWOWxxP17curandStateXORWOWx
.globl _Z13setup_gpu_rngxP17curandStateXORWOWx
.type _Z13setup_gpu_rngxP17curandStateXORWOWx, @function
_Z13setup_gpu_rngxP17curandStateXORWOWx:
.LFB4011:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z53__device_stub__Z13setup_gpu_rngxP17curandStateXORWOWxxP17curandStateXORWOWx
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4011:
.size _Z13setup_gpu_rngxP17curandStateXORWOWx, .-_Z13setup_gpu_rngxP17curandStateXORWOWx
.globl _Z57__device_stub__Z15gpu_estimate_pixP17curandStateXORWOWxPfxP17curandStateXORWOWxPf
.type _Z57__device_stub__Z15gpu_estimate_pixP17curandStateXORWOWxPfxP17curandStateXORWOWxPf, @function
_Z57__device_stub__Z15gpu_estimate_pixP17curandStateXORWOWxPfxP17curandStateXORWOWxPf:
.LFB4012:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L23
.L19:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L24
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z15gpu_estimate_pixP17curandStateXORWOWxPf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L19
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4012:
.size _Z57__device_stub__Z15gpu_estimate_pixP17curandStateXORWOWxPfxP17curandStateXORWOWxPf, .-_Z57__device_stub__Z15gpu_estimate_pixP17curandStateXORWOWxPfxP17curandStateXORWOWxPf
.globl _Z15gpu_estimate_pixP17curandStateXORWOWxPf
.type _Z15gpu_estimate_pixP17curandStateXORWOWxPf, @function
_Z15gpu_estimate_pixP17curandStateXORWOWxPf:
.LFB4013:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z57__device_stub__Z15gpu_estimate_pixP17curandStateXORWOWxPfxP17curandStateXORWOWxPf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4013:
.size _Z15gpu_estimate_pixP17curandStateXORWOWxPf, .-_Z15gpu_estimate_pixP17curandStateXORWOWxPf
.section .rodata.str1.1,"aMS",@progbits,1
.LC4:
.string "CPU-PI: "
.LC5:
.string "CPU "
.LC6:
.string "GPU-PI: "
.LC7:
.string "GPU "
.text
.globl main
.type main, @function
main:
.LFB3983:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $72, %rsp
.cfi_def_cfa_offset 128
movq %rsi, %rbx
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movslq %eax, %r13
movq 16(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movslq %eax, %r14
movq 24(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %r12
movslq %eax, %rbp
call _ZNSt6chrono3_V212steady_clock3nowEv@PLT
movq %rax, 8(%rsp)
movq %r13, %rdi
call _Z15cpu_estimate_pix
movss %xmm0, (%rsp)
call _ZNSt6chrono3_V212steady_clock3nowEv@PLT
movq %rax, %rbx
leaq .LC4(%rip), %rsi
leaq _ZSt4cout(%rip), %r15
movq %r15, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
pxor %xmm0, %xmm0
cvtss2sd (%rsp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq .LC5(%rip), %rsi
movq %r15, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq 8(%rsp), %rax
subq %rax, %rbx
movabsq $2361183241434822607, %rdx
movq %rbx, %rax
imulq %rdx
sarq $7, %rdx
sarq $63, %rbx
subq %rbx, %rdx
movq %rdx, %rsi
call _ZNSo9_M_insertIlEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq -1(%r13,%rbp), %rax
movq %r14, %rcx
imulq %rbp, %rcx
cqto
idivq %rcx
leaq 1(%rax), %r13
imulq %r13, %rbp
leaq 0(%rbp,%rbp,2), %rsi
salq $4, %rsi
leaq 16(%rsp), %rdi
call cudaMalloc@PLT
movl %r12d, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl %r13d, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L36
.L28:
leaq 0(,%rbp,4), %r15
leaq 24(%rsp), %rdi
movq %r15, %rsi
call cudaMalloc@PLT
movq %r15, %rdi
call malloc@PLT
movq %rax, %rbx
call _ZNSt6chrono3_V212steady_clock3nowEv@PLT
movq %rax, (%rsp)
movl %r12d, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl %r13d, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L37
.L29:
movl $2, %ecx
movq %r15, %rdx
movq 24(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
testq %rbp, %rbp
jle .L33
movq %rbx, %rax
addq %r15, %rbx
pxor %xmm0, %xmm0
.L31:
addss (%rax), %xmm0
addq $4, %rax
cmpq %rbx, %rax
jne .L31
.L30:
pxor %xmm1, %xmm1
cvtsi2ssq %rbp, %xmm1
divss %xmm1, %xmm0
movss %xmm0, 8(%rsp)
call _ZNSt6chrono3_V212steady_clock3nowEv@PLT
movq %rax, %rbx
leaq .LC6(%rip), %rsi
leaq _ZSt4cout(%rip), %rbp
movq %rbp, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
pxor %xmm0, %xmm0
cvtss2sd 8(%rsp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq .LC7(%rip), %rsi
movq %rbp, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq (%rsp), %rax
subq %rax, %rbx
movabsq $2361183241434822607, %rdx
movq %rbx, %rax
imulq %rdx
sarq $7, %rdx
sarq $63, %rbx
subq %rbx, %rdx
movq %rdx, %rsi
call _ZNSo9_M_insertIlEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L38
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L36:
.cfi_restore_state
movl $0, %edi
call time@PLT
movq %rax, %rdx
movq 16(%rsp), %rsi
movq %rbp, %rdi
call _Z53__device_stub__Z13setup_gpu_rngxP17curandStateXORWOWxxP17curandStateXORWOWx
jmp .L28
.L37:
movq 24(%rsp), %rcx
movq %r14, %rdx
movq 16(%rsp), %rsi
movq %rbp, %rdi
call _Z57__device_stub__Z15gpu_estimate_pixP17curandStateXORWOWxPfxP17curandStateXORWOWxPf
jmp .L29
.L33:
pxor %xmm0, %xmm0
jmp .L30
.L38:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3983:
.size main, .-main
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC8:
.string "_Z15gpu_estimate_pixP17curandStateXORWOWxPf"
.align 8
.LC9:
.string "_Z13setup_gpu_rngxP17curandStateXORWOWx"
.section .rodata.str1.1
.LC10:
.string "precalc_xorwow_matrix"
.LC11:
.string "precalc_xorwow_offset_matrix"
.LC12:
.string "mrg32k3aM1"
.LC13:
.string "mrg32k3aM2"
.LC14:
.string "mrg32k3aM1SubSeq"
.LC15:
.string "mrg32k3aM2SubSeq"
.LC16:
.string "mrg32k3aM1Seq"
.LC17:
.string "mrg32k3aM2Seq"
.LC18:
.string "__cr_lgamma_table"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB4015:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _Z15gpu_estimate_pixP17curandStateXORWOWxPf(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _Z13setup_gpu_rngxP17curandStateXORWOWx(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $102400, %r9d
movl $0, %r8d
leaq .LC10(%rip), %rdx
movq %rdx, %rcx
leaq _ZL21precalc_xorwow_matrix(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $102400, %r9d
movl $0, %r8d
leaq .LC11(%rip), %rdx
movq %rdx, %rcx
leaq _ZL28precalc_xorwow_offset_matrix(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC12(%rip), %rdx
movq %rdx, %rcx
leaq _ZL10mrg32k3aM1(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC13(%rip), %rdx
movq %rdx, %rcx
leaq _ZL10mrg32k3aM2(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2016, %r9d
movl $0, %r8d
leaq .LC14(%rip), %rdx
movq %rdx, %rcx
leaq _ZL16mrg32k3aM1SubSeq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2016, %r9d
movl $0, %r8d
leaq .LC15(%rip), %rdx
movq %rdx, %rcx
leaq _ZL16mrg32k3aM2SubSeq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC16(%rip), %rdx
movq %rdx, %rcx
leaq _ZL13mrg32k3aM1Seq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC17(%rip), %rdx
movq %rdx, %rcx
leaq _ZL13mrg32k3aM2Seq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $72, %r9d
movl $0, %r8d
leaq .LC18(%rip), %rdx
movq %rdx, %rcx
leaq _ZL17__cr_lgamma_table(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4015:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL17__cr_lgamma_table
.comm _ZL17__cr_lgamma_table,72,32
.local _ZL13mrg32k3aM2Seq
.comm _ZL13mrg32k3aM2Seq,2304,32
.local _ZL13mrg32k3aM1Seq
.comm _ZL13mrg32k3aM1Seq,2304,32
.local _ZL16mrg32k3aM2SubSeq
.comm _ZL16mrg32k3aM2SubSeq,2016,32
.local _ZL16mrg32k3aM1SubSeq
.comm _ZL16mrg32k3aM1SubSeq,2016,32
.local _ZL10mrg32k3aM2
.comm _ZL10mrg32k3aM2,2304,32
.local _ZL10mrg32k3aM1
.comm _ZL10mrg32k3aM1,2304,32
.local _ZL28precalc_xorwow_offset_matrix
.comm _ZL28precalc_xorwow_offset_matrix,102400,32
.local _ZL21precalc_xorwow_matrix
.comm _ZL21precalc_xorwow_matrix,102400,32
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC0:
.long 805306368
.align 4
.LC1:
.long 1065353216
.align 4
.LC2:
.long 1082130432
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <curand_kernel.h>
#include <curand.h>
#include <chrono>
#include <iostream>
#include <string.h>
#include <math.h>
#include <time.h>
#include <stdio.h>
__global__ void setup_gpu_rng(long long n, curandState *rng_states, long long seed) {
long long i = blockIdx.x * blockDim.x + threadIdx.x;
if (i < n) curand_init(seed, i, 0, &rng_states[i]);
}
__global__ void gpu_estimate_pi(long long n, curandState *rng_states, long long samples, float *pi_estimates) {
long long i = blockIdx.x * blockDim.x + threadIdx.x, count = 0;
float x, y, z;
if (i < n) {
for (long long j = 0; j < samples; j++) {
x = curand_uniform(&rng_states[i]);
y = curand_uniform(&rng_states[i]);
z = sqrt((x*x) + (y*y));
if (z <= 1.0) count++;
}
pi_estimates[i] = 4.0 * (float)count / (float)samples;
//printf("i: %lld est: %.2f\n", i, pi_estimates[i]);
}
}
float cpu_estimate_pi(long long n) {
// Calculate PI following a Monte Carlo method
float x, y, z;
int count;
for (int iter = 0; iter < n; iter++) {
// Generate random (X,Y) points
x = (float)random() / (float)RAND_MAX;
y = (float)random() / (float)RAND_MAX;
z = sqrt((x*x) + (y*y));
// Check if point is in unit circle
if (z <= 1.0)
{
count++;
}
}
return ((float)count / (float)n) * 4.0;
}
int main(int argc, char* argv[]) {
long long samples = std::atoi(argv[1]), samples_per_thread = std::atoi(argv[2]), thread_per_block = std::atoi(argv[3]);
auto start = std::chrono::steady_clock::now();
float pi = cpu_estimate_pi(samples);
auto end = std::chrono::steady_clock::now();
std::cout << "CPU-PI: " << pi << std::endl;
std::cout << "CPU " << std::chrono::duration_cast<std::chrono::microseconds>(end - start).count() << std::endl;
long long blocks = (samples + thread_per_block - 1) / (thread_per_block * samples_per_thread) + 1;
long long total_threads = blocks * thread_per_block;
curandState *rng;
cudaMalloc(&rng, sizeof(curandState) * total_threads);
setup_gpu_rng<<<blocks, thread_per_block>>>(total_threads, rng, time(NULL));
float *device_pi_estimates, *host_pi_estimates;
cudaMalloc(&device_pi_estimates, sizeof(float) * total_threads);
host_pi_estimates = (float*)malloc(sizeof(float) * total_threads);
start = std::chrono::steady_clock::now();
gpu_estimate_pi<<<blocks, thread_per_block>>>(total_threads, rng, samples_per_thread, device_pi_estimates);
cudaMemcpy(host_pi_estimates, device_pi_estimates, sizeof(float) * total_threads, cudaMemcpyDeviceToHost);
float gpu_pi = 0;
for (long long i = 0; i < total_threads; i++) {
gpu_pi += host_pi_estimates[i];
}
gpu_pi /= (float)total_threads;
end = std::chrono::steady_clock::now();
std::cout << "GPU-PI: " << gpu_pi << std::endl;
std::cout << "GPU " << std::chrono::duration_cast<std::chrono::microseconds>(end - start).count() << std::endl;
return 0;
} | #include <hip/hip_runtime.h>
#include <hiprand/hiprand_kernel.h>
#include <hiprand/hiprand.h>
#include <chrono>
#include <iostream>
#include <string.h>
#include <math.h>
#include <time.h>
#include <stdio.h>
__global__ void setup_gpu_rng(long long n, hiprandState *rng_states, long long seed) {
long long i = blockIdx.x * blockDim.x + threadIdx.x;
if (i < n) hiprand_init(seed, i, 0, &rng_states[i]);
}
__global__ void gpu_estimate_pi(long long n, hiprandState *rng_states, long long samples, float *pi_estimates) {
long long i = blockIdx.x * blockDim.x + threadIdx.x, count = 0;
float x, y, z;
if (i < n) {
for (long long j = 0; j < samples; j++) {
x = hiprand_uniform(&rng_states[i]);
y = hiprand_uniform(&rng_states[i]);
z = sqrt((x*x) + (y*y));
if (z <= 1.0) count++;
}
pi_estimates[i] = 4.0 * (float)count / (float)samples;
//printf("i: %lld est: %.2f\n", i, pi_estimates[i]);
}
}
float cpu_estimate_pi(long long n) {
// Calculate PI following a Monte Carlo method
float x, y, z;
int count;
for (int iter = 0; iter < n; iter++) {
// Generate random (X,Y) points
x = (float)random() / (float)RAND_MAX;
y = (float)random() / (float)RAND_MAX;
z = sqrt((x*x) + (y*y));
// Check if point is in unit circle
if (z <= 1.0)
{
count++;
}
}
return ((float)count / (float)n) * 4.0;
}
int main(int argc, char* argv[]) {
long long samples = std::atoi(argv[1]), samples_per_thread = std::atoi(argv[2]), thread_per_block = std::atoi(argv[3]);
auto start = std::chrono::steady_clock::now();
float pi = cpu_estimate_pi(samples);
auto end = std::chrono::steady_clock::now();
std::cout << "CPU-PI: " << pi << std::endl;
std::cout << "CPU " << std::chrono::duration_cast<std::chrono::microseconds>(end - start).count() << std::endl;
long long blocks = (samples + thread_per_block - 1) / (thread_per_block * samples_per_thread) + 1;
long long total_threads = blocks * thread_per_block;
hiprandState *rng;
hipMalloc(&rng, sizeof(hiprandState) * total_threads);
setup_gpu_rng<<<blocks, thread_per_block>>>(total_threads, rng, time(NULL));
float *device_pi_estimates, *host_pi_estimates;
hipMalloc(&device_pi_estimates, sizeof(float) * total_threads);
host_pi_estimates = (float*)malloc(sizeof(float) * total_threads);
start = std::chrono::steady_clock::now();
gpu_estimate_pi<<<blocks, thread_per_block>>>(total_threads, rng, samples_per_thread, device_pi_estimates);
hipMemcpy(host_pi_estimates, device_pi_estimates, sizeof(float) * total_threads, hipMemcpyDeviceToHost);
float gpu_pi = 0;
for (long long i = 0; i < total_threads; i++) {
gpu_pi += host_pi_estimates[i];
}
gpu_pi /= (float)total_threads;
end = std::chrono::steady_clock::now();
std::cout << "GPU-PI: " << gpu_pi << std::endl;
std::cout << "GPU " << std::chrono::duration_cast<std::chrono::microseconds>(end - start).count() << std::endl;
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <hiprand/hiprand_kernel.h>
#include <hiprand/hiprand.h>
#include <chrono>
#include <iostream>
#include <string.h>
#include <math.h>
#include <time.h>
#include <stdio.h>
__global__ void setup_gpu_rng(long long n, hiprandState *rng_states, long long seed) {
long long i = blockIdx.x * blockDim.x + threadIdx.x;
if (i < n) hiprand_init(seed, i, 0, &rng_states[i]);
}
__global__ void gpu_estimate_pi(long long n, hiprandState *rng_states, long long samples, float *pi_estimates) {
long long i = blockIdx.x * blockDim.x + threadIdx.x, count = 0;
float x, y, z;
if (i < n) {
for (long long j = 0; j < samples; j++) {
x = hiprand_uniform(&rng_states[i]);
y = hiprand_uniform(&rng_states[i]);
z = sqrt((x*x) + (y*y));
if (z <= 1.0) count++;
}
pi_estimates[i] = 4.0 * (float)count / (float)samples;
//printf("i: %lld est: %.2f\n", i, pi_estimates[i]);
}
}
float cpu_estimate_pi(long long n) {
// Calculate PI following a Monte Carlo method
float x, y, z;
int count;
for (int iter = 0; iter < n; iter++) {
// Generate random (X,Y) points
x = (float)random() / (float)RAND_MAX;
y = (float)random() / (float)RAND_MAX;
z = sqrt((x*x) + (y*y));
// Check if point is in unit circle
if (z <= 1.0)
{
count++;
}
}
return ((float)count / (float)n) * 4.0;
}
int main(int argc, char* argv[]) {
long long samples = std::atoi(argv[1]), samples_per_thread = std::atoi(argv[2]), thread_per_block = std::atoi(argv[3]);
auto start = std::chrono::steady_clock::now();
float pi = cpu_estimate_pi(samples);
auto end = std::chrono::steady_clock::now();
std::cout << "CPU-PI: " << pi << std::endl;
std::cout << "CPU " << std::chrono::duration_cast<std::chrono::microseconds>(end - start).count() << std::endl;
long long blocks = (samples + thread_per_block - 1) / (thread_per_block * samples_per_thread) + 1;
long long total_threads = blocks * thread_per_block;
hiprandState *rng;
hipMalloc(&rng, sizeof(hiprandState) * total_threads);
setup_gpu_rng<<<blocks, thread_per_block>>>(total_threads, rng, time(NULL));
float *device_pi_estimates, *host_pi_estimates;
hipMalloc(&device_pi_estimates, sizeof(float) * total_threads);
host_pi_estimates = (float*)malloc(sizeof(float) * total_threads);
start = std::chrono::steady_clock::now();
gpu_estimate_pi<<<blocks, thread_per_block>>>(total_threads, rng, samples_per_thread, device_pi_estimates);
hipMemcpy(host_pi_estimates, device_pi_estimates, sizeof(float) * total_threads, hipMemcpyDeviceToHost);
float gpu_pi = 0;
for (long long i = 0; i < total_threads; i++) {
gpu_pi += host_pi_estimates[i];
}
gpu_pi /= (float)total_threads;
end = std::chrono::steady_clock::now();
std::cout << "GPU-PI: " << gpu_pi << std::endl;
std::cout << "GPU " << std::chrono::duration_cast<std::chrono::microseconds>(end - start).count() << std::endl;
return 0;
} | .text
.file "exercise_4.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z28__device_stub__setup_gpu_rngxP12hiprandStatex # -- Begin function _Z28__device_stub__setup_gpu_rngxP12hiprandStatex
.p2align 4, 0x90
.type _Z28__device_stub__setup_gpu_rngxP12hiprandStatex,@function
_Z28__device_stub__setup_gpu_rngxP12hiprandStatex: # @_Z28__device_stub__setup_gpu_rngxP12hiprandStatex
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z13setup_gpu_rngxP12hiprandStatex, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z28__device_stub__setup_gpu_rngxP12hiprandStatex, .Lfunc_end0-_Z28__device_stub__setup_gpu_rngxP12hiprandStatex
.cfi_endproc
# -- End function
.globl _Z30__device_stub__gpu_estimate_pixP12hiprandStatexPf # -- Begin function _Z30__device_stub__gpu_estimate_pixP12hiprandStatexPf
.p2align 4, 0x90
.type _Z30__device_stub__gpu_estimate_pixP12hiprandStatexPf,@function
_Z30__device_stub__gpu_estimate_pixP12hiprandStatexPf: # @_Z30__device_stub__gpu_estimate_pixP12hiprandStatexPf
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movq %rcx, 48(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rax
movq %rax, 104(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z15gpu_estimate_pixP12hiprandStatexPf, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end1:
.size _Z30__device_stub__gpu_estimate_pixP12hiprandStatexPf, .Lfunc_end1-_Z30__device_stub__gpu_estimate_pixP12hiprandStatexPf
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z15cpu_estimate_pix
.LCPI2_0:
.long 0x30000000 # float 4.65661287E-10
.LCPI2_1:
.long 0x3f800000 # float 1
.LCPI2_2:
.long 0x40800000 # float 4
.LCPI2_3:
.long 0x00000000 # float 0
.text
.globl _Z15cpu_estimate_pix
.p2align 4, 0x90
.type _Z15cpu_estimate_pix,@function
_Z15cpu_estimate_pix: # @_Z15cpu_estimate_pix
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $16, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %rbp, -16
movq %rdi, %rbx
testq %rdi, %rdi
jle .LBB2_1
# %bb.4: # %.lr.ph.preheader
movq %rbx, %r14
# implicit-def: $ebp
jmp .LBB2_5
.p2align 4, 0x90
.LBB2_7: # %call.sqrt
# in Loop: Header=BB2_5 Depth=1
callq sqrtf
.LBB2_8: # %.lr.ph.split
# in Loop: Header=BB2_5 Depth=1
movss .LCPI2_1(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
ucomiss %xmm0, %xmm1
sbbl $-1, %ebp
decq %r14
je .LBB2_2
.LBB2_5: # %.lr.ph
# =>This Inner Loop Header: Depth=1
callq random
xorps %xmm1, %xmm1
cvtsi2ss %rax, %xmm1
movss .LCPI2_0(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
mulss %xmm0, %xmm1
movss %xmm1, 12(%rsp) # 4-byte Spill
callq random
xorps %xmm0, %xmm0
cvtsi2ss %rax, %xmm0
mulss .LCPI2_0(%rip), %xmm0
movss 12(%rsp), %xmm1 # 4-byte Reload
# xmm1 = mem[0],zero,zero,zero
mulss %xmm1, %xmm1
mulss %xmm0, %xmm0
addss %xmm1, %xmm0
ucomiss .LCPI2_3(%rip), %xmm0
jb .LBB2_7
# %bb.6: # in Loop: Header=BB2_5 Depth=1
sqrtss %xmm0, %xmm0
jmp .LBB2_8
.LBB2_2: # %._crit_edge.loopexit
xorps %xmm0, %xmm0
cvtsi2ss %ebp, %xmm0
jmp .LBB2_3
.LBB2_1:
xorps %xmm0, %xmm0
.LBB2_3: # %._crit_edge
xorps %xmm1, %xmm1
cvtsi2ss %rbx, %xmm1
divss %xmm1, %xmm0
mulss .LCPI2_2(%rip), %xmm0
addq $16, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z15cpu_estimate_pix, .Lfunc_end2-_Z15cpu_estimate_pix
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI3_0:
.long 0x30000000 # float 4.65661287E-10
.LCPI3_1:
.long 0x3f800000 # float 1
.LCPI3_2:
.long 0x40800000 # float 4
.LCPI3_3:
.long 0x00000000 # float 0
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $152, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %rbx
movq 8(%rsi), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r12
movslq %r12d, %r14
movq 16(%rbx), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, 16(%rsp) # 8-byte Spill
movq 24(%rbx), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %rbp
callq _ZNSt6chrono3_V212steady_clock3nowEv
movq %rax, %r15
testq %r14, %r14
jle .LBB3_1
# %bb.2: # %.lr.ph.i.preheader
movq %r14, %r13
# implicit-def: $ebx
jmp .LBB3_3
.p2align 4, 0x90
.LBB3_5: # %call.sqrt
# in Loop: Header=BB3_3 Depth=1
callq sqrtf
.LBB3_6: # %.lr.ph.i.split
# in Loop: Header=BB3_3 Depth=1
movss .LCPI3_1(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
ucomiss %xmm0, %xmm1
sbbl $-1, %ebx
decq %r13
je .LBB3_7
.LBB3_3: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
callq random
xorps %xmm1, %xmm1
cvtsi2ss %rax, %xmm1
movss .LCPI3_0(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
mulss %xmm0, %xmm1
movss %xmm1, 12(%rsp) # 4-byte Spill
callq random
xorps %xmm0, %xmm0
cvtsi2ss %rax, %xmm0
mulss .LCPI3_0(%rip), %xmm0
movss 12(%rsp), %xmm1 # 4-byte Reload
# xmm1 = mem[0],zero,zero,zero
mulss %xmm1, %xmm1
mulss %xmm0, %xmm0
addss %xmm1, %xmm0
ucomiss .LCPI3_3(%rip), %xmm0
jb .LBB3_5
# %bb.4: # in Loop: Header=BB3_3 Depth=1
sqrtss %xmm0, %xmm0
jmp .LBB3_6
.LBB3_7: # %._crit_edge.loopexit.i
xorps %xmm1, %xmm1
cvtsi2ss %ebx, %xmm1
jmp .LBB3_8
.LBB3_1:
xorps %xmm1, %xmm1
.LBB3_8: # %_Z15cpu_estimate_pix.exit
xorps %xmm0, %xmm0
cvtsi2ss %r12d, %xmm0
divss %xmm0, %xmm1
mulss .LCPI3_2(%rip), %xmm1
movss %xmm1, 12(%rsp) # 4-byte Spill
callq _ZNSt6chrono3_V212steady_clock3nowEv
movq %rax, %r12
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $8, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss 12(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r13
testq %r13, %r13
je .LBB3_33
# %bb.9: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%r13)
je .LBB3_11
# %bb.10:
movzbl 67(%r13), %ecx
jmp .LBB3_12
.LBB3_11:
movq %r13, %rdi
movq %rax, %rbx
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r13), %rax
movq %r13, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %rbx, %rax
.LBB3_12: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $4, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
subq %r15, %r12
movabsq $2361183241434822607, %rcx # imm = 0x20C49BA5E353F7CF
movq %r12, %rax
imulq %rcx
movq %rdx, %rsi
shrq $63, %rsi
sarq $7, %rdx
addq %rdx, %rsi
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIlEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r15
testq %r15, %r15
je .LBB3_33
# %bb.13: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i51
movq %rbp, %r13
movslq 16(%rsp), %rbx # 4-byte Folded Reload
movslq %r13d, %rbp
cmpb $0, 56(%r15)
je .LBB3_15
# %bb.14:
movzbl 67(%r15), %ecx
jmp .LBB3_16
.LBB3_15:
movq %r15, %rdi
movq %rax, %r12
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r12, %rax
.LBB3_16: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit54
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
leaq (%r14,%rbp), %rax
decq %rax
movq %rbp, %rcx
imulq %rbx, %rcx
cqto
idivq %rcx
movq %rax, %r14
incq %r14
imulq %r14, %rbp
movq %rbp, %rax
shlq $4, %rax
leaq (%rax,%rax,2), %rsi
leaq 104(%rsp), %rdi
callq hipMalloc
movl %r14d, %r15d
movabsq $4294967296, %rax # imm = 0x100000000
orq %rax, %r15
movl %r13d, %r12d
orq %rax, %r12
movq %r15, %rdi
movl $1, %esi
movq %r12, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_18
# %bb.17:
movq 104(%rsp), %r14
xorl %edi, %edi
callq time
movq %rbp, 88(%rsp)
movq %r14, 80(%rsp)
movq %rax, 72(%rsp)
leaq 88(%rsp), %rax
movq %rax, 112(%rsp)
leaq 80(%rsp), %rax
movq %rax, 120(%rsp)
leaq 72(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 64(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z13setup_gpu_rngxP12hiprandStatex, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_18:
leaq (,%rbp,4), %r13
leaq 96(%rsp), %rdi
movq %r13, %rsi
callq hipMalloc
movq %r13, %rdi
callq malloc
movq %rax, %r14
callq _ZNSt6chrono3_V212steady_clock3nowEv
movq %rax, 16(%rsp) # 8-byte Spill
movq %r15, %rdi
movl $1, %esi
movq %r12, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_20
# %bb.19:
movq 104(%rsp), %rax
movq 96(%rsp), %rcx
movq %rbp, 88(%rsp)
movq %rax, 80(%rsp)
movq %rbx, 72(%rsp)
movq %rcx, 64(%rsp)
leaq 88(%rsp), %rax
movq %rax, 112(%rsp)
leaq 80(%rsp), %rax
movq %rax, 120(%rsp)
leaq 72(%rsp), %rax
movq %rax, 128(%rsp)
leaq 64(%rsp), %rax
movq %rax, 136(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 144(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z15gpu_estimate_pixP12hiprandStatexPf, %edi
pushq 144(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_20:
movq 96(%rsp), %rsi
movq %r14, %rdi
movq %r13, %rdx
movl $2, %ecx
callq hipMemcpy
xorps %xmm1, %xmm1
testq %rbp, %rbp
jle .LBB3_21
# %bb.31: # %.lr.ph.preheader
xorl %eax, %eax
movabsq $2361183241434822607, %r12 # imm = 0x20C49BA5E353F7CF
.p2align 4, 0x90
.LBB3_32: # %.lr.ph
# =>This Inner Loop Header: Depth=1
addss (%r14,%rax,4), %xmm1
incq %rax
cmpq %rax, %rbp
jne .LBB3_32
jmp .LBB3_22
.LBB3_21:
movabsq $2361183241434822607, %r12 # imm = 0x20C49BA5E353F7CF
.LBB3_22: # %._crit_edge
cvtsi2ss %rbp, %xmm0
divss %xmm0, %xmm1
movss %xmm1, 12(%rsp) # 4-byte Spill
callq _ZNSt6chrono3_V212steady_clock3nowEv
movq %rax, %r14
movl $_ZSt4cout, %edi
movl $.L.str.2, %esi
movl $8, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss 12(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r15
testq %r15, %r15
je .LBB3_33
# %bb.23: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i56
cmpb $0, 56(%r15)
je .LBB3_25
# %bb.24:
movzbl 67(%r15), %ecx
jmp .LBB3_26
.LBB3_25:
movq %r15, %rdi
movq %rax, %rbx
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %rbx, %rax
.LBB3_26: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit59
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.3, %esi
movl $4, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
subq 16(%rsp), %r14 # 8-byte Folded Reload
movq %r14, %rax
imulq %r12
movq %rdx, %rsi
shrq $63, %rsi
sarq $7, %rdx
addq %rdx, %rsi
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIlEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB3_33
# %bb.27: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i61
cmpb $0, 56(%rbx)
je .LBB3_29
# %bb.28:
movzbl 67(%rbx), %ecx
jmp .LBB3_30
.LBB3_29:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB3_30: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit64
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
xorl %eax, %eax
addq $152, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB3_33:
.cfi_def_cfa_offset 208
callq _ZSt16__throw_bad_castv
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13setup_gpu_rngxP12hiprandStatex, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15gpu_estimate_pixP12hiprandStatexPf, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z13setup_gpu_rngxP12hiprandStatex,@object # @_Z13setup_gpu_rngxP12hiprandStatex
.section .rodata,"a",@progbits
.globl _Z13setup_gpu_rngxP12hiprandStatex
.p2align 3, 0x0
_Z13setup_gpu_rngxP12hiprandStatex:
.quad _Z28__device_stub__setup_gpu_rngxP12hiprandStatex
.size _Z13setup_gpu_rngxP12hiprandStatex, 8
.type _Z15gpu_estimate_pixP12hiprandStatexPf,@object # @_Z15gpu_estimate_pixP12hiprandStatexPf
.globl _Z15gpu_estimate_pixP12hiprandStatexPf
.p2align 3, 0x0
_Z15gpu_estimate_pixP12hiprandStatexPf:
.quad _Z30__device_stub__gpu_estimate_pixP12hiprandStatexPf
.size _Z15gpu_estimate_pixP12hiprandStatexPf, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "CPU-PI: "
.size .L.str, 9
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "CPU "
.size .L.str.1, 5
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "GPU-PI: "
.size .L.str.2, 9
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "GPU "
.size .L.str.3, 5
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z13setup_gpu_rngxP12hiprandStatex"
.size .L__unnamed_1, 35
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z15gpu_estimate_pixP12hiprandStatexPf"
.size .L__unnamed_2, 39
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__setup_gpu_rngxP12hiprandStatex
.addrsig_sym _Z30__device_stub__gpu_estimate_pixP12hiprandStatexPf
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z13setup_gpu_rngxP12hiprandStatex
.addrsig_sym _Z15gpu_estimate_pixP12hiprandStatexPf
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
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