system stringclasses 7 values | input stringlengths 10 94.5k | output stringlengths 14 55.5k |
|---|---|---|
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000fd52e_00000000-6_exercise_4.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3988:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3988:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z15cpu_estimate_pix
.type _Z15cpu_estimate_pix, @function
_Z15cpu_estimate_pix:
.LFB3982:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $16, %rsp
.cfi_def_cfa_offset 48
movq %rdi, %r12
testq %rdi, %rdi
jle .L4
movl $0, %ebx
.L7:
call random@PLT
pxor %xmm0, %xmm0
cvtsi2ssq %rax, %xmm0
mulss .LC0(%rip), %xmm0
movss %xmm0, 12(%rsp)
call random@PLT
pxor %xmm1, %xmm1
cvtsi2ssq %rax, %xmm1
mulss .LC0(%rip), %xmm1
movss 12(%rsp), %xmm0
mulss %xmm0, %xmm0
mulss %xmm1, %xmm1
addss %xmm1, %xmm0
sqrtss %xmm0, %xmm0
movss .LC1(%rip), %xmm2
comiss %xmm0, %xmm2
sbbl $-1, %ebp
addq $1, %rbx
cmpq %r12, %rbx
jne .L7
.L4:
pxor %xmm0, %xmm0
cvtsi2ssl %ebp, %xmm0
pxor %xmm1, %xmm1
cvtsi2ssq %r12, %xmm1
divss %xmm1, %xmm0
mulss .LC2(%rip), %xmm0
addq $16, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3982:
.size _Z15cpu_estimate_pix, .-_Z15cpu_estimate_pix
.globl _Z53__device_stub__Z13setup_gpu_rngxP17curandStateXORWOWxxP17curandStateXORWOWx
.type _Z53__device_stub__Z13setup_gpu_rngxP17curandStateXORWOWxxP17curandStateXORWOWx, @function
_Z53__device_stub__Z13setup_gpu_rngxP17curandStateXORWOWxxP17curandStateXORWOWx:
.LFB4010:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z13setup_gpu_rngxP17curandStateXORWOWx(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4010:
.size _Z53__device_stub__Z13setup_gpu_rngxP17curandStateXORWOWxxP17curandStateXORWOWx, .-_Z53__device_stub__Z13setup_gpu_rngxP17curandStateXORWOWxxP17curandStateXORWOWx
.globl _Z13setup_gpu_rngxP17curandStateXORWOWx
.type _Z13setup_gpu_rngxP17curandStateXORWOWx, @function
_Z13setup_gpu_rngxP17curandStateXORWOWx:
.LFB4011:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z53__device_stub__Z13setup_gpu_rngxP17curandStateXORWOWxxP17curandStateXORWOWx
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4011:
.size _Z13setup_gpu_rngxP17curandStateXORWOWx, .-_Z13setup_gpu_rngxP17curandStateXORWOWx
.globl _Z57__device_stub__Z15gpu_estimate_pixP17curandStateXORWOWxPfxP17curandStateXORWOWxPf
.type _Z57__device_stub__Z15gpu_estimate_pixP17curandStateXORWOWxPfxP17curandStateXORWOWxPf, @function
_Z57__device_stub__Z15gpu_estimate_pixP17curandStateXORWOWxPfxP17curandStateXORWOWxPf:
.LFB4012:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L23
.L19:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L24
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z15gpu_estimate_pixP17curandStateXORWOWxPf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L19
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4012:
.size _Z57__device_stub__Z15gpu_estimate_pixP17curandStateXORWOWxPfxP17curandStateXORWOWxPf, .-_Z57__device_stub__Z15gpu_estimate_pixP17curandStateXORWOWxPfxP17curandStateXORWOWxPf
.globl _Z15gpu_estimate_pixP17curandStateXORWOWxPf
.type _Z15gpu_estimate_pixP17curandStateXORWOWxPf, @function
_Z15gpu_estimate_pixP17curandStateXORWOWxPf:
.LFB4013:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z57__device_stub__Z15gpu_estimate_pixP17curandStateXORWOWxPfxP17curandStateXORWOWxPf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4013:
.size _Z15gpu_estimate_pixP17curandStateXORWOWxPf, .-_Z15gpu_estimate_pixP17curandStateXORWOWxPf
.section .rodata.str1.1,"aMS",@progbits,1
.LC4:
.string "CPU-PI: "
.LC5:
.string "CPU "
.LC6:
.string "GPU-PI: "
.LC7:
.string "GPU "
.text
.globl main
.type main, @function
main:
.LFB3983:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $72, %rsp
.cfi_def_cfa_offset 128
movq %rsi, %rbx
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movslq %eax, %r13
movq 16(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movslq %eax, %r14
movq 24(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %r12
movslq %eax, %rbp
call _ZNSt6chrono3_V212steady_clock3nowEv@PLT
movq %rax, 8(%rsp)
movq %r13, %rdi
call _Z15cpu_estimate_pix
movss %xmm0, (%rsp)
call _ZNSt6chrono3_V212steady_clock3nowEv@PLT
movq %rax, %rbx
leaq .LC4(%rip), %rsi
leaq _ZSt4cout(%rip), %r15
movq %r15, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
pxor %xmm0, %xmm0
cvtss2sd (%rsp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq .LC5(%rip), %rsi
movq %r15, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq 8(%rsp), %rax
subq %rax, %rbx
movabsq $2361183241434822607, %rdx
movq %rbx, %rax
imulq %rdx
sarq $7, %rdx
sarq $63, %rbx
subq %rbx, %rdx
movq %rdx, %rsi
call _ZNSo9_M_insertIlEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq -1(%r13,%rbp), %rax
movq %r14, %rcx
imulq %rbp, %rcx
cqto
idivq %rcx
leaq 1(%rax), %r13
imulq %r13, %rbp
leaq 0(%rbp,%rbp,2), %rsi
salq $4, %rsi
leaq 16(%rsp), %rdi
call cudaMalloc@PLT
movl %r12d, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl %r13d, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L36
.L28:
leaq 0(,%rbp,4), %r15
leaq 24(%rsp), %rdi
movq %r15, %rsi
call cudaMalloc@PLT
movq %r15, %rdi
call malloc@PLT
movq %rax, %rbx
call _ZNSt6chrono3_V212steady_clock3nowEv@PLT
movq %rax, (%rsp)
movl %r12d, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl %r13d, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L37
.L29:
movl $2, %ecx
movq %r15, %rdx
movq 24(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
testq %rbp, %rbp
jle .L33
movq %rbx, %rax
addq %r15, %rbx
pxor %xmm0, %xmm0
.L31:
addss (%rax), %xmm0
addq $4, %rax
cmpq %rbx, %rax
jne .L31
.L30:
pxor %xmm1, %xmm1
cvtsi2ssq %rbp, %xmm1
divss %xmm1, %xmm0
movss %xmm0, 8(%rsp)
call _ZNSt6chrono3_V212steady_clock3nowEv@PLT
movq %rax, %rbx
leaq .LC6(%rip), %rsi
leaq _ZSt4cout(%rip), %rbp
movq %rbp, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
pxor %xmm0, %xmm0
cvtss2sd 8(%rsp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq .LC7(%rip), %rsi
movq %rbp, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq (%rsp), %rax
subq %rax, %rbx
movabsq $2361183241434822607, %rdx
movq %rbx, %rax
imulq %rdx
sarq $7, %rdx
sarq $63, %rbx
subq %rbx, %rdx
movq %rdx, %rsi
call _ZNSo9_M_insertIlEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L38
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L36:
.cfi_restore_state
movl $0, %edi
call time@PLT
movq %rax, %rdx
movq 16(%rsp), %rsi
movq %rbp, %rdi
call _Z53__device_stub__Z13setup_gpu_rngxP17curandStateXORWOWxxP17curandStateXORWOWx
jmp .L28
.L37:
movq 24(%rsp), %rcx
movq %r14, %rdx
movq 16(%rsp), %rsi
movq %rbp, %rdi
call _Z57__device_stub__Z15gpu_estimate_pixP17curandStateXORWOWxPfxP17curandStateXORWOWxPf
jmp .L29
.L33:
pxor %xmm0, %xmm0
jmp .L30
.L38:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3983:
.size main, .-main
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC8:
.string "_Z15gpu_estimate_pixP17curandStateXORWOWxPf"
.align 8
.LC9:
.string "_Z13setup_gpu_rngxP17curandStateXORWOWx"
.section .rodata.str1.1
.LC10:
.string "precalc_xorwow_matrix"
.LC11:
.string "precalc_xorwow_offset_matrix"
.LC12:
.string "mrg32k3aM1"
.LC13:
.string "mrg32k3aM2"
.LC14:
.string "mrg32k3aM1SubSeq"
.LC15:
.string "mrg32k3aM2SubSeq"
.LC16:
.string "mrg32k3aM1Seq"
.LC17:
.string "mrg32k3aM2Seq"
.LC18:
.string "__cr_lgamma_table"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB4015:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _Z15gpu_estimate_pixP17curandStateXORWOWxPf(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _Z13setup_gpu_rngxP17curandStateXORWOWx(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $102400, %r9d
movl $0, %r8d
leaq .LC10(%rip), %rdx
movq %rdx, %rcx
leaq _ZL21precalc_xorwow_matrix(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $102400, %r9d
movl $0, %r8d
leaq .LC11(%rip), %rdx
movq %rdx, %rcx
leaq _ZL28precalc_xorwow_offset_matrix(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC12(%rip), %rdx
movq %rdx, %rcx
leaq _ZL10mrg32k3aM1(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC13(%rip), %rdx
movq %rdx, %rcx
leaq _ZL10mrg32k3aM2(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2016, %r9d
movl $0, %r8d
leaq .LC14(%rip), %rdx
movq %rdx, %rcx
leaq _ZL16mrg32k3aM1SubSeq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2016, %r9d
movl $0, %r8d
leaq .LC15(%rip), %rdx
movq %rdx, %rcx
leaq _ZL16mrg32k3aM2SubSeq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC16(%rip), %rdx
movq %rdx, %rcx
leaq _ZL13mrg32k3aM1Seq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC17(%rip), %rdx
movq %rdx, %rcx
leaq _ZL13mrg32k3aM2Seq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $72, %r9d
movl $0, %r8d
leaq .LC18(%rip), %rdx
movq %rdx, %rcx
leaq _ZL17__cr_lgamma_table(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4015:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL17__cr_lgamma_table
.comm _ZL17__cr_lgamma_table,72,32
.local _ZL13mrg32k3aM2Seq
.comm _ZL13mrg32k3aM2Seq,2304,32
.local _ZL13mrg32k3aM1Seq
.comm _ZL13mrg32k3aM1Seq,2304,32
.local _ZL16mrg32k3aM2SubSeq
.comm _ZL16mrg32k3aM2SubSeq,2016,32
.local _ZL16mrg32k3aM1SubSeq
.comm _ZL16mrg32k3aM1SubSeq,2016,32
.local _ZL10mrg32k3aM2
.comm _ZL10mrg32k3aM2,2304,32
.local _ZL10mrg32k3aM1
.comm _ZL10mrg32k3aM1,2304,32
.local _ZL28precalc_xorwow_offset_matrix
.comm _ZL28precalc_xorwow_offset_matrix,102400,32
.local _ZL21precalc_xorwow_matrix
.comm _ZL21precalc_xorwow_matrix,102400,32
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC0:
.long 805306368
.align 4
.LC1:
.long 1065353216
.align 4
.LC2:
.long 1082130432
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "exercise_4.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z28__device_stub__setup_gpu_rngxP12hiprandStatex # -- Begin function _Z28__device_stub__setup_gpu_rngxP12hiprandStatex
.p2align 4, 0x90
.type _Z28__device_stub__setup_gpu_rngxP12hiprandStatex,@function
_Z28__device_stub__setup_gpu_rngxP12hiprandStatex: # @_Z28__device_stub__setup_gpu_rngxP12hiprandStatex
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z13setup_gpu_rngxP12hiprandStatex, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z28__device_stub__setup_gpu_rngxP12hiprandStatex, .Lfunc_end0-_Z28__device_stub__setup_gpu_rngxP12hiprandStatex
.cfi_endproc
# -- End function
.globl _Z30__device_stub__gpu_estimate_pixP12hiprandStatexPf # -- Begin function _Z30__device_stub__gpu_estimate_pixP12hiprandStatexPf
.p2align 4, 0x90
.type _Z30__device_stub__gpu_estimate_pixP12hiprandStatexPf,@function
_Z30__device_stub__gpu_estimate_pixP12hiprandStatexPf: # @_Z30__device_stub__gpu_estimate_pixP12hiprandStatexPf
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movq %rcx, 48(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rax
movq %rax, 104(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z15gpu_estimate_pixP12hiprandStatexPf, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end1:
.size _Z30__device_stub__gpu_estimate_pixP12hiprandStatexPf, .Lfunc_end1-_Z30__device_stub__gpu_estimate_pixP12hiprandStatexPf
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z15cpu_estimate_pix
.LCPI2_0:
.long 0x30000000 # float 4.65661287E-10
.LCPI2_1:
.long 0x3f800000 # float 1
.LCPI2_2:
.long 0x40800000 # float 4
.LCPI2_3:
.long 0x00000000 # float 0
.text
.globl _Z15cpu_estimate_pix
.p2align 4, 0x90
.type _Z15cpu_estimate_pix,@function
_Z15cpu_estimate_pix: # @_Z15cpu_estimate_pix
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $16, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %rbp, -16
movq %rdi, %rbx
testq %rdi, %rdi
jle .LBB2_1
# %bb.4: # %.lr.ph.preheader
movq %rbx, %r14
# implicit-def: $ebp
jmp .LBB2_5
.p2align 4, 0x90
.LBB2_7: # %call.sqrt
# in Loop: Header=BB2_5 Depth=1
callq sqrtf
.LBB2_8: # %.lr.ph.split
# in Loop: Header=BB2_5 Depth=1
movss .LCPI2_1(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
ucomiss %xmm0, %xmm1
sbbl $-1, %ebp
decq %r14
je .LBB2_2
.LBB2_5: # %.lr.ph
# =>This Inner Loop Header: Depth=1
callq random
xorps %xmm1, %xmm1
cvtsi2ss %rax, %xmm1
movss .LCPI2_0(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
mulss %xmm0, %xmm1
movss %xmm1, 12(%rsp) # 4-byte Spill
callq random
xorps %xmm0, %xmm0
cvtsi2ss %rax, %xmm0
mulss .LCPI2_0(%rip), %xmm0
movss 12(%rsp), %xmm1 # 4-byte Reload
# xmm1 = mem[0],zero,zero,zero
mulss %xmm1, %xmm1
mulss %xmm0, %xmm0
addss %xmm1, %xmm0
ucomiss .LCPI2_3(%rip), %xmm0
jb .LBB2_7
# %bb.6: # in Loop: Header=BB2_5 Depth=1
sqrtss %xmm0, %xmm0
jmp .LBB2_8
.LBB2_2: # %._crit_edge.loopexit
xorps %xmm0, %xmm0
cvtsi2ss %ebp, %xmm0
jmp .LBB2_3
.LBB2_1:
xorps %xmm0, %xmm0
.LBB2_3: # %._crit_edge
xorps %xmm1, %xmm1
cvtsi2ss %rbx, %xmm1
divss %xmm1, %xmm0
mulss .LCPI2_2(%rip), %xmm0
addq $16, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z15cpu_estimate_pix, .Lfunc_end2-_Z15cpu_estimate_pix
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI3_0:
.long 0x30000000 # float 4.65661287E-10
.LCPI3_1:
.long 0x3f800000 # float 1
.LCPI3_2:
.long 0x40800000 # float 4
.LCPI3_3:
.long 0x00000000 # float 0
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $152, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %rbx
movq 8(%rsi), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r12
movslq %r12d, %r14
movq 16(%rbx), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, 16(%rsp) # 8-byte Spill
movq 24(%rbx), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %rbp
callq _ZNSt6chrono3_V212steady_clock3nowEv
movq %rax, %r15
testq %r14, %r14
jle .LBB3_1
# %bb.2: # %.lr.ph.i.preheader
movq %r14, %r13
# implicit-def: $ebx
jmp .LBB3_3
.p2align 4, 0x90
.LBB3_5: # %call.sqrt
# in Loop: Header=BB3_3 Depth=1
callq sqrtf
.LBB3_6: # %.lr.ph.i.split
# in Loop: Header=BB3_3 Depth=1
movss .LCPI3_1(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
ucomiss %xmm0, %xmm1
sbbl $-1, %ebx
decq %r13
je .LBB3_7
.LBB3_3: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
callq random
xorps %xmm1, %xmm1
cvtsi2ss %rax, %xmm1
movss .LCPI3_0(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
mulss %xmm0, %xmm1
movss %xmm1, 12(%rsp) # 4-byte Spill
callq random
xorps %xmm0, %xmm0
cvtsi2ss %rax, %xmm0
mulss .LCPI3_0(%rip), %xmm0
movss 12(%rsp), %xmm1 # 4-byte Reload
# xmm1 = mem[0],zero,zero,zero
mulss %xmm1, %xmm1
mulss %xmm0, %xmm0
addss %xmm1, %xmm0
ucomiss .LCPI3_3(%rip), %xmm0
jb .LBB3_5
# %bb.4: # in Loop: Header=BB3_3 Depth=1
sqrtss %xmm0, %xmm0
jmp .LBB3_6
.LBB3_7: # %._crit_edge.loopexit.i
xorps %xmm1, %xmm1
cvtsi2ss %ebx, %xmm1
jmp .LBB3_8
.LBB3_1:
xorps %xmm1, %xmm1
.LBB3_8: # %_Z15cpu_estimate_pix.exit
xorps %xmm0, %xmm0
cvtsi2ss %r12d, %xmm0
divss %xmm0, %xmm1
mulss .LCPI3_2(%rip), %xmm1
movss %xmm1, 12(%rsp) # 4-byte Spill
callq _ZNSt6chrono3_V212steady_clock3nowEv
movq %rax, %r12
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $8, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss 12(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r13
testq %r13, %r13
je .LBB3_33
# %bb.9: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%r13)
je .LBB3_11
# %bb.10:
movzbl 67(%r13), %ecx
jmp .LBB3_12
.LBB3_11:
movq %r13, %rdi
movq %rax, %rbx
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r13), %rax
movq %r13, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %rbx, %rax
.LBB3_12: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $4, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
subq %r15, %r12
movabsq $2361183241434822607, %rcx # imm = 0x20C49BA5E353F7CF
movq %r12, %rax
imulq %rcx
movq %rdx, %rsi
shrq $63, %rsi
sarq $7, %rdx
addq %rdx, %rsi
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIlEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r15
testq %r15, %r15
je .LBB3_33
# %bb.13: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i51
movq %rbp, %r13
movslq 16(%rsp), %rbx # 4-byte Folded Reload
movslq %r13d, %rbp
cmpb $0, 56(%r15)
je .LBB3_15
# %bb.14:
movzbl 67(%r15), %ecx
jmp .LBB3_16
.LBB3_15:
movq %r15, %rdi
movq %rax, %r12
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r12, %rax
.LBB3_16: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit54
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
leaq (%r14,%rbp), %rax
decq %rax
movq %rbp, %rcx
imulq %rbx, %rcx
cqto
idivq %rcx
movq %rax, %r14
incq %r14
imulq %r14, %rbp
movq %rbp, %rax
shlq $4, %rax
leaq (%rax,%rax,2), %rsi
leaq 104(%rsp), %rdi
callq hipMalloc
movl %r14d, %r15d
movabsq $4294967296, %rax # imm = 0x100000000
orq %rax, %r15
movl %r13d, %r12d
orq %rax, %r12
movq %r15, %rdi
movl $1, %esi
movq %r12, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_18
# %bb.17:
movq 104(%rsp), %r14
xorl %edi, %edi
callq time
movq %rbp, 88(%rsp)
movq %r14, 80(%rsp)
movq %rax, 72(%rsp)
leaq 88(%rsp), %rax
movq %rax, 112(%rsp)
leaq 80(%rsp), %rax
movq %rax, 120(%rsp)
leaq 72(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 64(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z13setup_gpu_rngxP12hiprandStatex, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_18:
leaq (,%rbp,4), %r13
leaq 96(%rsp), %rdi
movq %r13, %rsi
callq hipMalloc
movq %r13, %rdi
callq malloc
movq %rax, %r14
callq _ZNSt6chrono3_V212steady_clock3nowEv
movq %rax, 16(%rsp) # 8-byte Spill
movq %r15, %rdi
movl $1, %esi
movq %r12, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_20
# %bb.19:
movq 104(%rsp), %rax
movq 96(%rsp), %rcx
movq %rbp, 88(%rsp)
movq %rax, 80(%rsp)
movq %rbx, 72(%rsp)
movq %rcx, 64(%rsp)
leaq 88(%rsp), %rax
movq %rax, 112(%rsp)
leaq 80(%rsp), %rax
movq %rax, 120(%rsp)
leaq 72(%rsp), %rax
movq %rax, 128(%rsp)
leaq 64(%rsp), %rax
movq %rax, 136(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 144(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z15gpu_estimate_pixP12hiprandStatexPf, %edi
pushq 144(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_20:
movq 96(%rsp), %rsi
movq %r14, %rdi
movq %r13, %rdx
movl $2, %ecx
callq hipMemcpy
xorps %xmm1, %xmm1
testq %rbp, %rbp
jle .LBB3_21
# %bb.31: # %.lr.ph.preheader
xorl %eax, %eax
movabsq $2361183241434822607, %r12 # imm = 0x20C49BA5E353F7CF
.p2align 4, 0x90
.LBB3_32: # %.lr.ph
# =>This Inner Loop Header: Depth=1
addss (%r14,%rax,4), %xmm1
incq %rax
cmpq %rax, %rbp
jne .LBB3_32
jmp .LBB3_22
.LBB3_21:
movabsq $2361183241434822607, %r12 # imm = 0x20C49BA5E353F7CF
.LBB3_22: # %._crit_edge
cvtsi2ss %rbp, %xmm0
divss %xmm0, %xmm1
movss %xmm1, 12(%rsp) # 4-byte Spill
callq _ZNSt6chrono3_V212steady_clock3nowEv
movq %rax, %r14
movl $_ZSt4cout, %edi
movl $.L.str.2, %esi
movl $8, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss 12(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r15
testq %r15, %r15
je .LBB3_33
# %bb.23: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i56
cmpb $0, 56(%r15)
je .LBB3_25
# %bb.24:
movzbl 67(%r15), %ecx
jmp .LBB3_26
.LBB3_25:
movq %r15, %rdi
movq %rax, %rbx
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %rbx, %rax
.LBB3_26: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit59
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.3, %esi
movl $4, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
subq 16(%rsp), %r14 # 8-byte Folded Reload
movq %r14, %rax
imulq %r12
movq %rdx, %rsi
shrq $63, %rsi
sarq $7, %rdx
addq %rdx, %rsi
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIlEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB3_33
# %bb.27: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i61
cmpb $0, 56(%rbx)
je .LBB3_29
# %bb.28:
movzbl 67(%rbx), %ecx
jmp .LBB3_30
.LBB3_29:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB3_30: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit64
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
xorl %eax, %eax
addq $152, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB3_33:
.cfi_def_cfa_offset 208
callq _ZSt16__throw_bad_castv
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13setup_gpu_rngxP12hiprandStatex, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15gpu_estimate_pixP12hiprandStatexPf, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z13setup_gpu_rngxP12hiprandStatex,@object # @_Z13setup_gpu_rngxP12hiprandStatex
.section .rodata,"a",@progbits
.globl _Z13setup_gpu_rngxP12hiprandStatex
.p2align 3, 0x0
_Z13setup_gpu_rngxP12hiprandStatex:
.quad _Z28__device_stub__setup_gpu_rngxP12hiprandStatex
.size _Z13setup_gpu_rngxP12hiprandStatex, 8
.type _Z15gpu_estimate_pixP12hiprandStatexPf,@object # @_Z15gpu_estimate_pixP12hiprandStatexPf
.globl _Z15gpu_estimate_pixP12hiprandStatexPf
.p2align 3, 0x0
_Z15gpu_estimate_pixP12hiprandStatexPf:
.quad _Z30__device_stub__gpu_estimate_pixP12hiprandStatexPf
.size _Z15gpu_estimate_pixP12hiprandStatexPf, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "CPU-PI: "
.size .L.str, 9
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "CPU "
.size .L.str.1, 5
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "GPU-PI: "
.size .L.str.2, 9
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "GPU "
.size .L.str.3, 5
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z13setup_gpu_rngxP12hiprandStatex"
.size .L__unnamed_1, 35
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z15gpu_estimate_pixP12hiprandStatexPf"
.size .L__unnamed_2, 39
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__setup_gpu_rngxP12hiprandStatex
.addrsig_sym _Z30__device_stub__gpu_estimate_pixP12hiprandStatexPf
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z13setup_gpu_rngxP12hiprandStatex
.addrsig_sym _Z15gpu_estimate_pixP12hiprandStatexPf
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | /*
example to show how to use stream and async method to make the data
transfer and kernel function executed concurrently.
*/
#include <iostream>
using namespace std;
static void HandleError( cudaError_t err,const char *file, int line ) {
if (err != cudaSuccess) {
cout << cudaGetErrorString(err) << file << line << endl;
exit( EXIT_FAILURE );
}
}
#define HANDLE_ERROR( err ) (HandleError( err, __FILE__, __LINE__ ))
#define DIM 16
__shared__ int share[256];
__global__ void fun(int * in, int * out)
{
int tid = threadIdx.x + blockIdx.x * blockDim.x;
*out = *in + 1000*tid;
}
int main()
{
int * inGlobe;
int * outGlobe;
int tmp[DIM*DIM];
int tmp2[DIM*DIM];
cudaStream_t stream;
HANDLE_ERROR( cudaStreamCreate( &stream ) );
HANDLE_ERROR(cudaMalloc((void**)&inGlobe, DIM * DIM * sizeof (int)));
HANDLE_ERROR(cudaMalloc((void**)&outGlobe, DIM * DIM * sizeof (int)));
for (int i = 0; i < DIM*DIM; ++i)
tmp[i] = i;
for (int i = 0; i < DIM*DIM; ++i)
{
cudaMemcpyAsync(inGlobe+i,tmp+i,sizeof(int),cudaMemcpyHostToDevice,stream ) ;
//0 is device and stream is exec stream.
fun<<<1,1,0,stream>>>(inGlobe+i,outGlobe+i);
cudaMemcpyAsync(tmp2+i,outGlobe+i,sizeof(int),cudaMemcpyDeviceToHost,stream);
}
HANDLE_ERROR( cudaStreamSynchronize( stream ) );
for (int i = 0; i < DIM * DIM; ++i)
cout << tmp2[i] << " " ;
int k;
cin >> k;
return 0;
} | code for sm_80
Function : _Z3funPiS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ MOV R3, c[0x0][0x164] ; /* 0x0000590000037a02 */
/* 0x000fe20000000f00 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0030*/ MOV R2, c[0x0][0x160] ; /* 0x0000580000027a02 */
/* 0x000fca0000000f00 */
/*0040*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*0050*/ MOV R4, c[0x0][0x168] ; /* 0x00005a0000047a02 */
/* 0x000fc60000000f00 */
/*0060*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e280000002100 */
/*0070*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x000e240000002500 */
/*0080*/ IMAD R0, R5, c[0x0][0x0], R0 ; /* 0x0000000005007a24 */
/* 0x001fe200078e0200 */
/*0090*/ MOV R5, c[0x0][0x16c] ; /* 0x00005b0000057a02 */
/* 0x000fc60000000f00 */
/*00a0*/ IMAD R7, R0, 0x3e8, R3 ; /* 0x000003e800077824 */
/* 0x004fca00078e0203 */
/*00b0*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x000fe2000c101904 */
/*00c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00d0*/ BRA 0xd0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /*
example to show how to use stream and async method to make the data
transfer and kernel function executed concurrently.
*/
#include <iostream>
using namespace std;
static void HandleError( cudaError_t err,const char *file, int line ) {
if (err != cudaSuccess) {
cout << cudaGetErrorString(err) << file << line << endl;
exit( EXIT_FAILURE );
}
}
#define HANDLE_ERROR( err ) (HandleError( err, __FILE__, __LINE__ ))
#define DIM 16
__shared__ int share[256];
__global__ void fun(int * in, int * out)
{
int tid = threadIdx.x + blockIdx.x * blockDim.x;
*out = *in + 1000*tid;
}
int main()
{
int * inGlobe;
int * outGlobe;
int tmp[DIM*DIM];
int tmp2[DIM*DIM];
cudaStream_t stream;
HANDLE_ERROR( cudaStreamCreate( &stream ) );
HANDLE_ERROR(cudaMalloc((void**)&inGlobe, DIM * DIM * sizeof (int)));
HANDLE_ERROR(cudaMalloc((void**)&outGlobe, DIM * DIM * sizeof (int)));
for (int i = 0; i < DIM*DIM; ++i)
tmp[i] = i;
for (int i = 0; i < DIM*DIM; ++i)
{
cudaMemcpyAsync(inGlobe+i,tmp+i,sizeof(int),cudaMemcpyHostToDevice,stream ) ;
//0 is device and stream is exec stream.
fun<<<1,1,0,stream>>>(inGlobe+i,outGlobe+i);
cudaMemcpyAsync(tmp2+i,outGlobe+i,sizeof(int),cudaMemcpyDeviceToHost,stream);
}
HANDLE_ERROR( cudaStreamSynchronize( stream ) );
for (int i = 0; i < DIM * DIM; ++i)
cout << tmp2[i] << " " ;
int k;
cin >> k;
return 0;
} | .file "tmpxft_0009b56f_00000000-6_simpeStream.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL11HandleError9cudaErrorPKci, @function
_ZL11HandleError9cudaErrorPKci:
.LFB3669:
.cfi_startproc
testl %edi, %edi
jne .L6
ret
.L6:
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movq %rsi, %rbp
movl %edx, %ebx
call cudaGetErrorString@PLT
movq %rax, %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq %rbp, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl %ebx, %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $1, %edi
call exit@PLT
.cfi_endproc
.LFE3669:
.size _ZL11HandleError9cudaErrorPKci, .-_ZL11HandleError9cudaErrorPKci
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3673:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3673:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z24__device_stub__Z3funPiS_PiS_
.type _Z24__device_stub__Z3funPiS_PiS_, @function
_Z24__device_stub__Z3funPiS_PiS_:
.LFB3695:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L13
.L9:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L14
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L13:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z3funPiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L9
.L14:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3695:
.size _Z24__device_stub__Z3funPiS_PiS_, .-_Z24__device_stub__Z3funPiS_PiS_
.globl _Z3funPiS_
.type _Z3funPiS_, @function
_Z3funPiS_:
.LFB3696:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z24__device_stub__Z3funPiS_PiS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3696:
.size _Z3funPiS_, .-_Z3funPiS_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "/home/ubuntu/Datasets/stackv2/train-structured/SPLURGE831/practice/master/codes/cuda/simpeStream.cu"
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string " "
.text
.globl main
.type main, @function
main:
.LFB3670:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $2120, %rsp
.cfi_def_cfa_offset 2160
movq %fs:40, %rax
movq %rax, 2104(%rsp)
xorl %eax, %eax
leaq 16(%rsp), %rdi
call cudaStreamCreate@PLT
movl %eax, %edi
movl $33, %edx
leaq .LC0(%rip), %rbx
movq %rbx, %rsi
call _ZL11HandleError9cudaErrorPKci
movq %rsp, %rdi
movl $1024, %esi
call cudaMalloc@PLT
movl %eax, %edi
movl $35, %edx
movq %rbx, %rsi
call _ZL11HandleError9cudaErrorPKci
leaq 8(%rsp), %rdi
movl $1024, %esi
call cudaMalloc@PLT
movl %eax, %edi
movl $36, %edx
movq %rbx, %rsi
call _ZL11HandleError9cudaErrorPKci
movl $0, %eax
.L18:
movl %eax, 48(%rsp,%rax,4)
addq $1, %rax
cmpq $256, %rax
jne .L18
movl $0, %ebx
leaq 48(%rsp), %r12
jmp .L20
.L19:
leaq 1072(%rsp), %rbp
movq %rbx, %rsi
addq 8(%rsp), %rsi
leaq (%rbx,%rbp), %rdi
movq 16(%rsp), %r8
movl $2, %ecx
movl $4, %edx
call cudaMemcpyAsync@PLT
addq $4, %rbx
cmpq $1024, %rbx
je .L27
.L20:
leaq (%r12,%rbx), %rsi
movq %rbx, %rdi
addq (%rsp), %rdi
movq 16(%rsp), %r8
movl $1, %ecx
movl $4, %edx
call cudaMemcpyAsync@PLT
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movq 16(%rsp), %r9
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L19
movq %rbx, %rsi
addq 8(%rsp), %rsi
movq %rbx, %rdi
addq (%rsp), %rdi
call _Z24__device_stub__Z3funPiS_PiS_
jmp .L19
.L27:
movq 16(%rsp), %rdi
call cudaStreamSynchronize@PLT
movl %eax, %edi
movl $49, %edx
leaq .LC0(%rip), %rsi
call _ZL11HandleError9cudaErrorPKci
leaq 2096(%rsp), %r13
leaq _ZSt4cout(%rip), %r12
leaq .LC1(%rip), %rbx
.L21:
movl 0(%rbp), %esi
movq %r12, %rdi
call _ZNSolsEi@PLT
movq %rax, %rdi
movl $2, %edx
movq %rbx, %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
addq $4, %rbp
cmpq %r13, %rbp
jne .L21
leaq 36(%rsp), %rsi
leaq _ZSt3cin(%rip), %rdi
call _ZNSirsERi@PLT
movq 2104(%rsp), %rax
subq %fs:40, %rax
jne .L28
movl $0, %eax
addq $2120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L28:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3670:
.size main, .-main
.section .rodata.str1.1
.LC2:
.string "_Z3funPiS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3698:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z3funPiS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3698:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /*
example to show how to use stream and async method to make the data
transfer and kernel function executed concurrently.
*/
#include <iostream>
using namespace std;
static void HandleError( cudaError_t err,const char *file, int line ) {
if (err != cudaSuccess) {
cout << cudaGetErrorString(err) << file << line << endl;
exit( EXIT_FAILURE );
}
}
#define HANDLE_ERROR( err ) (HandleError( err, __FILE__, __LINE__ ))
#define DIM 16
__shared__ int share[256];
__global__ void fun(int * in, int * out)
{
int tid = threadIdx.x + blockIdx.x * blockDim.x;
*out = *in + 1000*tid;
}
int main()
{
int * inGlobe;
int * outGlobe;
int tmp[DIM*DIM];
int tmp2[DIM*DIM];
cudaStream_t stream;
HANDLE_ERROR( cudaStreamCreate( &stream ) );
HANDLE_ERROR(cudaMalloc((void**)&inGlobe, DIM * DIM * sizeof (int)));
HANDLE_ERROR(cudaMalloc((void**)&outGlobe, DIM * DIM * sizeof (int)));
for (int i = 0; i < DIM*DIM; ++i)
tmp[i] = i;
for (int i = 0; i < DIM*DIM; ++i)
{
cudaMemcpyAsync(inGlobe+i,tmp+i,sizeof(int),cudaMemcpyHostToDevice,stream ) ;
//0 is device and stream is exec stream.
fun<<<1,1,0,stream>>>(inGlobe+i,outGlobe+i);
cudaMemcpyAsync(tmp2+i,outGlobe+i,sizeof(int),cudaMemcpyDeviceToHost,stream);
}
HANDLE_ERROR( cudaStreamSynchronize( stream ) );
for (int i = 0; i < DIM * DIM; ++i)
cout << tmp2[i] << " " ;
int k;
cin >> k;
return 0;
} | /*
example to show how to use stream and async method to make the data
transfer and kernel function executed concurrently.
*/
#include <hip/hip_runtime.h>
#include <iostream>
using namespace std;
static void HandleError( hipError_t err,const char *file, int line ) {
if (err != hipSuccess) {
cout << hipGetErrorString(err) << file << line << endl;
exit( EXIT_FAILURE );
}
}
#define HANDLE_ERROR( err ) (HandleError( err, __FILE__, __LINE__ ))
#define DIM 16
__shared__ int share[256];
__global__ void fun(int * in, int * out)
{
int tid = threadIdx.x + blockIdx.x * blockDim.x;
*out = *in + 1000*tid;
}
int main()
{
int * inGlobe;
int * outGlobe;
int tmp[DIM*DIM];
int tmp2[DIM*DIM];
hipStream_t stream;
HANDLE_ERROR( hipStreamCreate( &stream ) );
HANDLE_ERROR(hipMalloc((void**)&inGlobe, DIM * DIM * sizeof (int)));
HANDLE_ERROR(hipMalloc((void**)&outGlobe, DIM * DIM * sizeof (int)));
for (int i = 0; i < DIM*DIM; ++i)
tmp[i] = i;
for (int i = 0; i < DIM*DIM; ++i)
{
hipMemcpyAsync(inGlobe+i,tmp+i,sizeof(int),hipMemcpyHostToDevice,stream ) ;
//0 is device and stream is exec stream.
fun<<<1,1,0,stream>>>(inGlobe+i,outGlobe+i);
hipMemcpyAsync(tmp2+i,outGlobe+i,sizeof(int),hipMemcpyDeviceToHost,stream);
}
HANDLE_ERROR( hipStreamSynchronize( stream ) );
for (int i = 0; i < DIM * DIM; ++i)
cout << tmp2[i] << " " ;
int k;
cin >> k;
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | /*
example to show how to use stream and async method to make the data
transfer and kernel function executed concurrently.
*/
#include <hip/hip_runtime.h>
#include <iostream>
using namespace std;
static void HandleError( hipError_t err,const char *file, int line ) {
if (err != hipSuccess) {
cout << hipGetErrorString(err) << file << line << endl;
exit( EXIT_FAILURE );
}
}
#define HANDLE_ERROR( err ) (HandleError( err, __FILE__, __LINE__ ))
#define DIM 16
__shared__ int share[256];
__global__ void fun(int * in, int * out)
{
int tid = threadIdx.x + blockIdx.x * blockDim.x;
*out = *in + 1000*tid;
}
int main()
{
int * inGlobe;
int * outGlobe;
int tmp[DIM*DIM];
int tmp2[DIM*DIM];
hipStream_t stream;
HANDLE_ERROR( hipStreamCreate( &stream ) );
HANDLE_ERROR(hipMalloc((void**)&inGlobe, DIM * DIM * sizeof (int)));
HANDLE_ERROR(hipMalloc((void**)&outGlobe, DIM * DIM * sizeof (int)));
for (int i = 0; i < DIM*DIM; ++i)
tmp[i] = i;
for (int i = 0; i < DIM*DIM; ++i)
{
hipMemcpyAsync(inGlobe+i,tmp+i,sizeof(int),hipMemcpyHostToDevice,stream ) ;
//0 is device and stream is exec stream.
fun<<<1,1,0,stream>>>(inGlobe+i,outGlobe+i);
hipMemcpyAsync(tmp2+i,outGlobe+i,sizeof(int),hipMemcpyDeviceToHost,stream);
}
HANDLE_ERROR( hipStreamSynchronize( stream ) );
for (int i = 0; i < DIM * DIM; ++i)
cout << tmp2[i] << " " ;
int k;
cin >> k;
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3funPiS_
.globl _Z3funPiS_
.p2align 8
.type _Z3funPiS_,@function
_Z3funPiS_:
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b32 s1, s[0:1], 0x1c
s_waitcnt lgkmcnt(0)
s_load_b32 s0, s[4:5], 0x0
s_and_b32 s1, s1, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[1:2], null, s15, s1, v[0:1]
v_mov_b32_e32 v0, 0
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[2:3], null, v1, 0x3e8, s[0:1]
global_store_b32 v0, v2, s[6:7]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3funPiS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3funPiS_, .Lfunc_end0-_Z3funPiS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3funPiS_
.private_segment_fixed_size: 0
.sgpr_count: 16
.sgpr_spill_count: 0
.symbol: _Z3funPiS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | /*
example to show how to use stream and async method to make the data
transfer and kernel function executed concurrently.
*/
#include <hip/hip_runtime.h>
#include <iostream>
using namespace std;
static void HandleError( hipError_t err,const char *file, int line ) {
if (err != hipSuccess) {
cout << hipGetErrorString(err) << file << line << endl;
exit( EXIT_FAILURE );
}
}
#define HANDLE_ERROR( err ) (HandleError( err, __FILE__, __LINE__ ))
#define DIM 16
__shared__ int share[256];
__global__ void fun(int * in, int * out)
{
int tid = threadIdx.x + blockIdx.x * blockDim.x;
*out = *in + 1000*tid;
}
int main()
{
int * inGlobe;
int * outGlobe;
int tmp[DIM*DIM];
int tmp2[DIM*DIM];
hipStream_t stream;
HANDLE_ERROR( hipStreamCreate( &stream ) );
HANDLE_ERROR(hipMalloc((void**)&inGlobe, DIM * DIM * sizeof (int)));
HANDLE_ERROR(hipMalloc((void**)&outGlobe, DIM * DIM * sizeof (int)));
for (int i = 0; i < DIM*DIM; ++i)
tmp[i] = i;
for (int i = 0; i < DIM*DIM; ++i)
{
hipMemcpyAsync(inGlobe+i,tmp+i,sizeof(int),hipMemcpyHostToDevice,stream ) ;
//0 is device and stream is exec stream.
fun<<<1,1,0,stream>>>(inGlobe+i,outGlobe+i);
hipMemcpyAsync(tmp2+i,outGlobe+i,sizeof(int),hipMemcpyDeviceToHost,stream);
}
HANDLE_ERROR( hipStreamSynchronize( stream ) );
for (int i = 0; i < DIM * DIM; ++i)
cout << tmp2[i] << " " ;
int k;
cin >> k;
return 0;
} | .text
.file "simpeStream.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z18__device_stub__funPiS_ # -- Begin function _Z18__device_stub__funPiS_
.p2align 4, 0x90
.type _Z18__device_stub__funPiS_,@function
_Z18__device_stub__funPiS_: # @_Z18__device_stub__funPiS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z3funPiS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z18__device_stub__funPiS_, .Lfunc_end0-_Z18__device_stub__funPiS_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $2168, %rsp # imm = 0x878
.cfi_def_cfa_offset 2224
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
leaq 8(%rsp), %rdi
callq hipStreamCreate
testl %eax, %eax
jne .LBB1_1
# %bb.3: # %_ZL11HandleError10hipError_tPKci.exit
leaq 24(%rsp), %rdi
movl $1024, %esi # imm = 0x400
callq hipMalloc
testl %eax, %eax
jne .LBB1_4
# %bb.5: # %_ZL11HandleError10hipError_tPKci.exit20
leaq 16(%rsp), %rdi
movl $1024, %esi # imm = 0x400
callq hipMalloc
testl %eax, %eax
jne .LBB1_17
# %bb.6: # %_ZL11HandleError10hipError_tPKci.exit22.preheader
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_7: # %_ZL11HandleError10hipError_tPKci.exit22
# =>This Inner Loop Header: Depth=1
movl %eax, 1136(%rsp,%rax,4)
incq %rax
cmpq $256, %rax # imm = 0x100
jne .LBB1_7
# %bb.8: # %.preheader
movabsq $4294967297, %rbx # imm = 0x100000001
xorl %r14d, %r14d
leaq 64(%rsp), %r15
leaq 56(%rsp), %r12
leaq 48(%rsp), %r13
leaq 32(%rsp), %rbp
jmp .LBB1_9
.p2align 4, 0x90
.LBB1_11: # in Loop: Header=BB1_9 Depth=1
leaq (%rsp,%r14), %rdi
addq $112, %rdi
movq 16(%rsp), %rsi
addq %r14, %rsi
movq 8(%rsp), %r8
movl $4, %edx
movl $2, %ecx
callq hipMemcpyAsync
addq $4, %r14
cmpq $1024, %r14 # imm = 0x400
je .LBB1_12
.LBB1_9: # =>This Inner Loop Header: Depth=1
movq 24(%rsp), %rdi
addq %r14, %rdi
leaq (%rsp,%r14), %rsi
addq $1136, %rsi # imm = 0x470
movq 8(%rsp), %r8
movl $4, %edx
movl $1, %ecx
callq hipMemcpyAsync
movq 8(%rsp), %r9
movq %rbx, %rdi
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_11
# %bb.10: # in Loop: Header=BB1_9 Depth=1
movq 24(%rsp), %rax
addq %r14, %rax
movq 16(%rsp), %rcx
addq %r14, %rcx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
leaq 104(%rsp), %rax
movq %rax, 32(%rsp)
leaq 96(%rsp), %rax
movq %rax, 40(%rsp)
leaq 80(%rsp), %rdi
movq %r15, %rsi
movq %r12, %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
movq 64(%rsp), %rcx
movl 72(%rsp), %r8d
movl $_Z3funPiS_, %edi
movq %rbp, %r9
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB1_11
.LBB1_12:
movq 8(%rsp), %rdi
callq hipStreamSynchronize
testl %eax, %eax
jne .LBB1_16
# %bb.13: # %_ZL11HandleError10hipError_tPKci.exit24.preheader
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_14: # %_ZL11HandleError10hipError_tPKci.exit24
# =>This Inner Loop Header: Depth=1
movl 112(%rsp,%rbx,4), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movl $.L.str.1, %esi
movl $2, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
incq %rbx
cmpq $256, %rbx # imm = 0x100
jne .LBB1_14
# %bb.15:
leaq 32(%rsp), %rsi
movl $_ZSt3cin, %edi
callq _ZNSirsERi
xorl %eax, %eax
addq $2168, %rsp # imm = 0x878
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_1:
.cfi_def_cfa_offset 2224
movl %eax, %edi
callq hipGetErrorString
movl $_ZSt4cout, %edi
movq %rax, %rsi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movl $.L.str, %esi
movq %rax, %rdi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movq %rax, %rdi
movl $35, %esi
jmp .LBB1_2
.LBB1_4:
movl %eax, %edi
callq hipGetErrorString
movl $_ZSt4cout, %edi
movq %rax, %rsi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movl $.L.str, %esi
movq %rax, %rdi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movq %rax, %rdi
movl $37, %esi
jmp .LBB1_2
.LBB1_17:
movl %eax, %edi
callq hipGetErrorString
movl $_ZSt4cout, %edi
movq %rax, %rsi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movl $.L.str, %esi
movq %rax, %rdi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movq %rax, %rdi
movl $38, %esi
jmp .LBB1_2
.LBB1_16:
movl %eax, %edi
callq hipGetErrorString
movl $_ZSt4cout, %edi
movq %rax, %rsi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movl $.L.str, %esi
movq %rax, %rdi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movq %rax, %rdi
movl $51, %esi
.LBB1_2:
callq _ZNSolsEi
movq %rax, %rdi
callq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_
movl $1, %edi
callq exit
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3funPiS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3funPiS_,@object # @_Z3funPiS_
.section .rodata,"a",@progbits
.globl _Z3funPiS_
.p2align 3, 0x0
_Z3funPiS_:
.quad _Z18__device_stub__funPiS_
.size _Z3funPiS_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/SPLURGE831/practice/master/codes/cuda/simpeStream.hip"
.size .L.str, 111
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz " "
.size .L.str.1, 3
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z3funPiS_"
.size .L__unnamed_1, 11
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__funPiS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3funPiS_
.addrsig_sym _ZSt4cout
.addrsig_sym _ZSt3cin
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z3funPiS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ MOV R3, c[0x0][0x164] ; /* 0x0000590000037a02 */
/* 0x000fe20000000f00 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0030*/ MOV R2, c[0x0][0x160] ; /* 0x0000580000027a02 */
/* 0x000fca0000000f00 */
/*0040*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*0050*/ MOV R4, c[0x0][0x168] ; /* 0x00005a0000047a02 */
/* 0x000fc60000000f00 */
/*0060*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e280000002100 */
/*0070*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x000e240000002500 */
/*0080*/ IMAD R0, R5, c[0x0][0x0], R0 ; /* 0x0000000005007a24 */
/* 0x001fe200078e0200 */
/*0090*/ MOV R5, c[0x0][0x16c] ; /* 0x00005b0000057a02 */
/* 0x000fc60000000f00 */
/*00a0*/ IMAD R7, R0, 0x3e8, R3 ; /* 0x000003e800077824 */
/* 0x004fca00078e0203 */
/*00b0*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x000fe2000c101904 */
/*00c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00d0*/ BRA 0xd0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3funPiS_
.globl _Z3funPiS_
.p2align 8
.type _Z3funPiS_,@function
_Z3funPiS_:
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b32 s1, s[0:1], 0x1c
s_waitcnt lgkmcnt(0)
s_load_b32 s0, s[4:5], 0x0
s_and_b32 s1, s1, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[1:2], null, s15, s1, v[0:1]
v_mov_b32_e32 v0, 0
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[2:3], null, v1, 0x3e8, s[0:1]
global_store_b32 v0, v2, s[6:7]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3funPiS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3funPiS_, .Lfunc_end0-_Z3funPiS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3funPiS_
.private_segment_fixed_size: 0
.sgpr_count: 16
.sgpr_spill_count: 0
.symbol: _Z3funPiS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0009b56f_00000000-6_simpeStream.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL11HandleError9cudaErrorPKci, @function
_ZL11HandleError9cudaErrorPKci:
.LFB3669:
.cfi_startproc
testl %edi, %edi
jne .L6
ret
.L6:
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movq %rsi, %rbp
movl %edx, %ebx
call cudaGetErrorString@PLT
movq %rax, %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq %rbp, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl %ebx, %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $1, %edi
call exit@PLT
.cfi_endproc
.LFE3669:
.size _ZL11HandleError9cudaErrorPKci, .-_ZL11HandleError9cudaErrorPKci
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3673:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3673:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z24__device_stub__Z3funPiS_PiS_
.type _Z24__device_stub__Z3funPiS_PiS_, @function
_Z24__device_stub__Z3funPiS_PiS_:
.LFB3695:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L13
.L9:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L14
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L13:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z3funPiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L9
.L14:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3695:
.size _Z24__device_stub__Z3funPiS_PiS_, .-_Z24__device_stub__Z3funPiS_PiS_
.globl _Z3funPiS_
.type _Z3funPiS_, @function
_Z3funPiS_:
.LFB3696:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z24__device_stub__Z3funPiS_PiS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3696:
.size _Z3funPiS_, .-_Z3funPiS_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "/home/ubuntu/Datasets/stackv2/train-structured/SPLURGE831/practice/master/codes/cuda/simpeStream.cu"
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string " "
.text
.globl main
.type main, @function
main:
.LFB3670:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $2120, %rsp
.cfi_def_cfa_offset 2160
movq %fs:40, %rax
movq %rax, 2104(%rsp)
xorl %eax, %eax
leaq 16(%rsp), %rdi
call cudaStreamCreate@PLT
movl %eax, %edi
movl $33, %edx
leaq .LC0(%rip), %rbx
movq %rbx, %rsi
call _ZL11HandleError9cudaErrorPKci
movq %rsp, %rdi
movl $1024, %esi
call cudaMalloc@PLT
movl %eax, %edi
movl $35, %edx
movq %rbx, %rsi
call _ZL11HandleError9cudaErrorPKci
leaq 8(%rsp), %rdi
movl $1024, %esi
call cudaMalloc@PLT
movl %eax, %edi
movl $36, %edx
movq %rbx, %rsi
call _ZL11HandleError9cudaErrorPKci
movl $0, %eax
.L18:
movl %eax, 48(%rsp,%rax,4)
addq $1, %rax
cmpq $256, %rax
jne .L18
movl $0, %ebx
leaq 48(%rsp), %r12
jmp .L20
.L19:
leaq 1072(%rsp), %rbp
movq %rbx, %rsi
addq 8(%rsp), %rsi
leaq (%rbx,%rbp), %rdi
movq 16(%rsp), %r8
movl $2, %ecx
movl $4, %edx
call cudaMemcpyAsync@PLT
addq $4, %rbx
cmpq $1024, %rbx
je .L27
.L20:
leaq (%r12,%rbx), %rsi
movq %rbx, %rdi
addq (%rsp), %rdi
movq 16(%rsp), %r8
movl $1, %ecx
movl $4, %edx
call cudaMemcpyAsync@PLT
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movq 16(%rsp), %r9
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L19
movq %rbx, %rsi
addq 8(%rsp), %rsi
movq %rbx, %rdi
addq (%rsp), %rdi
call _Z24__device_stub__Z3funPiS_PiS_
jmp .L19
.L27:
movq 16(%rsp), %rdi
call cudaStreamSynchronize@PLT
movl %eax, %edi
movl $49, %edx
leaq .LC0(%rip), %rsi
call _ZL11HandleError9cudaErrorPKci
leaq 2096(%rsp), %r13
leaq _ZSt4cout(%rip), %r12
leaq .LC1(%rip), %rbx
.L21:
movl 0(%rbp), %esi
movq %r12, %rdi
call _ZNSolsEi@PLT
movq %rax, %rdi
movl $2, %edx
movq %rbx, %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
addq $4, %rbp
cmpq %r13, %rbp
jne .L21
leaq 36(%rsp), %rsi
leaq _ZSt3cin(%rip), %rdi
call _ZNSirsERi@PLT
movq 2104(%rsp), %rax
subq %fs:40, %rax
jne .L28
movl $0, %eax
addq $2120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L28:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3670:
.size main, .-main
.section .rodata.str1.1
.LC2:
.string "_Z3funPiS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3698:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z3funPiS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3698:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "simpeStream.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z18__device_stub__funPiS_ # -- Begin function _Z18__device_stub__funPiS_
.p2align 4, 0x90
.type _Z18__device_stub__funPiS_,@function
_Z18__device_stub__funPiS_: # @_Z18__device_stub__funPiS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z3funPiS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z18__device_stub__funPiS_, .Lfunc_end0-_Z18__device_stub__funPiS_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $2168, %rsp # imm = 0x878
.cfi_def_cfa_offset 2224
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
leaq 8(%rsp), %rdi
callq hipStreamCreate
testl %eax, %eax
jne .LBB1_1
# %bb.3: # %_ZL11HandleError10hipError_tPKci.exit
leaq 24(%rsp), %rdi
movl $1024, %esi # imm = 0x400
callq hipMalloc
testl %eax, %eax
jne .LBB1_4
# %bb.5: # %_ZL11HandleError10hipError_tPKci.exit20
leaq 16(%rsp), %rdi
movl $1024, %esi # imm = 0x400
callq hipMalloc
testl %eax, %eax
jne .LBB1_17
# %bb.6: # %_ZL11HandleError10hipError_tPKci.exit22.preheader
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_7: # %_ZL11HandleError10hipError_tPKci.exit22
# =>This Inner Loop Header: Depth=1
movl %eax, 1136(%rsp,%rax,4)
incq %rax
cmpq $256, %rax # imm = 0x100
jne .LBB1_7
# %bb.8: # %.preheader
movabsq $4294967297, %rbx # imm = 0x100000001
xorl %r14d, %r14d
leaq 64(%rsp), %r15
leaq 56(%rsp), %r12
leaq 48(%rsp), %r13
leaq 32(%rsp), %rbp
jmp .LBB1_9
.p2align 4, 0x90
.LBB1_11: # in Loop: Header=BB1_9 Depth=1
leaq (%rsp,%r14), %rdi
addq $112, %rdi
movq 16(%rsp), %rsi
addq %r14, %rsi
movq 8(%rsp), %r8
movl $4, %edx
movl $2, %ecx
callq hipMemcpyAsync
addq $4, %r14
cmpq $1024, %r14 # imm = 0x400
je .LBB1_12
.LBB1_9: # =>This Inner Loop Header: Depth=1
movq 24(%rsp), %rdi
addq %r14, %rdi
leaq (%rsp,%r14), %rsi
addq $1136, %rsi # imm = 0x470
movq 8(%rsp), %r8
movl $4, %edx
movl $1, %ecx
callq hipMemcpyAsync
movq 8(%rsp), %r9
movq %rbx, %rdi
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_11
# %bb.10: # in Loop: Header=BB1_9 Depth=1
movq 24(%rsp), %rax
addq %r14, %rax
movq 16(%rsp), %rcx
addq %r14, %rcx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
leaq 104(%rsp), %rax
movq %rax, 32(%rsp)
leaq 96(%rsp), %rax
movq %rax, 40(%rsp)
leaq 80(%rsp), %rdi
movq %r15, %rsi
movq %r12, %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
movq 64(%rsp), %rcx
movl 72(%rsp), %r8d
movl $_Z3funPiS_, %edi
movq %rbp, %r9
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB1_11
.LBB1_12:
movq 8(%rsp), %rdi
callq hipStreamSynchronize
testl %eax, %eax
jne .LBB1_16
# %bb.13: # %_ZL11HandleError10hipError_tPKci.exit24.preheader
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_14: # %_ZL11HandleError10hipError_tPKci.exit24
# =>This Inner Loop Header: Depth=1
movl 112(%rsp,%rbx,4), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movl $.L.str.1, %esi
movl $2, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
incq %rbx
cmpq $256, %rbx # imm = 0x100
jne .LBB1_14
# %bb.15:
leaq 32(%rsp), %rsi
movl $_ZSt3cin, %edi
callq _ZNSirsERi
xorl %eax, %eax
addq $2168, %rsp # imm = 0x878
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_1:
.cfi_def_cfa_offset 2224
movl %eax, %edi
callq hipGetErrorString
movl $_ZSt4cout, %edi
movq %rax, %rsi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movl $.L.str, %esi
movq %rax, %rdi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movq %rax, %rdi
movl $35, %esi
jmp .LBB1_2
.LBB1_4:
movl %eax, %edi
callq hipGetErrorString
movl $_ZSt4cout, %edi
movq %rax, %rsi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movl $.L.str, %esi
movq %rax, %rdi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movq %rax, %rdi
movl $37, %esi
jmp .LBB1_2
.LBB1_17:
movl %eax, %edi
callq hipGetErrorString
movl $_ZSt4cout, %edi
movq %rax, %rsi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movl $.L.str, %esi
movq %rax, %rdi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movq %rax, %rdi
movl $38, %esi
jmp .LBB1_2
.LBB1_16:
movl %eax, %edi
callq hipGetErrorString
movl $_ZSt4cout, %edi
movq %rax, %rsi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movl $.L.str, %esi
movq %rax, %rdi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movq %rax, %rdi
movl $51, %esi
.LBB1_2:
callq _ZNSolsEi
movq %rax, %rdi
callq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_
movl $1, %edi
callq exit
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3funPiS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3funPiS_,@object # @_Z3funPiS_
.section .rodata,"a",@progbits
.globl _Z3funPiS_
.p2align 3, 0x0
_Z3funPiS_:
.quad _Z18__device_stub__funPiS_
.size _Z3funPiS_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/SPLURGE831/practice/master/codes/cuda/simpeStream.hip"
.size .L.str, 111
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz " "
.size .L.str.1, 3
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z3funPiS_"
.size .L__unnamed_1, 11
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__funPiS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3funPiS_
.addrsig_sym _ZSt4cout
.addrsig_sym _ZSt3cin
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
#define INTERVALS 1000000
// Max number of threads per block
#define THREADS 512
#define BLOCKS 64
double calculatePiCPU();
// Synchronous error checking call. Enable with nvcc -DDEBUG
__global__ void integrateOptimised(int *n, float *g_sum)
{
int idx = threadIdx.x + blockIdx.x * blockDim.x;
int tx = threadIdx.x;
// Shared memory to hold the sum for each block
__shared__ float s_sum[THREADS];
float sum = 0.0f;
float step = 1.0f / (float)*n;
for (int i = idx + 1; i <= *n; i += blockDim.x * BLOCKS)
{
float x = step * ((float)i - 0.5f);
sum += 4.0f / (1.0f+ x*x);
}
s_sum[tx] = sum * step;
// Wait for all threads to catch up
__syncthreads();
// For each block, do sum using shared memory
for (int i = blockDim.x / 2; i > 0; i >>= 1)
{
if (tx < i)
{
s_sum[tx] += s_sum[tx + i];
}
__syncthreads();
}
// Write results to global memory
g_sum[idx] = s_sum[tx];
} | code for sm_80
Function : _Z18integrateOptimisedPiPf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff047624 */
/* 0x000fe200078e00ff */
/*0020*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*0030*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff057624 */
/* 0x000fca00078e00ff */
/*0040*/ LDG.E R3, [R4.64] ; /* 0x0000000604037981 */
/* 0x000ea8000c1e1900 */
/*0050*/ S2R R7, SR_CTAID.X ; /* 0x0000000000077919 */
/* 0x000e280000002500 */
/*0060*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e220000002100 */
/*0070*/ I2F R6, R3 ; /* 0x0000000300067306 */
/* 0x004e640000201400 */
/*0080*/ IADD3 R2, R6, 0x1800000, RZ ; /* 0x0180000006027810 */
/* 0x002fc80007ffe0ff */
/*0090*/ LOP3.LUT R2, R2, 0x7f800000, RZ, 0xc0, !PT ; /* 0x7f80000002027812 */
/* 0x000fc800078ec0ff */
/*00a0*/ ISETP.GT.U32.AND P0, PT, R2, 0x1ffffff, PT ; /* 0x01ffffff0200780c */
/* 0x000fe20003f04070 */
/*00b0*/ IMAD R2, R7, c[0x0][0x0], R0 ; /* 0x0000000007027a24 */
/* 0x001fd800078e0200 */
/*00c0*/ @P0 BRA 0x110 ; /* 0x0000004000000947 */
/* 0x000fea0003800000 */
/*00d0*/ MOV R4, 0xf0 ; /* 0x000000f000047802 */
/* 0x000fe40000000f00 */
/*00e0*/ CALL.REL.NOINC 0x4c0 ; /* 0x000003d000007944 */
/* 0x000fea0003c00000 */
/*00f0*/ IMAD.MOV.U32 R4, RZ, RZ, R6 ; /* 0x000000ffff047224 */
/* 0x000fe200078e0006 */
/*0100*/ BRA 0x150 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*0110*/ MUFU.RCP R5, R6 ; /* 0x0000000600057308 */
/* 0x000e240000001000 */
/*0120*/ FFMA R4, R6, R5, -1 ; /* 0xbf80000006047423 */
/* 0x001fc80000000005 */
/*0130*/ FADD.FTZ R4, -R4, -RZ ; /* 0x800000ff04047221 */
/* 0x000fc80000010100 */
/*0140*/ FFMA R4, R5, R4, R5 ; /* 0x0000000405047223 */
/* 0x000fe40000000005 */
/*0150*/ ISETP.GE.AND P0, PT, R2, R3, PT ; /* 0x000000030200720c */
/* 0x000fe20003f06270 */
/*0160*/ BSSY B2, 0x340 ; /* 0x000001d000027945 */
/* 0x000fe20003800000 */
/*0170*/ IMAD.MOV.U32 R5, RZ, RZ, RZ ; /* 0x000000ffff057224 */
/* 0x000fd600078e00ff */
/*0180*/ @P0 BRA 0x330 ; /* 0x000001a000000947 */
/* 0x000fea0003800000 */
/*0190*/ IADD3 R6, R2, 0x1, RZ ; /* 0x0000000102067810 */
/* 0x000fe20007ffe0ff */
/*01a0*/ IMAD.MOV.U32 R5, RZ, RZ, RZ ; /* 0x000000ffff057224 */
/* 0x000fc600078e00ff */
/*01b0*/ I2F R7, R6 ; /* 0x0000000600077306 */
/* 0x0000620000201400 */
/*01c0*/ UMOV UR4, 0x40800000 ; /* 0x4080000000047882 */
/* 0x000fe20000000000 */
/*01d0*/ IMAD.MOV.U32 R9, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff097624 */
/* 0x000fe200078e00ff */
/*01e0*/ BSSY B1, 0x310 ; /* 0x0000012000017945 */
/* 0x000fe20003800000 */
/*01f0*/ IMAD.U32 R11, RZ, RZ, UR4 ; /* 0x00000004ff0b7e24 */
/* 0x000fe4000f8e00ff */
/*0200*/ IMAD R6, R9, 0x40, R6 ; /* 0x0000004009067824 */
/* 0x001fca00078e0206 */
/*0210*/ ISETP.GT.AND P2, PT, R6, R3, PT ; /* 0x000000030600720c */
/* 0x000fe20003f44270 */
/*0220*/ FADD R7, R7, -0.5 ; /* 0xbf00000007077421 */
/* 0x002fc80000000000 */
/*0230*/ FMUL R7, R7, R4 ; /* 0x0000000407077220 */
/* 0x000fc80000400000 */
/*0240*/ FFMA R10, R7, R7, 1 ; /* 0x3f800000070a7423 */
/* 0x000fc80000000007 */
/*0250*/ MUFU.RCP R7, R10 ; /* 0x0000000a00077308 */
/* 0x000e300000001000 */
/*0260*/ FCHK P0, R11, R10 ; /* 0x0000000a0b007302 */
/* 0x000e620000000000 */
/*0270*/ FFMA R8, -R10, R7, 1 ; /* 0x3f8000000a087423 */
/* 0x001fc80000000107 */
/*0280*/ FFMA R8, R7, R8, R7 ; /* 0x0000000807087223 */
/* 0x000fc80000000007 */
/*0290*/ FFMA R7, R8, 4, RZ ; /* 0x4080000008077823 */
/* 0x000fc800000000ff */
/*02a0*/ FFMA R9, -R10, R7, 4 ; /* 0x408000000a097423 */
/* 0x000fc80000000107 */
/*02b0*/ FFMA R8, R8, R9, R7 ; /* 0x0000000908087223 */
/* 0x000fe20000000007 */
/*02c0*/ @!P0 BRA 0x300 ; /* 0x0000003000008947 */
/* 0x002fea0003800000 */
/*02d0*/ MOV R8, 0x2f0 ; /* 0x000002f000087802 */
/* 0x000fe40000000f00 */
/*02e0*/ CALL.REL.NOINC 0x800 ; /* 0x0000051000007944 */
/* 0x000fea0003c00000 */
/*02f0*/ IMAD.MOV.U32 R8, RZ, RZ, R7 ; /* 0x000000ffff087224 */
/* 0x001fe400078e0007 */
/*0300*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0310*/ FADD R5, R8, R5 ; /* 0x0000000508057221 */
/* 0x000fe20000000000 */
/*0320*/ @!P2 BRA 0x1b0 ; /* 0xfffffe800000a947 */
/* 0x000fea000383ffff */
/*0330*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*0340*/ ULDC UR4, c[0x0][0x0] ; /* 0x0000000000047ab9 */
/* 0x000fe20000000800 */
/*0350*/ FMUL R5, R4, R5 ; /* 0x0000000504057220 */
/* 0x000fe20000400000 */
/*0360*/ USHF.R.U32.HI UR4, URZ, 0x1, UR4 ; /* 0x000000013f047899 */
/* 0x000fc80008011604 */
/*0370*/ STS [R0.X4], R5 ; /* 0x0000000500007388 */
/* 0x0001e80000004800 */
/*0380*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0390*/ ISETP.NE.AND P0, PT, RZ, UR4, PT ; /* 0x00000004ff007c0c */
/* 0x000fda000bf05270 */
/*03a0*/ @!P0 BRA 0x470 ; /* 0x000000c000008947 */
/* 0x000fea0003800000 */
/*03b0*/ IMAD.SHL.U32 R3, R0, 0x4, RZ ; /* 0x0000000400037824 */
/* 0x001fe400078e00ff */
/*03c0*/ IMAD.U32 R4, RZ, RZ, UR4 ; /* 0x00000004ff047e24 */
/* 0x000fca000f8e00ff */
/*03d0*/ ISETP.GE.AND P0, PT, R0, R4, PT ; /* 0x000000040000720c */
/* 0x000fda0003f06270 */
/*03e0*/ @!P0 IMAD R5, R4, 0x4, R3 ; /* 0x0000000404058824 */
/* 0x000fe200078e0203 */
/*03f0*/ @!P0 LDS R6, [R0.X4] ; /* 0x0000000000068984 */
/* 0x000fe20000004800 */
/*0400*/ SHF.R.U32.HI R4, RZ, 0x1, R4 ; /* 0x00000001ff047819 */
/* 0x000fc80000011604 */
/*0410*/ @!P0 LDS R5, [R5] ; /* 0x0000000005058984 */
/* 0x000e240000000800 */
/*0420*/ @!P0 FADD R7, R6, R5 ; /* 0x0000000506078221 */
/* 0x001fca0000000000 */
/*0430*/ @!P0 STS [R0.X4], R7 ; /* 0x0000000700008388 */
/* 0x0001e80000004800 */
/*0440*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0450*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fda0003f05270 */
/*0460*/ @P0 BRA 0x3d0 ; /* 0xffffff6000000947 */
/* 0x001fea000383ffff */
/*0470*/ LDS R5, [R0.X4] ; /* 0x0000000000057984 */
/* 0x001e220000004800 */
/*0480*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fc800078e00ff */
/*0490*/ IMAD.WIDE R2, R2, R3, c[0x0][0x168] ; /* 0x00005a0002027625 */
/* 0x000fca00078e0203 */
/*04a0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x001fe2000c101906 */
/*04b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*04c0*/ IMAD.SHL.U32 R5, R6, 0x2, RZ ; /* 0x0000000206057824 */
/* 0x000fca00078e00ff */
/*04d0*/ SHF.R.U32.HI R5, RZ, 0x18, R5 ; /* 0x00000018ff057819 */
/* 0x000fc80000011605 */
/*04e0*/ ISETP.NE.U32.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fda0003f05070 */
/*04f0*/ @P0 BRA 0x5b0 ; /* 0x000000b000000947 */
/* 0x000fea0003800000 */
/*0500*/ IMAD.SHL.U32 R5, R6, 0x2, RZ ; /* 0x0000000206057824 */
/* 0x000fca00078e00ff */
/*0510*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fda0003f05270 */
/*0520*/ @!P0 MUFU.RCP R5, R6 ; /* 0x0000000600058308 */
/* 0x0000620000001000 */
/*0530*/ @!P0 BRA 0x7d0 ; /* 0x0000029000008947 */
/* 0x000fea0003800000 */
/*0540*/ FFMA R6, R6, 1.84467440737095516160e+19, RZ ; /* 0x5f80000006067823 */
/* 0x001fc800000000ff */
/*0550*/ MUFU.RCP R5, R6 ; /* 0x0000000600057308 */
/* 0x002e240000001000 */
/*0560*/ FFMA R7, R6, R5, -1 ; /* 0xbf80000006077423 */
/* 0x001fc80000000005 */
/*0570*/ FADD.FTZ R8, -R7, -RZ ; /* 0x800000ff07087221 */
/* 0x000fc80000010100 */
/*0580*/ FFMA R5, R5, R8, R5 ; /* 0x0000000805057223 */
/* 0x000fc80000000005 */
/*0590*/ FFMA R5, R5, 1.84467440737095516160e+19, RZ ; /* 0x5f80000005057823 */
/* 0x000fe200000000ff */
/*05a0*/ BRA 0x7d0 ; /* 0x0000022000007947 */
/* 0x000fea0003800000 */
/*05b0*/ IADD3 R7, R5, -0xfd, RZ ; /* 0xffffff0305077810 */
/* 0x000fc80007ffe0ff */
/*05c0*/ ISETP.GT.U32.AND P0, PT, R7, 0x1, PT ; /* 0x000000010700780c */
/* 0x000fda0003f04070 */
/*05d0*/ @P0 BRA 0x7c0 ; /* 0x000001e000000947 */
/* 0x000fea0003800000 */
/*05e0*/ LOP3.LUT R8, R6, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff06087812 */
/* 0x000fe200078ec0ff */
/*05f0*/ IMAD.MOV.U32 R12, RZ, RZ, 0x3 ; /* 0x00000003ff0c7424 */
/* 0x000fe200078e00ff */
/*0600*/ IADD3 R5, R5, -0xfc, RZ ; /* 0xffffff0405057810 */
/* 0x000fe40007ffe0ff */
/*0610*/ LOP3.LUT R8, R8, 0x3f800000, RZ, 0xfc, !PT ; /* 0x3f80000008087812 */
/* 0x000fe400078efcff */
/*0620*/ SHF.L.U32 R13, R12, R7, RZ ; /* 0x000000070c0d7219 */
/* 0x000fe400000006ff */
/*0630*/ MUFU.RCP R9, R8 ; /* 0x0000000800097308 */
/* 0x000e240000001000 */
/*0640*/ FFMA R10, R8, R9, -1 ; /* 0xbf800000080a7423 */
/* 0x001fc80000000009 */
/*0650*/ FADD.FTZ R10, -R10, -RZ ; /* 0x800000ff0a0a7221 */
/* 0x000fc80000010100 */
/*0660*/ FFMA.RM R11, R9.reuse, R10.reuse, R9.reuse ; /* 0x0000000a090b7223 */
/* 0x1c0fe40000004009 */
/*0670*/ FFMA.RP R10, R9, R10, R9 ; /* 0x0000000a090a7223 */
/* 0x000fc60000008009 */
/*0680*/ LOP3.LUT R9, R11.reuse, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff0b097812 */
/* 0x040fe400078ec0ff */
/*0690*/ FSETP.NEU.FTZ.AND P0, PT, R11, R10, PT ; /* 0x0000000a0b00720b */
/* 0x000fe40003f1d000 */
/*06a0*/ LOP3.LUT R10, R9, 0x800000, RZ, 0xfc, !PT ; /* 0x00800000090a7812 */
/* 0x000fe400078efcff */
/*06b0*/ SEL R9, RZ, 0xffffffff, !P0 ; /* 0xffffffffff097807 */
/* 0x000fe40004000000 */
/*06c0*/ LOP3.LUT R8, R13, R10, RZ, 0xc0, !PT ; /* 0x0000000a0d087212 */
/* 0x000fe400078ec0ff */
/*06d0*/ SHF.R.U32.HI R5, RZ, R5, R10 ; /* 0x00000005ff057219 */
/* 0x000fe2000001160a */
/*06e0*/ IMAD.MOV R9, RZ, RZ, -R9 ; /* 0x000000ffff097224 */
/* 0x000fe200078e0a09 */
/*06f0*/ SHF.R.U32.HI R8, RZ, R7, R8 ; /* 0x00000007ff087219 */
/* 0x000fc80000011608 */
/*0700*/ LOP3.LUT P1, RZ, R9, R7, R10, 0xf8, !PT ; /* 0x0000000709ff7212 */
/* 0x000fe4000782f80a */
/*0710*/ LOP3.LUT P0, RZ, R8.reuse, 0x1, RZ, 0xc0, !PT ; /* 0x0000000108ff7812 */
/* 0x040fe4000780c0ff */
/*0720*/ LOP3.LUT P2, RZ, R8, 0x2, RZ, 0xc0, !PT ; /* 0x0000000208ff7812 */
/* 0x000fc8000784c0ff */
/*0730*/ PLOP3.LUT P0, PT, P0, P1, P2, 0xe0, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40000703c20 */
/*0740*/ LOP3.LUT P1, RZ, R6, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff06ff7812 */
/* 0x000fe4000782c0ff */
/*0750*/ SEL R7, RZ, 0x1, !P0 ; /* 0x00000001ff077807 */
/* 0x000fca0004000000 */
/*0760*/ IMAD.MOV R7, RZ, RZ, -R7 ; /* 0x000000ffff077224 */
/* 0x000fca00078e0a07 */
/*0770*/ ISETP.GE.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fda0003f06270 */
/*0780*/ @!P0 IADD3 R5, R5, 0x1, RZ ; /* 0x0000000105058810 */
/* 0x000fca0007ffe0ff */
/*0790*/ @!P1 IMAD.SHL.U32 R5, R5, 0x2, RZ ; /* 0x0000000205059824 */
/* 0x000fca00078e00ff */
/*07a0*/ LOP3.LUT R5, R5, 0x80000000, R6, 0xf8, !PT ; /* 0x8000000005057812 */
/* 0x000fe200078ef806 */
/*07b0*/ BRA 0x7d0 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*07c0*/ MUFU.RCP R5, R6 ; /* 0x0000000600057308 */
/* 0x0000640000001000 */
/*07d0*/ IMAD.MOV.U32 R6, RZ, RZ, R5 ; /* 0x000000ffff067224 */
/* 0x003fe400078e0005 */
/*07e0*/ IMAD.MOV.U32 R5, RZ, RZ, 0x0 ; /* 0x00000000ff057424 */
/* 0x000fc800078e00ff */
/*07f0*/ RET.REL.NODEC R4 0x0 ; /* 0xfffff80004007950 */
/* 0x000fea0003c3ffff */
/*0800*/ SHF.R.U32.HI R7, RZ, 0x17, R10 ; /* 0x00000017ff077819 */
/* 0x000fe2000001160a */
/*0810*/ BSSY B0, 0xde0 ; /* 0x000005c000007945 */
/* 0x000fe20003800000 */
/*0820*/ BSSY B3, 0x9d0 ; /* 0x000001a000037945 */
/* 0x000fe40003800000 */
/*0830*/ LOP3.LUT R16, R7, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff07107812 */
/* 0x000fc800078ec0ff */
/*0840*/ IADD3 R11, R16, -0x1, RZ ; /* 0xffffffff100b7810 */
/* 0x000fc80007ffe0ff */
/*0850*/ ISETP.GT.U32.AND P0, PT, R11, 0xfd, PT ; /* 0x000000fd0b00780c */
/* 0x000fda0003f04070 */
/*0860*/ @!P0 IMAD.MOV.U32 R9, RZ, RZ, RZ ; /* 0x000000ffff098224 */
/* 0x000fe200078e00ff */
/*0870*/ @!P0 BRA 0x9c0 ; /* 0x0000014000008947 */
/* 0x000fea0003800000 */
/*0880*/ FSETP.GTU.FTZ.AND P0, PT, |R10|, +INF , PT ; /* 0x7f8000000a00780b */
/* 0x000fe20003f1c200 */
/*0890*/ IMAD.MOV.U32 R7, RZ, RZ, R10 ; /* 0x000000ffff077224 */
/* 0x000fd800078e000a */
/*08a0*/ @P0 BREAK B3 ; /* 0x0000000000030942 */
/* 0x000fe20003800000 */
/*08b0*/ @P0 BRA 0xdc0 ; /* 0x0000050000000947 */
/* 0x000fea0003800000 */
/*08c0*/ IMAD.MOV.U32 R9, RZ, RZ, 0x40800000 ; /* 0x40800000ff097424 */
/* 0x000fca00078e00ff */
/*08d0*/ LOP3.LUT P0, RZ, R10, 0x7fffffff, R9, 0xc8, !PT ; /* 0x7fffffff0aff7812 */
/* 0x000fda000780c809 */
/*08e0*/ @!P0 BREAK B3 ; /* 0x0000000000038942 */
/* 0x000fe20003800000 */
/*08f0*/ @!P0 BRA 0xda0 ; /* 0x000004a000008947 */
/* 0x000fea0003800000 */
/*0900*/ FSETP.NEU.FTZ.AND P0, PT, |R7|, +INF , PT ; /* 0x7f8000000700780b */
/* 0x000fe40003f1d200 */
/*0910*/ LOP3.LUT P1, RZ, R9, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff09ff7812 */
/* 0x000fc8000782c0ff */
/*0920*/ PLOP3.LUT P0, PT, P0, P1, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000702572 */
/*0930*/ @P0 BREAK B3 ; /* 0x0000000000030942 */
/* 0x000fe20003800000 */
/*0940*/ @P0 BRA 0xd80 ; /* 0x0000043000000947 */
/* 0x000fea0003800000 */
/*0950*/ LOP3.LUT P0, RZ, R10, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff0aff7812 */
/* 0x000fda000780c0ff */
/*0960*/ @!P0 BREAK B3 ; /* 0x0000000000038942 */
/* 0x000fe20003800000 */
/*0970*/ @!P0 BRA 0xd50 ; /* 0x000003d000008947 */
/* 0x000fea0003800000 */
/*0980*/ ISETP.GE.AND P0, PT, R11, RZ, PT ; /* 0x000000ff0b00720c */
/* 0x000fe20003f06270 */
/*0990*/ IMAD.MOV.U32 R9, RZ, RZ, RZ ; /* 0x000000ffff097224 */
/* 0x000fd800078e00ff */
/*09a0*/ @!P0 FFMA R10, R7, 1.84467440737095516160e+19, RZ ; /* 0x5f800000070a8823 */
/* 0x000fe200000000ff */
/*09b0*/ @!P0 IADD3 R9, R9, 0x40, RZ ; /* 0x0000004009098810 */
/* 0x000fe40007ffe0ff */
/*09c0*/ BSYNC B3 ; /* 0x0000000000037941 */
/* 0x000fea0003800000 */
/*09d0*/ LEA R7, R16, 0xc0800000, 0x17 ; /* 0xc080000010077811 */
/* 0x000fe200078eb8ff */
/*09e0*/ UMOV UR4, 0x40800000 ; /* 0x4080000000047882 */
/* 0x000fe20000000000 */
/*09f0*/ IADD3 R9, R9, 0x81, -R16 ; /* 0x0000008109097810 */
/* 0x000fe20007ffe810 */
/*0a00*/ UIADD3 UR4, UR4, -0x1000000, URZ ; /* 0xff00000004047890 */
/* 0x000fe2000fffe03f */
/*0a10*/ BSSY B3, 0xd40 ; /* 0x0000032000037945 */
/* 0x000fe20003800000 */
/*0a20*/ IMAD.IADD R10, R10, 0x1, -R7 ; /* 0x000000010a0a7824 */
/* 0x000fc800078e0a07 */
/*0a30*/ MUFU.RCP R7, R10 ; /* 0x0000000a00077308 */
/* 0x000e220000001000 */
/*0a40*/ FADD.FTZ R12, -R10, -RZ ; /* 0x800000ff0a0c7221 */
/* 0x000fc80000010100 */
/*0a50*/ FFMA R14, R7, R12, 1 ; /* 0x3f800000070e7423 */
/* 0x001fc8000000000c */
/*0a60*/ FFMA R13, R7, R14, R7 ; /* 0x0000000e070d7223 */
/* 0x000fc80000000007 */
/*0a70*/ FFMA R7, R13, UR4, RZ ; /* 0x000000040d077c23 */
/* 0x000fc800080000ff */
/*0a80*/ FFMA R14, R12, R7, UR4 ; /* 0x000000040c0e7e23 */
/* 0x000fc80008000007 */
/*0a90*/ FFMA R14, R13, R14, R7 ; /* 0x0000000e0d0e7223 */
/* 0x000fc80000000007 */
/*0aa0*/ FFMA R12, R12, R14, UR4 ; /* 0x000000040c0c7e23 */
/* 0x000fc8000800000e */
/*0ab0*/ FFMA R7, R13, R12, R14 ; /* 0x0000000c0d077223 */
/* 0x000fca000000000e */
/*0ac0*/ SHF.R.U32.HI R10, RZ, 0x17, R7 ; /* 0x00000017ff0a7819 */
/* 0x000fc80000011607 */
/*0ad0*/ LOP3.LUT R10, R10, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff0a0a7812 */
/* 0x000fca00078ec0ff */
/*0ae0*/ IMAD.IADD R15, R10, 0x1, R9 ; /* 0x000000010a0f7824 */
/* 0x000fca00078e0209 */
/*0af0*/ IADD3 R10, R15, -0x1, RZ ; /* 0xffffffff0f0a7810 */
/* 0x000fc80007ffe0ff */
/*0b00*/ ISETP.GE.U32.AND P0, PT, R10, 0xfe, PT ; /* 0x000000fe0a00780c */
/* 0x000fda0003f06070 */
/*0b10*/ @!P0 BRA 0xd20 ; /* 0x0000020000008947 */
/* 0x000fea0003800000 */
/*0b20*/ ISETP.GT.AND P0, PT, R15, 0xfe, PT ; /* 0x000000fe0f00780c */
/* 0x000fda0003f04270 */
/*0b30*/ @P0 BRA 0xcf0 ; /* 0x000001b000000947 */
/* 0x000fea0003800000 */
/*0b40*/ ISETP.GE.AND P0, PT, R15, 0x1, PT ; /* 0x000000010f00780c */
/* 0x000fda0003f06270 */
/*0b50*/ @P0 BRA 0xd30 ; /* 0x000001d000000947 */
/* 0x000fea0003800000 */
/*0b60*/ ISETP.GE.AND P0, PT, R15, -0x18, PT ; /* 0xffffffe80f00780c */
/* 0x000fe40003f06270 */
/*0b70*/ LOP3.LUT R7, R7, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000007077812 */
/* 0x000fd600078ec0ff */
/*0b80*/ @!P0 BRA 0xd30 ; /* 0x000001a000008947 */
/* 0x000fea0003800000 */
/*0b90*/ FFMA.RZ R9, R13, R12.reuse, R14.reuse ; /* 0x0000000c0d097223 */
/* 0x180fe2000000c00e */
/*0ba0*/ ISETP.NE.AND P3, PT, R15, RZ, PT ; /* 0x000000ff0f00720c */
/* 0x000fe20003f65270 */
/*0bb0*/ FFMA.RM R10, R13, R12.reuse, R14.reuse ; /* 0x0000000c0d0a7223 */
/* 0x180fe2000000400e */
/*0bc0*/ ISETP.NE.AND P1, PT, R15, RZ, PT ; /* 0x000000ff0f00720c */
/* 0x000fe40003f25270 */
/*0bd0*/ LOP3.LUT R11, R9, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff090b7812 */
/* 0x000fe200078ec0ff */
/*0be0*/ FFMA.RP R9, R13, R12, R14 ; /* 0x0000000c0d097223 */
/* 0x000fe2000000800e */
/*0bf0*/ IADD3 R12, R15, 0x20, RZ ; /* 0x000000200f0c7810 */
/* 0x000fe20007ffe0ff */
/*0c00*/ IMAD.MOV R13, RZ, RZ, -R15 ; /* 0x000000ffff0d7224 */
/* 0x000fe200078e0a0f */
/*0c10*/ LOP3.LUT R11, R11, 0x800000, RZ, 0xfc, !PT ; /* 0x008000000b0b7812 */
/* 0x000fe400078efcff */
/*0c20*/ FSETP.NEU.FTZ.AND P0, PT, R9, R10, PT ; /* 0x0000000a0900720b */
/* 0x000fc40003f1d000 */
/*0c30*/ SHF.L.U32 R12, R11, R12, RZ ; /* 0x0000000c0b0c7219 */
/* 0x000fe400000006ff */
/*0c40*/ SEL R10, R13, RZ, P3 ; /* 0x000000ff0d0a7207 */
/* 0x000fe40001800000 */
/*0c50*/ ISETP.NE.AND P1, PT, R12, RZ, P1 ; /* 0x000000ff0c00720c */
/* 0x000fe40000f25270 */
/*0c60*/ SHF.R.U32.HI R10, RZ, R10, R11 ; /* 0x0000000aff0a7219 */
/* 0x000fe4000001160b */
/*0c70*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40000703570 */
/*0c80*/ SHF.R.U32.HI R12, RZ, 0x1, R10 ; /* 0x00000001ff0c7819 */
/* 0x000fc4000001160a */
/*0c90*/ SEL R9, RZ, 0x1, !P0 ; /* 0x00000001ff097807 */
/* 0x000fc80004000000 */
/*0ca0*/ LOP3.LUT R9, R9, 0x1, R12, 0xf8, !PT ; /* 0x0000000109097812 */
/* 0x000fc800078ef80c */
/*0cb0*/ LOP3.LUT R9, R9, R10, RZ, 0xc0, !PT ; /* 0x0000000a09097212 */
/* 0x000fca00078ec0ff */
/*0cc0*/ IMAD.IADD R12, R12, 0x1, R9 ; /* 0x000000010c0c7824 */
/* 0x000fca00078e0209 */
/*0cd0*/ LOP3.LUT R7, R12, R7, RZ, 0xfc, !PT ; /* 0x000000070c077212 */
/* 0x000fe200078efcff */
/*0ce0*/ BRA 0xd30 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*0cf0*/ LOP3.LUT R7, R7, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000007077812 */
/* 0x000fc800078ec0ff */
/*0d00*/ LOP3.LUT R7, R7, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000007077812 */
/* 0x000fe200078efcff */
/*0d10*/ BRA 0xd30 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0d20*/ IMAD R7, R9, 0x800000, R7 ; /* 0x0080000009077824 */
/* 0x000fe400078e0207 */
/*0d30*/ BSYNC B3 ; /* 0x0000000000037941 */
/* 0x000fea0003800000 */
/*0d40*/ BRA 0xdd0 ; /* 0x0000008000007947 */
/* 0x000fea0003800000 */
/*0d50*/ LOP3.LUT R7, R10, 0x80000000, R9, 0x48, !PT ; /* 0x800000000a077812 */
/* 0x000fc800078e4809 */
/*0d60*/ LOP3.LUT R7, R7, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000007077812 */
/* 0x000fe200078efcff */
/*0d70*/ BRA 0xdd0 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*0d80*/ LOP3.LUT R7, R10, 0x80000000, R9, 0x48, !PT ; /* 0x800000000a077812 */
/* 0x000fe200078e4809 */
/*0d90*/ BRA 0xdd0 ; /* 0x0000003000007947 */
/* 0x000fea0003800000 */
/*0da0*/ MUFU.RSQ R7, -QNAN ; /* 0xffc0000000077908 */
/* 0x000e220000001400 */
/*0db0*/ BRA 0xdd0 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0dc0*/ FADD.FTZ R7, R7, 4 ; /* 0x4080000007077421 */
/* 0x000fe40000010000 */
/*0dd0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0de0*/ IMAD.MOV.U32 R9, RZ, RZ, 0x0 ; /* 0x00000000ff097424 */
/* 0x000fc800078e00ff */
/*0df0*/ RET.REL.NODEC R8 0x0 ; /* 0xfffff20008007950 */
/* 0x000fea0003c3ffff */
/*0e00*/ BRA 0xe00; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0e10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ea0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0eb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ec0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ed0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ee0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ef0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
#define INTERVALS 1000000
// Max number of threads per block
#define THREADS 512
#define BLOCKS 64
double calculatePiCPU();
// Synchronous error checking call. Enable with nvcc -DDEBUG
__global__ void integrateOptimised(int *n, float *g_sum)
{
int idx = threadIdx.x + blockIdx.x * blockDim.x;
int tx = threadIdx.x;
// Shared memory to hold the sum for each block
__shared__ float s_sum[THREADS];
float sum = 0.0f;
float step = 1.0f / (float)*n;
for (int i = idx + 1; i <= *n; i += blockDim.x * BLOCKS)
{
float x = step * ((float)i - 0.5f);
sum += 4.0f / (1.0f+ x*x);
}
s_sum[tx] = sum * step;
// Wait for all threads to catch up
__syncthreads();
// For each block, do sum using shared memory
for (int i = blockDim.x / 2; i > 0; i >>= 1)
{
if (tx < i)
{
s_sum[tx] += s_sum[tx + i];
}
__syncthreads();
}
// Write results to global memory
g_sum[idx] = s_sum[tx];
} | .file "tmpxft_000fb078_00000000-6_integrateOptimised.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z40__device_stub__Z18integrateOptimisedPiPfPiPf
.type _Z40__device_stub__Z18integrateOptimisedPiPfPiPf, @function
_Z40__device_stub__Z18integrateOptimisedPiPfPiPf:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z18integrateOptimisedPiPf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z40__device_stub__Z18integrateOptimisedPiPfPiPf, .-_Z40__device_stub__Z18integrateOptimisedPiPfPiPf
.globl _Z18integrateOptimisedPiPf
.type _Z18integrateOptimisedPiPf, @function
_Z18integrateOptimisedPiPf:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z40__device_stub__Z18integrateOptimisedPiPfPiPf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z18integrateOptimisedPiPf, .-_Z18integrateOptimisedPiPf
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z18integrateOptimisedPiPf"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z18integrateOptimisedPiPf(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
#define INTERVALS 1000000
// Max number of threads per block
#define THREADS 512
#define BLOCKS 64
double calculatePiCPU();
// Synchronous error checking call. Enable with nvcc -DDEBUG
__global__ void integrateOptimised(int *n, float *g_sum)
{
int idx = threadIdx.x + blockIdx.x * blockDim.x;
int tx = threadIdx.x;
// Shared memory to hold the sum for each block
__shared__ float s_sum[THREADS];
float sum = 0.0f;
float step = 1.0f / (float)*n;
for (int i = idx + 1; i <= *n; i += blockDim.x * BLOCKS)
{
float x = step * ((float)i - 0.5f);
sum += 4.0f / (1.0f+ x*x);
}
s_sum[tx] = sum * step;
// Wait for all threads to catch up
__syncthreads();
// For each block, do sum using shared memory
for (int i = blockDim.x / 2; i > 0; i >>= 1)
{
if (tx < i)
{
s_sum[tx] += s_sum[tx + i];
}
__syncthreads();
}
// Write results to global memory
g_sum[idx] = s_sum[tx];
} | #include <hip/hip_runtime.h>
#include "includes.h"
#define INTERVALS 1000000
// Max number of threads per block
#define THREADS 512
#define BLOCKS 64
double calculatePiCPU();
// Synchronous error checking call. Enable with nvcc -DDEBUG
__global__ void integrateOptimised(int *n, float *g_sum)
{
int idx = threadIdx.x + blockIdx.x * blockDim.x;
int tx = threadIdx.x;
// Shared memory to hold the sum for each block
__shared__ float s_sum[THREADS];
float sum = 0.0f;
float step = 1.0f / (float)*n;
for (int i = idx + 1; i <= *n; i += blockDim.x * BLOCKS)
{
float x = step * ((float)i - 0.5f);
sum += 4.0f / (1.0f+ x*x);
}
s_sum[tx] = sum * step;
// Wait for all threads to catch up
__syncthreads();
// For each block, do sum using shared memory
for (int i = blockDim.x / 2; i > 0; i >>= 1)
{
if (tx < i)
{
s_sum[tx] += s_sum[tx + i];
}
__syncthreads();
}
// Write results to global memory
g_sum[idx] = s_sum[tx];
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
#define INTERVALS 1000000
// Max number of threads per block
#define THREADS 512
#define BLOCKS 64
double calculatePiCPU();
// Synchronous error checking call. Enable with nvcc -DDEBUG
__global__ void integrateOptimised(int *n, float *g_sum)
{
int idx = threadIdx.x + blockIdx.x * blockDim.x;
int tx = threadIdx.x;
// Shared memory to hold the sum for each block
__shared__ float s_sum[THREADS];
float sum = 0.0f;
float step = 1.0f / (float)*n;
for (int i = idx + 1; i <= *n; i += blockDim.x * BLOCKS)
{
float x = step * ((float)i - 0.5f);
sum += 4.0f / (1.0f+ x*x);
}
s_sum[tx] = sum * step;
// Wait for all threads to catch up
__syncthreads();
// For each block, do sum using shared memory
for (int i = blockDim.x / 2; i > 0; i >>= 1)
{
if (tx < i)
{
s_sum[tx] += s_sum[tx + i];
}
__syncthreads();
}
// Write results to global memory
g_sum[idx] = s_sum[tx];
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z18integrateOptimisedPiPf
.globl _Z18integrateOptimisedPiPf
.p2align 8
.type _Z18integrateOptimisedPiPf,@function
_Z18integrateOptimisedPiPf:
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x0
s_load_b32 s4, s[0:1], 0x1c
s_waitcnt lgkmcnt(0)
s_load_b32 s3, s[2:3], 0x0
s_and_b32 s2, s4, 0xffff
s_mov_b32 s4, exec_lo
s_waitcnt lgkmcnt(0)
v_cvt_f32_i32_e32 v3, s3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_div_scale_f32 v1, null, v3, v3, 1.0
v_div_scale_f32 v5, vcc_lo, 1.0, v3, 1.0
v_rcp_f32_e32 v4, v1
s_waitcnt_depctr 0xfff
v_fma_f32 v2, -v1, v4, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v4, v2, v4
v_mul_f32_e32 v6, v5, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v2, -v1, v6, v5
v_fmac_f32_e32 v6, v2, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_fma_f32 v5, -v1, v6, v5
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_div_fmas_f32 v2, v5, v4, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_div_fixup_f32 v2, v2, v3, 1.0
v_mov_b32_e32 v3, 0
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_4
v_dual_mov_b32 v3, 0 :: v_dual_add_nc_u32 v4, 1, v1
s_lshl_b32 s6, s2, 6
s_mov_b32 s5, 0
.p2align 6
.LBB0_2:
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_f32_i32_e32 v5, v4
v_dual_add_f32 v5, -0.5, v5 :: v_dual_add_nc_u32 v4, s6, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v5, v2, v5
v_fma_f32 v5, v5, v5, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_div_scale_f32 v6, null, v5, v5, 4.0
v_div_scale_f32 v9, vcc_lo, 4.0, v5, 4.0
v_rcp_f32_e32 v7, v6
s_waitcnt_depctr 0xfff
v_fma_f32 v8, -v6, v7, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v7, v8, v7
v_mul_f32_e32 v8, v9, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v10, -v6, v8, v9
v_fmac_f32_e32 v8, v10, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v6, -v6, v8, v9
v_div_fmas_f32 v6, v6, v7, v8
v_cmp_lt_i32_e32 vcc_lo, s3, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_div_fixup_f32 v5, v6, v5, 4.0
s_or_b32 s5, vcc_lo, s5
v_add_f32_e32 v3, v3, v5
s_and_not1_b32 exec_lo, exec_lo, s5
s_cbranch_execnz .LBB0_2
s_or_b32 exec_lo, exec_lo, s5
.LBB0_4:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_or_b32 exec_lo, exec_lo, s4
v_dual_mul_f32 v3, v2, v3 :: v_dual_lshlrev_b32 v2, 2, v0
s_cmp_lt_u32 s2, 2
ds_store_b32 v2, v3
s_waitcnt lgkmcnt(0)
s_barrier
s_branch .LBB0_6
.p2align 6
.LBB0_5:
s_or_b32 exec_lo, exec_lo, s4
s_waitcnt lgkmcnt(0)
s_barrier
s_cmp_lt_u32 s2, 4
s_mov_b32 s2, s3
.LBB0_6:
buffer_gl0_inv
s_cbranch_scc1 .LBB0_9
s_lshr_b32 s3, s2, 1
s_mov_b32 s4, exec_lo
v_cmpx_gt_u32_e64 s3, v0
s_cbranch_execz .LBB0_5
v_add_lshl_u32 v3, s3, v0, 2
ds_load_b32 v3, v3
ds_load_b32 v4, v2
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v3, v3, v4
ds_store_b32 v2, v3
s_branch .LBB0_5
.LBB0_9:
s_load_b64 s[0:1], s[0:1], 0x8
ds_load_b32 v3, v2
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v3, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z18integrateOptimisedPiPf
.amdhsa_group_segment_fixed_size 2048
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 11
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z18integrateOptimisedPiPf, .Lfunc_end0-_Z18integrateOptimisedPiPf
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 2048
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z18integrateOptimisedPiPf
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z18integrateOptimisedPiPf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 11
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
#define INTERVALS 1000000
// Max number of threads per block
#define THREADS 512
#define BLOCKS 64
double calculatePiCPU();
// Synchronous error checking call. Enable with nvcc -DDEBUG
__global__ void integrateOptimised(int *n, float *g_sum)
{
int idx = threadIdx.x + blockIdx.x * blockDim.x;
int tx = threadIdx.x;
// Shared memory to hold the sum for each block
__shared__ float s_sum[THREADS];
float sum = 0.0f;
float step = 1.0f / (float)*n;
for (int i = idx + 1; i <= *n; i += blockDim.x * BLOCKS)
{
float x = step * ((float)i - 0.5f);
sum += 4.0f / (1.0f+ x*x);
}
s_sum[tx] = sum * step;
// Wait for all threads to catch up
__syncthreads();
// For each block, do sum using shared memory
for (int i = blockDim.x / 2; i > 0; i >>= 1)
{
if (tx < i)
{
s_sum[tx] += s_sum[tx + i];
}
__syncthreads();
}
// Write results to global memory
g_sum[idx] = s_sum[tx];
} | .text
.file "integrateOptimised.hip"
.globl _Z33__device_stub__integrateOptimisedPiPf # -- Begin function _Z33__device_stub__integrateOptimisedPiPf
.p2align 4, 0x90
.type _Z33__device_stub__integrateOptimisedPiPf,@function
_Z33__device_stub__integrateOptimisedPiPf: # @_Z33__device_stub__integrateOptimisedPiPf
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z18integrateOptimisedPiPf, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z33__device_stub__integrateOptimisedPiPf, .Lfunc_end0-_Z33__device_stub__integrateOptimisedPiPf
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z18integrateOptimisedPiPf, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z18integrateOptimisedPiPf,@object # @_Z18integrateOptimisedPiPf
.section .rodata,"a",@progbits
.globl _Z18integrateOptimisedPiPf
.p2align 3, 0x0
_Z18integrateOptimisedPiPf:
.quad _Z33__device_stub__integrateOptimisedPiPf
.size _Z18integrateOptimisedPiPf, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z18integrateOptimisedPiPf"
.size .L__unnamed_1, 27
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z33__device_stub__integrateOptimisedPiPf
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z18integrateOptimisedPiPf
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z18integrateOptimisedPiPf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff047624 */
/* 0x000fe200078e00ff */
/*0020*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*0030*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff057624 */
/* 0x000fca00078e00ff */
/*0040*/ LDG.E R3, [R4.64] ; /* 0x0000000604037981 */
/* 0x000ea8000c1e1900 */
/*0050*/ S2R R7, SR_CTAID.X ; /* 0x0000000000077919 */
/* 0x000e280000002500 */
/*0060*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e220000002100 */
/*0070*/ I2F R6, R3 ; /* 0x0000000300067306 */
/* 0x004e640000201400 */
/*0080*/ IADD3 R2, R6, 0x1800000, RZ ; /* 0x0180000006027810 */
/* 0x002fc80007ffe0ff */
/*0090*/ LOP3.LUT R2, R2, 0x7f800000, RZ, 0xc0, !PT ; /* 0x7f80000002027812 */
/* 0x000fc800078ec0ff */
/*00a0*/ ISETP.GT.U32.AND P0, PT, R2, 0x1ffffff, PT ; /* 0x01ffffff0200780c */
/* 0x000fe20003f04070 */
/*00b0*/ IMAD R2, R7, c[0x0][0x0], R0 ; /* 0x0000000007027a24 */
/* 0x001fd800078e0200 */
/*00c0*/ @P0 BRA 0x110 ; /* 0x0000004000000947 */
/* 0x000fea0003800000 */
/*00d0*/ MOV R4, 0xf0 ; /* 0x000000f000047802 */
/* 0x000fe40000000f00 */
/*00e0*/ CALL.REL.NOINC 0x4c0 ; /* 0x000003d000007944 */
/* 0x000fea0003c00000 */
/*00f0*/ IMAD.MOV.U32 R4, RZ, RZ, R6 ; /* 0x000000ffff047224 */
/* 0x000fe200078e0006 */
/*0100*/ BRA 0x150 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*0110*/ MUFU.RCP R5, R6 ; /* 0x0000000600057308 */
/* 0x000e240000001000 */
/*0120*/ FFMA R4, R6, R5, -1 ; /* 0xbf80000006047423 */
/* 0x001fc80000000005 */
/*0130*/ FADD.FTZ R4, -R4, -RZ ; /* 0x800000ff04047221 */
/* 0x000fc80000010100 */
/*0140*/ FFMA R4, R5, R4, R5 ; /* 0x0000000405047223 */
/* 0x000fe40000000005 */
/*0150*/ ISETP.GE.AND P0, PT, R2, R3, PT ; /* 0x000000030200720c */
/* 0x000fe20003f06270 */
/*0160*/ BSSY B2, 0x340 ; /* 0x000001d000027945 */
/* 0x000fe20003800000 */
/*0170*/ IMAD.MOV.U32 R5, RZ, RZ, RZ ; /* 0x000000ffff057224 */
/* 0x000fd600078e00ff */
/*0180*/ @P0 BRA 0x330 ; /* 0x000001a000000947 */
/* 0x000fea0003800000 */
/*0190*/ IADD3 R6, R2, 0x1, RZ ; /* 0x0000000102067810 */
/* 0x000fe20007ffe0ff */
/*01a0*/ IMAD.MOV.U32 R5, RZ, RZ, RZ ; /* 0x000000ffff057224 */
/* 0x000fc600078e00ff */
/*01b0*/ I2F R7, R6 ; /* 0x0000000600077306 */
/* 0x0000620000201400 */
/*01c0*/ UMOV UR4, 0x40800000 ; /* 0x4080000000047882 */
/* 0x000fe20000000000 */
/*01d0*/ IMAD.MOV.U32 R9, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff097624 */
/* 0x000fe200078e00ff */
/*01e0*/ BSSY B1, 0x310 ; /* 0x0000012000017945 */
/* 0x000fe20003800000 */
/*01f0*/ IMAD.U32 R11, RZ, RZ, UR4 ; /* 0x00000004ff0b7e24 */
/* 0x000fe4000f8e00ff */
/*0200*/ IMAD R6, R9, 0x40, R6 ; /* 0x0000004009067824 */
/* 0x001fca00078e0206 */
/*0210*/ ISETP.GT.AND P2, PT, R6, R3, PT ; /* 0x000000030600720c */
/* 0x000fe20003f44270 */
/*0220*/ FADD R7, R7, -0.5 ; /* 0xbf00000007077421 */
/* 0x002fc80000000000 */
/*0230*/ FMUL R7, R7, R4 ; /* 0x0000000407077220 */
/* 0x000fc80000400000 */
/*0240*/ FFMA R10, R7, R7, 1 ; /* 0x3f800000070a7423 */
/* 0x000fc80000000007 */
/*0250*/ MUFU.RCP R7, R10 ; /* 0x0000000a00077308 */
/* 0x000e300000001000 */
/*0260*/ FCHK P0, R11, R10 ; /* 0x0000000a0b007302 */
/* 0x000e620000000000 */
/*0270*/ FFMA R8, -R10, R7, 1 ; /* 0x3f8000000a087423 */
/* 0x001fc80000000107 */
/*0280*/ FFMA R8, R7, R8, R7 ; /* 0x0000000807087223 */
/* 0x000fc80000000007 */
/*0290*/ FFMA R7, R8, 4, RZ ; /* 0x4080000008077823 */
/* 0x000fc800000000ff */
/*02a0*/ FFMA R9, -R10, R7, 4 ; /* 0x408000000a097423 */
/* 0x000fc80000000107 */
/*02b0*/ FFMA R8, R8, R9, R7 ; /* 0x0000000908087223 */
/* 0x000fe20000000007 */
/*02c0*/ @!P0 BRA 0x300 ; /* 0x0000003000008947 */
/* 0x002fea0003800000 */
/*02d0*/ MOV R8, 0x2f0 ; /* 0x000002f000087802 */
/* 0x000fe40000000f00 */
/*02e0*/ CALL.REL.NOINC 0x800 ; /* 0x0000051000007944 */
/* 0x000fea0003c00000 */
/*02f0*/ IMAD.MOV.U32 R8, RZ, RZ, R7 ; /* 0x000000ffff087224 */
/* 0x001fe400078e0007 */
/*0300*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0310*/ FADD R5, R8, R5 ; /* 0x0000000508057221 */
/* 0x000fe20000000000 */
/*0320*/ @!P2 BRA 0x1b0 ; /* 0xfffffe800000a947 */
/* 0x000fea000383ffff */
/*0330*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*0340*/ ULDC UR4, c[0x0][0x0] ; /* 0x0000000000047ab9 */
/* 0x000fe20000000800 */
/*0350*/ FMUL R5, R4, R5 ; /* 0x0000000504057220 */
/* 0x000fe20000400000 */
/*0360*/ USHF.R.U32.HI UR4, URZ, 0x1, UR4 ; /* 0x000000013f047899 */
/* 0x000fc80008011604 */
/*0370*/ STS [R0.X4], R5 ; /* 0x0000000500007388 */
/* 0x0001e80000004800 */
/*0380*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0390*/ ISETP.NE.AND P0, PT, RZ, UR4, PT ; /* 0x00000004ff007c0c */
/* 0x000fda000bf05270 */
/*03a0*/ @!P0 BRA 0x470 ; /* 0x000000c000008947 */
/* 0x000fea0003800000 */
/*03b0*/ IMAD.SHL.U32 R3, R0, 0x4, RZ ; /* 0x0000000400037824 */
/* 0x001fe400078e00ff */
/*03c0*/ IMAD.U32 R4, RZ, RZ, UR4 ; /* 0x00000004ff047e24 */
/* 0x000fca000f8e00ff */
/*03d0*/ ISETP.GE.AND P0, PT, R0, R4, PT ; /* 0x000000040000720c */
/* 0x000fda0003f06270 */
/*03e0*/ @!P0 IMAD R5, R4, 0x4, R3 ; /* 0x0000000404058824 */
/* 0x000fe200078e0203 */
/*03f0*/ @!P0 LDS R6, [R0.X4] ; /* 0x0000000000068984 */
/* 0x000fe20000004800 */
/*0400*/ SHF.R.U32.HI R4, RZ, 0x1, R4 ; /* 0x00000001ff047819 */
/* 0x000fc80000011604 */
/*0410*/ @!P0 LDS R5, [R5] ; /* 0x0000000005058984 */
/* 0x000e240000000800 */
/*0420*/ @!P0 FADD R7, R6, R5 ; /* 0x0000000506078221 */
/* 0x001fca0000000000 */
/*0430*/ @!P0 STS [R0.X4], R7 ; /* 0x0000000700008388 */
/* 0x0001e80000004800 */
/*0440*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0450*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fda0003f05270 */
/*0460*/ @P0 BRA 0x3d0 ; /* 0xffffff6000000947 */
/* 0x001fea000383ffff */
/*0470*/ LDS R5, [R0.X4] ; /* 0x0000000000057984 */
/* 0x001e220000004800 */
/*0480*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fc800078e00ff */
/*0490*/ IMAD.WIDE R2, R2, R3, c[0x0][0x168] ; /* 0x00005a0002027625 */
/* 0x000fca00078e0203 */
/*04a0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x001fe2000c101906 */
/*04b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*04c0*/ IMAD.SHL.U32 R5, R6, 0x2, RZ ; /* 0x0000000206057824 */
/* 0x000fca00078e00ff */
/*04d0*/ SHF.R.U32.HI R5, RZ, 0x18, R5 ; /* 0x00000018ff057819 */
/* 0x000fc80000011605 */
/*04e0*/ ISETP.NE.U32.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fda0003f05070 */
/*04f0*/ @P0 BRA 0x5b0 ; /* 0x000000b000000947 */
/* 0x000fea0003800000 */
/*0500*/ IMAD.SHL.U32 R5, R6, 0x2, RZ ; /* 0x0000000206057824 */
/* 0x000fca00078e00ff */
/*0510*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fda0003f05270 */
/*0520*/ @!P0 MUFU.RCP R5, R6 ; /* 0x0000000600058308 */
/* 0x0000620000001000 */
/*0530*/ @!P0 BRA 0x7d0 ; /* 0x0000029000008947 */
/* 0x000fea0003800000 */
/*0540*/ FFMA R6, R6, 1.84467440737095516160e+19, RZ ; /* 0x5f80000006067823 */
/* 0x001fc800000000ff */
/*0550*/ MUFU.RCP R5, R6 ; /* 0x0000000600057308 */
/* 0x002e240000001000 */
/*0560*/ FFMA R7, R6, R5, -1 ; /* 0xbf80000006077423 */
/* 0x001fc80000000005 */
/*0570*/ FADD.FTZ R8, -R7, -RZ ; /* 0x800000ff07087221 */
/* 0x000fc80000010100 */
/*0580*/ FFMA R5, R5, R8, R5 ; /* 0x0000000805057223 */
/* 0x000fc80000000005 */
/*0590*/ FFMA R5, R5, 1.84467440737095516160e+19, RZ ; /* 0x5f80000005057823 */
/* 0x000fe200000000ff */
/*05a0*/ BRA 0x7d0 ; /* 0x0000022000007947 */
/* 0x000fea0003800000 */
/*05b0*/ IADD3 R7, R5, -0xfd, RZ ; /* 0xffffff0305077810 */
/* 0x000fc80007ffe0ff */
/*05c0*/ ISETP.GT.U32.AND P0, PT, R7, 0x1, PT ; /* 0x000000010700780c */
/* 0x000fda0003f04070 */
/*05d0*/ @P0 BRA 0x7c0 ; /* 0x000001e000000947 */
/* 0x000fea0003800000 */
/*05e0*/ LOP3.LUT R8, R6, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff06087812 */
/* 0x000fe200078ec0ff */
/*05f0*/ IMAD.MOV.U32 R12, RZ, RZ, 0x3 ; /* 0x00000003ff0c7424 */
/* 0x000fe200078e00ff */
/*0600*/ IADD3 R5, R5, -0xfc, RZ ; /* 0xffffff0405057810 */
/* 0x000fe40007ffe0ff */
/*0610*/ LOP3.LUT R8, R8, 0x3f800000, RZ, 0xfc, !PT ; /* 0x3f80000008087812 */
/* 0x000fe400078efcff */
/*0620*/ SHF.L.U32 R13, R12, R7, RZ ; /* 0x000000070c0d7219 */
/* 0x000fe400000006ff */
/*0630*/ MUFU.RCP R9, R8 ; /* 0x0000000800097308 */
/* 0x000e240000001000 */
/*0640*/ FFMA R10, R8, R9, -1 ; /* 0xbf800000080a7423 */
/* 0x001fc80000000009 */
/*0650*/ FADD.FTZ R10, -R10, -RZ ; /* 0x800000ff0a0a7221 */
/* 0x000fc80000010100 */
/*0660*/ FFMA.RM R11, R9.reuse, R10.reuse, R9.reuse ; /* 0x0000000a090b7223 */
/* 0x1c0fe40000004009 */
/*0670*/ FFMA.RP R10, R9, R10, R9 ; /* 0x0000000a090a7223 */
/* 0x000fc60000008009 */
/*0680*/ LOP3.LUT R9, R11.reuse, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff0b097812 */
/* 0x040fe400078ec0ff */
/*0690*/ FSETP.NEU.FTZ.AND P0, PT, R11, R10, PT ; /* 0x0000000a0b00720b */
/* 0x000fe40003f1d000 */
/*06a0*/ LOP3.LUT R10, R9, 0x800000, RZ, 0xfc, !PT ; /* 0x00800000090a7812 */
/* 0x000fe400078efcff */
/*06b0*/ SEL R9, RZ, 0xffffffff, !P0 ; /* 0xffffffffff097807 */
/* 0x000fe40004000000 */
/*06c0*/ LOP3.LUT R8, R13, R10, RZ, 0xc0, !PT ; /* 0x0000000a0d087212 */
/* 0x000fe400078ec0ff */
/*06d0*/ SHF.R.U32.HI R5, RZ, R5, R10 ; /* 0x00000005ff057219 */
/* 0x000fe2000001160a */
/*06e0*/ IMAD.MOV R9, RZ, RZ, -R9 ; /* 0x000000ffff097224 */
/* 0x000fe200078e0a09 */
/*06f0*/ SHF.R.U32.HI R8, RZ, R7, R8 ; /* 0x00000007ff087219 */
/* 0x000fc80000011608 */
/*0700*/ LOP3.LUT P1, RZ, R9, R7, R10, 0xf8, !PT ; /* 0x0000000709ff7212 */
/* 0x000fe4000782f80a */
/*0710*/ LOP3.LUT P0, RZ, R8.reuse, 0x1, RZ, 0xc0, !PT ; /* 0x0000000108ff7812 */
/* 0x040fe4000780c0ff */
/*0720*/ LOP3.LUT P2, RZ, R8, 0x2, RZ, 0xc0, !PT ; /* 0x0000000208ff7812 */
/* 0x000fc8000784c0ff */
/*0730*/ PLOP3.LUT P0, PT, P0, P1, P2, 0xe0, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40000703c20 */
/*0740*/ LOP3.LUT P1, RZ, R6, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff06ff7812 */
/* 0x000fe4000782c0ff */
/*0750*/ SEL R7, RZ, 0x1, !P0 ; /* 0x00000001ff077807 */
/* 0x000fca0004000000 */
/*0760*/ IMAD.MOV R7, RZ, RZ, -R7 ; /* 0x000000ffff077224 */
/* 0x000fca00078e0a07 */
/*0770*/ ISETP.GE.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fda0003f06270 */
/*0780*/ @!P0 IADD3 R5, R5, 0x1, RZ ; /* 0x0000000105058810 */
/* 0x000fca0007ffe0ff */
/*0790*/ @!P1 IMAD.SHL.U32 R5, R5, 0x2, RZ ; /* 0x0000000205059824 */
/* 0x000fca00078e00ff */
/*07a0*/ LOP3.LUT R5, R5, 0x80000000, R6, 0xf8, !PT ; /* 0x8000000005057812 */
/* 0x000fe200078ef806 */
/*07b0*/ BRA 0x7d0 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*07c0*/ MUFU.RCP R5, R6 ; /* 0x0000000600057308 */
/* 0x0000640000001000 */
/*07d0*/ IMAD.MOV.U32 R6, RZ, RZ, R5 ; /* 0x000000ffff067224 */
/* 0x003fe400078e0005 */
/*07e0*/ IMAD.MOV.U32 R5, RZ, RZ, 0x0 ; /* 0x00000000ff057424 */
/* 0x000fc800078e00ff */
/*07f0*/ RET.REL.NODEC R4 0x0 ; /* 0xfffff80004007950 */
/* 0x000fea0003c3ffff */
/*0800*/ SHF.R.U32.HI R7, RZ, 0x17, R10 ; /* 0x00000017ff077819 */
/* 0x000fe2000001160a */
/*0810*/ BSSY B0, 0xde0 ; /* 0x000005c000007945 */
/* 0x000fe20003800000 */
/*0820*/ BSSY B3, 0x9d0 ; /* 0x000001a000037945 */
/* 0x000fe40003800000 */
/*0830*/ LOP3.LUT R16, R7, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff07107812 */
/* 0x000fc800078ec0ff */
/*0840*/ IADD3 R11, R16, -0x1, RZ ; /* 0xffffffff100b7810 */
/* 0x000fc80007ffe0ff */
/*0850*/ ISETP.GT.U32.AND P0, PT, R11, 0xfd, PT ; /* 0x000000fd0b00780c */
/* 0x000fda0003f04070 */
/*0860*/ @!P0 IMAD.MOV.U32 R9, RZ, RZ, RZ ; /* 0x000000ffff098224 */
/* 0x000fe200078e00ff */
/*0870*/ @!P0 BRA 0x9c0 ; /* 0x0000014000008947 */
/* 0x000fea0003800000 */
/*0880*/ FSETP.GTU.FTZ.AND P0, PT, |R10|, +INF , PT ; /* 0x7f8000000a00780b */
/* 0x000fe20003f1c200 */
/*0890*/ IMAD.MOV.U32 R7, RZ, RZ, R10 ; /* 0x000000ffff077224 */
/* 0x000fd800078e000a */
/*08a0*/ @P0 BREAK B3 ; /* 0x0000000000030942 */
/* 0x000fe20003800000 */
/*08b0*/ @P0 BRA 0xdc0 ; /* 0x0000050000000947 */
/* 0x000fea0003800000 */
/*08c0*/ IMAD.MOV.U32 R9, RZ, RZ, 0x40800000 ; /* 0x40800000ff097424 */
/* 0x000fca00078e00ff */
/*08d0*/ LOP3.LUT P0, RZ, R10, 0x7fffffff, R9, 0xc8, !PT ; /* 0x7fffffff0aff7812 */
/* 0x000fda000780c809 */
/*08e0*/ @!P0 BREAK B3 ; /* 0x0000000000038942 */
/* 0x000fe20003800000 */
/*08f0*/ @!P0 BRA 0xda0 ; /* 0x000004a000008947 */
/* 0x000fea0003800000 */
/*0900*/ FSETP.NEU.FTZ.AND P0, PT, |R7|, +INF , PT ; /* 0x7f8000000700780b */
/* 0x000fe40003f1d200 */
/*0910*/ LOP3.LUT P1, RZ, R9, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff09ff7812 */
/* 0x000fc8000782c0ff */
/*0920*/ PLOP3.LUT P0, PT, P0, P1, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000702572 */
/*0930*/ @P0 BREAK B3 ; /* 0x0000000000030942 */
/* 0x000fe20003800000 */
/*0940*/ @P0 BRA 0xd80 ; /* 0x0000043000000947 */
/* 0x000fea0003800000 */
/*0950*/ LOP3.LUT P0, RZ, R10, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff0aff7812 */
/* 0x000fda000780c0ff */
/*0960*/ @!P0 BREAK B3 ; /* 0x0000000000038942 */
/* 0x000fe20003800000 */
/*0970*/ @!P0 BRA 0xd50 ; /* 0x000003d000008947 */
/* 0x000fea0003800000 */
/*0980*/ ISETP.GE.AND P0, PT, R11, RZ, PT ; /* 0x000000ff0b00720c */
/* 0x000fe20003f06270 */
/*0990*/ IMAD.MOV.U32 R9, RZ, RZ, RZ ; /* 0x000000ffff097224 */
/* 0x000fd800078e00ff */
/*09a0*/ @!P0 FFMA R10, R7, 1.84467440737095516160e+19, RZ ; /* 0x5f800000070a8823 */
/* 0x000fe200000000ff */
/*09b0*/ @!P0 IADD3 R9, R9, 0x40, RZ ; /* 0x0000004009098810 */
/* 0x000fe40007ffe0ff */
/*09c0*/ BSYNC B3 ; /* 0x0000000000037941 */
/* 0x000fea0003800000 */
/*09d0*/ LEA R7, R16, 0xc0800000, 0x17 ; /* 0xc080000010077811 */
/* 0x000fe200078eb8ff */
/*09e0*/ UMOV UR4, 0x40800000 ; /* 0x4080000000047882 */
/* 0x000fe20000000000 */
/*09f0*/ IADD3 R9, R9, 0x81, -R16 ; /* 0x0000008109097810 */
/* 0x000fe20007ffe810 */
/*0a00*/ UIADD3 UR4, UR4, -0x1000000, URZ ; /* 0xff00000004047890 */
/* 0x000fe2000fffe03f */
/*0a10*/ BSSY B3, 0xd40 ; /* 0x0000032000037945 */
/* 0x000fe20003800000 */
/*0a20*/ IMAD.IADD R10, R10, 0x1, -R7 ; /* 0x000000010a0a7824 */
/* 0x000fc800078e0a07 */
/*0a30*/ MUFU.RCP R7, R10 ; /* 0x0000000a00077308 */
/* 0x000e220000001000 */
/*0a40*/ FADD.FTZ R12, -R10, -RZ ; /* 0x800000ff0a0c7221 */
/* 0x000fc80000010100 */
/*0a50*/ FFMA R14, R7, R12, 1 ; /* 0x3f800000070e7423 */
/* 0x001fc8000000000c */
/*0a60*/ FFMA R13, R7, R14, R7 ; /* 0x0000000e070d7223 */
/* 0x000fc80000000007 */
/*0a70*/ FFMA R7, R13, UR4, RZ ; /* 0x000000040d077c23 */
/* 0x000fc800080000ff */
/*0a80*/ FFMA R14, R12, R7, UR4 ; /* 0x000000040c0e7e23 */
/* 0x000fc80008000007 */
/*0a90*/ FFMA R14, R13, R14, R7 ; /* 0x0000000e0d0e7223 */
/* 0x000fc80000000007 */
/*0aa0*/ FFMA R12, R12, R14, UR4 ; /* 0x000000040c0c7e23 */
/* 0x000fc8000800000e */
/*0ab0*/ FFMA R7, R13, R12, R14 ; /* 0x0000000c0d077223 */
/* 0x000fca000000000e */
/*0ac0*/ SHF.R.U32.HI R10, RZ, 0x17, R7 ; /* 0x00000017ff0a7819 */
/* 0x000fc80000011607 */
/*0ad0*/ LOP3.LUT R10, R10, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff0a0a7812 */
/* 0x000fca00078ec0ff */
/*0ae0*/ IMAD.IADD R15, R10, 0x1, R9 ; /* 0x000000010a0f7824 */
/* 0x000fca00078e0209 */
/*0af0*/ IADD3 R10, R15, -0x1, RZ ; /* 0xffffffff0f0a7810 */
/* 0x000fc80007ffe0ff */
/*0b00*/ ISETP.GE.U32.AND P0, PT, R10, 0xfe, PT ; /* 0x000000fe0a00780c */
/* 0x000fda0003f06070 */
/*0b10*/ @!P0 BRA 0xd20 ; /* 0x0000020000008947 */
/* 0x000fea0003800000 */
/*0b20*/ ISETP.GT.AND P0, PT, R15, 0xfe, PT ; /* 0x000000fe0f00780c */
/* 0x000fda0003f04270 */
/*0b30*/ @P0 BRA 0xcf0 ; /* 0x000001b000000947 */
/* 0x000fea0003800000 */
/*0b40*/ ISETP.GE.AND P0, PT, R15, 0x1, PT ; /* 0x000000010f00780c */
/* 0x000fda0003f06270 */
/*0b50*/ @P0 BRA 0xd30 ; /* 0x000001d000000947 */
/* 0x000fea0003800000 */
/*0b60*/ ISETP.GE.AND P0, PT, R15, -0x18, PT ; /* 0xffffffe80f00780c */
/* 0x000fe40003f06270 */
/*0b70*/ LOP3.LUT R7, R7, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000007077812 */
/* 0x000fd600078ec0ff */
/*0b80*/ @!P0 BRA 0xd30 ; /* 0x000001a000008947 */
/* 0x000fea0003800000 */
/*0b90*/ FFMA.RZ R9, R13, R12.reuse, R14.reuse ; /* 0x0000000c0d097223 */
/* 0x180fe2000000c00e */
/*0ba0*/ ISETP.NE.AND P3, PT, R15, RZ, PT ; /* 0x000000ff0f00720c */
/* 0x000fe20003f65270 */
/*0bb0*/ FFMA.RM R10, R13, R12.reuse, R14.reuse ; /* 0x0000000c0d0a7223 */
/* 0x180fe2000000400e */
/*0bc0*/ ISETP.NE.AND P1, PT, R15, RZ, PT ; /* 0x000000ff0f00720c */
/* 0x000fe40003f25270 */
/*0bd0*/ LOP3.LUT R11, R9, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff090b7812 */
/* 0x000fe200078ec0ff */
/*0be0*/ FFMA.RP R9, R13, R12, R14 ; /* 0x0000000c0d097223 */
/* 0x000fe2000000800e */
/*0bf0*/ IADD3 R12, R15, 0x20, RZ ; /* 0x000000200f0c7810 */
/* 0x000fe20007ffe0ff */
/*0c00*/ IMAD.MOV R13, RZ, RZ, -R15 ; /* 0x000000ffff0d7224 */
/* 0x000fe200078e0a0f */
/*0c10*/ LOP3.LUT R11, R11, 0x800000, RZ, 0xfc, !PT ; /* 0x008000000b0b7812 */
/* 0x000fe400078efcff */
/*0c20*/ FSETP.NEU.FTZ.AND P0, PT, R9, R10, PT ; /* 0x0000000a0900720b */
/* 0x000fc40003f1d000 */
/*0c30*/ SHF.L.U32 R12, R11, R12, RZ ; /* 0x0000000c0b0c7219 */
/* 0x000fe400000006ff */
/*0c40*/ SEL R10, R13, RZ, P3 ; /* 0x000000ff0d0a7207 */
/* 0x000fe40001800000 */
/*0c50*/ ISETP.NE.AND P1, PT, R12, RZ, P1 ; /* 0x000000ff0c00720c */
/* 0x000fe40000f25270 */
/*0c60*/ SHF.R.U32.HI R10, RZ, R10, R11 ; /* 0x0000000aff0a7219 */
/* 0x000fe4000001160b */
/*0c70*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40000703570 */
/*0c80*/ SHF.R.U32.HI R12, RZ, 0x1, R10 ; /* 0x00000001ff0c7819 */
/* 0x000fc4000001160a */
/*0c90*/ SEL R9, RZ, 0x1, !P0 ; /* 0x00000001ff097807 */
/* 0x000fc80004000000 */
/*0ca0*/ LOP3.LUT R9, R9, 0x1, R12, 0xf8, !PT ; /* 0x0000000109097812 */
/* 0x000fc800078ef80c */
/*0cb0*/ LOP3.LUT R9, R9, R10, RZ, 0xc0, !PT ; /* 0x0000000a09097212 */
/* 0x000fca00078ec0ff */
/*0cc0*/ IMAD.IADD R12, R12, 0x1, R9 ; /* 0x000000010c0c7824 */
/* 0x000fca00078e0209 */
/*0cd0*/ LOP3.LUT R7, R12, R7, RZ, 0xfc, !PT ; /* 0x000000070c077212 */
/* 0x000fe200078efcff */
/*0ce0*/ BRA 0xd30 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*0cf0*/ LOP3.LUT R7, R7, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000007077812 */
/* 0x000fc800078ec0ff */
/*0d00*/ LOP3.LUT R7, R7, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000007077812 */
/* 0x000fe200078efcff */
/*0d10*/ BRA 0xd30 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0d20*/ IMAD R7, R9, 0x800000, R7 ; /* 0x0080000009077824 */
/* 0x000fe400078e0207 */
/*0d30*/ BSYNC B3 ; /* 0x0000000000037941 */
/* 0x000fea0003800000 */
/*0d40*/ BRA 0xdd0 ; /* 0x0000008000007947 */
/* 0x000fea0003800000 */
/*0d50*/ LOP3.LUT R7, R10, 0x80000000, R9, 0x48, !PT ; /* 0x800000000a077812 */
/* 0x000fc800078e4809 */
/*0d60*/ LOP3.LUT R7, R7, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000007077812 */
/* 0x000fe200078efcff */
/*0d70*/ BRA 0xdd0 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*0d80*/ LOP3.LUT R7, R10, 0x80000000, R9, 0x48, !PT ; /* 0x800000000a077812 */
/* 0x000fe200078e4809 */
/*0d90*/ BRA 0xdd0 ; /* 0x0000003000007947 */
/* 0x000fea0003800000 */
/*0da0*/ MUFU.RSQ R7, -QNAN ; /* 0xffc0000000077908 */
/* 0x000e220000001400 */
/*0db0*/ BRA 0xdd0 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0dc0*/ FADD.FTZ R7, R7, 4 ; /* 0x4080000007077421 */
/* 0x000fe40000010000 */
/*0dd0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0de0*/ IMAD.MOV.U32 R9, RZ, RZ, 0x0 ; /* 0x00000000ff097424 */
/* 0x000fc800078e00ff */
/*0df0*/ RET.REL.NODEC R8 0x0 ; /* 0xfffff20008007950 */
/* 0x000fea0003c3ffff */
/*0e00*/ BRA 0xe00; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0e10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ea0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0eb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ec0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ed0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ee0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ef0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z18integrateOptimisedPiPf
.globl _Z18integrateOptimisedPiPf
.p2align 8
.type _Z18integrateOptimisedPiPf,@function
_Z18integrateOptimisedPiPf:
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x0
s_load_b32 s4, s[0:1], 0x1c
s_waitcnt lgkmcnt(0)
s_load_b32 s3, s[2:3], 0x0
s_and_b32 s2, s4, 0xffff
s_mov_b32 s4, exec_lo
s_waitcnt lgkmcnt(0)
v_cvt_f32_i32_e32 v3, s3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_div_scale_f32 v1, null, v3, v3, 1.0
v_div_scale_f32 v5, vcc_lo, 1.0, v3, 1.0
v_rcp_f32_e32 v4, v1
s_waitcnt_depctr 0xfff
v_fma_f32 v2, -v1, v4, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v4, v2, v4
v_mul_f32_e32 v6, v5, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v2, -v1, v6, v5
v_fmac_f32_e32 v6, v2, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_fma_f32 v5, -v1, v6, v5
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_div_fmas_f32 v2, v5, v4, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_div_fixup_f32 v2, v2, v3, 1.0
v_mov_b32_e32 v3, 0
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_4
v_dual_mov_b32 v3, 0 :: v_dual_add_nc_u32 v4, 1, v1
s_lshl_b32 s6, s2, 6
s_mov_b32 s5, 0
.p2align 6
.LBB0_2:
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_f32_i32_e32 v5, v4
v_dual_add_f32 v5, -0.5, v5 :: v_dual_add_nc_u32 v4, s6, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v5, v2, v5
v_fma_f32 v5, v5, v5, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_div_scale_f32 v6, null, v5, v5, 4.0
v_div_scale_f32 v9, vcc_lo, 4.0, v5, 4.0
v_rcp_f32_e32 v7, v6
s_waitcnt_depctr 0xfff
v_fma_f32 v8, -v6, v7, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v7, v8, v7
v_mul_f32_e32 v8, v9, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v10, -v6, v8, v9
v_fmac_f32_e32 v8, v10, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v6, -v6, v8, v9
v_div_fmas_f32 v6, v6, v7, v8
v_cmp_lt_i32_e32 vcc_lo, s3, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_div_fixup_f32 v5, v6, v5, 4.0
s_or_b32 s5, vcc_lo, s5
v_add_f32_e32 v3, v3, v5
s_and_not1_b32 exec_lo, exec_lo, s5
s_cbranch_execnz .LBB0_2
s_or_b32 exec_lo, exec_lo, s5
.LBB0_4:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_or_b32 exec_lo, exec_lo, s4
v_dual_mul_f32 v3, v2, v3 :: v_dual_lshlrev_b32 v2, 2, v0
s_cmp_lt_u32 s2, 2
ds_store_b32 v2, v3
s_waitcnt lgkmcnt(0)
s_barrier
s_branch .LBB0_6
.p2align 6
.LBB0_5:
s_or_b32 exec_lo, exec_lo, s4
s_waitcnt lgkmcnt(0)
s_barrier
s_cmp_lt_u32 s2, 4
s_mov_b32 s2, s3
.LBB0_6:
buffer_gl0_inv
s_cbranch_scc1 .LBB0_9
s_lshr_b32 s3, s2, 1
s_mov_b32 s4, exec_lo
v_cmpx_gt_u32_e64 s3, v0
s_cbranch_execz .LBB0_5
v_add_lshl_u32 v3, s3, v0, 2
ds_load_b32 v3, v3
ds_load_b32 v4, v2
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v3, v3, v4
ds_store_b32 v2, v3
s_branch .LBB0_5
.LBB0_9:
s_load_b64 s[0:1], s[0:1], 0x8
ds_load_b32 v3, v2
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v3, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z18integrateOptimisedPiPf
.amdhsa_group_segment_fixed_size 2048
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 11
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z18integrateOptimisedPiPf, .Lfunc_end0-_Z18integrateOptimisedPiPf
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 2048
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z18integrateOptimisedPiPf
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z18integrateOptimisedPiPf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 11
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000fb078_00000000-6_integrateOptimised.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z40__device_stub__Z18integrateOptimisedPiPfPiPf
.type _Z40__device_stub__Z18integrateOptimisedPiPfPiPf, @function
_Z40__device_stub__Z18integrateOptimisedPiPfPiPf:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z18integrateOptimisedPiPf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z40__device_stub__Z18integrateOptimisedPiPfPiPf, .-_Z40__device_stub__Z18integrateOptimisedPiPfPiPf
.globl _Z18integrateOptimisedPiPf
.type _Z18integrateOptimisedPiPf, @function
_Z18integrateOptimisedPiPf:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z40__device_stub__Z18integrateOptimisedPiPfPiPf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z18integrateOptimisedPiPf, .-_Z18integrateOptimisedPiPf
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z18integrateOptimisedPiPf"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z18integrateOptimisedPiPf(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "integrateOptimised.hip"
.globl _Z33__device_stub__integrateOptimisedPiPf # -- Begin function _Z33__device_stub__integrateOptimisedPiPf
.p2align 4, 0x90
.type _Z33__device_stub__integrateOptimisedPiPf,@function
_Z33__device_stub__integrateOptimisedPiPf: # @_Z33__device_stub__integrateOptimisedPiPf
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z18integrateOptimisedPiPf, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z33__device_stub__integrateOptimisedPiPf, .Lfunc_end0-_Z33__device_stub__integrateOptimisedPiPf
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z18integrateOptimisedPiPf, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z18integrateOptimisedPiPf,@object # @_Z18integrateOptimisedPiPf
.section .rodata,"a",@progbits
.globl _Z18integrateOptimisedPiPf
.p2align 3, 0x0
_Z18integrateOptimisedPiPf:
.quad _Z33__device_stub__integrateOptimisedPiPf
.size _Z18integrateOptimisedPiPf, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z18integrateOptimisedPiPf"
.size .L__unnamed_1, 27
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z33__device_stub__integrateOptimisedPiPf
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z18integrateOptimisedPiPf
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #define SWAPS_PER_RUN 64
#define VL 64
extern "C"
__global__ void batch_sswap(int nswaps, int n, float *A, int lda, int *ipiv)
{
unsigned int tid = threadIdx.x + VL * blockIdx.x;
if( tid >= n ) return;
float *d_A = A + tid;
for (int i = 0; i < nswaps; i++)
{
int j = ipiv[i];
float temp = d_A[i*lda];
d_A[i*lda] = d_A[j*lda];
d_A[j*lda] = temp;
}
}
extern "C"
__global__ void batch_dswap(int nswaps, int n, double *A, int lda, int *ipiv)
{
unsigned int tid = threadIdx.x + blockDim.x * blockIdx.x;
if( tid >= n ) return;
double *d_A = A + tid;
for (int i = 0; i < nswaps; i++)
{
int j = ipiv[i];
double temp = d_A[i*lda];
d_A[i*lda] = d_A[j*lda];
d_A[j*lda] = temp;
}
} | code for sm_80
Function : batch_dswap
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x164], PT ; /* 0x0000590000007a0c */
/* 0x000fda0003f06070 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff027624 */
/* 0x000fca00078e00ff */
/*0070*/ ISETP.GE.AND P0, PT, R2, 0x1, PT ; /* 0x000000010200780c */
/* 0x000fda0003f06270 */
/*0080*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0090*/ IADD3 R3, R2.reuse, -0x1, RZ ; /* 0xffffffff02037810 */
/* 0x040fe20007ffe0ff */
/*00a0*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*00b0*/ LOP3.LUT R2, R2, 0x3, RZ, 0xc0, !PT ; /* 0x0000000302027812 */
/* 0x000fe200078ec0ff */
/*00c0*/ IMAD.MOV.U32 R5, RZ, RZ, RZ ; /* 0x000000ffff057224 */
/* 0x000fe200078e00ff */
/*00d0*/ ISETP.GE.U32.AND P1, PT, R3, 0x3, PT ; /* 0x000000030300780c */
/* 0x000fe40003f26070 */
/*00e0*/ ISETP.NE.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fd60003f05270 */
/*00f0*/ @!P1 BRA 0x590 ; /* 0x0000049000009947 */
/* 0x000fea0003800000 */
/*0100*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff047624 */
/* 0x000fe200078e00ff */
/*0110*/ LEA R8, P1, R0, c[0x0][0x168], 0x3 ; /* 0x00005a0000087a11 */
/* 0x000fe200078218ff */
/*0120*/ IMAD.MOV.U32 R5, RZ, RZ, RZ ; /* 0x000000ffff057224 */
/* 0x000fe200078e00ff */
/*0130*/ IADD3 R7, -R2, c[0x0][0x160], RZ ; /* 0x0000580002077a10 */
/* 0x000fe20007ffe1ff */
/*0140*/ IMAD.SHL.U32 R6, R4, 0x4, RZ ; /* 0x0000000404067824 */
/* 0x000fe200078e00ff */
/*0150*/ MOV R10, c[0x0][0x178] ; /* 0x00005e00000a7a02 */
/* 0x000fe20000000f00 */
/*0160*/ IMAD.MOV.U32 R11, RZ, RZ, c[0x0][0x17c] ; /* 0x00005f00ff0b7624 */
/* 0x000fe200078e00ff */
/*0170*/ LEA.HI.X R27, R0, c[0x0][0x16c], RZ, 0x3, P1 ; /* 0x00005b00001b7a11 */
/* 0x000fe200008f1cff */
/*0180*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*0190*/ SHF.R.S32.HI R3, RZ, 0x1f, R6 ; /* 0x0000001fff037819 */
/* 0x000fe20000011406 */
/*01a0*/ UMOV UR5, URZ ; /* 0x0000003f00057c82 */
/* 0x000fc40008000000 */
/*01b0*/ LDG.E R9, [R10.64] ; /* 0x000000060a097981 */
/* 0x000ea2000c1e1900 */
/*01c0*/ IMAD.MOV.U32 R16, RZ, RZ, R8 ; /* 0x000000ffff107224 */
/* 0x001fc400078e0008 */
/*01d0*/ IMAD.MOV.U32 R17, RZ, RZ, R27 ; /* 0x000000ffff117224 */
/* 0x000fca00078e001b */
/*01e0*/ LDG.E.64 R20, [R16.64] ; /* 0x0000000610147981 */
/* 0x000ee2000c1e1b00 */
/*01f0*/ IMAD R9, R9, c[0x0][0x170], RZ ; /* 0x00005c0009097a24 */
/* 0x004fca00078e02ff */
/*0200*/ IADD3 R12, P1, R0, R9, RZ ; /* 0x00000009000c7210 */
/* 0x000fc80007f3e0ff */
/*0210*/ LEA.HI.X.SX32 R9, R9, RZ, 0x1, P1 ; /* 0x000000ff09097211 */
/* 0x000fe400008f0eff */
/*0220*/ LEA R18, P1, R12, c[0x0][0x168], 0x3 ; /* 0x00005a000c127a11 */
/* 0x000fc800078218ff */
/*0230*/ LEA.HI.X R19, R12, c[0x0][0x16c], R9, 0x3, P1 ; /* 0x00005b000c137a11 */
/* 0x000fca00008f1c09 */
/*0240*/ LDG.E.64 R14, [R18.64] ; /* 0x00000006120e7981 */
/* 0x000ea2000c1e1b00 */
/*0250*/ IADD3 R26, P1, RZ, -R6, RZ ; /* 0x80000006ff1a7210 */
/* 0x000fc60007f3e0ff */
/*0260*/ STG.E.64 [R16.64], R14 ; /* 0x0000000e10007986 */
/* 0x0041e8000c101b06 */
/*0270*/ STG.E.64 [R18.64], R20 ; /* 0x0000001412007986 */
/* 0x0083e8000c101b06 */
/*0280*/ LDG.E R12, [R10.64+0x4] ; /* 0x000004060a0c7981 */
/* 0x000ea2000c1e1900 */
/*0290*/ IMAD.X R9, RZ, RZ, ~R3, P1 ; /* 0x000000ffff097224 */
/* 0x000fc800008e0e03 */
/*02a0*/ IMAD R9, R9, UR4, RZ ; /* 0x0000000409097c24 */
/* 0x000fc8000f8e02ff */
/*02b0*/ IMAD R9, R26, UR5, R9 ; /* 0x000000051a097c24 */
/* 0x000fe4000f8e0209 */
/*02c0*/ IMAD R12, R12, c[0x0][0x170], RZ ; /* 0x00005c000c0c7a24 */
/* 0x004fca00078e02ff */
/*02d0*/ SHF.R.S32.HI R13, RZ, 0x1f, R12 ; /* 0x0000001fff0d7819 */
/* 0x000fca000001140c */
/*02e0*/ IMAD.WIDE.U32 R12, R26, UR4, R12 ; /* 0x000000041a0c7c25 */
/* 0x000fc8000f8e000c */
/*02f0*/ IMAD.IADD R13, R13, 0x1, R9 ; /* 0x000000010d0d7824 */
/* 0x000fe200078e0209 */
/*0300*/ LEA R14, P1, R12, R8, 0x3 ; /* 0x000000080c0e7211 */
/* 0x001fc800078218ff */
/*0310*/ LEA.HI.X R15, R12, R27, R13, 0x3, P1 ; /* 0x0000001b0c0f7211 */
/* 0x000fe200008f1c0d */
/*0320*/ IMAD.WIDE R12, R4, 0x8, R16 ; /* 0x00000008040c7825 */
/* 0x000fc800078e0210 */
/*0330*/ LDG.E.64 R16, [R14.64] ; /* 0x000000060e107981 */
/* 0x000ea8000c1e1b00 */
/*0340*/ LDG.E.64 R18, [R12.64] ; /* 0x000000060c127981 */
/* 0x002ee8000c1e1b00 */
/*0350*/ STG.E.64 [R12.64], R16 ; /* 0x000000100c007986 */
/* 0x0041e8000c101b06 */
/*0360*/ STG.E.64 [R14.64], R18 ; /* 0x000000120e007986 */
/* 0x0083e8000c101b06 */
/*0370*/ LDG.E R22, [R10.64+0x8] ; /* 0x000008060a167981 */
/* 0x000ea4000c1e1900 */
/*0380*/ IMAD R22, R22, c[0x0][0x170], RZ ; /* 0x00005c0016167a24 */
/* 0x004fca00078e02ff */
/*0390*/ SHF.R.S32.HI R23, RZ, 0x1f, R22 ; /* 0x0000001fff177819 */
/* 0x000fca0000011416 */
/*03a0*/ IMAD.WIDE.U32 R22, R26, UR4, R22 ; /* 0x000000041a167c25 */
/* 0x000fca000f8e0016 */
/*03b0*/ IADD3 R21, R9, R23, RZ ; /* 0x0000001709157210 */
/* 0x000fe40007ffe0ff */
/*03c0*/ LEA R20, P1, R22, R8, 0x3 ; /* 0x0000000816147211 */
/* 0x000fc800078218ff */
/*03d0*/ LEA.HI.X R21, R22, R27, R21, 0x3, P1 ; /* 0x0000001b16157211 */
/* 0x000fe200008f1c15 */
/*03e0*/ IMAD.WIDE R22, R4, 0x8, R12 ; /* 0x0000000804167825 */
/* 0x000fc800078e020c */
/*03f0*/ LDG.E.64 R24, [R20.64] ; /* 0x0000000614187981 */
/* 0x000ea8000c1e1b00 */
/*0400*/ LDG.E.64 R12, [R22.64] ; /* 0x00000006160c7981 */
/* 0x001ee8000c1e1b00 */
/*0410*/ STG.E.64 [R22.64], R24 ; /* 0x0000001816007986 */
/* 0x0041e8000c101b06 */
/*0420*/ STG.E.64 [R20.64], R12 ; /* 0x0000000c14007986 */
/* 0x0081e8000c101b06 */
/*0430*/ LDG.E R16, [R10.64+0xc] ; /* 0x00000c060a107981 */
/* 0x000ea4000c1e1900 */
/*0440*/ IMAD R16, R16, c[0x0][0x170], RZ ; /* 0x00005c0010107a24 */
/* 0x004fca00078e02ff */
/*0450*/ SHF.R.S32.HI R17, RZ, 0x1f, R16 ; /* 0x0000001fff117819 */
/* 0x000fca0000011410 */
/*0460*/ IMAD.WIDE.U32 R16, R26, UR4, R16 ; /* 0x000000041a107c25 */
/* 0x000fc8000f8e0010 */
/*0470*/ IMAD.IADD R9, R9, 0x1, R17 ; /* 0x0000000109097824 */
/* 0x000fe200078e0211 */
/*0480*/ LEA R14, P1, R16, R8, 0x3 ; /* 0x00000008100e7211 */
/* 0x002fc800078218ff */
/*0490*/ LEA.HI.X R15, R16, R27, R9, 0x3, P1 ; /* 0x0000001b100f7211 */
/* 0x000fe200008f1c09 */
/*04a0*/ IMAD.WIDE R16, R4, 0x8, R22 ; /* 0x0000000804107825 */
/* 0x000fc800078e0216 */
/*04b0*/ LDG.E.64 R28, [R14.64] ; /* 0x000000060e1c7981 */
/* 0x000ea8000c1e1b00 */
/*04c0*/ LDG.E.64 R18, [R16.64] ; /* 0x0000000610127981 */
/* 0x000ee2000c1e1b00 */
/*04d0*/ IADD3 R7, R7, -0x4, RZ ; /* 0xfffffffc07077810 */
/* 0x000fc80007ffe0ff */
/*04e0*/ ISETP.NE.AND P1, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fe20003f25270 */
/*04f0*/ UIADD3 UR4, UP0, UR4, 0x1, URZ ; /* 0x0000000104047890 */
/* 0x000fe2000ff1e03f */
/*0500*/ IADD3 R10, P2, R10, 0x10, RZ ; /* 0x000000100a0a7810 */
/* 0x000fe20007f5e0ff */
/*0510*/ IMAD.WIDE R8, R4, 0x8, R16 ; /* 0x0000000804087825 */
/* 0x000fe400078e0210 */
/*0520*/ UIADD3.X UR5, URZ, UR5, URZ, UP0, !UPT ; /* 0x000000053f057290 */
/* 0x000fe200087fe43f */
/*0530*/ IADD3 R5, R5, 0x4, RZ ; /* 0x0000000405057810 */
/* 0x000fe20007ffe0ff */
/*0540*/ IMAD.X R11, RZ, RZ, R11, P2 ; /* 0x000000ffff0b7224 */
/* 0x000fe400010e060b */
/*0550*/ IMAD.MOV.U32 R27, RZ, RZ, R9 ; /* 0x000000ffff1b7224 */
/* 0x000fe200078e0009 */
/*0560*/ STG.E.64 [R16.64], R28 ; /* 0x0000001c10007986 */
/* 0x0041e8000c101b06 */
/*0570*/ STG.E.64 [R14.64], R18 ; /* 0x000000120e007986 */
/* 0x0081e2000c101b06 */
/*0580*/ @P1 BRA 0x1b0 ; /* 0xfffffc2000001947 */
/* 0x000fea000383ffff */
/*0590*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*05a0*/ IMAD R3, R5, c[0x0][0x170], RZ ; /* 0x00005c0005037a24 */
/* 0x000fe400078e02ff */
/*05b0*/ IMAD.MOV.U32 R4, RZ, RZ, 0x4 ; /* 0x00000004ff047424 */
/* 0x000fc600078e00ff */
/*05c0*/ IADD3 R17, P0, R0, R3, RZ ; /* 0x0000000300117210 */
/* 0x001fe20007f1e0ff */
/*05d0*/ IMAD.WIDE R4, R5, R4, c[0x0][0x178] ; /* 0x00005e0005047625 */
/* 0x000fc600078e0204 */
/*05e0*/ LEA R16, P1, R17, c[0x0][0x168], 0x3 ; /* 0x00005a0011107a11 */
/* 0x000fe200078218ff */
/*05f0*/ IMAD.MOV.U32 R14, RZ, RZ, R4 ; /* 0x000000ffff0e7224 */
/* 0x000fe200078e0004 */
/*0600*/ LEA.HI.X.SX32 R6, R3, RZ, 0x1, P0 ; /* 0x000000ff03067211 */
/* 0x000fe400000f0eff */
/*0610*/ MOV R15, R5 ; /* 0x00000005000f7202 */
/* 0x000fe40000000f00 */
/*0620*/ LEA.HI.X R17, R17, c[0x0][0x16c], R6, 0x3, P1 ; /* 0x00005b0011117a11 */
/* 0x000fe400008f1c06 */
/*0630*/ IMAD.MOV.U32 R10, RZ, RZ, R14 ; /* 0x000000ffff0a7224 */
/* 0x000fe400078e000e */
/*0640*/ IMAD.MOV.U32 R11, RZ, RZ, R15 ; /* 0x000000ffff0b7224 */
/* 0x000fca00078e000f */
/*0650*/ LDG.E R3, [R10.64] ; /* 0x000000060a037981 */
/* 0x000ea2000c1e1900 */
/*0660*/ IMAD.MOV.U32 R12, RZ, RZ, R16 ; /* 0x000000ffff0c7224 */
/* 0x001fe400078e0010 */
/*0670*/ IMAD.MOV.U32 R13, RZ, RZ, R17 ; /* 0x000000ffff0d7224 */
/* 0x000fe400078e0011 */
/*0680*/ IMAD R3, R3, c[0x0][0x170], RZ ; /* 0x00005c0003037a24 */
/* 0x004fca00078e02ff */
/*0690*/ IADD3 R4, P0, R0, R3, RZ ; /* 0x0000000300047210 */
/* 0x000fc80007f1e0ff */
/*06a0*/ LEA.HI.X.SX32 R3, R3, RZ, 0x1, P0 ; /* 0x000000ff03037211 */
/* 0x000fe400000f0eff */
/*06b0*/ LEA R6, P0, R4, c[0x0][0x168], 0x3 ; /* 0x00005a0004067a11 */
/* 0x000fc800078018ff */
/*06c0*/ LEA.HI.X R7, R4, c[0x0][0x16c], R3, 0x3, P0 ; /* 0x00005b0004077a11 */
/* 0x000fe400000f1c03 */
/*06d0*/ LDG.E.64 R4, [R12.64] ; /* 0x000000060c047981 */
/* 0x000ea8000c1e1b00 */
/*06e0*/ LDG.E.64 R8, [R6.64] ; /* 0x0000000606087981 */
/* 0x000ee2000c1e1b00 */
/*06f0*/ IADD3 R2, R2, -0x1, RZ ; /* 0xffffffff02027810 */
/* 0x000fc80007ffe0ff */
/*0700*/ ISETP.NE.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fe40003f05270 */
/*0710*/ MOV R11, c[0x0][0x170] ; /* 0x00005c00000b7a02 */
/* 0x000fe40000000f00 */
/*0720*/ IADD3 R14, P1, R14, 0x4, RZ ; /* 0x000000040e0e7810 */
/* 0x000fc60007f3e0ff */
/*0730*/ IMAD.WIDE R10, R11, 0x8, R12 ; /* 0x000000080b0a7825 */
/* 0x000fc800078e020c */
/*0740*/ IMAD.MOV.U32 R16, RZ, RZ, R10 ; /* 0x000000ffff107224 */
/* 0x000fe400078e000a */
/*0750*/ IMAD.MOV.U32 R17, RZ, RZ, R11 ; /* 0x000000ffff117224 */
/* 0x000fe400078e000b */
/*0760*/ IMAD.X R15, RZ, RZ, R15, P1 ; /* 0x000000ffff0f7224 */
/* 0x000fe200008e060f */
/*0770*/ STG.E.64 [R12.64], R8 ; /* 0x000000080c007986 */
/* 0x0081e8000c101b06 */
/*0780*/ STG.E.64 [R6.64], R4 ; /* 0x0000000406007986 */
/* 0x0041e2000c101b06 */
/*0790*/ @P0 BRA 0x630 ; /* 0xfffffe9000000947 */
/* 0x000fea000383ffff */
/*07a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*07b0*/ BRA 0x7b0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*07c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0800*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0810*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0820*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0830*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0840*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0850*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0860*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0870*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : batch_sswap
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, 0x40, R3 ; /* 0x0000004000007824 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x164], PT ; /* 0x0000590000007a0c */
/* 0x000fda0003f06070 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ IMAD.MOV.U32 R12, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff0c7624 */
/* 0x000fca00078e00ff */
/*0070*/ ISETP.GE.AND P0, PT, R12, 0x1, PT ; /* 0x000000010c00780c */
/* 0x000fda0003f06270 */
/*0080*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0090*/ IADD3 R2, R12.reuse, -0x1, RZ ; /* 0xffffffff0c027810 */
/* 0x040fe20007ffe0ff */
/*00a0*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*00b0*/ LOP3.LUT R12, R12, 0x3, RZ, 0xc0, !PT ; /* 0x000000030c0c7812 */
/* 0x000fe200078ec0ff */
/*00c0*/ IMAD.MOV.U32 R14, RZ, RZ, RZ ; /* 0x000000ffff0e7224 */
/* 0x000fe200078e00ff */
/*00d0*/ ISETP.GE.U32.AND P1, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fe40003f26070 */
/*00e0*/ ISETP.NE.AND P0, PT, R12, RZ, PT ; /* 0x000000ff0c00720c */
/* 0x000fd60003f05270 */
/*00f0*/ @!P1 BRA 0x580 ; /* 0x0000048000009947 */
/* 0x000fea0003800000 */
/*0100*/ IMAD.MOV.U32 R13, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff0d7624 */
/* 0x000fe200078e00ff */
/*0110*/ LEA R16, P1, R0, c[0x0][0x168], 0x2 ; /* 0x00005a0000107a11 */
/* 0x000fe200078210ff */
/*0120*/ IMAD.MOV.U32 R14, RZ, RZ, RZ ; /* 0x000000ffff0e7224 */
/* 0x000fe200078e00ff */
/*0130*/ IADD3 R15, -R12, c[0x0][0x160], RZ ; /* 0x000058000c0f7a10 */
/* 0x000fe20007ffe1ff */
/*0140*/ IMAD.SHL.U32 R21, R13, 0x4, RZ ; /* 0x000000040d157824 */
/* 0x000fe200078e00ff */
/*0150*/ MOV R3, c[0x0][0x17c] ; /* 0x00005f0000037a02 */
/* 0x000fe20000000f00 */
/*0160*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x178] ; /* 0x00005e00ff027624 */
/* 0x000fe200078e00ff */
/*0170*/ LEA.HI.X R17, R0, c[0x0][0x16c], RZ, 0x2, P1 ; /* 0x00005b0000117a11 */
/* 0x000fe200008f14ff */
/*0180*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*0190*/ SHF.R.S32.HI R20, RZ, 0x1f, R21 ; /* 0x0000001fff147819 */
/* 0x000fe20000011415 */
/*01a0*/ UMOV UR5, URZ ; /* 0x0000003f00057c82 */
/* 0x000fc40008000000 */
/*01b0*/ LDG.E R4, [R2.64] ; /* 0x0000000602047981 */
/* 0x004ea2000c1e1900 */
/*01c0*/ IMAD.MOV.U32 R6, RZ, RZ, R16 ; /* 0x000000ffff067224 */
/* 0x000fc400078e0010 */
/*01d0*/ IMAD.MOV.U32 R7, RZ, RZ, R17 ; /* 0x000000ffff077224 */
/* 0x000fca00078e0011 */
/*01e0*/ LDG.E R23, [R6.64] ; /* 0x0000000606177981 */
/* 0x000ee2000c1e1900 */
/*01f0*/ IMAD R5, R4, c[0x0][0x170], RZ ; /* 0x00005c0004057a24 */
/* 0x004fca00078e02ff */
/*0200*/ IADD3 R4, P1, R0, R5, RZ ; /* 0x0000000500047210 */
/* 0x000fc80007f3e0ff */
/*0210*/ LEA.HI.X.SX32 R5, R5, RZ, 0x1, P1 ; /* 0x000000ff05057211 */
/* 0x000fe400008f0eff */
/*0220*/ LEA R10, P1, R4, c[0x0][0x168], 0x2 ; /* 0x00005a00040a7a11 */
/* 0x000fc800078210ff */
/*0230*/ LEA.HI.X R11, R4, c[0x0][0x16c], R5, 0x2, P1 ; /* 0x00005b00040b7a11 */
/* 0x000fca00008f1405 */
/*0240*/ LDG.E R5, [R10.64] ; /* 0x000000060a057981 */
/* 0x000ea2000c1e1900 */
/*0250*/ IADD3 R18, P1, RZ, -R21, RZ ; /* 0x80000015ff127210 */
/* 0x000fc60007f3e0ff */
/*0260*/ STG.E [R6.64], R5 ; /* 0x0000000506007986 */
/* 0x0041e8000c101906 */
/*0270*/ STG.E [R10.64], R23 ; /* 0x000000170a007986 */
/* 0x0083e8000c101906 */
/*0280*/ LDG.E R8, [R2.64+0x4] ; /* 0x0000040602087981 */
/* 0x000ea2000c1e1900 */
/*0290*/ IMAD.X R19, RZ, RZ, ~R20, P1 ; /* 0x000000ffff137224 */
/* 0x000fc800008e0e14 */
/*02a0*/ IMAD R19, R19, UR4, RZ ; /* 0x0000000413137c24 */
/* 0x000fc8000f8e02ff */
/*02b0*/ IMAD R19, R18, UR5, R19 ; /* 0x0000000512137c24 */
/* 0x000fe4000f8e0213 */
/*02c0*/ IMAD.WIDE R6, R13, 0x4, R6 ; /* 0x000000040d067825 */
/* 0x001fca00078e0206 */
/*02d0*/ LDG.E R23, [R6.64] ; /* 0x0000000606177981 */
/* 0x002ee2000c1e1900 */
/*02e0*/ IMAD R8, R8, c[0x0][0x170], RZ ; /* 0x00005c0008087a24 */
/* 0x004fca00078e02ff */
/*02f0*/ SHF.R.S32.HI R9, RZ, 0x1f, R8 ; /* 0x0000001fff097819 */
/* 0x000fca0000011408 */
/*0300*/ IMAD.WIDE.U32 R8, R18, UR4, R8 ; /* 0x0000000412087c25 */
/* 0x000fc8000f8e0008 */
/*0310*/ IMAD.IADD R9, R9, 0x1, R19 ; /* 0x0000000109097824 */
/* 0x000fe200078e0213 */
/*0320*/ LEA R4, P1, R8, R16, 0x2 ; /* 0x0000001008047211 */
/* 0x000fc800078210ff */
/*0330*/ LEA.HI.X R5, R8, R17, R9, 0x2, P1 ; /* 0x0000001108057211 */
/* 0x000fca00008f1409 */
/*0340*/ LDG.E R25, [R4.64] ; /* 0x0000000604197981 */
/* 0x000ea8000c1e1900 */
/*0350*/ STG.E [R6.64], R25 ; /* 0x0000001906007986 */
/* 0x0041e8000c101906 */
/*0360*/ STG.E [R4.64], R23 ; /* 0x0000001704007986 */
/* 0x0083e8000c101906 */
/*0370*/ LDG.E R10, [R2.64+0x8] ; /* 0x00000806020a7981 */
/* 0x000ea4000c1e1900 */
/*0380*/ IMAD R10, R10, c[0x0][0x170], RZ ; /* 0x00005c000a0a7a24 */
/* 0x004fca00078e02ff */
/*0390*/ SHF.R.S32.HI R11, RZ, 0x1f, R10 ; /* 0x0000001fff0b7819 */
/* 0x000fca000001140a */
/*03a0*/ IMAD.WIDE.U32 R10, R18, UR4, R10 ; /* 0x00000004120a7c25 */
/* 0x000fc8000f8e000a */
/*03b0*/ IMAD.IADD R9, R19, 0x1, R11 ; /* 0x0000000113097824 */
/* 0x000fe200078e020b */
/*03c0*/ LEA R8, P1, R10, R16, 0x2 ; /* 0x000000100a087211 */
/* 0x000fc800078210ff */
/*03d0*/ LEA.HI.X R9, R10, R17, R9, 0x2, P1 ; /* 0x000000110a097211 */
/* 0x000fe200008f1409 */
/*03e0*/ IMAD.WIDE R10, R13, 0x4, R6 ; /* 0x000000040d0a7825 */
/* 0x000fc800078e0206 */
/*03f0*/ LDG.E R27, [R8.64] ; /* 0x00000006081b7981 */
/* 0x000ea8000c1e1900 */
/*0400*/ LDG.E R25, [R10.64] ; /* 0x000000060a197981 */
/* 0x001ee8000c1e1900 */
/*0410*/ STG.E [R10.64], R27 ; /* 0x0000001b0a007986 */
/* 0x0041e8000c101906 */
/*0420*/ STG.E [R8.64], R25 ; /* 0x0000001908007986 */
/* 0x0085e8000c101906 */
/*0430*/ LDG.E R6, [R2.64+0xc] ; /* 0x00000c0602067981 */
/* 0x000ee4000c1e1900 */
/*0440*/ IMAD R6, R6, c[0x0][0x170], RZ ; /* 0x00005c0006067a24 */
/* 0x008fca00078e02ff */
/*0450*/ SHF.R.S32.HI R7, RZ, 0x1f, R6 ; /* 0x0000001fff077819 */
/* 0x000fca0000011406 */
/*0460*/ IMAD.WIDE.U32 R6, R18, UR4, R6 ; /* 0x0000000412067c25 */
/* 0x000fca000f8e0006 */
/*0470*/ IADD3 R19, R19, R7, RZ ; /* 0x0000000713137210 */
/* 0x000fe40007ffe0ff */
/*0480*/ LEA R4, P1, R6, R16, 0x2 ; /* 0x0000001006047211 */
/* 0x002fc800078210ff */
/*0490*/ LEA.HI.X R5, R6, R17, R19, 0x2, P1 ; /* 0x0000001106057211 */
/* 0x000fe200008f1413 */
/*04a0*/ IMAD.WIDE R6, R13, 0x4, R10 ; /* 0x000000040d067825 */
/* 0x000fc800078e020a */
/*04b0*/ LDG.E R19, [R4.64] ; /* 0x0000000604137981 */
/* 0x000ee8000c1e1900 */
/*04c0*/ LDG.E R11, [R6.64] ; /* 0x00000006060b7981 */
/* 0x001f22000c1e1900 */
/*04d0*/ IADD3 R15, R15, -0x4, RZ ; /* 0xfffffffc0f0f7810 */
/* 0x000fc80007ffe0ff */
/*04e0*/ ISETP.NE.AND P1, PT, R15, RZ, PT ; /* 0x000000ff0f00720c */
/* 0x000fe20003f25270 */
/*04f0*/ UIADD3 UR4, UP0, UR4, 0x1, URZ ; /* 0x0000000104047890 */
/* 0x000fe2000ff1e03f */
/*0500*/ IADD3 R2, P2, R2, 0x10, RZ ; /* 0x0000001002027810 */
/* 0x000fc60007f5e0ff */
/*0510*/ UIADD3.X UR5, URZ, UR5, URZ, UP0, !UPT ; /* 0x000000053f057290 */
/* 0x000fe200087fe43f */
/*0520*/ IMAD.WIDE R16, R13, 0x4, R6 ; /* 0x000000040d107825 */
/* 0x000fe200078e0206 */
/*0530*/ IADD3 R14, R14, 0x4, RZ ; /* 0x000000040e0e7810 */
/* 0x000fc60007ffe0ff */
/*0540*/ IMAD.X R3, RZ, RZ, R3, P2 ; /* 0x000000ffff037224 */
/* 0x000fe200010e0603 */
/*0550*/ STG.E [R6.64], R19 ; /* 0x0000001306007986 */
/* 0x0085e8000c101906 */
/*0560*/ STG.E [R4.64], R11 ; /* 0x0000000b04007986 */
/* 0x0105e2000c101906 */
/*0570*/ @P1 BRA 0x1b0 ; /* 0xfffffc3000001947 */
/* 0x000fea000383ffff */
/*0580*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0590*/ IMAD R3, R14, c[0x0][0x170], RZ ; /* 0x00005c000e037a24 */
/* 0x000fe400078e02ff */
/*05a0*/ IMAD.MOV.U32 R15, RZ, RZ, 0x4 ; /* 0x00000004ff0f7424 */
/* 0x000fc600078e00ff */
/*05b0*/ IADD3 R13, P0, R0, R3, RZ ; /* 0x00000003000d7210 */
/* 0x000fe20007f1e0ff */
/*05c0*/ IMAD.WIDE R14, R14, R15, c[0x0][0x178] ; /* 0x00005e000e0e7625 */
/* 0x000fc600078e020f */
/*05d0*/ LEA R8, P1, R13, c[0x0][0x168], 0x2 ; /* 0x00005a000d087a11 */
/* 0x004fe400078210ff */
/*05e0*/ LEA.HI.X.SX32 R2, R3, RZ, 0x1, P0 ; /* 0x000000ff03027211 */
/* 0x000fc800000f0eff */
/*05f0*/ LEA.HI.X R13, R13, c[0x0][0x16c], R2, 0x2, P1 ; /* 0x00005b000d0d7a11 */
/* 0x000fe400008f1402 */
/*0600*/ IMAD.MOV.U32 R4, RZ, RZ, R14 ; /* 0x000000ffff047224 */
/* 0x000fe400078e000e */
/*0610*/ IMAD.MOV.U32 R5, RZ, RZ, R15 ; /* 0x000000ffff057224 */
/* 0x000fca00078e000f */
/*0620*/ LDG.E R2, [R4.64] ; /* 0x0000000604027981 */
/* 0x001ea2000c1e1900 */
/*0630*/ MOV R7, R13 ; /* 0x0000000d00077202 */
/* 0x000fe20000000f00 */
/*0640*/ IMAD R3, R2, c[0x0][0x170], RZ ; /* 0x00005c0002037a24 */
/* 0x004fca00078e02ff */
/*0650*/ IADD3 R6, P0, R0, R3, RZ ; /* 0x0000000300067210 */
/* 0x000fc80007f1e0ff */
/*0660*/ LEA.HI.X.SX32 R3, R3, RZ, 0x1, P0 ; /* 0x000000ff03037211 */
/* 0x000fe400000f0eff */
/*0670*/ LEA R2, P0, R6, c[0x0][0x168], 0x2 ; /* 0x00005a0006027a11 */
/* 0x000fc800078010ff */
/*0680*/ LEA.HI.X R3, R6, c[0x0][0x16c], R3, 0x2, P0 ; /* 0x00005b0006037a11 */
/* 0x000fe200000f1403 */
/*0690*/ IMAD.MOV.U32 R6, RZ, RZ, R8 ; /* 0x000000ffff067224 */
/* 0x000fc800078e0008 */
/*06a0*/ LDG.E R11, [R2.64] ; /* 0x00000006020b7981 */
/* 0x000ea8000c1e1900 */
/*06b0*/ LDG.E R9, [R6.64] ; /* 0x0000000606097981 */
/* 0x000ee2000c1e1900 */
/*06c0*/ IADD3 R12, R12, -0x1, RZ ; /* 0xffffffff0c0c7810 */
/* 0x000fe20007ffe0ff */
/*06d0*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff057624 */
/* 0x000fe200078e00ff */
/*06e0*/ IADD3 R14, P1, R14, 0x4, RZ ; /* 0x000000040e0e7810 */
/* 0x000fe40007f3e0ff */
/*06f0*/ ISETP.NE.AND P0, PT, R12, RZ, PT ; /* 0x000000ff0c00720c */
/* 0x000fe20003f05270 */
/*0700*/ IMAD.WIDE R4, R5, 0x4, R6 ; /* 0x0000000405047825 */
/* 0x000fc800078e0206 */
/*0710*/ IMAD.MOV.U32 R8, RZ, RZ, R4 ; /* 0x000000ffff087224 */
/* 0x000fe400078e0004 */
/*0720*/ IMAD.MOV.U32 R13, RZ, RZ, R5 ; /* 0x000000ffff0d7224 */
/* 0x000fe400078e0005 */
/*0730*/ IMAD.X R15, RZ, RZ, R15, P1 ; /* 0x000000ffff0f7224 */
/* 0x000fe200008e060f */
/*0740*/ STG.E [R6.64], R11 ; /* 0x0000000b06007986 */
/* 0x0041e8000c101906 */
/*0750*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x0081e2000c101906 */
/*0760*/ @P0 BRA 0x600 ; /* 0xfffffe9000000947 */
/* 0x000fea000383ffff */
/*0770*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0780*/ BRA 0x780; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0790*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0800*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0810*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0820*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0830*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0840*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0850*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0860*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0870*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #define SWAPS_PER_RUN 64
#define VL 64
extern "C"
__global__ void batch_sswap(int nswaps, int n, float *A, int lda, int *ipiv)
{
unsigned int tid = threadIdx.x + VL * blockIdx.x;
if( tid >= n ) return;
float *d_A = A + tid;
for (int i = 0; i < nswaps; i++)
{
int j = ipiv[i];
float temp = d_A[i*lda];
d_A[i*lda] = d_A[j*lda];
d_A[j*lda] = temp;
}
}
extern "C"
__global__ void batch_dswap(int nswaps, int n, double *A, int lda, int *ipiv)
{
unsigned int tid = threadIdx.x + blockDim.x * blockIdx.x;
if( tid >= n ) return;
double *d_A = A + tid;
for (int i = 0; i < nswaps; i++)
{
int j = ipiv[i];
double temp = d_A[i*lda];
d_A[i*lda] = d_A[j*lda];
d_A[j*lda] = temp;
}
} | .file "tmpxft_00151e26_00000000-6_swap.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z36__device_stub__Z11batch_sswapiiPfiPiiiPfiPi
.type _Z36__device_stub__Z11batch_sswapiiPfiPiiiPfiPi, @function
_Z36__device_stub__Z11batch_sswapiiPfiPiiiPfiPi:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movl %esi, 24(%rsp)
movq %rdx, 16(%rsp)
movl %ecx, 12(%rsp)
movq %r8, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq batch_sswap(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z36__device_stub__Z11batch_sswapiiPfiPiiiPfiPi, .-_Z36__device_stub__Z11batch_sswapiiPfiPiiiPfiPi
.globl batch_sswap
.type batch_sswap, @function
batch_sswap:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z36__device_stub__Z11batch_sswapiiPfiPiiiPfiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size batch_sswap, .-batch_sswap
.globl _Z36__device_stub__Z11batch_dswapiiPdiPiiiPdiPi
.type _Z36__device_stub__Z11batch_dswapiiPdiPiiiPdiPi, @function
_Z36__device_stub__Z11batch_dswapiiPdiPiiiPdiPi:
.LFB2053:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movl %esi, 24(%rsp)
movq %rdx, 16(%rsp)
movl %ecx, 12(%rsp)
movq %r8, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq batch_dswap(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2053:
.size _Z36__device_stub__Z11batch_dswapiiPdiPiiiPdiPi, .-_Z36__device_stub__Z11batch_dswapiiPdiPiiiPdiPi
.globl batch_dswap
.type batch_dswap, @function
batch_dswap:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z36__device_stub__Z11batch_dswapiiPdiPiiiPdiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size batch_dswap, .-batch_dswap
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "batch_dswap"
.LC1:
.string "batch_sswap"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2056:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq batch_dswap(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq batch_sswap(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2056:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #define SWAPS_PER_RUN 64
#define VL 64
extern "C"
__global__ void batch_sswap(int nswaps, int n, float *A, int lda, int *ipiv)
{
unsigned int tid = threadIdx.x + VL * blockIdx.x;
if( tid >= n ) return;
float *d_A = A + tid;
for (int i = 0; i < nswaps; i++)
{
int j = ipiv[i];
float temp = d_A[i*lda];
d_A[i*lda] = d_A[j*lda];
d_A[j*lda] = temp;
}
}
extern "C"
__global__ void batch_dswap(int nswaps, int n, double *A, int lda, int *ipiv)
{
unsigned int tid = threadIdx.x + blockDim.x * blockIdx.x;
if( tid >= n ) return;
double *d_A = A + tid;
for (int i = 0; i < nswaps; i++)
{
int j = ipiv[i];
double temp = d_A[i*lda];
d_A[i*lda] = d_A[j*lda];
d_A[j*lda] = temp;
}
} | #include <hip/hip_runtime.h>
#define SWAPS_PER_RUN 64
#define VL 64
extern "C"
__global__ void batch_sswap(int nswaps, int n, float *A, int lda, int *ipiv)
{
unsigned int tid = threadIdx.x + VL * blockIdx.x;
if( tid >= n ) return;
float *d_A = A + tid;
for (int i = 0; i < nswaps; i++)
{
int j = ipiv[i];
float temp = d_A[i*lda];
d_A[i*lda] = d_A[j*lda];
d_A[j*lda] = temp;
}
}
extern "C"
__global__ void batch_dswap(int nswaps, int n, double *A, int lda, int *ipiv)
{
unsigned int tid = threadIdx.x + blockDim.x * blockIdx.x;
if( tid >= n ) return;
double *d_A = A + tid;
for (int i = 0; i < nswaps; i++)
{
int j = ipiv[i];
double temp = d_A[i*lda];
d_A[i*lda] = d_A[j*lda];
d_A[j*lda] = temp;
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#define SWAPS_PER_RUN 64
#define VL 64
extern "C"
__global__ void batch_sswap(int nswaps, int n, float *A, int lda, int *ipiv)
{
unsigned int tid = threadIdx.x + VL * blockIdx.x;
if( tid >= n ) return;
float *d_A = A + tid;
for (int i = 0; i < nswaps; i++)
{
int j = ipiv[i];
float temp = d_A[i*lda];
d_A[i*lda] = d_A[j*lda];
d_A[j*lda] = temp;
}
}
extern "C"
__global__ void batch_dswap(int nswaps, int n, double *A, int lda, int *ipiv)
{
unsigned int tid = threadIdx.x + blockDim.x * blockIdx.x;
if( tid >= n ) return;
double *d_A = A + tid;
for (int i = 0; i < nswaps; i++)
{
int j = ipiv[i];
double temp = d_A[i*lda];
d_A[i*lda] = d_A[j*lda];
d_A[j*lda] = temp;
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected batch_sswap
.globl batch_sswap
.p2align 8
.type batch_sswap,@function
batch_sswap:
s_load_b32 s2, s[0:1], 0x4
v_lshl_add_u32 v0, s15, 6, v0
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_cmp_gt_u32_e32 vcc_lo, s2, v0
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_4
s_load_b32 s6, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s6, 1
s_cbranch_scc1 .LBB0_4
s_clause 0x1
s_load_b64 s[4:5], s[0:1], 0x8
s_load_b32 s2, s[0:1], 0x10
v_mov_b32_e32 v1, 0
s_load_b64 s[0:1], s[0:1], 0x18
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
s_ashr_i32 s3, s2, 31
s_lshl_b64 s[4:5], s[2:3], 2
s_delay_alu instid0(VALU_DEP_1)
v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0
.p2align 6
.LBB0_3:
s_load_b32 s3, s[0:1], 0x0
s_add_i32 s6, s6, -1
s_waitcnt lgkmcnt(0)
s_mul_i32 s8, s3, s2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_ashr_i32 s9, s8, 31
s_lshl_b64 s[8:9], s[8:9], 2
s_add_u32 s0, s0, 4
v_add_co_u32 v4, vcc_lo, v0, s8
v_add_co_ci_u32_e32 v5, vcc_lo, s9, v1, vcc_lo
s_addc_u32 s1, s1, 0
s_cmp_lg_u32 s6, 0
global_load_b32 v6, v[4:5], off
global_load_b32 v7, v[2:3], off
s_waitcnt vmcnt(1)
global_store_b32 v[2:3], v6, off
v_add_co_u32 v2, vcc_lo, v2, s4
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
s_waitcnt vmcnt(0)
global_store_b32 v[4:5], v7, off
s_cbranch_scc1 .LBB0_3
.LBB0_4:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel batch_sswap
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 32
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size batch_sswap, .Lfunc_end0-batch_sswap
.section .AMDGPU.csdata,"",@progbits
.text
.protected batch_dswap
.globl batch_dswap
.p2align 8
.type batch_dswap,@function
batch_dswap:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x4
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_u32_e64 s3, v1
s_cbranch_execz .LBB1_4
s_load_b32 s6, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s6, 1
s_cbranch_scc1 .LBB1_4
s_clause 0x1
s_load_b64 s[4:5], s[0:1], 0x8
s_load_b32 s2, s[0:1], 0x10
v_mov_b32_e32 v2, 0
s_load_b64 s[0:1], s[0:1], 0x18
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 3, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
s_ashr_i32 s3, s2, 31
s_lshl_b64 s[4:5], s[2:3], 3
s_delay_alu instid0(VALU_DEP_1)
v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0
.p2align 6
.LBB1_3:
s_load_b32 s3, s[0:1], 0x0
s_add_i32 s6, s6, -1
s_waitcnt lgkmcnt(0)
s_mul_i32 s8, s3, s2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_ashr_i32 s9, s8, 31
s_lshl_b64 s[8:9], s[8:9], 3
s_add_u32 s0, s0, 4
v_add_co_u32 v4, vcc_lo, v0, s8
v_add_co_ci_u32_e32 v5, vcc_lo, s9, v1, vcc_lo
s_addc_u32 s1, s1, 0
s_cmp_lg_u32 s6, 0
global_load_b64 v[6:7], v[4:5], off
global_load_b64 v[8:9], v[2:3], off
s_waitcnt vmcnt(1)
global_store_b64 v[2:3], v[6:7], off
v_add_co_u32 v2, vcc_lo, v2, s4
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
s_waitcnt vmcnt(0)
global_store_b64 v[4:5], v[8:9], off
s_cbranch_scc1 .LBB1_3
.LBB1_4:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel batch_dswap
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 10
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size batch_dswap, .Lfunc_end1-batch_dswap
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 32
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: batch_sswap
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: batch_sswap.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: batch_dswap
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: batch_dswap.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 10
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#define SWAPS_PER_RUN 64
#define VL 64
extern "C"
__global__ void batch_sswap(int nswaps, int n, float *A, int lda, int *ipiv)
{
unsigned int tid = threadIdx.x + VL * blockIdx.x;
if( tid >= n ) return;
float *d_A = A + tid;
for (int i = 0; i < nswaps; i++)
{
int j = ipiv[i];
float temp = d_A[i*lda];
d_A[i*lda] = d_A[j*lda];
d_A[j*lda] = temp;
}
}
extern "C"
__global__ void batch_dswap(int nswaps, int n, double *A, int lda, int *ipiv)
{
unsigned int tid = threadIdx.x + blockDim.x * blockIdx.x;
if( tid >= n ) return;
double *d_A = A + tid;
for (int i = 0; i < nswaps; i++)
{
int j = ipiv[i];
double temp = d_A[i*lda];
d_A[i*lda] = d_A[j*lda];
d_A[j*lda] = temp;
}
} | .text
.file "swap.hip"
.globl __device_stub__batch_sswap # -- Begin function __device_stub__batch_sswap
.p2align 4, 0x90
.type __device_stub__batch_sswap,@function
__device_stub__batch_sswap: # @__device_stub__batch_sswap
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 12(%rsp)
movl %esi, 8(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 4(%rsp)
movq %r8, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 8(%rsp), %rax
movq %rax, 88(%rsp)
leaq 72(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 64(%rsp), %rax
movq %rax, 112(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $batch_sswap, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size __device_stub__batch_sswap, .Lfunc_end0-__device_stub__batch_sswap
.cfi_endproc
# -- End function
.globl __device_stub__batch_dswap # -- Begin function __device_stub__batch_dswap
.p2align 4, 0x90
.type __device_stub__batch_dswap,@function
__device_stub__batch_dswap: # @__device_stub__batch_dswap
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 12(%rsp)
movl %esi, 8(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 4(%rsp)
movq %r8, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 8(%rsp), %rax
movq %rax, 88(%rsp)
leaq 72(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 64(%rsp), %rax
movq %rax, 112(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $batch_dswap, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end1:
.size __device_stub__batch_dswap, .Lfunc_end1-__device_stub__batch_dswap
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $batch_sswap, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $batch_dswap, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type batch_sswap,@object # @batch_sswap
.section .rodata,"a",@progbits
.globl batch_sswap
.p2align 3, 0x0
batch_sswap:
.quad __device_stub__batch_sswap
.size batch_sswap, 8
.type batch_dswap,@object # @batch_dswap
.globl batch_dswap
.p2align 3, 0x0
batch_dswap:
.quad __device_stub__batch_dswap
.size batch_dswap, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "batch_sswap"
.size .L__unnamed_1, 12
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "batch_dswap"
.size .L__unnamed_2, 12
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub__batch_sswap
.addrsig_sym __device_stub__batch_dswap
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym batch_sswap
.addrsig_sym batch_dswap
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : batch_dswap
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x164], PT ; /* 0x0000590000007a0c */
/* 0x000fda0003f06070 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff027624 */
/* 0x000fca00078e00ff */
/*0070*/ ISETP.GE.AND P0, PT, R2, 0x1, PT ; /* 0x000000010200780c */
/* 0x000fda0003f06270 */
/*0080*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0090*/ IADD3 R3, R2.reuse, -0x1, RZ ; /* 0xffffffff02037810 */
/* 0x040fe20007ffe0ff */
/*00a0*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*00b0*/ LOP3.LUT R2, R2, 0x3, RZ, 0xc0, !PT ; /* 0x0000000302027812 */
/* 0x000fe200078ec0ff */
/*00c0*/ IMAD.MOV.U32 R5, RZ, RZ, RZ ; /* 0x000000ffff057224 */
/* 0x000fe200078e00ff */
/*00d0*/ ISETP.GE.U32.AND P1, PT, R3, 0x3, PT ; /* 0x000000030300780c */
/* 0x000fe40003f26070 */
/*00e0*/ ISETP.NE.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fd60003f05270 */
/*00f0*/ @!P1 BRA 0x590 ; /* 0x0000049000009947 */
/* 0x000fea0003800000 */
/*0100*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff047624 */
/* 0x000fe200078e00ff */
/*0110*/ LEA R8, P1, R0, c[0x0][0x168], 0x3 ; /* 0x00005a0000087a11 */
/* 0x000fe200078218ff */
/*0120*/ IMAD.MOV.U32 R5, RZ, RZ, RZ ; /* 0x000000ffff057224 */
/* 0x000fe200078e00ff */
/*0130*/ IADD3 R7, -R2, c[0x0][0x160], RZ ; /* 0x0000580002077a10 */
/* 0x000fe20007ffe1ff */
/*0140*/ IMAD.SHL.U32 R6, R4, 0x4, RZ ; /* 0x0000000404067824 */
/* 0x000fe200078e00ff */
/*0150*/ MOV R10, c[0x0][0x178] ; /* 0x00005e00000a7a02 */
/* 0x000fe20000000f00 */
/*0160*/ IMAD.MOV.U32 R11, RZ, RZ, c[0x0][0x17c] ; /* 0x00005f00ff0b7624 */
/* 0x000fe200078e00ff */
/*0170*/ LEA.HI.X R27, R0, c[0x0][0x16c], RZ, 0x3, P1 ; /* 0x00005b00001b7a11 */
/* 0x000fe200008f1cff */
/*0180*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*0190*/ SHF.R.S32.HI R3, RZ, 0x1f, R6 ; /* 0x0000001fff037819 */
/* 0x000fe20000011406 */
/*01a0*/ UMOV UR5, URZ ; /* 0x0000003f00057c82 */
/* 0x000fc40008000000 */
/*01b0*/ LDG.E R9, [R10.64] ; /* 0x000000060a097981 */
/* 0x000ea2000c1e1900 */
/*01c0*/ IMAD.MOV.U32 R16, RZ, RZ, R8 ; /* 0x000000ffff107224 */
/* 0x001fc400078e0008 */
/*01d0*/ IMAD.MOV.U32 R17, RZ, RZ, R27 ; /* 0x000000ffff117224 */
/* 0x000fca00078e001b */
/*01e0*/ LDG.E.64 R20, [R16.64] ; /* 0x0000000610147981 */
/* 0x000ee2000c1e1b00 */
/*01f0*/ IMAD R9, R9, c[0x0][0x170], RZ ; /* 0x00005c0009097a24 */
/* 0x004fca00078e02ff */
/*0200*/ IADD3 R12, P1, R0, R9, RZ ; /* 0x00000009000c7210 */
/* 0x000fc80007f3e0ff */
/*0210*/ LEA.HI.X.SX32 R9, R9, RZ, 0x1, P1 ; /* 0x000000ff09097211 */
/* 0x000fe400008f0eff */
/*0220*/ LEA R18, P1, R12, c[0x0][0x168], 0x3 ; /* 0x00005a000c127a11 */
/* 0x000fc800078218ff */
/*0230*/ LEA.HI.X R19, R12, c[0x0][0x16c], R9, 0x3, P1 ; /* 0x00005b000c137a11 */
/* 0x000fca00008f1c09 */
/*0240*/ LDG.E.64 R14, [R18.64] ; /* 0x00000006120e7981 */
/* 0x000ea2000c1e1b00 */
/*0250*/ IADD3 R26, P1, RZ, -R6, RZ ; /* 0x80000006ff1a7210 */
/* 0x000fc60007f3e0ff */
/*0260*/ STG.E.64 [R16.64], R14 ; /* 0x0000000e10007986 */
/* 0x0041e8000c101b06 */
/*0270*/ STG.E.64 [R18.64], R20 ; /* 0x0000001412007986 */
/* 0x0083e8000c101b06 */
/*0280*/ LDG.E R12, [R10.64+0x4] ; /* 0x000004060a0c7981 */
/* 0x000ea2000c1e1900 */
/*0290*/ IMAD.X R9, RZ, RZ, ~R3, P1 ; /* 0x000000ffff097224 */
/* 0x000fc800008e0e03 */
/*02a0*/ IMAD R9, R9, UR4, RZ ; /* 0x0000000409097c24 */
/* 0x000fc8000f8e02ff */
/*02b0*/ IMAD R9, R26, UR5, R9 ; /* 0x000000051a097c24 */
/* 0x000fe4000f8e0209 */
/*02c0*/ IMAD R12, R12, c[0x0][0x170], RZ ; /* 0x00005c000c0c7a24 */
/* 0x004fca00078e02ff */
/*02d0*/ SHF.R.S32.HI R13, RZ, 0x1f, R12 ; /* 0x0000001fff0d7819 */
/* 0x000fca000001140c */
/*02e0*/ IMAD.WIDE.U32 R12, R26, UR4, R12 ; /* 0x000000041a0c7c25 */
/* 0x000fc8000f8e000c */
/*02f0*/ IMAD.IADD R13, R13, 0x1, R9 ; /* 0x000000010d0d7824 */
/* 0x000fe200078e0209 */
/*0300*/ LEA R14, P1, R12, R8, 0x3 ; /* 0x000000080c0e7211 */
/* 0x001fc800078218ff */
/*0310*/ LEA.HI.X R15, R12, R27, R13, 0x3, P1 ; /* 0x0000001b0c0f7211 */
/* 0x000fe200008f1c0d */
/*0320*/ IMAD.WIDE R12, R4, 0x8, R16 ; /* 0x00000008040c7825 */
/* 0x000fc800078e0210 */
/*0330*/ LDG.E.64 R16, [R14.64] ; /* 0x000000060e107981 */
/* 0x000ea8000c1e1b00 */
/*0340*/ LDG.E.64 R18, [R12.64] ; /* 0x000000060c127981 */
/* 0x002ee8000c1e1b00 */
/*0350*/ STG.E.64 [R12.64], R16 ; /* 0x000000100c007986 */
/* 0x0041e8000c101b06 */
/*0360*/ STG.E.64 [R14.64], R18 ; /* 0x000000120e007986 */
/* 0x0083e8000c101b06 */
/*0370*/ LDG.E R22, [R10.64+0x8] ; /* 0x000008060a167981 */
/* 0x000ea4000c1e1900 */
/*0380*/ IMAD R22, R22, c[0x0][0x170], RZ ; /* 0x00005c0016167a24 */
/* 0x004fca00078e02ff */
/*0390*/ SHF.R.S32.HI R23, RZ, 0x1f, R22 ; /* 0x0000001fff177819 */
/* 0x000fca0000011416 */
/*03a0*/ IMAD.WIDE.U32 R22, R26, UR4, R22 ; /* 0x000000041a167c25 */
/* 0x000fca000f8e0016 */
/*03b0*/ IADD3 R21, R9, R23, RZ ; /* 0x0000001709157210 */
/* 0x000fe40007ffe0ff */
/*03c0*/ LEA R20, P1, R22, R8, 0x3 ; /* 0x0000000816147211 */
/* 0x000fc800078218ff */
/*03d0*/ LEA.HI.X R21, R22, R27, R21, 0x3, P1 ; /* 0x0000001b16157211 */
/* 0x000fe200008f1c15 */
/*03e0*/ IMAD.WIDE R22, R4, 0x8, R12 ; /* 0x0000000804167825 */
/* 0x000fc800078e020c */
/*03f0*/ LDG.E.64 R24, [R20.64] ; /* 0x0000000614187981 */
/* 0x000ea8000c1e1b00 */
/*0400*/ LDG.E.64 R12, [R22.64] ; /* 0x00000006160c7981 */
/* 0x001ee8000c1e1b00 */
/*0410*/ STG.E.64 [R22.64], R24 ; /* 0x0000001816007986 */
/* 0x0041e8000c101b06 */
/*0420*/ STG.E.64 [R20.64], R12 ; /* 0x0000000c14007986 */
/* 0x0081e8000c101b06 */
/*0430*/ LDG.E R16, [R10.64+0xc] ; /* 0x00000c060a107981 */
/* 0x000ea4000c1e1900 */
/*0440*/ IMAD R16, R16, c[0x0][0x170], RZ ; /* 0x00005c0010107a24 */
/* 0x004fca00078e02ff */
/*0450*/ SHF.R.S32.HI R17, RZ, 0x1f, R16 ; /* 0x0000001fff117819 */
/* 0x000fca0000011410 */
/*0460*/ IMAD.WIDE.U32 R16, R26, UR4, R16 ; /* 0x000000041a107c25 */
/* 0x000fc8000f8e0010 */
/*0470*/ IMAD.IADD R9, R9, 0x1, R17 ; /* 0x0000000109097824 */
/* 0x000fe200078e0211 */
/*0480*/ LEA R14, P1, R16, R8, 0x3 ; /* 0x00000008100e7211 */
/* 0x002fc800078218ff */
/*0490*/ LEA.HI.X R15, R16, R27, R9, 0x3, P1 ; /* 0x0000001b100f7211 */
/* 0x000fe200008f1c09 */
/*04a0*/ IMAD.WIDE R16, R4, 0x8, R22 ; /* 0x0000000804107825 */
/* 0x000fc800078e0216 */
/*04b0*/ LDG.E.64 R28, [R14.64] ; /* 0x000000060e1c7981 */
/* 0x000ea8000c1e1b00 */
/*04c0*/ LDG.E.64 R18, [R16.64] ; /* 0x0000000610127981 */
/* 0x000ee2000c1e1b00 */
/*04d0*/ IADD3 R7, R7, -0x4, RZ ; /* 0xfffffffc07077810 */
/* 0x000fc80007ffe0ff */
/*04e0*/ ISETP.NE.AND P1, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fe20003f25270 */
/*04f0*/ UIADD3 UR4, UP0, UR4, 0x1, URZ ; /* 0x0000000104047890 */
/* 0x000fe2000ff1e03f */
/*0500*/ IADD3 R10, P2, R10, 0x10, RZ ; /* 0x000000100a0a7810 */
/* 0x000fe20007f5e0ff */
/*0510*/ IMAD.WIDE R8, R4, 0x8, R16 ; /* 0x0000000804087825 */
/* 0x000fe400078e0210 */
/*0520*/ UIADD3.X UR5, URZ, UR5, URZ, UP0, !UPT ; /* 0x000000053f057290 */
/* 0x000fe200087fe43f */
/*0530*/ IADD3 R5, R5, 0x4, RZ ; /* 0x0000000405057810 */
/* 0x000fe20007ffe0ff */
/*0540*/ IMAD.X R11, RZ, RZ, R11, P2 ; /* 0x000000ffff0b7224 */
/* 0x000fe400010e060b */
/*0550*/ IMAD.MOV.U32 R27, RZ, RZ, R9 ; /* 0x000000ffff1b7224 */
/* 0x000fe200078e0009 */
/*0560*/ STG.E.64 [R16.64], R28 ; /* 0x0000001c10007986 */
/* 0x0041e8000c101b06 */
/*0570*/ STG.E.64 [R14.64], R18 ; /* 0x000000120e007986 */
/* 0x0081e2000c101b06 */
/*0580*/ @P1 BRA 0x1b0 ; /* 0xfffffc2000001947 */
/* 0x000fea000383ffff */
/*0590*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*05a0*/ IMAD R3, R5, c[0x0][0x170], RZ ; /* 0x00005c0005037a24 */
/* 0x000fe400078e02ff */
/*05b0*/ IMAD.MOV.U32 R4, RZ, RZ, 0x4 ; /* 0x00000004ff047424 */
/* 0x000fc600078e00ff */
/*05c0*/ IADD3 R17, P0, R0, R3, RZ ; /* 0x0000000300117210 */
/* 0x001fe20007f1e0ff */
/*05d0*/ IMAD.WIDE R4, R5, R4, c[0x0][0x178] ; /* 0x00005e0005047625 */
/* 0x000fc600078e0204 */
/*05e0*/ LEA R16, P1, R17, c[0x0][0x168], 0x3 ; /* 0x00005a0011107a11 */
/* 0x000fe200078218ff */
/*05f0*/ IMAD.MOV.U32 R14, RZ, RZ, R4 ; /* 0x000000ffff0e7224 */
/* 0x000fe200078e0004 */
/*0600*/ LEA.HI.X.SX32 R6, R3, RZ, 0x1, P0 ; /* 0x000000ff03067211 */
/* 0x000fe400000f0eff */
/*0610*/ MOV R15, R5 ; /* 0x00000005000f7202 */
/* 0x000fe40000000f00 */
/*0620*/ LEA.HI.X R17, R17, c[0x0][0x16c], R6, 0x3, P1 ; /* 0x00005b0011117a11 */
/* 0x000fe400008f1c06 */
/*0630*/ IMAD.MOV.U32 R10, RZ, RZ, R14 ; /* 0x000000ffff0a7224 */
/* 0x000fe400078e000e */
/*0640*/ IMAD.MOV.U32 R11, RZ, RZ, R15 ; /* 0x000000ffff0b7224 */
/* 0x000fca00078e000f */
/*0650*/ LDG.E R3, [R10.64] ; /* 0x000000060a037981 */
/* 0x000ea2000c1e1900 */
/*0660*/ IMAD.MOV.U32 R12, RZ, RZ, R16 ; /* 0x000000ffff0c7224 */
/* 0x001fe400078e0010 */
/*0670*/ IMAD.MOV.U32 R13, RZ, RZ, R17 ; /* 0x000000ffff0d7224 */
/* 0x000fe400078e0011 */
/*0680*/ IMAD R3, R3, c[0x0][0x170], RZ ; /* 0x00005c0003037a24 */
/* 0x004fca00078e02ff */
/*0690*/ IADD3 R4, P0, R0, R3, RZ ; /* 0x0000000300047210 */
/* 0x000fc80007f1e0ff */
/*06a0*/ LEA.HI.X.SX32 R3, R3, RZ, 0x1, P0 ; /* 0x000000ff03037211 */
/* 0x000fe400000f0eff */
/*06b0*/ LEA R6, P0, R4, c[0x0][0x168], 0x3 ; /* 0x00005a0004067a11 */
/* 0x000fc800078018ff */
/*06c0*/ LEA.HI.X R7, R4, c[0x0][0x16c], R3, 0x3, P0 ; /* 0x00005b0004077a11 */
/* 0x000fe400000f1c03 */
/*06d0*/ LDG.E.64 R4, [R12.64] ; /* 0x000000060c047981 */
/* 0x000ea8000c1e1b00 */
/*06e0*/ LDG.E.64 R8, [R6.64] ; /* 0x0000000606087981 */
/* 0x000ee2000c1e1b00 */
/*06f0*/ IADD3 R2, R2, -0x1, RZ ; /* 0xffffffff02027810 */
/* 0x000fc80007ffe0ff */
/*0700*/ ISETP.NE.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fe40003f05270 */
/*0710*/ MOV R11, c[0x0][0x170] ; /* 0x00005c00000b7a02 */
/* 0x000fe40000000f00 */
/*0720*/ IADD3 R14, P1, R14, 0x4, RZ ; /* 0x000000040e0e7810 */
/* 0x000fc60007f3e0ff */
/*0730*/ IMAD.WIDE R10, R11, 0x8, R12 ; /* 0x000000080b0a7825 */
/* 0x000fc800078e020c */
/*0740*/ IMAD.MOV.U32 R16, RZ, RZ, R10 ; /* 0x000000ffff107224 */
/* 0x000fe400078e000a */
/*0750*/ IMAD.MOV.U32 R17, RZ, RZ, R11 ; /* 0x000000ffff117224 */
/* 0x000fe400078e000b */
/*0760*/ IMAD.X R15, RZ, RZ, R15, P1 ; /* 0x000000ffff0f7224 */
/* 0x000fe200008e060f */
/*0770*/ STG.E.64 [R12.64], R8 ; /* 0x000000080c007986 */
/* 0x0081e8000c101b06 */
/*0780*/ STG.E.64 [R6.64], R4 ; /* 0x0000000406007986 */
/* 0x0041e2000c101b06 */
/*0790*/ @P0 BRA 0x630 ; /* 0xfffffe9000000947 */
/* 0x000fea000383ffff */
/*07a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*07b0*/ BRA 0x7b0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*07c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0800*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0810*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0820*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0830*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0840*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0850*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0860*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0870*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : batch_sswap
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, 0x40, R3 ; /* 0x0000004000007824 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x164], PT ; /* 0x0000590000007a0c */
/* 0x000fda0003f06070 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ IMAD.MOV.U32 R12, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff0c7624 */
/* 0x000fca00078e00ff */
/*0070*/ ISETP.GE.AND P0, PT, R12, 0x1, PT ; /* 0x000000010c00780c */
/* 0x000fda0003f06270 */
/*0080*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0090*/ IADD3 R2, R12.reuse, -0x1, RZ ; /* 0xffffffff0c027810 */
/* 0x040fe20007ffe0ff */
/*00a0*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*00b0*/ LOP3.LUT R12, R12, 0x3, RZ, 0xc0, !PT ; /* 0x000000030c0c7812 */
/* 0x000fe200078ec0ff */
/*00c0*/ IMAD.MOV.U32 R14, RZ, RZ, RZ ; /* 0x000000ffff0e7224 */
/* 0x000fe200078e00ff */
/*00d0*/ ISETP.GE.U32.AND P1, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fe40003f26070 */
/*00e0*/ ISETP.NE.AND P0, PT, R12, RZ, PT ; /* 0x000000ff0c00720c */
/* 0x000fd60003f05270 */
/*00f0*/ @!P1 BRA 0x580 ; /* 0x0000048000009947 */
/* 0x000fea0003800000 */
/*0100*/ IMAD.MOV.U32 R13, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff0d7624 */
/* 0x000fe200078e00ff */
/*0110*/ LEA R16, P1, R0, c[0x0][0x168], 0x2 ; /* 0x00005a0000107a11 */
/* 0x000fe200078210ff */
/*0120*/ IMAD.MOV.U32 R14, RZ, RZ, RZ ; /* 0x000000ffff0e7224 */
/* 0x000fe200078e00ff */
/*0130*/ IADD3 R15, -R12, c[0x0][0x160], RZ ; /* 0x000058000c0f7a10 */
/* 0x000fe20007ffe1ff */
/*0140*/ IMAD.SHL.U32 R21, R13, 0x4, RZ ; /* 0x000000040d157824 */
/* 0x000fe200078e00ff */
/*0150*/ MOV R3, c[0x0][0x17c] ; /* 0x00005f0000037a02 */
/* 0x000fe20000000f00 */
/*0160*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x178] ; /* 0x00005e00ff027624 */
/* 0x000fe200078e00ff */
/*0170*/ LEA.HI.X R17, R0, c[0x0][0x16c], RZ, 0x2, P1 ; /* 0x00005b0000117a11 */
/* 0x000fe200008f14ff */
/*0180*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*0190*/ SHF.R.S32.HI R20, RZ, 0x1f, R21 ; /* 0x0000001fff147819 */
/* 0x000fe20000011415 */
/*01a0*/ UMOV UR5, URZ ; /* 0x0000003f00057c82 */
/* 0x000fc40008000000 */
/*01b0*/ LDG.E R4, [R2.64] ; /* 0x0000000602047981 */
/* 0x004ea2000c1e1900 */
/*01c0*/ IMAD.MOV.U32 R6, RZ, RZ, R16 ; /* 0x000000ffff067224 */
/* 0x000fc400078e0010 */
/*01d0*/ IMAD.MOV.U32 R7, RZ, RZ, R17 ; /* 0x000000ffff077224 */
/* 0x000fca00078e0011 */
/*01e0*/ LDG.E R23, [R6.64] ; /* 0x0000000606177981 */
/* 0x000ee2000c1e1900 */
/*01f0*/ IMAD R5, R4, c[0x0][0x170], RZ ; /* 0x00005c0004057a24 */
/* 0x004fca00078e02ff */
/*0200*/ IADD3 R4, P1, R0, R5, RZ ; /* 0x0000000500047210 */
/* 0x000fc80007f3e0ff */
/*0210*/ LEA.HI.X.SX32 R5, R5, RZ, 0x1, P1 ; /* 0x000000ff05057211 */
/* 0x000fe400008f0eff */
/*0220*/ LEA R10, P1, R4, c[0x0][0x168], 0x2 ; /* 0x00005a00040a7a11 */
/* 0x000fc800078210ff */
/*0230*/ LEA.HI.X R11, R4, c[0x0][0x16c], R5, 0x2, P1 ; /* 0x00005b00040b7a11 */
/* 0x000fca00008f1405 */
/*0240*/ LDG.E R5, [R10.64] ; /* 0x000000060a057981 */
/* 0x000ea2000c1e1900 */
/*0250*/ IADD3 R18, P1, RZ, -R21, RZ ; /* 0x80000015ff127210 */
/* 0x000fc60007f3e0ff */
/*0260*/ STG.E [R6.64], R5 ; /* 0x0000000506007986 */
/* 0x0041e8000c101906 */
/*0270*/ STG.E [R10.64], R23 ; /* 0x000000170a007986 */
/* 0x0083e8000c101906 */
/*0280*/ LDG.E R8, [R2.64+0x4] ; /* 0x0000040602087981 */
/* 0x000ea2000c1e1900 */
/*0290*/ IMAD.X R19, RZ, RZ, ~R20, P1 ; /* 0x000000ffff137224 */
/* 0x000fc800008e0e14 */
/*02a0*/ IMAD R19, R19, UR4, RZ ; /* 0x0000000413137c24 */
/* 0x000fc8000f8e02ff */
/*02b0*/ IMAD R19, R18, UR5, R19 ; /* 0x0000000512137c24 */
/* 0x000fe4000f8e0213 */
/*02c0*/ IMAD.WIDE R6, R13, 0x4, R6 ; /* 0x000000040d067825 */
/* 0x001fca00078e0206 */
/*02d0*/ LDG.E R23, [R6.64] ; /* 0x0000000606177981 */
/* 0x002ee2000c1e1900 */
/*02e0*/ IMAD R8, R8, c[0x0][0x170], RZ ; /* 0x00005c0008087a24 */
/* 0x004fca00078e02ff */
/*02f0*/ SHF.R.S32.HI R9, RZ, 0x1f, R8 ; /* 0x0000001fff097819 */
/* 0x000fca0000011408 */
/*0300*/ IMAD.WIDE.U32 R8, R18, UR4, R8 ; /* 0x0000000412087c25 */
/* 0x000fc8000f8e0008 */
/*0310*/ IMAD.IADD R9, R9, 0x1, R19 ; /* 0x0000000109097824 */
/* 0x000fe200078e0213 */
/*0320*/ LEA R4, P1, R8, R16, 0x2 ; /* 0x0000001008047211 */
/* 0x000fc800078210ff */
/*0330*/ LEA.HI.X R5, R8, R17, R9, 0x2, P1 ; /* 0x0000001108057211 */
/* 0x000fca00008f1409 */
/*0340*/ LDG.E R25, [R4.64] ; /* 0x0000000604197981 */
/* 0x000ea8000c1e1900 */
/*0350*/ STG.E [R6.64], R25 ; /* 0x0000001906007986 */
/* 0x0041e8000c101906 */
/*0360*/ STG.E [R4.64], R23 ; /* 0x0000001704007986 */
/* 0x0083e8000c101906 */
/*0370*/ LDG.E R10, [R2.64+0x8] ; /* 0x00000806020a7981 */
/* 0x000ea4000c1e1900 */
/*0380*/ IMAD R10, R10, c[0x0][0x170], RZ ; /* 0x00005c000a0a7a24 */
/* 0x004fca00078e02ff */
/*0390*/ SHF.R.S32.HI R11, RZ, 0x1f, R10 ; /* 0x0000001fff0b7819 */
/* 0x000fca000001140a */
/*03a0*/ IMAD.WIDE.U32 R10, R18, UR4, R10 ; /* 0x00000004120a7c25 */
/* 0x000fc8000f8e000a */
/*03b0*/ IMAD.IADD R9, R19, 0x1, R11 ; /* 0x0000000113097824 */
/* 0x000fe200078e020b */
/*03c0*/ LEA R8, P1, R10, R16, 0x2 ; /* 0x000000100a087211 */
/* 0x000fc800078210ff */
/*03d0*/ LEA.HI.X R9, R10, R17, R9, 0x2, P1 ; /* 0x000000110a097211 */
/* 0x000fe200008f1409 */
/*03e0*/ IMAD.WIDE R10, R13, 0x4, R6 ; /* 0x000000040d0a7825 */
/* 0x000fc800078e0206 */
/*03f0*/ LDG.E R27, [R8.64] ; /* 0x00000006081b7981 */
/* 0x000ea8000c1e1900 */
/*0400*/ LDG.E R25, [R10.64] ; /* 0x000000060a197981 */
/* 0x001ee8000c1e1900 */
/*0410*/ STG.E [R10.64], R27 ; /* 0x0000001b0a007986 */
/* 0x0041e8000c101906 */
/*0420*/ STG.E [R8.64], R25 ; /* 0x0000001908007986 */
/* 0x0085e8000c101906 */
/*0430*/ LDG.E R6, [R2.64+0xc] ; /* 0x00000c0602067981 */
/* 0x000ee4000c1e1900 */
/*0440*/ IMAD R6, R6, c[0x0][0x170], RZ ; /* 0x00005c0006067a24 */
/* 0x008fca00078e02ff */
/*0450*/ SHF.R.S32.HI R7, RZ, 0x1f, R6 ; /* 0x0000001fff077819 */
/* 0x000fca0000011406 */
/*0460*/ IMAD.WIDE.U32 R6, R18, UR4, R6 ; /* 0x0000000412067c25 */
/* 0x000fca000f8e0006 */
/*0470*/ IADD3 R19, R19, R7, RZ ; /* 0x0000000713137210 */
/* 0x000fe40007ffe0ff */
/*0480*/ LEA R4, P1, R6, R16, 0x2 ; /* 0x0000001006047211 */
/* 0x002fc800078210ff */
/*0490*/ LEA.HI.X R5, R6, R17, R19, 0x2, P1 ; /* 0x0000001106057211 */
/* 0x000fe200008f1413 */
/*04a0*/ IMAD.WIDE R6, R13, 0x4, R10 ; /* 0x000000040d067825 */
/* 0x000fc800078e020a */
/*04b0*/ LDG.E R19, [R4.64] ; /* 0x0000000604137981 */
/* 0x000ee8000c1e1900 */
/*04c0*/ LDG.E R11, [R6.64] ; /* 0x00000006060b7981 */
/* 0x001f22000c1e1900 */
/*04d0*/ IADD3 R15, R15, -0x4, RZ ; /* 0xfffffffc0f0f7810 */
/* 0x000fc80007ffe0ff */
/*04e0*/ ISETP.NE.AND P1, PT, R15, RZ, PT ; /* 0x000000ff0f00720c */
/* 0x000fe20003f25270 */
/*04f0*/ UIADD3 UR4, UP0, UR4, 0x1, URZ ; /* 0x0000000104047890 */
/* 0x000fe2000ff1e03f */
/*0500*/ IADD3 R2, P2, R2, 0x10, RZ ; /* 0x0000001002027810 */
/* 0x000fc60007f5e0ff */
/*0510*/ UIADD3.X UR5, URZ, UR5, URZ, UP0, !UPT ; /* 0x000000053f057290 */
/* 0x000fe200087fe43f */
/*0520*/ IMAD.WIDE R16, R13, 0x4, R6 ; /* 0x000000040d107825 */
/* 0x000fe200078e0206 */
/*0530*/ IADD3 R14, R14, 0x4, RZ ; /* 0x000000040e0e7810 */
/* 0x000fc60007ffe0ff */
/*0540*/ IMAD.X R3, RZ, RZ, R3, P2 ; /* 0x000000ffff037224 */
/* 0x000fe200010e0603 */
/*0550*/ STG.E [R6.64], R19 ; /* 0x0000001306007986 */
/* 0x0085e8000c101906 */
/*0560*/ STG.E [R4.64], R11 ; /* 0x0000000b04007986 */
/* 0x0105e2000c101906 */
/*0570*/ @P1 BRA 0x1b0 ; /* 0xfffffc3000001947 */
/* 0x000fea000383ffff */
/*0580*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0590*/ IMAD R3, R14, c[0x0][0x170], RZ ; /* 0x00005c000e037a24 */
/* 0x000fe400078e02ff */
/*05a0*/ IMAD.MOV.U32 R15, RZ, RZ, 0x4 ; /* 0x00000004ff0f7424 */
/* 0x000fc600078e00ff */
/*05b0*/ IADD3 R13, P0, R0, R3, RZ ; /* 0x00000003000d7210 */
/* 0x000fe20007f1e0ff */
/*05c0*/ IMAD.WIDE R14, R14, R15, c[0x0][0x178] ; /* 0x00005e000e0e7625 */
/* 0x000fc600078e020f */
/*05d0*/ LEA R8, P1, R13, c[0x0][0x168], 0x2 ; /* 0x00005a000d087a11 */
/* 0x004fe400078210ff */
/*05e0*/ LEA.HI.X.SX32 R2, R3, RZ, 0x1, P0 ; /* 0x000000ff03027211 */
/* 0x000fc800000f0eff */
/*05f0*/ LEA.HI.X R13, R13, c[0x0][0x16c], R2, 0x2, P1 ; /* 0x00005b000d0d7a11 */
/* 0x000fe400008f1402 */
/*0600*/ IMAD.MOV.U32 R4, RZ, RZ, R14 ; /* 0x000000ffff047224 */
/* 0x000fe400078e000e */
/*0610*/ IMAD.MOV.U32 R5, RZ, RZ, R15 ; /* 0x000000ffff057224 */
/* 0x000fca00078e000f */
/*0620*/ LDG.E R2, [R4.64] ; /* 0x0000000604027981 */
/* 0x001ea2000c1e1900 */
/*0630*/ MOV R7, R13 ; /* 0x0000000d00077202 */
/* 0x000fe20000000f00 */
/*0640*/ IMAD R3, R2, c[0x0][0x170], RZ ; /* 0x00005c0002037a24 */
/* 0x004fca00078e02ff */
/*0650*/ IADD3 R6, P0, R0, R3, RZ ; /* 0x0000000300067210 */
/* 0x000fc80007f1e0ff */
/*0660*/ LEA.HI.X.SX32 R3, R3, RZ, 0x1, P0 ; /* 0x000000ff03037211 */
/* 0x000fe400000f0eff */
/*0670*/ LEA R2, P0, R6, c[0x0][0x168], 0x2 ; /* 0x00005a0006027a11 */
/* 0x000fc800078010ff */
/*0680*/ LEA.HI.X R3, R6, c[0x0][0x16c], R3, 0x2, P0 ; /* 0x00005b0006037a11 */
/* 0x000fe200000f1403 */
/*0690*/ IMAD.MOV.U32 R6, RZ, RZ, R8 ; /* 0x000000ffff067224 */
/* 0x000fc800078e0008 */
/*06a0*/ LDG.E R11, [R2.64] ; /* 0x00000006020b7981 */
/* 0x000ea8000c1e1900 */
/*06b0*/ LDG.E R9, [R6.64] ; /* 0x0000000606097981 */
/* 0x000ee2000c1e1900 */
/*06c0*/ IADD3 R12, R12, -0x1, RZ ; /* 0xffffffff0c0c7810 */
/* 0x000fe20007ffe0ff */
/*06d0*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff057624 */
/* 0x000fe200078e00ff */
/*06e0*/ IADD3 R14, P1, R14, 0x4, RZ ; /* 0x000000040e0e7810 */
/* 0x000fe40007f3e0ff */
/*06f0*/ ISETP.NE.AND P0, PT, R12, RZ, PT ; /* 0x000000ff0c00720c */
/* 0x000fe20003f05270 */
/*0700*/ IMAD.WIDE R4, R5, 0x4, R6 ; /* 0x0000000405047825 */
/* 0x000fc800078e0206 */
/*0710*/ IMAD.MOV.U32 R8, RZ, RZ, R4 ; /* 0x000000ffff087224 */
/* 0x000fe400078e0004 */
/*0720*/ IMAD.MOV.U32 R13, RZ, RZ, R5 ; /* 0x000000ffff0d7224 */
/* 0x000fe400078e0005 */
/*0730*/ IMAD.X R15, RZ, RZ, R15, P1 ; /* 0x000000ffff0f7224 */
/* 0x000fe200008e060f */
/*0740*/ STG.E [R6.64], R11 ; /* 0x0000000b06007986 */
/* 0x0041e8000c101906 */
/*0750*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x0081e2000c101906 */
/*0760*/ @P0 BRA 0x600 ; /* 0xfffffe9000000947 */
/* 0x000fea000383ffff */
/*0770*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0780*/ BRA 0x780; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0790*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0800*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0810*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0820*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0830*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0840*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0850*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0860*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0870*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected batch_sswap
.globl batch_sswap
.p2align 8
.type batch_sswap,@function
batch_sswap:
s_load_b32 s2, s[0:1], 0x4
v_lshl_add_u32 v0, s15, 6, v0
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_cmp_gt_u32_e32 vcc_lo, s2, v0
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_4
s_load_b32 s6, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s6, 1
s_cbranch_scc1 .LBB0_4
s_clause 0x1
s_load_b64 s[4:5], s[0:1], 0x8
s_load_b32 s2, s[0:1], 0x10
v_mov_b32_e32 v1, 0
s_load_b64 s[0:1], s[0:1], 0x18
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
s_ashr_i32 s3, s2, 31
s_lshl_b64 s[4:5], s[2:3], 2
s_delay_alu instid0(VALU_DEP_1)
v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0
.p2align 6
.LBB0_3:
s_load_b32 s3, s[0:1], 0x0
s_add_i32 s6, s6, -1
s_waitcnt lgkmcnt(0)
s_mul_i32 s8, s3, s2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_ashr_i32 s9, s8, 31
s_lshl_b64 s[8:9], s[8:9], 2
s_add_u32 s0, s0, 4
v_add_co_u32 v4, vcc_lo, v0, s8
v_add_co_ci_u32_e32 v5, vcc_lo, s9, v1, vcc_lo
s_addc_u32 s1, s1, 0
s_cmp_lg_u32 s6, 0
global_load_b32 v6, v[4:5], off
global_load_b32 v7, v[2:3], off
s_waitcnt vmcnt(1)
global_store_b32 v[2:3], v6, off
v_add_co_u32 v2, vcc_lo, v2, s4
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
s_waitcnt vmcnt(0)
global_store_b32 v[4:5], v7, off
s_cbranch_scc1 .LBB0_3
.LBB0_4:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel batch_sswap
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 32
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size batch_sswap, .Lfunc_end0-batch_sswap
.section .AMDGPU.csdata,"",@progbits
.text
.protected batch_dswap
.globl batch_dswap
.p2align 8
.type batch_dswap,@function
batch_dswap:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x4
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_u32_e64 s3, v1
s_cbranch_execz .LBB1_4
s_load_b32 s6, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s6, 1
s_cbranch_scc1 .LBB1_4
s_clause 0x1
s_load_b64 s[4:5], s[0:1], 0x8
s_load_b32 s2, s[0:1], 0x10
v_mov_b32_e32 v2, 0
s_load_b64 s[0:1], s[0:1], 0x18
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 3, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
s_ashr_i32 s3, s2, 31
s_lshl_b64 s[4:5], s[2:3], 3
s_delay_alu instid0(VALU_DEP_1)
v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0
.p2align 6
.LBB1_3:
s_load_b32 s3, s[0:1], 0x0
s_add_i32 s6, s6, -1
s_waitcnt lgkmcnt(0)
s_mul_i32 s8, s3, s2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_ashr_i32 s9, s8, 31
s_lshl_b64 s[8:9], s[8:9], 3
s_add_u32 s0, s0, 4
v_add_co_u32 v4, vcc_lo, v0, s8
v_add_co_ci_u32_e32 v5, vcc_lo, s9, v1, vcc_lo
s_addc_u32 s1, s1, 0
s_cmp_lg_u32 s6, 0
global_load_b64 v[6:7], v[4:5], off
global_load_b64 v[8:9], v[2:3], off
s_waitcnt vmcnt(1)
global_store_b64 v[2:3], v[6:7], off
v_add_co_u32 v2, vcc_lo, v2, s4
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
s_waitcnt vmcnt(0)
global_store_b64 v[4:5], v[8:9], off
s_cbranch_scc1 .LBB1_3
.LBB1_4:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel batch_dswap
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 10
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size batch_dswap, .Lfunc_end1-batch_dswap
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 32
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: batch_sswap
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: batch_sswap.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: batch_dswap
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: batch_dswap.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 10
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00151e26_00000000-6_swap.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z36__device_stub__Z11batch_sswapiiPfiPiiiPfiPi
.type _Z36__device_stub__Z11batch_sswapiiPfiPiiiPfiPi, @function
_Z36__device_stub__Z11batch_sswapiiPfiPiiiPfiPi:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movl %esi, 24(%rsp)
movq %rdx, 16(%rsp)
movl %ecx, 12(%rsp)
movq %r8, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq batch_sswap(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z36__device_stub__Z11batch_sswapiiPfiPiiiPfiPi, .-_Z36__device_stub__Z11batch_sswapiiPfiPiiiPfiPi
.globl batch_sswap
.type batch_sswap, @function
batch_sswap:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z36__device_stub__Z11batch_sswapiiPfiPiiiPfiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size batch_sswap, .-batch_sswap
.globl _Z36__device_stub__Z11batch_dswapiiPdiPiiiPdiPi
.type _Z36__device_stub__Z11batch_dswapiiPdiPiiiPdiPi, @function
_Z36__device_stub__Z11batch_dswapiiPdiPiiiPdiPi:
.LFB2053:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movl %esi, 24(%rsp)
movq %rdx, 16(%rsp)
movl %ecx, 12(%rsp)
movq %r8, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq batch_dswap(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2053:
.size _Z36__device_stub__Z11batch_dswapiiPdiPiiiPdiPi, .-_Z36__device_stub__Z11batch_dswapiiPdiPiiiPdiPi
.globl batch_dswap
.type batch_dswap, @function
batch_dswap:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z36__device_stub__Z11batch_dswapiiPdiPiiiPdiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size batch_dswap, .-batch_dswap
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "batch_dswap"
.LC1:
.string "batch_sswap"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2056:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq batch_dswap(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq batch_sswap(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2056:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "swap.hip"
.globl __device_stub__batch_sswap # -- Begin function __device_stub__batch_sswap
.p2align 4, 0x90
.type __device_stub__batch_sswap,@function
__device_stub__batch_sswap: # @__device_stub__batch_sswap
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 12(%rsp)
movl %esi, 8(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 4(%rsp)
movq %r8, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 8(%rsp), %rax
movq %rax, 88(%rsp)
leaq 72(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 64(%rsp), %rax
movq %rax, 112(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $batch_sswap, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size __device_stub__batch_sswap, .Lfunc_end0-__device_stub__batch_sswap
.cfi_endproc
# -- End function
.globl __device_stub__batch_dswap # -- Begin function __device_stub__batch_dswap
.p2align 4, 0x90
.type __device_stub__batch_dswap,@function
__device_stub__batch_dswap: # @__device_stub__batch_dswap
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 12(%rsp)
movl %esi, 8(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 4(%rsp)
movq %r8, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 8(%rsp), %rax
movq %rax, 88(%rsp)
leaq 72(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 64(%rsp), %rax
movq %rax, 112(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $batch_dswap, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end1:
.size __device_stub__batch_dswap, .Lfunc_end1-__device_stub__batch_dswap
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $batch_sswap, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $batch_dswap, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type batch_sswap,@object # @batch_sswap
.section .rodata,"a",@progbits
.globl batch_sswap
.p2align 3, 0x0
batch_sswap:
.quad __device_stub__batch_sswap
.size batch_sswap, 8
.type batch_dswap,@object # @batch_dswap
.globl batch_dswap
.p2align 3, 0x0
batch_dswap:
.quad __device_stub__batch_dswap
.size batch_dswap, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "batch_sswap"
.size .L__unnamed_1, 12
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "batch_dswap"
.size .L__unnamed_2, 12
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub__batch_sswap
.addrsig_sym __device_stub__batch_dswap
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym batch_sswap
.addrsig_sym batch_dswap
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | extern __device__ int file2_func(int);
int __device__ file1_func(int x)
{
return file2_func(x);
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | extern __device__ int file2_func(int);
int __device__ file1_func(int x)
{
return file2_func(x);
} | .file "tmpxft_0007257e_00000000-6_file1.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z10file1_funci
.type _Z10file1_funci, @function
_Z10file1_funci:
.LFB2027:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2027:
.size _Z10file1_funci, .-_Z10file1_funci
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | extern __device__ int file2_func(int);
int __device__ file1_func(int x)
{
return file2_func(x);
} | #include <hip/hip_runtime.h>
extern __device__ int file2_func(int);
int __device__ file1_func(int x)
{
return file2_func(x);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
extern __device__ int file2_func(int);
int __device__ file1_func(int x)
{
return file2_func(x);
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
extern __device__ int file2_func(int);
int __device__ file1_func(int x)
{
return file2_func(x);
} | .text
.file "file1.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0007257e_00000000-6_file1.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z10file1_funci
.type _Z10file1_funci, @function
_Z10file1_funci:
.LFB2027:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2027:
.size _Z10file1_funci, .-_Z10file1_funci
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "file1.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void RecurrentWeightsRTRLDerivativesKernel( float *previousHiddenActivations, float *hiddenActivationDerivatives, float *recurrentWeights, float *recurrentWeightRTRLDerivatives, float *previousRecurrentWeightRTRLDerivatives )
{
int partialId = blockDim.x*blockIdx.y*gridDim.x //rows preceeding current row in grid
+ blockDim.x*blockIdx.x //blocks preceeding current block
+ threadIdx.x;
if (partialId < D_HIDDEN_UNITS * D_HIDDEN_UNITS * D_HIDDEN_UNITS)
{
int unitId = partialId / (D_HIDDEN_UNITS * D_HIDDEN_UNITS);
int weightId = partialId % (D_HIDDEN_UNITS * D_HIDDEN_UNITS);
int to = weightId / D_HIDDEN_UNITS;
int from = weightId % D_HIDDEN_UNITS;
float sum = 0;
for (int i = 0; i < D_HIDDEN_UNITS; i++)
{
sum += recurrentWeights[unitId * D_HIDDEN_UNITS + i] * previousRecurrentWeightRTRLDerivatives[i * (D_HIDDEN_UNITS * D_HIDDEN_UNITS) + weightId];
}
recurrentWeightRTRLDerivatives[partialId] = hiddenActivationDerivatives[unitId] * ((unitId == to) * previousHiddenActivations[from] + sum);
}
} | code for sm_80
Function : _Z37RecurrentWeightsRTRLDerivativesKernelPfS_S_S_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e220000002600 */
/*0020*/ IMAD.MOV.U32 R8, RZ, RZ, c[0x3][0x0] ; /* 0x00c00000ff087624 */
/* 0x000fc600078e00ff */
/*0030*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e220000002500 */
/*0040*/ IMAD R7, R8, c[0x3][0x0], RZ ; /* 0x00c0000008077a24 */
/* 0x000fc600078e02ff */
/*0050*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0060*/ IMAD R0, R0, c[0x0][0xc], R3 ; /* 0x0000030000007a24 */
/* 0x001fe400078e0203 */
/*0070*/ IMAD R3, R7, c[0x3][0x0], RZ ; /* 0x00c0000007037a24 */
/* 0x000fe400078e02ff */
/*0080*/ IMAD R0, R0, c[0x0][0x0], R5 ; /* 0x0000000000007a24 */
/* 0x002fca00078e0205 */
/*0090*/ ISETP.GE.AND P0, PT, R0, R3, PT ; /* 0x000000030000720c */
/* 0x000fda0003f06270 */
/*00a0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00b0*/ IABS R5, R7.reuse ; /* 0x0000000700057213 */
/* 0x080fe20000000000 */
/*00c0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00d0*/ IABS R10, R0 ; /* 0x00000000000a7213 */
/* 0x000fe40000000000 */
/*00e0*/ I2F.RP R4, R5 ; /* 0x0000000500047306 */
/* 0x000e220000209400 */
/*00f0*/ IABS R11, R7 ; /* 0x00000007000b7213 */
/* 0x000fce0000000000 */
/*0100*/ MUFU.RCP R4, R4 ; /* 0x0000000400047308 */
/* 0x001e240000001000 */
/*0110*/ IADD3 R2, R4, 0xffffffe, RZ ; /* 0x0ffffffe04027810 */
/* 0x001fcc0007ffe0ff */
/*0120*/ F2I.FTZ.U32.TRUNC.NTZ R3, R2 ; /* 0x0000000200037305 */
/* 0x000064000021f000 */
/*0130*/ HFMA2.MMA R2, -RZ, RZ, 0, 0 ; /* 0x00000000ff027435 */
/* 0x001fe200000001ff */
/*0140*/ IADD3 R6, RZ, -R3, RZ ; /* 0x80000003ff067210 */
/* 0x002fca0007ffe0ff */
/*0150*/ IMAD R9, R6, R5, RZ ; /* 0x0000000506097224 */
/* 0x000fe400078e02ff */
/*0160*/ IMAD.MOV.U32 R6, RZ, RZ, R10 ; /* 0x000000ffff067224 */
/* 0x000fe400078e000a */
/*0170*/ IMAD.HI.U32 R3, R3, R9, R2 ; /* 0x0000000903037227 */
/* 0x000fc800078e0002 */
/*0180*/ IMAD.MOV R9, RZ, RZ, -R11 ; /* 0x000000ffff097224 */
/* 0x000fe400078e0a0b */
/*0190*/ IMAD.HI.U32 R4, R3, R6, RZ ; /* 0x0000000603047227 */
/* 0x000fc800078e00ff */
/*01a0*/ IMAD R2, R4, R9, R6 ; /* 0x0000000904027224 */
/* 0x000fca00078e0206 */
/*01b0*/ ISETP.GT.U32.AND P2, PT, R5, R2, PT ; /* 0x000000020500720c */
/* 0x000fda0003f44070 */
/*01c0*/ @!P2 IADD3 R2, R2, -R5.reuse, RZ ; /* 0x800000050202a210 */
/* 0x080fe40007ffe0ff */
/*01d0*/ @!P2 IADD3 R4, R4, 0x1, RZ ; /* 0x000000010404a810 */
/* 0x000fe40007ffe0ff */
/*01e0*/ ISETP.GE.U32.AND P0, PT, R2, R5, PT ; /* 0x000000050200720c */
/* 0x000fe20003f06070 */
/*01f0*/ IMAD.MOV.U32 R5, RZ, RZ, RZ ; /* 0x000000ffff057224 */
/* 0x000fe200078e00ff */
/*0200*/ LOP3.LUT R2, R0, R7, RZ, 0x3c, !PT ; /* 0x0000000700027212 */
/* 0x000fe400078e3cff */
/*0210*/ ISETP.NE.AND P2, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fe40003f45270 */
/*0220*/ ISETP.GE.AND P1, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fce0003f26270 */
/*0230*/ @P0 IADD3 R4, R4, 0x1, RZ ; /* 0x0000000104040810 */
/* 0x000fe40007ffe0ff */
/*0240*/ ISETP.GE.AND P0, PT, R8, 0x1, PT ; /* 0x000000010800780c */
/* 0x000fc80003f06270 */
/*0250*/ @!P1 IMAD.MOV R4, RZ, RZ, -R4 ; /* 0x000000ffff049224 */
/* 0x000fe200078e0a04 */
/*0260*/ @!P2 LOP3.LUT R4, RZ, R7, RZ, 0x33, !PT ; /* 0x00000007ff04a212 */
/* 0x000fc800078e33ff */
/*0270*/ IADD3 R6, -R4, RZ, RZ ; /* 0x000000ff04067210 */
/* 0x000fca0007ffe1ff */
/*0280*/ IMAD R6, R7, R6, R0 ; /* 0x0000000607067224 */
/* 0x000fe200078e0200 */
/*0290*/ @!P0 BRA 0x600 ; /* 0x0000036000008947 */
/* 0x000fea0003800000 */
/*02a0*/ IADD3 R2, R8.reuse, -0x1, RZ ; /* 0xffffffff08027810 */
/* 0x040fe20007ffe0ff */
/*02b0*/ IMAD.MOV.U32 R17, RZ, RZ, RZ ; /* 0x000000ffff117224 */
/* 0x000fe200078e00ff */
/*02c0*/ LOP3.LUT R8, R8, 0x3, RZ, 0xc0, !PT ; /* 0x0000000308087812 */
/* 0x000fe400078ec0ff */
/*02d0*/ ISETP.GE.U32.AND P1, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fe40003f26070 */
/*02e0*/ ISETP.NE.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fe40003f05270 */
/*02f0*/ MOV R5, RZ ; /* 0x000000ff00057202 */
/* 0x000fd20000000f00 */
/*0300*/ @!P1 BRA 0x4f0 ; /* 0x000001e000009947 */
/* 0x000fea0003800000 */
/*0310*/ HFMA2.MMA R9, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff097435 */
/* 0x000fe200000001ff */
/*0320*/ IMAD R2, R4, c[0x3][0x0], RZ ; /* 0x00c0000004027a24 */
/* 0x000fe200078e02ff */
/*0330*/ IADD3 R16, R8, -c[0x3][0x0], RZ ; /* 0x80c0000008107a10 */
/* 0x000fe20007ffe0ff */
/*0340*/ IMAD.MOV.U32 R5, RZ, RZ, RZ ; /* 0x000000ffff057224 */
/* 0x000fe200078e00ff */
/*0350*/ MOV R17, RZ ; /* 0x000000ff00117202 */
/* 0x000fe20000000f00 */
/*0360*/ IMAD.MOV.U32 R18, RZ, RZ, R6 ; /* 0x000000ffff127224 */
/* 0x000fca00078e0006 */
/*0370*/ IMAD.WIDE R2, R2, R9, c[0x0][0x170] ; /* 0x00005c0002027625 */
/* 0x000fc800078e0209 */
/*0380*/ IMAD.WIDE R20, R18, R9, c[0x0][0x180] ; /* 0x0000600012147625 */
/* 0x000fe200078e0209 */
/*0390*/ LDG.E R19, [R2.64] ; /* 0x0000000402137981 */
/* 0x0000a8000c1e1900 */
/*03a0*/ LDG.E R22, [R2.64+0x4] ; /* 0x0000040402167981 */
/* 0x0000e2000c1e1900 */
/*03b0*/ IMAD.WIDE R10, R7, 0x4, R20 ; /* 0x00000004070a7825 */
/* 0x000fc600078e0214 */
/*03c0*/ LDG.E R20, [R20.64] ; /* 0x0000000414147981 */
/* 0x000ea6000c1e1900 */
/*03d0*/ IMAD.WIDE R12, R7.reuse, 0x4, R10 ; /* 0x00000004070c7825 */
/* 0x040fe200078e020a */
/*03e0*/ LDG.E R23, [R2.64+0x8] ; /* 0x0000080402177981 */
/* 0x000128000c1e1900 */
/*03f0*/ LDG.E R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x000ee2000c1e1900 */
/*0400*/ IMAD.WIDE R14, R7, 0x4, R12 ; /* 0x00000004070e7825 */
/* 0x000fc600078e020c */
/*0410*/ LDG.E R12, [R12.64] ; /* 0x000000040c0c7981 */
/* 0x000f28000c1e1900 */
/*0420*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000f68000c1e1900 */
/*0430*/ LDG.E R24, [R2.64+0xc] ; /* 0x00000c0402187981 */
/* 0x000162000c1e1900 */
/*0440*/ IADD3 R17, R17, 0x4, RZ ; /* 0x0000000411117810 */
/* 0x000fe40007ffe0ff */
/*0450*/ LEA R18, R7, R18, 0x2 ; /* 0x0000001207127211 */
/* 0x000fc400078e10ff */
/*0460*/ IADD3 R2, P2, R2, 0x10, RZ ; /* 0x0000001002027810 */
/* 0x001fca0007f5e0ff */
/*0470*/ IMAD.X R3, RZ, RZ, R3, P2 ; /* 0x000000ffff037224 */
/* 0x000fe400010e0603 */
/*0480*/ FFMA R19, R20, R19, R5 ; /* 0x0000001314137223 */
/* 0x004fe20000000005 */
/*0490*/ IADD3 R5, R16, R17, RZ ; /* 0x0000001110057210 */
/* 0x000fc80007ffe0ff */
/*04a0*/ ISETP.NE.AND P1, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe20003f25270 */
/*04b0*/ FFMA R19, R10, R22, R19 ; /* 0x000000160a137223 */
/* 0x008fc80000000013 */
/*04c0*/ FFMA R19, R12, R23, R19 ; /* 0x000000170c137223 */
/* 0x010fc80000000013 */
/*04d0*/ FFMA R5, R14, R24, R19 ; /* 0x000000180e057223 */
/* 0x020fc80000000013 */
/*04e0*/ @P1 BRA 0x380 ; /* 0xfffffe9000001947 */
/* 0x000fea000383ffff */
/*04f0*/ @!P0 BRA 0x600 ; /* 0x0000010000008947 */
/* 0x000fea0003800000 */
/*0500*/ IMAD.MOV.U32 R13, RZ, RZ, 0x4 ; /* 0x00000004ff0d7424 */
/* 0x000fe400078e00ff */
/*0510*/ IMAD R2, R4, c[0x3][0x0], R17 ; /* 0x00c0000004027a24 */
/* 0x000fe400078e0211 */
/*0520*/ IMAD R12, R7, R17, R6 ; /* 0x00000011070c7224 */
/* 0x000fe400078e0206 */
/*0530*/ IMAD.WIDE R2, R2, R13, c[0x0][0x170] ; /* 0x00005c0002027625 */
/* 0x000fc800078e020d */
/*0540*/ IMAD.MOV.U32 R11, RZ, RZ, R3 ; /* 0x000000ffff0b7224 */
/* 0x000fe200078e0003 */
/*0550*/ MOV R10, R2 ; /* 0x00000002000a7202 */
/* 0x000fc80000000f00 */
/*0560*/ IMAD.WIDE R2, R12, R13, c[0x0][0x180] ; /* 0x000060000c027625 */
/* 0x000fe200078e020d */
/*0570*/ LDG.E R9, [R10.64] ; /* 0x000000040a097981 */
/* 0x0000aa000c1e1900 */
/*0580*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*0590*/ IADD3 R8, R8, -0x1, RZ ; /* 0xffffffff08087810 */
/* 0x000fc80007ffe0ff */
/*05a0*/ ISETP.NE.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fe40003f05270 */
/*05b0*/ IADD3 R10, P1, R10, 0x4, RZ ; /* 0x000000040a0a7810 */
/* 0x001fe40007f3e0ff */
/*05c0*/ IADD3 R12, R7, R12, RZ ; /* 0x0000000c070c7210 */
/* 0x000fc60007ffe0ff */
/*05d0*/ IMAD.X R11, RZ, RZ, R11, P1 ; /* 0x000000ffff0b7224 */
/* 0x000fe400008e060b */
/*05e0*/ FFMA R5, R2, R9, R5 ; /* 0x0000000902057223 */
/* 0x004fc80000000005 */
/*05f0*/ @P0 BRA 0x560 ; /* 0xffffff6000000947 */
/* 0x000fea000383ffff */
/*0600*/ IABS R8, c[0x3][0x0] ; /* 0x00c0000000087a13 */
/* 0x000fe40000000000 */
/*0610*/ IABS R10, R6 ; /* 0x00000006000a7213 */
/* 0x000fe40000000000 */
/*0620*/ I2F.RP R7, R8 ; /* 0x0000000800077306 */
/* 0x000e220000209400 */
/*0630*/ MOV R11, 0x4 ; /* 0x00000004000b7802 */
/* 0x000fce0000000f00 */
/*0640*/ MUFU.RCP R7, R7 ; /* 0x0000000700077308 */
/* 0x001e240000001000 */
/*0650*/ IADD3 R2, R7, 0xffffffe, RZ ; /* 0x0ffffffe07027810 */
/* 0x001fcc0007ffe0ff */
/*0660*/ F2I.FTZ.U32.TRUNC.NTZ R3, R2 ; /* 0x0000000200037305 */
/* 0x000064000021f000 */
/*0670*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x001fe200078e00ff */
/*0680*/ IADD3 R9, RZ, -R3, RZ ; /* 0x80000003ff097210 */
/* 0x002fca0007ffe0ff */
/*0690*/ IMAD R9, R9, R8, RZ ; /* 0x0000000809097224 */
/* 0x000fc800078e02ff */
/*06a0*/ IMAD.HI.U32 R3, R3, R9, R2 ; /* 0x0000000903037227 */
/* 0x000fe200078e0002 */
/*06b0*/ MOV R9, R10 ; /* 0x0000000a00097202 */
/* 0x000fe40000000f00 */
/*06c0*/ LOP3.LUT R2, R6, c[0x3][0x0], RZ, 0x3c, !PT ; /* 0x00c0000006027a12 */
/* 0x000fc600078e3cff */
/*06d0*/ IMAD.HI.U32 R3, R3, R9, RZ ; /* 0x0000000903037227 */
/* 0x000fe200078e00ff */
/*06e0*/ ISETP.GE.AND P1, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fc60003f26270 */
/*06f0*/ IMAD.MOV R7, RZ, RZ, -R3 ; /* 0x000000ffff077224 */
/* 0x000fc800078e0a03 */
/*0700*/ IMAD R7, R8, R7, R9 ; /* 0x0000000708077224 */
/* 0x000fca00078e0209 */
/*0710*/ ISETP.GT.U32.AND P2, PT, R8, R7, PT ; /* 0x000000070800720c */
/* 0x000fda0003f44070 */
/*0720*/ @!P2 IADD3 R7, R7, -R8.reuse, RZ ; /* 0x800000080707a210 */
/* 0x080fe40007ffe0ff */
/*0730*/ @!P2 IADD3 R3, R3, 0x1, RZ ; /* 0x000000010303a810 */
/* 0x000fe40007ffe0ff */
/*0740*/ ISETP.GE.U32.AND P0, PT, R7, R8, PT ; /* 0x000000080700720c */
/* 0x000fe40003f06070 */
/*0750*/ ISETP.NE.AND P2, PT, RZ, c[0x3][0x0], PT ; /* 0x00c00000ff007a0c */
/* 0x000fd60003f45270 */
/*0760*/ @P0 IADD3 R3, R3, 0x1, RZ ; /* 0x0000000103030810 */
/* 0x000fca0007ffe0ff */
/*0770*/ IMAD.MOV.U32 R9, RZ, RZ, R3 ; /* 0x000000ffff097224 */
/* 0x000fca00078e0003 */
/*0780*/ @!P1 IADD3 R9, -R9, RZ, RZ ; /* 0x000000ff09099210 */
/* 0x000fe40007ffe1ff */
/*0790*/ @!P2 LOP3.LUT R9, RZ, c[0x3][0x0], RZ, 0x33, !PT ; /* 0x00c00000ff09aa12 */
/* 0x000fca00078e33ff */
/*07a0*/ IMAD.MOV R3, RZ, RZ, -R9 ; /* 0x000000ffff037224 */
/* 0x000fc800078e0a09 */
/*07b0*/ IMAD R2, R3, c[0x3][0x0], R6 ; /* 0x00c0000003027a24 */
/* 0x000fe400078e0206 */
/*07c0*/ IMAD.WIDE R6, R4, R11, c[0x0][0x168] ; /* 0x00005a0004067625 */
/* 0x000fc800078e020b */
/*07d0*/ IMAD.WIDE R2, R2, R11, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fe400078e020b */
/*07e0*/ LDG.E R7, [R6.64] ; /* 0x0000000406077981 */
/* 0x000ea8000c1e1900 */
/*07f0*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ee2000c1e1900 */
/*0800*/ ISETP.NE.AND P0, PT, R4, R9, PT ; /* 0x000000090400720c */
/* 0x000fc80003f05270 */
/*0810*/ FSEL R4, RZ, 1, P0 ; /* 0x3f800000ff047808 */
/* 0x000fca0000000000 */
/*0820*/ FFMA R8, R4, R2, R5 ; /* 0x0000000204087223 */
/* 0x008fe40000000005 */
/*0830*/ IMAD.WIDE R4, R0, R11, c[0x0][0x178] ; /* 0x00005e0000047625 */
/* 0x000fc800078e020b */
/*0840*/ FMUL R9, R8, R7 ; /* 0x0000000708097220 */
/* 0x004fca0000400000 */
/*0850*/ STG.E [R4.64], R9 ; /* 0x0000000904007986 */
/* 0x000fe2000c101904 */
/*0860*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0870*/ BRA 0x870; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0880*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0890*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void RecurrentWeightsRTRLDerivativesKernel( float *previousHiddenActivations, float *hiddenActivationDerivatives, float *recurrentWeights, float *recurrentWeightRTRLDerivatives, float *previousRecurrentWeightRTRLDerivatives )
{
int partialId = blockDim.x*blockIdx.y*gridDim.x //rows preceeding current row in grid
+ blockDim.x*blockIdx.x //blocks preceeding current block
+ threadIdx.x;
if (partialId < D_HIDDEN_UNITS * D_HIDDEN_UNITS * D_HIDDEN_UNITS)
{
int unitId = partialId / (D_HIDDEN_UNITS * D_HIDDEN_UNITS);
int weightId = partialId % (D_HIDDEN_UNITS * D_HIDDEN_UNITS);
int to = weightId / D_HIDDEN_UNITS;
int from = weightId % D_HIDDEN_UNITS;
float sum = 0;
for (int i = 0; i < D_HIDDEN_UNITS; i++)
{
sum += recurrentWeights[unitId * D_HIDDEN_UNITS + i] * previousRecurrentWeightRTRLDerivatives[i * (D_HIDDEN_UNITS * D_HIDDEN_UNITS) + weightId];
}
recurrentWeightRTRLDerivatives[partialId] = hiddenActivationDerivatives[unitId] * ((unitId == to) * previousHiddenActivations[from] + sum);
}
} | .file "tmpxft_001712c2_00000000-6_RecurrentWeightsRTRLDerivativesKernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z65__device_stub__Z37RecurrentWeightsRTRLDerivativesKernelPfS_S_S_S_PfS_S_S_S_
.type _Z65__device_stub__Z37RecurrentWeightsRTRLDerivativesKernelPfS_S_S_S_PfS_S_S_S_, @function
_Z65__device_stub__Z37RecurrentWeightsRTRLDerivativesKernelPfS_S_S_S_PfS_S_S_S_:
.LFB2051:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movq %r8, 8(%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 184
pushq 56(%rsp)
.cfi_def_cfa_offset 192
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z37RecurrentWeightsRTRLDerivativesKernelPfS_S_S_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z65__device_stub__Z37RecurrentWeightsRTRLDerivativesKernelPfS_S_S_S_PfS_S_S_S_, .-_Z65__device_stub__Z37RecurrentWeightsRTRLDerivativesKernelPfS_S_S_S_PfS_S_S_S_
.globl _Z37RecurrentWeightsRTRLDerivativesKernelPfS_S_S_S_
.type _Z37RecurrentWeightsRTRLDerivativesKernelPfS_S_S_S_, @function
_Z37RecurrentWeightsRTRLDerivativesKernelPfS_S_S_S_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z65__device_stub__Z37RecurrentWeightsRTRLDerivativesKernelPfS_S_S_S_PfS_S_S_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z37RecurrentWeightsRTRLDerivativesKernelPfS_S_S_S_, .-_Z37RecurrentWeightsRTRLDerivativesKernelPfS_S_S_S_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z37RecurrentWeightsRTRLDerivativesKernelPfS_S_S_S_"
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "D_HIDDEN_UNITS"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z37RecurrentWeightsRTRLDerivativesKernelPfS_S_S_S_(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $4, %r9d
movl $0, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _ZL14D_HIDDEN_UNITS(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL14D_HIDDEN_UNITS
.comm _ZL14D_HIDDEN_UNITS,4,4
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void RecurrentWeightsRTRLDerivativesKernel( float *previousHiddenActivations, float *hiddenActivationDerivatives, float *recurrentWeights, float *recurrentWeightRTRLDerivatives, float *previousRecurrentWeightRTRLDerivatives )
{
int partialId = blockDim.x*blockIdx.y*gridDim.x //rows preceeding current row in grid
+ blockDim.x*blockIdx.x //blocks preceeding current block
+ threadIdx.x;
if (partialId < D_HIDDEN_UNITS * D_HIDDEN_UNITS * D_HIDDEN_UNITS)
{
int unitId = partialId / (D_HIDDEN_UNITS * D_HIDDEN_UNITS);
int weightId = partialId % (D_HIDDEN_UNITS * D_HIDDEN_UNITS);
int to = weightId / D_HIDDEN_UNITS;
int from = weightId % D_HIDDEN_UNITS;
float sum = 0;
for (int i = 0; i < D_HIDDEN_UNITS; i++)
{
sum += recurrentWeights[unitId * D_HIDDEN_UNITS + i] * previousRecurrentWeightRTRLDerivatives[i * (D_HIDDEN_UNITS * D_HIDDEN_UNITS) + weightId];
}
recurrentWeightRTRLDerivatives[partialId] = hiddenActivationDerivatives[unitId] * ((unitId == to) * previousHiddenActivations[from] + sum);
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void RecurrentWeightsRTRLDerivativesKernel( float *previousHiddenActivations, float *hiddenActivationDerivatives, float *recurrentWeights, float *recurrentWeightRTRLDerivatives, float *previousRecurrentWeightRTRLDerivatives )
{
int partialId = blockDim.x*blockIdx.y*gridDim.x //rows preceeding current row in grid
+ blockDim.x*blockIdx.x //blocks preceeding current block
+ threadIdx.x;
if (partialId < D_HIDDEN_UNITS * D_HIDDEN_UNITS * D_HIDDEN_UNITS)
{
int unitId = partialId / (D_HIDDEN_UNITS * D_HIDDEN_UNITS);
int weightId = partialId % (D_HIDDEN_UNITS * D_HIDDEN_UNITS);
int to = weightId / D_HIDDEN_UNITS;
int from = weightId % D_HIDDEN_UNITS;
float sum = 0;
for (int i = 0; i < D_HIDDEN_UNITS; i++)
{
sum += recurrentWeights[unitId * D_HIDDEN_UNITS + i] * previousRecurrentWeightRTRLDerivatives[i * (D_HIDDEN_UNITS * D_HIDDEN_UNITS) + weightId];
}
recurrentWeightRTRLDerivatives[partialId] = hiddenActivationDerivatives[unitId] * ((unitId == to) * previousHiddenActivations[from] + sum);
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void RecurrentWeightsRTRLDerivativesKernel( float *previousHiddenActivations, float *hiddenActivationDerivatives, float *recurrentWeights, float *recurrentWeightRTRLDerivatives, float *previousRecurrentWeightRTRLDerivatives )
{
int partialId = blockDim.x*blockIdx.y*gridDim.x //rows preceeding current row in grid
+ blockDim.x*blockIdx.x //blocks preceeding current block
+ threadIdx.x;
if (partialId < D_HIDDEN_UNITS * D_HIDDEN_UNITS * D_HIDDEN_UNITS)
{
int unitId = partialId / (D_HIDDEN_UNITS * D_HIDDEN_UNITS);
int weightId = partialId % (D_HIDDEN_UNITS * D_HIDDEN_UNITS);
int to = weightId / D_HIDDEN_UNITS;
int from = weightId % D_HIDDEN_UNITS;
float sum = 0;
for (int i = 0; i < D_HIDDEN_UNITS; i++)
{
sum += recurrentWeights[unitId * D_HIDDEN_UNITS + i] * previousRecurrentWeightRTRLDerivatives[i * (D_HIDDEN_UNITS * D_HIDDEN_UNITS) + weightId];
}
recurrentWeightRTRLDerivatives[partialId] = hiddenActivationDerivatives[unitId] * ((unitId == to) * previousHiddenActivations[from] + sum);
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z37RecurrentWeightsRTRLDerivativesKernelPfS_S_S_S_
.globl _Z37RecurrentWeightsRTRLDerivativesKernelPfS_S_S_S_
.p2align 8
.type _Z37RecurrentWeightsRTRLDerivativesKernelPfS_S_S_S_,@function
_Z37RecurrentWeightsRTRLDerivativesKernelPfS_S_S_S_:
s_clause 0x1
s_load_b32 s5, s[0:1], 0x28
s_load_b32 s6, s[0:1], 0x34
s_getpc_b64 s[2:3]
s_add_u32 s2, s2, D_HIDDEN_UNITS@rel32@lo+4
s_addc_u32 s3, s3, D_HIDDEN_UNITS@rel32@hi+12
s_load_b32 s4, s[2:3], 0x0
s_waitcnt lgkmcnt(0)
s_mul_i32 s2, s5, s15
s_and_b32 s3, s6, 0xffff
s_add_i32 s2, s2, s14
s_mul_i32 s5, s4, s4
v_mad_u64_u32 v[1:2], null, s2, s3, v[0:1]
s_mul_i32 s2, s5, s4
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_cmp_gt_i32_e32 vcc_lo, s2, v1
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_6
v_cvt_f32_u32_e32 v0, s5
s_sub_i32 s2, 0, s5
v_ashrrev_i32_e32 v3, 31, v1
s_ashr_i32 s6, s4, 31
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v0, v0
v_add_nc_u32_e32 v4, v1, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_xor_b32_e32 v4, v4, v3
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v0, 0x4f7ffffe, v0
v_cvt_u32_f32_e32 v0, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_mul_lo_u32 v2, s2, v0
s_add_i32 s2, s4, s6
s_xor_b32 s7, s2, s6
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
s_sub_i32 s2, 0, s7
s_cmp_lt_i32 s4, 1
v_mul_hi_u32 v2, v0, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v0, v0, v2
v_mul_hi_u32 v0, v4, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v2, v0, s5
v_sub_nc_u32_e32 v2, v4, v2
v_add_nc_u32_e32 v4, 1, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_subrev_nc_u32_e32 v5, s5, v2
v_cmp_le_u32_e32 vcc_lo, s5, v2
v_cndmask_b32_e32 v0, v0, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_cndmask_b32_e32 v2, v2, v5, vcc_lo
v_cvt_f32_u32_e32 v5, s7
v_add_nc_u32_e32 v4, 1, v0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_le_u32_e32 vcc_lo, s5, v2
v_cndmask_b32_e32 v0, v0, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v4, v5
v_xor_b32_e32 v0, v0, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v2, v0, v3
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v0, 0x4f7ffffe, v4
v_mul_lo_u32 v3, v2, s5
v_cvt_u32_f32_e32 v0, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_mul_lo_u32 v4, s2, v0
v_sub_nc_u32_e32 v9, v1, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_ashrrev_i32_e32 v10, 31, v9
v_mul_hi_u32 v3, v0, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v4, v9, v10
v_add_nc_u32_e32 v0, v0, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_xor_b32_e32 v11, v4, v10
v_mad_u64_u32 v[3:4], null, v11, v0, 0
s_cbranch_scc1 .LBB0_4
s_clause 0x1
s_load_b64 s[8:9], s[0:1], 0x10
s_load_b64 s[2:3], s[0:1], 0x20
v_mul_lo_u32 v5, v2, s4
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v7, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v6, 31, v5
v_lshlrev_b64 v[5:6], 2, v[5:6]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v5, vcc_lo, s8, v5
v_add_co_ci_u32_e32 v6, vcc_lo, s9, v6, vcc_lo
s_mov_b32 s8, s4
.p2align 6
.LBB0_3:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_ashrrev_i32_e32 v8, 31, v7
s_add_i32 s8, s8, -1
s_cmp_eq_u32 s8, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[12:13], 2, v[7:8]
v_add_co_u32 v12, vcc_lo, s2, v12
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v13, vcc_lo, s3, v13, vcc_lo
global_load_b32 v3, v[5:6], off
global_load_b32 v8, v[12:13], off
v_add_co_u32 v5, vcc_lo, v5, 4
v_add_co_ci_u32_e32 v6, vcc_lo, 0, v6, vcc_lo
s_waitcnt vmcnt(0)
v_dual_fmac_f32 v0, v3, v8 :: v_dual_add_nc_u32 v7, s5, v7
s_cbranch_scc0 .LBB0_3
s_branch .LBB0_5
.LBB0_4:
v_mov_b32_e32 v0, 0
.LBB0_5:
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_lo_u32 v3, v4, s7
v_add_nc_u32_e32 v5, 1, v4
v_sub_nc_u32_e32 v3, v11, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v6, s7, v3
v_cmp_le_u32_e32 vcc_lo, s7, v3
v_dual_cndmask_b32 v4, v4, v5 :: v_dual_cndmask_b32 v3, v3, v6
v_xor_b32_e32 v6, s6, v10
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_nc_u32_e32 v5, 1, v4
v_cmp_le_u32_e32 vcc_lo, s7, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v3, v4, v5, vcc_lo
v_xor_b32_e32 v3, v3, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v8, v3, v6
v_mul_lo_u32 v3, v8, s4
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x18
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v4, v9, v3
v_ashrrev_i32_e32 v3, 31, v2
v_ashrrev_i32_e32 v5, 31, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[6:7], 2, v[2:3]
v_lshlrev_b64 v[4:5], 2, v[4:5]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v3, vcc_lo, s4, v4
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_4)
v_add_co_u32 v5, vcc_lo, s6, v6
v_add_co_ci_u32_e32 v6, vcc_lo, s7, v7, vcc_lo
global_load_b32 v3, v[3:4], off
global_load_b32 v4, v[5:6], off
v_cmp_eq_u32_e32 vcc_lo, v2, v8
v_ashrrev_i32_e32 v2, 31, v1
v_cndmask_b32_e64 v5, 0, 1.0, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_waitcnt vmcnt(1)
v_fmac_f32_e32 v0, v3, v5
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_mul_f32_e32 v3, v4, v0
v_add_co_u32 v0, vcc_lo, s0, v1
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v2, vcc_lo
global_store_b32 v[0:1], v3, off
.LBB0_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z37RecurrentWeightsRTRLDerivativesKernelPfS_S_S_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 14
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z37RecurrentWeightsRTRLDerivativesKernelPfS_S_S_S_, .Lfunc_end0-_Z37RecurrentWeightsRTRLDerivativesKernelPfS_S_S_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.protected D_HIDDEN_UNITS
.type D_HIDDEN_UNITS,@object
.section .bss,"aw",@nobits
.globl D_HIDDEN_UNITS
.p2align 2, 0x0
D_HIDDEN_UNITS:
.long 0
.size D_HIDDEN_UNITS, 4
.type __hip_cuid_,@object
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym D_HIDDEN_UNITS
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z37RecurrentWeightsRTRLDerivativesKernelPfS_S_S_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z37RecurrentWeightsRTRLDerivativesKernelPfS_S_S_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 14
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void RecurrentWeightsRTRLDerivativesKernel( float *previousHiddenActivations, float *hiddenActivationDerivatives, float *recurrentWeights, float *recurrentWeightRTRLDerivatives, float *previousRecurrentWeightRTRLDerivatives )
{
int partialId = blockDim.x*blockIdx.y*gridDim.x //rows preceeding current row in grid
+ blockDim.x*blockIdx.x //blocks preceeding current block
+ threadIdx.x;
if (partialId < D_HIDDEN_UNITS * D_HIDDEN_UNITS * D_HIDDEN_UNITS)
{
int unitId = partialId / (D_HIDDEN_UNITS * D_HIDDEN_UNITS);
int weightId = partialId % (D_HIDDEN_UNITS * D_HIDDEN_UNITS);
int to = weightId / D_HIDDEN_UNITS;
int from = weightId % D_HIDDEN_UNITS;
float sum = 0;
for (int i = 0; i < D_HIDDEN_UNITS; i++)
{
sum += recurrentWeights[unitId * D_HIDDEN_UNITS + i] * previousRecurrentWeightRTRLDerivatives[i * (D_HIDDEN_UNITS * D_HIDDEN_UNITS) + weightId];
}
recurrentWeightRTRLDerivatives[partialId] = hiddenActivationDerivatives[unitId] * ((unitId == to) * previousHiddenActivations[from] + sum);
}
} | .text
.file "RecurrentWeightsRTRLDerivativesKernel.hip"
.globl _Z52__device_stub__RecurrentWeightsRTRLDerivativesKernelPfS_S_S_S_ # -- Begin function _Z52__device_stub__RecurrentWeightsRTRLDerivativesKernelPfS_S_S_S_
.p2align 4, 0x90
.type _Z52__device_stub__RecurrentWeightsRTRLDerivativesKernelPfS_S_S_S_,@function
_Z52__device_stub__RecurrentWeightsRTRLDerivativesKernelPfS_S_S_S_: # @_Z52__device_stub__RecurrentWeightsRTRLDerivativesKernelPfS_S_S_S_
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z37RecurrentWeightsRTRLDerivativesKernelPfS_S_S_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end0:
.size _Z52__device_stub__RecurrentWeightsRTRLDerivativesKernelPfS_S_S_S_, .Lfunc_end0-_Z52__device_stub__RecurrentWeightsRTRLDerivativesKernelPfS_S_S_S_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z37RecurrentWeightsRTRLDerivativesKernelPfS_S_S_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $0, 8(%rsp)
movl $1, (%rsp)
movl $D_HIDDEN_UNITS, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movl $4, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
callq __hipRegisterVar
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type D_HIDDEN_UNITS,@object # @D_HIDDEN_UNITS
.local D_HIDDEN_UNITS
.comm D_HIDDEN_UNITS,4,4
.type _Z37RecurrentWeightsRTRLDerivativesKernelPfS_S_S_S_,@object # @_Z37RecurrentWeightsRTRLDerivativesKernelPfS_S_S_S_
.section .rodata,"a",@progbits
.globl _Z37RecurrentWeightsRTRLDerivativesKernelPfS_S_S_S_
.p2align 3, 0x0
_Z37RecurrentWeightsRTRLDerivativesKernelPfS_S_S_S_:
.quad _Z52__device_stub__RecurrentWeightsRTRLDerivativesKernelPfS_S_S_S_
.size _Z37RecurrentWeightsRTRLDerivativesKernelPfS_S_S_S_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z37RecurrentWeightsRTRLDerivativesKernelPfS_S_S_S_"
.size .L__unnamed_1, 52
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "D_HIDDEN_UNITS"
.size .L__unnamed_2, 15
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z52__device_stub__RecurrentWeightsRTRLDerivativesKernelPfS_S_S_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym D_HIDDEN_UNITS
.addrsig_sym _Z37RecurrentWeightsRTRLDerivativesKernelPfS_S_S_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z37RecurrentWeightsRTRLDerivativesKernelPfS_S_S_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e220000002600 */
/*0020*/ IMAD.MOV.U32 R8, RZ, RZ, c[0x3][0x0] ; /* 0x00c00000ff087624 */
/* 0x000fc600078e00ff */
/*0030*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e220000002500 */
/*0040*/ IMAD R7, R8, c[0x3][0x0], RZ ; /* 0x00c0000008077a24 */
/* 0x000fc600078e02ff */
/*0050*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0060*/ IMAD R0, R0, c[0x0][0xc], R3 ; /* 0x0000030000007a24 */
/* 0x001fe400078e0203 */
/*0070*/ IMAD R3, R7, c[0x3][0x0], RZ ; /* 0x00c0000007037a24 */
/* 0x000fe400078e02ff */
/*0080*/ IMAD R0, R0, c[0x0][0x0], R5 ; /* 0x0000000000007a24 */
/* 0x002fca00078e0205 */
/*0090*/ ISETP.GE.AND P0, PT, R0, R3, PT ; /* 0x000000030000720c */
/* 0x000fda0003f06270 */
/*00a0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00b0*/ IABS R5, R7.reuse ; /* 0x0000000700057213 */
/* 0x080fe20000000000 */
/*00c0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00d0*/ IABS R10, R0 ; /* 0x00000000000a7213 */
/* 0x000fe40000000000 */
/*00e0*/ I2F.RP R4, R5 ; /* 0x0000000500047306 */
/* 0x000e220000209400 */
/*00f0*/ IABS R11, R7 ; /* 0x00000007000b7213 */
/* 0x000fce0000000000 */
/*0100*/ MUFU.RCP R4, R4 ; /* 0x0000000400047308 */
/* 0x001e240000001000 */
/*0110*/ IADD3 R2, R4, 0xffffffe, RZ ; /* 0x0ffffffe04027810 */
/* 0x001fcc0007ffe0ff */
/*0120*/ F2I.FTZ.U32.TRUNC.NTZ R3, R2 ; /* 0x0000000200037305 */
/* 0x000064000021f000 */
/*0130*/ HFMA2.MMA R2, -RZ, RZ, 0, 0 ; /* 0x00000000ff027435 */
/* 0x001fe200000001ff */
/*0140*/ IADD3 R6, RZ, -R3, RZ ; /* 0x80000003ff067210 */
/* 0x002fca0007ffe0ff */
/*0150*/ IMAD R9, R6, R5, RZ ; /* 0x0000000506097224 */
/* 0x000fe400078e02ff */
/*0160*/ IMAD.MOV.U32 R6, RZ, RZ, R10 ; /* 0x000000ffff067224 */
/* 0x000fe400078e000a */
/*0170*/ IMAD.HI.U32 R3, R3, R9, R2 ; /* 0x0000000903037227 */
/* 0x000fc800078e0002 */
/*0180*/ IMAD.MOV R9, RZ, RZ, -R11 ; /* 0x000000ffff097224 */
/* 0x000fe400078e0a0b */
/*0190*/ IMAD.HI.U32 R4, R3, R6, RZ ; /* 0x0000000603047227 */
/* 0x000fc800078e00ff */
/*01a0*/ IMAD R2, R4, R9, R6 ; /* 0x0000000904027224 */
/* 0x000fca00078e0206 */
/*01b0*/ ISETP.GT.U32.AND P2, PT, R5, R2, PT ; /* 0x000000020500720c */
/* 0x000fda0003f44070 */
/*01c0*/ @!P2 IADD3 R2, R2, -R5.reuse, RZ ; /* 0x800000050202a210 */
/* 0x080fe40007ffe0ff */
/*01d0*/ @!P2 IADD3 R4, R4, 0x1, RZ ; /* 0x000000010404a810 */
/* 0x000fe40007ffe0ff */
/*01e0*/ ISETP.GE.U32.AND P0, PT, R2, R5, PT ; /* 0x000000050200720c */
/* 0x000fe20003f06070 */
/*01f0*/ IMAD.MOV.U32 R5, RZ, RZ, RZ ; /* 0x000000ffff057224 */
/* 0x000fe200078e00ff */
/*0200*/ LOP3.LUT R2, R0, R7, RZ, 0x3c, !PT ; /* 0x0000000700027212 */
/* 0x000fe400078e3cff */
/*0210*/ ISETP.NE.AND P2, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fe40003f45270 */
/*0220*/ ISETP.GE.AND P1, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fce0003f26270 */
/*0230*/ @P0 IADD3 R4, R4, 0x1, RZ ; /* 0x0000000104040810 */
/* 0x000fe40007ffe0ff */
/*0240*/ ISETP.GE.AND P0, PT, R8, 0x1, PT ; /* 0x000000010800780c */
/* 0x000fc80003f06270 */
/*0250*/ @!P1 IMAD.MOV R4, RZ, RZ, -R4 ; /* 0x000000ffff049224 */
/* 0x000fe200078e0a04 */
/*0260*/ @!P2 LOP3.LUT R4, RZ, R7, RZ, 0x33, !PT ; /* 0x00000007ff04a212 */
/* 0x000fc800078e33ff */
/*0270*/ IADD3 R6, -R4, RZ, RZ ; /* 0x000000ff04067210 */
/* 0x000fca0007ffe1ff */
/*0280*/ IMAD R6, R7, R6, R0 ; /* 0x0000000607067224 */
/* 0x000fe200078e0200 */
/*0290*/ @!P0 BRA 0x600 ; /* 0x0000036000008947 */
/* 0x000fea0003800000 */
/*02a0*/ IADD3 R2, R8.reuse, -0x1, RZ ; /* 0xffffffff08027810 */
/* 0x040fe20007ffe0ff */
/*02b0*/ IMAD.MOV.U32 R17, RZ, RZ, RZ ; /* 0x000000ffff117224 */
/* 0x000fe200078e00ff */
/*02c0*/ LOP3.LUT R8, R8, 0x3, RZ, 0xc0, !PT ; /* 0x0000000308087812 */
/* 0x000fe400078ec0ff */
/*02d0*/ ISETP.GE.U32.AND P1, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fe40003f26070 */
/*02e0*/ ISETP.NE.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fe40003f05270 */
/*02f0*/ MOV R5, RZ ; /* 0x000000ff00057202 */
/* 0x000fd20000000f00 */
/*0300*/ @!P1 BRA 0x4f0 ; /* 0x000001e000009947 */
/* 0x000fea0003800000 */
/*0310*/ HFMA2.MMA R9, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff097435 */
/* 0x000fe200000001ff */
/*0320*/ IMAD R2, R4, c[0x3][0x0], RZ ; /* 0x00c0000004027a24 */
/* 0x000fe200078e02ff */
/*0330*/ IADD3 R16, R8, -c[0x3][0x0], RZ ; /* 0x80c0000008107a10 */
/* 0x000fe20007ffe0ff */
/*0340*/ IMAD.MOV.U32 R5, RZ, RZ, RZ ; /* 0x000000ffff057224 */
/* 0x000fe200078e00ff */
/*0350*/ MOV R17, RZ ; /* 0x000000ff00117202 */
/* 0x000fe20000000f00 */
/*0360*/ IMAD.MOV.U32 R18, RZ, RZ, R6 ; /* 0x000000ffff127224 */
/* 0x000fca00078e0006 */
/*0370*/ IMAD.WIDE R2, R2, R9, c[0x0][0x170] ; /* 0x00005c0002027625 */
/* 0x000fc800078e0209 */
/*0380*/ IMAD.WIDE R20, R18, R9, c[0x0][0x180] ; /* 0x0000600012147625 */
/* 0x000fe200078e0209 */
/*0390*/ LDG.E R19, [R2.64] ; /* 0x0000000402137981 */
/* 0x0000a8000c1e1900 */
/*03a0*/ LDG.E R22, [R2.64+0x4] ; /* 0x0000040402167981 */
/* 0x0000e2000c1e1900 */
/*03b0*/ IMAD.WIDE R10, R7, 0x4, R20 ; /* 0x00000004070a7825 */
/* 0x000fc600078e0214 */
/*03c0*/ LDG.E R20, [R20.64] ; /* 0x0000000414147981 */
/* 0x000ea6000c1e1900 */
/*03d0*/ IMAD.WIDE R12, R7.reuse, 0x4, R10 ; /* 0x00000004070c7825 */
/* 0x040fe200078e020a */
/*03e0*/ LDG.E R23, [R2.64+0x8] ; /* 0x0000080402177981 */
/* 0x000128000c1e1900 */
/*03f0*/ LDG.E R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x000ee2000c1e1900 */
/*0400*/ IMAD.WIDE R14, R7, 0x4, R12 ; /* 0x00000004070e7825 */
/* 0x000fc600078e020c */
/*0410*/ LDG.E R12, [R12.64] ; /* 0x000000040c0c7981 */
/* 0x000f28000c1e1900 */
/*0420*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000f68000c1e1900 */
/*0430*/ LDG.E R24, [R2.64+0xc] ; /* 0x00000c0402187981 */
/* 0x000162000c1e1900 */
/*0440*/ IADD3 R17, R17, 0x4, RZ ; /* 0x0000000411117810 */
/* 0x000fe40007ffe0ff */
/*0450*/ LEA R18, R7, R18, 0x2 ; /* 0x0000001207127211 */
/* 0x000fc400078e10ff */
/*0460*/ IADD3 R2, P2, R2, 0x10, RZ ; /* 0x0000001002027810 */
/* 0x001fca0007f5e0ff */
/*0470*/ IMAD.X R3, RZ, RZ, R3, P2 ; /* 0x000000ffff037224 */
/* 0x000fe400010e0603 */
/*0480*/ FFMA R19, R20, R19, R5 ; /* 0x0000001314137223 */
/* 0x004fe20000000005 */
/*0490*/ IADD3 R5, R16, R17, RZ ; /* 0x0000001110057210 */
/* 0x000fc80007ffe0ff */
/*04a0*/ ISETP.NE.AND P1, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe20003f25270 */
/*04b0*/ FFMA R19, R10, R22, R19 ; /* 0x000000160a137223 */
/* 0x008fc80000000013 */
/*04c0*/ FFMA R19, R12, R23, R19 ; /* 0x000000170c137223 */
/* 0x010fc80000000013 */
/*04d0*/ FFMA R5, R14, R24, R19 ; /* 0x000000180e057223 */
/* 0x020fc80000000013 */
/*04e0*/ @P1 BRA 0x380 ; /* 0xfffffe9000001947 */
/* 0x000fea000383ffff */
/*04f0*/ @!P0 BRA 0x600 ; /* 0x0000010000008947 */
/* 0x000fea0003800000 */
/*0500*/ IMAD.MOV.U32 R13, RZ, RZ, 0x4 ; /* 0x00000004ff0d7424 */
/* 0x000fe400078e00ff */
/*0510*/ IMAD R2, R4, c[0x3][0x0], R17 ; /* 0x00c0000004027a24 */
/* 0x000fe400078e0211 */
/*0520*/ IMAD R12, R7, R17, R6 ; /* 0x00000011070c7224 */
/* 0x000fe400078e0206 */
/*0530*/ IMAD.WIDE R2, R2, R13, c[0x0][0x170] ; /* 0x00005c0002027625 */
/* 0x000fc800078e020d */
/*0540*/ IMAD.MOV.U32 R11, RZ, RZ, R3 ; /* 0x000000ffff0b7224 */
/* 0x000fe200078e0003 */
/*0550*/ MOV R10, R2 ; /* 0x00000002000a7202 */
/* 0x000fc80000000f00 */
/*0560*/ IMAD.WIDE R2, R12, R13, c[0x0][0x180] ; /* 0x000060000c027625 */
/* 0x000fe200078e020d */
/*0570*/ LDG.E R9, [R10.64] ; /* 0x000000040a097981 */
/* 0x0000aa000c1e1900 */
/*0580*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*0590*/ IADD3 R8, R8, -0x1, RZ ; /* 0xffffffff08087810 */
/* 0x000fc80007ffe0ff */
/*05a0*/ ISETP.NE.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fe40003f05270 */
/*05b0*/ IADD3 R10, P1, R10, 0x4, RZ ; /* 0x000000040a0a7810 */
/* 0x001fe40007f3e0ff */
/*05c0*/ IADD3 R12, R7, R12, RZ ; /* 0x0000000c070c7210 */
/* 0x000fc60007ffe0ff */
/*05d0*/ IMAD.X R11, RZ, RZ, R11, P1 ; /* 0x000000ffff0b7224 */
/* 0x000fe400008e060b */
/*05e0*/ FFMA R5, R2, R9, R5 ; /* 0x0000000902057223 */
/* 0x004fc80000000005 */
/*05f0*/ @P0 BRA 0x560 ; /* 0xffffff6000000947 */
/* 0x000fea000383ffff */
/*0600*/ IABS R8, c[0x3][0x0] ; /* 0x00c0000000087a13 */
/* 0x000fe40000000000 */
/*0610*/ IABS R10, R6 ; /* 0x00000006000a7213 */
/* 0x000fe40000000000 */
/*0620*/ I2F.RP R7, R8 ; /* 0x0000000800077306 */
/* 0x000e220000209400 */
/*0630*/ MOV R11, 0x4 ; /* 0x00000004000b7802 */
/* 0x000fce0000000f00 */
/*0640*/ MUFU.RCP R7, R7 ; /* 0x0000000700077308 */
/* 0x001e240000001000 */
/*0650*/ IADD3 R2, R7, 0xffffffe, RZ ; /* 0x0ffffffe07027810 */
/* 0x001fcc0007ffe0ff */
/*0660*/ F2I.FTZ.U32.TRUNC.NTZ R3, R2 ; /* 0x0000000200037305 */
/* 0x000064000021f000 */
/*0670*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x001fe200078e00ff */
/*0680*/ IADD3 R9, RZ, -R3, RZ ; /* 0x80000003ff097210 */
/* 0x002fca0007ffe0ff */
/*0690*/ IMAD R9, R9, R8, RZ ; /* 0x0000000809097224 */
/* 0x000fc800078e02ff */
/*06a0*/ IMAD.HI.U32 R3, R3, R9, R2 ; /* 0x0000000903037227 */
/* 0x000fe200078e0002 */
/*06b0*/ MOV R9, R10 ; /* 0x0000000a00097202 */
/* 0x000fe40000000f00 */
/*06c0*/ LOP3.LUT R2, R6, c[0x3][0x0], RZ, 0x3c, !PT ; /* 0x00c0000006027a12 */
/* 0x000fc600078e3cff */
/*06d0*/ IMAD.HI.U32 R3, R3, R9, RZ ; /* 0x0000000903037227 */
/* 0x000fe200078e00ff */
/*06e0*/ ISETP.GE.AND P1, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fc60003f26270 */
/*06f0*/ IMAD.MOV R7, RZ, RZ, -R3 ; /* 0x000000ffff077224 */
/* 0x000fc800078e0a03 */
/*0700*/ IMAD R7, R8, R7, R9 ; /* 0x0000000708077224 */
/* 0x000fca00078e0209 */
/*0710*/ ISETP.GT.U32.AND P2, PT, R8, R7, PT ; /* 0x000000070800720c */
/* 0x000fda0003f44070 */
/*0720*/ @!P2 IADD3 R7, R7, -R8.reuse, RZ ; /* 0x800000080707a210 */
/* 0x080fe40007ffe0ff */
/*0730*/ @!P2 IADD3 R3, R3, 0x1, RZ ; /* 0x000000010303a810 */
/* 0x000fe40007ffe0ff */
/*0740*/ ISETP.GE.U32.AND P0, PT, R7, R8, PT ; /* 0x000000080700720c */
/* 0x000fe40003f06070 */
/*0750*/ ISETP.NE.AND P2, PT, RZ, c[0x3][0x0], PT ; /* 0x00c00000ff007a0c */
/* 0x000fd60003f45270 */
/*0760*/ @P0 IADD3 R3, R3, 0x1, RZ ; /* 0x0000000103030810 */
/* 0x000fca0007ffe0ff */
/*0770*/ IMAD.MOV.U32 R9, RZ, RZ, R3 ; /* 0x000000ffff097224 */
/* 0x000fca00078e0003 */
/*0780*/ @!P1 IADD3 R9, -R9, RZ, RZ ; /* 0x000000ff09099210 */
/* 0x000fe40007ffe1ff */
/*0790*/ @!P2 LOP3.LUT R9, RZ, c[0x3][0x0], RZ, 0x33, !PT ; /* 0x00c00000ff09aa12 */
/* 0x000fca00078e33ff */
/*07a0*/ IMAD.MOV R3, RZ, RZ, -R9 ; /* 0x000000ffff037224 */
/* 0x000fc800078e0a09 */
/*07b0*/ IMAD R2, R3, c[0x3][0x0], R6 ; /* 0x00c0000003027a24 */
/* 0x000fe400078e0206 */
/*07c0*/ IMAD.WIDE R6, R4, R11, c[0x0][0x168] ; /* 0x00005a0004067625 */
/* 0x000fc800078e020b */
/*07d0*/ IMAD.WIDE R2, R2, R11, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fe400078e020b */
/*07e0*/ LDG.E R7, [R6.64] ; /* 0x0000000406077981 */
/* 0x000ea8000c1e1900 */
/*07f0*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ee2000c1e1900 */
/*0800*/ ISETP.NE.AND P0, PT, R4, R9, PT ; /* 0x000000090400720c */
/* 0x000fc80003f05270 */
/*0810*/ FSEL R4, RZ, 1, P0 ; /* 0x3f800000ff047808 */
/* 0x000fca0000000000 */
/*0820*/ FFMA R8, R4, R2, R5 ; /* 0x0000000204087223 */
/* 0x008fe40000000005 */
/*0830*/ IMAD.WIDE R4, R0, R11, c[0x0][0x178] ; /* 0x00005e0000047625 */
/* 0x000fc800078e020b */
/*0840*/ FMUL R9, R8, R7 ; /* 0x0000000708097220 */
/* 0x004fca0000400000 */
/*0850*/ STG.E [R4.64], R9 ; /* 0x0000000904007986 */
/* 0x000fe2000c101904 */
/*0860*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0870*/ BRA 0x870; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0880*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0890*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z37RecurrentWeightsRTRLDerivativesKernelPfS_S_S_S_
.globl _Z37RecurrentWeightsRTRLDerivativesKernelPfS_S_S_S_
.p2align 8
.type _Z37RecurrentWeightsRTRLDerivativesKernelPfS_S_S_S_,@function
_Z37RecurrentWeightsRTRLDerivativesKernelPfS_S_S_S_:
s_clause 0x1
s_load_b32 s5, s[0:1], 0x28
s_load_b32 s6, s[0:1], 0x34
s_getpc_b64 s[2:3]
s_add_u32 s2, s2, D_HIDDEN_UNITS@rel32@lo+4
s_addc_u32 s3, s3, D_HIDDEN_UNITS@rel32@hi+12
s_load_b32 s4, s[2:3], 0x0
s_waitcnt lgkmcnt(0)
s_mul_i32 s2, s5, s15
s_and_b32 s3, s6, 0xffff
s_add_i32 s2, s2, s14
s_mul_i32 s5, s4, s4
v_mad_u64_u32 v[1:2], null, s2, s3, v[0:1]
s_mul_i32 s2, s5, s4
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_cmp_gt_i32_e32 vcc_lo, s2, v1
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_6
v_cvt_f32_u32_e32 v0, s5
s_sub_i32 s2, 0, s5
v_ashrrev_i32_e32 v3, 31, v1
s_ashr_i32 s6, s4, 31
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v0, v0
v_add_nc_u32_e32 v4, v1, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_xor_b32_e32 v4, v4, v3
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v0, 0x4f7ffffe, v0
v_cvt_u32_f32_e32 v0, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_mul_lo_u32 v2, s2, v0
s_add_i32 s2, s4, s6
s_xor_b32 s7, s2, s6
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
s_sub_i32 s2, 0, s7
s_cmp_lt_i32 s4, 1
v_mul_hi_u32 v2, v0, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v0, v0, v2
v_mul_hi_u32 v0, v4, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v2, v0, s5
v_sub_nc_u32_e32 v2, v4, v2
v_add_nc_u32_e32 v4, 1, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_subrev_nc_u32_e32 v5, s5, v2
v_cmp_le_u32_e32 vcc_lo, s5, v2
v_cndmask_b32_e32 v0, v0, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_cndmask_b32_e32 v2, v2, v5, vcc_lo
v_cvt_f32_u32_e32 v5, s7
v_add_nc_u32_e32 v4, 1, v0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_le_u32_e32 vcc_lo, s5, v2
v_cndmask_b32_e32 v0, v0, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v4, v5
v_xor_b32_e32 v0, v0, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v2, v0, v3
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v0, 0x4f7ffffe, v4
v_mul_lo_u32 v3, v2, s5
v_cvt_u32_f32_e32 v0, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_mul_lo_u32 v4, s2, v0
v_sub_nc_u32_e32 v9, v1, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_ashrrev_i32_e32 v10, 31, v9
v_mul_hi_u32 v3, v0, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v4, v9, v10
v_add_nc_u32_e32 v0, v0, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_xor_b32_e32 v11, v4, v10
v_mad_u64_u32 v[3:4], null, v11, v0, 0
s_cbranch_scc1 .LBB0_4
s_clause 0x1
s_load_b64 s[8:9], s[0:1], 0x10
s_load_b64 s[2:3], s[0:1], 0x20
v_mul_lo_u32 v5, v2, s4
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v7, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v6, 31, v5
v_lshlrev_b64 v[5:6], 2, v[5:6]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v5, vcc_lo, s8, v5
v_add_co_ci_u32_e32 v6, vcc_lo, s9, v6, vcc_lo
s_mov_b32 s8, s4
.p2align 6
.LBB0_3:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_ashrrev_i32_e32 v8, 31, v7
s_add_i32 s8, s8, -1
s_cmp_eq_u32 s8, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[12:13], 2, v[7:8]
v_add_co_u32 v12, vcc_lo, s2, v12
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v13, vcc_lo, s3, v13, vcc_lo
global_load_b32 v3, v[5:6], off
global_load_b32 v8, v[12:13], off
v_add_co_u32 v5, vcc_lo, v5, 4
v_add_co_ci_u32_e32 v6, vcc_lo, 0, v6, vcc_lo
s_waitcnt vmcnt(0)
v_dual_fmac_f32 v0, v3, v8 :: v_dual_add_nc_u32 v7, s5, v7
s_cbranch_scc0 .LBB0_3
s_branch .LBB0_5
.LBB0_4:
v_mov_b32_e32 v0, 0
.LBB0_5:
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_lo_u32 v3, v4, s7
v_add_nc_u32_e32 v5, 1, v4
v_sub_nc_u32_e32 v3, v11, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v6, s7, v3
v_cmp_le_u32_e32 vcc_lo, s7, v3
v_dual_cndmask_b32 v4, v4, v5 :: v_dual_cndmask_b32 v3, v3, v6
v_xor_b32_e32 v6, s6, v10
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_nc_u32_e32 v5, 1, v4
v_cmp_le_u32_e32 vcc_lo, s7, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v3, v4, v5, vcc_lo
v_xor_b32_e32 v3, v3, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v8, v3, v6
v_mul_lo_u32 v3, v8, s4
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x18
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v4, v9, v3
v_ashrrev_i32_e32 v3, 31, v2
v_ashrrev_i32_e32 v5, 31, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[6:7], 2, v[2:3]
v_lshlrev_b64 v[4:5], 2, v[4:5]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v3, vcc_lo, s4, v4
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_4)
v_add_co_u32 v5, vcc_lo, s6, v6
v_add_co_ci_u32_e32 v6, vcc_lo, s7, v7, vcc_lo
global_load_b32 v3, v[3:4], off
global_load_b32 v4, v[5:6], off
v_cmp_eq_u32_e32 vcc_lo, v2, v8
v_ashrrev_i32_e32 v2, 31, v1
v_cndmask_b32_e64 v5, 0, 1.0, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_waitcnt vmcnt(1)
v_fmac_f32_e32 v0, v3, v5
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_mul_f32_e32 v3, v4, v0
v_add_co_u32 v0, vcc_lo, s0, v1
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v2, vcc_lo
global_store_b32 v[0:1], v3, off
.LBB0_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z37RecurrentWeightsRTRLDerivativesKernelPfS_S_S_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 14
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z37RecurrentWeightsRTRLDerivativesKernelPfS_S_S_S_, .Lfunc_end0-_Z37RecurrentWeightsRTRLDerivativesKernelPfS_S_S_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.protected D_HIDDEN_UNITS
.type D_HIDDEN_UNITS,@object
.section .bss,"aw",@nobits
.globl D_HIDDEN_UNITS
.p2align 2, 0x0
D_HIDDEN_UNITS:
.long 0
.size D_HIDDEN_UNITS, 4
.type __hip_cuid_,@object
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym D_HIDDEN_UNITS
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z37RecurrentWeightsRTRLDerivativesKernelPfS_S_S_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z37RecurrentWeightsRTRLDerivativesKernelPfS_S_S_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 14
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001712c2_00000000-6_RecurrentWeightsRTRLDerivativesKernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z65__device_stub__Z37RecurrentWeightsRTRLDerivativesKernelPfS_S_S_S_PfS_S_S_S_
.type _Z65__device_stub__Z37RecurrentWeightsRTRLDerivativesKernelPfS_S_S_S_PfS_S_S_S_, @function
_Z65__device_stub__Z37RecurrentWeightsRTRLDerivativesKernelPfS_S_S_S_PfS_S_S_S_:
.LFB2051:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movq %r8, 8(%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 184
pushq 56(%rsp)
.cfi_def_cfa_offset 192
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z37RecurrentWeightsRTRLDerivativesKernelPfS_S_S_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z65__device_stub__Z37RecurrentWeightsRTRLDerivativesKernelPfS_S_S_S_PfS_S_S_S_, .-_Z65__device_stub__Z37RecurrentWeightsRTRLDerivativesKernelPfS_S_S_S_PfS_S_S_S_
.globl _Z37RecurrentWeightsRTRLDerivativesKernelPfS_S_S_S_
.type _Z37RecurrentWeightsRTRLDerivativesKernelPfS_S_S_S_, @function
_Z37RecurrentWeightsRTRLDerivativesKernelPfS_S_S_S_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z65__device_stub__Z37RecurrentWeightsRTRLDerivativesKernelPfS_S_S_S_PfS_S_S_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z37RecurrentWeightsRTRLDerivativesKernelPfS_S_S_S_, .-_Z37RecurrentWeightsRTRLDerivativesKernelPfS_S_S_S_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z37RecurrentWeightsRTRLDerivativesKernelPfS_S_S_S_"
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "D_HIDDEN_UNITS"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z37RecurrentWeightsRTRLDerivativesKernelPfS_S_S_S_(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $4, %r9d
movl $0, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _ZL14D_HIDDEN_UNITS(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL14D_HIDDEN_UNITS
.comm _ZL14D_HIDDEN_UNITS,4,4
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "RecurrentWeightsRTRLDerivativesKernel.hip"
.globl _Z52__device_stub__RecurrentWeightsRTRLDerivativesKernelPfS_S_S_S_ # -- Begin function _Z52__device_stub__RecurrentWeightsRTRLDerivativesKernelPfS_S_S_S_
.p2align 4, 0x90
.type _Z52__device_stub__RecurrentWeightsRTRLDerivativesKernelPfS_S_S_S_,@function
_Z52__device_stub__RecurrentWeightsRTRLDerivativesKernelPfS_S_S_S_: # @_Z52__device_stub__RecurrentWeightsRTRLDerivativesKernelPfS_S_S_S_
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z37RecurrentWeightsRTRLDerivativesKernelPfS_S_S_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end0:
.size _Z52__device_stub__RecurrentWeightsRTRLDerivativesKernelPfS_S_S_S_, .Lfunc_end0-_Z52__device_stub__RecurrentWeightsRTRLDerivativesKernelPfS_S_S_S_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z37RecurrentWeightsRTRLDerivativesKernelPfS_S_S_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $0, 8(%rsp)
movl $1, (%rsp)
movl $D_HIDDEN_UNITS, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movl $4, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
callq __hipRegisterVar
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type D_HIDDEN_UNITS,@object # @D_HIDDEN_UNITS
.local D_HIDDEN_UNITS
.comm D_HIDDEN_UNITS,4,4
.type _Z37RecurrentWeightsRTRLDerivativesKernelPfS_S_S_S_,@object # @_Z37RecurrentWeightsRTRLDerivativesKernelPfS_S_S_S_
.section .rodata,"a",@progbits
.globl _Z37RecurrentWeightsRTRLDerivativesKernelPfS_S_S_S_
.p2align 3, 0x0
_Z37RecurrentWeightsRTRLDerivativesKernelPfS_S_S_S_:
.quad _Z52__device_stub__RecurrentWeightsRTRLDerivativesKernelPfS_S_S_S_
.size _Z37RecurrentWeightsRTRLDerivativesKernelPfS_S_S_S_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z37RecurrentWeightsRTRLDerivativesKernelPfS_S_S_S_"
.size .L__unnamed_1, 52
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "D_HIDDEN_UNITS"
.size .L__unnamed_2, 15
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z52__device_stub__RecurrentWeightsRTRLDerivativesKernelPfS_S_S_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym D_HIDDEN_UNITS
.addrsig_sym _Z37RecurrentWeightsRTRLDerivativesKernelPfS_S_S_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <thrust/scan.h>
#include <thrust/device_vector.h>
#include <iostream>
int main(){
int data[6] = {1, 0, 2, 2, 1, 3};
thrust::inclusive_scan(data, data + 6, data);
/* data[0] = data[0]
* data[1] = data[0] + data[1]
* data[2] = data[0] + data[1] + data[2]
* ...
* data[5] = data[0] + data[1] + ... + data[5]
*/
printf("{");
for(int i=0; i<6; i++)
printf("%d, ",data[i]);
printf("}\n");
// data is now {1, 1, 3, 5, 6, 9}
} | code for sm_80
Function : _ZN3cub17CUB_200700_800_NS11EmptyKernelIvEEvv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <thrust/scan.h>
#include <thrust/device_vector.h>
#include <iostream>
int main(){
int data[6] = {1, 0, 2, 2, 1, 3};
thrust::inclusive_scan(data, data + 6, data);
/* data[0] = data[0]
* data[1] = data[0] + data[1]
* data[2] = data[0] + data[1] + data[2]
* ...
* data[5] = data[0] + data[1] + ... + data[5]
*/
printf("{");
for(int i=0; i<6; i++)
printf("%d, ",data[i]);
printf("}\n");
// data is now {1, 1, 3, 5, 6, 9}
} | #include <hip/hip_runtime.h>
#include <thrust/scan.h>
#include <thrust/device_vector.h>
#include <iostream>
int main(){
int data[6] = {1, 0, 2, 2, 1, 3};
thrust::inclusive_scan(data, data + 6, data);
/* data[0] = data[0]
* data[1] = data[0] + data[1]
* data[2] = data[0] + data[1] + data[2]
* ...
* data[5] = data[0] + data[1] + ... + data[5]
*/
printf("{");
for(int i=0; i<6; i++)
printf("%d, ",data[i]);
printf("}\n");
// data is now {1, 1, 3, 5, 6, 9}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <thrust/scan.h>
#include <thrust/device_vector.h>
#include <iostream>
int main(){
int data[6] = {1, 0, 2, 2, 1, 3};
thrust::inclusive_scan(data, data + 6, data);
/* data[0] = data[0]
* data[1] = data[0] + data[1]
* data[2] = data[0] + data[1] + data[2]
* ...
* data[5] = data[0] + data[1] + ... + data[5]
*/
printf("{");
for(int i=0; i<6; i++)
printf("%d, ",data[i]);
printf("}\n");
// data is now {1, 1, 3, 5, 6, 9}
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <thrust/scan.h>
#include <thrust/device_vector.h>
#include <iostream>
int main(){
int data[6] = {1, 0, 2, 2, 1, 3};
thrust::inclusive_scan(data, data + 6, data);
/* data[0] = data[0]
* data[1] = data[0] + data[1]
* data[2] = data[0] + data[1] + data[2]
* ...
* data[5] = data[0] + data[1] + ... + data[5]
*/
printf("{");
for(int i=0; i<6; i++)
printf("%d, ",data[i]);
printf("}\n");
// data is now {1, 1, 3, 5, 6, 9}
} | .text
.file "scans.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function main
.LCPI0_0:
.long 1 # 0x1
.long 0 # 0x0
.long 2 # 0x2
.long 2 # 0x2
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
movaps .LCPI0_0(%rip), %xmm0 # xmm0 = [1,0,2,2]
movaps %xmm0, (%rsp)
movabsq $12884901889, %rax # imm = 0x300000001
movq %rax, 16(%rsp)
movl $1, %eax
movl $4, %ecx
.p2align 4, 0x90
.LBB0_1: # %.lr.ph.i.i.i.i.i
# =>This Inner Loop Header: Depth=1
addl (%rsp,%rcx), %eax
movl %eax, (%rsp,%rcx)
addq $4, %rcx
cmpq $24, %rcx
jne .LBB0_1
# %bb.2: # %_ZN6thrust14inclusive_scanIPiS1_EET0_T_S3_S2_.exit
movl $123, %edi
callq putchar@PLT
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB0_3: # =>This Inner Loop Header: Depth=1
movl (%rsp,%rbx,4), %esi
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
incq %rbx
cmpq $6, %rbx
jne .LBB0_3
# %bb.4:
movl $.Lstr, %edi
callq puts@PLT
xorl %eax, %eax
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "%d, "
.size .L.str.1, 5
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "}"
.size .Lstr, 2
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _ZN3cub17CUB_200700_800_NS11EmptyKernelIvEEvv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "median_tree.cuh" | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "median_tree.cuh" | .file "tmpxft_0008319c_00000000-6_median_tree.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3519:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3519:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3542:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3542:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "median_tree.cuh" | #ifndef RTS_2_MEDIAN_TREE_H
#define RTS_2_MEDIAN_TREE_H
#include <algorithm>
#include <memory>
#include <utility>
//#include <iostream>
#include "median_tree_node.cuh"
template<class T>
class MedianTree {
public:
MedianTree() = default;;
explicit MedianTree(T a)
: lt(new MedianTreeNode<T>(a)), left_max(a) {};
MedianTree(T a, T b);
// Insert and remove elements
void Insert(T val, bool balance = true, bool rotate = true);
short Remove(T val, short subtree = 0);
// rotate and rebalance subtrees
void BalanceElements();
void RotateSubtrees(bool recursive = false);
// getters
/**
* @brief Get a pointer to the left, or smaller, subtree.
* @return Pointer to the left subtree.
*/
std::shared_ptr<MedianTreeNode<T>> left() const { return lt; };
/**
* @brief Get a pointer to the right, or larger, subtree.
* @return Pointer to the right subtree.
*/
std::shared_ptr<MedianTreeNode<T>> right() const { return rt; };
/**
* @brief Get the number of elements in the left subtree.
* @return The number of elements in the left subtree.
*/
[[nodiscard]] int
count_left() const { return lt == nullptr ? 0 : lt->count(); };
/**
* @brief Get the number of elements in the right subtree.
* @return The number of elements in the right subtree.
*/
[[nodiscard]] int
count_right() const { return rt == nullptr ? 0 : rt->count(); };
/**
* @brief Get the number of elements in the tree.
* @return The sum of the number of elements in both subtrees.
*/
[[nodiscard]] unsigned
count() const { return count_left() + count_right(); };
[[nodiscard]] unsigned short height();
[[nodiscard]] short balance();
[[nodiscard]] short el_balance();
[[nodiscard]] float median() const;
private:
std::shared_ptr<MedianTreeNode<T>> lt; /*!< Left subtree. */
std::shared_ptr<MedianTreeNode<T>> rt; /*!< Right subtree. */
T left_max = 0; /*!< Maximum value of the left subtree. */
T right_min = 0; /*!< Minimum value of the right subtree. */
std::shared_ptr<MedianTreeNode<T>> RemoveRoot(std::shared_ptr<MedianTreeNode<T>> root);
void ShiftLTR();
void ShiftRTL();
std::shared_ptr<MedianTreeNode<T>>
RotateSubtree(std::shared_ptr<MedianTreeNode<T>> subtree);
std::shared_ptr<MedianTreeNode<T>>
LLRotate(std::shared_ptr<MedianTreeNode<T>> subtree);
std::shared_ptr<MedianTreeNode<T>>
LRRotate(std::shared_ptr<MedianTreeNode<T>> subtree);
std::shared_ptr<MedianTreeNode<T>>
RLRotate(std::shared_ptr<MedianTreeNode<T>> subtree);
std::shared_ptr<MedianTreeNode<T>>
RRRotate(std::shared_ptr<MedianTreeNode<T>> subtree);
};
/**
* @brief Construct a MedianTree with two elements, one for each subtree.
* @tparam T The type of values stored in this tree.
* @param a A value to store in the tree.
* @param b Another value to store in the tree.
*/
template<class T>
MedianTree<T>::MedianTree(T a, T b) {
auto min_val = std::min(a, b);
auto max_val = std::max(a, b);
lt.reset(new MedianTreeNode<T>(min_val));
left_max = min_val;
rt.reset(new MedianTreeNode<T>(max_val));
right_min = max_val;
}
/**
* @brief Insert a value into this tree.
* @tparam T The type of samples_ stored in the nodes of this tree.
* @param val The value to insert.
*/
template<class T>
void MedianTree<T>::Insert(T val, bool balance, bool rotate) {
if (val <= median()) {
if (lt == nullptr) {
lt.reset(new MedianTreeNode<T>(val));
} else {
lt->Insert(val, rotate);
}
left_max = count_left() == 1 ? val : std::max(left_max, val);
} else {
if (rt == nullptr) {
rt.reset(new MedianTreeNode<T>(val));
} else {
rt->Insert(val, rotate);
}
right_min = count_right() == 1 ? val : std::min(right_min, val);
}
// rebalance elements if necessary
if (balance) {
BalanceElements();
}
// perform rotations if necessary
if (rotate) {
RotateSubtrees();
}
}
/**
* @brief Remove a value from this tree.
* @tparam T The type of the samples_ stored in the nodes of this tree.
* @param val The value to remove from this tree.
* @param subtree Force remove from left subtree if 1, right subtree if -1,
* or detect if 0.
* @return 0 if value successfully found and removed, 1 otherwise.
*/
template<class T>
short MedianTree<T>::Remove(T val, short subtree) {
short res = 1;
if (lt != nullptr && (subtree == 1 || (subtree == 0 && val <= left_max))) {
if (lt->value() == val) {
lt = RemoveRoot(std::move(lt));
res = 0;
} else { // search for the value in the left subtree
res = lt->Remove(val, true);
}
// update right_min if we need to
if (res == 0 && val == left_max) {
left_max = lt == nullptr ? 0 : lt->max();
}
} else if (rt != nullptr &&
(subtree == -1 || (subtree == 0 && val >= right_min))) {
if (rt->value() == val) {
// actually remove the value at the root node
rt = RemoveRoot(std::move(rt));
res = 0;
} else { // search for the value in the right subtree
res = rt->Remove(val, true);
}
// update right_min if we need to
if (res == 0 && val == right_min) {
right_min = rt == nullptr ? 0 : rt->min();
}
}
return res;
}
/**
* @brief Perform tree rotations on left and right subtrees, if necessary.
* @tparam T The type of the value stored in the elements of each subtree.
*/
template<class T>
void MedianTree<T>::RotateSubtrees(bool recursive) {
if (recursive) {
if (lt != nullptr)
lt->RotateChildren(recursive);
if (rt != nullptr)
rt->RotateChildren(recursive);
}
lt = RotateSubtree(std::move(lt));
rt = RotateSubtree(std::move(rt));
}
/**
* @brief Shift elements between subtrees to maintain a difference of no more
* than a single element.
* @tparam T The type of samples_ stored in the nodes of this tree.
*/
template<class T>
void MedianTree<T>::BalanceElements() {
if (-2 < el_balance() && el_balance() < 2) { // tree is already balanced
return;
}
if (el_balance() < -1) {
ShiftRTL();
}
if (el_balance() > 1) {
ShiftLTR();
}
}
/**
* @brief Compute and return the height of this tree.
* @tparam T The type of samples_ stored in the nodes of this tree.
* @return The height of this tree.
*/
template<class T>
unsigned short MedianTree<T>::height() {
auto left_height = lt == nullptr ? 0 : lt->height();
auto right_height = rt == nullptr ? 0 : rt->height();
return 1 + std::max(left_height, right_height);
}
/**
* @brief Compute the balance between the heights of the left and right
* subtrees.
*
* Balance factor is defined to be the difference between the height of the
* left subtree and that of the right subtree. A tree is said to be
* "left-heavy" if the subtree has a larger height than the right subtree.
* "Right-heavy" is analogously defined. In AVL trees, a tree's balance,
* together with that of its subtrees, is used to determine when to rotate.
*
* @tparam T The type of samples_ stored in the nodes of this tree.
* @return The balance factor.
*/
template<class T>
short MedianTree<T>::balance() {
auto left_height = lt == nullptr ? 0 : lt->height();
auto right_height = rt == nullptr ? 0 : rt->height();
return left_height - right_height;
}
/**
* @brief Compute the balance between the counts of the left and right subtrees.
* @tparam T The type of samples_ stored in the nodes of this tree.
* @return The difference between the left tree's count and the right tree's
* count.
*/
template<class T>
short MedianTree<T>::el_balance() {
auto left_count = lt == nullptr ? 0 : lt->count();
auto right_count = rt == nullptr ? 0 : rt->count();
return left_count - right_count;
}
/**
* @brief Compute and return the ComputeMedian of all values in this tree.
* @tparam T The type of samples_ stored in the nodes of this tree.
* @return The ComputeMedian of all values.
*/
template<class T>
float MedianTree<T>::median() const {
float med;
if (count_left() == count_right()) {
med = (left_max + right_min) / 2.0f;
} else if (count_left() > count_right()) {
med = left_max;
} else { // count_right() > count_left()
med = right_min;
}
return med;
}
/**
* @brief Remove the root node of one of the subtrees.
*
* Only the root node is removed. Subtrees of `root` will be reinserted back
* into
*
* @tparam T The type of samples_ stored in the nodes of this tree.
* @param root The node to remove.
*/
template<class T>
std::shared_ptr<MedianTreeNode<T>>
MedianTree<T>::RemoveRoot(std::shared_ptr<MedianTreeNode<T>> root) {
auto left_child = root->left();
auto right_child = root->right();
if (left_child != nullptr) {
root.swap(left_child);
left_child.reset();
root->InsertSubtree(right_child, false);
} else {
root.swap(right_child);
right_child.reset();
}
return root;
}
/**
* @brief Perform an LL, LR, RL, or RR rotation on a subtree if it needs one.
* @tparam T The type of samples_ stored in the subtree.
* @param subtree Pointer to the subtree to rotate.
* @return Root of the new subtree to be inserted into the old subtree's place.
*/
template<class T>
std::shared_ptr<MedianTreeNode<T>>
MedianTree<T>::RotateSubtree(std::shared_ptr<MedianTreeNode<T>> subtree) {
if (subtree == nullptr) {
return subtree;
}
if (subtree->balance() >= 2) {
if (subtree->left()->balance() >= 1) {
subtree = LLRotate(std::move(subtree));
} else if (subtree->left()->balance() <= -1) {
subtree = LRRotate(std::move(subtree));
}
} else if (subtree->balance() <= -2) {
if (subtree->right()->balance() >= 1) {
subtree = RLRotate(std::move(subtree));
} else if (subtree->right() != nullptr
&& subtree->right()->balance() <= -1) {
subtree = RRRotate(std::move(subtree));
}
} else {
return subtree;
}
if (subtree->left() != nullptr) {
subtree->left()->UpdatePopulation();
}
if (subtree->right() != nullptr) {
subtree->right()->UpdatePopulation();
}
subtree->UpdatePopulation();
return subtree;
}
/**
* @brief Shift the largest value in the left subtree to the right subtree.
* @tparam T The type of samples_ stored in the nodes of this tree.
*/
template<class T>
void MedianTree<T>::ShiftLTR() {
auto max_val = left_max;
auto res = Remove(max_val, 1); // resets left_max for us
if (res == 1) // failure
return;
if (rt == nullptr) {
rt.reset(new MedianTreeNode<T>(max_val));
right_min = max_val;
} else {
rt->Insert(max_val, true);
right_min = std::min(max_val, right_min);
}
}
/**
* @brief Shift the smallest value in the right subtree to the left subtree.
* @tparam T T The type of samples_ stored in the nodes of this tree.
*/
template<class T>
void MedianTree<T>::ShiftRTL() {
auto min_val = right_min;
auto res = Remove(min_val, -1); // resets right_min for us
if (res == 1) // failure
return;
if (lt == nullptr) {
lt.reset(new MedianTreeNode<T>(min_val));
left_max = min_val;
} else {
lt->Insert(min_val, true);
left_max = std::max(min_val, left_max);
}
}
/**
* @brief Perform an LL rotation on a subtree node.
* @tparam T The type of samples_ stored in the nodes of this subtree.
* @param subtree The subtree needing a rotation.
* @return Root of the new subtree to be inserted into the old subtree's place.
*/
template<class T>
std::shared_ptr<MedianTreeNode<T>>
MedianTree<T>::LLRotate(std::shared_ptr<MedianTreeNode<T>> subtree) {
std::shared_ptr<MedianTreeNode<T>> tmp;
auto left_child = subtree->DetachSubtree(1);
auto right_child = subtree->DetachSubtree(-1);
subtree->InsertSubtree(left_child->DetachSubtree(-1)); // inserts on the left
subtree->InsertSubtree(right_child); // inserts on the right
tmp.swap(subtree);
left_child->InsertSubtree(tmp);
subtree.swap(left_child);
return subtree;
}
/**
* @brief Perform an LR rotation on a subtree node.
* @tparam T The type of samples_ stored in the nodes of this subtree.
* @param subtree The subtree needing a rotation.
* @return Root of the new subtree to be inserted into the old subtree's place.
*/
template<class T>
std::shared_ptr<MedianTreeNode<T>>
MedianTree<T>::LRRotate(std::shared_ptr<MedianTreeNode<T>> subtree) {
auto left_child = subtree->DetachSubtree(1);
auto tmp = left_child->DetachSubtree(-1);
subtree->InsertSubtree(tmp->DetachSubtree(-1)); // inserts on the left
left_child->InsertSubtree(tmp->DetachSubtree(1)); // inserts on the right
tmp->InsertSubtree(left_child); // inserts on the left
tmp->InsertSubtree(subtree); // inserts on the right
subtree.swap(tmp);
return subtree;
}
/**
* @brief Perform an RL rotation on a subtree.
* @tparam T The type of samples_ stored in the nodes of this subtree.
* @param subtree The subtree needing a rotation.
* @return Root of the new subtree to be inserted into the old subtree's place.
*/
template<class T>
std::shared_ptr<MedianTreeNode<T>>
MedianTree<T>::RLRotate(std::shared_ptr<MedianTreeNode<T>> subtree) {
auto right_child = subtree->DetachSubtree(-1);
auto tmp = right_child->DetachSubtree(1);
subtree->InsertSubtree(tmp->DetachSubtree(1)); // inserts on the right
right_child->InsertSubtree(tmp->DetachSubtree(-1)); // inserts on the left
tmp->InsertSubtree(right_child); // inserts on the right
tmp->InsertSubtree(subtree); // inserts on the left
subtree.swap(tmp);
return subtree;
}
/**
* @brief Perform an RR rotation on a subtree.
* @tparam T The type of samples_ stored in the nodes of this subtree.
* @param subtree The subtree needing a rotation.
* @return Root of the new subtree to be inserted into the old subtree's place.
*/
template<class T>
std::shared_ptr<MedianTreeNode<T>>
MedianTree<T>::RRRotate(std::shared_ptr<MedianTreeNode<T>> subtree) {
std::shared_ptr<MedianTreeNode<T>> tmp;
auto left_child = subtree->DetachSubtree(1);
auto right_child = subtree->DetachSubtree(-1);
// inserts on the right
subtree->InsertSubtree(right_child->DetachSubtree(1));
subtree->InsertSubtree(left_child); // inserts on the left
tmp.swap(subtree);
right_child->InsertSubtree(tmp);
subtree.swap(right_child);
return subtree;
}
#endif //RTS_2_MEDIAN_TREE_H |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #ifndef RTS_2_MEDIAN_TREE_H
#define RTS_2_MEDIAN_TREE_H
#include <algorithm>
#include <memory>
#include <utility>
//#include <iostream>
#include "median_tree_node.cuh"
template<class T>
class MedianTree {
public:
MedianTree() = default;;
explicit MedianTree(T a)
: lt(new MedianTreeNode<T>(a)), left_max(a) {};
MedianTree(T a, T b);
// Insert and remove elements
void Insert(T val, bool balance = true, bool rotate = true);
short Remove(T val, short subtree = 0);
// rotate and rebalance subtrees
void BalanceElements();
void RotateSubtrees(bool recursive = false);
// getters
/**
* @brief Get a pointer to the left, or smaller, subtree.
* @return Pointer to the left subtree.
*/
std::shared_ptr<MedianTreeNode<T>> left() const { return lt; };
/**
* @brief Get a pointer to the right, or larger, subtree.
* @return Pointer to the right subtree.
*/
std::shared_ptr<MedianTreeNode<T>> right() const { return rt; };
/**
* @brief Get the number of elements in the left subtree.
* @return The number of elements in the left subtree.
*/
[[nodiscard]] int
count_left() const { return lt == nullptr ? 0 : lt->count(); };
/**
* @brief Get the number of elements in the right subtree.
* @return The number of elements in the right subtree.
*/
[[nodiscard]] int
count_right() const { return rt == nullptr ? 0 : rt->count(); };
/**
* @brief Get the number of elements in the tree.
* @return The sum of the number of elements in both subtrees.
*/
[[nodiscard]] unsigned
count() const { return count_left() + count_right(); };
[[nodiscard]] unsigned short height();
[[nodiscard]] short balance();
[[nodiscard]] short el_balance();
[[nodiscard]] float median() const;
private:
std::shared_ptr<MedianTreeNode<T>> lt; /*!< Left subtree. */
std::shared_ptr<MedianTreeNode<T>> rt; /*!< Right subtree. */
T left_max = 0; /*!< Maximum value of the left subtree. */
T right_min = 0; /*!< Minimum value of the right subtree. */
std::shared_ptr<MedianTreeNode<T>> RemoveRoot(std::shared_ptr<MedianTreeNode<T>> root);
void ShiftLTR();
void ShiftRTL();
std::shared_ptr<MedianTreeNode<T>>
RotateSubtree(std::shared_ptr<MedianTreeNode<T>> subtree);
std::shared_ptr<MedianTreeNode<T>>
LLRotate(std::shared_ptr<MedianTreeNode<T>> subtree);
std::shared_ptr<MedianTreeNode<T>>
LRRotate(std::shared_ptr<MedianTreeNode<T>> subtree);
std::shared_ptr<MedianTreeNode<T>>
RLRotate(std::shared_ptr<MedianTreeNode<T>> subtree);
std::shared_ptr<MedianTreeNode<T>>
RRRotate(std::shared_ptr<MedianTreeNode<T>> subtree);
};
/**
* @brief Construct a MedianTree with two elements, one for each subtree.
* @tparam T The type of values stored in this tree.
* @param a A value to store in the tree.
* @param b Another value to store in the tree.
*/
template<class T>
MedianTree<T>::MedianTree(T a, T b) {
auto min_val = std::min(a, b);
auto max_val = std::max(a, b);
lt.reset(new MedianTreeNode<T>(min_val));
left_max = min_val;
rt.reset(new MedianTreeNode<T>(max_val));
right_min = max_val;
}
/**
* @brief Insert a value into this tree.
* @tparam T The type of samples_ stored in the nodes of this tree.
* @param val The value to insert.
*/
template<class T>
void MedianTree<T>::Insert(T val, bool balance, bool rotate) {
if (val <= median()) {
if (lt == nullptr) {
lt.reset(new MedianTreeNode<T>(val));
} else {
lt->Insert(val, rotate);
}
left_max = count_left() == 1 ? val : std::max(left_max, val);
} else {
if (rt == nullptr) {
rt.reset(new MedianTreeNode<T>(val));
} else {
rt->Insert(val, rotate);
}
right_min = count_right() == 1 ? val : std::min(right_min, val);
}
// rebalance elements if necessary
if (balance) {
BalanceElements();
}
// perform rotations if necessary
if (rotate) {
RotateSubtrees();
}
}
/**
* @brief Remove a value from this tree.
* @tparam T The type of the samples_ stored in the nodes of this tree.
* @param val The value to remove from this tree.
* @param subtree Force remove from left subtree if 1, right subtree if -1,
* or detect if 0.
* @return 0 if value successfully found and removed, 1 otherwise.
*/
template<class T>
short MedianTree<T>::Remove(T val, short subtree) {
short res = 1;
if (lt != nullptr && (subtree == 1 || (subtree == 0 && val <= left_max))) {
if (lt->value() == val) {
lt = RemoveRoot(std::move(lt));
res = 0;
} else { // search for the value in the left subtree
res = lt->Remove(val, true);
}
// update right_min if we need to
if (res == 0 && val == left_max) {
left_max = lt == nullptr ? 0 : lt->max();
}
} else if (rt != nullptr &&
(subtree == -1 || (subtree == 0 && val >= right_min))) {
if (rt->value() == val) {
// actually remove the value at the root node
rt = RemoveRoot(std::move(rt));
res = 0;
} else { // search for the value in the right subtree
res = rt->Remove(val, true);
}
// update right_min if we need to
if (res == 0 && val == right_min) {
right_min = rt == nullptr ? 0 : rt->min();
}
}
return res;
}
/**
* @brief Perform tree rotations on left and right subtrees, if necessary.
* @tparam T The type of the value stored in the elements of each subtree.
*/
template<class T>
void MedianTree<T>::RotateSubtrees(bool recursive) {
if (recursive) {
if (lt != nullptr)
lt->RotateChildren(recursive);
if (rt != nullptr)
rt->RotateChildren(recursive);
}
lt = RotateSubtree(std::move(lt));
rt = RotateSubtree(std::move(rt));
}
/**
* @brief Shift elements between subtrees to maintain a difference of no more
* than a single element.
* @tparam T The type of samples_ stored in the nodes of this tree.
*/
template<class T>
void MedianTree<T>::BalanceElements() {
if (-2 < el_balance() && el_balance() < 2) { // tree is already balanced
return;
}
if (el_balance() < -1) {
ShiftRTL();
}
if (el_balance() > 1) {
ShiftLTR();
}
}
/**
* @brief Compute and return the height of this tree.
* @tparam T The type of samples_ stored in the nodes of this tree.
* @return The height of this tree.
*/
template<class T>
unsigned short MedianTree<T>::height() {
auto left_height = lt == nullptr ? 0 : lt->height();
auto right_height = rt == nullptr ? 0 : rt->height();
return 1 + std::max(left_height, right_height);
}
/**
* @brief Compute the balance between the heights of the left and right
* subtrees.
*
* Balance factor is defined to be the difference between the height of the
* left subtree and that of the right subtree. A tree is said to be
* "left-heavy" if the subtree has a larger height than the right subtree.
* "Right-heavy" is analogously defined. In AVL trees, a tree's balance,
* together with that of its subtrees, is used to determine when to rotate.
*
* @tparam T The type of samples_ stored in the nodes of this tree.
* @return The balance factor.
*/
template<class T>
short MedianTree<T>::balance() {
auto left_height = lt == nullptr ? 0 : lt->height();
auto right_height = rt == nullptr ? 0 : rt->height();
return left_height - right_height;
}
/**
* @brief Compute the balance between the counts of the left and right subtrees.
* @tparam T The type of samples_ stored in the nodes of this tree.
* @return The difference between the left tree's count and the right tree's
* count.
*/
template<class T>
short MedianTree<T>::el_balance() {
auto left_count = lt == nullptr ? 0 : lt->count();
auto right_count = rt == nullptr ? 0 : rt->count();
return left_count - right_count;
}
/**
* @brief Compute and return the ComputeMedian of all values in this tree.
* @tparam T The type of samples_ stored in the nodes of this tree.
* @return The ComputeMedian of all values.
*/
template<class T>
float MedianTree<T>::median() const {
float med;
if (count_left() == count_right()) {
med = (left_max + right_min) / 2.0f;
} else if (count_left() > count_right()) {
med = left_max;
} else { // count_right() > count_left()
med = right_min;
}
return med;
}
/**
* @brief Remove the root node of one of the subtrees.
*
* Only the root node is removed. Subtrees of `root` will be reinserted back
* into
*
* @tparam T The type of samples_ stored in the nodes of this tree.
* @param root The node to remove.
*/
template<class T>
std::shared_ptr<MedianTreeNode<T>>
MedianTree<T>::RemoveRoot(std::shared_ptr<MedianTreeNode<T>> root) {
auto left_child = root->left();
auto right_child = root->right();
if (left_child != nullptr) {
root.swap(left_child);
left_child.reset();
root->InsertSubtree(right_child, false);
} else {
root.swap(right_child);
right_child.reset();
}
return root;
}
/**
* @brief Perform an LL, LR, RL, or RR rotation on a subtree if it needs one.
* @tparam T The type of samples_ stored in the subtree.
* @param subtree Pointer to the subtree to rotate.
* @return Root of the new subtree to be inserted into the old subtree's place.
*/
template<class T>
std::shared_ptr<MedianTreeNode<T>>
MedianTree<T>::RotateSubtree(std::shared_ptr<MedianTreeNode<T>> subtree) {
if (subtree == nullptr) {
return subtree;
}
if (subtree->balance() >= 2) {
if (subtree->left()->balance() >= 1) {
subtree = LLRotate(std::move(subtree));
} else if (subtree->left()->balance() <= -1) {
subtree = LRRotate(std::move(subtree));
}
} else if (subtree->balance() <= -2) {
if (subtree->right()->balance() >= 1) {
subtree = RLRotate(std::move(subtree));
} else if (subtree->right() != nullptr
&& subtree->right()->balance() <= -1) {
subtree = RRRotate(std::move(subtree));
}
} else {
return subtree;
}
if (subtree->left() != nullptr) {
subtree->left()->UpdatePopulation();
}
if (subtree->right() != nullptr) {
subtree->right()->UpdatePopulation();
}
subtree->UpdatePopulation();
return subtree;
}
/**
* @brief Shift the largest value in the left subtree to the right subtree.
* @tparam T The type of samples_ stored in the nodes of this tree.
*/
template<class T>
void MedianTree<T>::ShiftLTR() {
auto max_val = left_max;
auto res = Remove(max_val, 1); // resets left_max for us
if (res == 1) // failure
return;
if (rt == nullptr) {
rt.reset(new MedianTreeNode<T>(max_val));
right_min = max_val;
} else {
rt->Insert(max_val, true);
right_min = std::min(max_val, right_min);
}
}
/**
* @brief Shift the smallest value in the right subtree to the left subtree.
* @tparam T T The type of samples_ stored in the nodes of this tree.
*/
template<class T>
void MedianTree<T>::ShiftRTL() {
auto min_val = right_min;
auto res = Remove(min_val, -1); // resets right_min for us
if (res == 1) // failure
return;
if (lt == nullptr) {
lt.reset(new MedianTreeNode<T>(min_val));
left_max = min_val;
} else {
lt->Insert(min_val, true);
left_max = std::max(min_val, left_max);
}
}
/**
* @brief Perform an LL rotation on a subtree node.
* @tparam T The type of samples_ stored in the nodes of this subtree.
* @param subtree The subtree needing a rotation.
* @return Root of the new subtree to be inserted into the old subtree's place.
*/
template<class T>
std::shared_ptr<MedianTreeNode<T>>
MedianTree<T>::LLRotate(std::shared_ptr<MedianTreeNode<T>> subtree) {
std::shared_ptr<MedianTreeNode<T>> tmp;
auto left_child = subtree->DetachSubtree(1);
auto right_child = subtree->DetachSubtree(-1);
subtree->InsertSubtree(left_child->DetachSubtree(-1)); // inserts on the left
subtree->InsertSubtree(right_child); // inserts on the right
tmp.swap(subtree);
left_child->InsertSubtree(tmp);
subtree.swap(left_child);
return subtree;
}
/**
* @brief Perform an LR rotation on a subtree node.
* @tparam T The type of samples_ stored in the nodes of this subtree.
* @param subtree The subtree needing a rotation.
* @return Root of the new subtree to be inserted into the old subtree's place.
*/
template<class T>
std::shared_ptr<MedianTreeNode<T>>
MedianTree<T>::LRRotate(std::shared_ptr<MedianTreeNode<T>> subtree) {
auto left_child = subtree->DetachSubtree(1);
auto tmp = left_child->DetachSubtree(-1);
subtree->InsertSubtree(tmp->DetachSubtree(-1)); // inserts on the left
left_child->InsertSubtree(tmp->DetachSubtree(1)); // inserts on the right
tmp->InsertSubtree(left_child); // inserts on the left
tmp->InsertSubtree(subtree); // inserts on the right
subtree.swap(tmp);
return subtree;
}
/**
* @brief Perform an RL rotation on a subtree.
* @tparam T The type of samples_ stored in the nodes of this subtree.
* @param subtree The subtree needing a rotation.
* @return Root of the new subtree to be inserted into the old subtree's place.
*/
template<class T>
std::shared_ptr<MedianTreeNode<T>>
MedianTree<T>::RLRotate(std::shared_ptr<MedianTreeNode<T>> subtree) {
auto right_child = subtree->DetachSubtree(-1);
auto tmp = right_child->DetachSubtree(1);
subtree->InsertSubtree(tmp->DetachSubtree(1)); // inserts on the right
right_child->InsertSubtree(tmp->DetachSubtree(-1)); // inserts on the left
tmp->InsertSubtree(right_child); // inserts on the right
tmp->InsertSubtree(subtree); // inserts on the left
subtree.swap(tmp);
return subtree;
}
/**
* @brief Perform an RR rotation on a subtree.
* @tparam T The type of samples_ stored in the nodes of this subtree.
* @param subtree The subtree needing a rotation.
* @return Root of the new subtree to be inserted into the old subtree's place.
*/
template<class T>
std::shared_ptr<MedianTreeNode<T>>
MedianTree<T>::RRRotate(std::shared_ptr<MedianTreeNode<T>> subtree) {
std::shared_ptr<MedianTreeNode<T>> tmp;
auto left_child = subtree->DetachSubtree(1);
auto right_child = subtree->DetachSubtree(-1);
// inserts on the right
subtree->InsertSubtree(right_child->DetachSubtree(1));
subtree->InsertSubtree(left_child); // inserts on the left
tmp.swap(subtree);
right_child->InsertSubtree(tmp);
subtree.swap(right_child);
return subtree;
}
#endif //RTS_2_MEDIAN_TREE_H | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #ifndef RTS_2_MEDIAN_TREE_H
#define RTS_2_MEDIAN_TREE_H
#include <algorithm>
#include <memory>
#include <utility>
//#include <iostream>
#include "median_tree_node.cuh"
template<class T>
class MedianTree {
public:
MedianTree() = default;;
explicit MedianTree(T a)
: lt(new MedianTreeNode<T>(a)), left_max(a) {};
MedianTree(T a, T b);
// Insert and remove elements
void Insert(T val, bool balance = true, bool rotate = true);
short Remove(T val, short subtree = 0);
// rotate and rebalance subtrees
void BalanceElements();
void RotateSubtrees(bool recursive = false);
// getters
/**
* @brief Get a pointer to the left, or smaller, subtree.
* @return Pointer to the left subtree.
*/
std::shared_ptr<MedianTreeNode<T>> left() const { return lt; };
/**
* @brief Get a pointer to the right, or larger, subtree.
* @return Pointer to the right subtree.
*/
std::shared_ptr<MedianTreeNode<T>> right() const { return rt; };
/**
* @brief Get the number of elements in the left subtree.
* @return The number of elements in the left subtree.
*/
[[nodiscard]] int
count_left() const { return lt == nullptr ? 0 : lt->count(); };
/**
* @brief Get the number of elements in the right subtree.
* @return The number of elements in the right subtree.
*/
[[nodiscard]] int
count_right() const { return rt == nullptr ? 0 : rt->count(); };
/**
* @brief Get the number of elements in the tree.
* @return The sum of the number of elements in both subtrees.
*/
[[nodiscard]] unsigned
count() const { return count_left() + count_right(); };
[[nodiscard]] unsigned short height();
[[nodiscard]] short balance();
[[nodiscard]] short el_balance();
[[nodiscard]] float median() const;
private:
std::shared_ptr<MedianTreeNode<T>> lt; /*!< Left subtree. */
std::shared_ptr<MedianTreeNode<T>> rt; /*!< Right subtree. */
T left_max = 0; /*!< Maximum value of the left subtree. */
T right_min = 0; /*!< Minimum value of the right subtree. */
std::shared_ptr<MedianTreeNode<T>> RemoveRoot(std::shared_ptr<MedianTreeNode<T>> root);
void ShiftLTR();
void ShiftRTL();
std::shared_ptr<MedianTreeNode<T>>
RotateSubtree(std::shared_ptr<MedianTreeNode<T>> subtree);
std::shared_ptr<MedianTreeNode<T>>
LLRotate(std::shared_ptr<MedianTreeNode<T>> subtree);
std::shared_ptr<MedianTreeNode<T>>
LRRotate(std::shared_ptr<MedianTreeNode<T>> subtree);
std::shared_ptr<MedianTreeNode<T>>
RLRotate(std::shared_ptr<MedianTreeNode<T>> subtree);
std::shared_ptr<MedianTreeNode<T>>
RRRotate(std::shared_ptr<MedianTreeNode<T>> subtree);
};
/**
* @brief Construct a MedianTree with two elements, one for each subtree.
* @tparam T The type of values stored in this tree.
* @param a A value to store in the tree.
* @param b Another value to store in the tree.
*/
template<class T>
MedianTree<T>::MedianTree(T a, T b) {
auto min_val = std::min(a, b);
auto max_val = std::max(a, b);
lt.reset(new MedianTreeNode<T>(min_val));
left_max = min_val;
rt.reset(new MedianTreeNode<T>(max_val));
right_min = max_val;
}
/**
* @brief Insert a value into this tree.
* @tparam T The type of samples_ stored in the nodes of this tree.
* @param val The value to insert.
*/
template<class T>
void MedianTree<T>::Insert(T val, bool balance, bool rotate) {
if (val <= median()) {
if (lt == nullptr) {
lt.reset(new MedianTreeNode<T>(val));
} else {
lt->Insert(val, rotate);
}
left_max = count_left() == 1 ? val : std::max(left_max, val);
} else {
if (rt == nullptr) {
rt.reset(new MedianTreeNode<T>(val));
} else {
rt->Insert(val, rotate);
}
right_min = count_right() == 1 ? val : std::min(right_min, val);
}
// rebalance elements if necessary
if (balance) {
BalanceElements();
}
// perform rotations if necessary
if (rotate) {
RotateSubtrees();
}
}
/**
* @brief Remove a value from this tree.
* @tparam T The type of the samples_ stored in the nodes of this tree.
* @param val The value to remove from this tree.
* @param subtree Force remove from left subtree if 1, right subtree if -1,
* or detect if 0.
* @return 0 if value successfully found and removed, 1 otherwise.
*/
template<class T>
short MedianTree<T>::Remove(T val, short subtree) {
short res = 1;
if (lt != nullptr && (subtree == 1 || (subtree == 0 && val <= left_max))) {
if (lt->value() == val) {
lt = RemoveRoot(std::move(lt));
res = 0;
} else { // search for the value in the left subtree
res = lt->Remove(val, true);
}
// update right_min if we need to
if (res == 0 && val == left_max) {
left_max = lt == nullptr ? 0 : lt->max();
}
} else if (rt != nullptr &&
(subtree == -1 || (subtree == 0 && val >= right_min))) {
if (rt->value() == val) {
// actually remove the value at the root node
rt = RemoveRoot(std::move(rt));
res = 0;
} else { // search for the value in the right subtree
res = rt->Remove(val, true);
}
// update right_min if we need to
if (res == 0 && val == right_min) {
right_min = rt == nullptr ? 0 : rt->min();
}
}
return res;
}
/**
* @brief Perform tree rotations on left and right subtrees, if necessary.
* @tparam T The type of the value stored in the elements of each subtree.
*/
template<class T>
void MedianTree<T>::RotateSubtrees(bool recursive) {
if (recursive) {
if (lt != nullptr)
lt->RotateChildren(recursive);
if (rt != nullptr)
rt->RotateChildren(recursive);
}
lt = RotateSubtree(std::move(lt));
rt = RotateSubtree(std::move(rt));
}
/**
* @brief Shift elements between subtrees to maintain a difference of no more
* than a single element.
* @tparam T The type of samples_ stored in the nodes of this tree.
*/
template<class T>
void MedianTree<T>::BalanceElements() {
if (-2 < el_balance() && el_balance() < 2) { // tree is already balanced
return;
}
if (el_balance() < -1) {
ShiftRTL();
}
if (el_balance() > 1) {
ShiftLTR();
}
}
/**
* @brief Compute and return the height of this tree.
* @tparam T The type of samples_ stored in the nodes of this tree.
* @return The height of this tree.
*/
template<class T>
unsigned short MedianTree<T>::height() {
auto left_height = lt == nullptr ? 0 : lt->height();
auto right_height = rt == nullptr ? 0 : rt->height();
return 1 + std::max(left_height, right_height);
}
/**
* @brief Compute the balance between the heights of the left and right
* subtrees.
*
* Balance factor is defined to be the difference between the height of the
* left subtree and that of the right subtree. A tree is said to be
* "left-heavy" if the subtree has a larger height than the right subtree.
* "Right-heavy" is analogously defined. In AVL trees, a tree's balance,
* together with that of its subtrees, is used to determine when to rotate.
*
* @tparam T The type of samples_ stored in the nodes of this tree.
* @return The balance factor.
*/
template<class T>
short MedianTree<T>::balance() {
auto left_height = lt == nullptr ? 0 : lt->height();
auto right_height = rt == nullptr ? 0 : rt->height();
return left_height - right_height;
}
/**
* @brief Compute the balance between the counts of the left and right subtrees.
* @tparam T The type of samples_ stored in the nodes of this tree.
* @return The difference between the left tree's count and the right tree's
* count.
*/
template<class T>
short MedianTree<T>::el_balance() {
auto left_count = lt == nullptr ? 0 : lt->count();
auto right_count = rt == nullptr ? 0 : rt->count();
return left_count - right_count;
}
/**
* @brief Compute and return the ComputeMedian of all values in this tree.
* @tparam T The type of samples_ stored in the nodes of this tree.
* @return The ComputeMedian of all values.
*/
template<class T>
float MedianTree<T>::median() const {
float med;
if (count_left() == count_right()) {
med = (left_max + right_min) / 2.0f;
} else if (count_left() > count_right()) {
med = left_max;
} else { // count_right() > count_left()
med = right_min;
}
return med;
}
/**
* @brief Remove the root node of one of the subtrees.
*
* Only the root node is removed. Subtrees of `root` will be reinserted back
* into
*
* @tparam T The type of samples_ stored in the nodes of this tree.
* @param root The node to remove.
*/
template<class T>
std::shared_ptr<MedianTreeNode<T>>
MedianTree<T>::RemoveRoot(std::shared_ptr<MedianTreeNode<T>> root) {
auto left_child = root->left();
auto right_child = root->right();
if (left_child != nullptr) {
root.swap(left_child);
left_child.reset();
root->InsertSubtree(right_child, false);
} else {
root.swap(right_child);
right_child.reset();
}
return root;
}
/**
* @brief Perform an LL, LR, RL, or RR rotation on a subtree if it needs one.
* @tparam T The type of samples_ stored in the subtree.
* @param subtree Pointer to the subtree to rotate.
* @return Root of the new subtree to be inserted into the old subtree's place.
*/
template<class T>
std::shared_ptr<MedianTreeNode<T>>
MedianTree<T>::RotateSubtree(std::shared_ptr<MedianTreeNode<T>> subtree) {
if (subtree == nullptr) {
return subtree;
}
if (subtree->balance() >= 2) {
if (subtree->left()->balance() >= 1) {
subtree = LLRotate(std::move(subtree));
} else if (subtree->left()->balance() <= -1) {
subtree = LRRotate(std::move(subtree));
}
} else if (subtree->balance() <= -2) {
if (subtree->right()->balance() >= 1) {
subtree = RLRotate(std::move(subtree));
} else if (subtree->right() != nullptr
&& subtree->right()->balance() <= -1) {
subtree = RRRotate(std::move(subtree));
}
} else {
return subtree;
}
if (subtree->left() != nullptr) {
subtree->left()->UpdatePopulation();
}
if (subtree->right() != nullptr) {
subtree->right()->UpdatePopulation();
}
subtree->UpdatePopulation();
return subtree;
}
/**
* @brief Shift the largest value in the left subtree to the right subtree.
* @tparam T The type of samples_ stored in the nodes of this tree.
*/
template<class T>
void MedianTree<T>::ShiftLTR() {
auto max_val = left_max;
auto res = Remove(max_val, 1); // resets left_max for us
if (res == 1) // failure
return;
if (rt == nullptr) {
rt.reset(new MedianTreeNode<T>(max_val));
right_min = max_val;
} else {
rt->Insert(max_val, true);
right_min = std::min(max_val, right_min);
}
}
/**
* @brief Shift the smallest value in the right subtree to the left subtree.
* @tparam T T The type of samples_ stored in the nodes of this tree.
*/
template<class T>
void MedianTree<T>::ShiftRTL() {
auto min_val = right_min;
auto res = Remove(min_val, -1); // resets right_min for us
if (res == 1) // failure
return;
if (lt == nullptr) {
lt.reset(new MedianTreeNode<T>(min_val));
left_max = min_val;
} else {
lt->Insert(min_val, true);
left_max = std::max(min_val, left_max);
}
}
/**
* @brief Perform an LL rotation on a subtree node.
* @tparam T The type of samples_ stored in the nodes of this subtree.
* @param subtree The subtree needing a rotation.
* @return Root of the new subtree to be inserted into the old subtree's place.
*/
template<class T>
std::shared_ptr<MedianTreeNode<T>>
MedianTree<T>::LLRotate(std::shared_ptr<MedianTreeNode<T>> subtree) {
std::shared_ptr<MedianTreeNode<T>> tmp;
auto left_child = subtree->DetachSubtree(1);
auto right_child = subtree->DetachSubtree(-1);
subtree->InsertSubtree(left_child->DetachSubtree(-1)); // inserts on the left
subtree->InsertSubtree(right_child); // inserts on the right
tmp.swap(subtree);
left_child->InsertSubtree(tmp);
subtree.swap(left_child);
return subtree;
}
/**
* @brief Perform an LR rotation on a subtree node.
* @tparam T The type of samples_ stored in the nodes of this subtree.
* @param subtree The subtree needing a rotation.
* @return Root of the new subtree to be inserted into the old subtree's place.
*/
template<class T>
std::shared_ptr<MedianTreeNode<T>>
MedianTree<T>::LRRotate(std::shared_ptr<MedianTreeNode<T>> subtree) {
auto left_child = subtree->DetachSubtree(1);
auto tmp = left_child->DetachSubtree(-1);
subtree->InsertSubtree(tmp->DetachSubtree(-1)); // inserts on the left
left_child->InsertSubtree(tmp->DetachSubtree(1)); // inserts on the right
tmp->InsertSubtree(left_child); // inserts on the left
tmp->InsertSubtree(subtree); // inserts on the right
subtree.swap(tmp);
return subtree;
}
/**
* @brief Perform an RL rotation on a subtree.
* @tparam T The type of samples_ stored in the nodes of this subtree.
* @param subtree The subtree needing a rotation.
* @return Root of the new subtree to be inserted into the old subtree's place.
*/
template<class T>
std::shared_ptr<MedianTreeNode<T>>
MedianTree<T>::RLRotate(std::shared_ptr<MedianTreeNode<T>> subtree) {
auto right_child = subtree->DetachSubtree(-1);
auto tmp = right_child->DetachSubtree(1);
subtree->InsertSubtree(tmp->DetachSubtree(1)); // inserts on the right
right_child->InsertSubtree(tmp->DetachSubtree(-1)); // inserts on the left
tmp->InsertSubtree(right_child); // inserts on the right
tmp->InsertSubtree(subtree); // inserts on the left
subtree.swap(tmp);
return subtree;
}
/**
* @brief Perform an RR rotation on a subtree.
* @tparam T The type of samples_ stored in the nodes of this subtree.
* @param subtree The subtree needing a rotation.
* @return Root of the new subtree to be inserted into the old subtree's place.
*/
template<class T>
std::shared_ptr<MedianTreeNode<T>>
MedianTree<T>::RRRotate(std::shared_ptr<MedianTreeNode<T>> subtree) {
std::shared_ptr<MedianTreeNode<T>> tmp;
auto left_child = subtree->DetachSubtree(1);
auto right_child = subtree->DetachSubtree(-1);
// inserts on the right
subtree->InsertSubtree(right_child->DetachSubtree(1));
subtree->InsertSubtree(left_child); // inserts on the left
tmp.swap(subtree);
right_child->InsertSubtree(tmp);
subtree.swap(right_child);
return subtree;
}
#endif //RTS_2_MEDIAN_TREE_H | .text
.file "median_tree.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0008319c_00000000-6_median_tree.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3519:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3519:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3542:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3542:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "median_tree.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void matrix_2d_mul_float_gpu(float *A, float *B, float *C, int num_rows_A, int num_cols_A, int num_cols_B) {
// Create shared variables (Available to all threads on the same block)
__shared__ float A_tile[N_THREADS][N_THREADS];
__shared__ float B_tile[N_THREADS][N_THREADS];
// Block index
int bx = blockIdx.x; int by = blockIdx.y;
// Thread index
int tx = threadIdx.x; int ty = threadIdx.y;
// Index of the first sub-matrix of A processed by the block
int aBegin = num_cols_A * N_THREADS * by;
// Index of the last sub-matrix of A processed by the block
int aEnd = aBegin + num_cols_A - 1;
// Index of the first sub-matrix of B processed by the block
int bBegin = N_THREADS * bx;
int bStep = N_THREADS * num_cols_B;
int aStep = N_THREADS;
float sum = 0;
for (int a = aBegin, b = bBegin;a <= aEnd;a += aStep, b += bStep) {
A_tile[ty][tx] = A[a + num_cols_A * ty + tx];
B_tile[tx][ty] = B[b + num_cols_B * tx + ty];
// Synchronize to make sure the matrices are loaded
__syncthreads();
for (int k = 0; k < N_THREADS; ++k)
sum += A_tile[ty][k] * B_tile[k][tx];
// Wait other threads to finish their sub-matrices
__syncthreads();
}
// Write the block sub-matrix to device memory;
// each thread writes one element
int c = num_cols_B * N_THREADS * by + N_THREADS * bx;
C[c + num_cols_B * ty + tx] = sum;
} | code for sm_80
Function : _Z23matrix_2d_mul_float_gpuPfS_S_iii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2UR UR5, SR_CTAID.X ; /* 0x00000000000579c3 */
/* 0x000e220000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e620000002100 */
/*0030*/ MOV R0, c[0x0][0x17c] ; /* 0x00005f0000007a02 */
/* 0x000fe20000000f00 */
/*0040*/ ULDC.64 UR8, c[0x0][0x118] ; /* 0x0000460000087ab9 */
/* 0x000fe20000000a00 */
/*0050*/ HFMA2.MMA R15, -RZ, RZ, 0, 0 ; /* 0x00000000ff0f7435 */
/* 0x000fe200000001ff */
/*0060*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000ea20000002200 */
/*0070*/ ISETP.GE.AND P0, PT, R0, 0x1, PT ; /* 0x000000010000780c */
/* 0x000fe40003f06270 */
/*0080*/ MOV R0, c[0x0][0x180] ; /* 0x0000600000007a02 */
/* 0x000fe20000000f00 */
/*0090*/ S2UR UR10, SR_CTAID.Y ; /* 0x00000000000a79c3 */
/* 0x000ee60000002600 */
/*00a0*/ SHF.L.U32 R7, R0, 0x3, RZ ; /* 0x0000000300077819 */
/* 0x000fe200000006ff */
/*00b0*/ USHF.L.U32 UR5, UR5, 0x3, URZ ; /* 0x0000000305057899 */
/* 0x001fcc000800063f */
/*00c0*/ @!P0 BRA 0x880 ; /* 0x000007b000008947 */
/* 0x008fea0003800000 */
/*00d0*/ ULDC UR7, c[0x0][0x17c] ; /* 0x00005f0000077ab9 */
/* 0x002fe20000000800 */
/*00e0*/ LEA R5, R3, 0x100, 0x5 ; /* 0x0000010003057811 */
/* 0x000fe200078e28ff */
/*00f0*/ UIMAD UR4, UR10, UR7, URZ ; /* 0x000000070a0472a4 */
/* 0x000fe2000f8e023f */
/*0100*/ SHF.L.U32 R6, R2, 0x5, RZ ; /* 0x0000000502067819 */
/* 0x004fe200000006ff */
/*0110*/ ULEA UR6, UR10, 0x1, 0x3 ; /* 0x000000010a067891 */
/* 0x000fe2000f8e183f */
/*0120*/ MOV R9, UR5 ; /* 0x0000000500097c02 */
/* 0x000fe20008000f00 */
/*0130*/ USHF.L.U32 UR4, UR4, 0x3, URZ ; /* 0x0000000304047899 */
/* 0x000fe2000800063f */
/*0140*/ MOV R15, RZ ; /* 0x000000ff000f7202 */
/* 0x000fe20000000f00 */
/*0150*/ UIMAD UR6, UR6, UR7, URZ ; /* 0x00000007060672a4 */
/* 0x000fe4000f8e023f */
/*0160*/ UIADD3 UR7, UR4, 0x8, URZ ; /* 0x0000000804077890 */
/* 0x000fc4000fffe03f */
/*0170*/ LOP3.LUT R4, RZ, UR4, RZ, 0x33, !PT ; /* 0x00000004ff047c12 */
/* 0x000fe4000f8e33ff */
/*0180*/ UISETP.LT.AND UP0, UPT, UR6, UR7, UPT ; /* 0x000000070600728c */
/* 0x000fe2000bf01270 */
/*0190*/ MOV R18, UR4 ; /* 0x0000000400127c02 */
/* 0x000fc60008000f00 */
/*01a0*/ USEL UR6, UR6, UR7, !UP0 ; /* 0x0000000706067287 */
/* 0x000fcc000c000000 */
/*01b0*/ IADD3 R4, R4, UR6, RZ ; /* 0x0000000604047c10 */
/* 0x000fc8000fffe0ff */
/*01c0*/ LOP3.LUT P0, RZ, R4.reuse, 0x8, RZ, 0xc0, !PT ; /* 0x0000000804ff7812 */
/* 0x040fe4000780c0ff */
/*01d0*/ LOP3.LUT P1, RZ, R4, 0xfffffff8, RZ, 0xc0, !PT ; /* 0xfffffff804ff7812 */
/* 0x000fe4000782c0ff */
/*01e0*/ LEA R4, R2, R5, 0x2 ; /* 0x0000000502047211 */
/* 0x000fe400078e10ff */
/*01f0*/ LEA R5, R3, R6, 0x2 ; /* 0x0000000603057211 */
/* 0x000fce00078e10ff */
/*0200*/ @P0 BRA 0x420 ; /* 0x0000021000000947 */
/* 0x000fea0003800000 */
/*0210*/ IMAD R8, R2, c[0x0][0x17c], R3 ; /* 0x00005f0002087a24 */
/* 0x000fe200078e0203 */
/*0220*/ HFMA2.MMA R16, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff107435 */
/* 0x000fe200000001ff */
/*0230*/ IMAD R9, R3, c[0x0][0x180], R2 ; /* 0x0000600003097a24 */
/* 0x000fc600078e0202 */
/*0240*/ IADD3 R8, R8, UR4, RZ ; /* 0x0000000408087c10 */
/* 0x000fe4000fffe0ff */
/*0250*/ IADD3 R9, R9, UR5, RZ ; /* 0x0000000509097c10 */
/* 0x000fc8000fffe0ff */
/*0260*/ IMAD.WIDE R12, R8, R16, c[0x0][0x160] ; /* 0x00005800080c7625 */
/* 0x000fc800078e0210 */
/*0270*/ IMAD.WIDE R16, R9, R16, c[0x0][0x168] ; /* 0x00005a0009107625 */
/* 0x000fe200078e0210 */
/*0280*/ LDG.E R18, [R12.64] ; /* 0x000000080c127981 */
/* 0x000eaa000c1e1900 */
/*0290*/ LDG.E R17, [R16.64] ; /* 0x0000000810117981 */
/* 0x000ee8000c1e1900 */
/*02a0*/ STS [R5], R18 ; /* 0x0000001205007388 */
/* 0x004fe80000000800 */
/*02b0*/ STS [R4], R17 ; /* 0x0000001104007388 */
/* 0x008fe80000000800 */
/*02c0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*02d0*/ LDS R19, [R3.X4+0x100] ; /* 0x0001000003137984 */
/* 0x000fe80000004800 */
/*02e0*/ LDS.128 R8, [R6] ; /* 0x0000000006087984 */
/* 0x000e280000000c00 */
/*02f0*/ LDS R20, [R3.X4+0x120] ; /* 0x0001200003147984 */
/* 0x000e680000004800 */
/*0300*/ LDS R21, [R3.X4+0x140] ; /* 0x0001400003157984 */
/* 0x000ea80000004800 */
/*0310*/ LDS R22, [R3.X4+0x160] ; /* 0x0001600003167984 */
/* 0x000ee80000004800 */
/*0320*/ LDS R23, [R3.X4+0x180] ; /* 0x0001800003177984 */
/* 0x000fe80000004800 */
/*0330*/ LDS.128 R12, [R6+0x10] ; /* 0x00001000060c7984 */
/* 0x000f280000000c00 */
/*0340*/ LDS R24, [R3.X4+0x1a0] ; /* 0x0001a00003187984 */
/* 0x000f680000004800 */
/*0350*/ LDS R18, [R3.X4+0x1c0] ; /* 0x0001c00003127984 */
/* 0x000f680000004800 */
/*0360*/ LDS R16, [R3.X4+0x1e0] ; /* 0x0001e00003107984 */
/* 0x000f620000004800 */
/*0370*/ FFMA R8, R19, R8, RZ ; /* 0x0000000813087223 */
/* 0x001fc800000000ff */
/*0380*/ FFMA R9, R20, R9, R8 ; /* 0x0000000914097223 */
/* 0x002fc80000000008 */
/*0390*/ FFMA R10, R21, R10, R9 ; /* 0x0000000a150a7223 */
/* 0x004fe20000000009 */
/*03a0*/ IADD3 R9, R7, UR5, RZ ; /* 0x0000000507097c10 */
/* 0x000fc6000fffe0ff */
/*03b0*/ FFMA R11, R22, R11, R10 ; /* 0x0000000b160b7223 */
/* 0x008fc8000000000a */
/*03c0*/ FFMA R12, R23, R12, R11 ; /* 0x0000000c170c7223 */
/* 0x010fc8000000000b */
/*03d0*/ FFMA R13, R24, R13, R12 ; /* 0x0000000d180d7223 */
/* 0x020fc8000000000c */
/*03e0*/ FFMA R13, R18, R14, R13 ; /* 0x0000000e120d7223 */
/* 0x000fe2000000000d */
/*03f0*/ MOV R18, UR7 ; /* 0x0000000700127c02 */
/* 0x000fc60008000f00 */
/*0400*/ FFMA R15, R16, R15, R13 ; /* 0x0000000f100f7223 */
/* 0x000fe2000000000d */
/*0410*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0420*/ @!P1 BRA 0x880 ; /* 0x0000045000009947 */
/* 0x000fea0003800000 */
/*0430*/ IADD3 R11, R18, R3, RZ ; /* 0x00000003120b7210 */
/* 0x000fe20007ffe0ff */
/*0440*/ ULDC UR6, c[0x0][0x17c] ; /* 0x00005f0000067ab9 */
/* 0x000fe20000000800 */
/*0450*/ MOV R20, 0x4 ; /* 0x0000000400147802 */
/* 0x000fe20000000f00 */
/*0460*/ UIADD3 UR4, UR4, UR6, URZ ; /* 0x0000000604047290 */
/* 0x000fe2000fffe03f */
/*0470*/ IADD3 R10, R2.reuse, R9, RZ ; /* 0x00000009020a7210 */
/* 0x040fe20007ffe0ff */
/*0480*/ IMAD R11, R2, c[0x0][0x17c], R11 ; /* 0x00005f00020b7a24 */
/* 0x000fe200078e020b */
/*0490*/ IADD3 R21, R3, 0x8, RZ ; /* 0x0000000803157810 */
/* 0x000fc60007ffe0ff */
/*04a0*/ IMAD.WIDE R8, R11, R20, c[0x0][0x160] ; /* 0x000058000b087625 */
/* 0x000fc800078e0214 */
/*04b0*/ IMAD R21, R21, c[0x0][0x180], R10.reuse ; /* 0x0000600015157a24 */
/* 0x100fe200078e020a */
/*04c0*/ MOV R16, R8 ; /* 0x0000000800107202 */
/* 0x000fe20000000f00 */
/*04d0*/ IMAD R19, R3, c[0x0][0x180], R10 ; /* 0x0000600003137a24 */
/* 0x000fe200078e020a */
/*04e0*/ MOV R17, R9 ; /* 0x0000000900117202 */
/* 0x000fc80000000f00 */
/*04f0*/ IMAD.WIDE R12, R19, R20, c[0x0][0x168] ; /* 0x00005a00130c7625 */
/* 0x000fe200078e0214 */
/*0500*/ LDG.E R14, [R16.64] ; /* 0x00000008100e7981 */
/* 0x000eaa000c1e1900 */
/*0510*/ LDG.E R13, [R12.64] ; /* 0x000000080c0d7981 */
/* 0x000ee8000c1e1900 */
/*0520*/ STS [R5], R14 ; /* 0x0000000e05007388 */
/* 0x004fe80000000800 */
/*0530*/ STS [R4], R13 ; /* 0x0000000d04007388 */
/* 0x008fe80000000800 */
/*0540*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0550*/ LDS R22, [R3.X4+0x100] ; /* 0x0001000003167984 */
/* 0x000fe80000004800 */
/*0560*/ LDS.128 R8, [R6] ; /* 0x0000000006087984 */
/* 0x000e280000000c00 */
/*0570*/ LDS R23, [R3.X4+0x120] ; /* 0x0001200003177984 */
/* 0x000e680000004800 */
/*0580*/ LDS R24, [R3.X4+0x140] ; /* 0x0001400003187984 */
/* 0x000ea80000004800 */
/*0590*/ LDS R25, [R3.X4+0x160] ; /* 0x0001600003197984 */
/* 0x000ee80000004800 */
/*05a0*/ LDS R28, [R3.X4+0x1a0] ; /* 0x0001a000031c7984 */
/* 0x000fe80000004800 */
/*05b0*/ LDS R26, [R3.X4+0x1e0] ; /* 0x0001e000031a7984 */
/* 0x000fe20000004800 */
/*05c0*/ FFMA R8, R22, R8, R15 ; /* 0x0000000816087223 */
/* 0x001fc6000000000f */
/*05d0*/ LDS.128 R12, [R6+0x10] ; /* 0x00001000060c7984 */
/* 0x000fe20000000c00 */
/*05e0*/ FFMA R9, R23, R9, R8 ; /* 0x0000000917097223 */
/* 0x002fc60000000008 */
/*05f0*/ LDS R8, [R3.X4+0x180] ; /* 0x0001800003087984 */
/* 0x000e220000004800 */
/*0600*/ IMAD.WIDE R22, R21, R20, c[0x0][0x168] ; /* 0x00005a0015167625 */
/* 0x000fc800078e0214 */
/*0610*/ FFMA R10, R24, R10, R9 ; /* 0x0000000a180a7223 */
/* 0x004fc80000000009 */
/*0620*/ FFMA R11, R25, R11, R10 ; /* 0x0000000b190b7223 */
/* 0x008fe4000000000a */
/*0630*/ LDS R25, [R3.X4+0x1c0] ; /* 0x0001c00003197984 */
/* 0x000e680000004800 */
/*0640*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0650*/ LDG.E R29, [R16.64+0x20] ; /* 0x00002008101d7981 */
/* 0x0004e8000c1e1900 */
/*0660*/ LDG.E R23, [R22.64] ; /* 0x0000000816177981 */
/* 0x000f22000c1e1900 */
/*0670*/ FFMA R12, R8, R12, R11 ; /* 0x0000000c080c7223 */
/* 0x001fe2000000000b */
/*0680*/ IADD3 R18, R18, 0x10, RZ ; /* 0x0000001012127810 */
/* 0x000fc40007ffe0ff */
/*0690*/ LEA R19, R0, R19, 0x4 ; /* 0x0000001300137211 */
/* 0x000fe200078e20ff */
/*06a0*/ FFMA R12, R28, R13, R12 ; /* 0x0000000d1c0c7223 */
/* 0x000fe2000000000c */
/*06b0*/ ISETP.GE.AND P0, PT, R18, UR4, PT ; /* 0x0000000412007c0c */
/* 0x000fe4000bf06270 */
/*06c0*/ IADD3 R16, P1, R16, 0x40, RZ ; /* 0x0000004010107810 */
/* 0x004fe20007f3e0ff */
/*06d0*/ FFMA R12, R25, R14, R12 ; /* 0x0000000e190c7223 */
/* 0x002fe2000000000c */
/*06e0*/ LEA R21, R0, R21, 0x4 ; /* 0x0000001500157211 */
/* 0x000fe400078e20ff */
/*06f0*/ IADD3.X R17, RZ, R17, RZ, P1, !PT ; /* 0x00000011ff117210 */
/* 0x000fe20000ffe4ff */
/*0700*/ FFMA R12, R26, R15, R12 ; /* 0x0000000f1a0c7223 */
/* 0x000fe2000000000c */
/*0710*/ STS [R5], R29 ; /* 0x0000001d05007388 */
/* 0x008fe80000000800 */
/*0720*/ STS [R4], R23 ; /* 0x0000001704007388 */
/* 0x010fe80000000800 */
/*0730*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0740*/ LDS R27, [R3.X4+0x100] ; /* 0x00010000031b7984 */
/* 0x000fe80000004800 */
/*0750*/ LDS.128 R8, [R6] ; /* 0x0000000006087984 */
/* 0x000e280000000c00 */
/*0760*/ LDS R24, [R3.X4+0x120] ; /* 0x0001200003187984 */
/* 0x000e680000004800 */
/*0770*/ LDS R25, [R3.X4+0x140] ; /* 0x0001400003197984 */
/* 0x000ea80000004800 */
/*0780*/ LDS R22, [R3.X4+0x160] ; /* 0x0001600003167984 */
/* 0x000ee80000004800 */
/*0790*/ LDS R23, [R3.X4+0x180] ; /* 0x0001800003177984 */
/* 0x000fe80000004800 */
/*07a0*/ LDS R26, [R3.X4+0x1a0] ; /* 0x0001a000031a7984 */
/* 0x000fe20000004800 */
/*07b0*/ FFMA R8, R27, R8, R12 ; /* 0x000000081b087223 */
/* 0x001fc6000000000c */
/*07c0*/ LDS.128 R12, [R6+0x10] ; /* 0x00001000060c7984 */
/* 0x000e220000000c00 */
/*07d0*/ FFMA R24, R24, R9, R8 ; /* 0x0000000918187223 */
/* 0x002fc60000000008 */
/*07e0*/ LDS R9, [R3.X4+0x1c0] ; /* 0x0001c00003097984 */
/* 0x000e620000004800 */
/*07f0*/ FFMA R10, R25, R10, R24 ; /* 0x0000000a190a7223 */
/* 0x004fc60000000018 */
/*0800*/ LDS R8, [R3.X4+0x1e0] ; /* 0x0001e00003087984 */
/* 0x000ea20000004800 */
/*0810*/ FFMA R10, R22, R11, R10 ; /* 0x0000000b160a7223 */
/* 0x008fc8000000000a */
/*0820*/ FFMA R10, R23, R12, R10 ; /* 0x0000000c170a7223 */
/* 0x001fc8000000000a */
/*0830*/ FFMA R10, R26, R13, R10 ; /* 0x0000000d1a0a7223 */
/* 0x000fc8000000000a */
/*0840*/ FFMA R9, R9, R14, R10 ; /* 0x0000000e09097223 */
/* 0x002fc8000000000a */
/*0850*/ FFMA R15, R8, R15, R9 ; /* 0x0000000f080f7223 */
/* 0x004fe20000000009 */
/*0860*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0870*/ @!P0 BRA 0x4f0 ; /* 0xfffffc7000008947 */
/* 0x000fea000383ffff */
/*0880*/ IADD3 R3, R3, UR5, RZ ; /* 0x0000000503037c10 */
/* 0x002fca000fffe0ff */
/*0890*/ IMAD R2, R2, c[0x0][0x180], R3 ; /* 0x0000600002027a24 */
/* 0x004fe200078e0203 */
/*08a0*/ MOV R3, 0x4 ; /* 0x0000000400037802 */
/* 0x000fc60000000f00 */
/*08b0*/ IMAD R2, R7, UR10, R2 ; /* 0x0000000a07027c24 */
/* 0x000fc8000f8e0202 */
/*08c0*/ IMAD.WIDE R2, R2, R3, c[0x0][0x170] ; /* 0x00005c0002027625 */
/* 0x000fca00078e0203 */
/*08d0*/ STG.E [R2.64], R15 ; /* 0x0000000f02007986 */
/* 0x000fe2000c101908 */
/*08e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*08f0*/ BRA 0x8f0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0900*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0910*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0920*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0930*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0940*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0950*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0960*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0970*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void matrix_2d_mul_float_gpu(float *A, float *B, float *C, int num_rows_A, int num_cols_A, int num_cols_B) {
// Create shared variables (Available to all threads on the same block)
__shared__ float A_tile[N_THREADS][N_THREADS];
__shared__ float B_tile[N_THREADS][N_THREADS];
// Block index
int bx = blockIdx.x; int by = blockIdx.y;
// Thread index
int tx = threadIdx.x; int ty = threadIdx.y;
// Index of the first sub-matrix of A processed by the block
int aBegin = num_cols_A * N_THREADS * by;
// Index of the last sub-matrix of A processed by the block
int aEnd = aBegin + num_cols_A - 1;
// Index of the first sub-matrix of B processed by the block
int bBegin = N_THREADS * bx;
int bStep = N_THREADS * num_cols_B;
int aStep = N_THREADS;
float sum = 0;
for (int a = aBegin, b = bBegin;a <= aEnd;a += aStep, b += bStep) {
A_tile[ty][tx] = A[a + num_cols_A * ty + tx];
B_tile[tx][ty] = B[b + num_cols_B * tx + ty];
// Synchronize to make sure the matrices are loaded
__syncthreads();
for (int k = 0; k < N_THREADS; ++k)
sum += A_tile[ty][k] * B_tile[k][tx];
// Wait other threads to finish their sub-matrices
__syncthreads();
}
// Write the block sub-matrix to device memory;
// each thread writes one element
int c = num_cols_B * N_THREADS * by + N_THREADS * bx;
C[c + num_cols_B * ty + tx] = sum;
} | .file "tmpxft_00032a6b_00000000-6_matrix_2d_mul_float_gpu.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z50__device_stub__Z23matrix_2d_mul_float_gpuPfS_S_iiiPfS_S_iii
.type _Z50__device_stub__Z23matrix_2d_mul_float_gpuPfS_S_iiiPfS_S_iii, @function
_Z50__device_stub__Z23matrix_2d_mul_float_gpuPfS_S_iiiPfS_S_iii:
.LFB2051:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z23matrix_2d_mul_float_gpuPfS_S_iii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z50__device_stub__Z23matrix_2d_mul_float_gpuPfS_S_iiiPfS_S_iii, .-_Z50__device_stub__Z23matrix_2d_mul_float_gpuPfS_S_iiiPfS_S_iii
.globl _Z23matrix_2d_mul_float_gpuPfS_S_iii
.type _Z23matrix_2d_mul_float_gpuPfS_S_iii, @function
_Z23matrix_2d_mul_float_gpuPfS_S_iii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z50__device_stub__Z23matrix_2d_mul_float_gpuPfS_S_iiiPfS_S_iii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z23matrix_2d_mul_float_gpuPfS_S_iii, .-_Z23matrix_2d_mul_float_gpuPfS_S_iii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z23matrix_2d_mul_float_gpuPfS_S_iii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z23matrix_2d_mul_float_gpuPfS_S_iii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void matrix_2d_mul_float_gpu(float *A, float *B, float *C, int num_rows_A, int num_cols_A, int num_cols_B) {
// Create shared variables (Available to all threads on the same block)
__shared__ float A_tile[N_THREADS][N_THREADS];
__shared__ float B_tile[N_THREADS][N_THREADS];
// Block index
int bx = blockIdx.x; int by = blockIdx.y;
// Thread index
int tx = threadIdx.x; int ty = threadIdx.y;
// Index of the first sub-matrix of A processed by the block
int aBegin = num_cols_A * N_THREADS * by;
// Index of the last sub-matrix of A processed by the block
int aEnd = aBegin + num_cols_A - 1;
// Index of the first sub-matrix of B processed by the block
int bBegin = N_THREADS * bx;
int bStep = N_THREADS * num_cols_B;
int aStep = N_THREADS;
float sum = 0;
for (int a = aBegin, b = bBegin;a <= aEnd;a += aStep, b += bStep) {
A_tile[ty][tx] = A[a + num_cols_A * ty + tx];
B_tile[tx][ty] = B[b + num_cols_B * tx + ty];
// Synchronize to make sure the matrices are loaded
__syncthreads();
for (int k = 0; k < N_THREADS; ++k)
sum += A_tile[ty][k] * B_tile[k][tx];
// Wait other threads to finish their sub-matrices
__syncthreads();
}
// Write the block sub-matrix to device memory;
// each thread writes one element
int c = num_cols_B * N_THREADS * by + N_THREADS * bx;
C[c + num_cols_B * ty + tx] = sum;
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void matrix_2d_mul_float_gpu(float *A, float *B, float *C, int num_rows_A, int num_cols_A, int num_cols_B) {
// Create shared variables (Available to all threads on the same block)
__shared__ float A_tile[N_THREADS][N_THREADS];
__shared__ float B_tile[N_THREADS][N_THREADS];
// Block index
int bx = blockIdx.x; int by = blockIdx.y;
// Thread index
int tx = threadIdx.x; int ty = threadIdx.y;
// Index of the first sub-matrix of A processed by the block
int aBegin = num_cols_A * N_THREADS * by;
// Index of the last sub-matrix of A processed by the block
int aEnd = aBegin + num_cols_A - 1;
// Index of the first sub-matrix of B processed by the block
int bBegin = N_THREADS * bx;
int bStep = N_THREADS * num_cols_B;
int aStep = N_THREADS;
float sum = 0;
for (int a = aBegin, b = bBegin;a <= aEnd;a += aStep, b += bStep) {
A_tile[ty][tx] = A[a + num_cols_A * ty + tx];
B_tile[tx][ty] = B[b + num_cols_B * tx + ty];
// Synchronize to make sure the matrices are loaded
__syncthreads();
for (int k = 0; k < N_THREADS; ++k)
sum += A_tile[ty][k] * B_tile[k][tx];
// Wait other threads to finish their sub-matrices
__syncthreads();
}
// Write the block sub-matrix to device memory;
// each thread writes one element
int c = num_cols_B * N_THREADS * by + N_THREADS * bx;
C[c + num_cols_B * ty + tx] = sum;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void matrix_2d_mul_float_gpu(float *A, float *B, float *C, int num_rows_A, int num_cols_A, int num_cols_B) {
// Create shared variables (Available to all threads on the same block)
__shared__ float A_tile[N_THREADS][N_THREADS];
__shared__ float B_tile[N_THREADS][N_THREADS];
// Block index
int bx = blockIdx.x; int by = blockIdx.y;
// Thread index
int tx = threadIdx.x; int ty = threadIdx.y;
// Index of the first sub-matrix of A processed by the block
int aBegin = num_cols_A * N_THREADS * by;
// Index of the last sub-matrix of A processed by the block
int aEnd = aBegin + num_cols_A - 1;
// Index of the first sub-matrix of B processed by the block
int bBegin = N_THREADS * bx;
int bStep = N_THREADS * num_cols_B;
int aStep = N_THREADS;
float sum = 0;
for (int a = aBegin, b = bBegin;a <= aEnd;a += aStep, b += bStep) {
A_tile[ty][tx] = A[a + num_cols_A * ty + tx];
B_tile[tx][ty] = B[b + num_cols_B * tx + ty];
// Synchronize to make sure the matrices are loaded
__syncthreads();
for (int k = 0; k < N_THREADS; ++k)
sum += A_tile[ty][k] * B_tile[k][tx];
// Wait other threads to finish their sub-matrices
__syncthreads();
}
// Write the block sub-matrix to device memory;
// each thread writes one element
int c = num_cols_B * N_THREADS * by + N_THREADS * bx;
C[c + num_cols_B * ty + tx] = sum;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z23matrix_2d_mul_float_gpuPfS_S_iii
.globl _Z23matrix_2d_mul_float_gpuPfS_S_iii
.p2align 8
.type _Z23matrix_2d_mul_float_gpuPfS_S_iii,@function
_Z23matrix_2d_mul_float_gpuPfS_S_iii:
s_load_b64 s[2:3], s[0:1], 0x1c
v_and_b32_e32 v1, 0x3ff, v0
v_bfe_u32 v0, v0, 10, 10
s_lshl_b32 s9, s14, 3
s_waitcnt lgkmcnt(0)
s_lshl_b32 s8, s3, 3
s_cmp_lt_i32 s2, 1
s_cbranch_scc1 .LBB0_5
s_load_b128 s[4:7], s[0:1], 0x0
v_lshlrev_b32_e32 v8, 2, v1
v_lshlrev_b32_e32 v5, 5, v0
v_lshlrev_b32_e32 v7, 2, v0
v_lshlrev_b32_e32 v9, 5, v1
v_mad_u64_u32 v[2:3], null, v0, s2, v[1:2]
v_mad_u64_u32 v[3:4], null, v1, s3, v[0:1]
v_mov_b32_e32 v4, 0
s_mul_i32 s10, s2, s15
v_add_nc_u32_e32 v6, v5, v8
v_add3_u32 v7, v9, v7, 0x100
v_add_nc_u32_e32 v8, 0x100, v8
s_lshl_b32 s10, s10, 3
s_mov_b32 s11, s9
s_add_i32 s2, s10, s2
s_set_inst_prefetch_distance 0x1
.p2align 6
.LBB0_2:
v_add_nc_u32_e32 v9, s10, v2
v_add_nc_u32_e32 v11, s11, v3
s_mov_b32 s12, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v10, 31, v9
v_ashrrev_i32_e32 v12, 31, v11
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[9:10], 2, v[9:10]
v_lshlrev_b64 v[11:12], 2, v[11:12]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v9, vcc_lo, s4, v9
v_add_co_ci_u32_e32 v10, vcc_lo, s5, v10, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v11, vcc_lo, s6, v11
v_add_co_ci_u32_e32 v12, vcc_lo, s7, v12, vcc_lo
global_load_b32 v10, v[9:10], off
global_load_b32 v11, v[11:12], off
v_mov_b32_e32 v9, v8
s_waitcnt vmcnt(1)
ds_store_b32 v6, v10
s_waitcnt vmcnt(0)
ds_store_b32 v7, v11
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
.LBB0_3:
v_add_nc_u32_e32 v10, s12, v5
s_add_i32 s12, s12, 4
ds_load_b32 v11, v9
ds_load_b32 v10, v10
v_add_nc_u32_e32 v9, 32, v9
s_cmp_eq_u32 s12, 32
s_waitcnt lgkmcnt(0)
v_fmac_f32_e32 v4, v10, v11
s_cbranch_scc0 .LBB0_3
s_add_i32 s10, s10, 8
s_add_i32 s11, s11, s8
s_cmp_ge_i32 s10, s2
s_barrier
buffer_gl0_inv
s_cbranch_scc0 .LBB0_2
s_branch .LBB0_6
.LBB0_5:
v_mov_b32_e32 v4, 0
.LBB0_6:
s_set_inst_prefetch_distance 0x2
v_mul_lo_u32 v0, v0, s3
v_add_nc_u32_e32 v1, s9, v1
s_load_b64 s[0:1], s[0:1], 0x10
s_mul_i32 s8, s8, s15
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_add3_u32 v0, v1, v0, s8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v4, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z23matrix_2d_mul_float_gpuPfS_S_iii
.amdhsa_group_segment_fixed_size 512
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 36
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 13
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z23matrix_2d_mul_float_gpuPfS_S_iii, .Lfunc_end0-_Z23matrix_2d_mul_float_gpuPfS_S_iii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 512
.kernarg_segment_align: 8
.kernarg_segment_size: 36
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z23matrix_2d_mul_float_gpuPfS_S_iii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z23matrix_2d_mul_float_gpuPfS_S_iii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 13
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void matrix_2d_mul_float_gpu(float *A, float *B, float *C, int num_rows_A, int num_cols_A, int num_cols_B) {
// Create shared variables (Available to all threads on the same block)
__shared__ float A_tile[N_THREADS][N_THREADS];
__shared__ float B_tile[N_THREADS][N_THREADS];
// Block index
int bx = blockIdx.x; int by = blockIdx.y;
// Thread index
int tx = threadIdx.x; int ty = threadIdx.y;
// Index of the first sub-matrix of A processed by the block
int aBegin = num_cols_A * N_THREADS * by;
// Index of the last sub-matrix of A processed by the block
int aEnd = aBegin + num_cols_A - 1;
// Index of the first sub-matrix of B processed by the block
int bBegin = N_THREADS * bx;
int bStep = N_THREADS * num_cols_B;
int aStep = N_THREADS;
float sum = 0;
for (int a = aBegin, b = bBegin;a <= aEnd;a += aStep, b += bStep) {
A_tile[ty][tx] = A[a + num_cols_A * ty + tx];
B_tile[tx][ty] = B[b + num_cols_B * tx + ty];
// Synchronize to make sure the matrices are loaded
__syncthreads();
for (int k = 0; k < N_THREADS; ++k)
sum += A_tile[ty][k] * B_tile[k][tx];
// Wait other threads to finish their sub-matrices
__syncthreads();
}
// Write the block sub-matrix to device memory;
// each thread writes one element
int c = num_cols_B * N_THREADS * by + N_THREADS * bx;
C[c + num_cols_B * ty + tx] = sum;
} | .text
.file "matrix_2d_mul_float_gpu.hip"
.globl _Z38__device_stub__matrix_2d_mul_float_gpuPfS_S_iii # -- Begin function _Z38__device_stub__matrix_2d_mul_float_gpuPfS_S_iii
.p2align 4, 0x90
.type _Z38__device_stub__matrix_2d_mul_float_gpuPfS_S_iii,@function
_Z38__device_stub__matrix_2d_mul_float_gpuPfS_S_iii: # @_Z38__device_stub__matrix_2d_mul_float_gpuPfS_S_iii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z23matrix_2d_mul_float_gpuPfS_S_iii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z38__device_stub__matrix_2d_mul_float_gpuPfS_S_iii, .Lfunc_end0-_Z38__device_stub__matrix_2d_mul_float_gpuPfS_S_iii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z23matrix_2d_mul_float_gpuPfS_S_iii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z23matrix_2d_mul_float_gpuPfS_S_iii,@object # @_Z23matrix_2d_mul_float_gpuPfS_S_iii
.section .rodata,"a",@progbits
.globl _Z23matrix_2d_mul_float_gpuPfS_S_iii
.p2align 3, 0x0
_Z23matrix_2d_mul_float_gpuPfS_S_iii:
.quad _Z38__device_stub__matrix_2d_mul_float_gpuPfS_S_iii
.size _Z23matrix_2d_mul_float_gpuPfS_S_iii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z23matrix_2d_mul_float_gpuPfS_S_iii"
.size .L__unnamed_1, 37
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z38__device_stub__matrix_2d_mul_float_gpuPfS_S_iii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z23matrix_2d_mul_float_gpuPfS_S_iii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z23matrix_2d_mul_float_gpuPfS_S_iii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2UR UR5, SR_CTAID.X ; /* 0x00000000000579c3 */
/* 0x000e220000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e620000002100 */
/*0030*/ MOV R0, c[0x0][0x17c] ; /* 0x00005f0000007a02 */
/* 0x000fe20000000f00 */
/*0040*/ ULDC.64 UR8, c[0x0][0x118] ; /* 0x0000460000087ab9 */
/* 0x000fe20000000a00 */
/*0050*/ HFMA2.MMA R15, -RZ, RZ, 0, 0 ; /* 0x00000000ff0f7435 */
/* 0x000fe200000001ff */
/*0060*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000ea20000002200 */
/*0070*/ ISETP.GE.AND P0, PT, R0, 0x1, PT ; /* 0x000000010000780c */
/* 0x000fe40003f06270 */
/*0080*/ MOV R0, c[0x0][0x180] ; /* 0x0000600000007a02 */
/* 0x000fe20000000f00 */
/*0090*/ S2UR UR10, SR_CTAID.Y ; /* 0x00000000000a79c3 */
/* 0x000ee60000002600 */
/*00a0*/ SHF.L.U32 R7, R0, 0x3, RZ ; /* 0x0000000300077819 */
/* 0x000fe200000006ff */
/*00b0*/ USHF.L.U32 UR5, UR5, 0x3, URZ ; /* 0x0000000305057899 */
/* 0x001fcc000800063f */
/*00c0*/ @!P0 BRA 0x880 ; /* 0x000007b000008947 */
/* 0x008fea0003800000 */
/*00d0*/ ULDC UR7, c[0x0][0x17c] ; /* 0x00005f0000077ab9 */
/* 0x002fe20000000800 */
/*00e0*/ LEA R5, R3, 0x100, 0x5 ; /* 0x0000010003057811 */
/* 0x000fe200078e28ff */
/*00f0*/ UIMAD UR4, UR10, UR7, URZ ; /* 0x000000070a0472a4 */
/* 0x000fe2000f8e023f */
/*0100*/ SHF.L.U32 R6, R2, 0x5, RZ ; /* 0x0000000502067819 */
/* 0x004fe200000006ff */
/*0110*/ ULEA UR6, UR10, 0x1, 0x3 ; /* 0x000000010a067891 */
/* 0x000fe2000f8e183f */
/*0120*/ MOV R9, UR5 ; /* 0x0000000500097c02 */
/* 0x000fe20008000f00 */
/*0130*/ USHF.L.U32 UR4, UR4, 0x3, URZ ; /* 0x0000000304047899 */
/* 0x000fe2000800063f */
/*0140*/ MOV R15, RZ ; /* 0x000000ff000f7202 */
/* 0x000fe20000000f00 */
/*0150*/ UIMAD UR6, UR6, UR7, URZ ; /* 0x00000007060672a4 */
/* 0x000fe4000f8e023f */
/*0160*/ UIADD3 UR7, UR4, 0x8, URZ ; /* 0x0000000804077890 */
/* 0x000fc4000fffe03f */
/*0170*/ LOP3.LUT R4, RZ, UR4, RZ, 0x33, !PT ; /* 0x00000004ff047c12 */
/* 0x000fe4000f8e33ff */
/*0180*/ UISETP.LT.AND UP0, UPT, UR6, UR7, UPT ; /* 0x000000070600728c */
/* 0x000fe2000bf01270 */
/*0190*/ MOV R18, UR4 ; /* 0x0000000400127c02 */
/* 0x000fc60008000f00 */
/*01a0*/ USEL UR6, UR6, UR7, !UP0 ; /* 0x0000000706067287 */
/* 0x000fcc000c000000 */
/*01b0*/ IADD3 R4, R4, UR6, RZ ; /* 0x0000000604047c10 */
/* 0x000fc8000fffe0ff */
/*01c0*/ LOP3.LUT P0, RZ, R4.reuse, 0x8, RZ, 0xc0, !PT ; /* 0x0000000804ff7812 */
/* 0x040fe4000780c0ff */
/*01d0*/ LOP3.LUT P1, RZ, R4, 0xfffffff8, RZ, 0xc0, !PT ; /* 0xfffffff804ff7812 */
/* 0x000fe4000782c0ff */
/*01e0*/ LEA R4, R2, R5, 0x2 ; /* 0x0000000502047211 */
/* 0x000fe400078e10ff */
/*01f0*/ LEA R5, R3, R6, 0x2 ; /* 0x0000000603057211 */
/* 0x000fce00078e10ff */
/*0200*/ @P0 BRA 0x420 ; /* 0x0000021000000947 */
/* 0x000fea0003800000 */
/*0210*/ IMAD R8, R2, c[0x0][0x17c], R3 ; /* 0x00005f0002087a24 */
/* 0x000fe200078e0203 */
/*0220*/ HFMA2.MMA R16, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff107435 */
/* 0x000fe200000001ff */
/*0230*/ IMAD R9, R3, c[0x0][0x180], R2 ; /* 0x0000600003097a24 */
/* 0x000fc600078e0202 */
/*0240*/ IADD3 R8, R8, UR4, RZ ; /* 0x0000000408087c10 */
/* 0x000fe4000fffe0ff */
/*0250*/ IADD3 R9, R9, UR5, RZ ; /* 0x0000000509097c10 */
/* 0x000fc8000fffe0ff */
/*0260*/ IMAD.WIDE R12, R8, R16, c[0x0][0x160] ; /* 0x00005800080c7625 */
/* 0x000fc800078e0210 */
/*0270*/ IMAD.WIDE R16, R9, R16, c[0x0][0x168] ; /* 0x00005a0009107625 */
/* 0x000fe200078e0210 */
/*0280*/ LDG.E R18, [R12.64] ; /* 0x000000080c127981 */
/* 0x000eaa000c1e1900 */
/*0290*/ LDG.E R17, [R16.64] ; /* 0x0000000810117981 */
/* 0x000ee8000c1e1900 */
/*02a0*/ STS [R5], R18 ; /* 0x0000001205007388 */
/* 0x004fe80000000800 */
/*02b0*/ STS [R4], R17 ; /* 0x0000001104007388 */
/* 0x008fe80000000800 */
/*02c0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*02d0*/ LDS R19, [R3.X4+0x100] ; /* 0x0001000003137984 */
/* 0x000fe80000004800 */
/*02e0*/ LDS.128 R8, [R6] ; /* 0x0000000006087984 */
/* 0x000e280000000c00 */
/*02f0*/ LDS R20, [R3.X4+0x120] ; /* 0x0001200003147984 */
/* 0x000e680000004800 */
/*0300*/ LDS R21, [R3.X4+0x140] ; /* 0x0001400003157984 */
/* 0x000ea80000004800 */
/*0310*/ LDS R22, [R3.X4+0x160] ; /* 0x0001600003167984 */
/* 0x000ee80000004800 */
/*0320*/ LDS R23, [R3.X4+0x180] ; /* 0x0001800003177984 */
/* 0x000fe80000004800 */
/*0330*/ LDS.128 R12, [R6+0x10] ; /* 0x00001000060c7984 */
/* 0x000f280000000c00 */
/*0340*/ LDS R24, [R3.X4+0x1a0] ; /* 0x0001a00003187984 */
/* 0x000f680000004800 */
/*0350*/ LDS R18, [R3.X4+0x1c0] ; /* 0x0001c00003127984 */
/* 0x000f680000004800 */
/*0360*/ LDS R16, [R3.X4+0x1e0] ; /* 0x0001e00003107984 */
/* 0x000f620000004800 */
/*0370*/ FFMA R8, R19, R8, RZ ; /* 0x0000000813087223 */
/* 0x001fc800000000ff */
/*0380*/ FFMA R9, R20, R9, R8 ; /* 0x0000000914097223 */
/* 0x002fc80000000008 */
/*0390*/ FFMA R10, R21, R10, R9 ; /* 0x0000000a150a7223 */
/* 0x004fe20000000009 */
/*03a0*/ IADD3 R9, R7, UR5, RZ ; /* 0x0000000507097c10 */
/* 0x000fc6000fffe0ff */
/*03b0*/ FFMA R11, R22, R11, R10 ; /* 0x0000000b160b7223 */
/* 0x008fc8000000000a */
/*03c0*/ FFMA R12, R23, R12, R11 ; /* 0x0000000c170c7223 */
/* 0x010fc8000000000b */
/*03d0*/ FFMA R13, R24, R13, R12 ; /* 0x0000000d180d7223 */
/* 0x020fc8000000000c */
/*03e0*/ FFMA R13, R18, R14, R13 ; /* 0x0000000e120d7223 */
/* 0x000fe2000000000d */
/*03f0*/ MOV R18, UR7 ; /* 0x0000000700127c02 */
/* 0x000fc60008000f00 */
/*0400*/ FFMA R15, R16, R15, R13 ; /* 0x0000000f100f7223 */
/* 0x000fe2000000000d */
/*0410*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0420*/ @!P1 BRA 0x880 ; /* 0x0000045000009947 */
/* 0x000fea0003800000 */
/*0430*/ IADD3 R11, R18, R3, RZ ; /* 0x00000003120b7210 */
/* 0x000fe20007ffe0ff */
/*0440*/ ULDC UR6, c[0x0][0x17c] ; /* 0x00005f0000067ab9 */
/* 0x000fe20000000800 */
/*0450*/ MOV R20, 0x4 ; /* 0x0000000400147802 */
/* 0x000fe20000000f00 */
/*0460*/ UIADD3 UR4, UR4, UR6, URZ ; /* 0x0000000604047290 */
/* 0x000fe2000fffe03f */
/*0470*/ IADD3 R10, R2.reuse, R9, RZ ; /* 0x00000009020a7210 */
/* 0x040fe20007ffe0ff */
/*0480*/ IMAD R11, R2, c[0x0][0x17c], R11 ; /* 0x00005f00020b7a24 */
/* 0x000fe200078e020b */
/*0490*/ IADD3 R21, R3, 0x8, RZ ; /* 0x0000000803157810 */
/* 0x000fc60007ffe0ff */
/*04a0*/ IMAD.WIDE R8, R11, R20, c[0x0][0x160] ; /* 0x000058000b087625 */
/* 0x000fc800078e0214 */
/*04b0*/ IMAD R21, R21, c[0x0][0x180], R10.reuse ; /* 0x0000600015157a24 */
/* 0x100fe200078e020a */
/*04c0*/ MOV R16, R8 ; /* 0x0000000800107202 */
/* 0x000fe20000000f00 */
/*04d0*/ IMAD R19, R3, c[0x0][0x180], R10 ; /* 0x0000600003137a24 */
/* 0x000fe200078e020a */
/*04e0*/ MOV R17, R9 ; /* 0x0000000900117202 */
/* 0x000fc80000000f00 */
/*04f0*/ IMAD.WIDE R12, R19, R20, c[0x0][0x168] ; /* 0x00005a00130c7625 */
/* 0x000fe200078e0214 */
/*0500*/ LDG.E R14, [R16.64] ; /* 0x00000008100e7981 */
/* 0x000eaa000c1e1900 */
/*0510*/ LDG.E R13, [R12.64] ; /* 0x000000080c0d7981 */
/* 0x000ee8000c1e1900 */
/*0520*/ STS [R5], R14 ; /* 0x0000000e05007388 */
/* 0x004fe80000000800 */
/*0530*/ STS [R4], R13 ; /* 0x0000000d04007388 */
/* 0x008fe80000000800 */
/*0540*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0550*/ LDS R22, [R3.X4+0x100] ; /* 0x0001000003167984 */
/* 0x000fe80000004800 */
/*0560*/ LDS.128 R8, [R6] ; /* 0x0000000006087984 */
/* 0x000e280000000c00 */
/*0570*/ LDS R23, [R3.X4+0x120] ; /* 0x0001200003177984 */
/* 0x000e680000004800 */
/*0580*/ LDS R24, [R3.X4+0x140] ; /* 0x0001400003187984 */
/* 0x000ea80000004800 */
/*0590*/ LDS R25, [R3.X4+0x160] ; /* 0x0001600003197984 */
/* 0x000ee80000004800 */
/*05a0*/ LDS R28, [R3.X4+0x1a0] ; /* 0x0001a000031c7984 */
/* 0x000fe80000004800 */
/*05b0*/ LDS R26, [R3.X4+0x1e0] ; /* 0x0001e000031a7984 */
/* 0x000fe20000004800 */
/*05c0*/ FFMA R8, R22, R8, R15 ; /* 0x0000000816087223 */
/* 0x001fc6000000000f */
/*05d0*/ LDS.128 R12, [R6+0x10] ; /* 0x00001000060c7984 */
/* 0x000fe20000000c00 */
/*05e0*/ FFMA R9, R23, R9, R8 ; /* 0x0000000917097223 */
/* 0x002fc60000000008 */
/*05f0*/ LDS R8, [R3.X4+0x180] ; /* 0x0001800003087984 */
/* 0x000e220000004800 */
/*0600*/ IMAD.WIDE R22, R21, R20, c[0x0][0x168] ; /* 0x00005a0015167625 */
/* 0x000fc800078e0214 */
/*0610*/ FFMA R10, R24, R10, R9 ; /* 0x0000000a180a7223 */
/* 0x004fc80000000009 */
/*0620*/ FFMA R11, R25, R11, R10 ; /* 0x0000000b190b7223 */
/* 0x008fe4000000000a */
/*0630*/ LDS R25, [R3.X4+0x1c0] ; /* 0x0001c00003197984 */
/* 0x000e680000004800 */
/*0640*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0650*/ LDG.E R29, [R16.64+0x20] ; /* 0x00002008101d7981 */
/* 0x0004e8000c1e1900 */
/*0660*/ LDG.E R23, [R22.64] ; /* 0x0000000816177981 */
/* 0x000f22000c1e1900 */
/*0670*/ FFMA R12, R8, R12, R11 ; /* 0x0000000c080c7223 */
/* 0x001fe2000000000b */
/*0680*/ IADD3 R18, R18, 0x10, RZ ; /* 0x0000001012127810 */
/* 0x000fc40007ffe0ff */
/*0690*/ LEA R19, R0, R19, 0x4 ; /* 0x0000001300137211 */
/* 0x000fe200078e20ff */
/*06a0*/ FFMA R12, R28, R13, R12 ; /* 0x0000000d1c0c7223 */
/* 0x000fe2000000000c */
/*06b0*/ ISETP.GE.AND P0, PT, R18, UR4, PT ; /* 0x0000000412007c0c */
/* 0x000fe4000bf06270 */
/*06c0*/ IADD3 R16, P1, R16, 0x40, RZ ; /* 0x0000004010107810 */
/* 0x004fe20007f3e0ff */
/*06d0*/ FFMA R12, R25, R14, R12 ; /* 0x0000000e190c7223 */
/* 0x002fe2000000000c */
/*06e0*/ LEA R21, R0, R21, 0x4 ; /* 0x0000001500157211 */
/* 0x000fe400078e20ff */
/*06f0*/ IADD3.X R17, RZ, R17, RZ, P1, !PT ; /* 0x00000011ff117210 */
/* 0x000fe20000ffe4ff */
/*0700*/ FFMA R12, R26, R15, R12 ; /* 0x0000000f1a0c7223 */
/* 0x000fe2000000000c */
/*0710*/ STS [R5], R29 ; /* 0x0000001d05007388 */
/* 0x008fe80000000800 */
/*0720*/ STS [R4], R23 ; /* 0x0000001704007388 */
/* 0x010fe80000000800 */
/*0730*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0740*/ LDS R27, [R3.X4+0x100] ; /* 0x00010000031b7984 */
/* 0x000fe80000004800 */
/*0750*/ LDS.128 R8, [R6] ; /* 0x0000000006087984 */
/* 0x000e280000000c00 */
/*0760*/ LDS R24, [R3.X4+0x120] ; /* 0x0001200003187984 */
/* 0x000e680000004800 */
/*0770*/ LDS R25, [R3.X4+0x140] ; /* 0x0001400003197984 */
/* 0x000ea80000004800 */
/*0780*/ LDS R22, [R3.X4+0x160] ; /* 0x0001600003167984 */
/* 0x000ee80000004800 */
/*0790*/ LDS R23, [R3.X4+0x180] ; /* 0x0001800003177984 */
/* 0x000fe80000004800 */
/*07a0*/ LDS R26, [R3.X4+0x1a0] ; /* 0x0001a000031a7984 */
/* 0x000fe20000004800 */
/*07b0*/ FFMA R8, R27, R8, R12 ; /* 0x000000081b087223 */
/* 0x001fc6000000000c */
/*07c0*/ LDS.128 R12, [R6+0x10] ; /* 0x00001000060c7984 */
/* 0x000e220000000c00 */
/*07d0*/ FFMA R24, R24, R9, R8 ; /* 0x0000000918187223 */
/* 0x002fc60000000008 */
/*07e0*/ LDS R9, [R3.X4+0x1c0] ; /* 0x0001c00003097984 */
/* 0x000e620000004800 */
/*07f0*/ FFMA R10, R25, R10, R24 ; /* 0x0000000a190a7223 */
/* 0x004fc60000000018 */
/*0800*/ LDS R8, [R3.X4+0x1e0] ; /* 0x0001e00003087984 */
/* 0x000ea20000004800 */
/*0810*/ FFMA R10, R22, R11, R10 ; /* 0x0000000b160a7223 */
/* 0x008fc8000000000a */
/*0820*/ FFMA R10, R23, R12, R10 ; /* 0x0000000c170a7223 */
/* 0x001fc8000000000a */
/*0830*/ FFMA R10, R26, R13, R10 ; /* 0x0000000d1a0a7223 */
/* 0x000fc8000000000a */
/*0840*/ FFMA R9, R9, R14, R10 ; /* 0x0000000e09097223 */
/* 0x002fc8000000000a */
/*0850*/ FFMA R15, R8, R15, R9 ; /* 0x0000000f080f7223 */
/* 0x004fe20000000009 */
/*0860*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0870*/ @!P0 BRA 0x4f0 ; /* 0xfffffc7000008947 */
/* 0x000fea000383ffff */
/*0880*/ IADD3 R3, R3, UR5, RZ ; /* 0x0000000503037c10 */
/* 0x002fca000fffe0ff */
/*0890*/ IMAD R2, R2, c[0x0][0x180], R3 ; /* 0x0000600002027a24 */
/* 0x004fe200078e0203 */
/*08a0*/ MOV R3, 0x4 ; /* 0x0000000400037802 */
/* 0x000fc60000000f00 */
/*08b0*/ IMAD R2, R7, UR10, R2 ; /* 0x0000000a07027c24 */
/* 0x000fc8000f8e0202 */
/*08c0*/ IMAD.WIDE R2, R2, R3, c[0x0][0x170] ; /* 0x00005c0002027625 */
/* 0x000fca00078e0203 */
/*08d0*/ STG.E [R2.64], R15 ; /* 0x0000000f02007986 */
/* 0x000fe2000c101908 */
/*08e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*08f0*/ BRA 0x8f0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0900*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0910*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0920*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0930*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0940*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0950*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0960*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0970*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z23matrix_2d_mul_float_gpuPfS_S_iii
.globl _Z23matrix_2d_mul_float_gpuPfS_S_iii
.p2align 8
.type _Z23matrix_2d_mul_float_gpuPfS_S_iii,@function
_Z23matrix_2d_mul_float_gpuPfS_S_iii:
s_load_b64 s[2:3], s[0:1], 0x1c
v_and_b32_e32 v1, 0x3ff, v0
v_bfe_u32 v0, v0, 10, 10
s_lshl_b32 s9, s14, 3
s_waitcnt lgkmcnt(0)
s_lshl_b32 s8, s3, 3
s_cmp_lt_i32 s2, 1
s_cbranch_scc1 .LBB0_5
s_load_b128 s[4:7], s[0:1], 0x0
v_lshlrev_b32_e32 v8, 2, v1
v_lshlrev_b32_e32 v5, 5, v0
v_lshlrev_b32_e32 v7, 2, v0
v_lshlrev_b32_e32 v9, 5, v1
v_mad_u64_u32 v[2:3], null, v0, s2, v[1:2]
v_mad_u64_u32 v[3:4], null, v1, s3, v[0:1]
v_mov_b32_e32 v4, 0
s_mul_i32 s10, s2, s15
v_add_nc_u32_e32 v6, v5, v8
v_add3_u32 v7, v9, v7, 0x100
v_add_nc_u32_e32 v8, 0x100, v8
s_lshl_b32 s10, s10, 3
s_mov_b32 s11, s9
s_add_i32 s2, s10, s2
s_set_inst_prefetch_distance 0x1
.p2align 6
.LBB0_2:
v_add_nc_u32_e32 v9, s10, v2
v_add_nc_u32_e32 v11, s11, v3
s_mov_b32 s12, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v10, 31, v9
v_ashrrev_i32_e32 v12, 31, v11
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[9:10], 2, v[9:10]
v_lshlrev_b64 v[11:12], 2, v[11:12]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v9, vcc_lo, s4, v9
v_add_co_ci_u32_e32 v10, vcc_lo, s5, v10, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v11, vcc_lo, s6, v11
v_add_co_ci_u32_e32 v12, vcc_lo, s7, v12, vcc_lo
global_load_b32 v10, v[9:10], off
global_load_b32 v11, v[11:12], off
v_mov_b32_e32 v9, v8
s_waitcnt vmcnt(1)
ds_store_b32 v6, v10
s_waitcnt vmcnt(0)
ds_store_b32 v7, v11
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
.LBB0_3:
v_add_nc_u32_e32 v10, s12, v5
s_add_i32 s12, s12, 4
ds_load_b32 v11, v9
ds_load_b32 v10, v10
v_add_nc_u32_e32 v9, 32, v9
s_cmp_eq_u32 s12, 32
s_waitcnt lgkmcnt(0)
v_fmac_f32_e32 v4, v10, v11
s_cbranch_scc0 .LBB0_3
s_add_i32 s10, s10, 8
s_add_i32 s11, s11, s8
s_cmp_ge_i32 s10, s2
s_barrier
buffer_gl0_inv
s_cbranch_scc0 .LBB0_2
s_branch .LBB0_6
.LBB0_5:
v_mov_b32_e32 v4, 0
.LBB0_6:
s_set_inst_prefetch_distance 0x2
v_mul_lo_u32 v0, v0, s3
v_add_nc_u32_e32 v1, s9, v1
s_load_b64 s[0:1], s[0:1], 0x10
s_mul_i32 s8, s8, s15
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_add3_u32 v0, v1, v0, s8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v4, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z23matrix_2d_mul_float_gpuPfS_S_iii
.amdhsa_group_segment_fixed_size 512
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 36
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 13
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z23matrix_2d_mul_float_gpuPfS_S_iii, .Lfunc_end0-_Z23matrix_2d_mul_float_gpuPfS_S_iii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 512
.kernarg_segment_align: 8
.kernarg_segment_size: 36
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z23matrix_2d_mul_float_gpuPfS_S_iii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z23matrix_2d_mul_float_gpuPfS_S_iii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 13
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00032a6b_00000000-6_matrix_2d_mul_float_gpu.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z50__device_stub__Z23matrix_2d_mul_float_gpuPfS_S_iiiPfS_S_iii
.type _Z50__device_stub__Z23matrix_2d_mul_float_gpuPfS_S_iiiPfS_S_iii, @function
_Z50__device_stub__Z23matrix_2d_mul_float_gpuPfS_S_iiiPfS_S_iii:
.LFB2051:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z23matrix_2d_mul_float_gpuPfS_S_iii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z50__device_stub__Z23matrix_2d_mul_float_gpuPfS_S_iiiPfS_S_iii, .-_Z50__device_stub__Z23matrix_2d_mul_float_gpuPfS_S_iiiPfS_S_iii
.globl _Z23matrix_2d_mul_float_gpuPfS_S_iii
.type _Z23matrix_2d_mul_float_gpuPfS_S_iii, @function
_Z23matrix_2d_mul_float_gpuPfS_S_iii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z50__device_stub__Z23matrix_2d_mul_float_gpuPfS_S_iiiPfS_S_iii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z23matrix_2d_mul_float_gpuPfS_S_iii, .-_Z23matrix_2d_mul_float_gpuPfS_S_iii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z23matrix_2d_mul_float_gpuPfS_S_iii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z23matrix_2d_mul_float_gpuPfS_S_iii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "matrix_2d_mul_float_gpu.hip"
.globl _Z38__device_stub__matrix_2d_mul_float_gpuPfS_S_iii # -- Begin function _Z38__device_stub__matrix_2d_mul_float_gpuPfS_S_iii
.p2align 4, 0x90
.type _Z38__device_stub__matrix_2d_mul_float_gpuPfS_S_iii,@function
_Z38__device_stub__matrix_2d_mul_float_gpuPfS_S_iii: # @_Z38__device_stub__matrix_2d_mul_float_gpuPfS_S_iii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z23matrix_2d_mul_float_gpuPfS_S_iii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z38__device_stub__matrix_2d_mul_float_gpuPfS_S_iii, .Lfunc_end0-_Z38__device_stub__matrix_2d_mul_float_gpuPfS_S_iii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z23matrix_2d_mul_float_gpuPfS_S_iii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z23matrix_2d_mul_float_gpuPfS_S_iii,@object # @_Z23matrix_2d_mul_float_gpuPfS_S_iii
.section .rodata,"a",@progbits
.globl _Z23matrix_2d_mul_float_gpuPfS_S_iii
.p2align 3, 0x0
_Z23matrix_2d_mul_float_gpuPfS_S_iii:
.quad _Z38__device_stub__matrix_2d_mul_float_gpuPfS_S_iii
.size _Z23matrix_2d_mul_float_gpuPfS_S_iii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z23matrix_2d_mul_float_gpuPfS_S_iii"
.size .L__unnamed_1, 37
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z38__device_stub__matrix_2d_mul_float_gpuPfS_S_iii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z23matrix_2d_mul_float_gpuPfS_S_iii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <inttypes.h>
#include <math.h>
#include <sys/time.h>
#include <cuda_runtime.h>
const int block_size = 1024;
const int n = 4 * (1 << 20);
void reduce_cpu(int *v, int n, int *sum)
{
/*
int s = 0.0;
for (int i = 0; i < n; i++)
s += v[i];
*sum = s;
*/
// Kahan's summation algorithm
int s = v[0];
int c = (int)0.0;
for (int i = 1; i < n; i++) {
int y = v[i] - c;
int t = s + y;
c = (t - s) - y;
s = t;
}
*sum = s;
}
__global__ void reduce_per_block(int *v, int n, int *per_block_sum)
{
__shared__ int sdata[block_size];
int tid = threadIdx.x;
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i < n) {
sdata[tid] = v[i];
__syncthreads();
for (int s = 1; s < blockDim.x; s *= 2) {
if (tid % (2 * s) == 0)
sdata[tid] += sdata[tid + s];
__syncthreads();
}
if (tid == 0)
per_block_sum[blockIdx.x] = sdata[0];
}
}
double wtime()
{
struct timeval t;
gettimeofday(&t, NULL);
return (double)t.tv_sec + (double)t.tv_usec * 1E-6;
}
int main()
{
double tcpu = 0, tgpu = 0, tmem = 0;
size_t size = sizeof(int) * n;
int *v = (int *)malloc(size);
srand(0);
for (size_t i = 0; i < n; i++)
v[i] = i + 1;
int sum;
tcpu = -wtime();
reduce_cpu(v, n, &sum);
tcpu += wtime();
/* Allocate on device */
int threads_per_block = block_size;
int blocks = (n + threads_per_block - 1) / threads_per_block;
int *dv;
int *per_block_sum;
int *sums = (int *)malloc(sizeof(int) * blocks);
tmem = -wtime();
cudaMalloc((void **)&per_block_sum, sizeof(int) * blocks);
cudaMalloc((void **)&dv, size);
cudaMemcpy(dv, v, size, cudaMemcpyHostToDevice);
tmem += wtime();
printf("CUDA kernel launch with %d blocks of %d threads\n", blocks, threads_per_block);
fflush(stdout);
/* Compute per block sum */
tgpu = -wtime();
reduce_per_block<<<blocks, threads_per_block>>>(dv, n, per_block_sum);
cudaDeviceSynchronize();
tgpu += wtime();
tmem = -wtime();
cudaMemcpy(sums, per_block_sum, sizeof(int) * blocks, cudaMemcpyDeviceToHost);
tmem += wtime();
/* Compute block sum */
tgpu -= wtime();
int sum_gpu = 0;
for (int i = 0; i < blocks; i++)
sum_gpu += sums[i];
tgpu += wtime();
printf("Sum (CPU) = %d\n", sum);
printf("Sum (GPU) = %d\n", sum_gpu);
printf("CPU version (sec.): %.6f\n", tcpu);
printf("GPU version (sec.): %.6f\n", tgpu);
printf("GPU bandwidth (GiB/s): %.2f\n", 1.0e-9 * size / (tgpu + tmem));
printf("Speedup: %.2f\n", tcpu / tgpu);
printf("Speedup (with mem ops.): %.2f\n", tcpu / (tgpu + tmem));
cudaFree(per_block_sum);
cudaFree(dv);
free(sums);
free(v);
cudaDeviceReset();
return 0;
} | code for sm_80
Function : _Z16reduce_per_blockPiiS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R4, R0, c[0x0][0x0], R3 ; /* 0x0000000000047a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R4, c[0x0][0x168], PT ; /* 0x00005a0004007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; /* 0x00000004ff057424 */
/* 0x000fe200078e00ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0080*/ IMAD.WIDE R4, R4, R5, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fcc00078e0205 */
/*0090*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ MOV R2, c[0x0][0x0] ; /* 0x0000000000027a02 */
/* 0x000fe40000000f00 */
/*00b0*/ ISETP.NE.AND P0, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fe40003f05270 */
/*00c0*/ ISETP.GE.U32.AND P1, PT, R2, 0x2, PT ; /* 0x000000020200780c */
/* 0x000fe20003f26070 */
/*00d0*/ STS [R3.X4], R4 ; /* 0x0000000403007388 */
/* 0x0041e80000004800 */
/*00e0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000ff00000010000 */
/*00f0*/ @!P1 BRA 0x350 ; /* 0x0000025000009947 */
/* 0x000fea0003800000 */
/*0100*/ IABS R8, R3 ; /* 0x0000000300087213 */
/* 0x001fe20000000000 */
/*0110*/ IMAD.SHL.U32 R2, R3, 0x4, RZ ; /* 0x0000000403027824 */
/* 0x000fc400078e00ff */
/*0120*/ IMAD.MOV.U32 R7, RZ, RZ, 0x1 ; /* 0x00000001ff077424 */
/* 0x000fca00078e00ff */
/*0130*/ SHF.L.U32 R11, R7, 0x1, RZ ; /* 0x00000001070b7819 */
/* 0x000fe400000006ff */
/*0140*/ IABS R13, R3 ; /* 0x00000003000d7213 */
/* 0x000fe40000000000 */
/*0150*/ IABS R10, R11.reuse ; /* 0x0000000b000a7213 */
/* 0x080fe40000000000 */
/*0160*/ IABS R12, R11 ; /* 0x0000000b000c7213 */
/* 0x000fe40000000000 */
/*0170*/ I2F.RP R6, R10 ; /* 0x0000000a00067306 */
/* 0x000e220000209400 */
/*0180*/ ISETP.GE.AND P3, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fce0003f66270 */
/*0190*/ MUFU.RCP R6, R6 ; /* 0x0000000600067308 */
/* 0x001e240000001000 */
/*01a0*/ IADD3 R4, R6, 0xffffffe, RZ ; /* 0x0ffffffe06047810 */
/* 0x001fe40007ffe0ff */
/*01b0*/ IADD3 R6, RZ, -R12, RZ ; /* 0x8000000cff067210 */
/* 0x000fc80007ffe0ff */
/*01c0*/ F2I.FTZ.U32.TRUNC.NTZ R5, R4 ; /* 0x0000000400057305 */
/* 0x000064000021f000 */
/*01d0*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x001fe400078e00ff */
/*01e0*/ IMAD.MOV R9, RZ, RZ, -R5 ; /* 0x000000ffff097224 */
/* 0x002fc800078e0a05 */
/*01f0*/ IMAD R9, R9, R10, RZ ; /* 0x0000000a09097224 */
/* 0x000fc800078e02ff */
/*0200*/ IMAD.HI.U32 R5, R5, R9, R4 ; /* 0x0000000905057227 */
/* 0x000fc800078e0004 */
/*0210*/ IMAD.MOV.U32 R9, RZ, RZ, R13 ; /* 0x000000ffff097224 */
/* 0x000fe400078e000d */
/*0220*/ IMAD.HI.U32 R5, R5, R8, RZ ; /* 0x0000000805057227 */
/* 0x000fc800078e00ff */
/*0230*/ IMAD R5, R5, R6, R9 ; /* 0x0000000605057224 */
/* 0x000fca00078e0209 */
/*0240*/ ISETP.GT.U32.AND P1, PT, R10, R5, PT ; /* 0x000000050a00720c */
/* 0x000fda0003f24070 */
/*0250*/ @!P1 IMAD.IADD R5, R5, 0x1, -R10 ; /* 0x0000000105059824 */
/* 0x000fe200078e0a0a */
/*0260*/ ISETP.NE.AND P1, PT, R11, RZ, PT ; /* 0x000000ff0b00720c */
/* 0x000fc80003f25270 */
/*0270*/ ISETP.GT.U32.AND P2, PT, R10, R5, PT ; /* 0x000000050a00720c */
/* 0x000fda0003f44070 */
/*0280*/ @!P2 IADD3 R5, R5, -R10, RZ ; /* 0x8000000a0505a210 */
/* 0x000fca0007ffe0ff */
/*0290*/ @!P3 IMAD.MOV R5, RZ, RZ, -R5 ; /* 0x000000ffff05b224 */
/* 0x000fe200078e0a05 */
/*02a0*/ @!P1 LOP3.LUT R5, RZ, R11, RZ, 0x33, !PT ; /* 0x0000000bff059212 */
/* 0x000fc800078e33ff */
/*02b0*/ ISETP.NE.AND P1, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fda0003f25270 */
/*02c0*/ @!P1 IMAD R4, R7, 0x4, R2 ; /* 0x0000000407049824 */
/* 0x000fe200078e0202 */
/*02d0*/ @!P1 LDS R5, [R3.X4] ; /* 0x0000000003059984 */
/* 0x000fe20000004800 */
/*02e0*/ IMAD.MOV.U32 R7, RZ, RZ, R11 ; /* 0x000000ffff077224 */
/* 0x000fc800078e000b */
/*02f0*/ @!P1 LDS R4, [R4] ; /* 0x0000000004049984 */
/* 0x000e240000000800 */
/*0300*/ @!P1 IADD3 R6, R5, R4, RZ ; /* 0x0000000405069210 */
/* 0x001fca0007ffe0ff */
/*0310*/ @!P1 STS [R3.X4], R6 ; /* 0x0000000603009388 */
/* 0x0001e80000004800 */
/*0320*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0330*/ ISETP.GE.U32.AND P1, PT, R11, c[0x0][0x0], PT ; /* 0x000000000b007a0c */
/* 0x000fda0003f26070 */
/*0340*/ @!P1 BRA 0x130 ; /* 0xfffffde000009947 */
/* 0x001fea000383ffff */
/*0350*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x001fea0003800000 */
/*0360*/ LDS R5, [RZ] ; /* 0x00000000ff057984 */
/* 0x000e220000000800 */
/*0370*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fd400000001ff */
/*0380*/ IMAD.WIDE.U32 R2, R0, R3, c[0x0][0x170] ; /* 0x00005c0000027625 */
/* 0x000fca00078e0003 */
/*0390*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x001fe2000c101904 */
/*03a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*03b0*/ BRA 0x3b0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*03c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0400*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0410*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0420*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0430*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0440*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0450*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0460*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0470*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <inttypes.h>
#include <math.h>
#include <sys/time.h>
#include <cuda_runtime.h>
const int block_size = 1024;
const int n = 4 * (1 << 20);
void reduce_cpu(int *v, int n, int *sum)
{
/*
int s = 0.0;
for (int i = 0; i < n; i++)
s += v[i];
*sum = s;
*/
// Kahan's summation algorithm
int s = v[0];
int c = (int)0.0;
for (int i = 1; i < n; i++) {
int y = v[i] - c;
int t = s + y;
c = (t - s) - y;
s = t;
}
*sum = s;
}
__global__ void reduce_per_block(int *v, int n, int *per_block_sum)
{
__shared__ int sdata[block_size];
int tid = threadIdx.x;
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i < n) {
sdata[tid] = v[i];
__syncthreads();
for (int s = 1; s < blockDim.x; s *= 2) {
if (tid % (2 * s) == 0)
sdata[tid] += sdata[tid + s];
__syncthreads();
}
if (tid == 0)
per_block_sum[blockIdx.x] = sdata[0];
}
}
double wtime()
{
struct timeval t;
gettimeofday(&t, NULL);
return (double)t.tv_sec + (double)t.tv_usec * 1E-6;
}
int main()
{
double tcpu = 0, tgpu = 0, tmem = 0;
size_t size = sizeof(int) * n;
int *v = (int *)malloc(size);
srand(0);
for (size_t i = 0; i < n; i++)
v[i] = i + 1;
int sum;
tcpu = -wtime();
reduce_cpu(v, n, &sum);
tcpu += wtime();
/* Allocate on device */
int threads_per_block = block_size;
int blocks = (n + threads_per_block - 1) / threads_per_block;
int *dv;
int *per_block_sum;
int *sums = (int *)malloc(sizeof(int) * blocks);
tmem = -wtime();
cudaMalloc((void **)&per_block_sum, sizeof(int) * blocks);
cudaMalloc((void **)&dv, size);
cudaMemcpy(dv, v, size, cudaMemcpyHostToDevice);
tmem += wtime();
printf("CUDA kernel launch with %d blocks of %d threads\n", blocks, threads_per_block);
fflush(stdout);
/* Compute per block sum */
tgpu = -wtime();
reduce_per_block<<<blocks, threads_per_block>>>(dv, n, per_block_sum);
cudaDeviceSynchronize();
tgpu += wtime();
tmem = -wtime();
cudaMemcpy(sums, per_block_sum, sizeof(int) * blocks, cudaMemcpyDeviceToHost);
tmem += wtime();
/* Compute block sum */
tgpu -= wtime();
int sum_gpu = 0;
for (int i = 0; i < blocks; i++)
sum_gpu += sums[i];
tgpu += wtime();
printf("Sum (CPU) = %d\n", sum);
printf("Sum (GPU) = %d\n", sum_gpu);
printf("CPU version (sec.): %.6f\n", tcpu);
printf("GPU version (sec.): %.6f\n", tgpu);
printf("GPU bandwidth (GiB/s): %.2f\n", 1.0e-9 * size / (tgpu + tmem));
printf("Speedup: %.2f\n", tcpu / tgpu);
printf("Speedup (with mem ops.): %.2f\n", tcpu / (tgpu + tmem));
cudaFree(per_block_sum);
cudaFree(dv);
free(sums);
free(v);
cudaDeviceReset();
return 0;
} | .file "tmpxft_00031caf_00000000-6_reduction.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z10reduce_cpuPiiS_
.type _Z10reduce_cpuPiiS_, @function
_Z10reduce_cpuPiiS_:
.LFB2057:
.cfi_startproc
endbr64
movl (%rdi), %ecx
cmpl $1, %esi
jle .L4
leaq 4(%rdi), %rax
leal -2(%rsi), %esi
leaq 8(%rdi,%rsi,4), %rsi
.L5:
addl (%rax), %ecx
addq $4, %rax
cmpq %rsi, %rax
jne .L5
.L4:
movl %ecx, (%rdx)
ret
.cfi_endproc
.LFE2057:
.size _Z10reduce_cpuPiiS_, .-_Z10reduce_cpuPiiS_
.globl _Z5wtimev
.type _Z5wtimev, @function
_Z5wtimev:
.LFB2058:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movq %fs:40, %rax
movq %rax, 24(%rsp)
xorl %eax, %eax
movq %rsp, %rdi
movl $0, %esi
call gettimeofday@PLT
pxor %xmm0, %xmm0
cvtsi2sdq 8(%rsp), %xmm0
mulsd .LC0(%rip), %xmm0
pxor %xmm1, %xmm1
cvtsi2sdq (%rsp), %xmm1
addsd %xmm1, %xmm0
movq 24(%rsp), %rax
subq %fs:40, %rax
jne .L10
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L10:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size _Z5wtimev, .-_Z5wtimev
.globl _Z39__device_stub__Z16reduce_per_blockPiiS_PiiS_
.type _Z39__device_stub__Z16reduce_per_blockPiiS_PiiS_, @function
_Z39__device_stub__Z16reduce_per_blockPiiS_PiiS_:
.LFB2084:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z16reduce_per_blockPiiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z39__device_stub__Z16reduce_per_blockPiiS_PiiS_, .-_Z39__device_stub__Z16reduce_per_blockPiiS_PiiS_
.globl _Z16reduce_per_blockPiiS_
.type _Z16reduce_per_blockPiiS_, @function
_Z16reduce_per_blockPiiS_:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z39__device_stub__Z16reduce_per_blockPiiS_PiiS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z16reduce_per_blockPiiS_, .-_Z16reduce_per_blockPiiS_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "CUDA kernel launch with %d blocks of %d threads\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "Sum (CPU) = %d\n"
.LC3:
.string "Sum (GPU) = %d\n"
.LC4:
.string "CPU version (sec.): %.6f\n"
.LC5:
.string "GPU version (sec.): %.6f\n"
.LC7:
.string "GPU bandwidth (GiB/s): %.2f\n"
.LC8:
.string "Speedup: %.2f\n"
.section .rodata.str1.8
.align 8
.LC9:
.string "Speedup (with mem ops.): %.2f\n"
.text
.globl main
.type main, @function
main:
.LFB2059:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $104, %rsp
.cfi_def_cfa_offset 144
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
movl $16777216, %edi
call malloc@PLT
movq %rax, %rbp
movl $0, %edi
call srand@PLT
movl $1, %eax
.L20:
movl %eax, -4(%rbp,%rax,4)
addq $1, %rax
cmpq $4194305, %rax
jne .L20
call _Z5wtimev
movsd %xmm0, 8(%rsp)
leaq 44(%rsp), %rdx
movl $4194304, %esi
movq %rbp, %rdi
call _Z10reduce_cpuPiiS_
call _Z5wtimev
movapd %xmm0, %xmm4
subsd 8(%rsp), %xmm4
movsd %xmm4, 8(%rsp)
movl $16384, %edi
call malloc@PLT
movq %rax, %r12
call _Z5wtimev
leaq 56(%rsp), %rdi
movl $16384, %esi
call cudaMalloc@PLT
leaq 48(%rsp), %rdi
movl $16777216, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $16777216, %edx
movq %rbp, %rsi
movq 48(%rsp), %rdi
call cudaMemcpy@PLT
call _Z5wtimev
movl $1024, %ecx
movl $4096, %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq stdout(%rip), %rdi
call fflush@PLT
call _Z5wtimev
movsd %xmm0, 16(%rsp)
movl $1024, 76(%rsp)
movl $1, 80(%rsp)
movl $4096, 64(%rsp)
movl $1, 68(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 76(%rsp), %rdx
movl $1, %ecx
movq 64(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L27
.L21:
call cudaDeviceSynchronize@PLT
call _Z5wtimev
subsd 16(%rsp), %xmm0
movq %xmm0, %rbx
call _Z5wtimev
movsd %xmm0, 16(%rsp)
movl $2, %ecx
movl $16384, %edx
movq 56(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
call _Z5wtimev
movapd %xmm0, %xmm5
subsd 16(%rsp), %xmm5
movq %xmm5, %r14
call _Z5wtimev
movq %rbx, %xmm6
subsd %xmm0, %xmm6
movsd %xmm6, 16(%rsp)
movq %r12, %rax
leaq 16384(%r12), %rcx
movl $0, %edx
.L22:
movl %edx, %ebx
addl (%rax), %ebx
movl %ebx, %edx
addq $4, %rax
cmpq %rcx, %rax
jne .L22
call _Z5wtimev
addsd 16(%rsp), %xmm0
movsd %xmm0, 16(%rsp)
movl 44(%rsp), %edx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %ebx, %edx
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movsd 8(%rsp), %xmm0
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movsd 16(%rsp), %xmm0
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq %r14, %xmm3
addsd 16(%rsp), %xmm3
movsd .LC6(%rip), %xmm0
movsd %xmm3, 24(%rsp)
divsd %xmm3, %xmm0
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movsd 8(%rsp), %xmm2
divsd 16(%rsp), %xmm2
movapd %xmm2, %xmm0
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movsd 8(%rsp), %xmm0
divsd 24(%rsp), %xmm0
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 56(%rsp), %rdi
call cudaFree@PLT
movq 48(%rsp), %rdi
call cudaFree@PLT
movq %r12, %rdi
call free@PLT
movq %rbp, %rdi
call free@PLT
call cudaDeviceReset@PLT
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L28
movl $0, %eax
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L27:
.cfi_restore_state
movq 56(%rsp), %rdx
movl $4194304, %esi
movq 48(%rsp), %rdi
call _Z39__device_stub__Z16reduce_per_blockPiiS_PiiS_
jmp .L21
.L28:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size main, .-main
.section .rodata.str1.1
.LC10:
.string "_Z16reduce_per_blockPiiS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC10(%rip), %rdx
movq %rdx, %rcx
leaq _Z16reduce_per_blockPiiS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long -1598689907
.long 1051772663
.align 8
.LC6:
.long -400107883
.long 1066479115
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <inttypes.h>
#include <math.h>
#include <sys/time.h>
#include <cuda_runtime.h>
const int block_size = 1024;
const int n = 4 * (1 << 20);
void reduce_cpu(int *v, int n, int *sum)
{
/*
int s = 0.0;
for (int i = 0; i < n; i++)
s += v[i];
*sum = s;
*/
// Kahan's summation algorithm
int s = v[0];
int c = (int)0.0;
for (int i = 1; i < n; i++) {
int y = v[i] - c;
int t = s + y;
c = (t - s) - y;
s = t;
}
*sum = s;
}
__global__ void reduce_per_block(int *v, int n, int *per_block_sum)
{
__shared__ int sdata[block_size];
int tid = threadIdx.x;
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i < n) {
sdata[tid] = v[i];
__syncthreads();
for (int s = 1; s < blockDim.x; s *= 2) {
if (tid % (2 * s) == 0)
sdata[tid] += sdata[tid + s];
__syncthreads();
}
if (tid == 0)
per_block_sum[blockIdx.x] = sdata[0];
}
}
double wtime()
{
struct timeval t;
gettimeofday(&t, NULL);
return (double)t.tv_sec + (double)t.tv_usec * 1E-6;
}
int main()
{
double tcpu = 0, tgpu = 0, tmem = 0;
size_t size = sizeof(int) * n;
int *v = (int *)malloc(size);
srand(0);
for (size_t i = 0; i < n; i++)
v[i] = i + 1;
int sum;
tcpu = -wtime();
reduce_cpu(v, n, &sum);
tcpu += wtime();
/* Allocate on device */
int threads_per_block = block_size;
int blocks = (n + threads_per_block - 1) / threads_per_block;
int *dv;
int *per_block_sum;
int *sums = (int *)malloc(sizeof(int) * blocks);
tmem = -wtime();
cudaMalloc((void **)&per_block_sum, sizeof(int) * blocks);
cudaMalloc((void **)&dv, size);
cudaMemcpy(dv, v, size, cudaMemcpyHostToDevice);
tmem += wtime();
printf("CUDA kernel launch with %d blocks of %d threads\n", blocks, threads_per_block);
fflush(stdout);
/* Compute per block sum */
tgpu = -wtime();
reduce_per_block<<<blocks, threads_per_block>>>(dv, n, per_block_sum);
cudaDeviceSynchronize();
tgpu += wtime();
tmem = -wtime();
cudaMemcpy(sums, per_block_sum, sizeof(int) * blocks, cudaMemcpyDeviceToHost);
tmem += wtime();
/* Compute block sum */
tgpu -= wtime();
int sum_gpu = 0;
for (int i = 0; i < blocks; i++)
sum_gpu += sums[i];
tgpu += wtime();
printf("Sum (CPU) = %d\n", sum);
printf("Sum (GPU) = %d\n", sum_gpu);
printf("CPU version (sec.): %.6f\n", tcpu);
printf("GPU version (sec.): %.6f\n", tgpu);
printf("GPU bandwidth (GiB/s): %.2f\n", 1.0e-9 * size / (tgpu + tmem));
printf("Speedup: %.2f\n", tcpu / tgpu);
printf("Speedup (with mem ops.): %.2f\n", tcpu / (tgpu + tmem));
cudaFree(per_block_sum);
cudaFree(dv);
free(sums);
free(v);
cudaDeviceReset();
return 0;
} | #include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <inttypes.h>
#include <math.h>
#include <sys/time.h>
#include <hip/hip_runtime.h>
const int block_size = 1024;
const int n = 4 * (1 << 20);
void reduce_cpu(int *v, int n, int *sum)
{
/*
int s = 0.0;
for (int i = 0; i < n; i++)
s += v[i];
*sum = s;
*/
// Kahan's summation algorithm
int s = v[0];
int c = (int)0.0;
for (int i = 1; i < n; i++) {
int y = v[i] - c;
int t = s + y;
c = (t - s) - y;
s = t;
}
*sum = s;
}
__global__ void reduce_per_block(int *v, int n, int *per_block_sum)
{
__shared__ int sdata[block_size];
int tid = threadIdx.x;
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i < n) {
sdata[tid] = v[i];
__syncthreads();
for (int s = 1; s < blockDim.x; s *= 2) {
if (tid % (2 * s) == 0)
sdata[tid] += sdata[tid + s];
__syncthreads();
}
if (tid == 0)
per_block_sum[blockIdx.x] = sdata[0];
}
}
double wtime()
{
struct timeval t;
gettimeofday(&t, NULL);
return (double)t.tv_sec + (double)t.tv_usec * 1E-6;
}
int main()
{
double tcpu = 0, tgpu = 0, tmem = 0;
size_t size = sizeof(int) * n;
int *v = (int *)malloc(size);
srand(0);
for (size_t i = 0; i < n; i++)
v[i] = i + 1;
int sum;
tcpu = -wtime();
reduce_cpu(v, n, &sum);
tcpu += wtime();
/* Allocate on device */
int threads_per_block = block_size;
int blocks = (n + threads_per_block - 1) / threads_per_block;
int *dv;
int *per_block_sum;
int *sums = (int *)malloc(sizeof(int) * blocks);
tmem = -wtime();
hipMalloc((void **)&per_block_sum, sizeof(int) * blocks);
hipMalloc((void **)&dv, size);
hipMemcpy(dv, v, size, hipMemcpyHostToDevice);
tmem += wtime();
printf("CUDA kernel launch with %d blocks of %d threads\n", blocks, threads_per_block);
fflush(stdout);
/* Compute per block sum */
tgpu = -wtime();
reduce_per_block<<<blocks, threads_per_block>>>(dv, n, per_block_sum);
hipDeviceSynchronize();
tgpu += wtime();
tmem = -wtime();
hipMemcpy(sums, per_block_sum, sizeof(int) * blocks, hipMemcpyDeviceToHost);
tmem += wtime();
/* Compute block sum */
tgpu -= wtime();
int sum_gpu = 0;
for (int i = 0; i < blocks; i++)
sum_gpu += sums[i];
tgpu += wtime();
printf("Sum (CPU) = %d\n", sum);
printf("Sum (GPU) = %d\n", sum_gpu);
printf("CPU version (sec.): %.6f\n", tcpu);
printf("GPU version (sec.): %.6f\n", tgpu);
printf("GPU bandwidth (GiB/s): %.2f\n", 1.0e-9 * size / (tgpu + tmem));
printf("Speedup: %.2f\n", tcpu / tgpu);
printf("Speedup (with mem ops.): %.2f\n", tcpu / (tgpu + tmem));
hipFree(per_block_sum);
hipFree(dv);
free(sums);
free(v);
hipDeviceReset();
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <inttypes.h>
#include <math.h>
#include <sys/time.h>
#include <hip/hip_runtime.h>
const int block_size = 1024;
const int n = 4 * (1 << 20);
void reduce_cpu(int *v, int n, int *sum)
{
/*
int s = 0.0;
for (int i = 0; i < n; i++)
s += v[i];
*sum = s;
*/
// Kahan's summation algorithm
int s = v[0];
int c = (int)0.0;
for (int i = 1; i < n; i++) {
int y = v[i] - c;
int t = s + y;
c = (t - s) - y;
s = t;
}
*sum = s;
}
__global__ void reduce_per_block(int *v, int n, int *per_block_sum)
{
__shared__ int sdata[block_size];
int tid = threadIdx.x;
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i < n) {
sdata[tid] = v[i];
__syncthreads();
for (int s = 1; s < blockDim.x; s *= 2) {
if (tid % (2 * s) == 0)
sdata[tid] += sdata[tid + s];
__syncthreads();
}
if (tid == 0)
per_block_sum[blockIdx.x] = sdata[0];
}
}
double wtime()
{
struct timeval t;
gettimeofday(&t, NULL);
return (double)t.tv_sec + (double)t.tv_usec * 1E-6;
}
int main()
{
double tcpu = 0, tgpu = 0, tmem = 0;
size_t size = sizeof(int) * n;
int *v = (int *)malloc(size);
srand(0);
for (size_t i = 0; i < n; i++)
v[i] = i + 1;
int sum;
tcpu = -wtime();
reduce_cpu(v, n, &sum);
tcpu += wtime();
/* Allocate on device */
int threads_per_block = block_size;
int blocks = (n + threads_per_block - 1) / threads_per_block;
int *dv;
int *per_block_sum;
int *sums = (int *)malloc(sizeof(int) * blocks);
tmem = -wtime();
hipMalloc((void **)&per_block_sum, sizeof(int) * blocks);
hipMalloc((void **)&dv, size);
hipMemcpy(dv, v, size, hipMemcpyHostToDevice);
tmem += wtime();
printf("CUDA kernel launch with %d blocks of %d threads\n", blocks, threads_per_block);
fflush(stdout);
/* Compute per block sum */
tgpu = -wtime();
reduce_per_block<<<blocks, threads_per_block>>>(dv, n, per_block_sum);
hipDeviceSynchronize();
tgpu += wtime();
tmem = -wtime();
hipMemcpy(sums, per_block_sum, sizeof(int) * blocks, hipMemcpyDeviceToHost);
tmem += wtime();
/* Compute block sum */
tgpu -= wtime();
int sum_gpu = 0;
for (int i = 0; i < blocks; i++)
sum_gpu += sums[i];
tgpu += wtime();
printf("Sum (CPU) = %d\n", sum);
printf("Sum (GPU) = %d\n", sum_gpu);
printf("CPU version (sec.): %.6f\n", tcpu);
printf("GPU version (sec.): %.6f\n", tgpu);
printf("GPU bandwidth (GiB/s): %.2f\n", 1.0e-9 * size / (tgpu + tmem));
printf("Speedup: %.2f\n", tcpu / tgpu);
printf("Speedup (with mem ops.): %.2f\n", tcpu / (tgpu + tmem));
hipFree(per_block_sum);
hipFree(dv);
free(sums);
free(v);
hipDeviceReset();
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z16reduce_per_blockPiiS_
.globl _Z16reduce_per_blockPiiS_
.p2align 8
.type _Z16reduce_per_blockPiiS_,@function
_Z16reduce_per_blockPiiS_:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x24
s_load_b32 s4, s[0:1], 0x8
s_mov_b32 s2, s15
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s2, s3, v[0:1]
v_cmp_gt_i32_e32 vcc_lo, s4, v1
s_and_saveexec_b32 s4, vcc_lo
s_cbranch_execz .LBB0_8
s_load_b64 s[4:5], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_cmp_lt_u32 s3, 2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v1, vcc_lo, s4, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, s5, v2, vcc_lo
global_load_b32 v2, v[1:2], off
v_lshlrev_b32_e32 v1, 2, v0
s_waitcnt vmcnt(0)
ds_store_b32 v1, v2
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_6
s_mov_b32 s5, 1
s_branch .LBB0_4
.p2align 6
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s6
s_cmp_ge_u32 s4, s3
s_mov_b32 s5, s4
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_6
.LBB0_4:
s_lshl_b32 s4, s5, 1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s6, s4, -1
v_and_b32_e32 v2, s6, v0
s_mov_b32 s6, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_eq_u32_e32 0, v2
s_cbranch_execz .LBB0_3
v_add_lshl_u32 v2, s5, v0, 2
ds_load_b32 v2, v2
ds_load_b32 v3, v1
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v2, v3, v2
ds_store_b32 v1, v2
s_branch .LBB0_3
.LBB0_6:
v_cmp_eq_u32_e32 vcc_lo, 0, v0
s_mov_b32 s3, 0
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_8
v_mov_b32_e32 v0, 0
s_load_b64 s[0:1], s[0:1], 0x10
s_lshl_b64 s[2:3], s[2:3], 2
ds_load_b32 v1, v0
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
global_store_b32 v0, v1, s[0:1]
.LBB0_8:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z16reduce_per_blockPiiS_
.amdhsa_group_segment_fixed_size 4096
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z16reduce_per_blockPiiS_, .Lfunc_end0-_Z16reduce_per_blockPiiS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 4096
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z16reduce_per_blockPiiS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z16reduce_per_blockPiiS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <inttypes.h>
#include <math.h>
#include <sys/time.h>
#include <hip/hip_runtime.h>
const int block_size = 1024;
const int n = 4 * (1 << 20);
void reduce_cpu(int *v, int n, int *sum)
{
/*
int s = 0.0;
for (int i = 0; i < n; i++)
s += v[i];
*sum = s;
*/
// Kahan's summation algorithm
int s = v[0];
int c = (int)0.0;
for (int i = 1; i < n; i++) {
int y = v[i] - c;
int t = s + y;
c = (t - s) - y;
s = t;
}
*sum = s;
}
__global__ void reduce_per_block(int *v, int n, int *per_block_sum)
{
__shared__ int sdata[block_size];
int tid = threadIdx.x;
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i < n) {
sdata[tid] = v[i];
__syncthreads();
for (int s = 1; s < blockDim.x; s *= 2) {
if (tid % (2 * s) == 0)
sdata[tid] += sdata[tid + s];
__syncthreads();
}
if (tid == 0)
per_block_sum[blockIdx.x] = sdata[0];
}
}
double wtime()
{
struct timeval t;
gettimeofday(&t, NULL);
return (double)t.tv_sec + (double)t.tv_usec * 1E-6;
}
int main()
{
double tcpu = 0, tgpu = 0, tmem = 0;
size_t size = sizeof(int) * n;
int *v = (int *)malloc(size);
srand(0);
for (size_t i = 0; i < n; i++)
v[i] = i + 1;
int sum;
tcpu = -wtime();
reduce_cpu(v, n, &sum);
tcpu += wtime();
/* Allocate on device */
int threads_per_block = block_size;
int blocks = (n + threads_per_block - 1) / threads_per_block;
int *dv;
int *per_block_sum;
int *sums = (int *)malloc(sizeof(int) * blocks);
tmem = -wtime();
hipMalloc((void **)&per_block_sum, sizeof(int) * blocks);
hipMalloc((void **)&dv, size);
hipMemcpy(dv, v, size, hipMemcpyHostToDevice);
tmem += wtime();
printf("CUDA kernel launch with %d blocks of %d threads\n", blocks, threads_per_block);
fflush(stdout);
/* Compute per block sum */
tgpu = -wtime();
reduce_per_block<<<blocks, threads_per_block>>>(dv, n, per_block_sum);
hipDeviceSynchronize();
tgpu += wtime();
tmem = -wtime();
hipMemcpy(sums, per_block_sum, sizeof(int) * blocks, hipMemcpyDeviceToHost);
tmem += wtime();
/* Compute block sum */
tgpu -= wtime();
int sum_gpu = 0;
for (int i = 0; i < blocks; i++)
sum_gpu += sums[i];
tgpu += wtime();
printf("Sum (CPU) = %d\n", sum);
printf("Sum (GPU) = %d\n", sum_gpu);
printf("CPU version (sec.): %.6f\n", tcpu);
printf("GPU version (sec.): %.6f\n", tgpu);
printf("GPU bandwidth (GiB/s): %.2f\n", 1.0e-9 * size / (tgpu + tmem));
printf("Speedup: %.2f\n", tcpu / tgpu);
printf("Speedup (with mem ops.): %.2f\n", tcpu / (tgpu + tmem));
hipFree(per_block_sum);
hipFree(dv);
free(sums);
free(v);
hipDeviceReset();
return 0;
} | .text
.file "reduction.hip"
.globl _Z10reduce_cpuPiiS_ # -- Begin function _Z10reduce_cpuPiiS_
.p2align 4, 0x90
.type _Z10reduce_cpuPiiS_,@function
_Z10reduce_cpuPiiS_: # @_Z10reduce_cpuPiiS_
.cfi_startproc
# %bb.0:
movl (%rdi), %eax
cmpl $2, %esi
jl .LBB0_3
# %bb.1: # %.lr.ph.preheader
movl %esi, %ecx
movl $1, %esi
.p2align 4, 0x90
.LBB0_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
addl (%rdi,%rsi,4), %eax
incq %rsi
cmpq %rsi, %rcx
jne .LBB0_2
.LBB0_3: # %._crit_edge
movl %eax, (%rdx)
retq
.Lfunc_end0:
.size _Z10reduce_cpuPiiS_, .Lfunc_end0-_Z10reduce_cpuPiiS_
.cfi_endproc
# -- End function
.globl _Z31__device_stub__reduce_per_blockPiiS_ # -- Begin function _Z31__device_stub__reduce_per_blockPiiS_
.p2align 4, 0x90
.type _Z31__device_stub__reduce_per_blockPiiS_,@function
_Z31__device_stub__reduce_per_blockPiiS_: # @_Z31__device_stub__reduce_per_blockPiiS_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movl %esi, 12(%rsp)
movq %rdx, 64(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z16reduce_per_blockPiiS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end1:
.size _Z31__device_stub__reduce_per_blockPiiS_, .Lfunc_end1-_Z31__device_stub__reduce_per_blockPiiS_
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z5wtimev
.LCPI2_0:
.quad 0x3eb0c6f7a0b5ed8d # double 9.9999999999999995E-7
.text
.globl _Z5wtimev
.p2align 4, 0x90
.type _Z5wtimev,@function
_Z5wtimev: # @_Z5wtimev
.cfi_startproc
# %bb.0:
subq $24, %rsp
.cfi_def_cfa_offset 32
leaq 8(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
cvtsi2sdq 8(%rsp), %xmm1
cvtsi2sdq 16(%rsp), %xmm0
mulsd .LCPI2_0(%rip), %xmm0
addsd %xmm1, %xmm0
addq $24, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z5wtimev, .Lfunc_end2-_Z5wtimev
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI3_0:
.quad 0x3eb0c6f7a0b5ed8d # double 9.9999999999999995E-7
.LCPI3_1:
.quad 0x3f912e0be826d695 # double 0.016777216000000001
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $200, %rsp
.cfi_def_cfa_offset 256
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $16777216, %edi # imm = 0x1000000
callq malloc
movq %rax, %rbx
xorl %r14d, %r14d
xorl %edi, %edi
callq srand
.p2align 4, 0x90
.LBB3_1: # =>This Inner Loop Header: Depth=1
leaq 1(%r14), %rax
movl %eax, (%rbx,%r14,4)
movq %rax, %r14
cmpq $4194304, %rax # imm = 0x400000
jne .LBB3_1
# %bb.2:
movq %rsp, %rdi
xorl %esi, %esi
callq gettimeofday
movq (%rsp), %rax
movq %rax, 40(%rsp) # 8-byte Spill
movq 8(%rsp), %rax
movq %rax, 32(%rsp) # 8-byte Spill
movl (%rbx), %ebp
movl $1, %eax
.p2align 4, 0x90
.LBB3_3: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
addl (%rbx,%rax,4), %ebp
incq %rax
cmpq $4194304, %rax # imm = 0x400000
jne .LBB3_3
# %bb.4: # %_Z10reduce_cpuPiiS_.exit
xorl %r15d, %r15d
movq %rsp, %rdi
xorl %esi, %esi
callq gettimeofday
movq (%rsp), %rax
movq %rax, 128(%rsp) # 8-byte Spill
movq 8(%rsp), %rax
movq %rax, 56(%rsp) # 8-byte Spill
movl $16384, %edi # imm = 0x4000
callq malloc
movq %rax, %r14
movq %rsp, %rdi
xorl %esi, %esi
callq gettimeofday
leaq 64(%rsp), %rdi
movl $16384, %esi # imm = 0x4000
callq hipMalloc
leaq 72(%rsp), %rdi
movl $16777216, %esi # imm = 0x1000000
callq hipMalloc
movq 72(%rsp), %rdi
movl $16777216, %edx # imm = 0x1000000
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq %rsp, %rdi
xorl %esi, %esi
callq gettimeofday
movl $.L.str, %edi
movl $4096, %esi # imm = 0x1000
movl $1024, %edx # imm = 0x400
xorl %eax, %eax
callq printf
movq stdout(%rip), %rdi
callq fflush
movq %rsp, %rdi
xorl %esi, %esi
callq gettimeofday
movq (%rsp), %rax
movq %rax, 120(%rsp) # 8-byte Spill
movq 8(%rsp), %rax
movq %rax, 112(%rsp) # 8-byte Spill
movabsq $4294968320, %rdx # imm = 0x100000400
leaq 3072(%rdx), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_6
# %bb.5:
movq 72(%rsp), %rax
movq 64(%rsp), %rcx
movq %rax, 192(%rsp)
movl $4194304, 84(%rsp) # imm = 0x400000
movq %rcx, 184(%rsp)
leaq 192(%rsp), %rax
movq %rax, (%rsp)
leaq 84(%rsp), %rax
movq %rax, 8(%rsp)
leaq 184(%rsp), %rax
movq %rax, 16(%rsp)
leaq 168(%rsp), %rdi
leaq 152(%rsp), %rsi
leaq 144(%rsp), %rdx
leaq 136(%rsp), %rcx
callq __hipPopCallConfiguration
movq 168(%rsp), %rsi
movl 176(%rsp), %edx
movq 152(%rsp), %rcx
movl 160(%rsp), %r8d
movq %rsp, %r9
movl $_Z16reduce_per_blockPiiS_, %edi
pushq 136(%rsp)
.cfi_adjust_cfa_offset 8
pushq 152(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_6:
callq hipDeviceSynchronize
movq %rsp, %rdi
xorl %esi, %esi
callq gettimeofday
movq (%rsp), %rax
movq %rax, 104(%rsp) # 8-byte Spill
movq 8(%rsp), %rax
movq %rax, 96(%rsp) # 8-byte Spill
movq %rsp, %rdi
xorl %esi, %esi
callq gettimeofday
movq (%rsp), %rax
movq %rax, 48(%rsp) # 8-byte Spill
movq 8(%rsp), %rax
movq %rax, 88(%rsp) # 8-byte Spill
movq 64(%rsp), %rsi
movl $16384, %edx # imm = 0x4000
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
movq %rsp, %rdi
xorl %esi, %esi
callq gettimeofday
movq (%rsp), %r12
movq 8(%rsp), %r13
movq %rsp, %rdi
xorl %esi, %esi
callq gettimeofday
movq (%rsp), %rax
movq 8(%rsp), %rcx
xorl %edx, %edx
.p2align 4, 0x90
.LBB3_7: # =>This Inner Loop Header: Depth=1
addl (%r14,%rdx,4), %r15d
incq %rdx
cmpq $4096, %rdx # imm = 0x1000
jne .LBB3_7
# %bb.8:
cvtsi2sd %rcx, %xmm1
movsd .LCPI3_0(%rip), %xmm4 # xmm4 = mem[0],zero
mulsd %xmm4, %xmm1
cvtsi2sd %rax, %xmm0
addsd %xmm1, %xmm0
xorps %xmm1, %xmm1
cvtsi2sd %r13, %xmm1
cvtsi2sd %r12, %xmm3
mulsd %xmm4, %xmm1
addsd %xmm1, %xmm3
xorps %xmm1, %xmm1
cvtsi2sdq 88(%rsp), %xmm1 # 8-byte Folded Reload
mulsd %xmm4, %xmm1
cvtsi2sdq 48(%rsp), %xmm2 # 8-byte Folded Reload
addsd %xmm1, %xmm2
subsd %xmm2, %xmm3
movsd %xmm3, 48(%rsp) # 8-byte Spill
xorps %xmm1, %xmm1
cvtsi2sdq 96(%rsp), %xmm1 # 8-byte Folded Reload
mulsd %xmm4, %xmm1
xorps %xmm3, %xmm3
cvtsi2sdq 104(%rsp), %xmm3 # 8-byte Folded Reload
xorps %xmm2, %xmm2
cvtsi2sdq 112(%rsp), %xmm2 # 8-byte Folded Reload
addsd %xmm1, %xmm3
mulsd %xmm4, %xmm2
xorps %xmm1, %xmm1
cvtsi2sdq 120(%rsp), %xmm1 # 8-byte Folded Reload
addsd %xmm2, %xmm1
subsd %xmm1, %xmm3
xorps %xmm1, %xmm1
cvtsi2sdq 56(%rsp), %xmm1 # 8-byte Folded Reload
subsd %xmm0, %xmm3
movsd %xmm3, 56(%rsp) # 8-byte Spill
mulsd %xmm4, %xmm1
xorps %xmm2, %xmm2
cvtsi2sdq 128(%rsp), %xmm2 # 8-byte Folded Reload
addsd %xmm1, %xmm2
xorps %xmm0, %xmm0
cvtsi2sdq 32(%rsp), %xmm0 # 8-byte Folded Reload
mulsd %xmm4, %xmm0
xorps %xmm1, %xmm1
cvtsi2sdq 40(%rsp), %xmm1 # 8-byte Folded Reload
addsd %xmm0, %xmm1
subsd %xmm1, %xmm2
movsd %xmm2, 40(%rsp) # 8-byte Spill
movq %rsp, %rdi
xorl %esi, %esi
callq gettimeofday
xorps %xmm0, %xmm0
cvtsi2sdq (%rsp), %xmm0
xorps %xmm1, %xmm1
cvtsi2sdq 8(%rsp), %xmm1
mulsd .LCPI3_0(%rip), %xmm1
addsd %xmm0, %xmm1
addsd 56(%rsp), %xmm1 # 8-byte Folded Reload
movsd %xmm1, 32(%rsp) # 8-byte Spill
movl $.L.str.1, %edi
movl %ebp, %esi
xorl %eax, %eax
callq printf
movl $.L.str.2, %edi
movl %r15d, %esi
xorl %eax, %eax
callq printf
movl $.L.str.3, %edi
movsd 40(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
movb $1, %al
callq printf
movl $.L.str.4, %edi
movsd 32(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
movb $1, %al
callq printf
movsd 48(%rsp), %xmm1 # 8-byte Reload
# xmm1 = mem[0],zero
addsd 32(%rsp), %xmm1 # 8-byte Folded Reload
movsd %xmm1, 48(%rsp) # 8-byte Spill
movsd .LCPI3_1(%rip), %xmm0 # xmm0 = mem[0],zero
divsd %xmm1, %xmm0
movl $.L.str.5, %edi
movb $1, %al
callq printf
movsd 40(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
divsd 32(%rsp), %xmm0 # 8-byte Folded Reload
movl $.L.str.6, %edi
movb $1, %al
callq printf
movsd 40(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
divsd 48(%rsp), %xmm0 # 8-byte Folded Reload
movl $.L.str.7, %edi
movb $1, %al
callq printf
movq 64(%rsp), %rdi
callq hipFree
movq 72(%rsp), %rdi
callq hipFree
movq %r14, %rdi
callq free
movq %rbx, %rdi
callq free
callq hipDeviceReset
xorl %eax, %eax
addq $200, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z16reduce_per_blockPiiS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z16reduce_per_blockPiiS_,@object # @_Z16reduce_per_blockPiiS_
.section .rodata,"a",@progbits
.globl _Z16reduce_per_blockPiiS_
.p2align 3, 0x0
_Z16reduce_per_blockPiiS_:
.quad _Z31__device_stub__reduce_per_blockPiiS_
.size _Z16reduce_per_blockPiiS_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "CUDA kernel launch with %d blocks of %d threads\n"
.size .L.str, 49
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Sum (CPU) = %d\n"
.size .L.str.1, 16
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Sum (GPU) = %d\n"
.size .L.str.2, 16
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "CPU version (sec.): %.6f\n"
.size .L.str.3, 26
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "GPU version (sec.): %.6f\n"
.size .L.str.4, 26
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "GPU bandwidth (GiB/s): %.2f\n"
.size .L.str.5, 29
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "Speedup: %.2f\n"
.size .L.str.6, 15
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "Speedup (with mem ops.): %.2f\n"
.size .L.str.7, 31
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z16reduce_per_blockPiiS_"
.size .L__unnamed_1, 26
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z31__device_stub__reduce_per_blockPiiS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z16reduce_per_blockPiiS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z16reduce_per_blockPiiS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R4, R0, c[0x0][0x0], R3 ; /* 0x0000000000047a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R4, c[0x0][0x168], PT ; /* 0x00005a0004007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; /* 0x00000004ff057424 */
/* 0x000fe200078e00ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0080*/ IMAD.WIDE R4, R4, R5, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fcc00078e0205 */
/*0090*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ MOV R2, c[0x0][0x0] ; /* 0x0000000000027a02 */
/* 0x000fe40000000f00 */
/*00b0*/ ISETP.NE.AND P0, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fe40003f05270 */
/*00c0*/ ISETP.GE.U32.AND P1, PT, R2, 0x2, PT ; /* 0x000000020200780c */
/* 0x000fe20003f26070 */
/*00d0*/ STS [R3.X4], R4 ; /* 0x0000000403007388 */
/* 0x0041e80000004800 */
/*00e0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000ff00000010000 */
/*00f0*/ @!P1 BRA 0x350 ; /* 0x0000025000009947 */
/* 0x000fea0003800000 */
/*0100*/ IABS R8, R3 ; /* 0x0000000300087213 */
/* 0x001fe20000000000 */
/*0110*/ IMAD.SHL.U32 R2, R3, 0x4, RZ ; /* 0x0000000403027824 */
/* 0x000fc400078e00ff */
/*0120*/ IMAD.MOV.U32 R7, RZ, RZ, 0x1 ; /* 0x00000001ff077424 */
/* 0x000fca00078e00ff */
/*0130*/ SHF.L.U32 R11, R7, 0x1, RZ ; /* 0x00000001070b7819 */
/* 0x000fe400000006ff */
/*0140*/ IABS R13, R3 ; /* 0x00000003000d7213 */
/* 0x000fe40000000000 */
/*0150*/ IABS R10, R11.reuse ; /* 0x0000000b000a7213 */
/* 0x080fe40000000000 */
/*0160*/ IABS R12, R11 ; /* 0x0000000b000c7213 */
/* 0x000fe40000000000 */
/*0170*/ I2F.RP R6, R10 ; /* 0x0000000a00067306 */
/* 0x000e220000209400 */
/*0180*/ ISETP.GE.AND P3, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fce0003f66270 */
/*0190*/ MUFU.RCP R6, R6 ; /* 0x0000000600067308 */
/* 0x001e240000001000 */
/*01a0*/ IADD3 R4, R6, 0xffffffe, RZ ; /* 0x0ffffffe06047810 */
/* 0x001fe40007ffe0ff */
/*01b0*/ IADD3 R6, RZ, -R12, RZ ; /* 0x8000000cff067210 */
/* 0x000fc80007ffe0ff */
/*01c0*/ F2I.FTZ.U32.TRUNC.NTZ R5, R4 ; /* 0x0000000400057305 */
/* 0x000064000021f000 */
/*01d0*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x001fe400078e00ff */
/*01e0*/ IMAD.MOV R9, RZ, RZ, -R5 ; /* 0x000000ffff097224 */
/* 0x002fc800078e0a05 */
/*01f0*/ IMAD R9, R9, R10, RZ ; /* 0x0000000a09097224 */
/* 0x000fc800078e02ff */
/*0200*/ IMAD.HI.U32 R5, R5, R9, R4 ; /* 0x0000000905057227 */
/* 0x000fc800078e0004 */
/*0210*/ IMAD.MOV.U32 R9, RZ, RZ, R13 ; /* 0x000000ffff097224 */
/* 0x000fe400078e000d */
/*0220*/ IMAD.HI.U32 R5, R5, R8, RZ ; /* 0x0000000805057227 */
/* 0x000fc800078e00ff */
/*0230*/ IMAD R5, R5, R6, R9 ; /* 0x0000000605057224 */
/* 0x000fca00078e0209 */
/*0240*/ ISETP.GT.U32.AND P1, PT, R10, R5, PT ; /* 0x000000050a00720c */
/* 0x000fda0003f24070 */
/*0250*/ @!P1 IMAD.IADD R5, R5, 0x1, -R10 ; /* 0x0000000105059824 */
/* 0x000fe200078e0a0a */
/*0260*/ ISETP.NE.AND P1, PT, R11, RZ, PT ; /* 0x000000ff0b00720c */
/* 0x000fc80003f25270 */
/*0270*/ ISETP.GT.U32.AND P2, PT, R10, R5, PT ; /* 0x000000050a00720c */
/* 0x000fda0003f44070 */
/*0280*/ @!P2 IADD3 R5, R5, -R10, RZ ; /* 0x8000000a0505a210 */
/* 0x000fca0007ffe0ff */
/*0290*/ @!P3 IMAD.MOV R5, RZ, RZ, -R5 ; /* 0x000000ffff05b224 */
/* 0x000fe200078e0a05 */
/*02a0*/ @!P1 LOP3.LUT R5, RZ, R11, RZ, 0x33, !PT ; /* 0x0000000bff059212 */
/* 0x000fc800078e33ff */
/*02b0*/ ISETP.NE.AND P1, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fda0003f25270 */
/*02c0*/ @!P1 IMAD R4, R7, 0x4, R2 ; /* 0x0000000407049824 */
/* 0x000fe200078e0202 */
/*02d0*/ @!P1 LDS R5, [R3.X4] ; /* 0x0000000003059984 */
/* 0x000fe20000004800 */
/*02e0*/ IMAD.MOV.U32 R7, RZ, RZ, R11 ; /* 0x000000ffff077224 */
/* 0x000fc800078e000b */
/*02f0*/ @!P1 LDS R4, [R4] ; /* 0x0000000004049984 */
/* 0x000e240000000800 */
/*0300*/ @!P1 IADD3 R6, R5, R4, RZ ; /* 0x0000000405069210 */
/* 0x001fca0007ffe0ff */
/*0310*/ @!P1 STS [R3.X4], R6 ; /* 0x0000000603009388 */
/* 0x0001e80000004800 */
/*0320*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0330*/ ISETP.GE.U32.AND P1, PT, R11, c[0x0][0x0], PT ; /* 0x000000000b007a0c */
/* 0x000fda0003f26070 */
/*0340*/ @!P1 BRA 0x130 ; /* 0xfffffde000009947 */
/* 0x001fea000383ffff */
/*0350*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x001fea0003800000 */
/*0360*/ LDS R5, [RZ] ; /* 0x00000000ff057984 */
/* 0x000e220000000800 */
/*0370*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fd400000001ff */
/*0380*/ IMAD.WIDE.U32 R2, R0, R3, c[0x0][0x170] ; /* 0x00005c0000027625 */
/* 0x000fca00078e0003 */
/*0390*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x001fe2000c101904 */
/*03a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*03b0*/ BRA 0x3b0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*03c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0400*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0410*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0420*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0430*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0440*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0450*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0460*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0470*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z16reduce_per_blockPiiS_
.globl _Z16reduce_per_blockPiiS_
.p2align 8
.type _Z16reduce_per_blockPiiS_,@function
_Z16reduce_per_blockPiiS_:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x24
s_load_b32 s4, s[0:1], 0x8
s_mov_b32 s2, s15
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s2, s3, v[0:1]
v_cmp_gt_i32_e32 vcc_lo, s4, v1
s_and_saveexec_b32 s4, vcc_lo
s_cbranch_execz .LBB0_8
s_load_b64 s[4:5], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_cmp_lt_u32 s3, 2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v1, vcc_lo, s4, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, s5, v2, vcc_lo
global_load_b32 v2, v[1:2], off
v_lshlrev_b32_e32 v1, 2, v0
s_waitcnt vmcnt(0)
ds_store_b32 v1, v2
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_6
s_mov_b32 s5, 1
s_branch .LBB0_4
.p2align 6
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s6
s_cmp_ge_u32 s4, s3
s_mov_b32 s5, s4
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_6
.LBB0_4:
s_lshl_b32 s4, s5, 1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s6, s4, -1
v_and_b32_e32 v2, s6, v0
s_mov_b32 s6, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_eq_u32_e32 0, v2
s_cbranch_execz .LBB0_3
v_add_lshl_u32 v2, s5, v0, 2
ds_load_b32 v2, v2
ds_load_b32 v3, v1
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v2, v3, v2
ds_store_b32 v1, v2
s_branch .LBB0_3
.LBB0_6:
v_cmp_eq_u32_e32 vcc_lo, 0, v0
s_mov_b32 s3, 0
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_8
v_mov_b32_e32 v0, 0
s_load_b64 s[0:1], s[0:1], 0x10
s_lshl_b64 s[2:3], s[2:3], 2
ds_load_b32 v1, v0
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
global_store_b32 v0, v1, s[0:1]
.LBB0_8:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z16reduce_per_blockPiiS_
.amdhsa_group_segment_fixed_size 4096
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z16reduce_per_blockPiiS_, .Lfunc_end0-_Z16reduce_per_blockPiiS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 4096
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z16reduce_per_blockPiiS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z16reduce_per_blockPiiS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00031caf_00000000-6_reduction.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z10reduce_cpuPiiS_
.type _Z10reduce_cpuPiiS_, @function
_Z10reduce_cpuPiiS_:
.LFB2057:
.cfi_startproc
endbr64
movl (%rdi), %ecx
cmpl $1, %esi
jle .L4
leaq 4(%rdi), %rax
leal -2(%rsi), %esi
leaq 8(%rdi,%rsi,4), %rsi
.L5:
addl (%rax), %ecx
addq $4, %rax
cmpq %rsi, %rax
jne .L5
.L4:
movl %ecx, (%rdx)
ret
.cfi_endproc
.LFE2057:
.size _Z10reduce_cpuPiiS_, .-_Z10reduce_cpuPiiS_
.globl _Z5wtimev
.type _Z5wtimev, @function
_Z5wtimev:
.LFB2058:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movq %fs:40, %rax
movq %rax, 24(%rsp)
xorl %eax, %eax
movq %rsp, %rdi
movl $0, %esi
call gettimeofday@PLT
pxor %xmm0, %xmm0
cvtsi2sdq 8(%rsp), %xmm0
mulsd .LC0(%rip), %xmm0
pxor %xmm1, %xmm1
cvtsi2sdq (%rsp), %xmm1
addsd %xmm1, %xmm0
movq 24(%rsp), %rax
subq %fs:40, %rax
jne .L10
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L10:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size _Z5wtimev, .-_Z5wtimev
.globl _Z39__device_stub__Z16reduce_per_blockPiiS_PiiS_
.type _Z39__device_stub__Z16reduce_per_blockPiiS_PiiS_, @function
_Z39__device_stub__Z16reduce_per_blockPiiS_PiiS_:
.LFB2084:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z16reduce_per_blockPiiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z39__device_stub__Z16reduce_per_blockPiiS_PiiS_, .-_Z39__device_stub__Z16reduce_per_blockPiiS_PiiS_
.globl _Z16reduce_per_blockPiiS_
.type _Z16reduce_per_blockPiiS_, @function
_Z16reduce_per_blockPiiS_:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z39__device_stub__Z16reduce_per_blockPiiS_PiiS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z16reduce_per_blockPiiS_, .-_Z16reduce_per_blockPiiS_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "CUDA kernel launch with %d blocks of %d threads\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "Sum (CPU) = %d\n"
.LC3:
.string "Sum (GPU) = %d\n"
.LC4:
.string "CPU version (sec.): %.6f\n"
.LC5:
.string "GPU version (sec.): %.6f\n"
.LC7:
.string "GPU bandwidth (GiB/s): %.2f\n"
.LC8:
.string "Speedup: %.2f\n"
.section .rodata.str1.8
.align 8
.LC9:
.string "Speedup (with mem ops.): %.2f\n"
.text
.globl main
.type main, @function
main:
.LFB2059:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $104, %rsp
.cfi_def_cfa_offset 144
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
movl $16777216, %edi
call malloc@PLT
movq %rax, %rbp
movl $0, %edi
call srand@PLT
movl $1, %eax
.L20:
movl %eax, -4(%rbp,%rax,4)
addq $1, %rax
cmpq $4194305, %rax
jne .L20
call _Z5wtimev
movsd %xmm0, 8(%rsp)
leaq 44(%rsp), %rdx
movl $4194304, %esi
movq %rbp, %rdi
call _Z10reduce_cpuPiiS_
call _Z5wtimev
movapd %xmm0, %xmm4
subsd 8(%rsp), %xmm4
movsd %xmm4, 8(%rsp)
movl $16384, %edi
call malloc@PLT
movq %rax, %r12
call _Z5wtimev
leaq 56(%rsp), %rdi
movl $16384, %esi
call cudaMalloc@PLT
leaq 48(%rsp), %rdi
movl $16777216, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $16777216, %edx
movq %rbp, %rsi
movq 48(%rsp), %rdi
call cudaMemcpy@PLT
call _Z5wtimev
movl $1024, %ecx
movl $4096, %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq stdout(%rip), %rdi
call fflush@PLT
call _Z5wtimev
movsd %xmm0, 16(%rsp)
movl $1024, 76(%rsp)
movl $1, 80(%rsp)
movl $4096, 64(%rsp)
movl $1, 68(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 76(%rsp), %rdx
movl $1, %ecx
movq 64(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L27
.L21:
call cudaDeviceSynchronize@PLT
call _Z5wtimev
subsd 16(%rsp), %xmm0
movq %xmm0, %rbx
call _Z5wtimev
movsd %xmm0, 16(%rsp)
movl $2, %ecx
movl $16384, %edx
movq 56(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
call _Z5wtimev
movapd %xmm0, %xmm5
subsd 16(%rsp), %xmm5
movq %xmm5, %r14
call _Z5wtimev
movq %rbx, %xmm6
subsd %xmm0, %xmm6
movsd %xmm6, 16(%rsp)
movq %r12, %rax
leaq 16384(%r12), %rcx
movl $0, %edx
.L22:
movl %edx, %ebx
addl (%rax), %ebx
movl %ebx, %edx
addq $4, %rax
cmpq %rcx, %rax
jne .L22
call _Z5wtimev
addsd 16(%rsp), %xmm0
movsd %xmm0, 16(%rsp)
movl 44(%rsp), %edx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %ebx, %edx
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movsd 8(%rsp), %xmm0
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movsd 16(%rsp), %xmm0
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq %r14, %xmm3
addsd 16(%rsp), %xmm3
movsd .LC6(%rip), %xmm0
movsd %xmm3, 24(%rsp)
divsd %xmm3, %xmm0
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movsd 8(%rsp), %xmm2
divsd 16(%rsp), %xmm2
movapd %xmm2, %xmm0
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movsd 8(%rsp), %xmm0
divsd 24(%rsp), %xmm0
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 56(%rsp), %rdi
call cudaFree@PLT
movq 48(%rsp), %rdi
call cudaFree@PLT
movq %r12, %rdi
call free@PLT
movq %rbp, %rdi
call free@PLT
call cudaDeviceReset@PLT
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L28
movl $0, %eax
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L27:
.cfi_restore_state
movq 56(%rsp), %rdx
movl $4194304, %esi
movq 48(%rsp), %rdi
call _Z39__device_stub__Z16reduce_per_blockPiiS_PiiS_
jmp .L21
.L28:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size main, .-main
.section .rodata.str1.1
.LC10:
.string "_Z16reduce_per_blockPiiS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC10(%rip), %rdx
movq %rdx, %rcx
leaq _Z16reduce_per_blockPiiS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long -1598689907
.long 1051772663
.align 8
.LC6:
.long -400107883
.long 1066479115
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "reduction.hip"
.globl _Z10reduce_cpuPiiS_ # -- Begin function _Z10reduce_cpuPiiS_
.p2align 4, 0x90
.type _Z10reduce_cpuPiiS_,@function
_Z10reduce_cpuPiiS_: # @_Z10reduce_cpuPiiS_
.cfi_startproc
# %bb.0:
movl (%rdi), %eax
cmpl $2, %esi
jl .LBB0_3
# %bb.1: # %.lr.ph.preheader
movl %esi, %ecx
movl $1, %esi
.p2align 4, 0x90
.LBB0_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
addl (%rdi,%rsi,4), %eax
incq %rsi
cmpq %rsi, %rcx
jne .LBB0_2
.LBB0_3: # %._crit_edge
movl %eax, (%rdx)
retq
.Lfunc_end0:
.size _Z10reduce_cpuPiiS_, .Lfunc_end0-_Z10reduce_cpuPiiS_
.cfi_endproc
# -- End function
.globl _Z31__device_stub__reduce_per_blockPiiS_ # -- Begin function _Z31__device_stub__reduce_per_blockPiiS_
.p2align 4, 0x90
.type _Z31__device_stub__reduce_per_blockPiiS_,@function
_Z31__device_stub__reduce_per_blockPiiS_: # @_Z31__device_stub__reduce_per_blockPiiS_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movl %esi, 12(%rsp)
movq %rdx, 64(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z16reduce_per_blockPiiS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end1:
.size _Z31__device_stub__reduce_per_blockPiiS_, .Lfunc_end1-_Z31__device_stub__reduce_per_blockPiiS_
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z5wtimev
.LCPI2_0:
.quad 0x3eb0c6f7a0b5ed8d # double 9.9999999999999995E-7
.text
.globl _Z5wtimev
.p2align 4, 0x90
.type _Z5wtimev,@function
_Z5wtimev: # @_Z5wtimev
.cfi_startproc
# %bb.0:
subq $24, %rsp
.cfi_def_cfa_offset 32
leaq 8(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
cvtsi2sdq 8(%rsp), %xmm1
cvtsi2sdq 16(%rsp), %xmm0
mulsd .LCPI2_0(%rip), %xmm0
addsd %xmm1, %xmm0
addq $24, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z5wtimev, .Lfunc_end2-_Z5wtimev
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI3_0:
.quad 0x3eb0c6f7a0b5ed8d # double 9.9999999999999995E-7
.LCPI3_1:
.quad 0x3f912e0be826d695 # double 0.016777216000000001
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $200, %rsp
.cfi_def_cfa_offset 256
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $16777216, %edi # imm = 0x1000000
callq malloc
movq %rax, %rbx
xorl %r14d, %r14d
xorl %edi, %edi
callq srand
.p2align 4, 0x90
.LBB3_1: # =>This Inner Loop Header: Depth=1
leaq 1(%r14), %rax
movl %eax, (%rbx,%r14,4)
movq %rax, %r14
cmpq $4194304, %rax # imm = 0x400000
jne .LBB3_1
# %bb.2:
movq %rsp, %rdi
xorl %esi, %esi
callq gettimeofday
movq (%rsp), %rax
movq %rax, 40(%rsp) # 8-byte Spill
movq 8(%rsp), %rax
movq %rax, 32(%rsp) # 8-byte Spill
movl (%rbx), %ebp
movl $1, %eax
.p2align 4, 0x90
.LBB3_3: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
addl (%rbx,%rax,4), %ebp
incq %rax
cmpq $4194304, %rax # imm = 0x400000
jne .LBB3_3
# %bb.4: # %_Z10reduce_cpuPiiS_.exit
xorl %r15d, %r15d
movq %rsp, %rdi
xorl %esi, %esi
callq gettimeofday
movq (%rsp), %rax
movq %rax, 128(%rsp) # 8-byte Spill
movq 8(%rsp), %rax
movq %rax, 56(%rsp) # 8-byte Spill
movl $16384, %edi # imm = 0x4000
callq malloc
movq %rax, %r14
movq %rsp, %rdi
xorl %esi, %esi
callq gettimeofday
leaq 64(%rsp), %rdi
movl $16384, %esi # imm = 0x4000
callq hipMalloc
leaq 72(%rsp), %rdi
movl $16777216, %esi # imm = 0x1000000
callq hipMalloc
movq 72(%rsp), %rdi
movl $16777216, %edx # imm = 0x1000000
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq %rsp, %rdi
xorl %esi, %esi
callq gettimeofday
movl $.L.str, %edi
movl $4096, %esi # imm = 0x1000
movl $1024, %edx # imm = 0x400
xorl %eax, %eax
callq printf
movq stdout(%rip), %rdi
callq fflush
movq %rsp, %rdi
xorl %esi, %esi
callq gettimeofday
movq (%rsp), %rax
movq %rax, 120(%rsp) # 8-byte Spill
movq 8(%rsp), %rax
movq %rax, 112(%rsp) # 8-byte Spill
movabsq $4294968320, %rdx # imm = 0x100000400
leaq 3072(%rdx), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_6
# %bb.5:
movq 72(%rsp), %rax
movq 64(%rsp), %rcx
movq %rax, 192(%rsp)
movl $4194304, 84(%rsp) # imm = 0x400000
movq %rcx, 184(%rsp)
leaq 192(%rsp), %rax
movq %rax, (%rsp)
leaq 84(%rsp), %rax
movq %rax, 8(%rsp)
leaq 184(%rsp), %rax
movq %rax, 16(%rsp)
leaq 168(%rsp), %rdi
leaq 152(%rsp), %rsi
leaq 144(%rsp), %rdx
leaq 136(%rsp), %rcx
callq __hipPopCallConfiguration
movq 168(%rsp), %rsi
movl 176(%rsp), %edx
movq 152(%rsp), %rcx
movl 160(%rsp), %r8d
movq %rsp, %r9
movl $_Z16reduce_per_blockPiiS_, %edi
pushq 136(%rsp)
.cfi_adjust_cfa_offset 8
pushq 152(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_6:
callq hipDeviceSynchronize
movq %rsp, %rdi
xorl %esi, %esi
callq gettimeofday
movq (%rsp), %rax
movq %rax, 104(%rsp) # 8-byte Spill
movq 8(%rsp), %rax
movq %rax, 96(%rsp) # 8-byte Spill
movq %rsp, %rdi
xorl %esi, %esi
callq gettimeofday
movq (%rsp), %rax
movq %rax, 48(%rsp) # 8-byte Spill
movq 8(%rsp), %rax
movq %rax, 88(%rsp) # 8-byte Spill
movq 64(%rsp), %rsi
movl $16384, %edx # imm = 0x4000
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
movq %rsp, %rdi
xorl %esi, %esi
callq gettimeofday
movq (%rsp), %r12
movq 8(%rsp), %r13
movq %rsp, %rdi
xorl %esi, %esi
callq gettimeofday
movq (%rsp), %rax
movq 8(%rsp), %rcx
xorl %edx, %edx
.p2align 4, 0x90
.LBB3_7: # =>This Inner Loop Header: Depth=1
addl (%r14,%rdx,4), %r15d
incq %rdx
cmpq $4096, %rdx # imm = 0x1000
jne .LBB3_7
# %bb.8:
cvtsi2sd %rcx, %xmm1
movsd .LCPI3_0(%rip), %xmm4 # xmm4 = mem[0],zero
mulsd %xmm4, %xmm1
cvtsi2sd %rax, %xmm0
addsd %xmm1, %xmm0
xorps %xmm1, %xmm1
cvtsi2sd %r13, %xmm1
cvtsi2sd %r12, %xmm3
mulsd %xmm4, %xmm1
addsd %xmm1, %xmm3
xorps %xmm1, %xmm1
cvtsi2sdq 88(%rsp), %xmm1 # 8-byte Folded Reload
mulsd %xmm4, %xmm1
cvtsi2sdq 48(%rsp), %xmm2 # 8-byte Folded Reload
addsd %xmm1, %xmm2
subsd %xmm2, %xmm3
movsd %xmm3, 48(%rsp) # 8-byte Spill
xorps %xmm1, %xmm1
cvtsi2sdq 96(%rsp), %xmm1 # 8-byte Folded Reload
mulsd %xmm4, %xmm1
xorps %xmm3, %xmm3
cvtsi2sdq 104(%rsp), %xmm3 # 8-byte Folded Reload
xorps %xmm2, %xmm2
cvtsi2sdq 112(%rsp), %xmm2 # 8-byte Folded Reload
addsd %xmm1, %xmm3
mulsd %xmm4, %xmm2
xorps %xmm1, %xmm1
cvtsi2sdq 120(%rsp), %xmm1 # 8-byte Folded Reload
addsd %xmm2, %xmm1
subsd %xmm1, %xmm3
xorps %xmm1, %xmm1
cvtsi2sdq 56(%rsp), %xmm1 # 8-byte Folded Reload
subsd %xmm0, %xmm3
movsd %xmm3, 56(%rsp) # 8-byte Spill
mulsd %xmm4, %xmm1
xorps %xmm2, %xmm2
cvtsi2sdq 128(%rsp), %xmm2 # 8-byte Folded Reload
addsd %xmm1, %xmm2
xorps %xmm0, %xmm0
cvtsi2sdq 32(%rsp), %xmm0 # 8-byte Folded Reload
mulsd %xmm4, %xmm0
xorps %xmm1, %xmm1
cvtsi2sdq 40(%rsp), %xmm1 # 8-byte Folded Reload
addsd %xmm0, %xmm1
subsd %xmm1, %xmm2
movsd %xmm2, 40(%rsp) # 8-byte Spill
movq %rsp, %rdi
xorl %esi, %esi
callq gettimeofday
xorps %xmm0, %xmm0
cvtsi2sdq (%rsp), %xmm0
xorps %xmm1, %xmm1
cvtsi2sdq 8(%rsp), %xmm1
mulsd .LCPI3_0(%rip), %xmm1
addsd %xmm0, %xmm1
addsd 56(%rsp), %xmm1 # 8-byte Folded Reload
movsd %xmm1, 32(%rsp) # 8-byte Spill
movl $.L.str.1, %edi
movl %ebp, %esi
xorl %eax, %eax
callq printf
movl $.L.str.2, %edi
movl %r15d, %esi
xorl %eax, %eax
callq printf
movl $.L.str.3, %edi
movsd 40(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
movb $1, %al
callq printf
movl $.L.str.4, %edi
movsd 32(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
movb $1, %al
callq printf
movsd 48(%rsp), %xmm1 # 8-byte Reload
# xmm1 = mem[0],zero
addsd 32(%rsp), %xmm1 # 8-byte Folded Reload
movsd %xmm1, 48(%rsp) # 8-byte Spill
movsd .LCPI3_1(%rip), %xmm0 # xmm0 = mem[0],zero
divsd %xmm1, %xmm0
movl $.L.str.5, %edi
movb $1, %al
callq printf
movsd 40(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
divsd 32(%rsp), %xmm0 # 8-byte Folded Reload
movl $.L.str.6, %edi
movb $1, %al
callq printf
movsd 40(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
divsd 48(%rsp), %xmm0 # 8-byte Folded Reload
movl $.L.str.7, %edi
movb $1, %al
callq printf
movq 64(%rsp), %rdi
callq hipFree
movq 72(%rsp), %rdi
callq hipFree
movq %r14, %rdi
callq free
movq %rbx, %rdi
callq free
callq hipDeviceReset
xorl %eax, %eax
addq $200, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z16reduce_per_blockPiiS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z16reduce_per_blockPiiS_,@object # @_Z16reduce_per_blockPiiS_
.section .rodata,"a",@progbits
.globl _Z16reduce_per_blockPiiS_
.p2align 3, 0x0
_Z16reduce_per_blockPiiS_:
.quad _Z31__device_stub__reduce_per_blockPiiS_
.size _Z16reduce_per_blockPiiS_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "CUDA kernel launch with %d blocks of %d threads\n"
.size .L.str, 49
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Sum (CPU) = %d\n"
.size .L.str.1, 16
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Sum (GPU) = %d\n"
.size .L.str.2, 16
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "CPU version (sec.): %.6f\n"
.size .L.str.3, 26
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "GPU version (sec.): %.6f\n"
.size .L.str.4, 26
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "GPU bandwidth (GiB/s): %.2f\n"
.size .L.str.5, 29
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "Speedup: %.2f\n"
.size .L.str.6, 15
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "Speedup (with mem ops.): %.2f\n"
.size .L.str.7, 31
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z16reduce_per_blockPiiS_"
.size .L__unnamed_1, 26
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z31__device_stub__reduce_per_blockPiiS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z16reduce_per_blockPiiS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void matrixSub(double *a, double *b, double *c, int cr, int cc){
long x = blockIdx.x * blockDim.x + threadIdx.x; // col
long y = blockIdx.y * blockDim.y + threadIdx.y; // row
if(x < cc && y < cr){
c[y * cc + x] = a[y * cc + x] - b[y * cc + x];
}
} | code for sm_80
Function : _Z9matrixSubPdS_S_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR4, c[0x0][0x178] ; /* 0x00005e0000047ab9 */
/* 0x000fe40000000a00 */
/*0030*/ USHF.R.S32.HI UR5, URZ, 0x1f, UR5 ; /* 0x0000001f3f057899 */
/* 0x000fe20008011405 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e220000002100 */
/*0050*/ USHF.R.S32.HI UR4, URZ, 0x1f, UR4 ; /* 0x0000001f3f047899 */
/* 0x000fc60008011404 */
/*0060*/ S2R R5, SR_CTAID.Y ; /* 0x0000000000057919 */
/* 0x000e680000002600 */
/*0070*/ S2R R0, SR_TID.Y ; /* 0x0000000000007919 */
/* 0x000e620000002200 */
/*0080*/ IMAD R2, R2, c[0x0][0x0], R3 ; /* 0x0000000002027a24 */
/* 0x001fca00078e0203 */
/*0090*/ ISETP.GE.U32.AND P1, PT, R2, c[0x0][0x17c], PT ; /* 0x00005f0002007a0c */
/* 0x000fe20003f26070 */
/*00a0*/ IMAD R5, R5, c[0x0][0x4], R0 ; /* 0x0000010005057a24 */
/* 0x002fc600078e0200 */
/*00b0*/ ISETP.GE.AND.EX P1, PT, RZ, UR5, PT, P1 ; /* 0x00000005ff007c0c */
/* 0x000fe4000bf26310 */
/*00c0*/ ISETP.GE.U32.AND P0, PT, R5, c[0x0][0x178], PT ; /* 0x00005e0005007a0c */
/* 0x000fc80003f06070 */
/*00d0*/ ISETP.GE.OR.EX P0, PT, RZ, UR4, P1, P0 ; /* 0x00000004ff007c0c */
/* 0x000fda0008f06700 */
/*00e0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00f0*/ IMAD.MOV.U32 R3, RZ, RZ, RZ ; /* 0x000000ffff037224 */
/* 0x000fe200078e00ff */
/*0100*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*0110*/ IMAD R7, R5.reuse, UR5, RZ ; /* 0x0000000505077c24 */
/* 0x040fe4000f8e02ff */
/*0120*/ IMAD.WIDE.U32 R2, R5, c[0x0][0x17c], R2 ; /* 0x00005f0005027a25 */
/* 0x000fc800078e0002 */
/*0130*/ IMAD.IADD R3, R3, 0x1, R7 ; /* 0x0000000103037824 */
/* 0x000fe400078e0207 */
/*0140*/ IMAD.SHL.U32 R8, R2, 0x8, RZ ; /* 0x0000000802087824 */
/* 0x000fc600078e00ff */
/*0150*/ SHF.L.U64.HI R0, R2, 0x3, R3 ; /* 0x0000000302007819 */
/* 0x000fe40000010203 */
/*0160*/ IADD3 R4, P0, R8.reuse, c[0x0][0x160], RZ ; /* 0x0000580008047a10 */
/* 0x040fe40007f1e0ff */
/*0170*/ IADD3 R6, P1, R8, c[0x0][0x168], RZ ; /* 0x00005a0008067a10 */
/* 0x000fe40007f3e0ff */
/*0180*/ IADD3.X R5, R0.reuse, c[0x0][0x164], RZ, P0, !PT ; /* 0x0000590000057a10 */
/* 0x040fe400007fe4ff */
/*0190*/ IADD3.X R7, R0, c[0x0][0x16c], RZ, P1, !PT ; /* 0x00005b0000077a10 */
/* 0x000fc80000ffe4ff */
/*01a0*/ LDG.E.64 R4, [R4.64] ; /* 0x0000000604047981 */
/* 0x000ea8000c1e1b00 */
/*01b0*/ LDG.E.64 R2, [R6.64] ; /* 0x0000000606027981 */
/* 0x000ea2000c1e1b00 */
/*01c0*/ IADD3 R8, P0, R8, c[0x0][0x170], RZ ; /* 0x00005c0008087a10 */
/* 0x000fc80007f1e0ff */
/*01d0*/ IADD3.X R9, R0, c[0x0][0x174], RZ, P0, !PT ; /* 0x00005d0000097a10 */
/* 0x000fe200007fe4ff */
/*01e0*/ DADD R2, -R2, R4 ; /* 0x0000000002027229 */
/* 0x004e0e0000000104 */
/*01f0*/ STG.E.64 [R8.64], R2 ; /* 0x0000000208007986 */
/* 0x001fe2000c101b06 */
/*0200*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0210*/ BRA 0x210; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void matrixSub(double *a, double *b, double *c, int cr, int cc){
long x = blockIdx.x * blockDim.x + threadIdx.x; // col
long y = blockIdx.y * blockDim.y + threadIdx.y; // row
if(x < cc && y < cr){
c[y * cc + x] = a[y * cc + x] - b[y * cc + x];
}
} | .file "tmpxft_000b35ab_00000000-6_matrixSub.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z34__device_stub__Z9matrixSubPdS_S_iiPdS_S_ii
.type _Z34__device_stub__Z9matrixSubPdS_S_iiPdS_S_ii, @function
_Z34__device_stub__Z9matrixSubPdS_S_iiPdS_S_ii:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9matrixSubPdS_S_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z34__device_stub__Z9matrixSubPdS_S_iiPdS_S_ii, .-_Z34__device_stub__Z9matrixSubPdS_S_iiPdS_S_ii
.globl _Z9matrixSubPdS_S_ii
.type _Z9matrixSubPdS_S_ii, @function
_Z9matrixSubPdS_S_ii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z34__device_stub__Z9matrixSubPdS_S_iiPdS_S_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z9matrixSubPdS_S_ii, .-_Z9matrixSubPdS_S_ii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z9matrixSubPdS_S_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z9matrixSubPdS_S_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void matrixSub(double *a, double *b, double *c, int cr, int cc){
long x = blockIdx.x * blockDim.x + threadIdx.x; // col
long y = blockIdx.y * blockDim.y + threadIdx.y; // row
if(x < cc && y < cr){
c[y * cc + x] = a[y * cc + x] - b[y * cc + x];
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void matrixSub(double *a, double *b, double *c, int cr, int cc){
long x = blockIdx.x * blockDim.x + threadIdx.x; // col
long y = blockIdx.y * blockDim.y + threadIdx.y; // row
if(x < cc && y < cr){
c[y * cc + x] = a[y * cc + x] - b[y * cc + x];
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void matrixSub(double *a, double *b, double *c, int cr, int cc){
long x = blockIdx.x * blockDim.x + threadIdx.x; // col
long y = blockIdx.y * blockDim.y + threadIdx.y; // row
if(x < cc && y < cr){
c[y * cc + x] = a[y * cc + x] - b[y * cc + x];
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9matrixSubPdS_S_ii
.globl _Z9matrixSubPdS_S_ii
.p2align 8
.type _Z9matrixSubPdS_S_ii,@function
_Z9matrixSubPdS_S_ii:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x2c
s_load_b64 s[2:3], s[0:1], 0x18
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v4, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s5, s4, 0xffff
s_lshr_b32 s4, s4, 16
v_mad_u64_u32 v[0:1], null, s14, s5, v[2:3]
v_mov_b32_e32 v1, 0
v_mad_u64_u32 v[2:3], null, s15, s4, v[4:5]
s_ashr_i32 s7, s2, 31
s_ashr_i32 s5, s3, 31
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_mov_b32_e32 v3, v1
s_mov_b32 s4, s3
s_mov_b32 s6, s2
v_cmp_gt_i64_e32 vcc_lo, s[4:5], v[0:1]
v_cmp_gt_i64_e64 s2, s[6:7], v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, vcc_lo, s2
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_2
v_mad_u64_u32 v[3:4], null, v2, s4, v[0:1]
s_clause 0x1
s_load_b128 s[8:11], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mov_b32_e32 v0, v4
v_mad_u64_u32 v[4:5], null, v2, s5, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 3, v[3:4]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s8, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s9, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s10, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s11, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b64 v[2:3], v[2:3], off
global_load_b64 v[4:5], v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_f64 v[2:3], v[2:3], -v[4:5]
global_store_b64 v[0:1], v[2:3], off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9matrixSubPdS_S_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9matrixSubPdS_S_ii, .Lfunc_end0-_Z9matrixSubPdS_S_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9matrixSubPdS_S_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9matrixSubPdS_S_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void matrixSub(double *a, double *b, double *c, int cr, int cc){
long x = blockIdx.x * blockDim.x + threadIdx.x; // col
long y = blockIdx.y * blockDim.y + threadIdx.y; // row
if(x < cc && y < cr){
c[y * cc + x] = a[y * cc + x] - b[y * cc + x];
}
} | .text
.file "matrixSub.hip"
.globl _Z24__device_stub__matrixSubPdS_S_ii # -- Begin function _Z24__device_stub__matrixSubPdS_S_ii
.p2align 4, 0x90
.type _Z24__device_stub__matrixSubPdS_S_ii,@function
_Z24__device_stub__matrixSubPdS_S_ii: # @_Z24__device_stub__matrixSubPdS_S_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9matrixSubPdS_S_ii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z24__device_stub__matrixSubPdS_S_ii, .Lfunc_end0-_Z24__device_stub__matrixSubPdS_S_ii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9matrixSubPdS_S_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9matrixSubPdS_S_ii,@object # @_Z9matrixSubPdS_S_ii
.section .rodata,"a",@progbits
.globl _Z9matrixSubPdS_S_ii
.p2align 3, 0x0
_Z9matrixSubPdS_S_ii:
.quad _Z24__device_stub__matrixSubPdS_S_ii
.size _Z9matrixSubPdS_S_ii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z9matrixSubPdS_S_ii"
.size .L__unnamed_1, 21
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__matrixSubPdS_S_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9matrixSubPdS_S_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z9matrixSubPdS_S_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR4, c[0x0][0x178] ; /* 0x00005e0000047ab9 */
/* 0x000fe40000000a00 */
/*0030*/ USHF.R.S32.HI UR5, URZ, 0x1f, UR5 ; /* 0x0000001f3f057899 */
/* 0x000fe20008011405 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e220000002100 */
/*0050*/ USHF.R.S32.HI UR4, URZ, 0x1f, UR4 ; /* 0x0000001f3f047899 */
/* 0x000fc60008011404 */
/*0060*/ S2R R5, SR_CTAID.Y ; /* 0x0000000000057919 */
/* 0x000e680000002600 */
/*0070*/ S2R R0, SR_TID.Y ; /* 0x0000000000007919 */
/* 0x000e620000002200 */
/*0080*/ IMAD R2, R2, c[0x0][0x0], R3 ; /* 0x0000000002027a24 */
/* 0x001fca00078e0203 */
/*0090*/ ISETP.GE.U32.AND P1, PT, R2, c[0x0][0x17c], PT ; /* 0x00005f0002007a0c */
/* 0x000fe20003f26070 */
/*00a0*/ IMAD R5, R5, c[0x0][0x4], R0 ; /* 0x0000010005057a24 */
/* 0x002fc600078e0200 */
/*00b0*/ ISETP.GE.AND.EX P1, PT, RZ, UR5, PT, P1 ; /* 0x00000005ff007c0c */
/* 0x000fe4000bf26310 */
/*00c0*/ ISETP.GE.U32.AND P0, PT, R5, c[0x0][0x178], PT ; /* 0x00005e0005007a0c */
/* 0x000fc80003f06070 */
/*00d0*/ ISETP.GE.OR.EX P0, PT, RZ, UR4, P1, P0 ; /* 0x00000004ff007c0c */
/* 0x000fda0008f06700 */
/*00e0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00f0*/ IMAD.MOV.U32 R3, RZ, RZ, RZ ; /* 0x000000ffff037224 */
/* 0x000fe200078e00ff */
/*0100*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*0110*/ IMAD R7, R5.reuse, UR5, RZ ; /* 0x0000000505077c24 */
/* 0x040fe4000f8e02ff */
/*0120*/ IMAD.WIDE.U32 R2, R5, c[0x0][0x17c], R2 ; /* 0x00005f0005027a25 */
/* 0x000fc800078e0002 */
/*0130*/ IMAD.IADD R3, R3, 0x1, R7 ; /* 0x0000000103037824 */
/* 0x000fe400078e0207 */
/*0140*/ IMAD.SHL.U32 R8, R2, 0x8, RZ ; /* 0x0000000802087824 */
/* 0x000fc600078e00ff */
/*0150*/ SHF.L.U64.HI R0, R2, 0x3, R3 ; /* 0x0000000302007819 */
/* 0x000fe40000010203 */
/*0160*/ IADD3 R4, P0, R8.reuse, c[0x0][0x160], RZ ; /* 0x0000580008047a10 */
/* 0x040fe40007f1e0ff */
/*0170*/ IADD3 R6, P1, R8, c[0x0][0x168], RZ ; /* 0x00005a0008067a10 */
/* 0x000fe40007f3e0ff */
/*0180*/ IADD3.X R5, R0.reuse, c[0x0][0x164], RZ, P0, !PT ; /* 0x0000590000057a10 */
/* 0x040fe400007fe4ff */
/*0190*/ IADD3.X R7, R0, c[0x0][0x16c], RZ, P1, !PT ; /* 0x00005b0000077a10 */
/* 0x000fc80000ffe4ff */
/*01a0*/ LDG.E.64 R4, [R4.64] ; /* 0x0000000604047981 */
/* 0x000ea8000c1e1b00 */
/*01b0*/ LDG.E.64 R2, [R6.64] ; /* 0x0000000606027981 */
/* 0x000ea2000c1e1b00 */
/*01c0*/ IADD3 R8, P0, R8, c[0x0][0x170], RZ ; /* 0x00005c0008087a10 */
/* 0x000fc80007f1e0ff */
/*01d0*/ IADD3.X R9, R0, c[0x0][0x174], RZ, P0, !PT ; /* 0x00005d0000097a10 */
/* 0x000fe200007fe4ff */
/*01e0*/ DADD R2, -R2, R4 ; /* 0x0000000002027229 */
/* 0x004e0e0000000104 */
/*01f0*/ STG.E.64 [R8.64], R2 ; /* 0x0000000208007986 */
/* 0x001fe2000c101b06 */
/*0200*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0210*/ BRA 0x210; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9matrixSubPdS_S_ii
.globl _Z9matrixSubPdS_S_ii
.p2align 8
.type _Z9matrixSubPdS_S_ii,@function
_Z9matrixSubPdS_S_ii:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x2c
s_load_b64 s[2:3], s[0:1], 0x18
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v4, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s5, s4, 0xffff
s_lshr_b32 s4, s4, 16
v_mad_u64_u32 v[0:1], null, s14, s5, v[2:3]
v_mov_b32_e32 v1, 0
v_mad_u64_u32 v[2:3], null, s15, s4, v[4:5]
s_ashr_i32 s7, s2, 31
s_ashr_i32 s5, s3, 31
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_mov_b32_e32 v3, v1
s_mov_b32 s4, s3
s_mov_b32 s6, s2
v_cmp_gt_i64_e32 vcc_lo, s[4:5], v[0:1]
v_cmp_gt_i64_e64 s2, s[6:7], v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, vcc_lo, s2
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_2
v_mad_u64_u32 v[3:4], null, v2, s4, v[0:1]
s_clause 0x1
s_load_b128 s[8:11], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mov_b32_e32 v0, v4
v_mad_u64_u32 v[4:5], null, v2, s5, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 3, v[3:4]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s8, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s9, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s10, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s11, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b64 v[2:3], v[2:3], off
global_load_b64 v[4:5], v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_f64 v[2:3], v[2:3], -v[4:5]
global_store_b64 v[0:1], v[2:3], off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9matrixSubPdS_S_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9matrixSubPdS_S_ii, .Lfunc_end0-_Z9matrixSubPdS_S_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9matrixSubPdS_S_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9matrixSubPdS_S_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000b35ab_00000000-6_matrixSub.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z34__device_stub__Z9matrixSubPdS_S_iiPdS_S_ii
.type _Z34__device_stub__Z9matrixSubPdS_S_iiPdS_S_ii, @function
_Z34__device_stub__Z9matrixSubPdS_S_iiPdS_S_ii:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9matrixSubPdS_S_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z34__device_stub__Z9matrixSubPdS_S_iiPdS_S_ii, .-_Z34__device_stub__Z9matrixSubPdS_S_iiPdS_S_ii
.globl _Z9matrixSubPdS_S_ii
.type _Z9matrixSubPdS_S_ii, @function
_Z9matrixSubPdS_S_ii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z34__device_stub__Z9matrixSubPdS_S_iiPdS_S_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z9matrixSubPdS_S_ii, .-_Z9matrixSubPdS_S_ii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z9matrixSubPdS_S_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z9matrixSubPdS_S_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "matrixSub.hip"
.globl _Z24__device_stub__matrixSubPdS_S_ii # -- Begin function _Z24__device_stub__matrixSubPdS_S_ii
.p2align 4, 0x90
.type _Z24__device_stub__matrixSubPdS_S_ii,@function
_Z24__device_stub__matrixSubPdS_S_ii: # @_Z24__device_stub__matrixSubPdS_S_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9matrixSubPdS_S_ii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z24__device_stub__matrixSubPdS_S_ii, .Lfunc_end0-_Z24__device_stub__matrixSubPdS_S_ii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9matrixSubPdS_S_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9matrixSubPdS_S_ii,@object # @_Z9matrixSubPdS_S_ii
.section .rodata,"a",@progbits
.globl _Z9matrixSubPdS_S_ii
.p2align 3, 0x0
_Z9matrixSubPdS_S_ii:
.quad _Z24__device_stub__matrixSubPdS_S_ii
.size _Z9matrixSubPdS_S_ii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z9matrixSubPdS_S_ii"
.size .L__unnamed_1, 21
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__matrixSubPdS_S_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9matrixSubPdS_S_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | //////////////////////////////////////////////////////////////////////
//Name: CombineCost.cu
//Created date: 4-2-2012
//Modified date: 4-2-2012
//Author: Gorkem Saygili, Jianbin Fang and Jie Shen
//Discription: combine initial cost with state-of-the-art (cuda kernel)
///////////////////////////////////////////////////////////////////////
#include <math.h>
__global__ void combineCost(float *cost_image1,
float *cost_image2, const float lambda1,
const float lambda2, const int rdim, const int cdim,
int dispRange){
int x = blockIdx.x * blockDim.x + threadIdx.x;
int y = blockIdx.y * blockDim.y + threadIdx.y;
float cost1=0,cost2=0;
int idx=0,a=0;
for(int d=0; d<dispRange; d++){
idx = d+dispRange*(x+cdim*y);
cost1 = cost_image1[idx];
cost2 = cost_image2[idx];
cost1 = 1-exp(-cost1/lambda1);
cost2 = 1-exp(-cost2/lambda2);
cost_image1[idx] = cost1+cost2;
}
} | .file "tmpxft_00092ed7_00000000-6_CombineCost.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z38__device_stub__Z11combineCostPfS_ffiiiPfS_ffiii
.type _Z38__device_stub__Z11combineCostPfS_ffiiiPfS_ffiii, @function
_Z38__device_stub__Z11combineCostPfS_ffiiiPfS_ffiii:
.LFB2051:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movss %xmm0, 28(%rsp)
movss %xmm1, 24(%rsp)
movl %edx, 20(%rsp)
movl %ecx, 16(%rsp)
movl %r8d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 28(%rsp), %rax
movq %rax, 128(%rsp)
leaq 24(%rsp), %rax
movq %rax, 136(%rsp)
leaq 20(%rsp), %rax
movq %rax, 144(%rsp)
leaq 16(%rsp), %rax
movq %rax, 152(%rsp)
leaq 12(%rsp), %rax
movq %rax, 160(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z11combineCostPfS_ffiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z38__device_stub__Z11combineCostPfS_ffiiiPfS_ffiii, .-_Z38__device_stub__Z11combineCostPfS_ffiiiPfS_ffiii
.globl _Z11combineCostPfS_ffiii
.type _Z11combineCostPfS_ffiii, @function
_Z11combineCostPfS_ffiii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z38__device_stub__Z11combineCostPfS_ffiiiPfS_ffiii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z11combineCostPfS_ffiii, .-_Z11combineCostPfS_ffiii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z11combineCostPfS_ffiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z11combineCostPfS_ffiii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | //////////////////////////////////////////////////////////////////////
//Name: CombineCost.cu
//Created date: 4-2-2012
//Modified date: 4-2-2012
//Author: Gorkem Saygili, Jianbin Fang and Jie Shen
//Discription: combine initial cost with state-of-the-art (cuda kernel)
///////////////////////////////////////////////////////////////////////
#include <math.h>
__global__ void combineCost(float *cost_image1,
float *cost_image2, const float lambda1,
const float lambda2, const int rdim, const int cdim,
int dispRange){
int x = blockIdx.x * blockDim.x + threadIdx.x;
int y = blockIdx.y * blockDim.y + threadIdx.y;
float cost1=0,cost2=0;
int idx=0,a=0;
for(int d=0; d<dispRange; d++){
idx = d+dispRange*(x+cdim*y);
cost1 = cost_image1[idx];
cost2 = cost_image2[idx];
cost1 = 1-exp(-cost1/lambda1);
cost2 = 1-exp(-cost2/lambda2);
cost_image1[idx] = cost1+cost2;
}
} | //////////////////////////////////////////////////////////////////////
//Name: CombineCost.cu
//Created date: 4-2-2012
//Modified date: 4-2-2012
//Author: Gorkem Saygili, Jianbin Fang and Jie Shen
//Discription: combine initial cost with state-of-the-art (cuda kernel)
///////////////////////////////////////////////////////////////////////
#include <hip/hip_runtime.h>
#include <math.h>
__global__ void combineCost(float *cost_image1,
float *cost_image2, const float lambda1,
const float lambda2, const int rdim, const int cdim,
int dispRange){
int x = blockIdx.x * blockDim.x + threadIdx.x;
int y = blockIdx.y * blockDim.y + threadIdx.y;
float cost1=0,cost2=0;
int idx=0,a=0;
for(int d=0; d<dispRange; d++){
idx = d+dispRange*(x+cdim*y);
cost1 = cost_image1[idx];
cost2 = cost_image2[idx];
cost1 = 1-exp(-cost1/lambda1);
cost2 = 1-exp(-cost2/lambda2);
cost_image1[idx] = cost1+cost2;
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | //////////////////////////////////////////////////////////////////////
//Name: CombineCost.cu
//Created date: 4-2-2012
//Modified date: 4-2-2012
//Author: Gorkem Saygili, Jianbin Fang and Jie Shen
//Discription: combine initial cost with state-of-the-art (cuda kernel)
///////////////////////////////////////////////////////////////////////
#include <hip/hip_runtime.h>
#include <math.h>
__global__ void combineCost(float *cost_image1,
float *cost_image2, const float lambda1,
const float lambda2, const int rdim, const int cdim,
int dispRange){
int x = blockIdx.x * blockDim.x + threadIdx.x;
int y = blockIdx.y * blockDim.y + threadIdx.y;
float cost1=0,cost2=0;
int idx=0,a=0;
for(int d=0; d<dispRange; d++){
idx = d+dispRange*(x+cdim*y);
cost1 = cost_image1[idx];
cost2 = cost_image2[idx];
cost1 = 1-exp(-cost1/lambda1);
cost2 = 1-exp(-cost2/lambda2);
cost_image1[idx] = cost1+cost2;
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11combineCostPfS_ffiii
.globl _Z11combineCostPfS_ffiii
.p2align 8
.type _Z11combineCostPfS_ffiii,@function
_Z11combineCostPfS_ffiii:
s_load_b32 s4, s[0:1], 0x20
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s4, 1
s_cbranch_scc1 .LBB0_3
s_clause 0x1
s_load_b32 s2, s[0:1], 0x34
s_load_b32 s3, s[0:1], 0x1c
v_bfe_u32 v1, v0, 10, 10
v_and_b32_e32 v0, 0x3ff, v0
s_load_b128 s[8:11], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s5, s2, 16
s_and_b32 s2, s2, 0xffff
v_mad_u64_u32 v[2:3], null, s15, s5, v[1:2]
s_mul_i32 s14, s14, s2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mul_lo_u32 v1, v2, s3
s_load_b64 s[2:3], s[0:1], 0x10
v_add3_u32 v0, s14, v0, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v0, v0, s4
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[0:1]
v_add_co_u32 v0, vcc_lo, s8, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s9, v3, vcc_lo
v_add_co_u32 v2, vcc_lo, s10, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s11, v3, vcc_lo
.LBB0_2:
global_load_b32 v4, v[0:1], off
global_load_b32 v5, v[2:3], off
s_add_i32 s4, s4, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s4, 0
s_waitcnt vmcnt(1) lgkmcnt(0)
v_div_scale_f32 v6, null, s2, s2, -v4
s_waitcnt vmcnt(0)
v_div_scale_f32 v7, null, s3, s3, -v5
v_div_scale_f32 v12, vcc_lo, -v4, s2, -v4
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_rcp_f32_e32 v8, v6
v_rcp_f32_e32 v9, v7
s_waitcnt_depctr 0xfff
v_fma_f32 v10, -v6, v8, 1.0
v_fma_f32 v11, -v7, v9, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_dual_fmac_f32 v8, v10, v8 :: v_dual_fmac_f32 v9, v11, v9
v_div_scale_f32 v10, s0, -v5, s3, -v5
v_mul_f32_e32 v11, v12, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v14, -v6, v11, v12
v_fmac_f32_e32 v11, v14, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v6, -v6, v11, v12
v_div_fmas_f32 v6, v6, v8, v11
s_mov_b32 vcc_lo, s0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fixup_f32 v4, v6, s2, -v4
v_dual_mul_f32 v13, v10, v9 :: v_dual_mul_f32 v6, 0x3fb8aa3b, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v15, -v7, v13, v10
v_fma_f32 v8, v4, 0x3fb8aa3b, -v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_fmac_f32 v13, v15, v9 :: v_dual_fmac_f32 v8, 0x32a5705f, v4
v_fma_f32 v7, -v7, v13, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_div_fmas_f32 v7, v7, v9, v13
v_rndne_f32_e32 v9, v6
v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v4
v_div_fixup_f32 v5, v7, s3, -v5
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_f32_e32 v6, v6, v9
v_dual_mul_f32 v7, 0x3fb8aa3b, v5 :: v_dual_add_f32 v6, v6, v8
v_cvt_i32_f32_e32 v8, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fma_f32 v10, v5, 0x3fb8aa3b, -v7
v_exp_f32_e32 v6, v6
v_rndne_f32_e32 v11, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fmac_f32_e32 v10, 0x32a5705f, v5
v_cvt_i32_f32_e32 v9, v11
s_waitcnt_depctr 0xfff
v_ldexp_f32 v6, v6, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_sub_f32 v7, v7, v11 :: v_dual_cndmask_b32 v6, 0, v6
v_add_f32_e32 v7, v7, v10
v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_exp_f32_e32 v7, v7
s_waitcnt_depctr 0xfff
v_ldexp_f32 v7, v7, v9
v_cndmask_b32_e32 v7, 0, v7, vcc_lo
v_cmp_nlt_f32_e32 vcc_lo, 0x42b17218, v4
v_cndmask_b32_e32 v4, 0x7f800000, v6, vcc_lo
v_cmp_nlt_f32_e32 vcc_lo, 0x42b17218, v5
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v5, 0x7f800000, v7, vcc_lo
v_dual_sub_f32 v5, 1.0, v5 :: v_dual_sub_f32 v4, 1.0, v4
s_delay_alu instid0(VALU_DEP_1)
v_add_f32_e32 v4, v4, v5
global_store_b32 v[0:1], v4, off
v_add_co_u32 v0, vcc_lo, v0, 4
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
v_add_co_u32 v2, vcc_lo, v2, 4
v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
s_cbranch_scc0 .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11combineCostPfS_ffiii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 16
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z11combineCostPfS_ffiii, .Lfunc_end0-_Z11combineCostPfS_ffiii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11combineCostPfS_ffiii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z11combineCostPfS_ffiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 16
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | //////////////////////////////////////////////////////////////////////
//Name: CombineCost.cu
//Created date: 4-2-2012
//Modified date: 4-2-2012
//Author: Gorkem Saygili, Jianbin Fang and Jie Shen
//Discription: combine initial cost with state-of-the-art (cuda kernel)
///////////////////////////////////////////////////////////////////////
#include <hip/hip_runtime.h>
#include <math.h>
__global__ void combineCost(float *cost_image1,
float *cost_image2, const float lambda1,
const float lambda2, const int rdim, const int cdim,
int dispRange){
int x = blockIdx.x * blockDim.x + threadIdx.x;
int y = blockIdx.y * blockDim.y + threadIdx.y;
float cost1=0,cost2=0;
int idx=0,a=0;
for(int d=0; d<dispRange; d++){
idx = d+dispRange*(x+cdim*y);
cost1 = cost_image1[idx];
cost2 = cost_image2[idx];
cost1 = 1-exp(-cost1/lambda1);
cost2 = 1-exp(-cost2/lambda2);
cost_image1[idx] = cost1+cost2;
}
} | .text
.file "CombineCost.hip"
.globl _Z26__device_stub__combineCostPfS_ffiii # -- Begin function _Z26__device_stub__combineCostPfS_ffiii
.p2align 4, 0x90
.type _Z26__device_stub__combineCostPfS_ffiii,@function
_Z26__device_stub__combineCostPfS_ffiii: # @_Z26__device_stub__combineCostPfS_ffiii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movss %xmm0, 28(%rsp)
movss %xmm1, 24(%rsp)
movl %edx, 20(%rsp)
movl %ecx, 16(%rsp)
movl %r8d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 28(%rsp), %rax
movq %rax, 112(%rsp)
leaq 24(%rsp), %rax
movq %rax, 120(%rsp)
leaq 20(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 12(%rsp), %rax
movq %rax, 144(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z11combineCostPfS_ffiii, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z26__device_stub__combineCostPfS_ffiii, .Lfunc_end0-_Z26__device_stub__combineCostPfS_ffiii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11combineCostPfS_ffiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z11combineCostPfS_ffiii,@object # @_Z11combineCostPfS_ffiii
.section .rodata,"a",@progbits
.globl _Z11combineCostPfS_ffiii
.p2align 3, 0x0
_Z11combineCostPfS_ffiii:
.quad _Z26__device_stub__combineCostPfS_ffiii
.size _Z11combineCostPfS_ffiii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z11combineCostPfS_ffiii"
.size .L__unnamed_1, 25
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__combineCostPfS_ffiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11combineCostPfS_ffiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00092ed7_00000000-6_CombineCost.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z38__device_stub__Z11combineCostPfS_ffiiiPfS_ffiii
.type _Z38__device_stub__Z11combineCostPfS_ffiiiPfS_ffiii, @function
_Z38__device_stub__Z11combineCostPfS_ffiiiPfS_ffiii:
.LFB2051:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movss %xmm0, 28(%rsp)
movss %xmm1, 24(%rsp)
movl %edx, 20(%rsp)
movl %ecx, 16(%rsp)
movl %r8d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 28(%rsp), %rax
movq %rax, 128(%rsp)
leaq 24(%rsp), %rax
movq %rax, 136(%rsp)
leaq 20(%rsp), %rax
movq %rax, 144(%rsp)
leaq 16(%rsp), %rax
movq %rax, 152(%rsp)
leaq 12(%rsp), %rax
movq %rax, 160(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z11combineCostPfS_ffiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z38__device_stub__Z11combineCostPfS_ffiiiPfS_ffiii, .-_Z38__device_stub__Z11combineCostPfS_ffiiiPfS_ffiii
.globl _Z11combineCostPfS_ffiii
.type _Z11combineCostPfS_ffiii, @function
_Z11combineCostPfS_ffiii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z38__device_stub__Z11combineCostPfS_ffiiiPfS_ffiii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z11combineCostPfS_ffiii, .-_Z11combineCostPfS_ffiii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z11combineCostPfS_ffiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z11combineCostPfS_ffiii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "CombineCost.hip"
.globl _Z26__device_stub__combineCostPfS_ffiii # -- Begin function _Z26__device_stub__combineCostPfS_ffiii
.p2align 4, 0x90
.type _Z26__device_stub__combineCostPfS_ffiii,@function
_Z26__device_stub__combineCostPfS_ffiii: # @_Z26__device_stub__combineCostPfS_ffiii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movss %xmm0, 28(%rsp)
movss %xmm1, 24(%rsp)
movl %edx, 20(%rsp)
movl %ecx, 16(%rsp)
movl %r8d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 28(%rsp), %rax
movq %rax, 112(%rsp)
leaq 24(%rsp), %rax
movq %rax, 120(%rsp)
leaq 20(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 12(%rsp), %rax
movq %rax, 144(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z11combineCostPfS_ffiii, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z26__device_stub__combineCostPfS_ffiii, .Lfunc_end0-_Z26__device_stub__combineCostPfS_ffiii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11combineCostPfS_ffiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z11combineCostPfS_ffiii,@object # @_Z11combineCostPfS_ffiii
.section .rodata,"a",@progbits
.globl _Z11combineCostPfS_ffiii
.p2align 3, 0x0
_Z11combineCostPfS_ffiii:
.quad _Z26__device_stub__combineCostPfS_ffiii
.size _Z11combineCostPfS_ffiii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z11combineCostPfS_ffiii"
.size .L__unnamed_1, 25
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__combineCostPfS_ffiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11combineCostPfS_ffiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <cstdio>
#include <cstdlib>
#include <vector>
#include <memory>
#include <iostream>
#include <cuda.h>
#include <curand.h>
#include <curand_kernel.h>
__device__ float generate(curandState* globalState, int ind)
{
curandState localState = globalState[ind];
float RANDOM = curand_uniform( &localState );
globalState[ind] = localState;
return RANDOM;
}
__global__ void setup_kernel ( curandState * state, unsigned long seed )
{
int id = threadIdx.x + blockIdx.x * blockDim.x;
curand_init ( seed, id, 0, &state[id] );
}
__global__ void addToCount(int N, int *y, curandState* globalState)
{
int id = threadIdx.x + blockIdx.x * blockDim.x;
while (id < N)
{
int number = generate(globalState, id) * 1000000;
printf("%i\n", number);
atomicAdd(&(y[0]), number);
id += blockDim.x * gridDim.x;
}
}
__device__ float3 generate3(curandState* globalState, int ind)
{
/*
generate random x, y, z position for particles
*/
float3 newposition = make_float3(0.0,0.0,0.0);
curandState localState = globalState[ind];
newposition.x = curand_uniform( &localState );
newposition.y = curand_uniform( &localState );
newposition.z = curand_uniform( &localState );
globalState[ind] = localState;
return newposition;
}
__global__ void initPosition(int N, float4 *d_par, curandState* globalState)
{
int id = threadIdx.x + blockIdx.x * blockDim.x;
if (id < N) // final block may not have all the threads
{
auto position = generate3(globalState, id);
d_par[id].w = (float) id / 1000.0; // mass
d_par[id].x = 2.0*position.x-1.0;
d_par[id].y = 2.0*position.y-1.0;
d_par[id].z = 2.0*position.z-1.0;
//id += blockDim.x * gridDim.x;
}
}
int main(int argc, char** argv)
{
int N = 768;
int *d_y;
float4 *d_par; // particle positions and mass
std::vector<int> y(N);
std::vector<float4> par(N);
int blocksize = 256; // value usually chosen by tuning and hardware constraints
int nblocks = ceil( (float) N/blocksize);
printf("nblocks = %i\n", nblocks);
cudaMalloc(&d_y, N * sizeof(int));
//cudaMemcpy(d_y, &y[0], N * sizeof(int), cudaMemcpyHostToDevice);
// allocate memory on device
cudaMalloc(&d_par, N * sizeof(float4));
curandState* devStates;
cudaMalloc (&devStates, N * sizeof(curandState));
//srand(time(0));
srand(1234);
/** ADD THESE TWO LINES **/
int seed = rand();
setup_kernel<<<nblocks, blocksize>>>(devStates,seed);
/** END ADDITION **/
addToCount<<<nblocks, blocksize>>>(N, d_y, devStates);
initPosition<<<nblocks, blocksize>>>(N, d_par, devStates);
cudaDeviceSynchronize();
cudaMemcpy(&y[0], d_y, N*sizeof(int), cudaMemcpyDeviceToHost);
//cudaMemcpy(y, d_y, N*sizeof(int), cudaMemcpyDeviceToHost);
cudaMemcpy(&par[0], d_par, N*sizeof(float4), cudaMemcpyDeviceToHost);
printf("final = %i\n", y[0]);
printf("# %i particles:\n", N);
for (auto particle : par) {
printf("%15.7f %15.7f %15.7f %15.7f\n", particle.w,
particle.x, particle.y, particle.z);
}
// Free the GPU memory here
cudaFree(d_y);
cudaFree(d_par);
cudaFree(devStates);
} | .file "tmpxft_0010659a_00000000-6_test4.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB4838:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4838:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z8generateP17curandStateXORWOWi
.type _Z8generateP17curandStateXORWOWi, @function
_Z8generateP17curandStateXORWOWi:
.LFB4833:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE4833:
.size _Z8generateP17curandStateXORWOWi, .-_Z8generateP17curandStateXORWOWi
.globl _Z9generate3P17curandStateXORWOWi
.type _Z9generate3P17curandStateXORWOWi, @function
_Z9generate3P17curandStateXORWOWi:
.LFB4834:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE4834:
.size _Z9generate3P17curandStateXORWOWi, .-_Z9generate3P17curandStateXORWOWi
.globl _Z51__device_stub__Z12setup_kernelP17curandStateXORWOWmP17curandStateXORWOWm
.type _Z51__device_stub__Z12setup_kernelP17curandStateXORWOWmP17curandStateXORWOWm, @function
_Z51__device_stub__Z12setup_kernelP17curandStateXORWOWmP17curandStateXORWOWm:
.LFB4860:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L11
.L7:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L12
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z12setup_kernelP17curandStateXORWOWm(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L7
.L12:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4860:
.size _Z51__device_stub__Z12setup_kernelP17curandStateXORWOWmP17curandStateXORWOWm, .-_Z51__device_stub__Z12setup_kernelP17curandStateXORWOWmP17curandStateXORWOWm
.globl _Z12setup_kernelP17curandStateXORWOWm
.type _Z12setup_kernelP17curandStateXORWOWm, @function
_Z12setup_kernelP17curandStateXORWOWm:
.LFB4861:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z51__device_stub__Z12setup_kernelP17curandStateXORWOWmP17curandStateXORWOWm
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4861:
.size _Z12setup_kernelP17curandStateXORWOWm, .-_Z12setup_kernelP17curandStateXORWOWm
.globl _Z51__device_stub__Z10addToCountiPiP17curandStateXORWOWiPiP17curandStateXORWOW
.type _Z51__device_stub__Z10addToCountiPiP17curandStateXORWOWiPiP17curandStateXORWOW, @function
_Z51__device_stub__Z10addToCountiPiP17curandStateXORWOWiPiP17curandStateXORWOW:
.LFB4862:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movl %edi, 28(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L19
.L15:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L20
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z10addToCountiPiP17curandStateXORWOW(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L15
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4862:
.size _Z51__device_stub__Z10addToCountiPiP17curandStateXORWOWiPiP17curandStateXORWOW, .-_Z51__device_stub__Z10addToCountiPiP17curandStateXORWOWiPiP17curandStateXORWOW
.globl _Z10addToCountiPiP17curandStateXORWOW
.type _Z10addToCountiPiP17curandStateXORWOW, @function
_Z10addToCountiPiP17curandStateXORWOW:
.LFB4863:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z51__device_stub__Z10addToCountiPiP17curandStateXORWOWiPiP17curandStateXORWOW
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4863:
.size _Z10addToCountiPiP17curandStateXORWOW, .-_Z10addToCountiPiP17curandStateXORWOW
.globl _Z59__device_stub__Z12initPositioniP6float4P17curandStateXORWOWiP6float4P17curandStateXORWOW
.type _Z59__device_stub__Z12initPositioniP6float4P17curandStateXORWOWiP6float4P17curandStateXORWOW, @function
_Z59__device_stub__Z12initPositioniP6float4P17curandStateXORWOWiP6float4P17curandStateXORWOW:
.LFB4864:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movl %edi, 28(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L27
.L23:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L28
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L27:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z12initPositioniP6float4P17curandStateXORWOW(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L23
.L28:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4864:
.size _Z59__device_stub__Z12initPositioniP6float4P17curandStateXORWOWiP6float4P17curandStateXORWOW, .-_Z59__device_stub__Z12initPositioniP6float4P17curandStateXORWOWiP6float4P17curandStateXORWOW
.globl _Z12initPositioniP6float4P17curandStateXORWOW
.type _Z12initPositioniP6float4P17curandStateXORWOW, @function
_Z12initPositioniP6float4P17curandStateXORWOW:
.LFB4865:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z59__device_stub__Z12initPositioniP6float4P17curandStateXORWOWiP6float4P17curandStateXORWOW
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4865:
.size _Z12initPositioniP6float4P17curandStateXORWOW, .-_Z12initPositioniP6float4P17curandStateXORWOW
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z12initPositioniP6float4P17curandStateXORWOW"
.align 8
.LC1:
.string "_Z10addToCountiPiP17curandStateXORWOW"
.align 8
.LC2:
.string "_Z12setup_kernelP17curandStateXORWOWm"
.section .rodata.str1.1,"aMS",@progbits,1
.LC3:
.string "precalc_xorwow_matrix"
.LC4:
.string "precalc_xorwow_offset_matrix"
.LC5:
.string "mrg32k3aM1"
.LC6:
.string "mrg32k3aM2"
.LC7:
.string "mrg32k3aM1SubSeq"
.LC8:
.string "mrg32k3aM2SubSeq"
.LC9:
.string "mrg32k3aM1Seq"
.LC10:
.string "mrg32k3aM2Seq"
.LC11:
.string "__cr_lgamma_table"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB4867:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z12initPositioniP6float4P17curandStateXORWOW(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z10addToCountiPiP17curandStateXORWOW(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z12setup_kernelP17curandStateXORWOWm(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $102400, %r9d
movl $0, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _ZL21precalc_xorwow_matrix(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $102400, %r9d
movl $0, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _ZL28precalc_xorwow_offset_matrix(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _ZL10mrg32k3aM1(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _ZL10mrg32k3aM2(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2016, %r9d
movl $0, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _ZL16mrg32k3aM1SubSeq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2016, %r9d
movl $0, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _ZL16mrg32k3aM2SubSeq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _ZL13mrg32k3aM1Seq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC10(%rip), %rdx
movq %rdx, %rcx
leaq _ZL13mrg32k3aM2Seq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $72, %r9d
movl $0, %r8d
leaq .LC11(%rip), %rdx
movq %rdx, %rcx
leaq _ZL17__cr_lgamma_table(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4867:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .text._ZNSt6vectorIiSaIiEED2Ev,"axG",@progbits,_ZNSt6vectorIiSaIiEED5Ev,comdat
.align 2
.weak _ZNSt6vectorIiSaIiEED2Ev
.type _ZNSt6vectorIiSaIiEED2Ev, @function
_ZNSt6vectorIiSaIiEED2Ev:
.LFB5182:
.cfi_startproc
endbr64
movq (%rdi), %rax
testq %rax, %rax
je .L36
subq $8, %rsp
.cfi_def_cfa_offset 16
movq 16(%rdi), %rsi
subq %rax, %rsi
movq %rax, %rdi
call _ZdlPvm@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.L36:
ret
.cfi_endproc
.LFE5182:
.size _ZNSt6vectorIiSaIiEED2Ev, .-_ZNSt6vectorIiSaIiEED2Ev
.weak _ZNSt6vectorIiSaIiEED1Ev
.set _ZNSt6vectorIiSaIiEED1Ev,_ZNSt6vectorIiSaIiEED2Ev
.section .text._ZNSt6vectorI6float4SaIS0_EED2Ev,"axG",@progbits,_ZNSt6vectorI6float4SaIS0_EED5Ev,comdat
.align 2
.weak _ZNSt6vectorI6float4SaIS0_EED2Ev
.type _ZNSt6vectorI6float4SaIS0_EED2Ev, @function
_ZNSt6vectorI6float4SaIS0_EED2Ev:
.LFB5194:
.cfi_startproc
endbr64
movq (%rdi), %rax
testq %rax, %rax
je .L42
subq $8, %rsp
.cfi_def_cfa_offset 16
movq 16(%rdi), %rsi
subq %rax, %rsi
movq %rax, %rdi
call _ZdlPvm@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.L42:
ret
.cfi_endproc
.LFE5194:
.size _ZNSt6vectorI6float4SaIS0_EED2Ev, .-_ZNSt6vectorI6float4SaIS0_EED2Ev
.weak _ZNSt6vectorI6float4SaIS0_EED1Ev
.set _ZNSt6vectorI6float4SaIS0_EED1Ev,_ZNSt6vectorI6float4SaIS0_EED2Ev
.section .rodata.str1.1
.LC13:
.string "nblocks = %i\n"
.LC14:
.string "final = %i\n"
.LC15:
.string "# %i particles:\n"
.LC16:
.string "%15.7f %15.7f %15.7f %15.7f\n"
.text
.globl main
.type main, @function
main:
.LFB4835:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA4835
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $112, %rsp
.cfi_def_cfa_offset 144
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
movl $3072, %edi
.LEHB0:
call _Znwm@PLT
.LEHE0:
movq %rax, %rbx
movq %rax, 48(%rsp)
leaq 3072(%rax), %rdx
movq %rdx, 64(%rsp)
movl $0, (%rax)
leaq 4(%rax), %rax
.L46:
movl $0, (%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L46
movq %rdx, 56(%rsp)
movq $0, 88(%rsp)
movq $0, 96(%rsp)
movl $12288, %edi
.LEHB1:
call _Znwm@PLT
.LEHE1:
movq %rax, %rbp
movq %rax, 80(%rsp)
leaq 12288(%rax), %rdx
movq %rdx, 96(%rsp)
movl $0x00000000, (%rax)
movl $0x00000000, 4(%rax)
movl $0x00000000, 8(%rax)
movl $0x00000000, 12(%rax)
leaq 16(%rax), %rax
.L47:
movdqa 0(%rbp), %xmm4
movaps %xmm4, (%rax)
addq $16, %rax
cmpq %rax, %rdx
jne .L47
movq %rdx, 88(%rsp)
movl $3, %edx
leaq .LC13(%rip), %rsi
movl $2, %edi
movl $0, %eax
.LEHB2:
call __printf_chk@PLT
movq %rsp, %rdi
movl $3072, %esi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movl $12288, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $36864, %esi
call cudaMalloc@PLT
movl $1234, %edi
call srand@PLT
call rand@PLT
movl %eax, %r12d
movl $256, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $3, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L48
movslq %r12d, %rsi
movq 16(%rsp), %rdi
call _Z51__device_stub__Z12setup_kernelP17curandStateXORWOWmP17curandStateXORWOWm
.L48:
movl $256, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $3, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L49
movq 16(%rsp), %rdx
movq (%rsp), %rsi
movl $768, %edi
call _Z51__device_stub__Z10addToCountiPiP17curandStateXORWOWiPiP17curandStateXORWOW
.L49:
movl $256, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $3, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L50
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
movl $768, %edi
call _Z59__device_stub__Z12initPositioniP6float4P17curandStateXORWOWiP6float4P17curandStateXORWOW
.L50:
call cudaDeviceSynchronize@PLT
movl $2, %ecx
movl $3072, %edx
movq (%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movl $2, %ecx
movl $12288, %edx
movq 8(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
movl (%rbx), %edx
leaq .LC14(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $768, %edx
leaq .LC15(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rbp, %rbx
addq $12288, %rbp
leaq .LC16(%rip), %r12
jmp .L51
.L64:
addq $16, %rbx
cmpq %rbx, %rbp
je .L63
.L51:
pxor %xmm0, %xmm0
cvtss2sd 12(%rbx), %xmm0
pxor %xmm3, %xmm3
cvtss2sd 8(%rbx), %xmm3
pxor %xmm2, %xmm2
cvtss2sd 4(%rbx), %xmm2
pxor %xmm1, %xmm1
cvtss2sd (%rbx), %xmm1
movq %r12, %rsi
movl $2, %edi
movl $4, %eax
call __printf_chk@PLT
jmp .L64
.L63:
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
.LEHE2:
leaq 80(%rsp), %rdi
call _ZNSt6vectorI6float4SaIS0_EED1Ev
leaq 48(%rsp), %rdi
call _ZNSt6vectorIiSaIiEED1Ev
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L65
movl $0, %eax
addq $112, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L57:
.cfi_restore_state
endbr64
movq %rax, %rbx
leaq 80(%rsp), %rdi
call _ZNSt6vectorI6float4SaIS0_EED1Ev
.L53:
leaq 48(%rsp), %rdi
call _ZNSt6vectorIiSaIiEED1Ev
movq 104(%rsp), %rax
subq %fs:40, %rax
je .L54
call __stack_chk_fail@PLT
.L56:
endbr64
movq %rax, %rbx
jmp .L53
.L54:
movq %rbx, %rdi
.LEHB3:
call _Unwind_Resume@PLT
.LEHE3:
.L65:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4835:
.globl __gxx_personality_v0
.section .gcc_except_table,"a",@progbits
.LLSDA4835:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE4835-.LLSDACSB4835
.LLSDACSB4835:
.uleb128 .LEHB0-.LFB4835
.uleb128 .LEHE0-.LEHB0
.uleb128 0
.uleb128 0
.uleb128 .LEHB1-.LFB4835
.uleb128 .LEHE1-.LEHB1
.uleb128 .L56-.LFB4835
.uleb128 0
.uleb128 .LEHB2-.LFB4835
.uleb128 .LEHE2-.LEHB2
.uleb128 .L57-.LFB4835
.uleb128 0
.uleb128 .LEHB3-.LFB4835
.uleb128 .LEHE3-.LEHB3
.uleb128 0
.uleb128 0
.LLSDACSE4835:
.text
.size main, .-main
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL17__cr_lgamma_table
.comm _ZL17__cr_lgamma_table,72,32
.local _ZL13mrg32k3aM2Seq
.comm _ZL13mrg32k3aM2Seq,2304,32
.local _ZL13mrg32k3aM1Seq
.comm _ZL13mrg32k3aM1Seq,2304,32
.local _ZL16mrg32k3aM2SubSeq
.comm _ZL16mrg32k3aM2SubSeq,2016,32
.local _ZL16mrg32k3aM1SubSeq
.comm _ZL16mrg32k3aM1SubSeq,2016,32
.local _ZL10mrg32k3aM2
.comm _ZL10mrg32k3aM2,2304,32
.local _ZL10mrg32k3aM1
.comm _ZL10mrg32k3aM1,2304,32
.local _ZL28precalc_xorwow_offset_matrix
.comm _ZL28precalc_xorwow_offset_matrix,102400,32
.local _ZL21precalc_xorwow_matrix
.comm _ZL21precalc_xorwow_matrix,102400,32
.hidden DW.ref.__gxx_personality_v0
.weak DW.ref.__gxx_personality_v0
.section .data.rel.local.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat
.align 8
.type DW.ref.__gxx_personality_v0, @object
.size DW.ref.__gxx_personality_v0, 8
DW.ref.__gxx_personality_v0:
.quad __gxx_personality_v0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <cstdio>
#include <cstdlib>
#include <vector>
#include <memory>
#include <iostream>
#include <cuda.h>
#include <curand.h>
#include <curand_kernel.h>
__device__ float generate(curandState* globalState, int ind)
{
curandState localState = globalState[ind];
float RANDOM = curand_uniform( &localState );
globalState[ind] = localState;
return RANDOM;
}
__global__ void setup_kernel ( curandState * state, unsigned long seed )
{
int id = threadIdx.x + blockIdx.x * blockDim.x;
curand_init ( seed, id, 0, &state[id] );
}
__global__ void addToCount(int N, int *y, curandState* globalState)
{
int id = threadIdx.x + blockIdx.x * blockDim.x;
while (id < N)
{
int number = generate(globalState, id) * 1000000;
printf("%i\n", number);
atomicAdd(&(y[0]), number);
id += blockDim.x * gridDim.x;
}
}
__device__ float3 generate3(curandState* globalState, int ind)
{
/*
generate random x, y, z position for particles
*/
float3 newposition = make_float3(0.0,0.0,0.0);
curandState localState = globalState[ind];
newposition.x = curand_uniform( &localState );
newposition.y = curand_uniform( &localState );
newposition.z = curand_uniform( &localState );
globalState[ind] = localState;
return newposition;
}
__global__ void initPosition(int N, float4 *d_par, curandState* globalState)
{
int id = threadIdx.x + blockIdx.x * blockDim.x;
if (id < N) // final block may not have all the threads
{
auto position = generate3(globalState, id);
d_par[id].w = (float) id / 1000.0; // mass
d_par[id].x = 2.0*position.x-1.0;
d_par[id].y = 2.0*position.y-1.0;
d_par[id].z = 2.0*position.z-1.0;
//id += blockDim.x * gridDim.x;
}
}
int main(int argc, char** argv)
{
int N = 768;
int *d_y;
float4 *d_par; // particle positions and mass
std::vector<int> y(N);
std::vector<float4> par(N);
int blocksize = 256; // value usually chosen by tuning and hardware constraints
int nblocks = ceil( (float) N/blocksize);
printf("nblocks = %i\n", nblocks);
cudaMalloc(&d_y, N * sizeof(int));
//cudaMemcpy(d_y, &y[0], N * sizeof(int), cudaMemcpyHostToDevice);
// allocate memory on device
cudaMalloc(&d_par, N * sizeof(float4));
curandState* devStates;
cudaMalloc (&devStates, N * sizeof(curandState));
//srand(time(0));
srand(1234);
/** ADD THESE TWO LINES **/
int seed = rand();
setup_kernel<<<nblocks, blocksize>>>(devStates,seed);
/** END ADDITION **/
addToCount<<<nblocks, blocksize>>>(N, d_y, devStates);
initPosition<<<nblocks, blocksize>>>(N, d_par, devStates);
cudaDeviceSynchronize();
cudaMemcpy(&y[0], d_y, N*sizeof(int), cudaMemcpyDeviceToHost);
//cudaMemcpy(y, d_y, N*sizeof(int), cudaMemcpyDeviceToHost);
cudaMemcpy(&par[0], d_par, N*sizeof(float4), cudaMemcpyDeviceToHost);
printf("final = %i\n", y[0]);
printf("# %i particles:\n", N);
for (auto particle : par) {
printf("%15.7f %15.7f %15.7f %15.7f\n", particle.w,
particle.x, particle.y, particle.z);
}
// Free the GPU memory here
cudaFree(d_y);
cudaFree(d_par);
cudaFree(devStates);
} | #include <cstdio>
#include <cstdlib>
#include <vector>
#include <memory>
#include <iostream>
#include <hip/hip_runtime.h>
#include <hiprand/hiprand.h>
#include <hiprand/hiprand_kernel.h>
__device__ float generate(hiprandState* globalState, int ind)
{
hiprandState localState = globalState[ind];
float RANDOM = hiprand_uniform( &localState );
globalState[ind] = localState;
return RANDOM;
}
__global__ void setup_kernel ( hiprandState * state, unsigned long seed )
{
int id = threadIdx.x + blockIdx.x * blockDim.x;
hiprand_init ( seed, id, 0, &state[id] );
}
__global__ void addToCount(int N, int *y, hiprandState* globalState)
{
int id = threadIdx.x + blockIdx.x * blockDim.x;
while (id < N)
{
int number = generate(globalState, id) * 1000000;
printf("%i\n", number);
atomicAdd(&(y[0]), number);
id += blockDim.x * gridDim.x;
}
}
__device__ float3 generate3(hiprandState* globalState, int ind)
{
/*
generate random x, y, z position for particles
*/
float3 newposition = make_float3(0.0,0.0,0.0);
hiprandState localState = globalState[ind];
newposition.x = hiprand_uniform( &localState );
newposition.y = hiprand_uniform( &localState );
newposition.z = hiprand_uniform( &localState );
globalState[ind] = localState;
return newposition;
}
__global__ void initPosition(int N, float4 *d_par, hiprandState* globalState)
{
int id = threadIdx.x + blockIdx.x * blockDim.x;
if (id < N) // final block may not have all the threads
{
auto position = generate3(globalState, id);
d_par[id].w = (float) id / 1000.0; // mass
d_par[id].x = 2.0*position.x-1.0;
d_par[id].y = 2.0*position.y-1.0;
d_par[id].z = 2.0*position.z-1.0;
//id += blockDim.x * gridDim.x;
}
}
int main(int argc, char** argv)
{
int N = 768;
int *d_y;
float4 *d_par; // particle positions and mass
std::vector<int> y(N);
std::vector<float4> par(N);
int blocksize = 256; // value usually chosen by tuning and hardware constraints
int nblocks = ceil( (float) N/blocksize);
printf("nblocks = %i\n", nblocks);
hipMalloc(&d_y, N * sizeof(int));
//cudaMemcpy(d_y, &y[0], N * sizeof(int), cudaMemcpyHostToDevice);
// allocate memory on device
hipMalloc(&d_par, N * sizeof(float4));
hiprandState* devStates;
hipMalloc (&devStates, N * sizeof(hiprandState));
//srand(time(0));
srand(1234);
/** ADD THESE TWO LINES **/
int seed = rand();
setup_kernel<<<nblocks, blocksize>>>(devStates,seed);
/** END ADDITION **/
addToCount<<<nblocks, blocksize>>>(N, d_y, devStates);
initPosition<<<nblocks, blocksize>>>(N, d_par, devStates);
hipDeviceSynchronize();
hipMemcpy(&y[0], d_y, N*sizeof(int), hipMemcpyDeviceToHost);
//cudaMemcpy(y, d_y, N*sizeof(int), cudaMemcpyDeviceToHost);
hipMemcpy(&par[0], d_par, N*sizeof(float4), hipMemcpyDeviceToHost);
printf("final = %i\n", y[0]);
printf("# %i particles:\n", N);
for (auto particle : par) {
printf("%15.7f %15.7f %15.7f %15.7f\n", particle.w,
particle.x, particle.y, particle.z);
}
// Free the GPU memory here
hipFree(d_y);
hipFree(d_par);
hipFree(devStates);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <cstdio>
#include <cstdlib>
#include <vector>
#include <memory>
#include <iostream>
#include <hip/hip_runtime.h>
#include <hiprand/hiprand.h>
#include <hiprand/hiprand_kernel.h>
__device__ float generate(hiprandState* globalState, int ind)
{
hiprandState localState = globalState[ind];
float RANDOM = hiprand_uniform( &localState );
globalState[ind] = localState;
return RANDOM;
}
__global__ void setup_kernel ( hiprandState * state, unsigned long seed )
{
int id = threadIdx.x + blockIdx.x * blockDim.x;
hiprand_init ( seed, id, 0, &state[id] );
}
__global__ void addToCount(int N, int *y, hiprandState* globalState)
{
int id = threadIdx.x + blockIdx.x * blockDim.x;
while (id < N)
{
int number = generate(globalState, id) * 1000000;
printf("%i\n", number);
atomicAdd(&(y[0]), number);
id += blockDim.x * gridDim.x;
}
}
__device__ float3 generate3(hiprandState* globalState, int ind)
{
/*
generate random x, y, z position for particles
*/
float3 newposition = make_float3(0.0,0.0,0.0);
hiprandState localState = globalState[ind];
newposition.x = hiprand_uniform( &localState );
newposition.y = hiprand_uniform( &localState );
newposition.z = hiprand_uniform( &localState );
globalState[ind] = localState;
return newposition;
}
__global__ void initPosition(int N, float4 *d_par, hiprandState* globalState)
{
int id = threadIdx.x + blockIdx.x * blockDim.x;
if (id < N) // final block may not have all the threads
{
auto position = generate3(globalState, id);
d_par[id].w = (float) id / 1000.0; // mass
d_par[id].x = 2.0*position.x-1.0;
d_par[id].y = 2.0*position.y-1.0;
d_par[id].z = 2.0*position.z-1.0;
//id += blockDim.x * gridDim.x;
}
}
int main(int argc, char** argv)
{
int N = 768;
int *d_y;
float4 *d_par; // particle positions and mass
std::vector<int> y(N);
std::vector<float4> par(N);
int blocksize = 256; // value usually chosen by tuning and hardware constraints
int nblocks = ceil( (float) N/blocksize);
printf("nblocks = %i\n", nblocks);
hipMalloc(&d_y, N * sizeof(int));
//cudaMemcpy(d_y, &y[0], N * sizeof(int), cudaMemcpyHostToDevice);
// allocate memory on device
hipMalloc(&d_par, N * sizeof(float4));
hiprandState* devStates;
hipMalloc (&devStates, N * sizeof(hiprandState));
//srand(time(0));
srand(1234);
/** ADD THESE TWO LINES **/
int seed = rand();
setup_kernel<<<nblocks, blocksize>>>(devStates,seed);
/** END ADDITION **/
addToCount<<<nblocks, blocksize>>>(N, d_y, devStates);
initPosition<<<nblocks, blocksize>>>(N, d_par, devStates);
hipDeviceSynchronize();
hipMemcpy(&y[0], d_y, N*sizeof(int), hipMemcpyDeviceToHost);
//cudaMemcpy(y, d_y, N*sizeof(int), cudaMemcpyDeviceToHost);
hipMemcpy(&par[0], d_par, N*sizeof(float4), hipMemcpyDeviceToHost);
printf("final = %i\n", y[0]);
printf("# %i particles:\n", N);
for (auto particle : par) {
printf("%15.7f %15.7f %15.7f %15.7f\n", particle.w,
particle.x, particle.y, particle.z);
}
// Free the GPU memory here
hipFree(d_y);
hipFree(d_par);
hipFree(devStates);
} | .text
.file "test4.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z27__device_stub__setup_kernelP12hiprandStatem # -- Begin function _Z27__device_stub__setup_kernelP12hiprandStatem
.p2align 4, 0x90
.type _Z27__device_stub__setup_kernelP12hiprandStatem,@function
_Z27__device_stub__setup_kernelP12hiprandStatem: # @_Z27__device_stub__setup_kernelP12hiprandStatem
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z12setup_kernelP12hiprandStatem, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z27__device_stub__setup_kernelP12hiprandStatem, .Lfunc_end0-_Z27__device_stub__setup_kernelP12hiprandStatem
.cfi_endproc
# -- End function
.globl _Z25__device_stub__addToCountiPiP12hiprandState # -- Begin function _Z25__device_stub__addToCountiPiP12hiprandState
.p2align 4, 0x90
.type _Z25__device_stub__addToCountiPiP12hiprandState,@function
_Z25__device_stub__addToCountiPiP12hiprandState: # @_Z25__device_stub__addToCountiPiP12hiprandState
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movl %edi, 12(%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 72(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10addToCountiPiP12hiprandState, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end1:
.size _Z25__device_stub__addToCountiPiP12hiprandState, .Lfunc_end1-_Z25__device_stub__addToCountiPiP12hiprandState
.cfi_endproc
# -- End function
.globl _Z27__device_stub__initPositioniP15HIP_vector_typeIfLj4EEP12hiprandState # -- Begin function _Z27__device_stub__initPositioniP15HIP_vector_typeIfLj4EEP12hiprandState
.p2align 4, 0x90
.type _Z27__device_stub__initPositioniP15HIP_vector_typeIfLj4EEP12hiprandState,@function
_Z27__device_stub__initPositioniP15HIP_vector_typeIfLj4EEP12hiprandState: # @_Z27__device_stub__initPositioniP15HIP_vector_typeIfLj4EEP12hiprandState
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movl %edi, 12(%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 72(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z12initPositioniP15HIP_vector_typeIfLj4EEP12hiprandState, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end2:
.size _Z27__device_stub__initPositioniP15HIP_vector_typeIfLj4EEP12hiprandState, .Lfunc_end2-_Z27__device_stub__initPositioniP15HIP_vector_typeIfLj4EEP12hiprandState
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.Lfunc_begin0:
.cfi_startproc
.cfi_personality 3, __gxx_personality_v0
.cfi_lsda 3, .Lexception0
# %bb.0: # %_ZNSt6vectorIiSaIiEEC2EmRKS0_.exit
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $120, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
.cfi_escape 0x2e, 0x00
movl $3072, %edi # imm = 0xC00
callq _Znwm
movq %rax, %rbx
.cfi_escape 0x2e, 0x00
movl $3072, %edx # imm = 0xC00
movq %rax, %rdi
xorl %esi, %esi
callq memset@PLT
.Ltmp0:
.cfi_escape 0x2e, 0x00
movl $12288, %edi # imm = 0x3000
callq _Znwm
.Ltmp1:
# %bb.1: # %_ZNSt6vectorI15HIP_vector_typeIfLj4EESaIS1_EEC2EmRKS2_.exit
movq %rax, %r14
.cfi_escape 0x2e, 0x00
movl $12288, %edx # imm = 0x3000
movq %rax, %rdi
xorl %esi, %esi
callq memset@PLT
.cfi_escape 0x2e, 0x00
movl $.L.str, %edi
movl $3, %esi
xorl %eax, %eax
callq printf
.Ltmp3:
.cfi_escape 0x2e, 0x00
leaq 88(%rsp), %rdi
movl $3072, %esi # imm = 0xC00
callq hipMalloc
.Ltmp4:
# %bb.2: # %_ZL9hipMallocIiE10hipError_tPPT_m.exit
.Ltmp5:
.cfi_escape 0x2e, 0x00
leaq 80(%rsp), %rdi
movl $12288, %esi # imm = 0x3000
callq hipMalloc
.Ltmp6:
# %bb.3: # %_ZL9hipMallocI15HIP_vector_typeIfLj4EEE10hipError_tPPT_m.exit
.Ltmp8:
.cfi_escape 0x2e, 0x00
leaq 72(%rsp), %rdi
movl $36864, %esi # imm = 0x9000
callq hipMalloc
.Ltmp9:
# %bb.4: # %_ZL9hipMallocI12hiprandStateE10hipError_tPPT_m.exit
.cfi_escape 0x2e, 0x00
movl $1234, %edi # imm = 0x4D2
callq srand
.cfi_escape 0x2e, 0x00
callq rand
movl %eax, %ebp
.Ltmp11:
.cfi_escape 0x2e, 0x00
movabsq $4294967299, %rdi # imm = 0x100000003
movabsq $4294967552, %rdx # imm = 0x100000100
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
.Ltmp12:
# %bb.5:
testl %eax, %eax
jne .LBB3_8
# %bb.6:
movq 72(%rsp), %rax
movslq %ebp, %rcx
movq %rax, 64(%rsp)
movq %rcx, 56(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 56(%rsp), %rax
movq %rax, 104(%rsp)
.Ltmp13:
.cfi_escape 0x2e, 0x00
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
.Ltmp14:
# %bb.7: # %.noexc
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
.Ltmp15:
.cfi_escape 0x2e, 0x10
leaq 96(%rsp), %r9
movl $_Z12setup_kernelP12hiprandStatem, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.Ltmp16:
.LBB3_8:
.Ltmp17:
.cfi_escape 0x2e, 0x00
movabsq $4294967299, %rdi # imm = 0x100000003
movabsq $4294967552, %rdx # imm = 0x100000100
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
.Ltmp18:
# %bb.9:
testl %eax, %eax
jne .LBB3_12
# %bb.10:
movq 88(%rsp), %rax
movq 72(%rsp), %rcx
movl $768, 4(%rsp) # imm = 0x300
movq %rax, 64(%rsp)
movq %rcx, 56(%rsp)
leaq 4(%rsp), %rax
movq %rax, 96(%rsp)
leaq 64(%rsp), %rax
movq %rax, 104(%rsp)
leaq 56(%rsp), %rax
movq %rax, 112(%rsp)
.Ltmp19:
.cfi_escape 0x2e, 0x00
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
.Ltmp20:
# %bb.11: # %.noexc52
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
.Ltmp21:
.cfi_escape 0x2e, 0x10
leaq 96(%rsp), %r9
movl $_Z10addToCountiPiP12hiprandState, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.Ltmp22:
.LBB3_12:
.Ltmp23:
.cfi_escape 0x2e, 0x00
movabsq $4294967299, %rdi # imm = 0x100000003
movabsq $4294967552, %rdx # imm = 0x100000100
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
.Ltmp24:
# %bb.13:
testl %eax, %eax
jne .LBB3_16
# %bb.14:
movq 80(%rsp), %rax
movq 72(%rsp), %rcx
movl $768, 4(%rsp) # imm = 0x300
movq %rax, 64(%rsp)
movq %rcx, 56(%rsp)
leaq 4(%rsp), %rax
movq %rax, 96(%rsp)
leaq 64(%rsp), %rax
movq %rax, 104(%rsp)
leaq 56(%rsp), %rax
movq %rax, 112(%rsp)
.Ltmp25:
.cfi_escape 0x2e, 0x00
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
.Ltmp26:
# %bb.15: # %.noexc60
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
.Ltmp27:
.cfi_escape 0x2e, 0x10
leaq 96(%rsp), %r9
movl $_Z12initPositioniP15HIP_vector_typeIfLj4EEP12hiprandState, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.Ltmp28:
.LBB3_16:
.Ltmp29:
.cfi_escape 0x2e, 0x00
callq hipDeviceSynchronize
.Ltmp30:
# %bb.17:
movq 88(%rsp), %rsi
.Ltmp31:
.cfi_escape 0x2e, 0x00
movl $3072, %edx # imm = 0xC00
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
.Ltmp32:
# %bb.18:
movq 80(%rsp), %rsi
.Ltmp33:
.cfi_escape 0x2e, 0x00
movl $12288, %edx # imm = 0x3000
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
.Ltmp34:
# %bb.19:
movl (%rbx), %esi
.cfi_escape 0x2e, 0x00
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
.cfi_escape 0x2e, 0x00
movl $.L.str.2, %edi
movl $768, %esi # imm = 0x300
xorl %eax, %eax
callq printf
movl $12, %r15d
.p2align 4, 0x90
.LBB3_20: # =>This Inner Loop Header: Depth=1
movss -12(%r14,%r15), %xmm1 # xmm1 = mem[0],zero,zero,zero
movss -8(%r14,%r15), %xmm2 # xmm2 = mem[0],zero,zero,zero
movss -4(%r14,%r15), %xmm3 # xmm3 = mem[0],zero,zero,zero
movss (%r14,%r15), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
cvtss2sd %xmm1, %xmm1
cvtss2sd %xmm2, %xmm2
cvtss2sd %xmm3, %xmm3
.cfi_escape 0x2e, 0x00
movl $.L.str.3, %edi
movb $4, %al
callq printf
addq $16, %r15
cmpq $12300, %r15 # imm = 0x300C
jne .LBB3_20
# %bb.21:
movq 88(%rsp), %rdi
.Ltmp35:
.cfi_escape 0x2e, 0x00
callq hipFree
.Ltmp36:
# %bb.22:
movq 80(%rsp), %rdi
.Ltmp37:
.cfi_escape 0x2e, 0x00
callq hipFree
.Ltmp38:
# %bb.23:
movq 72(%rsp), %rdi
.Ltmp39:
.cfi_escape 0x2e, 0x00
callq hipFree
.Ltmp40:
# %bb.24: # %_ZNSt6vectorI15HIP_vector_typeIfLj4EESaIS1_EED2Ev.exit
.cfi_escape 0x2e, 0x00
movq %r14, %rdi
callq _ZdlPv
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
callq _ZdlPv
xorl %eax, %eax
addq $120, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB3_28:
.cfi_def_cfa_offset 160
.Ltmp10:
jmp .LBB3_29
.LBB3_25:
.Ltmp2:
movq %rax, %r15
jmp .LBB3_30
.LBB3_26:
.Ltmp7:
jmp .LBB3_29
.LBB3_27:
.Ltmp41:
.LBB3_29: # %_ZNSt6vectorI15HIP_vector_typeIfLj4EESaIS1_EED2Ev.exit64
movq %rax, %r15
.cfi_escape 0x2e, 0x00
movq %r14, %rdi
callq _ZdlPv
.LBB3_30: # %_ZNSt6vectorIiSaIiEED2Ev.exit66
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
callq _ZdlPv
.cfi_escape 0x2e, 0x00
movq %r15, %rdi
callq _Unwind_Resume@PLT
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
.section .gcc_except_table,"a",@progbits
.p2align 2, 0x0
GCC_except_table3:
.Lexception0:
.byte 255 # @LPStart Encoding = omit
.byte 255 # @TType Encoding = omit
.byte 1 # Call site Encoding = uleb128
.uleb128 .Lcst_end0-.Lcst_begin0
.Lcst_begin0:
.uleb128 .Lfunc_begin0-.Lfunc_begin0 # >> Call Site 1 <<
.uleb128 .Ltmp0-.Lfunc_begin0 # Call between .Lfunc_begin0 and .Ltmp0
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp0-.Lfunc_begin0 # >> Call Site 2 <<
.uleb128 .Ltmp1-.Ltmp0 # Call between .Ltmp0 and .Ltmp1
.uleb128 .Ltmp2-.Lfunc_begin0 # jumps to .Ltmp2
.byte 0 # On action: cleanup
.uleb128 .Ltmp1-.Lfunc_begin0 # >> Call Site 3 <<
.uleb128 .Ltmp3-.Ltmp1 # Call between .Ltmp1 and .Ltmp3
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp3-.Lfunc_begin0 # >> Call Site 4 <<
.uleb128 .Ltmp6-.Ltmp3 # Call between .Ltmp3 and .Ltmp6
.uleb128 .Ltmp7-.Lfunc_begin0 # jumps to .Ltmp7
.byte 0 # On action: cleanup
.uleb128 .Ltmp8-.Lfunc_begin0 # >> Call Site 5 <<
.uleb128 .Ltmp9-.Ltmp8 # Call between .Ltmp8 and .Ltmp9
.uleb128 .Ltmp10-.Lfunc_begin0 # jumps to .Ltmp10
.byte 0 # On action: cleanup
.uleb128 .Ltmp11-.Lfunc_begin0 # >> Call Site 6 <<
.uleb128 .Ltmp40-.Ltmp11 # Call between .Ltmp11 and .Ltmp40
.uleb128 .Ltmp41-.Lfunc_begin0 # jumps to .Ltmp41
.byte 0 # On action: cleanup
.uleb128 .Ltmp40-.Lfunc_begin0 # >> Call Site 7 <<
.uleb128 .Lfunc_end3-.Ltmp40 # Call between .Ltmp40 and .Lfunc_end3
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.Lcst_end0:
.p2align 2, 0x0
# -- End function
.text
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12setup_kernelP12hiprandStatem, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10addToCountiPiP12hiprandState, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12initPositioniP15HIP_vector_typeIfLj4EEP12hiprandState, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z12setup_kernelP12hiprandStatem,@object # @_Z12setup_kernelP12hiprandStatem
.section .rodata,"a",@progbits
.globl _Z12setup_kernelP12hiprandStatem
.p2align 3, 0x0
_Z12setup_kernelP12hiprandStatem:
.quad _Z27__device_stub__setup_kernelP12hiprandStatem
.size _Z12setup_kernelP12hiprandStatem, 8
.type _Z10addToCountiPiP12hiprandState,@object # @_Z10addToCountiPiP12hiprandState
.globl _Z10addToCountiPiP12hiprandState
.p2align 3, 0x0
_Z10addToCountiPiP12hiprandState:
.quad _Z25__device_stub__addToCountiPiP12hiprandState
.size _Z10addToCountiPiP12hiprandState, 8
.type _Z12initPositioniP15HIP_vector_typeIfLj4EEP12hiprandState,@object # @_Z12initPositioniP15HIP_vector_typeIfLj4EEP12hiprandState
.globl _Z12initPositioniP15HIP_vector_typeIfLj4EEP12hiprandState
.p2align 3, 0x0
_Z12initPositioniP15HIP_vector_typeIfLj4EEP12hiprandState:
.quad _Z27__device_stub__initPositioniP15HIP_vector_typeIfLj4EEP12hiprandState
.size _Z12initPositioniP15HIP_vector_typeIfLj4EEP12hiprandState, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "nblocks = %i\n"
.size .L.str, 14
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "final = %i\n"
.size .L.str.1, 12
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "# %i particles:\n"
.size .L.str.2, 17
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "%15.7f %15.7f %15.7f %15.7f\n"
.size .L.str.3, 29
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z12setup_kernelP12hiprandStatem"
.size .L__unnamed_1, 33
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z10addToCountiPiP12hiprandState"
.size .L__unnamed_2, 33
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z12initPositioniP15HIP_vector_typeIfLj4EEP12hiprandState"
.size .L__unnamed_3, 58
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__setup_kernelP12hiprandStatem
.addrsig_sym _Z25__device_stub__addToCountiPiP12hiprandState
.addrsig_sym _Z27__device_stub__initPositioniP15HIP_vector_typeIfLj4EEP12hiprandState
.addrsig_sym __gxx_personality_v0
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Unwind_Resume
.addrsig_sym _Z12setup_kernelP12hiprandStatem
.addrsig_sym _Z10addToCountiPiP12hiprandState
.addrsig_sym _Z12initPositioniP15HIP_vector_typeIfLj4EEP12hiprandState
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0010659a_00000000-6_test4.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB4838:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4838:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z8generateP17curandStateXORWOWi
.type _Z8generateP17curandStateXORWOWi, @function
_Z8generateP17curandStateXORWOWi:
.LFB4833:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE4833:
.size _Z8generateP17curandStateXORWOWi, .-_Z8generateP17curandStateXORWOWi
.globl _Z9generate3P17curandStateXORWOWi
.type _Z9generate3P17curandStateXORWOWi, @function
_Z9generate3P17curandStateXORWOWi:
.LFB4834:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE4834:
.size _Z9generate3P17curandStateXORWOWi, .-_Z9generate3P17curandStateXORWOWi
.globl _Z51__device_stub__Z12setup_kernelP17curandStateXORWOWmP17curandStateXORWOWm
.type _Z51__device_stub__Z12setup_kernelP17curandStateXORWOWmP17curandStateXORWOWm, @function
_Z51__device_stub__Z12setup_kernelP17curandStateXORWOWmP17curandStateXORWOWm:
.LFB4860:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L11
.L7:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L12
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z12setup_kernelP17curandStateXORWOWm(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L7
.L12:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4860:
.size _Z51__device_stub__Z12setup_kernelP17curandStateXORWOWmP17curandStateXORWOWm, .-_Z51__device_stub__Z12setup_kernelP17curandStateXORWOWmP17curandStateXORWOWm
.globl _Z12setup_kernelP17curandStateXORWOWm
.type _Z12setup_kernelP17curandStateXORWOWm, @function
_Z12setup_kernelP17curandStateXORWOWm:
.LFB4861:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z51__device_stub__Z12setup_kernelP17curandStateXORWOWmP17curandStateXORWOWm
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4861:
.size _Z12setup_kernelP17curandStateXORWOWm, .-_Z12setup_kernelP17curandStateXORWOWm
.globl _Z51__device_stub__Z10addToCountiPiP17curandStateXORWOWiPiP17curandStateXORWOW
.type _Z51__device_stub__Z10addToCountiPiP17curandStateXORWOWiPiP17curandStateXORWOW, @function
_Z51__device_stub__Z10addToCountiPiP17curandStateXORWOWiPiP17curandStateXORWOW:
.LFB4862:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movl %edi, 28(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L19
.L15:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L20
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z10addToCountiPiP17curandStateXORWOW(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L15
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4862:
.size _Z51__device_stub__Z10addToCountiPiP17curandStateXORWOWiPiP17curandStateXORWOW, .-_Z51__device_stub__Z10addToCountiPiP17curandStateXORWOWiPiP17curandStateXORWOW
.globl _Z10addToCountiPiP17curandStateXORWOW
.type _Z10addToCountiPiP17curandStateXORWOW, @function
_Z10addToCountiPiP17curandStateXORWOW:
.LFB4863:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z51__device_stub__Z10addToCountiPiP17curandStateXORWOWiPiP17curandStateXORWOW
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4863:
.size _Z10addToCountiPiP17curandStateXORWOW, .-_Z10addToCountiPiP17curandStateXORWOW
.globl _Z59__device_stub__Z12initPositioniP6float4P17curandStateXORWOWiP6float4P17curandStateXORWOW
.type _Z59__device_stub__Z12initPositioniP6float4P17curandStateXORWOWiP6float4P17curandStateXORWOW, @function
_Z59__device_stub__Z12initPositioniP6float4P17curandStateXORWOWiP6float4P17curandStateXORWOW:
.LFB4864:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movl %edi, 28(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L27
.L23:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L28
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L27:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z12initPositioniP6float4P17curandStateXORWOW(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L23
.L28:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4864:
.size _Z59__device_stub__Z12initPositioniP6float4P17curandStateXORWOWiP6float4P17curandStateXORWOW, .-_Z59__device_stub__Z12initPositioniP6float4P17curandStateXORWOWiP6float4P17curandStateXORWOW
.globl _Z12initPositioniP6float4P17curandStateXORWOW
.type _Z12initPositioniP6float4P17curandStateXORWOW, @function
_Z12initPositioniP6float4P17curandStateXORWOW:
.LFB4865:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z59__device_stub__Z12initPositioniP6float4P17curandStateXORWOWiP6float4P17curandStateXORWOW
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4865:
.size _Z12initPositioniP6float4P17curandStateXORWOW, .-_Z12initPositioniP6float4P17curandStateXORWOW
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z12initPositioniP6float4P17curandStateXORWOW"
.align 8
.LC1:
.string "_Z10addToCountiPiP17curandStateXORWOW"
.align 8
.LC2:
.string "_Z12setup_kernelP17curandStateXORWOWm"
.section .rodata.str1.1,"aMS",@progbits,1
.LC3:
.string "precalc_xorwow_matrix"
.LC4:
.string "precalc_xorwow_offset_matrix"
.LC5:
.string "mrg32k3aM1"
.LC6:
.string "mrg32k3aM2"
.LC7:
.string "mrg32k3aM1SubSeq"
.LC8:
.string "mrg32k3aM2SubSeq"
.LC9:
.string "mrg32k3aM1Seq"
.LC10:
.string "mrg32k3aM2Seq"
.LC11:
.string "__cr_lgamma_table"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB4867:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z12initPositioniP6float4P17curandStateXORWOW(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z10addToCountiPiP17curandStateXORWOW(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z12setup_kernelP17curandStateXORWOWm(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $102400, %r9d
movl $0, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _ZL21precalc_xorwow_matrix(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $102400, %r9d
movl $0, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _ZL28precalc_xorwow_offset_matrix(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _ZL10mrg32k3aM1(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _ZL10mrg32k3aM2(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2016, %r9d
movl $0, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _ZL16mrg32k3aM1SubSeq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2016, %r9d
movl $0, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _ZL16mrg32k3aM2SubSeq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _ZL13mrg32k3aM1Seq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC10(%rip), %rdx
movq %rdx, %rcx
leaq _ZL13mrg32k3aM2Seq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $72, %r9d
movl $0, %r8d
leaq .LC11(%rip), %rdx
movq %rdx, %rcx
leaq _ZL17__cr_lgamma_table(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4867:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .text._ZNSt6vectorIiSaIiEED2Ev,"axG",@progbits,_ZNSt6vectorIiSaIiEED5Ev,comdat
.align 2
.weak _ZNSt6vectorIiSaIiEED2Ev
.type _ZNSt6vectorIiSaIiEED2Ev, @function
_ZNSt6vectorIiSaIiEED2Ev:
.LFB5182:
.cfi_startproc
endbr64
movq (%rdi), %rax
testq %rax, %rax
je .L36
subq $8, %rsp
.cfi_def_cfa_offset 16
movq 16(%rdi), %rsi
subq %rax, %rsi
movq %rax, %rdi
call _ZdlPvm@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.L36:
ret
.cfi_endproc
.LFE5182:
.size _ZNSt6vectorIiSaIiEED2Ev, .-_ZNSt6vectorIiSaIiEED2Ev
.weak _ZNSt6vectorIiSaIiEED1Ev
.set _ZNSt6vectorIiSaIiEED1Ev,_ZNSt6vectorIiSaIiEED2Ev
.section .text._ZNSt6vectorI6float4SaIS0_EED2Ev,"axG",@progbits,_ZNSt6vectorI6float4SaIS0_EED5Ev,comdat
.align 2
.weak _ZNSt6vectorI6float4SaIS0_EED2Ev
.type _ZNSt6vectorI6float4SaIS0_EED2Ev, @function
_ZNSt6vectorI6float4SaIS0_EED2Ev:
.LFB5194:
.cfi_startproc
endbr64
movq (%rdi), %rax
testq %rax, %rax
je .L42
subq $8, %rsp
.cfi_def_cfa_offset 16
movq 16(%rdi), %rsi
subq %rax, %rsi
movq %rax, %rdi
call _ZdlPvm@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.L42:
ret
.cfi_endproc
.LFE5194:
.size _ZNSt6vectorI6float4SaIS0_EED2Ev, .-_ZNSt6vectorI6float4SaIS0_EED2Ev
.weak _ZNSt6vectorI6float4SaIS0_EED1Ev
.set _ZNSt6vectorI6float4SaIS0_EED1Ev,_ZNSt6vectorI6float4SaIS0_EED2Ev
.section .rodata.str1.1
.LC13:
.string "nblocks = %i\n"
.LC14:
.string "final = %i\n"
.LC15:
.string "# %i particles:\n"
.LC16:
.string "%15.7f %15.7f %15.7f %15.7f\n"
.text
.globl main
.type main, @function
main:
.LFB4835:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA4835
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $112, %rsp
.cfi_def_cfa_offset 144
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
movl $3072, %edi
.LEHB0:
call _Znwm@PLT
.LEHE0:
movq %rax, %rbx
movq %rax, 48(%rsp)
leaq 3072(%rax), %rdx
movq %rdx, 64(%rsp)
movl $0, (%rax)
leaq 4(%rax), %rax
.L46:
movl $0, (%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L46
movq %rdx, 56(%rsp)
movq $0, 88(%rsp)
movq $0, 96(%rsp)
movl $12288, %edi
.LEHB1:
call _Znwm@PLT
.LEHE1:
movq %rax, %rbp
movq %rax, 80(%rsp)
leaq 12288(%rax), %rdx
movq %rdx, 96(%rsp)
movl $0x00000000, (%rax)
movl $0x00000000, 4(%rax)
movl $0x00000000, 8(%rax)
movl $0x00000000, 12(%rax)
leaq 16(%rax), %rax
.L47:
movdqa 0(%rbp), %xmm4
movaps %xmm4, (%rax)
addq $16, %rax
cmpq %rax, %rdx
jne .L47
movq %rdx, 88(%rsp)
movl $3, %edx
leaq .LC13(%rip), %rsi
movl $2, %edi
movl $0, %eax
.LEHB2:
call __printf_chk@PLT
movq %rsp, %rdi
movl $3072, %esi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movl $12288, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $36864, %esi
call cudaMalloc@PLT
movl $1234, %edi
call srand@PLT
call rand@PLT
movl %eax, %r12d
movl $256, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $3, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L48
movslq %r12d, %rsi
movq 16(%rsp), %rdi
call _Z51__device_stub__Z12setup_kernelP17curandStateXORWOWmP17curandStateXORWOWm
.L48:
movl $256, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $3, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L49
movq 16(%rsp), %rdx
movq (%rsp), %rsi
movl $768, %edi
call _Z51__device_stub__Z10addToCountiPiP17curandStateXORWOWiPiP17curandStateXORWOW
.L49:
movl $256, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $3, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L50
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
movl $768, %edi
call _Z59__device_stub__Z12initPositioniP6float4P17curandStateXORWOWiP6float4P17curandStateXORWOW
.L50:
call cudaDeviceSynchronize@PLT
movl $2, %ecx
movl $3072, %edx
movq (%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movl $2, %ecx
movl $12288, %edx
movq 8(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
movl (%rbx), %edx
leaq .LC14(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $768, %edx
leaq .LC15(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rbp, %rbx
addq $12288, %rbp
leaq .LC16(%rip), %r12
jmp .L51
.L64:
addq $16, %rbx
cmpq %rbx, %rbp
je .L63
.L51:
pxor %xmm0, %xmm0
cvtss2sd 12(%rbx), %xmm0
pxor %xmm3, %xmm3
cvtss2sd 8(%rbx), %xmm3
pxor %xmm2, %xmm2
cvtss2sd 4(%rbx), %xmm2
pxor %xmm1, %xmm1
cvtss2sd (%rbx), %xmm1
movq %r12, %rsi
movl $2, %edi
movl $4, %eax
call __printf_chk@PLT
jmp .L64
.L63:
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
.LEHE2:
leaq 80(%rsp), %rdi
call _ZNSt6vectorI6float4SaIS0_EED1Ev
leaq 48(%rsp), %rdi
call _ZNSt6vectorIiSaIiEED1Ev
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L65
movl $0, %eax
addq $112, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L57:
.cfi_restore_state
endbr64
movq %rax, %rbx
leaq 80(%rsp), %rdi
call _ZNSt6vectorI6float4SaIS0_EED1Ev
.L53:
leaq 48(%rsp), %rdi
call _ZNSt6vectorIiSaIiEED1Ev
movq 104(%rsp), %rax
subq %fs:40, %rax
je .L54
call __stack_chk_fail@PLT
.L56:
endbr64
movq %rax, %rbx
jmp .L53
.L54:
movq %rbx, %rdi
.LEHB3:
call _Unwind_Resume@PLT
.LEHE3:
.L65:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4835:
.globl __gxx_personality_v0
.section .gcc_except_table,"a",@progbits
.LLSDA4835:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE4835-.LLSDACSB4835
.LLSDACSB4835:
.uleb128 .LEHB0-.LFB4835
.uleb128 .LEHE0-.LEHB0
.uleb128 0
.uleb128 0
.uleb128 .LEHB1-.LFB4835
.uleb128 .LEHE1-.LEHB1
.uleb128 .L56-.LFB4835
.uleb128 0
.uleb128 .LEHB2-.LFB4835
.uleb128 .LEHE2-.LEHB2
.uleb128 .L57-.LFB4835
.uleb128 0
.uleb128 .LEHB3-.LFB4835
.uleb128 .LEHE3-.LEHB3
.uleb128 0
.uleb128 0
.LLSDACSE4835:
.text
.size main, .-main
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL17__cr_lgamma_table
.comm _ZL17__cr_lgamma_table,72,32
.local _ZL13mrg32k3aM2Seq
.comm _ZL13mrg32k3aM2Seq,2304,32
.local _ZL13mrg32k3aM1Seq
.comm _ZL13mrg32k3aM1Seq,2304,32
.local _ZL16mrg32k3aM2SubSeq
.comm _ZL16mrg32k3aM2SubSeq,2016,32
.local _ZL16mrg32k3aM1SubSeq
.comm _ZL16mrg32k3aM1SubSeq,2016,32
.local _ZL10mrg32k3aM2
.comm _ZL10mrg32k3aM2,2304,32
.local _ZL10mrg32k3aM1
.comm _ZL10mrg32k3aM1,2304,32
.local _ZL28precalc_xorwow_offset_matrix
.comm _ZL28precalc_xorwow_offset_matrix,102400,32
.local _ZL21precalc_xorwow_matrix
.comm _ZL21precalc_xorwow_matrix,102400,32
.hidden DW.ref.__gxx_personality_v0
.weak DW.ref.__gxx_personality_v0
.section .data.rel.local.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat
.align 8
.type DW.ref.__gxx_personality_v0, @object
.size DW.ref.__gxx_personality_v0, 8
DW.ref.__gxx_personality_v0:
.quad __gxx_personality_v0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "test4.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z27__device_stub__setup_kernelP12hiprandStatem # -- Begin function _Z27__device_stub__setup_kernelP12hiprandStatem
.p2align 4, 0x90
.type _Z27__device_stub__setup_kernelP12hiprandStatem,@function
_Z27__device_stub__setup_kernelP12hiprandStatem: # @_Z27__device_stub__setup_kernelP12hiprandStatem
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z12setup_kernelP12hiprandStatem, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z27__device_stub__setup_kernelP12hiprandStatem, .Lfunc_end0-_Z27__device_stub__setup_kernelP12hiprandStatem
.cfi_endproc
# -- End function
.globl _Z25__device_stub__addToCountiPiP12hiprandState # -- Begin function _Z25__device_stub__addToCountiPiP12hiprandState
.p2align 4, 0x90
.type _Z25__device_stub__addToCountiPiP12hiprandState,@function
_Z25__device_stub__addToCountiPiP12hiprandState: # @_Z25__device_stub__addToCountiPiP12hiprandState
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movl %edi, 12(%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 72(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10addToCountiPiP12hiprandState, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end1:
.size _Z25__device_stub__addToCountiPiP12hiprandState, .Lfunc_end1-_Z25__device_stub__addToCountiPiP12hiprandState
.cfi_endproc
# -- End function
.globl _Z27__device_stub__initPositioniP15HIP_vector_typeIfLj4EEP12hiprandState # -- Begin function _Z27__device_stub__initPositioniP15HIP_vector_typeIfLj4EEP12hiprandState
.p2align 4, 0x90
.type _Z27__device_stub__initPositioniP15HIP_vector_typeIfLj4EEP12hiprandState,@function
_Z27__device_stub__initPositioniP15HIP_vector_typeIfLj4EEP12hiprandState: # @_Z27__device_stub__initPositioniP15HIP_vector_typeIfLj4EEP12hiprandState
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movl %edi, 12(%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 72(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z12initPositioniP15HIP_vector_typeIfLj4EEP12hiprandState, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end2:
.size _Z27__device_stub__initPositioniP15HIP_vector_typeIfLj4EEP12hiprandState, .Lfunc_end2-_Z27__device_stub__initPositioniP15HIP_vector_typeIfLj4EEP12hiprandState
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.Lfunc_begin0:
.cfi_startproc
.cfi_personality 3, __gxx_personality_v0
.cfi_lsda 3, .Lexception0
# %bb.0: # %_ZNSt6vectorIiSaIiEEC2EmRKS0_.exit
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $120, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
.cfi_escape 0x2e, 0x00
movl $3072, %edi # imm = 0xC00
callq _Znwm
movq %rax, %rbx
.cfi_escape 0x2e, 0x00
movl $3072, %edx # imm = 0xC00
movq %rax, %rdi
xorl %esi, %esi
callq memset@PLT
.Ltmp0:
.cfi_escape 0x2e, 0x00
movl $12288, %edi # imm = 0x3000
callq _Znwm
.Ltmp1:
# %bb.1: # %_ZNSt6vectorI15HIP_vector_typeIfLj4EESaIS1_EEC2EmRKS2_.exit
movq %rax, %r14
.cfi_escape 0x2e, 0x00
movl $12288, %edx # imm = 0x3000
movq %rax, %rdi
xorl %esi, %esi
callq memset@PLT
.cfi_escape 0x2e, 0x00
movl $.L.str, %edi
movl $3, %esi
xorl %eax, %eax
callq printf
.Ltmp3:
.cfi_escape 0x2e, 0x00
leaq 88(%rsp), %rdi
movl $3072, %esi # imm = 0xC00
callq hipMalloc
.Ltmp4:
# %bb.2: # %_ZL9hipMallocIiE10hipError_tPPT_m.exit
.Ltmp5:
.cfi_escape 0x2e, 0x00
leaq 80(%rsp), %rdi
movl $12288, %esi # imm = 0x3000
callq hipMalloc
.Ltmp6:
# %bb.3: # %_ZL9hipMallocI15HIP_vector_typeIfLj4EEE10hipError_tPPT_m.exit
.Ltmp8:
.cfi_escape 0x2e, 0x00
leaq 72(%rsp), %rdi
movl $36864, %esi # imm = 0x9000
callq hipMalloc
.Ltmp9:
# %bb.4: # %_ZL9hipMallocI12hiprandStateE10hipError_tPPT_m.exit
.cfi_escape 0x2e, 0x00
movl $1234, %edi # imm = 0x4D2
callq srand
.cfi_escape 0x2e, 0x00
callq rand
movl %eax, %ebp
.Ltmp11:
.cfi_escape 0x2e, 0x00
movabsq $4294967299, %rdi # imm = 0x100000003
movabsq $4294967552, %rdx # imm = 0x100000100
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
.Ltmp12:
# %bb.5:
testl %eax, %eax
jne .LBB3_8
# %bb.6:
movq 72(%rsp), %rax
movslq %ebp, %rcx
movq %rax, 64(%rsp)
movq %rcx, 56(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 56(%rsp), %rax
movq %rax, 104(%rsp)
.Ltmp13:
.cfi_escape 0x2e, 0x00
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
.Ltmp14:
# %bb.7: # %.noexc
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
.Ltmp15:
.cfi_escape 0x2e, 0x10
leaq 96(%rsp), %r9
movl $_Z12setup_kernelP12hiprandStatem, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.Ltmp16:
.LBB3_8:
.Ltmp17:
.cfi_escape 0x2e, 0x00
movabsq $4294967299, %rdi # imm = 0x100000003
movabsq $4294967552, %rdx # imm = 0x100000100
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
.Ltmp18:
# %bb.9:
testl %eax, %eax
jne .LBB3_12
# %bb.10:
movq 88(%rsp), %rax
movq 72(%rsp), %rcx
movl $768, 4(%rsp) # imm = 0x300
movq %rax, 64(%rsp)
movq %rcx, 56(%rsp)
leaq 4(%rsp), %rax
movq %rax, 96(%rsp)
leaq 64(%rsp), %rax
movq %rax, 104(%rsp)
leaq 56(%rsp), %rax
movq %rax, 112(%rsp)
.Ltmp19:
.cfi_escape 0x2e, 0x00
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
.Ltmp20:
# %bb.11: # %.noexc52
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
.Ltmp21:
.cfi_escape 0x2e, 0x10
leaq 96(%rsp), %r9
movl $_Z10addToCountiPiP12hiprandState, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.Ltmp22:
.LBB3_12:
.Ltmp23:
.cfi_escape 0x2e, 0x00
movabsq $4294967299, %rdi # imm = 0x100000003
movabsq $4294967552, %rdx # imm = 0x100000100
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
.Ltmp24:
# %bb.13:
testl %eax, %eax
jne .LBB3_16
# %bb.14:
movq 80(%rsp), %rax
movq 72(%rsp), %rcx
movl $768, 4(%rsp) # imm = 0x300
movq %rax, 64(%rsp)
movq %rcx, 56(%rsp)
leaq 4(%rsp), %rax
movq %rax, 96(%rsp)
leaq 64(%rsp), %rax
movq %rax, 104(%rsp)
leaq 56(%rsp), %rax
movq %rax, 112(%rsp)
.Ltmp25:
.cfi_escape 0x2e, 0x00
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
.Ltmp26:
# %bb.15: # %.noexc60
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
.Ltmp27:
.cfi_escape 0x2e, 0x10
leaq 96(%rsp), %r9
movl $_Z12initPositioniP15HIP_vector_typeIfLj4EEP12hiprandState, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.Ltmp28:
.LBB3_16:
.Ltmp29:
.cfi_escape 0x2e, 0x00
callq hipDeviceSynchronize
.Ltmp30:
# %bb.17:
movq 88(%rsp), %rsi
.Ltmp31:
.cfi_escape 0x2e, 0x00
movl $3072, %edx # imm = 0xC00
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
.Ltmp32:
# %bb.18:
movq 80(%rsp), %rsi
.Ltmp33:
.cfi_escape 0x2e, 0x00
movl $12288, %edx # imm = 0x3000
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
.Ltmp34:
# %bb.19:
movl (%rbx), %esi
.cfi_escape 0x2e, 0x00
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
.cfi_escape 0x2e, 0x00
movl $.L.str.2, %edi
movl $768, %esi # imm = 0x300
xorl %eax, %eax
callq printf
movl $12, %r15d
.p2align 4, 0x90
.LBB3_20: # =>This Inner Loop Header: Depth=1
movss -12(%r14,%r15), %xmm1 # xmm1 = mem[0],zero,zero,zero
movss -8(%r14,%r15), %xmm2 # xmm2 = mem[0],zero,zero,zero
movss -4(%r14,%r15), %xmm3 # xmm3 = mem[0],zero,zero,zero
movss (%r14,%r15), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
cvtss2sd %xmm1, %xmm1
cvtss2sd %xmm2, %xmm2
cvtss2sd %xmm3, %xmm3
.cfi_escape 0x2e, 0x00
movl $.L.str.3, %edi
movb $4, %al
callq printf
addq $16, %r15
cmpq $12300, %r15 # imm = 0x300C
jne .LBB3_20
# %bb.21:
movq 88(%rsp), %rdi
.Ltmp35:
.cfi_escape 0x2e, 0x00
callq hipFree
.Ltmp36:
# %bb.22:
movq 80(%rsp), %rdi
.Ltmp37:
.cfi_escape 0x2e, 0x00
callq hipFree
.Ltmp38:
# %bb.23:
movq 72(%rsp), %rdi
.Ltmp39:
.cfi_escape 0x2e, 0x00
callq hipFree
.Ltmp40:
# %bb.24: # %_ZNSt6vectorI15HIP_vector_typeIfLj4EESaIS1_EED2Ev.exit
.cfi_escape 0x2e, 0x00
movq %r14, %rdi
callq _ZdlPv
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
callq _ZdlPv
xorl %eax, %eax
addq $120, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB3_28:
.cfi_def_cfa_offset 160
.Ltmp10:
jmp .LBB3_29
.LBB3_25:
.Ltmp2:
movq %rax, %r15
jmp .LBB3_30
.LBB3_26:
.Ltmp7:
jmp .LBB3_29
.LBB3_27:
.Ltmp41:
.LBB3_29: # %_ZNSt6vectorI15HIP_vector_typeIfLj4EESaIS1_EED2Ev.exit64
movq %rax, %r15
.cfi_escape 0x2e, 0x00
movq %r14, %rdi
callq _ZdlPv
.LBB3_30: # %_ZNSt6vectorIiSaIiEED2Ev.exit66
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
callq _ZdlPv
.cfi_escape 0x2e, 0x00
movq %r15, %rdi
callq _Unwind_Resume@PLT
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
.section .gcc_except_table,"a",@progbits
.p2align 2, 0x0
GCC_except_table3:
.Lexception0:
.byte 255 # @LPStart Encoding = omit
.byte 255 # @TType Encoding = omit
.byte 1 # Call site Encoding = uleb128
.uleb128 .Lcst_end0-.Lcst_begin0
.Lcst_begin0:
.uleb128 .Lfunc_begin0-.Lfunc_begin0 # >> Call Site 1 <<
.uleb128 .Ltmp0-.Lfunc_begin0 # Call between .Lfunc_begin0 and .Ltmp0
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp0-.Lfunc_begin0 # >> Call Site 2 <<
.uleb128 .Ltmp1-.Ltmp0 # Call between .Ltmp0 and .Ltmp1
.uleb128 .Ltmp2-.Lfunc_begin0 # jumps to .Ltmp2
.byte 0 # On action: cleanup
.uleb128 .Ltmp1-.Lfunc_begin0 # >> Call Site 3 <<
.uleb128 .Ltmp3-.Ltmp1 # Call between .Ltmp1 and .Ltmp3
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp3-.Lfunc_begin0 # >> Call Site 4 <<
.uleb128 .Ltmp6-.Ltmp3 # Call between .Ltmp3 and .Ltmp6
.uleb128 .Ltmp7-.Lfunc_begin0 # jumps to .Ltmp7
.byte 0 # On action: cleanup
.uleb128 .Ltmp8-.Lfunc_begin0 # >> Call Site 5 <<
.uleb128 .Ltmp9-.Ltmp8 # Call between .Ltmp8 and .Ltmp9
.uleb128 .Ltmp10-.Lfunc_begin0 # jumps to .Ltmp10
.byte 0 # On action: cleanup
.uleb128 .Ltmp11-.Lfunc_begin0 # >> Call Site 6 <<
.uleb128 .Ltmp40-.Ltmp11 # Call between .Ltmp11 and .Ltmp40
.uleb128 .Ltmp41-.Lfunc_begin0 # jumps to .Ltmp41
.byte 0 # On action: cleanup
.uleb128 .Ltmp40-.Lfunc_begin0 # >> Call Site 7 <<
.uleb128 .Lfunc_end3-.Ltmp40 # Call between .Ltmp40 and .Lfunc_end3
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.Lcst_end0:
.p2align 2, 0x0
# -- End function
.text
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12setup_kernelP12hiprandStatem, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10addToCountiPiP12hiprandState, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12initPositioniP15HIP_vector_typeIfLj4EEP12hiprandState, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z12setup_kernelP12hiprandStatem,@object # @_Z12setup_kernelP12hiprandStatem
.section .rodata,"a",@progbits
.globl _Z12setup_kernelP12hiprandStatem
.p2align 3, 0x0
_Z12setup_kernelP12hiprandStatem:
.quad _Z27__device_stub__setup_kernelP12hiprandStatem
.size _Z12setup_kernelP12hiprandStatem, 8
.type _Z10addToCountiPiP12hiprandState,@object # @_Z10addToCountiPiP12hiprandState
.globl _Z10addToCountiPiP12hiprandState
.p2align 3, 0x0
_Z10addToCountiPiP12hiprandState:
.quad _Z25__device_stub__addToCountiPiP12hiprandState
.size _Z10addToCountiPiP12hiprandState, 8
.type _Z12initPositioniP15HIP_vector_typeIfLj4EEP12hiprandState,@object # @_Z12initPositioniP15HIP_vector_typeIfLj4EEP12hiprandState
.globl _Z12initPositioniP15HIP_vector_typeIfLj4EEP12hiprandState
.p2align 3, 0x0
_Z12initPositioniP15HIP_vector_typeIfLj4EEP12hiprandState:
.quad _Z27__device_stub__initPositioniP15HIP_vector_typeIfLj4EEP12hiprandState
.size _Z12initPositioniP15HIP_vector_typeIfLj4EEP12hiprandState, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "nblocks = %i\n"
.size .L.str, 14
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "final = %i\n"
.size .L.str.1, 12
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "# %i particles:\n"
.size .L.str.2, 17
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "%15.7f %15.7f %15.7f %15.7f\n"
.size .L.str.3, 29
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z12setup_kernelP12hiprandStatem"
.size .L__unnamed_1, 33
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z10addToCountiPiP12hiprandState"
.size .L__unnamed_2, 33
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z12initPositioniP15HIP_vector_typeIfLj4EEP12hiprandState"
.size .L__unnamed_3, 58
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__setup_kernelP12hiprandStatem
.addrsig_sym _Z25__device_stub__addToCountiPiP12hiprandState
.addrsig_sym _Z27__device_stub__initPositioniP15HIP_vector_typeIfLj4EEP12hiprandState
.addrsig_sym __gxx_personality_v0
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Unwind_Resume
.addrsig_sym _Z12setup_kernelP12hiprandStatem
.addrsig_sym _Z10addToCountiPiP12hiprandState
.addrsig_sym _Z12initPositioniP15HIP_vector_typeIfLj4EEP12hiprandState
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <cmath>
#include <cstdlib>
#include <cstring>
#include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <stdio.h>
// -------------------------------------------------------------------------------------
__global__ void FMaxPoolForward(const float* ori_data, float* pool_data, int* indice_data,
const int num, const int channels,
const int height, const int width,
const int pooled_height, const int pooled_width,
const int poolsize, const int poolstrike) {
int poolx = threadIdx.x + blockIdx.x * blockDim.x;
int pooly = threadIdx.y + blockIdx.y * blockDim.y;
int poolz = blockIdx.z;
if (pooly < pooled_height && poolx < pooled_width) {
int hstart = pooly * poolstrike;
int hend = hstart + poolsize;
int wstart = poolx * poolstrike;
int wend = wstart + poolsize;
float maxval = -9999;
int indice = 0;
ori_data += poolz * height * width;
for (int h = hstart; h < hend; h++) {
for (int w = wstart; w < wend; w++) {
if( ori_data[h * width + w] > maxval){
maxval = ori_data[h * width + w];
indice = (h - hstart) * poolsize + w - wstart ;
}
}
}
pool_data[poolx + pooly * pooled_width + poolz * pooled_height * pooled_width] = maxval;
indice_data[poolx + pooly * pooled_width + poolz * pooled_height * pooled_width] = indice;
}
}
//---------------------------------------------------------------------------------------
__global__ void FMaxPoolBackward(float* reverse_data, float* pool_data, int* indice_data,
const int num, const int channels,
const int height, const int width,
const int pooled_height, const int pooled_width,
const int poolsize, const int poolstrike) {
int poolx = threadIdx.x + blockIdx.x * blockDim.x;
int pooly = threadIdx.y + blockIdx.y * blockDim.y;
int poolz = blockIdx.z;
if (pooly < pooled_height && poolx < pooled_width) {
float maxdata = pool_data[poolx + pooly * pooled_width + poolz * pooled_height * pooled_width] ;
int posit = indice_data[poolx + pooly * pooled_width + poolz * pooled_height * pooled_width] ;
int hstart = pooly * poolstrike;
int wstart = poolx * poolstrike;
int woffset = posit % poolsize;
int hoffset = int(posit / poolsize);
int h = hstart + hoffset;
int w = wstart + woffset;
reverse_data += poolz * height * width;
reverse_data[h * width + w] = maxdata;
}
}
//--------------------------------------------------------------------------------------------
__global__ void FMaxPoolForwardFix(const float* ori_data, float* pool_data, int* indice_data,
const int num, const int channels,
const int height, const int width,
const int pooled_height, const int pooled_width,
const int poolsize, const int poolstrike) {
int poolx = threadIdx.x + blockIdx.x * blockDim.x;
int pooly = threadIdx.y + blockIdx.y * blockDim.y;
int poolz = blockIdx.z;
if (pooly < pooled_height && poolx < pooled_width) {
int posit = indice_data[poolx + pooly * pooled_width + poolz * pooled_height * pooled_width] ;
int hstart = pooly * poolstrike;
int wstart = poolx * poolstrike;
int woffset = posit % poolsize;
int hoffset = int(posit / poolsize);
int h = hstart + hoffset;
int w = wstart + woffset;
ori_data += poolz * height * width;
pool_data[poolx + pooly * pooled_width + poolz * pooled_height * pooled_width] = ori_data[h * width + w];
}
} | .file "tmpxft_000991c4_00000000-6_Fmaxpool.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2059:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z48__device_stub__Z15FMaxPoolForwardPKfPfPiiiiiiiiiPKfPfPiiiiiiiii
.type _Z48__device_stub__Z15FMaxPoolForwardPKfPfPiiiiiiiiiPKfPfPiiiiiiiii, @function
_Z48__device_stub__Z15FMaxPoolForwardPKfPfPiiiiiiiiiPKfPfPiiiiiiiii:
.LFB2081:
.cfi_startproc
endbr64
subq $216, %rsp
.cfi_def_cfa_offset 224
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 200(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
leaq 224(%rsp), %rax
movq %rax, 160(%rsp)
leaq 232(%rsp), %rax
movq %rax, 168(%rsp)
leaq 240(%rsp), %rax
movq %rax, 176(%rsp)
leaq 248(%rsp), %rax
movq %rax, 184(%rsp)
leaq 256(%rsp), %rax
movq %rax, 192(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 200(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $216, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 232
pushq 56(%rsp)
.cfi_def_cfa_offset 240
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z15FMaxPoolForwardPKfPfPiiiiiiiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 224
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2081:
.size _Z48__device_stub__Z15FMaxPoolForwardPKfPfPiiiiiiiiiPKfPfPiiiiiiiii, .-_Z48__device_stub__Z15FMaxPoolForwardPKfPfPiiiiiiiiiPKfPfPiiiiiiiii
.globl _Z15FMaxPoolForwardPKfPfPiiiiiiiii
.type _Z15FMaxPoolForwardPKfPfPiiiiiiiii, @function
_Z15FMaxPoolForwardPKfPfPiiiiiiiii:
.LFB2082:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 40
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 48
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 56
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 64
call _Z48__device_stub__Z15FMaxPoolForwardPKfPfPiiiiiiiiiPKfPfPiiiiiiiii
addq $56, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2082:
.size _Z15FMaxPoolForwardPKfPfPiiiiiiiii, .-_Z15FMaxPoolForwardPKfPfPiiiiiiiii
.globl _Z48__device_stub__Z16FMaxPoolBackwardPfS_PiiiiiiiiiPfS_Piiiiiiiii
.type _Z48__device_stub__Z16FMaxPoolBackwardPfS_PiiiiiiiiiPfS_Piiiiiiiii, @function
_Z48__device_stub__Z16FMaxPoolBackwardPfS_PiiiiiiiiiPfS_Piiiiiiiii:
.LFB2083:
.cfi_startproc
endbr64
subq $216, %rsp
.cfi_def_cfa_offset 224
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 200(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
leaq 224(%rsp), %rax
movq %rax, 160(%rsp)
leaq 232(%rsp), %rax
movq %rax, 168(%rsp)
leaq 240(%rsp), %rax
movq %rax, 176(%rsp)
leaq 248(%rsp), %rax
movq %rax, 184(%rsp)
leaq 256(%rsp), %rax
movq %rax, 192(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 200(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $216, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 232
pushq 56(%rsp)
.cfi_def_cfa_offset 240
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z16FMaxPoolBackwardPfS_Piiiiiiiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 224
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z48__device_stub__Z16FMaxPoolBackwardPfS_PiiiiiiiiiPfS_Piiiiiiiii, .-_Z48__device_stub__Z16FMaxPoolBackwardPfS_PiiiiiiiiiPfS_Piiiiiiiii
.globl _Z16FMaxPoolBackwardPfS_Piiiiiiiii
.type _Z16FMaxPoolBackwardPfS_Piiiiiiiii, @function
_Z16FMaxPoolBackwardPfS_Piiiiiiiii:
.LFB2084:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 40
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 48
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 56
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 64
call _Z48__device_stub__Z16FMaxPoolBackwardPfS_PiiiiiiiiiPfS_Piiiiiiiii
addq $56, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z16FMaxPoolBackwardPfS_Piiiiiiiii, .-_Z16FMaxPoolBackwardPfS_Piiiiiiiii
.globl _Z51__device_stub__Z18FMaxPoolForwardFixPKfPfPiiiiiiiiiPKfPfPiiiiiiiii
.type _Z51__device_stub__Z18FMaxPoolForwardFixPKfPfPiiiiiiiiiPKfPfPiiiiiiiii, @function
_Z51__device_stub__Z18FMaxPoolForwardFixPKfPfPiiiiiiiiiPKfPfPiiiiiiiii:
.LFB2085:
.cfi_startproc
endbr64
subq $216, %rsp
.cfi_def_cfa_offset 224
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 200(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
leaq 224(%rsp), %rax
movq %rax, 160(%rsp)
leaq 232(%rsp), %rax
movq %rax, 168(%rsp)
leaq 240(%rsp), %rax
movq %rax, 176(%rsp)
leaq 248(%rsp), %rax
movq %rax, 184(%rsp)
leaq 256(%rsp), %rax
movq %rax, 192(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L23
.L19:
movq 200(%rsp), %rax
subq %fs:40, %rax
jne .L24
addq $216, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 232
pushq 56(%rsp)
.cfi_def_cfa_offset 240
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z18FMaxPoolForwardFixPKfPfPiiiiiiiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 224
jmp .L19
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2085:
.size _Z51__device_stub__Z18FMaxPoolForwardFixPKfPfPiiiiiiiiiPKfPfPiiiiiiiii, .-_Z51__device_stub__Z18FMaxPoolForwardFixPKfPfPiiiiiiiiiPKfPfPiiiiiiiii
.globl _Z18FMaxPoolForwardFixPKfPfPiiiiiiiii
.type _Z18FMaxPoolForwardFixPKfPfPiiiiiiiii, @function
_Z18FMaxPoolForwardFixPKfPfPiiiiiiiii:
.LFB2086:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 40
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 48
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 56
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 64
call _Z51__device_stub__Z18FMaxPoolForwardFixPKfPfPiiiiiiiiiPKfPfPiiiiiiiii
addq $56, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _Z18FMaxPoolForwardFixPKfPfPiiiiiiiii, .-_Z18FMaxPoolForwardFixPKfPfPiiiiiiiii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z18FMaxPoolForwardFixPKfPfPiiiiiiiii"
.align 8
.LC1:
.string "_Z16FMaxPoolBackwardPfS_Piiiiiiiii"
.align 8
.LC2:
.string "_Z15FMaxPoolForwardPKfPfPiiiiiiiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2088:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z18FMaxPoolForwardFixPKfPfPiiiiiiiii(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z16FMaxPoolBackwardPfS_Piiiiiiiii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z15FMaxPoolForwardPKfPfPiiiiiiiii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2088:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <cmath>
#include <cstdlib>
#include <cstring>
#include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <stdio.h>
// -------------------------------------------------------------------------------------
__global__ void FMaxPoolForward(const float* ori_data, float* pool_data, int* indice_data,
const int num, const int channels,
const int height, const int width,
const int pooled_height, const int pooled_width,
const int poolsize, const int poolstrike) {
int poolx = threadIdx.x + blockIdx.x * blockDim.x;
int pooly = threadIdx.y + blockIdx.y * blockDim.y;
int poolz = blockIdx.z;
if (pooly < pooled_height && poolx < pooled_width) {
int hstart = pooly * poolstrike;
int hend = hstart + poolsize;
int wstart = poolx * poolstrike;
int wend = wstart + poolsize;
float maxval = -9999;
int indice = 0;
ori_data += poolz * height * width;
for (int h = hstart; h < hend; h++) {
for (int w = wstart; w < wend; w++) {
if( ori_data[h * width + w] > maxval){
maxval = ori_data[h * width + w];
indice = (h - hstart) * poolsize + w - wstart ;
}
}
}
pool_data[poolx + pooly * pooled_width + poolz * pooled_height * pooled_width] = maxval;
indice_data[poolx + pooly * pooled_width + poolz * pooled_height * pooled_width] = indice;
}
}
//---------------------------------------------------------------------------------------
__global__ void FMaxPoolBackward(float* reverse_data, float* pool_data, int* indice_data,
const int num, const int channels,
const int height, const int width,
const int pooled_height, const int pooled_width,
const int poolsize, const int poolstrike) {
int poolx = threadIdx.x + blockIdx.x * blockDim.x;
int pooly = threadIdx.y + blockIdx.y * blockDim.y;
int poolz = blockIdx.z;
if (pooly < pooled_height && poolx < pooled_width) {
float maxdata = pool_data[poolx + pooly * pooled_width + poolz * pooled_height * pooled_width] ;
int posit = indice_data[poolx + pooly * pooled_width + poolz * pooled_height * pooled_width] ;
int hstart = pooly * poolstrike;
int wstart = poolx * poolstrike;
int woffset = posit % poolsize;
int hoffset = int(posit / poolsize);
int h = hstart + hoffset;
int w = wstart + woffset;
reverse_data += poolz * height * width;
reverse_data[h * width + w] = maxdata;
}
}
//--------------------------------------------------------------------------------------------
__global__ void FMaxPoolForwardFix(const float* ori_data, float* pool_data, int* indice_data,
const int num, const int channels,
const int height, const int width,
const int pooled_height, const int pooled_width,
const int poolsize, const int poolstrike) {
int poolx = threadIdx.x + blockIdx.x * blockDim.x;
int pooly = threadIdx.y + blockIdx.y * blockDim.y;
int poolz = blockIdx.z;
if (pooly < pooled_height && poolx < pooled_width) {
int posit = indice_data[poolx + pooly * pooled_width + poolz * pooled_height * pooled_width] ;
int hstart = pooly * poolstrike;
int wstart = poolx * poolstrike;
int woffset = posit % poolsize;
int hoffset = int(posit / poolsize);
int h = hstart + hoffset;
int w = wstart + woffset;
ori_data += poolz * height * width;
pool_data[poolx + pooly * pooled_width + poolz * pooled_height * pooled_width] = ori_data[h * width + w];
}
} | #include <cmath>
#include <cstdlib>
#include <cstring>
#include "hip/hip_runtime.h"
#include <stdio.h>
// -------------------------------------------------------------------------------------
__global__ void FMaxPoolForward(const float* ori_data, float* pool_data, int* indice_data,
const int num, const int channels,
const int height, const int width,
const int pooled_height, const int pooled_width,
const int poolsize, const int poolstrike) {
int poolx = threadIdx.x + blockIdx.x * blockDim.x;
int pooly = threadIdx.y + blockIdx.y * blockDim.y;
int poolz = blockIdx.z;
if (pooly < pooled_height && poolx < pooled_width) {
int hstart = pooly * poolstrike;
int hend = hstart + poolsize;
int wstart = poolx * poolstrike;
int wend = wstart + poolsize;
float maxval = -9999;
int indice = 0;
ori_data += poolz * height * width;
for (int h = hstart; h < hend; h++) {
for (int w = wstart; w < wend; w++) {
if( ori_data[h * width + w] > maxval){
maxval = ori_data[h * width + w];
indice = (h - hstart) * poolsize + w - wstart ;
}
}
}
pool_data[poolx + pooly * pooled_width + poolz * pooled_height * pooled_width] = maxval;
indice_data[poolx + pooly * pooled_width + poolz * pooled_height * pooled_width] = indice;
}
}
//---------------------------------------------------------------------------------------
__global__ void FMaxPoolBackward(float* reverse_data, float* pool_data, int* indice_data,
const int num, const int channels,
const int height, const int width,
const int pooled_height, const int pooled_width,
const int poolsize, const int poolstrike) {
int poolx = threadIdx.x + blockIdx.x * blockDim.x;
int pooly = threadIdx.y + blockIdx.y * blockDim.y;
int poolz = blockIdx.z;
if (pooly < pooled_height && poolx < pooled_width) {
float maxdata = pool_data[poolx + pooly * pooled_width + poolz * pooled_height * pooled_width] ;
int posit = indice_data[poolx + pooly * pooled_width + poolz * pooled_height * pooled_width] ;
int hstart = pooly * poolstrike;
int wstart = poolx * poolstrike;
int woffset = posit % poolsize;
int hoffset = int(posit / poolsize);
int h = hstart + hoffset;
int w = wstart + woffset;
reverse_data += poolz * height * width;
reverse_data[h * width + w] = maxdata;
}
}
//--------------------------------------------------------------------------------------------
__global__ void FMaxPoolForwardFix(const float* ori_data, float* pool_data, int* indice_data,
const int num, const int channels,
const int height, const int width,
const int pooled_height, const int pooled_width,
const int poolsize, const int poolstrike) {
int poolx = threadIdx.x + blockIdx.x * blockDim.x;
int pooly = threadIdx.y + blockIdx.y * blockDim.y;
int poolz = blockIdx.z;
if (pooly < pooled_height && poolx < pooled_width) {
int posit = indice_data[poolx + pooly * pooled_width + poolz * pooled_height * pooled_width] ;
int hstart = pooly * poolstrike;
int wstart = poolx * poolstrike;
int woffset = posit % poolsize;
int hoffset = int(posit / poolsize);
int h = hstart + hoffset;
int w = wstart + woffset;
ori_data += poolz * height * width;
pool_data[poolx + pooly * pooled_width + poolz * pooled_height * pooled_width] = ori_data[h * width + w];
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <cmath>
#include <cstdlib>
#include <cstring>
#include "hip/hip_runtime.h"
#include <stdio.h>
// -------------------------------------------------------------------------------------
__global__ void FMaxPoolForward(const float* ori_data, float* pool_data, int* indice_data,
const int num, const int channels,
const int height, const int width,
const int pooled_height, const int pooled_width,
const int poolsize, const int poolstrike) {
int poolx = threadIdx.x + blockIdx.x * blockDim.x;
int pooly = threadIdx.y + blockIdx.y * blockDim.y;
int poolz = blockIdx.z;
if (pooly < pooled_height && poolx < pooled_width) {
int hstart = pooly * poolstrike;
int hend = hstart + poolsize;
int wstart = poolx * poolstrike;
int wend = wstart + poolsize;
float maxval = -9999;
int indice = 0;
ori_data += poolz * height * width;
for (int h = hstart; h < hend; h++) {
for (int w = wstart; w < wend; w++) {
if( ori_data[h * width + w] > maxval){
maxval = ori_data[h * width + w];
indice = (h - hstart) * poolsize + w - wstart ;
}
}
}
pool_data[poolx + pooly * pooled_width + poolz * pooled_height * pooled_width] = maxval;
indice_data[poolx + pooly * pooled_width + poolz * pooled_height * pooled_width] = indice;
}
}
//---------------------------------------------------------------------------------------
__global__ void FMaxPoolBackward(float* reverse_data, float* pool_data, int* indice_data,
const int num, const int channels,
const int height, const int width,
const int pooled_height, const int pooled_width,
const int poolsize, const int poolstrike) {
int poolx = threadIdx.x + blockIdx.x * blockDim.x;
int pooly = threadIdx.y + blockIdx.y * blockDim.y;
int poolz = blockIdx.z;
if (pooly < pooled_height && poolx < pooled_width) {
float maxdata = pool_data[poolx + pooly * pooled_width + poolz * pooled_height * pooled_width] ;
int posit = indice_data[poolx + pooly * pooled_width + poolz * pooled_height * pooled_width] ;
int hstart = pooly * poolstrike;
int wstart = poolx * poolstrike;
int woffset = posit % poolsize;
int hoffset = int(posit / poolsize);
int h = hstart + hoffset;
int w = wstart + woffset;
reverse_data += poolz * height * width;
reverse_data[h * width + w] = maxdata;
}
}
//--------------------------------------------------------------------------------------------
__global__ void FMaxPoolForwardFix(const float* ori_data, float* pool_data, int* indice_data,
const int num, const int channels,
const int height, const int width,
const int pooled_height, const int pooled_width,
const int poolsize, const int poolstrike) {
int poolx = threadIdx.x + blockIdx.x * blockDim.x;
int pooly = threadIdx.y + blockIdx.y * blockDim.y;
int poolz = blockIdx.z;
if (pooly < pooled_height && poolx < pooled_width) {
int posit = indice_data[poolx + pooly * pooled_width + poolz * pooled_height * pooled_width] ;
int hstart = pooly * poolstrike;
int wstart = poolx * poolstrike;
int woffset = posit % poolsize;
int hoffset = int(posit / poolsize);
int h = hstart + hoffset;
int w = wstart + woffset;
ori_data += poolz * height * width;
pool_data[poolx + pooly * pooled_width + poolz * pooled_height * pooled_width] = ori_data[h * width + w];
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z15FMaxPoolForwardPKfPfPiiiiiiiii
.globl _Z15FMaxPoolForwardPKfPfPiiiiiiiii
.p2align 8
.type _Z15FMaxPoolForwardPKfPfPiiiiiiiii,@function
_Z15FMaxPoolForwardPKfPfPiiiiiiiii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x44
s_load_b64 s[4:5], s[0:1], 0x28
v_bfe_u32 v4, v0, 10, 10
v_and_b32_e32 v3, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_lshr_b32 s2, s2, 16
s_mul_i32 s13, s13, s3
v_mad_u64_u32 v[1:2], null, s14, s2, v[4:5]
v_add_nc_u32_e32 v0, s13, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cmp_gt_i32_e64 s2, s5, v0
v_cmp_gt_i32_e32 vcc_lo, s4, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, s2, vcc_lo
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_9
s_load_b32 s8, s[0:1], 0x30
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s8, 1
s_cbranch_scc1 .LBB0_7
s_clause 0x2
s_load_b64 s[6:7], s[0:1], 0x20
s_load_b32 s9, s[0:1], 0x34
s_load_b64 s[2:3], s[0:1], 0x0
v_dual_mov_b32 v5, 0 :: v_dual_mov_b32 v6, 0xc61c3c00
s_waitcnt lgkmcnt(0)
v_mul_lo_u32 v2, s7, v1
v_mul_lo_u32 v7, v1, s9
v_mul_lo_u32 v8, v0, s9
s_mul_i32 s6, s15, s6
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s10, s6, s7
s_ashr_i32 s11, s10, 31
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add3_u32 v2, v3, v2, s13
v_add_nc_u32_e32 v9, s8, v7
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_add_nc_u32_e32 v10, s8, v8
s_lshl_b64 s[10:11], s[10:11], 2
s_add_u32 s6, s2, s10
v_mul_lo_u32 v2, s9, v2
s_addc_u32 s10, s3, s11
s_mov_b32 s9, 0
s_mov_b32 s11, 0
s_set_inst_prefetch_distance 0x1
.p2align 6
.LBB0_3:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v3, 31, v2
v_mov_b32_e32 v11, v8
s_mov_b32 s12, 0
s_mov_b32 s13, s11
v_lshlrev_b64 v[3:4], 2, v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v3, vcc_lo, s6, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s10, v4, vcc_lo
.p2align 6
.LBB0_4:
global_load_b32 v12, v[3:4], off
v_add_nc_u32_e32 v11, 1, v11
v_add_co_u32 v3, vcc_lo, v3, 4
v_add_co_ci_u32_e32 v4, vcc_lo, 0, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_cmp_ge_i32_e64 s3, v11, v10
s_waitcnt vmcnt(0)
v_cmp_gt_f32_e64 s2, v12, v6
v_cndmask_b32_e64 v6, v6, v12, s2
v_cndmask_b32_e64 v5, v5, s13, s2
s_add_i32 s13, s13, 1
s_or_b32 s12, s3, s12
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s12
s_cbranch_execnz .LBB0_4
s_or_b32 exec_lo, exec_lo, s12
v_add_nc_u32_e32 v7, 1, v7
v_add_nc_u32_e32 v2, s7, v2
s_add_i32 s11, s11, s8
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_ge_i32_e32 vcc_lo, v7, v9
s_or_b32 s9, vcc_lo, s9
s_and_not1_b32 exec_lo, exec_lo, s9
s_cbranch_execnz .LBB0_3
s_set_inst_prefetch_distance 0x2
s_or_b32 exec_lo, exec_lo, s9
s_branch .LBB0_8
.LBB0_7:
v_dual_mov_b32 v5, 0 :: v_dual_mov_b32 v6, 0xc61c3c00
.LBB0_8:
v_mad_u64_u32 v[2:3], null, s15, s4, v[1:2]
s_load_b128 s[0:3], s[0:1], 0x8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[3:4], null, v2, s5, v[0:1]
v_ashrrev_i32_e32 v4, 31, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[3:4]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_store_b32 v[2:3], v6, off
global_store_b32 v[0:1], v5, off
.LBB0_9:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z15FMaxPoolForwardPKfPfPiiiiiiiii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 312
.amdhsa_user_sgpr_count 13
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 1
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 13
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z15FMaxPoolForwardPKfPfPiiiiiiiii, .Lfunc_end0-_Z15FMaxPoolForwardPKfPfPiiiiiiiii
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z16FMaxPoolBackwardPfS_Piiiiiiiii
.globl _Z16FMaxPoolBackwardPfS_Piiiiiiiii
.p2align 8
.type _Z16FMaxPoolBackwardPfS_Piiiiiiiii,@function
_Z16FMaxPoolBackwardPfS_Piiiiiiiii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x44
s_load_b64 s[4:5], s[0:1], 0x28
v_bfe_u32 v1, v0, 10, 10
v_and_b32_e32 v4, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_lshr_b32 s2, s2, 16
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[2:3], null, s14, s2, v[1:2]
v_mad_u64_u32 v[0:1], null, s13, s3, v[4:5]
v_cmp_gt_i32_e32 vcc_lo, s4, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i32_e64 s2, s5, v0
s_and_b32 s2, s2, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB1_2
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[3:4], null, s15, s4, v[2:3]
s_load_b64 s[2:3], s[0:1], 0x10
v_mad_u64_u32 v[4:5], null, v3, s5, v[0:1]
s_load_b128 s[4:7], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v5, 31, v4
v_lshlrev_b64 v[3:4], 2, v[4:5]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v5, vcc_lo, s2, v3
v_add_co_ci_u32_e32 v6, vcc_lo, s3, v4, vcc_lo
v_add_co_u32 v3, vcc_lo, s6, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s7, v4, vcc_lo
global_load_b32 v5, v[5:6], off
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x30
s_load_b64 s[0:1], s[0:1], 0x20
global_load_b32 v6, v[3:4], off
s_waitcnt lgkmcnt(0)
s_ashr_i32 s6, s2, 31
v_mul_lo_u32 v0, v0, s3
s_add_i32 s7, s2, s6
s_mul_i32 s0, s15, s0
s_xor_b32 s7, s7, s6
s_mul_i32 s0, s0, s1
v_cvt_f32_u32_e32 v1, s7
s_sub_i32 s8, 0, s7
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v1, v1
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v1, 0x4f7ffffe, v1
v_cvt_u32_f32_e32 v1, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v3, s8, v1
v_mul_hi_u32 v3, v1, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v1, v1, v3
s_waitcnt vmcnt(1)
v_ashrrev_i32_e32 v4, 31, v5
v_add_nc_u32_e32 v7, v5, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_xor_b32_e32 v3, v7, v4
v_xor_b32_e32 v4, s6, v4
v_mul_hi_u32 v1, v3, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v7, v1, s7
v_sub_nc_u32_e32 v3, v3, v7
v_add_nc_u32_e32 v7, 1, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_subrev_nc_u32_e32 v8, s7, v3
v_cmp_le_u32_e32 vcc_lo, s7, v3
v_cndmask_b32_e32 v1, v1, v7, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v3, v3, v8, vcc_lo
v_add_nc_u32_e32 v7, 1, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_le_u32_e32 vcc_lo, s7, v3
v_cndmask_b32_e32 v1, v1, v7, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_xor_b32_e32 v1, v1, v4
v_sub_nc_u32_e32 v1, v1, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[3:4], null, v2, s3, v[1:2]
v_mul_lo_u32 v1, v1, s2
v_mul_lo_u32 v2, v3, s1
s_ashr_i32 s1, s0, 31
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_sub_nc_u32_e32 v1, v5, v1
s_lshl_b64 s[0:1], s[0:1], 2
s_add_u32 s0, s4, s0
s_addc_u32 s1, s5, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add3_u32 v0, v1, v0, v2
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[0:1]
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
global_store_b32 v[0:1], v6, off
.LBB1_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z16FMaxPoolBackwardPfS_Piiiiiiiii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 312
.amdhsa_user_sgpr_count 13
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 1
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z16FMaxPoolBackwardPfS_Piiiiiiiii, .Lfunc_end1-_Z16FMaxPoolBackwardPfS_Piiiiiiiii
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z18FMaxPoolForwardFixPKfPfPiiiiiiiii
.globl _Z18FMaxPoolForwardFixPKfPfPiiiiiiiii
.p2align 8
.type _Z18FMaxPoolForwardFixPKfPfPiiiiiiiii,@function
_Z18FMaxPoolForwardFixPKfPfPiiiiiiiii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x44
s_load_b64 s[4:5], s[0:1], 0x28
v_bfe_u32 v1, v0, 10, 10
v_and_b32_e32 v4, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_lshr_b32 s2, s2, 16
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[2:3], null, s14, s2, v[1:2]
v_mad_u64_u32 v[0:1], null, s13, s3, v[4:5]
v_cmp_gt_i32_e32 vcc_lo, s4, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i32_e64 s2, s5, v0
s_and_b32 s2, s2, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB2_2
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[3:4], null, s15, s4, v[2:3]
s_load_b64 s[2:3], s[0:1], 0x10
v_mad_u64_u32 v[4:5], null, v3, s5, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v5, 31, v4
v_lshlrev_b64 v[3:4], 2, v[4:5]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v5, vcc_lo, s2, v3
v_add_co_ci_u32_e32 v6, vcc_lo, s3, v4, vcc_lo
s_load_b64 s[2:3], s[0:1], 0x30
global_load_b32 v7, v[5:6], off
s_waitcnt lgkmcnt(0)
s_ashr_i32 s4, s2, 31
v_mul_lo_u32 v0, v0, s3
s_add_i32 s5, s2, s4
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_xor_b32 s5, s5, s4
v_cvt_f32_u32_e32 v1, s5
s_sub_i32 s6, 0, s5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v1, v1
s_waitcnt vmcnt(0)
v_ashrrev_i32_e32 v6, 31, v7
s_waitcnt_depctr 0xfff
v_dual_mul_f32 v1, 0x4f7ffffe, v1 :: v_dual_add_nc_u32 v8, v7, v6
v_cvt_u32_f32_e32 v1, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v5, s6, v1
v_mul_hi_u32 v5, v1, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v1, v1, v5
v_xor_b32_e32 v5, v8, v6
v_xor_b32_e32 v6, s4, v6
v_mul_hi_u32 v1, v5, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v8, v1, s5
v_sub_nc_u32_e32 v5, v5, v8
v_add_nc_u32_e32 v8, 1, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_subrev_nc_u32_e32 v9, s5, v5
v_cmp_le_u32_e32 vcc_lo, s5, v5
v_cndmask_b32_e32 v1, v1, v8, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v5, v5, v9, vcc_lo
v_add_nc_u32_e32 v8, 1, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cmp_le_u32_e32 vcc_lo, s5, v5
s_load_b64 s[4:5], s[0:1], 0x20
v_cndmask_b32_e32 v1, v1, v8, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_xor_b32_e32 v1, v1, v6
v_sub_nc_u32_e32 v1, v1, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[5:6], null, v2, s3, v[1:2]
v_mul_lo_u32 v1, v1, s2
s_load_b128 s[0:3], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_mul_i32 s4, s15, s4
s_mul_i32 s4, s4, s5
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_lo_u32 v2, v5, s5
s_ashr_i32 s5, s4, 31
v_sub_nc_u32_e32 v1, v7, v1
s_lshl_b64 s[4:5], s[4:5], 2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add3_u32 v0, v1, v0, v2
v_ashrrev_i32_e32 v1, 31, v0
s_add_u32 s0, s0, s4
s_addc_u32 s1, s1, s5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[0:1]
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b32 v2, v[0:1], off
v_add_co_u32 v0, vcc_lo, s2, v3
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v4, vcc_lo
s_waitcnt vmcnt(0)
global_store_b32 v[0:1], v2, off
.LBB2_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z18FMaxPoolForwardFixPKfPfPiiiiiiiii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 312
.amdhsa_user_sgpr_count 13
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 1
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 10
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end2:
.size _Z18FMaxPoolForwardFixPKfPfPiiiiiiiii, .Lfunc_end2-_Z18FMaxPoolForwardFixPKfPfPiiiiiiiii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 36
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: by_value
- .offset: 44
.size: 4
.value_kind: by_value
- .offset: 48
.size: 4
.value_kind: by_value
- .offset: 52
.size: 4
.value_kind: by_value
- .offset: 56
.size: 4
.value_kind: hidden_block_count_x
- .offset: 60
.size: 4
.value_kind: hidden_block_count_y
- .offset: 64
.size: 4
.value_kind: hidden_block_count_z
- .offset: 68
.size: 2
.value_kind: hidden_group_size_x
- .offset: 70
.size: 2
.value_kind: hidden_group_size_y
- .offset: 72
.size: 2
.value_kind: hidden_group_size_z
- .offset: 74
.size: 2
.value_kind: hidden_remainder_x
- .offset: 76
.size: 2
.value_kind: hidden_remainder_y
- .offset: 78
.size: 2
.value_kind: hidden_remainder_z
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 112
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 120
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 312
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z15FMaxPoolForwardPKfPfPiiiiiiiii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z15FMaxPoolForwardPKfPfPiiiiiiiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 13
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 36
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: by_value
- .offset: 44
.size: 4
.value_kind: by_value
- .offset: 48
.size: 4
.value_kind: by_value
- .offset: 52
.size: 4
.value_kind: by_value
- .offset: 56
.size: 4
.value_kind: hidden_block_count_x
- .offset: 60
.size: 4
.value_kind: hidden_block_count_y
- .offset: 64
.size: 4
.value_kind: hidden_block_count_z
- .offset: 68
.size: 2
.value_kind: hidden_group_size_x
- .offset: 70
.size: 2
.value_kind: hidden_group_size_y
- .offset: 72
.size: 2
.value_kind: hidden_group_size_z
- .offset: 74
.size: 2
.value_kind: hidden_remainder_x
- .offset: 76
.size: 2
.value_kind: hidden_remainder_y
- .offset: 78
.size: 2
.value_kind: hidden_remainder_z
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 112
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 120
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 312
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z16FMaxPoolBackwardPfS_Piiiiiiiii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z16FMaxPoolBackwardPfS_Piiiiiiiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 36
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: by_value
- .offset: 44
.size: 4
.value_kind: by_value
- .offset: 48
.size: 4
.value_kind: by_value
- .offset: 52
.size: 4
.value_kind: by_value
- .offset: 56
.size: 4
.value_kind: hidden_block_count_x
- .offset: 60
.size: 4
.value_kind: hidden_block_count_y
- .offset: 64
.size: 4
.value_kind: hidden_block_count_z
- .offset: 68
.size: 2
.value_kind: hidden_group_size_x
- .offset: 70
.size: 2
.value_kind: hidden_group_size_y
- .offset: 72
.size: 2
.value_kind: hidden_group_size_z
- .offset: 74
.size: 2
.value_kind: hidden_remainder_x
- .offset: 76
.size: 2
.value_kind: hidden_remainder_y
- .offset: 78
.size: 2
.value_kind: hidden_remainder_z
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 112
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 120
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 312
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z18FMaxPoolForwardFixPKfPfPiiiiiiiii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z18FMaxPoolForwardFixPKfPfPiiiiiiiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 10
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <cmath>
#include <cstdlib>
#include <cstring>
#include "hip/hip_runtime.h"
#include <stdio.h>
// -------------------------------------------------------------------------------------
__global__ void FMaxPoolForward(const float* ori_data, float* pool_data, int* indice_data,
const int num, const int channels,
const int height, const int width,
const int pooled_height, const int pooled_width,
const int poolsize, const int poolstrike) {
int poolx = threadIdx.x + blockIdx.x * blockDim.x;
int pooly = threadIdx.y + blockIdx.y * blockDim.y;
int poolz = blockIdx.z;
if (pooly < pooled_height && poolx < pooled_width) {
int hstart = pooly * poolstrike;
int hend = hstart + poolsize;
int wstart = poolx * poolstrike;
int wend = wstart + poolsize;
float maxval = -9999;
int indice = 0;
ori_data += poolz * height * width;
for (int h = hstart; h < hend; h++) {
for (int w = wstart; w < wend; w++) {
if( ori_data[h * width + w] > maxval){
maxval = ori_data[h * width + w];
indice = (h - hstart) * poolsize + w - wstart ;
}
}
}
pool_data[poolx + pooly * pooled_width + poolz * pooled_height * pooled_width] = maxval;
indice_data[poolx + pooly * pooled_width + poolz * pooled_height * pooled_width] = indice;
}
}
//---------------------------------------------------------------------------------------
__global__ void FMaxPoolBackward(float* reverse_data, float* pool_data, int* indice_data,
const int num, const int channels,
const int height, const int width,
const int pooled_height, const int pooled_width,
const int poolsize, const int poolstrike) {
int poolx = threadIdx.x + blockIdx.x * blockDim.x;
int pooly = threadIdx.y + blockIdx.y * blockDim.y;
int poolz = blockIdx.z;
if (pooly < pooled_height && poolx < pooled_width) {
float maxdata = pool_data[poolx + pooly * pooled_width + poolz * pooled_height * pooled_width] ;
int posit = indice_data[poolx + pooly * pooled_width + poolz * pooled_height * pooled_width] ;
int hstart = pooly * poolstrike;
int wstart = poolx * poolstrike;
int woffset = posit % poolsize;
int hoffset = int(posit / poolsize);
int h = hstart + hoffset;
int w = wstart + woffset;
reverse_data += poolz * height * width;
reverse_data[h * width + w] = maxdata;
}
}
//--------------------------------------------------------------------------------------------
__global__ void FMaxPoolForwardFix(const float* ori_data, float* pool_data, int* indice_data,
const int num, const int channels,
const int height, const int width,
const int pooled_height, const int pooled_width,
const int poolsize, const int poolstrike) {
int poolx = threadIdx.x + blockIdx.x * blockDim.x;
int pooly = threadIdx.y + blockIdx.y * blockDim.y;
int poolz = blockIdx.z;
if (pooly < pooled_height && poolx < pooled_width) {
int posit = indice_data[poolx + pooly * pooled_width + poolz * pooled_height * pooled_width] ;
int hstart = pooly * poolstrike;
int wstart = poolx * poolstrike;
int woffset = posit % poolsize;
int hoffset = int(posit / poolsize);
int h = hstart + hoffset;
int w = wstart + woffset;
ori_data += poolz * height * width;
pool_data[poolx + pooly * pooled_width + poolz * pooled_height * pooled_width] = ori_data[h * width + w];
}
} | .text
.file "Fmaxpool.hip"
.globl _Z30__device_stub__FMaxPoolForwardPKfPfPiiiiiiiii # -- Begin function _Z30__device_stub__FMaxPoolForwardPKfPfPiiiiiiiii
.p2align 4, 0x90
.type _Z30__device_stub__FMaxPoolForwardPKfPfPiiiiiiiii,@function
_Z30__device_stub__FMaxPoolForwardPKfPfPiiiiiiiii: # @_Z30__device_stub__FMaxPoolForwardPKfPfPiiiiiiiii
.cfi_startproc
# %bb.0:
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 192(%rsp), %rax
movq %rax, 144(%rsp)
leaq 200(%rsp), %rax
movq %rax, 152(%rsp)
leaq 208(%rsp), %rax
movq %rax, 160(%rsp)
leaq 216(%rsp), %rax
movq %rax, 168(%rsp)
leaq 224(%rsp), %rax
movq %rax, 176(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z15FMaxPoolForwardPKfPfPiiiiiiiii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $200, %rsp
.cfi_adjust_cfa_offset -200
retq
.Lfunc_end0:
.size _Z30__device_stub__FMaxPoolForwardPKfPfPiiiiiiiii, .Lfunc_end0-_Z30__device_stub__FMaxPoolForwardPKfPfPiiiiiiiii
.cfi_endproc
# -- End function
.globl _Z31__device_stub__FMaxPoolBackwardPfS_Piiiiiiiii # -- Begin function _Z31__device_stub__FMaxPoolBackwardPfS_Piiiiiiiii
.p2align 4, 0x90
.type _Z31__device_stub__FMaxPoolBackwardPfS_Piiiiiiiii,@function
_Z31__device_stub__FMaxPoolBackwardPfS_Piiiiiiiii: # @_Z31__device_stub__FMaxPoolBackwardPfS_Piiiiiiiii
.cfi_startproc
# %bb.0:
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 192(%rsp), %rax
movq %rax, 144(%rsp)
leaq 200(%rsp), %rax
movq %rax, 152(%rsp)
leaq 208(%rsp), %rax
movq %rax, 160(%rsp)
leaq 216(%rsp), %rax
movq %rax, 168(%rsp)
leaq 224(%rsp), %rax
movq %rax, 176(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z16FMaxPoolBackwardPfS_Piiiiiiiii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $200, %rsp
.cfi_adjust_cfa_offset -200
retq
.Lfunc_end1:
.size _Z31__device_stub__FMaxPoolBackwardPfS_Piiiiiiiii, .Lfunc_end1-_Z31__device_stub__FMaxPoolBackwardPfS_Piiiiiiiii
.cfi_endproc
# -- End function
.globl _Z33__device_stub__FMaxPoolForwardFixPKfPfPiiiiiiiii # -- Begin function _Z33__device_stub__FMaxPoolForwardFixPKfPfPiiiiiiiii
.p2align 4, 0x90
.type _Z33__device_stub__FMaxPoolForwardFixPKfPfPiiiiiiiii,@function
_Z33__device_stub__FMaxPoolForwardFixPKfPfPiiiiiiiii: # @_Z33__device_stub__FMaxPoolForwardFixPKfPfPiiiiiiiii
.cfi_startproc
# %bb.0:
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 192(%rsp), %rax
movq %rax, 144(%rsp)
leaq 200(%rsp), %rax
movq %rax, 152(%rsp)
leaq 208(%rsp), %rax
movq %rax, 160(%rsp)
leaq 216(%rsp), %rax
movq %rax, 168(%rsp)
leaq 224(%rsp), %rax
movq %rax, 176(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z18FMaxPoolForwardFixPKfPfPiiiiiiiii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $200, %rsp
.cfi_adjust_cfa_offset -200
retq
.Lfunc_end2:
.size _Z33__device_stub__FMaxPoolForwardFixPKfPfPiiiiiiiii, .Lfunc_end2-_Z33__device_stub__FMaxPoolForwardFixPKfPfPiiiiiiiii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15FMaxPoolForwardPKfPfPiiiiiiiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z16FMaxPoolBackwardPfS_Piiiiiiiii, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z18FMaxPoolForwardFixPKfPfPiiiiiiiii, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z15FMaxPoolForwardPKfPfPiiiiiiiii,@object # @_Z15FMaxPoolForwardPKfPfPiiiiiiiii
.section .rodata,"a",@progbits
.globl _Z15FMaxPoolForwardPKfPfPiiiiiiiii
.p2align 3, 0x0
_Z15FMaxPoolForwardPKfPfPiiiiiiiii:
.quad _Z30__device_stub__FMaxPoolForwardPKfPfPiiiiiiiii
.size _Z15FMaxPoolForwardPKfPfPiiiiiiiii, 8
.type _Z16FMaxPoolBackwardPfS_Piiiiiiiii,@object # @_Z16FMaxPoolBackwardPfS_Piiiiiiiii
.globl _Z16FMaxPoolBackwardPfS_Piiiiiiiii
.p2align 3, 0x0
_Z16FMaxPoolBackwardPfS_Piiiiiiiii:
.quad _Z31__device_stub__FMaxPoolBackwardPfS_Piiiiiiiii
.size _Z16FMaxPoolBackwardPfS_Piiiiiiiii, 8
.type _Z18FMaxPoolForwardFixPKfPfPiiiiiiiii,@object # @_Z18FMaxPoolForwardFixPKfPfPiiiiiiiii
.globl _Z18FMaxPoolForwardFixPKfPfPiiiiiiiii
.p2align 3, 0x0
_Z18FMaxPoolForwardFixPKfPfPiiiiiiiii:
.quad _Z33__device_stub__FMaxPoolForwardFixPKfPfPiiiiiiiii
.size _Z18FMaxPoolForwardFixPKfPfPiiiiiiiii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z15FMaxPoolForwardPKfPfPiiiiiiiii"
.size .L__unnamed_1, 35
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z16FMaxPoolBackwardPfS_Piiiiiiiii"
.size .L__unnamed_2, 35
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z18FMaxPoolForwardFixPKfPfPiiiiiiiii"
.size .L__unnamed_3, 38
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z30__device_stub__FMaxPoolForwardPKfPfPiiiiiiiii
.addrsig_sym _Z31__device_stub__FMaxPoolBackwardPfS_Piiiiiiiii
.addrsig_sym _Z33__device_stub__FMaxPoolForwardFixPKfPfPiiiiiiiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z15FMaxPoolForwardPKfPfPiiiiiiiii
.addrsig_sym _Z16FMaxPoolBackwardPfS_Piiiiiiiii
.addrsig_sym _Z18FMaxPoolForwardFixPKfPfPiiiiiiiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000991c4_00000000-6_Fmaxpool.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2059:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z48__device_stub__Z15FMaxPoolForwardPKfPfPiiiiiiiiiPKfPfPiiiiiiiii
.type _Z48__device_stub__Z15FMaxPoolForwardPKfPfPiiiiiiiiiPKfPfPiiiiiiiii, @function
_Z48__device_stub__Z15FMaxPoolForwardPKfPfPiiiiiiiiiPKfPfPiiiiiiiii:
.LFB2081:
.cfi_startproc
endbr64
subq $216, %rsp
.cfi_def_cfa_offset 224
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 200(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
leaq 224(%rsp), %rax
movq %rax, 160(%rsp)
leaq 232(%rsp), %rax
movq %rax, 168(%rsp)
leaq 240(%rsp), %rax
movq %rax, 176(%rsp)
leaq 248(%rsp), %rax
movq %rax, 184(%rsp)
leaq 256(%rsp), %rax
movq %rax, 192(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 200(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $216, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 232
pushq 56(%rsp)
.cfi_def_cfa_offset 240
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z15FMaxPoolForwardPKfPfPiiiiiiiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 224
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2081:
.size _Z48__device_stub__Z15FMaxPoolForwardPKfPfPiiiiiiiiiPKfPfPiiiiiiiii, .-_Z48__device_stub__Z15FMaxPoolForwardPKfPfPiiiiiiiiiPKfPfPiiiiiiiii
.globl _Z15FMaxPoolForwardPKfPfPiiiiiiiii
.type _Z15FMaxPoolForwardPKfPfPiiiiiiiii, @function
_Z15FMaxPoolForwardPKfPfPiiiiiiiii:
.LFB2082:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 40
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 48
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 56
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 64
call _Z48__device_stub__Z15FMaxPoolForwardPKfPfPiiiiiiiiiPKfPfPiiiiiiiii
addq $56, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2082:
.size _Z15FMaxPoolForwardPKfPfPiiiiiiiii, .-_Z15FMaxPoolForwardPKfPfPiiiiiiiii
.globl _Z48__device_stub__Z16FMaxPoolBackwardPfS_PiiiiiiiiiPfS_Piiiiiiiii
.type _Z48__device_stub__Z16FMaxPoolBackwardPfS_PiiiiiiiiiPfS_Piiiiiiiii, @function
_Z48__device_stub__Z16FMaxPoolBackwardPfS_PiiiiiiiiiPfS_Piiiiiiiii:
.LFB2083:
.cfi_startproc
endbr64
subq $216, %rsp
.cfi_def_cfa_offset 224
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 200(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
leaq 224(%rsp), %rax
movq %rax, 160(%rsp)
leaq 232(%rsp), %rax
movq %rax, 168(%rsp)
leaq 240(%rsp), %rax
movq %rax, 176(%rsp)
leaq 248(%rsp), %rax
movq %rax, 184(%rsp)
leaq 256(%rsp), %rax
movq %rax, 192(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 200(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $216, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 232
pushq 56(%rsp)
.cfi_def_cfa_offset 240
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z16FMaxPoolBackwardPfS_Piiiiiiiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 224
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z48__device_stub__Z16FMaxPoolBackwardPfS_PiiiiiiiiiPfS_Piiiiiiiii, .-_Z48__device_stub__Z16FMaxPoolBackwardPfS_PiiiiiiiiiPfS_Piiiiiiiii
.globl _Z16FMaxPoolBackwardPfS_Piiiiiiiii
.type _Z16FMaxPoolBackwardPfS_Piiiiiiiii, @function
_Z16FMaxPoolBackwardPfS_Piiiiiiiii:
.LFB2084:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 40
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 48
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 56
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 64
call _Z48__device_stub__Z16FMaxPoolBackwardPfS_PiiiiiiiiiPfS_Piiiiiiiii
addq $56, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z16FMaxPoolBackwardPfS_Piiiiiiiii, .-_Z16FMaxPoolBackwardPfS_Piiiiiiiii
.globl _Z51__device_stub__Z18FMaxPoolForwardFixPKfPfPiiiiiiiiiPKfPfPiiiiiiiii
.type _Z51__device_stub__Z18FMaxPoolForwardFixPKfPfPiiiiiiiiiPKfPfPiiiiiiiii, @function
_Z51__device_stub__Z18FMaxPoolForwardFixPKfPfPiiiiiiiiiPKfPfPiiiiiiiii:
.LFB2085:
.cfi_startproc
endbr64
subq $216, %rsp
.cfi_def_cfa_offset 224
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 200(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
leaq 224(%rsp), %rax
movq %rax, 160(%rsp)
leaq 232(%rsp), %rax
movq %rax, 168(%rsp)
leaq 240(%rsp), %rax
movq %rax, 176(%rsp)
leaq 248(%rsp), %rax
movq %rax, 184(%rsp)
leaq 256(%rsp), %rax
movq %rax, 192(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L23
.L19:
movq 200(%rsp), %rax
subq %fs:40, %rax
jne .L24
addq $216, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 232
pushq 56(%rsp)
.cfi_def_cfa_offset 240
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z18FMaxPoolForwardFixPKfPfPiiiiiiiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 224
jmp .L19
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2085:
.size _Z51__device_stub__Z18FMaxPoolForwardFixPKfPfPiiiiiiiiiPKfPfPiiiiiiiii, .-_Z51__device_stub__Z18FMaxPoolForwardFixPKfPfPiiiiiiiiiPKfPfPiiiiiiiii
.globl _Z18FMaxPoolForwardFixPKfPfPiiiiiiiii
.type _Z18FMaxPoolForwardFixPKfPfPiiiiiiiii, @function
_Z18FMaxPoolForwardFixPKfPfPiiiiiiiii:
.LFB2086:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 40
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 48
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 56
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 64
call _Z51__device_stub__Z18FMaxPoolForwardFixPKfPfPiiiiiiiiiPKfPfPiiiiiiiii
addq $56, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _Z18FMaxPoolForwardFixPKfPfPiiiiiiiii, .-_Z18FMaxPoolForwardFixPKfPfPiiiiiiiii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z18FMaxPoolForwardFixPKfPfPiiiiiiiii"
.align 8
.LC1:
.string "_Z16FMaxPoolBackwardPfS_Piiiiiiiii"
.align 8
.LC2:
.string "_Z15FMaxPoolForwardPKfPfPiiiiiiiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2088:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z18FMaxPoolForwardFixPKfPfPiiiiiiiii(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z16FMaxPoolBackwardPfS_Piiiiiiiii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z15FMaxPoolForwardPKfPfPiiiiiiiii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2088:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "Fmaxpool.hip"
.globl _Z30__device_stub__FMaxPoolForwardPKfPfPiiiiiiiii # -- Begin function _Z30__device_stub__FMaxPoolForwardPKfPfPiiiiiiiii
.p2align 4, 0x90
.type _Z30__device_stub__FMaxPoolForwardPKfPfPiiiiiiiii,@function
_Z30__device_stub__FMaxPoolForwardPKfPfPiiiiiiiii: # @_Z30__device_stub__FMaxPoolForwardPKfPfPiiiiiiiii
.cfi_startproc
# %bb.0:
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 192(%rsp), %rax
movq %rax, 144(%rsp)
leaq 200(%rsp), %rax
movq %rax, 152(%rsp)
leaq 208(%rsp), %rax
movq %rax, 160(%rsp)
leaq 216(%rsp), %rax
movq %rax, 168(%rsp)
leaq 224(%rsp), %rax
movq %rax, 176(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z15FMaxPoolForwardPKfPfPiiiiiiiii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $200, %rsp
.cfi_adjust_cfa_offset -200
retq
.Lfunc_end0:
.size _Z30__device_stub__FMaxPoolForwardPKfPfPiiiiiiiii, .Lfunc_end0-_Z30__device_stub__FMaxPoolForwardPKfPfPiiiiiiiii
.cfi_endproc
# -- End function
.globl _Z31__device_stub__FMaxPoolBackwardPfS_Piiiiiiiii # -- Begin function _Z31__device_stub__FMaxPoolBackwardPfS_Piiiiiiiii
.p2align 4, 0x90
.type _Z31__device_stub__FMaxPoolBackwardPfS_Piiiiiiiii,@function
_Z31__device_stub__FMaxPoolBackwardPfS_Piiiiiiiii: # @_Z31__device_stub__FMaxPoolBackwardPfS_Piiiiiiiii
.cfi_startproc
# %bb.0:
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 192(%rsp), %rax
movq %rax, 144(%rsp)
leaq 200(%rsp), %rax
movq %rax, 152(%rsp)
leaq 208(%rsp), %rax
movq %rax, 160(%rsp)
leaq 216(%rsp), %rax
movq %rax, 168(%rsp)
leaq 224(%rsp), %rax
movq %rax, 176(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z16FMaxPoolBackwardPfS_Piiiiiiiii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $200, %rsp
.cfi_adjust_cfa_offset -200
retq
.Lfunc_end1:
.size _Z31__device_stub__FMaxPoolBackwardPfS_Piiiiiiiii, .Lfunc_end1-_Z31__device_stub__FMaxPoolBackwardPfS_Piiiiiiiii
.cfi_endproc
# -- End function
.globl _Z33__device_stub__FMaxPoolForwardFixPKfPfPiiiiiiiii # -- Begin function _Z33__device_stub__FMaxPoolForwardFixPKfPfPiiiiiiiii
.p2align 4, 0x90
.type _Z33__device_stub__FMaxPoolForwardFixPKfPfPiiiiiiiii,@function
_Z33__device_stub__FMaxPoolForwardFixPKfPfPiiiiiiiii: # @_Z33__device_stub__FMaxPoolForwardFixPKfPfPiiiiiiiii
.cfi_startproc
# %bb.0:
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 192(%rsp), %rax
movq %rax, 144(%rsp)
leaq 200(%rsp), %rax
movq %rax, 152(%rsp)
leaq 208(%rsp), %rax
movq %rax, 160(%rsp)
leaq 216(%rsp), %rax
movq %rax, 168(%rsp)
leaq 224(%rsp), %rax
movq %rax, 176(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z18FMaxPoolForwardFixPKfPfPiiiiiiiii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $200, %rsp
.cfi_adjust_cfa_offset -200
retq
.Lfunc_end2:
.size _Z33__device_stub__FMaxPoolForwardFixPKfPfPiiiiiiiii, .Lfunc_end2-_Z33__device_stub__FMaxPoolForwardFixPKfPfPiiiiiiiii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15FMaxPoolForwardPKfPfPiiiiiiiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z16FMaxPoolBackwardPfS_Piiiiiiiii, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z18FMaxPoolForwardFixPKfPfPiiiiiiiii, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z15FMaxPoolForwardPKfPfPiiiiiiiii,@object # @_Z15FMaxPoolForwardPKfPfPiiiiiiiii
.section .rodata,"a",@progbits
.globl _Z15FMaxPoolForwardPKfPfPiiiiiiiii
.p2align 3, 0x0
_Z15FMaxPoolForwardPKfPfPiiiiiiiii:
.quad _Z30__device_stub__FMaxPoolForwardPKfPfPiiiiiiiii
.size _Z15FMaxPoolForwardPKfPfPiiiiiiiii, 8
.type _Z16FMaxPoolBackwardPfS_Piiiiiiiii,@object # @_Z16FMaxPoolBackwardPfS_Piiiiiiiii
.globl _Z16FMaxPoolBackwardPfS_Piiiiiiiii
.p2align 3, 0x0
_Z16FMaxPoolBackwardPfS_Piiiiiiiii:
.quad _Z31__device_stub__FMaxPoolBackwardPfS_Piiiiiiiii
.size _Z16FMaxPoolBackwardPfS_Piiiiiiiii, 8
.type _Z18FMaxPoolForwardFixPKfPfPiiiiiiiii,@object # @_Z18FMaxPoolForwardFixPKfPfPiiiiiiiii
.globl _Z18FMaxPoolForwardFixPKfPfPiiiiiiiii
.p2align 3, 0x0
_Z18FMaxPoolForwardFixPKfPfPiiiiiiiii:
.quad _Z33__device_stub__FMaxPoolForwardFixPKfPfPiiiiiiiii
.size _Z18FMaxPoolForwardFixPKfPfPiiiiiiiii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z15FMaxPoolForwardPKfPfPiiiiiiiii"
.size .L__unnamed_1, 35
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z16FMaxPoolBackwardPfS_Piiiiiiiii"
.size .L__unnamed_2, 35
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z18FMaxPoolForwardFixPKfPfPiiiiiiiii"
.size .L__unnamed_3, 38
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z30__device_stub__FMaxPoolForwardPKfPfPiiiiiiiii
.addrsig_sym _Z31__device_stub__FMaxPoolBackwardPfS_Piiiiiiiii
.addrsig_sym _Z33__device_stub__FMaxPoolForwardFixPKfPfPiiiiiiiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z15FMaxPoolForwardPKfPfPiiiiiiiii
.addrsig_sym _Z16FMaxPoolBackwardPfS_Piiiiiiiii
.addrsig_sym _Z18FMaxPoolForwardFixPKfPfPiiiiiiiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | // Jordan Cazamias
// CUDA World Gen 2015
#include <iostream>
#include <ctime>
#include <stdlib.h>
#include "cuda_runtime.h"
#include "cuda_runtime_api.h"
using namespace std;
__global__ void AddInts(int *a, int *b, int count)
{
int id = blockIdx.x * blockDim.x + threadIdx.x;
if (id < count)
{
a[id] += b[id];
}
//printf("id: %d\n", id);
}
/*
int main()
{
srand(time(NULL));
int count = 100;
int *h_a = new int[count];
int *h_b = new int[count];
for (int i = 0; i < count; i++)
{
h_a[i] = rand() % 1000;
h_b[i] = rand() % 1000;
}
cout << "Prior to addition:" << endl;
for (int i = 0; i < 5; i++)
{
cout << i << ": " << h_a[i] << " " << h_b[i] << endl;
}
int *d_a, *d_b;
if (cudaMalloc(&d_a, sizeof(int) * count) != cudaSuccess)
{
cout << "CUDA Malloc failed!";
return 1;
}
if (cudaMalloc(&d_b, sizeof(int) * count) != cudaSuccess)
{
cout << "CUDA Malloc failed!";
cudaFree(d_a);
return 1;
}
if (cudaMemcpy(d_a, h_a, sizeof(int)*count, cudaMemcpyHostToDevice) != cudaSuccess)
{
cout << "CUDA copy to device failed!";
cudaFree(d_a);
cudaFree(d_b);
return 1;
}
if (cudaMemcpy(d_b, h_b, sizeof(int)*count, cudaMemcpyHostToDevice) != cudaSuccess)
{
cout << "CUDA copy to device failed!";
cudaFree(d_a);
cudaFree(d_b);
return 1;
}
// Add integers together
int blocks = count / 256 + 1;
int threads = 256;
AddInts<<<blocks, threads>>>(d_a, d_b, count);
if (cudaMemcpy(h_a, d_a, sizeof(int)*count, cudaMemcpyDeviceToHost) != cudaSuccess)
{
cout << "CUDA copy to host failed!";
cudaFree(d_a);
cudaFree(d_b);
return 1;
}
if (cudaMemcpy(h_a, d_a, sizeof(int)*count, cudaMemcpyDeviceToHost) != cudaSuccess)
{
cout << "CUDA copy to host failed!";
cudaFree(d_a);
cudaFree(d_b);
return 1;
}
for (int i = 0; i < 5; i++)
{
cout << "Ans: " << h_a[i] << endl;
}
delete[] h_a;
delete[] h_b;
return 0;
}
*/ | code for sm_80
Function : _Z7AddIntsPiS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R4, R4, c[0x0][0x0], R3 ; /* 0x0000000004047a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R4, c[0x0][0x170], PT ; /* 0x00005c0004007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R2, R4, R5, c[0x0][0x168] ; /* 0x00005a0004027625 */
/* 0x000fc800078e0205 */
/*0090*/ IMAD.WIDE R4, R4, R5, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fe400078e0205 */
/*00a0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R0, [R4.64] ; /* 0x0000000404007981 */
/* 0x000ea4000c1e1900 */
/*00c0*/ IADD3 R7, R0, R3, RZ ; /* 0x0000000300077210 */
/* 0x004fca0007ffe0ff */
/*00d0*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x000fe2000c101904 */
/*00e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00f0*/ BRA 0xf0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | // Jordan Cazamias
// CUDA World Gen 2015
#include <iostream>
#include <ctime>
#include <stdlib.h>
#include "cuda_runtime.h"
#include "cuda_runtime_api.h"
using namespace std;
__global__ void AddInts(int *a, int *b, int count)
{
int id = blockIdx.x * blockDim.x + threadIdx.x;
if (id < count)
{
a[id] += b[id];
}
//printf("id: %d\n", id);
}
/*
int main()
{
srand(time(NULL));
int count = 100;
int *h_a = new int[count];
int *h_b = new int[count];
for (int i = 0; i < count; i++)
{
h_a[i] = rand() % 1000;
h_b[i] = rand() % 1000;
}
cout << "Prior to addition:" << endl;
for (int i = 0; i < 5; i++)
{
cout << i << ": " << h_a[i] << " " << h_b[i] << endl;
}
int *d_a, *d_b;
if (cudaMalloc(&d_a, sizeof(int) * count) != cudaSuccess)
{
cout << "CUDA Malloc failed!";
return 1;
}
if (cudaMalloc(&d_b, sizeof(int) * count) != cudaSuccess)
{
cout << "CUDA Malloc failed!";
cudaFree(d_a);
return 1;
}
if (cudaMemcpy(d_a, h_a, sizeof(int)*count, cudaMemcpyHostToDevice) != cudaSuccess)
{
cout << "CUDA copy to device failed!";
cudaFree(d_a);
cudaFree(d_b);
return 1;
}
if (cudaMemcpy(d_b, h_b, sizeof(int)*count, cudaMemcpyHostToDevice) != cudaSuccess)
{
cout << "CUDA copy to device failed!";
cudaFree(d_a);
cudaFree(d_b);
return 1;
}
// Add integers together
int blocks = count / 256 + 1;
int threads = 256;
AddInts<<<blocks, threads>>>(d_a, d_b, count);
if (cudaMemcpy(h_a, d_a, sizeof(int)*count, cudaMemcpyDeviceToHost) != cudaSuccess)
{
cout << "CUDA copy to host failed!";
cudaFree(d_a);
cudaFree(d_b);
return 1;
}
if (cudaMemcpy(h_a, d_a, sizeof(int)*count, cudaMemcpyDeviceToHost) != cudaSuccess)
{
cout << "CUDA copy to host failed!";
cudaFree(d_a);
cudaFree(d_b);
return 1;
}
for (int i = 0; i < 5; i++)
{
cout << "Ans: " << h_a[i] << endl;
}
delete[] h_a;
delete[] h_b;
return 0;
}
*/ | .file "tmpxft_0010d767_00000000-6_tut2.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3671:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3671:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z29__device_stub__Z7AddIntsPiS_iPiS_i
.type _Z29__device_stub__Z7AddIntsPiS_iPiS_i, @function
_Z29__device_stub__Z7AddIntsPiS_iPiS_i:
.LFB3693:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z7AddIntsPiS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3693:
.size _Z29__device_stub__Z7AddIntsPiS_iPiS_i, .-_Z29__device_stub__Z7AddIntsPiS_iPiS_i
.globl _Z7AddIntsPiS_i
.type _Z7AddIntsPiS_i, @function
_Z7AddIntsPiS_i:
.LFB3694:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z7AddIntsPiS_iPiS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3694:
.size _Z7AddIntsPiS_i, .-_Z7AddIntsPiS_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z7AddIntsPiS_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3696:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z7AddIntsPiS_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3696:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | // Jordan Cazamias
// CUDA World Gen 2015
#include <iostream>
#include <ctime>
#include <stdlib.h>
#include "cuda_runtime.h"
#include "cuda_runtime_api.h"
using namespace std;
__global__ void AddInts(int *a, int *b, int count)
{
int id = blockIdx.x * blockDim.x + threadIdx.x;
if (id < count)
{
a[id] += b[id];
}
//printf("id: %d\n", id);
}
/*
int main()
{
srand(time(NULL));
int count = 100;
int *h_a = new int[count];
int *h_b = new int[count];
for (int i = 0; i < count; i++)
{
h_a[i] = rand() % 1000;
h_b[i] = rand() % 1000;
}
cout << "Prior to addition:" << endl;
for (int i = 0; i < 5; i++)
{
cout << i << ": " << h_a[i] << " " << h_b[i] << endl;
}
int *d_a, *d_b;
if (cudaMalloc(&d_a, sizeof(int) * count) != cudaSuccess)
{
cout << "CUDA Malloc failed!";
return 1;
}
if (cudaMalloc(&d_b, sizeof(int) * count) != cudaSuccess)
{
cout << "CUDA Malloc failed!";
cudaFree(d_a);
return 1;
}
if (cudaMemcpy(d_a, h_a, sizeof(int)*count, cudaMemcpyHostToDevice) != cudaSuccess)
{
cout << "CUDA copy to device failed!";
cudaFree(d_a);
cudaFree(d_b);
return 1;
}
if (cudaMemcpy(d_b, h_b, sizeof(int)*count, cudaMemcpyHostToDevice) != cudaSuccess)
{
cout << "CUDA copy to device failed!";
cudaFree(d_a);
cudaFree(d_b);
return 1;
}
// Add integers together
int blocks = count / 256 + 1;
int threads = 256;
AddInts<<<blocks, threads>>>(d_a, d_b, count);
if (cudaMemcpy(h_a, d_a, sizeof(int)*count, cudaMemcpyDeviceToHost) != cudaSuccess)
{
cout << "CUDA copy to host failed!";
cudaFree(d_a);
cudaFree(d_b);
return 1;
}
if (cudaMemcpy(h_a, d_a, sizeof(int)*count, cudaMemcpyDeviceToHost) != cudaSuccess)
{
cout << "CUDA copy to host failed!";
cudaFree(d_a);
cudaFree(d_b);
return 1;
}
for (int i = 0; i < 5; i++)
{
cout << "Ans: " << h_a[i] << endl;
}
delete[] h_a;
delete[] h_b;
return 0;
}
*/ | // Jordan Cazamias
// CUDA World Gen 2015
#include <iostream>
#include <ctime>
#include <stdlib.h>
#include "hip/hip_runtime.h"
#include "hip/hip_runtime_api.h"
using namespace std;
__global__ void AddInts(int *a, int *b, int count)
{
int id = blockIdx.x * blockDim.x + threadIdx.x;
if (id < count)
{
a[id] += b[id];
}
//printf("id: %d\n", id);
}
/*
int main()
{
srand(time(NULL));
int count = 100;
int *h_a = new int[count];
int *h_b = new int[count];
for (int i = 0; i < count; i++)
{
h_a[i] = rand() % 1000;
h_b[i] = rand() % 1000;
}
cout << "Prior to addition:" << endl;
for (int i = 0; i < 5; i++)
{
cout << i << ": " << h_a[i] << " " << h_b[i] << endl;
}
int *d_a, *d_b;
if (cudaMalloc(&d_a, sizeof(int) * count) != cudaSuccess)
{
cout << "CUDA Malloc failed!";
return 1;
}
if (cudaMalloc(&d_b, sizeof(int) * count) != cudaSuccess)
{
cout << "CUDA Malloc failed!";
cudaFree(d_a);
return 1;
}
if (cudaMemcpy(d_a, h_a, sizeof(int)*count, cudaMemcpyHostToDevice) != cudaSuccess)
{
cout << "CUDA copy to device failed!";
cudaFree(d_a);
cudaFree(d_b);
return 1;
}
if (cudaMemcpy(d_b, h_b, sizeof(int)*count, cudaMemcpyHostToDevice) != cudaSuccess)
{
cout << "CUDA copy to device failed!";
cudaFree(d_a);
cudaFree(d_b);
return 1;
}
// Add integers together
int blocks = count / 256 + 1;
int threads = 256;
AddInts<<<blocks, threads>>>(d_a, d_b, count);
if (cudaMemcpy(h_a, d_a, sizeof(int)*count, cudaMemcpyDeviceToHost) != cudaSuccess)
{
cout << "CUDA copy to host failed!";
cudaFree(d_a);
cudaFree(d_b);
return 1;
}
if (cudaMemcpy(h_a, d_a, sizeof(int)*count, cudaMemcpyDeviceToHost) != cudaSuccess)
{
cout << "CUDA copy to host failed!";
cudaFree(d_a);
cudaFree(d_b);
return 1;
}
for (int i = 0; i < 5; i++)
{
cout << "Ans: " << h_a[i] << endl;
}
delete[] h_a;
delete[] h_b;
return 0;
}
*/ |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | // Jordan Cazamias
// CUDA World Gen 2015
#include <iostream>
#include <ctime>
#include <stdlib.h>
#include "hip/hip_runtime.h"
#include "hip/hip_runtime_api.h"
using namespace std;
__global__ void AddInts(int *a, int *b, int count)
{
int id = blockIdx.x * blockDim.x + threadIdx.x;
if (id < count)
{
a[id] += b[id];
}
//printf("id: %d\n", id);
}
/*
int main()
{
srand(time(NULL));
int count = 100;
int *h_a = new int[count];
int *h_b = new int[count];
for (int i = 0; i < count; i++)
{
h_a[i] = rand() % 1000;
h_b[i] = rand() % 1000;
}
cout << "Prior to addition:" << endl;
for (int i = 0; i < 5; i++)
{
cout << i << ": " << h_a[i] << " " << h_b[i] << endl;
}
int *d_a, *d_b;
if (cudaMalloc(&d_a, sizeof(int) * count) != cudaSuccess)
{
cout << "CUDA Malloc failed!";
return 1;
}
if (cudaMalloc(&d_b, sizeof(int) * count) != cudaSuccess)
{
cout << "CUDA Malloc failed!";
cudaFree(d_a);
return 1;
}
if (cudaMemcpy(d_a, h_a, sizeof(int)*count, cudaMemcpyHostToDevice) != cudaSuccess)
{
cout << "CUDA copy to device failed!";
cudaFree(d_a);
cudaFree(d_b);
return 1;
}
if (cudaMemcpy(d_b, h_b, sizeof(int)*count, cudaMemcpyHostToDevice) != cudaSuccess)
{
cout << "CUDA copy to device failed!";
cudaFree(d_a);
cudaFree(d_b);
return 1;
}
// Add integers together
int blocks = count / 256 + 1;
int threads = 256;
AddInts<<<blocks, threads>>>(d_a, d_b, count);
if (cudaMemcpy(h_a, d_a, sizeof(int)*count, cudaMemcpyDeviceToHost) != cudaSuccess)
{
cout << "CUDA copy to host failed!";
cudaFree(d_a);
cudaFree(d_b);
return 1;
}
if (cudaMemcpy(h_a, d_a, sizeof(int)*count, cudaMemcpyDeviceToHost) != cudaSuccess)
{
cout << "CUDA copy to host failed!";
cudaFree(d_a);
cudaFree(d_b);
return 1;
}
for (int i = 0; i < 5; i++)
{
cout << "Ans: " << h_a[i] << endl;
}
delete[] h_a;
delete[] h_b;
return 0;
}
*/ | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z7AddIntsPiS_i
.globl _Z7AddIntsPiS_i
.p2align 8
.type _Z7AddIntsPiS_i,@function
_Z7AddIntsPiS_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[0:3], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[0:1], off
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v2, v3, v2
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7AddIntsPiS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z7AddIntsPiS_i, .Lfunc_end0-_Z7AddIntsPiS_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7AddIntsPiS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z7AddIntsPiS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | // Jordan Cazamias
// CUDA World Gen 2015
#include <iostream>
#include <ctime>
#include <stdlib.h>
#include "hip/hip_runtime.h"
#include "hip/hip_runtime_api.h"
using namespace std;
__global__ void AddInts(int *a, int *b, int count)
{
int id = blockIdx.x * blockDim.x + threadIdx.x;
if (id < count)
{
a[id] += b[id];
}
//printf("id: %d\n", id);
}
/*
int main()
{
srand(time(NULL));
int count = 100;
int *h_a = new int[count];
int *h_b = new int[count];
for (int i = 0; i < count; i++)
{
h_a[i] = rand() % 1000;
h_b[i] = rand() % 1000;
}
cout << "Prior to addition:" << endl;
for (int i = 0; i < 5; i++)
{
cout << i << ": " << h_a[i] << " " << h_b[i] << endl;
}
int *d_a, *d_b;
if (cudaMalloc(&d_a, sizeof(int) * count) != cudaSuccess)
{
cout << "CUDA Malloc failed!";
return 1;
}
if (cudaMalloc(&d_b, sizeof(int) * count) != cudaSuccess)
{
cout << "CUDA Malloc failed!";
cudaFree(d_a);
return 1;
}
if (cudaMemcpy(d_a, h_a, sizeof(int)*count, cudaMemcpyHostToDevice) != cudaSuccess)
{
cout << "CUDA copy to device failed!";
cudaFree(d_a);
cudaFree(d_b);
return 1;
}
if (cudaMemcpy(d_b, h_b, sizeof(int)*count, cudaMemcpyHostToDevice) != cudaSuccess)
{
cout << "CUDA copy to device failed!";
cudaFree(d_a);
cudaFree(d_b);
return 1;
}
// Add integers together
int blocks = count / 256 + 1;
int threads = 256;
AddInts<<<blocks, threads>>>(d_a, d_b, count);
if (cudaMemcpy(h_a, d_a, sizeof(int)*count, cudaMemcpyDeviceToHost) != cudaSuccess)
{
cout << "CUDA copy to host failed!";
cudaFree(d_a);
cudaFree(d_b);
return 1;
}
if (cudaMemcpy(h_a, d_a, sizeof(int)*count, cudaMemcpyDeviceToHost) != cudaSuccess)
{
cout << "CUDA copy to host failed!";
cudaFree(d_a);
cudaFree(d_b);
return 1;
}
for (int i = 0; i < 5; i++)
{
cout << "Ans: " << h_a[i] << endl;
}
delete[] h_a;
delete[] h_b;
return 0;
}
*/ | .text
.file "tut2.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z22__device_stub__AddIntsPiS_i # -- Begin function _Z22__device_stub__AddIntsPiS_i
.p2align 4, 0x90
.type _Z22__device_stub__AddIntsPiS_i,@function
_Z22__device_stub__AddIntsPiS_i: # @_Z22__device_stub__AddIntsPiS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z7AddIntsPiS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z22__device_stub__AddIntsPiS_i, .Lfunc_end0-_Z22__device_stub__AddIntsPiS_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7AddIntsPiS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z7AddIntsPiS_i,@object # @_Z7AddIntsPiS_i
.section .rodata,"a",@progbits
.globl _Z7AddIntsPiS_i
.p2align 3, 0x0
_Z7AddIntsPiS_i:
.quad _Z22__device_stub__AddIntsPiS_i
.size _Z7AddIntsPiS_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z7AddIntsPiS_i"
.size .L__unnamed_1, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__AddIntsPiS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7AddIntsPiS_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z7AddIntsPiS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R4, R4, c[0x0][0x0], R3 ; /* 0x0000000004047a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R4, c[0x0][0x170], PT ; /* 0x00005c0004007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R2, R4, R5, c[0x0][0x168] ; /* 0x00005a0004027625 */
/* 0x000fc800078e0205 */
/*0090*/ IMAD.WIDE R4, R4, R5, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fe400078e0205 */
/*00a0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R0, [R4.64] ; /* 0x0000000404007981 */
/* 0x000ea4000c1e1900 */
/*00c0*/ IADD3 R7, R0, R3, RZ ; /* 0x0000000300077210 */
/* 0x004fca0007ffe0ff */
/*00d0*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x000fe2000c101904 */
/*00e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00f0*/ BRA 0xf0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z7AddIntsPiS_i
.globl _Z7AddIntsPiS_i
.p2align 8
.type _Z7AddIntsPiS_i,@function
_Z7AddIntsPiS_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[0:3], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[0:1], off
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v2, v3, v2
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7AddIntsPiS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z7AddIntsPiS_i, .Lfunc_end0-_Z7AddIntsPiS_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7AddIntsPiS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z7AddIntsPiS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0010d767_00000000-6_tut2.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3671:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3671:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z29__device_stub__Z7AddIntsPiS_iPiS_i
.type _Z29__device_stub__Z7AddIntsPiS_iPiS_i, @function
_Z29__device_stub__Z7AddIntsPiS_iPiS_i:
.LFB3693:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z7AddIntsPiS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3693:
.size _Z29__device_stub__Z7AddIntsPiS_iPiS_i, .-_Z29__device_stub__Z7AddIntsPiS_iPiS_i
.globl _Z7AddIntsPiS_i
.type _Z7AddIntsPiS_i, @function
_Z7AddIntsPiS_i:
.LFB3694:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z7AddIntsPiS_iPiS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3694:
.size _Z7AddIntsPiS_i, .-_Z7AddIntsPiS_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z7AddIntsPiS_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3696:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z7AddIntsPiS_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3696:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "tut2.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z22__device_stub__AddIntsPiS_i # -- Begin function _Z22__device_stub__AddIntsPiS_i
.p2align 4, 0x90
.type _Z22__device_stub__AddIntsPiS_i,@function
_Z22__device_stub__AddIntsPiS_i: # @_Z22__device_stub__AddIntsPiS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z7AddIntsPiS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z22__device_stub__AddIntsPiS_i, .Lfunc_end0-_Z22__device_stub__AddIntsPiS_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7AddIntsPiS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z7AddIntsPiS_i,@object # @_Z7AddIntsPiS_i
.section .rodata,"a",@progbits
.globl _Z7AddIntsPiS_i
.p2align 3, 0x0
_Z7AddIntsPiS_i:
.quad _Z22__device_stub__AddIntsPiS_i
.size _Z7AddIntsPiS_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z7AddIntsPiS_i"
.size .L__unnamed_1, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__AddIntsPiS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7AddIntsPiS_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include<stdlib.h>
#include<stdio.h>
/* The purpose of these microkernels is to
offer the user a sanity check. These microkernels
take the exact same parameters as their "real"
implementations and perform simple modifications
so the user can be sure the kernel is unpacking
and modifying the parameters the correct way. */
__device__ void ComputeTest(void* params){
//Params| &table | offset |
//Bytes | 8 | 4 |
void *table = *((void**)params);
int offset = *((int*)(((void**)params)+1));
//Extract all the values.
int np = *((int*) table);
int nd = *(((int*) table)+1);
int size = np * nd;
double *mass = (double*)(((int*)table)+2);
double *pos = mass + 1;
double *vel = pos + size;
double *acc = vel + size;
double *f = acc + size;
double *pe = f + size;
double *ke = pe + size;
int j;
int tid = threadIdx.x % 32;
int k = offset + tid;
//Compute all the potential energy and forces.
for(j=0; j<np; j++){
if(k == j){ continue; }
int index = j + k *nd;
f[index] += 1;
pe[index] += 1;
ke[index] += 1;
}
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include<stdlib.h>
#include<stdio.h>
/* The purpose of these microkernels is to
offer the user a sanity check. These microkernels
take the exact same parameters as their "real"
implementations and perform simple modifications
so the user can be sure the kernel is unpacking
and modifying the parameters the correct way. */
__device__ void ComputeTest(void* params){
//Params| &table | offset |
//Bytes | 8 | 4 |
void *table = *((void**)params);
int offset = *((int*)(((void**)params)+1));
//Extract all the values.
int np = *((int*) table);
int nd = *(((int*) table)+1);
int size = np * nd;
double *mass = (double*)(((int*)table)+2);
double *pos = mass + 1;
double *vel = pos + size;
double *acc = vel + size;
double *f = acc + size;
double *pe = f + size;
double *ke = pe + size;
int j;
int tid = threadIdx.x % 32;
int k = offset + tid;
//Compute all the potential energy and forces.
for(j=0; j<np; j++){
if(k == j){ continue; }
int index = j + k *nd;
f[index] += 1;
pe[index] += 1;
ke[index] += 1;
}
} | .file "tmpxft_0015d96c_00000000-6_MDFake.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z11ComputeTestPv
.type _Z11ComputeTestPv, @function
_Z11ComputeTestPv:
.LFB2057:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size _Z11ComputeTestPv, .-_Z11ComputeTestPv
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include<stdlib.h>
#include<stdio.h>
/* The purpose of these microkernels is to
offer the user a sanity check. These microkernels
take the exact same parameters as their "real"
implementations and perform simple modifications
so the user can be sure the kernel is unpacking
and modifying the parameters the correct way. */
__device__ void ComputeTest(void* params){
//Params| &table | offset |
//Bytes | 8 | 4 |
void *table = *((void**)params);
int offset = *((int*)(((void**)params)+1));
//Extract all the values.
int np = *((int*) table);
int nd = *(((int*) table)+1);
int size = np * nd;
double *mass = (double*)(((int*)table)+2);
double *pos = mass + 1;
double *vel = pos + size;
double *acc = vel + size;
double *f = acc + size;
double *pe = f + size;
double *ke = pe + size;
int j;
int tid = threadIdx.x % 32;
int k = offset + tid;
//Compute all the potential energy and forces.
for(j=0; j<np; j++){
if(k == j){ continue; }
int index = j + k *nd;
f[index] += 1;
pe[index] += 1;
ke[index] += 1;
}
} | #include <hip/hip_runtime.h>
#include<stdlib.h>
#include<stdio.h>
/* The purpose of these microkernels is to
offer the user a sanity check. These microkernels
take the exact same parameters as their "real"
implementations and perform simple modifications
so the user can be sure the kernel is unpacking
and modifying the parameters the correct way. */
__device__ void ComputeTest(void* params){
//Params| &table | offset |
//Bytes | 8 | 4 |
void *table = *((void**)params);
int offset = *((int*)(((void**)params)+1));
//Extract all the values.
int np = *((int*) table);
int nd = *(((int*) table)+1);
int size = np * nd;
double *mass = (double*)(((int*)table)+2);
double *pos = mass + 1;
double *vel = pos + size;
double *acc = vel + size;
double *f = acc + size;
double *pe = f + size;
double *ke = pe + size;
int j;
int tid = threadIdx.x % 32;
int k = offset + tid;
//Compute all the potential energy and forces.
for(j=0; j<np; j++){
if(k == j){ continue; }
int index = j + k *nd;
f[index] += 1;
pe[index] += 1;
ke[index] += 1;
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include<stdlib.h>
#include<stdio.h>
/* The purpose of these microkernels is to
offer the user a sanity check. These microkernels
take the exact same parameters as their "real"
implementations and perform simple modifications
so the user can be sure the kernel is unpacking
and modifying the parameters the correct way. */
__device__ void ComputeTest(void* params){
//Params| &table | offset |
//Bytes | 8 | 4 |
void *table = *((void**)params);
int offset = *((int*)(((void**)params)+1));
//Extract all the values.
int np = *((int*) table);
int nd = *(((int*) table)+1);
int size = np * nd;
double *mass = (double*)(((int*)table)+2);
double *pos = mass + 1;
double *vel = pos + size;
double *acc = vel + size;
double *f = acc + size;
double *pe = f + size;
double *ke = pe + size;
int j;
int tid = threadIdx.x % 32;
int k = offset + tid;
//Compute all the potential energy and forces.
for(j=0; j<np; j++){
if(k == j){ continue; }
int index = j + k *nd;
f[index] += 1;
pe[index] += 1;
ke[index] += 1;
}
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include<stdlib.h>
#include<stdio.h>
/* The purpose of these microkernels is to
offer the user a sanity check. These microkernels
take the exact same parameters as their "real"
implementations and perform simple modifications
so the user can be sure the kernel is unpacking
and modifying the parameters the correct way. */
__device__ void ComputeTest(void* params){
//Params| &table | offset |
//Bytes | 8 | 4 |
void *table = *((void**)params);
int offset = *((int*)(((void**)params)+1));
//Extract all the values.
int np = *((int*) table);
int nd = *(((int*) table)+1);
int size = np * nd;
double *mass = (double*)(((int*)table)+2);
double *pos = mass + 1;
double *vel = pos + size;
double *acc = vel + size;
double *f = acc + size;
double *pe = f + size;
double *ke = pe + size;
int j;
int tid = threadIdx.x % 32;
int k = offset + tid;
//Compute all the potential energy and forces.
for(j=0; j<np; j++){
if(k == j){ continue; }
int index = j + k *nd;
f[index] += 1;
pe[index] += 1;
ke[index] += 1;
}
} | .text
.file "MDFake.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0015d96c_00000000-6_MDFake.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z11ComputeTestPv
.type _Z11ComputeTestPv, @function
_Z11ComputeTestPv:
.LFB2057:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size _Z11ComputeTestPv, .-_Z11ComputeTestPv
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "MDFake.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <stdlib.h>
int main()
{
printf("Hello World !\n");
exit(EXIT_SUCCESS);
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <stdlib.h>
int main()
{
printf("Hello World !\n");
exit(EXIT_SUCCESS);
} | .file "tmpxft_00045d71_00000000-6_hello_world.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Hello World !\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <stdlib.h>
int main()
{
printf("Hello World !\n");
exit(EXIT_SUCCESS);
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
int main()
{
printf("Hello World !\n");
exit(EXIT_SUCCESS);
} |
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