system stringclasses 7 values | input stringlengths 10 94.5k | output stringlengths 14 55.5k |
|---|---|---|
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
int main()
{
printf("Hello World !\n");
exit(EXIT_SUCCESS);
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
int main()
{
printf("Hello World !\n");
exit(EXIT_SUCCESS);
} | .text
.file "hello_world.hip"
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
movl $.Lstr, %edi
callq puts@PLT
xorl %edi, %edi
callq exit
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Hello World !"
.size .Lstr, 14
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00045d71_00000000-6_hello_world.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Hello World !\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "hello_world.hip"
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
movl $.Lstr, %edi
callq puts@PLT
xorl %edi, %edi
callq exit
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Hello World !"
.size .Lstr, 14
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
////////////////////////////////////////////////////////////////////////////
//
// Copyright 1993-2015 NVIDIA Corporation. All rights reserved.
//
// Please refer to the NVIDIA end user license agreement (EULA) associated
// with this source code for terms and conditions that govern your use of
// this software. Any use, reproduction, disclosure, or distribution of
// this software and related documentation outside the terms of the EULA
// is strictly prohibited.
//
////////////////////////////////////////////////////////////////////////////
//
// This sample illustrates the usage of CUDA events for both GPU timing and
// overlapping CPU and GPU execution. Events are inserted into a stream
// of CUDA calls. Since CUDA stream calls are asynchronous, the CPU can
// perform computations while GPU is executing (including DMA memcopies
// between the host and device). CPU can query CUDA events to determine
// whether GPU has completed tasks.
//
// includes, system
// includes CUDA Runtime
// includes, project
__global__ void increment_kernel(int *g_data, int inc_value)
{
int idx = blockIdx.x * blockDim.x + threadIdx.x;
g_data[idx] = g_data[idx] + inc_value;
} | code for sm_80
Function : _Z16increment_kernelPii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R2, R2, c[0x0][0x0], R3 ; /* 0x0000000002027a24 */
/* 0x001fca00078e0203 */
/*0060*/ IMAD.WIDE R2, R2, R5, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0205 */
/*0070*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea4000c1e1900 */
/*0080*/ IADD3 R5, R0, c[0x0][0x168], RZ ; /* 0x00005a0000057a10 */
/* 0x004fca0007ffe0ff */
/*0090*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*00a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00b0*/ BRA 0xb0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
////////////////////////////////////////////////////////////////////////////
//
// Copyright 1993-2015 NVIDIA Corporation. All rights reserved.
//
// Please refer to the NVIDIA end user license agreement (EULA) associated
// with this source code for terms and conditions that govern your use of
// this software. Any use, reproduction, disclosure, or distribution of
// this software and related documentation outside the terms of the EULA
// is strictly prohibited.
//
////////////////////////////////////////////////////////////////////////////
//
// This sample illustrates the usage of CUDA events for both GPU timing and
// overlapping CPU and GPU execution. Events are inserted into a stream
// of CUDA calls. Since CUDA stream calls are asynchronous, the CPU can
// perform computations while GPU is executing (including DMA memcopies
// between the host and device). CPU can query CUDA events to determine
// whether GPU has completed tasks.
//
// includes, system
// includes CUDA Runtime
// includes, project
__global__ void increment_kernel(int *g_data, int inc_value)
{
int idx = blockIdx.x * blockDim.x + threadIdx.x;
g_data[idx] = g_data[idx] + inc_value;
} | .file "tmpxft_00124e3e_00000000-6_increment_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z37__device_stub__Z16increment_kernelPiiPii
.type _Z37__device_stub__Z16increment_kernelPiiPii, @function
_Z37__device_stub__Z16increment_kernelPiiPii:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z16increment_kernelPii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z37__device_stub__Z16increment_kernelPiiPii, .-_Z37__device_stub__Z16increment_kernelPiiPii
.globl _Z16increment_kernelPii
.type _Z16increment_kernelPii, @function
_Z16increment_kernelPii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z37__device_stub__Z16increment_kernelPiiPii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z16increment_kernelPii, .-_Z16increment_kernelPii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z16increment_kernelPii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z16increment_kernelPii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
////////////////////////////////////////////////////////////////////////////
//
// Copyright 1993-2015 NVIDIA Corporation. All rights reserved.
//
// Please refer to the NVIDIA end user license agreement (EULA) associated
// with this source code for terms and conditions that govern your use of
// this software. Any use, reproduction, disclosure, or distribution of
// this software and related documentation outside the terms of the EULA
// is strictly prohibited.
//
////////////////////////////////////////////////////////////////////////////
//
// This sample illustrates the usage of CUDA events for both GPU timing and
// overlapping CPU and GPU execution. Events are inserted into a stream
// of CUDA calls. Since CUDA stream calls are asynchronous, the CPU can
// perform computations while GPU is executing (including DMA memcopies
// between the host and device). CPU can query CUDA events to determine
// whether GPU has completed tasks.
//
// includes, system
// includes CUDA Runtime
// includes, project
__global__ void increment_kernel(int *g_data, int inc_value)
{
int idx = blockIdx.x * blockDim.x + threadIdx.x;
g_data[idx] = g_data[idx] + inc_value;
} | #include <hip/hip_runtime.h>
#include "includes.h"
////////////////////////////////////////////////////////////////////////////
//
// Copyright 1993-2015 NVIDIA Corporation. All rights reserved.
//
// Please refer to the NVIDIA end user license agreement (EULA) associated
// with this source code for terms and conditions that govern your use of
// this software. Any use, reproduction, disclosure, or distribution of
// this software and related documentation outside the terms of the EULA
// is strictly prohibited.
//
////////////////////////////////////////////////////////////////////////////
//
// This sample illustrates the usage of CUDA events for both GPU timing and
// overlapping CPU and GPU execution. Events are inserted into a stream
// of CUDA calls. Since CUDA stream calls are asynchronous, the CPU can
// perform computations while GPU is executing (including DMA memcopies
// between the host and device). CPU can query CUDA events to determine
// whether GPU has completed tasks.
//
// includes, system
// includes CUDA Runtime
// includes, project
__global__ void increment_kernel(int *g_data, int inc_value)
{
int idx = blockIdx.x * blockDim.x + threadIdx.x;
g_data[idx] = g_data[idx] + inc_value;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
////////////////////////////////////////////////////////////////////////////
//
// Copyright 1993-2015 NVIDIA Corporation. All rights reserved.
//
// Please refer to the NVIDIA end user license agreement (EULA) associated
// with this source code for terms and conditions that govern your use of
// this software. Any use, reproduction, disclosure, or distribution of
// this software and related documentation outside the terms of the EULA
// is strictly prohibited.
//
////////////////////////////////////////////////////////////////////////////
//
// This sample illustrates the usage of CUDA events for both GPU timing and
// overlapping CPU and GPU execution. Events are inserted into a stream
// of CUDA calls. Since CUDA stream calls are asynchronous, the CPU can
// perform computations while GPU is executing (including DMA memcopies
// between the host and device). CPU can query CUDA events to determine
// whether GPU has completed tasks.
//
// includes, system
// includes CUDA Runtime
// includes, project
__global__ void increment_kernel(int *g_data, int inc_value)
{
int idx = blockIdx.x * blockDim.x + threadIdx.x;
g_data[idx] = g_data[idx] + inc_value;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z16increment_kernelPii
.globl _Z16increment_kernelPii
.p2align 8
.type _Z16increment_kernelPii,@function
_Z16increment_kernelPii:
s_load_b32 s2, s[0:1], 0x1c
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s2, 0xffff
s_load_b64 s[2:3], s[0:1], 0x0
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
s_load_b32 s0, s[0:1], 0x8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_load_b32 v2, v[0:1], off
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v2, s0, v2
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z16increment_kernelPii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z16increment_kernelPii, .Lfunc_end0-_Z16increment_kernelPii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z16increment_kernelPii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z16increment_kernelPii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
////////////////////////////////////////////////////////////////////////////
//
// Copyright 1993-2015 NVIDIA Corporation. All rights reserved.
//
// Please refer to the NVIDIA end user license agreement (EULA) associated
// with this source code for terms and conditions that govern your use of
// this software. Any use, reproduction, disclosure, or distribution of
// this software and related documentation outside the terms of the EULA
// is strictly prohibited.
//
////////////////////////////////////////////////////////////////////////////
//
// This sample illustrates the usage of CUDA events for both GPU timing and
// overlapping CPU and GPU execution. Events are inserted into a stream
// of CUDA calls. Since CUDA stream calls are asynchronous, the CPU can
// perform computations while GPU is executing (including DMA memcopies
// between the host and device). CPU can query CUDA events to determine
// whether GPU has completed tasks.
//
// includes, system
// includes CUDA Runtime
// includes, project
__global__ void increment_kernel(int *g_data, int inc_value)
{
int idx = blockIdx.x * blockDim.x + threadIdx.x;
g_data[idx] = g_data[idx] + inc_value;
} | .text
.file "increment_kernel.hip"
.globl _Z31__device_stub__increment_kernelPii # -- Begin function _Z31__device_stub__increment_kernelPii
.p2align 4, 0x90
.type _Z31__device_stub__increment_kernelPii,@function
_Z31__device_stub__increment_kernelPii: # @_Z31__device_stub__increment_kernelPii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z16increment_kernelPii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z31__device_stub__increment_kernelPii, .Lfunc_end0-_Z31__device_stub__increment_kernelPii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z16increment_kernelPii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z16increment_kernelPii,@object # @_Z16increment_kernelPii
.section .rodata,"a",@progbits
.globl _Z16increment_kernelPii
.p2align 3, 0x0
_Z16increment_kernelPii:
.quad _Z31__device_stub__increment_kernelPii
.size _Z16increment_kernelPii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z16increment_kernelPii"
.size .L__unnamed_1, 24
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z31__device_stub__increment_kernelPii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z16increment_kernelPii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z16increment_kernelPii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R2, R2, c[0x0][0x0], R3 ; /* 0x0000000002027a24 */
/* 0x001fca00078e0203 */
/*0060*/ IMAD.WIDE R2, R2, R5, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0205 */
/*0070*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea4000c1e1900 */
/*0080*/ IADD3 R5, R0, c[0x0][0x168], RZ ; /* 0x00005a0000057a10 */
/* 0x004fca0007ffe0ff */
/*0090*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*00a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00b0*/ BRA 0xb0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z16increment_kernelPii
.globl _Z16increment_kernelPii
.p2align 8
.type _Z16increment_kernelPii,@function
_Z16increment_kernelPii:
s_load_b32 s2, s[0:1], 0x1c
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s2, 0xffff
s_load_b64 s[2:3], s[0:1], 0x0
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
s_load_b32 s0, s[0:1], 0x8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_load_b32 v2, v[0:1], off
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v2, s0, v2
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z16increment_kernelPii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z16increment_kernelPii, .Lfunc_end0-_Z16increment_kernelPii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z16increment_kernelPii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z16increment_kernelPii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00124e3e_00000000-6_increment_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z37__device_stub__Z16increment_kernelPiiPii
.type _Z37__device_stub__Z16increment_kernelPiiPii, @function
_Z37__device_stub__Z16increment_kernelPiiPii:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z16increment_kernelPii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z37__device_stub__Z16increment_kernelPiiPii, .-_Z37__device_stub__Z16increment_kernelPiiPii
.globl _Z16increment_kernelPii
.type _Z16increment_kernelPii, @function
_Z16increment_kernelPii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z37__device_stub__Z16increment_kernelPiiPii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z16increment_kernelPii, .-_Z16increment_kernelPii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z16increment_kernelPii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z16increment_kernelPii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "increment_kernel.hip"
.globl _Z31__device_stub__increment_kernelPii # -- Begin function _Z31__device_stub__increment_kernelPii
.p2align 4, 0x90
.type _Z31__device_stub__increment_kernelPii,@function
_Z31__device_stub__increment_kernelPii: # @_Z31__device_stub__increment_kernelPii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z16increment_kernelPii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z31__device_stub__increment_kernelPii, .Lfunc_end0-_Z31__device_stub__increment_kernelPii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z16increment_kernelPii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z16increment_kernelPii,@object # @_Z16increment_kernelPii
.section .rodata,"a",@progbits
.globl _Z16increment_kernelPii
.p2align 3, 0x0
_Z16increment_kernelPii:
.quad _Z31__device_stub__increment_kernelPii
.size _Z16increment_kernelPii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z16increment_kernelPii"
.size .L__unnamed_1, 24
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z31__device_stub__increment_kernelPii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z16increment_kernelPii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | // On Maverick2: sbatch mvk2GPUMatMul
// nvcc BrodayWalker1B.cu -o BrodayWalker1B.exe
//***************************************************************************
// Name: Broday Walker
// Instructor: Dr. Colmenares
// Class: CMPS 5433
// Date: March 2, 2020
//***************************************************************************
// This program implements matrix multiplication using a GPU on Maverick2.
// The program reports the elapsed time taken to complete the matrix
// multiplication in milliseconds. It is significantly faster than its
// sequential counterpart.
//***************************************************************************
#include <stdio.h>
#include <cuda.h>
enum N {N = 32};
// matmulKernel performs matrix multiplication on a linearized array
// This code was given in the slides and adapted for use here
__global__ void matmulKernel(int *Ad, int *Bd, int *Cd, int width)
{
int tx = threadIdx.x;
int ty = threadIdx.y;
float sum = 0;
for (int k = 0; k < width; k++)
{
int Aelement = Ad[ty * width + k];
int Belement = Bd[k * width + tx];
sum += Aelement * Belement;
}
Cd[ty * width + tx] = sum;
}
int main()
{
// Declarations
int A[N * N], B[N * N], C[N * N];
int *Ad, *Bd, *Cd;
int size = N * N * sizeof(int);
int sum = 0;
// Declare the timer
// Reference:
// https://devblogs.nvidia.com/how-implement-performance-metrics-cuda-cc/
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
float milliseconds = 0;
// Fill arrays A and C
// Array C will be filled with 0s
for (int i = 0; i < N; i++)
for (int j = 0; j < N; j++)
{
A[i * N + j] = i;
C[i * N + j] = 0;
}
// Fill B
int row = N - 1;
for (int i = 0; i < N; i++)
{
for (int j = 0; j < N; j++)
B[i * N + j] = row;
row--;
}
/* Allocate memory and copy to device */
cudaMalloc((void**)&Ad, size);
cudaMemcpy(Ad, A, size, cudaMemcpyHostToDevice);
cudaMalloc((void**)&Bd, size);
cudaMemcpy(Bd, B, size, cudaMemcpyHostToDevice);
cudaMalloc((void**)&Cd, size);
/* End memory allocation and copying to device */
/* Define grid and block dimensions */
dim3 dimGrid( 1, 1 );
dim3 dimBlock( N, N );
/* Record start time */
cudaEventRecord(start);
/* Invoke the kernel */
matmulKernel<<<dimGrid, dimBlock>>>(Ad, Bd, Cd, N);
/* Record end time */
cudaEventRecord(stop);
/* Copy the matrix multiplication results from device to host */
cudaMemcpy(C, Cd, size, cudaMemcpyDeviceToHost);
/* Block CPU execution until the specified event is recorded */
cudaEventSynchronize(stop);
/* Returns the elapsed time in milliseconds to the first argument */
cudaEventElapsedTime(&milliseconds, start, stop);
cudaFree(Ad);
cudaFree(Bd);
cudaFree(Cd);
// Sum the array and print the results
for (int i = 0; i < N * N; i++)
sum += C[i];
// Print results
printf("The summation of all the elements is %d.\n", sum);
// Print elapsed time
printf("\nElapsed time in milliseconds: %f.\n", milliseconds);
return 0;
} | code for sm_80
Function : _Z12matmulKernelPiS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e220000002100 */
/*0020*/ MOV R2, c[0x0][0x178] ; /* 0x00005e0000027a02 */
/* 0x000fe20000000f00 */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ HFMA2.MMA R11, -RZ, RZ, 0, 0 ; /* 0x00000000ff0b7435 */
/* 0x000fe200000001ff */
/*0050*/ S2R R3, SR_TID.Y ; /* 0x0000000000037919 */
/* 0x000e620000002200 */
/*0060*/ ISETP.GE.AND P0, PT, R2, 0x1, PT ; /* 0x000000010200780c */
/* 0x000fda0003f06270 */
/*0070*/ @!P0 BRA 0xf50 ; /* 0x00000ed000008947 */
/* 0x000fea0003800000 */
/*0080*/ IADD3 R4, R2.reuse, -0x1, RZ ; /* 0xffffffff02047810 */
/* 0x040fe40007ffe0ff */
/*0090*/ LOP3.LUT R5, R2, 0x3, RZ, 0xc0, !PT ; /* 0x0000000302057812 */
/* 0x000fe400078ec0ff */
/*00a0*/ ISETP.GE.U32.AND P0, PT, R4, 0x3, PT ; /* 0x000000030400780c */
/* 0x000fe40003f06070 */
/*00b0*/ MOV R11, RZ ; /* 0x000000ff000b7202 */
/* 0x000fe40000000f00 */
/*00c0*/ MOV R4, RZ ; /* 0x000000ff00047202 */
/* 0x000fd20000000f00 */
/*00d0*/ @!P0 BRA 0xe10 ; /* 0x00000d3000008947 */
/* 0x000fea0003800000 */
/*00e0*/ IADD3 R7, -R5, c[0x0][0x178], RZ ; /* 0x00005e0005077a10 */
/* 0x000fe20007ffe1ff */
/*00f0*/ HFMA2.MMA R23, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff177435 */
/* 0x000fe200000001ff */
/*0100*/ ULDC.64 UR6, c[0x0][0x160] ; /* 0x0000580000067ab9 */
/* 0x000fe20000000a00 */
/*0110*/ HFMA2.MMA R4, -RZ, RZ, 0, 0 ; /* 0x00000000ff047435 */
/* 0x000fe200000001ff */
/*0120*/ ISETP.GT.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fe20003f04270 */
/*0130*/ IMAD R6, R3, c[0x0][0x178], RZ ; /* 0x00005e0003067a24 */
/* 0x002fe200078e02ff */
/*0140*/ MOV R11, RZ ; /* 0x000000ff000b7202 */
/* 0x000fca0000000f00 */
/*0150*/ IMAD.WIDE R22, R0, R23, c[0x0][0x168] ; /* 0x00005a0000167625 */
/* 0x001fcc00078e0217 */
/*0160*/ @!P0 BRA 0xc00 ; /* 0x00000a9000008947 */
/* 0x000fea0003800000 */
/*0170*/ ISETP.GT.AND P1, PT, R7, 0xc, PT ; /* 0x0000000c0700780c */
/* 0x000fe40003f24270 */
/*0180*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*0190*/ @!P1 BRA 0x840 ; /* 0x000006a000009947 */
/* 0x000fea0003800000 */
/*01a0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*01b0*/ MOV R14, UR6 ; /* 0x00000006000e7c02 */
/* 0x000fe20008000f00 */
/*01c0*/ IMAD.WIDE R16, R2, 0x4, R22 ; /* 0x0000000402107825 */
/* 0x000fe200078e0216 */
/*01d0*/ MOV R15, UR7 ; /* 0x00000007000f7c02 */
/* 0x000fe20008000f00 */
/*01e0*/ LDG.E R8, [R22.64] ; /* 0x0000000416087981 */
/* 0x0000a8000c1e1900 */
/*01f0*/ IMAD.WIDE R14, R6, 0x4, R14 ; /* 0x00000004060e7825 */
/* 0x000fe200078e020e */
/*0200*/ LDG.E R10, [R16.64] ; /* 0x00000004100a7981 */
/* 0x0002e8000c1e1900 */
/*0210*/ LDG.E R9, [R14.64] ; /* 0x000000040e097981 */
/* 0x000ea2000c1e1900 */
/*0220*/ IMAD.WIDE R12, R2, 0x4, R16 ; /* 0x00000004020c7825 */
/* 0x000fc600078e0210 */
/*0230*/ LDG.E R29, [R14.64+0x4] ; /* 0x000004040e1d7981 */
/* 0x000ee8000c1e1900 */
/*0240*/ LDG.E R26, [R12.64] ; /* 0x000000040c1a7981 */
/* 0x000968000c1e1900 */
/*0250*/ LDG.E R27, [R14.64+0x8] ; /* 0x000008040e1b7981 */
/* 0x000f68000c1e1900 */
/*0260*/ LDG.E R21, [R14.64+0xc] ; /* 0x00000c040e157981 */
/* 0x000f62000c1e1900 */
/*0270*/ IMAD.WIDE R12, R2, 0x4, R12 ; /* 0x00000004020c7825 */
/* 0x010fc600078e020c */
/*0280*/ LDG.E R23, [R14.64+0x14] ; /* 0x000014040e177981 */
/* 0x001f28000c1e1900 */
/*0290*/ LDG.E R20, [R12.64] ; /* 0x000000040c147981 */
/* 0x000122000c1e1900 */
/*02a0*/ IMAD.WIDE R18, R2, 0x4, R12 ; /* 0x0000000402127825 */
/* 0x000fc600078e020c */
/*02b0*/ LDG.E R25, [R14.64+0x10] ; /* 0x000010040e197981 */
/* 0x000f26000c1e1900 */
/*02c0*/ IMAD.WIDE R16, R2.reuse, 0x4, R18 ; /* 0x0000000402107825 */
/* 0x042fe200078e0212 */
/*02d0*/ LDG.E R22, [R18.64] ; /* 0x0000000412167981 */
/* 0x000328000c1e1900 */
/*02e0*/ LDG.E R24, [R16.64] ; /* 0x0000000410187981 */
/* 0x000322000c1e1900 */
/*02f0*/ IMAD.WIDE R12, R2, 0x4, R16 ; /* 0x00000004020c7825 */
/* 0x001fc800078e0210 */
/*0300*/ IMAD R8, R8, R9, RZ ; /* 0x0000000908087224 */
/* 0x004fe400078e02ff */
/*0310*/ IMAD R10, R10, R29, RZ ; /* 0x0000001d0a0a7224 */
/* 0x008fc800078e02ff */
/*0320*/ I2F R8, R8 ; /* 0x0000000800087306 */
/* 0x000e220000201400 */
/*0330*/ IMAD R26, R26, R27, RZ ; /* 0x0000001b1a1a7224 */
/* 0x020fce00078e02ff */
/*0340*/ I2F R18, R10 ; /* 0x0000000a00127306 */
/* 0x0028620000201400 */
/*0350*/ IMAD.WIDE R28, R2, 0x4, R12 ; /* 0x00000004021c7825 */
/* 0x000fe200078e020c */
/*0360*/ LDG.E R27, [R12.64] ; /* 0x000000040c1b7981 */
/* 0x0004ec000c1e1900 */
/*0370*/ I2F R26, R26 ; /* 0x0000001a001a7306 */
/* 0x000f620000201400 */
/*0380*/ IMAD R10, R20, R21, RZ ; /* 0x00000015140a7224 */
/* 0x010fe400078e02ff */
/*0390*/ FADD R11, R8, R11 ; /* 0x0000000b080b7221 */
/* 0x001fe20000000000 */
/*03a0*/ LDG.E R20, [R14.64+0x18] ; /* 0x000018040e147981 */
/* 0x000ee2000c1e1900 */
/*03b0*/ IMAD.WIDE R8, R2, 0x4, R28 ; /* 0x0000000402087825 */
/* 0x000fc600078e021c */
/*03c0*/ I2F R10, R10 ; /* 0x0000000a000a7306 */
/* 0x000e220000201400 */
/*03d0*/ LDG.E R28, [R28.64] ; /* 0x000000041c1c7981 */
/* 0x000f22000c1e1900 */
/*03e0*/ FADD R11, R11, R18 ; /* 0x000000120b0b7221 */
/* 0x002fe40000000000 */
/*03f0*/ IMAD.WIDE R18, R2.reuse, 0x4, R8 ; /* 0x0000000402127825 */
/* 0x040fe200078e0208 */
/*0400*/ LDG.E R21, [R14.64+0x1c] ; /* 0x00001c040e157981 */
/* 0x000f26000c1e1900 */
/*0410*/ FADD R11, R11, R26 ; /* 0x0000001a0b0b7221 */
/* 0x020fe20000000000 */
/*0420*/ LDG.E R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x000362000c1e1900 */
/*0430*/ IMAD.WIDE R16, R2, 0x4, R18 ; /* 0x0000000402107825 */
/* 0x000fc600078e0212 */
/*0440*/ LDG.E R12, [R14.64+0x24] ; /* 0x000024040e0c7981 */
/* 0x004ea2000c1e1900 */
/*0450*/ FADD R10, R11, R10 ; /* 0x0000000a0b0a7221 */
/* 0x001fc60000000000 */
/*0460*/ LDG.E R13, [R16.64] ; /* 0x00000004100d7981 */
/* 0x0000a8000c1e1900 */
/*0470*/ LDG.E R9, [R18.64] ; /* 0x0000000412097981 */
/* 0x0022a8000c1e1900 */
/*0480*/ LDG.E R11, [R14.64+0x20] ; /* 0x000020040e0b7981 */
/* 0x000f62000c1e1900 */
/*0490*/ IMAD.WIDE R16, R2, 0x4, R16 ; /* 0x0000000402107825 */
/* 0x001fc800078e0210 */
/*04a0*/ IMAD R23, R24, R23, RZ ; /* 0x0000001718177224 */
/* 0x000fe200078e02ff */
/*04b0*/ LDG.E R26, [R16.64] ; /* 0x00000004101a7981 */
/* 0x000162000c1e1900 */
/*04c0*/ IMAD R22, R22, R25, RZ ; /* 0x0000001916167224 */
/* 0x000fc600078e02ff */
/*04d0*/ LDG.E R24, [R14.64+0x28] ; /* 0x000028040e187981 */
/* 0x000f68000c1e1900 */
/*04e0*/ LDG.E R25, [R14.64+0x2c] ; /* 0x00002c040e197981 */
/* 0x000f62000c1e1900 */
/*04f0*/ IMAD.WIDE R18, R2, 0x4, R16 ; /* 0x0000000402127825 */
/* 0x002fc600078e0210 */
/*0500*/ LDG.E R17, [R14.64+0x30] ; /* 0x000030040e117981 */
/* 0x001162000c1e1900 */
/*0510*/ IMAD R27, R27, R20, RZ ; /* 0x000000141b1b7224 */
/* 0x008fe400078e02ff */
/*0520*/ IMAD R29, R28, R21, RZ ; /* 0x000000151c1d7224 */
/* 0x010fe400078e02ff */
/*0530*/ IMAD.WIDE R20, R2, 0x4, R18 ; /* 0x0000000402147825 */
/* 0x000fe200078e0212 */
/*0540*/ LDG.E R28, [R18.64] ; /* 0x00000004121c7981 */
/* 0x0002e8000c1e1900 */
/*0550*/ LDG.E R18, [R20.64] ; /* 0x0000000414127981 */
/* 0x002322000c1e1900 */
/*0560*/ IMAD R16, R9, R12, RZ ; /* 0x0000000c09107224 */
/* 0x004fc600078e02ff */
/*0570*/ LDG.E R19, [R14.64+0x34] ; /* 0x000034040e137981 */
/* 0x000122000c1e1900 */
/*0580*/ IMAD R11, R8, R11, RZ ; /* 0x0000000b080b7224 */
/* 0x020fe400078e02ff */
/*0590*/ IMAD.WIDE R8, R2, 0x4, R20 ; /* 0x0000000402087825 */
/* 0x000fc800078e0214 */
/*05a0*/ IMAD R24, R13, R24, RZ ; /* 0x000000180d187224 */
/* 0x000fe400078e02ff */
/*05b0*/ IMAD.WIDE R12, R2, 0x4, R8 ; /* 0x00000004020c7825 */
/* 0x000fc800078e0208 */
/*05c0*/ IMAD R26, R26, R25, RZ ; /* 0x000000191a1a7224 */
/* 0x000fe200078e02ff */
/*05d0*/ LDG.E R20, [R12.64] ; /* 0x000000040c147981 */
/* 0x002ea8000c1e1900 */
/*05e0*/ LDG.E R25, [R8.64] ; /* 0x0000000408197981 */
/* 0x000368000c1e1900 */
/*05f0*/ LDG.E R8, [R14.64+0x38] ; /* 0x000038040e087981 */
/* 0x002168000c1e1900 */
/*0600*/ LDG.E R9, [R14.64+0x3c] ; /* 0x00003c040e097981 */
/* 0x0000a2000c1e1900 */
/*0610*/ I2F R22, R22 ; /* 0x0000001600167306 */
/* 0x000e700000201400 */
/*0620*/ I2F R23, R23 ; /* 0x0000001700177306 */
/* 0x000e300000201400 */
/*0630*/ I2F R27, R27 ; /* 0x0000001b001b7306 */
/* 0x000e220000201400 */
/*0640*/ FADD R10, R10, R22 ; /* 0x000000160a0a7221 */
/* 0x002fce0000000000 */
/*0650*/ I2F R29, R29 ; /* 0x0000001d001d7306 */
/* 0x000e620000201400 */
/*0660*/ FADD R14, R10, R23 ; /* 0x000000170a0e7221 */
/* 0x001fce0000000000 */
/*0670*/ I2F R11, R11 ; /* 0x0000000b000b7306 */
/* 0x000e220000201400 */
/*0680*/ FADD R14, R14, R27 ; /* 0x0000001b0e0e7221 */
/* 0x000fce0000000000 */
/*0690*/ I2F R16, R16 ; /* 0x0000001000107306 */
/* 0x000e220000201400 */
/*06a0*/ FADD R14, R14, R29 ; /* 0x0000001d0e0e7221 */
/* 0x002fce0000000000 */
/*06b0*/ I2F R24, R24 ; /* 0x0000001800187306 */
/* 0x000e620000201400 */
/*06c0*/ FADD R11, R14, R11 ; /* 0x0000000b0e0b7221 */
/* 0x001fce0000000000 */
/*06d0*/ I2F R26, R26 ; /* 0x0000001a001a7306 */
/* 0x000e220000201400 */
/*06e0*/ FADD R11, R11, R16 ; /* 0x000000100b0b7221 */
/* 0x000fe20000000000 */
/*06f0*/ IADD3 R7, R7, -0x10, RZ ; /* 0xfffffff007077810 */
/* 0x000fc60007ffe0ff */
/*0700*/ FADD R11, R11, R24 ; /* 0x000000180b0b7221 */
/* 0x002fe20000000000 */
/*0710*/ ISETP.GT.AND P1, PT, R7, 0xc, PT ; /* 0x0000000c0700780c */
/* 0x000fc60003f24270 */
/*0720*/ FADD R11, R11, R26 ; /* 0x0000001a0b0b7221 */
/* 0x001fe20000000000 */
/*0730*/ UIADD3 UR6, UP0, UR6, 0x40, URZ ; /* 0x0000004006067890 */
/* 0x000fe2000ff1e03f */
/*0740*/ IADD3 R4, R4, 0x10, RZ ; /* 0x0000001004047810 */
/* 0x000fc60007ffe0ff */
/*0750*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0760*/ IMAD.WIDE R22, R2, 0x4, R12 ; /* 0x0000000402167825 */
/* 0x000fc800078e020c */
/*0770*/ IMAD R17, R28, R17, RZ ; /* 0x000000111c117224 */
/* 0x008fc800078e02ff */
/*0780*/ I2F R10, R17 ; /* 0x00000011000a7306 */
/* 0x000e220000201400 */
/*0790*/ IMAD R18, R18, R19, RZ ; /* 0x0000001312127224 */
/* 0x010fce00078e02ff */
/*07a0*/ I2F R15, R18 ; /* 0x00000012000f7306 */
/* 0x000e620000201400 */
/*07b0*/ FADD R10, R11, R10 ; /* 0x0000000a0b0a7221 */
/* 0x001fe40000000000 */
/*07c0*/ IMAD R8, R25, R8, RZ ; /* 0x0000000819087224 */
/* 0x020fe400078e02ff */
/*07d0*/ IMAD R9, R20, R9, RZ ; /* 0x0000000914097224 */
/* 0x004fc600078e02ff */
/*07e0*/ I2F R19, R8 ; /* 0x0000000800137306 */
/* 0x000e300000201400 */
/*07f0*/ I2F R9, R9 ; /* 0x0000000900097306 */
/* 0x000ea20000201400 */
/*0800*/ FADD R10, R10, R15 ; /* 0x0000000f0a0a7221 */
/* 0x002fc80000000000 */
/*0810*/ FADD R10, R10, R19 ; /* 0x000000130a0a7221 */
/* 0x001fc80000000000 */
/*0820*/ FADD R11, R10, R9 ; /* 0x000000090a0b7221 */
/* 0x004fe20000000000 */
/*0830*/ @P1 BRA 0x1b0 ; /* 0xfffff97000001947 */
/* 0x000fea000383ffff */
/*0840*/ ISETP.GT.AND P1, PT, R7, 0x4, PT ; /* 0x000000040700780c */
/* 0x000fda0003f24270 */
/*0850*/ @!P1 BRA 0xbe0 ; /* 0x0000038000009947 */
/* 0x000fea0003800000 */
/*0860*/ IMAD.WIDE R20, R2, 0x4, R22 ; /* 0x0000000402147825 */
/* 0x000fe200078e0216 */
/*0870*/ MOV R8, UR6 ; /* 0x0000000600087c02 */
/* 0x000fe20008000f00 */
/*0880*/ LDG.E R22, [R22.64] ; /* 0x0000000416167981 */
/* 0x0000a2000c1e1900 */
/*0890*/ MOV R9, UR7 ; /* 0x0000000700097c02 */
/* 0x000fc60008000f00 */
/*08a0*/ IMAD.WIDE R12, R2, 0x4, R20 ; /* 0x00000004020c7825 */
/* 0x000fe200078e0214 */
/*08b0*/ LDG.E R10, [R20.64] ; /* 0x00000004140a7981 */
/* 0x0002e6000c1e1900 */
/*08c0*/ IMAD.WIDE R8, R6, 0x4, R8 ; /* 0x0000000406087825 */
/* 0x000fe200078e0208 */
/*08d0*/ LDG.E R27, [R12.64] ; /* 0x000000040c1b7981 */
/* 0x000966000c1e1900 */
/*08e0*/ IMAD.WIDE R14, R2.reuse, 0x4, R12 ; /* 0x00000004020e7825 */
/* 0x040fe200078e020c */
/*08f0*/ LDG.E R25, [R8.64] ; /* 0x0000000408197981 */
/* 0x000ea8000c1e1900 */
/*0900*/ LDG.E R23, [R8.64+0x4] ; /* 0x0000040408177981 */
/* 0x001ee2000c1e1900 */
/*0910*/ IMAD.WIDE R16, R2, 0x4, R14 ; /* 0x0000000402107825 */
/* 0x000fc600078e020e */
/*0920*/ LDG.E R26, [R8.64+0x8] ; /* 0x00000804081a7981 */
/* 0x000f66000c1e1900 */
/*0930*/ IMAD.WIDE R18, R2.reuse, 0x4, R16 ; /* 0x0000000402127825 */
/* 0x040fe200078e0210 */
/*0940*/ LDG.E R24, [R14.64] ; /* 0x000000040e187981 */
/* 0x000168000c1e1900 */
/*0950*/ LDG.E R29, [R8.64+0xc] ; /* 0x00000c04081d7981 */
/* 0x000f62000c1e1900 */
/*0960*/ IMAD.WIDE R20, R2, 0x4, R18 ; /* 0x0000000402147825 */
/* 0x002fc600078e0212 */
/*0970*/ LDG.E R28, [R8.64+0x10] ; /* 0x00001004081c7981 */
/* 0x000f68000c1e1900 */
/*0980*/ LDG.E R15, [R16.64] ; /* 0x00000004100f7981 */
/* 0x001162000c1e1900 */
/*0990*/ IMAD.WIDE R12, R2, 0x4, R20 ; /* 0x00000004020c7825 */
/* 0x010fc600078e0214 */
/*09a0*/ LDG.E R14, [R8.64+0x14] ; /* 0x00001404080e7981 */
/* 0x000f28000c1e1900 */
/*09b0*/ LDG.E R17, [R18.64] ; /* 0x0000000412117981 */
/* 0x001128000c1e1900 */
/*09c0*/ LDG.E R16, [R20.64] ; /* 0x0000000414107981 */
/* 0x000328000c1e1900 */
/*09d0*/ LDG.E R19, [R8.64+0x18] ; /* 0x0000180408137981 */
/* 0x001128000c1e1900 */
/*09e0*/ LDG.E R18, [R8.64+0x1c] ; /* 0x00001c0408127981 */
/* 0x000128000c1e1900 */
/*09f0*/ LDG.E R21, [R12.64] ; /* 0x000000040c157981 */
/* 0x002f22000c1e1900 */
/*0a00*/ UIADD3 UR6, UP0, UR6, 0x20, URZ ; /* 0x0000002006067890 */
/* 0x000fe2000ff1e03f */
/*0a10*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc40003f0e170 */
/*0a20*/ IADD3 R4, R4, 0x8, RZ ; /* 0x0000000804047810 */
/* 0x000fe40007ffe0ff */
/*0a30*/ IADD3 R7, R7, -0x8, RZ ; /* 0xfffffff807077810 */
/* 0x000fe20007ffe0ff */
/*0a40*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0a50*/ IMAD R22, R22, R25, RZ ; /* 0x0000001916167224 */
/* 0x004fe400078e02ff */
/*0a60*/ IMAD R10, R10, R23, RZ ; /* 0x000000170a0a7224 */
/* 0x008fc800078e02ff */
/*0a70*/ I2F R22, R22 ; /* 0x0000001600167306 */
/* 0x000e620000201400 */
/*0a80*/ IMAD R23, R27, R26, RZ ; /* 0x0000001a1b177224 */
/* 0x020fce00078e02ff */
/*0a90*/ I2F R10, R10 ; /* 0x0000000a000a7306 */
/* 0x000ea20000201400 */
/*0aa0*/ IMAD R20, R24, R29, RZ ; /* 0x0000001d18147224 */
/* 0x000fce00078e02ff */
/*0ab0*/ I2F R23, R23 ; /* 0x0000001700177306 */
/* 0x000ee20000201400 */
/*0ac0*/ IMAD R15, R15, R28, RZ ; /* 0x0000001c0f0f7224 */
/* 0x000fe400078e02ff */
/*0ad0*/ FADD R11, R11, R22 ; /* 0x000000160b0b7221 */
/* 0x002fca0000000000 */
/*0ae0*/ I2F R20, R20 ; /* 0x0000001400147306 */
/* 0x000e620000201400 */
/*0af0*/ IMAD R14, R17, R14, RZ ; /* 0x0000000e110e7224 */
/* 0x010fce00078e02ff */
/*0b00*/ I2F R8, R15 ; /* 0x0000000f00087306 */
/* 0x001e220000201400 */
/*0b10*/ FADD R10, R11, R10 ; /* 0x0000000a0b0a7221 */
/* 0x004fe40000000000 */
/*0b20*/ IMAD R16, R16, R19, RZ ; /* 0x0000001310107224 */
/* 0x000fca00078e02ff */
/*0b30*/ I2F R9, R14 ; /* 0x0000000e00097306 */
/* 0x000ea20000201400 */
/*0b40*/ FADD R23, R10, R23 ; /* 0x000000170a177221 */
/* 0x008fe40000000000 */
/*0b50*/ IMAD R18, R21, R18, RZ ; /* 0x0000001215127224 */
/* 0x000fca00078e02ff */
/*0b60*/ I2F R11, R16 ; /* 0x00000010000b7306 */
/* 0x000ee20000201400 */
/*0b70*/ FADD R23, R23, R20 ; /* 0x0000001417177221 */
/* 0x002fce0000000000 */
/*0b80*/ I2F R18, R18 ; /* 0x0000001200127306 */
/* 0x000e620000201400 */
/*0b90*/ FADD R8, R23, R8 ; /* 0x0000000817087221 */
/* 0x001fc80000000000 */
/*0ba0*/ FADD R8, R8, R9 ; /* 0x0000000908087221 */
/* 0x004fc80000000000 */
/*0bb0*/ FADD R11, R8, R11 ; /* 0x0000000b080b7221 */
/* 0x008fe40000000000 */
/*0bc0*/ IMAD.WIDE R22, R2, 0x4, R12 ; /* 0x0000000402167825 */
/* 0x000fc800078e020c */
/*0bd0*/ FADD R11, R11, R18 ; /* 0x000000120b0b7221 */
/* 0x002fe40000000000 */
/*0be0*/ ISETP.NE.OR P0, PT, R7, RZ, P0 ; /* 0x000000ff0700720c */
/* 0x000fda0000705670 */
/*0bf0*/ @!P0 BRA 0xe10 ; /* 0x0000021000008947 */
/* 0x000fea0003800000 */
/*0c00*/ MOV R8, UR6 ; /* 0x0000000600087c02 */
/* 0x000fe20008000f00 */
/*0c10*/ IMAD.WIDE R16, R2, 0x4, R22 ; /* 0x0000000402107825 */
/* 0x000fe200078e0216 */
/*0c20*/ MOV R9, UR7 ; /* 0x0000000700097c02 */
/* 0x000fe20008000f00 */
/*0c30*/ LDG.E R22, [R22.64] ; /* 0x0000000416167981 */
/* 0x000ea8000c1e1900 */
/*0c40*/ IMAD.WIDE R8, R6, 0x4, R8 ; /* 0x0000000406087825 */
/* 0x000fc800078e0208 */
/*0c50*/ IMAD.WIDE R14, R2.reuse, 0x4, R16 ; /* 0x00000004020e7825 */
/* 0x040fe200078e0210 */
/*0c60*/ LDG.E R19, [R8.64] ; /* 0x0000000408137981 */
/* 0x000ea8000c1e1900 */
/*0c70*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x000ee8000c1e1900 */
/*0c80*/ LDG.E R21, [R8.64+0x4] ; /* 0x0000040408157981 */
/* 0x000ee2000c1e1900 */
/*0c90*/ IMAD.WIDE R12, R2, 0x4, R14 ; /* 0x00000004020c7825 */
/* 0x000fc600078e020e */
/*0ca0*/ LDG.E R18, [R14.64] ; /* 0x000000040e127981 */
/* 0x000f28000c1e1900 */
/*0cb0*/ LDG.E R25, [R8.64+0x8] ; /* 0x0000080408197981 */
/* 0x000f28000c1e1900 */
/*0cc0*/ LDG.E R27, [R8.64+0xc] ; /* 0x00000c04081b7981 */
/* 0x000f68000c1e1900 */
/*0cd0*/ LDG.E R20, [R12.64] ; /* 0x000000040c147981 */
/* 0x000f62000c1e1900 */
/*0ce0*/ IADD3 R7, R7, -0x4, RZ ; /* 0xfffffffc07077810 */
/* 0x000fc80007ffe0ff */
/*0cf0*/ ISETP.NE.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fe20003f05270 */
/*0d00*/ UIADD3 UR6, UP0, UR6, 0x10, URZ ; /* 0x0000001006067890 */
/* 0x000fe2000ff1e03f */
/*0d10*/ IADD3 R4, R4, 0x4, RZ ; /* 0x0000000404047810 */
/* 0x000fc60007ffe0ff */
/*0d20*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0d30*/ IMAD R19, R22, R19, RZ ; /* 0x0000001316137224 */
/* 0x004fc800078e02ff */
/*0d40*/ I2F R10, R19 ; /* 0x00000013000a7306 */
/* 0x000e220000201400 */
/*0d50*/ IMAD R21, R16, R21, RZ ; /* 0x0000001510157224 */
/* 0x008fce00078e02ff */
/*0d60*/ I2F R21, R21 ; /* 0x0000001500157306 */
/* 0x000e620000201400 */
/*0d70*/ IMAD R18, R18, R25, RZ ; /* 0x0000001912127224 */
/* 0x010fce00078e02ff */
/*0d80*/ I2F R17, R18 ; /* 0x0000001200117306 */
/* 0x000ea20000201400 */
/*0d90*/ IMAD R20, R20, R27, RZ ; /* 0x0000001b14147224 */
/* 0x020fe400078e02ff */
/*0da0*/ FADD R10, R10, R11 ; /* 0x0000000b0a0a7221 */
/* 0x001fca0000000000 */
/*0db0*/ I2F R15, R20 ; /* 0x00000014000f7306 */
/* 0x000e220000201400 */
/*0dc0*/ FADD R10, R10, R21 ; /* 0x000000150a0a7221 */
/* 0x002fe40000000000 */
/*0dd0*/ IMAD.WIDE R22, R2, 0x4, R12 ; /* 0x0000000402167825 */
/* 0x000fc800078e020c */
/*0de0*/ FADD R10, R10, R17 ; /* 0x000000110a0a7221 */
/* 0x004fc80000000000 */
/*0df0*/ FADD R11, R10, R15 ; /* 0x0000000f0a0b7221 */
/* 0x001fe20000000000 */
/*0e00*/ @P0 BRA 0xc00 ; /* 0xfffffdf000000947 */
/* 0x000fea000383ffff */
/*0e10*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fda0003f05270 */
/*0e20*/ @!P0 BRA 0xf50 ; /* 0x0000012000008947 */
/* 0x000fea0003800000 */
/*0e30*/ HFMA2.MMA R9, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff097435 */
/* 0x000fe200000001ff */
/*0e40*/ IMAD R6, R3, c[0x0][0x178], R4 ; /* 0x00005e0003067a24 */
/* 0x002fe400078e0204 */
/*0e50*/ IMAD R4, R4, c[0x0][0x178], R0 ; /* 0x00005e0004047a24 */
/* 0x001fce00078e0200 */
/*0e60*/ IMAD.WIDE R6, R6, R9, c[0x0][0x160] ; /* 0x0000580006067625 */
/* 0x000fc800078e0209 */
/*0e70*/ IMAD.WIDE R8, R4, R9, c[0x0][0x168] ; /* 0x00005a0004087625 */
/* 0x000fe200078e0209 */
/*0e80*/ MOV R13, R7 ; /* 0x00000007000d7202 */
/* 0x000fc80000000f00 */
/*0e90*/ MOV R7, R13 ; /* 0x0000000d00077202 */
/* 0x000fe20000000f00 */
/*0ea0*/ LDG.E R4, [R8.64] ; /* 0x0000000408047981 */
/* 0x0000aa000c1e1900 */
/*0eb0*/ LDG.E R7, [R6.64] ; /* 0x0000000406077981 */
/* 0x0002a2000c1e1900 */
/*0ec0*/ IADD3 R5, R5, -0x1, RZ ; /* 0xffffffff05057810 */
/* 0x000fc80007ffe0ff */
/*0ed0*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe20003f05270 */
/*0ee0*/ IMAD.WIDE R8, R2, 0x4, R8 ; /* 0x0000000402087825 */
/* 0x001fe200078e0208 */
/*0ef0*/ IADD3 R6, P1, R6, 0x4, RZ ; /* 0x0000000406067810 */
/* 0x002fc80007f3e0ff */
/*0f00*/ IADD3.X R13, RZ, R13, RZ, P1, !PT ; /* 0x0000000dff0d7210 */
/* 0x000fe20000ffe4ff */
/*0f10*/ IMAD R4, R4, R7, RZ ; /* 0x0000000704047224 */
/* 0x004fcc00078e02ff */
/*0f20*/ I2F R4, R4 ; /* 0x0000000400047306 */
/* 0x000e240000201400 */
/*0f30*/ FADD R11, R4, R11 ; /* 0x0000000b040b7221 */
/* 0x001fe20000000000 */
/*0f40*/ @P0 BRA 0xe90 ; /* 0xffffff4000000947 */
/* 0x000fea000383ffff */
/*0f50*/ F2I.TRUNC.NTZ R11, R11 ; /* 0x0000000b000b7305 */
/* 0x000ea2000020f100 */
/*0f60*/ MOV R2, 0x4 ; /* 0x0000000400027802 */
/* 0x000fe20000000f00 */
/*0f70*/ IMAD R3, R3, c[0x0][0x178], R0 ; /* 0x00005e0003037a24 */
/* 0x003fc800078e0200 */
/*0f80*/ IMAD.WIDE R2, R3, R2, c[0x0][0x170] ; /* 0x00005c0003027625 */
/* 0x000fca00078e0202 */
/*0f90*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x004fe2000c101904 */
/*0fa0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0fb0*/ BRA 0xfb0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0fc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0fd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0fe0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ff0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1000*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1010*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1020*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | // On Maverick2: sbatch mvk2GPUMatMul
// nvcc BrodayWalker1B.cu -o BrodayWalker1B.exe
//***************************************************************************
// Name: Broday Walker
// Instructor: Dr. Colmenares
// Class: CMPS 5433
// Date: March 2, 2020
//***************************************************************************
// This program implements matrix multiplication using a GPU on Maverick2.
// The program reports the elapsed time taken to complete the matrix
// multiplication in milliseconds. It is significantly faster than its
// sequential counterpart.
//***************************************************************************
#include <stdio.h>
#include <cuda.h>
enum N {N = 32};
// matmulKernel performs matrix multiplication on a linearized array
// This code was given in the slides and adapted for use here
__global__ void matmulKernel(int *Ad, int *Bd, int *Cd, int width)
{
int tx = threadIdx.x;
int ty = threadIdx.y;
float sum = 0;
for (int k = 0; k < width; k++)
{
int Aelement = Ad[ty * width + k];
int Belement = Bd[k * width + tx];
sum += Aelement * Belement;
}
Cd[ty * width + tx] = sum;
}
int main()
{
// Declarations
int A[N * N], B[N * N], C[N * N];
int *Ad, *Bd, *Cd;
int size = N * N * sizeof(int);
int sum = 0;
// Declare the timer
// Reference:
// https://devblogs.nvidia.com/how-implement-performance-metrics-cuda-cc/
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
float milliseconds = 0;
// Fill arrays A and C
// Array C will be filled with 0s
for (int i = 0; i < N; i++)
for (int j = 0; j < N; j++)
{
A[i * N + j] = i;
C[i * N + j] = 0;
}
// Fill B
int row = N - 1;
for (int i = 0; i < N; i++)
{
for (int j = 0; j < N; j++)
B[i * N + j] = row;
row--;
}
/* Allocate memory and copy to device */
cudaMalloc((void**)&Ad, size);
cudaMemcpy(Ad, A, size, cudaMemcpyHostToDevice);
cudaMalloc((void**)&Bd, size);
cudaMemcpy(Bd, B, size, cudaMemcpyHostToDevice);
cudaMalloc((void**)&Cd, size);
/* End memory allocation and copying to device */
/* Define grid and block dimensions */
dim3 dimGrid( 1, 1 );
dim3 dimBlock( N, N );
/* Record start time */
cudaEventRecord(start);
/* Invoke the kernel */
matmulKernel<<<dimGrid, dimBlock>>>(Ad, Bd, Cd, N);
/* Record end time */
cudaEventRecord(stop);
/* Copy the matrix multiplication results from device to host */
cudaMemcpy(C, Cd, size, cudaMemcpyDeviceToHost);
/* Block CPU execution until the specified event is recorded */
cudaEventSynchronize(stop);
/* Returns the elapsed time in milliseconds to the first argument */
cudaEventElapsedTime(&milliseconds, start, stop);
cudaFree(Ad);
cudaFree(Bd);
cudaFree(Cd);
// Sum the array and print the results
for (int i = 0; i < N * N; i++)
sum += C[i];
// Print results
printf("The summation of all the elements is %d.\n", sum);
// Print elapsed time
printf("\nElapsed time in milliseconds: %f.\n", milliseconds);
return 0;
} | .file "tmpxft_0008c0d3_00000000-6_BrodayWalker1B.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z37__device_stub__Z12matmulKernelPiS_S_iPiS_S_i
.type _Z37__device_stub__Z12matmulKernelPiS_S_iPiS_S_i, @function
_Z37__device_stub__Z12matmulKernelPiS_S_iPiS_S_i:
.LFB2082:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z12matmulKernelPiS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z37__device_stub__Z12matmulKernelPiS_S_iPiS_S_i, .-_Z37__device_stub__Z12matmulKernelPiS_S_iPiS_S_i
.globl _Z12matmulKernelPiS_S_i
.type _Z12matmulKernelPiS_S_i, @function
_Z12matmulKernelPiS_S_i:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z37__device_stub__Z12matmulKernelPiS_S_iPiS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z12matmulKernelPiS_S_i, .-_Z12matmulKernelPiS_S_i
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "The summation of all the elements is %d.\n"
.align 8
.LC2:
.string "\nElapsed time in milliseconds: %f.\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $4096, %rsp
.cfi_def_cfa_offset 4112
orq $0, (%rsp)
subq $4096, %rsp
.cfi_def_cfa_offset 8208
orq $0, (%rsp)
subq $4096, %rsp
.cfi_def_cfa_offset 12304
orq $0, (%rsp)
subq $96, %rsp
.cfi_def_cfa_offset 12400
movq %fs:40, %rax
movq %rax, 12376(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rdi
call cudaEventCreate@PLT
leaq 48(%rsp), %rdi
call cudaEventCreate@PLT
movl $0x00000000, 12(%rsp)
leaq 80(%rsp), %rsi
leaq 8272(%rsp), %rbx
movq %rbx, %rcx
movl $0, %edx
.L12:
movl $0, %eax
.L13:
movl %edx, (%rsi,%rax)
movl $0, (%rcx,%rax)
addq $4, %rax
cmpq $128, %rax
jne .L13
addl $1, %edx
subq $-128, %rsi
subq $-128, %rcx
cmpl $32, %edx
jne .L12
leaq 4304(%rsp), %rcx
movl $31, %edx
.L14:
leaq -128(%rcx), %rax
.L15:
movl %edx, (%rax)
addq $4, %rax
cmpq %rcx, %rax
jne .L15
subl $1, %edx
subq $-128, %rcx
cmpl $-1, %edx
jne .L14
leaq 16(%rsp), %rdi
movl $4096, %esi
call cudaMalloc@PLT
leaq 80(%rsp), %rsi
movl $1, %ecx
movl $4096, %edx
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
leaq 24(%rsp), %rdi
movl $4096, %esi
call cudaMalloc@PLT
leaq 4176(%rsp), %rsi
movl $1, %ecx
movl $4096, %edx
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
leaq 32(%rsp), %rdi
movl $4096, %esi
call cudaMalloc@PLT
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $32, 68(%rsp)
movl $32, 72(%rsp)
movl $1, 76(%rsp)
movl $0, %esi
movq 40(%rsp), %rdi
call cudaEventRecord@PLT
movl 76(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 68(%rsp), %rdx
movq 56(%rsp), %rdi
movl 64(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L25
.L17:
movl $0, %esi
movq 48(%rsp), %rdi
call cudaEventRecord@PLT
leaq 8272(%rsp), %rdi
movl $2, %ecx
movl $4096, %edx
movq 32(%rsp), %rsi
call cudaMemcpy@PLT
movq 48(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 12(%rsp), %rdi
movq 48(%rsp), %rdx
movq 40(%rsp), %rsi
call cudaEventElapsedTime@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
leaq 4096(%rbx), %rcx
movl $0, %eax
.L18:
addl (%rbx), %eax
movl %eax, %edx
addq $4, %rbx
cmpq %rcx, %rbx
jne .L18
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
pxor %xmm0, %xmm0
cvtss2sd 12(%rsp), %xmm0
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 12376(%rsp), %rax
subq %fs:40, %rax
jne .L26
movl $0, %eax
addq $12384, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L25:
.cfi_restore_state
movl $32, %ecx
movq 32(%rsp), %rdx
movq 24(%rsp), %rsi
movq 16(%rsp), %rdi
call _Z37__device_stub__Z12matmulKernelPiS_S_iPiS_S_i
jmp .L17
.L26:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC3:
.string "_Z12matmulKernelPiS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z12matmulKernelPiS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | // On Maverick2: sbatch mvk2GPUMatMul
// nvcc BrodayWalker1B.cu -o BrodayWalker1B.exe
//***************************************************************************
// Name: Broday Walker
// Instructor: Dr. Colmenares
// Class: CMPS 5433
// Date: March 2, 2020
//***************************************************************************
// This program implements matrix multiplication using a GPU on Maverick2.
// The program reports the elapsed time taken to complete the matrix
// multiplication in milliseconds. It is significantly faster than its
// sequential counterpart.
//***************************************************************************
#include <stdio.h>
#include <cuda.h>
enum N {N = 32};
// matmulKernel performs matrix multiplication on a linearized array
// This code was given in the slides and adapted for use here
__global__ void matmulKernel(int *Ad, int *Bd, int *Cd, int width)
{
int tx = threadIdx.x;
int ty = threadIdx.y;
float sum = 0;
for (int k = 0; k < width; k++)
{
int Aelement = Ad[ty * width + k];
int Belement = Bd[k * width + tx];
sum += Aelement * Belement;
}
Cd[ty * width + tx] = sum;
}
int main()
{
// Declarations
int A[N * N], B[N * N], C[N * N];
int *Ad, *Bd, *Cd;
int size = N * N * sizeof(int);
int sum = 0;
// Declare the timer
// Reference:
// https://devblogs.nvidia.com/how-implement-performance-metrics-cuda-cc/
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
float milliseconds = 0;
// Fill arrays A and C
// Array C will be filled with 0s
for (int i = 0; i < N; i++)
for (int j = 0; j < N; j++)
{
A[i * N + j] = i;
C[i * N + j] = 0;
}
// Fill B
int row = N - 1;
for (int i = 0; i < N; i++)
{
for (int j = 0; j < N; j++)
B[i * N + j] = row;
row--;
}
/* Allocate memory and copy to device */
cudaMalloc((void**)&Ad, size);
cudaMemcpy(Ad, A, size, cudaMemcpyHostToDevice);
cudaMalloc((void**)&Bd, size);
cudaMemcpy(Bd, B, size, cudaMemcpyHostToDevice);
cudaMalloc((void**)&Cd, size);
/* End memory allocation and copying to device */
/* Define grid and block dimensions */
dim3 dimGrid( 1, 1 );
dim3 dimBlock( N, N );
/* Record start time */
cudaEventRecord(start);
/* Invoke the kernel */
matmulKernel<<<dimGrid, dimBlock>>>(Ad, Bd, Cd, N);
/* Record end time */
cudaEventRecord(stop);
/* Copy the matrix multiplication results from device to host */
cudaMemcpy(C, Cd, size, cudaMemcpyDeviceToHost);
/* Block CPU execution until the specified event is recorded */
cudaEventSynchronize(stop);
/* Returns the elapsed time in milliseconds to the first argument */
cudaEventElapsedTime(&milliseconds, start, stop);
cudaFree(Ad);
cudaFree(Bd);
cudaFree(Cd);
// Sum the array and print the results
for (int i = 0; i < N * N; i++)
sum += C[i];
// Print results
printf("The summation of all the elements is %d.\n", sum);
// Print elapsed time
printf("\nElapsed time in milliseconds: %f.\n", milliseconds);
return 0;
} | // On Maverick2: sbatch mvk2GPUMatMul
// nvcc BrodayWalker1B.cu -o BrodayWalker1B.exe
//***************************************************************************
// Name: Broday Walker
// Instructor: Dr. Colmenares
// Class: CMPS 5433
// Date: March 2, 2020
//***************************************************************************
// This program implements matrix multiplication using a GPU on Maverick2.
// The program reports the elapsed time taken to complete the matrix
// multiplication in milliseconds. It is significantly faster than its
// sequential counterpart.
//***************************************************************************
#include <stdio.h>
#include <hip/hip_runtime.h>
enum N {N = 32};
// matmulKernel performs matrix multiplication on a linearized array
// This code was given in the slides and adapted for use here
__global__ void matmulKernel(int *Ad, int *Bd, int *Cd, int width)
{
int tx = threadIdx.x;
int ty = threadIdx.y;
float sum = 0;
for (int k = 0; k < width; k++)
{
int Aelement = Ad[ty * width + k];
int Belement = Bd[k * width + tx];
sum += Aelement * Belement;
}
Cd[ty * width + tx] = sum;
}
int main()
{
// Declarations
int A[N * N], B[N * N], C[N * N];
int *Ad, *Bd, *Cd;
int size = N * N * sizeof(int);
int sum = 0;
// Declare the timer
// Reference:
// https://devblogs.nvidia.com/how-implement-performance-metrics-cuda-cc/
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
float milliseconds = 0;
// Fill arrays A and C
// Array C will be filled with 0s
for (int i = 0; i < N; i++)
for (int j = 0; j < N; j++)
{
A[i * N + j] = i;
C[i * N + j] = 0;
}
// Fill B
int row = N - 1;
for (int i = 0; i < N; i++)
{
for (int j = 0; j < N; j++)
B[i * N + j] = row;
row--;
}
/* Allocate memory and copy to device */
hipMalloc((void**)&Ad, size);
hipMemcpy(Ad, A, size, hipMemcpyHostToDevice);
hipMalloc((void**)&Bd, size);
hipMemcpy(Bd, B, size, hipMemcpyHostToDevice);
hipMalloc((void**)&Cd, size);
/* End memory allocation and copying to device */
/* Define grid and block dimensions */
dim3 dimGrid( 1, 1 );
dim3 dimBlock( N, N );
/* Record start time */
hipEventRecord(start);
/* Invoke the kernel */
matmulKernel<<<dimGrid, dimBlock>>>(Ad, Bd, Cd, N);
/* Record end time */
hipEventRecord(stop);
/* Copy the matrix multiplication results from device to host */
hipMemcpy(C, Cd, size, hipMemcpyDeviceToHost);
/* Block CPU execution until the specified event is recorded */
hipEventSynchronize(stop);
/* Returns the elapsed time in milliseconds to the first argument */
hipEventElapsedTime(&milliseconds, start, stop);
hipFree(Ad);
hipFree(Bd);
hipFree(Cd);
// Sum the array and print the results
for (int i = 0; i < N * N; i++)
sum += C[i];
// Print results
printf("The summation of all the elements is %d.\n", sum);
// Print elapsed time
printf("\nElapsed time in milliseconds: %f.\n", milliseconds);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | // On Maverick2: sbatch mvk2GPUMatMul
// nvcc BrodayWalker1B.cu -o BrodayWalker1B.exe
//***************************************************************************
// Name: Broday Walker
// Instructor: Dr. Colmenares
// Class: CMPS 5433
// Date: March 2, 2020
//***************************************************************************
// This program implements matrix multiplication using a GPU on Maverick2.
// The program reports the elapsed time taken to complete the matrix
// multiplication in milliseconds. It is significantly faster than its
// sequential counterpart.
//***************************************************************************
#include <stdio.h>
#include <hip/hip_runtime.h>
enum N {N = 32};
// matmulKernel performs matrix multiplication on a linearized array
// This code was given in the slides and adapted for use here
__global__ void matmulKernel(int *Ad, int *Bd, int *Cd, int width)
{
int tx = threadIdx.x;
int ty = threadIdx.y;
float sum = 0;
for (int k = 0; k < width; k++)
{
int Aelement = Ad[ty * width + k];
int Belement = Bd[k * width + tx];
sum += Aelement * Belement;
}
Cd[ty * width + tx] = sum;
}
int main()
{
// Declarations
int A[N * N], B[N * N], C[N * N];
int *Ad, *Bd, *Cd;
int size = N * N * sizeof(int);
int sum = 0;
// Declare the timer
// Reference:
// https://devblogs.nvidia.com/how-implement-performance-metrics-cuda-cc/
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
float milliseconds = 0;
// Fill arrays A and C
// Array C will be filled with 0s
for (int i = 0; i < N; i++)
for (int j = 0; j < N; j++)
{
A[i * N + j] = i;
C[i * N + j] = 0;
}
// Fill B
int row = N - 1;
for (int i = 0; i < N; i++)
{
for (int j = 0; j < N; j++)
B[i * N + j] = row;
row--;
}
/* Allocate memory and copy to device */
hipMalloc((void**)&Ad, size);
hipMemcpy(Ad, A, size, hipMemcpyHostToDevice);
hipMalloc((void**)&Bd, size);
hipMemcpy(Bd, B, size, hipMemcpyHostToDevice);
hipMalloc((void**)&Cd, size);
/* End memory allocation and copying to device */
/* Define grid and block dimensions */
dim3 dimGrid( 1, 1 );
dim3 dimBlock( N, N );
/* Record start time */
hipEventRecord(start);
/* Invoke the kernel */
matmulKernel<<<dimGrid, dimBlock>>>(Ad, Bd, Cd, N);
/* Record end time */
hipEventRecord(stop);
/* Copy the matrix multiplication results from device to host */
hipMemcpy(C, Cd, size, hipMemcpyDeviceToHost);
/* Block CPU execution until the specified event is recorded */
hipEventSynchronize(stop);
/* Returns the elapsed time in milliseconds to the first argument */
hipEventElapsedTime(&milliseconds, start, stop);
hipFree(Ad);
hipFree(Bd);
hipFree(Cd);
// Sum the array and print the results
for (int i = 0; i < N * N; i++)
sum += C[i];
// Print results
printf("The summation of all the elements is %d.\n", sum);
// Print elapsed time
printf("\nElapsed time in milliseconds: %f.\n", milliseconds);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z12matmulKernelPiS_S_i
.globl _Z12matmulKernelPiS_S_i
.p2align 8
.type _Z12matmulKernelPiS_S_i,@function
_Z12matmulKernelPiS_S_i:
s_load_b32 s2, s[0:1], 0x18
v_and_b32_e32 v1, 0x3ff, v0
v_bfe_u32 v0, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s2, 1
s_cbranch_scc1 .LBB0_4
s_load_b128 s[4:7], s[0:1], 0x0
v_mul_lo_u32 v2, v0, s2
v_mov_b32_e32 v3, 0
s_mov_b32 s3, s2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[4:5], 2, v[2:3]
v_mov_b32_e32 v2, v1
v_mov_b32_e32 v6, v3
s_waitcnt lgkmcnt(0)
v_add_co_u32 v4, vcc_lo, s4, v4
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
.p2align 6
.LBB0_2:
v_lshlrev_b64 v[7:8], 2, v[2:3]
v_add_nc_u32_e32 v2, s2, v2
s_add_i32 s3, s3, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
s_cmp_eq_u32 s3, 0
v_add_co_u32 v7, vcc_lo, s6, v7
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v8, vcc_lo, s7, v8, vcc_lo
global_load_b32 v9, v[4:5], off
global_load_b32 v7, v[7:8], off
v_add_co_u32 v4, vcc_lo, v4, 4
v_add_co_ci_u32_e32 v5, vcc_lo, 0, v5, vcc_lo
s_waitcnt vmcnt(0)
v_mul_lo_u32 v7, v7, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_f32_i32_e32 v7, v7
v_add_f32_e32 v6, v6, v7
s_cbranch_scc0 .LBB0_2
s_delay_alu instid0(VALU_DEP_1)
v_cvt_i32_f32_e32 v2, v6
s_branch .LBB0_5
.LBB0_4:
v_mov_b32_e32 v2, 0
.LBB0_5:
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[3:4], null, v0, s2, v[1:2]
v_ashrrev_i32_e32 v4, 31, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[3:4]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12matmulKernelPiS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 28
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 10
.amdhsa_next_free_sgpr 8
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z12matmulKernelPiS_S_i, .Lfunc_end0-_Z12matmulKernelPiS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 28
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12matmulKernelPiS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 10
.sgpr_spill_count: 0
.symbol: _Z12matmulKernelPiS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 10
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | // On Maverick2: sbatch mvk2GPUMatMul
// nvcc BrodayWalker1B.cu -o BrodayWalker1B.exe
//***************************************************************************
// Name: Broday Walker
// Instructor: Dr. Colmenares
// Class: CMPS 5433
// Date: March 2, 2020
//***************************************************************************
// This program implements matrix multiplication using a GPU on Maverick2.
// The program reports the elapsed time taken to complete the matrix
// multiplication in milliseconds. It is significantly faster than its
// sequential counterpart.
//***************************************************************************
#include <stdio.h>
#include <hip/hip_runtime.h>
enum N {N = 32};
// matmulKernel performs matrix multiplication on a linearized array
// This code was given in the slides and adapted for use here
__global__ void matmulKernel(int *Ad, int *Bd, int *Cd, int width)
{
int tx = threadIdx.x;
int ty = threadIdx.y;
float sum = 0;
for (int k = 0; k < width; k++)
{
int Aelement = Ad[ty * width + k];
int Belement = Bd[k * width + tx];
sum += Aelement * Belement;
}
Cd[ty * width + tx] = sum;
}
int main()
{
// Declarations
int A[N * N], B[N * N], C[N * N];
int *Ad, *Bd, *Cd;
int size = N * N * sizeof(int);
int sum = 0;
// Declare the timer
// Reference:
// https://devblogs.nvidia.com/how-implement-performance-metrics-cuda-cc/
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
float milliseconds = 0;
// Fill arrays A and C
// Array C will be filled with 0s
for (int i = 0; i < N; i++)
for (int j = 0; j < N; j++)
{
A[i * N + j] = i;
C[i * N + j] = 0;
}
// Fill B
int row = N - 1;
for (int i = 0; i < N; i++)
{
for (int j = 0; j < N; j++)
B[i * N + j] = row;
row--;
}
/* Allocate memory and copy to device */
hipMalloc((void**)&Ad, size);
hipMemcpy(Ad, A, size, hipMemcpyHostToDevice);
hipMalloc((void**)&Bd, size);
hipMemcpy(Bd, B, size, hipMemcpyHostToDevice);
hipMalloc((void**)&Cd, size);
/* End memory allocation and copying to device */
/* Define grid and block dimensions */
dim3 dimGrid( 1, 1 );
dim3 dimBlock( N, N );
/* Record start time */
hipEventRecord(start);
/* Invoke the kernel */
matmulKernel<<<dimGrid, dimBlock>>>(Ad, Bd, Cd, N);
/* Record end time */
hipEventRecord(stop);
/* Copy the matrix multiplication results from device to host */
hipMemcpy(C, Cd, size, hipMemcpyDeviceToHost);
/* Block CPU execution until the specified event is recorded */
hipEventSynchronize(stop);
/* Returns the elapsed time in milliseconds to the first argument */
hipEventElapsedTime(&milliseconds, start, stop);
hipFree(Ad);
hipFree(Bd);
hipFree(Cd);
// Sum the array and print the results
for (int i = 0; i < N * N; i++)
sum += C[i];
// Print results
printf("The summation of all the elements is %d.\n", sum);
// Print elapsed time
printf("\nElapsed time in milliseconds: %f.\n", milliseconds);
return 0;
} | .text
.file "BrodayWalker1B.hip"
.globl _Z27__device_stub__matmulKernelPiS_S_i # -- Begin function _Z27__device_stub__matmulKernelPiS_S_i
.p2align 4, 0x90
.type _Z27__device_stub__matmulKernelPiS_S_i,@function
_Z27__device_stub__matmulKernelPiS_S_i: # @_Z27__device_stub__matmulKernelPiS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z12matmulKernelPiS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z27__device_stub__matmulKernelPiS_S_i, .Lfunc_end0-_Z27__device_stub__matmulKernelPiS_S_i
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $12448, %rsp # imm = 0x30A0
.cfi_def_cfa_offset 12464
.cfi_offset %rbx, -16
leaq 48(%rsp), %rdi
callq hipEventCreate
leaq 8(%rsp), %rdi
callq hipEventCreate
movl $0, 4(%rsp)
leaq 160(%rsp), %rdi
xorl %ebx, %ebx
movl $4096, %edx # imm = 0x1000
xorl %esi, %esi
callq memset@PLT
leaq 8352(%rsp), %rax
.p2align 4, 0x90
.LBB1_1: # %.preheader44
# =>This Loop Header: Depth=1
# Child Loop BB1_2 Depth 2
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB1_2: # Parent Loop BB1_1 Depth=1
# => This Inner Loop Header: Depth=2
movl %ebx, (%rax,%rcx,4)
incq %rcx
cmpq $32, %rcx
jne .LBB1_2
# %bb.3: # in Loop: Header=BB1_1 Depth=1
incq %rbx
subq $-128, %rax
cmpq $32, %rbx
jne .LBB1_1
# %bb.4: # %.preheader.preheader
movl $31, %eax
leaq 4256(%rsp), %rcx
xorl %edx, %edx
.p2align 4, 0x90
.LBB1_5: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_6 Depth 2
xorl %esi, %esi
.p2align 4, 0x90
.LBB1_6: # Parent Loop BB1_5 Depth=1
# => This Inner Loop Header: Depth=2
movl %eax, (%rcx,%rsi,4)
incq %rsi
cmpq $32, %rsi
jne .LBB1_6
# %bb.7: # in Loop: Header=BB1_5 Depth=1
decl %eax
incq %rdx
subq $-128, %rcx
cmpq $32, %rdx
jne .LBB1_5
# %bb.8:
leaq 32(%rsp), %rdi
movl $4096, %esi # imm = 0x1000
callq hipMalloc
movq 32(%rsp), %rdi
leaq 8352(%rsp), %rsi
movl $4096, %edx # imm = 0x1000
movl $1, %ecx
callq hipMemcpy
leaq 24(%rsp), %rdi
movl $4096, %esi # imm = 0x1000
callq hipMalloc
movq 24(%rsp), %rdi
leaq 4256(%rsp), %rsi
movl $4096, %edx # imm = 0x1000
movl $1, %ecx
callq hipMemcpy
leaq 16(%rsp), %rdi
movl $4096, %esi # imm = 0x1000
callq hipMalloc
movq 48(%rsp), %rdi
xorl %ebx, %ebx
xorl %esi, %esi
callq hipEventRecord
movabsq $4294967297, %rdi # imm = 0x100000001
movabsq $137438953504, %rdx # imm = 0x2000000020
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_10
# %bb.9:
movq 32(%rsp), %rax
movq 24(%rsp), %rcx
movq 16(%rsp), %rdx
movq %rax, 120(%rsp)
movq %rcx, 112(%rsp)
movq %rdx, 104(%rsp)
movl $32, 44(%rsp)
leaq 120(%rsp), %rax
movq %rax, 128(%rsp)
leaq 112(%rsp), %rax
movq %rax, 136(%rsp)
leaq 104(%rsp), %rax
movq %rax, 144(%rsp)
leaq 44(%rsp), %rax
movq %rax, 152(%rsp)
leaq 88(%rsp), %rdi
leaq 72(%rsp), %rsi
leaq 64(%rsp), %rdx
leaq 56(%rsp), %rcx
callq __hipPopCallConfiguration
movq 88(%rsp), %rsi
movl 96(%rsp), %edx
movq 72(%rsp), %rcx
movl 80(%rsp), %r8d
leaq 128(%rsp), %r9
movl $_Z12matmulKernelPiS_S_i, %edi
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_10:
movq 8(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 16(%rsp), %rsi
leaq 160(%rsp), %rdi
movl $4096, %edx # imm = 0x1000
movl $2, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
callq hipEventSynchronize
movq 48(%rsp), %rsi
movq 8(%rsp), %rdx
leaq 4(%rsp), %rdi
callq hipEventElapsedTime
movq 32(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_11: # =>This Inner Loop Header: Depth=1
addl 160(%rsp,%rax,4), %ebx
incq %rax
cmpq $1024, %rax # imm = 0x400
jne .LBB1_11
# %bb.12:
movl $.L.str, %edi
movl %ebx, %esi
xorl %eax, %eax
callq printf
movss 4(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.1, %edi
movb $1, %al
callq printf
xorl %eax, %eax
addq $12448, %rsp # imm = 0x30A0
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12matmulKernelPiS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z12matmulKernelPiS_S_i,@object # @_Z12matmulKernelPiS_S_i
.section .rodata,"a",@progbits
.globl _Z12matmulKernelPiS_S_i
.p2align 3, 0x0
_Z12matmulKernelPiS_S_i:
.quad _Z27__device_stub__matmulKernelPiS_S_i
.size _Z12matmulKernelPiS_S_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "The summation of all the elements is %d.\n"
.size .L.str, 42
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "\nElapsed time in milliseconds: %f.\n"
.size .L.str.1, 36
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z12matmulKernelPiS_S_i"
.size .L__unnamed_1, 24
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__matmulKernelPiS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12matmulKernelPiS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z12matmulKernelPiS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e220000002100 */
/*0020*/ MOV R2, c[0x0][0x178] ; /* 0x00005e0000027a02 */
/* 0x000fe20000000f00 */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ HFMA2.MMA R11, -RZ, RZ, 0, 0 ; /* 0x00000000ff0b7435 */
/* 0x000fe200000001ff */
/*0050*/ S2R R3, SR_TID.Y ; /* 0x0000000000037919 */
/* 0x000e620000002200 */
/*0060*/ ISETP.GE.AND P0, PT, R2, 0x1, PT ; /* 0x000000010200780c */
/* 0x000fda0003f06270 */
/*0070*/ @!P0 BRA 0xf50 ; /* 0x00000ed000008947 */
/* 0x000fea0003800000 */
/*0080*/ IADD3 R4, R2.reuse, -0x1, RZ ; /* 0xffffffff02047810 */
/* 0x040fe40007ffe0ff */
/*0090*/ LOP3.LUT R5, R2, 0x3, RZ, 0xc0, !PT ; /* 0x0000000302057812 */
/* 0x000fe400078ec0ff */
/*00a0*/ ISETP.GE.U32.AND P0, PT, R4, 0x3, PT ; /* 0x000000030400780c */
/* 0x000fe40003f06070 */
/*00b0*/ MOV R11, RZ ; /* 0x000000ff000b7202 */
/* 0x000fe40000000f00 */
/*00c0*/ MOV R4, RZ ; /* 0x000000ff00047202 */
/* 0x000fd20000000f00 */
/*00d0*/ @!P0 BRA 0xe10 ; /* 0x00000d3000008947 */
/* 0x000fea0003800000 */
/*00e0*/ IADD3 R7, -R5, c[0x0][0x178], RZ ; /* 0x00005e0005077a10 */
/* 0x000fe20007ffe1ff */
/*00f0*/ HFMA2.MMA R23, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff177435 */
/* 0x000fe200000001ff */
/*0100*/ ULDC.64 UR6, c[0x0][0x160] ; /* 0x0000580000067ab9 */
/* 0x000fe20000000a00 */
/*0110*/ HFMA2.MMA R4, -RZ, RZ, 0, 0 ; /* 0x00000000ff047435 */
/* 0x000fe200000001ff */
/*0120*/ ISETP.GT.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fe20003f04270 */
/*0130*/ IMAD R6, R3, c[0x0][0x178], RZ ; /* 0x00005e0003067a24 */
/* 0x002fe200078e02ff */
/*0140*/ MOV R11, RZ ; /* 0x000000ff000b7202 */
/* 0x000fca0000000f00 */
/*0150*/ IMAD.WIDE R22, R0, R23, c[0x0][0x168] ; /* 0x00005a0000167625 */
/* 0x001fcc00078e0217 */
/*0160*/ @!P0 BRA 0xc00 ; /* 0x00000a9000008947 */
/* 0x000fea0003800000 */
/*0170*/ ISETP.GT.AND P1, PT, R7, 0xc, PT ; /* 0x0000000c0700780c */
/* 0x000fe40003f24270 */
/*0180*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*0190*/ @!P1 BRA 0x840 ; /* 0x000006a000009947 */
/* 0x000fea0003800000 */
/*01a0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*01b0*/ MOV R14, UR6 ; /* 0x00000006000e7c02 */
/* 0x000fe20008000f00 */
/*01c0*/ IMAD.WIDE R16, R2, 0x4, R22 ; /* 0x0000000402107825 */
/* 0x000fe200078e0216 */
/*01d0*/ MOV R15, UR7 ; /* 0x00000007000f7c02 */
/* 0x000fe20008000f00 */
/*01e0*/ LDG.E R8, [R22.64] ; /* 0x0000000416087981 */
/* 0x0000a8000c1e1900 */
/*01f0*/ IMAD.WIDE R14, R6, 0x4, R14 ; /* 0x00000004060e7825 */
/* 0x000fe200078e020e */
/*0200*/ LDG.E R10, [R16.64] ; /* 0x00000004100a7981 */
/* 0x0002e8000c1e1900 */
/*0210*/ LDG.E R9, [R14.64] ; /* 0x000000040e097981 */
/* 0x000ea2000c1e1900 */
/*0220*/ IMAD.WIDE R12, R2, 0x4, R16 ; /* 0x00000004020c7825 */
/* 0x000fc600078e0210 */
/*0230*/ LDG.E R29, [R14.64+0x4] ; /* 0x000004040e1d7981 */
/* 0x000ee8000c1e1900 */
/*0240*/ LDG.E R26, [R12.64] ; /* 0x000000040c1a7981 */
/* 0x000968000c1e1900 */
/*0250*/ LDG.E R27, [R14.64+0x8] ; /* 0x000008040e1b7981 */
/* 0x000f68000c1e1900 */
/*0260*/ LDG.E R21, [R14.64+0xc] ; /* 0x00000c040e157981 */
/* 0x000f62000c1e1900 */
/*0270*/ IMAD.WIDE R12, R2, 0x4, R12 ; /* 0x00000004020c7825 */
/* 0x010fc600078e020c */
/*0280*/ LDG.E R23, [R14.64+0x14] ; /* 0x000014040e177981 */
/* 0x001f28000c1e1900 */
/*0290*/ LDG.E R20, [R12.64] ; /* 0x000000040c147981 */
/* 0x000122000c1e1900 */
/*02a0*/ IMAD.WIDE R18, R2, 0x4, R12 ; /* 0x0000000402127825 */
/* 0x000fc600078e020c */
/*02b0*/ LDG.E R25, [R14.64+0x10] ; /* 0x000010040e197981 */
/* 0x000f26000c1e1900 */
/*02c0*/ IMAD.WIDE R16, R2.reuse, 0x4, R18 ; /* 0x0000000402107825 */
/* 0x042fe200078e0212 */
/*02d0*/ LDG.E R22, [R18.64] ; /* 0x0000000412167981 */
/* 0x000328000c1e1900 */
/*02e0*/ LDG.E R24, [R16.64] ; /* 0x0000000410187981 */
/* 0x000322000c1e1900 */
/*02f0*/ IMAD.WIDE R12, R2, 0x4, R16 ; /* 0x00000004020c7825 */
/* 0x001fc800078e0210 */
/*0300*/ IMAD R8, R8, R9, RZ ; /* 0x0000000908087224 */
/* 0x004fe400078e02ff */
/*0310*/ IMAD R10, R10, R29, RZ ; /* 0x0000001d0a0a7224 */
/* 0x008fc800078e02ff */
/*0320*/ I2F R8, R8 ; /* 0x0000000800087306 */
/* 0x000e220000201400 */
/*0330*/ IMAD R26, R26, R27, RZ ; /* 0x0000001b1a1a7224 */
/* 0x020fce00078e02ff */
/*0340*/ I2F R18, R10 ; /* 0x0000000a00127306 */
/* 0x0028620000201400 */
/*0350*/ IMAD.WIDE R28, R2, 0x4, R12 ; /* 0x00000004021c7825 */
/* 0x000fe200078e020c */
/*0360*/ LDG.E R27, [R12.64] ; /* 0x000000040c1b7981 */
/* 0x0004ec000c1e1900 */
/*0370*/ I2F R26, R26 ; /* 0x0000001a001a7306 */
/* 0x000f620000201400 */
/*0380*/ IMAD R10, R20, R21, RZ ; /* 0x00000015140a7224 */
/* 0x010fe400078e02ff */
/*0390*/ FADD R11, R8, R11 ; /* 0x0000000b080b7221 */
/* 0x001fe20000000000 */
/*03a0*/ LDG.E R20, [R14.64+0x18] ; /* 0x000018040e147981 */
/* 0x000ee2000c1e1900 */
/*03b0*/ IMAD.WIDE R8, R2, 0x4, R28 ; /* 0x0000000402087825 */
/* 0x000fc600078e021c */
/*03c0*/ I2F R10, R10 ; /* 0x0000000a000a7306 */
/* 0x000e220000201400 */
/*03d0*/ LDG.E R28, [R28.64] ; /* 0x000000041c1c7981 */
/* 0x000f22000c1e1900 */
/*03e0*/ FADD R11, R11, R18 ; /* 0x000000120b0b7221 */
/* 0x002fe40000000000 */
/*03f0*/ IMAD.WIDE R18, R2.reuse, 0x4, R8 ; /* 0x0000000402127825 */
/* 0x040fe200078e0208 */
/*0400*/ LDG.E R21, [R14.64+0x1c] ; /* 0x00001c040e157981 */
/* 0x000f26000c1e1900 */
/*0410*/ FADD R11, R11, R26 ; /* 0x0000001a0b0b7221 */
/* 0x020fe20000000000 */
/*0420*/ LDG.E R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x000362000c1e1900 */
/*0430*/ IMAD.WIDE R16, R2, 0x4, R18 ; /* 0x0000000402107825 */
/* 0x000fc600078e0212 */
/*0440*/ LDG.E R12, [R14.64+0x24] ; /* 0x000024040e0c7981 */
/* 0x004ea2000c1e1900 */
/*0450*/ FADD R10, R11, R10 ; /* 0x0000000a0b0a7221 */
/* 0x001fc60000000000 */
/*0460*/ LDG.E R13, [R16.64] ; /* 0x00000004100d7981 */
/* 0x0000a8000c1e1900 */
/*0470*/ LDG.E R9, [R18.64] ; /* 0x0000000412097981 */
/* 0x0022a8000c1e1900 */
/*0480*/ LDG.E R11, [R14.64+0x20] ; /* 0x000020040e0b7981 */
/* 0x000f62000c1e1900 */
/*0490*/ IMAD.WIDE R16, R2, 0x4, R16 ; /* 0x0000000402107825 */
/* 0x001fc800078e0210 */
/*04a0*/ IMAD R23, R24, R23, RZ ; /* 0x0000001718177224 */
/* 0x000fe200078e02ff */
/*04b0*/ LDG.E R26, [R16.64] ; /* 0x00000004101a7981 */
/* 0x000162000c1e1900 */
/*04c0*/ IMAD R22, R22, R25, RZ ; /* 0x0000001916167224 */
/* 0x000fc600078e02ff */
/*04d0*/ LDG.E R24, [R14.64+0x28] ; /* 0x000028040e187981 */
/* 0x000f68000c1e1900 */
/*04e0*/ LDG.E R25, [R14.64+0x2c] ; /* 0x00002c040e197981 */
/* 0x000f62000c1e1900 */
/*04f0*/ IMAD.WIDE R18, R2, 0x4, R16 ; /* 0x0000000402127825 */
/* 0x002fc600078e0210 */
/*0500*/ LDG.E R17, [R14.64+0x30] ; /* 0x000030040e117981 */
/* 0x001162000c1e1900 */
/*0510*/ IMAD R27, R27, R20, RZ ; /* 0x000000141b1b7224 */
/* 0x008fe400078e02ff */
/*0520*/ IMAD R29, R28, R21, RZ ; /* 0x000000151c1d7224 */
/* 0x010fe400078e02ff */
/*0530*/ IMAD.WIDE R20, R2, 0x4, R18 ; /* 0x0000000402147825 */
/* 0x000fe200078e0212 */
/*0540*/ LDG.E R28, [R18.64] ; /* 0x00000004121c7981 */
/* 0x0002e8000c1e1900 */
/*0550*/ LDG.E R18, [R20.64] ; /* 0x0000000414127981 */
/* 0x002322000c1e1900 */
/*0560*/ IMAD R16, R9, R12, RZ ; /* 0x0000000c09107224 */
/* 0x004fc600078e02ff */
/*0570*/ LDG.E R19, [R14.64+0x34] ; /* 0x000034040e137981 */
/* 0x000122000c1e1900 */
/*0580*/ IMAD R11, R8, R11, RZ ; /* 0x0000000b080b7224 */
/* 0x020fe400078e02ff */
/*0590*/ IMAD.WIDE R8, R2, 0x4, R20 ; /* 0x0000000402087825 */
/* 0x000fc800078e0214 */
/*05a0*/ IMAD R24, R13, R24, RZ ; /* 0x000000180d187224 */
/* 0x000fe400078e02ff */
/*05b0*/ IMAD.WIDE R12, R2, 0x4, R8 ; /* 0x00000004020c7825 */
/* 0x000fc800078e0208 */
/*05c0*/ IMAD R26, R26, R25, RZ ; /* 0x000000191a1a7224 */
/* 0x000fe200078e02ff */
/*05d0*/ LDG.E R20, [R12.64] ; /* 0x000000040c147981 */
/* 0x002ea8000c1e1900 */
/*05e0*/ LDG.E R25, [R8.64] ; /* 0x0000000408197981 */
/* 0x000368000c1e1900 */
/*05f0*/ LDG.E R8, [R14.64+0x38] ; /* 0x000038040e087981 */
/* 0x002168000c1e1900 */
/*0600*/ LDG.E R9, [R14.64+0x3c] ; /* 0x00003c040e097981 */
/* 0x0000a2000c1e1900 */
/*0610*/ I2F R22, R22 ; /* 0x0000001600167306 */
/* 0x000e700000201400 */
/*0620*/ I2F R23, R23 ; /* 0x0000001700177306 */
/* 0x000e300000201400 */
/*0630*/ I2F R27, R27 ; /* 0x0000001b001b7306 */
/* 0x000e220000201400 */
/*0640*/ FADD R10, R10, R22 ; /* 0x000000160a0a7221 */
/* 0x002fce0000000000 */
/*0650*/ I2F R29, R29 ; /* 0x0000001d001d7306 */
/* 0x000e620000201400 */
/*0660*/ FADD R14, R10, R23 ; /* 0x000000170a0e7221 */
/* 0x001fce0000000000 */
/*0670*/ I2F R11, R11 ; /* 0x0000000b000b7306 */
/* 0x000e220000201400 */
/*0680*/ FADD R14, R14, R27 ; /* 0x0000001b0e0e7221 */
/* 0x000fce0000000000 */
/*0690*/ I2F R16, R16 ; /* 0x0000001000107306 */
/* 0x000e220000201400 */
/*06a0*/ FADD R14, R14, R29 ; /* 0x0000001d0e0e7221 */
/* 0x002fce0000000000 */
/*06b0*/ I2F R24, R24 ; /* 0x0000001800187306 */
/* 0x000e620000201400 */
/*06c0*/ FADD R11, R14, R11 ; /* 0x0000000b0e0b7221 */
/* 0x001fce0000000000 */
/*06d0*/ I2F R26, R26 ; /* 0x0000001a001a7306 */
/* 0x000e220000201400 */
/*06e0*/ FADD R11, R11, R16 ; /* 0x000000100b0b7221 */
/* 0x000fe20000000000 */
/*06f0*/ IADD3 R7, R7, -0x10, RZ ; /* 0xfffffff007077810 */
/* 0x000fc60007ffe0ff */
/*0700*/ FADD R11, R11, R24 ; /* 0x000000180b0b7221 */
/* 0x002fe20000000000 */
/*0710*/ ISETP.GT.AND P1, PT, R7, 0xc, PT ; /* 0x0000000c0700780c */
/* 0x000fc60003f24270 */
/*0720*/ FADD R11, R11, R26 ; /* 0x0000001a0b0b7221 */
/* 0x001fe20000000000 */
/*0730*/ UIADD3 UR6, UP0, UR6, 0x40, URZ ; /* 0x0000004006067890 */
/* 0x000fe2000ff1e03f */
/*0740*/ IADD3 R4, R4, 0x10, RZ ; /* 0x0000001004047810 */
/* 0x000fc60007ffe0ff */
/*0750*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0760*/ IMAD.WIDE R22, R2, 0x4, R12 ; /* 0x0000000402167825 */
/* 0x000fc800078e020c */
/*0770*/ IMAD R17, R28, R17, RZ ; /* 0x000000111c117224 */
/* 0x008fc800078e02ff */
/*0780*/ I2F R10, R17 ; /* 0x00000011000a7306 */
/* 0x000e220000201400 */
/*0790*/ IMAD R18, R18, R19, RZ ; /* 0x0000001312127224 */
/* 0x010fce00078e02ff */
/*07a0*/ I2F R15, R18 ; /* 0x00000012000f7306 */
/* 0x000e620000201400 */
/*07b0*/ FADD R10, R11, R10 ; /* 0x0000000a0b0a7221 */
/* 0x001fe40000000000 */
/*07c0*/ IMAD R8, R25, R8, RZ ; /* 0x0000000819087224 */
/* 0x020fe400078e02ff */
/*07d0*/ IMAD R9, R20, R9, RZ ; /* 0x0000000914097224 */
/* 0x004fc600078e02ff */
/*07e0*/ I2F R19, R8 ; /* 0x0000000800137306 */
/* 0x000e300000201400 */
/*07f0*/ I2F R9, R9 ; /* 0x0000000900097306 */
/* 0x000ea20000201400 */
/*0800*/ FADD R10, R10, R15 ; /* 0x0000000f0a0a7221 */
/* 0x002fc80000000000 */
/*0810*/ FADD R10, R10, R19 ; /* 0x000000130a0a7221 */
/* 0x001fc80000000000 */
/*0820*/ FADD R11, R10, R9 ; /* 0x000000090a0b7221 */
/* 0x004fe20000000000 */
/*0830*/ @P1 BRA 0x1b0 ; /* 0xfffff97000001947 */
/* 0x000fea000383ffff */
/*0840*/ ISETP.GT.AND P1, PT, R7, 0x4, PT ; /* 0x000000040700780c */
/* 0x000fda0003f24270 */
/*0850*/ @!P1 BRA 0xbe0 ; /* 0x0000038000009947 */
/* 0x000fea0003800000 */
/*0860*/ IMAD.WIDE R20, R2, 0x4, R22 ; /* 0x0000000402147825 */
/* 0x000fe200078e0216 */
/*0870*/ MOV R8, UR6 ; /* 0x0000000600087c02 */
/* 0x000fe20008000f00 */
/*0880*/ LDG.E R22, [R22.64] ; /* 0x0000000416167981 */
/* 0x0000a2000c1e1900 */
/*0890*/ MOV R9, UR7 ; /* 0x0000000700097c02 */
/* 0x000fc60008000f00 */
/*08a0*/ IMAD.WIDE R12, R2, 0x4, R20 ; /* 0x00000004020c7825 */
/* 0x000fe200078e0214 */
/*08b0*/ LDG.E R10, [R20.64] ; /* 0x00000004140a7981 */
/* 0x0002e6000c1e1900 */
/*08c0*/ IMAD.WIDE R8, R6, 0x4, R8 ; /* 0x0000000406087825 */
/* 0x000fe200078e0208 */
/*08d0*/ LDG.E R27, [R12.64] ; /* 0x000000040c1b7981 */
/* 0x000966000c1e1900 */
/*08e0*/ IMAD.WIDE R14, R2.reuse, 0x4, R12 ; /* 0x00000004020e7825 */
/* 0x040fe200078e020c */
/*08f0*/ LDG.E R25, [R8.64] ; /* 0x0000000408197981 */
/* 0x000ea8000c1e1900 */
/*0900*/ LDG.E R23, [R8.64+0x4] ; /* 0x0000040408177981 */
/* 0x001ee2000c1e1900 */
/*0910*/ IMAD.WIDE R16, R2, 0x4, R14 ; /* 0x0000000402107825 */
/* 0x000fc600078e020e */
/*0920*/ LDG.E R26, [R8.64+0x8] ; /* 0x00000804081a7981 */
/* 0x000f66000c1e1900 */
/*0930*/ IMAD.WIDE R18, R2.reuse, 0x4, R16 ; /* 0x0000000402127825 */
/* 0x040fe200078e0210 */
/*0940*/ LDG.E R24, [R14.64] ; /* 0x000000040e187981 */
/* 0x000168000c1e1900 */
/*0950*/ LDG.E R29, [R8.64+0xc] ; /* 0x00000c04081d7981 */
/* 0x000f62000c1e1900 */
/*0960*/ IMAD.WIDE R20, R2, 0x4, R18 ; /* 0x0000000402147825 */
/* 0x002fc600078e0212 */
/*0970*/ LDG.E R28, [R8.64+0x10] ; /* 0x00001004081c7981 */
/* 0x000f68000c1e1900 */
/*0980*/ LDG.E R15, [R16.64] ; /* 0x00000004100f7981 */
/* 0x001162000c1e1900 */
/*0990*/ IMAD.WIDE R12, R2, 0x4, R20 ; /* 0x00000004020c7825 */
/* 0x010fc600078e0214 */
/*09a0*/ LDG.E R14, [R8.64+0x14] ; /* 0x00001404080e7981 */
/* 0x000f28000c1e1900 */
/*09b0*/ LDG.E R17, [R18.64] ; /* 0x0000000412117981 */
/* 0x001128000c1e1900 */
/*09c0*/ LDG.E R16, [R20.64] ; /* 0x0000000414107981 */
/* 0x000328000c1e1900 */
/*09d0*/ LDG.E R19, [R8.64+0x18] ; /* 0x0000180408137981 */
/* 0x001128000c1e1900 */
/*09e0*/ LDG.E R18, [R8.64+0x1c] ; /* 0x00001c0408127981 */
/* 0x000128000c1e1900 */
/*09f0*/ LDG.E R21, [R12.64] ; /* 0x000000040c157981 */
/* 0x002f22000c1e1900 */
/*0a00*/ UIADD3 UR6, UP0, UR6, 0x20, URZ ; /* 0x0000002006067890 */
/* 0x000fe2000ff1e03f */
/*0a10*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc40003f0e170 */
/*0a20*/ IADD3 R4, R4, 0x8, RZ ; /* 0x0000000804047810 */
/* 0x000fe40007ffe0ff */
/*0a30*/ IADD3 R7, R7, -0x8, RZ ; /* 0xfffffff807077810 */
/* 0x000fe20007ffe0ff */
/*0a40*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0a50*/ IMAD R22, R22, R25, RZ ; /* 0x0000001916167224 */
/* 0x004fe400078e02ff */
/*0a60*/ IMAD R10, R10, R23, RZ ; /* 0x000000170a0a7224 */
/* 0x008fc800078e02ff */
/*0a70*/ I2F R22, R22 ; /* 0x0000001600167306 */
/* 0x000e620000201400 */
/*0a80*/ IMAD R23, R27, R26, RZ ; /* 0x0000001a1b177224 */
/* 0x020fce00078e02ff */
/*0a90*/ I2F R10, R10 ; /* 0x0000000a000a7306 */
/* 0x000ea20000201400 */
/*0aa0*/ IMAD R20, R24, R29, RZ ; /* 0x0000001d18147224 */
/* 0x000fce00078e02ff */
/*0ab0*/ I2F R23, R23 ; /* 0x0000001700177306 */
/* 0x000ee20000201400 */
/*0ac0*/ IMAD R15, R15, R28, RZ ; /* 0x0000001c0f0f7224 */
/* 0x000fe400078e02ff */
/*0ad0*/ FADD R11, R11, R22 ; /* 0x000000160b0b7221 */
/* 0x002fca0000000000 */
/*0ae0*/ I2F R20, R20 ; /* 0x0000001400147306 */
/* 0x000e620000201400 */
/*0af0*/ IMAD R14, R17, R14, RZ ; /* 0x0000000e110e7224 */
/* 0x010fce00078e02ff */
/*0b00*/ I2F R8, R15 ; /* 0x0000000f00087306 */
/* 0x001e220000201400 */
/*0b10*/ FADD R10, R11, R10 ; /* 0x0000000a0b0a7221 */
/* 0x004fe40000000000 */
/*0b20*/ IMAD R16, R16, R19, RZ ; /* 0x0000001310107224 */
/* 0x000fca00078e02ff */
/*0b30*/ I2F R9, R14 ; /* 0x0000000e00097306 */
/* 0x000ea20000201400 */
/*0b40*/ FADD R23, R10, R23 ; /* 0x000000170a177221 */
/* 0x008fe40000000000 */
/*0b50*/ IMAD R18, R21, R18, RZ ; /* 0x0000001215127224 */
/* 0x000fca00078e02ff */
/*0b60*/ I2F R11, R16 ; /* 0x00000010000b7306 */
/* 0x000ee20000201400 */
/*0b70*/ FADD R23, R23, R20 ; /* 0x0000001417177221 */
/* 0x002fce0000000000 */
/*0b80*/ I2F R18, R18 ; /* 0x0000001200127306 */
/* 0x000e620000201400 */
/*0b90*/ FADD R8, R23, R8 ; /* 0x0000000817087221 */
/* 0x001fc80000000000 */
/*0ba0*/ FADD R8, R8, R9 ; /* 0x0000000908087221 */
/* 0x004fc80000000000 */
/*0bb0*/ FADD R11, R8, R11 ; /* 0x0000000b080b7221 */
/* 0x008fe40000000000 */
/*0bc0*/ IMAD.WIDE R22, R2, 0x4, R12 ; /* 0x0000000402167825 */
/* 0x000fc800078e020c */
/*0bd0*/ FADD R11, R11, R18 ; /* 0x000000120b0b7221 */
/* 0x002fe40000000000 */
/*0be0*/ ISETP.NE.OR P0, PT, R7, RZ, P0 ; /* 0x000000ff0700720c */
/* 0x000fda0000705670 */
/*0bf0*/ @!P0 BRA 0xe10 ; /* 0x0000021000008947 */
/* 0x000fea0003800000 */
/*0c00*/ MOV R8, UR6 ; /* 0x0000000600087c02 */
/* 0x000fe20008000f00 */
/*0c10*/ IMAD.WIDE R16, R2, 0x4, R22 ; /* 0x0000000402107825 */
/* 0x000fe200078e0216 */
/*0c20*/ MOV R9, UR7 ; /* 0x0000000700097c02 */
/* 0x000fe20008000f00 */
/*0c30*/ LDG.E R22, [R22.64] ; /* 0x0000000416167981 */
/* 0x000ea8000c1e1900 */
/*0c40*/ IMAD.WIDE R8, R6, 0x4, R8 ; /* 0x0000000406087825 */
/* 0x000fc800078e0208 */
/*0c50*/ IMAD.WIDE R14, R2.reuse, 0x4, R16 ; /* 0x00000004020e7825 */
/* 0x040fe200078e0210 */
/*0c60*/ LDG.E R19, [R8.64] ; /* 0x0000000408137981 */
/* 0x000ea8000c1e1900 */
/*0c70*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x000ee8000c1e1900 */
/*0c80*/ LDG.E R21, [R8.64+0x4] ; /* 0x0000040408157981 */
/* 0x000ee2000c1e1900 */
/*0c90*/ IMAD.WIDE R12, R2, 0x4, R14 ; /* 0x00000004020c7825 */
/* 0x000fc600078e020e */
/*0ca0*/ LDG.E R18, [R14.64] ; /* 0x000000040e127981 */
/* 0x000f28000c1e1900 */
/*0cb0*/ LDG.E R25, [R8.64+0x8] ; /* 0x0000080408197981 */
/* 0x000f28000c1e1900 */
/*0cc0*/ LDG.E R27, [R8.64+0xc] ; /* 0x00000c04081b7981 */
/* 0x000f68000c1e1900 */
/*0cd0*/ LDG.E R20, [R12.64] ; /* 0x000000040c147981 */
/* 0x000f62000c1e1900 */
/*0ce0*/ IADD3 R7, R7, -0x4, RZ ; /* 0xfffffffc07077810 */
/* 0x000fc80007ffe0ff */
/*0cf0*/ ISETP.NE.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fe20003f05270 */
/*0d00*/ UIADD3 UR6, UP0, UR6, 0x10, URZ ; /* 0x0000001006067890 */
/* 0x000fe2000ff1e03f */
/*0d10*/ IADD3 R4, R4, 0x4, RZ ; /* 0x0000000404047810 */
/* 0x000fc60007ffe0ff */
/*0d20*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0d30*/ IMAD R19, R22, R19, RZ ; /* 0x0000001316137224 */
/* 0x004fc800078e02ff */
/*0d40*/ I2F R10, R19 ; /* 0x00000013000a7306 */
/* 0x000e220000201400 */
/*0d50*/ IMAD R21, R16, R21, RZ ; /* 0x0000001510157224 */
/* 0x008fce00078e02ff */
/*0d60*/ I2F R21, R21 ; /* 0x0000001500157306 */
/* 0x000e620000201400 */
/*0d70*/ IMAD R18, R18, R25, RZ ; /* 0x0000001912127224 */
/* 0x010fce00078e02ff */
/*0d80*/ I2F R17, R18 ; /* 0x0000001200117306 */
/* 0x000ea20000201400 */
/*0d90*/ IMAD R20, R20, R27, RZ ; /* 0x0000001b14147224 */
/* 0x020fe400078e02ff */
/*0da0*/ FADD R10, R10, R11 ; /* 0x0000000b0a0a7221 */
/* 0x001fca0000000000 */
/*0db0*/ I2F R15, R20 ; /* 0x00000014000f7306 */
/* 0x000e220000201400 */
/*0dc0*/ FADD R10, R10, R21 ; /* 0x000000150a0a7221 */
/* 0x002fe40000000000 */
/*0dd0*/ IMAD.WIDE R22, R2, 0x4, R12 ; /* 0x0000000402167825 */
/* 0x000fc800078e020c */
/*0de0*/ FADD R10, R10, R17 ; /* 0x000000110a0a7221 */
/* 0x004fc80000000000 */
/*0df0*/ FADD R11, R10, R15 ; /* 0x0000000f0a0b7221 */
/* 0x001fe20000000000 */
/*0e00*/ @P0 BRA 0xc00 ; /* 0xfffffdf000000947 */
/* 0x000fea000383ffff */
/*0e10*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fda0003f05270 */
/*0e20*/ @!P0 BRA 0xf50 ; /* 0x0000012000008947 */
/* 0x000fea0003800000 */
/*0e30*/ HFMA2.MMA R9, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff097435 */
/* 0x000fe200000001ff */
/*0e40*/ IMAD R6, R3, c[0x0][0x178], R4 ; /* 0x00005e0003067a24 */
/* 0x002fe400078e0204 */
/*0e50*/ IMAD R4, R4, c[0x0][0x178], R0 ; /* 0x00005e0004047a24 */
/* 0x001fce00078e0200 */
/*0e60*/ IMAD.WIDE R6, R6, R9, c[0x0][0x160] ; /* 0x0000580006067625 */
/* 0x000fc800078e0209 */
/*0e70*/ IMAD.WIDE R8, R4, R9, c[0x0][0x168] ; /* 0x00005a0004087625 */
/* 0x000fe200078e0209 */
/*0e80*/ MOV R13, R7 ; /* 0x00000007000d7202 */
/* 0x000fc80000000f00 */
/*0e90*/ MOV R7, R13 ; /* 0x0000000d00077202 */
/* 0x000fe20000000f00 */
/*0ea0*/ LDG.E R4, [R8.64] ; /* 0x0000000408047981 */
/* 0x0000aa000c1e1900 */
/*0eb0*/ LDG.E R7, [R6.64] ; /* 0x0000000406077981 */
/* 0x0002a2000c1e1900 */
/*0ec0*/ IADD3 R5, R5, -0x1, RZ ; /* 0xffffffff05057810 */
/* 0x000fc80007ffe0ff */
/*0ed0*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe20003f05270 */
/*0ee0*/ IMAD.WIDE R8, R2, 0x4, R8 ; /* 0x0000000402087825 */
/* 0x001fe200078e0208 */
/*0ef0*/ IADD3 R6, P1, R6, 0x4, RZ ; /* 0x0000000406067810 */
/* 0x002fc80007f3e0ff */
/*0f00*/ IADD3.X R13, RZ, R13, RZ, P1, !PT ; /* 0x0000000dff0d7210 */
/* 0x000fe20000ffe4ff */
/*0f10*/ IMAD R4, R4, R7, RZ ; /* 0x0000000704047224 */
/* 0x004fcc00078e02ff */
/*0f20*/ I2F R4, R4 ; /* 0x0000000400047306 */
/* 0x000e240000201400 */
/*0f30*/ FADD R11, R4, R11 ; /* 0x0000000b040b7221 */
/* 0x001fe20000000000 */
/*0f40*/ @P0 BRA 0xe90 ; /* 0xffffff4000000947 */
/* 0x000fea000383ffff */
/*0f50*/ F2I.TRUNC.NTZ R11, R11 ; /* 0x0000000b000b7305 */
/* 0x000ea2000020f100 */
/*0f60*/ MOV R2, 0x4 ; /* 0x0000000400027802 */
/* 0x000fe20000000f00 */
/*0f70*/ IMAD R3, R3, c[0x0][0x178], R0 ; /* 0x00005e0003037a24 */
/* 0x003fc800078e0200 */
/*0f80*/ IMAD.WIDE R2, R3, R2, c[0x0][0x170] ; /* 0x00005c0003027625 */
/* 0x000fca00078e0202 */
/*0f90*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x004fe2000c101904 */
/*0fa0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0fb0*/ BRA 0xfb0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0fc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0fd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0fe0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ff0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1000*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1010*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1020*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z12matmulKernelPiS_S_i
.globl _Z12matmulKernelPiS_S_i
.p2align 8
.type _Z12matmulKernelPiS_S_i,@function
_Z12matmulKernelPiS_S_i:
s_load_b32 s2, s[0:1], 0x18
v_and_b32_e32 v1, 0x3ff, v0
v_bfe_u32 v0, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s2, 1
s_cbranch_scc1 .LBB0_4
s_load_b128 s[4:7], s[0:1], 0x0
v_mul_lo_u32 v2, v0, s2
v_mov_b32_e32 v3, 0
s_mov_b32 s3, s2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[4:5], 2, v[2:3]
v_mov_b32_e32 v2, v1
v_mov_b32_e32 v6, v3
s_waitcnt lgkmcnt(0)
v_add_co_u32 v4, vcc_lo, s4, v4
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
.p2align 6
.LBB0_2:
v_lshlrev_b64 v[7:8], 2, v[2:3]
v_add_nc_u32_e32 v2, s2, v2
s_add_i32 s3, s3, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
s_cmp_eq_u32 s3, 0
v_add_co_u32 v7, vcc_lo, s6, v7
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v8, vcc_lo, s7, v8, vcc_lo
global_load_b32 v9, v[4:5], off
global_load_b32 v7, v[7:8], off
v_add_co_u32 v4, vcc_lo, v4, 4
v_add_co_ci_u32_e32 v5, vcc_lo, 0, v5, vcc_lo
s_waitcnt vmcnt(0)
v_mul_lo_u32 v7, v7, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_f32_i32_e32 v7, v7
v_add_f32_e32 v6, v6, v7
s_cbranch_scc0 .LBB0_2
s_delay_alu instid0(VALU_DEP_1)
v_cvt_i32_f32_e32 v2, v6
s_branch .LBB0_5
.LBB0_4:
v_mov_b32_e32 v2, 0
.LBB0_5:
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[3:4], null, v0, s2, v[1:2]
v_ashrrev_i32_e32 v4, 31, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[3:4]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12matmulKernelPiS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 28
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 10
.amdhsa_next_free_sgpr 8
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z12matmulKernelPiS_S_i, .Lfunc_end0-_Z12matmulKernelPiS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 28
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12matmulKernelPiS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 10
.sgpr_spill_count: 0
.symbol: _Z12matmulKernelPiS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 10
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0008c0d3_00000000-6_BrodayWalker1B.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z37__device_stub__Z12matmulKernelPiS_S_iPiS_S_i
.type _Z37__device_stub__Z12matmulKernelPiS_S_iPiS_S_i, @function
_Z37__device_stub__Z12matmulKernelPiS_S_iPiS_S_i:
.LFB2082:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z12matmulKernelPiS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z37__device_stub__Z12matmulKernelPiS_S_iPiS_S_i, .-_Z37__device_stub__Z12matmulKernelPiS_S_iPiS_S_i
.globl _Z12matmulKernelPiS_S_i
.type _Z12matmulKernelPiS_S_i, @function
_Z12matmulKernelPiS_S_i:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z37__device_stub__Z12matmulKernelPiS_S_iPiS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z12matmulKernelPiS_S_i, .-_Z12matmulKernelPiS_S_i
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "The summation of all the elements is %d.\n"
.align 8
.LC2:
.string "\nElapsed time in milliseconds: %f.\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $4096, %rsp
.cfi_def_cfa_offset 4112
orq $0, (%rsp)
subq $4096, %rsp
.cfi_def_cfa_offset 8208
orq $0, (%rsp)
subq $4096, %rsp
.cfi_def_cfa_offset 12304
orq $0, (%rsp)
subq $96, %rsp
.cfi_def_cfa_offset 12400
movq %fs:40, %rax
movq %rax, 12376(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rdi
call cudaEventCreate@PLT
leaq 48(%rsp), %rdi
call cudaEventCreate@PLT
movl $0x00000000, 12(%rsp)
leaq 80(%rsp), %rsi
leaq 8272(%rsp), %rbx
movq %rbx, %rcx
movl $0, %edx
.L12:
movl $0, %eax
.L13:
movl %edx, (%rsi,%rax)
movl $0, (%rcx,%rax)
addq $4, %rax
cmpq $128, %rax
jne .L13
addl $1, %edx
subq $-128, %rsi
subq $-128, %rcx
cmpl $32, %edx
jne .L12
leaq 4304(%rsp), %rcx
movl $31, %edx
.L14:
leaq -128(%rcx), %rax
.L15:
movl %edx, (%rax)
addq $4, %rax
cmpq %rcx, %rax
jne .L15
subl $1, %edx
subq $-128, %rcx
cmpl $-1, %edx
jne .L14
leaq 16(%rsp), %rdi
movl $4096, %esi
call cudaMalloc@PLT
leaq 80(%rsp), %rsi
movl $1, %ecx
movl $4096, %edx
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
leaq 24(%rsp), %rdi
movl $4096, %esi
call cudaMalloc@PLT
leaq 4176(%rsp), %rsi
movl $1, %ecx
movl $4096, %edx
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
leaq 32(%rsp), %rdi
movl $4096, %esi
call cudaMalloc@PLT
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $32, 68(%rsp)
movl $32, 72(%rsp)
movl $1, 76(%rsp)
movl $0, %esi
movq 40(%rsp), %rdi
call cudaEventRecord@PLT
movl 76(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 68(%rsp), %rdx
movq 56(%rsp), %rdi
movl 64(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L25
.L17:
movl $0, %esi
movq 48(%rsp), %rdi
call cudaEventRecord@PLT
leaq 8272(%rsp), %rdi
movl $2, %ecx
movl $4096, %edx
movq 32(%rsp), %rsi
call cudaMemcpy@PLT
movq 48(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 12(%rsp), %rdi
movq 48(%rsp), %rdx
movq 40(%rsp), %rsi
call cudaEventElapsedTime@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
leaq 4096(%rbx), %rcx
movl $0, %eax
.L18:
addl (%rbx), %eax
movl %eax, %edx
addq $4, %rbx
cmpq %rcx, %rbx
jne .L18
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
pxor %xmm0, %xmm0
cvtss2sd 12(%rsp), %xmm0
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 12376(%rsp), %rax
subq %fs:40, %rax
jne .L26
movl $0, %eax
addq $12384, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L25:
.cfi_restore_state
movl $32, %ecx
movq 32(%rsp), %rdx
movq 24(%rsp), %rsi
movq 16(%rsp), %rdi
call _Z37__device_stub__Z12matmulKernelPiS_S_iPiS_S_i
jmp .L17
.L26:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC3:
.string "_Z12matmulKernelPiS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z12matmulKernelPiS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "BrodayWalker1B.hip"
.globl _Z27__device_stub__matmulKernelPiS_S_i # -- Begin function _Z27__device_stub__matmulKernelPiS_S_i
.p2align 4, 0x90
.type _Z27__device_stub__matmulKernelPiS_S_i,@function
_Z27__device_stub__matmulKernelPiS_S_i: # @_Z27__device_stub__matmulKernelPiS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z12matmulKernelPiS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z27__device_stub__matmulKernelPiS_S_i, .Lfunc_end0-_Z27__device_stub__matmulKernelPiS_S_i
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $12448, %rsp # imm = 0x30A0
.cfi_def_cfa_offset 12464
.cfi_offset %rbx, -16
leaq 48(%rsp), %rdi
callq hipEventCreate
leaq 8(%rsp), %rdi
callq hipEventCreate
movl $0, 4(%rsp)
leaq 160(%rsp), %rdi
xorl %ebx, %ebx
movl $4096, %edx # imm = 0x1000
xorl %esi, %esi
callq memset@PLT
leaq 8352(%rsp), %rax
.p2align 4, 0x90
.LBB1_1: # %.preheader44
# =>This Loop Header: Depth=1
# Child Loop BB1_2 Depth 2
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB1_2: # Parent Loop BB1_1 Depth=1
# => This Inner Loop Header: Depth=2
movl %ebx, (%rax,%rcx,4)
incq %rcx
cmpq $32, %rcx
jne .LBB1_2
# %bb.3: # in Loop: Header=BB1_1 Depth=1
incq %rbx
subq $-128, %rax
cmpq $32, %rbx
jne .LBB1_1
# %bb.4: # %.preheader.preheader
movl $31, %eax
leaq 4256(%rsp), %rcx
xorl %edx, %edx
.p2align 4, 0x90
.LBB1_5: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_6 Depth 2
xorl %esi, %esi
.p2align 4, 0x90
.LBB1_6: # Parent Loop BB1_5 Depth=1
# => This Inner Loop Header: Depth=2
movl %eax, (%rcx,%rsi,4)
incq %rsi
cmpq $32, %rsi
jne .LBB1_6
# %bb.7: # in Loop: Header=BB1_5 Depth=1
decl %eax
incq %rdx
subq $-128, %rcx
cmpq $32, %rdx
jne .LBB1_5
# %bb.8:
leaq 32(%rsp), %rdi
movl $4096, %esi # imm = 0x1000
callq hipMalloc
movq 32(%rsp), %rdi
leaq 8352(%rsp), %rsi
movl $4096, %edx # imm = 0x1000
movl $1, %ecx
callq hipMemcpy
leaq 24(%rsp), %rdi
movl $4096, %esi # imm = 0x1000
callq hipMalloc
movq 24(%rsp), %rdi
leaq 4256(%rsp), %rsi
movl $4096, %edx # imm = 0x1000
movl $1, %ecx
callq hipMemcpy
leaq 16(%rsp), %rdi
movl $4096, %esi # imm = 0x1000
callq hipMalloc
movq 48(%rsp), %rdi
xorl %ebx, %ebx
xorl %esi, %esi
callq hipEventRecord
movabsq $4294967297, %rdi # imm = 0x100000001
movabsq $137438953504, %rdx # imm = 0x2000000020
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_10
# %bb.9:
movq 32(%rsp), %rax
movq 24(%rsp), %rcx
movq 16(%rsp), %rdx
movq %rax, 120(%rsp)
movq %rcx, 112(%rsp)
movq %rdx, 104(%rsp)
movl $32, 44(%rsp)
leaq 120(%rsp), %rax
movq %rax, 128(%rsp)
leaq 112(%rsp), %rax
movq %rax, 136(%rsp)
leaq 104(%rsp), %rax
movq %rax, 144(%rsp)
leaq 44(%rsp), %rax
movq %rax, 152(%rsp)
leaq 88(%rsp), %rdi
leaq 72(%rsp), %rsi
leaq 64(%rsp), %rdx
leaq 56(%rsp), %rcx
callq __hipPopCallConfiguration
movq 88(%rsp), %rsi
movl 96(%rsp), %edx
movq 72(%rsp), %rcx
movl 80(%rsp), %r8d
leaq 128(%rsp), %r9
movl $_Z12matmulKernelPiS_S_i, %edi
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_10:
movq 8(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 16(%rsp), %rsi
leaq 160(%rsp), %rdi
movl $4096, %edx # imm = 0x1000
movl $2, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
callq hipEventSynchronize
movq 48(%rsp), %rsi
movq 8(%rsp), %rdx
leaq 4(%rsp), %rdi
callq hipEventElapsedTime
movq 32(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_11: # =>This Inner Loop Header: Depth=1
addl 160(%rsp,%rax,4), %ebx
incq %rax
cmpq $1024, %rax # imm = 0x400
jne .LBB1_11
# %bb.12:
movl $.L.str, %edi
movl %ebx, %esi
xorl %eax, %eax
callq printf
movss 4(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.1, %edi
movb $1, %al
callq printf
xorl %eax, %eax
addq $12448, %rsp # imm = 0x30A0
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12matmulKernelPiS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z12matmulKernelPiS_S_i,@object # @_Z12matmulKernelPiS_S_i
.section .rodata,"a",@progbits
.globl _Z12matmulKernelPiS_S_i
.p2align 3, 0x0
_Z12matmulKernelPiS_S_i:
.quad _Z27__device_stub__matmulKernelPiS_S_i
.size _Z12matmulKernelPiS_S_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "The summation of all the elements is %d.\n"
.size .L.str, 42
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "\nElapsed time in milliseconds: %f.\n"
.size .L.str.1, 36
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z12matmulKernelPiS_S_i"
.size .L__unnamed_1, 24
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__matmulKernelPiS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12matmulKernelPiS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdbool.h>
#include <stdio.h>
#include <string.h>
#include <getopt.h>
#include <curand_kernel.h>
#include <stdlib.h>
#include <cuda.h>
#include <sys/time.h>
#include "LSTMDeltaKernelBPTT.cu"
#include<chrono>
#include<iostream>
using namespace std;
using namespace std::chrono;
int blocks_[20][2] = {{8,8},{16,16},{24,24},{32,32},{1,64},{1,128},{1,192},{1,256},{1,320},{1,384},{1,448},{1,512},{1,576},{1,640},{1,704},{1,768},{1,832},{1,896},{1,960},{1,1024}};
int matrices_[7][2] = {{240,240},{496,496},{784,784},{1016,1016},{1232,1232},{1680,1680},{2024,2024}};
int main(int argc, char **argv) {
cudaSetDevice(0);
char* p;int matrix_len=strtol(argv[1], &p, 10);
for(int matrix_looper=0;matrix_looper<matrix_len;matrix_looper++){
for(int block_looper=0;block_looper<20;block_looper++){
int XSIZE=matrices_[matrix_looper][0],YSIZE=matrices_[matrix_looper][1],BLOCKX=blocks_[block_looper][0],BLOCKY=blocks_[block_looper][1];
float *deltas = NULL;
cudaMalloc(&deltas, XSIZE*YSIZE);
float *cellStates = NULL;
cudaMalloc(&cellStates, XSIZE*YSIZE);
float *previousCellStates = NULL;
cudaMalloc(&previousCellStates, XSIZE*YSIZE);
float *cellStateErrors = NULL;
cudaMalloc(&cellStateErrors, XSIZE*YSIZE);
float *nextCellStateErrors = NULL;
cudaMalloc(&nextCellStateErrors, XSIZE*YSIZE);
float *outputGateDeltas = NULL;
cudaMalloc(&outputGateDeltas, XSIZE*YSIZE);
float *forgetGateDeltas = NULL;
cudaMalloc(&forgetGateDeltas, XSIZE*YSIZE);
float *nextForgetGateDeltas = NULL;
cudaMalloc(&nextForgetGateDeltas, XSIZE*YSIZE);
float *inputGateDeltas = NULL;
cudaMalloc(&inputGateDeltas, XSIZE*YSIZE);
float *nextInputGateDeltas = NULL;
cudaMalloc(&nextInputGateDeltas, XSIZE*YSIZE);
float *cellInputDeltas = NULL;
cudaMalloc(&cellInputDeltas, XSIZE*YSIZE);
float *cellInputActivations = NULL;
cudaMalloc(&cellInputActivations, XSIZE*YSIZE);
float *cellStateActivations = NULL;
cudaMalloc(&cellStateActivations, XSIZE*YSIZE);
float *outputGateActivations = NULL;
cudaMalloc(&outputGateActivations, XSIZE*YSIZE);
float *nextForgetGateActivations = NULL;
cudaMalloc(&nextForgetGateActivations, XSIZE*YSIZE);
float *inputGateActivations = NULL;
cudaMalloc(&inputGateActivations, XSIZE*YSIZE);
float *cellInputActivationDerivatives = NULL;
cudaMalloc(&cellInputActivationDerivatives, XSIZE*YSIZE);
float *cellStateActivationDerivatives = NULL;
cudaMalloc(&cellStateActivationDerivatives, XSIZE*YSIZE);
float *outputGateActivationDerivatives = NULL;
cudaMalloc(&outputGateActivationDerivatives, XSIZE*YSIZE);
float *forgetGateActivationDerivatives = NULL;
cudaMalloc(&forgetGateActivationDerivatives, XSIZE*YSIZE);
float *inputGateActivationDerivatives = NULL;
cudaMalloc(&inputGateActivationDerivatives, XSIZE*YSIZE);
float *cellInputWeights = NULL;
cudaMalloc(&cellInputWeights, XSIZE*YSIZE);
float *outputGateWeights = NULL;
cudaMalloc(&outputGateWeights, XSIZE*YSIZE);
float *forgetGateWeights = NULL;
cudaMalloc(&forgetGateWeights, XSIZE*YSIZE);
float *inputGateWeights = NULL;
cudaMalloc(&inputGateWeights, XSIZE*YSIZE);
int inputCount = 1;
int cellCount = 1;
int cellsPerBlock = 1;
int iXSIZE= XSIZE;
int iYSIZE= YSIZE;
while(iXSIZE%BLOCKX!=0)
{
iXSIZE++;
}
while(iYSIZE%BLOCKY!=0)
{
iYSIZE++;
}
dim3 gridBlock(iXSIZE/BLOCKX, iYSIZE/BLOCKY);
dim3 threadBlock(BLOCKX, BLOCKY);
cudaFree(0);
LSTMDeltaKernelBPTT<<<gridBlock,threadBlock>>>(deltas,cellStates,previousCellStates,cellStateErrors,nextCellStateErrors,outputGateDeltas,forgetGateDeltas,nextForgetGateDeltas,inputGateDeltas,nextInputGateDeltas,cellInputDeltas,cellInputActivations,cellStateActivations,outputGateActivations,nextForgetGateActivations,inputGateActivations,cellInputActivationDerivatives,cellStateActivationDerivatives,outputGateActivationDerivatives,forgetGateActivationDerivatives,inputGateActivationDerivatives,cellInputWeights,outputGateWeights,forgetGateWeights,inputGateWeights,inputCount,cellCount,cellsPerBlock);
cudaDeviceSynchronize();
for (int loop_counter = 0; loop_counter < 10; ++loop_counter) {
LSTMDeltaKernelBPTT<<<gridBlock,threadBlock>>>(deltas,cellStates,previousCellStates,cellStateErrors,nextCellStateErrors,outputGateDeltas,forgetGateDeltas,nextForgetGateDeltas,inputGateDeltas,nextInputGateDeltas,cellInputDeltas,cellInputActivations,cellStateActivations,outputGateActivations,nextForgetGateActivations,inputGateActivations,cellInputActivationDerivatives,cellStateActivationDerivatives,outputGateActivationDerivatives,forgetGateActivationDerivatives,inputGateActivationDerivatives,cellInputWeights,outputGateWeights,forgetGateWeights,inputGateWeights,inputCount,cellCount,cellsPerBlock);
}
auto start = steady_clock::now();
for (int loop_counter = 0; loop_counter < 1000; loop_counter++) {
LSTMDeltaKernelBPTT<<<gridBlock,threadBlock>>>(deltas,cellStates,previousCellStates,cellStateErrors,nextCellStateErrors,outputGateDeltas,forgetGateDeltas,nextForgetGateDeltas,inputGateDeltas,nextInputGateDeltas,cellInputDeltas,cellInputActivations,cellStateActivations,outputGateActivations,nextForgetGateActivations,inputGateActivations,cellInputActivationDerivatives,cellStateActivationDerivatives,outputGateActivationDerivatives,forgetGateActivationDerivatives,inputGateActivationDerivatives,cellInputWeights,outputGateWeights,forgetGateWeights,inputGateWeights,inputCount,cellCount,cellsPerBlock);
}
auto end = steady_clock::now();
auto usecs = duration_cast<duration<float, microseconds::period> >(end - start);
cout <<'['<<usecs.count()<<','<<'('<<BLOCKX<<','<<BLOCKY<<')' << ','<<'('<<XSIZE<<','<<YSIZE<<')'<<']' << endl;
}
}} | .file "tmpxft_000c4567_00000000-6_main.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3988:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3988:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z90__device_stub__Z19LSTMDeltaKernelBPTTPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_iiiPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_iii
.type _Z90__device_stub__Z19LSTMDeltaKernelBPTTPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_iiiPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_iii, @function
_Z90__device_stub__Z19LSTMDeltaKernelBPTTPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_iiiPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_iii:
.LFB4010:
.cfi_startproc
endbr64
subq $520, %rsp
.cfi_def_cfa_offset 528
movq %rdi, 200(%rsp)
movq %rsi, 192(%rsp)
movq %rdx, 184(%rsp)
movq %rcx, 176(%rsp)
movq %r8, 168(%rsp)
movq %r9, 160(%rsp)
movq 528(%rsp), %rax
movq %rax, 152(%rsp)
movq 536(%rsp), %rax
movq %rax, 144(%rsp)
movq 544(%rsp), %rax
movq %rax, 136(%rsp)
movq 552(%rsp), %rax
movq %rax, 128(%rsp)
movq 560(%rsp), %rax
movq %rax, 120(%rsp)
movq 568(%rsp), %rax
movq %rax, 112(%rsp)
movq 576(%rsp), %rax
movq %rax, 104(%rsp)
movq 584(%rsp), %rax
movq %rax, 96(%rsp)
movq 592(%rsp), %rax
movq %rax, 88(%rsp)
movq 600(%rsp), %rax
movq %rax, 80(%rsp)
movq 608(%rsp), %rax
movq %rax, 72(%rsp)
movq 616(%rsp), %rax
movq %rax, 64(%rsp)
movq 624(%rsp), %rax
movq %rax, 56(%rsp)
movq 632(%rsp), %rax
movq %rax, 48(%rsp)
movq 640(%rsp), %rax
movq %rax, 40(%rsp)
movq 648(%rsp), %rax
movq %rax, 32(%rsp)
movq 656(%rsp), %rax
movq %rax, 24(%rsp)
movq 664(%rsp), %rax
movq %rax, 16(%rsp)
movq 672(%rsp), %rax
movq %rax, 8(%rsp)
movq %fs:40, %rax
movq %rax, 504(%rsp)
xorl %eax, %eax
leaq 200(%rsp), %rax
movq %rax, 272(%rsp)
leaq 192(%rsp), %rax
movq %rax, 280(%rsp)
leaq 184(%rsp), %rax
movq %rax, 288(%rsp)
leaq 176(%rsp), %rax
movq %rax, 296(%rsp)
leaq 168(%rsp), %rax
movq %rax, 304(%rsp)
leaq 160(%rsp), %rax
movq %rax, 312(%rsp)
leaq 152(%rsp), %rax
movq %rax, 320(%rsp)
leaq 144(%rsp), %rax
movq %rax, 328(%rsp)
leaq 136(%rsp), %rax
movq %rax, 336(%rsp)
leaq 128(%rsp), %rax
movq %rax, 344(%rsp)
leaq 120(%rsp), %rax
movq %rax, 352(%rsp)
leaq 112(%rsp), %rax
movq %rax, 360(%rsp)
leaq 104(%rsp), %rax
movq %rax, 368(%rsp)
leaq 96(%rsp), %rax
movq %rax, 376(%rsp)
leaq 88(%rsp), %rax
movq %rax, 384(%rsp)
leaq 80(%rsp), %rax
movq %rax, 392(%rsp)
leaq 72(%rsp), %rax
movq %rax, 400(%rsp)
leaq 64(%rsp), %rax
movq %rax, 408(%rsp)
leaq 56(%rsp), %rax
movq %rax, 416(%rsp)
leaq 48(%rsp), %rax
movq %rax, 424(%rsp)
leaq 40(%rsp), %rax
movq %rax, 432(%rsp)
leaq 32(%rsp), %rax
movq %rax, 440(%rsp)
leaq 24(%rsp), %rax
movq %rax, 448(%rsp)
leaq 16(%rsp), %rax
movq %rax, 456(%rsp)
leaq 8(%rsp), %rax
movq %rax, 464(%rsp)
leaq 680(%rsp), %rax
movq %rax, 472(%rsp)
leaq 688(%rsp), %rax
movq %rax, 480(%rsp)
leaq 696(%rsp), %rax
movq %rax, 488(%rsp)
movl $1, 224(%rsp)
movl $1, 228(%rsp)
movl $1, 232(%rsp)
movl $1, 236(%rsp)
movl $1, 240(%rsp)
movl $1, 244(%rsp)
leaq 216(%rsp), %rcx
leaq 208(%rsp), %rdx
leaq 236(%rsp), %rsi
leaq 224(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 504(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $520, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 216(%rsp)
.cfi_def_cfa_offset 536
pushq 216(%rsp)
.cfi_def_cfa_offset 544
leaq 288(%rsp), %r9
movq 252(%rsp), %rcx
movl 260(%rsp), %r8d
movq 240(%rsp), %rsi
movl 248(%rsp), %edx
leaq _Z19LSTMDeltaKernelBPTTPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_iii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 528
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4010:
.size _Z90__device_stub__Z19LSTMDeltaKernelBPTTPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_iiiPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_iii, .-_Z90__device_stub__Z19LSTMDeltaKernelBPTTPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_iiiPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_iii
.globl _Z19LSTMDeltaKernelBPTTPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_iii
.type _Z19LSTMDeltaKernelBPTTPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_iii, @function
_Z19LSTMDeltaKernelBPTTPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_iii:
.LFB4011:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl 184(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 24
movl 184(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
movl 184(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 40
pushq 184(%rsp)
.cfi_def_cfa_offset 48
pushq 184(%rsp)
.cfi_def_cfa_offset 56
pushq 184(%rsp)
.cfi_def_cfa_offset 64
pushq 184(%rsp)
.cfi_def_cfa_offset 72
pushq 184(%rsp)
.cfi_def_cfa_offset 80
pushq 184(%rsp)
.cfi_def_cfa_offset 88
pushq 184(%rsp)
.cfi_def_cfa_offset 96
pushq 184(%rsp)
.cfi_def_cfa_offset 104
pushq 184(%rsp)
.cfi_def_cfa_offset 112
pushq 184(%rsp)
.cfi_def_cfa_offset 120
pushq 184(%rsp)
.cfi_def_cfa_offset 128
pushq 184(%rsp)
.cfi_def_cfa_offset 136
pushq 184(%rsp)
.cfi_def_cfa_offset 144
pushq 184(%rsp)
.cfi_def_cfa_offset 152
pushq 184(%rsp)
.cfi_def_cfa_offset 160
pushq 184(%rsp)
.cfi_def_cfa_offset 168
pushq 184(%rsp)
.cfi_def_cfa_offset 176
pushq 184(%rsp)
.cfi_def_cfa_offset 184
pushq 184(%rsp)
.cfi_def_cfa_offset 192
call _Z90__device_stub__Z19LSTMDeltaKernelBPTTPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_iiiPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_iii
addq $184, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4011:
.size _Z19LSTMDeltaKernelBPTTPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_iii, .-_Z19LSTMDeltaKernelBPTTPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_iii
.globl main
.type main, @function
main:
.LFB3982:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $312, %rsp
.cfi_def_cfa_offset 368
movq %rsi, %rbx
movq %fs:40, %rax
movq %rax, 296(%rsp)
xorl %eax, %eax
movl $0, %edi
call cudaSetDevice@PLT
leaq 64(%rsp), %rsi
movq 8(%rbx), %rdi
movl $10, %edx
call __isoc23_strtol@PLT
testl %eax, %eax
jle .L12
leaq matrices_(%rip), %r8
leal -1(%rax), %edx
leaq 8(%r8), %rax
leaq (%rax,%rdx,8), %rbp
leaq _ZSt4cout(%rip), %r13
jmp .L13
.L49:
movl %r14d, %esi
jmp .L14
.L50:
movl 4(%rsp), %ecx
jmp .L16
.L61:
pushq $1
.cfi_def_cfa_offset 376
pushq $1
.cfi_def_cfa_offset 384
pushq $1
.cfi_def_cfa_offset 392
pushq 288(%rsp)
.cfi_def_cfa_offset 400
pushq 288(%rsp)
.cfi_def_cfa_offset 408
pushq 288(%rsp)
.cfi_def_cfa_offset 416
pushq 288(%rsp)
.cfi_def_cfa_offset 424
pushq 288(%rsp)
.cfi_def_cfa_offset 432
pushq 288(%rsp)
.cfi_def_cfa_offset 440
pushq 288(%rsp)
.cfi_def_cfa_offset 448
pushq 288(%rsp)
.cfi_def_cfa_offset 456
pushq 288(%rsp)
.cfi_def_cfa_offset 464
pushq 288(%rsp)
.cfi_def_cfa_offset 472
pushq 288(%rsp)
.cfi_def_cfa_offset 480
pushq 288(%rsp)
.cfi_def_cfa_offset 488
pushq 288(%rsp)
.cfi_def_cfa_offset 496
pushq 288(%rsp)
.cfi_def_cfa_offset 504
pushq 288(%rsp)
.cfi_def_cfa_offset 512
pushq 288(%rsp)
.cfi_def_cfa_offset 520
pushq 288(%rsp)
.cfi_def_cfa_offset 528
pushq 288(%rsp)
.cfi_def_cfa_offset 536
pushq 288(%rsp)
.cfi_def_cfa_offset 544
movq 288(%rsp), %r9
movq 280(%rsp), %r8
movq 272(%rsp), %rcx
movq 264(%rsp), %rdx
movq 256(%rsp), %rsi
movq 248(%rsp), %rdi
call _Z90__device_stub__Z19LSTMDeltaKernelBPTTPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_iiiPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_iii
addq $176, %rsp
.cfi_def_cfa_offset 368
jmp .L18
.L19:
subl $1, %ebx
je .L57
.L20:
movl 292(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 284(%rsp), %rdx
movq 272(%rsp), %rdi
movl 280(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L19
pushq $1
.cfi_def_cfa_offset 376
pushq $1
.cfi_def_cfa_offset 384
pushq $1
.cfi_def_cfa_offset 392
pushq 288(%rsp)
.cfi_def_cfa_offset 400
pushq 288(%rsp)
.cfi_def_cfa_offset 408
pushq 288(%rsp)
.cfi_def_cfa_offset 416
pushq 288(%rsp)
.cfi_def_cfa_offset 424
pushq 288(%rsp)
.cfi_def_cfa_offset 432
pushq 288(%rsp)
.cfi_def_cfa_offset 440
pushq 288(%rsp)
.cfi_def_cfa_offset 448
pushq 288(%rsp)
.cfi_def_cfa_offset 456
pushq 288(%rsp)
.cfi_def_cfa_offset 464
pushq 288(%rsp)
.cfi_def_cfa_offset 472
pushq 288(%rsp)
.cfi_def_cfa_offset 480
pushq 288(%rsp)
.cfi_def_cfa_offset 488
pushq 288(%rsp)
.cfi_def_cfa_offset 496
pushq 288(%rsp)
.cfi_def_cfa_offset 504
pushq 288(%rsp)
.cfi_def_cfa_offset 512
pushq 288(%rsp)
.cfi_def_cfa_offset 520
pushq 288(%rsp)
.cfi_def_cfa_offset 528
pushq 288(%rsp)
.cfi_def_cfa_offset 536
pushq 288(%rsp)
.cfi_def_cfa_offset 544
movq 288(%rsp), %r9
movq 280(%rsp), %r8
movq 272(%rsp), %rcx
movq 264(%rsp), %rdx
movq 256(%rsp), %rsi
movq 248(%rsp), %rdi
call _Z90__device_stub__Z19LSTMDeltaKernelBPTTPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_iiiPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_iii
addq $176, %rsp
.cfi_def_cfa_offset 368
jmp .L19
.L57:
call _ZNSt6chrono3_V212steady_clock3nowEv@PLT
movq %rax, 8(%rsp)
movl $1000, %ebx
jmp .L22
.L21:
subl $1, %ebx
je .L58
.L22:
movl 292(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 284(%rsp), %rdx
movq 272(%rsp), %rdi
movl 280(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L21
pushq $1
.cfi_def_cfa_offset 376
pushq $1
.cfi_def_cfa_offset 384
pushq $1
.cfi_def_cfa_offset 392
pushq 288(%rsp)
.cfi_def_cfa_offset 400
pushq 288(%rsp)
.cfi_def_cfa_offset 408
pushq 288(%rsp)
.cfi_def_cfa_offset 416
pushq 288(%rsp)
.cfi_def_cfa_offset 424
pushq 288(%rsp)
.cfi_def_cfa_offset 432
pushq 288(%rsp)
.cfi_def_cfa_offset 440
pushq 288(%rsp)
.cfi_def_cfa_offset 448
pushq 288(%rsp)
.cfi_def_cfa_offset 456
pushq 288(%rsp)
.cfi_def_cfa_offset 464
pushq 288(%rsp)
.cfi_def_cfa_offset 472
pushq 288(%rsp)
.cfi_def_cfa_offset 480
pushq 288(%rsp)
.cfi_def_cfa_offset 488
pushq 288(%rsp)
.cfi_def_cfa_offset 496
pushq 288(%rsp)
.cfi_def_cfa_offset 504
pushq 288(%rsp)
.cfi_def_cfa_offset 512
pushq 288(%rsp)
.cfi_def_cfa_offset 520
pushq 288(%rsp)
.cfi_def_cfa_offset 528
pushq 288(%rsp)
.cfi_def_cfa_offset 536
pushq 288(%rsp)
.cfi_def_cfa_offset 544
movq 288(%rsp), %r9
movq 280(%rsp), %r8
movq 272(%rsp), %rcx
movq 264(%rsp), %rdx
movq 256(%rsp), %rsi
movq 248(%rsp), %rdi
call _Z90__device_stub__Z19LSTMDeltaKernelBPTTPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_iiiPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_iii
addq $176, %rsp
.cfi_def_cfa_offset 368
jmp .L21
.L58:
call _ZNSt6chrono3_V212steady_clock3nowEv@PLT
movq 8(%rsp), %rdx
subq %rdx, %rax
pxor %xmm0, %xmm0
cvtsi2ssq %rax, %xmm0
divss .LC0(%rip), %xmm0
movss %xmm0, 8(%rsp)
movb $91, 63(%rsp)
movq 0(%r13), %rax
movq -24(%rax), %rax
cmpq $0, 16(%r13,%rax)
je .L23
leaq 63(%rsp), %rsi
movl $1, %edx
movq %r13, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq %rax, %rdi
.L24:
pxor %xmm0, %xmm0
cvtss2sd 8(%rsp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rbx
movb $44, 63(%rsp)
movq (%rax), %rax
movq -24(%rax), %rax
cmpq $0, 16(%rbx,%rax)
je .L25
leaq 63(%rsp), %rsi
movl $1, %edx
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq %rax, %rbx
.L26:
movb $40, 63(%rsp)
movq (%rbx), %rax
movq -24(%rax), %rax
cmpq $0, 16(%rbx,%rax)
je .L27
leaq 63(%rsp), %rsi
movl $1, %edx
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq %rax, %rbx
.L28:
movl %r12d, %esi
movq %rbx, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbx
movb $44, 63(%rsp)
movq (%rax), %rax
movq -24(%rax), %rax
cmpq $0, 16(%rbx,%rax)
je .L29
leaq 63(%rsp), %rsi
movl $1, %edx
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq %rax, %rbx
.L30:
movl %ebp, %esi
movq %rbx, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbx
movb $41, 63(%rsp)
movq (%rax), %rax
movq -24(%rax), %rax
cmpq $0, 16(%rbx,%rax)
je .L31
leaq 63(%rsp), %rsi
movl $1, %edx
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq %rax, %rbx
.L32:
movb $44, 63(%rsp)
movq (%rbx), %rax
movq -24(%rax), %rax
cmpq $0, 16(%rbx,%rax)
je .L33
leaq 63(%rsp), %rsi
movl $1, %edx
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq %rax, %rbx
.L34:
movb $40, 63(%rsp)
movq (%rbx), %rax
movq -24(%rax), %rax
cmpq $0, 16(%rbx,%rax)
je .L35
leaq 63(%rsp), %rsi
movl $1, %edx
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq %rax, %rbx
.L36:
movl %r14d, %esi
movq %rbx, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbx
movb $44, 63(%rsp)
movq (%rax), %rax
movq -24(%rax), %rax
cmpq $0, 16(%rbx,%rax)
je .L37
leaq 63(%rsp), %rsi
movl $1, %edx
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq %rax, %rbx
.L38:
movl 4(%rsp), %esi
movq %rbx, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbx
movb $41, 63(%rsp)
movq (%rax), %rax
movq -24(%rax), %rax
cmpq $0, 16(%rbx,%rax)
je .L39
leaq 63(%rsp), %rsi
movl $1, %edx
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq %rax, %rbx
.L40:
movb $93, 63(%rsp)
movq (%rbx), %rax
movq -24(%rax), %rax
cmpq $0, 16(%rbx,%rax)
je .L41
leaq 63(%rsp), %rsi
movl $1, %edx
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq %rax, %rbx
.L42:
movq (%rbx), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %rbp
testq %rbp, %rbp
je .L59
cmpb $0, 56(%rbp)
je .L45
movzbl 67(%rbp), %eax
.L46:
movsbl %al, %esi
movq %rbx, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
addq $8, %r15
leaq 160+blocks_(%rip), %rax
cmpq %rax, %r15
je .L60
.L47:
movq 16(%rsp), %rax
movl (%rax), %r14d
movl 4(%rax), %eax
movl %eax, 4(%rsp)
movl (%r15), %r12d
movl 4(%r15), %ebp
movq $0, 72(%rsp)
movl %eax, %ebx
imull %r14d, %ebx
movslq %ebx, %rbx
movq %rbx, %rsi
movq 24(%rsp), %rdi
call cudaMalloc@PLT
movq $0, 80(%rsp)
movq %rbx, %rsi
movq 32(%rsp), %rdi
call cudaMalloc@PLT
movq $0, 88(%rsp)
leaq 88(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movq $0, 96(%rsp)
leaq 96(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movq $0, 104(%rsp)
leaq 104(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movq $0, 112(%rsp)
leaq 112(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movq $0, 120(%rsp)
leaq 120(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movq $0, 128(%rsp)
leaq 128(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movq $0, 136(%rsp)
leaq 136(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movq $0, 144(%rsp)
leaq 144(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movq $0, 152(%rsp)
leaq 152(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movq $0, 160(%rsp)
leaq 160(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movq $0, 168(%rsp)
leaq 168(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movq $0, 176(%rsp)
leaq 176(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movq $0, 184(%rsp)
leaq 184(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movq $0, 192(%rsp)
leaq 192(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movq $0, 200(%rsp)
leaq 200(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movq $0, 208(%rsp)
leaq 208(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movq $0, 216(%rsp)
leaq 216(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movq $0, 224(%rsp)
leaq 224(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movq $0, 232(%rsp)
leaq 232(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movq $0, 240(%rsp)
leaq 240(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movq $0, 248(%rsp)
leaq 248(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movq $0, 256(%rsp)
leaq 256(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movq $0, 264(%rsp)
leaq 264(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl %r14d, %eax
cltd
idivl %r12d
testl %edx, %edx
je .L49
movl %r14d, %esi
.L15:
addl $1, %esi
movl %esi, %eax
cltd
idivl %r12d
testl %edx, %edx
jne .L15
.L14:
movl 4(%rsp), %eax
cltd
idivl %ebp
testl %edx, %edx
je .L50
movl 4(%rsp), %ecx
.L17:
addl $1, %ecx
movl %ecx, %eax
cltd
idivl %ebp
testl %edx, %edx
jne .L17
.L16:
movl %esi, %eax
cltd
idivl %r12d
movl %eax, 272(%rsp)
movl %ecx, %eax
cltd
idivl %ebp
movl %eax, 276(%rsp)
movl $1, 280(%rsp)
movl %r12d, 284(%rsp)
movl %ebp, 288(%rsp)
movl $1, 292(%rsp)
movl $0, %edi
call cudaFree@PLT
movl 292(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 284(%rsp), %rdx
movq 272(%rsp), %rdi
movl 280(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L61
.L18:
call cudaDeviceSynchronize@PLT
movl $10, %ebx
jmp .L20
.L23:
movl $91, %esi
movq %r13, %rdi
call _ZNSo3putEc@PLT
movq %r13, %rdi
jmp .L24
.L25:
movl $44, %esi
movq %rbx, %rdi
call _ZNSo3putEc@PLT
jmp .L26
.L27:
movl $40, %esi
movq %rbx, %rdi
call _ZNSo3putEc@PLT
jmp .L28
.L29:
movl $44, %esi
movq %rbx, %rdi
call _ZNSo3putEc@PLT
jmp .L30
.L31:
movl $41, %esi
movq %rbx, %rdi
call _ZNSo3putEc@PLT
jmp .L32
.L33:
movl $44, %esi
movq %rbx, %rdi
call _ZNSo3putEc@PLT
jmp .L34
.L35:
movl $40, %esi
movq %rbx, %rdi
call _ZNSo3putEc@PLT
jmp .L36
.L37:
movl $44, %esi
movq %rbx, %rdi
call _ZNSo3putEc@PLT
jmp .L38
.L39:
movl $41, %esi
movq %rbx, %rdi
call _ZNSo3putEc@PLT
jmp .L40
.L41:
movl $93, %esi
movq %rbx, %rdi
call _ZNSo3putEc@PLT
jmp .L42
.L59:
movq 296(%rsp), %rax
subq %fs:40, %rax
jne .L62
call _ZSt16__throw_bad_castv@PLT
.L62:
call __stack_chk_fail@PLT
.L45:
movq %rbp, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq 0(%rbp), %rax
movl $10, %esi
movq %rbp, %rdi
call *48(%rax)
jmp .L46
.L60:
movq 40(%rsp), %rbp
movq 16(%rsp), %r8
addq $8, %r8
cmpq %r8, %rbp
je .L12
.L13:
leaq blocks_(%rip), %r15
leaq 72(%rsp), %rax
movq %rax, 24(%rsp)
leaq 80(%rsp), %rax
movq %rax, 32(%rsp)
movq %rbp, 40(%rsp)
movq %r8, 16(%rsp)
jmp .L47
.L12:
movq 296(%rsp), %rax
subq %fs:40, %rax
jne .L63
movl $0, %eax
addq $312, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L63:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3982:
.size main, .-main
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "_Z19LSTMDeltaKernelBPTTPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_iii"
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "precalc_xorwow_matrix"
.LC3:
.string "precalc_xorwow_offset_matrix"
.LC4:
.string "mrg32k3aM1"
.LC5:
.string "mrg32k3aM2"
.LC6:
.string "mrg32k3aM1SubSeq"
.LC7:
.string "mrg32k3aM2SubSeq"
.LC8:
.string "mrg32k3aM1Seq"
.LC9:
.string "mrg32k3aM2Seq"
.LC10:
.string "__cr_lgamma_table"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB4013:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z19LSTMDeltaKernelBPTTPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_iii(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $102400, %r9d
movl $0, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _ZL21precalc_xorwow_matrix(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $102400, %r9d
movl $0, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _ZL28precalc_xorwow_offset_matrix(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _ZL10mrg32k3aM1(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _ZL10mrg32k3aM2(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2016, %r9d
movl $0, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _ZL16mrg32k3aM1SubSeq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2016, %r9d
movl $0, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _ZL16mrg32k3aM2SubSeq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _ZL13mrg32k3aM1Seq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _ZL13mrg32k3aM2Seq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $72, %r9d
movl $0, %r8d
leaq .LC10(%rip), %rdx
movq %rdx, %rcx
leaq _ZL17__cr_lgamma_table(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4013:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl matrices_
.data
.align 32
.type matrices_, @object
.size matrices_, 56
matrices_:
.long 240
.long 240
.long 496
.long 496
.long 784
.long 784
.long 1016
.long 1016
.long 1232
.long 1232
.long 1680
.long 1680
.long 2024
.long 2024
.globl blocks_
.align 32
.type blocks_, @object
.size blocks_, 160
blocks_:
.long 8
.long 8
.long 16
.long 16
.long 24
.long 24
.long 32
.long 32
.long 1
.long 64
.long 1
.long 128
.long 1
.long 192
.long 1
.long 256
.long 1
.long 320
.long 1
.long 384
.long 1
.long 448
.long 1
.long 512
.long 1
.long 576
.long 1
.long 640
.long 1
.long 704
.long 1
.long 768
.long 1
.long 832
.long 1
.long 896
.long 1
.long 960
.long 1
.long 1024
.local _ZL17__cr_lgamma_table
.comm _ZL17__cr_lgamma_table,72,32
.local _ZL13mrg32k3aM2Seq
.comm _ZL13mrg32k3aM2Seq,2304,32
.local _ZL13mrg32k3aM1Seq
.comm _ZL13mrg32k3aM1Seq,2304,32
.local _ZL16mrg32k3aM2SubSeq
.comm _ZL16mrg32k3aM2SubSeq,2016,32
.local _ZL16mrg32k3aM1SubSeq
.comm _ZL16mrg32k3aM1SubSeq,2016,32
.local _ZL10mrg32k3aM2
.comm _ZL10mrg32k3aM2,2304,32
.local _ZL10mrg32k3aM1
.comm _ZL10mrg32k3aM1,2304,32
.local _ZL28precalc_xorwow_offset_matrix
.comm _ZL28precalc_xorwow_offset_matrix,102400,32
.local _ZL21precalc_xorwow_matrix
.comm _ZL21precalc_xorwow_matrix,102400,32
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC0:
.long 1148846080
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdbool.h>
#include <stdio.h>
#include <string.h>
#include <getopt.h>
#include <curand_kernel.h>
#include <stdlib.h>
#include <cuda.h>
#include <sys/time.h>
#include "LSTMDeltaKernelBPTT.cu"
#include<chrono>
#include<iostream>
using namespace std;
using namespace std::chrono;
int blocks_[20][2] = {{8,8},{16,16},{24,24},{32,32},{1,64},{1,128},{1,192},{1,256},{1,320},{1,384},{1,448},{1,512},{1,576},{1,640},{1,704},{1,768},{1,832},{1,896},{1,960},{1,1024}};
int matrices_[7][2] = {{240,240},{496,496},{784,784},{1016,1016},{1232,1232},{1680,1680},{2024,2024}};
int main(int argc, char **argv) {
cudaSetDevice(0);
char* p;int matrix_len=strtol(argv[1], &p, 10);
for(int matrix_looper=0;matrix_looper<matrix_len;matrix_looper++){
for(int block_looper=0;block_looper<20;block_looper++){
int XSIZE=matrices_[matrix_looper][0],YSIZE=matrices_[matrix_looper][1],BLOCKX=blocks_[block_looper][0],BLOCKY=blocks_[block_looper][1];
float *deltas = NULL;
cudaMalloc(&deltas, XSIZE*YSIZE);
float *cellStates = NULL;
cudaMalloc(&cellStates, XSIZE*YSIZE);
float *previousCellStates = NULL;
cudaMalloc(&previousCellStates, XSIZE*YSIZE);
float *cellStateErrors = NULL;
cudaMalloc(&cellStateErrors, XSIZE*YSIZE);
float *nextCellStateErrors = NULL;
cudaMalloc(&nextCellStateErrors, XSIZE*YSIZE);
float *outputGateDeltas = NULL;
cudaMalloc(&outputGateDeltas, XSIZE*YSIZE);
float *forgetGateDeltas = NULL;
cudaMalloc(&forgetGateDeltas, XSIZE*YSIZE);
float *nextForgetGateDeltas = NULL;
cudaMalloc(&nextForgetGateDeltas, XSIZE*YSIZE);
float *inputGateDeltas = NULL;
cudaMalloc(&inputGateDeltas, XSIZE*YSIZE);
float *nextInputGateDeltas = NULL;
cudaMalloc(&nextInputGateDeltas, XSIZE*YSIZE);
float *cellInputDeltas = NULL;
cudaMalloc(&cellInputDeltas, XSIZE*YSIZE);
float *cellInputActivations = NULL;
cudaMalloc(&cellInputActivations, XSIZE*YSIZE);
float *cellStateActivations = NULL;
cudaMalloc(&cellStateActivations, XSIZE*YSIZE);
float *outputGateActivations = NULL;
cudaMalloc(&outputGateActivations, XSIZE*YSIZE);
float *nextForgetGateActivations = NULL;
cudaMalloc(&nextForgetGateActivations, XSIZE*YSIZE);
float *inputGateActivations = NULL;
cudaMalloc(&inputGateActivations, XSIZE*YSIZE);
float *cellInputActivationDerivatives = NULL;
cudaMalloc(&cellInputActivationDerivatives, XSIZE*YSIZE);
float *cellStateActivationDerivatives = NULL;
cudaMalloc(&cellStateActivationDerivatives, XSIZE*YSIZE);
float *outputGateActivationDerivatives = NULL;
cudaMalloc(&outputGateActivationDerivatives, XSIZE*YSIZE);
float *forgetGateActivationDerivatives = NULL;
cudaMalloc(&forgetGateActivationDerivatives, XSIZE*YSIZE);
float *inputGateActivationDerivatives = NULL;
cudaMalloc(&inputGateActivationDerivatives, XSIZE*YSIZE);
float *cellInputWeights = NULL;
cudaMalloc(&cellInputWeights, XSIZE*YSIZE);
float *outputGateWeights = NULL;
cudaMalloc(&outputGateWeights, XSIZE*YSIZE);
float *forgetGateWeights = NULL;
cudaMalloc(&forgetGateWeights, XSIZE*YSIZE);
float *inputGateWeights = NULL;
cudaMalloc(&inputGateWeights, XSIZE*YSIZE);
int inputCount = 1;
int cellCount = 1;
int cellsPerBlock = 1;
int iXSIZE= XSIZE;
int iYSIZE= YSIZE;
while(iXSIZE%BLOCKX!=0)
{
iXSIZE++;
}
while(iYSIZE%BLOCKY!=0)
{
iYSIZE++;
}
dim3 gridBlock(iXSIZE/BLOCKX, iYSIZE/BLOCKY);
dim3 threadBlock(BLOCKX, BLOCKY);
cudaFree(0);
LSTMDeltaKernelBPTT<<<gridBlock,threadBlock>>>(deltas,cellStates,previousCellStates,cellStateErrors,nextCellStateErrors,outputGateDeltas,forgetGateDeltas,nextForgetGateDeltas,inputGateDeltas,nextInputGateDeltas,cellInputDeltas,cellInputActivations,cellStateActivations,outputGateActivations,nextForgetGateActivations,inputGateActivations,cellInputActivationDerivatives,cellStateActivationDerivatives,outputGateActivationDerivatives,forgetGateActivationDerivatives,inputGateActivationDerivatives,cellInputWeights,outputGateWeights,forgetGateWeights,inputGateWeights,inputCount,cellCount,cellsPerBlock);
cudaDeviceSynchronize();
for (int loop_counter = 0; loop_counter < 10; ++loop_counter) {
LSTMDeltaKernelBPTT<<<gridBlock,threadBlock>>>(deltas,cellStates,previousCellStates,cellStateErrors,nextCellStateErrors,outputGateDeltas,forgetGateDeltas,nextForgetGateDeltas,inputGateDeltas,nextInputGateDeltas,cellInputDeltas,cellInputActivations,cellStateActivations,outputGateActivations,nextForgetGateActivations,inputGateActivations,cellInputActivationDerivatives,cellStateActivationDerivatives,outputGateActivationDerivatives,forgetGateActivationDerivatives,inputGateActivationDerivatives,cellInputWeights,outputGateWeights,forgetGateWeights,inputGateWeights,inputCount,cellCount,cellsPerBlock);
}
auto start = steady_clock::now();
for (int loop_counter = 0; loop_counter < 1000; loop_counter++) {
LSTMDeltaKernelBPTT<<<gridBlock,threadBlock>>>(deltas,cellStates,previousCellStates,cellStateErrors,nextCellStateErrors,outputGateDeltas,forgetGateDeltas,nextForgetGateDeltas,inputGateDeltas,nextInputGateDeltas,cellInputDeltas,cellInputActivations,cellStateActivations,outputGateActivations,nextForgetGateActivations,inputGateActivations,cellInputActivationDerivatives,cellStateActivationDerivatives,outputGateActivationDerivatives,forgetGateActivationDerivatives,inputGateActivationDerivatives,cellInputWeights,outputGateWeights,forgetGateWeights,inputGateWeights,inputCount,cellCount,cellsPerBlock);
}
auto end = steady_clock::now();
auto usecs = duration_cast<duration<float, microseconds::period> >(end - start);
cout <<'['<<usecs.count()<<','<<'('<<BLOCKX<<','<<BLOCKY<<')' << ','<<'('<<XSIZE<<','<<YSIZE<<')'<<']' << endl;
}
}} | #include <stdbool.h>
#include <stdio.h>
#include <string.h>
#include <getopt.h>
#include <hiprand/hiprand_kernel.h>
#include <stdlib.h>
#include <hip/hip_runtime.h>
#include <sys/time.h>
#include "LSTMDeltaKernelBPTT.cu"
#include<chrono>
#include<iostream>
using namespace std;
using namespace std::chrono;
int blocks_[20][2] = {{8,8},{16,16},{24,24},{32,32},{1,64},{1,128},{1,192},{1,256},{1,320},{1,384},{1,448},{1,512},{1,576},{1,640},{1,704},{1,768},{1,832},{1,896},{1,960},{1,1024}};
int matrices_[7][2] = {{240,240},{496,496},{784,784},{1016,1016},{1232,1232},{1680,1680},{2024,2024}};
int main(int argc, char **argv) {
hipSetDevice(0);
char* p;int matrix_len=strtol(argv[1], &p, 10);
for(int matrix_looper=0;matrix_looper<matrix_len;matrix_looper++){
for(int block_looper=0;block_looper<20;block_looper++){
int XSIZE=matrices_[matrix_looper][0],YSIZE=matrices_[matrix_looper][1],BLOCKX=blocks_[block_looper][0],BLOCKY=blocks_[block_looper][1];
float *deltas = NULL;
hipMalloc(&deltas, XSIZE*YSIZE);
float *cellStates = NULL;
hipMalloc(&cellStates, XSIZE*YSIZE);
float *previousCellStates = NULL;
hipMalloc(&previousCellStates, XSIZE*YSIZE);
float *cellStateErrors = NULL;
hipMalloc(&cellStateErrors, XSIZE*YSIZE);
float *nextCellStateErrors = NULL;
hipMalloc(&nextCellStateErrors, XSIZE*YSIZE);
float *outputGateDeltas = NULL;
hipMalloc(&outputGateDeltas, XSIZE*YSIZE);
float *forgetGateDeltas = NULL;
hipMalloc(&forgetGateDeltas, XSIZE*YSIZE);
float *nextForgetGateDeltas = NULL;
hipMalloc(&nextForgetGateDeltas, XSIZE*YSIZE);
float *inputGateDeltas = NULL;
hipMalloc(&inputGateDeltas, XSIZE*YSIZE);
float *nextInputGateDeltas = NULL;
hipMalloc(&nextInputGateDeltas, XSIZE*YSIZE);
float *cellInputDeltas = NULL;
hipMalloc(&cellInputDeltas, XSIZE*YSIZE);
float *cellInputActivations = NULL;
hipMalloc(&cellInputActivations, XSIZE*YSIZE);
float *cellStateActivations = NULL;
hipMalloc(&cellStateActivations, XSIZE*YSIZE);
float *outputGateActivations = NULL;
hipMalloc(&outputGateActivations, XSIZE*YSIZE);
float *nextForgetGateActivations = NULL;
hipMalloc(&nextForgetGateActivations, XSIZE*YSIZE);
float *inputGateActivations = NULL;
hipMalloc(&inputGateActivations, XSIZE*YSIZE);
float *cellInputActivationDerivatives = NULL;
hipMalloc(&cellInputActivationDerivatives, XSIZE*YSIZE);
float *cellStateActivationDerivatives = NULL;
hipMalloc(&cellStateActivationDerivatives, XSIZE*YSIZE);
float *outputGateActivationDerivatives = NULL;
hipMalloc(&outputGateActivationDerivatives, XSIZE*YSIZE);
float *forgetGateActivationDerivatives = NULL;
hipMalloc(&forgetGateActivationDerivatives, XSIZE*YSIZE);
float *inputGateActivationDerivatives = NULL;
hipMalloc(&inputGateActivationDerivatives, XSIZE*YSIZE);
float *cellInputWeights = NULL;
hipMalloc(&cellInputWeights, XSIZE*YSIZE);
float *outputGateWeights = NULL;
hipMalloc(&outputGateWeights, XSIZE*YSIZE);
float *forgetGateWeights = NULL;
hipMalloc(&forgetGateWeights, XSIZE*YSIZE);
float *inputGateWeights = NULL;
hipMalloc(&inputGateWeights, XSIZE*YSIZE);
int inputCount = 1;
int cellCount = 1;
int cellsPerBlock = 1;
int iXSIZE= XSIZE;
int iYSIZE= YSIZE;
while(iXSIZE%BLOCKX!=0)
{
iXSIZE++;
}
while(iYSIZE%BLOCKY!=0)
{
iYSIZE++;
}
dim3 gridBlock(iXSIZE/BLOCKX, iYSIZE/BLOCKY);
dim3 threadBlock(BLOCKX, BLOCKY);
hipFree(0);
LSTMDeltaKernelBPTT<<<gridBlock,threadBlock>>>(deltas,cellStates,previousCellStates,cellStateErrors,nextCellStateErrors,outputGateDeltas,forgetGateDeltas,nextForgetGateDeltas,inputGateDeltas,nextInputGateDeltas,cellInputDeltas,cellInputActivations,cellStateActivations,outputGateActivations,nextForgetGateActivations,inputGateActivations,cellInputActivationDerivatives,cellStateActivationDerivatives,outputGateActivationDerivatives,forgetGateActivationDerivatives,inputGateActivationDerivatives,cellInputWeights,outputGateWeights,forgetGateWeights,inputGateWeights,inputCount,cellCount,cellsPerBlock);
hipDeviceSynchronize();
for (int loop_counter = 0; loop_counter < 10; ++loop_counter) {
LSTMDeltaKernelBPTT<<<gridBlock,threadBlock>>>(deltas,cellStates,previousCellStates,cellStateErrors,nextCellStateErrors,outputGateDeltas,forgetGateDeltas,nextForgetGateDeltas,inputGateDeltas,nextInputGateDeltas,cellInputDeltas,cellInputActivations,cellStateActivations,outputGateActivations,nextForgetGateActivations,inputGateActivations,cellInputActivationDerivatives,cellStateActivationDerivatives,outputGateActivationDerivatives,forgetGateActivationDerivatives,inputGateActivationDerivatives,cellInputWeights,outputGateWeights,forgetGateWeights,inputGateWeights,inputCount,cellCount,cellsPerBlock);
}
auto start = steady_clock::now();
for (int loop_counter = 0; loop_counter < 1000; loop_counter++) {
LSTMDeltaKernelBPTT<<<gridBlock,threadBlock>>>(deltas,cellStates,previousCellStates,cellStateErrors,nextCellStateErrors,outputGateDeltas,forgetGateDeltas,nextForgetGateDeltas,inputGateDeltas,nextInputGateDeltas,cellInputDeltas,cellInputActivations,cellStateActivations,outputGateActivations,nextForgetGateActivations,inputGateActivations,cellInputActivationDerivatives,cellStateActivationDerivatives,outputGateActivationDerivatives,forgetGateActivationDerivatives,inputGateActivationDerivatives,cellInputWeights,outputGateWeights,forgetGateWeights,inputGateWeights,inputCount,cellCount,cellsPerBlock);
}
auto end = steady_clock::now();
auto usecs = duration_cast<duration<float, microseconds::period> >(end - start);
cout <<'['<<usecs.count()<<','<<'('<<BLOCKX<<','<<BLOCKY<<')' << ','<<'('<<XSIZE<<','<<YSIZE<<')'<<']' << endl;
}
}} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <stdbool.h>
#include <stdio.h>
#include <string.h>
#include <getopt.h>
#include <hiprand/hiprand_kernel.h>
#include <stdlib.h>
#include <hip/hip_runtime.h>
#include <sys/time.h>
#include "LSTMDeltaKernelBPTT.cu"
#include<chrono>
#include<iostream>
using namespace std;
using namespace std::chrono;
int blocks_[20][2] = {{8,8},{16,16},{24,24},{32,32},{1,64},{1,128},{1,192},{1,256},{1,320},{1,384},{1,448},{1,512},{1,576},{1,640},{1,704},{1,768},{1,832},{1,896},{1,960},{1,1024}};
int matrices_[7][2] = {{240,240},{496,496},{784,784},{1016,1016},{1232,1232},{1680,1680},{2024,2024}};
int main(int argc, char **argv) {
hipSetDevice(0);
char* p;int matrix_len=strtol(argv[1], &p, 10);
for(int matrix_looper=0;matrix_looper<matrix_len;matrix_looper++){
for(int block_looper=0;block_looper<20;block_looper++){
int XSIZE=matrices_[matrix_looper][0],YSIZE=matrices_[matrix_looper][1],BLOCKX=blocks_[block_looper][0],BLOCKY=blocks_[block_looper][1];
float *deltas = NULL;
hipMalloc(&deltas, XSIZE*YSIZE);
float *cellStates = NULL;
hipMalloc(&cellStates, XSIZE*YSIZE);
float *previousCellStates = NULL;
hipMalloc(&previousCellStates, XSIZE*YSIZE);
float *cellStateErrors = NULL;
hipMalloc(&cellStateErrors, XSIZE*YSIZE);
float *nextCellStateErrors = NULL;
hipMalloc(&nextCellStateErrors, XSIZE*YSIZE);
float *outputGateDeltas = NULL;
hipMalloc(&outputGateDeltas, XSIZE*YSIZE);
float *forgetGateDeltas = NULL;
hipMalloc(&forgetGateDeltas, XSIZE*YSIZE);
float *nextForgetGateDeltas = NULL;
hipMalloc(&nextForgetGateDeltas, XSIZE*YSIZE);
float *inputGateDeltas = NULL;
hipMalloc(&inputGateDeltas, XSIZE*YSIZE);
float *nextInputGateDeltas = NULL;
hipMalloc(&nextInputGateDeltas, XSIZE*YSIZE);
float *cellInputDeltas = NULL;
hipMalloc(&cellInputDeltas, XSIZE*YSIZE);
float *cellInputActivations = NULL;
hipMalloc(&cellInputActivations, XSIZE*YSIZE);
float *cellStateActivations = NULL;
hipMalloc(&cellStateActivations, XSIZE*YSIZE);
float *outputGateActivations = NULL;
hipMalloc(&outputGateActivations, XSIZE*YSIZE);
float *nextForgetGateActivations = NULL;
hipMalloc(&nextForgetGateActivations, XSIZE*YSIZE);
float *inputGateActivations = NULL;
hipMalloc(&inputGateActivations, XSIZE*YSIZE);
float *cellInputActivationDerivatives = NULL;
hipMalloc(&cellInputActivationDerivatives, XSIZE*YSIZE);
float *cellStateActivationDerivatives = NULL;
hipMalloc(&cellStateActivationDerivatives, XSIZE*YSIZE);
float *outputGateActivationDerivatives = NULL;
hipMalloc(&outputGateActivationDerivatives, XSIZE*YSIZE);
float *forgetGateActivationDerivatives = NULL;
hipMalloc(&forgetGateActivationDerivatives, XSIZE*YSIZE);
float *inputGateActivationDerivatives = NULL;
hipMalloc(&inputGateActivationDerivatives, XSIZE*YSIZE);
float *cellInputWeights = NULL;
hipMalloc(&cellInputWeights, XSIZE*YSIZE);
float *outputGateWeights = NULL;
hipMalloc(&outputGateWeights, XSIZE*YSIZE);
float *forgetGateWeights = NULL;
hipMalloc(&forgetGateWeights, XSIZE*YSIZE);
float *inputGateWeights = NULL;
hipMalloc(&inputGateWeights, XSIZE*YSIZE);
int inputCount = 1;
int cellCount = 1;
int cellsPerBlock = 1;
int iXSIZE= XSIZE;
int iYSIZE= YSIZE;
while(iXSIZE%BLOCKX!=0)
{
iXSIZE++;
}
while(iYSIZE%BLOCKY!=0)
{
iYSIZE++;
}
dim3 gridBlock(iXSIZE/BLOCKX, iYSIZE/BLOCKY);
dim3 threadBlock(BLOCKX, BLOCKY);
hipFree(0);
LSTMDeltaKernelBPTT<<<gridBlock,threadBlock>>>(deltas,cellStates,previousCellStates,cellStateErrors,nextCellStateErrors,outputGateDeltas,forgetGateDeltas,nextForgetGateDeltas,inputGateDeltas,nextInputGateDeltas,cellInputDeltas,cellInputActivations,cellStateActivations,outputGateActivations,nextForgetGateActivations,inputGateActivations,cellInputActivationDerivatives,cellStateActivationDerivatives,outputGateActivationDerivatives,forgetGateActivationDerivatives,inputGateActivationDerivatives,cellInputWeights,outputGateWeights,forgetGateWeights,inputGateWeights,inputCount,cellCount,cellsPerBlock);
hipDeviceSynchronize();
for (int loop_counter = 0; loop_counter < 10; ++loop_counter) {
LSTMDeltaKernelBPTT<<<gridBlock,threadBlock>>>(deltas,cellStates,previousCellStates,cellStateErrors,nextCellStateErrors,outputGateDeltas,forgetGateDeltas,nextForgetGateDeltas,inputGateDeltas,nextInputGateDeltas,cellInputDeltas,cellInputActivations,cellStateActivations,outputGateActivations,nextForgetGateActivations,inputGateActivations,cellInputActivationDerivatives,cellStateActivationDerivatives,outputGateActivationDerivatives,forgetGateActivationDerivatives,inputGateActivationDerivatives,cellInputWeights,outputGateWeights,forgetGateWeights,inputGateWeights,inputCount,cellCount,cellsPerBlock);
}
auto start = steady_clock::now();
for (int loop_counter = 0; loop_counter < 1000; loop_counter++) {
LSTMDeltaKernelBPTT<<<gridBlock,threadBlock>>>(deltas,cellStates,previousCellStates,cellStateErrors,nextCellStateErrors,outputGateDeltas,forgetGateDeltas,nextForgetGateDeltas,inputGateDeltas,nextInputGateDeltas,cellInputDeltas,cellInputActivations,cellStateActivations,outputGateActivations,nextForgetGateActivations,inputGateActivations,cellInputActivationDerivatives,cellStateActivationDerivatives,outputGateActivationDerivatives,forgetGateActivationDerivatives,inputGateActivationDerivatives,cellInputWeights,outputGateWeights,forgetGateWeights,inputGateWeights,inputCount,cellCount,cellsPerBlock);
}
auto end = steady_clock::now();
auto usecs = duration_cast<duration<float, microseconds::period> >(end - start);
cout <<'['<<usecs.count()<<','<<'('<<BLOCKX<<','<<BLOCKY<<')' << ','<<'('<<XSIZE<<','<<YSIZE<<')'<<']' << endl;
}
}} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z19LSTMDeltaKernelBPTTPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_iii
.globl _Z19LSTMDeltaKernelBPTTPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_iii
.p2align 8
.type _Z19LSTMDeltaKernelBPTTPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_iii,@function
_Z19LSTMDeltaKernelBPTTPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_iii:
s_clause 0x2
s_load_b64 s[2:3], s[0:1], 0xcc
s_load_b32 s4, s[0:1], 0xd8
s_load_b32 s5, s[0:1], 0xe4
s_waitcnt lgkmcnt(0)
s_ashr_i32 s6, s3, 31
s_ashr_i32 s10, s2, 31
s_add_i32 s7, s3, s6
s_add_i32 s11, s2, s10
s_xor_b32 s7, s7, s6
s_xor_b32 s11, s11, s10
v_cvt_f32_u32_e32 v1, s7
s_sub_i32 s9, 0, s7
s_mul_i32 s4, s4, s15
s_and_b32 s5, s5, 0xffff
s_add_i32 s4, s4, s14
v_rcp_iflag_f32_e32 v1, v1
s_xor_b32 s6, s10, s6
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v1, 0x4f7ffffe, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_u32_f32_e32 v1, v1
v_readfirstlane_b32 s8, v1
v_mad_u64_u32 v[1:2], null, s4, s5, v[0:1]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s9, s9, s8
s_mul_hi_u32 s9, s8, s9
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s8, s8, s9
s_mul_hi_u32 s8, s11, s8
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
s_mul_i32 s9, s8, s7
s_add_i32 s10, s8, 1
s_sub_i32 s9, s11, s9
s_sub_i32 s11, s9, s7
s_cmp_ge_u32 s9, s7
s_cselect_b32 s4, s10, s8
s_cselect_b32 s5, s11, s9
s_add_i32 s8, s4, 1
s_cmp_ge_u32 s5, s7
s_cselect_b32 s4, s8, s4
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_xor_b32 s4, s4, s6
s_sub_i32 s4, s4, s6
s_delay_alu instid0(SALU_CYCLE_1)
v_cmp_gt_i32_e32 vcc_lo, s4, v1
s_and_saveexec_b32 s4, vcc_lo
s_cbranch_execz .LBB0_11
s_clause 0x1
s_load_b64 s[4:5], s[0:1], 0x28
s_load_b64 s[24:25], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
v_mul_lo_u32 v3, v1, s3
v_mov_b32_e32 v7, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[5:6], 2, v[1:2]
v_add_nc_u32_e32 v0, s3, v3
v_ashrrev_i32_e32 v4, 31, v3
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v5, vcc_lo, s4, v5
v_add_co_ci_u32_e32 v6, vcc_lo, s5, v6, vcc_lo
s_mov_b32 s4, exec_lo
global_store_b32 v[5:6], v7, off
v_cmpx_lt_i32_e64 v3, v0
s_cbranch_execz .LBB0_4
global_load_b32 v11, v[5:6], off
s_load_b64 s[6:7], s[0:1], 0x60
v_lshlrev_b64 v[9:10], 2, v[3:4]
s_mov_b32 s5, s3
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v7, vcc_lo, s6, v9
v_add_co_ci_u32_e32 v8, vcc_lo, s7, v10, vcc_lo
v_add_co_u32 v9, vcc_lo, s24, v9
v_add_co_ci_u32_e32 v10, vcc_lo, s25, v10, vcc_lo
.LBB0_3:
global_load_b32 v12, v[7:8], off
global_load_b32 v13, v[9:10], off
v_add_co_u32 v7, vcc_lo, v7, 4
v_add_co_ci_u32_e32 v8, vcc_lo, 0, v8, vcc_lo
v_add_co_u32 v9, vcc_lo, v9, 4
v_add_co_ci_u32_e32 v10, vcc_lo, 0, v10, vcc_lo
s_add_i32 s5, s5, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s5, 0
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v11, v12, v13
global_store_b32 v[5:6], v11, off
s_cbranch_scc0 .LBB0_3
.LBB0_4:
s_or_b32 exec_lo, exec_lo, s4
s_clause 0x1
s_load_b64 s[4:5], s[0:1], 0x90
s_load_b64 s[20:21], s[0:1], 0x18
v_lshlrev_b64 v[15:16], 2, v[1:2]
s_mov_b32 s26, exec_lo
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v7, vcc_lo, s4, v15
v_add_co_ci_u32_e32 v8, vcc_lo, s5, v16, vcc_lo
global_load_b32 v7, v[7:8], off
global_load_b32 v8, v[5:6], off
s_waitcnt vmcnt(0)
v_mul_f32_e32 v7, v7, v8
global_store_b32 v[5:6], v7, off
v_cmpx_lt_i32_e64 v3, v0
s_cbranch_execz .LBB0_7
s_clause 0x7
s_load_b32 s27, s[0:1], 0xc8
s_load_b256 s[4:11], s[0:1], 0x68
s_load_b128 s[16:19], s[0:1], 0x48
s_load_b64 s[28:29], s[0:1], 0x38
s_load_b64 s[30:31], s[0:1], 0x20
s_load_b64 s[22:23], s[0:1], 0xc0
s_load_b64 s[34:35], s[0:1], 0x88
s_load_b128 s[12:15], s[0:1], 0xb0
v_lshlrev_b64 v[27:28], 2, v[3:4]
s_waitcnt lgkmcnt(0)
s_add_i32 s2, s2, s27
v_add_co_u32 v7, vcc_lo, s4, v15
v_add_co_ci_u32_e32 v8, vcc_lo, s5, v16, vcc_lo
v_add_co_u32 v9, vcc_lo, s6, v15
v_add_co_ci_u32_e32 v10, vcc_lo, s7, v16, vcc_lo
v_add_co_u32 v11, vcc_lo, s16, v15
v_add_co_ci_u32_e32 v12, vcc_lo, s17, v16, vcc_lo
v_add_co_u32 v13, vcc_lo, s28, v15
v_add_co_ci_u32_e32 v14, vcc_lo, s29, v16, vcc_lo
v_add_co_u32 v15, vcc_lo, s8, v15
v_add_co_ci_u32_e32 v16, vcc_lo, s9, v16, vcc_lo
v_add_co_u32 v17, vcc_lo, s24, v27
v_add_co_ci_u32_e32 v18, vcc_lo, s25, v28, vcc_lo
v_add_co_u32 v19, vcc_lo, s34, v27
v_add_co_ci_u32_e32 v20, vcc_lo, s35, v28, vcc_lo
v_add_co_u32 v21, vcc_lo, s30, v27
s_add_i32 s4, s2, s3
v_add_co_ci_u32_e32 v22, vcc_lo, s31, v28, vcc_lo
v_add_co_u32 v23, vcc_lo, s20, v27
v_mul_lo_u32 v29, v1, s4
v_add_co_ci_u32_e32 v24, vcc_lo, s21, v28, vcc_lo
v_add_co_u32 v25, vcc_lo, s10, v27
v_add_co_ci_u32_e32 v26, vcc_lo, s11, v28, vcc_lo
v_add_co_u32 v27, vcc_lo, s18, v27
v_add_co_ci_u32_e32 v28, vcc_lo, s19, v28, vcc_lo
v_add3_u32 v29, v29, v1, s2
s_mov_b32 s2, s3
.LBB0_6:
s_delay_alu instid0(VALU_DEP_1)
v_ashrrev_i32_e32 v30, 31, v29
global_load_b32 v36, v[17:18], off
global_load_b32 v37, v[7:8], off
global_load_b32 v38, v[19:20], off
global_load_b32 v39, v[21:22], off
global_load_b32 v40, v[9:10], off
global_load_b32 v41, v[11:12], off
global_load_b32 v42, v[13:14], off
global_load_b32 v43, v[5:6], off
s_add_i32 s2, s2, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
s_cmp_eq_u32 s2, 0
v_lshlrev_b64 v[30:31], 2, v[29:30]
v_add_nc_u32_e32 v29, 1, v29
v_add_co_u32 v32, vcc_lo, s22, v30
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v33, vcc_lo, s23, v31, vcc_lo
v_add_co_u32 v34, vcc_lo, s14, v30
v_add_co_ci_u32_e32 v35, vcc_lo, s15, v31, vcc_lo
v_add_co_u32 v30, vcc_lo, s12, v30
v_add_co_ci_u32_e32 v31, vcc_lo, s13, v31, vcc_lo
global_load_b32 v32, v[32:33], off
global_load_b32 v33, v[34:35], off
global_load_b32 v30, v[30:31], off
v_add_co_u32 v17, vcc_lo, v17, 4
v_add_co_ci_u32_e32 v18, vcc_lo, 0, v18, vcc_lo
v_add_co_u32 v19, vcc_lo, v19, 4
v_add_co_ci_u32_e32 v20, vcc_lo, 0, v20, vcc_lo
v_add_co_u32 v21, vcc_lo, v21, 4
v_add_co_ci_u32_e32 v22, vcc_lo, 0, v22, vcc_lo
s_waitcnt vmcnt(6)
v_dual_mul_f32 v31, v36, v37 :: v_dual_mul_f32 v34, v39, v40
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v34, v31, v38
s_waitcnt vmcnt(2)
v_fmac_f32_e32 v34, v41, v32
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v34, v42, v33
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v34, v43, v30
global_store_b32 v[23:24], v34, off
global_load_b32 v30, v[15:16], off
global_load_b32 v31, v[25:26], off
v_add_co_u32 v23, vcc_lo, v23, 4
v_add_co_ci_u32_e32 v24, vcc_lo, 0, v24, vcc_lo
v_add_co_u32 v25, vcc_lo, v25, 4
v_add_co_ci_u32_e32 v26, vcc_lo, 0, v26, vcc_lo
s_waitcnt vmcnt(0)
v_mul_f32_e32 v30, v30, v31
s_delay_alu instid0(VALU_DEP_1)
v_mul_f32_e32 v30, v34, v30
global_store_b32 v[27:28], v30, off
v_add_co_u32 v27, vcc_lo, v27, 4
v_add_co_ci_u32_e32 v28, vcc_lo, 0, v28, vcc_lo
s_cbranch_scc0 .LBB0_6
.LBB0_7:
s_or_b32 exec_lo, exec_lo, s26
s_clause 0x1
s_load_b64 s[4:5], s[0:1], 0x40
s_load_b64 s[6:7], s[0:1], 0x30
v_lshlrev_b64 v[5:6], 2, v[1:2]
v_mov_b32_e32 v9, 0
s_mov_b32 s2, exec_lo
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v7, vcc_lo, s4, v5
v_add_co_ci_u32_e32 v8, vcc_lo, s5, v6, vcc_lo
v_add_co_u32 v5, vcc_lo, s6, v5
v_add_co_ci_u32_e32 v6, vcc_lo, s7, v6, vcc_lo
global_store_b32 v[7:8], v9, off
global_store_b32 v[5:6], v9, off
v_cmpx_lt_i32_e64 v3, v0
s_cbranch_execz .LBB0_10
s_clause 0x1
s_load_b64 s[4:5], s[0:1], 0x58
s_load_b64 s[6:7], s[0:1], 0x10
v_lshlrev_b64 v[11:12], 2, v[3:4]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v3, vcc_lo, s20, v11
v_add_co_ci_u32_e32 v4, vcc_lo, s21, v12, vcc_lo
s_waitcnt lgkmcnt(0)
v_add_co_u32 v9, vcc_lo, s4, v11
v_add_co_ci_u32_e32 v10, vcc_lo, s5, v12, vcc_lo
v_add_co_u32 v11, vcc_lo, s6, v11
v_add_co_ci_u32_e32 v12, vcc_lo, s7, v12, vcc_lo
.p2align 6
.LBB0_9:
global_load_b32 v0, v[3:4], off
global_load_b32 v13, v[9:10], off
global_load_b32 v14, v[7:8], off
v_add_co_u32 v9, vcc_lo, v9, 4
v_add_co_ci_u32_e32 v10, vcc_lo, 0, v10, vcc_lo
s_add_i32 s3, s3, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s3, 0
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v14, v0, v13
global_store_b32 v[7:8], v14, off
global_load_b32 v0, v[3:4], off
global_load_b32 v13, v[11:12], off
global_load_b32 v14, v[5:6], off
v_add_co_u32 v3, vcc_lo, v3, 4
v_add_co_ci_u32_e32 v4, vcc_lo, 0, v4, vcc_lo
v_add_co_u32 v11, vcc_lo, v11, 4
v_add_co_ci_u32_e32 v12, vcc_lo, 0, v12, vcc_lo
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v14, v0, v13
global_store_b32 v[5:6], v14, off
s_cbranch_scc0 .LBB0_9
.LBB0_10:
s_or_b32 exec_lo, exec_lo, s2
s_load_b128 s[0:3], s[0:1], 0x98
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v4, v[7:8], off
global_load_b32 v2, v[2:3], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_mul_f32_e32 v2, v2, v4
global_store_b32 v[7:8], v2, off
global_load_b32 v0, v[0:1], off
global_load_b32 v1, v[5:6], off
s_waitcnt vmcnt(0)
v_mul_f32_e32 v0, v0, v1
global_store_b32 v[5:6], v0, off
.LBB0_11:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z19LSTMDeltaKernelBPTTPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_iii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 472
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 44
.amdhsa_next_free_sgpr 36
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z19LSTMDeltaKernelBPTTPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_iii, .Lfunc_end0-_Z19LSTMDeltaKernelBPTTPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_iii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
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.size: 4
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.size: 4
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.size: 4
.value_kind: by_value
- .offset: 216
.size: 4
.value_kind: hidden_block_count_x
- .offset: 220
.size: 4
.value_kind: hidden_block_count_y
- .offset: 224
.size: 4
.value_kind: hidden_block_count_z
- .offset: 228
.size: 2
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- .offset: 230
.size: 2
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.size: 2
.value_kind: hidden_group_size_z
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.size: 2
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.size: 2
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.size: 2
.value_kind: hidden_remainder_z
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.size: 8
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.size: 8
.value_kind: hidden_global_offset_z
- .offset: 280
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 472
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z19LSTMDeltaKernelBPTTPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_iii
.private_segment_fixed_size: 0
.sgpr_count: 38
.sgpr_spill_count: 0
.symbol: _Z19LSTMDeltaKernelBPTTPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_iii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 44
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <stdbool.h>
#include <stdio.h>
#include <string.h>
#include <getopt.h>
#include <hiprand/hiprand_kernel.h>
#include <stdlib.h>
#include <hip/hip_runtime.h>
#include <sys/time.h>
#include "LSTMDeltaKernelBPTT.cu"
#include<chrono>
#include<iostream>
using namespace std;
using namespace std::chrono;
int blocks_[20][2] = {{8,8},{16,16},{24,24},{32,32},{1,64},{1,128},{1,192},{1,256},{1,320},{1,384},{1,448},{1,512},{1,576},{1,640},{1,704},{1,768},{1,832},{1,896},{1,960},{1,1024}};
int matrices_[7][2] = {{240,240},{496,496},{784,784},{1016,1016},{1232,1232},{1680,1680},{2024,2024}};
int main(int argc, char **argv) {
hipSetDevice(0);
char* p;int matrix_len=strtol(argv[1], &p, 10);
for(int matrix_looper=0;matrix_looper<matrix_len;matrix_looper++){
for(int block_looper=0;block_looper<20;block_looper++){
int XSIZE=matrices_[matrix_looper][0],YSIZE=matrices_[matrix_looper][1],BLOCKX=blocks_[block_looper][0],BLOCKY=blocks_[block_looper][1];
float *deltas = NULL;
hipMalloc(&deltas, XSIZE*YSIZE);
float *cellStates = NULL;
hipMalloc(&cellStates, XSIZE*YSIZE);
float *previousCellStates = NULL;
hipMalloc(&previousCellStates, XSIZE*YSIZE);
float *cellStateErrors = NULL;
hipMalloc(&cellStateErrors, XSIZE*YSIZE);
float *nextCellStateErrors = NULL;
hipMalloc(&nextCellStateErrors, XSIZE*YSIZE);
float *outputGateDeltas = NULL;
hipMalloc(&outputGateDeltas, XSIZE*YSIZE);
float *forgetGateDeltas = NULL;
hipMalloc(&forgetGateDeltas, XSIZE*YSIZE);
float *nextForgetGateDeltas = NULL;
hipMalloc(&nextForgetGateDeltas, XSIZE*YSIZE);
float *inputGateDeltas = NULL;
hipMalloc(&inputGateDeltas, XSIZE*YSIZE);
float *nextInputGateDeltas = NULL;
hipMalloc(&nextInputGateDeltas, XSIZE*YSIZE);
float *cellInputDeltas = NULL;
hipMalloc(&cellInputDeltas, XSIZE*YSIZE);
float *cellInputActivations = NULL;
hipMalloc(&cellInputActivations, XSIZE*YSIZE);
float *cellStateActivations = NULL;
hipMalloc(&cellStateActivations, XSIZE*YSIZE);
float *outputGateActivations = NULL;
hipMalloc(&outputGateActivations, XSIZE*YSIZE);
float *nextForgetGateActivations = NULL;
hipMalloc(&nextForgetGateActivations, XSIZE*YSIZE);
float *inputGateActivations = NULL;
hipMalloc(&inputGateActivations, XSIZE*YSIZE);
float *cellInputActivationDerivatives = NULL;
hipMalloc(&cellInputActivationDerivatives, XSIZE*YSIZE);
float *cellStateActivationDerivatives = NULL;
hipMalloc(&cellStateActivationDerivatives, XSIZE*YSIZE);
float *outputGateActivationDerivatives = NULL;
hipMalloc(&outputGateActivationDerivatives, XSIZE*YSIZE);
float *forgetGateActivationDerivatives = NULL;
hipMalloc(&forgetGateActivationDerivatives, XSIZE*YSIZE);
float *inputGateActivationDerivatives = NULL;
hipMalloc(&inputGateActivationDerivatives, XSIZE*YSIZE);
float *cellInputWeights = NULL;
hipMalloc(&cellInputWeights, XSIZE*YSIZE);
float *outputGateWeights = NULL;
hipMalloc(&outputGateWeights, XSIZE*YSIZE);
float *forgetGateWeights = NULL;
hipMalloc(&forgetGateWeights, XSIZE*YSIZE);
float *inputGateWeights = NULL;
hipMalloc(&inputGateWeights, XSIZE*YSIZE);
int inputCount = 1;
int cellCount = 1;
int cellsPerBlock = 1;
int iXSIZE= XSIZE;
int iYSIZE= YSIZE;
while(iXSIZE%BLOCKX!=0)
{
iXSIZE++;
}
while(iYSIZE%BLOCKY!=0)
{
iYSIZE++;
}
dim3 gridBlock(iXSIZE/BLOCKX, iYSIZE/BLOCKY);
dim3 threadBlock(BLOCKX, BLOCKY);
hipFree(0);
LSTMDeltaKernelBPTT<<<gridBlock,threadBlock>>>(deltas,cellStates,previousCellStates,cellStateErrors,nextCellStateErrors,outputGateDeltas,forgetGateDeltas,nextForgetGateDeltas,inputGateDeltas,nextInputGateDeltas,cellInputDeltas,cellInputActivations,cellStateActivations,outputGateActivations,nextForgetGateActivations,inputGateActivations,cellInputActivationDerivatives,cellStateActivationDerivatives,outputGateActivationDerivatives,forgetGateActivationDerivatives,inputGateActivationDerivatives,cellInputWeights,outputGateWeights,forgetGateWeights,inputGateWeights,inputCount,cellCount,cellsPerBlock);
hipDeviceSynchronize();
for (int loop_counter = 0; loop_counter < 10; ++loop_counter) {
LSTMDeltaKernelBPTT<<<gridBlock,threadBlock>>>(deltas,cellStates,previousCellStates,cellStateErrors,nextCellStateErrors,outputGateDeltas,forgetGateDeltas,nextForgetGateDeltas,inputGateDeltas,nextInputGateDeltas,cellInputDeltas,cellInputActivations,cellStateActivations,outputGateActivations,nextForgetGateActivations,inputGateActivations,cellInputActivationDerivatives,cellStateActivationDerivatives,outputGateActivationDerivatives,forgetGateActivationDerivatives,inputGateActivationDerivatives,cellInputWeights,outputGateWeights,forgetGateWeights,inputGateWeights,inputCount,cellCount,cellsPerBlock);
}
auto start = steady_clock::now();
for (int loop_counter = 0; loop_counter < 1000; loop_counter++) {
LSTMDeltaKernelBPTT<<<gridBlock,threadBlock>>>(deltas,cellStates,previousCellStates,cellStateErrors,nextCellStateErrors,outputGateDeltas,forgetGateDeltas,nextForgetGateDeltas,inputGateDeltas,nextInputGateDeltas,cellInputDeltas,cellInputActivations,cellStateActivations,outputGateActivations,nextForgetGateActivations,inputGateActivations,cellInputActivationDerivatives,cellStateActivationDerivatives,outputGateActivationDerivatives,forgetGateActivationDerivatives,inputGateActivationDerivatives,cellInputWeights,outputGateWeights,forgetGateWeights,inputGateWeights,inputCount,cellCount,cellsPerBlock);
}
auto end = steady_clock::now();
auto usecs = duration_cast<duration<float, microseconds::period> >(end - start);
cout <<'['<<usecs.count()<<','<<'('<<BLOCKX<<','<<BLOCKY<<')' << ','<<'('<<XSIZE<<','<<YSIZE<<')'<<']' << endl;
}
}} | .text
.file "main.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z34__device_stub__LSTMDeltaKernelBPTTPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_iii # -- Begin function _Z34__device_stub__LSTMDeltaKernelBPTTPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_iii
.p2align 4, 0x90
.type _Z34__device_stub__LSTMDeltaKernelBPTTPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_iii,@function
_Z34__device_stub__LSTMDeltaKernelBPTTPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_iii: # @_Z34__device_stub__LSTMDeltaKernelBPTTPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_iii
.cfi_startproc
# %bb.0:
subq $328, %rsp # imm = 0x148
.cfi_def_cfa_offset 336
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
movq %r9, 48(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 336(%rsp), %rax
movq %rax, 144(%rsp)
leaq 344(%rsp), %rax
movq %rax, 152(%rsp)
leaq 352(%rsp), %rax
movq %rax, 160(%rsp)
leaq 360(%rsp), %rax
movq %rax, 168(%rsp)
leaq 368(%rsp), %rax
movq %rax, 176(%rsp)
leaq 376(%rsp), %rax
movq %rax, 184(%rsp)
leaq 384(%rsp), %rax
movq %rax, 192(%rsp)
leaq 392(%rsp), %rax
movq %rax, 200(%rsp)
leaq 400(%rsp), %rax
movq %rax, 208(%rsp)
leaq 408(%rsp), %rax
movq %rax, 216(%rsp)
leaq 416(%rsp), %rax
movq %rax, 224(%rsp)
leaq 424(%rsp), %rax
movq %rax, 232(%rsp)
leaq 432(%rsp), %rax
movq %rax, 240(%rsp)
leaq 440(%rsp), %rax
movq %rax, 248(%rsp)
leaq 448(%rsp), %rax
movq %rax, 256(%rsp)
leaq 456(%rsp), %rax
movq %rax, 264(%rsp)
leaq 464(%rsp), %rax
movq %rax, 272(%rsp)
leaq 472(%rsp), %rax
movq %rax, 280(%rsp)
leaq 480(%rsp), %rax
movq %rax, 288(%rsp)
leaq 488(%rsp), %rax
movq %rax, 296(%rsp)
leaq 496(%rsp), %rax
movq %rax, 304(%rsp)
leaq 504(%rsp), %rax
movq %rax, 312(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z19LSTMDeltaKernelBPTTPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_iii, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $344, %rsp # imm = 0x158
.cfi_adjust_cfa_offset -344
retq
.Lfunc_end0:
.size _Z34__device_stub__LSTMDeltaKernelBPTTPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_iii, .Lfunc_end0-_Z34__device_stub__LSTMDeltaKernelBPTTPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_iii
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI1_0:
.long 0x447a0000 # float 1000
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $264, %rsp # imm = 0x108
.cfi_def_cfa_offset 320
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %rbx
xorl %edi, %edi
callq hipSetDevice
movq 8(%rbx), %rdi
leaq 256(%rsp), %rsi
movl $10, %edx
callq __isoc23_strtol
testl %eax, %eax
jle .LBB1_20
# %bb.1: # %.preheader163.preheader
movl %eax, %eax
movq %rax, 240(%rsp) # 8-byte Spill
xorl %eax, %eax
movq %rax, 216(%rsp) # 8-byte Spill
jmp .LBB1_2
.p2align 4, 0x90
.LBB1_19: # in Loop: Header=BB1_2 Depth=1
movq 216(%rsp), %rcx # 8-byte Reload
incq %rcx
movq %rcx, %rax
movq %rcx, 216(%rsp) # 8-byte Spill
cmpq 240(%rsp), %rcx # 8-byte Folded Reload
je .LBB1_20
.LBB1_2: # %.preheader163
# =>This Loop Header: Depth=1
# Child Loop BB1_3 Depth 2
# Child Loop BB1_4 Depth 3
# Child Loop BB1_6 Depth 3
# Child Loop BB1_10 Depth 3
# Child Loop BB1_14 Depth 3
xorl %ecx, %ecx
jmp .LBB1_3
.p2align 4, 0x90
.LBB1_52: # in Loop: Header=BB1_3 Depth=2
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_53: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
# in Loop: Header=BB1_3 Depth=2
movsbl %al, %esi
movq %rbx, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq 248(%rsp), %rcx # 8-byte Reload
incq %rcx
cmpq $20, %rcx
je .LBB1_19
.LBB1_3: # Parent Loop BB1_2 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB1_4 Depth 3
# Child Loop BB1_6 Depth 3
# Child Loop BB1_10 Depth 3
# Child Loop BB1_14 Depth 3
movq 216(%rsp), %rax # 8-byte Reload
movl matrices_(,%rax,8), %r12d
movl matrices_+4(,%rax,8), %r15d
movl blocks_(,%rcx,8), %ebp
movq %rcx, 248(%rsp) # 8-byte Spill
movl blocks_+4(,%rcx,8), %r14d
movq $0, 208(%rsp)
movl %r15d, %eax
imull %r12d, %eax
movslq %eax, %rbx
leaq 208(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
movq $0, 200(%rsp)
leaq 200(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
movq $0, 192(%rsp)
leaq 192(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
movq $0, 184(%rsp)
leaq 184(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
movq $0, 176(%rsp)
leaq 176(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
movq $0, 168(%rsp)
leaq 168(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
movq $0, 160(%rsp)
leaq 160(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
movq $0, 152(%rsp)
leaq 152(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
movq $0, 144(%rsp)
leaq 144(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
movq $0, 136(%rsp)
leaq 136(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
movq $0, 128(%rsp)
leaq 128(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
movq $0, 120(%rsp)
leaq 120(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
movq $0, 112(%rsp)
leaq 112(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
movq $0, 104(%rsp)
leaq 104(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
movq $0, 96(%rsp)
leaq 96(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
movq $0, 88(%rsp)
leaq 88(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
movq $0, 80(%rsp)
leaq 80(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
movq $0, 72(%rsp)
leaq 72(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
movq $0, 64(%rsp)
leaq 64(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
movq $0, 56(%rsp)
leaq 56(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
movq $0, 48(%rsp)
leaq 48(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
movq $0, 40(%rsp)
leaq 40(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
movq $0, 32(%rsp)
leaq 32(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
movq $0, 24(%rsp)
leaq 24(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
movq $0, 16(%rsp)
leaq 16(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
movl %r12d, 232(%rsp) # 4-byte Spill
movl %r12d, %ecx
.p2align 4, 0x90
.LBB1_4: # Parent Loop BB1_2 Depth=1
# Parent Loop BB1_3 Depth=2
# => This Inner Loop Header: Depth=3
movl %ecx, %eax
cltd
idivl %ebp
incl %ecx
testl %edx, %edx
jne .LBB1_4
# %bb.5: # %.preheader.preheader
# in Loop: Header=BB1_3 Depth=2
movl %eax, %esi
movl %r15d, %ecx
.p2align 4, 0x90
.LBB1_6: # %.preheader
# Parent Loop BB1_2 Depth=1
# Parent Loop BB1_3 Depth=2
# => This Inner Loop Header: Depth=3
movl %ecx, %eax
cltd
idivl %r14d
incl %ecx
testl %edx, %edx
jne .LBB1_6
# %bb.7: # in Loop: Header=BB1_3 Depth=2
movl %eax, %ebx
movl %r15d, 236(%rsp) # 4-byte Spill
movl %esi, %eax
shlq $32, %rbx
orq %rax, %rbx
movq %r14, %r13
shlq $32, %r13
orq %rbp, %r13
xorl %edi, %edi
callq hipFree
movq %rbx, %rdi
movl $1, %esi
movq %r13, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_9
# %bb.8: # in Loop: Header=BB1_3 Depth=2
movq 208(%rsp), %rdi
movq 200(%rsp), %rsi
movq 192(%rsp), %rdx
movq 184(%rsp), %rcx
movq 176(%rsp), %r8
movq 168(%rsp), %r9
pushq $1
.cfi_adjust_cfa_offset 8
pushq $1
.cfi_adjust_cfa_offset 8
pushq $1
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
pushq 88(%rsp)
.cfi_adjust_cfa_offset 8
pushq 104(%rsp)
.cfi_adjust_cfa_offset 8
pushq 120(%rsp)
.cfi_adjust_cfa_offset 8
pushq 136(%rsp)
.cfi_adjust_cfa_offset 8
pushq 152(%rsp)
.cfi_adjust_cfa_offset 8
pushq 168(%rsp)
.cfi_adjust_cfa_offset 8
pushq 184(%rsp)
.cfi_adjust_cfa_offset 8
pushq 200(%rsp)
.cfi_adjust_cfa_offset 8
pushq 216(%rsp)
.cfi_adjust_cfa_offset 8
pushq 232(%rsp)
.cfi_adjust_cfa_offset 8
pushq 248(%rsp)
.cfi_adjust_cfa_offset 8
pushq 264(%rsp)
.cfi_adjust_cfa_offset 8
pushq 280(%rsp)
.cfi_adjust_cfa_offset 8
pushq 296(%rsp)
.cfi_adjust_cfa_offset 8
pushq 312(%rsp)
.cfi_adjust_cfa_offset 8
pushq 328(%rsp)
.cfi_adjust_cfa_offset 8
callq _Z34__device_stub__LSTMDeltaKernelBPTTPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_iii
addq $176, %rsp
.cfi_adjust_cfa_offset -176
.LBB1_9: # in Loop: Header=BB1_3 Depth=2
callq hipDeviceSynchronize
movl $10, %r15d
jmp .LBB1_10
.p2align 4, 0x90
.LBB1_12: # in Loop: Header=BB1_10 Depth=3
decl %r15d
je .LBB1_13
.LBB1_10: # Parent Loop BB1_2 Depth=1
# Parent Loop BB1_3 Depth=2
# => This Inner Loop Header: Depth=3
movq %rbx, %rdi
movl $1, %esi
movq %r13, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_12
# %bb.11: # in Loop: Header=BB1_10 Depth=3
movq 208(%rsp), %rdi
movq 200(%rsp), %rsi
movq 192(%rsp), %rdx
movq 184(%rsp), %rcx
movq 176(%rsp), %r8
movq 168(%rsp), %r9
pushq $1
.cfi_adjust_cfa_offset 8
pushq $1
.cfi_adjust_cfa_offset 8
pushq $1
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
pushq 88(%rsp)
.cfi_adjust_cfa_offset 8
pushq 104(%rsp)
.cfi_adjust_cfa_offset 8
pushq 120(%rsp)
.cfi_adjust_cfa_offset 8
pushq 136(%rsp)
.cfi_adjust_cfa_offset 8
pushq 152(%rsp)
.cfi_adjust_cfa_offset 8
pushq 168(%rsp)
.cfi_adjust_cfa_offset 8
pushq 184(%rsp)
.cfi_adjust_cfa_offset 8
pushq 200(%rsp)
.cfi_adjust_cfa_offset 8
pushq 216(%rsp)
.cfi_adjust_cfa_offset 8
pushq 232(%rsp)
.cfi_adjust_cfa_offset 8
pushq 248(%rsp)
.cfi_adjust_cfa_offset 8
pushq 264(%rsp)
.cfi_adjust_cfa_offset 8
pushq 280(%rsp)
.cfi_adjust_cfa_offset 8
pushq 296(%rsp)
.cfi_adjust_cfa_offset 8
pushq 312(%rsp)
.cfi_adjust_cfa_offset 8
pushq 328(%rsp)
.cfi_adjust_cfa_offset 8
callq _Z34__device_stub__LSTMDeltaKernelBPTTPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_iii
addq $176, %rsp
.cfi_adjust_cfa_offset -176
jmp .LBB1_12
.p2align 4, 0x90
.LBB1_13: # in Loop: Header=BB1_3 Depth=2
movl $1000, %r12d # imm = 0x3E8
callq _ZNSt6chrono3_V212steady_clock3nowEv
movq %rax, %r15
jmp .LBB1_14
.p2align 4, 0x90
.LBB1_16: # in Loop: Header=BB1_14 Depth=3
decl %r12d
je .LBB1_17
.LBB1_14: # Parent Loop BB1_2 Depth=1
# Parent Loop BB1_3 Depth=2
# => This Inner Loop Header: Depth=3
movq %rbx, %rdi
movl $1, %esi
movq %r13, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_16
# %bb.15: # in Loop: Header=BB1_14 Depth=3
movq 208(%rsp), %rdi
movq 200(%rsp), %rsi
movq 192(%rsp), %rdx
movq 184(%rsp), %rcx
movq 176(%rsp), %r8
movq 168(%rsp), %r9
pushq $1
.cfi_adjust_cfa_offset 8
pushq $1
.cfi_adjust_cfa_offset 8
pushq $1
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
pushq 88(%rsp)
.cfi_adjust_cfa_offset 8
pushq 104(%rsp)
.cfi_adjust_cfa_offset 8
pushq 120(%rsp)
.cfi_adjust_cfa_offset 8
pushq 136(%rsp)
.cfi_adjust_cfa_offset 8
pushq 152(%rsp)
.cfi_adjust_cfa_offset 8
pushq 168(%rsp)
.cfi_adjust_cfa_offset 8
pushq 184(%rsp)
.cfi_adjust_cfa_offset 8
pushq 200(%rsp)
.cfi_adjust_cfa_offset 8
pushq 216(%rsp)
.cfi_adjust_cfa_offset 8
pushq 232(%rsp)
.cfi_adjust_cfa_offset 8
pushq 248(%rsp)
.cfi_adjust_cfa_offset 8
pushq 264(%rsp)
.cfi_adjust_cfa_offset 8
pushq 280(%rsp)
.cfi_adjust_cfa_offset 8
pushq 296(%rsp)
.cfi_adjust_cfa_offset 8
pushq 312(%rsp)
.cfi_adjust_cfa_offset 8
pushq 328(%rsp)
.cfi_adjust_cfa_offset 8
callq _Z34__device_stub__LSTMDeltaKernelBPTTPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_iii
addq $176, %rsp
.cfi_adjust_cfa_offset -176
jmp .LBB1_16
.p2align 4, 0x90
.LBB1_17: # in Loop: Header=BB1_3 Depth=2
callq _ZNSt6chrono3_V212steady_clock3nowEv
subq %r15, %rax
cvtsi2ss %rax, %xmm0
divss .LCPI1_0(%rip), %xmm0
movss %xmm0, 228(%rsp) # 4-byte Spill
movb $91, 15(%rsp)
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
cmpq $0, _ZSt4cout+16(%rax)
je .LBB1_21
# %bb.18: # in Loop: Header=BB1_3 Depth=2
movl $_ZSt4cout, %edi
movl $1, %edx
leaq 15(%rsp), %r15
movq %r15, %rsi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq %rax, %rbx
jmp .LBB1_22
.p2align 4, 0x90
.LBB1_21: # in Loop: Header=BB1_3 Depth=2
movl $_ZSt4cout, %ebx
movl $_ZSt4cout, %edi
movl $91, %esi
callq _ZNSo3putEc
leaq 15(%rsp), %r15
.LBB1_22: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c.exit
# in Loop: Header=BB1_3 Depth=2
movss 228(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movq %rbx, %rdi
callq _ZNSo9_M_insertIdEERSoT_
movb $44, 15(%rsp)
movq (%rax), %rcx
movq -24(%rcx), %rcx
cmpq $0, 16(%rax,%rcx)
je .LBB1_24
# %bb.23: # in Loop: Header=BB1_3 Depth=2
movl $1, %edx
movq %rax, %rdi
movq %r15, %rsi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq %rax, %rbx
jmp .LBB1_25
.p2align 4, 0x90
.LBB1_24: # in Loop: Header=BB1_3 Depth=2
movq %rax, %rbx
movq %rax, %rdi
movl $44, %esi
callq _ZNSo3putEc
.LBB1_25: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c.exit124
# in Loop: Header=BB1_3 Depth=2
movb $40, 15(%rsp)
movq (%rbx), %rcx
movq -24(%rcx), %rcx
cmpq $0, 16(%rbx,%rcx)
je .LBB1_27
# %bb.26: # in Loop: Header=BB1_3 Depth=2
movl $1, %edx
movq %rbx, %rdi
movq %r15, %rsi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq %rax, %rdi
jmp .LBB1_28
.p2align 4, 0x90
.LBB1_27: # in Loop: Header=BB1_3 Depth=2
movq %rbx, %rdi
movl $40, %esi
callq _ZNSo3putEc
movq %rbx, %rdi
.LBB1_28: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c.exit127
# in Loop: Header=BB1_3 Depth=2
movl %ebp, %esi
callq _ZNSolsEi
movb $44, 15(%rsp)
movq (%rax), %rcx
movq -24(%rcx), %rcx
cmpq $0, 16(%rax,%rcx)
je .LBB1_30
# %bb.29: # in Loop: Header=BB1_3 Depth=2
movl $1, %edx
movq %rax, %rdi
movq %r15, %rsi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq %rax, %rdi
jmp .LBB1_31
.p2align 4, 0x90
.LBB1_30: # in Loop: Header=BB1_3 Depth=2
movq %rax, %rbx
movq %rax, %rdi
movl $44, %esi
callq _ZNSo3putEc
movq %rbx, %rdi
.LBB1_31: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c.exit130
# in Loop: Header=BB1_3 Depth=2
movl %r14d, %esi
callq _ZNSolsEi
movq %rax, %rbx
movb $41, 15(%rsp)
movq (%rax), %rax
movq -24(%rax), %rax
cmpq $0, 16(%rbx,%rax)
je .LBB1_33
# %bb.32: # in Loop: Header=BB1_3 Depth=2
movl $1, %edx
movq %rbx, %rdi
movq %r15, %rsi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq %rax, %rbx
jmp .LBB1_34
.p2align 4, 0x90
.LBB1_33: # in Loop: Header=BB1_3 Depth=2
movq %rbx, %rdi
movl $41, %esi
callq _ZNSo3putEc
.LBB1_34: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c.exit133
# in Loop: Header=BB1_3 Depth=2
movb $44, 15(%rsp)
movq (%rbx), %rax
movq -24(%rax), %rax
cmpq $0, 16(%rbx,%rax)
je .LBB1_36
# %bb.35: # in Loop: Header=BB1_3 Depth=2
movl $1, %edx
movq %rbx, %rdi
movq %r15, %rsi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq %rax, %rbx
jmp .LBB1_37
.p2align 4, 0x90
.LBB1_36: # in Loop: Header=BB1_3 Depth=2
movq %rbx, %rdi
movl $44, %esi
callq _ZNSo3putEc
.LBB1_37: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c.exit136
# in Loop: Header=BB1_3 Depth=2
movb $40, 15(%rsp)
movq (%rbx), %rax
movq -24(%rax), %rax
cmpq $0, 16(%rbx,%rax)
je .LBB1_39
# %bb.38: # in Loop: Header=BB1_3 Depth=2
movl $1, %edx
movq %rbx, %rdi
movq %r15, %rsi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq %rax, %rbx
jmp .LBB1_40
.p2align 4, 0x90
.LBB1_39: # in Loop: Header=BB1_3 Depth=2
movq %rbx, %rdi
movl $40, %esi
callq _ZNSo3putEc
.LBB1_40: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c.exit139
# in Loop: Header=BB1_3 Depth=2
movq %rbx, %rdi
movl 232(%rsp), %esi # 4-byte Reload
callq _ZNSolsEi
movb $44, 15(%rsp)
movq (%rax), %rcx
movq -24(%rcx), %rcx
cmpq $0, 16(%rax,%rcx)
je .LBB1_42
# %bb.41: # in Loop: Header=BB1_3 Depth=2
movl $1, %edx
movq %rax, %rdi
movq %r15, %rsi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq %rax, %rdi
jmp .LBB1_43
.p2align 4, 0x90
.LBB1_42: # in Loop: Header=BB1_3 Depth=2
movq %rax, %rbx
movq %rax, %rdi
movl $44, %esi
callq _ZNSo3putEc
movq %rbx, %rdi
.LBB1_43: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c.exit142
# in Loop: Header=BB1_3 Depth=2
movl 236(%rsp), %esi # 4-byte Reload
callq _ZNSolsEi
movq %rax, %rbx
movb $41, 15(%rsp)
movq (%rax), %rax
movq -24(%rax), %rax
cmpq $0, 16(%rbx,%rax)
je .LBB1_45
# %bb.44: # in Loop: Header=BB1_3 Depth=2
movl $1, %edx
movq %rbx, %rdi
movq %r15, %rsi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq %rax, %rbx
jmp .LBB1_46
.p2align 4, 0x90
.LBB1_45: # in Loop: Header=BB1_3 Depth=2
movq %rbx, %rdi
movl $41, %esi
callq _ZNSo3putEc
.LBB1_46: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c.exit145
# in Loop: Header=BB1_3 Depth=2
movb $93, 15(%rsp)
movq (%rbx), %rax
movq -24(%rax), %rax
cmpq $0, 16(%rbx,%rax)
je .LBB1_48
# %bb.47: # in Loop: Header=BB1_3 Depth=2
movl $1, %edx
movq %rbx, %rdi
movq %r15, %rsi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq %rax, %rbx
jmp .LBB1_49
.p2align 4, 0x90
.LBB1_48: # in Loop: Header=BB1_3 Depth=2
movq %rbx, %rdi
movl $93, %esi
callq _ZNSo3putEc
.LBB1_49: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c.exit148
# in Loop: Header=BB1_3 Depth=2
movq (%rbx), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r14
testq %r14, %r14
je .LBB1_54
# %bb.50: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
# in Loop: Header=BB1_3 Depth=2
cmpb $0, 56(%r14)
je .LBB1_52
# %bb.51: # in Loop: Header=BB1_3 Depth=2
movzbl 67(%r14), %eax
jmp .LBB1_53
.LBB1_20: # %._crit_edge
xorl %eax, %eax
addq $264, %rsp # imm = 0x108
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_54:
.cfi_def_cfa_offset 320
callq _ZSt16__throw_bad_castv
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z19LSTMDeltaKernelBPTTPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_iii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z19LSTMDeltaKernelBPTTPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_iii,@object # @_Z19LSTMDeltaKernelBPTTPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_iii
.section .rodata,"a",@progbits
.globl _Z19LSTMDeltaKernelBPTTPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_iii
.p2align 3, 0x0
_Z19LSTMDeltaKernelBPTTPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_iii:
.quad _Z34__device_stub__LSTMDeltaKernelBPTTPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_iii
.size _Z19LSTMDeltaKernelBPTTPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_iii, 8
.type blocks_,@object # @blocks_
.data
.globl blocks_
.p2align 4, 0x0
blocks_:
.long 8 # 0x8
.long 8 # 0x8
.long 16 # 0x10
.long 16 # 0x10
.long 24 # 0x18
.long 24 # 0x18
.long 32 # 0x20
.long 32 # 0x20
.long 1 # 0x1
.long 64 # 0x40
.long 1 # 0x1
.long 128 # 0x80
.long 1 # 0x1
.long 192 # 0xc0
.long 1 # 0x1
.long 256 # 0x100
.long 1 # 0x1
.long 320 # 0x140
.long 1 # 0x1
.long 384 # 0x180
.long 1 # 0x1
.long 448 # 0x1c0
.long 1 # 0x1
.long 512 # 0x200
.long 1 # 0x1
.long 576 # 0x240
.long 1 # 0x1
.long 640 # 0x280
.long 1 # 0x1
.long 704 # 0x2c0
.long 1 # 0x1
.long 768 # 0x300
.long 1 # 0x1
.long 832 # 0x340
.long 1 # 0x1
.long 896 # 0x380
.long 1 # 0x1
.long 960 # 0x3c0
.long 1 # 0x1
.long 1024 # 0x400
.size blocks_, 160
.type matrices_,@object # @matrices_
.globl matrices_
.p2align 4, 0x0
matrices_:
.long 240 # 0xf0
.long 240 # 0xf0
.long 496 # 0x1f0
.long 496 # 0x1f0
.long 784 # 0x310
.long 784 # 0x310
.long 1016 # 0x3f8
.long 1016 # 0x3f8
.long 1232 # 0x4d0
.long 1232 # 0x4d0
.long 1680 # 0x690
.long 1680 # 0x690
.long 2024 # 0x7e8
.long 2024 # 0x7e8
.size matrices_, 56
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z19LSTMDeltaKernelBPTTPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_iii"
.size .L__unnamed_1, 77
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z34__device_stub__LSTMDeltaKernelBPTTPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_iii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z19LSTMDeltaKernelBPTTPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_iii
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <cuda.h>
#include <stdio.h>
#include <iostream>
#define NUM_THREADS 1000000
#define ARRAY_SIZE 100
#define BLOCK_WIDTH 1000
struct GpuTimer
{
cudaEvent_t start;
cudaEvent_t stop;
GpuTimer ()
{
cudaEventCreate(&start);
cudaEventCreate(&stop);
}
~GpuTimer ()
{
cudaEventDestroy(start);
cudaEventDestroy(stop);
}
void Start ()
{
cudaEventRecord(start, 0);
}
void Stop ()
{
cudaEventRecord(stop, 0);
}
float Elapsed ()
{
float elapsed;
cudaEventSynchronize(stop);
cudaEventElapsedTime(&elapsed, start, stop);
return elapsed;
}
};
struct GpuTimerWrapper
{
GpuTimer timer;
GpuTimerWrapper ()
{
timer.Start();
}
~GpuTimerWrapper ()
{
timer.Stop();
printf("Time elapsed = %g ms\n", timer.Elapsed());
}
};
void print_array (int *array, int size)
{
printf("{");
for (int i = 0; i < size; i++) { printf("%d ", array[i]); }
printf("}\n");
}
__global__ void increment_atomic (int *g)
{
// which thread is this?
int i = blockIdx.x * blockDim.x + threadIdx.x;
// each thread to increment consecutive elements, wrapping at ARRAY_SIZE
i = i % ARRAY_SIZE;
atomicAdd(& g[i], 1);
}
int main ()
{
//GpuTimer timer;
printf("%d total threads in %d blocks writing into %d array elements\n",
NUM_THREADS, NUM_THREADS / BLOCK_WIDTH, ARRAY_SIZE);
// declare and allocate host memory
int h_array[ARRAY_SIZE];
const int ARRAY_BYTES = ARRAY_SIZE * sizeof(int);
// declare, allocate, and zero out GPU memory
int * d_array;
// init data in host
cudaMalloc((void **) &d_array, ARRAY_BYTES);
if (d_array == NULL) {
std::cout << "Failed to alloc GPU mem\n";
return -1;
}
cudaMemset((void *) d_array, 0, ARRAY_BYTES);
// launch the kernel - comment out one of these
{
GpuTimerWrapper();
//timer.Start();
increment_atomic<<<NUM_THREADS/BLOCK_WIDTH, BLOCK_WIDTH>>>(d_array);
//timer.Stop();
}
// copy back the array of sums from GPU and print
cudaMemcpy(h_array, d_array, ARRAY_BYTES, cudaMemcpyDeviceToHost);
print_array(h_array, ARRAY_SIZE);
//printf("Time elapsed = %g ms\n", timer.Elapsed());
// free GPU memory allocation and exit
cudaFree(d_array);
return 0;
} | code for sm_80
Function : _Z16increment_atomicPi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ MOV R5, 0x1 ; /* 0x0000000100057802 */
/* 0x000fe20000000f00 */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fc800078e0203 */
/*0060*/ IMAD.HI R2, R0, 0x51eb851f, RZ ; /* 0x51eb851f00027827 */
/* 0x000fca00078e02ff */
/*0070*/ SHF.R.U32.HI R3, RZ, 0x1f, R2 ; /* 0x0000001fff037819 */
/* 0x000fc80000011602 */
/*0080*/ LEA.HI.SX32 R3, R2, R3, 0x1b ; /* 0x0000000302037211 */
/* 0x000fe200078fdaff */
/*0090*/ HFMA2.MMA R2, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff027435 */
/* 0x000fc800000001ff */
/*00a0*/ IMAD R3, R3, -0x64, R0 ; /* 0xffffff9c03037824 */
/* 0x000fcc00078e0200 */
/*00b0*/ IMAD.WIDE R2, R3, R2, c[0x0][0x160] ; /* 0x0000580003027625 */
/* 0x000fca00078e0202 */
/*00c0*/ RED.E.ADD.STRONG.GPU [R2.64], R5 ; /* 0x000000050200798e */
/* 0x000fe2000c10e184 */
/*00d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00e0*/ BRA 0xe0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <cuda.h>
#include <stdio.h>
#include <iostream>
#define NUM_THREADS 1000000
#define ARRAY_SIZE 100
#define BLOCK_WIDTH 1000
struct GpuTimer
{
cudaEvent_t start;
cudaEvent_t stop;
GpuTimer ()
{
cudaEventCreate(&start);
cudaEventCreate(&stop);
}
~GpuTimer ()
{
cudaEventDestroy(start);
cudaEventDestroy(stop);
}
void Start ()
{
cudaEventRecord(start, 0);
}
void Stop ()
{
cudaEventRecord(stop, 0);
}
float Elapsed ()
{
float elapsed;
cudaEventSynchronize(stop);
cudaEventElapsedTime(&elapsed, start, stop);
return elapsed;
}
};
struct GpuTimerWrapper
{
GpuTimer timer;
GpuTimerWrapper ()
{
timer.Start();
}
~GpuTimerWrapper ()
{
timer.Stop();
printf("Time elapsed = %g ms\n", timer.Elapsed());
}
};
void print_array (int *array, int size)
{
printf("{");
for (int i = 0; i < size; i++) { printf("%d ", array[i]); }
printf("}\n");
}
__global__ void increment_atomic (int *g)
{
// which thread is this?
int i = blockIdx.x * blockDim.x + threadIdx.x;
// each thread to increment consecutive elements, wrapping at ARRAY_SIZE
i = i % ARRAY_SIZE;
atomicAdd(& g[i], 1);
}
int main ()
{
//GpuTimer timer;
printf("%d total threads in %d blocks writing into %d array elements\n",
NUM_THREADS, NUM_THREADS / BLOCK_WIDTH, ARRAY_SIZE);
// declare and allocate host memory
int h_array[ARRAY_SIZE];
const int ARRAY_BYTES = ARRAY_SIZE * sizeof(int);
// declare, allocate, and zero out GPU memory
int * d_array;
// init data in host
cudaMalloc((void **) &d_array, ARRAY_BYTES);
if (d_array == NULL) {
std::cout << "Failed to alloc GPU mem\n";
return -1;
}
cudaMemset((void *) d_array, 0, ARRAY_BYTES);
// launch the kernel - comment out one of these
{
GpuTimerWrapper();
//timer.Start();
increment_atomic<<<NUM_THREADS/BLOCK_WIDTH, BLOCK_WIDTH>>>(d_array);
//timer.Stop();
}
// copy back the array of sums from GPU and print
cudaMemcpy(h_array, d_array, ARRAY_BYTES, cudaMemcpyDeviceToHost);
print_array(h_array, ARRAY_SIZE);
//printf("Time elapsed = %g ms\n", timer.Elapsed());
// free GPU memory allocation and exit
cudaFree(d_array);
return 0;
} | .file "tmpxft_000bd518_00000000-6_atomic.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3688:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3688:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "{"
.LC1:
.string "%d "
.LC2:
.string "}\n"
.text
.globl _Z11print_arrayPii
.type _Z11print_arrayPii, @function
_Z11print_arrayPii:
.LFB3684:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
movq %rdi, %r12
movl %esi, %ebp
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
testl %ebp, %ebp
jle .L4
movq %r12, %rbx
movslq %ebp, %rbp
leaq (%r12,%rbp,4), %r12
leaq .LC1(%rip), %rbp
.L5:
movl (%rbx), %edx
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %r12, %rbx
jne .L5
.L4:
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3684:
.size _Z11print_arrayPii, .-_Z11print_arrayPii
.globl _Z36__device_stub__Z16increment_atomicPiPi
.type _Z36__device_stub__Z16increment_atomicPiPi, @function
_Z36__device_stub__Z16increment_atomicPiPi:
.LFB3710:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L12
.L8:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L13
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L12:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z16increment_atomicPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L8
.L13:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3710:
.size _Z36__device_stub__Z16increment_atomicPiPi, .-_Z36__device_stub__Z16increment_atomicPiPi
.globl _Z16increment_atomicPi
.type _Z16increment_atomicPi, @function
_Z16increment_atomicPi:
.LFB3711:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z36__device_stub__Z16increment_atomicPiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3711:
.size _Z16increment_atomicPi, .-_Z16increment_atomicPi
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC3:
.string "%d total threads in %d blocks writing into %d array elements\n"
.section .rodata.str1.1
.LC4:
.string "Failed to alloc GPU mem\n"
.LC5:
.string "Time elapsed = %g ms\n"
.text
.globl main
.type main, @function
main:
.LFB3685:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA3685
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $464, %rsp
.cfi_def_cfa_offset 480
movq %fs:40, %rax
movq %rax, 456(%rsp)
xorl %eax, %eax
movl $100, %r8d
movl $1000, %ecx
movl $1000000, %edx
leaq .LC3(%rip), %rsi
movl $2, %edi
.LEHB0:
call __printf_chk@PLT
leaq 8(%rsp), %rdi
movl $400, %esi
call cudaMalloc@PLT
movq 8(%rsp), %rdi
testq %rdi, %rdi
je .L27
movl $400, %edx
movl $0, %esi
call cudaMemset@PLT
leaq 32(%rsp), %rdi
call cudaEventCreate@PLT
leaq 40(%rsp), %rdi
call cudaEventCreate@PLT
.LEHE0:
movl $0, %esi
movq 32(%rsp), %rdi
.LEHB1:
call cudaEventRecord@PLT
.LEHE1:
jmp .L28
.L27:
leaq .LC4(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
.LEHB2:
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
.LEHE2:
movl $-1, %eax
jmp .L16
.L24:
endbr64
movq %rax, %rbx
movq 32(%rsp), %rdi
call cudaEventDestroy@PLT
movq 40(%rsp), %rdi
call cudaEventDestroy@PLT
movq 456(%rsp), %rax
subq %fs:40, %rax
je .L21
call __stack_chk_fail@PLT
.L21:
movq %rbx, %rdi
.LEHB3:
call _Unwind_Resume@PLT
.LEHE3:
.L28:
movl $0, %esi
movq 40(%rsp), %rdi
call cudaEventRecord@PLT
movq 40(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 20(%rsp), %rdi
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtss2sd 20(%rsp), %xmm0
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 32(%rsp), %rdi
call cudaEventDestroy@PLT
movq 40(%rsp), %rdi
call cudaEventDestroy@PLT
movl $1000, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1000, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 32(%rsp), %rdx
movl $1, %ecx
movq 20(%rsp), %rdi
movl $1, %esi
.LEHB4:
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L29
.L22:
leaq 48(%rsp), %rbx
movl $2, %ecx
movl $400, %edx
movq 8(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movl $100, %esi
movq %rbx, %rdi
call _Z11print_arrayPii
movq 8(%rsp), %rdi
call cudaFree@PLT
movl $0, %eax
.L16:
movq 456(%rsp), %rdx
subq %fs:40, %rdx
jne .L30
addq $464, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L29:
.cfi_restore_state
movq 8(%rsp), %rdi
call _Z36__device_stub__Z16increment_atomicPiPi
.LEHE4:
jmp .L22
.L30:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3685:
.globl __gxx_personality_v0
.section .gcc_except_table,"a",@progbits
.LLSDA3685:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE3685-.LLSDACSB3685
.LLSDACSB3685:
.uleb128 .LEHB0-.LFB3685
.uleb128 .LEHE0-.LEHB0
.uleb128 0
.uleb128 0
.uleb128 .LEHB1-.LFB3685
.uleb128 .LEHE1-.LEHB1
.uleb128 .L24-.LFB3685
.uleb128 0
.uleb128 .LEHB2-.LFB3685
.uleb128 .LEHE2-.LEHB2
.uleb128 0
.uleb128 0
.uleb128 .LEHB3-.LFB3685
.uleb128 .LEHE3-.LEHB3
.uleb128 0
.uleb128 0
.uleb128 .LEHB4-.LFB3685
.uleb128 .LEHE4-.LEHB4
.uleb128 0
.uleb128 0
.LLSDACSE3685:
.text
.size main, .-main
.section .rodata.str1.1
.LC6:
.string "_Z16increment_atomicPi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3713:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _Z16increment_atomicPi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3713:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.hidden DW.ref.__gxx_personality_v0
.weak DW.ref.__gxx_personality_v0
.section .data.rel.local.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat
.align 8
.type DW.ref.__gxx_personality_v0, @object
.size DW.ref.__gxx_personality_v0, 8
DW.ref.__gxx_personality_v0:
.quad __gxx_personality_v0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <cuda.h>
#include <stdio.h>
#include <iostream>
#define NUM_THREADS 1000000
#define ARRAY_SIZE 100
#define BLOCK_WIDTH 1000
struct GpuTimer
{
cudaEvent_t start;
cudaEvent_t stop;
GpuTimer ()
{
cudaEventCreate(&start);
cudaEventCreate(&stop);
}
~GpuTimer ()
{
cudaEventDestroy(start);
cudaEventDestroy(stop);
}
void Start ()
{
cudaEventRecord(start, 0);
}
void Stop ()
{
cudaEventRecord(stop, 0);
}
float Elapsed ()
{
float elapsed;
cudaEventSynchronize(stop);
cudaEventElapsedTime(&elapsed, start, stop);
return elapsed;
}
};
struct GpuTimerWrapper
{
GpuTimer timer;
GpuTimerWrapper ()
{
timer.Start();
}
~GpuTimerWrapper ()
{
timer.Stop();
printf("Time elapsed = %g ms\n", timer.Elapsed());
}
};
void print_array (int *array, int size)
{
printf("{");
for (int i = 0; i < size; i++) { printf("%d ", array[i]); }
printf("}\n");
}
__global__ void increment_atomic (int *g)
{
// which thread is this?
int i = blockIdx.x * blockDim.x + threadIdx.x;
// each thread to increment consecutive elements, wrapping at ARRAY_SIZE
i = i % ARRAY_SIZE;
atomicAdd(& g[i], 1);
}
int main ()
{
//GpuTimer timer;
printf("%d total threads in %d blocks writing into %d array elements\n",
NUM_THREADS, NUM_THREADS / BLOCK_WIDTH, ARRAY_SIZE);
// declare and allocate host memory
int h_array[ARRAY_SIZE];
const int ARRAY_BYTES = ARRAY_SIZE * sizeof(int);
// declare, allocate, and zero out GPU memory
int * d_array;
// init data in host
cudaMalloc((void **) &d_array, ARRAY_BYTES);
if (d_array == NULL) {
std::cout << "Failed to alloc GPU mem\n";
return -1;
}
cudaMemset((void *) d_array, 0, ARRAY_BYTES);
// launch the kernel - comment out one of these
{
GpuTimerWrapper();
//timer.Start();
increment_atomic<<<NUM_THREADS/BLOCK_WIDTH, BLOCK_WIDTH>>>(d_array);
//timer.Stop();
}
// copy back the array of sums from GPU and print
cudaMemcpy(h_array, d_array, ARRAY_BYTES, cudaMemcpyDeviceToHost);
print_array(h_array, ARRAY_SIZE);
//printf("Time elapsed = %g ms\n", timer.Elapsed());
// free GPU memory allocation and exit
cudaFree(d_array);
return 0;
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <iostream>
#define NUM_THREADS 1000000
#define ARRAY_SIZE 100
#define BLOCK_WIDTH 1000
struct GpuTimer
{
hipEvent_t start;
hipEvent_t stop;
GpuTimer ()
{
hipEventCreate(&start);
hipEventCreate(&stop);
}
~GpuTimer ()
{
hipEventDestroy(start);
hipEventDestroy(stop);
}
void Start ()
{
hipEventRecord(start, 0);
}
void Stop ()
{
hipEventRecord(stop, 0);
}
float Elapsed ()
{
float elapsed;
hipEventSynchronize(stop);
hipEventElapsedTime(&elapsed, start, stop);
return elapsed;
}
};
struct GpuTimerWrapper
{
GpuTimer timer;
GpuTimerWrapper ()
{
timer.Start();
}
~GpuTimerWrapper ()
{
timer.Stop();
printf("Time elapsed = %g ms\n", timer.Elapsed());
}
};
void print_array (int *array, int size)
{
printf("{");
for (int i = 0; i < size; i++) { printf("%d ", array[i]); }
printf("}\n");
}
__global__ void increment_atomic (int *g)
{
// which thread is this?
int i = blockIdx.x * blockDim.x + threadIdx.x;
// each thread to increment consecutive elements, wrapping at ARRAY_SIZE
i = i % ARRAY_SIZE;
atomicAdd(& g[i], 1);
}
int main ()
{
//GpuTimer timer;
printf("%d total threads in %d blocks writing into %d array elements\n",
NUM_THREADS, NUM_THREADS / BLOCK_WIDTH, ARRAY_SIZE);
// declare and allocate host memory
int h_array[ARRAY_SIZE];
const int ARRAY_BYTES = ARRAY_SIZE * sizeof(int);
// declare, allocate, and zero out GPU memory
int * d_array;
// init data in host
hipMalloc((void **) &d_array, ARRAY_BYTES);
if (d_array == NULL) {
std::cout << "Failed to alloc GPU mem\n";
return -1;
}
hipMemset((void *) d_array, 0, ARRAY_BYTES);
// launch the kernel - comment out one of these
{
GpuTimerWrapper();
//timer.Start();
increment_atomic<<<NUM_THREADS/BLOCK_WIDTH, BLOCK_WIDTH>>>(d_array);
//timer.Stop();
}
// copy back the array of sums from GPU and print
hipMemcpy(h_array, d_array, ARRAY_BYTES, hipMemcpyDeviceToHost);
print_array(h_array, ARRAY_SIZE);
//printf("Time elapsed = %g ms\n", timer.Elapsed());
// free GPU memory allocation and exit
hipFree(d_array);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <iostream>
#define NUM_THREADS 1000000
#define ARRAY_SIZE 100
#define BLOCK_WIDTH 1000
struct GpuTimer
{
hipEvent_t start;
hipEvent_t stop;
GpuTimer ()
{
hipEventCreate(&start);
hipEventCreate(&stop);
}
~GpuTimer ()
{
hipEventDestroy(start);
hipEventDestroy(stop);
}
void Start ()
{
hipEventRecord(start, 0);
}
void Stop ()
{
hipEventRecord(stop, 0);
}
float Elapsed ()
{
float elapsed;
hipEventSynchronize(stop);
hipEventElapsedTime(&elapsed, start, stop);
return elapsed;
}
};
struct GpuTimerWrapper
{
GpuTimer timer;
GpuTimerWrapper ()
{
timer.Start();
}
~GpuTimerWrapper ()
{
timer.Stop();
printf("Time elapsed = %g ms\n", timer.Elapsed());
}
};
void print_array (int *array, int size)
{
printf("{");
for (int i = 0; i < size; i++) { printf("%d ", array[i]); }
printf("}\n");
}
__global__ void increment_atomic (int *g)
{
// which thread is this?
int i = blockIdx.x * blockDim.x + threadIdx.x;
// each thread to increment consecutive elements, wrapping at ARRAY_SIZE
i = i % ARRAY_SIZE;
atomicAdd(& g[i], 1);
}
int main ()
{
//GpuTimer timer;
printf("%d total threads in %d blocks writing into %d array elements\n",
NUM_THREADS, NUM_THREADS / BLOCK_WIDTH, ARRAY_SIZE);
// declare and allocate host memory
int h_array[ARRAY_SIZE];
const int ARRAY_BYTES = ARRAY_SIZE * sizeof(int);
// declare, allocate, and zero out GPU memory
int * d_array;
// init data in host
hipMalloc((void **) &d_array, ARRAY_BYTES);
if (d_array == NULL) {
std::cout << "Failed to alloc GPU mem\n";
return -1;
}
hipMemset((void *) d_array, 0, ARRAY_BYTES);
// launch the kernel - comment out one of these
{
GpuTimerWrapper();
//timer.Start();
increment_atomic<<<NUM_THREADS/BLOCK_WIDTH, BLOCK_WIDTH>>>(d_array);
//timer.Stop();
}
// copy back the array of sums from GPU and print
hipMemcpy(h_array, d_array, ARRAY_BYTES, hipMemcpyDeviceToHost);
print_array(h_array, ARRAY_SIZE);
//printf("Time elapsed = %g ms\n", timer.Elapsed());
// free GPU memory allocation and exit
hipFree(d_array);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z16increment_atomicPi
.globl _Z16increment_atomicPi
.p2align 8
.type _Z16increment_atomicPi,@function
_Z16increment_atomicPi:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x14
s_load_b64 s[0:1], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_mul_hi_i32 v0, v1, 0x51eb851f
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshrrev_b32_e32 v2, 31, v0
v_ashrrev_i32_e32 v0, 5, v0
v_add_nc_u32_e32 v0, v0, v2
v_mov_b32_e32 v2, 1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v0, v0, 0x64
v_sub_nc_u32_e32 v0, v1, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_atomic_add_u32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z16increment_atomicPi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 264
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z16increment_atomicPi, .Lfunc_end0-_Z16increment_atomicPi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: hidden_block_count_x
- .offset: 12
.size: 4
.value_kind: hidden_block_count_y
- .offset: 16
.size: 4
.value_kind: hidden_block_count_z
- .offset: 20
.size: 2
.value_kind: hidden_group_size_x
- .offset: 22
.size: 2
.value_kind: hidden_group_size_y
- .offset: 24
.size: 2
.value_kind: hidden_group_size_z
- .offset: 26
.size: 2
.value_kind: hidden_remainder_x
- .offset: 28
.size: 2
.value_kind: hidden_remainder_y
- .offset: 30
.size: 2
.value_kind: hidden_remainder_z
- .offset: 48
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 72
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 264
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z16increment_atomicPi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z16increment_atomicPi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <iostream>
#define NUM_THREADS 1000000
#define ARRAY_SIZE 100
#define BLOCK_WIDTH 1000
struct GpuTimer
{
hipEvent_t start;
hipEvent_t stop;
GpuTimer ()
{
hipEventCreate(&start);
hipEventCreate(&stop);
}
~GpuTimer ()
{
hipEventDestroy(start);
hipEventDestroy(stop);
}
void Start ()
{
hipEventRecord(start, 0);
}
void Stop ()
{
hipEventRecord(stop, 0);
}
float Elapsed ()
{
float elapsed;
hipEventSynchronize(stop);
hipEventElapsedTime(&elapsed, start, stop);
return elapsed;
}
};
struct GpuTimerWrapper
{
GpuTimer timer;
GpuTimerWrapper ()
{
timer.Start();
}
~GpuTimerWrapper ()
{
timer.Stop();
printf("Time elapsed = %g ms\n", timer.Elapsed());
}
};
void print_array (int *array, int size)
{
printf("{");
for (int i = 0; i < size; i++) { printf("%d ", array[i]); }
printf("}\n");
}
__global__ void increment_atomic (int *g)
{
// which thread is this?
int i = blockIdx.x * blockDim.x + threadIdx.x;
// each thread to increment consecutive elements, wrapping at ARRAY_SIZE
i = i % ARRAY_SIZE;
atomicAdd(& g[i], 1);
}
int main ()
{
//GpuTimer timer;
printf("%d total threads in %d blocks writing into %d array elements\n",
NUM_THREADS, NUM_THREADS / BLOCK_WIDTH, ARRAY_SIZE);
// declare and allocate host memory
int h_array[ARRAY_SIZE];
const int ARRAY_BYTES = ARRAY_SIZE * sizeof(int);
// declare, allocate, and zero out GPU memory
int * d_array;
// init data in host
hipMalloc((void **) &d_array, ARRAY_BYTES);
if (d_array == NULL) {
std::cout << "Failed to alloc GPU mem\n";
return -1;
}
hipMemset((void *) d_array, 0, ARRAY_BYTES);
// launch the kernel - comment out one of these
{
GpuTimerWrapper();
//timer.Start();
increment_atomic<<<NUM_THREADS/BLOCK_WIDTH, BLOCK_WIDTH>>>(d_array);
//timer.Stop();
}
// copy back the array of sums from GPU and print
hipMemcpy(h_array, d_array, ARRAY_BYTES, hipMemcpyDeviceToHost);
print_array(h_array, ARRAY_SIZE);
//printf("Time elapsed = %g ms\n", timer.Elapsed());
// free GPU memory allocation and exit
hipFree(d_array);
return 0;
} | .text
.file "atomic.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z11print_arrayPii # -- Begin function _Z11print_arrayPii
.p2align 4, 0x90
.type _Z11print_arrayPii,@function
_Z11print_arrayPii: # @_Z11print_arrayPii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
pushq %rax
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %esi, %ebp
movq %rdi, %rbx
movl $123, %edi
callq putchar@PLT
testl %ebp, %ebp
jle .LBB0_3
# %bb.1: # %.lr.ph.preheader
movl %ebp, %r14d
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB0_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl (%rbx,%r15,4), %esi
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
incq %r15
cmpq %r15, %r14
jne .LBB0_2
.LBB0_3: # %._crit_edge
movl $.Lstr, %edi
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
jmp puts@PLT # TAILCALL
.Lfunc_end0:
.size _Z11print_arrayPii, .Lfunc_end0-_Z11print_arrayPii
.cfi_endproc
# -- End function
.globl _Z31__device_stub__increment_atomicPi # -- Begin function _Z31__device_stub__increment_atomicPi
.p2align 4, 0x90
.type _Z31__device_stub__increment_atomicPi,@function
_Z31__device_stub__increment_atomicPi: # @_Z31__device_stub__increment_atomicPi
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z16increment_atomicPi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end1:
.size _Z31__device_stub__increment_atomicPi, .Lfunc_end1-_Z31__device_stub__increment_atomicPi
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.Lfunc_begin0:
.cfi_startproc
.cfi_personality 3, __gxx_personality_v0
.cfi_lsda 3, .Lexception0
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $480, %rsp # imm = 0x1E0
.cfi_def_cfa_offset 496
.cfi_offset %rbx, -16
.cfi_escape 0x2e, 0x00
movl $.L.str.3, %edi
movl $1000000, %esi # imm = 0xF4240
movl $1000, %edx # imm = 0x3E8
movl $100, %ecx
xorl %eax, %eax
callq printf
.cfi_escape 0x2e, 0x00
leaq 8(%rsp), %rdi
movl $400, %esi # imm = 0x190
callq hipMalloc
movq 8(%rsp), %rdi
testq %rdi, %rdi
je .LBB2_1
# %bb.3:
.cfi_escape 0x2e, 0x00
movl $400, %edx # imm = 0x190
xorl %esi, %esi
callq hipMemset
.cfi_escape 0x2e, 0x00
leaq 16(%rsp), %rdi
callq hipEventCreate
leaq 24(%rsp), %rdi
.cfi_escape 0x2e, 0x00
callq hipEventCreate
movq 16(%rsp), %rdi
.Ltmp0:
.cfi_escape 0x2e, 0x00
xorl %esi, %esi
callq hipEventRecord
.Ltmp1:
# %bb.4: # %_ZN15GpuTimerWrapperC2Ev.exit
.cfi_escape 0x2e, 0x00
leaq 16(%rsp), %rdi
callq _ZN15GpuTimerWrapperD2Ev
.cfi_escape 0x2e, 0x00
movabsq $4294968296, %rdi # imm = 0x1000003E8
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_6
# %bb.5:
movq 8(%rsp), %rax
movq %rax, 72(%rsp)
leaq 72(%rsp), %rax
movq %rax, 32(%rsp)
.cfi_escape 0x2e, 0x00
leaq 80(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
.cfi_escape 0x2e, 0x10
leaq 32(%rsp), %r9
movl $_Z16increment_atomicPi, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_6:
movq 8(%rsp), %rsi
.cfi_escape 0x2e, 0x00
leaq 80(%rsp), %rdi
movl $400, %edx # imm = 0x190
movl $2, %ecx
callq hipMemcpy
.cfi_escape 0x2e, 0x00
movl $123, %edi
callq putchar@PLT
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB2_7: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
movl 80(%rsp,%rbx,4), %esi
.cfi_escape 0x2e, 0x00
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
incq %rbx
cmpq $100, %rbx
jne .LBB2_7
# %bb.8: # %_Z11print_arrayPii.exit
.cfi_escape 0x2e, 0x00
movl $.Lstr, %edi
callq puts@PLT
movq 8(%rsp), %rdi
.cfi_escape 0x2e, 0x00
callq hipFree
xorl %eax, %eax
jmp .LBB2_9
.LBB2_1:
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
movl $.L.str.4, %esi
movl $24, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $-1, %eax
.LBB2_9:
addq $480, %rsp # imm = 0x1E0
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.LBB2_2:
.cfi_def_cfa_offset 496
.Ltmp2:
movq %rax, %rbx
.cfi_escape 0x2e, 0x00
leaq 16(%rsp), %rdi
callq _ZN8GpuTimerD2Ev
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
callq _Unwind_Resume@PLT
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
.section .gcc_except_table,"a",@progbits
.p2align 2, 0x0
GCC_except_table2:
.Lexception0:
.byte 255 # @LPStart Encoding = omit
.byte 255 # @TType Encoding = omit
.byte 1 # Call site Encoding = uleb128
.uleb128 .Lcst_end0-.Lcst_begin0
.Lcst_begin0:
.uleb128 .Lfunc_begin0-.Lfunc_begin0 # >> Call Site 1 <<
.uleb128 .Ltmp0-.Lfunc_begin0 # Call between .Lfunc_begin0 and .Ltmp0
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp0-.Lfunc_begin0 # >> Call Site 2 <<
.uleb128 .Ltmp1-.Ltmp0 # Call between .Ltmp0 and .Ltmp1
.uleb128 .Ltmp2-.Lfunc_begin0 # jumps to .Ltmp2
.byte 0 # On action: cleanup
.uleb128 .Ltmp1-.Lfunc_begin0 # >> Call Site 3 <<
.uleb128 .Lfunc_end2-.Ltmp1 # Call between .Ltmp1 and .Lfunc_end2
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.Lcst_end0:
.p2align 2, 0x0
# -- End function
.section .text._ZN15GpuTimerWrapperD2Ev,"axG",@progbits,_ZN15GpuTimerWrapperD2Ev,comdat
.weak _ZN15GpuTimerWrapperD2Ev # -- Begin function _ZN15GpuTimerWrapperD2Ev
.p2align 4, 0x90
.type _ZN15GpuTimerWrapperD2Ev,@function
_ZN15GpuTimerWrapperD2Ev: # @_ZN15GpuTimerWrapperD2Ev
.Lfunc_begin1:
.cfi_startproc
.cfi_personality 3, __gxx_personality_v0
.cfi_lsda 3, .Lexception1
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $16, %rsp
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -16
movq %rdi, %rbx
movq 8(%rdi), %rdi
.Ltmp3:
xorl %esi, %esi
callq hipEventRecord
.Ltmp4:
# %bb.1: # %_ZN8GpuTimer4StopEv.exit
movq 8(%rbx), %rdi
.Ltmp5:
callq hipEventSynchronize
.Ltmp6:
# %bb.2: # %.noexc
movq (%rbx), %rsi
movq 8(%rbx), %rdx
.Ltmp7:
leaq 12(%rsp), %rdi
callq hipEventElapsedTime
.Ltmp8:
# %bb.3: # %_ZN8GpuTimer7ElapsedEv.exit
movss 12(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.5, %edi
movb $1, %al
callq printf
movq (%rbx), %rdi
.Ltmp10:
callq hipEventDestroy
.Ltmp11:
# %bb.4:
movq 8(%rbx), %rdi
.Ltmp12:
callq hipEventDestroy
.Ltmp13:
# %bb.5: # %_ZN8GpuTimerD2Ev.exit
addq $16, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.LBB3_7:
.cfi_def_cfa_offset 32
.Ltmp14:
movq %rax, %rdi
callq __clang_call_terminate
.LBB3_6:
.Ltmp9:
movq %rax, %rdi
callq __clang_call_terminate
.Lfunc_end3:
.size _ZN15GpuTimerWrapperD2Ev, .Lfunc_end3-_ZN15GpuTimerWrapperD2Ev
.cfi_endproc
.section .gcc_except_table._ZN15GpuTimerWrapperD2Ev,"aG",@progbits,_ZN15GpuTimerWrapperD2Ev,comdat
.p2align 2, 0x0
GCC_except_table3:
.Lexception1:
.byte 255 # @LPStart Encoding = omit
.byte 3 # @TType Encoding = udata4
.uleb128 .Lttbase0-.Lttbaseref0
.Lttbaseref0:
.byte 1 # Call site Encoding = uleb128
.uleb128 .Lcst_end1-.Lcst_begin1
.Lcst_begin1:
.uleb128 .Ltmp3-.Lfunc_begin1 # >> Call Site 1 <<
.uleb128 .Ltmp8-.Ltmp3 # Call between .Ltmp3 and .Ltmp8
.uleb128 .Ltmp9-.Lfunc_begin1 # jumps to .Ltmp9
.byte 1 # On action: 1
.uleb128 .Ltmp10-.Lfunc_begin1 # >> Call Site 2 <<
.uleb128 .Ltmp13-.Ltmp10 # Call between .Ltmp10 and .Ltmp13
.uleb128 .Ltmp14-.Lfunc_begin1 # jumps to .Ltmp14
.byte 1 # On action: 1
.Lcst_end1:
.byte 1 # >> Action Record 1 <<
# Catch TypeInfo 1
.byte 0 # No further actions
.p2align 2, 0x0
# >> Catch TypeInfos <<
.long 0 # TypeInfo 1
.Lttbase0:
.p2align 2, 0x0
# -- End function
.section .text._ZN8GpuTimerD2Ev,"axG",@progbits,_ZN8GpuTimerD2Ev,comdat
.weak _ZN8GpuTimerD2Ev # -- Begin function _ZN8GpuTimerD2Ev
.p2align 4, 0x90
.type _ZN8GpuTimerD2Ev,@function
_ZN8GpuTimerD2Ev: # @_ZN8GpuTimerD2Ev
.Lfunc_begin2:
.cfi_startproc
.cfi_personality 3, __gxx_personality_v0
.cfi_lsda 3, .Lexception2
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
movq %rdi, %rbx
movq (%rdi), %rdi
.Ltmp15:
callq hipEventDestroy
.Ltmp16:
# %bb.1:
movq 8(%rbx), %rdi
.Ltmp17:
callq hipEventDestroy
.Ltmp18:
# %bb.2:
popq %rbx
.cfi_def_cfa_offset 8
retq
.LBB4_3:
.cfi_def_cfa_offset 16
.Ltmp19:
movq %rax, %rdi
callq __clang_call_terminate
.Lfunc_end4:
.size _ZN8GpuTimerD2Ev, .Lfunc_end4-_ZN8GpuTimerD2Ev
.cfi_endproc
.section .gcc_except_table._ZN8GpuTimerD2Ev,"aG",@progbits,_ZN8GpuTimerD2Ev,comdat
.p2align 2, 0x0
GCC_except_table4:
.Lexception2:
.byte 255 # @LPStart Encoding = omit
.byte 3 # @TType Encoding = udata4
.uleb128 .Lttbase1-.Lttbaseref1
.Lttbaseref1:
.byte 1 # Call site Encoding = uleb128
.uleb128 .Lcst_end2-.Lcst_begin2
.Lcst_begin2:
.uleb128 .Ltmp15-.Lfunc_begin2 # >> Call Site 1 <<
.uleb128 .Ltmp18-.Ltmp15 # Call between .Ltmp15 and .Ltmp18
.uleb128 .Ltmp19-.Lfunc_begin2 # jumps to .Ltmp19
.byte 1 # On action: 1
.Lcst_end2:
.byte 1 # >> Action Record 1 <<
# Catch TypeInfo 1
.byte 0 # No further actions
.p2align 2, 0x0
# >> Catch TypeInfos <<
.long 0 # TypeInfo 1
.Lttbase1:
.p2align 2, 0x0
# -- End function
.section .text.__clang_call_terminate,"axG",@progbits,__clang_call_terminate,comdat
.hidden __clang_call_terminate # -- Begin function __clang_call_terminate
.weak __clang_call_terminate
.p2align 4, 0x90
.type __clang_call_terminate,@function
__clang_call_terminate: # @__clang_call_terminate
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
callq __cxa_begin_catch
callq _ZSt9terminatev
.Lfunc_end5:
.size __clang_call_terminate, .Lfunc_end5-__clang_call_terminate
.cfi_endproc
# -- End function
.text
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB6_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB6_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z16increment_atomicPi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end6:
.size __hip_module_ctor, .Lfunc_end6-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB7_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB7_2:
retq
.Lfunc_end7:
.size __hip_module_dtor, .Lfunc_end7-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "%d "
.size .L.str.1, 4
.type _Z16increment_atomicPi,@object # @_Z16increment_atomicPi
.section .rodata,"a",@progbits
.globl _Z16increment_atomicPi
.p2align 3, 0x0
_Z16increment_atomicPi:
.quad _Z31__device_stub__increment_atomicPi
.size _Z16increment_atomicPi, 8
.type .L.str.3,@object # @.str.3
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.3:
.asciz "%d total threads in %d blocks writing into %d array elements\n"
.size .L.str.3, 62
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Failed to alloc GPU mem\n"
.size .L.str.4, 25
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Time elapsed = %g ms\n"
.size .L.str.5, 22
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z16increment_atomicPi"
.size .L__unnamed_1, 23
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "}"
.size .Lstr, 2
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z31__device_stub__increment_atomicPi
.addrsig_sym __gxx_personality_v0
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Unwind_Resume
.addrsig_sym _Z16increment_atomicPi
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z16increment_atomicPi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ MOV R5, 0x1 ; /* 0x0000000100057802 */
/* 0x000fe20000000f00 */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fc800078e0203 */
/*0060*/ IMAD.HI R2, R0, 0x51eb851f, RZ ; /* 0x51eb851f00027827 */
/* 0x000fca00078e02ff */
/*0070*/ SHF.R.U32.HI R3, RZ, 0x1f, R2 ; /* 0x0000001fff037819 */
/* 0x000fc80000011602 */
/*0080*/ LEA.HI.SX32 R3, R2, R3, 0x1b ; /* 0x0000000302037211 */
/* 0x000fe200078fdaff */
/*0090*/ HFMA2.MMA R2, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff027435 */
/* 0x000fc800000001ff */
/*00a0*/ IMAD R3, R3, -0x64, R0 ; /* 0xffffff9c03037824 */
/* 0x000fcc00078e0200 */
/*00b0*/ IMAD.WIDE R2, R3, R2, c[0x0][0x160] ; /* 0x0000580003027625 */
/* 0x000fca00078e0202 */
/*00c0*/ RED.E.ADD.STRONG.GPU [R2.64], R5 ; /* 0x000000050200798e */
/* 0x000fe2000c10e184 */
/*00d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00e0*/ BRA 0xe0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z16increment_atomicPi
.globl _Z16increment_atomicPi
.p2align 8
.type _Z16increment_atomicPi,@function
_Z16increment_atomicPi:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x14
s_load_b64 s[0:1], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_mul_hi_i32 v0, v1, 0x51eb851f
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshrrev_b32_e32 v2, 31, v0
v_ashrrev_i32_e32 v0, 5, v0
v_add_nc_u32_e32 v0, v0, v2
v_mov_b32_e32 v2, 1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v0, v0, 0x64
v_sub_nc_u32_e32 v0, v1, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_atomic_add_u32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z16increment_atomicPi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 264
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z16increment_atomicPi, .Lfunc_end0-_Z16increment_atomicPi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: hidden_block_count_x
- .offset: 12
.size: 4
.value_kind: hidden_block_count_y
- .offset: 16
.size: 4
.value_kind: hidden_block_count_z
- .offset: 20
.size: 2
.value_kind: hidden_group_size_x
- .offset: 22
.size: 2
.value_kind: hidden_group_size_y
- .offset: 24
.size: 2
.value_kind: hidden_group_size_z
- .offset: 26
.size: 2
.value_kind: hidden_remainder_x
- .offset: 28
.size: 2
.value_kind: hidden_remainder_y
- .offset: 30
.size: 2
.value_kind: hidden_remainder_z
- .offset: 48
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 72
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 264
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z16increment_atomicPi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z16increment_atomicPi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000bd518_00000000-6_atomic.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3688:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3688:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "{"
.LC1:
.string "%d "
.LC2:
.string "}\n"
.text
.globl _Z11print_arrayPii
.type _Z11print_arrayPii, @function
_Z11print_arrayPii:
.LFB3684:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
movq %rdi, %r12
movl %esi, %ebp
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
testl %ebp, %ebp
jle .L4
movq %r12, %rbx
movslq %ebp, %rbp
leaq (%r12,%rbp,4), %r12
leaq .LC1(%rip), %rbp
.L5:
movl (%rbx), %edx
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %r12, %rbx
jne .L5
.L4:
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3684:
.size _Z11print_arrayPii, .-_Z11print_arrayPii
.globl _Z36__device_stub__Z16increment_atomicPiPi
.type _Z36__device_stub__Z16increment_atomicPiPi, @function
_Z36__device_stub__Z16increment_atomicPiPi:
.LFB3710:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L12
.L8:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L13
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L12:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z16increment_atomicPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L8
.L13:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3710:
.size _Z36__device_stub__Z16increment_atomicPiPi, .-_Z36__device_stub__Z16increment_atomicPiPi
.globl _Z16increment_atomicPi
.type _Z16increment_atomicPi, @function
_Z16increment_atomicPi:
.LFB3711:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z36__device_stub__Z16increment_atomicPiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3711:
.size _Z16increment_atomicPi, .-_Z16increment_atomicPi
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC3:
.string "%d total threads in %d blocks writing into %d array elements\n"
.section .rodata.str1.1
.LC4:
.string "Failed to alloc GPU mem\n"
.LC5:
.string "Time elapsed = %g ms\n"
.text
.globl main
.type main, @function
main:
.LFB3685:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA3685
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $464, %rsp
.cfi_def_cfa_offset 480
movq %fs:40, %rax
movq %rax, 456(%rsp)
xorl %eax, %eax
movl $100, %r8d
movl $1000, %ecx
movl $1000000, %edx
leaq .LC3(%rip), %rsi
movl $2, %edi
.LEHB0:
call __printf_chk@PLT
leaq 8(%rsp), %rdi
movl $400, %esi
call cudaMalloc@PLT
movq 8(%rsp), %rdi
testq %rdi, %rdi
je .L27
movl $400, %edx
movl $0, %esi
call cudaMemset@PLT
leaq 32(%rsp), %rdi
call cudaEventCreate@PLT
leaq 40(%rsp), %rdi
call cudaEventCreate@PLT
.LEHE0:
movl $0, %esi
movq 32(%rsp), %rdi
.LEHB1:
call cudaEventRecord@PLT
.LEHE1:
jmp .L28
.L27:
leaq .LC4(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
.LEHB2:
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
.LEHE2:
movl $-1, %eax
jmp .L16
.L24:
endbr64
movq %rax, %rbx
movq 32(%rsp), %rdi
call cudaEventDestroy@PLT
movq 40(%rsp), %rdi
call cudaEventDestroy@PLT
movq 456(%rsp), %rax
subq %fs:40, %rax
je .L21
call __stack_chk_fail@PLT
.L21:
movq %rbx, %rdi
.LEHB3:
call _Unwind_Resume@PLT
.LEHE3:
.L28:
movl $0, %esi
movq 40(%rsp), %rdi
call cudaEventRecord@PLT
movq 40(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 20(%rsp), %rdi
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtss2sd 20(%rsp), %xmm0
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 32(%rsp), %rdi
call cudaEventDestroy@PLT
movq 40(%rsp), %rdi
call cudaEventDestroy@PLT
movl $1000, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1000, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 32(%rsp), %rdx
movl $1, %ecx
movq 20(%rsp), %rdi
movl $1, %esi
.LEHB4:
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L29
.L22:
leaq 48(%rsp), %rbx
movl $2, %ecx
movl $400, %edx
movq 8(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movl $100, %esi
movq %rbx, %rdi
call _Z11print_arrayPii
movq 8(%rsp), %rdi
call cudaFree@PLT
movl $0, %eax
.L16:
movq 456(%rsp), %rdx
subq %fs:40, %rdx
jne .L30
addq $464, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L29:
.cfi_restore_state
movq 8(%rsp), %rdi
call _Z36__device_stub__Z16increment_atomicPiPi
.LEHE4:
jmp .L22
.L30:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3685:
.globl __gxx_personality_v0
.section .gcc_except_table,"a",@progbits
.LLSDA3685:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE3685-.LLSDACSB3685
.LLSDACSB3685:
.uleb128 .LEHB0-.LFB3685
.uleb128 .LEHE0-.LEHB0
.uleb128 0
.uleb128 0
.uleb128 .LEHB1-.LFB3685
.uleb128 .LEHE1-.LEHB1
.uleb128 .L24-.LFB3685
.uleb128 0
.uleb128 .LEHB2-.LFB3685
.uleb128 .LEHE2-.LEHB2
.uleb128 0
.uleb128 0
.uleb128 .LEHB3-.LFB3685
.uleb128 .LEHE3-.LEHB3
.uleb128 0
.uleb128 0
.uleb128 .LEHB4-.LFB3685
.uleb128 .LEHE4-.LEHB4
.uleb128 0
.uleb128 0
.LLSDACSE3685:
.text
.size main, .-main
.section .rodata.str1.1
.LC6:
.string "_Z16increment_atomicPi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3713:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _Z16increment_atomicPi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3713:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.hidden DW.ref.__gxx_personality_v0
.weak DW.ref.__gxx_personality_v0
.section .data.rel.local.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat
.align 8
.type DW.ref.__gxx_personality_v0, @object
.size DW.ref.__gxx_personality_v0, 8
DW.ref.__gxx_personality_v0:
.quad __gxx_personality_v0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "atomic.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z11print_arrayPii # -- Begin function _Z11print_arrayPii
.p2align 4, 0x90
.type _Z11print_arrayPii,@function
_Z11print_arrayPii: # @_Z11print_arrayPii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
pushq %rax
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %esi, %ebp
movq %rdi, %rbx
movl $123, %edi
callq putchar@PLT
testl %ebp, %ebp
jle .LBB0_3
# %bb.1: # %.lr.ph.preheader
movl %ebp, %r14d
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB0_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl (%rbx,%r15,4), %esi
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
incq %r15
cmpq %r15, %r14
jne .LBB0_2
.LBB0_3: # %._crit_edge
movl $.Lstr, %edi
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
jmp puts@PLT # TAILCALL
.Lfunc_end0:
.size _Z11print_arrayPii, .Lfunc_end0-_Z11print_arrayPii
.cfi_endproc
# -- End function
.globl _Z31__device_stub__increment_atomicPi # -- Begin function _Z31__device_stub__increment_atomicPi
.p2align 4, 0x90
.type _Z31__device_stub__increment_atomicPi,@function
_Z31__device_stub__increment_atomicPi: # @_Z31__device_stub__increment_atomicPi
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z16increment_atomicPi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end1:
.size _Z31__device_stub__increment_atomicPi, .Lfunc_end1-_Z31__device_stub__increment_atomicPi
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.Lfunc_begin0:
.cfi_startproc
.cfi_personality 3, __gxx_personality_v0
.cfi_lsda 3, .Lexception0
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $480, %rsp # imm = 0x1E0
.cfi_def_cfa_offset 496
.cfi_offset %rbx, -16
.cfi_escape 0x2e, 0x00
movl $.L.str.3, %edi
movl $1000000, %esi # imm = 0xF4240
movl $1000, %edx # imm = 0x3E8
movl $100, %ecx
xorl %eax, %eax
callq printf
.cfi_escape 0x2e, 0x00
leaq 8(%rsp), %rdi
movl $400, %esi # imm = 0x190
callq hipMalloc
movq 8(%rsp), %rdi
testq %rdi, %rdi
je .LBB2_1
# %bb.3:
.cfi_escape 0x2e, 0x00
movl $400, %edx # imm = 0x190
xorl %esi, %esi
callq hipMemset
.cfi_escape 0x2e, 0x00
leaq 16(%rsp), %rdi
callq hipEventCreate
leaq 24(%rsp), %rdi
.cfi_escape 0x2e, 0x00
callq hipEventCreate
movq 16(%rsp), %rdi
.Ltmp0:
.cfi_escape 0x2e, 0x00
xorl %esi, %esi
callq hipEventRecord
.Ltmp1:
# %bb.4: # %_ZN15GpuTimerWrapperC2Ev.exit
.cfi_escape 0x2e, 0x00
leaq 16(%rsp), %rdi
callq _ZN15GpuTimerWrapperD2Ev
.cfi_escape 0x2e, 0x00
movabsq $4294968296, %rdi # imm = 0x1000003E8
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_6
# %bb.5:
movq 8(%rsp), %rax
movq %rax, 72(%rsp)
leaq 72(%rsp), %rax
movq %rax, 32(%rsp)
.cfi_escape 0x2e, 0x00
leaq 80(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
.cfi_escape 0x2e, 0x10
leaq 32(%rsp), %r9
movl $_Z16increment_atomicPi, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_6:
movq 8(%rsp), %rsi
.cfi_escape 0x2e, 0x00
leaq 80(%rsp), %rdi
movl $400, %edx # imm = 0x190
movl $2, %ecx
callq hipMemcpy
.cfi_escape 0x2e, 0x00
movl $123, %edi
callq putchar@PLT
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB2_7: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
movl 80(%rsp,%rbx,4), %esi
.cfi_escape 0x2e, 0x00
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
incq %rbx
cmpq $100, %rbx
jne .LBB2_7
# %bb.8: # %_Z11print_arrayPii.exit
.cfi_escape 0x2e, 0x00
movl $.Lstr, %edi
callq puts@PLT
movq 8(%rsp), %rdi
.cfi_escape 0x2e, 0x00
callq hipFree
xorl %eax, %eax
jmp .LBB2_9
.LBB2_1:
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
movl $.L.str.4, %esi
movl $24, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $-1, %eax
.LBB2_9:
addq $480, %rsp # imm = 0x1E0
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.LBB2_2:
.cfi_def_cfa_offset 496
.Ltmp2:
movq %rax, %rbx
.cfi_escape 0x2e, 0x00
leaq 16(%rsp), %rdi
callq _ZN8GpuTimerD2Ev
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
callq _Unwind_Resume@PLT
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
.section .gcc_except_table,"a",@progbits
.p2align 2, 0x0
GCC_except_table2:
.Lexception0:
.byte 255 # @LPStart Encoding = omit
.byte 255 # @TType Encoding = omit
.byte 1 # Call site Encoding = uleb128
.uleb128 .Lcst_end0-.Lcst_begin0
.Lcst_begin0:
.uleb128 .Lfunc_begin0-.Lfunc_begin0 # >> Call Site 1 <<
.uleb128 .Ltmp0-.Lfunc_begin0 # Call between .Lfunc_begin0 and .Ltmp0
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp0-.Lfunc_begin0 # >> Call Site 2 <<
.uleb128 .Ltmp1-.Ltmp0 # Call between .Ltmp0 and .Ltmp1
.uleb128 .Ltmp2-.Lfunc_begin0 # jumps to .Ltmp2
.byte 0 # On action: cleanup
.uleb128 .Ltmp1-.Lfunc_begin0 # >> Call Site 3 <<
.uleb128 .Lfunc_end2-.Ltmp1 # Call between .Ltmp1 and .Lfunc_end2
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.Lcst_end0:
.p2align 2, 0x0
# -- End function
.section .text._ZN15GpuTimerWrapperD2Ev,"axG",@progbits,_ZN15GpuTimerWrapperD2Ev,comdat
.weak _ZN15GpuTimerWrapperD2Ev # -- Begin function _ZN15GpuTimerWrapperD2Ev
.p2align 4, 0x90
.type _ZN15GpuTimerWrapperD2Ev,@function
_ZN15GpuTimerWrapperD2Ev: # @_ZN15GpuTimerWrapperD2Ev
.Lfunc_begin1:
.cfi_startproc
.cfi_personality 3, __gxx_personality_v0
.cfi_lsda 3, .Lexception1
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $16, %rsp
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -16
movq %rdi, %rbx
movq 8(%rdi), %rdi
.Ltmp3:
xorl %esi, %esi
callq hipEventRecord
.Ltmp4:
# %bb.1: # %_ZN8GpuTimer4StopEv.exit
movq 8(%rbx), %rdi
.Ltmp5:
callq hipEventSynchronize
.Ltmp6:
# %bb.2: # %.noexc
movq (%rbx), %rsi
movq 8(%rbx), %rdx
.Ltmp7:
leaq 12(%rsp), %rdi
callq hipEventElapsedTime
.Ltmp8:
# %bb.3: # %_ZN8GpuTimer7ElapsedEv.exit
movss 12(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.5, %edi
movb $1, %al
callq printf
movq (%rbx), %rdi
.Ltmp10:
callq hipEventDestroy
.Ltmp11:
# %bb.4:
movq 8(%rbx), %rdi
.Ltmp12:
callq hipEventDestroy
.Ltmp13:
# %bb.5: # %_ZN8GpuTimerD2Ev.exit
addq $16, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.LBB3_7:
.cfi_def_cfa_offset 32
.Ltmp14:
movq %rax, %rdi
callq __clang_call_terminate
.LBB3_6:
.Ltmp9:
movq %rax, %rdi
callq __clang_call_terminate
.Lfunc_end3:
.size _ZN15GpuTimerWrapperD2Ev, .Lfunc_end3-_ZN15GpuTimerWrapperD2Ev
.cfi_endproc
.section .gcc_except_table._ZN15GpuTimerWrapperD2Ev,"aG",@progbits,_ZN15GpuTimerWrapperD2Ev,comdat
.p2align 2, 0x0
GCC_except_table3:
.Lexception1:
.byte 255 # @LPStart Encoding = omit
.byte 3 # @TType Encoding = udata4
.uleb128 .Lttbase0-.Lttbaseref0
.Lttbaseref0:
.byte 1 # Call site Encoding = uleb128
.uleb128 .Lcst_end1-.Lcst_begin1
.Lcst_begin1:
.uleb128 .Ltmp3-.Lfunc_begin1 # >> Call Site 1 <<
.uleb128 .Ltmp8-.Ltmp3 # Call between .Ltmp3 and .Ltmp8
.uleb128 .Ltmp9-.Lfunc_begin1 # jumps to .Ltmp9
.byte 1 # On action: 1
.uleb128 .Ltmp10-.Lfunc_begin1 # >> Call Site 2 <<
.uleb128 .Ltmp13-.Ltmp10 # Call between .Ltmp10 and .Ltmp13
.uleb128 .Ltmp14-.Lfunc_begin1 # jumps to .Ltmp14
.byte 1 # On action: 1
.Lcst_end1:
.byte 1 # >> Action Record 1 <<
# Catch TypeInfo 1
.byte 0 # No further actions
.p2align 2, 0x0
# >> Catch TypeInfos <<
.long 0 # TypeInfo 1
.Lttbase0:
.p2align 2, 0x0
# -- End function
.section .text._ZN8GpuTimerD2Ev,"axG",@progbits,_ZN8GpuTimerD2Ev,comdat
.weak _ZN8GpuTimerD2Ev # -- Begin function _ZN8GpuTimerD2Ev
.p2align 4, 0x90
.type _ZN8GpuTimerD2Ev,@function
_ZN8GpuTimerD2Ev: # @_ZN8GpuTimerD2Ev
.Lfunc_begin2:
.cfi_startproc
.cfi_personality 3, __gxx_personality_v0
.cfi_lsda 3, .Lexception2
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
movq %rdi, %rbx
movq (%rdi), %rdi
.Ltmp15:
callq hipEventDestroy
.Ltmp16:
# %bb.1:
movq 8(%rbx), %rdi
.Ltmp17:
callq hipEventDestroy
.Ltmp18:
# %bb.2:
popq %rbx
.cfi_def_cfa_offset 8
retq
.LBB4_3:
.cfi_def_cfa_offset 16
.Ltmp19:
movq %rax, %rdi
callq __clang_call_terminate
.Lfunc_end4:
.size _ZN8GpuTimerD2Ev, .Lfunc_end4-_ZN8GpuTimerD2Ev
.cfi_endproc
.section .gcc_except_table._ZN8GpuTimerD2Ev,"aG",@progbits,_ZN8GpuTimerD2Ev,comdat
.p2align 2, 0x0
GCC_except_table4:
.Lexception2:
.byte 255 # @LPStart Encoding = omit
.byte 3 # @TType Encoding = udata4
.uleb128 .Lttbase1-.Lttbaseref1
.Lttbaseref1:
.byte 1 # Call site Encoding = uleb128
.uleb128 .Lcst_end2-.Lcst_begin2
.Lcst_begin2:
.uleb128 .Ltmp15-.Lfunc_begin2 # >> Call Site 1 <<
.uleb128 .Ltmp18-.Ltmp15 # Call between .Ltmp15 and .Ltmp18
.uleb128 .Ltmp19-.Lfunc_begin2 # jumps to .Ltmp19
.byte 1 # On action: 1
.Lcst_end2:
.byte 1 # >> Action Record 1 <<
# Catch TypeInfo 1
.byte 0 # No further actions
.p2align 2, 0x0
# >> Catch TypeInfos <<
.long 0 # TypeInfo 1
.Lttbase1:
.p2align 2, 0x0
# -- End function
.section .text.__clang_call_terminate,"axG",@progbits,__clang_call_terminate,comdat
.hidden __clang_call_terminate # -- Begin function __clang_call_terminate
.weak __clang_call_terminate
.p2align 4, 0x90
.type __clang_call_terminate,@function
__clang_call_terminate: # @__clang_call_terminate
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
callq __cxa_begin_catch
callq _ZSt9terminatev
.Lfunc_end5:
.size __clang_call_terminate, .Lfunc_end5-__clang_call_terminate
.cfi_endproc
# -- End function
.text
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB6_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB6_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z16increment_atomicPi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end6:
.size __hip_module_ctor, .Lfunc_end6-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB7_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB7_2:
retq
.Lfunc_end7:
.size __hip_module_dtor, .Lfunc_end7-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "%d "
.size .L.str.1, 4
.type _Z16increment_atomicPi,@object # @_Z16increment_atomicPi
.section .rodata,"a",@progbits
.globl _Z16increment_atomicPi
.p2align 3, 0x0
_Z16increment_atomicPi:
.quad _Z31__device_stub__increment_atomicPi
.size _Z16increment_atomicPi, 8
.type .L.str.3,@object # @.str.3
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.3:
.asciz "%d total threads in %d blocks writing into %d array elements\n"
.size .L.str.3, 62
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Failed to alloc GPU mem\n"
.size .L.str.4, 25
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Time elapsed = %g ms\n"
.size .L.str.5, 22
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z16increment_atomicPi"
.size .L__unnamed_1, 23
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "}"
.size .Lstr, 2
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z31__device_stub__increment_atomicPi
.addrsig_sym __gxx_personality_v0
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Unwind_Resume
.addrsig_sym _Z16increment_atomicPi
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | __global__ void matching(int *keypoints ,const unsigned char *in, int *allProbablities, int *allIndexList, int *matchingResult , int width, int height, int lenght, int fernNum, int fernSize, int patchLenght){
int index = blockIdx.x * blockDim.x + threadIdx.x;
int patchSize =(int)(patchLenght /2);
int x = keypoints[index*2];
int y = keypoints[index*2+1];
int startX = x - patchSize;
int endX = x + patchSize;
int startY = y - patchSize;
int endY = y + patchSize;
if(startX < 0 ){
startX = 0;
}
if (endX >= width ){
endX = width -1;
}
if(startY < 0 ){
startY = 0;
}
if (endY >= height){
endY = height -1;
}
int patchHeight = endY - startY;
int patcWidth = endX - endY;
int size = patchHeight*patcWidth;
int patch[1024];
int count = 0;
for(int j= 0; j < patchHeight; j++){
for(int i = startY ; i < endY; i++){
patch[count] = in[startX*height+i];
count++;
}
startX = startX +1;
}
int result[250];
int I1, I2,num, decimalNum, index2;
for(int i = 0; i< fernNum ; i++){
decimalNum = 0;
num = lenght/2;
for(int j = 0; j < fernSize; j++){
index2 = (fernSize*i*2)+(j*2);
I1 = allIndexList[index2];
I2 = allIndexList[index2+1];
if(I1 < size && I2 < size){
if(patch[I1] < patch[I2]){
decimalNum = decimalNum +num;
}
num = num /2;
}
}
for(int j = 0; j< 250; j++){
result[j] = result[j] + logf(allProbablities[j*lenght+decimalNum]);
}
}
num = result[0];
index2 = 0;
for(int k = 1; k < 250; k++){
decimalNum = result[k];
if( decimalNum> num ){
num = decimalNum;
index2 = k;
}
}
matchingResult[index] = index2;
} | .file "tmpxft_000db69b_00000000-6_matching.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z42__device_stub__Z8matchingPiPKhS_S_S_iiiiiiPiPKhS_S_S_iiiiii
.type _Z42__device_stub__Z8matchingPiPKhS_S_S_iiiiiiPiPKhS_S_S_iiiiii, @function
_Z42__device_stub__Z8matchingPiPKhS_S_S_iiiiiiPiPKhS_S_S_iiiiii:
.LFB2051:
.cfi_startproc
endbr64
subq $216, %rsp
.cfi_def_cfa_offset 224
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movq %r8, 8(%rsp)
movl %r9d, 4(%rsp)
movq %fs:40, %rax
movq %rax, 200(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
leaq 4(%rsp), %rax
movq %rax, 152(%rsp)
leaq 224(%rsp), %rax
movq %rax, 160(%rsp)
leaq 232(%rsp), %rax
movq %rax, 168(%rsp)
leaq 240(%rsp), %rax
movq %rax, 176(%rsp)
leaq 248(%rsp), %rax
movq %rax, 184(%rsp)
leaq 256(%rsp), %rax
movq %rax, 192(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 200(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $216, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 232
pushq 56(%rsp)
.cfi_def_cfa_offset 240
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z8matchingPiPKhS_S_S_iiiiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 224
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z42__device_stub__Z8matchingPiPKhS_S_S_iiiiiiPiPKhS_S_S_iiiiii, .-_Z42__device_stub__Z8matchingPiPKhS_S_S_iiiiiiPiPKhS_S_S_iiiiii
.globl _Z8matchingPiPKhS_S_S_iiiiii
.type _Z8matchingPiPKhS_S_S_iiiiii, @function
_Z8matchingPiPKhS_S_S_iiiiii:
.LFB2052:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 40
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 48
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 56
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 64
call _Z42__device_stub__Z8matchingPiPKhS_S_S_iiiiiiPiPKhS_S_S_iiiiii
addq $56, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z8matchingPiPKhS_S_S_iiiiii, .-_Z8matchingPiPKhS_S_S_iiiiii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z8matchingPiPKhS_S_S_iiiiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z8matchingPiPKhS_S_S_iiiiii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | __global__ void matching(int *keypoints ,const unsigned char *in, int *allProbablities, int *allIndexList, int *matchingResult , int width, int height, int lenght, int fernNum, int fernSize, int patchLenght){
int index = blockIdx.x * blockDim.x + threadIdx.x;
int patchSize =(int)(patchLenght /2);
int x = keypoints[index*2];
int y = keypoints[index*2+1];
int startX = x - patchSize;
int endX = x + patchSize;
int startY = y - patchSize;
int endY = y + patchSize;
if(startX < 0 ){
startX = 0;
}
if (endX >= width ){
endX = width -1;
}
if(startY < 0 ){
startY = 0;
}
if (endY >= height){
endY = height -1;
}
int patchHeight = endY - startY;
int patcWidth = endX - endY;
int size = patchHeight*patcWidth;
int patch[1024];
int count = 0;
for(int j= 0; j < patchHeight; j++){
for(int i = startY ; i < endY; i++){
patch[count] = in[startX*height+i];
count++;
}
startX = startX +1;
}
int result[250];
int I1, I2,num, decimalNum, index2;
for(int i = 0; i< fernNum ; i++){
decimalNum = 0;
num = lenght/2;
for(int j = 0; j < fernSize; j++){
index2 = (fernSize*i*2)+(j*2);
I1 = allIndexList[index2];
I2 = allIndexList[index2+1];
if(I1 < size && I2 < size){
if(patch[I1] < patch[I2]){
decimalNum = decimalNum +num;
}
num = num /2;
}
}
for(int j = 0; j< 250; j++){
result[j] = result[j] + logf(allProbablities[j*lenght+decimalNum]);
}
}
num = result[0];
index2 = 0;
for(int k = 1; k < 250; k++){
decimalNum = result[k];
if( decimalNum> num ){
num = decimalNum;
index2 = k;
}
}
matchingResult[index] = index2;
} | #include <hip/hip_runtime.h>
__global__ void matching(int *keypoints ,const unsigned char *in, int *allProbablities, int *allIndexList, int *matchingResult , int width, int height, int lenght, int fernNum, int fernSize, int patchLenght){
int index = blockIdx.x * blockDim.x + threadIdx.x;
int patchSize =(int)(patchLenght /2);
int x = keypoints[index*2];
int y = keypoints[index*2+1];
int startX = x - patchSize;
int endX = x + patchSize;
int startY = y - patchSize;
int endY = y + patchSize;
if(startX < 0 ){
startX = 0;
}
if (endX >= width ){
endX = width -1;
}
if(startY < 0 ){
startY = 0;
}
if (endY >= height){
endY = height -1;
}
int patchHeight = endY - startY;
int patcWidth = endX - endY;
int size = patchHeight*patcWidth;
int patch[1024];
int count = 0;
for(int j= 0; j < patchHeight; j++){
for(int i = startY ; i < endY; i++){
patch[count] = in[startX*height+i];
count++;
}
startX = startX +1;
}
int result[250];
int I1, I2,num, decimalNum, index2;
for(int i = 0; i< fernNum ; i++){
decimalNum = 0;
num = lenght/2;
for(int j = 0; j < fernSize; j++){
index2 = (fernSize*i*2)+(j*2);
I1 = allIndexList[index2];
I2 = allIndexList[index2+1];
if(I1 < size && I2 < size){
if(patch[I1] < patch[I2]){
decimalNum = decimalNum +num;
}
num = num /2;
}
}
for(int j = 0; j< 250; j++){
result[j] = result[j] + logf(allProbablities[j*lenght+decimalNum]);
}
}
num = result[0];
index2 = 0;
for(int k = 1; k < 250; k++){
decimalNum = result[k];
if( decimalNum> num ){
num = decimalNum;
index2 = k;
}
}
matchingResult[index] = index2;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
__global__ void matching(int *keypoints ,const unsigned char *in, int *allProbablities, int *allIndexList, int *matchingResult , int width, int height, int lenght, int fernNum, int fernSize, int patchLenght){
int index = blockIdx.x * blockDim.x + threadIdx.x;
int patchSize =(int)(patchLenght /2);
int x = keypoints[index*2];
int y = keypoints[index*2+1];
int startX = x - patchSize;
int endX = x + patchSize;
int startY = y - patchSize;
int endY = y + patchSize;
if(startX < 0 ){
startX = 0;
}
if (endX >= width ){
endX = width -1;
}
if(startY < 0 ){
startY = 0;
}
if (endY >= height){
endY = height -1;
}
int patchHeight = endY - startY;
int patcWidth = endX - endY;
int size = patchHeight*patcWidth;
int patch[1024];
int count = 0;
for(int j= 0; j < patchHeight; j++){
for(int i = startY ; i < endY; i++){
patch[count] = in[startX*height+i];
count++;
}
startX = startX +1;
}
int result[250];
int I1, I2,num, decimalNum, index2;
for(int i = 0; i< fernNum ; i++){
decimalNum = 0;
num = lenght/2;
for(int j = 0; j < fernSize; j++){
index2 = (fernSize*i*2)+(j*2);
I1 = allIndexList[index2];
I2 = allIndexList[index2+1];
if(I1 < size && I2 < size){
if(patch[I1] < patch[I2]){
decimalNum = decimalNum +num;
}
num = num /2;
}
}
for(int j = 0; j< 250; j++){
result[j] = result[j] + logf(allProbablities[j*lenght+decimalNum]);
}
}
num = result[0];
index2 = 0;
for(int k = 1; k < 250; k++){
decimalNum = result[k];
if( decimalNum> num ){
num = decimalNum;
index2 = k;
}
}
matchingResult[index] = index2;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z8matchingPiPKhS_S_S_iiiiii
.globl _Z8matchingPiPKhS_S_S_iiiiii
.p2align 8
.type _Z8matchingPiPKhS_S_S_iiiiii,@function
_Z8matchingPiPKhS_S_S_iiiiii:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x4c
s_load_b32 s7, s[0:1], 0x2c
s_load_b32 s4, s[0:1], 0x3c
s_mov_b32 s9, 0
s_mov_b32 s8, exec_lo
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_load_b64 s[2:3], s[0:1], 0x0
v_lshlrev_b32_e32 v2, 1, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_or_b32_e32 v3, 1, v2
v_ashrrev_i32_e32 v4, 31, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[3:4]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, vcc_lo, s2, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v4, vcc_lo
global_load_b32 v0, v[3:4], off
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s2, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
s_lshr_b32 s2, s4, 31
s_delay_alu instid0(SALU_CYCLE_1)
s_add_i32 s4, s4, s2
global_load_b32 v6, v[2:3], off
s_ashr_i32 s6, s4, 1
s_add_i32 s2, s7, -1
s_waitcnt vmcnt(1)
v_add_nc_u32_e32 v3, s6, v0
v_subrev_nc_u32_e32 v2, s6, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_gt_i32_e32 vcc_lo, s7, v3
v_max_i32_e32 v0, 0, v2
v_cndmask_b32_e32 v7, s2, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v5, v7, v0
v_cmpx_lt_i32_e32 0, v5
s_cbranch_execz .LBB0_7
s_load_b64 s[4:5], s[0:1], 0x8
s_waitcnt vmcnt(0)
v_subrev_nc_u32_e32 v2, s6, v6
v_cmp_gt_i32_e32 vcc_lo, v7, v0
v_mov_b32_e32 v8, 0
s_mov_b32 s10, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_max_i32_e32 v4, 0, v2
v_mad_u64_u32 v[2:3], null, s7, v4, v[0:1]
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_3
.p2align 6
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s11
s_add_i32 s10, s10, 1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v2, s7, v2
v_cmp_ge_i32_e64 s2, s10, v5
s_or_b32 s9, s2, s9
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s9
s_cbranch_execz .LBB0_7
.LBB0_3:
s_and_saveexec_b32 s11, vcc_lo
s_cbranch_execz .LBB0_2
s_delay_alu instid0(VALU_DEP_1)
v_ashrrev_i32_e32 v4, 31, v2
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, s2, s4, v2
v_lshl_add_u32 v9, v8, 2, 16
v_mov_b32_e32 v10, v0
v_add_co_ci_u32_e64 v4, s2, s5, v4, s2
s_mov_b32 s12, 0
.LBB0_5:
global_load_u8 v11, v[3:4], off
v_add_nc_u32_e32 v10, 1, v10
v_add_co_u32 v3, s2, v3, 1
v_add_nc_u32_e32 v8, 1, v8
v_add_co_ci_u32_e64 v4, s2, 0, v4, s2
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_ge_i32_e64 s3, v10, v7
s_or_b32 s12, s3, s12
s_waitcnt vmcnt(0)
scratch_store_b32 v9, v11, off
v_add_nc_u32_e32 v9, 4, v9
s_and_not1_b32 exec_lo, exec_lo, s12
s_cbranch_execnz .LBB0_5
s_or_b32 exec_lo, exec_lo, s12
s_branch .LBB0_2
.LBB0_7:
s_set_inst_prefetch_distance 0x2
s_or_b32 exec_lo, exec_lo, s8
s_load_b32 s11, s[0:1], 0x34
s_mov_b32 s10, 1
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s11, 1
s_cbranch_scc1 .LBB0_17
s_clause 0x2
s_load_b32 s3, s[0:1], 0x28
s_load_b32 s2, s[0:1], 0x30
s_load_b32 s12, s[0:1], 0x38
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v0, s6, v6
s_load_b128 s[4:7], s[0:1], 0x10
s_mov_b32 s14, 1
s_mov_b32 s16, 0
s_waitcnt lgkmcnt(0)
v_cmp_gt_i32_e32 vcc_lo, s3, v0
s_add_i32 s8, s3, -1
s_lshr_b32 s3, s2, 31
v_cndmask_b32_e32 v0, s8, v0, vcc_lo
s_add_i32 s8, s2, s3
s_ashr_i32 s3, s2, 31
s_ashr_i32 s13, s8, 1
s_cmp_gt_i32 s12, 0
v_sub_nc_u32_e32 v0, v0, v7
s_cselect_b32 s15, -1, 0
s_lshl_b32 s17, s12, 1
s_lshl_b64 s[2:3], s[2:3], 2
s_delay_alu instid0(VALU_DEP_1)
v_mul_lo_u32 v0, v5, v0
.LBB0_9:
v_mov_b32_e32 v2, 0
s_and_not1_b32 vcc_lo, exec_lo, s15
s_cbranch_vccnz .LBB0_14
v_mov_b32_e32 v3, s13
s_mov_b32 s8, s14
s_mov_b32 s18, s12
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_12
.p2align 6
.LBB0_11:
s_or_b32 exec_lo, exec_lo, s9
s_add_i32 s18, s18, -1
s_add_i32 s8, s8, 2
s_cmp_eq_u32 s18, 0
s_cbranch_scc1 .LBB0_14
.LBB0_12:
s_add_i32 s20, s8, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_ashr_i32 s21, s20, 31
s_lshl_b64 s[20:21], s[20:21], 2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
s_add_u32 s20, s6, s20
s_addc_u32 s21, s7, s21
s_ashr_i32 s9, s8, 31
s_lshl_b64 s[22:23], s[8:9], 2
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s22, s6, s22
s_addc_u32 s23, s7, s23
s_clause 0x1
s_load_b32 s19, s[20:21], 0x0
s_load_b32 s20, s[22:23], 0x0
s_waitcnt lgkmcnt(0)
s_max_i32 s9, s19, s20
s_delay_alu instid0(SALU_CYCLE_1)
v_cmp_lt_i32_e32 vcc_lo, s9, v0
s_and_saveexec_b32 s9, vcc_lo
s_cbranch_execz .LBB0_11
s_lshl_b32 s19, s19, 2
s_lshl_b32 s20, s20, 2
s_add_i32 s19, s19, 16
s_add_i32 s20, s20, 16
s_clause 0x1
scratch_load_b32 v4, off, s19
scratch_load_b32 v5, off, s20
v_lshrrev_b32_e32 v6, 31, v3
s_waitcnt vmcnt(0)
v_cmp_lt_i32_e32 vcc_lo, v4, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_cndmask_b32 v4, 0, v3 :: v_dual_add_nc_u32 v3, v3, v6
v_add_nc_u32_e32 v2, v4, v2
s_delay_alu instid0(VALU_DEP_2)
v_ashrrev_i32_e32 v3, 1, v3
s_branch .LBB0_11
.LBB0_14:
s_set_inst_prefetch_distance 0x2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
s_mov_b32 s8, 0
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
s_set_inst_prefetch_distance 0x1
.p2align 6
.LBB0_15:
global_load_b32 v4, v[2:3], off
s_add_i32 s9, s8, 0x1010
s_add_i32 s8, s8, 4
scratch_load_b32 v5, off, s9
s_cmpk_eq_i32 s8, 0x3e8
s_waitcnt vmcnt(1)
v_cvt_f32_i32_e32 v4, v4
s_waitcnt vmcnt(0)
v_cvt_f32_i32_e32 v5, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_gt_f32_e32 vcc_lo, 0x800000, v4
v_cndmask_b32_e64 v6, 1.0, 0x4f800000, vcc_lo
v_mul_f32_e32 v4, v4, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_log_f32_e32 v4, v4
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v6, 0x3f317217, v4
v_fma_f32 v7, v4, 0x3f317217, -v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v7, 0x3377d1cf, v4
v_add_f32_e32 v6, v6, v7
v_cndmask_b32_e64 v7, 0, 0x41b17218, vcc_lo
v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v4|
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_cndmask_b32_e32 v4, v4, v6, vcc_lo
v_add_co_u32 v2, vcc_lo, v2, s2
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
v_sub_f32_e32 v4, v4, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v4, v4, v5
v_cvt_i32_f32_e32 v4, v4
scratch_store_b32 off, v4, s9
s_cbranch_scc0 .LBB0_15
s_set_inst_prefetch_distance 0x2
s_add_i32 s16, s16, 1
s_add_i32 s14, s14, s17
s_cmp_eq_u32 s16, s11
s_cbranch_scc0 .LBB0_9
.LBB0_17:
s_movk_i32 s2, 0x1010
v_or_b32_e64 v3, 0x1010, 4
scratch_load_b32 v2, off, s2
v_mov_b32_e32 v0, 0
.LBB0_18:
scratch_load_b32 v4, v3, off
v_add_nc_u32_e32 v3, 4, v3
s_waitcnt vmcnt(0)
v_cmp_gt_i32_e32 vcc_lo, v4, v2
v_max_i32_e32 v2, v4, v2
v_cndmask_b32_e64 v0, v0, s10, vcc_lo
s_add_i32 s10, s10, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmpk_eq_i32 s10, 0xfa
s_cbranch_scc0 .LBB0_18
s_load_b64 s[0:1], s[0:1], 0x20
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v1, vcc_lo, s0, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
global_store_b32 v[1:2], v0, off
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8matchingPiPKhS_S_S_iiiiii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 5120
.amdhsa_kernarg_size 320
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 1
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 12
.amdhsa_next_free_sgpr 24
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z8matchingPiPKhS_S_S_iiiiii, .Lfunc_end0-_Z8matchingPiPKhS_S_S_iiiiii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .offset: 40
.size: 4
.value_kind: by_value
- .offset: 44
.size: 4
.value_kind: by_value
- .offset: 48
.size: 4
.value_kind: by_value
- .offset: 52
.size: 4
.value_kind: by_value
- .offset: 56
.size: 4
.value_kind: by_value
- .offset: 60
.size: 4
.value_kind: by_value
- .offset: 64
.size: 4
.value_kind: hidden_block_count_x
- .offset: 68
.size: 4
.value_kind: hidden_block_count_y
- .offset: 72
.size: 4
.value_kind: hidden_block_count_z
- .offset: 76
.size: 2
.value_kind: hidden_group_size_x
- .offset: 78
.size: 2
.value_kind: hidden_group_size_y
- .offset: 80
.size: 2
.value_kind: hidden_group_size_z
- .offset: 82
.size: 2
.value_kind: hidden_remainder_x
- .offset: 84
.size: 2
.value_kind: hidden_remainder_y
- .offset: 86
.size: 2
.value_kind: hidden_remainder_z
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 112
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 120
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 128
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 320
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8matchingPiPKhS_S_S_iiiiii
.private_segment_fixed_size: 5120
.sgpr_count: 26
.sgpr_spill_count: 0
.symbol: _Z8matchingPiPKhS_S_S_iiiiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 12
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
__global__ void matching(int *keypoints ,const unsigned char *in, int *allProbablities, int *allIndexList, int *matchingResult , int width, int height, int lenght, int fernNum, int fernSize, int patchLenght){
int index = blockIdx.x * blockDim.x + threadIdx.x;
int patchSize =(int)(patchLenght /2);
int x = keypoints[index*2];
int y = keypoints[index*2+1];
int startX = x - patchSize;
int endX = x + patchSize;
int startY = y - patchSize;
int endY = y + patchSize;
if(startX < 0 ){
startX = 0;
}
if (endX >= width ){
endX = width -1;
}
if(startY < 0 ){
startY = 0;
}
if (endY >= height){
endY = height -1;
}
int patchHeight = endY - startY;
int patcWidth = endX - endY;
int size = patchHeight*patcWidth;
int patch[1024];
int count = 0;
for(int j= 0; j < patchHeight; j++){
for(int i = startY ; i < endY; i++){
patch[count] = in[startX*height+i];
count++;
}
startX = startX +1;
}
int result[250];
int I1, I2,num, decimalNum, index2;
for(int i = 0; i< fernNum ; i++){
decimalNum = 0;
num = lenght/2;
for(int j = 0; j < fernSize; j++){
index2 = (fernSize*i*2)+(j*2);
I1 = allIndexList[index2];
I2 = allIndexList[index2+1];
if(I1 < size && I2 < size){
if(patch[I1] < patch[I2]){
decimalNum = decimalNum +num;
}
num = num /2;
}
}
for(int j = 0; j< 250; j++){
result[j] = result[j] + logf(allProbablities[j*lenght+decimalNum]);
}
}
num = result[0];
index2 = 0;
for(int k = 1; k < 250; k++){
decimalNum = result[k];
if( decimalNum> num ){
num = decimalNum;
index2 = k;
}
}
matchingResult[index] = index2;
} | .text
.file "matching.hip"
.globl _Z23__device_stub__matchingPiPKhS_S_S_iiiiii # -- Begin function _Z23__device_stub__matchingPiPKhS_S_S_iiiiii
.p2align 4, 0x90
.type _Z23__device_stub__matchingPiPKhS_S_S_iiiiii,@function
_Z23__device_stub__matchingPiPKhS_S_S_iiiiii: # @_Z23__device_stub__matchingPiPKhS_S_S_iiiiii
.cfi_startproc
# %bb.0:
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
movl %r9d, 4(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 4(%rsp), %rax
movq %rax, 136(%rsp)
leaq 192(%rsp), %rax
movq %rax, 144(%rsp)
leaq 200(%rsp), %rax
movq %rax, 152(%rsp)
leaq 208(%rsp), %rax
movq %rax, 160(%rsp)
leaq 216(%rsp), %rax
movq %rax, 168(%rsp)
leaq 224(%rsp), %rax
movq %rax, 176(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z8matchingPiPKhS_S_S_iiiiii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $200, %rsp
.cfi_adjust_cfa_offset -200
retq
.Lfunc_end0:
.size _Z23__device_stub__matchingPiPKhS_S_S_iiiiii, .Lfunc_end0-_Z23__device_stub__matchingPiPKhS_S_S_iiiiii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8matchingPiPKhS_S_S_iiiiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z8matchingPiPKhS_S_S_iiiiii,@object # @_Z8matchingPiPKhS_S_S_iiiiii
.section .rodata,"a",@progbits
.globl _Z8matchingPiPKhS_S_S_iiiiii
.p2align 3, 0x0
_Z8matchingPiPKhS_S_S_iiiiii:
.quad _Z23__device_stub__matchingPiPKhS_S_S_iiiiii
.size _Z8matchingPiPKhS_S_S_iiiiii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z8matchingPiPKhS_S_S_iiiiii"
.size .L__unnamed_1, 29
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__matchingPiPKhS_S_S_iiiiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8matchingPiPKhS_S_S_iiiiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000db69b_00000000-6_matching.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z42__device_stub__Z8matchingPiPKhS_S_S_iiiiiiPiPKhS_S_S_iiiiii
.type _Z42__device_stub__Z8matchingPiPKhS_S_S_iiiiiiPiPKhS_S_S_iiiiii, @function
_Z42__device_stub__Z8matchingPiPKhS_S_S_iiiiiiPiPKhS_S_S_iiiiii:
.LFB2051:
.cfi_startproc
endbr64
subq $216, %rsp
.cfi_def_cfa_offset 224
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movq %r8, 8(%rsp)
movl %r9d, 4(%rsp)
movq %fs:40, %rax
movq %rax, 200(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
leaq 4(%rsp), %rax
movq %rax, 152(%rsp)
leaq 224(%rsp), %rax
movq %rax, 160(%rsp)
leaq 232(%rsp), %rax
movq %rax, 168(%rsp)
leaq 240(%rsp), %rax
movq %rax, 176(%rsp)
leaq 248(%rsp), %rax
movq %rax, 184(%rsp)
leaq 256(%rsp), %rax
movq %rax, 192(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 200(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $216, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 232
pushq 56(%rsp)
.cfi_def_cfa_offset 240
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z8matchingPiPKhS_S_S_iiiiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 224
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z42__device_stub__Z8matchingPiPKhS_S_S_iiiiiiPiPKhS_S_S_iiiiii, .-_Z42__device_stub__Z8matchingPiPKhS_S_S_iiiiiiPiPKhS_S_S_iiiiii
.globl _Z8matchingPiPKhS_S_S_iiiiii
.type _Z8matchingPiPKhS_S_S_iiiiii, @function
_Z8matchingPiPKhS_S_S_iiiiii:
.LFB2052:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 40
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 48
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 56
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 64
call _Z42__device_stub__Z8matchingPiPKhS_S_S_iiiiiiPiPKhS_S_S_iiiiii
addq $56, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z8matchingPiPKhS_S_S_iiiiii, .-_Z8matchingPiPKhS_S_S_iiiiii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z8matchingPiPKhS_S_S_iiiiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z8matchingPiPKhS_S_S_iiiiii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "matching.hip"
.globl _Z23__device_stub__matchingPiPKhS_S_S_iiiiii # -- Begin function _Z23__device_stub__matchingPiPKhS_S_S_iiiiii
.p2align 4, 0x90
.type _Z23__device_stub__matchingPiPKhS_S_S_iiiiii,@function
_Z23__device_stub__matchingPiPKhS_S_S_iiiiii: # @_Z23__device_stub__matchingPiPKhS_S_S_iiiiii
.cfi_startproc
# %bb.0:
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
movl %r9d, 4(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 4(%rsp), %rax
movq %rax, 136(%rsp)
leaq 192(%rsp), %rax
movq %rax, 144(%rsp)
leaq 200(%rsp), %rax
movq %rax, 152(%rsp)
leaq 208(%rsp), %rax
movq %rax, 160(%rsp)
leaq 216(%rsp), %rax
movq %rax, 168(%rsp)
leaq 224(%rsp), %rax
movq %rax, 176(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z8matchingPiPKhS_S_S_iiiiii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $200, %rsp
.cfi_adjust_cfa_offset -200
retq
.Lfunc_end0:
.size _Z23__device_stub__matchingPiPKhS_S_S_iiiiii, .Lfunc_end0-_Z23__device_stub__matchingPiPKhS_S_S_iiiiii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8matchingPiPKhS_S_S_iiiiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z8matchingPiPKhS_S_S_iiiiii,@object # @_Z8matchingPiPKhS_S_S_iiiiii
.section .rodata,"a",@progbits
.globl _Z8matchingPiPKhS_S_S_iiiiii
.p2align 3, 0x0
_Z8matchingPiPKhS_S_S_iiiiii:
.quad _Z23__device_stub__matchingPiPKhS_S_S_iiiiii
.size _Z8matchingPiPKhS_S_S_iiiiii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z8matchingPiPKhS_S_S_iiiiii"
.size .L__unnamed_1, 29
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__matchingPiPKhS_S_S_iiiiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8matchingPiPKhS_S_S_iiiiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void ForwardSoftmax(float *Z, int nColsZ, float *sumExp, float *A)
{
int row = threadIdx.x;
int col = blockIdx.x;
atomicAdd(&sumExp[col], exp(Z[row * nColsZ + col]));
__syncthreads();
A[row * nColsZ + col] = exp(Z[row * nColsZ + col]) / sumExp[col];
} | code for sm_80
Function : _Z14ForwardSoftmaxPfiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e220000002100 */
/*0020*/ IMAD.MOV.U32 R8, RZ, RZ, 0x4 ; /* 0x00000004ff087424 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R9, SR_CTAID.X ; /* 0x0000000000097919 */
/* 0x000e240000002500 */
/*0050*/ IMAD R0, R0, c[0x0][0x168], R9 ; /* 0x00005a0000007a24 */
/* 0x001fc800078e0209 */
/*0060*/ IMAD.WIDE R2, R0, R8, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fca00078e0208 */
/*0070*/ LDG.E R4, [R2.64] ; /* 0x0000000402047981 */
/* 0x000ea2000c1e1900 */
/*0080*/ IMAD.MOV.U32 R11, RZ, RZ, 0x3bbb989d ; /* 0x3bbb989dff0b7424 */
/* 0x000fe400078e00ff */
/*0090*/ IMAD.MOV.U32 R10, RZ, RZ, 0x437c0000 ; /* 0x437c0000ff0a7424 */
/* 0x000fe400078e00ff */
/*00a0*/ FFMA.SAT R5, R4, R11, 0.5 ; /* 0x3f00000004057423 */
/* 0x004fc8000000200b */
/*00b0*/ FFMA.RM R5, R5, R10, 12582913 ; /* 0x4b40000105057423 */
/* 0x000fc8000000400a */
/*00c0*/ FADD R7, R5.reuse, -12583039 ; /* 0xcb40007f05077421 */
/* 0x040fe40000000000 */
/*00d0*/ IMAD.SHL.U32 R6, R5, 0x800000, RZ ; /* 0x0080000005067824 */
/* 0x000fe400078e00ff */
/*00e0*/ FFMA R7, R4, 1.4426950216293334961, -R7 ; /* 0x3fb8aa3b04077823 */
/* 0x000fc80000000807 */
/*00f0*/ FFMA R7, R4, 1.925963033500011079e-08, R7 ; /* 0x32a5706004077823 */
/* 0x000fe40000000007 */
/*0100*/ IMAD.WIDE R4, R9, R8, c[0x0][0x170] ; /* 0x00005c0009047625 */
/* 0x000fc800078e0208 */
/*0110*/ MUFU.EX2 R7, R7 ; /* 0x0000000700077308 */
/* 0x000e240000000800 */
/*0120*/ FMUL R9, R6, R7 ; /* 0x0000000706097220 */
/* 0x001fca0000400000 */
/*0130*/ RED.E.ADD.F32.FTZ.RN.STRONG.GPU [R4.64], R9 ; /* 0x000000090400798e */
/* 0x0001e8000c10e784 */
/*0140*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0150*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*0160*/ LDG.E R13, [R4.64] ; /* 0x00000004040d7981 */
/* 0x000ee2000c1e1900 */
/*0170*/ BSSY B0, 0x2b0 ; /* 0x0000013000007945 */
/* 0x000fe20003800000 */
/*0180*/ FFMA.SAT R6, R2, R11, 0.5 ; /* 0x3f00000002067423 */
/* 0x004fc8000000200b */
/*0190*/ FFMA.RM R6, R6, R10, 12582913 ; /* 0x4b40000106067423 */
/* 0x000fe2000000400a */
/*01a0*/ MUFU.RCP R8, R13 ; /* 0x0000000d00087308 */
/* 0x008e660000001000 */
/*01b0*/ FADD R11, R6.reuse, -12583039 ; /* 0xcb40007f060b7421 */
/* 0x040fe40000000000 */
/*01c0*/ IMAD.SHL.U32 R6, R6, 0x800000, RZ ; /* 0x0080000006067824 */
/* 0x000fe400078e00ff */
/*01d0*/ FFMA R11, R2, 1.4426950216293334961, -R11 ; /* 0x3fb8aa3b020b7823 */
/* 0x000fc8000000080b */
/*01e0*/ FFMA R11, R2, 1.925963033500011079e-08, R11 ; /* 0x32a57060020b7823 */
/* 0x000fe4000000000b */
/*01f0*/ FFMA R7, -R13, R8, 1 ; /* 0x3f8000000d077423 */
/* 0x002fc80000000108 */
/*0200*/ MUFU.EX2 R11, R11 ; /* 0x0000000b000b7308 */
/* 0x000e620000000800 */
/*0210*/ FFMA R7, R8, R7, R8 ; /* 0x0000000708077223 */
/* 0x000fe40000000008 */
/*0220*/ FMUL R6, R6, R11 ; /* 0x0000000b06067220 */
/* 0x002fca0000400000 */
/*0230*/ FCHK P0, R6, R13 ; /* 0x0000000d06007302 */
/* 0x000e620000000000 */
/*0240*/ FFMA R2, R6, R7, RZ ; /* 0x0000000706027223 */
/* 0x000fc800000000ff */
/*0250*/ FFMA R3, -R13, R2, R6 ; /* 0x000000020d037223 */
/* 0x000fc80000000106 */
/*0260*/ FFMA R7, R7, R3, R2 ; /* 0x0000000307077223 */
/* 0x000fe20000000002 */
/*0270*/ @!P0 BRA 0x2a0 ; /* 0x0000002000008947 */
/* 0x002fea0003800000 */
/*0280*/ MOV R2, 0x2a0 ; /* 0x000002a000027802 */
/* 0x001fe40000000f00 */
/*0290*/ CALL.REL.NOINC 0x2f0 ; /* 0x0000005000007944 */
/* 0x000fea0003c00000 */
/*02a0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x001fea0003800000 */
/*02b0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fc800078e00ff */
/*02c0*/ IMAD.WIDE R2, R0, R3, c[0x0][0x178] ; /* 0x00005e0000027625 */
/* 0x000fca00078e0203 */
/*02d0*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x000fe2000c101904 */
/*02e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*02f0*/ SHF.R.U32.HI R4, RZ, 0x17, R13.reuse ; /* 0x00000017ff047819 */
/* 0x100fe2000001160d */
/*0300*/ BSSY B1, 0x950 ; /* 0x0000064000017945 */
/* 0x000fe20003800000 */
/*0310*/ SHF.R.U32.HI R3, RZ, 0x17, R6.reuse ; /* 0x00000017ff037819 */
/* 0x100fe20000011606 */
/*0320*/ IMAD.MOV.U32 R5, RZ, RZ, R6 ; /* 0x000000ffff057224 */
/* 0x000fe200078e0006 */
/*0330*/ LOP3.LUT R4, R4, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff04047812 */
/* 0x000fe200078ec0ff */
/*0340*/ IMAD.MOV.U32 R8, RZ, RZ, R13 ; /* 0x000000ffff087224 */
/* 0x000fe200078e000d */
/*0350*/ LOP3.LUT R3, R3, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff03037812 */
/* 0x000fe400078ec0ff */
/*0360*/ IADD3 R10, R4, -0x1, RZ ; /* 0xffffffff040a7810 */
/* 0x000fe40007ffe0ff */
/*0370*/ IADD3 R9, R3, -0x1, RZ ; /* 0xffffffff03097810 */
/* 0x000fc40007ffe0ff */
/*0380*/ ISETP.GT.U32.AND P0, PT, R10, 0xfd, PT ; /* 0x000000fd0a00780c */
/* 0x000fc80003f04070 */
/*0390*/ ISETP.GT.U32.OR P0, PT, R9, 0xfd, P0 ; /* 0x000000fd0900780c */
/* 0x000fda0000704470 */
/*03a0*/ @!P0 IMAD.MOV.U32 R7, RZ, RZ, RZ ; /* 0x000000ffff078224 */
/* 0x000fe200078e00ff */
/*03b0*/ @!P0 BRA 0x530 ; /* 0x0000017000008947 */
/* 0x000fea0003800000 */
/*03c0*/ FSETP.GTU.FTZ.AND P0, PT, |R6|, +INF , PT ; /* 0x7f8000000600780b */
/* 0x000fe40003f1c200 */
/*03d0*/ FSETP.GTU.FTZ.AND P1, PT, |R13|, +INF , PT ; /* 0x7f8000000d00780b */
/* 0x000fc80003f3c200 */
/*03e0*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000703570 */
/*03f0*/ @P0 BRA 0x930 ; /* 0x0000053000000947 */
/* 0x000fea0003800000 */
/*0400*/ LOP3.LUT P0, RZ, R8, 0x7fffffff, R5, 0xc8, !PT ; /* 0x7fffffff08ff7812 */
/* 0x000fda000780c805 */
/*0410*/ @!P0 BRA 0x910 ; /* 0x000004f000008947 */
/* 0x000fea0003800000 */
/*0420*/ FSETP.NEU.FTZ.AND P2, PT, |R6|.reuse, +INF , PT ; /* 0x7f8000000600780b */
/* 0x040fe40003f5d200 */
/*0430*/ FSETP.NEU.FTZ.AND P1, PT, |R13|, +INF , PT ; /* 0x7f8000000d00780b */
/* 0x000fe40003f3d200 */
/*0440*/ FSETP.NEU.FTZ.AND P0, PT, |R6|, +INF , PT ; /* 0x7f8000000600780b */
/* 0x000fd60003f1d200 */
/*0450*/ @!P1 BRA !P2, 0x910 ; /* 0x000004b000009947 */
/* 0x000fea0005000000 */
/*0460*/ LOP3.LUT P2, RZ, R5, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff05ff7812 */
/* 0x000fc8000784c0ff */
/*0470*/ PLOP3.LUT P1, PT, P1, P2, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000f24572 */
/*0480*/ @P1 BRA 0x8f0 ; /* 0x0000046000001947 */
/* 0x000fea0003800000 */
/*0490*/ LOP3.LUT P1, RZ, R8, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff08ff7812 */
/* 0x000fc8000782c0ff */
/*04a0*/ PLOP3.LUT P0, PT, P0, P1, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000702572 */
/*04b0*/ @P0 BRA 0x8c0 ; /* 0x0000040000000947 */
/* 0x000fea0003800000 */
/*04c0*/ ISETP.GE.AND P0, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x000fe40003f06270 */
/*04d0*/ ISETP.GE.AND P1, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fd60003f26270 */
/*04e0*/ @P0 MOV R7, RZ ; /* 0x000000ff00070202 */
/* 0x000fe20000000f00 */
/*04f0*/ @!P0 IMAD.MOV.U32 R7, RZ, RZ, -0x40 ; /* 0xffffffc0ff078424 */
/* 0x000fe400078e00ff */
/*0500*/ @!P0 FFMA R5, R6, 1.84467440737095516160e+19, RZ ; /* 0x5f80000006058823 */
/* 0x000fe400000000ff */
/*0510*/ @!P1 FFMA R8, R13, 1.84467440737095516160e+19, RZ ; /* 0x5f8000000d089823 */
/* 0x000fe200000000ff */
/*0520*/ @!P1 IADD3 R7, R7, 0x40, RZ ; /* 0x0000004007079810 */
/* 0x000fe40007ffe0ff */
/*0530*/ LEA R9, R4, 0xc0800000, 0x17 ; /* 0xc080000004097811 */
/* 0x000fe200078eb8ff */
/*0540*/ BSSY B2, 0x8b0 ; /* 0x0000036000027945 */
/* 0x000fe20003800000 */
/*0550*/ IADD3 R6, R3, -0x7f, RZ ; /* 0xffffff8103067810 */
/* 0x000fc60007ffe0ff */
/*0560*/ IMAD.IADD R9, R8, 0x1, -R9 ; /* 0x0000000108097824 */
/* 0x000fe400078e0a09 */
/*0570*/ IMAD R5, R6.reuse, -0x800000, R5 ; /* 0xff80000006057824 */
/* 0x040fe200078e0205 */
/*0580*/ IADD3 R6, R6, 0x7f, -R4 ; /* 0x0000007f06067810 */
/* 0x000fe20007ffe804 */
/*0590*/ MUFU.RCP R8, R9 ; /* 0x0000000900087308 */
/* 0x000e220000001000 */
/*05a0*/ FADD.FTZ R10, -R9, -RZ ; /* 0x800000ff090a7221 */
/* 0x000fc60000010100 */
/*05b0*/ IMAD.IADD R6, R6, 0x1, R7 ; /* 0x0000000106067824 */
/* 0x000fe400078e0207 */
/*05c0*/ FFMA R3, R8, R10, 1 ; /* 0x3f80000008037423 */
/* 0x001fc8000000000a */
/*05d0*/ FFMA R12, R8, R3, R8 ; /* 0x00000003080c7223 */
/* 0x000fc80000000008 */
/*05e0*/ FFMA R3, R5, R12, RZ ; /* 0x0000000c05037223 */
/* 0x000fc800000000ff */
/*05f0*/ FFMA R8, R10, R3, R5 ; /* 0x000000030a087223 */
/* 0x000fc80000000005 */
/*0600*/ FFMA R11, R12, R8, R3 ; /* 0x000000080c0b7223 */
/* 0x000fc80000000003 */
/*0610*/ FFMA R5, R10, R11, R5 ; /* 0x0000000b0a057223 */
/* 0x000fc80000000005 */
/*0620*/ FFMA R3, R12, R5, R11 ; /* 0x000000050c037223 */
/* 0x000fca000000000b */
/*0630*/ SHF.R.U32.HI R4, RZ, 0x17, R3 ; /* 0x00000017ff047819 */
/* 0x000fc80000011603 */
/*0640*/ LOP3.LUT R4, R4, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff04047812 */
/* 0x000fca00078ec0ff */
/*0650*/ IMAD.IADD R8, R4, 0x1, R6 ; /* 0x0000000104087824 */
/* 0x000fca00078e0206 */
/*0660*/ IADD3 R4, R8, -0x1, RZ ; /* 0xffffffff08047810 */
/* 0x000fc80007ffe0ff */
/*0670*/ ISETP.GE.U32.AND P0, PT, R4, 0xfe, PT ; /* 0x000000fe0400780c */
/* 0x000fda0003f06070 */
/*0680*/ @!P0 BRA 0x890 ; /* 0x0000020000008947 */
/* 0x000fea0003800000 */
/*0690*/ ISETP.GT.AND P0, PT, R8, 0xfe, PT ; /* 0x000000fe0800780c */
/* 0x000fda0003f04270 */
/*06a0*/ @P0 BRA 0x860 ; /* 0x000001b000000947 */
/* 0x000fea0003800000 */
/*06b0*/ ISETP.GE.AND P0, PT, R8, 0x1, PT ; /* 0x000000010800780c */
/* 0x000fda0003f06270 */
/*06c0*/ @P0 BRA 0x8a0 ; /* 0x000001d000000947 */
/* 0x000fea0003800000 */
/*06d0*/ ISETP.GE.AND P0, PT, R8, -0x18, PT ; /* 0xffffffe80800780c */
/* 0x000fe40003f06270 */
/*06e0*/ LOP3.LUT R3, R3, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000003037812 */
/* 0x000fd600078ec0ff */
/*06f0*/ @!P0 BRA 0x8a0 ; /* 0x000001a000008947 */
/* 0x000fea0003800000 */
/*0700*/ FFMA.RZ R4, R12, R5.reuse, R11.reuse ; /* 0x000000050c047223 */
/* 0x180fe2000000c00b */
/*0710*/ IADD3 R7, R8.reuse, 0x20, RZ ; /* 0x0000002008077810 */
/* 0x040fe40007ffe0ff */
/*0720*/ ISETP.NE.AND P2, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fe40003f45270 */
/*0730*/ LOP3.LUT R6, R4, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff04067812 */
/* 0x000fe200078ec0ff */
/*0740*/ FFMA.RP R4, R12, R5.reuse, R11.reuse ; /* 0x000000050c047223 */
/* 0x180fe2000000800b */
/*0750*/ ISETP.NE.AND P1, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fe20003f25270 */
/*0760*/ FFMA.RM R5, R12, R5, R11 ; /* 0x000000050c057223 */
/* 0x000fe2000000400b */
/*0770*/ LOP3.LUT R6, R6, 0x800000, RZ, 0xfc, !PT ; /* 0x0080000006067812 */
/* 0x000fe200078efcff */
/*0780*/ IMAD.MOV R8, RZ, RZ, -R8 ; /* 0x000000ffff087224 */
/* 0x000fc600078e0a08 */
/*0790*/ SHF.L.U32 R7, R6, R7, RZ ; /* 0x0000000706077219 */
/* 0x000fe400000006ff */
/*07a0*/ FSETP.NEU.FTZ.AND P0, PT, R4, R5, PT ; /* 0x000000050400720b */
/* 0x000fe40003f1d000 */
/*07b0*/ SEL R5, R8, RZ, P2 ; /* 0x000000ff08057207 */
/* 0x000fe40001000000 */
/*07c0*/ ISETP.NE.AND P1, PT, R7, RZ, P1 ; /* 0x000000ff0700720c */
/* 0x000fe40000f25270 */
/*07d0*/ SHF.R.U32.HI R5, RZ, R5, R6 ; /* 0x00000005ff057219 */
/* 0x000fe40000011606 */
/*07e0*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc40000703570 */
/*07f0*/ SHF.R.U32.HI R7, RZ, 0x1, R5 ; /* 0x00000001ff077819 */
/* 0x000fe40000011605 */
/*0800*/ SEL R4, RZ, 0x1, !P0 ; /* 0x00000001ff047807 */
/* 0x000fc80004000000 */
/*0810*/ LOP3.LUT R4, R4, 0x1, R7, 0xf8, !PT ; /* 0x0000000104047812 */
/* 0x000fc800078ef807 */
/*0820*/ LOP3.LUT R4, R4, R5, RZ, 0xc0, !PT ; /* 0x0000000504047212 */
/* 0x000fc800078ec0ff */
/*0830*/ IADD3 R4, R7, R4, RZ ; /* 0x0000000407047210 */
/* 0x000fc80007ffe0ff */
/*0840*/ LOP3.LUT R3, R4, R3, RZ, 0xfc, !PT ; /* 0x0000000304037212 */
/* 0x000fe200078efcff */
/*0850*/ BRA 0x8a0 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*0860*/ LOP3.LUT R3, R3, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000003037812 */
/* 0x000fc800078ec0ff */
/*0870*/ LOP3.LUT R3, R3, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000003037812 */
/* 0x000fe200078efcff */
/*0880*/ BRA 0x8a0 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0890*/ IMAD R3, R6, 0x800000, R3 ; /* 0x0080000006037824 */
/* 0x000fe400078e0203 */
/*08a0*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*08b0*/ BRA 0x940 ; /* 0x0000008000007947 */
/* 0x000fea0003800000 */
/*08c0*/ LOP3.LUT R3, R8, 0x80000000, R5, 0x48, !PT ; /* 0x8000000008037812 */
/* 0x000fc800078e4805 */
/*08d0*/ LOP3.LUT R3, R3, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000003037812 */
/* 0x000fe200078efcff */
/*08e0*/ BRA 0x940 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*08f0*/ LOP3.LUT R3, R8, 0x80000000, R5, 0x48, !PT ; /* 0x8000000008037812 */
/* 0x000fe200078e4805 */
/*0900*/ BRA 0x940 ; /* 0x0000003000007947 */
/* 0x000fea0003800000 */
/*0910*/ MUFU.RSQ R3, -QNAN ; /* 0xffc0000000037908 */
/* 0x000e220000001400 */
/*0920*/ BRA 0x940 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0930*/ FADD.FTZ R3, R6, R13 ; /* 0x0000000d06037221 */
/* 0x000fe40000010000 */
/*0940*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0950*/ IMAD.MOV.U32 R7, RZ, RZ, R3 ; /* 0x000000ffff077224 */
/* 0x001fe400078e0003 */
/*0960*/ IMAD.MOV.U32 R3, RZ, RZ, 0x0 ; /* 0x00000000ff037424 */
/* 0x000fc800078e00ff */
/*0970*/ RET.REL.NODEC R2 0x0 ; /* 0xfffff68002007950 */
/* 0x000fea0003c3ffff */
/*0980*/ BRA 0x980; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0990*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void ForwardSoftmax(float *Z, int nColsZ, float *sumExp, float *A)
{
int row = threadIdx.x;
int col = blockIdx.x;
atomicAdd(&sumExp[col], exp(Z[row * nColsZ + col]));
__syncthreads();
A[row * nColsZ + col] = exp(Z[row * nColsZ + col]) / sumExp[col];
} | .file "tmpxft_001727dd_00000000-6_ForwardSoftmax.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z39__device_stub__Z14ForwardSoftmaxPfiS_S_PfiS_S_
.type _Z39__device_stub__Z14ForwardSoftmaxPfiS_S_PfiS_S_, @function
_Z39__device_stub__Z14ForwardSoftmaxPfiS_S_PfiS_S_:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movq %rdx, 8(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z14ForwardSoftmaxPfiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z39__device_stub__Z14ForwardSoftmaxPfiS_S_PfiS_S_, .-_Z39__device_stub__Z14ForwardSoftmaxPfiS_S_PfiS_S_
.globl _Z14ForwardSoftmaxPfiS_S_
.type _Z14ForwardSoftmaxPfiS_S_, @function
_Z14ForwardSoftmaxPfiS_S_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z39__device_stub__Z14ForwardSoftmaxPfiS_S_PfiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z14ForwardSoftmaxPfiS_S_, .-_Z14ForwardSoftmaxPfiS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z14ForwardSoftmaxPfiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z14ForwardSoftmaxPfiS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void ForwardSoftmax(float *Z, int nColsZ, float *sumExp, float *A)
{
int row = threadIdx.x;
int col = blockIdx.x;
atomicAdd(&sumExp[col], exp(Z[row * nColsZ + col]));
__syncthreads();
A[row * nColsZ + col] = exp(Z[row * nColsZ + col]) / sumExp[col];
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void ForwardSoftmax(float *Z, int nColsZ, float *sumExp, float *A)
{
int row = threadIdx.x;
int col = blockIdx.x;
atomicAdd(&sumExp[col], exp(Z[row * nColsZ + col]));
__syncthreads();
A[row * nColsZ + col] = exp(Z[row * nColsZ + col]) / sumExp[col];
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void ForwardSoftmax(float *Z, int nColsZ, float *sumExp, float *A)
{
int row = threadIdx.x;
int col = blockIdx.x;
atomicAdd(&sumExp[col], exp(Z[row * nColsZ + col]));
__syncthreads();
A[row * nColsZ + col] = exp(Z[row * nColsZ + col]) / sumExp[col];
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z14ForwardSoftmaxPfiS_S_
.globl _Z14ForwardSoftmaxPfiS_S_
.p2align 8
.type _Z14ForwardSoftmaxPfiS_S_,@function
_Z14ForwardSoftmaxPfiS_S_:
s_clause 0x1
s_load_b32 s6, s[0:1], 0x8
s_load_b64 s[4:5], s[0:1], 0x0
s_mov_b32 s2, s15
s_mov_b32 s3, exec_lo
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[1:2], null, v0, s6, s[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[3:4], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v3, vcc_lo, s4, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
global_load_b32 v0, v[3:4], off
s_waitcnt vmcnt(0)
v_mul_f32_e32 v5, 0x3fb8aa3b, v0
v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fma_f32 v6, v0, 0x3fb8aa3b, -v5
v_rndne_f32_e32 v7, v5
v_dual_fmamk_f32 v6, v0, 0x32a5705f, v6 :: v_dual_sub_f32 v5, v5, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_f32_e32 v5, v5, v6
v_cvt_i32_f32_e32 v6, v7
v_exp_f32_e32 v5, v5
s_waitcnt_depctr 0xfff
v_ldexp_f32 v5, v5, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_cndmask_b32_e32 v5, 0, v5, vcc_lo
v_cmp_nlt_f32_e32 vcc_lo, 0x42b17218, v0
v_bfrev_b32_e32 v0, 1
v_cndmask_b32_e32 v5, 0x7f800000, v5, vcc_lo
.LBB0_1:
s_ctz_i32_b32 s4, s3
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_readlane_b32 s5, v5, s4
s_lshl_b32 s4, 1, s4
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_not1_b32 s3, s3, s4
s_cmp_lg_u32 s3, 0
s_delay_alu instid0(VALU_DEP_1)
v_add_f32_e32 v0, s5, v0
s_cbranch_scc1 .LBB0_1
s_load_b64 s[4:5], s[0:1], 0x10
s_ashr_i32 s3, s2, 31
v_mbcnt_lo_u32_b32 v5, exec_lo, 0
s_lshl_b64 s[2:3], s[2:3], 2
s_waitcnt lgkmcnt(0)
s_add_u32 s2, s4, s2
s_addc_u32 s3, s5, s3
s_mov_b32 s5, 0
s_mov_b32 s4, exec_lo
v_cmpx_eq_u32_e32 0, v5
s_xor_b32 s4, exec_lo, s4
s_cbranch_execz .LBB0_6
s_load_b32 s6, s[2:3], 0x0
s_waitcnt lgkmcnt(0)
v_dual_mov_b32 v7, 0 :: v_dual_mov_b32 v6, s6
.LBB0_4:
s_delay_alu instid0(VALU_DEP_1)
v_add_f32_e32 v5, v6, v0
global_atomic_cmpswap_b32 v5, v7, v[5:6], s[2:3] glc
s_waitcnt vmcnt(0)
v_cmp_eq_u32_e32 vcc_lo, v5, v6
v_mov_b32_e32 v6, v5
s_or_b32 s5, vcc_lo, s5
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s5
s_cbranch_execnz .LBB0_4
s_or_b32 exec_lo, exec_lo, s5
.LBB0_6:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s4
s_barrier
buffer_gl0_inv
global_load_b32 v0, v[3:4], off
v_mov_b32_e32 v3, 0
s_load_b64 s[0:1], s[0:1], 0x18
s_waitcnt vmcnt(0)
v_mul_f32_e32 v4, 0x3fb8aa3b, v0
global_load_b32 v3, v3, s[2:3]
v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v0
v_rndne_f32_e32 v5, v4
v_fma_f32 v6, v0, 0x3fb8aa3b, -v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_f32_e32 v4, v4, v5
v_fmamk_f32 v6, v0, 0x32a5705f, v6
v_cvt_i32_f32_e32 v5, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v4, v4, v6
v_exp_f32_e32 v4, v4
s_waitcnt_depctr 0xfff
v_ldexp_f32 v4, v4, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v4, 0, v4, vcc_lo
v_cmp_nlt_f32_e32 vcc_lo, 0x42b17218, v0
v_cndmask_b32_e32 v4, 0x7f800000, v4, vcc_lo
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_div_scale_f32 v0, null, v3, v3, v4
v_div_scale_f32 v7, vcc_lo, v4, v3, v4
v_rcp_f32_e32 v5, v0
s_waitcnt_depctr 0xfff
v_fma_f32 v6, -v0, v5, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v5, v6, v5
v_mul_f32_e32 v6, v7, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v8, -v0, v6, v7
v_fmac_f32_e32 v6, v8, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v0, -v0, v6, v7
v_div_fmas_f32 v5, v0, v5, v6
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_div_fixup_f32 v2, v5, v3, v4
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z14ForwardSoftmaxPfiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 32
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z14ForwardSoftmaxPfiS_S_, .Lfunc_end0-_Z14ForwardSoftmaxPfiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 32
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z14ForwardSoftmaxPfiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z14ForwardSoftmaxPfiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void ForwardSoftmax(float *Z, int nColsZ, float *sumExp, float *A)
{
int row = threadIdx.x;
int col = blockIdx.x;
atomicAdd(&sumExp[col], exp(Z[row * nColsZ + col]));
__syncthreads();
A[row * nColsZ + col] = exp(Z[row * nColsZ + col]) / sumExp[col];
} | .text
.file "ForwardSoftmax.hip"
.globl _Z29__device_stub__ForwardSoftmaxPfiS_S_ # -- Begin function _Z29__device_stub__ForwardSoftmaxPfiS_S_
.p2align 4, 0x90
.type _Z29__device_stub__ForwardSoftmaxPfiS_S_,@function
_Z29__device_stub__ForwardSoftmaxPfiS_S_: # @_Z29__device_stub__ForwardSoftmaxPfiS_S_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movl %esi, 4(%rsp)
movq %rdx, 64(%rsp)
movq %rcx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 56(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z14ForwardSoftmaxPfiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z29__device_stub__ForwardSoftmaxPfiS_S_, .Lfunc_end0-_Z29__device_stub__ForwardSoftmaxPfiS_S_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14ForwardSoftmaxPfiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z14ForwardSoftmaxPfiS_S_,@object # @_Z14ForwardSoftmaxPfiS_S_
.section .rodata,"a",@progbits
.globl _Z14ForwardSoftmaxPfiS_S_
.p2align 3, 0x0
_Z14ForwardSoftmaxPfiS_S_:
.quad _Z29__device_stub__ForwardSoftmaxPfiS_S_
.size _Z14ForwardSoftmaxPfiS_S_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z14ForwardSoftmaxPfiS_S_"
.size .L__unnamed_1, 26
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z29__device_stub__ForwardSoftmaxPfiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z14ForwardSoftmaxPfiS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z14ForwardSoftmaxPfiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e220000002100 */
/*0020*/ IMAD.MOV.U32 R8, RZ, RZ, 0x4 ; /* 0x00000004ff087424 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R9, SR_CTAID.X ; /* 0x0000000000097919 */
/* 0x000e240000002500 */
/*0050*/ IMAD R0, R0, c[0x0][0x168], R9 ; /* 0x00005a0000007a24 */
/* 0x001fc800078e0209 */
/*0060*/ IMAD.WIDE R2, R0, R8, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fca00078e0208 */
/*0070*/ LDG.E R4, [R2.64] ; /* 0x0000000402047981 */
/* 0x000ea2000c1e1900 */
/*0080*/ IMAD.MOV.U32 R11, RZ, RZ, 0x3bbb989d ; /* 0x3bbb989dff0b7424 */
/* 0x000fe400078e00ff */
/*0090*/ IMAD.MOV.U32 R10, RZ, RZ, 0x437c0000 ; /* 0x437c0000ff0a7424 */
/* 0x000fe400078e00ff */
/*00a0*/ FFMA.SAT R5, R4, R11, 0.5 ; /* 0x3f00000004057423 */
/* 0x004fc8000000200b */
/*00b0*/ FFMA.RM R5, R5, R10, 12582913 ; /* 0x4b40000105057423 */
/* 0x000fc8000000400a */
/*00c0*/ FADD R7, R5.reuse, -12583039 ; /* 0xcb40007f05077421 */
/* 0x040fe40000000000 */
/*00d0*/ IMAD.SHL.U32 R6, R5, 0x800000, RZ ; /* 0x0080000005067824 */
/* 0x000fe400078e00ff */
/*00e0*/ FFMA R7, R4, 1.4426950216293334961, -R7 ; /* 0x3fb8aa3b04077823 */
/* 0x000fc80000000807 */
/*00f0*/ FFMA R7, R4, 1.925963033500011079e-08, R7 ; /* 0x32a5706004077823 */
/* 0x000fe40000000007 */
/*0100*/ IMAD.WIDE R4, R9, R8, c[0x0][0x170] ; /* 0x00005c0009047625 */
/* 0x000fc800078e0208 */
/*0110*/ MUFU.EX2 R7, R7 ; /* 0x0000000700077308 */
/* 0x000e240000000800 */
/*0120*/ FMUL R9, R6, R7 ; /* 0x0000000706097220 */
/* 0x001fca0000400000 */
/*0130*/ RED.E.ADD.F32.FTZ.RN.STRONG.GPU [R4.64], R9 ; /* 0x000000090400798e */
/* 0x0001e8000c10e784 */
/*0140*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0150*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*0160*/ LDG.E R13, [R4.64] ; /* 0x00000004040d7981 */
/* 0x000ee2000c1e1900 */
/*0170*/ BSSY B0, 0x2b0 ; /* 0x0000013000007945 */
/* 0x000fe20003800000 */
/*0180*/ FFMA.SAT R6, R2, R11, 0.5 ; /* 0x3f00000002067423 */
/* 0x004fc8000000200b */
/*0190*/ FFMA.RM R6, R6, R10, 12582913 ; /* 0x4b40000106067423 */
/* 0x000fe2000000400a */
/*01a0*/ MUFU.RCP R8, R13 ; /* 0x0000000d00087308 */
/* 0x008e660000001000 */
/*01b0*/ FADD R11, R6.reuse, -12583039 ; /* 0xcb40007f060b7421 */
/* 0x040fe40000000000 */
/*01c0*/ IMAD.SHL.U32 R6, R6, 0x800000, RZ ; /* 0x0080000006067824 */
/* 0x000fe400078e00ff */
/*01d0*/ FFMA R11, R2, 1.4426950216293334961, -R11 ; /* 0x3fb8aa3b020b7823 */
/* 0x000fc8000000080b */
/*01e0*/ FFMA R11, R2, 1.925963033500011079e-08, R11 ; /* 0x32a57060020b7823 */
/* 0x000fe4000000000b */
/*01f0*/ FFMA R7, -R13, R8, 1 ; /* 0x3f8000000d077423 */
/* 0x002fc80000000108 */
/*0200*/ MUFU.EX2 R11, R11 ; /* 0x0000000b000b7308 */
/* 0x000e620000000800 */
/*0210*/ FFMA R7, R8, R7, R8 ; /* 0x0000000708077223 */
/* 0x000fe40000000008 */
/*0220*/ FMUL R6, R6, R11 ; /* 0x0000000b06067220 */
/* 0x002fca0000400000 */
/*0230*/ FCHK P0, R6, R13 ; /* 0x0000000d06007302 */
/* 0x000e620000000000 */
/*0240*/ FFMA R2, R6, R7, RZ ; /* 0x0000000706027223 */
/* 0x000fc800000000ff */
/*0250*/ FFMA R3, -R13, R2, R6 ; /* 0x000000020d037223 */
/* 0x000fc80000000106 */
/*0260*/ FFMA R7, R7, R3, R2 ; /* 0x0000000307077223 */
/* 0x000fe20000000002 */
/*0270*/ @!P0 BRA 0x2a0 ; /* 0x0000002000008947 */
/* 0x002fea0003800000 */
/*0280*/ MOV R2, 0x2a0 ; /* 0x000002a000027802 */
/* 0x001fe40000000f00 */
/*0290*/ CALL.REL.NOINC 0x2f0 ; /* 0x0000005000007944 */
/* 0x000fea0003c00000 */
/*02a0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x001fea0003800000 */
/*02b0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fc800078e00ff */
/*02c0*/ IMAD.WIDE R2, R0, R3, c[0x0][0x178] ; /* 0x00005e0000027625 */
/* 0x000fca00078e0203 */
/*02d0*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x000fe2000c101904 */
/*02e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*02f0*/ SHF.R.U32.HI R4, RZ, 0x17, R13.reuse ; /* 0x00000017ff047819 */
/* 0x100fe2000001160d */
/*0300*/ BSSY B1, 0x950 ; /* 0x0000064000017945 */
/* 0x000fe20003800000 */
/*0310*/ SHF.R.U32.HI R3, RZ, 0x17, R6.reuse ; /* 0x00000017ff037819 */
/* 0x100fe20000011606 */
/*0320*/ IMAD.MOV.U32 R5, RZ, RZ, R6 ; /* 0x000000ffff057224 */
/* 0x000fe200078e0006 */
/*0330*/ LOP3.LUT R4, R4, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff04047812 */
/* 0x000fe200078ec0ff */
/*0340*/ IMAD.MOV.U32 R8, RZ, RZ, R13 ; /* 0x000000ffff087224 */
/* 0x000fe200078e000d */
/*0350*/ LOP3.LUT R3, R3, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff03037812 */
/* 0x000fe400078ec0ff */
/*0360*/ IADD3 R10, R4, -0x1, RZ ; /* 0xffffffff040a7810 */
/* 0x000fe40007ffe0ff */
/*0370*/ IADD3 R9, R3, -0x1, RZ ; /* 0xffffffff03097810 */
/* 0x000fc40007ffe0ff */
/*0380*/ ISETP.GT.U32.AND P0, PT, R10, 0xfd, PT ; /* 0x000000fd0a00780c */
/* 0x000fc80003f04070 */
/*0390*/ ISETP.GT.U32.OR P0, PT, R9, 0xfd, P0 ; /* 0x000000fd0900780c */
/* 0x000fda0000704470 */
/*03a0*/ @!P0 IMAD.MOV.U32 R7, RZ, RZ, RZ ; /* 0x000000ffff078224 */
/* 0x000fe200078e00ff */
/*03b0*/ @!P0 BRA 0x530 ; /* 0x0000017000008947 */
/* 0x000fea0003800000 */
/*03c0*/ FSETP.GTU.FTZ.AND P0, PT, |R6|, +INF , PT ; /* 0x7f8000000600780b */
/* 0x000fe40003f1c200 */
/*03d0*/ FSETP.GTU.FTZ.AND P1, PT, |R13|, +INF , PT ; /* 0x7f8000000d00780b */
/* 0x000fc80003f3c200 */
/*03e0*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000703570 */
/*03f0*/ @P0 BRA 0x930 ; /* 0x0000053000000947 */
/* 0x000fea0003800000 */
/*0400*/ LOP3.LUT P0, RZ, R8, 0x7fffffff, R5, 0xc8, !PT ; /* 0x7fffffff08ff7812 */
/* 0x000fda000780c805 */
/*0410*/ @!P0 BRA 0x910 ; /* 0x000004f000008947 */
/* 0x000fea0003800000 */
/*0420*/ FSETP.NEU.FTZ.AND P2, PT, |R6|.reuse, +INF , PT ; /* 0x7f8000000600780b */
/* 0x040fe40003f5d200 */
/*0430*/ FSETP.NEU.FTZ.AND P1, PT, |R13|, +INF , PT ; /* 0x7f8000000d00780b */
/* 0x000fe40003f3d200 */
/*0440*/ FSETP.NEU.FTZ.AND P0, PT, |R6|, +INF , PT ; /* 0x7f8000000600780b */
/* 0x000fd60003f1d200 */
/*0450*/ @!P1 BRA !P2, 0x910 ; /* 0x000004b000009947 */
/* 0x000fea0005000000 */
/*0460*/ LOP3.LUT P2, RZ, R5, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff05ff7812 */
/* 0x000fc8000784c0ff */
/*0470*/ PLOP3.LUT P1, PT, P1, P2, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000f24572 */
/*0480*/ @P1 BRA 0x8f0 ; /* 0x0000046000001947 */
/* 0x000fea0003800000 */
/*0490*/ LOP3.LUT P1, RZ, R8, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff08ff7812 */
/* 0x000fc8000782c0ff */
/*04a0*/ PLOP3.LUT P0, PT, P0, P1, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000702572 */
/*04b0*/ @P0 BRA 0x8c0 ; /* 0x0000040000000947 */
/* 0x000fea0003800000 */
/*04c0*/ ISETP.GE.AND P0, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x000fe40003f06270 */
/*04d0*/ ISETP.GE.AND P1, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fd60003f26270 */
/*04e0*/ @P0 MOV R7, RZ ; /* 0x000000ff00070202 */
/* 0x000fe20000000f00 */
/*04f0*/ @!P0 IMAD.MOV.U32 R7, RZ, RZ, -0x40 ; /* 0xffffffc0ff078424 */
/* 0x000fe400078e00ff */
/*0500*/ @!P0 FFMA R5, R6, 1.84467440737095516160e+19, RZ ; /* 0x5f80000006058823 */
/* 0x000fe400000000ff */
/*0510*/ @!P1 FFMA R8, R13, 1.84467440737095516160e+19, RZ ; /* 0x5f8000000d089823 */
/* 0x000fe200000000ff */
/*0520*/ @!P1 IADD3 R7, R7, 0x40, RZ ; /* 0x0000004007079810 */
/* 0x000fe40007ffe0ff */
/*0530*/ LEA R9, R4, 0xc0800000, 0x17 ; /* 0xc080000004097811 */
/* 0x000fe200078eb8ff */
/*0540*/ BSSY B2, 0x8b0 ; /* 0x0000036000027945 */
/* 0x000fe20003800000 */
/*0550*/ IADD3 R6, R3, -0x7f, RZ ; /* 0xffffff8103067810 */
/* 0x000fc60007ffe0ff */
/*0560*/ IMAD.IADD R9, R8, 0x1, -R9 ; /* 0x0000000108097824 */
/* 0x000fe400078e0a09 */
/*0570*/ IMAD R5, R6.reuse, -0x800000, R5 ; /* 0xff80000006057824 */
/* 0x040fe200078e0205 */
/*0580*/ IADD3 R6, R6, 0x7f, -R4 ; /* 0x0000007f06067810 */
/* 0x000fe20007ffe804 */
/*0590*/ MUFU.RCP R8, R9 ; /* 0x0000000900087308 */
/* 0x000e220000001000 */
/*05a0*/ FADD.FTZ R10, -R9, -RZ ; /* 0x800000ff090a7221 */
/* 0x000fc60000010100 */
/*05b0*/ IMAD.IADD R6, R6, 0x1, R7 ; /* 0x0000000106067824 */
/* 0x000fe400078e0207 */
/*05c0*/ FFMA R3, R8, R10, 1 ; /* 0x3f80000008037423 */
/* 0x001fc8000000000a */
/*05d0*/ FFMA R12, R8, R3, R8 ; /* 0x00000003080c7223 */
/* 0x000fc80000000008 */
/*05e0*/ FFMA R3, R5, R12, RZ ; /* 0x0000000c05037223 */
/* 0x000fc800000000ff */
/*05f0*/ FFMA R8, R10, R3, R5 ; /* 0x000000030a087223 */
/* 0x000fc80000000005 */
/*0600*/ FFMA R11, R12, R8, R3 ; /* 0x000000080c0b7223 */
/* 0x000fc80000000003 */
/*0610*/ FFMA R5, R10, R11, R5 ; /* 0x0000000b0a057223 */
/* 0x000fc80000000005 */
/*0620*/ FFMA R3, R12, R5, R11 ; /* 0x000000050c037223 */
/* 0x000fca000000000b */
/*0630*/ SHF.R.U32.HI R4, RZ, 0x17, R3 ; /* 0x00000017ff047819 */
/* 0x000fc80000011603 */
/*0640*/ LOP3.LUT R4, R4, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff04047812 */
/* 0x000fca00078ec0ff */
/*0650*/ IMAD.IADD R8, R4, 0x1, R6 ; /* 0x0000000104087824 */
/* 0x000fca00078e0206 */
/*0660*/ IADD3 R4, R8, -0x1, RZ ; /* 0xffffffff08047810 */
/* 0x000fc80007ffe0ff */
/*0670*/ ISETP.GE.U32.AND P0, PT, R4, 0xfe, PT ; /* 0x000000fe0400780c */
/* 0x000fda0003f06070 */
/*0680*/ @!P0 BRA 0x890 ; /* 0x0000020000008947 */
/* 0x000fea0003800000 */
/*0690*/ ISETP.GT.AND P0, PT, R8, 0xfe, PT ; /* 0x000000fe0800780c */
/* 0x000fda0003f04270 */
/*06a0*/ @P0 BRA 0x860 ; /* 0x000001b000000947 */
/* 0x000fea0003800000 */
/*06b0*/ ISETP.GE.AND P0, PT, R8, 0x1, PT ; /* 0x000000010800780c */
/* 0x000fda0003f06270 */
/*06c0*/ @P0 BRA 0x8a0 ; /* 0x000001d000000947 */
/* 0x000fea0003800000 */
/*06d0*/ ISETP.GE.AND P0, PT, R8, -0x18, PT ; /* 0xffffffe80800780c */
/* 0x000fe40003f06270 */
/*06e0*/ LOP3.LUT R3, R3, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000003037812 */
/* 0x000fd600078ec0ff */
/*06f0*/ @!P0 BRA 0x8a0 ; /* 0x000001a000008947 */
/* 0x000fea0003800000 */
/*0700*/ FFMA.RZ R4, R12, R5.reuse, R11.reuse ; /* 0x000000050c047223 */
/* 0x180fe2000000c00b */
/*0710*/ IADD3 R7, R8.reuse, 0x20, RZ ; /* 0x0000002008077810 */
/* 0x040fe40007ffe0ff */
/*0720*/ ISETP.NE.AND P2, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fe40003f45270 */
/*0730*/ LOP3.LUT R6, R4, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff04067812 */
/* 0x000fe200078ec0ff */
/*0740*/ FFMA.RP R4, R12, R5.reuse, R11.reuse ; /* 0x000000050c047223 */
/* 0x180fe2000000800b */
/*0750*/ ISETP.NE.AND P1, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fe20003f25270 */
/*0760*/ FFMA.RM R5, R12, R5, R11 ; /* 0x000000050c057223 */
/* 0x000fe2000000400b */
/*0770*/ LOP3.LUT R6, R6, 0x800000, RZ, 0xfc, !PT ; /* 0x0080000006067812 */
/* 0x000fe200078efcff */
/*0780*/ IMAD.MOV R8, RZ, RZ, -R8 ; /* 0x000000ffff087224 */
/* 0x000fc600078e0a08 */
/*0790*/ SHF.L.U32 R7, R6, R7, RZ ; /* 0x0000000706077219 */
/* 0x000fe400000006ff */
/*07a0*/ FSETP.NEU.FTZ.AND P0, PT, R4, R5, PT ; /* 0x000000050400720b */
/* 0x000fe40003f1d000 */
/*07b0*/ SEL R5, R8, RZ, P2 ; /* 0x000000ff08057207 */
/* 0x000fe40001000000 */
/*07c0*/ ISETP.NE.AND P1, PT, R7, RZ, P1 ; /* 0x000000ff0700720c */
/* 0x000fe40000f25270 */
/*07d0*/ SHF.R.U32.HI R5, RZ, R5, R6 ; /* 0x00000005ff057219 */
/* 0x000fe40000011606 */
/*07e0*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc40000703570 */
/*07f0*/ SHF.R.U32.HI R7, RZ, 0x1, R5 ; /* 0x00000001ff077819 */
/* 0x000fe40000011605 */
/*0800*/ SEL R4, RZ, 0x1, !P0 ; /* 0x00000001ff047807 */
/* 0x000fc80004000000 */
/*0810*/ LOP3.LUT R4, R4, 0x1, R7, 0xf8, !PT ; /* 0x0000000104047812 */
/* 0x000fc800078ef807 */
/*0820*/ LOP3.LUT R4, R4, R5, RZ, 0xc0, !PT ; /* 0x0000000504047212 */
/* 0x000fc800078ec0ff */
/*0830*/ IADD3 R4, R7, R4, RZ ; /* 0x0000000407047210 */
/* 0x000fc80007ffe0ff */
/*0840*/ LOP3.LUT R3, R4, R3, RZ, 0xfc, !PT ; /* 0x0000000304037212 */
/* 0x000fe200078efcff */
/*0850*/ BRA 0x8a0 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*0860*/ LOP3.LUT R3, R3, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000003037812 */
/* 0x000fc800078ec0ff */
/*0870*/ LOP3.LUT R3, R3, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000003037812 */
/* 0x000fe200078efcff */
/*0880*/ BRA 0x8a0 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0890*/ IMAD R3, R6, 0x800000, R3 ; /* 0x0080000006037824 */
/* 0x000fe400078e0203 */
/*08a0*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*08b0*/ BRA 0x940 ; /* 0x0000008000007947 */
/* 0x000fea0003800000 */
/*08c0*/ LOP3.LUT R3, R8, 0x80000000, R5, 0x48, !PT ; /* 0x8000000008037812 */
/* 0x000fc800078e4805 */
/*08d0*/ LOP3.LUT R3, R3, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000003037812 */
/* 0x000fe200078efcff */
/*08e0*/ BRA 0x940 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*08f0*/ LOP3.LUT R3, R8, 0x80000000, R5, 0x48, !PT ; /* 0x8000000008037812 */
/* 0x000fe200078e4805 */
/*0900*/ BRA 0x940 ; /* 0x0000003000007947 */
/* 0x000fea0003800000 */
/*0910*/ MUFU.RSQ R3, -QNAN ; /* 0xffc0000000037908 */
/* 0x000e220000001400 */
/*0920*/ BRA 0x940 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0930*/ FADD.FTZ R3, R6, R13 ; /* 0x0000000d06037221 */
/* 0x000fe40000010000 */
/*0940*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0950*/ IMAD.MOV.U32 R7, RZ, RZ, R3 ; /* 0x000000ffff077224 */
/* 0x001fe400078e0003 */
/*0960*/ IMAD.MOV.U32 R3, RZ, RZ, 0x0 ; /* 0x00000000ff037424 */
/* 0x000fc800078e00ff */
/*0970*/ RET.REL.NODEC R2 0x0 ; /* 0xfffff68002007950 */
/* 0x000fea0003c3ffff */
/*0980*/ BRA 0x980; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0990*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z14ForwardSoftmaxPfiS_S_
.globl _Z14ForwardSoftmaxPfiS_S_
.p2align 8
.type _Z14ForwardSoftmaxPfiS_S_,@function
_Z14ForwardSoftmaxPfiS_S_:
s_clause 0x1
s_load_b32 s6, s[0:1], 0x8
s_load_b64 s[4:5], s[0:1], 0x0
s_mov_b32 s2, s15
s_mov_b32 s3, exec_lo
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[1:2], null, v0, s6, s[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[3:4], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v3, vcc_lo, s4, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
global_load_b32 v0, v[3:4], off
s_waitcnt vmcnt(0)
v_mul_f32_e32 v5, 0x3fb8aa3b, v0
v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fma_f32 v6, v0, 0x3fb8aa3b, -v5
v_rndne_f32_e32 v7, v5
v_dual_fmamk_f32 v6, v0, 0x32a5705f, v6 :: v_dual_sub_f32 v5, v5, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_f32_e32 v5, v5, v6
v_cvt_i32_f32_e32 v6, v7
v_exp_f32_e32 v5, v5
s_waitcnt_depctr 0xfff
v_ldexp_f32 v5, v5, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_cndmask_b32_e32 v5, 0, v5, vcc_lo
v_cmp_nlt_f32_e32 vcc_lo, 0x42b17218, v0
v_bfrev_b32_e32 v0, 1
v_cndmask_b32_e32 v5, 0x7f800000, v5, vcc_lo
.LBB0_1:
s_ctz_i32_b32 s4, s3
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_readlane_b32 s5, v5, s4
s_lshl_b32 s4, 1, s4
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_not1_b32 s3, s3, s4
s_cmp_lg_u32 s3, 0
s_delay_alu instid0(VALU_DEP_1)
v_add_f32_e32 v0, s5, v0
s_cbranch_scc1 .LBB0_1
s_load_b64 s[4:5], s[0:1], 0x10
s_ashr_i32 s3, s2, 31
v_mbcnt_lo_u32_b32 v5, exec_lo, 0
s_lshl_b64 s[2:3], s[2:3], 2
s_waitcnt lgkmcnt(0)
s_add_u32 s2, s4, s2
s_addc_u32 s3, s5, s3
s_mov_b32 s5, 0
s_mov_b32 s4, exec_lo
v_cmpx_eq_u32_e32 0, v5
s_xor_b32 s4, exec_lo, s4
s_cbranch_execz .LBB0_6
s_load_b32 s6, s[2:3], 0x0
s_waitcnt lgkmcnt(0)
v_dual_mov_b32 v7, 0 :: v_dual_mov_b32 v6, s6
.LBB0_4:
s_delay_alu instid0(VALU_DEP_1)
v_add_f32_e32 v5, v6, v0
global_atomic_cmpswap_b32 v5, v7, v[5:6], s[2:3] glc
s_waitcnt vmcnt(0)
v_cmp_eq_u32_e32 vcc_lo, v5, v6
v_mov_b32_e32 v6, v5
s_or_b32 s5, vcc_lo, s5
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s5
s_cbranch_execnz .LBB0_4
s_or_b32 exec_lo, exec_lo, s5
.LBB0_6:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s4
s_barrier
buffer_gl0_inv
global_load_b32 v0, v[3:4], off
v_mov_b32_e32 v3, 0
s_load_b64 s[0:1], s[0:1], 0x18
s_waitcnt vmcnt(0)
v_mul_f32_e32 v4, 0x3fb8aa3b, v0
global_load_b32 v3, v3, s[2:3]
v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v0
v_rndne_f32_e32 v5, v4
v_fma_f32 v6, v0, 0x3fb8aa3b, -v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_f32_e32 v4, v4, v5
v_fmamk_f32 v6, v0, 0x32a5705f, v6
v_cvt_i32_f32_e32 v5, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v4, v4, v6
v_exp_f32_e32 v4, v4
s_waitcnt_depctr 0xfff
v_ldexp_f32 v4, v4, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v4, 0, v4, vcc_lo
v_cmp_nlt_f32_e32 vcc_lo, 0x42b17218, v0
v_cndmask_b32_e32 v4, 0x7f800000, v4, vcc_lo
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_div_scale_f32 v0, null, v3, v3, v4
v_div_scale_f32 v7, vcc_lo, v4, v3, v4
v_rcp_f32_e32 v5, v0
s_waitcnt_depctr 0xfff
v_fma_f32 v6, -v0, v5, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v5, v6, v5
v_mul_f32_e32 v6, v7, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v8, -v0, v6, v7
v_fmac_f32_e32 v6, v8, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v0, -v0, v6, v7
v_div_fmas_f32 v5, v0, v5, v6
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_div_fixup_f32 v2, v5, v3, v4
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z14ForwardSoftmaxPfiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 32
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z14ForwardSoftmaxPfiS_S_, .Lfunc_end0-_Z14ForwardSoftmaxPfiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 32
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z14ForwardSoftmaxPfiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z14ForwardSoftmaxPfiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001727dd_00000000-6_ForwardSoftmax.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z39__device_stub__Z14ForwardSoftmaxPfiS_S_PfiS_S_
.type _Z39__device_stub__Z14ForwardSoftmaxPfiS_S_PfiS_S_, @function
_Z39__device_stub__Z14ForwardSoftmaxPfiS_S_PfiS_S_:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movq %rdx, 8(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z14ForwardSoftmaxPfiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z39__device_stub__Z14ForwardSoftmaxPfiS_S_PfiS_S_, .-_Z39__device_stub__Z14ForwardSoftmaxPfiS_S_PfiS_S_
.globl _Z14ForwardSoftmaxPfiS_S_
.type _Z14ForwardSoftmaxPfiS_S_, @function
_Z14ForwardSoftmaxPfiS_S_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z39__device_stub__Z14ForwardSoftmaxPfiS_S_PfiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z14ForwardSoftmaxPfiS_S_, .-_Z14ForwardSoftmaxPfiS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z14ForwardSoftmaxPfiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z14ForwardSoftmaxPfiS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "ForwardSoftmax.hip"
.globl _Z29__device_stub__ForwardSoftmaxPfiS_S_ # -- Begin function _Z29__device_stub__ForwardSoftmaxPfiS_S_
.p2align 4, 0x90
.type _Z29__device_stub__ForwardSoftmaxPfiS_S_,@function
_Z29__device_stub__ForwardSoftmaxPfiS_S_: # @_Z29__device_stub__ForwardSoftmaxPfiS_S_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movl %esi, 4(%rsp)
movq %rdx, 64(%rsp)
movq %rcx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 56(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z14ForwardSoftmaxPfiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z29__device_stub__ForwardSoftmaxPfiS_S_, .Lfunc_end0-_Z29__device_stub__ForwardSoftmaxPfiS_S_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14ForwardSoftmaxPfiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z14ForwardSoftmaxPfiS_S_,@object # @_Z14ForwardSoftmaxPfiS_S_
.section .rodata,"a",@progbits
.globl _Z14ForwardSoftmaxPfiS_S_
.p2align 3, 0x0
_Z14ForwardSoftmaxPfiS_S_:
.quad _Z29__device_stub__ForwardSoftmaxPfiS_S_
.size _Z14ForwardSoftmaxPfiS_S_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z14ForwardSoftmaxPfiS_S_"
.size .L__unnamed_1, 26
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z29__device_stub__ForwardSoftmaxPfiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z14ForwardSoftmaxPfiS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <thrust/host_vector.h>
#include <thrust/device_vector.h>
#include <thrust/copy.h>
#include <thrust/fill.h>
#include <thrust/sort.h>
#include <thrust/scan.h>
#include <iostream>
using namespace std;
#include <cuda.h>
#include <curand.h>
int main() {
int N = 6;
thrust::host_vector<int> A(N);
for(int i=0;i<N;++i)A[i]=i*i;
thrust::device_vector<int> B = A;
thrust::inclusive_scan(B.begin(), B.end(), B.begin());
thrust::host_vector<int> C = B;
for(int i = 0; i<A.size();++i) cout << A[i] << " "; cout << endl;
for(int i=0;i<C.size();++i) cout << C[i] << " "; cout << endl;
thrust::device_vector<double> D(N);
double* D_ptr = thrust::raw_pointer_cast(D.data());
curandGenerator_t gen;
curandCreateGenerator(&gen, CURAND_RNG_PSEUDO_DEFAULT);
curandGenerateUniformDouble(gen, D_ptr, N);
thrust::host_vector<double> E(N);
thrust::copy(D.begin(), D.end(), E.begin());
cout << "Random Gaussian : " << endl;
for(int i = 0; i < E.size(); i++) cout << " >> " << E[i] << endl;
} | #include <thrust/host_vector.h>
#include <thrust/device_vector.h>
#include <thrust/copy.h>
#include <thrust/fill.h>
#include <thrust/sort.h>
#include <thrust/scan.h>
#include <iostream>
using namespace std;
#include <hip/hip_runtime.h>
#include <hiprand/hiprand.h>
int main() {
int N = 6;
thrust::host_vector<int> A(N);
for(int i=0;i<N;++i)A[i]=i*i;
thrust::device_vector<int> B = A;
thrust::inclusive_scan(B.begin(), B.end(), B.begin());
thrust::host_vector<int> C = B;
for(int i = 0; i<A.size();++i) cout << A[i] << " "; cout << endl;
for(int i=0;i<C.size();++i) cout << C[i] << " "; cout << endl;
thrust::device_vector<double> D(N);
double* D_ptr = thrust::raw_pointer_cast(D.data());
hiprandGenerator_t gen;
hiprandCreateGenerator(&gen, HIPRAND_RNG_PSEUDO_DEFAULT);
hiprandGenerateUniformDouble(gen, D_ptr, N);
thrust::host_vector<double> E(N);
thrust::copy(D.begin(), D.end(), E.begin());
cout << "Random Gaussian : " << endl;
for(int i = 0; i < E.size(); i++) cout << " >> " << E[i] << endl;
} |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | // Undone
__global__ void reduction_sum( double *h_input, double *h_output, int ARRAY_SIZE, int ARRAY_BYTES ){
// Create, Allocate, Calculate, Free Memory, and Return
return;
} | code for sm_80
Function : _Z13reduction_sumPdS_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | // Undone
__global__ void reduction_sum( double *h_input, double *h_output, int ARRAY_SIZE, int ARRAY_BYTES ){
// Create, Allocate, Calculate, Free Memory, and Return
return;
} | .file "tmpxft_000adc50_00000000-6_reduction_sum.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z37__device_stub__Z13reduction_sumPdS_iiPdS_ii
.type _Z37__device_stub__Z13reduction_sumPdS_iiPdS_ii, @function
_Z37__device_stub__Z13reduction_sumPdS_iiPdS_ii:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z13reduction_sumPdS_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z37__device_stub__Z13reduction_sumPdS_iiPdS_ii, .-_Z37__device_stub__Z13reduction_sumPdS_iiPdS_ii
.globl _Z13reduction_sumPdS_ii
.type _Z13reduction_sumPdS_ii, @function
_Z13reduction_sumPdS_ii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z37__device_stub__Z13reduction_sumPdS_iiPdS_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z13reduction_sumPdS_ii, .-_Z13reduction_sumPdS_ii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z13reduction_sumPdS_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z13reduction_sumPdS_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | // Undone
__global__ void reduction_sum( double *h_input, double *h_output, int ARRAY_SIZE, int ARRAY_BYTES ){
// Create, Allocate, Calculate, Free Memory, and Return
return;
} | #include <hip/hip_runtime.h>
// Undone
__global__ void reduction_sum( double *h_input, double *h_output, int ARRAY_SIZE, int ARRAY_BYTES ){
// Create, Allocate, Calculate, Free Memory, and Return
return;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
// Undone
__global__ void reduction_sum( double *h_input, double *h_output, int ARRAY_SIZE, int ARRAY_BYTES ){
// Create, Allocate, Calculate, Free Memory, and Return
return;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z13reduction_sumPdS_ii
.globl _Z13reduction_sumPdS_ii
.p2align 8
.type _Z13reduction_sumPdS_ii,@function
_Z13reduction_sumPdS_ii:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13reduction_sumPdS_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 1
.amdhsa_next_free_sgpr 1
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z13reduction_sumPdS_ii, .Lfunc_end0-_Z13reduction_sumPdS_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13reduction_sumPdS_ii
.private_segment_fixed_size: 0
.sgpr_count: 0
.sgpr_spill_count: 0
.symbol: _Z13reduction_sumPdS_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 0
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
// Undone
__global__ void reduction_sum( double *h_input, double *h_output, int ARRAY_SIZE, int ARRAY_BYTES ){
// Create, Allocate, Calculate, Free Memory, and Return
return;
} | .text
.file "reduction_sum.hip"
.globl _Z28__device_stub__reduction_sumPdS_ii # -- Begin function _Z28__device_stub__reduction_sumPdS_ii
.p2align 4, 0x90
.type _Z28__device_stub__reduction_sumPdS_ii,@function
_Z28__device_stub__reduction_sumPdS_ii: # @_Z28__device_stub__reduction_sumPdS_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z13reduction_sumPdS_ii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z28__device_stub__reduction_sumPdS_ii, .Lfunc_end0-_Z28__device_stub__reduction_sumPdS_ii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13reduction_sumPdS_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z13reduction_sumPdS_ii,@object # @_Z13reduction_sumPdS_ii
.section .rodata,"a",@progbits
.globl _Z13reduction_sumPdS_ii
.p2align 3, 0x0
_Z13reduction_sumPdS_ii:
.quad _Z28__device_stub__reduction_sumPdS_ii
.size _Z13reduction_sumPdS_ii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z13reduction_sumPdS_ii"
.size .L__unnamed_1, 24
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__reduction_sumPdS_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z13reduction_sumPdS_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z13reduction_sumPdS_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z13reduction_sumPdS_ii
.globl _Z13reduction_sumPdS_ii
.p2align 8
.type _Z13reduction_sumPdS_ii,@function
_Z13reduction_sumPdS_ii:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13reduction_sumPdS_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 1
.amdhsa_next_free_sgpr 1
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z13reduction_sumPdS_ii, .Lfunc_end0-_Z13reduction_sumPdS_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13reduction_sumPdS_ii
.private_segment_fixed_size: 0
.sgpr_count: 0
.sgpr_spill_count: 0
.symbol: _Z13reduction_sumPdS_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 0
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000adc50_00000000-6_reduction_sum.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z37__device_stub__Z13reduction_sumPdS_iiPdS_ii
.type _Z37__device_stub__Z13reduction_sumPdS_iiPdS_ii, @function
_Z37__device_stub__Z13reduction_sumPdS_iiPdS_ii:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z13reduction_sumPdS_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z37__device_stub__Z13reduction_sumPdS_iiPdS_ii, .-_Z37__device_stub__Z13reduction_sumPdS_iiPdS_ii
.globl _Z13reduction_sumPdS_ii
.type _Z13reduction_sumPdS_ii, @function
_Z13reduction_sumPdS_ii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z37__device_stub__Z13reduction_sumPdS_iiPdS_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z13reduction_sumPdS_ii, .-_Z13reduction_sumPdS_ii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z13reduction_sumPdS_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z13reduction_sumPdS_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "reduction_sum.hip"
.globl _Z28__device_stub__reduction_sumPdS_ii # -- Begin function _Z28__device_stub__reduction_sumPdS_ii
.p2align 4, 0x90
.type _Z28__device_stub__reduction_sumPdS_ii,@function
_Z28__device_stub__reduction_sumPdS_ii: # @_Z28__device_stub__reduction_sumPdS_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z13reduction_sumPdS_ii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z28__device_stub__reduction_sumPdS_ii, .Lfunc_end0-_Z28__device_stub__reduction_sumPdS_ii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13reduction_sumPdS_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z13reduction_sumPdS_ii,@object # @_Z13reduction_sumPdS_ii
.section .rodata,"a",@progbits
.globl _Z13reduction_sumPdS_ii
.p2align 3, 0x0
_Z13reduction_sumPdS_ii:
.quad _Z28__device_stub__reduction_sumPdS_ii
.size _Z13reduction_sumPdS_ii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z13reduction_sumPdS_ii"
.size .L__unnamed_1, 24
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__reduction_sumPdS_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z13reduction_sumPdS_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <cstdio>
#include <ctime>
/* we need these includes for CUDA's random number stuff */
#include <curand.h>
#include <curand_kernel.h>
#include <iostream>
#include <random>
#include <chrono>
#include "cuda_runtime_api.h"
#define N 8
#define MAX 20
#define PERCENTAGEINTERVAL 5
/* this GPU kernel function is used to initialize the random states */
__global__ void init(unsigned int seed, curandState_t* states) {
/* we have to initialize the state */
curand_init(seed, /* the seed can be the same for each core, here we pass the time in from the CPU */
blockIdx.x, /* the sequence number should be different for each core (unless you want all
cores to get the same sequence of numbers for some reason - use thread id! */
blockIdx.y, /* the offset is how much extra we advance in the sequence for each call, can be 0 */
&states[blockIdx.x]);
}
/* this GPU kernel takes an array of states, and an array of ints, and puts a random int into each */
__global__ void randoms(curandState_t* states, uint8_t* numbers) {
/* curand works like rand - except that it takes a state as a parameter */
uint32_t randInt = curand(&states[blockIdx.x]);
numbers[4 * blockIdx.x] = ((randInt & 0xFF000000UL) >> 24) % MAX + 1;
numbers[4 * blockIdx.x + 1] = ((randInt & 0x00FF0000UL) >> 16) % MAX + 1;
numbers[4 * blockIdx.x + 2] = ((randInt & 0x0000FF00UL) >> 8 ) % MAX + 1;
numbers[4 * blockIdx.x + 3] = ((randInt & 0x000000FFUL) ) % MAX + 1;
}
/* this GPU kernel takes an array of ints and adds 1 to the passcounter if they're greater than or equal to the given int */
__global__ void passcheck(unsigned long long int* passcounter, int8_t* numberstopass, const uint8_t* numbers) {
if (numbers[blockIdx.x * blockDim.x + threadIdx.x] >= numberstopass[0]) { atomicAdd(passcounter, 1); }
}
void printLoadingBar(long long int rolled, long long int counterStop, double start_time ) {
printf("Rolled: %lld%% ", (long long int)ceil(rolled * 100/counterStop));
auto end = std::chrono::system_clock::now().time_since_epoch().count();
double diff = end - start_time;
printf(": %lld rolls per second \n", (long long int)ceil(((double)rolled * 10000000) / diff));
}
// you must first call the cudaGetDeviceProperties() function, then pass
// the devProp structure returned to this function:
int getSPcores(cudaDeviceProp devProp)
{
int cores = 0;
int mp = devProp.multiProcessorCount;
switch (devProp.major){
case 2: // Fermi
if (devProp.minor == 1) cores = mp * 48;
else cores = mp * 32;
break;
case 3: // Kepler
cores = mp * 192;
break;
case 5: // Maxwell
cores = mp * 128;
break;
case 6: // Pascal
if ((devProp.minor == 1) || (devProp.minor == 2)) cores = mp * 128;
else if (devProp.minor == 0) cores = mp * 64;
else printf("Unknown device type\n");
break;
case 7: // Volta and Turing
if ((devProp.minor == 0) || (devProp.minor == 5)) cores = mp * 64;
else printf("Unknown device type\n");
break;
case 8: // Ampere
if (devProp.minor == 0) cores = mp * 64;
else if (devProp.minor == 6) cores = mp * 128;
else printf("Unknown device type\n");
break;
default:
printf("Unknown device type\n");
break;
}
return cores;
}
int main() {
cudaDeviceProp cudaDeviceProp;
cudaGetDeviceProperties(&cudaDeviceProp, 0);
int nrCores = getSPcores(cudaDeviceProp);
std::cout << "ShaderCores: " << nrCores << "\n";
// After how many rolls should you stop
long long int counter = 0;
long long int counterstop = (long long int)(INT32_MAX) * 2;
// Cuda performance metrics
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
// /* allocate an array of int8_t on the CPU and GPU */
// uint8_t cpu_nums[ 4];
uint8_t* gpu_nums;
cudaMalloc((void **) &gpu_nums, nrCores * N * 4 * sizeof(uint8_t));
/* allocate an array of int8_t on the CPU and GPU */
unsigned long long int cpu_pass_counter[1];
cpu_pass_counter[0] = 0;
unsigned long long int* gpu_pass_counter;
cudaMalloc((void **) &gpu_pass_counter, 1 * sizeof(unsigned long long int));
cudaMemcpy(gpu_pass_counter, cpu_pass_counter, 1 * sizeof(unsigned long long int), cudaMemcpyHostToDevice);
/* allocate an array of int8_t on the CPU and GPU of numbers that should be checked against */
int8_t cpu_num_to_pass[1];
cpu_num_to_pass[0] = 11;
int8_t* gpu_num_to_roll;
cudaMalloc((void **) &gpu_num_to_roll, 1 * sizeof(int8_t));
cudaMemcpy(gpu_num_to_roll, cpu_num_to_pass, 1 * sizeof(int8_t), cudaMemcpyHostToDevice);
cudaDeviceSynchronize();
/* allocate space on the GPU for the random states */
curandState_t* states;
cudaMalloc((void **) &states, nrCores * N * sizeof(curandState_t));
/* invoke the GPU to initialize all of the random states */
init<<<nrCores * N, 1>>>(time(nullptr), states);
auto start_timer = std::chrono::system_clock::now();
printLoadingBar(counter, counterstop, start_timer.time_since_epoch().count());
cudaEventRecord(start);
int loopcounter = 0;
while (counter < counterstop) {
/* invoke the kernel to get some random numbers */
randoms<<<nrCores * N, 1>>>(states, gpu_nums);
passcheck<<<nrCores * N, 4>>>(gpu_pass_counter, gpu_num_to_roll, gpu_nums);
/* copy the random numbers back */
// cudaMemcpy(cpu_nums, gpu_nums, nrCores * N * 4 * sizeof(int8_t), cudaMemcpyDeviceToHost);
// cudaMemcpy(cpu_pass_counter, gpu_pass_counter, 1 * sizeof(int64_t), cudaMemcpyDeviceToHost);
counter += nrCores * N * 4;
if ((loopcounter % ((counterstop/(N * nrCores * 4)) / (int)( 1 / ((float)(PERCENTAGEINTERVAL) / 100 ) ))) == 0) {
printLoadingBar(counter, counterstop, start_timer.time_since_epoch().count());
}
loopcounter++;
}
cudaEventRecord(stop);
printLoadingBar(counter, counterstop, start_timer.time_since_epoch().count());
cudaMemcpy(cpu_pass_counter, gpu_pass_counter, 1 * sizeof(unsigned long long int), cudaMemcpyDeviceToHost);
/* free memory from GPU */
cudaFree(states);
cudaFree(gpu_nums);
cudaFree(gpu_pass_counter);
cudaFree(gpu_num_to_roll);
cudaEventSynchronize(stop);
float milliseconds = 0;
cudaEventElapsedTime(&milliseconds, start, stop);
printf("Ran %lld simulations resulting in %lld d%i rolls above %i taking %fs \n", counter, cpu_pass_counter[0], MAX, cpu_num_to_pass[0], milliseconds/1000);
printf("Averaged: %lld rolls per second", (long long int)(counter / (milliseconds/1000)));
do
{
std::cout << '\n' << "Enter any key to continue...";
} while (std::cin.get() != '\n');
return 0;
} | .file "tmpxft_00066fbe_00000000-6_main.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB5072:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE5072:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Rolled: %lld%% "
.LC2:
.string ": %lld rolls per second \n"
.text
.globl _Z15printLoadingBarxxd
.type _Z15printLoadingBarxxd, @function
_Z15printLoadingBarxxd:
.LFB5066:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $16, %rsp
.cfi_def_cfa_offset 32
movq %rdi, %rbx
movsd %xmm0, 8(%rsp)
leaq (%rdi,%rdi,4), %rax
leaq (%rax,%rax,4), %rax
salq $2, %rax
cqto
idivq %rsi
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
cvttsd2siq %xmm0, %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
call _ZNSt6chrono3_V212system_clock3nowEv@PLT
pxor %xmm0, %xmm0
cvtsi2sdq %rbx, %xmm0
mulsd .LC1(%rip), %xmm0
pxor %xmm1, %xmm1
cvtsi2sdq %rax, %xmm1
subsd 8(%rsp), %xmm1
divsd %xmm1, %xmm0
call ceil@PLT
cvttsd2siq %xmm0, %rdx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE5066:
.size _Z15printLoadingBarxxd, .-_Z15printLoadingBarxxd
.section .rodata.str1.1
.LC3:
.string "Unknown device type\n"
.text
.globl _Z10getSPcores14cudaDeviceProp
.type _Z10getSPcores14cudaDeviceProp, @function
_Z10getSPcores14cudaDeviceProp:
.LFB5067:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl 380(%rsp), %esi
movl 404(%rsp), %ecx
cmpl $8, 376(%rsp)
ja .L6
movl 376(%rsp), %eax
leaq .L8(%rip), %rdx
movslq (%rdx,%rax,4), %rax
addq %rdx, %rax
notrack jmp *%rax
.section .rodata
.align 4
.align 4
.L8:
.long .L6-.L8
.long .L6-.L8
.long .L13-.L8
.long .L12-.L8
.long .L6-.L8
.long .L11-.L8
.long .L10-.L8
.long .L9-.L8
.long .L7-.L8
.text
.L13:
movl %ecx, %eax
sall $5, %eax
cmpl $1, %esi
jne .L5
leal (%rcx,%rcx,2), %eax
sall $4, %eax
jmp .L5
.L12:
leal (%rcx,%rcx,2), %eax
sall $6, %eax
.L5:
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
movl %ecx, %eax
sall $7, %eax
jmp .L5
.L10:
leal -1(%rsi), %eax
cmpl $1, %eax
jbe .L24
testl %esi, %esi
jne .L17
movl %ecx, %eax
sall $6, %eax
jmp .L5
.L24:
movl %ecx, %eax
sall $7, %eax
jmp .L5
.L17:
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %eax
jmp .L5
.L9:
cmpl $5, %esi
je .L22
testl %esi, %esi
jne .L18
.L22:
movl %ecx, %eax
sall $6, %eax
jmp .L5
.L18:
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %eax
jmp .L5
.L7:
testl %esi, %esi
jne .L20
movl %ecx, %eax
sall $6, %eax
jmp .L5
.L20:
cmpl $6, %esi
jne .L21
movl %ecx, %eax
sall $7, %eax
jmp .L5
.L21:
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %eax
jmp .L5
.L6:
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %eax
jmp .L5
.cfi_endproc
.LFE5067:
.size _Z10getSPcores14cudaDeviceProp, .-_Z10getSPcores14cudaDeviceProp
.globl _Z42__device_stub__Z4initjP17curandStateXORWOWjP17curandStateXORWOW
.type _Z42__device_stub__Z4initjP17curandStateXORWOWjP17curandStateXORWOW, @function
_Z42__device_stub__Z4initjP17curandStateXORWOWjP17curandStateXORWOW:
.LFB5094:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 12(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L29
.L25:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L30
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L29:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z4initjP17curandStateXORWOW(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L25
.L30:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE5094:
.size _Z42__device_stub__Z4initjP17curandStateXORWOWjP17curandStateXORWOW, .-_Z42__device_stub__Z4initjP17curandStateXORWOWjP17curandStateXORWOW
.globl _Z4initjP17curandStateXORWOW
.type _Z4initjP17curandStateXORWOW, @function
_Z4initjP17curandStateXORWOW:
.LFB5095:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z42__device_stub__Z4initjP17curandStateXORWOWjP17curandStateXORWOW
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE5095:
.size _Z4initjP17curandStateXORWOW, .-_Z4initjP17curandStateXORWOW
.globl _Z46__device_stub__Z7randomsP17curandStateXORWOWPhP17curandStateXORWOWPh
.type _Z46__device_stub__Z7randomsP17curandStateXORWOWPhP17curandStateXORWOWPh, @function
_Z46__device_stub__Z7randomsP17curandStateXORWOWPhP17curandStateXORWOWPh:
.LFB5096:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L37
.L33:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L38
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L37:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z7randomsP17curandStateXORWOWPh(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L33
.L38:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE5096:
.size _Z46__device_stub__Z7randomsP17curandStateXORWOWPhP17curandStateXORWOWPh, .-_Z46__device_stub__Z7randomsP17curandStateXORWOWPhP17curandStateXORWOWPh
.globl _Z7randomsP17curandStateXORWOWPh
.type _Z7randomsP17curandStateXORWOWPh, @function
_Z7randomsP17curandStateXORWOWPh:
.LFB5097:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z46__device_stub__Z7randomsP17curandStateXORWOWPhP17curandStateXORWOWPh
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE5097:
.size _Z7randomsP17curandStateXORWOWPh, .-_Z7randomsP17curandStateXORWOWPh
.globl _Z33__device_stub__Z9passcheckPyPaPKhPyPaPKh
.type _Z33__device_stub__Z9passcheckPyPaPKhPyPaPKh, @function
_Z33__device_stub__Z9passcheckPyPaPKhPyPaPKh:
.LFB5098:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L45
.L41:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L46
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L45:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9passcheckPyPaPKh(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L41
.L46:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE5098:
.size _Z33__device_stub__Z9passcheckPyPaPKhPyPaPKh, .-_Z33__device_stub__Z9passcheckPyPaPKhPyPaPKh
.globl _Z9passcheckPyPaPKh
.type _Z9passcheckPyPaPKh, @function
_Z9passcheckPyPaPKh:
.LFB5099:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z9passcheckPyPaPKhPyPaPKh
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE5099:
.size _Z9passcheckPyPaPKh, .-_Z9passcheckPyPaPKh
.section .rodata.str1.1
.LC4:
.string "ShaderCores: "
.LC5:
.string "\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC8:
.string "Ran %lld simulations resulting in %lld d%i rolls above %i taking %fs \n"
.align 8
.LC9:
.string "Averaged: %lld rolls per second"
.section .rodata.str1.1
.LC10:
.string "Enter any key to continue..."
.text
.globl main
.type main, @function
main:
.LFB5068:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $1160, %rsp
.cfi_def_cfa_offset 1216
movq %fs:40, %rax
movq %rax, 1144(%rsp)
xorl %eax, %eax
leaq 96(%rsp), %rbx
movl $0, %esi
movq %rbx, %rdi
call cudaGetDeviceProperties_v2@PLT
subq $1040, %rsp
.cfi_def_cfa_offset 2256
movl $129, %ecx
movq %rsp, %rdi
movq %rbx, %rsi
rep movsq
call _Z10getSPcores14cudaDeviceProp
movl %eax, %r13d
addq $1040, %rsp
.cfi_def_cfa_offset 1216
leaq .LC4(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl %r13d, %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
leaq .LC5(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
leaq 16(%rsp), %rdi
call cudaEventCreate@PLT
leaq 24(%rsp), %rdi
call cudaEventCreate@PLT
movl %r13d, %r12d
sall $5, %r12d
movslq %r12d, %rsi
leaq 32(%rsp), %rdi
call cudaMalloc@PLT
movq $0, 88(%rsp)
leaq 40(%rsp), %rdi
movl $8, %esi
call cudaMalloc@PLT
leaq 88(%rsp), %rsi
movl $1, %ecx
movl $8, %edx
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
movb $11, 1143(%rsp)
leaq 48(%rsp), %rdi
movl $1, %esi
call cudaMalloc@PLT
leaq 1143(%rsp), %rsi
movl $1, %ecx
movl $1, %edx
movq 48(%rsp), %rdi
call cudaMemcpy@PLT
call cudaDeviceSynchronize@PLT
sall $3, %r13d
movslq %r13d, %rax
leaq (%rax,%rax,2), %rsi
salq $4, %rsi
leaq 56(%rsp), %rdi
call cudaMalloc@PLT
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl %r13d, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 76(%rsp), %rdx
movl $1, %ecx
movq 64(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L62
.L50:
call _ZNSt6chrono3_V212system_clock3nowEv@PLT
pxor %xmm2, %xmm2
cvtsi2sdq %rax, %xmm2
movsd %xmm2, 8(%rsp)
movapd %xmm2, %xmm0
movl $4294967294, %esi
movl $0, %edi
call _Z15printLoadingBarxxd
movl $0, %esi
movq 16(%rsp), %rdi
call cudaEventRecord@PLT
movl $0, %ebx
movl $0, %ebp
movslq %r12d, %r12
movl $4294967294, %r14d
movl $4294967293, %r15d
jmp .L54
.L62:
movq 56(%rsp), %rbx
movl $0, %edi
call time@PLT
movq %rbx, %rsi
movl %eax, %edi
call _Z42__device_stub__Z4initjP17curandStateXORWOWjP17curandStateXORWOW
jmp .L50
.L64:
movq 32(%rsp), %rsi
movq 56(%rsp), %rdi
call _Z46__device_stub__Z7randomsP17curandStateXORWOWPhP17curandStateXORWOWPh
jmp .L51
.L65:
movq 32(%rsp), %rdx
movq 48(%rsp), %rsi
movq 40(%rsp), %rdi
call _Z33__device_stub__Z9passcheckPyPaPKhPyPaPKh
jmp .L52
.L53:
addq $1, %rbx
cmpq %r15, %rbp
jg .L63
.L54:
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl %r13d, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 76(%rsp), %rdx
movl $1, %ecx
movq 64(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L64
.L51:
movl $4, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl %r13d, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 76(%rsp), %rdx
movl $1, %ecx
movq 64(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L65
.L52:
addq %r12, %rbp
movq %r14, %rax
cqto
idivq %r12
movq %rax, %rcx
movabsq $7378697629483820647, %rax
imulq %rcx
sarq $3, %rdx
movq %rcx, %rax
sarq $63, %rax
movq %rdx, %rcx
subq %rax, %rcx
movq %rbx, %rax
cqto
idivq %rcx
testq %rdx, %rdx
jne .L53
movsd 8(%rsp), %xmm0
movq %r14, %rsi
movq %rbp, %rdi
call _Z15printLoadingBarxxd
jmp .L53
.L63:
movl $0, %esi
movq 24(%rsp), %rdi
call cudaEventRecord@PLT
movsd 8(%rsp), %xmm0
movl $4294967294, %esi
movq %rbp, %rdi
call _Z15printLoadingBarxxd
leaq 88(%rsp), %rdi
movl $2, %ecx
movl $8, %edx
movq 40(%rsp), %rsi
call cudaMemcpy@PLT
movq 56(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq 48(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaEventSynchronize@PLT
movl $0x00000000, 76(%rsp)
leaq 76(%rsp), %rdi
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
call cudaEventElapsedTime@PLT
movss 76(%rsp), %xmm0
divss .LC7(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movsbl 1143(%rsp), %r9d
movl $20, %r8d
movq 88(%rsp), %rcx
movq %rbp, %rdx
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
pxor %xmm0, %xmm0
cvtsi2ssq %rbp, %xmm0
movss 76(%rsp), %xmm1
divss .LC7(%rip), %xmm1
divss %xmm1, %xmm0
cvttss2siq %xmm0, %rdx
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq _ZSt4cout(%rip), %rbx
leaq 64(%rsp), %r13
leaq .LC10(%rip), %r12
leaq _ZSt3cin(%rip), %rbp
jmp .L57
.L67:
movl $1, %edx
movq %r13, %rsi
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq %rax, %rdi
.L56:
movl $28, %edx
movq %r12, %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq %rbp, %rdi
call _ZNSi3getEv@PLT
cmpl $10, %eax
je .L66
.L57:
movb $10, 64(%rsp)
movq (%rbx), %rax
movq -24(%rax), %rax
cmpq $0, 16(%rbx,%rax)
jne .L67
movl $10, %esi
movq %rbx, %rdi
call _ZNSo3putEc@PLT
movq %rbx, %rdi
jmp .L56
.L66:
movq 1144(%rsp), %rax
subq %fs:40, %rax
jne .L68
movl $0, %eax
addq $1160, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L68:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE5068:
.size main, .-main
.section .rodata.str1.1
.LC11:
.string "_Z9passcheckPyPaPKh"
.section .rodata.str1.8
.align 8
.LC12:
.string "_Z7randomsP17curandStateXORWOWPh"
.section .rodata.str1.1
.LC13:
.string "_Z4initjP17curandStateXORWOW"
.LC14:
.string "precalc_xorwow_matrix"
.LC15:
.string "precalc_xorwow_offset_matrix"
.LC16:
.string "mrg32k3aM1"
.LC17:
.string "mrg32k3aM2"
.LC18:
.string "mrg32k3aM1SubSeq"
.LC19:
.string "mrg32k3aM2SubSeq"
.LC20:
.string "mrg32k3aM1Seq"
.LC21:
.string "mrg32k3aM2Seq"
.LC22:
.string "__cr_lgamma_table"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB5101:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC11(%rip), %rdx
movq %rdx, %rcx
leaq _Z9passcheckPyPaPKh(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC12(%rip), %rdx
movq %rdx, %rcx
leaq _Z7randomsP17curandStateXORWOWPh(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC13(%rip), %rdx
movq %rdx, %rcx
leaq _Z4initjP17curandStateXORWOW(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $102400, %r9d
movl $0, %r8d
leaq .LC14(%rip), %rdx
movq %rdx, %rcx
leaq _ZL21precalc_xorwow_matrix(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $102400, %r9d
movl $0, %r8d
leaq .LC15(%rip), %rdx
movq %rdx, %rcx
leaq _ZL28precalc_xorwow_offset_matrix(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC16(%rip), %rdx
movq %rdx, %rcx
leaq _ZL10mrg32k3aM1(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC17(%rip), %rdx
movq %rdx, %rcx
leaq _ZL10mrg32k3aM2(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2016, %r9d
movl $0, %r8d
leaq .LC18(%rip), %rdx
movq %rdx, %rcx
leaq _ZL16mrg32k3aM1SubSeq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2016, %r9d
movl $0, %r8d
leaq .LC19(%rip), %rdx
movq %rdx, %rcx
leaq _ZL16mrg32k3aM2SubSeq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC20(%rip), %rdx
movq %rdx, %rcx
leaq _ZL13mrg32k3aM1Seq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC21(%rip), %rdx
movq %rdx, %rcx
leaq _ZL13mrg32k3aM2Seq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $72, %r9d
movl $0, %r8d
leaq .LC22(%rip), %rdx
movq %rdx, %rcx
leaq _ZL17__cr_lgamma_table(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE5101:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL17__cr_lgamma_table
.comm _ZL17__cr_lgamma_table,72,32
.local _ZL13mrg32k3aM2Seq
.comm _ZL13mrg32k3aM2Seq,2304,32
.local _ZL13mrg32k3aM1Seq
.comm _ZL13mrg32k3aM1Seq,2304,32
.local _ZL16mrg32k3aM2SubSeq
.comm _ZL16mrg32k3aM2SubSeq,2016,32
.local _ZL16mrg32k3aM1SubSeq
.comm _ZL16mrg32k3aM1SubSeq,2016,32
.local _ZL10mrg32k3aM2
.comm _ZL10mrg32k3aM2,2304,32
.local _ZL10mrg32k3aM1
.comm _ZL10mrg32k3aM1,2304,32
.local _ZL28precalc_xorwow_offset_matrix
.comm _ZL28precalc_xorwow_offset_matrix,102400,32
.local _ZL21precalc_xorwow_matrix
.comm _ZL21precalc_xorwow_matrix,102400,32
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC1:
.long 0
.long 1097011920
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC7:
.long 1148846080
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <cstdio>
#include <ctime>
/* we need these includes for CUDA's random number stuff */
#include <curand.h>
#include <curand_kernel.h>
#include <iostream>
#include <random>
#include <chrono>
#include "cuda_runtime_api.h"
#define N 8
#define MAX 20
#define PERCENTAGEINTERVAL 5
/* this GPU kernel function is used to initialize the random states */
__global__ void init(unsigned int seed, curandState_t* states) {
/* we have to initialize the state */
curand_init(seed, /* the seed can be the same for each core, here we pass the time in from the CPU */
blockIdx.x, /* the sequence number should be different for each core (unless you want all
cores to get the same sequence of numbers for some reason - use thread id! */
blockIdx.y, /* the offset is how much extra we advance in the sequence for each call, can be 0 */
&states[blockIdx.x]);
}
/* this GPU kernel takes an array of states, and an array of ints, and puts a random int into each */
__global__ void randoms(curandState_t* states, uint8_t* numbers) {
/* curand works like rand - except that it takes a state as a parameter */
uint32_t randInt = curand(&states[blockIdx.x]);
numbers[4 * blockIdx.x] = ((randInt & 0xFF000000UL) >> 24) % MAX + 1;
numbers[4 * blockIdx.x + 1] = ((randInt & 0x00FF0000UL) >> 16) % MAX + 1;
numbers[4 * blockIdx.x + 2] = ((randInt & 0x0000FF00UL) >> 8 ) % MAX + 1;
numbers[4 * blockIdx.x + 3] = ((randInt & 0x000000FFUL) ) % MAX + 1;
}
/* this GPU kernel takes an array of ints and adds 1 to the passcounter if they're greater than or equal to the given int */
__global__ void passcheck(unsigned long long int* passcounter, int8_t* numberstopass, const uint8_t* numbers) {
if (numbers[blockIdx.x * blockDim.x + threadIdx.x] >= numberstopass[0]) { atomicAdd(passcounter, 1); }
}
void printLoadingBar(long long int rolled, long long int counterStop, double start_time ) {
printf("Rolled: %lld%% ", (long long int)ceil(rolled * 100/counterStop));
auto end = std::chrono::system_clock::now().time_since_epoch().count();
double diff = end - start_time;
printf(": %lld rolls per second \n", (long long int)ceil(((double)rolled * 10000000) / diff));
}
// you must first call the cudaGetDeviceProperties() function, then pass
// the devProp structure returned to this function:
int getSPcores(cudaDeviceProp devProp)
{
int cores = 0;
int mp = devProp.multiProcessorCount;
switch (devProp.major){
case 2: // Fermi
if (devProp.minor == 1) cores = mp * 48;
else cores = mp * 32;
break;
case 3: // Kepler
cores = mp * 192;
break;
case 5: // Maxwell
cores = mp * 128;
break;
case 6: // Pascal
if ((devProp.minor == 1) || (devProp.minor == 2)) cores = mp * 128;
else if (devProp.minor == 0) cores = mp * 64;
else printf("Unknown device type\n");
break;
case 7: // Volta and Turing
if ((devProp.minor == 0) || (devProp.minor == 5)) cores = mp * 64;
else printf("Unknown device type\n");
break;
case 8: // Ampere
if (devProp.minor == 0) cores = mp * 64;
else if (devProp.minor == 6) cores = mp * 128;
else printf("Unknown device type\n");
break;
default:
printf("Unknown device type\n");
break;
}
return cores;
}
int main() {
cudaDeviceProp cudaDeviceProp;
cudaGetDeviceProperties(&cudaDeviceProp, 0);
int nrCores = getSPcores(cudaDeviceProp);
std::cout << "ShaderCores: " << nrCores << "\n";
// After how many rolls should you stop
long long int counter = 0;
long long int counterstop = (long long int)(INT32_MAX) * 2;
// Cuda performance metrics
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
// /* allocate an array of int8_t on the CPU and GPU */
// uint8_t cpu_nums[ 4];
uint8_t* gpu_nums;
cudaMalloc((void **) &gpu_nums, nrCores * N * 4 * sizeof(uint8_t));
/* allocate an array of int8_t on the CPU and GPU */
unsigned long long int cpu_pass_counter[1];
cpu_pass_counter[0] = 0;
unsigned long long int* gpu_pass_counter;
cudaMalloc((void **) &gpu_pass_counter, 1 * sizeof(unsigned long long int));
cudaMemcpy(gpu_pass_counter, cpu_pass_counter, 1 * sizeof(unsigned long long int), cudaMemcpyHostToDevice);
/* allocate an array of int8_t on the CPU and GPU of numbers that should be checked against */
int8_t cpu_num_to_pass[1];
cpu_num_to_pass[0] = 11;
int8_t* gpu_num_to_roll;
cudaMalloc((void **) &gpu_num_to_roll, 1 * sizeof(int8_t));
cudaMemcpy(gpu_num_to_roll, cpu_num_to_pass, 1 * sizeof(int8_t), cudaMemcpyHostToDevice);
cudaDeviceSynchronize();
/* allocate space on the GPU for the random states */
curandState_t* states;
cudaMalloc((void **) &states, nrCores * N * sizeof(curandState_t));
/* invoke the GPU to initialize all of the random states */
init<<<nrCores * N, 1>>>(time(nullptr), states);
auto start_timer = std::chrono::system_clock::now();
printLoadingBar(counter, counterstop, start_timer.time_since_epoch().count());
cudaEventRecord(start);
int loopcounter = 0;
while (counter < counterstop) {
/* invoke the kernel to get some random numbers */
randoms<<<nrCores * N, 1>>>(states, gpu_nums);
passcheck<<<nrCores * N, 4>>>(gpu_pass_counter, gpu_num_to_roll, gpu_nums);
/* copy the random numbers back */
// cudaMemcpy(cpu_nums, gpu_nums, nrCores * N * 4 * sizeof(int8_t), cudaMemcpyDeviceToHost);
// cudaMemcpy(cpu_pass_counter, gpu_pass_counter, 1 * sizeof(int64_t), cudaMemcpyDeviceToHost);
counter += nrCores * N * 4;
if ((loopcounter % ((counterstop/(N * nrCores * 4)) / (int)( 1 / ((float)(PERCENTAGEINTERVAL) / 100 ) ))) == 0) {
printLoadingBar(counter, counterstop, start_timer.time_since_epoch().count());
}
loopcounter++;
}
cudaEventRecord(stop);
printLoadingBar(counter, counterstop, start_timer.time_since_epoch().count());
cudaMemcpy(cpu_pass_counter, gpu_pass_counter, 1 * sizeof(unsigned long long int), cudaMemcpyDeviceToHost);
/* free memory from GPU */
cudaFree(states);
cudaFree(gpu_nums);
cudaFree(gpu_pass_counter);
cudaFree(gpu_num_to_roll);
cudaEventSynchronize(stop);
float milliseconds = 0;
cudaEventElapsedTime(&milliseconds, start, stop);
printf("Ran %lld simulations resulting in %lld d%i rolls above %i taking %fs \n", counter, cpu_pass_counter[0], MAX, cpu_num_to_pass[0], milliseconds/1000);
printf("Averaged: %lld rolls per second", (long long int)(counter / (milliseconds/1000)));
do
{
std::cout << '\n' << "Enter any key to continue...";
} while (std::cin.get() != '\n');
return 0;
} | #include <hip/hip_runtime.h>
#include <cstdio>
#include <ctime>
/* we need these includes for CUDA's random number stuff */
#include <hiprand/hiprand.h>
#include <hiprand/hiprand_kernel.h>
#include <iostream>
#include <random>
#include <chrono>
#include "hip/hip_runtime_api.h"
#define N 8
#define MAX 20
#define PERCENTAGEINTERVAL 5
/* this GPU kernel function is used to initialize the random states */
__global__ void init(unsigned int seed, hiprandState_t* states) {
/* we have to initialize the state */
hiprand_init(seed, /* the seed can be the same for each core, here we pass the time in from the CPU */
blockIdx.x, /* the sequence number should be different for each core (unless you want all
cores to get the same sequence of numbers for some reason - use thread id! */
blockIdx.y, /* the offset is how much extra we advance in the sequence for each call, can be 0 */
&states[blockIdx.x]);
}
/* this GPU kernel takes an array of states, and an array of ints, and puts a random int into each */
__global__ void randoms(hiprandState_t* states, uint8_t* numbers) {
/* curand works like rand - except that it takes a state as a parameter */
uint32_t randInt = hiprand(&states[blockIdx.x]);
numbers[4 * blockIdx.x] = ((randInt & 0xFF000000UL) >> 24) % MAX + 1;
numbers[4 * blockIdx.x + 1] = ((randInt & 0x00FF0000UL) >> 16) % MAX + 1;
numbers[4 * blockIdx.x + 2] = ((randInt & 0x0000FF00UL) >> 8 ) % MAX + 1;
numbers[4 * blockIdx.x + 3] = ((randInt & 0x000000FFUL) ) % MAX + 1;
}
/* this GPU kernel takes an array of ints and adds 1 to the passcounter if they're greater than or equal to the given int */
__global__ void passcheck(unsigned long long int* passcounter, int8_t* numberstopass, const uint8_t* numbers) {
if (numbers[blockIdx.x * blockDim.x + threadIdx.x] >= numberstopass[0]) { atomicAdd(passcounter, 1); }
}
void printLoadingBar(long long int rolled, long long int counterStop, double start_time ) {
printf("Rolled: %lld%% ", (long long int)ceil(rolled * 100/counterStop));
auto end = std::chrono::system_clock::now().time_since_epoch().count();
double diff = end - start_time;
printf(": %lld rolls per second \n", (long long int)ceil(((double)rolled * 10000000) / diff));
}
// you must first call the cudaGetDeviceProperties() function, then pass
// the devProp structure returned to this function:
int getSPcores(hipDeviceProp_t devProp)
{
int cores = 0;
int mp = devProp.multiProcessorCount;
switch (devProp.major){
case 2: // Fermi
if (devProp.minor == 1) cores = mp * 48;
else cores = mp * 32;
break;
case 3: // Kepler
cores = mp * 192;
break;
case 5: // Maxwell
cores = mp * 128;
break;
case 6: // Pascal
if ((devProp.minor == 1) || (devProp.minor == 2)) cores = mp * 128;
else if (devProp.minor == 0) cores = mp * 64;
else printf("Unknown device type\n");
break;
case 7: // Volta and Turing
if ((devProp.minor == 0) || (devProp.minor == 5)) cores = mp * 64;
else printf("Unknown device type\n");
break;
case 8: // Ampere
if (devProp.minor == 0) cores = mp * 64;
else if (devProp.minor == 6) cores = mp * 128;
else printf("Unknown device type\n");
break;
default:
printf("Unknown device type\n");
break;
}
return cores;
}
int main() {
hipDeviceProp_t hipDeviceProp_t;
hipGetDeviceProperties(&hipDeviceProp_t, 0);
int nrCores = getSPcores(hipDeviceProp_t);
std::cout << "ShaderCores: " << nrCores << "\n";
// After how many rolls should you stop
long long int counter = 0;
long long int counterstop = (long long int)(INT32_MAX) * 2;
// Cuda performance metrics
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
// /* allocate an array of int8_t on the CPU and GPU */
// uint8_t cpu_nums[ 4];
uint8_t* gpu_nums;
hipMalloc((void **) &gpu_nums, nrCores * N * 4 * sizeof(uint8_t));
/* allocate an array of int8_t on the CPU and GPU */
unsigned long long int cpu_pass_counter[1];
cpu_pass_counter[0] = 0;
unsigned long long int* gpu_pass_counter;
hipMalloc((void **) &gpu_pass_counter, 1 * sizeof(unsigned long long int));
hipMemcpy(gpu_pass_counter, cpu_pass_counter, 1 * sizeof(unsigned long long int), hipMemcpyHostToDevice);
/* allocate an array of int8_t on the CPU and GPU of numbers that should be checked against */
int8_t cpu_num_to_pass[1];
cpu_num_to_pass[0] = 11;
int8_t* gpu_num_to_roll;
hipMalloc((void **) &gpu_num_to_roll, 1 * sizeof(int8_t));
hipMemcpy(gpu_num_to_roll, cpu_num_to_pass, 1 * sizeof(int8_t), hipMemcpyHostToDevice);
hipDeviceSynchronize();
/* allocate space on the GPU for the random states */
hiprandState_t* states;
hipMalloc((void **) &states, nrCores * N * sizeof(hiprandState_t));
/* invoke the GPU to initialize all of the random states */
init<<<nrCores * N, 1>>>(time(nullptr), states);
auto start_timer = std::chrono::system_clock::now();
printLoadingBar(counter, counterstop, start_timer.time_since_epoch().count());
hipEventRecord(start);
int loopcounter = 0;
while (counter < counterstop) {
/* invoke the kernel to get some random numbers */
randoms<<<nrCores * N, 1>>>(states, gpu_nums);
passcheck<<<nrCores * N, 4>>>(gpu_pass_counter, gpu_num_to_roll, gpu_nums);
/* copy the random numbers back */
// cudaMemcpy(cpu_nums, gpu_nums, nrCores * N * 4 * sizeof(int8_t), cudaMemcpyDeviceToHost);
// cudaMemcpy(cpu_pass_counter, gpu_pass_counter, 1 * sizeof(int64_t), cudaMemcpyDeviceToHost);
counter += nrCores * N * 4;
if ((loopcounter % ((counterstop/(N * nrCores * 4)) / (int)( 1 / ((float)(PERCENTAGEINTERVAL) / 100 ) ))) == 0) {
printLoadingBar(counter, counterstop, start_timer.time_since_epoch().count());
}
loopcounter++;
}
hipEventRecord(stop);
printLoadingBar(counter, counterstop, start_timer.time_since_epoch().count());
hipMemcpy(cpu_pass_counter, gpu_pass_counter, 1 * sizeof(unsigned long long int), hipMemcpyDeviceToHost);
/* free memory from GPU */
hipFree(states);
hipFree(gpu_nums);
hipFree(gpu_pass_counter);
hipFree(gpu_num_to_roll);
hipEventSynchronize(stop);
float milliseconds = 0;
hipEventElapsedTime(&milliseconds, start, stop);
printf("Ran %lld simulations resulting in %lld d%i rolls above %i taking %fs \n", counter, cpu_pass_counter[0], MAX, cpu_num_to_pass[0], milliseconds/1000);
printf("Averaged: %lld rolls per second", (long long int)(counter / (milliseconds/1000)));
do
{
std::cout << '\n' << "Enter any key to continue...";
} while (std::cin.get() != '\n');
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <cstdio>
#include <ctime>
/* we need these includes for CUDA's random number stuff */
#include <hiprand/hiprand.h>
#include <hiprand/hiprand_kernel.h>
#include <iostream>
#include <random>
#include <chrono>
#include "hip/hip_runtime_api.h"
#define N 8
#define MAX 20
#define PERCENTAGEINTERVAL 5
/* this GPU kernel function is used to initialize the random states */
__global__ void init(unsigned int seed, hiprandState_t* states) {
/* we have to initialize the state */
hiprand_init(seed, /* the seed can be the same for each core, here we pass the time in from the CPU */
blockIdx.x, /* the sequence number should be different for each core (unless you want all
cores to get the same sequence of numbers for some reason - use thread id! */
blockIdx.y, /* the offset is how much extra we advance in the sequence for each call, can be 0 */
&states[blockIdx.x]);
}
/* this GPU kernel takes an array of states, and an array of ints, and puts a random int into each */
__global__ void randoms(hiprandState_t* states, uint8_t* numbers) {
/* curand works like rand - except that it takes a state as a parameter */
uint32_t randInt = hiprand(&states[blockIdx.x]);
numbers[4 * blockIdx.x] = ((randInt & 0xFF000000UL) >> 24) % MAX + 1;
numbers[4 * blockIdx.x + 1] = ((randInt & 0x00FF0000UL) >> 16) % MAX + 1;
numbers[4 * blockIdx.x + 2] = ((randInt & 0x0000FF00UL) >> 8 ) % MAX + 1;
numbers[4 * blockIdx.x + 3] = ((randInt & 0x000000FFUL) ) % MAX + 1;
}
/* this GPU kernel takes an array of ints and adds 1 to the passcounter if they're greater than or equal to the given int */
__global__ void passcheck(unsigned long long int* passcounter, int8_t* numberstopass, const uint8_t* numbers) {
if (numbers[blockIdx.x * blockDim.x + threadIdx.x] >= numberstopass[0]) { atomicAdd(passcounter, 1); }
}
void printLoadingBar(long long int rolled, long long int counterStop, double start_time ) {
printf("Rolled: %lld%% ", (long long int)ceil(rolled * 100/counterStop));
auto end = std::chrono::system_clock::now().time_since_epoch().count();
double diff = end - start_time;
printf(": %lld rolls per second \n", (long long int)ceil(((double)rolled * 10000000) / diff));
}
// you must first call the cudaGetDeviceProperties() function, then pass
// the devProp structure returned to this function:
int getSPcores(hipDeviceProp_t devProp)
{
int cores = 0;
int mp = devProp.multiProcessorCount;
switch (devProp.major){
case 2: // Fermi
if (devProp.minor == 1) cores = mp * 48;
else cores = mp * 32;
break;
case 3: // Kepler
cores = mp * 192;
break;
case 5: // Maxwell
cores = mp * 128;
break;
case 6: // Pascal
if ((devProp.minor == 1) || (devProp.minor == 2)) cores = mp * 128;
else if (devProp.minor == 0) cores = mp * 64;
else printf("Unknown device type\n");
break;
case 7: // Volta and Turing
if ((devProp.minor == 0) || (devProp.minor == 5)) cores = mp * 64;
else printf("Unknown device type\n");
break;
case 8: // Ampere
if (devProp.minor == 0) cores = mp * 64;
else if (devProp.minor == 6) cores = mp * 128;
else printf("Unknown device type\n");
break;
default:
printf("Unknown device type\n");
break;
}
return cores;
}
int main() {
hipDeviceProp_t hipDeviceProp_t;
hipGetDeviceProperties(&hipDeviceProp_t, 0);
int nrCores = getSPcores(hipDeviceProp_t);
std::cout << "ShaderCores: " << nrCores << "\n";
// After how many rolls should you stop
long long int counter = 0;
long long int counterstop = (long long int)(INT32_MAX) * 2;
// Cuda performance metrics
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
// /* allocate an array of int8_t on the CPU and GPU */
// uint8_t cpu_nums[ 4];
uint8_t* gpu_nums;
hipMalloc((void **) &gpu_nums, nrCores * N * 4 * sizeof(uint8_t));
/* allocate an array of int8_t on the CPU and GPU */
unsigned long long int cpu_pass_counter[1];
cpu_pass_counter[0] = 0;
unsigned long long int* gpu_pass_counter;
hipMalloc((void **) &gpu_pass_counter, 1 * sizeof(unsigned long long int));
hipMemcpy(gpu_pass_counter, cpu_pass_counter, 1 * sizeof(unsigned long long int), hipMemcpyHostToDevice);
/* allocate an array of int8_t on the CPU and GPU of numbers that should be checked against */
int8_t cpu_num_to_pass[1];
cpu_num_to_pass[0] = 11;
int8_t* gpu_num_to_roll;
hipMalloc((void **) &gpu_num_to_roll, 1 * sizeof(int8_t));
hipMemcpy(gpu_num_to_roll, cpu_num_to_pass, 1 * sizeof(int8_t), hipMemcpyHostToDevice);
hipDeviceSynchronize();
/* allocate space on the GPU for the random states */
hiprandState_t* states;
hipMalloc((void **) &states, nrCores * N * sizeof(hiprandState_t));
/* invoke the GPU to initialize all of the random states */
init<<<nrCores * N, 1>>>(time(nullptr), states);
auto start_timer = std::chrono::system_clock::now();
printLoadingBar(counter, counterstop, start_timer.time_since_epoch().count());
hipEventRecord(start);
int loopcounter = 0;
while (counter < counterstop) {
/* invoke the kernel to get some random numbers */
randoms<<<nrCores * N, 1>>>(states, gpu_nums);
passcheck<<<nrCores * N, 4>>>(gpu_pass_counter, gpu_num_to_roll, gpu_nums);
/* copy the random numbers back */
// cudaMemcpy(cpu_nums, gpu_nums, nrCores * N * 4 * sizeof(int8_t), cudaMemcpyDeviceToHost);
// cudaMemcpy(cpu_pass_counter, gpu_pass_counter, 1 * sizeof(int64_t), cudaMemcpyDeviceToHost);
counter += nrCores * N * 4;
if ((loopcounter % ((counterstop/(N * nrCores * 4)) / (int)( 1 / ((float)(PERCENTAGEINTERVAL) / 100 ) ))) == 0) {
printLoadingBar(counter, counterstop, start_timer.time_since_epoch().count());
}
loopcounter++;
}
hipEventRecord(stop);
printLoadingBar(counter, counterstop, start_timer.time_since_epoch().count());
hipMemcpy(cpu_pass_counter, gpu_pass_counter, 1 * sizeof(unsigned long long int), hipMemcpyDeviceToHost);
/* free memory from GPU */
hipFree(states);
hipFree(gpu_nums);
hipFree(gpu_pass_counter);
hipFree(gpu_num_to_roll);
hipEventSynchronize(stop);
float milliseconds = 0;
hipEventElapsedTime(&milliseconds, start, stop);
printf("Ran %lld simulations resulting in %lld d%i rolls above %i taking %fs \n", counter, cpu_pass_counter[0], MAX, cpu_num_to_pass[0], milliseconds/1000);
printf("Averaged: %lld rolls per second", (long long int)(counter / (milliseconds/1000)));
do
{
std::cout << '\n' << "Enter any key to continue...";
} while (std::cin.get() != '\n');
return 0;
} | .text
.file "main.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z19__device_stub__initjP12hiprandState # -- Begin function _Z19__device_stub__initjP12hiprandState
.p2align 4, 0x90
.type _Z19__device_stub__initjP12hiprandState,@function
_Z19__device_stub__initjP12hiprandState: # @_Z19__device_stub__initjP12hiprandState
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movl %edi, 4(%rsp)
movq %rsi, 56(%rsp)
leaq 4(%rsp), %rax
movq %rax, 64(%rsp)
leaq 56(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z4initjP12hiprandState, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z19__device_stub__initjP12hiprandState, .Lfunc_end0-_Z19__device_stub__initjP12hiprandState
.cfi_endproc
# -- End function
.globl _Z22__device_stub__randomsP12hiprandStatePh # -- Begin function _Z22__device_stub__randomsP12hiprandStatePh
.p2align 4, 0x90
.type _Z22__device_stub__randomsP12hiprandStatePh,@function
_Z22__device_stub__randomsP12hiprandStatePh: # @_Z22__device_stub__randomsP12hiprandStatePh
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z7randomsP12hiprandStatePh, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end1:
.size _Z22__device_stub__randomsP12hiprandStatePh, .Lfunc_end1-_Z22__device_stub__randomsP12hiprandStatePh
.cfi_endproc
# -- End function
.globl _Z24__device_stub__passcheckPyPaPKh # -- Begin function _Z24__device_stub__passcheckPyPaPKh
.p2align 4, 0x90
.type _Z24__device_stub__passcheckPyPaPKh,@function
_Z24__device_stub__passcheckPyPaPKh: # @_Z24__device_stub__passcheckPyPaPKh
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9passcheckPyPaPKh, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end2:
.size _Z24__device_stub__passcheckPyPaPKh, .Lfunc_end2-_Z24__device_stub__passcheckPyPaPKh
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z15printLoadingBarxxd
.LCPI3_0:
.quad 0x416312d000000000 # double 1.0E+7
.text
.globl _Z15printLoadingBarxxd
.p2align 4, 0x90
.type _Z15printLoadingBarxxd,@function
_Z15printLoadingBarxxd: # @_Z15printLoadingBarxxd
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $16, %rsp
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -16
movsd %xmm0, 8(%rsp) # 8-byte Spill
movq %rdi, %rbx
imulq $100, %rdi, %rax
cqto
idivq %rsi
xorps %xmm0, %xmm0
cvtsi2sd %rax, %xmm0
cvttsd2si %xmm0, %rsi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
callq _ZNSt6chrono3_V212system_clock3nowEv
cvtsi2sd %rax, %xmm1
xorps %xmm0, %xmm0
cvtsi2sd %rbx, %xmm0
subsd 8(%rsp), %xmm1 # 8-byte Folded Reload
mulsd .LCPI3_0(%rip), %xmm0
divsd %xmm1, %xmm0
callq ceil@PLT
cvttsd2si %xmm0, %rsi
movl $.L.str.1, %edi
xorl %eax, %eax
addq $16, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp printf # TAILCALL
.Lfunc_end3:
.size _Z15printLoadingBarxxd, .Lfunc_end3-_Z15printLoadingBarxxd
.cfi_endproc
# -- End function
.globl _Z10getSPcores20hipDeviceProp_tR0600 # -- Begin function _Z10getSPcores20hipDeviceProp_tR0600
.p2align 4, 0x90
.type _Z10getSPcores20hipDeviceProp_tR0600,@function
_Z10getSPcores20hipDeviceProp_tR0600: # @_Z10getSPcores20hipDeviceProp_tR0600
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
movl 376(%rsp), %ecx
addl $-2, %ecx
cmpl $6, %ecx
ja .LBB4_12
# %bb.1:
leaq 16(%rsp), %rdx
movl 404(%rsp), %eax
jmpq *.LJTI4_0(,%rcx,8)
.LBB4_2:
cmpl $1, 364(%rdx)
jne .LBB4_15
# %bb.3:
shll $4, %eax
jmp .LBB4_4
.LBB4_6:
movl 364(%rdx), %ecx
cmpl $6, %ecx
jne .LBB4_7
jmp .LBB4_16
.LBB4_9:
shll $6, %eax
.LBB4_4:
leal (%rax,%rax,2), %eax
# kill: def $eax killed $eax killed $rax
popq %rcx
.cfi_def_cfa_offset 8
retq
.LBB4_10:
.cfi_def_cfa_offset 16
movl 364(%rdx), %ecx
leal -1(%rcx), %edx
cmpl $1, %edx
ja .LBB4_11
.LBB4_16:
shll $7, %eax
# kill: def $eax killed $eax killed $rax
popq %rcx
.cfi_def_cfa_offset 8
retq
.LBB4_13:
.cfi_def_cfa_offset 16
movl 364(%rdx), %ecx
cmpl $5, %ecx
je .LBB4_8
.LBB4_7:
testl %ecx, %ecx
jne .LBB4_12
.LBB4_8:
shll $6, %eax
# kill: def $eax killed $eax killed $rax
popq %rcx
.cfi_def_cfa_offset 8
retq
.LBB4_15:
.cfi_def_cfa_offset 16
shll $5, %eax
# kill: def $eax killed $eax killed $rax
popq %rcx
.cfi_def_cfa_offset 8
retq
.LBB4_11:
.cfi_def_cfa_offset 16
testl %ecx, %ecx
je .LBB4_8
.LBB4_12:
movl $.Lstr.3, %edi
callq puts@PLT
xorl %eax, %eax
# kill: def $eax killed $eax killed $rax
popq %rcx
.cfi_def_cfa_offset 8
retq
.Lfunc_end4:
.size _Z10getSPcores20hipDeviceProp_tR0600, .Lfunc_end4-_Z10getSPcores20hipDeviceProp_tR0600
.cfi_endproc
.section .rodata,"a",@progbits
.p2align 3, 0x0
.LJTI4_0:
.quad .LBB4_2
.quad .LBB4_9
.quad .LBB4_12
.quad .LBB4_16
.quad .LBB4_10
.quad .LBB4_13
.quad .LBB4_6
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI5_0:
.quad 0x416312d000000000 # double 1.0E+7
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0
.LCPI5_1:
.long 0x447a0000 # float 1000
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $1656, %rsp # imm = 0x678
.cfi_def_cfa_offset 1712
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
leaq 184(%rsp), %rdi
xorl %ebx, %ebx
xorl %esi, %esi
callq hipGetDevicePropertiesR0600
movl 544(%rsp), %edx
addl $-2, %edx
cmpl $6, %edx
ja .LBB5_5
# %bb.1:
movl 548(%rsp), %ecx
movl 572(%rsp), %eax
jmpq *.LJTI5_0(,%rdx,8)
.LBB5_2:
cmpl $1, %ecx
jne .LBB5_13
# %bb.3:
shll $4, %eax
leal (%rax,%rax,2), %ebx
jmp .LBB5_15
.LBB5_4:
cmpl $6, %ecx
jne .LBB5_10
jmp .LBB5_8
.LBB5_5:
movl $.Lstr.3, %edi
callq puts@PLT
jmp .LBB5_15
.LBB5_6:
shll $6, %eax
leal (%rax,%rax,2), %ebx
jmp .LBB5_15
.LBB5_7:
leal -1(%rcx), %edx
cmpl $1, %edx
ja .LBB5_10
.LBB5_8:
shll $7, %eax
jmp .LBB5_14
.LBB5_9:
cmpl $5, %ecx
je .LBB5_12
.LBB5_10:
testl %ecx, %ecx
je .LBB5_12
# %bb.11:
movl $.Lstr.3, %edi
callq puts@PLT
xorl %ebx, %ebx
jmp .LBB5_15
.LBB5_12:
shll $6, %eax
jmp .LBB5_14
.LBB5_13:
shll $5, %eax
.LBB5_14: # %_Z10getSPcores20hipDeviceProp_tR0600.exit
movl %eax, %ebx
.LBB5_15: # %_Z10getSPcores20hipDeviceProp_tR0600.exit
movabsq $4294967297, %r12 # imm = 0x100000001
movl $_ZSt4cout, %edi
movl $.L.str.3, %esi
movl $13, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl %ebx, %esi
callq _ZNSolsEi
movl $.L.str.4, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
leaq 152(%rsp), %rdi
callq hipEventCreate
leaq 144(%rsp), %rdi
callq hipEventCreate
leal (,%rbx,8), %r15d
shll $5, %ebx
movslq %ebx, %r14
leaq 136(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
movq $0, 128(%rsp)
leaq 72(%rsp), %rdi
movl $8, %esi
callq hipMalloc
movq 72(%rsp), %rdi
leaq 128(%rsp), %rsi
movl $8, %edx
movl $1, %ecx
callq hipMemcpy
movb $11, 7(%rsp)
leaq 120(%rsp), %rdi
movl $1, %esi
callq hipMalloc
movq 120(%rsp), %rdi
leaq 7(%rsp), %rsi
movl $1, %edx
movl $1, %ecx
callq hipMemcpy
callq hipDeviceSynchronize
movslq %r15d, %rax
shlq $4, %rax
leaq (%rax,%rax,2), %rsi
leaq 112(%rsp), %rdi
callq hipMalloc
addq %r12, %r15
decq %r15
movq %r15, %rdi
movl $1, %esi
movq %r12, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB5_17
# %bb.16:
xorl %edi, %edi
callq time
movq 112(%rsp), %rcx
movl %eax, 24(%rsp)
movq %rcx, 64(%rsp)
leaq 24(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 8(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 56(%rsp), %rdx
leaq 48(%rsp), %rcx
callq __hipPopCallConfiguration
movq 8(%rsp), %rsi
movl 16(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z4initjP12hiprandState, %edi
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB5_17:
callq _ZNSt6chrono3_V212system_clock3nowEv
cvtsi2sd %rax, %xmm0
movsd %xmm0, 104(%rsp) # 8-byte Spill
movl $.L.str, %edi
xorl %esi, %esi
xorl %eax, %eax
callq printf
callq _ZNSt6chrono3_V212system_clock3nowEv
cvtsi2sd %rax, %xmm1
subsd 104(%rsp), %xmm1 # 8-byte Folded Reload
xorpd %xmm0, %xmm0
divsd %xmm1, %xmm0
callq ceil@PLT
cvttsd2si %xmm0, %rsi
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
movq 152(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
imulq $100, %r14, %rbp
leaq 3(%r12), %rax
movq %rax, 168(%rsp) # 8-byte Spill
leaq -3(%r12), %rax
movq %rax, 160(%rsp) # 8-byte Spill
xorl %r13d, %r13d
xorl %ebx, %ebx
xorl %r12d, %r12d
jmp .LBB5_19
.p2align 4, 0x90
.LBB5_18: # in Loop: Header=BB5_19 Depth=1
incq %rbx
addq %rbp, %r13
cmpq 160(%rsp), %r12 # 8-byte Folded Reload
jge .LBB5_25
.LBB5_19: # =>This Inner Loop Header: Depth=1
movq %r15, %rdi
movl $1, %esi
movabsq $4294967297, %rdx # imm = 0x100000001
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB5_21
# %bb.20: # in Loop: Header=BB5_19 Depth=1
movq 112(%rsp), %rax
movq 136(%rsp), %rcx
movq %rax, 64(%rsp)
movq %rcx, 56(%rsp)
leaq 64(%rsp), %rax
movq %rax, 80(%rsp)
leaq 56(%rsp), %rax
movq %rax, 88(%rsp)
leaq 8(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 8(%rsp), %rsi
movl 16(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movl $_Z7randomsP12hiprandStatePh, %edi
leaq 80(%rsp), %r9
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB5_21: # in Loop: Header=BB5_19 Depth=1
movq %r15, %rdi
movl $1, %esi
movq 168(%rsp), %rdx # 8-byte Reload
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB5_23
# %bb.22: # in Loop: Header=BB5_19 Depth=1
movq 72(%rsp), %rax
movq 120(%rsp), %rcx
movq 136(%rsp), %rdx
movq %rax, 64(%rsp)
movq %rcx, 56(%rsp)
movq %rdx, 48(%rsp)
leaq 64(%rsp), %rax
movq %rax, 80(%rsp)
leaq 56(%rsp), %rax
movq %rax, 88(%rsp)
leaq 48(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 176(%rsp), %rcx
callq __hipPopCallConfiguration
movq 8(%rsp), %rsi
movl 16(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movl $_Z9passcheckPyPaPKh, %edi
leaq 80(%rsp), %r9
pushq 176(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB5_23: # in Loop: Header=BB5_19 Depth=1
addq %r14, %r12
movl $4294967294, %eax # imm = 0xFFFFFFFE
xorl %edx, %edx
idivq %r14
movabsq $7378697629483820647, %rcx # imm = 0x6666666666666667
imulq %rcx
movq %rdx, %rcx
movq %rdx, %rax
shrq $63, %rax
sarq $3, %rcx
addq %rax, %rcx
movq %rbx, %rax
cqto
idivq %rcx
testq %rdx, %rdx
jne .LBB5_18
# %bb.24: # in Loop: Header=BB5_19 Depth=1
movq %rbp, %rcx
addq %r13, %rcx
movq %rcx, %rax
movabsq $-9223372032559808509, %rdx # imm = 0x8000000100000003
imulq %rdx
addq %rcx, %rdx
movq %rdx, %rax
shrq $63, %rax
sarq $31, %rdx
addq %rax, %rdx
xorps %xmm0, %xmm0
cvtsi2sd %rdx, %xmm0
cvttsd2si %xmm0, %rsi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
callq _ZNSt6chrono3_V212system_clock3nowEv
xorps %xmm1, %xmm1
cvtsi2sd %rax, %xmm1
subsd 104(%rsp), %xmm1 # 8-byte Folded Reload
xorps %xmm0, %xmm0
cvtsi2sd %r12, %xmm0
mulsd .LCPI5_0(%rip), %xmm0
divsd %xmm1, %xmm0
callq ceil@PLT
cvttsd2si %xmm0, %rsi
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
jmp .LBB5_18
.LBB5_25:
movq 144(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
shrq %r13
movq %r13, %rax
movabsq $-9223372032559808509, %rcx # imm = 0x8000000100000003
mulq %rcx
shrq $30, %rdx
movl $.L.str, %edi
movq %rdx, %rsi
xorl %eax, %eax
callq printf
callq _ZNSt6chrono3_V212system_clock3nowEv
xorps %xmm1, %xmm1
cvtsi2sd %rax, %xmm1
xorps %xmm0, %xmm0
cvtsi2sd %r12, %xmm0
subsd 104(%rsp), %xmm1 # 8-byte Folded Reload
mulsd .LCPI5_0(%rip), %xmm0
divsd %xmm1, %xmm0
callq ceil@PLT
cvttsd2si %xmm0, %rsi
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
movq 72(%rsp), %rsi
leaq 128(%rsp), %rdi
movl $8, %edx
movl $2, %ecx
callq hipMemcpy
movq 112(%rsp), %rdi
callq hipFree
movq 136(%rsp), %rdi
callq hipFree
movq 72(%rsp), %rdi
callq hipFree
movq 120(%rsp), %rdi
callq hipFree
movq 144(%rsp), %rdi
callq hipEventSynchronize
movl $0, 80(%rsp)
movq 152(%rsp), %rsi
movq 144(%rsp), %rdx
leaq 80(%rsp), %rdi
callq hipEventElapsedTime
movq 128(%rsp), %rdx
movsbl 7(%rsp), %r8d
movss 80(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
divss .LCPI5_1(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movl $.L.str.5, %edi
movq %r12, %rsi
movl $20, %ecx
movb $1, %al
callq printf
xorps %xmm0, %xmm0
cvtsi2ss %r12, %xmm0
movss 80(%rsp), %xmm1 # xmm1 = mem[0],zero,zero,zero
divss .LCPI5_1(%rip), %xmm1
divss %xmm1, %xmm0
cvttss2si %xmm0, %rsi
movl $.L.str.6, %edi
xorl %eax, %eax
callq printf
leaq 8(%rsp), %rbx
jmp .LBB5_28
.p2align 4, 0x90
.LBB5_26: # in Loop: Header=BB5_28 Depth=1
movl $_ZSt4cout, %r14d
movl $_ZSt4cout, %edi
movl $10, %esi
callq _ZNSo3putEc
.LBB5_27: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c.exit
# in Loop: Header=BB5_28 Depth=1
movl $.L.str.7, %esi
movl $28, %edx
movq %r14, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt3cin, %edi
callq _ZNSi3getEv
cmpl $10, %eax
je .LBB5_30
.LBB5_28: # =>This Inner Loop Header: Depth=1
movb $10, 8(%rsp)
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
cmpq $0, _ZSt4cout+16(%rax)
je .LBB5_26
# %bb.29: # in Loop: Header=BB5_28 Depth=1
movl $_ZSt4cout, %edi
movl $1, %edx
movq %rbx, %rsi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq %rax, %r14
jmp .LBB5_27
.LBB5_30:
xorl %eax, %eax
addq $1656, %rsp # imm = 0x678
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end5:
.size main, .Lfunc_end5-main
.cfi_endproc
.section .rodata,"a",@progbits
.p2align 3, 0x0
.LJTI5_0:
.quad .LBB5_2
.quad .LBB5_6
.quad .LBB5_5
.quad .LBB5_8
.quad .LBB5_7
.quad .LBB5_9
.quad .LBB5_4
# -- End function
.text
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB6_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB6_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z4initjP12hiprandState, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7randomsP12hiprandStatePh, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9passcheckPyPaPKh, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end6:
.size __hip_module_ctor, .Lfunc_end6-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB7_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB7_2:
retq
.Lfunc_end7:
.size __hip_module_dtor, .Lfunc_end7-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z4initjP12hiprandState,@object # @_Z4initjP12hiprandState
.section .rodata,"a",@progbits
.globl _Z4initjP12hiprandState
.p2align 3, 0x0
_Z4initjP12hiprandState:
.quad _Z19__device_stub__initjP12hiprandState
.size _Z4initjP12hiprandState, 8
.type _Z7randomsP12hiprandStatePh,@object # @_Z7randomsP12hiprandStatePh
.globl _Z7randomsP12hiprandStatePh
.p2align 3, 0x0
_Z7randomsP12hiprandStatePh:
.quad _Z22__device_stub__randomsP12hiprandStatePh
.size _Z7randomsP12hiprandStatePh, 8
.type _Z9passcheckPyPaPKh,@object # @_Z9passcheckPyPaPKh
.globl _Z9passcheckPyPaPKh
.p2align 3, 0x0
_Z9passcheckPyPaPKh:
.quad _Z24__device_stub__passcheckPyPaPKh
.size _Z9passcheckPyPaPKh, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Rolled: %lld%% "
.size .L.str, 16
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz ": %lld rolls per second \n"
.size .L.str.1, 26
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "ShaderCores: "
.size .L.str.3, 14
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "\n"
.size .L.str.4, 2
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Ran %lld simulations resulting in %lld d%i rolls above %i taking %fs \n"
.size .L.str.5, 71
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "Averaged: %lld rolls per second"
.size .L.str.6, 32
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "Enter any key to continue..."
.size .L.str.7, 29
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z4initjP12hiprandState"
.size .L__unnamed_1, 24
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z7randomsP12hiprandStatePh"
.size .L__unnamed_2, 28
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z9passcheckPyPaPKh"
.size .L__unnamed_3, 20
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr.3,@object # @str.3
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr.3:
.asciz "Unknown device type"
.size .Lstr.3, 20
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z19__device_stub__initjP12hiprandState
.addrsig_sym _Z22__device_stub__randomsP12hiprandStatePh
.addrsig_sym _Z24__device_stub__passcheckPyPaPKh
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z4initjP12hiprandState
.addrsig_sym _Z7randomsP12hiprandStatePh
.addrsig_sym _Z9passcheckPyPaPKh
.addrsig_sym _ZSt4cout
.addrsig_sym _ZSt3cin
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00066fbe_00000000-6_main.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB5072:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE5072:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Rolled: %lld%% "
.LC2:
.string ": %lld rolls per second \n"
.text
.globl _Z15printLoadingBarxxd
.type _Z15printLoadingBarxxd, @function
_Z15printLoadingBarxxd:
.LFB5066:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $16, %rsp
.cfi_def_cfa_offset 32
movq %rdi, %rbx
movsd %xmm0, 8(%rsp)
leaq (%rdi,%rdi,4), %rax
leaq (%rax,%rax,4), %rax
salq $2, %rax
cqto
idivq %rsi
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
cvttsd2siq %xmm0, %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
call _ZNSt6chrono3_V212system_clock3nowEv@PLT
pxor %xmm0, %xmm0
cvtsi2sdq %rbx, %xmm0
mulsd .LC1(%rip), %xmm0
pxor %xmm1, %xmm1
cvtsi2sdq %rax, %xmm1
subsd 8(%rsp), %xmm1
divsd %xmm1, %xmm0
call ceil@PLT
cvttsd2siq %xmm0, %rdx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE5066:
.size _Z15printLoadingBarxxd, .-_Z15printLoadingBarxxd
.section .rodata.str1.1
.LC3:
.string "Unknown device type\n"
.text
.globl _Z10getSPcores14cudaDeviceProp
.type _Z10getSPcores14cudaDeviceProp, @function
_Z10getSPcores14cudaDeviceProp:
.LFB5067:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl 380(%rsp), %esi
movl 404(%rsp), %ecx
cmpl $8, 376(%rsp)
ja .L6
movl 376(%rsp), %eax
leaq .L8(%rip), %rdx
movslq (%rdx,%rax,4), %rax
addq %rdx, %rax
notrack jmp *%rax
.section .rodata
.align 4
.align 4
.L8:
.long .L6-.L8
.long .L6-.L8
.long .L13-.L8
.long .L12-.L8
.long .L6-.L8
.long .L11-.L8
.long .L10-.L8
.long .L9-.L8
.long .L7-.L8
.text
.L13:
movl %ecx, %eax
sall $5, %eax
cmpl $1, %esi
jne .L5
leal (%rcx,%rcx,2), %eax
sall $4, %eax
jmp .L5
.L12:
leal (%rcx,%rcx,2), %eax
sall $6, %eax
.L5:
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
movl %ecx, %eax
sall $7, %eax
jmp .L5
.L10:
leal -1(%rsi), %eax
cmpl $1, %eax
jbe .L24
testl %esi, %esi
jne .L17
movl %ecx, %eax
sall $6, %eax
jmp .L5
.L24:
movl %ecx, %eax
sall $7, %eax
jmp .L5
.L17:
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %eax
jmp .L5
.L9:
cmpl $5, %esi
je .L22
testl %esi, %esi
jne .L18
.L22:
movl %ecx, %eax
sall $6, %eax
jmp .L5
.L18:
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %eax
jmp .L5
.L7:
testl %esi, %esi
jne .L20
movl %ecx, %eax
sall $6, %eax
jmp .L5
.L20:
cmpl $6, %esi
jne .L21
movl %ecx, %eax
sall $7, %eax
jmp .L5
.L21:
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %eax
jmp .L5
.L6:
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %eax
jmp .L5
.cfi_endproc
.LFE5067:
.size _Z10getSPcores14cudaDeviceProp, .-_Z10getSPcores14cudaDeviceProp
.globl _Z42__device_stub__Z4initjP17curandStateXORWOWjP17curandStateXORWOW
.type _Z42__device_stub__Z4initjP17curandStateXORWOWjP17curandStateXORWOW, @function
_Z42__device_stub__Z4initjP17curandStateXORWOWjP17curandStateXORWOW:
.LFB5094:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 12(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L29
.L25:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L30
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L29:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z4initjP17curandStateXORWOW(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L25
.L30:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE5094:
.size _Z42__device_stub__Z4initjP17curandStateXORWOWjP17curandStateXORWOW, .-_Z42__device_stub__Z4initjP17curandStateXORWOWjP17curandStateXORWOW
.globl _Z4initjP17curandStateXORWOW
.type _Z4initjP17curandStateXORWOW, @function
_Z4initjP17curandStateXORWOW:
.LFB5095:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z42__device_stub__Z4initjP17curandStateXORWOWjP17curandStateXORWOW
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE5095:
.size _Z4initjP17curandStateXORWOW, .-_Z4initjP17curandStateXORWOW
.globl _Z46__device_stub__Z7randomsP17curandStateXORWOWPhP17curandStateXORWOWPh
.type _Z46__device_stub__Z7randomsP17curandStateXORWOWPhP17curandStateXORWOWPh, @function
_Z46__device_stub__Z7randomsP17curandStateXORWOWPhP17curandStateXORWOWPh:
.LFB5096:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L37
.L33:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L38
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L37:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z7randomsP17curandStateXORWOWPh(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L33
.L38:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE5096:
.size _Z46__device_stub__Z7randomsP17curandStateXORWOWPhP17curandStateXORWOWPh, .-_Z46__device_stub__Z7randomsP17curandStateXORWOWPhP17curandStateXORWOWPh
.globl _Z7randomsP17curandStateXORWOWPh
.type _Z7randomsP17curandStateXORWOWPh, @function
_Z7randomsP17curandStateXORWOWPh:
.LFB5097:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z46__device_stub__Z7randomsP17curandStateXORWOWPhP17curandStateXORWOWPh
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE5097:
.size _Z7randomsP17curandStateXORWOWPh, .-_Z7randomsP17curandStateXORWOWPh
.globl _Z33__device_stub__Z9passcheckPyPaPKhPyPaPKh
.type _Z33__device_stub__Z9passcheckPyPaPKhPyPaPKh, @function
_Z33__device_stub__Z9passcheckPyPaPKhPyPaPKh:
.LFB5098:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L45
.L41:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L46
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L45:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9passcheckPyPaPKh(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L41
.L46:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE5098:
.size _Z33__device_stub__Z9passcheckPyPaPKhPyPaPKh, .-_Z33__device_stub__Z9passcheckPyPaPKhPyPaPKh
.globl _Z9passcheckPyPaPKh
.type _Z9passcheckPyPaPKh, @function
_Z9passcheckPyPaPKh:
.LFB5099:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z9passcheckPyPaPKhPyPaPKh
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE5099:
.size _Z9passcheckPyPaPKh, .-_Z9passcheckPyPaPKh
.section .rodata.str1.1
.LC4:
.string "ShaderCores: "
.LC5:
.string "\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC8:
.string "Ran %lld simulations resulting in %lld d%i rolls above %i taking %fs \n"
.align 8
.LC9:
.string "Averaged: %lld rolls per second"
.section .rodata.str1.1
.LC10:
.string "Enter any key to continue..."
.text
.globl main
.type main, @function
main:
.LFB5068:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $1160, %rsp
.cfi_def_cfa_offset 1216
movq %fs:40, %rax
movq %rax, 1144(%rsp)
xorl %eax, %eax
leaq 96(%rsp), %rbx
movl $0, %esi
movq %rbx, %rdi
call cudaGetDeviceProperties_v2@PLT
subq $1040, %rsp
.cfi_def_cfa_offset 2256
movl $129, %ecx
movq %rsp, %rdi
movq %rbx, %rsi
rep movsq
call _Z10getSPcores14cudaDeviceProp
movl %eax, %r13d
addq $1040, %rsp
.cfi_def_cfa_offset 1216
leaq .LC4(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl %r13d, %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
leaq .LC5(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
leaq 16(%rsp), %rdi
call cudaEventCreate@PLT
leaq 24(%rsp), %rdi
call cudaEventCreate@PLT
movl %r13d, %r12d
sall $5, %r12d
movslq %r12d, %rsi
leaq 32(%rsp), %rdi
call cudaMalloc@PLT
movq $0, 88(%rsp)
leaq 40(%rsp), %rdi
movl $8, %esi
call cudaMalloc@PLT
leaq 88(%rsp), %rsi
movl $1, %ecx
movl $8, %edx
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
movb $11, 1143(%rsp)
leaq 48(%rsp), %rdi
movl $1, %esi
call cudaMalloc@PLT
leaq 1143(%rsp), %rsi
movl $1, %ecx
movl $1, %edx
movq 48(%rsp), %rdi
call cudaMemcpy@PLT
call cudaDeviceSynchronize@PLT
sall $3, %r13d
movslq %r13d, %rax
leaq (%rax,%rax,2), %rsi
salq $4, %rsi
leaq 56(%rsp), %rdi
call cudaMalloc@PLT
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl %r13d, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 76(%rsp), %rdx
movl $1, %ecx
movq 64(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L62
.L50:
call _ZNSt6chrono3_V212system_clock3nowEv@PLT
pxor %xmm2, %xmm2
cvtsi2sdq %rax, %xmm2
movsd %xmm2, 8(%rsp)
movapd %xmm2, %xmm0
movl $4294967294, %esi
movl $0, %edi
call _Z15printLoadingBarxxd
movl $0, %esi
movq 16(%rsp), %rdi
call cudaEventRecord@PLT
movl $0, %ebx
movl $0, %ebp
movslq %r12d, %r12
movl $4294967294, %r14d
movl $4294967293, %r15d
jmp .L54
.L62:
movq 56(%rsp), %rbx
movl $0, %edi
call time@PLT
movq %rbx, %rsi
movl %eax, %edi
call _Z42__device_stub__Z4initjP17curandStateXORWOWjP17curandStateXORWOW
jmp .L50
.L64:
movq 32(%rsp), %rsi
movq 56(%rsp), %rdi
call _Z46__device_stub__Z7randomsP17curandStateXORWOWPhP17curandStateXORWOWPh
jmp .L51
.L65:
movq 32(%rsp), %rdx
movq 48(%rsp), %rsi
movq 40(%rsp), %rdi
call _Z33__device_stub__Z9passcheckPyPaPKhPyPaPKh
jmp .L52
.L53:
addq $1, %rbx
cmpq %r15, %rbp
jg .L63
.L54:
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl %r13d, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 76(%rsp), %rdx
movl $1, %ecx
movq 64(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L64
.L51:
movl $4, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl %r13d, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 76(%rsp), %rdx
movl $1, %ecx
movq 64(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L65
.L52:
addq %r12, %rbp
movq %r14, %rax
cqto
idivq %r12
movq %rax, %rcx
movabsq $7378697629483820647, %rax
imulq %rcx
sarq $3, %rdx
movq %rcx, %rax
sarq $63, %rax
movq %rdx, %rcx
subq %rax, %rcx
movq %rbx, %rax
cqto
idivq %rcx
testq %rdx, %rdx
jne .L53
movsd 8(%rsp), %xmm0
movq %r14, %rsi
movq %rbp, %rdi
call _Z15printLoadingBarxxd
jmp .L53
.L63:
movl $0, %esi
movq 24(%rsp), %rdi
call cudaEventRecord@PLT
movsd 8(%rsp), %xmm0
movl $4294967294, %esi
movq %rbp, %rdi
call _Z15printLoadingBarxxd
leaq 88(%rsp), %rdi
movl $2, %ecx
movl $8, %edx
movq 40(%rsp), %rsi
call cudaMemcpy@PLT
movq 56(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq 48(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaEventSynchronize@PLT
movl $0x00000000, 76(%rsp)
leaq 76(%rsp), %rdi
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
call cudaEventElapsedTime@PLT
movss 76(%rsp), %xmm0
divss .LC7(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movsbl 1143(%rsp), %r9d
movl $20, %r8d
movq 88(%rsp), %rcx
movq %rbp, %rdx
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
pxor %xmm0, %xmm0
cvtsi2ssq %rbp, %xmm0
movss 76(%rsp), %xmm1
divss .LC7(%rip), %xmm1
divss %xmm1, %xmm0
cvttss2siq %xmm0, %rdx
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq _ZSt4cout(%rip), %rbx
leaq 64(%rsp), %r13
leaq .LC10(%rip), %r12
leaq _ZSt3cin(%rip), %rbp
jmp .L57
.L67:
movl $1, %edx
movq %r13, %rsi
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq %rax, %rdi
.L56:
movl $28, %edx
movq %r12, %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq %rbp, %rdi
call _ZNSi3getEv@PLT
cmpl $10, %eax
je .L66
.L57:
movb $10, 64(%rsp)
movq (%rbx), %rax
movq -24(%rax), %rax
cmpq $0, 16(%rbx,%rax)
jne .L67
movl $10, %esi
movq %rbx, %rdi
call _ZNSo3putEc@PLT
movq %rbx, %rdi
jmp .L56
.L66:
movq 1144(%rsp), %rax
subq %fs:40, %rax
jne .L68
movl $0, %eax
addq $1160, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L68:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE5068:
.size main, .-main
.section .rodata.str1.1
.LC11:
.string "_Z9passcheckPyPaPKh"
.section .rodata.str1.8
.align 8
.LC12:
.string "_Z7randomsP17curandStateXORWOWPh"
.section .rodata.str1.1
.LC13:
.string "_Z4initjP17curandStateXORWOW"
.LC14:
.string "precalc_xorwow_matrix"
.LC15:
.string "precalc_xorwow_offset_matrix"
.LC16:
.string "mrg32k3aM1"
.LC17:
.string "mrg32k3aM2"
.LC18:
.string "mrg32k3aM1SubSeq"
.LC19:
.string "mrg32k3aM2SubSeq"
.LC20:
.string "mrg32k3aM1Seq"
.LC21:
.string "mrg32k3aM2Seq"
.LC22:
.string "__cr_lgamma_table"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB5101:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC11(%rip), %rdx
movq %rdx, %rcx
leaq _Z9passcheckPyPaPKh(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC12(%rip), %rdx
movq %rdx, %rcx
leaq _Z7randomsP17curandStateXORWOWPh(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC13(%rip), %rdx
movq %rdx, %rcx
leaq _Z4initjP17curandStateXORWOW(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $102400, %r9d
movl $0, %r8d
leaq .LC14(%rip), %rdx
movq %rdx, %rcx
leaq _ZL21precalc_xorwow_matrix(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $102400, %r9d
movl $0, %r8d
leaq .LC15(%rip), %rdx
movq %rdx, %rcx
leaq _ZL28precalc_xorwow_offset_matrix(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC16(%rip), %rdx
movq %rdx, %rcx
leaq _ZL10mrg32k3aM1(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC17(%rip), %rdx
movq %rdx, %rcx
leaq _ZL10mrg32k3aM2(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2016, %r9d
movl $0, %r8d
leaq .LC18(%rip), %rdx
movq %rdx, %rcx
leaq _ZL16mrg32k3aM1SubSeq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2016, %r9d
movl $0, %r8d
leaq .LC19(%rip), %rdx
movq %rdx, %rcx
leaq _ZL16mrg32k3aM2SubSeq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC20(%rip), %rdx
movq %rdx, %rcx
leaq _ZL13mrg32k3aM1Seq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC21(%rip), %rdx
movq %rdx, %rcx
leaq _ZL13mrg32k3aM2Seq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $72, %r9d
movl $0, %r8d
leaq .LC22(%rip), %rdx
movq %rdx, %rcx
leaq _ZL17__cr_lgamma_table(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE5101:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL17__cr_lgamma_table
.comm _ZL17__cr_lgamma_table,72,32
.local _ZL13mrg32k3aM2Seq
.comm _ZL13mrg32k3aM2Seq,2304,32
.local _ZL13mrg32k3aM1Seq
.comm _ZL13mrg32k3aM1Seq,2304,32
.local _ZL16mrg32k3aM2SubSeq
.comm _ZL16mrg32k3aM2SubSeq,2016,32
.local _ZL16mrg32k3aM1SubSeq
.comm _ZL16mrg32k3aM1SubSeq,2016,32
.local _ZL10mrg32k3aM2
.comm _ZL10mrg32k3aM2,2304,32
.local _ZL10mrg32k3aM1
.comm _ZL10mrg32k3aM1,2304,32
.local _ZL28precalc_xorwow_offset_matrix
.comm _ZL28precalc_xorwow_offset_matrix,102400,32
.local _ZL21precalc_xorwow_matrix
.comm _ZL21precalc_xorwow_matrix,102400,32
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC1:
.long 0
.long 1097011920
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC7:
.long 1148846080
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "main.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z19__device_stub__initjP12hiprandState # -- Begin function _Z19__device_stub__initjP12hiprandState
.p2align 4, 0x90
.type _Z19__device_stub__initjP12hiprandState,@function
_Z19__device_stub__initjP12hiprandState: # @_Z19__device_stub__initjP12hiprandState
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movl %edi, 4(%rsp)
movq %rsi, 56(%rsp)
leaq 4(%rsp), %rax
movq %rax, 64(%rsp)
leaq 56(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z4initjP12hiprandState, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z19__device_stub__initjP12hiprandState, .Lfunc_end0-_Z19__device_stub__initjP12hiprandState
.cfi_endproc
# -- End function
.globl _Z22__device_stub__randomsP12hiprandStatePh # -- Begin function _Z22__device_stub__randomsP12hiprandStatePh
.p2align 4, 0x90
.type _Z22__device_stub__randomsP12hiprandStatePh,@function
_Z22__device_stub__randomsP12hiprandStatePh: # @_Z22__device_stub__randomsP12hiprandStatePh
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z7randomsP12hiprandStatePh, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end1:
.size _Z22__device_stub__randomsP12hiprandStatePh, .Lfunc_end1-_Z22__device_stub__randomsP12hiprandStatePh
.cfi_endproc
# -- End function
.globl _Z24__device_stub__passcheckPyPaPKh # -- Begin function _Z24__device_stub__passcheckPyPaPKh
.p2align 4, 0x90
.type _Z24__device_stub__passcheckPyPaPKh,@function
_Z24__device_stub__passcheckPyPaPKh: # @_Z24__device_stub__passcheckPyPaPKh
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9passcheckPyPaPKh, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end2:
.size _Z24__device_stub__passcheckPyPaPKh, .Lfunc_end2-_Z24__device_stub__passcheckPyPaPKh
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z15printLoadingBarxxd
.LCPI3_0:
.quad 0x416312d000000000 # double 1.0E+7
.text
.globl _Z15printLoadingBarxxd
.p2align 4, 0x90
.type _Z15printLoadingBarxxd,@function
_Z15printLoadingBarxxd: # @_Z15printLoadingBarxxd
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $16, %rsp
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -16
movsd %xmm0, 8(%rsp) # 8-byte Spill
movq %rdi, %rbx
imulq $100, %rdi, %rax
cqto
idivq %rsi
xorps %xmm0, %xmm0
cvtsi2sd %rax, %xmm0
cvttsd2si %xmm0, %rsi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
callq _ZNSt6chrono3_V212system_clock3nowEv
cvtsi2sd %rax, %xmm1
xorps %xmm0, %xmm0
cvtsi2sd %rbx, %xmm0
subsd 8(%rsp), %xmm1 # 8-byte Folded Reload
mulsd .LCPI3_0(%rip), %xmm0
divsd %xmm1, %xmm0
callq ceil@PLT
cvttsd2si %xmm0, %rsi
movl $.L.str.1, %edi
xorl %eax, %eax
addq $16, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp printf # TAILCALL
.Lfunc_end3:
.size _Z15printLoadingBarxxd, .Lfunc_end3-_Z15printLoadingBarxxd
.cfi_endproc
# -- End function
.globl _Z10getSPcores20hipDeviceProp_tR0600 # -- Begin function _Z10getSPcores20hipDeviceProp_tR0600
.p2align 4, 0x90
.type _Z10getSPcores20hipDeviceProp_tR0600,@function
_Z10getSPcores20hipDeviceProp_tR0600: # @_Z10getSPcores20hipDeviceProp_tR0600
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
movl 376(%rsp), %ecx
addl $-2, %ecx
cmpl $6, %ecx
ja .LBB4_12
# %bb.1:
leaq 16(%rsp), %rdx
movl 404(%rsp), %eax
jmpq *.LJTI4_0(,%rcx,8)
.LBB4_2:
cmpl $1, 364(%rdx)
jne .LBB4_15
# %bb.3:
shll $4, %eax
jmp .LBB4_4
.LBB4_6:
movl 364(%rdx), %ecx
cmpl $6, %ecx
jne .LBB4_7
jmp .LBB4_16
.LBB4_9:
shll $6, %eax
.LBB4_4:
leal (%rax,%rax,2), %eax
# kill: def $eax killed $eax killed $rax
popq %rcx
.cfi_def_cfa_offset 8
retq
.LBB4_10:
.cfi_def_cfa_offset 16
movl 364(%rdx), %ecx
leal -1(%rcx), %edx
cmpl $1, %edx
ja .LBB4_11
.LBB4_16:
shll $7, %eax
# kill: def $eax killed $eax killed $rax
popq %rcx
.cfi_def_cfa_offset 8
retq
.LBB4_13:
.cfi_def_cfa_offset 16
movl 364(%rdx), %ecx
cmpl $5, %ecx
je .LBB4_8
.LBB4_7:
testl %ecx, %ecx
jne .LBB4_12
.LBB4_8:
shll $6, %eax
# kill: def $eax killed $eax killed $rax
popq %rcx
.cfi_def_cfa_offset 8
retq
.LBB4_15:
.cfi_def_cfa_offset 16
shll $5, %eax
# kill: def $eax killed $eax killed $rax
popq %rcx
.cfi_def_cfa_offset 8
retq
.LBB4_11:
.cfi_def_cfa_offset 16
testl %ecx, %ecx
je .LBB4_8
.LBB4_12:
movl $.Lstr.3, %edi
callq puts@PLT
xorl %eax, %eax
# kill: def $eax killed $eax killed $rax
popq %rcx
.cfi_def_cfa_offset 8
retq
.Lfunc_end4:
.size _Z10getSPcores20hipDeviceProp_tR0600, .Lfunc_end4-_Z10getSPcores20hipDeviceProp_tR0600
.cfi_endproc
.section .rodata,"a",@progbits
.p2align 3, 0x0
.LJTI4_0:
.quad .LBB4_2
.quad .LBB4_9
.quad .LBB4_12
.quad .LBB4_16
.quad .LBB4_10
.quad .LBB4_13
.quad .LBB4_6
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI5_0:
.quad 0x416312d000000000 # double 1.0E+7
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0
.LCPI5_1:
.long 0x447a0000 # float 1000
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $1656, %rsp # imm = 0x678
.cfi_def_cfa_offset 1712
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
leaq 184(%rsp), %rdi
xorl %ebx, %ebx
xorl %esi, %esi
callq hipGetDevicePropertiesR0600
movl 544(%rsp), %edx
addl $-2, %edx
cmpl $6, %edx
ja .LBB5_5
# %bb.1:
movl 548(%rsp), %ecx
movl 572(%rsp), %eax
jmpq *.LJTI5_0(,%rdx,8)
.LBB5_2:
cmpl $1, %ecx
jne .LBB5_13
# %bb.3:
shll $4, %eax
leal (%rax,%rax,2), %ebx
jmp .LBB5_15
.LBB5_4:
cmpl $6, %ecx
jne .LBB5_10
jmp .LBB5_8
.LBB5_5:
movl $.Lstr.3, %edi
callq puts@PLT
jmp .LBB5_15
.LBB5_6:
shll $6, %eax
leal (%rax,%rax,2), %ebx
jmp .LBB5_15
.LBB5_7:
leal -1(%rcx), %edx
cmpl $1, %edx
ja .LBB5_10
.LBB5_8:
shll $7, %eax
jmp .LBB5_14
.LBB5_9:
cmpl $5, %ecx
je .LBB5_12
.LBB5_10:
testl %ecx, %ecx
je .LBB5_12
# %bb.11:
movl $.Lstr.3, %edi
callq puts@PLT
xorl %ebx, %ebx
jmp .LBB5_15
.LBB5_12:
shll $6, %eax
jmp .LBB5_14
.LBB5_13:
shll $5, %eax
.LBB5_14: # %_Z10getSPcores20hipDeviceProp_tR0600.exit
movl %eax, %ebx
.LBB5_15: # %_Z10getSPcores20hipDeviceProp_tR0600.exit
movabsq $4294967297, %r12 # imm = 0x100000001
movl $_ZSt4cout, %edi
movl $.L.str.3, %esi
movl $13, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl %ebx, %esi
callq _ZNSolsEi
movl $.L.str.4, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
leaq 152(%rsp), %rdi
callq hipEventCreate
leaq 144(%rsp), %rdi
callq hipEventCreate
leal (,%rbx,8), %r15d
shll $5, %ebx
movslq %ebx, %r14
leaq 136(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
movq $0, 128(%rsp)
leaq 72(%rsp), %rdi
movl $8, %esi
callq hipMalloc
movq 72(%rsp), %rdi
leaq 128(%rsp), %rsi
movl $8, %edx
movl $1, %ecx
callq hipMemcpy
movb $11, 7(%rsp)
leaq 120(%rsp), %rdi
movl $1, %esi
callq hipMalloc
movq 120(%rsp), %rdi
leaq 7(%rsp), %rsi
movl $1, %edx
movl $1, %ecx
callq hipMemcpy
callq hipDeviceSynchronize
movslq %r15d, %rax
shlq $4, %rax
leaq (%rax,%rax,2), %rsi
leaq 112(%rsp), %rdi
callq hipMalloc
addq %r12, %r15
decq %r15
movq %r15, %rdi
movl $1, %esi
movq %r12, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB5_17
# %bb.16:
xorl %edi, %edi
callq time
movq 112(%rsp), %rcx
movl %eax, 24(%rsp)
movq %rcx, 64(%rsp)
leaq 24(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 8(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 56(%rsp), %rdx
leaq 48(%rsp), %rcx
callq __hipPopCallConfiguration
movq 8(%rsp), %rsi
movl 16(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z4initjP12hiprandState, %edi
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB5_17:
callq _ZNSt6chrono3_V212system_clock3nowEv
cvtsi2sd %rax, %xmm0
movsd %xmm0, 104(%rsp) # 8-byte Spill
movl $.L.str, %edi
xorl %esi, %esi
xorl %eax, %eax
callq printf
callq _ZNSt6chrono3_V212system_clock3nowEv
cvtsi2sd %rax, %xmm1
subsd 104(%rsp), %xmm1 # 8-byte Folded Reload
xorpd %xmm0, %xmm0
divsd %xmm1, %xmm0
callq ceil@PLT
cvttsd2si %xmm0, %rsi
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
movq 152(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
imulq $100, %r14, %rbp
leaq 3(%r12), %rax
movq %rax, 168(%rsp) # 8-byte Spill
leaq -3(%r12), %rax
movq %rax, 160(%rsp) # 8-byte Spill
xorl %r13d, %r13d
xorl %ebx, %ebx
xorl %r12d, %r12d
jmp .LBB5_19
.p2align 4, 0x90
.LBB5_18: # in Loop: Header=BB5_19 Depth=1
incq %rbx
addq %rbp, %r13
cmpq 160(%rsp), %r12 # 8-byte Folded Reload
jge .LBB5_25
.LBB5_19: # =>This Inner Loop Header: Depth=1
movq %r15, %rdi
movl $1, %esi
movabsq $4294967297, %rdx # imm = 0x100000001
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB5_21
# %bb.20: # in Loop: Header=BB5_19 Depth=1
movq 112(%rsp), %rax
movq 136(%rsp), %rcx
movq %rax, 64(%rsp)
movq %rcx, 56(%rsp)
leaq 64(%rsp), %rax
movq %rax, 80(%rsp)
leaq 56(%rsp), %rax
movq %rax, 88(%rsp)
leaq 8(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 8(%rsp), %rsi
movl 16(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movl $_Z7randomsP12hiprandStatePh, %edi
leaq 80(%rsp), %r9
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB5_21: # in Loop: Header=BB5_19 Depth=1
movq %r15, %rdi
movl $1, %esi
movq 168(%rsp), %rdx # 8-byte Reload
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB5_23
# %bb.22: # in Loop: Header=BB5_19 Depth=1
movq 72(%rsp), %rax
movq 120(%rsp), %rcx
movq 136(%rsp), %rdx
movq %rax, 64(%rsp)
movq %rcx, 56(%rsp)
movq %rdx, 48(%rsp)
leaq 64(%rsp), %rax
movq %rax, 80(%rsp)
leaq 56(%rsp), %rax
movq %rax, 88(%rsp)
leaq 48(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 176(%rsp), %rcx
callq __hipPopCallConfiguration
movq 8(%rsp), %rsi
movl 16(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movl $_Z9passcheckPyPaPKh, %edi
leaq 80(%rsp), %r9
pushq 176(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB5_23: # in Loop: Header=BB5_19 Depth=1
addq %r14, %r12
movl $4294967294, %eax # imm = 0xFFFFFFFE
xorl %edx, %edx
idivq %r14
movabsq $7378697629483820647, %rcx # imm = 0x6666666666666667
imulq %rcx
movq %rdx, %rcx
movq %rdx, %rax
shrq $63, %rax
sarq $3, %rcx
addq %rax, %rcx
movq %rbx, %rax
cqto
idivq %rcx
testq %rdx, %rdx
jne .LBB5_18
# %bb.24: # in Loop: Header=BB5_19 Depth=1
movq %rbp, %rcx
addq %r13, %rcx
movq %rcx, %rax
movabsq $-9223372032559808509, %rdx # imm = 0x8000000100000003
imulq %rdx
addq %rcx, %rdx
movq %rdx, %rax
shrq $63, %rax
sarq $31, %rdx
addq %rax, %rdx
xorps %xmm0, %xmm0
cvtsi2sd %rdx, %xmm0
cvttsd2si %xmm0, %rsi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
callq _ZNSt6chrono3_V212system_clock3nowEv
xorps %xmm1, %xmm1
cvtsi2sd %rax, %xmm1
subsd 104(%rsp), %xmm1 # 8-byte Folded Reload
xorps %xmm0, %xmm0
cvtsi2sd %r12, %xmm0
mulsd .LCPI5_0(%rip), %xmm0
divsd %xmm1, %xmm0
callq ceil@PLT
cvttsd2si %xmm0, %rsi
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
jmp .LBB5_18
.LBB5_25:
movq 144(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
shrq %r13
movq %r13, %rax
movabsq $-9223372032559808509, %rcx # imm = 0x8000000100000003
mulq %rcx
shrq $30, %rdx
movl $.L.str, %edi
movq %rdx, %rsi
xorl %eax, %eax
callq printf
callq _ZNSt6chrono3_V212system_clock3nowEv
xorps %xmm1, %xmm1
cvtsi2sd %rax, %xmm1
xorps %xmm0, %xmm0
cvtsi2sd %r12, %xmm0
subsd 104(%rsp), %xmm1 # 8-byte Folded Reload
mulsd .LCPI5_0(%rip), %xmm0
divsd %xmm1, %xmm0
callq ceil@PLT
cvttsd2si %xmm0, %rsi
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
movq 72(%rsp), %rsi
leaq 128(%rsp), %rdi
movl $8, %edx
movl $2, %ecx
callq hipMemcpy
movq 112(%rsp), %rdi
callq hipFree
movq 136(%rsp), %rdi
callq hipFree
movq 72(%rsp), %rdi
callq hipFree
movq 120(%rsp), %rdi
callq hipFree
movq 144(%rsp), %rdi
callq hipEventSynchronize
movl $0, 80(%rsp)
movq 152(%rsp), %rsi
movq 144(%rsp), %rdx
leaq 80(%rsp), %rdi
callq hipEventElapsedTime
movq 128(%rsp), %rdx
movsbl 7(%rsp), %r8d
movss 80(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
divss .LCPI5_1(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movl $.L.str.5, %edi
movq %r12, %rsi
movl $20, %ecx
movb $1, %al
callq printf
xorps %xmm0, %xmm0
cvtsi2ss %r12, %xmm0
movss 80(%rsp), %xmm1 # xmm1 = mem[0],zero,zero,zero
divss .LCPI5_1(%rip), %xmm1
divss %xmm1, %xmm0
cvttss2si %xmm0, %rsi
movl $.L.str.6, %edi
xorl %eax, %eax
callq printf
leaq 8(%rsp), %rbx
jmp .LBB5_28
.p2align 4, 0x90
.LBB5_26: # in Loop: Header=BB5_28 Depth=1
movl $_ZSt4cout, %r14d
movl $_ZSt4cout, %edi
movl $10, %esi
callq _ZNSo3putEc
.LBB5_27: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c.exit
# in Loop: Header=BB5_28 Depth=1
movl $.L.str.7, %esi
movl $28, %edx
movq %r14, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt3cin, %edi
callq _ZNSi3getEv
cmpl $10, %eax
je .LBB5_30
.LBB5_28: # =>This Inner Loop Header: Depth=1
movb $10, 8(%rsp)
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
cmpq $0, _ZSt4cout+16(%rax)
je .LBB5_26
# %bb.29: # in Loop: Header=BB5_28 Depth=1
movl $_ZSt4cout, %edi
movl $1, %edx
movq %rbx, %rsi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq %rax, %r14
jmp .LBB5_27
.LBB5_30:
xorl %eax, %eax
addq $1656, %rsp # imm = 0x678
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end5:
.size main, .Lfunc_end5-main
.cfi_endproc
.section .rodata,"a",@progbits
.p2align 3, 0x0
.LJTI5_0:
.quad .LBB5_2
.quad .LBB5_6
.quad .LBB5_5
.quad .LBB5_8
.quad .LBB5_7
.quad .LBB5_9
.quad .LBB5_4
# -- End function
.text
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB6_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB6_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z4initjP12hiprandState, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7randomsP12hiprandStatePh, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9passcheckPyPaPKh, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end6:
.size __hip_module_ctor, .Lfunc_end6-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB7_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB7_2:
retq
.Lfunc_end7:
.size __hip_module_dtor, .Lfunc_end7-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z4initjP12hiprandState,@object # @_Z4initjP12hiprandState
.section .rodata,"a",@progbits
.globl _Z4initjP12hiprandState
.p2align 3, 0x0
_Z4initjP12hiprandState:
.quad _Z19__device_stub__initjP12hiprandState
.size _Z4initjP12hiprandState, 8
.type _Z7randomsP12hiprandStatePh,@object # @_Z7randomsP12hiprandStatePh
.globl _Z7randomsP12hiprandStatePh
.p2align 3, 0x0
_Z7randomsP12hiprandStatePh:
.quad _Z22__device_stub__randomsP12hiprandStatePh
.size _Z7randomsP12hiprandStatePh, 8
.type _Z9passcheckPyPaPKh,@object # @_Z9passcheckPyPaPKh
.globl _Z9passcheckPyPaPKh
.p2align 3, 0x0
_Z9passcheckPyPaPKh:
.quad _Z24__device_stub__passcheckPyPaPKh
.size _Z9passcheckPyPaPKh, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Rolled: %lld%% "
.size .L.str, 16
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz ": %lld rolls per second \n"
.size .L.str.1, 26
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "ShaderCores: "
.size .L.str.3, 14
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "\n"
.size .L.str.4, 2
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Ran %lld simulations resulting in %lld d%i rolls above %i taking %fs \n"
.size .L.str.5, 71
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "Averaged: %lld rolls per second"
.size .L.str.6, 32
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "Enter any key to continue..."
.size .L.str.7, 29
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z4initjP12hiprandState"
.size .L__unnamed_1, 24
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z7randomsP12hiprandStatePh"
.size .L__unnamed_2, 28
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z9passcheckPyPaPKh"
.size .L__unnamed_3, 20
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr.3,@object # @str.3
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr.3:
.asciz "Unknown device type"
.size .Lstr.3, 20
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z19__device_stub__initjP12hiprandState
.addrsig_sym _Z22__device_stub__randomsP12hiprandStatePh
.addrsig_sym _Z24__device_stub__passcheckPyPaPKh
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z4initjP12hiprandState
.addrsig_sym _Z7randomsP12hiprandStatePh
.addrsig_sym _Z9passcheckPyPaPKh
.addrsig_sym _ZSt4cout
.addrsig_sym _ZSt3cin
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <cstdio>
extern "C" {
__global__ void helloWorld(char *data) {
#if __CUDA_ARCH__ >= 200
printf("Hello, world! I'm thread (%d,%d,%d) in block (%d,%d,%d).\n",
threadIdx.x, threadIdx.y, threadIdx.z,
blockIdx.x, blockIdx.y, blockIdx.z);
#endif
int sum = 0;
for (int i=0; i<100; i++) {
sum += data[i];
}
#if __CUDA_ARCH__ >= 200
printf("The sum is: %d\n", sum);
#endif
}
} | code for sm_80
Function : helloWorld
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R11, SR_TID.Y ; /* 0x00000000000b7919 */
/* 0x000e220000002200 */
/*0020*/ MOV R8, 0x0 ; /* 0x0000000000087802 */
/* 0x000fe20000000f00 */
/*0030*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x8] ; /* 0x01000200ff047624 */
/* 0x000fe200078e00ff */
/*0040*/ IADD3 R1, R1, -0x18, RZ ; /* 0xffffffe801017810 */
/* 0x000fe20007ffe0ff */
/*0050*/ S2R R10, SR_TID.X ; /* 0x00000000000a7919 */
/* 0x000e220000002100 */
/*0060*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0xc] ; /* 0x01000300ff057624 */
/* 0x000fe400078e00ff */
/*0070*/ LDC.64 R8, c[0x4][R8] ; /* 0x0100000008087b82 */
/* 0x000e620000000a00 */
/*0080*/ S2R R13, SR_CTAID.X ; /* 0x00000000000d7919 */
/* 0x000ea20000002500 */
/*0090*/ IADD3 R2, P0, R1, c[0x0][0x20], RZ ; /* 0x0000080001027a10 */
/* 0x000fe20007f1e0ff */
/*00a0*/ IMAD.MOV.U32 R19, RZ, RZ, RZ ; /* 0x000000ffff137224 */
/* 0x000fc400078e00ff */
/*00b0*/ S2R R12, SR_TID.Z ; /* 0x00000000000c7919 */
/* 0x000ea20000002300 */
/*00c0*/ IMAD.MOV.U32 R16, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff107624 */
/* 0x000fe400078e00ff */
/*00d0*/ IMAD.X R18, RZ, RZ, c[0x0][0x24], P0 ; /* 0x00000900ff127624 */
/* 0x000fe200000e06ff */
/*00e0*/ S2R R15, SR_CTAID.Z ; /* 0x00000000000f7919 */
/* 0x000ee20000002700 */
/*00f0*/ IMAD.MOV.U32 R17, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff117624 */
/* 0x000fe400078e00ff */
/*0100*/ IMAD.MOV.U32 R6, RZ, RZ, R2 ; /* 0x000000ffff067224 */
/* 0x000fe200078e0002 */
/*0110*/ S2R R14, SR_CTAID.Y ; /* 0x00000000000e7919 */
/* 0x000ee20000002600 */
/*0120*/ IMAD.MOV.U32 R7, RZ, RZ, R18 ; /* 0x000000ffff077224 */
/* 0x000fc600078e0012 */
/*0130*/ STL.64 [R1], R10 ; /* 0x0000000a01007387 */
/* 0x0011e80000100a00 */
/*0140*/ STL.64 [R1+0x8], R12 ; /* 0x0000080c01007387 */
/* 0x0041e80000100a00 */
/*0150*/ STL.64 [R1+0x10], R14 ; /* 0x0000100e01007387 */
/* 0x0081e40000100a00 */
/*0160*/ LEPC R10 ; /* 0x00000000000a734e */
/* 0x003fe20000000000 */
/*0170*/ MOV R3, 0x1e0 ; /* 0x000001e000037802 */
/* 0x000fe40000000f00 */
/*0180*/ MOV R20, 0x160 ; /* 0x0000016000147802 */
/* 0x000fc40000000f00 */
/*0190*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*01a0*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe40000000f00 */
/*01b0*/ IADD3 R20, P0, P1, -R20, R3, R10 ; /* 0x0000000314147210 */
/* 0x000fc8000791e10a */
/*01c0*/ IADD3.X R21, ~R0, R21, R11, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e250b */
/*01d0*/ CALL.ABS.NOINC R8 ; /* 0x0000000008007343 */
/* 0x000fea0003c00000 */
/*01e0*/ ISETP.GE.AND P0, PT, R19, 0x64, PT ; /* 0x000000641300780c */
/* 0x000fe20003f06270 */
/*01f0*/ BSSY B0, 0x710 ; /* 0x0000051000007945 */
/* 0x000fe20003800000 */
/*0200*/ IMAD.MOV.U32 R0, RZ, RZ, RZ ; /* 0x000000ffff007224 */
/* 0x000fd600078e00ff */
/*0210*/ @P0 BRA 0x620 ; /* 0x0000040000000947 */
/* 0x000fea0003800000 */
/*0220*/ IADD3 R3, -R19, 0x64, RZ ; /* 0x0000006413037810 */
/* 0x000fe40007ffe1ff */
/*0230*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0f070 */
/*0240*/ ISETP.GT.AND P1, PT, R3, 0xc, PT ; /* 0x0000000c0300780c */
/* 0x000fda0003f24270 */
/*0250*/ @!P1 BRA 0x480 ; /* 0x0000022000009947 */
/* 0x000fea0003800000 */
/*0260*/ BSSY B1, 0x480 ; /* 0x0000021000017945 */
/* 0x000fe20003800000 */
/*0270*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0280*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0290*/ LDG.E.S8 R5, [R16.64] ; /* 0x0000000410057981 */
/* 0x000ea8000c1e1300 */
/*02a0*/ LDG.E.S8 R6, [R16.64+0x1] ; /* 0x0000010410067981 */
/* 0x000ea8000c1e1300 */
/*02b0*/ LDG.E.S8 R8, [R16.64+0x2] ; /* 0x0000020410087981 */
/* 0x0000e8000c1e1300 */
/*02c0*/ LDG.E.S8 R7, [R16.64+0x3] ; /* 0x0000030410077981 */
/* 0x0000e8000c1e1300 */
/*02d0*/ LDG.E.S8 R10, [R16.64+0x4] ; /* 0x00000404100a7981 */
/* 0x000128000c1e1300 */
/*02e0*/ LDG.E.S8 R9, [R16.64+0x5] ; /* 0x0000050410097981 */
/* 0x000128000c1e1300 */
/*02f0*/ LDG.E.S8 R12, [R16.64+0x6] ; /* 0x00000604100c7981 */
/* 0x000168000c1e1300 */
/*0300*/ LDG.E.S8 R11, [R16.64+0x7] ; /* 0x00000704100b7981 */
/* 0x000168000c1e1300 */
/*0310*/ LDG.E.S8 R14, [R16.64+0x8] ; /* 0x00000804100e7981 */
/* 0x000168000c1e1300 */
/*0320*/ LDG.E.S8 R13, [R16.64+0x9] ; /* 0x00000904100d7981 */
/* 0x000168000c1e1300 */
/*0330*/ LDG.E.S8 R20, [R16.64+0xa] ; /* 0x00000a0410147981 */
/* 0x000168000c1e1300 */
/*0340*/ LDG.E.S8 R15, [R16.64+0xb] ; /* 0x00000b04100f7981 */
/* 0x000168000c1e1300 */
/*0350*/ LDG.E.S8 R22, [R16.64+0xc] ; /* 0x00000c0410167981 */
/* 0x000168000c1e1300 */
/*0360*/ LDG.E.S8 R21, [R16.64+0xd] ; /* 0x00000d0410157981 */
/* 0x000168000c1e1300 */
/*0370*/ LDG.E.S8 R3, [R16.64+0xe] ; /* 0x00000e0410037981 */
/* 0x000168000c1e1300 */
/*0380*/ LDG.E.S8 R4, [R16.64+0xf] ; /* 0x00000f0410047981 */
/* 0x000162000c1e1300 */
/*0390*/ IADD3 R19, R19, 0x10, RZ ; /* 0x0000001013137810 */
/* 0x000fc80007ffe0ff */
/*03a0*/ ISETP.GE.AND P1, PT, R19, 0x58, PT ; /* 0x000000581300780c */
/* 0x000fe40003f26270 */
/*03b0*/ IADD3 R5, R6, R0, R5 ; /* 0x0000000006057210 */
/* 0x004fe40007ffe005 */
/*03c0*/ IADD3 R6, P2, R16, 0x10, RZ ; /* 0x0000001010067810 */
/* 0x000fca0007f5e0ff */
/*03d0*/ IMAD.X R17, RZ, RZ, R17, P2 ; /* 0x000000ffff117224 */
/* 0x001fe200010e0611 */
/*03e0*/ IADD3 R5, R7, R5, R8 ; /* 0x0000000507057210 */
/* 0x008fe20007ffe008 */
/*03f0*/ IMAD.MOV.U32 R16, RZ, RZ, R6 ; /* 0x000000ffff107224 */
/* 0x000fc600078e0006 */
/*0400*/ IADD3 R5, R9, R5, R10 ; /* 0x0000000509057210 */
/* 0x010fc80007ffe00a */
/*0410*/ IADD3 R5, R11, R5, R12 ; /* 0x000000050b057210 */
/* 0x020fc80007ffe00c */
/*0420*/ IADD3 R5, R13, R5, R14 ; /* 0x000000050d057210 */
/* 0x000fc80007ffe00e */
/*0430*/ IADD3 R5, R15, R5, R20 ; /* 0x000000050f057210 */
/* 0x000fc80007ffe014 */
/*0440*/ IADD3 R5, R21, R5, R22 ; /* 0x0000000515057210 */
/* 0x000fc80007ffe016 */
/*0450*/ IADD3 R0, R4, R5, R3 ; /* 0x0000000504007210 */
/* 0x000fe20007ffe003 */
/*0460*/ @!P1 BRA 0x280 ; /* 0xfffffe1000009947 */
/* 0x000fea000383ffff */
/*0470*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0480*/ IADD3 R3, -R19, 0x64, RZ ; /* 0x0000006413037810 */
/* 0x000fe20007ffe1ff */
/*0490*/ BSSY B1, 0x600 ; /* 0x0000016000017945 */
/* 0x000fe60003800000 */
/*04a0*/ ISETP.GT.AND P1, PT, R3, 0x4, PT ; /* 0x000000040300780c */
/* 0x000fda0003f24270 */
/*04b0*/ @!P1 BRA 0x5f0 ; /* 0x0000013000009947 */
/* 0x000fea0003800000 */
/*04c0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*04d0*/ LDG.E.S8 R3, [R16.64] ; /* 0x0000000410037981 */
/* 0x000ea8000c1e1300 */
/*04e0*/ LDG.E.S8 R4, [R16.64+0x1] ; /* 0x0000010410047981 */
/* 0x000ea8000c1e1300 */
/*04f0*/ LDG.E.S8 R6, [R16.64+0x2] ; /* 0x0000020410067981 */
/* 0x0000e8000c1e1300 */
/*0500*/ LDG.E.S8 R5, [R16.64+0x3] ; /* 0x0000030410057981 */
/* 0x0000e8000c1e1300 */
/*0510*/ LDG.E.S8 R8, [R16.64+0x4] ; /* 0x0000040410087981 */
/* 0x000128000c1e1300 */
/*0520*/ LDG.E.S8 R7, [R16.64+0x5] ; /* 0x0000050410077981 */
/* 0x000128000c1e1300 */
/*0530*/ LDG.E.S8 R10, [R16.64+0x6] ; /* 0x00000604100a7981 */
/* 0x000168000c1e1300 */
/*0540*/ LDG.E.S8 R9, [R16.64+0x7] ; /* 0x0000070410097981 */
/* 0x000162000c1e1300 */
/*0550*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc40003f0e170 */
/*0560*/ IADD3 R19, R19, 0x8, RZ ; /* 0x0000000813137810 */
/* 0x000fe40007ffe0ff */
/*0570*/ IADD3 R3, R4, R0, R3 ; /* 0x0000000004037210 */
/* 0x004fe40007ffe003 */
/*0580*/ IADD3 R4, P1, R16, 0x8, RZ ; /* 0x0000000810047810 */
/* 0x000fca0007f3e0ff */
/*0590*/ IMAD.MOV.U32 R16, RZ, RZ, R4 ; /* 0x000000ffff107224 */
/* 0x001fe200078e0004 */
/*05a0*/ IADD3 R3, R5, R3, R6 ; /* 0x0000000305037210 */
/* 0x008fe20007ffe006 */
/*05b0*/ IMAD.X R5, RZ, RZ, R17, P1 ; /* 0x000000ffff057224 */
/* 0x000fc800008e0611 */
/*05c0*/ IMAD.MOV.U32 R17, RZ, RZ, R5 ; /* 0x000000ffff117224 */
/* 0x000fe200078e0005 */
/*05d0*/ IADD3 R3, R7, R3, R8 ; /* 0x0000000307037210 */
/* 0x010fc80007ffe008 */
/*05e0*/ IADD3 R0, R9, R3, R10 ; /* 0x0000000309007210 */
/* 0x020fe40007ffe00a */
/*05f0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0600*/ ISETP.NE.OR P0, PT, R19, 0x64, P0 ; /* 0x000000641300780c */
/* 0x000fda0000705670 */
/*0610*/ @!P0 BRA 0x700 ; /* 0x000000e000008947 */
/* 0x000fea0003800000 */
/*0620*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0630*/ LDG.E.S8 R5, [R16.64] ; /* 0x0000000410057981 */
/* 0x0000a8000c1e1300 */
/*0640*/ LDG.E.S8 R4, [R16.64+0x1] ; /* 0x0000010410047981 */
/* 0x0000a8000c1e1300 */
/*0650*/ LDG.E.S8 R7, [R16.64+0x2] ; /* 0x0000020410077981 */
/* 0x0000e8000c1e1300 */
/*0660*/ LDG.E.S8 R6, [R16.64+0x3] ; /* 0x0000030410067981 */
/* 0x0000e2000c1e1300 */
/*0670*/ IADD3 R19, R19, 0x4, RZ ; /* 0x0000000413137810 */
/* 0x000fc40007ffe0ff */
/*0680*/ IADD3 R3, P1, R16, 0x4, RZ ; /* 0x0000000410037810 */
/* 0x000fe40007f3e0ff */
/*0690*/ ISETP.NE.AND P0, PT, R19, 0x64, PT ; /* 0x000000641300780c */
/* 0x000fc60003f05270 */
/*06a0*/ IMAD.MOV.U32 R16, RZ, RZ, R3 ; /* 0x000000ffff107224 */
/* 0x001fe200078e0003 */
/*06b0*/ IADD3 R0, R4, R0, R5 ; /* 0x0000000004007210 */
/* 0x004fe20007ffe005 */
/*06c0*/ IMAD.X R4, RZ, RZ, R17, P1 ; /* 0x000000ffff047224 */
/* 0x000fc800008e0611 */
/*06d0*/ IMAD.MOV.U32 R17, RZ, RZ, R4 ; /* 0x000000ffff117224 */
/* 0x000fe200078e0004 */
/*06e0*/ IADD3 R0, R6, R0, R7 ; /* 0x0000000006007210 */
/* 0x008fc60007ffe007 */
/*06f0*/ @P0 BRA 0x620 ; /* 0xffffff2000000947 */
/* 0x000fea000383ffff */
/*0700*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0710*/ MOV R3, 0x0 ; /* 0x0000000000037802 */
/* 0x000fe20000000f00 */
/*0720*/ STL [R1], R0 ; /* 0x0000000001007387 */
/* 0x0001e20000100800 */
/*0730*/ IMAD.MOV.U32 R6, RZ, RZ, R2 ; /* 0x000000ffff067224 */
/* 0x000fe400078e0002 */
/*0740*/ LDC.64 R8, c[0x4][R3] ; /* 0x0100000003087b82 */
/* 0x0000620000000a00 */
/*0750*/ IMAD.MOV.U32 R7, RZ, RZ, R18 ; /* 0x000000ffff077224 */
/* 0x000fe400078e0012 */
/*0760*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x10] ; /* 0x01000400ff047624 */
/* 0x000fe400078e00ff */
/*0770*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0x14] ; /* 0x01000500ff057624 */
/* 0x000fc600078e00ff */
/*0780*/ LEPC R2 ; /* 0x000000000002734e */
/* 0x001fe20000000000 */
/*0790*/ MOV R11, 0x800 ; /* 0x00000800000b7802 */
/* 0x000fc40000000f00 */
/*07a0*/ MOV R20, 0x780 ; /* 0x0000078000147802 */
/* 0x000fe40000000f00 */
/*07b0*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*07c0*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe40000000f00 */
/*07d0*/ IADD3 R20, P0, P1, -R20, R11, R2 ; /* 0x0000000b14147210 */
/* 0x000fc8000791e102 */
/*07e0*/ IADD3.X R21, ~R0, R21, R3, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2503 */
/*07f0*/ CALL.ABS.NOINC R8 ; /* 0x0000000008007343 */
/* 0x002fea0003c00000 */
/*0800*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0810*/ BRA 0x810; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0820*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0830*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0840*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0850*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0860*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0870*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0880*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0890*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <cstdio>
extern "C" {
__global__ void helloWorld(char *data) {
#if __CUDA_ARCH__ >= 200
printf("Hello, world! I'm thread (%d,%d,%d) in block (%d,%d,%d).\n",
threadIdx.x, threadIdx.y, threadIdx.z,
blockIdx.x, blockIdx.y, blockIdx.z);
#endif
int sum = 0;
for (int i=0; i<100; i++) {
sum += data[i];
}
#if __CUDA_ARCH__ >= 200
printf("The sum is: %d\n", sum);
#endif
}
} | .file "tmpxft_00073957_00000000-6_test.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2059:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z30__device_stub__Z10helloWorldPcPc
.type _Z30__device_stub__Z10helloWorldPcPc, @function
_Z30__device_stub__Z10helloWorldPcPc:
.LFB2081:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq helloWorld(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2081:
.size _Z30__device_stub__Z10helloWorldPcPc, .-_Z30__device_stub__Z10helloWorldPcPc
.globl helloWorld
.type helloWorld, @function
helloWorld:
.LFB2082:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z10helloWorldPcPc
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2082:
.size helloWorld, .-helloWorld
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "helloWorld"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq helloWorld(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <cstdio>
extern "C" {
__global__ void helloWorld(char *data) {
#if __CUDA_ARCH__ >= 200
printf("Hello, world! I'm thread (%d,%d,%d) in block (%d,%d,%d).\n",
threadIdx.x, threadIdx.y, threadIdx.z,
blockIdx.x, blockIdx.y, blockIdx.z);
#endif
int sum = 0;
for (int i=0; i<100; i++) {
sum += data[i];
}
#if __CUDA_ARCH__ >= 200
printf("The sum is: %d\n", sum);
#endif
}
} | #include <hip/hip_runtime.h>
#include <cstdio>
extern "C" {
__global__ void helloWorld(char *data) {
#if __CUDA_ARCH__ >= 200
printf("Hello, world! I'm thread (%d,%d,%d) in block (%d,%d,%d).\n",
threadIdx.x, threadIdx.y, threadIdx.z,
blockIdx.x, blockIdx.y, blockIdx.z);
#endif
int sum = 0;
for (int i=0; i<100; i++) {
sum += data[i];
}
#if __CUDA_ARCH__ >= 200
printf("The sum is: %d\n", sum);
#endif
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <cstdio>
extern "C" {
__global__ void helloWorld(char *data) {
#if __CUDA_ARCH__ >= 200
printf("Hello, world! I'm thread (%d,%d,%d) in block (%d,%d,%d).\n",
threadIdx.x, threadIdx.y, threadIdx.z,
blockIdx.x, blockIdx.y, blockIdx.z);
#endif
int sum = 0;
for (int i=0; i<100; i++) {
sum += data[i];
}
#if __CUDA_ARCH__ >= 200
printf("The sum is: %d\n", sum);
#endif
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected helloWorld
.globl helloWorld
.p2align 8
.type helloWorld,@function
helloWorld:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel helloWorld
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 8
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 1
.amdhsa_next_free_sgpr 1
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size helloWorld, .Lfunc_end0-helloWorld
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 8
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: helloWorld
.private_segment_fixed_size: 0
.sgpr_count: 0
.sgpr_spill_count: 0
.symbol: helloWorld.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 0
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <cstdio>
extern "C" {
__global__ void helloWorld(char *data) {
#if __CUDA_ARCH__ >= 200
printf("Hello, world! I'm thread (%d,%d,%d) in block (%d,%d,%d).\n",
threadIdx.x, threadIdx.y, threadIdx.z,
blockIdx.x, blockIdx.y, blockIdx.z);
#endif
int sum = 0;
for (int i=0; i<100; i++) {
sum += data[i];
}
#if __CUDA_ARCH__ >= 200
printf("The sum is: %d\n", sum);
#endif
}
} | .text
.file "test.hip"
.globl __device_stub__helloWorld # -- Begin function __device_stub__helloWorld
.p2align 4, 0x90
.type __device_stub__helloWorld,@function
__device_stub__helloWorld: # @__device_stub__helloWorld
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $helloWorld, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size __device_stub__helloWorld, .Lfunc_end0-__device_stub__helloWorld
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $helloWorld, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type helloWorld,@object # @helloWorld
.section .rodata,"a",@progbits
.globl helloWorld
.p2align 3, 0x0
helloWorld:
.quad __device_stub__helloWorld
.size helloWorld, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "helloWorld"
.size .L__unnamed_1, 11
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub__helloWorld
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym helloWorld
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : helloWorld
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R11, SR_TID.Y ; /* 0x00000000000b7919 */
/* 0x000e220000002200 */
/*0020*/ MOV R8, 0x0 ; /* 0x0000000000087802 */
/* 0x000fe20000000f00 */
/*0030*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x8] ; /* 0x01000200ff047624 */
/* 0x000fe200078e00ff */
/*0040*/ IADD3 R1, R1, -0x18, RZ ; /* 0xffffffe801017810 */
/* 0x000fe20007ffe0ff */
/*0050*/ S2R R10, SR_TID.X ; /* 0x00000000000a7919 */
/* 0x000e220000002100 */
/*0060*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0xc] ; /* 0x01000300ff057624 */
/* 0x000fe400078e00ff */
/*0070*/ LDC.64 R8, c[0x4][R8] ; /* 0x0100000008087b82 */
/* 0x000e620000000a00 */
/*0080*/ S2R R13, SR_CTAID.X ; /* 0x00000000000d7919 */
/* 0x000ea20000002500 */
/*0090*/ IADD3 R2, P0, R1, c[0x0][0x20], RZ ; /* 0x0000080001027a10 */
/* 0x000fe20007f1e0ff */
/*00a0*/ IMAD.MOV.U32 R19, RZ, RZ, RZ ; /* 0x000000ffff137224 */
/* 0x000fc400078e00ff */
/*00b0*/ S2R R12, SR_TID.Z ; /* 0x00000000000c7919 */
/* 0x000ea20000002300 */
/*00c0*/ IMAD.MOV.U32 R16, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff107624 */
/* 0x000fe400078e00ff */
/*00d0*/ IMAD.X R18, RZ, RZ, c[0x0][0x24], P0 ; /* 0x00000900ff127624 */
/* 0x000fe200000e06ff */
/*00e0*/ S2R R15, SR_CTAID.Z ; /* 0x00000000000f7919 */
/* 0x000ee20000002700 */
/*00f0*/ IMAD.MOV.U32 R17, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff117624 */
/* 0x000fe400078e00ff */
/*0100*/ IMAD.MOV.U32 R6, RZ, RZ, R2 ; /* 0x000000ffff067224 */
/* 0x000fe200078e0002 */
/*0110*/ S2R R14, SR_CTAID.Y ; /* 0x00000000000e7919 */
/* 0x000ee20000002600 */
/*0120*/ IMAD.MOV.U32 R7, RZ, RZ, R18 ; /* 0x000000ffff077224 */
/* 0x000fc600078e0012 */
/*0130*/ STL.64 [R1], R10 ; /* 0x0000000a01007387 */
/* 0x0011e80000100a00 */
/*0140*/ STL.64 [R1+0x8], R12 ; /* 0x0000080c01007387 */
/* 0x0041e80000100a00 */
/*0150*/ STL.64 [R1+0x10], R14 ; /* 0x0000100e01007387 */
/* 0x0081e40000100a00 */
/*0160*/ LEPC R10 ; /* 0x00000000000a734e */
/* 0x003fe20000000000 */
/*0170*/ MOV R3, 0x1e0 ; /* 0x000001e000037802 */
/* 0x000fe40000000f00 */
/*0180*/ MOV R20, 0x160 ; /* 0x0000016000147802 */
/* 0x000fc40000000f00 */
/*0190*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*01a0*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe40000000f00 */
/*01b0*/ IADD3 R20, P0, P1, -R20, R3, R10 ; /* 0x0000000314147210 */
/* 0x000fc8000791e10a */
/*01c0*/ IADD3.X R21, ~R0, R21, R11, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e250b */
/*01d0*/ CALL.ABS.NOINC R8 ; /* 0x0000000008007343 */
/* 0x000fea0003c00000 */
/*01e0*/ ISETP.GE.AND P0, PT, R19, 0x64, PT ; /* 0x000000641300780c */
/* 0x000fe20003f06270 */
/*01f0*/ BSSY B0, 0x710 ; /* 0x0000051000007945 */
/* 0x000fe20003800000 */
/*0200*/ IMAD.MOV.U32 R0, RZ, RZ, RZ ; /* 0x000000ffff007224 */
/* 0x000fd600078e00ff */
/*0210*/ @P0 BRA 0x620 ; /* 0x0000040000000947 */
/* 0x000fea0003800000 */
/*0220*/ IADD3 R3, -R19, 0x64, RZ ; /* 0x0000006413037810 */
/* 0x000fe40007ffe1ff */
/*0230*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0f070 */
/*0240*/ ISETP.GT.AND P1, PT, R3, 0xc, PT ; /* 0x0000000c0300780c */
/* 0x000fda0003f24270 */
/*0250*/ @!P1 BRA 0x480 ; /* 0x0000022000009947 */
/* 0x000fea0003800000 */
/*0260*/ BSSY B1, 0x480 ; /* 0x0000021000017945 */
/* 0x000fe20003800000 */
/*0270*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0280*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0290*/ LDG.E.S8 R5, [R16.64] ; /* 0x0000000410057981 */
/* 0x000ea8000c1e1300 */
/*02a0*/ LDG.E.S8 R6, [R16.64+0x1] ; /* 0x0000010410067981 */
/* 0x000ea8000c1e1300 */
/*02b0*/ LDG.E.S8 R8, [R16.64+0x2] ; /* 0x0000020410087981 */
/* 0x0000e8000c1e1300 */
/*02c0*/ LDG.E.S8 R7, [R16.64+0x3] ; /* 0x0000030410077981 */
/* 0x0000e8000c1e1300 */
/*02d0*/ LDG.E.S8 R10, [R16.64+0x4] ; /* 0x00000404100a7981 */
/* 0x000128000c1e1300 */
/*02e0*/ LDG.E.S8 R9, [R16.64+0x5] ; /* 0x0000050410097981 */
/* 0x000128000c1e1300 */
/*02f0*/ LDG.E.S8 R12, [R16.64+0x6] ; /* 0x00000604100c7981 */
/* 0x000168000c1e1300 */
/*0300*/ LDG.E.S8 R11, [R16.64+0x7] ; /* 0x00000704100b7981 */
/* 0x000168000c1e1300 */
/*0310*/ LDG.E.S8 R14, [R16.64+0x8] ; /* 0x00000804100e7981 */
/* 0x000168000c1e1300 */
/*0320*/ LDG.E.S8 R13, [R16.64+0x9] ; /* 0x00000904100d7981 */
/* 0x000168000c1e1300 */
/*0330*/ LDG.E.S8 R20, [R16.64+0xa] ; /* 0x00000a0410147981 */
/* 0x000168000c1e1300 */
/*0340*/ LDG.E.S8 R15, [R16.64+0xb] ; /* 0x00000b04100f7981 */
/* 0x000168000c1e1300 */
/*0350*/ LDG.E.S8 R22, [R16.64+0xc] ; /* 0x00000c0410167981 */
/* 0x000168000c1e1300 */
/*0360*/ LDG.E.S8 R21, [R16.64+0xd] ; /* 0x00000d0410157981 */
/* 0x000168000c1e1300 */
/*0370*/ LDG.E.S8 R3, [R16.64+0xe] ; /* 0x00000e0410037981 */
/* 0x000168000c1e1300 */
/*0380*/ LDG.E.S8 R4, [R16.64+0xf] ; /* 0x00000f0410047981 */
/* 0x000162000c1e1300 */
/*0390*/ IADD3 R19, R19, 0x10, RZ ; /* 0x0000001013137810 */
/* 0x000fc80007ffe0ff */
/*03a0*/ ISETP.GE.AND P1, PT, R19, 0x58, PT ; /* 0x000000581300780c */
/* 0x000fe40003f26270 */
/*03b0*/ IADD3 R5, R6, R0, R5 ; /* 0x0000000006057210 */
/* 0x004fe40007ffe005 */
/*03c0*/ IADD3 R6, P2, R16, 0x10, RZ ; /* 0x0000001010067810 */
/* 0x000fca0007f5e0ff */
/*03d0*/ IMAD.X R17, RZ, RZ, R17, P2 ; /* 0x000000ffff117224 */
/* 0x001fe200010e0611 */
/*03e0*/ IADD3 R5, R7, R5, R8 ; /* 0x0000000507057210 */
/* 0x008fe20007ffe008 */
/*03f0*/ IMAD.MOV.U32 R16, RZ, RZ, R6 ; /* 0x000000ffff107224 */
/* 0x000fc600078e0006 */
/*0400*/ IADD3 R5, R9, R5, R10 ; /* 0x0000000509057210 */
/* 0x010fc80007ffe00a */
/*0410*/ IADD3 R5, R11, R5, R12 ; /* 0x000000050b057210 */
/* 0x020fc80007ffe00c */
/*0420*/ IADD3 R5, R13, R5, R14 ; /* 0x000000050d057210 */
/* 0x000fc80007ffe00e */
/*0430*/ IADD3 R5, R15, R5, R20 ; /* 0x000000050f057210 */
/* 0x000fc80007ffe014 */
/*0440*/ IADD3 R5, R21, R5, R22 ; /* 0x0000000515057210 */
/* 0x000fc80007ffe016 */
/*0450*/ IADD3 R0, R4, R5, R3 ; /* 0x0000000504007210 */
/* 0x000fe20007ffe003 */
/*0460*/ @!P1 BRA 0x280 ; /* 0xfffffe1000009947 */
/* 0x000fea000383ffff */
/*0470*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0480*/ IADD3 R3, -R19, 0x64, RZ ; /* 0x0000006413037810 */
/* 0x000fe20007ffe1ff */
/*0490*/ BSSY B1, 0x600 ; /* 0x0000016000017945 */
/* 0x000fe60003800000 */
/*04a0*/ ISETP.GT.AND P1, PT, R3, 0x4, PT ; /* 0x000000040300780c */
/* 0x000fda0003f24270 */
/*04b0*/ @!P1 BRA 0x5f0 ; /* 0x0000013000009947 */
/* 0x000fea0003800000 */
/*04c0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*04d0*/ LDG.E.S8 R3, [R16.64] ; /* 0x0000000410037981 */
/* 0x000ea8000c1e1300 */
/*04e0*/ LDG.E.S8 R4, [R16.64+0x1] ; /* 0x0000010410047981 */
/* 0x000ea8000c1e1300 */
/*04f0*/ LDG.E.S8 R6, [R16.64+0x2] ; /* 0x0000020410067981 */
/* 0x0000e8000c1e1300 */
/*0500*/ LDG.E.S8 R5, [R16.64+0x3] ; /* 0x0000030410057981 */
/* 0x0000e8000c1e1300 */
/*0510*/ LDG.E.S8 R8, [R16.64+0x4] ; /* 0x0000040410087981 */
/* 0x000128000c1e1300 */
/*0520*/ LDG.E.S8 R7, [R16.64+0x5] ; /* 0x0000050410077981 */
/* 0x000128000c1e1300 */
/*0530*/ LDG.E.S8 R10, [R16.64+0x6] ; /* 0x00000604100a7981 */
/* 0x000168000c1e1300 */
/*0540*/ LDG.E.S8 R9, [R16.64+0x7] ; /* 0x0000070410097981 */
/* 0x000162000c1e1300 */
/*0550*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc40003f0e170 */
/*0560*/ IADD3 R19, R19, 0x8, RZ ; /* 0x0000000813137810 */
/* 0x000fe40007ffe0ff */
/*0570*/ IADD3 R3, R4, R0, R3 ; /* 0x0000000004037210 */
/* 0x004fe40007ffe003 */
/*0580*/ IADD3 R4, P1, R16, 0x8, RZ ; /* 0x0000000810047810 */
/* 0x000fca0007f3e0ff */
/*0590*/ IMAD.MOV.U32 R16, RZ, RZ, R4 ; /* 0x000000ffff107224 */
/* 0x001fe200078e0004 */
/*05a0*/ IADD3 R3, R5, R3, R6 ; /* 0x0000000305037210 */
/* 0x008fe20007ffe006 */
/*05b0*/ IMAD.X R5, RZ, RZ, R17, P1 ; /* 0x000000ffff057224 */
/* 0x000fc800008e0611 */
/*05c0*/ IMAD.MOV.U32 R17, RZ, RZ, R5 ; /* 0x000000ffff117224 */
/* 0x000fe200078e0005 */
/*05d0*/ IADD3 R3, R7, R3, R8 ; /* 0x0000000307037210 */
/* 0x010fc80007ffe008 */
/*05e0*/ IADD3 R0, R9, R3, R10 ; /* 0x0000000309007210 */
/* 0x020fe40007ffe00a */
/*05f0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0600*/ ISETP.NE.OR P0, PT, R19, 0x64, P0 ; /* 0x000000641300780c */
/* 0x000fda0000705670 */
/*0610*/ @!P0 BRA 0x700 ; /* 0x000000e000008947 */
/* 0x000fea0003800000 */
/*0620*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0630*/ LDG.E.S8 R5, [R16.64] ; /* 0x0000000410057981 */
/* 0x0000a8000c1e1300 */
/*0640*/ LDG.E.S8 R4, [R16.64+0x1] ; /* 0x0000010410047981 */
/* 0x0000a8000c1e1300 */
/*0650*/ LDG.E.S8 R7, [R16.64+0x2] ; /* 0x0000020410077981 */
/* 0x0000e8000c1e1300 */
/*0660*/ LDG.E.S8 R6, [R16.64+0x3] ; /* 0x0000030410067981 */
/* 0x0000e2000c1e1300 */
/*0670*/ IADD3 R19, R19, 0x4, RZ ; /* 0x0000000413137810 */
/* 0x000fc40007ffe0ff */
/*0680*/ IADD3 R3, P1, R16, 0x4, RZ ; /* 0x0000000410037810 */
/* 0x000fe40007f3e0ff */
/*0690*/ ISETP.NE.AND P0, PT, R19, 0x64, PT ; /* 0x000000641300780c */
/* 0x000fc60003f05270 */
/*06a0*/ IMAD.MOV.U32 R16, RZ, RZ, R3 ; /* 0x000000ffff107224 */
/* 0x001fe200078e0003 */
/*06b0*/ IADD3 R0, R4, R0, R5 ; /* 0x0000000004007210 */
/* 0x004fe20007ffe005 */
/*06c0*/ IMAD.X R4, RZ, RZ, R17, P1 ; /* 0x000000ffff047224 */
/* 0x000fc800008e0611 */
/*06d0*/ IMAD.MOV.U32 R17, RZ, RZ, R4 ; /* 0x000000ffff117224 */
/* 0x000fe200078e0004 */
/*06e0*/ IADD3 R0, R6, R0, R7 ; /* 0x0000000006007210 */
/* 0x008fc60007ffe007 */
/*06f0*/ @P0 BRA 0x620 ; /* 0xffffff2000000947 */
/* 0x000fea000383ffff */
/*0700*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0710*/ MOV R3, 0x0 ; /* 0x0000000000037802 */
/* 0x000fe20000000f00 */
/*0720*/ STL [R1], R0 ; /* 0x0000000001007387 */
/* 0x0001e20000100800 */
/*0730*/ IMAD.MOV.U32 R6, RZ, RZ, R2 ; /* 0x000000ffff067224 */
/* 0x000fe400078e0002 */
/*0740*/ LDC.64 R8, c[0x4][R3] ; /* 0x0100000003087b82 */
/* 0x0000620000000a00 */
/*0750*/ IMAD.MOV.U32 R7, RZ, RZ, R18 ; /* 0x000000ffff077224 */
/* 0x000fe400078e0012 */
/*0760*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x10] ; /* 0x01000400ff047624 */
/* 0x000fe400078e00ff */
/*0770*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0x14] ; /* 0x01000500ff057624 */
/* 0x000fc600078e00ff */
/*0780*/ LEPC R2 ; /* 0x000000000002734e */
/* 0x001fe20000000000 */
/*0790*/ MOV R11, 0x800 ; /* 0x00000800000b7802 */
/* 0x000fc40000000f00 */
/*07a0*/ MOV R20, 0x780 ; /* 0x0000078000147802 */
/* 0x000fe40000000f00 */
/*07b0*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*07c0*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe40000000f00 */
/*07d0*/ IADD3 R20, P0, P1, -R20, R11, R2 ; /* 0x0000000b14147210 */
/* 0x000fc8000791e102 */
/*07e0*/ IADD3.X R21, ~R0, R21, R3, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2503 */
/*07f0*/ CALL.ABS.NOINC R8 ; /* 0x0000000008007343 */
/* 0x002fea0003c00000 */
/*0800*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0810*/ BRA 0x810; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0820*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0830*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0840*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0850*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0860*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0870*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0880*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0890*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected helloWorld
.globl helloWorld
.p2align 8
.type helloWorld,@function
helloWorld:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel helloWorld
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 8
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 1
.amdhsa_next_free_sgpr 1
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size helloWorld, .Lfunc_end0-helloWorld
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 8
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: helloWorld
.private_segment_fixed_size: 0
.sgpr_count: 0
.sgpr_spill_count: 0
.symbol: helloWorld.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 0
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00073957_00000000-6_test.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2059:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z30__device_stub__Z10helloWorldPcPc
.type _Z30__device_stub__Z10helloWorldPcPc, @function
_Z30__device_stub__Z10helloWorldPcPc:
.LFB2081:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq helloWorld(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2081:
.size _Z30__device_stub__Z10helloWorldPcPc, .-_Z30__device_stub__Z10helloWorldPcPc
.globl helloWorld
.type helloWorld, @function
helloWorld:
.LFB2082:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z10helloWorldPcPc
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2082:
.size helloWorld, .-helloWorld
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "helloWorld"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq helloWorld(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "test.hip"
.globl __device_stub__helloWorld # -- Begin function __device_stub__helloWorld
.p2align 4, 0x90
.type __device_stub__helloWorld,@function
__device_stub__helloWorld: # @__device_stub__helloWorld
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $helloWorld, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size __device_stub__helloWorld, .Lfunc_end0-__device_stub__helloWorld
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $helloWorld, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type helloWorld,@object # @helloWorld
.section .rodata,"a",@progbits
.globl helloWorld
.p2align 3, 0x0
helloWorld:
.quad __device_stub__helloWorld
.size helloWorld, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "helloWorld"
.size .L__unnamed_1, 11
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub__helloWorld
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym helloWorld
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | //
// Created by bruno on 2021/7/2.
//
#include <stdio.h>
__global__ void hellofromgpu(void )
{
printf("Hello World from GPU\n");
}
int main(void )
{
printf("hello from cpu\n");
hellofromgpu<<<1,10>>>();
cudaDeviceReset();
return 0;
} | code for sm_80
Function : _Z12hellofromgpuv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe20000000f00 */
/*0020*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x8] ; /* 0x01000200ff047624 */
/* 0x000fe200078e00ff */
/*0030*/ CS2R R6, SRZ ; /* 0x0000000000067805 */
/* 0x000fe2000001ff00 */
/*0040*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0xc] ; /* 0x01000300ff057624 */
/* 0x000fe200078e00ff */
/*0050*/ LDC.64 R2, c[0x4][R0] ; /* 0x0100000000027b82 */
/* 0x00006c0000000a00 */
/*0060*/ LEPC R8 ; /* 0x000000000008734e */
/* 0x000fe40000000000 */
/*0070*/ MOV R11, 0xe0 ; /* 0x000000e0000b7802 */
/* 0x000fe40000000f00 */
/*0080*/ MOV R20, 0x60 ; /* 0x0000006000147802 */
/* 0x000fe40000000f00 */
/*0090*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*00a0*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x001fc40000000f00 */
/*00b0*/ IADD3 R20, P0, P1, -R20, R11, R8 ; /* 0x0000000b14147210 */
/* 0x000fc8000791e108 */
/*00c0*/ IADD3.X R21, ~R0, R21, R9, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2509 */
/*00d0*/ CALL.ABS.NOINC R2 ; /* 0x0000000002007343 */
/* 0x002fea0003c00000 */
/*00e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00f0*/ BRA 0xf0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | //
// Created by bruno on 2021/7/2.
//
#include <stdio.h>
__global__ void hellofromgpu(void )
{
printf("Hello World from GPU\n");
}
int main(void )
{
printf("hello from cpu\n");
hellofromgpu<<<1,10>>>();
cudaDeviceReset();
return 0;
} | .file "tmpxft_0011553f_00000000-6_hello_gpu.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z31__device_stub__Z12hellofromgpuvv
.type _Z31__device_stub__Z12hellofromgpuvv, @function
_Z31__device_stub__Z12hellofromgpuvv:
.LFB2082:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z12hellofromgpuv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z31__device_stub__Z12hellofromgpuvv, .-_Z31__device_stub__Z12hellofromgpuvv
.globl _Z12hellofromgpuv
.type _Z12hellofromgpuv, @function
_Z12hellofromgpuv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z12hellofromgpuvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z12hellofromgpuv, .-_Z12hellofromgpuv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "hello from cpu\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $10, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L12:
call cudaDeviceReset@PLT
movl $0, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
call _Z31__device_stub__Z12hellofromgpuvv
jmp .L12
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z12hellofromgpuv"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z12hellofromgpuv(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | //
// Created by bruno on 2021/7/2.
//
#include <stdio.h>
__global__ void hellofromgpu(void )
{
printf("Hello World from GPU\n");
}
int main(void )
{
printf("hello from cpu\n");
hellofromgpu<<<1,10>>>();
cudaDeviceReset();
return 0;
} | //
// Created by bruno on 2021/7/2.
//
#include <hip/hip_runtime.h>
#include <stdio.h>
__global__ void hellofromgpu(void )
{
printf("Hello World from GPU\n");
}
int main(void )
{
printf("hello from cpu\n");
hellofromgpu<<<1,10>>>();
hipDeviceReset();
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | //
// Created by bruno on 2021/7/2.
//
#include <hip/hip_runtime.h>
#include <stdio.h>
__global__ void hellofromgpu(void )
{
printf("Hello World from GPU\n");
}
int main(void )
{
printf("hello from cpu\n");
hellofromgpu<<<1,10>>>();
hipDeviceReset();
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z12hellofromgpuv
.globl _Z12hellofromgpuv
.p2align 8
.type _Z12hellofromgpuv,@function
_Z12hellofromgpuv:
s_load_b64 s[2:3], s[0:1], 0x50
v_mbcnt_lo_u32_b32 v20, -1, 0
v_mov_b32_e32 v6, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_dual_mov_b32 v7, 0 :: v_dual_mov_b32 v4, v20
v_readfirstlane_b32 s0, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_eq_u32_e64 s0, s0, v4
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_6
v_mov_b32_e32 v0, 0
s_mov_b32 s4, exec_lo
s_waitcnt lgkmcnt(0)
global_load_b64 v[8:9], v0, s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
s_clause 0x1
global_load_b64 v[1:2], v0, s[2:3] offset:40
global_load_b64 v[5:6], v0, s[2:3]
s_waitcnt vmcnt(1)
v_and_b32_e32 v1, v1, v8
v_and_b32_e32 v2, v2, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_hi_u32 v3, v1, 24
v_mul_lo_u32 v2, v2, 24
v_mul_lo_u32 v1, v1, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v2, v3, v2
s_waitcnt vmcnt(0)
v_add_co_u32 v1, vcc_lo, v5, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, v6, v2, vcc_lo
global_load_b64 v[6:7], v[1:2], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[6:7], v0, v[6:9], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmpx_ne_u64_e64 v[6:7], v[8:9]
s_cbranch_execz .LBB0_5
s_mov_b32 s5, 0
.p2align 6
.LBB0_3:
s_sleep 1
s_clause 0x1
global_load_b64 v[1:2], v0, s[2:3] offset:40
global_load_b64 v[10:11], v0, s[2:3]
v_dual_mov_b32 v9, v7 :: v_dual_mov_b32 v8, v6
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_and_b32_e32 v1, v1, v8
v_and_b32_e32 v7, v2, v9
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[5:6], null, v1, 24, v[10:11]
v_mov_b32_e32 v1, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, v7, 24, v[1:2]
v_mov_b32_e32 v6, v2
global_load_b64 v[6:7], v[5:6], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[6:7], v0, v[6:9], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmp_eq_u64_e32 vcc_lo, v[6:7], v[8:9]
s_or_b32 s5, vcc_lo, s5
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s5
s_cbranch_execnz .LBB0_3
s_or_b32 exec_lo, exec_lo, s5
.LBB0_5:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s4
.LBB0_6:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s1
v_mov_b32_e32 v5, 0
v_readfirstlane_b32 s4, v6
v_readfirstlane_b32 s5, v7
s_mov_b32 s8, exec_lo
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_load_b64 v[8:9], v5, s[2:3] offset:40
global_load_b128 v[0:3], v5, s[2:3]
s_waitcnt vmcnt(1)
v_readfirstlane_b32 s6, v8
v_readfirstlane_b32 s7, v9
s_delay_alu instid0(VALU_DEP_1)
s_and_b64 s[6:7], s[4:5], s[6:7]
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_8
v_dual_mov_b32 v6, s8 :: v_dual_mov_b32 v7, 0
s_mul_i32 s8, s7, 24
s_mul_hi_u32 s9, s6, 24
v_dual_mov_b32 v8, 2 :: v_dual_mov_b32 v9, 1
s_add_i32 s9, s9, s8
s_mul_i32 s8, s6, 24
s_waitcnt vmcnt(0)
v_add_co_u32 v10, vcc_lo, v0, s8
v_add_co_ci_u32_e32 v11, vcc_lo, s9, v1, vcc_lo
global_store_b128 v[10:11], v[6:9], off offset:8
.LBB0_8:
s_or_b32 exec_lo, exec_lo, s1
s_lshl_b64 s[8:9], s[6:7], 12
v_lshlrev_b64 v[4:5], 6, v[4:5]
s_waitcnt vmcnt(0)
v_add_co_u32 v2, vcc_lo, v2, s8
v_add_co_ci_u32_e32 v7, vcc_lo, s9, v3, vcc_lo
v_mov_b32_e32 v3, 0
s_mov_b32 s8, 0
s_delay_alu instid0(VALU_DEP_3)
v_add_co_u32 v6, vcc_lo, v2, v4
v_mov_b32_e32 v2, 33
s_mov_b32 s9, s8
s_mov_b32 s10, s8
s_mov_b32 s11, s8
v_add_co_ci_u32_e32 v7, vcc_lo, v7, v5, vcc_lo
v_mov_b32_e32 v4, v3
v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v8, s8
v_dual_mov_b32 v9, s9 :: v_dual_mov_b32 v10, s10
v_mov_b32_e32 v11, s11
s_clause 0x3
global_store_b128 v[6:7], v[2:5], off
global_store_b128 v[6:7], v[8:11], off offset:16
global_store_b128 v[6:7], v[8:11], off offset:32
global_store_b128 v[6:7], v[8:11], off offset:48
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_16
v_dual_mov_b32 v10, 0 :: v_dual_mov_b32 v11, s4
v_mov_b32_e32 v12, s5
s_clause 0x1
global_load_b64 v[13:14], v10, s[2:3] offset:32 glc
global_load_b64 v[2:3], v10, s[2:3] offset:40
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s8, v2
v_readfirstlane_b32 s9, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b64 s[8:9], s[8:9], s[4:5]
s_mul_i32 s9, s9, 24
s_mul_hi_u32 s10, s8, 24
s_mul_i32 s8, s8, 24
s_add_i32 s10, s10, s9
v_add_co_u32 v8, vcc_lo, v0, s8
v_add_co_ci_u32_e32 v9, vcc_lo, s10, v1, vcc_lo
s_mov_b32 s8, exec_lo
global_store_b64 v[8:9], v[13:14], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[4:5], v10, v[11:14], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmpx_ne_u64_e64 v[4:5], v[13:14]
s_cbranch_execz .LBB0_12
s_mov_b32 s9, 0
.LBB0_11:
v_dual_mov_b32 v2, s4 :: v_dual_mov_b32 v3, s5
s_sleep 1
global_store_b64 v[8:9], v[4:5], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v10, v[2:5], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5]
v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
s_or_b32 s9, vcc_lo, s9
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s9
s_cbranch_execnz .LBB0_11
.LBB0_12:
s_or_b32 exec_lo, exec_lo, s8
v_mov_b32_e32 v2, 0
s_mov_b32 s9, exec_lo
s_mov_b32 s8, exec_lo
v_mbcnt_lo_u32_b32 v4, s9, 0
global_load_b64 v[2:3], v2, s[2:3] offset:16
v_cmpx_eq_u32_e32 0, v4
s_cbranch_execz .LBB0_14
s_bcnt1_i32_b32 s9, s9
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v5, 0 :: v_dual_mov_b32 v4, s9
s_waitcnt vmcnt(0)
global_atomic_add_u64 v[2:3], v[4:5], off offset:8
.LBB0_14:
s_or_b32 exec_lo, exec_lo, s8
s_waitcnt vmcnt(0)
global_load_b64 v[4:5], v[2:3], off offset:16
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, 0, v[4:5]
s_cbranch_vccnz .LBB0_16
global_load_b32 v2, v[2:3], off offset:24
v_mov_b32_e32 v3, 0
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s8, v2
s_waitcnt_vscnt null, 0x0
global_store_b64 v[4:5], v[2:3], off
s_and_b32 m0, s8, 0xff
s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_16:
s_or_b32 exec_lo, exec_lo, s1
s_mul_i32 s1, s7, 24
s_mul_hi_u32 s7, s6, 24
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_add_i32 s7, s7, s1
s_mul_i32 s1, s6, 24
v_add_co_u32 v0, vcc_lo, v0, s1
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v0, 20
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
s_branch .LBB0_20
.p2align 6
.LBB0_17:
s_or_b32 exec_lo, exec_lo, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s1, v2
s_cmp_eq_u32 s1, 0
s_cbranch_scc1 .LBB0_19
s_sleep 1
s_cbranch_execnz .LBB0_20
s_branch .LBB0_22
.p2align 6
.LBB0_19:
s_branch .LBB0_22
.LBB0_20:
v_mov_b32_e32 v2, 1
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_17
global_load_b32 v2, v[0:1], off glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_and_b32_e32 v2, 1, v2
s_branch .LBB0_17
.LBB0_22:
global_load_b64 v[22:23], v[6:7], off
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_26
v_mov_b32_e32 v6, 0
s_clause 0x2
global_load_b64 v[2:3], v6, s[2:3] offset:40
global_load_b64 v[7:8], v6, s[2:3] offset:24 glc
global_load_b64 v[4:5], v6, s[2:3]
s_waitcnt vmcnt(2)
v_add_co_u32 v9, vcc_lo, v2, 1
v_add_co_ci_u32_e32 v10, vcc_lo, 0, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v9, s4
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v10, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_eq_u64_e32 vcc_lo, 0, v[0:1]
v_dual_cndmask_b32 v1, v1, v10 :: v_dual_cndmask_b32 v0, v0, v9
v_and_b32_e32 v3, v1, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_and_b32_e32 v2, v0, v2
v_mul_lo_u32 v3, v3, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_hi_u32 v9, v2, 24
v_mul_lo_u32 v2, v2, 24
v_add_nc_u32_e32 v3, v9, v3
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_u32 v4, vcc_lo, v4, v2
v_mov_b32_e32 v2, v7
v_add_co_ci_u32_e32 v5, vcc_lo, v5, v3, vcc_lo
v_mov_b32_e32 v3, v8
global_store_b64 v[4:5], v[7:8], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v6, v[0:3], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_ne_u64_e32 vcc_lo, v[2:3], v[7:8]
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_26
s_mov_b32 s0, 0
.LBB0_25:
s_sleep 1
global_store_b64 v[4:5], v[2:3], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[7:8], v6, v[0:3], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[7:8], v[2:3]
v_dual_mov_b32 v2, v7 :: v_dual_mov_b32 v3, v8
s_or_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB0_25
.LBB0_26:
s_or_b32 exec_lo, exec_lo, s1
s_getpc_b64 s[4:5]
s_add_u32 s4, s4, .str@rel32@lo+4
s_addc_u32 s5, s5, .str@rel32@hi+12
s_mov_b32 s0, -1
s_cmp_lg_u64 s[4:5], 0
s_cbranch_scc0 .LBB0_105
s_waitcnt vmcnt(0)
v_dual_mov_b32 v1, v23 :: v_dual_and_b32 v0, -3, v22
v_mov_b32_e32 v25, 0
s_mov_b64 s[6:7], 22
s_branch .LBB0_29
.LBB0_28:
s_or_b32 exec_lo, exec_lo, s1
s_sub_u32 s6, s6, s8
s_subb_u32 s7, s7, s9
s_add_u32 s4, s4, s8
s_addc_u32 s5, s5, s9
s_cmp_lg_u64 s[6:7], 0
s_cbranch_scc0 .LBB0_104
.LBB0_29:
v_cmp_lt_u64_e64 s0, s[6:7], 56
s_delay_alu instid0(VALU_DEP_1)
s_and_b32 s0, s0, exec_lo
s_cselect_b32 s8, s6, 56
s_cselect_b32 s9, s7, 0
s_cmp_gt_u32 s8, 7
s_mov_b32 s0, -1
s_cbranch_scc1 .LBB0_34
v_mov_b32_e32 v2, 0
v_mov_b32_e32 v3, 0
s_cmp_eq_u32 s8, 0
s_cbranch_scc1 .LBB0_33
s_lshl_b64 s[0:1], s[8:9], 3
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], s[4:5]
.LBB0_32:
global_load_u8 v4, v25, s[12:13]
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v4
s_delay_alu instid0(VALU_DEP_1)
v_lshlrev_b64 v[4:5], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_add_u32 s12, s12, 1
s_addc_u32 s13, s13, 0
s_cmp_lg_u32 s0, s10
v_or_b32_e32 v2, v4, v2
v_or_b32_e32 v3, v5, v3
s_cbranch_scc1 .LBB0_32
.LBB0_33:
s_mov_b32 s0, 0
s_mov_b32 s15, 0
.LBB0_34:
s_and_not1_b32 vcc_lo, exec_lo, s0
s_mov_b64 s[0:1], s[4:5]
s_cbranch_vccnz .LBB0_36
global_load_b64 v[2:3], v25, s[4:5]
s_add_i32 s15, s8, -8
s_add_u32 s0, s4, 8
s_addc_u32 s1, s5, 0
.LBB0_36:
s_cmp_gt_u32 s15, 7
s_cbranch_scc1 .LBB0_41
v_mov_b32_e32 v4, 0
v_mov_b32_e32 v5, 0
s_cmp_eq_u32 s15, 0
s_cbranch_scc1 .LBB0_40
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_39:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v6, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[6:7], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s15, s12
v_or_b32_e32 v4, v6, v4
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v5, v7, v5
s_cbranch_scc1 .LBB0_39
.LBB0_40:
s_mov_b32 s14, 0
s_cbranch_execz .LBB0_42
s_branch .LBB0_43
.LBB0_41:
.LBB0_42:
global_load_b64 v[4:5], v25, s[0:1]
s_add_i32 s14, s15, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_43:
s_cmp_gt_u32 s14, 7
s_cbranch_scc1 .LBB0_48
v_mov_b32_e32 v6, 0
v_mov_b32_e32 v7, 0
s_cmp_eq_u32 s14, 0
s_cbranch_scc1 .LBB0_47
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_46:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v8, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[8:9], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s14, s12
v_or_b32_e32 v6, v8, v6
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v7, v9, v7
s_cbranch_scc1 .LBB0_46
.LBB0_47:
s_mov_b32 s15, 0
s_cbranch_execz .LBB0_49
s_branch .LBB0_50
.LBB0_48:
.LBB0_49:
global_load_b64 v[6:7], v25, s[0:1]
s_add_i32 s15, s14, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_50:
s_cmp_gt_u32 s15, 7
s_cbranch_scc1 .LBB0_55
v_mov_b32_e32 v8, 0
v_mov_b32_e32 v9, 0
s_cmp_eq_u32 s15, 0
s_cbranch_scc1 .LBB0_54
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_53:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v10, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[10:11], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s15, s12
v_or_b32_e32 v8, v10, v8
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v9, v11, v9
s_cbranch_scc1 .LBB0_53
.LBB0_54:
s_mov_b32 s14, 0
s_cbranch_execz .LBB0_56
s_branch .LBB0_57
.LBB0_55:
.LBB0_56:
global_load_b64 v[8:9], v25, s[0:1]
s_add_i32 s14, s15, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_57:
s_cmp_gt_u32 s14, 7
s_cbranch_scc1 .LBB0_62
v_mov_b32_e32 v10, 0
v_mov_b32_e32 v11, 0
s_cmp_eq_u32 s14, 0
s_cbranch_scc1 .LBB0_61
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_60:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v12, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[12:13], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s14, s12
v_or_b32_e32 v10, v12, v10
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v11, v13, v11
s_cbranch_scc1 .LBB0_60
.LBB0_61:
s_mov_b32 s15, 0
s_cbranch_execz .LBB0_63
s_branch .LBB0_64
.LBB0_62:
.LBB0_63:
global_load_b64 v[10:11], v25, s[0:1]
s_add_i32 s15, s14, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_64:
s_cmp_gt_u32 s15, 7
s_cbranch_scc1 .LBB0_69
v_mov_b32_e32 v12, 0
v_mov_b32_e32 v13, 0
s_cmp_eq_u32 s15, 0
s_cbranch_scc1 .LBB0_68
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_67:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v14, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v14
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[14:15], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s15, s12
v_or_b32_e32 v12, v14, v12
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v13, v15, v13
s_cbranch_scc1 .LBB0_67
.LBB0_68:
s_mov_b32 s14, 0
s_cbranch_execz .LBB0_70
s_branch .LBB0_71
.LBB0_69:
.LBB0_70:
global_load_b64 v[12:13], v25, s[0:1]
s_add_i32 s14, s15, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_71:
s_cmp_gt_u32 s14, 7
s_cbranch_scc1 .LBB0_76
v_mov_b32_e32 v14, 0
v_mov_b32_e32 v15, 0
s_cmp_eq_u32 s14, 0
s_cbranch_scc1 .LBB0_75
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], s[0:1]
.LBB0_74:
global_load_u8 v16, v25, s[12:13]
s_add_i32 s14, s14, -1
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v16
s_delay_alu instid0(VALU_DEP_1)
v_lshlrev_b64 v[16:17], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_add_u32 s12, s12, 1
s_addc_u32 s13, s13, 0
s_cmp_lg_u32 s14, 0
v_or_b32_e32 v14, v16, v14
v_or_b32_e32 v15, v17, v15
s_cbranch_scc1 .LBB0_74
.LBB0_75:
s_cbranch_execz .LBB0_77
s_branch .LBB0_78
.LBB0_76:
.LBB0_77:
global_load_b64 v[14:15], v25, s[0:1]
.LBB0_78:
v_mov_b32_e32 v24, v20
v_mov_b32_e32 v26, 0
v_mov_b32_e32 v27, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s0, v24
v_cmp_eq_u32_e64 s0, s0, v24
s_delay_alu instid0(VALU_DEP_1)
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_84
global_load_b64 v[18:19], v25, s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
s_clause 0x1
global_load_b64 v[16:17], v25, s[2:3] offset:40
global_load_b64 v[26:27], v25, s[2:3]
s_mov_b32 s10, exec_lo
s_waitcnt vmcnt(1)
v_and_b32_e32 v17, v17, v19
v_and_b32_e32 v16, v16, v18
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_lo_u32 v17, v17, 24
v_mul_hi_u32 v21, v16, 24
v_mul_lo_u32 v16, v16, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v17, v21, v17
s_waitcnt vmcnt(0)
v_add_co_u32 v16, vcc_lo, v26, v16
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v17, vcc_lo, v27, v17, vcc_lo
global_load_b64 v[16:17], v[16:17], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[26:27], v25, v[16:19], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmpx_ne_u64_e64 v[26:27], v[18:19]
s_cbranch_execz .LBB0_83
s_mov_b32 s11, 0
.p2align 6
.LBB0_81:
s_sleep 1
s_clause 0x1
global_load_b64 v[16:17], v25, s[2:3] offset:40
global_load_b64 v[28:29], v25, s[2:3]
v_dual_mov_b32 v18, v26 :: v_dual_mov_b32 v19, v27
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_and_b32_e32 v16, v16, v18
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[26:27], null, v16, 24, v[28:29]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mov_b32 v16, v27 :: v_dual_and_b32 v17, v17, v19
v_mad_u64_u32 v[27:28], null, v17, 24, v[16:17]
global_load_b64 v[16:17], v[26:27], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[26:27], v25, v[16:19], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmp_eq_u64_e32 vcc_lo, v[26:27], v[18:19]
s_or_b32 s11, vcc_lo, s11
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s11
s_cbranch_execnz .LBB0_81
s_or_b32 exec_lo, exec_lo, s11
.LBB0_83:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s10
.LBB0_84:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s1
s_clause 0x1
global_load_b64 v[28:29], v25, s[2:3] offset:40
global_load_b128 v[16:19], v25, s[2:3]
v_readfirstlane_b32 s10, v26
v_readfirstlane_b32 s11, v27
s_mov_b32 s14, exec_lo
s_waitcnt vmcnt(1)
v_readfirstlane_b32 s12, v28
v_readfirstlane_b32 s13, v29
s_delay_alu instid0(VALU_DEP_1)
s_and_b64 s[12:13], s[10:11], s[12:13]
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_86
v_dual_mov_b32 v26, s14 :: v_dual_mov_b32 v27, 0
s_mul_i32 s14, s13, 24
s_mul_hi_u32 s15, s12, 24
v_dual_mov_b32 v28, 2 :: v_dual_mov_b32 v29, 1
s_add_i32 s15, s15, s14
s_mul_i32 s14, s12, 24
s_waitcnt vmcnt(0)
v_add_co_u32 v30, vcc_lo, v16, s14
v_add_co_ci_u32_e32 v31, vcc_lo, s15, v17, vcc_lo
global_store_b128 v[30:31], v[26:29], off offset:8
.LBB0_86:
s_or_b32 exec_lo, exec_lo, s1
v_cmp_gt_u64_e64 vcc_lo, s[6:7], 56
v_or_b32_e32 v21, 2, v0
s_lshl_b64 s[14:15], s[12:13], 12
v_lshlrev_b64 v[26:27], 6, v[24:25]
s_lshl_b32 s1, s8, 2
s_delay_alu instid0(SALU_CYCLE_1)
s_add_i32 s1, s1, 28
v_cndmask_b32_e32 v0, v21, v0, vcc_lo
s_waitcnt vmcnt(0)
v_add_co_u32 v18, vcc_lo, v18, s14
v_add_co_ci_u32_e32 v19, vcc_lo, s15, v19, vcc_lo
s_and_b32 s1, s1, 0x1e0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_u32 v18, vcc_lo, v18, v26
v_and_or_b32 v0, v0, 0xffffff1f, s1
v_add_co_ci_u32_e32 v19, vcc_lo, v19, v27, vcc_lo
s_clause 0x3
global_store_b128 v[18:19], v[0:3], off
global_store_b128 v[18:19], v[4:7], off offset:16
global_store_b128 v[18:19], v[8:11], off offset:32
global_store_b128 v[18:19], v[12:15], off offset:48
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_94
s_clause 0x1
global_load_b64 v[8:9], v25, s[2:3] offset:32 glc
global_load_b64 v[0:1], v25, s[2:3] offset:40
v_dual_mov_b32 v6, s10 :: v_dual_mov_b32 v7, s11
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s14, v0
v_readfirstlane_b32 s15, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b64 s[14:15], s[14:15], s[10:11]
s_mul_i32 s15, s15, 24
s_mul_hi_u32 s16, s14, 24
s_mul_i32 s14, s14, 24
s_add_i32 s16, s16, s15
v_add_co_u32 v4, vcc_lo, v16, s14
v_add_co_ci_u32_e32 v5, vcc_lo, s16, v17, vcc_lo
s_mov_b32 s14, exec_lo
global_store_b64 v[4:5], v[8:9], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v25, v[6:9], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmpx_ne_u64_e64 v[2:3], v[8:9]
s_cbranch_execz .LBB0_90
s_mov_b32 s15, 0
.LBB0_89:
v_dual_mov_b32 v0, s10 :: v_dual_mov_b32 v1, s11
s_sleep 1
global_store_b64 v[4:5], v[2:3], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[0:1], v25, v[0:3], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[2:3]
v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0
s_or_b32 s15, vcc_lo, s15
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s15
s_cbranch_execnz .LBB0_89
.LBB0_90:
s_or_b32 exec_lo, exec_lo, s14
global_load_b64 v[0:1], v25, s[2:3] offset:16
s_mov_b32 s15, exec_lo
s_mov_b32 s14, exec_lo
v_mbcnt_lo_u32_b32 v2, s15, 0
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_eq_u32_e32 0, v2
s_cbranch_execz .LBB0_92
s_bcnt1_i32_b32 s15, s15
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v2, s15
s_waitcnt vmcnt(0)
global_atomic_add_u64 v[0:1], v[2:3], off offset:8
.LBB0_92:
s_or_b32 exec_lo, exec_lo, s14
s_waitcnt vmcnt(0)
global_load_b64 v[2:3], v[0:1], off offset:16
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
s_cbranch_vccnz .LBB0_94
global_load_b32 v24, v[0:1], off offset:24
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s14, v24
s_waitcnt_vscnt null, 0x0
global_store_b64 v[2:3], v[24:25], off
s_and_b32 m0, s14, 0xff
s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_94:
s_or_b32 exec_lo, exec_lo, s1
s_mul_i32 s1, s13, 24
s_mul_hi_u32 s13, s12, 24
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_add_i32 s13, s13, s1
s_mul_i32 s1, s12, 24
v_add_co_u32 v0, vcc_lo, v16, s1
v_add_co_ci_u32_e32 v1, vcc_lo, s13, v17, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v0, 20
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
s_branch .LBB0_98
.p2align 6
.LBB0_95:
s_or_b32 exec_lo, exec_lo, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s1, v2
s_cmp_eq_u32 s1, 0
s_cbranch_scc1 .LBB0_97
s_sleep 1
s_cbranch_execnz .LBB0_98
s_branch .LBB0_100
.p2align 6
.LBB0_97:
s_branch .LBB0_100
.LBB0_98:
v_mov_b32_e32 v2, 1
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_95
global_load_b32 v2, v[0:1], off glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_and_b32_e32 v2, 1, v2
s_branch .LBB0_95
.LBB0_100:
global_load_b64 v[0:1], v[18:19], off
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_28
s_clause 0x2
global_load_b64 v[4:5], v25, s[2:3] offset:40
global_load_b64 v[8:9], v25, s[2:3] offset:24 glc
global_load_b64 v[6:7], v25, s[2:3]
s_waitcnt vmcnt(2)
v_add_co_u32 v10, vcc_lo, v4, 1
v_add_co_ci_u32_e32 v11, vcc_lo, 0, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, v10, s10
v_add_co_ci_u32_e32 v3, vcc_lo, s11, v11, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
v_dual_cndmask_b32 v3, v3, v11 :: v_dual_cndmask_b32 v2, v2, v10
v_and_b32_e32 v5, v3, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_and_b32_e32 v4, v2, v4
v_mul_hi_u32 v10, v4, 24
v_mul_lo_u32 v4, v4, 24
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_add_co_u32 v6, vcc_lo, v6, v4
v_mov_b32_e32 v4, v8
v_mul_lo_u32 v5, v5, 24
v_add_nc_u32_e32 v5, v10, v5
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e32 v7, vcc_lo, v7, v5, vcc_lo
v_mov_b32_e32 v5, v9
global_store_b64 v[6:7], v[8:9], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[4:5], v25, v[2:5], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_ne_u64_e32 vcc_lo, v[4:5], v[8:9]
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_28
s_mov_b32 s0, 0
.LBB0_103:
s_sleep 1
global_store_b64 v[6:7], v[4:5], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[8:9], v25, v[2:5], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[8:9], v[4:5]
v_dual_mov_b32 v4, v8 :: v_dual_mov_b32 v5, v9
s_or_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB0_103
s_branch .LBB0_28
.LBB0_104:
s_mov_b32 s0, 0
.LBB0_105:
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 vcc_lo, exec_lo, s0
s_cbranch_vccz .LBB0_132
v_readfirstlane_b32 s0, v20
v_mov_b32_e32 v4, 0
v_mov_b32_e32 v5, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_eq_u32_e64 s0, s0, v20
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_112
s_waitcnt vmcnt(0)
v_mov_b32_e32 v0, 0
s_mov_b32 s4, exec_lo
global_load_b64 v[6:7], v0, s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
s_clause 0x1
global_load_b64 v[1:2], v0, s[2:3] offset:40
global_load_b64 v[3:4], v0, s[2:3]
s_waitcnt vmcnt(1)
v_and_b32_e32 v1, v1, v6
v_and_b32_e32 v2, v2, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_hi_u32 v5, v1, 24
v_mul_lo_u32 v2, v2, 24
v_mul_lo_u32 v1, v1, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v2, v5, v2
s_waitcnt vmcnt(0)
v_add_co_u32 v1, vcc_lo, v3, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, v4, v2, vcc_lo
global_load_b64 v[4:5], v[1:2], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[4:5], v0, v[4:7], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmpx_ne_u64_e64 v[4:5], v[6:7]
s_cbranch_execz .LBB0_111
s_mov_b32 s5, 0
.p2align 6
.LBB0_109:
s_sleep 1
s_clause 0x1
global_load_b64 v[1:2], v0, s[2:3] offset:40
global_load_b64 v[8:9], v0, s[2:3]
v_dual_mov_b32 v7, v5 :: v_dual_mov_b32 v6, v4
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_and_b32_e32 v1, v1, v6
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[3:4], null, v1, 24, v[8:9]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mov_b32 v1, v4 :: v_dual_and_b32 v2, v2, v7
v_mad_u64_u32 v[4:5], null, v2, 24, v[1:2]
global_load_b64 v[4:5], v[3:4], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[4:5], v0, v[4:7], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmp_eq_u64_e32 vcc_lo, v[4:5], v[6:7]
s_or_b32 s5, vcc_lo, s5
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s5
s_cbranch_execnz .LBB0_109
s_or_b32 exec_lo, exec_lo, s5
.LBB0_111:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s4
.LBB0_112:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s1
v_mov_b32_e32 v21, 0
v_readfirstlane_b32 s4, v4
v_readfirstlane_b32 s5, v5
s_mov_b32 s8, exec_lo
s_clause 0x1
global_load_b64 v[6:7], v21, s[2:3] offset:40
global_load_b128 v[0:3], v21, s[2:3]
s_waitcnt vmcnt(1)
v_readfirstlane_b32 s6, v6
v_readfirstlane_b32 s7, v7
s_delay_alu instid0(VALU_DEP_1)
s_and_b64 s[6:7], s[4:5], s[6:7]
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_114
v_dual_mov_b32 v4, s8 :: v_dual_mov_b32 v5, 0
s_mul_i32 s8, s7, 24
s_mul_hi_u32 s9, s6, 24
v_dual_mov_b32 v6, 2 :: v_dual_mov_b32 v7, 1
s_add_i32 s9, s9, s8
s_mul_i32 s8, s6, 24
s_waitcnt vmcnt(0)
v_add_co_u32 v8, vcc_lo, v0, s8
v_add_co_ci_u32_e32 v9, vcc_lo, s9, v1, vcc_lo
global_store_b128 v[8:9], v[4:7], off offset:8
.LBB0_114:
s_or_b32 exec_lo, exec_lo, s1
s_lshl_b64 s[8:9], s[6:7], 12
v_and_or_b32 v22, v22, 0xffffff1d, 34
s_waitcnt vmcnt(0)
v_add_co_u32 v4, vcc_lo, v2, s8
v_add_co_ci_u32_e32 v5, vcc_lo, s9, v3, vcc_lo
v_lshlrev_b64 v[2:3], 6, v[20:21]
s_mov_b32 s8, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
s_mov_b32 s9, s8
s_mov_b32 s10, s8
s_mov_b32 s11, s8
v_add_co_u32 v8, vcc_lo, v4, v2
v_mov_b32_e32 v6, 0
v_add_co_ci_u32_e32 v9, vcc_lo, v5, v3, vcc_lo
v_dual_mov_b32 v2, s8 :: v_dual_mov_b32 v5, s11
v_dual_mov_b32 v3, s9 :: v_dual_mov_b32 v4, s10
s_delay_alu instid0(VALU_DEP_4)
v_mov_b32_e32 v7, v6
s_clause 0x4
global_store_b64 v[8:9], v[22:23], off
global_store_b128 v[8:9], v[2:5], off offset:8
global_store_b128 v[8:9], v[2:5], off offset:24
global_store_b128 v[8:9], v[2:5], off offset:40
global_store_b64 v[8:9], v[6:7], off offset:56
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_122
v_dual_mov_b32 v8, 0 :: v_dual_mov_b32 v9, s4
v_mov_b32_e32 v10, s5
s_clause 0x1
global_load_b64 v[11:12], v8, s[2:3] offset:32 glc
global_load_b64 v[2:3], v8, s[2:3] offset:40
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s8, v2
v_readfirstlane_b32 s9, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b64 s[8:9], s[8:9], s[4:5]
s_mul_i32 s9, s9, 24
s_mul_hi_u32 s10, s8, 24
s_mul_i32 s8, s8, 24
s_add_i32 s10, s10, s9
v_add_co_u32 v6, vcc_lo, v0, s8
v_add_co_ci_u32_e32 v7, vcc_lo, s10, v1, vcc_lo
s_mov_b32 s8, exec_lo
global_store_b64 v[6:7], v[11:12], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[4:5], v8, v[9:12], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmpx_ne_u64_e64 v[4:5], v[11:12]
s_cbranch_execz .LBB0_118
s_mov_b32 s9, 0
.LBB0_117:
v_dual_mov_b32 v2, s4 :: v_dual_mov_b32 v3, s5
s_sleep 1
global_store_b64 v[6:7], v[4:5], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v8, v[2:5], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5]
v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
s_or_b32 s9, vcc_lo, s9
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s9
s_cbranch_execnz .LBB0_117
.LBB0_118:
s_or_b32 exec_lo, exec_lo, s8
v_mov_b32_e32 v2, 0
s_mov_b32 s9, exec_lo
s_mov_b32 s8, exec_lo
v_mbcnt_lo_u32_b32 v4, s9, 0
global_load_b64 v[2:3], v2, s[2:3] offset:16
v_cmpx_eq_u32_e32 0, v4
s_cbranch_execz .LBB0_120
s_bcnt1_i32_b32 s9, s9
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v5, 0 :: v_dual_mov_b32 v4, s9
s_waitcnt vmcnt(0)
global_atomic_add_u64 v[2:3], v[4:5], off offset:8
.LBB0_120:
s_or_b32 exec_lo, exec_lo, s8
s_waitcnt vmcnt(0)
global_load_b64 v[4:5], v[2:3], off offset:16
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, 0, v[4:5]
s_cbranch_vccnz .LBB0_122
global_load_b32 v2, v[2:3], off offset:24
v_mov_b32_e32 v3, 0
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s8, v2
s_waitcnt_vscnt null, 0x0
global_store_b64 v[4:5], v[2:3], off
s_and_b32 m0, s8, 0xff
s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_122:
s_or_b32 exec_lo, exec_lo, s1
s_mul_i32 s1, s7, 24
s_mul_hi_u32 s7, s6, 24
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_add_i32 s7, s7, s1
s_mul_i32 s1, s6, 24
v_add_co_u32 v0, vcc_lo, v0, s1
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v0, 20
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
s_branch .LBB0_126
.p2align 6
.LBB0_123:
s_or_b32 exec_lo, exec_lo, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s1, v2
s_cmp_eq_u32 s1, 0
s_cbranch_scc1 .LBB0_125
s_sleep 1
s_cbranch_execnz .LBB0_126
s_branch .LBB0_128
.p2align 6
.LBB0_125:
s_branch .LBB0_128
.LBB0_126:
v_mov_b32_e32 v2, 1
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_123
global_load_b32 v2, v[0:1], off glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_and_b32_e32 v2, 1, v2
s_branch .LBB0_123
.LBB0_128:
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_132
v_mov_b32_e32 v6, 0
s_clause 0x2
global_load_b64 v[2:3], v6, s[2:3] offset:40
global_load_b64 v[7:8], v6, s[2:3] offset:24 glc
global_load_b64 v[4:5], v6, s[2:3]
s_waitcnt vmcnt(2)
v_add_co_u32 v9, vcc_lo, v2, 1
v_add_co_ci_u32_e32 v10, vcc_lo, 0, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v9, s4
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v10, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_eq_u64_e32 vcc_lo, 0, v[0:1]
v_dual_cndmask_b32 v1, v1, v10 :: v_dual_cndmask_b32 v0, v0, v9
v_and_b32_e32 v3, v1, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_and_b32_e32 v2, v0, v2
v_mul_lo_u32 v3, v3, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_hi_u32 v9, v2, 24
v_mul_lo_u32 v2, v2, 24
v_add_nc_u32_e32 v3, v9, v3
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_u32 v4, vcc_lo, v4, v2
v_mov_b32_e32 v2, v7
v_add_co_ci_u32_e32 v5, vcc_lo, v5, v3, vcc_lo
v_mov_b32_e32 v3, v8
global_store_b64 v[4:5], v[7:8], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v6, v[0:3], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_ne_u64_e32 vcc_lo, v[2:3], v[7:8]
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_132
s_mov_b32 s0, 0
.LBB0_131:
s_sleep 1
global_store_b64 v[4:5], v[2:3], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[7:8], v6, v[0:3], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[7:8], v[2:3]
v_dual_mov_b32 v2, v7 :: v_dual_mov_b32 v3, v8
s_or_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB0_131
.LBB0_132:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12hellofromgpuv
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 256
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 32
.amdhsa_next_free_sgpr 18
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z12hellofromgpuv, .Lfunc_end0-_Z12hellofromgpuv
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type .str,@object
.section .rodata.str1.1,"aMS",@progbits,1
.str:
.asciz "Hello World from GPU\n"
.size .str, 22
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: hidden_block_count_x
- .offset: 4
.size: 4
.value_kind: hidden_block_count_y
- .offset: 8
.size: 4
.value_kind: hidden_block_count_z
- .offset: 12
.size: 2
.value_kind: hidden_group_size_x
- .offset: 14
.size: 2
.value_kind: hidden_group_size_y
- .offset: 16
.size: 2
.value_kind: hidden_group_size_z
- .offset: 18
.size: 2
.value_kind: hidden_remainder_x
- .offset: 20
.size: 2
.value_kind: hidden_remainder_y
- .offset: 22
.size: 2
.value_kind: hidden_remainder_z
- .offset: 40
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 48
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 64
.size: 2
.value_kind: hidden_grid_dims
- .offset: 80
.size: 8
.value_kind: hidden_hostcall_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 256
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12hellofromgpuv
.private_segment_fixed_size: 0
.sgpr_count: 20
.sgpr_spill_count: 0
.symbol: _Z12hellofromgpuv.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 32
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | //
// Created by bruno on 2021/7/2.
//
#include <hip/hip_runtime.h>
#include <stdio.h>
__global__ void hellofromgpu(void )
{
printf("Hello World from GPU\n");
}
int main(void )
{
printf("hello from cpu\n");
hellofromgpu<<<1,10>>>();
hipDeviceReset();
return 0;
} | .text
.file "hello_gpu.hip"
.globl _Z27__device_stub__hellofromgpuv # -- Begin function _Z27__device_stub__hellofromgpuv
.p2align 4, 0x90
.type _Z27__device_stub__hellofromgpuv,@function
_Z27__device_stub__hellofromgpuv: # @_Z27__device_stub__hellofromgpuv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z12hellofromgpuv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z27__device_stub__hellofromgpuv, .Lfunc_end0-_Z27__device_stub__hellofromgpuv
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
movl $.Lstr, %edi
callq puts@PLT
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 9(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z12hellofromgpuv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
callq hipDeviceReset
xorl %eax, %eax
addq $56, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12hellofromgpuv, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z12hellofromgpuv,@object # @_Z12hellofromgpuv
.section .rodata,"a",@progbits
.globl _Z12hellofromgpuv
.p2align 3, 0x0
_Z12hellofromgpuv:
.quad _Z27__device_stub__hellofromgpuv
.size _Z12hellofromgpuv, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z12hellofromgpuv"
.size .L__unnamed_1, 18
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "hello from cpu"
.size .Lstr, 15
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__hellofromgpuv
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12hellofromgpuv
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z12hellofromgpuv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe20000000f00 */
/*0020*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x8] ; /* 0x01000200ff047624 */
/* 0x000fe200078e00ff */
/*0030*/ CS2R R6, SRZ ; /* 0x0000000000067805 */
/* 0x000fe2000001ff00 */
/*0040*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0xc] ; /* 0x01000300ff057624 */
/* 0x000fe200078e00ff */
/*0050*/ LDC.64 R2, c[0x4][R0] ; /* 0x0100000000027b82 */
/* 0x00006c0000000a00 */
/*0060*/ LEPC R8 ; /* 0x000000000008734e */
/* 0x000fe40000000000 */
/*0070*/ MOV R11, 0xe0 ; /* 0x000000e0000b7802 */
/* 0x000fe40000000f00 */
/*0080*/ MOV R20, 0x60 ; /* 0x0000006000147802 */
/* 0x000fe40000000f00 */
/*0090*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*00a0*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x001fc40000000f00 */
/*00b0*/ IADD3 R20, P0, P1, -R20, R11, R8 ; /* 0x0000000b14147210 */
/* 0x000fc8000791e108 */
/*00c0*/ IADD3.X R21, ~R0, R21, R9, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2509 */
/*00d0*/ CALL.ABS.NOINC R2 ; /* 0x0000000002007343 */
/* 0x002fea0003c00000 */
/*00e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00f0*/ BRA 0xf0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z12hellofromgpuv
.globl _Z12hellofromgpuv
.p2align 8
.type _Z12hellofromgpuv,@function
_Z12hellofromgpuv:
s_load_b64 s[2:3], s[0:1], 0x50
v_mbcnt_lo_u32_b32 v20, -1, 0
v_mov_b32_e32 v6, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_dual_mov_b32 v7, 0 :: v_dual_mov_b32 v4, v20
v_readfirstlane_b32 s0, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_eq_u32_e64 s0, s0, v4
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_6
v_mov_b32_e32 v0, 0
s_mov_b32 s4, exec_lo
s_waitcnt lgkmcnt(0)
global_load_b64 v[8:9], v0, s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
s_clause 0x1
global_load_b64 v[1:2], v0, s[2:3] offset:40
global_load_b64 v[5:6], v0, s[2:3]
s_waitcnt vmcnt(1)
v_and_b32_e32 v1, v1, v8
v_and_b32_e32 v2, v2, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_hi_u32 v3, v1, 24
v_mul_lo_u32 v2, v2, 24
v_mul_lo_u32 v1, v1, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v2, v3, v2
s_waitcnt vmcnt(0)
v_add_co_u32 v1, vcc_lo, v5, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, v6, v2, vcc_lo
global_load_b64 v[6:7], v[1:2], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[6:7], v0, v[6:9], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmpx_ne_u64_e64 v[6:7], v[8:9]
s_cbranch_execz .LBB0_5
s_mov_b32 s5, 0
.p2align 6
.LBB0_3:
s_sleep 1
s_clause 0x1
global_load_b64 v[1:2], v0, s[2:3] offset:40
global_load_b64 v[10:11], v0, s[2:3]
v_dual_mov_b32 v9, v7 :: v_dual_mov_b32 v8, v6
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_and_b32_e32 v1, v1, v8
v_and_b32_e32 v7, v2, v9
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[5:6], null, v1, 24, v[10:11]
v_mov_b32_e32 v1, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, v7, 24, v[1:2]
v_mov_b32_e32 v6, v2
global_load_b64 v[6:7], v[5:6], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[6:7], v0, v[6:9], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmp_eq_u64_e32 vcc_lo, v[6:7], v[8:9]
s_or_b32 s5, vcc_lo, s5
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s5
s_cbranch_execnz .LBB0_3
s_or_b32 exec_lo, exec_lo, s5
.LBB0_5:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s4
.LBB0_6:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s1
v_mov_b32_e32 v5, 0
v_readfirstlane_b32 s4, v6
v_readfirstlane_b32 s5, v7
s_mov_b32 s8, exec_lo
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_load_b64 v[8:9], v5, s[2:3] offset:40
global_load_b128 v[0:3], v5, s[2:3]
s_waitcnt vmcnt(1)
v_readfirstlane_b32 s6, v8
v_readfirstlane_b32 s7, v9
s_delay_alu instid0(VALU_DEP_1)
s_and_b64 s[6:7], s[4:5], s[6:7]
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_8
v_dual_mov_b32 v6, s8 :: v_dual_mov_b32 v7, 0
s_mul_i32 s8, s7, 24
s_mul_hi_u32 s9, s6, 24
v_dual_mov_b32 v8, 2 :: v_dual_mov_b32 v9, 1
s_add_i32 s9, s9, s8
s_mul_i32 s8, s6, 24
s_waitcnt vmcnt(0)
v_add_co_u32 v10, vcc_lo, v0, s8
v_add_co_ci_u32_e32 v11, vcc_lo, s9, v1, vcc_lo
global_store_b128 v[10:11], v[6:9], off offset:8
.LBB0_8:
s_or_b32 exec_lo, exec_lo, s1
s_lshl_b64 s[8:9], s[6:7], 12
v_lshlrev_b64 v[4:5], 6, v[4:5]
s_waitcnt vmcnt(0)
v_add_co_u32 v2, vcc_lo, v2, s8
v_add_co_ci_u32_e32 v7, vcc_lo, s9, v3, vcc_lo
v_mov_b32_e32 v3, 0
s_mov_b32 s8, 0
s_delay_alu instid0(VALU_DEP_3)
v_add_co_u32 v6, vcc_lo, v2, v4
v_mov_b32_e32 v2, 33
s_mov_b32 s9, s8
s_mov_b32 s10, s8
s_mov_b32 s11, s8
v_add_co_ci_u32_e32 v7, vcc_lo, v7, v5, vcc_lo
v_mov_b32_e32 v4, v3
v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v8, s8
v_dual_mov_b32 v9, s9 :: v_dual_mov_b32 v10, s10
v_mov_b32_e32 v11, s11
s_clause 0x3
global_store_b128 v[6:7], v[2:5], off
global_store_b128 v[6:7], v[8:11], off offset:16
global_store_b128 v[6:7], v[8:11], off offset:32
global_store_b128 v[6:7], v[8:11], off offset:48
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_16
v_dual_mov_b32 v10, 0 :: v_dual_mov_b32 v11, s4
v_mov_b32_e32 v12, s5
s_clause 0x1
global_load_b64 v[13:14], v10, s[2:3] offset:32 glc
global_load_b64 v[2:3], v10, s[2:3] offset:40
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s8, v2
v_readfirstlane_b32 s9, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b64 s[8:9], s[8:9], s[4:5]
s_mul_i32 s9, s9, 24
s_mul_hi_u32 s10, s8, 24
s_mul_i32 s8, s8, 24
s_add_i32 s10, s10, s9
v_add_co_u32 v8, vcc_lo, v0, s8
v_add_co_ci_u32_e32 v9, vcc_lo, s10, v1, vcc_lo
s_mov_b32 s8, exec_lo
global_store_b64 v[8:9], v[13:14], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[4:5], v10, v[11:14], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmpx_ne_u64_e64 v[4:5], v[13:14]
s_cbranch_execz .LBB0_12
s_mov_b32 s9, 0
.LBB0_11:
v_dual_mov_b32 v2, s4 :: v_dual_mov_b32 v3, s5
s_sleep 1
global_store_b64 v[8:9], v[4:5], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v10, v[2:5], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5]
v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
s_or_b32 s9, vcc_lo, s9
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s9
s_cbranch_execnz .LBB0_11
.LBB0_12:
s_or_b32 exec_lo, exec_lo, s8
v_mov_b32_e32 v2, 0
s_mov_b32 s9, exec_lo
s_mov_b32 s8, exec_lo
v_mbcnt_lo_u32_b32 v4, s9, 0
global_load_b64 v[2:3], v2, s[2:3] offset:16
v_cmpx_eq_u32_e32 0, v4
s_cbranch_execz .LBB0_14
s_bcnt1_i32_b32 s9, s9
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v5, 0 :: v_dual_mov_b32 v4, s9
s_waitcnt vmcnt(0)
global_atomic_add_u64 v[2:3], v[4:5], off offset:8
.LBB0_14:
s_or_b32 exec_lo, exec_lo, s8
s_waitcnt vmcnt(0)
global_load_b64 v[4:5], v[2:3], off offset:16
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, 0, v[4:5]
s_cbranch_vccnz .LBB0_16
global_load_b32 v2, v[2:3], off offset:24
v_mov_b32_e32 v3, 0
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s8, v2
s_waitcnt_vscnt null, 0x0
global_store_b64 v[4:5], v[2:3], off
s_and_b32 m0, s8, 0xff
s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_16:
s_or_b32 exec_lo, exec_lo, s1
s_mul_i32 s1, s7, 24
s_mul_hi_u32 s7, s6, 24
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_add_i32 s7, s7, s1
s_mul_i32 s1, s6, 24
v_add_co_u32 v0, vcc_lo, v0, s1
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v0, 20
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
s_branch .LBB0_20
.p2align 6
.LBB0_17:
s_or_b32 exec_lo, exec_lo, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s1, v2
s_cmp_eq_u32 s1, 0
s_cbranch_scc1 .LBB0_19
s_sleep 1
s_cbranch_execnz .LBB0_20
s_branch .LBB0_22
.p2align 6
.LBB0_19:
s_branch .LBB0_22
.LBB0_20:
v_mov_b32_e32 v2, 1
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_17
global_load_b32 v2, v[0:1], off glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_and_b32_e32 v2, 1, v2
s_branch .LBB0_17
.LBB0_22:
global_load_b64 v[22:23], v[6:7], off
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_26
v_mov_b32_e32 v6, 0
s_clause 0x2
global_load_b64 v[2:3], v6, s[2:3] offset:40
global_load_b64 v[7:8], v6, s[2:3] offset:24 glc
global_load_b64 v[4:5], v6, s[2:3]
s_waitcnt vmcnt(2)
v_add_co_u32 v9, vcc_lo, v2, 1
v_add_co_ci_u32_e32 v10, vcc_lo, 0, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v9, s4
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v10, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_eq_u64_e32 vcc_lo, 0, v[0:1]
v_dual_cndmask_b32 v1, v1, v10 :: v_dual_cndmask_b32 v0, v0, v9
v_and_b32_e32 v3, v1, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_and_b32_e32 v2, v0, v2
v_mul_lo_u32 v3, v3, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_hi_u32 v9, v2, 24
v_mul_lo_u32 v2, v2, 24
v_add_nc_u32_e32 v3, v9, v3
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_u32 v4, vcc_lo, v4, v2
v_mov_b32_e32 v2, v7
v_add_co_ci_u32_e32 v5, vcc_lo, v5, v3, vcc_lo
v_mov_b32_e32 v3, v8
global_store_b64 v[4:5], v[7:8], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v6, v[0:3], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_ne_u64_e32 vcc_lo, v[2:3], v[7:8]
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_26
s_mov_b32 s0, 0
.LBB0_25:
s_sleep 1
global_store_b64 v[4:5], v[2:3], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[7:8], v6, v[0:3], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[7:8], v[2:3]
v_dual_mov_b32 v2, v7 :: v_dual_mov_b32 v3, v8
s_or_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB0_25
.LBB0_26:
s_or_b32 exec_lo, exec_lo, s1
s_getpc_b64 s[4:5]
s_add_u32 s4, s4, .str@rel32@lo+4
s_addc_u32 s5, s5, .str@rel32@hi+12
s_mov_b32 s0, -1
s_cmp_lg_u64 s[4:5], 0
s_cbranch_scc0 .LBB0_105
s_waitcnt vmcnt(0)
v_dual_mov_b32 v1, v23 :: v_dual_and_b32 v0, -3, v22
v_mov_b32_e32 v25, 0
s_mov_b64 s[6:7], 22
s_branch .LBB0_29
.LBB0_28:
s_or_b32 exec_lo, exec_lo, s1
s_sub_u32 s6, s6, s8
s_subb_u32 s7, s7, s9
s_add_u32 s4, s4, s8
s_addc_u32 s5, s5, s9
s_cmp_lg_u64 s[6:7], 0
s_cbranch_scc0 .LBB0_104
.LBB0_29:
v_cmp_lt_u64_e64 s0, s[6:7], 56
s_delay_alu instid0(VALU_DEP_1)
s_and_b32 s0, s0, exec_lo
s_cselect_b32 s8, s6, 56
s_cselect_b32 s9, s7, 0
s_cmp_gt_u32 s8, 7
s_mov_b32 s0, -1
s_cbranch_scc1 .LBB0_34
v_mov_b32_e32 v2, 0
v_mov_b32_e32 v3, 0
s_cmp_eq_u32 s8, 0
s_cbranch_scc1 .LBB0_33
s_lshl_b64 s[0:1], s[8:9], 3
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], s[4:5]
.LBB0_32:
global_load_u8 v4, v25, s[12:13]
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v4
s_delay_alu instid0(VALU_DEP_1)
v_lshlrev_b64 v[4:5], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_add_u32 s12, s12, 1
s_addc_u32 s13, s13, 0
s_cmp_lg_u32 s0, s10
v_or_b32_e32 v2, v4, v2
v_or_b32_e32 v3, v5, v3
s_cbranch_scc1 .LBB0_32
.LBB0_33:
s_mov_b32 s0, 0
s_mov_b32 s15, 0
.LBB0_34:
s_and_not1_b32 vcc_lo, exec_lo, s0
s_mov_b64 s[0:1], s[4:5]
s_cbranch_vccnz .LBB0_36
global_load_b64 v[2:3], v25, s[4:5]
s_add_i32 s15, s8, -8
s_add_u32 s0, s4, 8
s_addc_u32 s1, s5, 0
.LBB0_36:
s_cmp_gt_u32 s15, 7
s_cbranch_scc1 .LBB0_41
v_mov_b32_e32 v4, 0
v_mov_b32_e32 v5, 0
s_cmp_eq_u32 s15, 0
s_cbranch_scc1 .LBB0_40
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_39:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v6, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[6:7], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s15, s12
v_or_b32_e32 v4, v6, v4
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v5, v7, v5
s_cbranch_scc1 .LBB0_39
.LBB0_40:
s_mov_b32 s14, 0
s_cbranch_execz .LBB0_42
s_branch .LBB0_43
.LBB0_41:
.LBB0_42:
global_load_b64 v[4:5], v25, s[0:1]
s_add_i32 s14, s15, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_43:
s_cmp_gt_u32 s14, 7
s_cbranch_scc1 .LBB0_48
v_mov_b32_e32 v6, 0
v_mov_b32_e32 v7, 0
s_cmp_eq_u32 s14, 0
s_cbranch_scc1 .LBB0_47
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_46:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v8, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[8:9], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s14, s12
v_or_b32_e32 v6, v8, v6
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v7, v9, v7
s_cbranch_scc1 .LBB0_46
.LBB0_47:
s_mov_b32 s15, 0
s_cbranch_execz .LBB0_49
s_branch .LBB0_50
.LBB0_48:
.LBB0_49:
global_load_b64 v[6:7], v25, s[0:1]
s_add_i32 s15, s14, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_50:
s_cmp_gt_u32 s15, 7
s_cbranch_scc1 .LBB0_55
v_mov_b32_e32 v8, 0
v_mov_b32_e32 v9, 0
s_cmp_eq_u32 s15, 0
s_cbranch_scc1 .LBB0_54
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_53:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v10, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[10:11], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s15, s12
v_or_b32_e32 v8, v10, v8
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v9, v11, v9
s_cbranch_scc1 .LBB0_53
.LBB0_54:
s_mov_b32 s14, 0
s_cbranch_execz .LBB0_56
s_branch .LBB0_57
.LBB0_55:
.LBB0_56:
global_load_b64 v[8:9], v25, s[0:1]
s_add_i32 s14, s15, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_57:
s_cmp_gt_u32 s14, 7
s_cbranch_scc1 .LBB0_62
v_mov_b32_e32 v10, 0
v_mov_b32_e32 v11, 0
s_cmp_eq_u32 s14, 0
s_cbranch_scc1 .LBB0_61
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_60:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v12, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[12:13], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s14, s12
v_or_b32_e32 v10, v12, v10
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v11, v13, v11
s_cbranch_scc1 .LBB0_60
.LBB0_61:
s_mov_b32 s15, 0
s_cbranch_execz .LBB0_63
s_branch .LBB0_64
.LBB0_62:
.LBB0_63:
global_load_b64 v[10:11], v25, s[0:1]
s_add_i32 s15, s14, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_64:
s_cmp_gt_u32 s15, 7
s_cbranch_scc1 .LBB0_69
v_mov_b32_e32 v12, 0
v_mov_b32_e32 v13, 0
s_cmp_eq_u32 s15, 0
s_cbranch_scc1 .LBB0_68
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_67:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v14, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v14
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[14:15], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s15, s12
v_or_b32_e32 v12, v14, v12
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v13, v15, v13
s_cbranch_scc1 .LBB0_67
.LBB0_68:
s_mov_b32 s14, 0
s_cbranch_execz .LBB0_70
s_branch .LBB0_71
.LBB0_69:
.LBB0_70:
global_load_b64 v[12:13], v25, s[0:1]
s_add_i32 s14, s15, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_71:
s_cmp_gt_u32 s14, 7
s_cbranch_scc1 .LBB0_76
v_mov_b32_e32 v14, 0
v_mov_b32_e32 v15, 0
s_cmp_eq_u32 s14, 0
s_cbranch_scc1 .LBB0_75
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], s[0:1]
.LBB0_74:
global_load_u8 v16, v25, s[12:13]
s_add_i32 s14, s14, -1
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v16
s_delay_alu instid0(VALU_DEP_1)
v_lshlrev_b64 v[16:17], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_add_u32 s12, s12, 1
s_addc_u32 s13, s13, 0
s_cmp_lg_u32 s14, 0
v_or_b32_e32 v14, v16, v14
v_or_b32_e32 v15, v17, v15
s_cbranch_scc1 .LBB0_74
.LBB0_75:
s_cbranch_execz .LBB0_77
s_branch .LBB0_78
.LBB0_76:
.LBB0_77:
global_load_b64 v[14:15], v25, s[0:1]
.LBB0_78:
v_mov_b32_e32 v24, v20
v_mov_b32_e32 v26, 0
v_mov_b32_e32 v27, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s0, v24
v_cmp_eq_u32_e64 s0, s0, v24
s_delay_alu instid0(VALU_DEP_1)
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_84
global_load_b64 v[18:19], v25, s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
s_clause 0x1
global_load_b64 v[16:17], v25, s[2:3] offset:40
global_load_b64 v[26:27], v25, s[2:3]
s_mov_b32 s10, exec_lo
s_waitcnt vmcnt(1)
v_and_b32_e32 v17, v17, v19
v_and_b32_e32 v16, v16, v18
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_lo_u32 v17, v17, 24
v_mul_hi_u32 v21, v16, 24
v_mul_lo_u32 v16, v16, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v17, v21, v17
s_waitcnt vmcnt(0)
v_add_co_u32 v16, vcc_lo, v26, v16
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v17, vcc_lo, v27, v17, vcc_lo
global_load_b64 v[16:17], v[16:17], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[26:27], v25, v[16:19], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmpx_ne_u64_e64 v[26:27], v[18:19]
s_cbranch_execz .LBB0_83
s_mov_b32 s11, 0
.p2align 6
.LBB0_81:
s_sleep 1
s_clause 0x1
global_load_b64 v[16:17], v25, s[2:3] offset:40
global_load_b64 v[28:29], v25, s[2:3]
v_dual_mov_b32 v18, v26 :: v_dual_mov_b32 v19, v27
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_and_b32_e32 v16, v16, v18
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[26:27], null, v16, 24, v[28:29]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mov_b32 v16, v27 :: v_dual_and_b32 v17, v17, v19
v_mad_u64_u32 v[27:28], null, v17, 24, v[16:17]
global_load_b64 v[16:17], v[26:27], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[26:27], v25, v[16:19], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmp_eq_u64_e32 vcc_lo, v[26:27], v[18:19]
s_or_b32 s11, vcc_lo, s11
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s11
s_cbranch_execnz .LBB0_81
s_or_b32 exec_lo, exec_lo, s11
.LBB0_83:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s10
.LBB0_84:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s1
s_clause 0x1
global_load_b64 v[28:29], v25, s[2:3] offset:40
global_load_b128 v[16:19], v25, s[2:3]
v_readfirstlane_b32 s10, v26
v_readfirstlane_b32 s11, v27
s_mov_b32 s14, exec_lo
s_waitcnt vmcnt(1)
v_readfirstlane_b32 s12, v28
v_readfirstlane_b32 s13, v29
s_delay_alu instid0(VALU_DEP_1)
s_and_b64 s[12:13], s[10:11], s[12:13]
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_86
v_dual_mov_b32 v26, s14 :: v_dual_mov_b32 v27, 0
s_mul_i32 s14, s13, 24
s_mul_hi_u32 s15, s12, 24
v_dual_mov_b32 v28, 2 :: v_dual_mov_b32 v29, 1
s_add_i32 s15, s15, s14
s_mul_i32 s14, s12, 24
s_waitcnt vmcnt(0)
v_add_co_u32 v30, vcc_lo, v16, s14
v_add_co_ci_u32_e32 v31, vcc_lo, s15, v17, vcc_lo
global_store_b128 v[30:31], v[26:29], off offset:8
.LBB0_86:
s_or_b32 exec_lo, exec_lo, s1
v_cmp_gt_u64_e64 vcc_lo, s[6:7], 56
v_or_b32_e32 v21, 2, v0
s_lshl_b64 s[14:15], s[12:13], 12
v_lshlrev_b64 v[26:27], 6, v[24:25]
s_lshl_b32 s1, s8, 2
s_delay_alu instid0(SALU_CYCLE_1)
s_add_i32 s1, s1, 28
v_cndmask_b32_e32 v0, v21, v0, vcc_lo
s_waitcnt vmcnt(0)
v_add_co_u32 v18, vcc_lo, v18, s14
v_add_co_ci_u32_e32 v19, vcc_lo, s15, v19, vcc_lo
s_and_b32 s1, s1, 0x1e0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_u32 v18, vcc_lo, v18, v26
v_and_or_b32 v0, v0, 0xffffff1f, s1
v_add_co_ci_u32_e32 v19, vcc_lo, v19, v27, vcc_lo
s_clause 0x3
global_store_b128 v[18:19], v[0:3], off
global_store_b128 v[18:19], v[4:7], off offset:16
global_store_b128 v[18:19], v[8:11], off offset:32
global_store_b128 v[18:19], v[12:15], off offset:48
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_94
s_clause 0x1
global_load_b64 v[8:9], v25, s[2:3] offset:32 glc
global_load_b64 v[0:1], v25, s[2:3] offset:40
v_dual_mov_b32 v6, s10 :: v_dual_mov_b32 v7, s11
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s14, v0
v_readfirstlane_b32 s15, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b64 s[14:15], s[14:15], s[10:11]
s_mul_i32 s15, s15, 24
s_mul_hi_u32 s16, s14, 24
s_mul_i32 s14, s14, 24
s_add_i32 s16, s16, s15
v_add_co_u32 v4, vcc_lo, v16, s14
v_add_co_ci_u32_e32 v5, vcc_lo, s16, v17, vcc_lo
s_mov_b32 s14, exec_lo
global_store_b64 v[4:5], v[8:9], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v25, v[6:9], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmpx_ne_u64_e64 v[2:3], v[8:9]
s_cbranch_execz .LBB0_90
s_mov_b32 s15, 0
.LBB0_89:
v_dual_mov_b32 v0, s10 :: v_dual_mov_b32 v1, s11
s_sleep 1
global_store_b64 v[4:5], v[2:3], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[0:1], v25, v[0:3], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[2:3]
v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0
s_or_b32 s15, vcc_lo, s15
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s15
s_cbranch_execnz .LBB0_89
.LBB0_90:
s_or_b32 exec_lo, exec_lo, s14
global_load_b64 v[0:1], v25, s[2:3] offset:16
s_mov_b32 s15, exec_lo
s_mov_b32 s14, exec_lo
v_mbcnt_lo_u32_b32 v2, s15, 0
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_eq_u32_e32 0, v2
s_cbranch_execz .LBB0_92
s_bcnt1_i32_b32 s15, s15
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v2, s15
s_waitcnt vmcnt(0)
global_atomic_add_u64 v[0:1], v[2:3], off offset:8
.LBB0_92:
s_or_b32 exec_lo, exec_lo, s14
s_waitcnt vmcnt(0)
global_load_b64 v[2:3], v[0:1], off offset:16
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
s_cbranch_vccnz .LBB0_94
global_load_b32 v24, v[0:1], off offset:24
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s14, v24
s_waitcnt_vscnt null, 0x0
global_store_b64 v[2:3], v[24:25], off
s_and_b32 m0, s14, 0xff
s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_94:
s_or_b32 exec_lo, exec_lo, s1
s_mul_i32 s1, s13, 24
s_mul_hi_u32 s13, s12, 24
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_add_i32 s13, s13, s1
s_mul_i32 s1, s12, 24
v_add_co_u32 v0, vcc_lo, v16, s1
v_add_co_ci_u32_e32 v1, vcc_lo, s13, v17, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v0, 20
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
s_branch .LBB0_98
.p2align 6
.LBB0_95:
s_or_b32 exec_lo, exec_lo, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s1, v2
s_cmp_eq_u32 s1, 0
s_cbranch_scc1 .LBB0_97
s_sleep 1
s_cbranch_execnz .LBB0_98
s_branch .LBB0_100
.p2align 6
.LBB0_97:
s_branch .LBB0_100
.LBB0_98:
v_mov_b32_e32 v2, 1
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_95
global_load_b32 v2, v[0:1], off glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_and_b32_e32 v2, 1, v2
s_branch .LBB0_95
.LBB0_100:
global_load_b64 v[0:1], v[18:19], off
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_28
s_clause 0x2
global_load_b64 v[4:5], v25, s[2:3] offset:40
global_load_b64 v[8:9], v25, s[2:3] offset:24 glc
global_load_b64 v[6:7], v25, s[2:3]
s_waitcnt vmcnt(2)
v_add_co_u32 v10, vcc_lo, v4, 1
v_add_co_ci_u32_e32 v11, vcc_lo, 0, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, v10, s10
v_add_co_ci_u32_e32 v3, vcc_lo, s11, v11, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
v_dual_cndmask_b32 v3, v3, v11 :: v_dual_cndmask_b32 v2, v2, v10
v_and_b32_e32 v5, v3, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_and_b32_e32 v4, v2, v4
v_mul_hi_u32 v10, v4, 24
v_mul_lo_u32 v4, v4, 24
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_add_co_u32 v6, vcc_lo, v6, v4
v_mov_b32_e32 v4, v8
v_mul_lo_u32 v5, v5, 24
v_add_nc_u32_e32 v5, v10, v5
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e32 v7, vcc_lo, v7, v5, vcc_lo
v_mov_b32_e32 v5, v9
global_store_b64 v[6:7], v[8:9], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[4:5], v25, v[2:5], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_ne_u64_e32 vcc_lo, v[4:5], v[8:9]
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_28
s_mov_b32 s0, 0
.LBB0_103:
s_sleep 1
global_store_b64 v[6:7], v[4:5], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[8:9], v25, v[2:5], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[8:9], v[4:5]
v_dual_mov_b32 v4, v8 :: v_dual_mov_b32 v5, v9
s_or_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB0_103
s_branch .LBB0_28
.LBB0_104:
s_mov_b32 s0, 0
.LBB0_105:
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 vcc_lo, exec_lo, s0
s_cbranch_vccz .LBB0_132
v_readfirstlane_b32 s0, v20
v_mov_b32_e32 v4, 0
v_mov_b32_e32 v5, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_eq_u32_e64 s0, s0, v20
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_112
s_waitcnt vmcnt(0)
v_mov_b32_e32 v0, 0
s_mov_b32 s4, exec_lo
global_load_b64 v[6:7], v0, s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
s_clause 0x1
global_load_b64 v[1:2], v0, s[2:3] offset:40
global_load_b64 v[3:4], v0, s[2:3]
s_waitcnt vmcnt(1)
v_and_b32_e32 v1, v1, v6
v_and_b32_e32 v2, v2, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_hi_u32 v5, v1, 24
v_mul_lo_u32 v2, v2, 24
v_mul_lo_u32 v1, v1, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v2, v5, v2
s_waitcnt vmcnt(0)
v_add_co_u32 v1, vcc_lo, v3, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, v4, v2, vcc_lo
global_load_b64 v[4:5], v[1:2], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[4:5], v0, v[4:7], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmpx_ne_u64_e64 v[4:5], v[6:7]
s_cbranch_execz .LBB0_111
s_mov_b32 s5, 0
.p2align 6
.LBB0_109:
s_sleep 1
s_clause 0x1
global_load_b64 v[1:2], v0, s[2:3] offset:40
global_load_b64 v[8:9], v0, s[2:3]
v_dual_mov_b32 v7, v5 :: v_dual_mov_b32 v6, v4
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_and_b32_e32 v1, v1, v6
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[3:4], null, v1, 24, v[8:9]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mov_b32 v1, v4 :: v_dual_and_b32 v2, v2, v7
v_mad_u64_u32 v[4:5], null, v2, 24, v[1:2]
global_load_b64 v[4:5], v[3:4], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[4:5], v0, v[4:7], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmp_eq_u64_e32 vcc_lo, v[4:5], v[6:7]
s_or_b32 s5, vcc_lo, s5
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s5
s_cbranch_execnz .LBB0_109
s_or_b32 exec_lo, exec_lo, s5
.LBB0_111:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s4
.LBB0_112:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s1
v_mov_b32_e32 v21, 0
v_readfirstlane_b32 s4, v4
v_readfirstlane_b32 s5, v5
s_mov_b32 s8, exec_lo
s_clause 0x1
global_load_b64 v[6:7], v21, s[2:3] offset:40
global_load_b128 v[0:3], v21, s[2:3]
s_waitcnt vmcnt(1)
v_readfirstlane_b32 s6, v6
v_readfirstlane_b32 s7, v7
s_delay_alu instid0(VALU_DEP_1)
s_and_b64 s[6:7], s[4:5], s[6:7]
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_114
v_dual_mov_b32 v4, s8 :: v_dual_mov_b32 v5, 0
s_mul_i32 s8, s7, 24
s_mul_hi_u32 s9, s6, 24
v_dual_mov_b32 v6, 2 :: v_dual_mov_b32 v7, 1
s_add_i32 s9, s9, s8
s_mul_i32 s8, s6, 24
s_waitcnt vmcnt(0)
v_add_co_u32 v8, vcc_lo, v0, s8
v_add_co_ci_u32_e32 v9, vcc_lo, s9, v1, vcc_lo
global_store_b128 v[8:9], v[4:7], off offset:8
.LBB0_114:
s_or_b32 exec_lo, exec_lo, s1
s_lshl_b64 s[8:9], s[6:7], 12
v_and_or_b32 v22, v22, 0xffffff1d, 34
s_waitcnt vmcnt(0)
v_add_co_u32 v4, vcc_lo, v2, s8
v_add_co_ci_u32_e32 v5, vcc_lo, s9, v3, vcc_lo
v_lshlrev_b64 v[2:3], 6, v[20:21]
s_mov_b32 s8, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
s_mov_b32 s9, s8
s_mov_b32 s10, s8
s_mov_b32 s11, s8
v_add_co_u32 v8, vcc_lo, v4, v2
v_mov_b32_e32 v6, 0
v_add_co_ci_u32_e32 v9, vcc_lo, v5, v3, vcc_lo
v_dual_mov_b32 v2, s8 :: v_dual_mov_b32 v5, s11
v_dual_mov_b32 v3, s9 :: v_dual_mov_b32 v4, s10
s_delay_alu instid0(VALU_DEP_4)
v_mov_b32_e32 v7, v6
s_clause 0x4
global_store_b64 v[8:9], v[22:23], off
global_store_b128 v[8:9], v[2:5], off offset:8
global_store_b128 v[8:9], v[2:5], off offset:24
global_store_b128 v[8:9], v[2:5], off offset:40
global_store_b64 v[8:9], v[6:7], off offset:56
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_122
v_dual_mov_b32 v8, 0 :: v_dual_mov_b32 v9, s4
v_mov_b32_e32 v10, s5
s_clause 0x1
global_load_b64 v[11:12], v8, s[2:3] offset:32 glc
global_load_b64 v[2:3], v8, s[2:3] offset:40
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s8, v2
v_readfirstlane_b32 s9, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b64 s[8:9], s[8:9], s[4:5]
s_mul_i32 s9, s9, 24
s_mul_hi_u32 s10, s8, 24
s_mul_i32 s8, s8, 24
s_add_i32 s10, s10, s9
v_add_co_u32 v6, vcc_lo, v0, s8
v_add_co_ci_u32_e32 v7, vcc_lo, s10, v1, vcc_lo
s_mov_b32 s8, exec_lo
global_store_b64 v[6:7], v[11:12], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[4:5], v8, v[9:12], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmpx_ne_u64_e64 v[4:5], v[11:12]
s_cbranch_execz .LBB0_118
s_mov_b32 s9, 0
.LBB0_117:
v_dual_mov_b32 v2, s4 :: v_dual_mov_b32 v3, s5
s_sleep 1
global_store_b64 v[6:7], v[4:5], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v8, v[2:5], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5]
v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
s_or_b32 s9, vcc_lo, s9
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s9
s_cbranch_execnz .LBB0_117
.LBB0_118:
s_or_b32 exec_lo, exec_lo, s8
v_mov_b32_e32 v2, 0
s_mov_b32 s9, exec_lo
s_mov_b32 s8, exec_lo
v_mbcnt_lo_u32_b32 v4, s9, 0
global_load_b64 v[2:3], v2, s[2:3] offset:16
v_cmpx_eq_u32_e32 0, v4
s_cbranch_execz .LBB0_120
s_bcnt1_i32_b32 s9, s9
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v5, 0 :: v_dual_mov_b32 v4, s9
s_waitcnt vmcnt(0)
global_atomic_add_u64 v[2:3], v[4:5], off offset:8
.LBB0_120:
s_or_b32 exec_lo, exec_lo, s8
s_waitcnt vmcnt(0)
global_load_b64 v[4:5], v[2:3], off offset:16
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, 0, v[4:5]
s_cbranch_vccnz .LBB0_122
global_load_b32 v2, v[2:3], off offset:24
v_mov_b32_e32 v3, 0
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s8, v2
s_waitcnt_vscnt null, 0x0
global_store_b64 v[4:5], v[2:3], off
s_and_b32 m0, s8, 0xff
s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_122:
s_or_b32 exec_lo, exec_lo, s1
s_mul_i32 s1, s7, 24
s_mul_hi_u32 s7, s6, 24
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_add_i32 s7, s7, s1
s_mul_i32 s1, s6, 24
v_add_co_u32 v0, vcc_lo, v0, s1
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v0, 20
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
s_branch .LBB0_126
.p2align 6
.LBB0_123:
s_or_b32 exec_lo, exec_lo, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s1, v2
s_cmp_eq_u32 s1, 0
s_cbranch_scc1 .LBB0_125
s_sleep 1
s_cbranch_execnz .LBB0_126
s_branch .LBB0_128
.p2align 6
.LBB0_125:
s_branch .LBB0_128
.LBB0_126:
v_mov_b32_e32 v2, 1
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_123
global_load_b32 v2, v[0:1], off glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_and_b32_e32 v2, 1, v2
s_branch .LBB0_123
.LBB0_128:
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_132
v_mov_b32_e32 v6, 0
s_clause 0x2
global_load_b64 v[2:3], v6, s[2:3] offset:40
global_load_b64 v[7:8], v6, s[2:3] offset:24 glc
global_load_b64 v[4:5], v6, s[2:3]
s_waitcnt vmcnt(2)
v_add_co_u32 v9, vcc_lo, v2, 1
v_add_co_ci_u32_e32 v10, vcc_lo, 0, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v9, s4
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v10, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_eq_u64_e32 vcc_lo, 0, v[0:1]
v_dual_cndmask_b32 v1, v1, v10 :: v_dual_cndmask_b32 v0, v0, v9
v_and_b32_e32 v3, v1, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_and_b32_e32 v2, v0, v2
v_mul_lo_u32 v3, v3, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_hi_u32 v9, v2, 24
v_mul_lo_u32 v2, v2, 24
v_add_nc_u32_e32 v3, v9, v3
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_u32 v4, vcc_lo, v4, v2
v_mov_b32_e32 v2, v7
v_add_co_ci_u32_e32 v5, vcc_lo, v5, v3, vcc_lo
v_mov_b32_e32 v3, v8
global_store_b64 v[4:5], v[7:8], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v6, v[0:3], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_ne_u64_e32 vcc_lo, v[2:3], v[7:8]
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_132
s_mov_b32 s0, 0
.LBB0_131:
s_sleep 1
global_store_b64 v[4:5], v[2:3], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[7:8], v6, v[0:3], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[7:8], v[2:3]
v_dual_mov_b32 v2, v7 :: v_dual_mov_b32 v3, v8
s_or_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB0_131
.LBB0_132:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12hellofromgpuv
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 256
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 32
.amdhsa_next_free_sgpr 18
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z12hellofromgpuv, .Lfunc_end0-_Z12hellofromgpuv
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type .str,@object
.section .rodata.str1.1,"aMS",@progbits,1
.str:
.asciz "Hello World from GPU\n"
.size .str, 22
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: hidden_block_count_x
- .offset: 4
.size: 4
.value_kind: hidden_block_count_y
- .offset: 8
.size: 4
.value_kind: hidden_block_count_z
- .offset: 12
.size: 2
.value_kind: hidden_group_size_x
- .offset: 14
.size: 2
.value_kind: hidden_group_size_y
- .offset: 16
.size: 2
.value_kind: hidden_group_size_z
- .offset: 18
.size: 2
.value_kind: hidden_remainder_x
- .offset: 20
.size: 2
.value_kind: hidden_remainder_y
- .offset: 22
.size: 2
.value_kind: hidden_remainder_z
- .offset: 40
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 48
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 64
.size: 2
.value_kind: hidden_grid_dims
- .offset: 80
.size: 8
.value_kind: hidden_hostcall_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 256
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12hellofromgpuv
.private_segment_fixed_size: 0
.sgpr_count: 20
.sgpr_spill_count: 0
.symbol: _Z12hellofromgpuv.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 32
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0011553f_00000000-6_hello_gpu.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z31__device_stub__Z12hellofromgpuvv
.type _Z31__device_stub__Z12hellofromgpuvv, @function
_Z31__device_stub__Z12hellofromgpuvv:
.LFB2082:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z12hellofromgpuv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z31__device_stub__Z12hellofromgpuvv, .-_Z31__device_stub__Z12hellofromgpuvv
.globl _Z12hellofromgpuv
.type _Z12hellofromgpuv, @function
_Z12hellofromgpuv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z12hellofromgpuvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z12hellofromgpuv, .-_Z12hellofromgpuv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "hello from cpu\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $10, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L12:
call cudaDeviceReset@PLT
movl $0, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
call _Z31__device_stub__Z12hellofromgpuvv
jmp .L12
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z12hellofromgpuv"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z12hellofromgpuv(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "hello_gpu.hip"
.globl _Z27__device_stub__hellofromgpuv # -- Begin function _Z27__device_stub__hellofromgpuv
.p2align 4, 0x90
.type _Z27__device_stub__hellofromgpuv,@function
_Z27__device_stub__hellofromgpuv: # @_Z27__device_stub__hellofromgpuv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z12hellofromgpuv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z27__device_stub__hellofromgpuv, .Lfunc_end0-_Z27__device_stub__hellofromgpuv
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
movl $.Lstr, %edi
callq puts@PLT
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 9(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z12hellofromgpuv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
callq hipDeviceReset
xorl %eax, %eax
addq $56, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12hellofromgpuv, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z12hellofromgpuv,@object # @_Z12hellofromgpuv
.section .rodata,"a",@progbits
.globl _Z12hellofromgpuv
.p2align 3, 0x0
_Z12hellofromgpuv:
.quad _Z27__device_stub__hellofromgpuv
.size _Z12hellofromgpuv, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z12hellofromgpuv"
.size .L__unnamed_1, 18
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "hello from cpu"
.size .Lstr, 15
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__hellofromgpuv
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12hellofromgpuv
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <cuda.h>
#include <stdio.h>
#include <time.h>
#include <stdlib.h>
#define BLOCK_WIDTH 32
// kernel
__global__ void tiledConvolution_2D_Kernel(float* d_m, const float* __restrict__ d_mask, float* d_n, size_t a, size_t b, size_t maskWidth, int N_TILE_WIDTH)
{
float result = 0;
// indexing variables
int n_row = blockIdx.y * N_TILE_WIDTH + threadIdx.y;
int n_col = blockIdx.x * N_TILE_WIDTH + threadIdx.x;
int m_row = n_row - maskWidth / 2;
int m_col = n_col - maskWidth / 2;
__shared__ float tile_m[BLOCK_WIDTH][BLOCK_WIDTH];
// thread boundary check for loading input tiles
if(m_row >= 0 && m_row < a && m_col >= 0 && m_col < b)
{
tile_m[threadIdx.y][threadIdx.x] = d_m[m_row * b + m_col];
}
else
{
tile_m[threadIdx.y][threadIdx.x] = 0;
}
__syncthreads();
// thread boundary check for calculation
if(threadIdx.y < N_TILE_WIDTH && threadIdx.x < N_TILE_WIDTH && n_row < a && n_col < b)
{
for(int i = 0; i < maskWidth; ++i)
{
for(int j = 0; j < maskWidth; ++j)
{
result += d_mask[i * maskWidth + j] * tile_m[threadIdx.y + i][threadIdx.x + j];
}
}
// write result
d_n[n_row * b + n_col] = result;
}
}
// CUDA error checking
void errorCheck(unsigned int line)
{
cudaError_t cudaError = cudaGetLastError();
if(cudaError != cudaSuccess)
{
printf("CUDA error in line %u in file %s: %s\n", line - 1, __FILE__, cudaGetErrorString(cudaError));
exit(EXIT_FAILURE);
}
}
// host function containing kernel call
void convolution_2D(float* m, float* mask, float* n, size_t a, size_t b, size_t maskWidth, int N_TILE_WIDTH)
{
dim3 numOfBlocks(ceil(b / (float) N_TILE_WIDTH), ceil(a / (float) N_TILE_WIDTH), 1);
dim3 numOfThreads(BLOCK_WIDTH, BLOCK_WIDTH, 1);
size_t bytes_m = a * b * sizeof(float);
size_t bytes_mask = maskWidth * maskWidth * sizeof(float);
float* d_m;
float* d_mask;
float* d_n;
cudaMalloc((void**) &d_m, bytes_m);
errorCheck(__LINE__);
cudaMalloc((void**) &d_mask, bytes_mask);
errorCheck(__LINE__);
cudaMalloc((void**) &d_n, bytes_m);
errorCheck(__LINE__);
cudaMemcpy(d_m, m, bytes_m, cudaMemcpyHostToDevice);
errorCheck(__LINE__);
cudaMemcpy(d_mask, mask, bytes_mask, cudaMemcpyHostToDevice);
errorCheck(__LINE__);
tiledConvolution_2D_Kernel<<<numOfBlocks, numOfThreads>>>(d_m, d_mask, d_n, a, b, maskWidth, N_TILE_WIDTH);
errorCheck(__LINE__);
cudaMemcpy(n, d_n, bytes_m, cudaMemcpyDeviceToHost);
errorCheck(__LINE__);
cudaFree(d_m);
errorCheck(__LINE__);
cudaFree(d_mask);
errorCheck(__LINE__);
cudaFree(d_n);
errorCheck(__LINE__);
}
int main()
{
struct timespec start, end;
srand(time(NULL));
size_t a = rand() % 257 + 3840;
size_t b = rand() % 257 + 3840;
size_t maskWidth = 11;
int N_TILE_WIDTH = BLOCK_WIDTH - (maskWidth - 1);
float* m = (float*) malloc(a * b * sizeof(float));
float* mask = (float*) malloc(maskWidth * maskWidth * sizeof(float));
float* n = (float*) malloc(a * b * sizeof(float));
for(int i = 0; i < a * b; ++i)
{
m[i] = rand() % 129 - 64;
}
for(int j = 0; j < maskWidth * maskWidth; ++j)
{
mask[j] = rand() % 1001 / 1000.0;
}
clock_gettime(CLOCK_REALTIME, &start);
// do convolution
convolution_2D(m, mask, n, a, b, maskWidth, N_TILE_WIDTH);
clock_gettime(CLOCK_REALTIME, &end);
time_t execTime = (end.tv_sec - start.tv_sec) * 1000000 + (end.tv_nsec - start.tv_nsec) / 1000;
printf("Execution time: %d microseconds.", execTime);
return 0;
} | code for sm_80
Function : _Z26tiledConvolution_2D_KernelPfPKfS_mmmi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R9, SR_CTAID.Y ; /* 0x0000000000097919 */
/* 0x000e220000002600 */
/*0020*/ IMAD.MOV.U32 R12, RZ, RZ, c[0x0][0x188] ; /* 0x00006200ff0c7624 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR8, c[0x0][0x118] ; /* 0x0000460000087ab9 */
/* 0x000fe20000000a00 */
/*0040*/ IMAD.MOV.U32 R11, RZ, RZ, c[0x0][0x18c] ; /* 0x00006300ff0b7624 */
/* 0x000fe200078e00ff */
/*0050*/ S2R R0, SR_TID.Y ; /* 0x0000000000007919 */
/* 0x000e280000002200 */
/*0060*/ S2R R7, SR_CTAID.X ; /* 0x0000000000077919 */
/* 0x000e620000002500 */
/*0070*/ SHF.R.U64 R2, R12, 0x1, R11 ; /* 0x000000010c027819 */
/* 0x000fc6000000120b */
/*0080*/ S2R R8, SR_TID.X ; /* 0x0000000000087919 */
/* 0x000e620000002100 */
/*0090*/ IMAD R9, R9, c[0x0][0x190], R0 ; /* 0x0000640009097a24 */
/* 0x001fc800078e0200 */
/*00a0*/ IMAD.IADD R5, R9, 0x1, -R2 ; /* 0x0000000109057824 */
/* 0x000fe400078e0a02 */
/*00b0*/ IMAD R6, R7, c[0x0][0x190], R8 ; /* 0x0000640007067a24 */
/* 0x002fc600078e0208 */
/*00c0*/ ISETP.GE.U32.AND P0, PT, R5, c[0x0][0x178], PT ; /* 0x00005e0005007a0c */
/* 0x000fe40003f06070 */
/*00d0*/ SHF.R.S32.HI R4, RZ, 0x1f, R5 ; /* 0x0000001fff047819 */
/* 0x000fe20000011405 */
/*00e0*/ IMAD.IADD R2, R6, 0x1, -R2 ; /* 0x0000000106027824 */
/* 0x000fc600078e0a02 */
/*00f0*/ ISETP.GE.U32.AND.EX P0, PT, R4, c[0x0][0x17c], PT, P0 ; /* 0x00005f0004007a0c */
/* 0x000fe40003f06100 */
/*0100*/ LOP3.LUT R7, R5, R2, RZ, 0xfc, !PT ; /* 0x0000000205077212 */
/* 0x000fe400078efcff */
/*0110*/ ISETP.LT.U32.AND P1, PT, R2, c[0x0][0x180], PT ; /* 0x0000600002007a0c */
/* 0x000fe40003f21070 */
/*0120*/ SHF.R.S32.HI R3, RZ, 0x1f, R2 ; /* 0x0000001fff037819 */
/* 0x000fe40000011402 */
/*0130*/ ISETP.GT.AND P0, PT, R7, -0x1, !P0 ; /* 0xffffffff0700780c */
/* 0x000fc80004704270 */
/*0140*/ ISETP.LT.U32.AND.EX P0, PT, R3, c[0x0][0x184], P0, P1 ; /* 0x0000610003007a0c */
/* 0x000fda0000701110 */
/*0150*/ @P0 IMAD R4, R4, c[0x0][0x180], RZ ; /* 0x0000600004040a24 */
/* 0x000fe400078e02ff */
/*0160*/ @P0 IMAD.WIDE.U32 R2, R5, c[0x0][0x180], R2 ; /* 0x0000600005020a25 */
/* 0x000fc800078e0002 */
/*0170*/ @P0 IMAD R5, R5, c[0x0][0x184], R4 ; /* 0x0000610005050a24 */
/* 0x000fe200078e0204 */
/*0180*/ @P0 LEA R4, P1, R2, c[0x0][0x160], 0x2 ; /* 0x0000580002040a11 */
/* 0x000fc600078210ff */
/*0190*/ @P0 IMAD.IADD R3, R3, 0x1, R5 ; /* 0x0000000103030824 */
/* 0x000fca00078e0205 */
/*01a0*/ @P0 LEA.HI.X R5, R2, c[0x0][0x164], R3, 0x2, P1 ; /* 0x0000590002050a11 */
/* 0x000fcc00008f1403 */
/*01b0*/ @P0 LDG.E R5, [R4.64] ; /* 0x0000000804050981 */
/* 0x000ea2000c1e1900 */
/*01c0*/ IMAD.SHL.U32 R3, R8.reuse, 0x4, RZ ; /* 0x0000000408037824 */
/* 0x040fe200078e00ff */
/*01d0*/ ISETP.GE.U32.AND P1, PT, R8, c[0x0][0x190], PT ; /* 0x0000640008007a0c */
/* 0x000fe40003f26070 */
/*01e0*/ ISETP.GE.U32.AND P3, PT, R9, c[0x0][0x178], PT ; /* 0x00005e0009007a0c */
/* 0x000fe20003f66070 */
/*01f0*/ IMAD R2, R0.reuse, 0x80, R3 ; /* 0x0000008000027824 */
/* 0x040fe200078e0203 */
/*0200*/ ISETP.GE.U32.OR P2, PT, R0, c[0x0][0x190], P1 ; /* 0x0000640000007a0c */
/* 0x000fe40000f46470 */
/*0210*/ SHF.R.S32.HI R10, RZ, 0x1f, R9 ; /* 0x0000001fff0a7819 */
/* 0x000fe40000011409 */
/*0220*/ @!P0 STS [R2], RZ ; /* 0x000000ff02008388 */
/* 0x0001e20000000800 */
/*0230*/ ISETP.GE.U32.AND P1, PT, R6, c[0x0][0x180], PT ; /* 0x0000600006007a0c */
/* 0x000fc40003f26070 */
/*0240*/ SHF.R.S32.HI R7, RZ, 0x1f, R6 ; /* 0x0000001fff077819 */
/* 0x000fe40000011406 */
/*0250*/ ISETP.GE.U32.OR.EX P2, PT, R10, c[0x0][0x17c], P2, P3 ; /* 0x00005f000a007a0c */
/* 0x000fc80001746530 */
/*0260*/ ISETP.GE.U32.OR.EX P1, PT, R7, c[0x0][0x184], P2, P1 ; /* 0x0000610007007a0c */
/* 0x000fe20001726510 */
/*0270*/ @P0 STS [R2], R5 ; /* 0x0000000502000388 */
/* 0x0041e80000000800 */
/*0280*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000ff00000010000 */
/*0290*/ @P1 EXIT ; /* 0x000000000000194d */
/* 0x000fea0003800000 */
/*02a0*/ ISETP.NE.U32.AND P0, PT, RZ, c[0x0][0x188], PT ; /* 0x00006200ff007a0c */
/* 0x001fe20003f05070 */
/*02b0*/ IMAD.MOV.U32 R22, RZ, RZ, RZ ; /* 0x000000ffff167224 */
/* 0x000fc600078e00ff */
/*02c0*/ ISETP.NE.AND.EX P0, PT, RZ, c[0x0][0x18c], PT, P0 ; /* 0x00006300ff007a0c */
/* 0x000fda0003f05300 */
/*02d0*/ @!P0 BRA 0xe50 ; /* 0x00000b7000008947 */
/* 0x000fea0003800000 */
/*02e0*/ IADD3 R2, P0, R12.reuse, -0x1, RZ ; /* 0xffffffff0c027810 */
/* 0x040fe20007f1e0ff */
/*02f0*/ UMOV UR4, 0x8 ; /* 0x0000000800047882 */
/* 0x000fe20000000000 */
/*0300*/ LOP3.LUT R12, R12, 0x3, RZ, 0xc0, !PT ; /* 0x000000030c0c7812 */
/* 0x000fe200078ec0ff */
/*0310*/ ULDC.64 UR6, c[0x0][0x168] ; /* 0x00005a0000067ab9 */
/* 0x000fe20000000a00 */
/*0320*/ ISETP.GE.U32.AND P1, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fe20003f26070 */
/*0330*/ UIADD3 UR4, UP0, UR4, UR6, URZ ; /* 0x0000000604047290 */
/* 0x000fe2000ff1e03f */
/*0340*/ IADD3.X R2, R11, -0x1, RZ, P0, !PT ; /* 0xffffffff0b027810 */
/* 0x000fe200007fe4ff */
/*0350*/ IMAD.MOV.U32 R22, RZ, RZ, RZ ; /* 0x000000ffff167224 */
/* 0x000fe200078e00ff */
/*0360*/ IADD3 R13, P0, R12, -c[0x0][0x188], RZ ; /* 0x800062000c0d7a10 */
/* 0x000fe20007f1e0ff */
/*0370*/ IMAD.MOV.U32 R15, RZ, RZ, RZ ; /* 0x000000ffff0f7224 */
/* 0x000fe200078e00ff */
/*0380*/ ISETP.GE.U32.AND.EX P1, PT, R2, RZ, PT, P1 ; /* 0x000000ff0200720c */
/* 0x000fe20003f26110 */
/*0390*/ UIADD3.X UR5, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f057290 */
/* 0x000fe200087fe43f */
/*03a0*/ IADD3 R14, R3, 0x8, RZ ; /* 0x00000008030e7810 */
/* 0x000fe20007ffe0ff */
/*03b0*/ IMAD.X R16, RZ, RZ, ~c[0x0][0x18c], P0 ; /* 0x80006300ff107624 */
/* 0x000fc400000e06ff */
/*03c0*/ SHF.R.S32.HI R2, RZ, 0x1f, R15 ; /* 0x0000001fff027819 */
/* 0x000fe2000001140f */
/*03d0*/ IMAD.WIDE.U32 R4, R15, c[0x0][0x188], RZ ; /* 0x000062000f047a25 */
/* 0x000fc800078e00ff */
/*03e0*/ IMAD R2, R2, c[0x0][0x188], RZ ; /* 0x0000620002027a24 */
/* 0x000fe400078e02ff */
/*03f0*/ IMAD.IADD R17, R0, 0x1, R15 ; /* 0x0000000100117824 */
/* 0x000fe400078e020f */
/*0400*/ IMAD R19, R15, c[0x0][0x18c], R2 ; /* 0x000063000f137a24 */
/* 0x000fe400078e0202 */
/*0410*/ IMAD.MOV.U32 R11, RZ, RZ, RZ ; /* 0x000000ffff0b7224 */
/* 0x000fe400078e00ff */
/*0420*/ IMAD.IADD R19, R5, 0x1, R19 ; /* 0x0000000105137824 */
/* 0x000fe200078e0213 */
/*0430*/ @!P1 BRA 0xc90 ; /* 0x0000085000009947 */
/* 0x000fea0003800000 */
/*0440*/ ISETP.GE.AND P0, PT, R16, RZ, PT ; /* 0x000000ff1000720c */
/* 0x000fe20003f06270 */
/*0450*/ IMAD R18, R17, 0x80, R14 ; /* 0x0000008011127824 */
/* 0x000fe200078e020e */
/*0460*/ LEA R2, P2, R4, UR4, 0x2 ; /* 0x0000000404027c11 */
/* 0x000fe2000f8410ff */
/*0470*/ IMAD.MOV.U32 R11, RZ, RZ, RZ ; /* 0x000000ffff0b7224 */
/* 0x000fc400078e00ff */
/*0480*/ IMAD.MOV.U32 R21, RZ, RZ, R13 ; /* 0x000000ffff157224 */
/* 0x000fe200078e000d */
/*0490*/ LEA.HI.X R3, R4, UR5, R19, 0x2, P2 ; /* 0x0000000504037c11 */
/* 0x000fe200090f1413 */
/*04a0*/ IMAD.MOV.U32 R20, RZ, RZ, R16 ; /* 0x000000ffff147224 */
/* 0x000fcc00078e0010 */
/*04b0*/ @P0 BRA 0xb40 ; /* 0x0000068000000947 */
/* 0x000fea0003800000 */
/*04c0*/ IADD3 R23, P0, RZ, -R21, RZ ; /* 0x80000015ff177210 */
/* 0x000fc80007f1e0ff */
/*04d0*/ ISETP.GT.U32.AND P2, PT, R23, 0xc, PT ; /* 0x0000000c1700780c */
/* 0x000fe20003f44070 */
/*04e0*/ IMAD.X R23, RZ, RZ, ~R20, P0 ; /* 0x000000ffff177224 */
/* 0x000fe200000e0e14 */
/*04f0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fc80003f0f070 */
/*0500*/ ISETP.GT.AND.EX P2, PT, R23, RZ, PT, P2 ; /* 0x000000ff1700720c */
/* 0x000fda0003f44320 */
/*0510*/ @!P2 BRA 0x8c0 ; /* 0x000003a00000a947 */
/* 0x000fea0003800000 */
/*0520*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0530*/ LDG.E.CONSTANT R26, [R2.64+-0x8] ; /* 0xfffff808021a7981 */
/* 0x000ea8000c1e9900 */
/*0540*/ LDG.E.CONSTANT R27, [R2.64+-0x4] ; /* 0xfffffc08021b7981 */
/* 0x000ee8000c1e9900 */
/*0550*/ LDG.E.CONSTANT R24, [R2.64] ; /* 0x0000000802187981 */
/* 0x000f28000c1e9900 */
/*0560*/ LDG.E.CONSTANT R23, [R2.64+0x4] ; /* 0x0000040802177981 */
/* 0x000f68000c1e9900 */
/*0570*/ LDS R25, [R18+-0x8] ; /* 0xfffff80012197984 */
/* 0x000ea40000000800 */
/*0580*/ FFMA R25, R25, R26, R22 ; /* 0x0000001a19197223 */
/* 0x004fc40000000016 */
/*0590*/ LDS R22, [R18+-0x4] ; /* 0xfffffc0012167984 */
/* 0x000ee80000000800 */
/*05a0*/ LDS R26, [R18] ; /* 0x00000000121a7984 */
/* 0x000f220000000800 */
/*05b0*/ FFMA R25, R22, R27, R25 ; /* 0x0000001b16197223 */
/* 0x008fc60000000019 */
/*05c0*/ LDG.E.CONSTANT R22, [R2.64+0x8] ; /* 0x0000080802167981 */
/* 0x000ea2000c1e9900 */
/*05d0*/ FFMA R26, R26, R24, R25 ; /* 0x000000181a1a7223 */
/* 0x010fc60000000019 */
/*05e0*/ LDS R25, [R18+0x4] ; /* 0x0000040012197984 */
/* 0x000f680000000800 */
/*05f0*/ LDG.E.CONSTANT R24, [R2.64+0xc] ; /* 0x00000c0802187981 */
/* 0x000ee2000c1e9900 */
/*0600*/ FFMA R27, R25, R23, R26 ; /* 0x00000017191b7223 */
/* 0x020fc6000000001a */
/*0610*/ LDG.E.CONSTANT R25, [R2.64+0x10] ; /* 0x0000100802197981 */
/* 0x000f28000c1e9900 */
/*0620*/ LDG.E.CONSTANT R23, [R2.64+0x14] ; /* 0x0000140802177981 */
/* 0x000f68000c1e9900 */
/*0630*/ LDS R26, [R18+0x8] ; /* 0x00000800121a7984 */
/* 0x000ea40000000800 */
/*0640*/ FFMA R27, R26, R22, R27 ; /* 0x000000161a1b7223 */
/* 0x004fc4000000001b */
/*0650*/ LDS R22, [R18+0xc] ; /* 0x00000c0012167984 */
/* 0x000ee80000000800 */
/*0660*/ LDS R26, [R18+0x10] ; /* 0x00001000121a7984 */
/* 0x000f220000000800 */
/*0670*/ FFMA R24, R22, R24, R27 ; /* 0x0000001816187223 */
/* 0x008fc6000000001b */
/*0680*/ LDG.E.CONSTANT R22, [R2.64+0x18] ; /* 0x0000180802167981 */
/* 0x000ea2000c1e9900 */
/*0690*/ FFMA R26, R26, R25, R24 ; /* 0x000000191a1a7223 */
/* 0x010fc60000000018 */
/*06a0*/ LDS R25, [R18+0x14] ; /* 0x0000140012197984 */
/* 0x000f680000000800 */
/*06b0*/ LDG.E.CONSTANT R24, [R2.64+0x1c] ; /* 0x00001c0802187981 */
/* 0x000ee2000c1e9900 */
/*06c0*/ FFMA R27, R25, R23, R26 ; /* 0x00000017191b7223 */
/* 0x020fc6000000001a */
/*06d0*/ LDG.E.CONSTANT R25, [R2.64+0x20] ; /* 0x0000200802197981 */
/* 0x000f28000c1e9900 */
/*06e0*/ LDG.E.CONSTANT R23, [R2.64+0x24] ; /* 0x0000240802177981 */
/* 0x000f68000c1e9900 */
/*06f0*/ LDS R26, [R18+0x18] ; /* 0x00001800121a7984 */
/* 0x000ea40000000800 */
/*0700*/ FFMA R27, R26, R22, R27 ; /* 0x000000161a1b7223 */
/* 0x004fc4000000001b */
/*0710*/ LDS R22, [R18+0x1c] ; /* 0x00001c0012167984 */
/* 0x000ee80000000800 */
/*0720*/ LDS R26, [R18+0x20] ; /* 0x00002000121a7984 */
/* 0x000f220000000800 */
/*0730*/ FFMA R24, R22, R24, R27 ; /* 0x0000001816187223 */
/* 0x008fc6000000001b */
/*0740*/ LDG.E.CONSTANT R22, [R2.64+0x28] ; /* 0x0000280802167981 */
/* 0x0000a2000c1e9900 */
/*0750*/ FFMA R26, R26, R25, R24 ; /* 0x000000191a1a7223 */
/* 0x010fc60000000018 */
/*0760*/ LDS R25, [R18+0x24] ; /* 0x0000240012197984 */
/* 0x000f680000000800 */
/*0770*/ LDG.E.CONSTANT R24, [R2.64+0x2c] ; /* 0x00002c0802187981 */
/* 0x0000e2000c1e9900 */
/*0780*/ FFMA R27, R25, R23, R26 ; /* 0x00000017191b7223 */
/* 0x020fc6000000001a */
/*0790*/ LDG.E.CONSTANT R25, [R2.64+0x30] ; /* 0x0000300802197981 */
/* 0x000128000c1e9900 */
/*07a0*/ LDG.E.CONSTANT R23, [R2.64+0x34] ; /* 0x0000340802177981 */
/* 0x000162000c1e9900 */
/*07b0*/ IADD3 R21, P2, R21, 0x10, RZ ; /* 0x0000001015157810 */
/* 0x000fe40007f5e0ff */
/*07c0*/ IADD3 R11, R11, 0x10, RZ ; /* 0x000000100b0b7810 */
/* 0x000fe20007ffe0ff */
/*07d0*/ LDS R26, [R18+0x28] ; /* 0x00002800121a7984 */
/* 0x000ea40000000800 */
/*07e0*/ IMAD.X R20, RZ, RZ, R20, P2 ; /* 0x000000ffff147224 */
/* 0x000fe200010e0614 */
/*07f0*/ ISETP.GE.U32.AND P2, PT, R21, -0xc, PT ; /* 0xfffffff41500780c */
/* 0x000fc40003f46070 */
/*0800*/ IADD3 R2, P3, R2, 0x40, RZ ; /* 0x0000004002027810 */
/* 0x001fe40007f7e0ff */
/*0810*/ ISETP.GE.AND.EX P2, PT, R20, -0x1, PT, P2 ; /* 0xffffffff1400780c */
/* 0x000fc60003f46320 */
/*0820*/ IMAD.X R3, RZ, RZ, R3, P3 ; /* 0x000000ffff037224 */
/* 0x000fe400018e0603 */
/*0830*/ FFMA R27, R26, R22, R27 ; /* 0x000000161a1b7223 */
/* 0x004fe4000000001b */
/*0840*/ LDS R22, [R18+0x2c] ; /* 0x00002c0012167984 */
/* 0x000ee80000000800 */
/*0850*/ LDS R26, [R18+0x34] ; /* 0x00003400121a7984 */
/* 0x000fe20000000800 */
/*0860*/ FFMA R22, R22, R24, R27 ; /* 0x0000001816167223 */
/* 0x008fc6000000001b */
/*0870*/ LDS R24, [R18+0x30] ; /* 0x0000300012187984 */
/* 0x0001240000000800 */
/*0880*/ IADD3 R18, R18, 0x40, RZ ; /* 0x0000004012127810 */
/* 0x001fe20007ffe0ff */
/*0890*/ FFMA R22, R24, R25, R22 ; /* 0x0000001918167223 */
/* 0x010fc80000000016 */
/*08a0*/ FFMA R22, R26, R23, R22 ; /* 0x000000171a167223 */
/* 0x020fe20000000016 */
/*08b0*/ @!P2 BRA 0x530 ; /* 0xfffffc700000a947 */
/* 0x000fea000383ffff */
/*08c0*/ IADD3 R23, P3, RZ, -R21, RZ ; /* 0x80000015ff177210 */
/* 0x000fc80007f7e0ff */
/*08d0*/ ISETP.GT.U32.AND P2, PT, R23, 0x4, PT ; /* 0x000000041700780c */
/* 0x000fe20003f44070 */
/*08e0*/ IMAD.X R23, RZ, RZ, ~R20, P3 ; /* 0x000000ffff177224 */
/* 0x000fca00018e0e14 */
/*08f0*/ ISETP.GT.AND.EX P2, PT, R23, RZ, PT, P2 ; /* 0x000000ff1700720c */
/* 0x000fda0003f44320 */
/*0900*/ @!P2 BRA 0xb10 ; /* 0x000002000000a947 */
/* 0x000fea0003800000 */
/*0910*/ LDG.E.CONSTANT R26, [R2.64+-0x8] ; /* 0xfffff808021a7981 */
/* 0x000ea8000c1e9900 */
/*0920*/ LDG.E.CONSTANT R27, [R2.64+-0x4] ; /* 0xfffffc08021b7981 */
/* 0x000ee8000c1e9900 */
/*0930*/ LDG.E.CONSTANT R24, [R2.64] ; /* 0x0000000802187981 */
/* 0x000f28000c1e9900 */
/*0940*/ LDG.E.CONSTANT R23, [R2.64+0x4] ; /* 0x0000040802177981 */
/* 0x000f68000c1e9900 */
/*0950*/ LDS R25, [R18+-0x8] ; /* 0xfffff80012197984 */
/* 0x000ea40000000800 */
/*0960*/ FFMA R25, R25, R26, R22 ; /* 0x0000001a19197223 */
/* 0x004fc40000000016 */
/*0970*/ LDS R22, [R18+-0x4] ; /* 0xfffffc0012167984 */
/* 0x000ee80000000800 */
/*0980*/ LDS R26, [R18] ; /* 0x00000000121a7984 */
/* 0x000f220000000800 */
/*0990*/ FFMA R25, R22, R27, R25 ; /* 0x0000001b16197223 */
/* 0x008fc60000000019 */
/*09a0*/ LDG.E.CONSTANT R22, [R2.64+0x8] ; /* 0x0000080802167981 */
/* 0x000ea2000c1e9900 */
/*09b0*/ FFMA R26, R26, R24, R25 ; /* 0x000000181a1a7223 */
/* 0x010fc60000000019 */
/*09c0*/ LDS R25, [R18+0x4] ; /* 0x0000040012197984 */
/* 0x000f680000000800 */
/*09d0*/ LDG.E.CONSTANT R24, [R2.64+0xc] ; /* 0x00000c0802187981 */
/* 0x000ee2000c1e9900 */
/*09e0*/ FFMA R27, R25, R23, R26 ; /* 0x00000017191b7223 */
/* 0x020fc6000000001a */
/*09f0*/ LDG.E.CONSTANT R25, [R2.64+0x10] ; /* 0x0000100802197981 */
/* 0x000f28000c1e9900 */
/*0a00*/ LDG.E.CONSTANT R23, [R2.64+0x14] ; /* 0x0000140802177981 */
/* 0x000f62000c1e9900 */
/*0a10*/ IADD3 R21, P3, R21, 0x8, RZ ; /* 0x0000000815157810 */
/* 0x000fe40007f7e0ff */
/*0a20*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe20003f0e170 */
/*0a30*/ LDS R26, [R18+0x8] ; /* 0x00000800121a7984 */
/* 0x000ea20000000800 */
/*0a40*/ IADD3 R11, R11, 0x8, RZ ; /* 0x000000080b0b7810 */
/* 0x000fe20007ffe0ff */
/*0a50*/ IMAD.X R20, RZ, RZ, R20, P3 ; /* 0x000000ffff147224 */
/* 0x000fc400018e0614 */
/*0a60*/ FFMA R27, R26, R22, R27 ; /* 0x000000161a1b7223 */
/* 0x004fe4000000001b */
/*0a70*/ LDS R22, [R18+0xc] ; /* 0x00000c0012167984 */
/* 0x000ee80000000800 */
/*0a80*/ LDS R26, [R18+0x14] ; /* 0x00001400121a7984 */
/* 0x000fe20000000800 */
/*0a90*/ FFMA R22, R22, R24, R27 ; /* 0x0000001816167223 */
/* 0x008fc6000000001b */
/*0aa0*/ LDS R24, [R18+0x10] ; /* 0x0000100012187984 */
/* 0x0001240000000800 */
/*0ab0*/ IADD3 R18, R18, 0x20, RZ ; /* 0x0000002012127810 */
/* 0x001fe20007ffe0ff */
/*0ac0*/ FFMA R22, R24, R25, R22 ; /* 0x0000001918167223 */
/* 0x010fe20000000016 */
/*0ad0*/ IADD3 R24, P2, R2, 0x20, RZ ; /* 0x0000002002187810 */
/* 0x000fc60007f5e0ff */
/*0ae0*/ FFMA R22, R26, R23, R22 ; /* 0x000000171a167223 */
/* 0x020fe40000000016 */
/*0af0*/ IMAD.X R3, RZ, RZ, R3, P2 ; /* 0x000000ffff037224 */
/* 0x000fe400010e0603 */
/*0b00*/ IMAD.MOV.U32 R2, RZ, RZ, R24 ; /* 0x000000ffff027224 */
/* 0x000fe400078e0018 */
/*0b10*/ ISETP.NE.U32.AND P2, PT, R21, RZ, PT ; /* 0x000000ff1500720c */
/* 0x000fc80003f45070 */
/*0b20*/ ISETP.NE.OR.EX P0, PT, R20, RZ, P0, P2 ; /* 0x000000ff1400720c */
/* 0x000fda0000705720 */
/*0b30*/ @!P0 BRA 0xc90 ; /* 0x0000015000008947 */
/* 0x000fea0003800000 */
/*0b40*/ LDG.E.CONSTANT R26, [R2.64+-0x8] ; /* 0xfffff808021a7981 */
/* 0x0000a8000c1e9900 */
/*0b50*/ LDG.E.CONSTANT R27, [R2.64+-0x4] ; /* 0xfffffc08021b7981 */
/* 0x0000e8000c1e9900 */
/*0b60*/ LDG.E.CONSTANT R24, [R2.64] ; /* 0x0000000802187981 */
/* 0x000128000c1e9900 */
/*0b70*/ LDG.E.CONSTANT R23, [R2.64+0x4] ; /* 0x0000040802177981 */
/* 0x000162000c1e9900 */
/*0b80*/ IADD3 R21, P0, R21, 0x4, RZ ; /* 0x0000000415157810 */
/* 0x000fc40007f1e0ff */
/*0b90*/ IADD3 R11, R11, 0x4, RZ ; /* 0x000000040b0b7810 */
/* 0x000fe20007ffe0ff */
/*0ba0*/ LDS R25, [R18+-0x8] ; /* 0xfffff80012197984 */
/* 0x000ea40000000800 */
/*0bb0*/ IMAD.X R20, RZ, RZ, R20, P0 ; /* 0x000000ffff147224 */
/* 0x000fe200000e0614 */
/*0bc0*/ ISETP.NE.U32.AND P0, PT, R21, RZ, PT ; /* 0x000000ff1500720c */
/* 0x000fe40003f05070 */
/*0bd0*/ IADD3 R2, P2, R2, 0x10, RZ ; /* 0x0000001002027810 */
/* 0x001fe40007f5e0ff */
/*0be0*/ ISETP.NE.AND.EX P0, PT, R20, RZ, PT, P0 ; /* 0x000000ff1400720c */
/* 0x000fc60003f05300 */
/*0bf0*/ IMAD.X R3, RZ, RZ, R3, P2 ; /* 0x000000ffff037224 */
/* 0x000fe400010e0603 */
/*0c00*/ FFMA R25, R25, R26, R22 ; /* 0x0000001a19197223 */
/* 0x004fe40000000016 */
/*0c10*/ LDS R22, [R18+-0x4] ; /* 0xfffffc0012167984 */
/* 0x000ee80000000800 */
/*0c20*/ LDS R26, [R18+0x4] ; /* 0x00000400121a7984 */
/* 0x000fe20000000800 */
/*0c30*/ FFMA R25, R22, R27, R25 ; /* 0x0000001b16197223 */
/* 0x008fc60000000019 */
/*0c40*/ LDS R22, [R18] ; /* 0x0000000012167984 */
/* 0x0001240000000800 */
/*0c50*/ IADD3 R18, R18, 0x10, RZ ; /* 0x0000001012127810 */
/* 0x001fe20007ffe0ff */
/*0c60*/ FFMA R22, R22, R24, R25 ; /* 0x0000001816167223 */
/* 0x010fc80000000019 */
/*0c70*/ FFMA R22, R26, R23, R22 ; /* 0x000000171a167223 */
/* 0x020fe20000000016 */
/*0c80*/ @P0 BRA 0xb40 ; /* 0xfffffeb000000947 */
/* 0x000fea000383ffff */
/*0c90*/ ISETP.NE.U32.AND P0, PT, R12, RZ, PT ; /* 0x000000ff0c00720c */
/* 0x000fc80003f05070 */
/*0ca0*/ ISETP.NE.AND.EX P0, PT, RZ, RZ, PT, P0 ; /* 0x000000ffff00720c */
/* 0x000fda0003f05300 */
/*0cb0*/ @!P0 BRA 0xe10 ; /* 0x0000015000008947 */
/* 0x000fea0003800000 */
/*0cc0*/ IADD3 R4, P0, R11, R4, RZ ; /* 0x000000040b047210 */
/* 0x000fc80007f1e0ff */
/*0cd0*/ LEA.HI.X.SX32 R19, R11, R19, 0x1, P0 ; /* 0x000000130b137211 */
/* 0x000fe400000f0eff */
/*0ce0*/ LEA R2, P0, R4, c[0x0][0x168], 0x2 ; /* 0x00005a0004027a11 */
/* 0x000fc800078010ff */
/*0cf0*/ LEA.HI.X R3, R4, c[0x0][0x16c], R19, 0x2, P0 ; /* 0x00005b0004037a11 */
/* 0x000fca00000f1413 */
/*0d00*/ LDG.E.CONSTANT R18, [R2.64] ; /* 0x0000000802127981 */
/* 0x000ea2000c1e9900 */
/*0d10*/ IMAD.IADD R4, R8, 0x1, R11 ; /* 0x0000000108047824 */
/* 0x000fe200078e020b */
/*0d20*/ ISETP.NE.U32.AND P0, PT, R12, 0x1, PT ; /* 0x000000010c00780c */
/* 0x000fc60003f05070 */
/*0d30*/ IMAD R4, R17, 0x20, R4 ; /* 0x0000002011047824 */
/* 0x000fe200078e0204 */
/*0d40*/ ISETP.NE.AND.EX P0, PT, RZ, RZ, PT, P0 ; /* 0x000000ffff00720c */
/* 0x000fc60003f05300 */
/*0d50*/ IMAD.SHL.U32 R19, R4, 0x4, RZ ; /* 0x0000000404137824 */
/* 0x000fca00078e00ff */
/*0d60*/ LDS R5, [R19] ; /* 0x0000000013057984 */
/* 0x000ea40000000800 */
/*0d70*/ FFMA R22, R5, R18, R22 ; /* 0x0000001205167223 */
/* 0x004fc60000000016 */
/*0d80*/ @!P0 BRA 0xe10 ; /* 0x0000008000008947 */
/* 0x000fea0003800000 */
/*0d90*/ ISETP.NE.U32.AND P0, PT, R12, 0x2, PT ; /* 0x000000020c00780c */
/* 0x000fe20003f05070 */
/*0da0*/ LDG.E.CONSTANT R4, [R2.64+0x4] ; /* 0x0000040802047981 */
/* 0x000ea6000c1e9900 */
/*0db0*/ ISETP.NE.AND.EX P0, PT, RZ, RZ, PT, P0 ; /* 0x000000ffff00720c */
/* 0x000fe20003f05300 */
/*0dc0*/ LDS R5, [R19+0x4] ; /* 0x0000040013057984 */
/* 0x000e980000000800 */
/*0dd0*/ @P0 LDG.E.CONSTANT R17, [R2.64+0x8] ; /* 0x0000080802110981 */
/* 0x000ee8000c1e9900 */
/*0de0*/ @P0 LDS R11, [R19+0x8] ; /* 0x00000800130b0984 */
/* 0x000ee20000000800 */
/*0df0*/ FFMA R22, R5, R4, R22 ; /* 0x0000000405167223 */
/* 0x004fc80000000016 */
/*0e00*/ @P0 FFMA R22, R11, R17, R22 ; /* 0x000000110b160223 */
/* 0x008fe40000000016 */
/*0e10*/ IADD3 R15, R15, 0x1, RZ ; /* 0x000000010f0f7810 */
/* 0x000fc80007ffe0ff */
/*0e20*/ ISETP.GE.U32.AND P0, PT, R15, c[0x0][0x188], PT ; /* 0x000062000f007a0c */
/* 0x000fc80003f06070 */
/*0e30*/ ISETP.GE.U32.AND.EX P0, PT, RZ, c[0x0][0x18c], PT, P0 ; /* 0x00006300ff007a0c */
/* 0x000fda0003f06100 */
/*0e40*/ @!P0 BRA 0x3c0 ; /* 0xfffff57000008947 */
/* 0x000fea000383ffff */
/*0e50*/ IMAD R10, R10, c[0x0][0x180], RZ ; /* 0x000060000a0a7a24 */
/* 0x000fe400078e02ff */
/*0e60*/ IMAD.WIDE.U32 R6, R9, c[0x0][0x180], R6 ; /* 0x0000600009067a25 */
/* 0x000fc800078e0006 */
/*0e70*/ IMAD R3, R9, c[0x0][0x184], R10 ; /* 0x0000610009037a24 */
/* 0x000fe200078e020a */
/*0e80*/ LEA R2, P0, R6, c[0x0][0x170], 0x2 ; /* 0x00005c0006027a11 */
/* 0x000fc600078010ff */
/*0e90*/ IMAD.IADD R3, R7, 0x1, R3 ; /* 0x0000000107037824 */
/* 0x000fca00078e0203 */
/*0ea0*/ LEA.HI.X R3, R6, c[0x0][0x174], R3, 0x2, P0 ; /* 0x00005d0006037a11 */
/* 0x000fca00000f1403 */
/*0eb0*/ STG.E [R2.64], R22 ; /* 0x0000001602007986 */
/* 0x000fe2000c101908 */
/*0ec0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0ed0*/ BRA 0xed0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0ee0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ef0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <cuda.h>
#include <stdio.h>
#include <time.h>
#include <stdlib.h>
#define BLOCK_WIDTH 32
// kernel
__global__ void tiledConvolution_2D_Kernel(float* d_m, const float* __restrict__ d_mask, float* d_n, size_t a, size_t b, size_t maskWidth, int N_TILE_WIDTH)
{
float result = 0;
// indexing variables
int n_row = blockIdx.y * N_TILE_WIDTH + threadIdx.y;
int n_col = blockIdx.x * N_TILE_WIDTH + threadIdx.x;
int m_row = n_row - maskWidth / 2;
int m_col = n_col - maskWidth / 2;
__shared__ float tile_m[BLOCK_WIDTH][BLOCK_WIDTH];
// thread boundary check for loading input tiles
if(m_row >= 0 && m_row < a && m_col >= 0 && m_col < b)
{
tile_m[threadIdx.y][threadIdx.x] = d_m[m_row * b + m_col];
}
else
{
tile_m[threadIdx.y][threadIdx.x] = 0;
}
__syncthreads();
// thread boundary check for calculation
if(threadIdx.y < N_TILE_WIDTH && threadIdx.x < N_TILE_WIDTH && n_row < a && n_col < b)
{
for(int i = 0; i < maskWidth; ++i)
{
for(int j = 0; j < maskWidth; ++j)
{
result += d_mask[i * maskWidth + j] * tile_m[threadIdx.y + i][threadIdx.x + j];
}
}
// write result
d_n[n_row * b + n_col] = result;
}
}
// CUDA error checking
void errorCheck(unsigned int line)
{
cudaError_t cudaError = cudaGetLastError();
if(cudaError != cudaSuccess)
{
printf("CUDA error in line %u in file %s: %s\n", line - 1, __FILE__, cudaGetErrorString(cudaError));
exit(EXIT_FAILURE);
}
}
// host function containing kernel call
void convolution_2D(float* m, float* mask, float* n, size_t a, size_t b, size_t maskWidth, int N_TILE_WIDTH)
{
dim3 numOfBlocks(ceil(b / (float) N_TILE_WIDTH), ceil(a / (float) N_TILE_WIDTH), 1);
dim3 numOfThreads(BLOCK_WIDTH, BLOCK_WIDTH, 1);
size_t bytes_m = a * b * sizeof(float);
size_t bytes_mask = maskWidth * maskWidth * sizeof(float);
float* d_m;
float* d_mask;
float* d_n;
cudaMalloc((void**) &d_m, bytes_m);
errorCheck(__LINE__);
cudaMalloc((void**) &d_mask, bytes_mask);
errorCheck(__LINE__);
cudaMalloc((void**) &d_n, bytes_m);
errorCheck(__LINE__);
cudaMemcpy(d_m, m, bytes_m, cudaMemcpyHostToDevice);
errorCheck(__LINE__);
cudaMemcpy(d_mask, mask, bytes_mask, cudaMemcpyHostToDevice);
errorCheck(__LINE__);
tiledConvolution_2D_Kernel<<<numOfBlocks, numOfThreads>>>(d_m, d_mask, d_n, a, b, maskWidth, N_TILE_WIDTH);
errorCheck(__LINE__);
cudaMemcpy(n, d_n, bytes_m, cudaMemcpyDeviceToHost);
errorCheck(__LINE__);
cudaFree(d_m);
errorCheck(__LINE__);
cudaFree(d_mask);
errorCheck(__LINE__);
cudaFree(d_n);
errorCheck(__LINE__);
}
int main()
{
struct timespec start, end;
srand(time(NULL));
size_t a = rand() % 257 + 3840;
size_t b = rand() % 257 + 3840;
size_t maskWidth = 11;
int N_TILE_WIDTH = BLOCK_WIDTH - (maskWidth - 1);
float* m = (float*) malloc(a * b * sizeof(float));
float* mask = (float*) malloc(maskWidth * maskWidth * sizeof(float));
float* n = (float*) malloc(a * b * sizeof(float));
for(int i = 0; i < a * b; ++i)
{
m[i] = rand() % 129 - 64;
}
for(int j = 0; j < maskWidth * maskWidth; ++j)
{
mask[j] = rand() % 1001 / 1000.0;
}
clock_gettime(CLOCK_REALTIME, &start);
// do convolution
convolution_2D(m, mask, n, a, b, maskWidth, N_TILE_WIDTH);
clock_gettime(CLOCK_REALTIME, &end);
time_t execTime = (end.tv_sec - start.tv_sec) * 1000000 + (end.tv_nsec - start.tv_nsec) / 1000;
printf("Execution time: %d microseconds.", execTime);
return 0;
} | .file "tmpxft_000b2b0e_00000000-6_tiledConvolution-2D.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "/home/ubuntu/Datasets/stackv2/train-structured/daniel0306123/cuda/master/convolution/tiledConvolution-2D.cu"
.align 8
.LC1:
.string "CUDA error in line %u in file %s: %s\n"
.text
.globl _Z10errorCheckj
.type _Z10errorCheckj, @function
_Z10errorCheckj:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movl %edi, %ebx
call cudaGetLastError@PLT
testl %eax, %eax
jne .L6
popq %rbx
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L6:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
leal -1(%rbx), %edx
leaq .LC0(%rip), %rcx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size _Z10errorCheckj, .-_Z10errorCheckj
.globl _Z55__device_stub__Z26tiledConvolution_2D_KernelPfPKfS_mmmiPfPKfS_mmmi
.type _Z55__device_stub__Z26tiledConvolution_2D_KernelPfPKfS_mmmiPfPKfS_mmmi, @function
_Z55__device_stub__Z26tiledConvolution_2D_KernelPfPKfS_mmmiPfPKfS_mmmi:
.LFB2084:
.cfi_startproc
endbr64
subq $200, %rsp
.cfi_def_cfa_offset 208
movq %rdi, 40(%rsp)
movq %rdx, 32(%rsp)
movq %rcx, 24(%rsp)
movq %r8, 16(%rsp)
movq %r9, 8(%rsp)
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 128(%rsp)
movq %rsi, 56(%rsp)
leaq 56(%rsp), %rax
movq %rax, 136(%rsp)
leaq 32(%rsp), %rax
movq %rax, 144(%rsp)
leaq 24(%rsp), %rax
movq %rax, 152(%rsp)
leaq 16(%rsp), %rax
movq %rax, 160(%rsp)
leaq 8(%rsp), %rax
movq %rax, 168(%rsp)
leaq 208(%rsp), %rax
movq %rax, 176(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L11
.L7:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L12
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 216
pushq 72(%rsp)
.cfi_def_cfa_offset 224
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq _Z26tiledConvolution_2D_KernelPfPKfS_mmmi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L7
.L12:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z55__device_stub__Z26tiledConvolution_2D_KernelPfPKfS_mmmiPfPKfS_mmmi, .-_Z55__device_stub__Z26tiledConvolution_2D_KernelPfPKfS_mmmiPfPKfS_mmmi
.globl _Z26tiledConvolution_2D_KernelPfPKfS_mmmi
.type _Z26tiledConvolution_2D_KernelPfPKfS_mmmi, @function
_Z26tiledConvolution_2D_KernelPfPKfS_mmmi:
.LFB2085:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
call _Z55__device_stub__Z26tiledConvolution_2D_KernelPfPKfS_mmmiPfPKfS_mmmi
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z26tiledConvolution_2D_KernelPfPKfS_mmmi, .-_Z26tiledConvolution_2D_KernelPfPKfS_mmmi
.globl _Z14convolution_2DPfS_S_mmmi
.type _Z14convolution_2DPfS_S_mmmi, @function
_Z14convolution_2DPfS_S_mmmi:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $88, %rsp
.cfi_def_cfa_offset 144
movq %rdi, %r15
movq %rsi, (%rsp)
movq %rdx, 8(%rsp)
movq %rcx, %rbp
movq %r8, %r12
movq %r9, %r13
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
pxor %xmm4, %xmm4
cvtsi2ssl 144(%rsp), %xmm4
testq %rcx, %rcx
js .L16
pxor %xmm0, %xmm0
cvtsi2ssq %rcx, %xmm0
.L17:
divss %xmm4, %xmm0
movaps %xmm0, %xmm1
movss .LC5(%rip), %xmm3
movaps %xmm0, %xmm2
andps %xmm3, %xmm2
movss .LC2(%rip), %xmm5
ucomiss %xmm2, %xmm5
jbe .L18
cvttss2sil %xmm0, %eax
pxor %xmm2, %xmm2
cvtsi2ssl %eax, %xmm2
cmpnless %xmm2, %xmm1
movss .LC4(%rip), %xmm5
andps %xmm5, %xmm1
addss %xmm2, %xmm1
andnps %xmm0, %xmm3
orps %xmm3, %xmm1
.L18:
testq %r12, %r12
js .L19
pxor %xmm0, %xmm0
cvtsi2ssq %r12, %xmm0
.L20:
divss %xmm4, %xmm0
movaps %xmm0, %xmm4
movss .LC5(%rip), %xmm3
movaps %xmm0, %xmm2
andps %xmm3, %xmm2
movss .LC2(%rip), %xmm5
ucomiss %xmm2, %xmm5
jbe .L21
cvttss2sil %xmm0, %eax
pxor %xmm2, %xmm2
cvtsi2ssl %eax, %xmm2
cmpnless %xmm2, %xmm4
movss .LC4(%rip), %xmm5
andps %xmm5, %xmm4
addss %xmm2, %xmm4
andnps %xmm0, %xmm3
orps %xmm3, %xmm4
.L21:
cvttss2siq %xmm4, %rax
movl %eax, 48(%rsp)
cvttss2siq %xmm1, %rax
movl %eax, 52(%rsp)
movl $1, 56(%rsp)
movl $32, 60(%rsp)
movl $32, 64(%rsp)
movl $1, 68(%rsp)
movq %rbp, %rbx
imulq %r12, %rbx
salq $2, %rbx
movq %r13, %r14
imulq %r13, %r14
salq $2, %r14
leaq 24(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl $76, %edi
call _Z10errorCheckj
leaq 32(%rsp), %rdi
movq %r14, %rsi
call cudaMalloc@PLT
movl $78, %edi
call _Z10errorCheckj
leaq 40(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl $80, %edi
call _Z10errorCheckj
movl $1, %ecx
movq %rbx, %rdx
movq %r15, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl $83, %edi
call _Z10errorCheckj
movl $1, %ecx
movq %r14, %rdx
movq (%rsp), %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
movl $85, %edi
call _Z10errorCheckj
movl 68(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movq 48(%rsp), %rdi
movl 56(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L25
.L22:
movl $88, %edi
call _Z10errorCheckj
movl $2, %ecx
movq %rbx, %rdx
movq 40(%rsp), %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $91, %edi
call _Z10errorCheckj
movq 24(%rsp), %rdi
call cudaFree@PLT
movl $94, %edi
call _Z10errorCheckj
movq 32(%rsp), %rdi
call cudaFree@PLT
movl $96, %edi
call _Z10errorCheckj
movq 40(%rsp), %rdi
call cudaFree@PLT
movl $98, %edi
call _Z10errorCheckj
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L26
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L16:
.cfi_restore_state
movq %rcx, %rax
shrq %rax
movq %rcx, %rdx
andl $1, %edx
orq %rdx, %rax
pxor %xmm0, %xmm0
cvtsi2ssq %rax, %xmm0
addss %xmm0, %xmm0
jmp .L17
.L19:
movq %r12, %rax
shrq %rax
movq %r12, %rdx
andl $1, %edx
orq %rdx, %rax
pxor %xmm0, %xmm0
cvtsi2ssq %rax, %xmm0
addss %xmm0, %xmm0
jmp .L20
.L25:
subq $8, %rsp
.cfi_def_cfa_offset 152
movl 152(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 160
movq %r13, %r9
movq %r12, %r8
movq %rbp, %rcx
movq 56(%rsp), %rdx
movq 48(%rsp), %rsi
movq 40(%rsp), %rdi
call _Z55__device_stub__Z26tiledConvolution_2D_KernelPfPKfS_mmmiPfPKfS_mmmi
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L22
.L26:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size _Z14convolution_2DPfS_S_mmmi, .-_Z14convolution_2DPfS_S_mmmi
.section .rodata.str1.8
.align 8
.LC7:
.string "Execution time: %d microseconds."
.text
.globl main
.type main, @function
main:
.LFB2059:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $72, %rsp
.cfi_def_cfa_offset 128
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $0, %edi
call time@PLT
movl %eax, %edi
call srand@PLT
call rand@PLT
movslq %eax, %rdx
imulq $2139127681, %rdx, %rdx
sarq $39, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
movl %edx, %ecx
sall $8, %ecx
addl %ecx, %edx
subl %edx, %eax
leal 3840(%rax), %r12d
movslq %r12d, %r12
call rand@PLT
movslq %eax, %rdx
imulq $2139127681, %rdx, %rdx
sarq $39, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
movl %edx, %ecx
sall $8, %ecx
addl %ecx, %edx
subl %edx, %eax
leal 3840(%rax), %r13d
movslq %r13d, %r13
movq %r12, %rbp
imulq %r13, %rbp
salq $2, %rbp
movq %rbp, %rdi
call malloc@PLT
movq %rax, %r14
movl $484, %edi
call malloc@PLT
movq %rax, %r15
movq %rbp, %rdi
call malloc@PLT
movq %rax, 8(%rsp)
movq %r14, %rbx
addq %r14, %rbp
.L28:
call rand@PLT
movslq %eax, %rdx
imulq $266354561, %rdx, %rdx
sarq $35, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
movl %edx, %ecx
sall $7, %ecx
addl %ecx, %edx
subl %edx, %eax
subl $64, %eax
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, (%rbx)
addq $4, %rbx
cmpq %rbp, %rbx
jne .L28
movq %r15, %rbx
leaq 484(%r15), %rbp
.L29:
call rand@PLT
movslq %eax, %rdx
imulq $1098413215, %rdx, %rdx
sarq $40, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
imull $1001, %edx, %edx
subl %edx, %eax
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
divsd .LC6(%rip), %xmm0
cvtsd2ss %xmm0, %xmm0
movss %xmm0, (%rbx)
addq $4, %rbx
cmpq %rbp, %rbx
jne .L29
leaq 16(%rsp), %rsi
movl $0, %edi
call clock_gettime@PLT
subq $8, %rsp
.cfi_def_cfa_offset 136
pushq $22
.cfi_def_cfa_offset 144
movl $11, %r9d
movq %r13, %r8
movq %r12, %rcx
movq 24(%rsp), %rdx
movq %r15, %rsi
movq %r14, %rdi
call _Z14convolution_2DPfS_S_mmmi
leaq 48(%rsp), %rsi
movl $0, %edi
call clock_gettime@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
movq 32(%rsp), %rcx
subq 16(%rsp), %rcx
imulq $1000000, %rcx, %rcx
movq 40(%rsp), %rsi
subq 24(%rsp), %rsi
movabsq $2361183241434822607, %rdx
movq %rsi, %rax
imulq %rdx
sarq $7, %rdx
sarq $63, %rsi
subq %rsi, %rdx
addq %rcx, %rdx
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L34
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L34:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size main, .-main
.section .rodata.str1.8
.align 8
.LC8:
.string "_Z26tiledConvolution_2D_KernelPfPKfS_mmmi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _Z26tiledConvolution_2D_KernelPfPKfS_mmmi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC2:
.long 1258291200
.align 4
.LC4:
.long 1065353216
.align 4
.LC5:
.long 2147483647
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC6:
.long 0
.long 1083129856
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <cuda.h>
#include <stdio.h>
#include <time.h>
#include <stdlib.h>
#define BLOCK_WIDTH 32
// kernel
__global__ void tiledConvolution_2D_Kernel(float* d_m, const float* __restrict__ d_mask, float* d_n, size_t a, size_t b, size_t maskWidth, int N_TILE_WIDTH)
{
float result = 0;
// indexing variables
int n_row = blockIdx.y * N_TILE_WIDTH + threadIdx.y;
int n_col = blockIdx.x * N_TILE_WIDTH + threadIdx.x;
int m_row = n_row - maskWidth / 2;
int m_col = n_col - maskWidth / 2;
__shared__ float tile_m[BLOCK_WIDTH][BLOCK_WIDTH];
// thread boundary check for loading input tiles
if(m_row >= 0 && m_row < a && m_col >= 0 && m_col < b)
{
tile_m[threadIdx.y][threadIdx.x] = d_m[m_row * b + m_col];
}
else
{
tile_m[threadIdx.y][threadIdx.x] = 0;
}
__syncthreads();
// thread boundary check for calculation
if(threadIdx.y < N_TILE_WIDTH && threadIdx.x < N_TILE_WIDTH && n_row < a && n_col < b)
{
for(int i = 0; i < maskWidth; ++i)
{
for(int j = 0; j < maskWidth; ++j)
{
result += d_mask[i * maskWidth + j] * tile_m[threadIdx.y + i][threadIdx.x + j];
}
}
// write result
d_n[n_row * b + n_col] = result;
}
}
// CUDA error checking
void errorCheck(unsigned int line)
{
cudaError_t cudaError = cudaGetLastError();
if(cudaError != cudaSuccess)
{
printf("CUDA error in line %u in file %s: %s\n", line - 1, __FILE__, cudaGetErrorString(cudaError));
exit(EXIT_FAILURE);
}
}
// host function containing kernel call
void convolution_2D(float* m, float* mask, float* n, size_t a, size_t b, size_t maskWidth, int N_TILE_WIDTH)
{
dim3 numOfBlocks(ceil(b / (float) N_TILE_WIDTH), ceil(a / (float) N_TILE_WIDTH), 1);
dim3 numOfThreads(BLOCK_WIDTH, BLOCK_WIDTH, 1);
size_t bytes_m = a * b * sizeof(float);
size_t bytes_mask = maskWidth * maskWidth * sizeof(float);
float* d_m;
float* d_mask;
float* d_n;
cudaMalloc((void**) &d_m, bytes_m);
errorCheck(__LINE__);
cudaMalloc((void**) &d_mask, bytes_mask);
errorCheck(__LINE__);
cudaMalloc((void**) &d_n, bytes_m);
errorCheck(__LINE__);
cudaMemcpy(d_m, m, bytes_m, cudaMemcpyHostToDevice);
errorCheck(__LINE__);
cudaMemcpy(d_mask, mask, bytes_mask, cudaMemcpyHostToDevice);
errorCheck(__LINE__);
tiledConvolution_2D_Kernel<<<numOfBlocks, numOfThreads>>>(d_m, d_mask, d_n, a, b, maskWidth, N_TILE_WIDTH);
errorCheck(__LINE__);
cudaMemcpy(n, d_n, bytes_m, cudaMemcpyDeviceToHost);
errorCheck(__LINE__);
cudaFree(d_m);
errorCheck(__LINE__);
cudaFree(d_mask);
errorCheck(__LINE__);
cudaFree(d_n);
errorCheck(__LINE__);
}
int main()
{
struct timespec start, end;
srand(time(NULL));
size_t a = rand() % 257 + 3840;
size_t b = rand() % 257 + 3840;
size_t maskWidth = 11;
int N_TILE_WIDTH = BLOCK_WIDTH - (maskWidth - 1);
float* m = (float*) malloc(a * b * sizeof(float));
float* mask = (float*) malloc(maskWidth * maskWidth * sizeof(float));
float* n = (float*) malloc(a * b * sizeof(float));
for(int i = 0; i < a * b; ++i)
{
m[i] = rand() % 129 - 64;
}
for(int j = 0; j < maskWidth * maskWidth; ++j)
{
mask[j] = rand() % 1001 / 1000.0;
}
clock_gettime(CLOCK_REALTIME, &start);
// do convolution
convolution_2D(m, mask, n, a, b, maskWidth, N_TILE_WIDTH);
clock_gettime(CLOCK_REALTIME, &end);
time_t execTime = (end.tv_sec - start.tv_sec) * 1000000 + (end.tv_nsec - start.tv_nsec) / 1000;
printf("Execution time: %d microseconds.", execTime);
return 0;
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <time.h>
#include <stdlib.h>
#define BLOCK_WIDTH 32
// kernel
__global__ void tiledConvolution_2D_Kernel(float* d_m, const float* __restrict__ d_mask, float* d_n, size_t a, size_t b, size_t maskWidth, int N_TILE_WIDTH)
{
float result = 0;
// indexing variables
int n_row = blockIdx.y * N_TILE_WIDTH + threadIdx.y;
int n_col = blockIdx.x * N_TILE_WIDTH + threadIdx.x;
int m_row = n_row - maskWidth / 2;
int m_col = n_col - maskWidth / 2;
__shared__ float tile_m[BLOCK_WIDTH][BLOCK_WIDTH];
// thread boundary check for loading input tiles
if(m_row >= 0 && m_row < a && m_col >= 0 && m_col < b)
{
tile_m[threadIdx.y][threadIdx.x] = d_m[m_row * b + m_col];
}
else
{
tile_m[threadIdx.y][threadIdx.x] = 0;
}
__syncthreads();
// thread boundary check for calculation
if(threadIdx.y < N_TILE_WIDTH && threadIdx.x < N_TILE_WIDTH && n_row < a && n_col < b)
{
for(int i = 0; i < maskWidth; ++i)
{
for(int j = 0; j < maskWidth; ++j)
{
result += d_mask[i * maskWidth + j] * tile_m[threadIdx.y + i][threadIdx.x + j];
}
}
// write result
d_n[n_row * b + n_col] = result;
}
}
// CUDA error checking
void errorCheck(unsigned int line)
{
hipError_t hipError_t = hipGetLastError();
if(hipError_t != hipSuccess)
{
printf("CUDA error in line %u in file %s: %s\n", line - 1, __FILE__, hipGetErrorString(hipError_t));
exit(EXIT_FAILURE);
}
}
// host function containing kernel call
void convolution_2D(float* m, float* mask, float* n, size_t a, size_t b, size_t maskWidth, int N_TILE_WIDTH)
{
dim3 numOfBlocks(ceil(b / (float) N_TILE_WIDTH), ceil(a / (float) N_TILE_WIDTH), 1);
dim3 numOfThreads(BLOCK_WIDTH, BLOCK_WIDTH, 1);
size_t bytes_m = a * b * sizeof(float);
size_t bytes_mask = maskWidth * maskWidth * sizeof(float);
float* d_m;
float* d_mask;
float* d_n;
hipMalloc((void**) &d_m, bytes_m);
errorCheck(__LINE__);
hipMalloc((void**) &d_mask, bytes_mask);
errorCheck(__LINE__);
hipMalloc((void**) &d_n, bytes_m);
errorCheck(__LINE__);
hipMemcpy(d_m, m, bytes_m, hipMemcpyHostToDevice);
errorCheck(__LINE__);
hipMemcpy(d_mask, mask, bytes_mask, hipMemcpyHostToDevice);
errorCheck(__LINE__);
tiledConvolution_2D_Kernel<<<numOfBlocks, numOfThreads>>>(d_m, d_mask, d_n, a, b, maskWidth, N_TILE_WIDTH);
errorCheck(__LINE__);
hipMemcpy(n, d_n, bytes_m, hipMemcpyDeviceToHost);
errorCheck(__LINE__);
hipFree(d_m);
errorCheck(__LINE__);
hipFree(d_mask);
errorCheck(__LINE__);
hipFree(d_n);
errorCheck(__LINE__);
}
int main()
{
struct timespec start, end;
srand(time(NULL));
size_t a = rand() % 257 + 3840;
size_t b = rand() % 257 + 3840;
size_t maskWidth = 11;
int N_TILE_WIDTH = BLOCK_WIDTH - (maskWidth - 1);
float* m = (float*) malloc(a * b * sizeof(float));
float* mask = (float*) malloc(maskWidth * maskWidth * sizeof(float));
float* n = (float*) malloc(a * b * sizeof(float));
for(int i = 0; i < a * b; ++i)
{
m[i] = rand() % 129 - 64;
}
for(int j = 0; j < maskWidth * maskWidth; ++j)
{
mask[j] = rand() % 1001 / 1000.0;
}
clock_gettime(CLOCK_REALTIME, &start);
// do convolution
convolution_2D(m, mask, n, a, b, maskWidth, N_TILE_WIDTH);
clock_gettime(CLOCK_REALTIME, &end);
time_t execTime = (end.tv_sec - start.tv_sec) * 1000000 + (end.tv_nsec - start.tv_nsec) / 1000;
printf("Execution time: %d microseconds.", execTime);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <time.h>
#include <stdlib.h>
#define BLOCK_WIDTH 32
// kernel
__global__ void tiledConvolution_2D_Kernel(float* d_m, const float* __restrict__ d_mask, float* d_n, size_t a, size_t b, size_t maskWidth, int N_TILE_WIDTH)
{
float result = 0;
// indexing variables
int n_row = blockIdx.y * N_TILE_WIDTH + threadIdx.y;
int n_col = blockIdx.x * N_TILE_WIDTH + threadIdx.x;
int m_row = n_row - maskWidth / 2;
int m_col = n_col - maskWidth / 2;
__shared__ float tile_m[BLOCK_WIDTH][BLOCK_WIDTH];
// thread boundary check for loading input tiles
if(m_row >= 0 && m_row < a && m_col >= 0 && m_col < b)
{
tile_m[threadIdx.y][threadIdx.x] = d_m[m_row * b + m_col];
}
else
{
tile_m[threadIdx.y][threadIdx.x] = 0;
}
__syncthreads();
// thread boundary check for calculation
if(threadIdx.y < N_TILE_WIDTH && threadIdx.x < N_TILE_WIDTH && n_row < a && n_col < b)
{
for(int i = 0; i < maskWidth; ++i)
{
for(int j = 0; j < maskWidth; ++j)
{
result += d_mask[i * maskWidth + j] * tile_m[threadIdx.y + i][threadIdx.x + j];
}
}
// write result
d_n[n_row * b + n_col] = result;
}
}
// CUDA error checking
void errorCheck(unsigned int line)
{
hipError_t hipError_t = hipGetLastError();
if(hipError_t != hipSuccess)
{
printf("CUDA error in line %u in file %s: %s\n", line - 1, __FILE__, hipGetErrorString(hipError_t));
exit(EXIT_FAILURE);
}
}
// host function containing kernel call
void convolution_2D(float* m, float* mask, float* n, size_t a, size_t b, size_t maskWidth, int N_TILE_WIDTH)
{
dim3 numOfBlocks(ceil(b / (float) N_TILE_WIDTH), ceil(a / (float) N_TILE_WIDTH), 1);
dim3 numOfThreads(BLOCK_WIDTH, BLOCK_WIDTH, 1);
size_t bytes_m = a * b * sizeof(float);
size_t bytes_mask = maskWidth * maskWidth * sizeof(float);
float* d_m;
float* d_mask;
float* d_n;
hipMalloc((void**) &d_m, bytes_m);
errorCheck(__LINE__);
hipMalloc((void**) &d_mask, bytes_mask);
errorCheck(__LINE__);
hipMalloc((void**) &d_n, bytes_m);
errorCheck(__LINE__);
hipMemcpy(d_m, m, bytes_m, hipMemcpyHostToDevice);
errorCheck(__LINE__);
hipMemcpy(d_mask, mask, bytes_mask, hipMemcpyHostToDevice);
errorCheck(__LINE__);
tiledConvolution_2D_Kernel<<<numOfBlocks, numOfThreads>>>(d_m, d_mask, d_n, a, b, maskWidth, N_TILE_WIDTH);
errorCheck(__LINE__);
hipMemcpy(n, d_n, bytes_m, hipMemcpyDeviceToHost);
errorCheck(__LINE__);
hipFree(d_m);
errorCheck(__LINE__);
hipFree(d_mask);
errorCheck(__LINE__);
hipFree(d_n);
errorCheck(__LINE__);
}
int main()
{
struct timespec start, end;
srand(time(NULL));
size_t a = rand() % 257 + 3840;
size_t b = rand() % 257 + 3840;
size_t maskWidth = 11;
int N_TILE_WIDTH = BLOCK_WIDTH - (maskWidth - 1);
float* m = (float*) malloc(a * b * sizeof(float));
float* mask = (float*) malloc(maskWidth * maskWidth * sizeof(float));
float* n = (float*) malloc(a * b * sizeof(float));
for(int i = 0; i < a * b; ++i)
{
m[i] = rand() % 129 - 64;
}
for(int j = 0; j < maskWidth * maskWidth; ++j)
{
mask[j] = rand() % 1001 / 1000.0;
}
clock_gettime(CLOCK_REALTIME, &start);
// do convolution
convolution_2D(m, mask, n, a, b, maskWidth, N_TILE_WIDTH);
clock_gettime(CLOCK_REALTIME, &end);
time_t execTime = (end.tv_sec - start.tv_sec) * 1000000 + (end.tv_nsec - start.tv_nsec) / 1000;
printf("Execution time: %d microseconds.", execTime);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z26tiledConvolution_2D_KernelPfPKfS_mmmi
.globl _Z26tiledConvolution_2D_KernelPfPKfS_mmmi
.p2align 8
.type _Z26tiledConvolution_2D_KernelPfPKfS_mmmi,@function
_Z26tiledConvolution_2D_KernelPfPKfS_mmmi:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x30
s_load_b64 s[8:9], s[0:1], 0x28
v_bfe_u32 v5, v0, 10, 10
s_load_b128 s[4:7], s[0:1], 0x18
v_dual_mov_b32 v7, 0 :: v_dual_and_b32 v0, 0x3ff, v0
s_mov_b32 s10, exec_lo
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[1:2], null, s15, s3, v[5:6]
v_alignbit_b32 v2, s9, s8, 1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[3:4], null, s14, s3, v[0:1]
v_sub_nc_u32_e32 v6, v1, v2
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_lt_i32_e32 -1, v6
s_cbranch_execz .LBB0_6
v_mov_b32_e32 v7, 0
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v8, v3, v2
v_cmp_gt_u64_e32 vcc_lo, s[4:5], v[6:7]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_lt_i32_e64 s2, -1, v8
s_and_b32 s11, s2, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s2, s11
s_cbranch_execz .LBB0_5
v_mov_b32_e32 v9, 0
s_mov_b32 s11, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_u64_e64 s[6:7], v[8:9]
s_cbranch_execz .LBB0_4
v_mad_u64_u32 v[10:11], null, v6, s6, 0
s_load_b64 s[12:13], s[0:1], 0x0
v_lshlrev_b64 v[8:9], 2, v[8:9]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mov_b32_e32 v2, v11
v_mad_u64_u32 v[11:12], null, v6, s7, v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[6:7], 2, v[10:11]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s12, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, s13, v7, vcc_lo
v_add_co_u32 v6, vcc_lo, v2, v8
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v7, vcc_lo, v4, v9, vcc_lo
global_load_b32 v9, v[6:7], off
.LBB0_4:
s_or_b32 exec_lo, exec_lo, s11
s_waitcnt vmcnt(0)
v_mov_b32_e32 v7, v9
.LBB0_5:
s_or_b32 exec_lo, exec_lo, s2
.LBB0_6:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
s_or_b32 exec_lo, exec_lo, s10
v_lshlrev_b32_e32 v2, 2, v0
s_mov_b32 s2, exec_lo
v_lshl_add_u32 v2, v5, 7, v2
ds_store_b32 v2, v7
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_gt_u32_e64 s3, v5
s_cbranch_execz .LBB0_15
v_ashrrev_i32_e32 v2, 31, v1
v_ashrrev_i32_e32 v4, 31, v3
v_cmp_gt_u32_e64 s2, s3, v0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cmp_gt_u64_e32 vcc_lo, s[4:5], v[1:2]
v_cmp_gt_u64_e64 s3, s[6:7], v[3:4]
s_delay_alu instid0(VALU_DEP_3)
s_and_b32 s2, s2, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
s_and_b32 s2, s3, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 exec_lo, exec_lo, s2
s_cbranch_execz .LBB0_15
s_cmp_eq_u64 s[8:9], 0
s_mov_b64 s[2:3], 0
s_cbranch_scc1 .LBB0_13
s_load_b64 s[4:5], s[0:1], 0x8
v_lshlrev_b32_e32 v0, 2, v0
s_lshl_b64 s[10:11], s[8:9], 2
s_delay_alu instid0(VALU_DEP_1)
v_lshl_add_u32 v5, v5, 7, v0
v_mov_b32_e32 v0, 0
.p2align 6
.LBB0_10:
s_delay_alu instid0(VALU_DEP_2)
v_mov_b32_e32 v6, v5
s_mov_b64 s[12:13], 0
s_waitcnt lgkmcnt(0)
s_mov_b64 s[14:15], s[4:5]
.LBB0_11:
s_load_b32 s16, s[14:15], 0x0
ds_load_b32 v7, v6
s_add_u32 s12, s12, 1
s_addc_u32 s13, s13, 0
v_add_nc_u32_e32 v6, 4, v6
v_cmp_ge_u64_e64 s17, s[12:13], s[8:9]
s_add_u32 s14, s14, 4
s_addc_u32 s15, s15, 0
s_delay_alu instid0(VALU_DEP_1)
s_and_b32 vcc_lo, exec_lo, s17
s_waitcnt lgkmcnt(0)
v_fmac_f32_e32 v0, s16, v7
s_cbranch_vccz .LBB0_11
s_add_u32 s2, s2, 1
s_addc_u32 s3, s3, 0
v_add_nc_u32_e32 v5, 0x80, v5
v_cmp_ge_u64_e64 s12, s[2:3], s[8:9]
s_add_u32 s4, s4, s10
s_addc_u32 s5, s5, s11
s_delay_alu instid0(VALU_DEP_1)
s_and_b32 vcc_lo, exec_lo, s12
s_cbranch_vccz .LBB0_10
s_branch .LBB0_14
.LBB0_13:
v_mov_b32_e32 v0, 0
.LBB0_14:
s_load_b64 s[0:1], s[0:1], 0x10
v_mul_lo_u32 v2, v2, s6
v_mul_lo_u32 v7, v1, s7
v_mad_u64_u32 v[5:6], null, v1, s6, 0
v_lshlrev_b64 v[3:4], 2, v[3:4]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add3_u32 v6, v6, v7, v2
v_lshlrev_b64 v[1:2], 2, v[5:6]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v1, vcc_lo, s0, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v1, vcc_lo, v1, v3
v_add_co_ci_u32_e32 v2, vcc_lo, v2, v4, vcc_lo
global_store_b32 v[1:2], v0, off
.LBB0_15:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z26tiledConvolution_2D_KernelPfPKfS_mmmi
.amdhsa_group_segment_fixed_size 4096
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 52
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 13
.amdhsa_next_free_sgpr 18
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z26tiledConvolution_2D_KernelPfPKfS_mmmi, .Lfunc_end0-_Z26tiledConvolution_2D_KernelPfPKfS_mmmi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .actual_access: read_only
.address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 8
.value_kind: by_value
- .offset: 32
.size: 8
.value_kind: by_value
- .offset: 40
.size: 8
.value_kind: by_value
- .offset: 48
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 4096
.kernarg_segment_align: 8
.kernarg_segment_size: 52
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z26tiledConvolution_2D_KernelPfPKfS_mmmi
.private_segment_fixed_size: 0
.sgpr_count: 20
.sgpr_spill_count: 0
.symbol: _Z26tiledConvolution_2D_KernelPfPKfS_mmmi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 13
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <time.h>
#include <stdlib.h>
#define BLOCK_WIDTH 32
// kernel
__global__ void tiledConvolution_2D_Kernel(float* d_m, const float* __restrict__ d_mask, float* d_n, size_t a, size_t b, size_t maskWidth, int N_TILE_WIDTH)
{
float result = 0;
// indexing variables
int n_row = blockIdx.y * N_TILE_WIDTH + threadIdx.y;
int n_col = blockIdx.x * N_TILE_WIDTH + threadIdx.x;
int m_row = n_row - maskWidth / 2;
int m_col = n_col - maskWidth / 2;
__shared__ float tile_m[BLOCK_WIDTH][BLOCK_WIDTH];
// thread boundary check for loading input tiles
if(m_row >= 0 && m_row < a && m_col >= 0 && m_col < b)
{
tile_m[threadIdx.y][threadIdx.x] = d_m[m_row * b + m_col];
}
else
{
tile_m[threadIdx.y][threadIdx.x] = 0;
}
__syncthreads();
// thread boundary check for calculation
if(threadIdx.y < N_TILE_WIDTH && threadIdx.x < N_TILE_WIDTH && n_row < a && n_col < b)
{
for(int i = 0; i < maskWidth; ++i)
{
for(int j = 0; j < maskWidth; ++j)
{
result += d_mask[i * maskWidth + j] * tile_m[threadIdx.y + i][threadIdx.x + j];
}
}
// write result
d_n[n_row * b + n_col] = result;
}
}
// CUDA error checking
void errorCheck(unsigned int line)
{
hipError_t hipError_t = hipGetLastError();
if(hipError_t != hipSuccess)
{
printf("CUDA error in line %u in file %s: %s\n", line - 1, __FILE__, hipGetErrorString(hipError_t));
exit(EXIT_FAILURE);
}
}
// host function containing kernel call
void convolution_2D(float* m, float* mask, float* n, size_t a, size_t b, size_t maskWidth, int N_TILE_WIDTH)
{
dim3 numOfBlocks(ceil(b / (float) N_TILE_WIDTH), ceil(a / (float) N_TILE_WIDTH), 1);
dim3 numOfThreads(BLOCK_WIDTH, BLOCK_WIDTH, 1);
size_t bytes_m = a * b * sizeof(float);
size_t bytes_mask = maskWidth * maskWidth * sizeof(float);
float* d_m;
float* d_mask;
float* d_n;
hipMalloc((void**) &d_m, bytes_m);
errorCheck(__LINE__);
hipMalloc((void**) &d_mask, bytes_mask);
errorCheck(__LINE__);
hipMalloc((void**) &d_n, bytes_m);
errorCheck(__LINE__);
hipMemcpy(d_m, m, bytes_m, hipMemcpyHostToDevice);
errorCheck(__LINE__);
hipMemcpy(d_mask, mask, bytes_mask, hipMemcpyHostToDevice);
errorCheck(__LINE__);
tiledConvolution_2D_Kernel<<<numOfBlocks, numOfThreads>>>(d_m, d_mask, d_n, a, b, maskWidth, N_TILE_WIDTH);
errorCheck(__LINE__);
hipMemcpy(n, d_n, bytes_m, hipMemcpyDeviceToHost);
errorCheck(__LINE__);
hipFree(d_m);
errorCheck(__LINE__);
hipFree(d_mask);
errorCheck(__LINE__);
hipFree(d_n);
errorCheck(__LINE__);
}
int main()
{
struct timespec start, end;
srand(time(NULL));
size_t a = rand() % 257 + 3840;
size_t b = rand() % 257 + 3840;
size_t maskWidth = 11;
int N_TILE_WIDTH = BLOCK_WIDTH - (maskWidth - 1);
float* m = (float*) malloc(a * b * sizeof(float));
float* mask = (float*) malloc(maskWidth * maskWidth * sizeof(float));
float* n = (float*) malloc(a * b * sizeof(float));
for(int i = 0; i < a * b; ++i)
{
m[i] = rand() % 129 - 64;
}
for(int j = 0; j < maskWidth * maskWidth; ++j)
{
mask[j] = rand() % 1001 / 1000.0;
}
clock_gettime(CLOCK_REALTIME, &start);
// do convolution
convolution_2D(m, mask, n, a, b, maskWidth, N_TILE_WIDTH);
clock_gettime(CLOCK_REALTIME, &end);
time_t execTime = (end.tv_sec - start.tv_sec) * 1000000 + (end.tv_nsec - start.tv_nsec) / 1000;
printf("Execution time: %d microseconds.", execTime);
return 0;
} | .text
.file "tiledConvolution-2D.hip"
.globl _Z41__device_stub__tiledConvolution_2D_KernelPfPKfS_mmmi # -- Begin function _Z41__device_stub__tiledConvolution_2D_KernelPfPKfS_mmmi
.p2align 4, 0x90
.type _Z41__device_stub__tiledConvolution_2D_KernelPfPKfS_mmmi,@function
_Z41__device_stub__tiledConvolution_2D_KernelPfPKfS_mmmi: # @_Z41__device_stub__tiledConvolution_2D_KernelPfPKfS_mmmi
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
movq %r9, 48(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 160(%rsp), %rax
movq %rax, 144(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z26tiledConvolution_2D_KernelPfPKfS_mmmi, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z41__device_stub__tiledConvolution_2D_KernelPfPKfS_mmmi, .Lfunc_end0-_Z41__device_stub__tiledConvolution_2D_KernelPfPKfS_mmmi
.cfi_endproc
# -- End function
.globl _Z10errorCheckj # -- Begin function _Z10errorCheckj
.p2align 4, 0x90
.type _Z10errorCheckj,@function
_Z10errorCheckj: # @_Z10errorCheckj
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
movl %edi, %ebx
callq hipGetLastError
testl %eax, %eax
jne .LBB1_2
# %bb.1:
popq %rbx
.cfi_def_cfa_offset 8
retq
.LBB1_2:
.cfi_def_cfa_offset 16
decl %ebx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.1, %edx
movl %ebx, %esi
movq %rax, %rcx
xorl %eax, %eax
callq printf
movl $1, %edi
callq exit
.Lfunc_end1:
.size _Z10errorCheckj, .Lfunc_end1-_Z10errorCheckj
.cfi_endproc
# -- End function
.globl _Z14convolution_2DPfS_S_mmmi # -- Begin function _Z14convolution_2DPfS_S_mmmi
.p2align 4, 0x90
.type _Z14convolution_2DPfS_S_mmmi,@function
_Z14convolution_2DPfS_S_mmmi: # @_Z14convolution_2DPfS_S_mmmi
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $216, %rsp
.cfi_def_cfa_offset 272
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %r9, %r14
movq %r8, %r15
movq %rcx, %r12
movq %rdx, 48(%rsp) # 8-byte Spill
movq %rsi, 56(%rsp) # 8-byte Spill
movq %rdi, %rbx
testq %r8, %r8
js .LBB2_1
# %bb.2:
cvtsi2ss %r15, %xmm0
jmp .LBB2_3
.LBB2_1:
movq %r15, %rax
shrq %rax
movl %r15d, %ecx
andl $1, %ecx
orq %rax, %rcx
cvtsi2ss %rcx, %xmm0
addss %xmm0, %xmm0
.LBB2_3:
cvtsi2ssl 272(%rsp), %xmm1
movss %xmm1, 12(%rsp) # 4-byte Spill
divss %xmm1, %xmm0
callq ceilf@PLT
movss %xmm0, 40(%rsp) # 4-byte Spill
testq %r12, %r12
js .LBB2_4
# %bb.5:
xorps %xmm0, %xmm0
cvtsi2ss %r12, %xmm0
jmp .LBB2_6
.LBB2_4:
movq %r12, %rax
shrq %rax
movl %r12d, %ecx
andl $1, %ecx
orq %rax, %rcx
xorps %xmm0, %xmm0
cvtsi2ss %rcx, %xmm0
addss %xmm0, %xmm0
.LBB2_6:
divss 12(%rsp), %xmm0 # 4-byte Folded Reload
callq ceilf@PLT
movss %xmm0, 12(%rsp) # 4-byte Spill
movq %r12, %r13
imulq %r15, %r13
shlq $2, %r13
leaq 32(%rsp), %rdi
movq %r13, %rsi
callq hipMalloc
callq hipGetLastError
testl %eax, %eax
jne .LBB2_7
# %bb.9: # %_Z10errorCheckj.exit
movq %r14, %rbp
imulq %r14, %r14
shlq $2, %r14
leaq 24(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
callq hipGetLastError
testl %eax, %eax
jne .LBB2_10
# %bb.11: # %_Z10errorCheckj.exit27
leaq 16(%rsp), %rdi
movq %r13, %rsi
callq hipMalloc
callq hipGetLastError
testl %eax, %eax
jne .LBB2_12
# %bb.13: # %_Z10errorCheckj.exit29
movq 32(%rsp), %rdi
movq %rbx, %rsi
movq %r13, %rdx
movl $1, %ecx
callq hipMemcpy
callq hipGetLastError
testl %eax, %eax
jne .LBB2_14
# %bb.15: # %_Z10errorCheckj.exit31
movq 24(%rsp), %rdi
movq 56(%rsp), %rsi # 8-byte Reload
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
callq hipGetLastError
testl %eax, %eax
jne .LBB2_16
# %bb.17: # %_Z10errorCheckj.exit33
cvttss2si 40(%rsp), %rax # 4-byte Folded Reload
cvttss2si 12(%rsp), %rdi # 4-byte Folded Reload
movl %eax, %eax
shlq $32, %rdi
orq %rax, %rdi
movabsq $137438953504, %rdx # imm = 0x2000000020
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_19
# %bb.18:
movq 32(%rsp), %rax
movq 24(%rsp), %rcx
movq 16(%rsp), %rdx
movq %rax, 152(%rsp)
movq %rcx, 144(%rsp)
movq %rdx, 136(%rsp)
movq %r12, 128(%rsp)
movq %r15, 120(%rsp)
movq %rbp, 112(%rsp)
movl 272(%rsp), %eax
movl %eax, 44(%rsp)
leaq 152(%rsp), %rax
movq %rax, 160(%rsp)
leaq 144(%rsp), %rax
movq %rax, 168(%rsp)
leaq 136(%rsp), %rax
movq %rax, 176(%rsp)
leaq 128(%rsp), %rax
movq %rax, 184(%rsp)
leaq 120(%rsp), %rax
movq %rax, 192(%rsp)
leaq 112(%rsp), %rax
movq %rax, 200(%rsp)
leaq 44(%rsp), %rax
movq %rax, 208(%rsp)
leaq 96(%rsp), %rdi
leaq 80(%rsp), %rsi
leaq 72(%rsp), %rdx
leaq 64(%rsp), %rcx
callq __hipPopCallConfiguration
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
movq 80(%rsp), %rcx
movl 88(%rsp), %r8d
leaq 160(%rsp), %r9
movl $_Z26tiledConvolution_2D_KernelPfPKfS_mmmi, %edi
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
pushq 80(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_19:
callq hipGetLastError
testl %eax, %eax
jne .LBB2_20
# %bb.21: # %_Z10errorCheckj.exit35
movq 16(%rsp), %rsi
movq 48(%rsp), %rdi # 8-byte Reload
movq %r13, %rdx
movl $2, %ecx
callq hipMemcpy
callq hipGetLastError
testl %eax, %eax
jne .LBB2_22
# %bb.23: # %_Z10errorCheckj.exit37
movq 32(%rsp), %rdi
callq hipFree
callq hipGetLastError
testl %eax, %eax
jne .LBB2_24
# %bb.25: # %_Z10errorCheckj.exit39
movq 24(%rsp), %rdi
callq hipFree
callq hipGetLastError
testl %eax, %eax
jne .LBB2_26
# %bb.27: # %_Z10errorCheckj.exit41
movq 16(%rsp), %rdi
callq hipFree
callq hipGetLastError
testl %eax, %eax
jne .LBB2_28
# %bb.29: # %_Z10errorCheckj.exit43
addq $216, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB2_7:
.cfi_def_cfa_offset 272
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.1, %edx
movl $75, %esi
jmp .LBB2_8
.LBB2_10:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.1, %edx
movl $77, %esi
jmp .LBB2_8
.LBB2_12:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.1, %edx
movl $79, %esi
jmp .LBB2_8
.LBB2_14:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.1, %edx
movl $82, %esi
jmp .LBB2_8
.LBB2_16:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.1, %edx
movl $84, %esi
jmp .LBB2_8
.LBB2_20:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.1, %edx
movl $87, %esi
jmp .LBB2_8
.LBB2_22:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.1, %edx
movl $90, %esi
jmp .LBB2_8
.LBB2_24:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.1, %edx
movl $93, %esi
jmp .LBB2_8
.LBB2_26:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.1, %edx
movl $95, %esi
jmp .LBB2_8
.LBB2_28:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.1, %edx
movl $97, %esi
.LBB2_8:
movq %rax, %rcx
xorl %eax, %eax
callq printf
movl $1, %edi
callq exit
.Lfunc_end2:
.size _Z14convolution_2DPfS_S_mmmi, .Lfunc_end2-_Z14convolution_2DPfS_S_mmmi
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI3_0:
.quad 0x408f400000000000 # double 1000
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0: # %.lr.ph.preheader
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $56, %rsp
.cfi_def_cfa_offset 112
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
xorl %ebp, %ebp
xorl %edi, %edi
callq time
movl %eax, %edi
callq srand
callq rand
cltq
imulq $2139127681, %rax, %rcx # imm = 0x7F807F81
movq %rcx, %rdx
shrq $63, %rdx
sarq $39, %rcx
addl %edx, %ecx
movl %ecx, %edx
shll $8, %edx
addl %ecx, %edx
negl %edx
leal (%rax,%rdx), %r15d
addl $3840, %r15d # imm = 0xF00
callq rand
cltq
imulq $2139127681, %rax, %rcx # imm = 0x7F807F81
movq %rcx, %rdx
shrq $63, %rdx
sarq $39, %rcx
addl %edx, %ecx
movl %ecx, %edx
shll $8, %edx
addl %ecx, %edx
negl %edx
leal (%rax,%rdx), %ebx
addl $3840, %ebx # imm = 0xF00
movq %rbx, %r14
movq %r15, 16(%rsp) # 8-byte Spill
imulq %r15, %r14
leaq (,%r14,4), %r13
movq %r13, %rdi
callq malloc
movq %rax, %r15
movl $484, %edi # imm = 0x1E4
callq malloc
movq %rax, %r12
movq %r13, %rdi
callq malloc
movq %rax, %r13
.p2align 4, 0x90
.LBB3_1: # %.lr.ph
# =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $266354561, %rax, %rcx # imm = 0xFE03F81
movq %rcx, %rdx
shrq $63, %rdx
sarq $35, %rcx
addl %edx, %ecx
movl %ecx, %edx
shll $7, %edx
addl %ecx, %edx
negl %edx
addl %edx, %eax
addl $-64, %eax
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, (%r15,%rbp,4)
incq %rbp
cmpq %rbp, %r14
jne .LBB3_1
# %bb.2: # %.preheader.preheader
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB3_3: # %.preheader
# =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $1098413215, %rax, %rcx # imm = 0x4178749F
movq %rcx, %rdx
shrq $63, %rdx
sarq $40, %rcx
addl %edx, %ecx
imull $1001, %ecx, %ecx # imm = 0x3E9
subl %ecx, %eax
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
divsd .LCPI3_0(%rip), %xmm0
cvtsd2ss %xmm0, %xmm0
movss %xmm0, (%r12,%r14,4)
incq %r14
cmpq $121, %r14
jne .LBB3_3
# %bb.4:
leaq 40(%rsp), %rsi
xorl %edi, %edi
callq clock_gettime
movl $22, (%rsp)
movl $11, %r9d
movq %r15, %rdi
movq %r12, %rsi
movq %r13, %rdx
movq 16(%rsp), %rcx # 8-byte Reload
movq %rbx, %r8
callq _Z14convolution_2DPfS_S_mmmi
leaq 24(%rsp), %rsi
xorl %edi, %edi
callq clock_gettime
movq 24(%rsp), %rcx
movq 32(%rsp), %rax
subq 40(%rsp), %rcx
imulq $1000000, %rcx, %rcx # imm = 0xF4240
subq 48(%rsp), %rax
movabsq $2361183241434822607, %rdx # imm = 0x20C49BA5E353F7CF
imulq %rdx
movq %rdx, %rsi
shrq $63, %rsi
sarq $7, %rdx
addq %rdx, %rsi
addq %rcx, %rsi
movl $.L.str.2, %edi
xorl %eax, %eax
callq printf
xorl %eax, %eax
addq $56, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z26tiledConvolution_2D_KernelPfPKfS_mmmi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z26tiledConvolution_2D_KernelPfPKfS_mmmi,@object # @_Z26tiledConvolution_2D_KernelPfPKfS_mmmi
.section .rodata,"a",@progbits
.globl _Z26tiledConvolution_2D_KernelPfPKfS_mmmi
.p2align 3, 0x0
_Z26tiledConvolution_2D_KernelPfPKfS_mmmi:
.quad _Z41__device_stub__tiledConvolution_2D_KernelPfPKfS_mmmi
.size _Z26tiledConvolution_2D_KernelPfPKfS_mmmi, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "CUDA error in line %u in file %s: %s\n"
.size .L.str, 38
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/daniel0306123/cuda/master/convolution/tiledConvolution-2D.hip"
.size .L.str.1, 119
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Execution time: %d microseconds."
.size .L.str.2, 33
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z26tiledConvolution_2D_KernelPfPKfS_mmmi"
.size .L__unnamed_1, 42
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z41__device_stub__tiledConvolution_2D_KernelPfPKfS_mmmi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z26tiledConvolution_2D_KernelPfPKfS_mmmi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z26tiledConvolution_2D_KernelPfPKfS_mmmi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R9, SR_CTAID.Y ; /* 0x0000000000097919 */
/* 0x000e220000002600 */
/*0020*/ IMAD.MOV.U32 R12, RZ, RZ, c[0x0][0x188] ; /* 0x00006200ff0c7624 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR8, c[0x0][0x118] ; /* 0x0000460000087ab9 */
/* 0x000fe20000000a00 */
/*0040*/ IMAD.MOV.U32 R11, RZ, RZ, c[0x0][0x18c] ; /* 0x00006300ff0b7624 */
/* 0x000fe200078e00ff */
/*0050*/ S2R R0, SR_TID.Y ; /* 0x0000000000007919 */
/* 0x000e280000002200 */
/*0060*/ S2R R7, SR_CTAID.X ; /* 0x0000000000077919 */
/* 0x000e620000002500 */
/*0070*/ SHF.R.U64 R2, R12, 0x1, R11 ; /* 0x000000010c027819 */
/* 0x000fc6000000120b */
/*0080*/ S2R R8, SR_TID.X ; /* 0x0000000000087919 */
/* 0x000e620000002100 */
/*0090*/ IMAD R9, R9, c[0x0][0x190], R0 ; /* 0x0000640009097a24 */
/* 0x001fc800078e0200 */
/*00a0*/ IMAD.IADD R5, R9, 0x1, -R2 ; /* 0x0000000109057824 */
/* 0x000fe400078e0a02 */
/*00b0*/ IMAD R6, R7, c[0x0][0x190], R8 ; /* 0x0000640007067a24 */
/* 0x002fc600078e0208 */
/*00c0*/ ISETP.GE.U32.AND P0, PT, R5, c[0x0][0x178], PT ; /* 0x00005e0005007a0c */
/* 0x000fe40003f06070 */
/*00d0*/ SHF.R.S32.HI R4, RZ, 0x1f, R5 ; /* 0x0000001fff047819 */
/* 0x000fe20000011405 */
/*00e0*/ IMAD.IADD R2, R6, 0x1, -R2 ; /* 0x0000000106027824 */
/* 0x000fc600078e0a02 */
/*00f0*/ ISETP.GE.U32.AND.EX P0, PT, R4, c[0x0][0x17c], PT, P0 ; /* 0x00005f0004007a0c */
/* 0x000fe40003f06100 */
/*0100*/ LOP3.LUT R7, R5, R2, RZ, 0xfc, !PT ; /* 0x0000000205077212 */
/* 0x000fe400078efcff */
/*0110*/ ISETP.LT.U32.AND P1, PT, R2, c[0x0][0x180], PT ; /* 0x0000600002007a0c */
/* 0x000fe40003f21070 */
/*0120*/ SHF.R.S32.HI R3, RZ, 0x1f, R2 ; /* 0x0000001fff037819 */
/* 0x000fe40000011402 */
/*0130*/ ISETP.GT.AND P0, PT, R7, -0x1, !P0 ; /* 0xffffffff0700780c */
/* 0x000fc80004704270 */
/*0140*/ ISETP.LT.U32.AND.EX P0, PT, R3, c[0x0][0x184], P0, P1 ; /* 0x0000610003007a0c */
/* 0x000fda0000701110 */
/*0150*/ @P0 IMAD R4, R4, c[0x0][0x180], RZ ; /* 0x0000600004040a24 */
/* 0x000fe400078e02ff */
/*0160*/ @P0 IMAD.WIDE.U32 R2, R5, c[0x0][0x180], R2 ; /* 0x0000600005020a25 */
/* 0x000fc800078e0002 */
/*0170*/ @P0 IMAD R5, R5, c[0x0][0x184], R4 ; /* 0x0000610005050a24 */
/* 0x000fe200078e0204 */
/*0180*/ @P0 LEA R4, P1, R2, c[0x0][0x160], 0x2 ; /* 0x0000580002040a11 */
/* 0x000fc600078210ff */
/*0190*/ @P0 IMAD.IADD R3, R3, 0x1, R5 ; /* 0x0000000103030824 */
/* 0x000fca00078e0205 */
/*01a0*/ @P0 LEA.HI.X R5, R2, c[0x0][0x164], R3, 0x2, P1 ; /* 0x0000590002050a11 */
/* 0x000fcc00008f1403 */
/*01b0*/ @P0 LDG.E R5, [R4.64] ; /* 0x0000000804050981 */
/* 0x000ea2000c1e1900 */
/*01c0*/ IMAD.SHL.U32 R3, R8.reuse, 0x4, RZ ; /* 0x0000000408037824 */
/* 0x040fe200078e00ff */
/*01d0*/ ISETP.GE.U32.AND P1, PT, R8, c[0x0][0x190], PT ; /* 0x0000640008007a0c */
/* 0x000fe40003f26070 */
/*01e0*/ ISETP.GE.U32.AND P3, PT, R9, c[0x0][0x178], PT ; /* 0x00005e0009007a0c */
/* 0x000fe20003f66070 */
/*01f0*/ IMAD R2, R0.reuse, 0x80, R3 ; /* 0x0000008000027824 */
/* 0x040fe200078e0203 */
/*0200*/ ISETP.GE.U32.OR P2, PT, R0, c[0x0][0x190], P1 ; /* 0x0000640000007a0c */
/* 0x000fe40000f46470 */
/*0210*/ SHF.R.S32.HI R10, RZ, 0x1f, R9 ; /* 0x0000001fff0a7819 */
/* 0x000fe40000011409 */
/*0220*/ @!P0 STS [R2], RZ ; /* 0x000000ff02008388 */
/* 0x0001e20000000800 */
/*0230*/ ISETP.GE.U32.AND P1, PT, R6, c[0x0][0x180], PT ; /* 0x0000600006007a0c */
/* 0x000fc40003f26070 */
/*0240*/ SHF.R.S32.HI R7, RZ, 0x1f, R6 ; /* 0x0000001fff077819 */
/* 0x000fe40000011406 */
/*0250*/ ISETP.GE.U32.OR.EX P2, PT, R10, c[0x0][0x17c], P2, P3 ; /* 0x00005f000a007a0c */
/* 0x000fc80001746530 */
/*0260*/ ISETP.GE.U32.OR.EX P1, PT, R7, c[0x0][0x184], P2, P1 ; /* 0x0000610007007a0c */
/* 0x000fe20001726510 */
/*0270*/ @P0 STS [R2], R5 ; /* 0x0000000502000388 */
/* 0x0041e80000000800 */
/*0280*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000ff00000010000 */
/*0290*/ @P1 EXIT ; /* 0x000000000000194d */
/* 0x000fea0003800000 */
/*02a0*/ ISETP.NE.U32.AND P0, PT, RZ, c[0x0][0x188], PT ; /* 0x00006200ff007a0c */
/* 0x001fe20003f05070 */
/*02b0*/ IMAD.MOV.U32 R22, RZ, RZ, RZ ; /* 0x000000ffff167224 */
/* 0x000fc600078e00ff */
/*02c0*/ ISETP.NE.AND.EX P0, PT, RZ, c[0x0][0x18c], PT, P0 ; /* 0x00006300ff007a0c */
/* 0x000fda0003f05300 */
/*02d0*/ @!P0 BRA 0xe50 ; /* 0x00000b7000008947 */
/* 0x000fea0003800000 */
/*02e0*/ IADD3 R2, P0, R12.reuse, -0x1, RZ ; /* 0xffffffff0c027810 */
/* 0x040fe20007f1e0ff */
/*02f0*/ UMOV UR4, 0x8 ; /* 0x0000000800047882 */
/* 0x000fe20000000000 */
/*0300*/ LOP3.LUT R12, R12, 0x3, RZ, 0xc0, !PT ; /* 0x000000030c0c7812 */
/* 0x000fe200078ec0ff */
/*0310*/ ULDC.64 UR6, c[0x0][0x168] ; /* 0x00005a0000067ab9 */
/* 0x000fe20000000a00 */
/*0320*/ ISETP.GE.U32.AND P1, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fe20003f26070 */
/*0330*/ UIADD3 UR4, UP0, UR4, UR6, URZ ; /* 0x0000000604047290 */
/* 0x000fe2000ff1e03f */
/*0340*/ IADD3.X R2, R11, -0x1, RZ, P0, !PT ; /* 0xffffffff0b027810 */
/* 0x000fe200007fe4ff */
/*0350*/ IMAD.MOV.U32 R22, RZ, RZ, RZ ; /* 0x000000ffff167224 */
/* 0x000fe200078e00ff */
/*0360*/ IADD3 R13, P0, R12, -c[0x0][0x188], RZ ; /* 0x800062000c0d7a10 */
/* 0x000fe20007f1e0ff */
/*0370*/ IMAD.MOV.U32 R15, RZ, RZ, RZ ; /* 0x000000ffff0f7224 */
/* 0x000fe200078e00ff */
/*0380*/ ISETP.GE.U32.AND.EX P1, PT, R2, RZ, PT, P1 ; /* 0x000000ff0200720c */
/* 0x000fe20003f26110 */
/*0390*/ UIADD3.X UR5, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f057290 */
/* 0x000fe200087fe43f */
/*03a0*/ IADD3 R14, R3, 0x8, RZ ; /* 0x00000008030e7810 */
/* 0x000fe20007ffe0ff */
/*03b0*/ IMAD.X R16, RZ, RZ, ~c[0x0][0x18c], P0 ; /* 0x80006300ff107624 */
/* 0x000fc400000e06ff */
/*03c0*/ SHF.R.S32.HI R2, RZ, 0x1f, R15 ; /* 0x0000001fff027819 */
/* 0x000fe2000001140f */
/*03d0*/ IMAD.WIDE.U32 R4, R15, c[0x0][0x188], RZ ; /* 0x000062000f047a25 */
/* 0x000fc800078e00ff */
/*03e0*/ IMAD R2, R2, c[0x0][0x188], RZ ; /* 0x0000620002027a24 */
/* 0x000fe400078e02ff */
/*03f0*/ IMAD.IADD R17, R0, 0x1, R15 ; /* 0x0000000100117824 */
/* 0x000fe400078e020f */
/*0400*/ IMAD R19, R15, c[0x0][0x18c], R2 ; /* 0x000063000f137a24 */
/* 0x000fe400078e0202 */
/*0410*/ IMAD.MOV.U32 R11, RZ, RZ, RZ ; /* 0x000000ffff0b7224 */
/* 0x000fe400078e00ff */
/*0420*/ IMAD.IADD R19, R5, 0x1, R19 ; /* 0x0000000105137824 */
/* 0x000fe200078e0213 */
/*0430*/ @!P1 BRA 0xc90 ; /* 0x0000085000009947 */
/* 0x000fea0003800000 */
/*0440*/ ISETP.GE.AND P0, PT, R16, RZ, PT ; /* 0x000000ff1000720c */
/* 0x000fe20003f06270 */
/*0450*/ IMAD R18, R17, 0x80, R14 ; /* 0x0000008011127824 */
/* 0x000fe200078e020e */
/*0460*/ LEA R2, P2, R4, UR4, 0x2 ; /* 0x0000000404027c11 */
/* 0x000fe2000f8410ff */
/*0470*/ IMAD.MOV.U32 R11, RZ, RZ, RZ ; /* 0x000000ffff0b7224 */
/* 0x000fc400078e00ff */
/*0480*/ IMAD.MOV.U32 R21, RZ, RZ, R13 ; /* 0x000000ffff157224 */
/* 0x000fe200078e000d */
/*0490*/ LEA.HI.X R3, R4, UR5, R19, 0x2, P2 ; /* 0x0000000504037c11 */
/* 0x000fe200090f1413 */
/*04a0*/ IMAD.MOV.U32 R20, RZ, RZ, R16 ; /* 0x000000ffff147224 */
/* 0x000fcc00078e0010 */
/*04b0*/ @P0 BRA 0xb40 ; /* 0x0000068000000947 */
/* 0x000fea0003800000 */
/*04c0*/ IADD3 R23, P0, RZ, -R21, RZ ; /* 0x80000015ff177210 */
/* 0x000fc80007f1e0ff */
/*04d0*/ ISETP.GT.U32.AND P2, PT, R23, 0xc, PT ; /* 0x0000000c1700780c */
/* 0x000fe20003f44070 */
/*04e0*/ IMAD.X R23, RZ, RZ, ~R20, P0 ; /* 0x000000ffff177224 */
/* 0x000fe200000e0e14 */
/*04f0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fc80003f0f070 */
/*0500*/ ISETP.GT.AND.EX P2, PT, R23, RZ, PT, P2 ; /* 0x000000ff1700720c */
/* 0x000fda0003f44320 */
/*0510*/ @!P2 BRA 0x8c0 ; /* 0x000003a00000a947 */
/* 0x000fea0003800000 */
/*0520*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0530*/ LDG.E.CONSTANT R26, [R2.64+-0x8] ; /* 0xfffff808021a7981 */
/* 0x000ea8000c1e9900 */
/*0540*/ LDG.E.CONSTANT R27, [R2.64+-0x4] ; /* 0xfffffc08021b7981 */
/* 0x000ee8000c1e9900 */
/*0550*/ LDG.E.CONSTANT R24, [R2.64] ; /* 0x0000000802187981 */
/* 0x000f28000c1e9900 */
/*0560*/ LDG.E.CONSTANT R23, [R2.64+0x4] ; /* 0x0000040802177981 */
/* 0x000f68000c1e9900 */
/*0570*/ LDS R25, [R18+-0x8] ; /* 0xfffff80012197984 */
/* 0x000ea40000000800 */
/*0580*/ FFMA R25, R25, R26, R22 ; /* 0x0000001a19197223 */
/* 0x004fc40000000016 */
/*0590*/ LDS R22, [R18+-0x4] ; /* 0xfffffc0012167984 */
/* 0x000ee80000000800 */
/*05a0*/ LDS R26, [R18] ; /* 0x00000000121a7984 */
/* 0x000f220000000800 */
/*05b0*/ FFMA R25, R22, R27, R25 ; /* 0x0000001b16197223 */
/* 0x008fc60000000019 */
/*05c0*/ LDG.E.CONSTANT R22, [R2.64+0x8] ; /* 0x0000080802167981 */
/* 0x000ea2000c1e9900 */
/*05d0*/ FFMA R26, R26, R24, R25 ; /* 0x000000181a1a7223 */
/* 0x010fc60000000019 */
/*05e0*/ LDS R25, [R18+0x4] ; /* 0x0000040012197984 */
/* 0x000f680000000800 */
/*05f0*/ LDG.E.CONSTANT R24, [R2.64+0xc] ; /* 0x00000c0802187981 */
/* 0x000ee2000c1e9900 */
/*0600*/ FFMA R27, R25, R23, R26 ; /* 0x00000017191b7223 */
/* 0x020fc6000000001a */
/*0610*/ LDG.E.CONSTANT R25, [R2.64+0x10] ; /* 0x0000100802197981 */
/* 0x000f28000c1e9900 */
/*0620*/ LDG.E.CONSTANT R23, [R2.64+0x14] ; /* 0x0000140802177981 */
/* 0x000f68000c1e9900 */
/*0630*/ LDS R26, [R18+0x8] ; /* 0x00000800121a7984 */
/* 0x000ea40000000800 */
/*0640*/ FFMA R27, R26, R22, R27 ; /* 0x000000161a1b7223 */
/* 0x004fc4000000001b */
/*0650*/ LDS R22, [R18+0xc] ; /* 0x00000c0012167984 */
/* 0x000ee80000000800 */
/*0660*/ LDS R26, [R18+0x10] ; /* 0x00001000121a7984 */
/* 0x000f220000000800 */
/*0670*/ FFMA R24, R22, R24, R27 ; /* 0x0000001816187223 */
/* 0x008fc6000000001b */
/*0680*/ LDG.E.CONSTANT R22, [R2.64+0x18] ; /* 0x0000180802167981 */
/* 0x000ea2000c1e9900 */
/*0690*/ FFMA R26, R26, R25, R24 ; /* 0x000000191a1a7223 */
/* 0x010fc60000000018 */
/*06a0*/ LDS R25, [R18+0x14] ; /* 0x0000140012197984 */
/* 0x000f680000000800 */
/*06b0*/ LDG.E.CONSTANT R24, [R2.64+0x1c] ; /* 0x00001c0802187981 */
/* 0x000ee2000c1e9900 */
/*06c0*/ FFMA R27, R25, R23, R26 ; /* 0x00000017191b7223 */
/* 0x020fc6000000001a */
/*06d0*/ LDG.E.CONSTANT R25, [R2.64+0x20] ; /* 0x0000200802197981 */
/* 0x000f28000c1e9900 */
/*06e0*/ LDG.E.CONSTANT R23, [R2.64+0x24] ; /* 0x0000240802177981 */
/* 0x000f68000c1e9900 */
/*06f0*/ LDS R26, [R18+0x18] ; /* 0x00001800121a7984 */
/* 0x000ea40000000800 */
/*0700*/ FFMA R27, R26, R22, R27 ; /* 0x000000161a1b7223 */
/* 0x004fc4000000001b */
/*0710*/ LDS R22, [R18+0x1c] ; /* 0x00001c0012167984 */
/* 0x000ee80000000800 */
/*0720*/ LDS R26, [R18+0x20] ; /* 0x00002000121a7984 */
/* 0x000f220000000800 */
/*0730*/ FFMA R24, R22, R24, R27 ; /* 0x0000001816187223 */
/* 0x008fc6000000001b */
/*0740*/ LDG.E.CONSTANT R22, [R2.64+0x28] ; /* 0x0000280802167981 */
/* 0x0000a2000c1e9900 */
/*0750*/ FFMA R26, R26, R25, R24 ; /* 0x000000191a1a7223 */
/* 0x010fc60000000018 */
/*0760*/ LDS R25, [R18+0x24] ; /* 0x0000240012197984 */
/* 0x000f680000000800 */
/*0770*/ LDG.E.CONSTANT R24, [R2.64+0x2c] ; /* 0x00002c0802187981 */
/* 0x0000e2000c1e9900 */
/*0780*/ FFMA R27, R25, R23, R26 ; /* 0x00000017191b7223 */
/* 0x020fc6000000001a */
/*0790*/ LDG.E.CONSTANT R25, [R2.64+0x30] ; /* 0x0000300802197981 */
/* 0x000128000c1e9900 */
/*07a0*/ LDG.E.CONSTANT R23, [R2.64+0x34] ; /* 0x0000340802177981 */
/* 0x000162000c1e9900 */
/*07b0*/ IADD3 R21, P2, R21, 0x10, RZ ; /* 0x0000001015157810 */
/* 0x000fe40007f5e0ff */
/*07c0*/ IADD3 R11, R11, 0x10, RZ ; /* 0x000000100b0b7810 */
/* 0x000fe20007ffe0ff */
/*07d0*/ LDS R26, [R18+0x28] ; /* 0x00002800121a7984 */
/* 0x000ea40000000800 */
/*07e0*/ IMAD.X R20, RZ, RZ, R20, P2 ; /* 0x000000ffff147224 */
/* 0x000fe200010e0614 */
/*07f0*/ ISETP.GE.U32.AND P2, PT, R21, -0xc, PT ; /* 0xfffffff41500780c */
/* 0x000fc40003f46070 */
/*0800*/ IADD3 R2, P3, R2, 0x40, RZ ; /* 0x0000004002027810 */
/* 0x001fe40007f7e0ff */
/*0810*/ ISETP.GE.AND.EX P2, PT, R20, -0x1, PT, P2 ; /* 0xffffffff1400780c */
/* 0x000fc60003f46320 */
/*0820*/ IMAD.X R3, RZ, RZ, R3, P3 ; /* 0x000000ffff037224 */
/* 0x000fe400018e0603 */
/*0830*/ FFMA R27, R26, R22, R27 ; /* 0x000000161a1b7223 */
/* 0x004fe4000000001b */
/*0840*/ LDS R22, [R18+0x2c] ; /* 0x00002c0012167984 */
/* 0x000ee80000000800 */
/*0850*/ LDS R26, [R18+0x34] ; /* 0x00003400121a7984 */
/* 0x000fe20000000800 */
/*0860*/ FFMA R22, R22, R24, R27 ; /* 0x0000001816167223 */
/* 0x008fc6000000001b */
/*0870*/ LDS R24, [R18+0x30] ; /* 0x0000300012187984 */
/* 0x0001240000000800 */
/*0880*/ IADD3 R18, R18, 0x40, RZ ; /* 0x0000004012127810 */
/* 0x001fe20007ffe0ff */
/*0890*/ FFMA R22, R24, R25, R22 ; /* 0x0000001918167223 */
/* 0x010fc80000000016 */
/*08a0*/ FFMA R22, R26, R23, R22 ; /* 0x000000171a167223 */
/* 0x020fe20000000016 */
/*08b0*/ @!P2 BRA 0x530 ; /* 0xfffffc700000a947 */
/* 0x000fea000383ffff */
/*08c0*/ IADD3 R23, P3, RZ, -R21, RZ ; /* 0x80000015ff177210 */
/* 0x000fc80007f7e0ff */
/*08d0*/ ISETP.GT.U32.AND P2, PT, R23, 0x4, PT ; /* 0x000000041700780c */
/* 0x000fe20003f44070 */
/*08e0*/ IMAD.X R23, RZ, RZ, ~R20, P3 ; /* 0x000000ffff177224 */
/* 0x000fca00018e0e14 */
/*08f0*/ ISETP.GT.AND.EX P2, PT, R23, RZ, PT, P2 ; /* 0x000000ff1700720c */
/* 0x000fda0003f44320 */
/*0900*/ @!P2 BRA 0xb10 ; /* 0x000002000000a947 */
/* 0x000fea0003800000 */
/*0910*/ LDG.E.CONSTANT R26, [R2.64+-0x8] ; /* 0xfffff808021a7981 */
/* 0x000ea8000c1e9900 */
/*0920*/ LDG.E.CONSTANT R27, [R2.64+-0x4] ; /* 0xfffffc08021b7981 */
/* 0x000ee8000c1e9900 */
/*0930*/ LDG.E.CONSTANT R24, [R2.64] ; /* 0x0000000802187981 */
/* 0x000f28000c1e9900 */
/*0940*/ LDG.E.CONSTANT R23, [R2.64+0x4] ; /* 0x0000040802177981 */
/* 0x000f68000c1e9900 */
/*0950*/ LDS R25, [R18+-0x8] ; /* 0xfffff80012197984 */
/* 0x000ea40000000800 */
/*0960*/ FFMA R25, R25, R26, R22 ; /* 0x0000001a19197223 */
/* 0x004fc40000000016 */
/*0970*/ LDS R22, [R18+-0x4] ; /* 0xfffffc0012167984 */
/* 0x000ee80000000800 */
/*0980*/ LDS R26, [R18] ; /* 0x00000000121a7984 */
/* 0x000f220000000800 */
/*0990*/ FFMA R25, R22, R27, R25 ; /* 0x0000001b16197223 */
/* 0x008fc60000000019 */
/*09a0*/ LDG.E.CONSTANT R22, [R2.64+0x8] ; /* 0x0000080802167981 */
/* 0x000ea2000c1e9900 */
/*09b0*/ FFMA R26, R26, R24, R25 ; /* 0x000000181a1a7223 */
/* 0x010fc60000000019 */
/*09c0*/ LDS R25, [R18+0x4] ; /* 0x0000040012197984 */
/* 0x000f680000000800 */
/*09d0*/ LDG.E.CONSTANT R24, [R2.64+0xc] ; /* 0x00000c0802187981 */
/* 0x000ee2000c1e9900 */
/*09e0*/ FFMA R27, R25, R23, R26 ; /* 0x00000017191b7223 */
/* 0x020fc6000000001a */
/*09f0*/ LDG.E.CONSTANT R25, [R2.64+0x10] ; /* 0x0000100802197981 */
/* 0x000f28000c1e9900 */
/*0a00*/ LDG.E.CONSTANT R23, [R2.64+0x14] ; /* 0x0000140802177981 */
/* 0x000f62000c1e9900 */
/*0a10*/ IADD3 R21, P3, R21, 0x8, RZ ; /* 0x0000000815157810 */
/* 0x000fe40007f7e0ff */
/*0a20*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe20003f0e170 */
/*0a30*/ LDS R26, [R18+0x8] ; /* 0x00000800121a7984 */
/* 0x000ea20000000800 */
/*0a40*/ IADD3 R11, R11, 0x8, RZ ; /* 0x000000080b0b7810 */
/* 0x000fe20007ffe0ff */
/*0a50*/ IMAD.X R20, RZ, RZ, R20, P3 ; /* 0x000000ffff147224 */
/* 0x000fc400018e0614 */
/*0a60*/ FFMA R27, R26, R22, R27 ; /* 0x000000161a1b7223 */
/* 0x004fe4000000001b */
/*0a70*/ LDS R22, [R18+0xc] ; /* 0x00000c0012167984 */
/* 0x000ee80000000800 */
/*0a80*/ LDS R26, [R18+0x14] ; /* 0x00001400121a7984 */
/* 0x000fe20000000800 */
/*0a90*/ FFMA R22, R22, R24, R27 ; /* 0x0000001816167223 */
/* 0x008fc6000000001b */
/*0aa0*/ LDS R24, [R18+0x10] ; /* 0x0000100012187984 */
/* 0x0001240000000800 */
/*0ab0*/ IADD3 R18, R18, 0x20, RZ ; /* 0x0000002012127810 */
/* 0x001fe20007ffe0ff */
/*0ac0*/ FFMA R22, R24, R25, R22 ; /* 0x0000001918167223 */
/* 0x010fe20000000016 */
/*0ad0*/ IADD3 R24, P2, R2, 0x20, RZ ; /* 0x0000002002187810 */
/* 0x000fc60007f5e0ff */
/*0ae0*/ FFMA R22, R26, R23, R22 ; /* 0x000000171a167223 */
/* 0x020fe40000000016 */
/*0af0*/ IMAD.X R3, RZ, RZ, R3, P2 ; /* 0x000000ffff037224 */
/* 0x000fe400010e0603 */
/*0b00*/ IMAD.MOV.U32 R2, RZ, RZ, R24 ; /* 0x000000ffff027224 */
/* 0x000fe400078e0018 */
/*0b10*/ ISETP.NE.U32.AND P2, PT, R21, RZ, PT ; /* 0x000000ff1500720c */
/* 0x000fc80003f45070 */
/*0b20*/ ISETP.NE.OR.EX P0, PT, R20, RZ, P0, P2 ; /* 0x000000ff1400720c */
/* 0x000fda0000705720 */
/*0b30*/ @!P0 BRA 0xc90 ; /* 0x0000015000008947 */
/* 0x000fea0003800000 */
/*0b40*/ LDG.E.CONSTANT R26, [R2.64+-0x8] ; /* 0xfffff808021a7981 */
/* 0x0000a8000c1e9900 */
/*0b50*/ LDG.E.CONSTANT R27, [R2.64+-0x4] ; /* 0xfffffc08021b7981 */
/* 0x0000e8000c1e9900 */
/*0b60*/ LDG.E.CONSTANT R24, [R2.64] ; /* 0x0000000802187981 */
/* 0x000128000c1e9900 */
/*0b70*/ LDG.E.CONSTANT R23, [R2.64+0x4] ; /* 0x0000040802177981 */
/* 0x000162000c1e9900 */
/*0b80*/ IADD3 R21, P0, R21, 0x4, RZ ; /* 0x0000000415157810 */
/* 0x000fc40007f1e0ff */
/*0b90*/ IADD3 R11, R11, 0x4, RZ ; /* 0x000000040b0b7810 */
/* 0x000fe20007ffe0ff */
/*0ba0*/ LDS R25, [R18+-0x8] ; /* 0xfffff80012197984 */
/* 0x000ea40000000800 */
/*0bb0*/ IMAD.X R20, RZ, RZ, R20, P0 ; /* 0x000000ffff147224 */
/* 0x000fe200000e0614 */
/*0bc0*/ ISETP.NE.U32.AND P0, PT, R21, RZ, PT ; /* 0x000000ff1500720c */
/* 0x000fe40003f05070 */
/*0bd0*/ IADD3 R2, P2, R2, 0x10, RZ ; /* 0x0000001002027810 */
/* 0x001fe40007f5e0ff */
/*0be0*/ ISETP.NE.AND.EX P0, PT, R20, RZ, PT, P0 ; /* 0x000000ff1400720c */
/* 0x000fc60003f05300 */
/*0bf0*/ IMAD.X R3, RZ, RZ, R3, P2 ; /* 0x000000ffff037224 */
/* 0x000fe400010e0603 */
/*0c00*/ FFMA R25, R25, R26, R22 ; /* 0x0000001a19197223 */
/* 0x004fe40000000016 */
/*0c10*/ LDS R22, [R18+-0x4] ; /* 0xfffffc0012167984 */
/* 0x000ee80000000800 */
/*0c20*/ LDS R26, [R18+0x4] ; /* 0x00000400121a7984 */
/* 0x000fe20000000800 */
/*0c30*/ FFMA R25, R22, R27, R25 ; /* 0x0000001b16197223 */
/* 0x008fc60000000019 */
/*0c40*/ LDS R22, [R18] ; /* 0x0000000012167984 */
/* 0x0001240000000800 */
/*0c50*/ IADD3 R18, R18, 0x10, RZ ; /* 0x0000001012127810 */
/* 0x001fe20007ffe0ff */
/*0c60*/ FFMA R22, R22, R24, R25 ; /* 0x0000001816167223 */
/* 0x010fc80000000019 */
/*0c70*/ FFMA R22, R26, R23, R22 ; /* 0x000000171a167223 */
/* 0x020fe20000000016 */
/*0c80*/ @P0 BRA 0xb40 ; /* 0xfffffeb000000947 */
/* 0x000fea000383ffff */
/*0c90*/ ISETP.NE.U32.AND P0, PT, R12, RZ, PT ; /* 0x000000ff0c00720c */
/* 0x000fc80003f05070 */
/*0ca0*/ ISETP.NE.AND.EX P0, PT, RZ, RZ, PT, P0 ; /* 0x000000ffff00720c */
/* 0x000fda0003f05300 */
/*0cb0*/ @!P0 BRA 0xe10 ; /* 0x0000015000008947 */
/* 0x000fea0003800000 */
/*0cc0*/ IADD3 R4, P0, R11, R4, RZ ; /* 0x000000040b047210 */
/* 0x000fc80007f1e0ff */
/*0cd0*/ LEA.HI.X.SX32 R19, R11, R19, 0x1, P0 ; /* 0x000000130b137211 */
/* 0x000fe400000f0eff */
/*0ce0*/ LEA R2, P0, R4, c[0x0][0x168], 0x2 ; /* 0x00005a0004027a11 */
/* 0x000fc800078010ff */
/*0cf0*/ LEA.HI.X R3, R4, c[0x0][0x16c], R19, 0x2, P0 ; /* 0x00005b0004037a11 */
/* 0x000fca00000f1413 */
/*0d00*/ LDG.E.CONSTANT R18, [R2.64] ; /* 0x0000000802127981 */
/* 0x000ea2000c1e9900 */
/*0d10*/ IMAD.IADD R4, R8, 0x1, R11 ; /* 0x0000000108047824 */
/* 0x000fe200078e020b */
/*0d20*/ ISETP.NE.U32.AND P0, PT, R12, 0x1, PT ; /* 0x000000010c00780c */
/* 0x000fc60003f05070 */
/*0d30*/ IMAD R4, R17, 0x20, R4 ; /* 0x0000002011047824 */
/* 0x000fe200078e0204 */
/*0d40*/ ISETP.NE.AND.EX P0, PT, RZ, RZ, PT, P0 ; /* 0x000000ffff00720c */
/* 0x000fc60003f05300 */
/*0d50*/ IMAD.SHL.U32 R19, R4, 0x4, RZ ; /* 0x0000000404137824 */
/* 0x000fca00078e00ff */
/*0d60*/ LDS R5, [R19] ; /* 0x0000000013057984 */
/* 0x000ea40000000800 */
/*0d70*/ FFMA R22, R5, R18, R22 ; /* 0x0000001205167223 */
/* 0x004fc60000000016 */
/*0d80*/ @!P0 BRA 0xe10 ; /* 0x0000008000008947 */
/* 0x000fea0003800000 */
/*0d90*/ ISETP.NE.U32.AND P0, PT, R12, 0x2, PT ; /* 0x000000020c00780c */
/* 0x000fe20003f05070 */
/*0da0*/ LDG.E.CONSTANT R4, [R2.64+0x4] ; /* 0x0000040802047981 */
/* 0x000ea6000c1e9900 */
/*0db0*/ ISETP.NE.AND.EX P0, PT, RZ, RZ, PT, P0 ; /* 0x000000ffff00720c */
/* 0x000fe20003f05300 */
/*0dc0*/ LDS R5, [R19+0x4] ; /* 0x0000040013057984 */
/* 0x000e980000000800 */
/*0dd0*/ @P0 LDG.E.CONSTANT R17, [R2.64+0x8] ; /* 0x0000080802110981 */
/* 0x000ee8000c1e9900 */
/*0de0*/ @P0 LDS R11, [R19+0x8] ; /* 0x00000800130b0984 */
/* 0x000ee20000000800 */
/*0df0*/ FFMA R22, R5, R4, R22 ; /* 0x0000000405167223 */
/* 0x004fc80000000016 */
/*0e00*/ @P0 FFMA R22, R11, R17, R22 ; /* 0x000000110b160223 */
/* 0x008fe40000000016 */
/*0e10*/ IADD3 R15, R15, 0x1, RZ ; /* 0x000000010f0f7810 */
/* 0x000fc80007ffe0ff */
/*0e20*/ ISETP.GE.U32.AND P0, PT, R15, c[0x0][0x188], PT ; /* 0x000062000f007a0c */
/* 0x000fc80003f06070 */
/*0e30*/ ISETP.GE.U32.AND.EX P0, PT, RZ, c[0x0][0x18c], PT, P0 ; /* 0x00006300ff007a0c */
/* 0x000fda0003f06100 */
/*0e40*/ @!P0 BRA 0x3c0 ; /* 0xfffff57000008947 */
/* 0x000fea000383ffff */
/*0e50*/ IMAD R10, R10, c[0x0][0x180], RZ ; /* 0x000060000a0a7a24 */
/* 0x000fe400078e02ff */
/*0e60*/ IMAD.WIDE.U32 R6, R9, c[0x0][0x180], R6 ; /* 0x0000600009067a25 */
/* 0x000fc800078e0006 */
/*0e70*/ IMAD R3, R9, c[0x0][0x184], R10 ; /* 0x0000610009037a24 */
/* 0x000fe200078e020a */
/*0e80*/ LEA R2, P0, R6, c[0x0][0x170], 0x2 ; /* 0x00005c0006027a11 */
/* 0x000fc600078010ff */
/*0e90*/ IMAD.IADD R3, R7, 0x1, R3 ; /* 0x0000000107037824 */
/* 0x000fca00078e0203 */
/*0ea0*/ LEA.HI.X R3, R6, c[0x0][0x174], R3, 0x2, P0 ; /* 0x00005d0006037a11 */
/* 0x000fca00000f1403 */
/*0eb0*/ STG.E [R2.64], R22 ; /* 0x0000001602007986 */
/* 0x000fe2000c101908 */
/*0ec0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0ed0*/ BRA 0xed0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0ee0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ef0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z26tiledConvolution_2D_KernelPfPKfS_mmmi
.globl _Z26tiledConvolution_2D_KernelPfPKfS_mmmi
.p2align 8
.type _Z26tiledConvolution_2D_KernelPfPKfS_mmmi,@function
_Z26tiledConvolution_2D_KernelPfPKfS_mmmi:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x30
s_load_b64 s[8:9], s[0:1], 0x28
v_bfe_u32 v5, v0, 10, 10
s_load_b128 s[4:7], s[0:1], 0x18
v_dual_mov_b32 v7, 0 :: v_dual_and_b32 v0, 0x3ff, v0
s_mov_b32 s10, exec_lo
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[1:2], null, s15, s3, v[5:6]
v_alignbit_b32 v2, s9, s8, 1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[3:4], null, s14, s3, v[0:1]
v_sub_nc_u32_e32 v6, v1, v2
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_lt_i32_e32 -1, v6
s_cbranch_execz .LBB0_6
v_mov_b32_e32 v7, 0
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v8, v3, v2
v_cmp_gt_u64_e32 vcc_lo, s[4:5], v[6:7]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_lt_i32_e64 s2, -1, v8
s_and_b32 s11, s2, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s2, s11
s_cbranch_execz .LBB0_5
v_mov_b32_e32 v9, 0
s_mov_b32 s11, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_u64_e64 s[6:7], v[8:9]
s_cbranch_execz .LBB0_4
v_mad_u64_u32 v[10:11], null, v6, s6, 0
s_load_b64 s[12:13], s[0:1], 0x0
v_lshlrev_b64 v[8:9], 2, v[8:9]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mov_b32_e32 v2, v11
v_mad_u64_u32 v[11:12], null, v6, s7, v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[6:7], 2, v[10:11]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s12, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, s13, v7, vcc_lo
v_add_co_u32 v6, vcc_lo, v2, v8
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v7, vcc_lo, v4, v9, vcc_lo
global_load_b32 v9, v[6:7], off
.LBB0_4:
s_or_b32 exec_lo, exec_lo, s11
s_waitcnt vmcnt(0)
v_mov_b32_e32 v7, v9
.LBB0_5:
s_or_b32 exec_lo, exec_lo, s2
.LBB0_6:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
s_or_b32 exec_lo, exec_lo, s10
v_lshlrev_b32_e32 v2, 2, v0
s_mov_b32 s2, exec_lo
v_lshl_add_u32 v2, v5, 7, v2
ds_store_b32 v2, v7
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_gt_u32_e64 s3, v5
s_cbranch_execz .LBB0_15
v_ashrrev_i32_e32 v2, 31, v1
v_ashrrev_i32_e32 v4, 31, v3
v_cmp_gt_u32_e64 s2, s3, v0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cmp_gt_u64_e32 vcc_lo, s[4:5], v[1:2]
v_cmp_gt_u64_e64 s3, s[6:7], v[3:4]
s_delay_alu instid0(VALU_DEP_3)
s_and_b32 s2, s2, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
s_and_b32 s2, s3, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 exec_lo, exec_lo, s2
s_cbranch_execz .LBB0_15
s_cmp_eq_u64 s[8:9], 0
s_mov_b64 s[2:3], 0
s_cbranch_scc1 .LBB0_13
s_load_b64 s[4:5], s[0:1], 0x8
v_lshlrev_b32_e32 v0, 2, v0
s_lshl_b64 s[10:11], s[8:9], 2
s_delay_alu instid0(VALU_DEP_1)
v_lshl_add_u32 v5, v5, 7, v0
v_mov_b32_e32 v0, 0
.p2align 6
.LBB0_10:
s_delay_alu instid0(VALU_DEP_2)
v_mov_b32_e32 v6, v5
s_mov_b64 s[12:13], 0
s_waitcnt lgkmcnt(0)
s_mov_b64 s[14:15], s[4:5]
.LBB0_11:
s_load_b32 s16, s[14:15], 0x0
ds_load_b32 v7, v6
s_add_u32 s12, s12, 1
s_addc_u32 s13, s13, 0
v_add_nc_u32_e32 v6, 4, v6
v_cmp_ge_u64_e64 s17, s[12:13], s[8:9]
s_add_u32 s14, s14, 4
s_addc_u32 s15, s15, 0
s_delay_alu instid0(VALU_DEP_1)
s_and_b32 vcc_lo, exec_lo, s17
s_waitcnt lgkmcnt(0)
v_fmac_f32_e32 v0, s16, v7
s_cbranch_vccz .LBB0_11
s_add_u32 s2, s2, 1
s_addc_u32 s3, s3, 0
v_add_nc_u32_e32 v5, 0x80, v5
v_cmp_ge_u64_e64 s12, s[2:3], s[8:9]
s_add_u32 s4, s4, s10
s_addc_u32 s5, s5, s11
s_delay_alu instid0(VALU_DEP_1)
s_and_b32 vcc_lo, exec_lo, s12
s_cbranch_vccz .LBB0_10
s_branch .LBB0_14
.LBB0_13:
v_mov_b32_e32 v0, 0
.LBB0_14:
s_load_b64 s[0:1], s[0:1], 0x10
v_mul_lo_u32 v2, v2, s6
v_mul_lo_u32 v7, v1, s7
v_mad_u64_u32 v[5:6], null, v1, s6, 0
v_lshlrev_b64 v[3:4], 2, v[3:4]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add3_u32 v6, v6, v7, v2
v_lshlrev_b64 v[1:2], 2, v[5:6]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v1, vcc_lo, s0, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v1, vcc_lo, v1, v3
v_add_co_ci_u32_e32 v2, vcc_lo, v2, v4, vcc_lo
global_store_b32 v[1:2], v0, off
.LBB0_15:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z26tiledConvolution_2D_KernelPfPKfS_mmmi
.amdhsa_group_segment_fixed_size 4096
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 52
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 13
.amdhsa_next_free_sgpr 18
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z26tiledConvolution_2D_KernelPfPKfS_mmmi, .Lfunc_end0-_Z26tiledConvolution_2D_KernelPfPKfS_mmmi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .actual_access: read_only
.address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 8
.value_kind: by_value
- .offset: 32
.size: 8
.value_kind: by_value
- .offset: 40
.size: 8
.value_kind: by_value
- .offset: 48
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 4096
.kernarg_segment_align: 8
.kernarg_segment_size: 52
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z26tiledConvolution_2D_KernelPfPKfS_mmmi
.private_segment_fixed_size: 0
.sgpr_count: 20
.sgpr_spill_count: 0
.symbol: _Z26tiledConvolution_2D_KernelPfPKfS_mmmi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 13
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000b2b0e_00000000-6_tiledConvolution-2D.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "/home/ubuntu/Datasets/stackv2/train-structured/daniel0306123/cuda/master/convolution/tiledConvolution-2D.cu"
.align 8
.LC1:
.string "CUDA error in line %u in file %s: %s\n"
.text
.globl _Z10errorCheckj
.type _Z10errorCheckj, @function
_Z10errorCheckj:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movl %edi, %ebx
call cudaGetLastError@PLT
testl %eax, %eax
jne .L6
popq %rbx
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L6:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
leal -1(%rbx), %edx
leaq .LC0(%rip), %rcx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size _Z10errorCheckj, .-_Z10errorCheckj
.globl _Z55__device_stub__Z26tiledConvolution_2D_KernelPfPKfS_mmmiPfPKfS_mmmi
.type _Z55__device_stub__Z26tiledConvolution_2D_KernelPfPKfS_mmmiPfPKfS_mmmi, @function
_Z55__device_stub__Z26tiledConvolution_2D_KernelPfPKfS_mmmiPfPKfS_mmmi:
.LFB2084:
.cfi_startproc
endbr64
subq $200, %rsp
.cfi_def_cfa_offset 208
movq %rdi, 40(%rsp)
movq %rdx, 32(%rsp)
movq %rcx, 24(%rsp)
movq %r8, 16(%rsp)
movq %r9, 8(%rsp)
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 128(%rsp)
movq %rsi, 56(%rsp)
leaq 56(%rsp), %rax
movq %rax, 136(%rsp)
leaq 32(%rsp), %rax
movq %rax, 144(%rsp)
leaq 24(%rsp), %rax
movq %rax, 152(%rsp)
leaq 16(%rsp), %rax
movq %rax, 160(%rsp)
leaq 8(%rsp), %rax
movq %rax, 168(%rsp)
leaq 208(%rsp), %rax
movq %rax, 176(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L11
.L7:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L12
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 216
pushq 72(%rsp)
.cfi_def_cfa_offset 224
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq _Z26tiledConvolution_2D_KernelPfPKfS_mmmi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L7
.L12:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z55__device_stub__Z26tiledConvolution_2D_KernelPfPKfS_mmmiPfPKfS_mmmi, .-_Z55__device_stub__Z26tiledConvolution_2D_KernelPfPKfS_mmmiPfPKfS_mmmi
.globl _Z26tiledConvolution_2D_KernelPfPKfS_mmmi
.type _Z26tiledConvolution_2D_KernelPfPKfS_mmmi, @function
_Z26tiledConvolution_2D_KernelPfPKfS_mmmi:
.LFB2085:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
call _Z55__device_stub__Z26tiledConvolution_2D_KernelPfPKfS_mmmiPfPKfS_mmmi
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z26tiledConvolution_2D_KernelPfPKfS_mmmi, .-_Z26tiledConvolution_2D_KernelPfPKfS_mmmi
.globl _Z14convolution_2DPfS_S_mmmi
.type _Z14convolution_2DPfS_S_mmmi, @function
_Z14convolution_2DPfS_S_mmmi:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $88, %rsp
.cfi_def_cfa_offset 144
movq %rdi, %r15
movq %rsi, (%rsp)
movq %rdx, 8(%rsp)
movq %rcx, %rbp
movq %r8, %r12
movq %r9, %r13
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
pxor %xmm4, %xmm4
cvtsi2ssl 144(%rsp), %xmm4
testq %rcx, %rcx
js .L16
pxor %xmm0, %xmm0
cvtsi2ssq %rcx, %xmm0
.L17:
divss %xmm4, %xmm0
movaps %xmm0, %xmm1
movss .LC5(%rip), %xmm3
movaps %xmm0, %xmm2
andps %xmm3, %xmm2
movss .LC2(%rip), %xmm5
ucomiss %xmm2, %xmm5
jbe .L18
cvttss2sil %xmm0, %eax
pxor %xmm2, %xmm2
cvtsi2ssl %eax, %xmm2
cmpnless %xmm2, %xmm1
movss .LC4(%rip), %xmm5
andps %xmm5, %xmm1
addss %xmm2, %xmm1
andnps %xmm0, %xmm3
orps %xmm3, %xmm1
.L18:
testq %r12, %r12
js .L19
pxor %xmm0, %xmm0
cvtsi2ssq %r12, %xmm0
.L20:
divss %xmm4, %xmm0
movaps %xmm0, %xmm4
movss .LC5(%rip), %xmm3
movaps %xmm0, %xmm2
andps %xmm3, %xmm2
movss .LC2(%rip), %xmm5
ucomiss %xmm2, %xmm5
jbe .L21
cvttss2sil %xmm0, %eax
pxor %xmm2, %xmm2
cvtsi2ssl %eax, %xmm2
cmpnless %xmm2, %xmm4
movss .LC4(%rip), %xmm5
andps %xmm5, %xmm4
addss %xmm2, %xmm4
andnps %xmm0, %xmm3
orps %xmm3, %xmm4
.L21:
cvttss2siq %xmm4, %rax
movl %eax, 48(%rsp)
cvttss2siq %xmm1, %rax
movl %eax, 52(%rsp)
movl $1, 56(%rsp)
movl $32, 60(%rsp)
movl $32, 64(%rsp)
movl $1, 68(%rsp)
movq %rbp, %rbx
imulq %r12, %rbx
salq $2, %rbx
movq %r13, %r14
imulq %r13, %r14
salq $2, %r14
leaq 24(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl $76, %edi
call _Z10errorCheckj
leaq 32(%rsp), %rdi
movq %r14, %rsi
call cudaMalloc@PLT
movl $78, %edi
call _Z10errorCheckj
leaq 40(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl $80, %edi
call _Z10errorCheckj
movl $1, %ecx
movq %rbx, %rdx
movq %r15, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl $83, %edi
call _Z10errorCheckj
movl $1, %ecx
movq %r14, %rdx
movq (%rsp), %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
movl $85, %edi
call _Z10errorCheckj
movl 68(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movq 48(%rsp), %rdi
movl 56(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L25
.L22:
movl $88, %edi
call _Z10errorCheckj
movl $2, %ecx
movq %rbx, %rdx
movq 40(%rsp), %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $91, %edi
call _Z10errorCheckj
movq 24(%rsp), %rdi
call cudaFree@PLT
movl $94, %edi
call _Z10errorCheckj
movq 32(%rsp), %rdi
call cudaFree@PLT
movl $96, %edi
call _Z10errorCheckj
movq 40(%rsp), %rdi
call cudaFree@PLT
movl $98, %edi
call _Z10errorCheckj
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L26
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L16:
.cfi_restore_state
movq %rcx, %rax
shrq %rax
movq %rcx, %rdx
andl $1, %edx
orq %rdx, %rax
pxor %xmm0, %xmm0
cvtsi2ssq %rax, %xmm0
addss %xmm0, %xmm0
jmp .L17
.L19:
movq %r12, %rax
shrq %rax
movq %r12, %rdx
andl $1, %edx
orq %rdx, %rax
pxor %xmm0, %xmm0
cvtsi2ssq %rax, %xmm0
addss %xmm0, %xmm0
jmp .L20
.L25:
subq $8, %rsp
.cfi_def_cfa_offset 152
movl 152(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 160
movq %r13, %r9
movq %r12, %r8
movq %rbp, %rcx
movq 56(%rsp), %rdx
movq 48(%rsp), %rsi
movq 40(%rsp), %rdi
call _Z55__device_stub__Z26tiledConvolution_2D_KernelPfPKfS_mmmiPfPKfS_mmmi
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L22
.L26:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size _Z14convolution_2DPfS_S_mmmi, .-_Z14convolution_2DPfS_S_mmmi
.section .rodata.str1.8
.align 8
.LC7:
.string "Execution time: %d microseconds."
.text
.globl main
.type main, @function
main:
.LFB2059:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $72, %rsp
.cfi_def_cfa_offset 128
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $0, %edi
call time@PLT
movl %eax, %edi
call srand@PLT
call rand@PLT
movslq %eax, %rdx
imulq $2139127681, %rdx, %rdx
sarq $39, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
movl %edx, %ecx
sall $8, %ecx
addl %ecx, %edx
subl %edx, %eax
leal 3840(%rax), %r12d
movslq %r12d, %r12
call rand@PLT
movslq %eax, %rdx
imulq $2139127681, %rdx, %rdx
sarq $39, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
movl %edx, %ecx
sall $8, %ecx
addl %ecx, %edx
subl %edx, %eax
leal 3840(%rax), %r13d
movslq %r13d, %r13
movq %r12, %rbp
imulq %r13, %rbp
salq $2, %rbp
movq %rbp, %rdi
call malloc@PLT
movq %rax, %r14
movl $484, %edi
call malloc@PLT
movq %rax, %r15
movq %rbp, %rdi
call malloc@PLT
movq %rax, 8(%rsp)
movq %r14, %rbx
addq %r14, %rbp
.L28:
call rand@PLT
movslq %eax, %rdx
imulq $266354561, %rdx, %rdx
sarq $35, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
movl %edx, %ecx
sall $7, %ecx
addl %ecx, %edx
subl %edx, %eax
subl $64, %eax
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, (%rbx)
addq $4, %rbx
cmpq %rbp, %rbx
jne .L28
movq %r15, %rbx
leaq 484(%r15), %rbp
.L29:
call rand@PLT
movslq %eax, %rdx
imulq $1098413215, %rdx, %rdx
sarq $40, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
imull $1001, %edx, %edx
subl %edx, %eax
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
divsd .LC6(%rip), %xmm0
cvtsd2ss %xmm0, %xmm0
movss %xmm0, (%rbx)
addq $4, %rbx
cmpq %rbp, %rbx
jne .L29
leaq 16(%rsp), %rsi
movl $0, %edi
call clock_gettime@PLT
subq $8, %rsp
.cfi_def_cfa_offset 136
pushq $22
.cfi_def_cfa_offset 144
movl $11, %r9d
movq %r13, %r8
movq %r12, %rcx
movq 24(%rsp), %rdx
movq %r15, %rsi
movq %r14, %rdi
call _Z14convolution_2DPfS_S_mmmi
leaq 48(%rsp), %rsi
movl $0, %edi
call clock_gettime@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
movq 32(%rsp), %rcx
subq 16(%rsp), %rcx
imulq $1000000, %rcx, %rcx
movq 40(%rsp), %rsi
subq 24(%rsp), %rsi
movabsq $2361183241434822607, %rdx
movq %rsi, %rax
imulq %rdx
sarq $7, %rdx
sarq $63, %rsi
subq %rsi, %rdx
addq %rcx, %rdx
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L34
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L34:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size main, .-main
.section .rodata.str1.8
.align 8
.LC8:
.string "_Z26tiledConvolution_2D_KernelPfPKfS_mmmi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _Z26tiledConvolution_2D_KernelPfPKfS_mmmi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC2:
.long 1258291200
.align 4
.LC4:
.long 1065353216
.align 4
.LC5:
.long 2147483647
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC6:
.long 0
.long 1083129856
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "tiledConvolution-2D.hip"
.globl _Z41__device_stub__tiledConvolution_2D_KernelPfPKfS_mmmi # -- Begin function _Z41__device_stub__tiledConvolution_2D_KernelPfPKfS_mmmi
.p2align 4, 0x90
.type _Z41__device_stub__tiledConvolution_2D_KernelPfPKfS_mmmi,@function
_Z41__device_stub__tiledConvolution_2D_KernelPfPKfS_mmmi: # @_Z41__device_stub__tiledConvolution_2D_KernelPfPKfS_mmmi
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
movq %r9, 48(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 160(%rsp), %rax
movq %rax, 144(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z26tiledConvolution_2D_KernelPfPKfS_mmmi, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z41__device_stub__tiledConvolution_2D_KernelPfPKfS_mmmi, .Lfunc_end0-_Z41__device_stub__tiledConvolution_2D_KernelPfPKfS_mmmi
.cfi_endproc
# -- End function
.globl _Z10errorCheckj # -- Begin function _Z10errorCheckj
.p2align 4, 0x90
.type _Z10errorCheckj,@function
_Z10errorCheckj: # @_Z10errorCheckj
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
movl %edi, %ebx
callq hipGetLastError
testl %eax, %eax
jne .LBB1_2
# %bb.1:
popq %rbx
.cfi_def_cfa_offset 8
retq
.LBB1_2:
.cfi_def_cfa_offset 16
decl %ebx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.1, %edx
movl %ebx, %esi
movq %rax, %rcx
xorl %eax, %eax
callq printf
movl $1, %edi
callq exit
.Lfunc_end1:
.size _Z10errorCheckj, .Lfunc_end1-_Z10errorCheckj
.cfi_endproc
# -- End function
.globl _Z14convolution_2DPfS_S_mmmi # -- Begin function _Z14convolution_2DPfS_S_mmmi
.p2align 4, 0x90
.type _Z14convolution_2DPfS_S_mmmi,@function
_Z14convolution_2DPfS_S_mmmi: # @_Z14convolution_2DPfS_S_mmmi
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $216, %rsp
.cfi_def_cfa_offset 272
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %r9, %r14
movq %r8, %r15
movq %rcx, %r12
movq %rdx, 48(%rsp) # 8-byte Spill
movq %rsi, 56(%rsp) # 8-byte Spill
movq %rdi, %rbx
testq %r8, %r8
js .LBB2_1
# %bb.2:
cvtsi2ss %r15, %xmm0
jmp .LBB2_3
.LBB2_1:
movq %r15, %rax
shrq %rax
movl %r15d, %ecx
andl $1, %ecx
orq %rax, %rcx
cvtsi2ss %rcx, %xmm0
addss %xmm0, %xmm0
.LBB2_3:
cvtsi2ssl 272(%rsp), %xmm1
movss %xmm1, 12(%rsp) # 4-byte Spill
divss %xmm1, %xmm0
callq ceilf@PLT
movss %xmm0, 40(%rsp) # 4-byte Spill
testq %r12, %r12
js .LBB2_4
# %bb.5:
xorps %xmm0, %xmm0
cvtsi2ss %r12, %xmm0
jmp .LBB2_6
.LBB2_4:
movq %r12, %rax
shrq %rax
movl %r12d, %ecx
andl $1, %ecx
orq %rax, %rcx
xorps %xmm0, %xmm0
cvtsi2ss %rcx, %xmm0
addss %xmm0, %xmm0
.LBB2_6:
divss 12(%rsp), %xmm0 # 4-byte Folded Reload
callq ceilf@PLT
movss %xmm0, 12(%rsp) # 4-byte Spill
movq %r12, %r13
imulq %r15, %r13
shlq $2, %r13
leaq 32(%rsp), %rdi
movq %r13, %rsi
callq hipMalloc
callq hipGetLastError
testl %eax, %eax
jne .LBB2_7
# %bb.9: # %_Z10errorCheckj.exit
movq %r14, %rbp
imulq %r14, %r14
shlq $2, %r14
leaq 24(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
callq hipGetLastError
testl %eax, %eax
jne .LBB2_10
# %bb.11: # %_Z10errorCheckj.exit27
leaq 16(%rsp), %rdi
movq %r13, %rsi
callq hipMalloc
callq hipGetLastError
testl %eax, %eax
jne .LBB2_12
# %bb.13: # %_Z10errorCheckj.exit29
movq 32(%rsp), %rdi
movq %rbx, %rsi
movq %r13, %rdx
movl $1, %ecx
callq hipMemcpy
callq hipGetLastError
testl %eax, %eax
jne .LBB2_14
# %bb.15: # %_Z10errorCheckj.exit31
movq 24(%rsp), %rdi
movq 56(%rsp), %rsi # 8-byte Reload
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
callq hipGetLastError
testl %eax, %eax
jne .LBB2_16
# %bb.17: # %_Z10errorCheckj.exit33
cvttss2si 40(%rsp), %rax # 4-byte Folded Reload
cvttss2si 12(%rsp), %rdi # 4-byte Folded Reload
movl %eax, %eax
shlq $32, %rdi
orq %rax, %rdi
movabsq $137438953504, %rdx # imm = 0x2000000020
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_19
# %bb.18:
movq 32(%rsp), %rax
movq 24(%rsp), %rcx
movq 16(%rsp), %rdx
movq %rax, 152(%rsp)
movq %rcx, 144(%rsp)
movq %rdx, 136(%rsp)
movq %r12, 128(%rsp)
movq %r15, 120(%rsp)
movq %rbp, 112(%rsp)
movl 272(%rsp), %eax
movl %eax, 44(%rsp)
leaq 152(%rsp), %rax
movq %rax, 160(%rsp)
leaq 144(%rsp), %rax
movq %rax, 168(%rsp)
leaq 136(%rsp), %rax
movq %rax, 176(%rsp)
leaq 128(%rsp), %rax
movq %rax, 184(%rsp)
leaq 120(%rsp), %rax
movq %rax, 192(%rsp)
leaq 112(%rsp), %rax
movq %rax, 200(%rsp)
leaq 44(%rsp), %rax
movq %rax, 208(%rsp)
leaq 96(%rsp), %rdi
leaq 80(%rsp), %rsi
leaq 72(%rsp), %rdx
leaq 64(%rsp), %rcx
callq __hipPopCallConfiguration
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
movq 80(%rsp), %rcx
movl 88(%rsp), %r8d
leaq 160(%rsp), %r9
movl $_Z26tiledConvolution_2D_KernelPfPKfS_mmmi, %edi
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
pushq 80(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_19:
callq hipGetLastError
testl %eax, %eax
jne .LBB2_20
# %bb.21: # %_Z10errorCheckj.exit35
movq 16(%rsp), %rsi
movq 48(%rsp), %rdi # 8-byte Reload
movq %r13, %rdx
movl $2, %ecx
callq hipMemcpy
callq hipGetLastError
testl %eax, %eax
jne .LBB2_22
# %bb.23: # %_Z10errorCheckj.exit37
movq 32(%rsp), %rdi
callq hipFree
callq hipGetLastError
testl %eax, %eax
jne .LBB2_24
# %bb.25: # %_Z10errorCheckj.exit39
movq 24(%rsp), %rdi
callq hipFree
callq hipGetLastError
testl %eax, %eax
jne .LBB2_26
# %bb.27: # %_Z10errorCheckj.exit41
movq 16(%rsp), %rdi
callq hipFree
callq hipGetLastError
testl %eax, %eax
jne .LBB2_28
# %bb.29: # %_Z10errorCheckj.exit43
addq $216, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB2_7:
.cfi_def_cfa_offset 272
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.1, %edx
movl $75, %esi
jmp .LBB2_8
.LBB2_10:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.1, %edx
movl $77, %esi
jmp .LBB2_8
.LBB2_12:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.1, %edx
movl $79, %esi
jmp .LBB2_8
.LBB2_14:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.1, %edx
movl $82, %esi
jmp .LBB2_8
.LBB2_16:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.1, %edx
movl $84, %esi
jmp .LBB2_8
.LBB2_20:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.1, %edx
movl $87, %esi
jmp .LBB2_8
.LBB2_22:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.1, %edx
movl $90, %esi
jmp .LBB2_8
.LBB2_24:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.1, %edx
movl $93, %esi
jmp .LBB2_8
.LBB2_26:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.1, %edx
movl $95, %esi
jmp .LBB2_8
.LBB2_28:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.1, %edx
movl $97, %esi
.LBB2_8:
movq %rax, %rcx
xorl %eax, %eax
callq printf
movl $1, %edi
callq exit
.Lfunc_end2:
.size _Z14convolution_2DPfS_S_mmmi, .Lfunc_end2-_Z14convolution_2DPfS_S_mmmi
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI3_0:
.quad 0x408f400000000000 # double 1000
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0: # %.lr.ph.preheader
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $56, %rsp
.cfi_def_cfa_offset 112
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
xorl %ebp, %ebp
xorl %edi, %edi
callq time
movl %eax, %edi
callq srand
callq rand
cltq
imulq $2139127681, %rax, %rcx # imm = 0x7F807F81
movq %rcx, %rdx
shrq $63, %rdx
sarq $39, %rcx
addl %edx, %ecx
movl %ecx, %edx
shll $8, %edx
addl %ecx, %edx
negl %edx
leal (%rax,%rdx), %r15d
addl $3840, %r15d # imm = 0xF00
callq rand
cltq
imulq $2139127681, %rax, %rcx # imm = 0x7F807F81
movq %rcx, %rdx
shrq $63, %rdx
sarq $39, %rcx
addl %edx, %ecx
movl %ecx, %edx
shll $8, %edx
addl %ecx, %edx
negl %edx
leal (%rax,%rdx), %ebx
addl $3840, %ebx # imm = 0xF00
movq %rbx, %r14
movq %r15, 16(%rsp) # 8-byte Spill
imulq %r15, %r14
leaq (,%r14,4), %r13
movq %r13, %rdi
callq malloc
movq %rax, %r15
movl $484, %edi # imm = 0x1E4
callq malloc
movq %rax, %r12
movq %r13, %rdi
callq malloc
movq %rax, %r13
.p2align 4, 0x90
.LBB3_1: # %.lr.ph
# =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $266354561, %rax, %rcx # imm = 0xFE03F81
movq %rcx, %rdx
shrq $63, %rdx
sarq $35, %rcx
addl %edx, %ecx
movl %ecx, %edx
shll $7, %edx
addl %ecx, %edx
negl %edx
addl %edx, %eax
addl $-64, %eax
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, (%r15,%rbp,4)
incq %rbp
cmpq %rbp, %r14
jne .LBB3_1
# %bb.2: # %.preheader.preheader
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB3_3: # %.preheader
# =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $1098413215, %rax, %rcx # imm = 0x4178749F
movq %rcx, %rdx
shrq $63, %rdx
sarq $40, %rcx
addl %edx, %ecx
imull $1001, %ecx, %ecx # imm = 0x3E9
subl %ecx, %eax
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
divsd .LCPI3_0(%rip), %xmm0
cvtsd2ss %xmm0, %xmm0
movss %xmm0, (%r12,%r14,4)
incq %r14
cmpq $121, %r14
jne .LBB3_3
# %bb.4:
leaq 40(%rsp), %rsi
xorl %edi, %edi
callq clock_gettime
movl $22, (%rsp)
movl $11, %r9d
movq %r15, %rdi
movq %r12, %rsi
movq %r13, %rdx
movq 16(%rsp), %rcx # 8-byte Reload
movq %rbx, %r8
callq _Z14convolution_2DPfS_S_mmmi
leaq 24(%rsp), %rsi
xorl %edi, %edi
callq clock_gettime
movq 24(%rsp), %rcx
movq 32(%rsp), %rax
subq 40(%rsp), %rcx
imulq $1000000, %rcx, %rcx # imm = 0xF4240
subq 48(%rsp), %rax
movabsq $2361183241434822607, %rdx # imm = 0x20C49BA5E353F7CF
imulq %rdx
movq %rdx, %rsi
shrq $63, %rsi
sarq $7, %rdx
addq %rdx, %rsi
addq %rcx, %rsi
movl $.L.str.2, %edi
xorl %eax, %eax
callq printf
xorl %eax, %eax
addq $56, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z26tiledConvolution_2D_KernelPfPKfS_mmmi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z26tiledConvolution_2D_KernelPfPKfS_mmmi,@object # @_Z26tiledConvolution_2D_KernelPfPKfS_mmmi
.section .rodata,"a",@progbits
.globl _Z26tiledConvolution_2D_KernelPfPKfS_mmmi
.p2align 3, 0x0
_Z26tiledConvolution_2D_KernelPfPKfS_mmmi:
.quad _Z41__device_stub__tiledConvolution_2D_KernelPfPKfS_mmmi
.size _Z26tiledConvolution_2D_KernelPfPKfS_mmmi, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "CUDA error in line %u in file %s: %s\n"
.size .L.str, 38
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/daniel0306123/cuda/master/convolution/tiledConvolution-2D.hip"
.size .L.str.1, 119
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Execution time: %d microseconds."
.size .L.str.2, 33
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z26tiledConvolution_2D_KernelPfPKfS_mmmi"
.size .L__unnamed_1, 42
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z41__device_stub__tiledConvolution_2D_KernelPfPKfS_mmmi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z26tiledConvolution_2D_KernelPfPKfS_mmmi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | /* Program : To find the matrix multiplication of rectangular matrices using tiling
* Author : Anant Shah
* Date : 11-9-2018
* Roll Number : EE16B105
**/
#include<stdio.h>
#define ERROR_HANDLER(error_msg,line) error_handler(error_msg,line)
#define ROWS_M 8192
#define COLS_M 16384
#define ROWS_N 16384
#define COLS_N 32768
#define NUM_THREADS_X 32
#define NUM_THREADS_Y 32
#define TILE_WIDTH_X 32
#define TILE_WIDTH_Y 32
void error_handler(cudaError_t error_msg,int line){
if(error_msg!=cudaSuccess){
printf("%s in %s at %d",cudaGetErrorString(error_msg),__FILE__,line);
exit(EXIT_FAILURE);
}
}
void fill_matrix(double *mat,unsigned numRows,unsigned numCols){
/* function to fill a mtrix with values */
for(unsigned i=0;i<numRows;i++){
for(unsigned j=0;j<numCols;j++){
mat[i*numCols+j] = i*2.1f + j*3.2f;
}
}
}
void print_matrix_to_file(double *mat,unsigned numRows,unsigned numCols){
/* function to print a matrix to a file */
const char *fname = "assignment2_out";
FILE *f = fopen(fname,"a");
for(unsigned i=0;i<numRows;i++){
for(unsigned j=0;j<numCols;j++){
fprintf(f,"%4.4f ", mat[i*numCols+j]);
}
fprintf(f,"\n");
}
fclose(f);
}
__global__ void matrixMul(double *M,double *N,double *P,int numRows_M,int numCols_N,int width){
/* Kernel function to calculate the matrix multiplication of rectangular matrices */
int tx = threadIdx.x; /* Thread-ID in the x-direction */
int ty = threadIdx.y; /* Thread-ID in the y-direction */
__shared__ double Ms[TILE_WIDTH_Y][TILE_WIDTH_X]; /* Shared memory to be used by threads in a block */
__shared__ double Ns[TILE_WIDTH_X][TILE_WIDTH_Y]; /* Shared memory to be used by therads in a block */
int row = blockIdx.y*blockDim.y + ty; /* row in the output matrix */
int col = blockIdx.x*blockDim.x + tx; /* column in the output matrix */
double pSum = 0.0;
for(int m=0;m<(width+NUM_THREADS_X-1)/NUM_THREADS_X;m++){
/* Load Pahse : Load elements cooperatively into the shared memeory */
Ms[ty][tx] = M[row*width+m*TILE_WIDTH_X+tx];
Ns[ty][tx] = N[(ty+m*TILE_WIDTH_Y)*numCols_N+col]; /* This is assuming that the tile is a sqaure */
__syncthreads();
for(int i=0;i<TILE_WIDTH_X;i++){
pSum += Ms[ty][i]*Ns[i][tx];
}
__syncthreads();
}
P[row*numCols_N+col] = pSum;
}
int main(int argc,char **argv){
if(argc!=1){
printf("error : Invalid number of arguments\n");
exit(EXIT_FAILURE);
}
if(COLS_M!=ROWS_N){
printf("Error : Invalid matrix dimensions");
exit(EXIT_FAILURE);
}
/************************************* Variable Initialization **************************************/
double *h_M; /*Rectangular matrix M on the host */
double *d_M; /*Rectangular matrix M on the device */
size_t size_M; /* Size of the rectangular matrix M in bytes */
double *h_N; /* Rectangular matrix N on the host */
double *d_N; /* Rectangular matrix N on the device */
size_t size_N; /* Size of the matrix N in bytes */
double *h_P; /* Product M*N on the host */
double *d_P; /* Product M*N on the device */
size_t size_P; /* Size of the matrix P in bytes */
cudaEvent_t start,stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
size_M = sizeof(double)*ROWS_M*COLS_M;
size_N = sizeof(double)*ROWS_N*COLS_N;
size_P = sizeof(double)*ROWS_M*COLS_N;
/************************************** Memory Allocation on the Host ********************************/
h_M = (double *)malloc(size_M);
h_N = (double *)malloc(size_N);
h_P = (double *)malloc(size_P);
/************************************** Initialize the matrices ***************************************/
fill_matrix(h_M,ROWS_M,COLS_M);
fill_matrix(h_N,ROWS_N,COLS_N);
/************************************** Allocate memory on the device *********************************/
ERROR_HANDLER(cudaMalloc((void **)&d_M,size_M),__LINE__);
ERROR_HANDLER(cudaMalloc((void **)&d_N,size_N),__LINE__);
ERROR_HANDLER(cudaMalloc((void **)&d_P,size_P),__LINE__);
/************************************** Copy Matrices to the device ***********************************/
ERROR_HANDLER(cudaMemcpy(d_M,h_M,size_M,cudaMemcpyHostToDevice),__LINE__);
ERROR_HANDLER(cudaMemcpy(d_N,h_N,size_N,cudaMemcpyHostToDevice),__LINE__);
/************************************** Kernel invocation *********************************************/
dim3 threads(NUM_THREADS_X,NUM_THREADS_Y); /*2-D layout of the threads in a block */
dim3 blocks((COLS_N+NUM_THREADS_X-1)/NUM_THREADS_X,(ROWS_M+NUM_THREADS_Y-1)/NUM_THREADS_Y); /*2-D layout of blocks in a grid */
cudaEventRecord(start);
matrixMul<<<blocks,threads>>>(d_M,d_N,d_P,ROWS_M,COLS_N,COLS_M); /* The last parameter could have been <ROWS_N> */
cudaEventRecord(stop);
ERROR_HANDLER(cudaMemcpy(h_P,d_P,size_P,cudaMemcpyDeviceToHost),__LINE__);
cudaEventSynchronize(stop);
float run_time = 0.0;
cudaEventElapsedTime(&run_time,start,stop);
printf("Run-Time(seconds) : %.4f",run_time/1000);
print_matrix_to_file(h_P,ROWS_M,COLS_N);
/********************************** Free Allocated Memory ********************************************/
cudaFree(d_M);
cudaFree(d_N);
cudaFree(d_P);
free(h_M);
free(h_N);
free(h_P);
} | code for sm_80
Function : _Z9matrixMulPdS_S_iii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e220000002600 */
/*0020*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x180] ; /* 0x00006000ff027624 */
/* 0x000fe200078e00ff */
/*0030*/ HFMA2.MMA R17, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff117435 */
/* 0x000fe200000001ff */
/*0040*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*0050*/ S2R R7, SR_TID.Y ; /* 0x0000000000077919 */
/* 0x000e220000002200 */
/*0060*/ CS2R R10, SRZ ; /* 0x00000000000a7805 */
/* 0x000fe2000001ff00 */
/*0070*/ ISETP.GE.AND P0, PT, R2, 0x1, PT ; /* 0x000000010200780c */
/* 0x000fe40003f06270 */
/*0080*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x000e680000002500 */
/*0090*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e620000002100 */
/*00a0*/ IMAD R3, R3, c[0x0][0x4], R7 ; /* 0x0000010003037a24 */
/* 0x001fc400078e0207 */
/*00b0*/ IMAD R4, R5, c[0x0][0x0], R0 ; /* 0x0000000005047a24 */
/* 0x002fc800078e0200 */
/*00c0*/ IMAD R16, R3, c[0x0][0x17c], R4 ; /* 0x00005f0003107a24 */
/* 0x000fc800078e0204 */
/*00d0*/ IMAD.WIDE R16, R16, R17, c[0x0][0x170] ; /* 0x00005c0010107625 */
/* 0x000fe200078e0211 */
/*00e0*/ @!P0 BRA 0x7d0 ; /* 0x000006e000008947 */
/* 0x000fea0003800000 */
/*00f0*/ IADD3 R5, R2, 0x1f, RZ ; /* 0x0000001f02057810 */
/* 0x000fe20007ffe0ff */
/*0100*/ IMAD.MOV.U32 R18, RZ, RZ, 0x8 ; /* 0x00000008ff127424 */
/* 0x000fe200078e00ff */
/*0110*/ CS2R R10, SRZ ; /* 0x00000000000a7805 */
/* 0x000fe2000001ff00 */
/*0120*/ IMAD R3, R3, c[0x0][0x180], R0 ; /* 0x0000600003037a24 */
/* 0x000fe200078e0200 */
/*0130*/ SHF.R.S32.HI R6, RZ, 0x1f, R5 ; /* 0x0000001fff067819 */
/* 0x000fe20000011405 */
/*0140*/ IMAD R4, R7.reuse, c[0x0][0x17c], R4 ; /* 0x00005f0007047a24 */
/* 0x040fe200078e0204 */
/*0150*/ SHF.L.U32 R7, R7, 0x8, RZ ; /* 0x0000000807077819 */
/* 0x000fe200000006ff */
/*0160*/ IMAD.WIDE R2, R3, R18.reuse, c[0x0][0x160] ; /* 0x0000580003027625 */
/* 0x080fe200078e0212 */
/*0170*/ LEA.HI R8, R6, R5, RZ, 0x5 ; /* 0x0000000506087211 */
/* 0x000fe200078f28ff */
/*0180*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*0190*/ LEA R6, R0, R7, 0x3 ; /* 0x0000000700067211 */
/* 0x000fe200078e18ff */
/*01a0*/ IMAD.WIDE R18, R4, R18, c[0x0][0x168] ; /* 0x00005a0004127625 */
/* 0x000fe200078e0212 */
/*01b0*/ MOV R5, R3 ; /* 0x0000000300057202 */
/* 0x000fc60000000f00 */
/*01c0*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x17c] ; /* 0x00005f00ff037624 */
/* 0x000fc800078e00ff */
/*01d0*/ IMAD.SHL.U32 R4, R3, 0x20, RZ ; /* 0x0000002003047824 */
/* 0x000fe200078e00ff */
/*01e0*/ SHF.R.S32.HI R3, RZ, 0x5, R8 ; /* 0x00000005ff037819 */
/* 0x000fe40000011408 */
/*01f0*/ IMAD.MOV.U32 R26, RZ, RZ, R2 ; /* 0x000000ffff1a7224 */
/* 0x000fe200078e0002 */
/*0200*/ MOV R27, R5 ; /* 0x00000005001b7202 */
/* 0x000fe20000000f00 */
/*0210*/ LDG.E.64 R24, [R18.64] ; /* 0x0000000612187981 */
/* 0x0000aa000c1e1b00 */
/*0220*/ LDG.E.64 R26, [R26.64] ; /* 0x000000061a1a7981 */
/* 0x000ee2000c1e1b00 */
/*0230*/ UIADD3 UR4, UR4, 0x1, URZ ; /* 0x0000000104047890 */
/* 0x000fe2000fffe03f */
/*0240*/ IADD3 R2, P1, R2, 0x100, RZ ; /* 0x0000010002027810 */
/* 0x000fe20007f3e0ff */
/*0250*/ IMAD.WIDE R18, R4, 0x8, R18 ; /* 0x0000000804127825 */
/* 0x001fc600078e0212 */
/*0260*/ IADD3.X R5, RZ, R5, RZ, P1, !PT ; /* 0x00000005ff057210 */
/* 0x000fe40000ffe4ff */
/*0270*/ ISETP.LE.AND P0, PT, R3, UR4, PT ; /* 0x0000000403007c0c */
/* 0x000fe2000bf03270 */
/*0280*/ STS.64 [R6+0x2000], R24 ; /* 0x0020001806007388 */
/* 0x004fe80000000a00 */
/*0290*/ STS.64 [R6], R26 ; /* 0x0000001a06007388 */
/* 0x008fe80000000a00 */
/*02a0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*02b0*/ LDS.64 R8, [R0.X8+0x2000] ; /* 0x0020000000087984 */
/* 0x000fe80000008a00 */
/*02c0*/ LDS.128 R12, [R7] ; /* 0x00000000070c7984 */
/* 0x000e280000000c00 */
/*02d0*/ LDS.64 R20, [R0.X8+0x2100] ; /* 0x0021000000147984 */
/* 0x000e680000008a00 */
/*02e0*/ LDS.64 R22, [R0.X8+0x2200] ; /* 0x0022000000167984 */
/* 0x000fe80000008a00 */
/*02f0*/ LDS.64 R24, [R0.X8+0x2400] ; /* 0x0024000000187984 */
/* 0x000fe20000008a00 */
/*0300*/ DFMA R12, R8, R12, R10 ; /* 0x0000000c080c722b */
/* 0x001046000000000a */
/*0310*/ LDS.128 R8, [R7+0x10] ; /* 0x0000100007087984 */
/* 0x001e260000000c00 */
/*0320*/ DFMA R14, R20, R14, R12 ; /* 0x0000000e140e722b */
/* 0x002224000000000c */
/*0330*/ LDS.64 R20, [R0.X8+0x2300] ; /* 0x0023000000147984 */
/* 0x002e680000008a00 */
/*0340*/ DFMA R8, R22, R8, R14 ; /* 0x000000081608722b */
/* 0x001048000000000e */
/*0350*/ LDS.128 R12, [R7+0x20] ; /* 0x00002000070c7984 */
/* 0x001e240000000c00 */
/*0360*/ DFMA R10, R20, R10, R8 ; /* 0x0000000a140a722b */
/* 0x0022240000000008 */
/*0370*/ LDS.64 R22, [R0.X8+0x2600] ; /* 0x0026000000167984 */
/* 0x000fe80000008a00 */
/*0380*/ LDS.64 R20, [R0.X8+0x2500] ; /* 0x0025000000147984 */
/* 0x002e620000008a00 */
/*0390*/ DFMA R12, R24, R12, R10 ; /* 0x0000000c180c722b */
/* 0x001046000000000a */
/*03a0*/ LDS.128 R8, [R7+0x30] ; /* 0x0000300007087984 */
/* 0x001e280000000c00 */
/*03b0*/ LDS.64 R24, [R0.X8+0x2800] ; /* 0x0028000000187984 */
/* 0x000fe20000008a00 */
/*03c0*/ DFMA R14, R20, R14, R12 ; /* 0x0000000e140e722b */
/* 0x002206000000000c */
/*03d0*/ LDS.64 R20, [R0.X8+0x2700] ; /* 0x0027000000147984 */
/* 0x002e660000008a00 */
/*03e0*/ DFMA R8, R22, R8, R14 ; /* 0x000000081608722b */
/* 0x001048000000000e */
/*03f0*/ LDS.128 R12, [R7+0x40] ; /* 0x00004000070c7984 */
/* 0x001e280000000c00 */
/*0400*/ LDS.64 R22, [R0.X8+0x2a00] ; /* 0x002a000000167984 */
/* 0x000fe20000008a00 */
/*0410*/ DFMA R10, R20, R10, R8 ; /* 0x0000000a140a722b */
/* 0x0022060000000008 */
/*0420*/ LDS.64 R20, [R0.X8+0x2900] ; /* 0x0029000000147984 */
/* 0x002e660000008a00 */
/*0430*/ DFMA R12, R24, R12, R10 ; /* 0x0000000c180c722b */
/* 0x001048000000000a */
/*0440*/ LDS.128 R8, [R7+0x50] ; /* 0x0000500007087984 */
/* 0x001e280000000c00 */
/*0450*/ LDS.64 R24, [R0.X8+0x2c00] ; /* 0x002c000000187984 */
/* 0x000fe20000008a00 */
/*0460*/ DFMA R14, R20, R14, R12 ; /* 0x0000000e140e722b */
/* 0x002206000000000c */
/*0470*/ LDS.64 R20, [R0.X8+0x2b00] ; /* 0x002b000000147984 */
/* 0x002e660000008a00 */
/*0480*/ DFMA R8, R22, R8, R14 ; /* 0x000000081608722b */
/* 0x001048000000000e */
/*0490*/ LDS.128 R12, [R7+0x60] ; /* 0x00006000070c7984 */
/* 0x001e280000000c00 */
/*04a0*/ LDS.64 R22, [R0.X8+0x2e00] ; /* 0x002e000000167984 */
/* 0x000fe20000008a00 */
/*04b0*/ DFMA R10, R20, R10, R8 ; /* 0x0000000a140a722b */
/* 0x0022060000000008 */
/*04c0*/ LDS.64 R20, [R0.X8+0x2d00] ; /* 0x002d000000147984 */
/* 0x002e660000008a00 */
/*04d0*/ DFMA R12, R24, R12, R10 ; /* 0x0000000c180c722b */
/* 0x001048000000000a */
/*04e0*/ LDS.128 R8, [R7+0x70] ; /* 0x0000700007087984 */
/* 0x001e280000000c00 */
/*04f0*/ LDS.64 R24, [R0.X8+0x3000] ; /* 0x0030000000187984 */
/* 0x000fe20000008a00 */
/*0500*/ DFMA R14, R20, R14, R12 ; /* 0x0000000e140e722b */
/* 0x002206000000000c */
/*0510*/ LDS.64 R20, [R0.X8+0x2f00] ; /* 0x002f000000147984 */
/* 0x002e660000008a00 */
/*0520*/ DFMA R8, R22, R8, R14 ; /* 0x000000081608722b */
/* 0x001048000000000e */
/*0530*/ LDS.128 R12, [R7+0x80] ; /* 0x00008000070c7984 */
/* 0x001e280000000c00 */
/*0540*/ LDS.64 R22, [R0.X8+0x3200] ; /* 0x0032000000167984 */
/* 0x000fe20000008a00 */
/*0550*/ DFMA R10, R20, R10, R8 ; /* 0x0000000a140a722b */
/* 0x0022060000000008 */
/*0560*/ LDS.64 R20, [R0.X8+0x3100] ; /* 0x0031000000147984 */
/* 0x002e660000008a00 */
/*0570*/ DFMA R12, R24, R12, R10 ; /* 0x0000000c180c722b */
/* 0x001048000000000a */
/*0580*/ LDS.128 R8, [R7+0x90] ; /* 0x0000900007087984 */
/* 0x001e280000000c00 */
/*0590*/ LDS.64 R24, [R0.X8+0x3400] ; /* 0x0034000000187984 */
/* 0x000fe20000008a00 */
/*05a0*/ DFMA R14, R20, R14, R12 ; /* 0x0000000e140e722b */
/* 0x002206000000000c */
/*05b0*/ LDS.64 R20, [R0.X8+0x3300] ; /* 0x0033000000147984 */
/* 0x002e660000008a00 */
/*05c0*/ DFMA R8, R22, R8, R14 ; /* 0x000000081608722b */
/* 0x001048000000000e */
/*05d0*/ LDS.128 R12, [R7+0xa0] ; /* 0x0000a000070c7984 */
/* 0x001e280000000c00 */
/*05e0*/ LDS.64 R22, [R0.X8+0x3600] ; /* 0x0036000000167984 */
/* 0x000fe20000008a00 */
/*05f0*/ DFMA R10, R20, R10, R8 ; /* 0x0000000a140a722b */
/* 0x0022060000000008 */
/*0600*/ LDS.64 R20, [R0.X8+0x3500] ; /* 0x0035000000147984 */
/* 0x002e660000008a00 */
/*0610*/ DFMA R12, R24, R12, R10 ; /* 0x0000000c180c722b */
/* 0x001048000000000a */
/*0620*/ LDS.128 R8, [R7+0xb0] ; /* 0x0000b00007087984 */
/* 0x001e280000000c00 */
/*0630*/ LDS.64 R24, [R0.X8+0x3800] ; /* 0x0038000000187984 */
/* 0x000fe20000008a00 */
/*0640*/ DFMA R14, R20, R14, R12 ; /* 0x0000000e140e722b */
/* 0x002206000000000c */
/*0650*/ LDS.64 R20, [R0.X8+0x3700] ; /* 0x0037000000147984 */
/* 0x002e660000008a00 */
/*0660*/ DFMA R8, R22, R8, R14 ; /* 0x000000081608722b */
/* 0x001048000000000e */
/*0670*/ LDS.128 R12, [R7+0xc0] ; /* 0x0000c000070c7984 */
/* 0x001e280000000c00 */
/*0680*/ LDS.64 R22, [R0.X8+0x3a00] ; /* 0x003a000000167984 */
/* 0x000fe20000008a00 */
/*0690*/ DFMA R10, R20, R10, R8 ; /* 0x0000000a140a722b */
/* 0x0022060000000008 */
/*06a0*/ LDS.64 R20, [R0.X8+0x3900] ; /* 0x0039000000147984 */
/* 0x002e660000008a00 */
/*06b0*/ DFMA R12, R24, R12, R10 ; /* 0x0000000c180c722b */
/* 0x001048000000000a */
/*06c0*/ LDS.128 R8, [R7+0xd0] ; /* 0x0000d00007087984 */
/* 0x001e280000000c00 */
/*06d0*/ LDS.64 R24, [R0.X8+0x3c00] ; /* 0x003c000000187984 */
/* 0x000fe20000008a00 */
/*06e0*/ DFMA R14, R20, R14, R12 ; /* 0x0000000e140e722b */
/* 0x002206000000000c */
/*06f0*/ LDS.64 R20, [R0.X8+0x3b00] ; /* 0x003b000000147984 */
/* 0x002e660000008a00 */
/*0700*/ DFMA R8, R22, R8, R14 ; /* 0x000000081608722b */
/* 0x001048000000000e */
/*0710*/ LDS.128 R12, [R7+0xe0] ; /* 0x0000e000070c7984 */
/* 0x001e280000000c00 */
/*0720*/ LDS.64 R22, [R0.X8+0x3d00] ; /* 0x003d000000167984 */
/* 0x000ea20000008a00 */
/*0730*/ DFMA R10, R20, R10, R8 ; /* 0x0000000a140a722b */
/* 0x0022060000000008 */
/*0740*/ LDS.64 R20, [R0.X8+0x3e00] ; /* 0x003e000000147984 */
/* 0x002fe60000008a00 */
/*0750*/ DFMA R24, R24, R12, R10 ; /* 0x0000000c1818722b */
/* 0x001088000000000a */
/*0760*/ LDS.128 R8, [R7+0xf0] ; /* 0x0000f00007087984 */
/* 0x001e280000000c00 */
/*0770*/ LDS.64 R12, [R0.X8+0x3f00] ; /* 0x003f0000000c7984 */
/* 0x000e620000008a00 */
/*0780*/ DFMA R14, R22, R14, R24 ; /* 0x0000000e160e722b */
/* 0x004e0c0000000018 */
/*0790*/ DFMA R8, R20, R8, R14 ; /* 0x000000081408722b */
/* 0x001e4c000000000e */
/*07a0*/ DFMA R10, R12, R10, R8 ; /* 0x0000000a0c0a722b */
/* 0x0020620000000008 */
/*07b0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*07c0*/ @!P0 BRA 0x1f0 ; /* 0xfffffa2000008947 */
/* 0x003fea000383ffff */
/*07d0*/ STG.E.64 [R16.64], R10 ; /* 0x0000000a10007986 */
/* 0x000fe2000c101b06 */
/*07e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*07f0*/ BRA 0x7f0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0800*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0810*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0820*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0830*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0840*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0850*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0860*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0870*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /* Program : To find the matrix multiplication of rectangular matrices using tiling
* Author : Anant Shah
* Date : 11-9-2018
* Roll Number : EE16B105
**/
#include<stdio.h>
#define ERROR_HANDLER(error_msg,line) error_handler(error_msg,line)
#define ROWS_M 8192
#define COLS_M 16384
#define ROWS_N 16384
#define COLS_N 32768
#define NUM_THREADS_X 32
#define NUM_THREADS_Y 32
#define TILE_WIDTH_X 32
#define TILE_WIDTH_Y 32
void error_handler(cudaError_t error_msg,int line){
if(error_msg!=cudaSuccess){
printf("%s in %s at %d",cudaGetErrorString(error_msg),__FILE__,line);
exit(EXIT_FAILURE);
}
}
void fill_matrix(double *mat,unsigned numRows,unsigned numCols){
/* function to fill a mtrix with values */
for(unsigned i=0;i<numRows;i++){
for(unsigned j=0;j<numCols;j++){
mat[i*numCols+j] = i*2.1f + j*3.2f;
}
}
}
void print_matrix_to_file(double *mat,unsigned numRows,unsigned numCols){
/* function to print a matrix to a file */
const char *fname = "assignment2_out";
FILE *f = fopen(fname,"a");
for(unsigned i=0;i<numRows;i++){
for(unsigned j=0;j<numCols;j++){
fprintf(f,"%4.4f ", mat[i*numCols+j]);
}
fprintf(f,"\n");
}
fclose(f);
}
__global__ void matrixMul(double *M,double *N,double *P,int numRows_M,int numCols_N,int width){
/* Kernel function to calculate the matrix multiplication of rectangular matrices */
int tx = threadIdx.x; /* Thread-ID in the x-direction */
int ty = threadIdx.y; /* Thread-ID in the y-direction */
__shared__ double Ms[TILE_WIDTH_Y][TILE_WIDTH_X]; /* Shared memory to be used by threads in a block */
__shared__ double Ns[TILE_WIDTH_X][TILE_WIDTH_Y]; /* Shared memory to be used by therads in a block */
int row = blockIdx.y*blockDim.y + ty; /* row in the output matrix */
int col = blockIdx.x*blockDim.x + tx; /* column in the output matrix */
double pSum = 0.0;
for(int m=0;m<(width+NUM_THREADS_X-1)/NUM_THREADS_X;m++){
/* Load Pahse : Load elements cooperatively into the shared memeory */
Ms[ty][tx] = M[row*width+m*TILE_WIDTH_X+tx];
Ns[ty][tx] = N[(ty+m*TILE_WIDTH_Y)*numCols_N+col]; /* This is assuming that the tile is a sqaure */
__syncthreads();
for(int i=0;i<TILE_WIDTH_X;i++){
pSum += Ms[ty][i]*Ns[i][tx];
}
__syncthreads();
}
P[row*numCols_N+col] = pSum;
}
int main(int argc,char **argv){
if(argc!=1){
printf("error : Invalid number of arguments\n");
exit(EXIT_FAILURE);
}
if(COLS_M!=ROWS_N){
printf("Error : Invalid matrix dimensions");
exit(EXIT_FAILURE);
}
/************************************* Variable Initialization **************************************/
double *h_M; /*Rectangular matrix M on the host */
double *d_M; /*Rectangular matrix M on the device */
size_t size_M; /* Size of the rectangular matrix M in bytes */
double *h_N; /* Rectangular matrix N on the host */
double *d_N; /* Rectangular matrix N on the device */
size_t size_N; /* Size of the matrix N in bytes */
double *h_P; /* Product M*N on the host */
double *d_P; /* Product M*N on the device */
size_t size_P; /* Size of the matrix P in bytes */
cudaEvent_t start,stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
size_M = sizeof(double)*ROWS_M*COLS_M;
size_N = sizeof(double)*ROWS_N*COLS_N;
size_P = sizeof(double)*ROWS_M*COLS_N;
/************************************** Memory Allocation on the Host ********************************/
h_M = (double *)malloc(size_M);
h_N = (double *)malloc(size_N);
h_P = (double *)malloc(size_P);
/************************************** Initialize the matrices ***************************************/
fill_matrix(h_M,ROWS_M,COLS_M);
fill_matrix(h_N,ROWS_N,COLS_N);
/************************************** Allocate memory on the device *********************************/
ERROR_HANDLER(cudaMalloc((void **)&d_M,size_M),__LINE__);
ERROR_HANDLER(cudaMalloc((void **)&d_N,size_N),__LINE__);
ERROR_HANDLER(cudaMalloc((void **)&d_P,size_P),__LINE__);
/************************************** Copy Matrices to the device ***********************************/
ERROR_HANDLER(cudaMemcpy(d_M,h_M,size_M,cudaMemcpyHostToDevice),__LINE__);
ERROR_HANDLER(cudaMemcpy(d_N,h_N,size_N,cudaMemcpyHostToDevice),__LINE__);
/************************************** Kernel invocation *********************************************/
dim3 threads(NUM_THREADS_X,NUM_THREADS_Y); /*2-D layout of the threads in a block */
dim3 blocks((COLS_N+NUM_THREADS_X-1)/NUM_THREADS_X,(ROWS_M+NUM_THREADS_Y-1)/NUM_THREADS_Y); /*2-D layout of blocks in a grid */
cudaEventRecord(start);
matrixMul<<<blocks,threads>>>(d_M,d_N,d_P,ROWS_M,COLS_N,COLS_M); /* The last parameter could have been <ROWS_N> */
cudaEventRecord(stop);
ERROR_HANDLER(cudaMemcpy(h_P,d_P,size_P,cudaMemcpyDeviceToHost),__LINE__);
cudaEventSynchronize(stop);
float run_time = 0.0;
cudaEventElapsedTime(&run_time,start,stop);
printf("Run-Time(seconds) : %.4f",run_time/1000);
print_matrix_to_file(h_P,ROWS_M,COLS_N);
/********************************** Free Allocated Memory ********************************************/
cudaFree(d_M);
cudaFree(d_N);
cudaFree(d_P);
free(h_M);
free(h_N);
free(h_P);
} | .file "tmpxft_0013a91f_00000000-6_ee16b105_7.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2063:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2063:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "/home/ubuntu/Datasets/stackv2/train-structured/anantshah200/CS6023/master/Assignment2/ee16b105_7.cu"
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "%s in %s at %d"
.text
.globl _Z13error_handler9cudaErrori
.type _Z13error_handler9cudaErrori, @function
_Z13error_handler9cudaErrori:
.LFB2057:
.cfi_startproc
endbr64
testl %edi, %edi
jne .L8
ret
.L8:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movl %esi, %ebx
call cudaGetErrorString@PLT
movq %rax, %rdx
movl %ebx, %r8d
leaq .LC0(%rip), %rcx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size _Z13error_handler9cudaErrori, .-_Z13error_handler9cudaErrori
.globl _Z11fill_matrixPdjj
.type _Z11fill_matrixPdjj, @function
_Z11fill_matrixPdjj:
.LFB2058:
.cfi_startproc
endbr64
movq %rdi, %r9
movl $0, %r8d
movl $0, %r10d
movss .LC2(%rip), %xmm3
movss .LC3(%rip), %xmm2
testl %esi, %esi
jne .L10
ret
.L17:
movl %r10d, %eax
pxor %xmm1, %xmm1
cvtsi2ssq %rax, %xmm1
mulss %xmm3, %xmm1
movl $0, %eax
.L16:
leal (%r8,%rax), %ecx
movl %eax, %edi
pxor %xmm0, %xmm0
cvtsi2ssq %rdi, %xmm0
mulss %xmm2, %xmm0
addss %xmm1, %xmm0
cvtss2sd %xmm0, %xmm0
movsd %xmm0, (%r9,%rcx,8)
addl $1, %eax
cmpl %eax, %edx
jne .L16
.L18:
addl $1, %r10d
addl %edx, %r8d
cmpl %r10d, %esi
je .L9
.L10:
testl %edx, %edx
jne .L17
jmp .L18
.L9:
ret
.cfi_endproc
.LFE2058:
.size _Z11fill_matrixPdjj, .-_Z11fill_matrixPdjj
.section .rodata.str1.1
.LC4:
.string "a"
.LC5:
.string "assignment2_out"
.LC6:
.string "%4.4f "
.LC7:
.string "\n"
.text
.globl _Z20print_matrix_to_filePdjj
.type _Z20print_matrix_to_filePdjj, @function
_Z20print_matrix_to_filePdjj:
.LFB2059:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $24, %rsp
.cfi_def_cfa_offset 80
movq %rdi, %r13
movl %esi, %ebx
movl %esi, 12(%rsp)
movl %edx, %r15d
leaq .LC4(%rip), %rsi
leaq .LC5(%rip), %rdi
call fopen@PLT
movq %rax, %r12
movl %r15d, %ebp
movl $0, 8(%rsp)
leaq .LC6(%rip), %r14
testl %ebx, %ebx
jne .L23
.L24:
movq %r12, %rdi
call fclose@PLT
addq $24, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L25:
.cfi_restore_state
movl %ebx, %eax
movsd 0(%r13,%rax,8), %xmm0
movq %r14, %rdx
movl $2, %esi
movq %r12, %rdi
movl $1, %eax
call __fprintf_chk@PLT
addl $1, %ebx
cmpl %ebp, %ebx
jne .L25
.L27:
leaq .LC7(%rip), %rdx
movl $2, %esi
movq %r12, %rdi
movl $0, %eax
call __fprintf_chk@PLT
addl $1, 8(%rsp)
movl 8(%rsp), %eax
addl %r15d, %ebp
cmpl %eax, 12(%rsp)
je .L24
.L23:
movl %ebp, %ebx
subl %r15d, %ebx
testl %r15d, %r15d
jne .L25
jmp .L27
.cfi_endproc
.LFE2059:
.size _Z20print_matrix_to_filePdjj, .-_Z20print_matrix_to_filePdjj
.globl _Z35__device_stub__Z9matrixMulPdS_S_iiiPdS_S_iii
.type _Z35__device_stub__Z9matrixMulPdS_S_iiiPdS_S_iii, @function
_Z35__device_stub__Z9matrixMulPdS_S_iiiPdS_S_iii:
.LFB2085:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L37
.L33:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L38
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L37:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z9matrixMulPdS_S_iii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L33
.L38:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2085:
.size _Z35__device_stub__Z9matrixMulPdS_S_iiiPdS_S_iii, .-_Z35__device_stub__Z9matrixMulPdS_S_iiiPdS_S_iii
.globl _Z9matrixMulPdS_S_iii
.type _Z9matrixMulPdS_S_iii, @function
_Z9matrixMulPdS_S_iii:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z9matrixMulPdS_S_iiiPdS_S_iii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _Z9matrixMulPdS_S_iii, .-_Z9matrixMulPdS_S_iii
.section .rodata.str1.8
.align 8
.LC8:
.string "error : Invalid number of arguments\n"
.section .rodata.str1.1
.LC11:
.string "Run-Time(seconds) : %.4f"
.text
.globl main
.type main, @function
main:
.LFB2060:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $80, %rsp
.cfi_def_cfa_offset 128
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
cmpl $1, %edi
jne .L46
leaq 32(%rsp), %rdi
call cudaEventCreate@PLT
leaq 40(%rsp), %rdi
call cudaEventCreate@PLT
movl $1073741824, %edi
call malloc@PLT
movq %rax, %r12
movabsq $4294967296, %r13
movq %r13, %rdi
call malloc@PLT
movq %rax, %rbp
movl $2147483648, %r14d
movq %r14, %rdi
call malloc@PLT
movq %rax, %rbx
movl $16384, %edx
movl $8192, %esi
movq %r12, %rdi
call _Z11fill_matrixPdjj
movl $32768, %edx
movl $16384, %esi
movq %rbp, %rdi
call _Z11fill_matrixPdjj
leaq 8(%rsp), %rdi
movl $1073741824, %esi
call cudaMalloc@PLT
movl %eax, %edi
movl $116, %esi
call _Z13error_handler9cudaErrori
leaq 16(%rsp), %rdi
movq %r13, %rsi
call cudaMalloc@PLT
movl %eax, %edi
movl $117, %esi
call _Z13error_handler9cudaErrori
leaq 24(%rsp), %rdi
movq %r14, %rsi
call cudaMalloc@PLT
movl %eax, %edi
movl $118, %esi
call _Z13error_handler9cudaErrori
movl $1, %ecx
movl $1073741824, %edx
movq %r12, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
movl $122, %esi
call _Z13error_handler9cudaErrori
movl $1, %ecx
movq %r13, %rdx
movq %rbp, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
movl $123, %esi
call _Z13error_handler9cudaErrori
movl $32, 48(%rsp)
movl $32, 52(%rsp)
movl $1, 56(%rsp)
movl $1024, 60(%rsp)
movl $256, 64(%rsp)
movl $1, 68(%rsp)
movl $0, %esi
movq 32(%rsp), %rdi
call cudaEventRecord@PLT
movl 56(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 48(%rsp), %rdx
movq 60(%rsp), %rdi
movl 68(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L47
.L43:
movl $0, %esi
movq 40(%rsp), %rdi
call cudaEventRecord@PLT
movl $2, %ecx
movl $2147483648, %edx
movq 24(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movl %eax, %edi
movl $134, %esi
call _Z13error_handler9cudaErrori
movq 40(%rsp), %rdi
call cudaEventSynchronize@PLT
movl $0x00000000, 4(%rsp)
leaq 4(%rsp), %rdi
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
call cudaEventElapsedTime@PLT
movss 4(%rsp), %xmm0
divss .LC10(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl $32768, %edx
movl $8192, %esi
movq %rbx, %rdi
call _Z20print_matrix_to_filePdjj
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq %r12, %rdi
call free@PLT
movq %rbp, %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L48
movl $0, %eax
addq $80, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L46:
.cfi_restore_state
leaq .LC8(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L47:
movl $16384, %r9d
movl $32768, %r8d
movl $8192, %ecx
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z35__device_stub__Z9matrixMulPdS_S_iiiPdS_S_iii
jmp .L43
.L48:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2060:
.size main, .-main
.section .rodata.str1.1
.LC12:
.string "_Z9matrixMulPdS_S_iii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2088:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC12(%rip), %rdx
movq %rdx, %rcx
leaq _Z9matrixMulPdS_S_iii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2088:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC2:
.long 1074161254
.align 4
.LC3:
.long 1078774989
.align 4
.LC10:
.long 1148846080
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /* Program : To find the matrix multiplication of rectangular matrices using tiling
* Author : Anant Shah
* Date : 11-9-2018
* Roll Number : EE16B105
**/
#include<stdio.h>
#define ERROR_HANDLER(error_msg,line) error_handler(error_msg,line)
#define ROWS_M 8192
#define COLS_M 16384
#define ROWS_N 16384
#define COLS_N 32768
#define NUM_THREADS_X 32
#define NUM_THREADS_Y 32
#define TILE_WIDTH_X 32
#define TILE_WIDTH_Y 32
void error_handler(cudaError_t error_msg,int line){
if(error_msg!=cudaSuccess){
printf("%s in %s at %d",cudaGetErrorString(error_msg),__FILE__,line);
exit(EXIT_FAILURE);
}
}
void fill_matrix(double *mat,unsigned numRows,unsigned numCols){
/* function to fill a mtrix with values */
for(unsigned i=0;i<numRows;i++){
for(unsigned j=0;j<numCols;j++){
mat[i*numCols+j] = i*2.1f + j*3.2f;
}
}
}
void print_matrix_to_file(double *mat,unsigned numRows,unsigned numCols){
/* function to print a matrix to a file */
const char *fname = "assignment2_out";
FILE *f = fopen(fname,"a");
for(unsigned i=0;i<numRows;i++){
for(unsigned j=0;j<numCols;j++){
fprintf(f,"%4.4f ", mat[i*numCols+j]);
}
fprintf(f,"\n");
}
fclose(f);
}
__global__ void matrixMul(double *M,double *N,double *P,int numRows_M,int numCols_N,int width){
/* Kernel function to calculate the matrix multiplication of rectangular matrices */
int tx = threadIdx.x; /* Thread-ID in the x-direction */
int ty = threadIdx.y; /* Thread-ID in the y-direction */
__shared__ double Ms[TILE_WIDTH_Y][TILE_WIDTH_X]; /* Shared memory to be used by threads in a block */
__shared__ double Ns[TILE_WIDTH_X][TILE_WIDTH_Y]; /* Shared memory to be used by therads in a block */
int row = blockIdx.y*blockDim.y + ty; /* row in the output matrix */
int col = blockIdx.x*blockDim.x + tx; /* column in the output matrix */
double pSum = 0.0;
for(int m=0;m<(width+NUM_THREADS_X-1)/NUM_THREADS_X;m++){
/* Load Pahse : Load elements cooperatively into the shared memeory */
Ms[ty][tx] = M[row*width+m*TILE_WIDTH_X+tx];
Ns[ty][tx] = N[(ty+m*TILE_WIDTH_Y)*numCols_N+col]; /* This is assuming that the tile is a sqaure */
__syncthreads();
for(int i=0;i<TILE_WIDTH_X;i++){
pSum += Ms[ty][i]*Ns[i][tx];
}
__syncthreads();
}
P[row*numCols_N+col] = pSum;
}
int main(int argc,char **argv){
if(argc!=1){
printf("error : Invalid number of arguments\n");
exit(EXIT_FAILURE);
}
if(COLS_M!=ROWS_N){
printf("Error : Invalid matrix dimensions");
exit(EXIT_FAILURE);
}
/************************************* Variable Initialization **************************************/
double *h_M; /*Rectangular matrix M on the host */
double *d_M; /*Rectangular matrix M on the device */
size_t size_M; /* Size of the rectangular matrix M in bytes */
double *h_N; /* Rectangular matrix N on the host */
double *d_N; /* Rectangular matrix N on the device */
size_t size_N; /* Size of the matrix N in bytes */
double *h_P; /* Product M*N on the host */
double *d_P; /* Product M*N on the device */
size_t size_P; /* Size of the matrix P in bytes */
cudaEvent_t start,stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
size_M = sizeof(double)*ROWS_M*COLS_M;
size_N = sizeof(double)*ROWS_N*COLS_N;
size_P = sizeof(double)*ROWS_M*COLS_N;
/************************************** Memory Allocation on the Host ********************************/
h_M = (double *)malloc(size_M);
h_N = (double *)malloc(size_N);
h_P = (double *)malloc(size_P);
/************************************** Initialize the matrices ***************************************/
fill_matrix(h_M,ROWS_M,COLS_M);
fill_matrix(h_N,ROWS_N,COLS_N);
/************************************** Allocate memory on the device *********************************/
ERROR_HANDLER(cudaMalloc((void **)&d_M,size_M),__LINE__);
ERROR_HANDLER(cudaMalloc((void **)&d_N,size_N),__LINE__);
ERROR_HANDLER(cudaMalloc((void **)&d_P,size_P),__LINE__);
/************************************** Copy Matrices to the device ***********************************/
ERROR_HANDLER(cudaMemcpy(d_M,h_M,size_M,cudaMemcpyHostToDevice),__LINE__);
ERROR_HANDLER(cudaMemcpy(d_N,h_N,size_N,cudaMemcpyHostToDevice),__LINE__);
/************************************** Kernel invocation *********************************************/
dim3 threads(NUM_THREADS_X,NUM_THREADS_Y); /*2-D layout of the threads in a block */
dim3 blocks((COLS_N+NUM_THREADS_X-1)/NUM_THREADS_X,(ROWS_M+NUM_THREADS_Y-1)/NUM_THREADS_Y); /*2-D layout of blocks in a grid */
cudaEventRecord(start);
matrixMul<<<blocks,threads>>>(d_M,d_N,d_P,ROWS_M,COLS_N,COLS_M); /* The last parameter could have been <ROWS_N> */
cudaEventRecord(stop);
ERROR_HANDLER(cudaMemcpy(h_P,d_P,size_P,cudaMemcpyDeviceToHost),__LINE__);
cudaEventSynchronize(stop);
float run_time = 0.0;
cudaEventElapsedTime(&run_time,start,stop);
printf("Run-Time(seconds) : %.4f",run_time/1000);
print_matrix_to_file(h_P,ROWS_M,COLS_N);
/********************************** Free Allocated Memory ********************************************/
cudaFree(d_M);
cudaFree(d_N);
cudaFree(d_P);
free(h_M);
free(h_N);
free(h_P);
} | /* Program : To find the matrix multiplication of rectangular matrices using tiling
* Author : Anant Shah
* Date : 11-9-2018
* Roll Number : EE16B105
**/
#include <hip/hip_runtime.h>
#include<stdio.h>
#define ERROR_HANDLER(error_msg,line) error_handler(error_msg,line)
#define ROWS_M 8192
#define COLS_M 16384
#define ROWS_N 16384
#define COLS_N 32768
#define NUM_THREADS_X 32
#define NUM_THREADS_Y 32
#define TILE_WIDTH_X 32
#define TILE_WIDTH_Y 32
void error_handler(hipError_t error_msg,int line){
if(error_msg!=hipSuccess){
printf("%s in %s at %d",hipGetErrorString(error_msg),__FILE__,line);
exit(EXIT_FAILURE);
}
}
void fill_matrix(double *mat,unsigned numRows,unsigned numCols){
/* function to fill a mtrix with values */
for(unsigned i=0;i<numRows;i++){
for(unsigned j=0;j<numCols;j++){
mat[i*numCols+j] = i*2.1f + j*3.2f;
}
}
}
void print_matrix_to_file(double *mat,unsigned numRows,unsigned numCols){
/* function to print a matrix to a file */
const char *fname = "assignment2_out";
FILE *f = fopen(fname,"a");
for(unsigned i=0;i<numRows;i++){
for(unsigned j=0;j<numCols;j++){
fprintf(f,"%4.4f ", mat[i*numCols+j]);
}
fprintf(f,"\n");
}
fclose(f);
}
__global__ void matrixMul(double *M,double *N,double *P,int numRows_M,int numCols_N,int width){
/* Kernel function to calculate the matrix multiplication of rectangular matrices */
int tx = threadIdx.x; /* Thread-ID in the x-direction */
int ty = threadIdx.y; /* Thread-ID in the y-direction */
__shared__ double Ms[TILE_WIDTH_Y][TILE_WIDTH_X]; /* Shared memory to be used by threads in a block */
__shared__ double Ns[TILE_WIDTH_X][TILE_WIDTH_Y]; /* Shared memory to be used by therads in a block */
int row = blockIdx.y*blockDim.y + ty; /* row in the output matrix */
int col = blockIdx.x*blockDim.x + tx; /* column in the output matrix */
double pSum = 0.0;
for(int m=0;m<(width+NUM_THREADS_X-1)/NUM_THREADS_X;m++){
/* Load Pahse : Load elements cooperatively into the shared memeory */
Ms[ty][tx] = M[row*width+m*TILE_WIDTH_X+tx];
Ns[ty][tx] = N[(ty+m*TILE_WIDTH_Y)*numCols_N+col]; /* This is assuming that the tile is a sqaure */
__syncthreads();
for(int i=0;i<TILE_WIDTH_X;i++){
pSum += Ms[ty][i]*Ns[i][tx];
}
__syncthreads();
}
P[row*numCols_N+col] = pSum;
}
int main(int argc,char **argv){
if(argc!=1){
printf("error : Invalid number of arguments\n");
exit(EXIT_FAILURE);
}
if(COLS_M!=ROWS_N){
printf("Error : Invalid matrix dimensions");
exit(EXIT_FAILURE);
}
/************************************* Variable Initialization **************************************/
double *h_M; /*Rectangular matrix M on the host */
double *d_M; /*Rectangular matrix M on the device */
size_t size_M; /* Size of the rectangular matrix M in bytes */
double *h_N; /* Rectangular matrix N on the host */
double *d_N; /* Rectangular matrix N on the device */
size_t size_N; /* Size of the matrix N in bytes */
double *h_P; /* Product M*N on the host */
double *d_P; /* Product M*N on the device */
size_t size_P; /* Size of the matrix P in bytes */
hipEvent_t start,stop;
hipEventCreate(&start);
hipEventCreate(&stop);
size_M = sizeof(double)*ROWS_M*COLS_M;
size_N = sizeof(double)*ROWS_N*COLS_N;
size_P = sizeof(double)*ROWS_M*COLS_N;
/************************************** Memory Allocation on the Host ********************************/
h_M = (double *)malloc(size_M);
h_N = (double *)malloc(size_N);
h_P = (double *)malloc(size_P);
/************************************** Initialize the matrices ***************************************/
fill_matrix(h_M,ROWS_M,COLS_M);
fill_matrix(h_N,ROWS_N,COLS_N);
/************************************** Allocate memory on the device *********************************/
ERROR_HANDLER(hipMalloc((void **)&d_M,size_M),__LINE__);
ERROR_HANDLER(hipMalloc((void **)&d_N,size_N),__LINE__);
ERROR_HANDLER(hipMalloc((void **)&d_P,size_P),__LINE__);
/************************************** Copy Matrices to the device ***********************************/
ERROR_HANDLER(hipMemcpy(d_M,h_M,size_M,hipMemcpyHostToDevice),__LINE__);
ERROR_HANDLER(hipMemcpy(d_N,h_N,size_N,hipMemcpyHostToDevice),__LINE__);
/************************************** Kernel invocation *********************************************/
dim3 threads(NUM_THREADS_X,NUM_THREADS_Y); /*2-D layout of the threads in a block */
dim3 blocks((COLS_N+NUM_THREADS_X-1)/NUM_THREADS_X,(ROWS_M+NUM_THREADS_Y-1)/NUM_THREADS_Y); /*2-D layout of blocks in a grid */
hipEventRecord(start);
matrixMul<<<blocks,threads>>>(d_M,d_N,d_P,ROWS_M,COLS_N,COLS_M); /* The last parameter could have been <ROWS_N> */
hipEventRecord(stop);
ERROR_HANDLER(hipMemcpy(h_P,d_P,size_P,hipMemcpyDeviceToHost),__LINE__);
hipEventSynchronize(stop);
float run_time = 0.0;
hipEventElapsedTime(&run_time,start,stop);
printf("Run-Time(seconds) : %.4f",run_time/1000);
print_matrix_to_file(h_P,ROWS_M,COLS_N);
/********************************** Free Allocated Memory ********************************************/
hipFree(d_M);
hipFree(d_N);
hipFree(d_P);
free(h_M);
free(h_N);
free(h_P);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | /* Program : To find the matrix multiplication of rectangular matrices using tiling
* Author : Anant Shah
* Date : 11-9-2018
* Roll Number : EE16B105
**/
#include <hip/hip_runtime.h>
#include<stdio.h>
#define ERROR_HANDLER(error_msg,line) error_handler(error_msg,line)
#define ROWS_M 8192
#define COLS_M 16384
#define ROWS_N 16384
#define COLS_N 32768
#define NUM_THREADS_X 32
#define NUM_THREADS_Y 32
#define TILE_WIDTH_X 32
#define TILE_WIDTH_Y 32
void error_handler(hipError_t error_msg,int line){
if(error_msg!=hipSuccess){
printf("%s in %s at %d",hipGetErrorString(error_msg),__FILE__,line);
exit(EXIT_FAILURE);
}
}
void fill_matrix(double *mat,unsigned numRows,unsigned numCols){
/* function to fill a mtrix with values */
for(unsigned i=0;i<numRows;i++){
for(unsigned j=0;j<numCols;j++){
mat[i*numCols+j] = i*2.1f + j*3.2f;
}
}
}
void print_matrix_to_file(double *mat,unsigned numRows,unsigned numCols){
/* function to print a matrix to a file */
const char *fname = "assignment2_out";
FILE *f = fopen(fname,"a");
for(unsigned i=0;i<numRows;i++){
for(unsigned j=0;j<numCols;j++){
fprintf(f,"%4.4f ", mat[i*numCols+j]);
}
fprintf(f,"\n");
}
fclose(f);
}
__global__ void matrixMul(double *M,double *N,double *P,int numRows_M,int numCols_N,int width){
/* Kernel function to calculate the matrix multiplication of rectangular matrices */
int tx = threadIdx.x; /* Thread-ID in the x-direction */
int ty = threadIdx.y; /* Thread-ID in the y-direction */
__shared__ double Ms[TILE_WIDTH_Y][TILE_WIDTH_X]; /* Shared memory to be used by threads in a block */
__shared__ double Ns[TILE_WIDTH_X][TILE_WIDTH_Y]; /* Shared memory to be used by therads in a block */
int row = blockIdx.y*blockDim.y + ty; /* row in the output matrix */
int col = blockIdx.x*blockDim.x + tx; /* column in the output matrix */
double pSum = 0.0;
for(int m=0;m<(width+NUM_THREADS_X-1)/NUM_THREADS_X;m++){
/* Load Pahse : Load elements cooperatively into the shared memeory */
Ms[ty][tx] = M[row*width+m*TILE_WIDTH_X+tx];
Ns[ty][tx] = N[(ty+m*TILE_WIDTH_Y)*numCols_N+col]; /* This is assuming that the tile is a sqaure */
__syncthreads();
for(int i=0;i<TILE_WIDTH_X;i++){
pSum += Ms[ty][i]*Ns[i][tx];
}
__syncthreads();
}
P[row*numCols_N+col] = pSum;
}
int main(int argc,char **argv){
if(argc!=1){
printf("error : Invalid number of arguments\n");
exit(EXIT_FAILURE);
}
if(COLS_M!=ROWS_N){
printf("Error : Invalid matrix dimensions");
exit(EXIT_FAILURE);
}
/************************************* Variable Initialization **************************************/
double *h_M; /*Rectangular matrix M on the host */
double *d_M; /*Rectangular matrix M on the device */
size_t size_M; /* Size of the rectangular matrix M in bytes */
double *h_N; /* Rectangular matrix N on the host */
double *d_N; /* Rectangular matrix N on the device */
size_t size_N; /* Size of the matrix N in bytes */
double *h_P; /* Product M*N on the host */
double *d_P; /* Product M*N on the device */
size_t size_P; /* Size of the matrix P in bytes */
hipEvent_t start,stop;
hipEventCreate(&start);
hipEventCreate(&stop);
size_M = sizeof(double)*ROWS_M*COLS_M;
size_N = sizeof(double)*ROWS_N*COLS_N;
size_P = sizeof(double)*ROWS_M*COLS_N;
/************************************** Memory Allocation on the Host ********************************/
h_M = (double *)malloc(size_M);
h_N = (double *)malloc(size_N);
h_P = (double *)malloc(size_P);
/************************************** Initialize the matrices ***************************************/
fill_matrix(h_M,ROWS_M,COLS_M);
fill_matrix(h_N,ROWS_N,COLS_N);
/************************************** Allocate memory on the device *********************************/
ERROR_HANDLER(hipMalloc((void **)&d_M,size_M),__LINE__);
ERROR_HANDLER(hipMalloc((void **)&d_N,size_N),__LINE__);
ERROR_HANDLER(hipMalloc((void **)&d_P,size_P),__LINE__);
/************************************** Copy Matrices to the device ***********************************/
ERROR_HANDLER(hipMemcpy(d_M,h_M,size_M,hipMemcpyHostToDevice),__LINE__);
ERROR_HANDLER(hipMemcpy(d_N,h_N,size_N,hipMemcpyHostToDevice),__LINE__);
/************************************** Kernel invocation *********************************************/
dim3 threads(NUM_THREADS_X,NUM_THREADS_Y); /*2-D layout of the threads in a block */
dim3 blocks((COLS_N+NUM_THREADS_X-1)/NUM_THREADS_X,(ROWS_M+NUM_THREADS_Y-1)/NUM_THREADS_Y); /*2-D layout of blocks in a grid */
hipEventRecord(start);
matrixMul<<<blocks,threads>>>(d_M,d_N,d_P,ROWS_M,COLS_N,COLS_M); /* The last parameter could have been <ROWS_N> */
hipEventRecord(stop);
ERROR_HANDLER(hipMemcpy(h_P,d_P,size_P,hipMemcpyDeviceToHost),__LINE__);
hipEventSynchronize(stop);
float run_time = 0.0;
hipEventElapsedTime(&run_time,start,stop);
printf("Run-Time(seconds) : %.4f",run_time/1000);
print_matrix_to_file(h_P,ROWS_M,COLS_N);
/********************************** Free Allocated Memory ********************************************/
hipFree(d_M);
hipFree(d_N);
hipFree(d_P);
free(h_M);
free(h_N);
free(h_P);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9matrixMulPdS_S_iii
.globl _Z9matrixMulPdS_S_iii
.p2align 8
.type _Z9matrixMulPdS_S_iii,@function
_Z9matrixMulPdS_S_iii:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x34
s_load_b64 s[2:3], s[0:1], 0x1c
v_bfe_u32 v3, v0, 10, 10
v_and_b32_e32 v4, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s5, s4, 16
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(VALU_DEP_1)
v_mad_u64_u32 v[0:1], null, s15, s5, v[3:4]
v_mad_u64_u32 v[1:2], null, s14, s4, v[4:5]
s_cmp_lt_i32 s3, 1
s_cbranch_scc1 .LBB0_5
s_load_b128 s[4:7], s[0:1], 0x0
v_lshlrev_b32_e32 v5, 3, v4
v_lshlrev_b32_e32 v2, 8, v3
s_add_i32 s8, s3, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
s_lshr_b32 s8, s8, 5
v_or_b32_e32 v8, 0x2000, v5
v_mad_u64_u32 v[6:7], null, v0, s3, v[4:5]
v_dual_mov_b32 v4, 0 :: v_dual_add_nc_u32 v7, v2, v5
v_mov_b32_e32 v5, 0
s_delay_alu instid0(VALU_DEP_4)
v_add_nc_u32_e32 v9, v8, v2
s_max_i32 s3, s8, 1
s_mov_b32 s8, 0
s_set_inst_prefetch_distance 0x1
.p2align 6
.LBB0_2:
s_lshl_b32 s9, s8, 5
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v11, s9, v3
v_add_nc_u32_e32 v10, s9, v6
s_mov_b32 s9, 0
v_mad_u64_u32 v[12:13], null, v11, s2, v[1:2]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v11, 31, v10
v_lshlrev_b64 v[10:11], 3, v[10:11]
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v13, 31, v12
s_waitcnt lgkmcnt(0)
v_add_co_u32 v10, vcc_lo, s4, v10
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_lshlrev_b64 v[12:13], 3, v[12:13]
v_add_co_ci_u32_e32 v11, vcc_lo, s5, v11, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v12, vcc_lo, s6, v12
v_add_co_ci_u32_e32 v13, vcc_lo, s7, v13, vcc_lo
global_load_b64 v[14:15], v[10:11], off
global_load_b64 v[11:12], v[12:13], off
v_mov_b32_e32 v10, v8
s_waitcnt vmcnt(1)
ds_store_b64 v7, v[14:15]
s_waitcnt vmcnt(0)
ds_store_b64 v9, v[11:12]
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
.LBB0_3:
v_add_nc_u32_e32 v13, s9, v2
s_add_i32 s9, s9, 8
ds_load_b64 v[11:12], v10
ds_load_b64 v[13:14], v13
v_add_nc_u32_e32 v10, 0x100, v10
s_cmpk_eq_i32 s9, 0x100
s_waitcnt lgkmcnt(0)
v_fma_f64 v[4:5], v[13:14], v[11:12], v[4:5]
s_cbranch_scc0 .LBB0_3
s_add_i32 s8, s8, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s8, s3
s_barrier
buffer_gl0_inv
s_cbranch_scc0 .LBB0_2
s_branch .LBB0_6
.LBB0_5:
v_mov_b32_e32 v4, 0
v_mov_b32_e32 v5, 0
.LBB0_6:
s_set_inst_prefetch_distance 0x2
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, v0, s2, v[1:2]
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 3, v[2:3]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b64 v[0:1], v[4:5], off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9matrixMulPdS_S_iii
.amdhsa_group_segment_fixed_size 16384
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 16
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9matrixMulPdS_S_iii, .Lfunc_end0-_Z9matrixMulPdS_S_iii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 16384
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9matrixMulPdS_S_iii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9matrixMulPdS_S_iii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 16
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | /* Program : To find the matrix multiplication of rectangular matrices using tiling
* Author : Anant Shah
* Date : 11-9-2018
* Roll Number : EE16B105
**/
#include <hip/hip_runtime.h>
#include<stdio.h>
#define ERROR_HANDLER(error_msg,line) error_handler(error_msg,line)
#define ROWS_M 8192
#define COLS_M 16384
#define ROWS_N 16384
#define COLS_N 32768
#define NUM_THREADS_X 32
#define NUM_THREADS_Y 32
#define TILE_WIDTH_X 32
#define TILE_WIDTH_Y 32
void error_handler(hipError_t error_msg,int line){
if(error_msg!=hipSuccess){
printf("%s in %s at %d",hipGetErrorString(error_msg),__FILE__,line);
exit(EXIT_FAILURE);
}
}
void fill_matrix(double *mat,unsigned numRows,unsigned numCols){
/* function to fill a mtrix with values */
for(unsigned i=0;i<numRows;i++){
for(unsigned j=0;j<numCols;j++){
mat[i*numCols+j] = i*2.1f + j*3.2f;
}
}
}
void print_matrix_to_file(double *mat,unsigned numRows,unsigned numCols){
/* function to print a matrix to a file */
const char *fname = "assignment2_out";
FILE *f = fopen(fname,"a");
for(unsigned i=0;i<numRows;i++){
for(unsigned j=0;j<numCols;j++){
fprintf(f,"%4.4f ", mat[i*numCols+j]);
}
fprintf(f,"\n");
}
fclose(f);
}
__global__ void matrixMul(double *M,double *N,double *P,int numRows_M,int numCols_N,int width){
/* Kernel function to calculate the matrix multiplication of rectangular matrices */
int tx = threadIdx.x; /* Thread-ID in the x-direction */
int ty = threadIdx.y; /* Thread-ID in the y-direction */
__shared__ double Ms[TILE_WIDTH_Y][TILE_WIDTH_X]; /* Shared memory to be used by threads in a block */
__shared__ double Ns[TILE_WIDTH_X][TILE_WIDTH_Y]; /* Shared memory to be used by therads in a block */
int row = blockIdx.y*blockDim.y + ty; /* row in the output matrix */
int col = blockIdx.x*blockDim.x + tx; /* column in the output matrix */
double pSum = 0.0;
for(int m=0;m<(width+NUM_THREADS_X-1)/NUM_THREADS_X;m++){
/* Load Pahse : Load elements cooperatively into the shared memeory */
Ms[ty][tx] = M[row*width+m*TILE_WIDTH_X+tx];
Ns[ty][tx] = N[(ty+m*TILE_WIDTH_Y)*numCols_N+col]; /* This is assuming that the tile is a sqaure */
__syncthreads();
for(int i=0;i<TILE_WIDTH_X;i++){
pSum += Ms[ty][i]*Ns[i][tx];
}
__syncthreads();
}
P[row*numCols_N+col] = pSum;
}
int main(int argc,char **argv){
if(argc!=1){
printf("error : Invalid number of arguments\n");
exit(EXIT_FAILURE);
}
if(COLS_M!=ROWS_N){
printf("Error : Invalid matrix dimensions");
exit(EXIT_FAILURE);
}
/************************************* Variable Initialization **************************************/
double *h_M; /*Rectangular matrix M on the host */
double *d_M; /*Rectangular matrix M on the device */
size_t size_M; /* Size of the rectangular matrix M in bytes */
double *h_N; /* Rectangular matrix N on the host */
double *d_N; /* Rectangular matrix N on the device */
size_t size_N; /* Size of the matrix N in bytes */
double *h_P; /* Product M*N on the host */
double *d_P; /* Product M*N on the device */
size_t size_P; /* Size of the matrix P in bytes */
hipEvent_t start,stop;
hipEventCreate(&start);
hipEventCreate(&stop);
size_M = sizeof(double)*ROWS_M*COLS_M;
size_N = sizeof(double)*ROWS_N*COLS_N;
size_P = sizeof(double)*ROWS_M*COLS_N;
/************************************** Memory Allocation on the Host ********************************/
h_M = (double *)malloc(size_M);
h_N = (double *)malloc(size_N);
h_P = (double *)malloc(size_P);
/************************************** Initialize the matrices ***************************************/
fill_matrix(h_M,ROWS_M,COLS_M);
fill_matrix(h_N,ROWS_N,COLS_N);
/************************************** Allocate memory on the device *********************************/
ERROR_HANDLER(hipMalloc((void **)&d_M,size_M),__LINE__);
ERROR_HANDLER(hipMalloc((void **)&d_N,size_N),__LINE__);
ERROR_HANDLER(hipMalloc((void **)&d_P,size_P),__LINE__);
/************************************** Copy Matrices to the device ***********************************/
ERROR_HANDLER(hipMemcpy(d_M,h_M,size_M,hipMemcpyHostToDevice),__LINE__);
ERROR_HANDLER(hipMemcpy(d_N,h_N,size_N,hipMemcpyHostToDevice),__LINE__);
/************************************** Kernel invocation *********************************************/
dim3 threads(NUM_THREADS_X,NUM_THREADS_Y); /*2-D layout of the threads in a block */
dim3 blocks((COLS_N+NUM_THREADS_X-1)/NUM_THREADS_X,(ROWS_M+NUM_THREADS_Y-1)/NUM_THREADS_Y); /*2-D layout of blocks in a grid */
hipEventRecord(start);
matrixMul<<<blocks,threads>>>(d_M,d_N,d_P,ROWS_M,COLS_N,COLS_M); /* The last parameter could have been <ROWS_N> */
hipEventRecord(stop);
ERROR_HANDLER(hipMemcpy(h_P,d_P,size_P,hipMemcpyDeviceToHost),__LINE__);
hipEventSynchronize(stop);
float run_time = 0.0;
hipEventElapsedTime(&run_time,start,stop);
printf("Run-Time(seconds) : %.4f",run_time/1000);
print_matrix_to_file(h_P,ROWS_M,COLS_N);
/********************************** Free Allocated Memory ********************************************/
hipFree(d_M);
hipFree(d_N);
hipFree(d_P);
free(h_M);
free(h_N);
free(h_P);
} | .text
.file "ee16b105_7.hip"
.globl _Z13error_handler10hipError_ti # -- Begin function _Z13error_handler10hipError_ti
.p2align 4, 0x90
.type _Z13error_handler10hipError_ti,@function
_Z13error_handler10hipError_ti: # @_Z13error_handler10hipError_ti
.cfi_startproc
# %bb.0:
testl %edi, %edi
jne .LBB0_2
# %bb.1:
retq
.LBB0_2:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
movl %esi, %ebx
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.1, %edx
movq %rax, %rsi
movl %ebx, %ecx
xorl %eax, %eax
callq printf
movl $1, %edi
callq exit
.Lfunc_end0:
.size _Z13error_handler10hipError_ti, .Lfunc_end0-_Z13error_handler10hipError_ti
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z11fill_matrixPdjj
.LCPI1_0:
.long 0x40066666 # float 2.0999999
.LCPI1_1:
.long 0x404ccccd # float 3.20000005
.text
.globl _Z11fill_matrixPdjj
.p2align 4, 0x90
.type _Z11fill_matrixPdjj,@function
_Z11fill_matrixPdjj: # @_Z11fill_matrixPdjj
.cfi_startproc
# %bb.0:
testl %esi, %esi
je .LBB1_6
# %bb.1: # %.preheader.lr.ph
movl %edx, %eax
xorl %ecx, %ecx
movss .LCPI1_0(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
movss .LCPI1_1(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
xorl %r8d, %r8d
jmp .LBB1_2
.p2align 4, 0x90
.LBB1_5: # %._crit_edge
# in Loop: Header=BB1_2 Depth=1
incl %r8d
addq %rax, %rcx
cmpl %esi, %r8d
je .LBB1_6
.LBB1_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_4 Depth 2
testl %edx, %edx
je .LBB1_5
# %bb.3: # %.lr.ph
# in Loop: Header=BB1_2 Depth=1
movl %r8d, %r9d
xorps %xmm2, %xmm2
cvtsi2ss %r9, %xmm2
mulss %xmm0, %xmm2
xorl %r9d, %r9d
.p2align 4, 0x90
.LBB1_4: # Parent Loop BB1_2 Depth=1
# => This Inner Loop Header: Depth=2
movl %r9d, %r10d
xorps %xmm3, %xmm3
cvtsi2ss %r10, %xmm3
mulss %xmm1, %xmm3
addss %xmm2, %xmm3
cvtss2sd %xmm3, %xmm3
leal (%rcx,%r9), %r10d
movsd %xmm3, (%rdi,%r10,8)
incq %r9
cmpq %r9, %rax
jne .LBB1_4
jmp .LBB1_5
.LBB1_6: # %._crit_edge15
retq
.Lfunc_end1:
.size _Z11fill_matrixPdjj, .Lfunc_end1-_Z11fill_matrixPdjj
.cfi_endproc
# -- End function
.globl _Z20print_matrix_to_filePdjj # -- Begin function _Z20print_matrix_to_filePdjj
.p2align 4, 0x90
.type _Z20print_matrix_to_filePdjj,@function
_Z20print_matrix_to_filePdjj: # @_Z20print_matrix_to_filePdjj
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $24, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %edx, %ebx
movl %esi, %ebp
movq %rdi, %r14
movl $.L.str.2, %edi
movl $.L.str.3, %esi
callq fopen
movq %rax, %r15
movl %ebp, 12(%rsp) # 4-byte Spill
testl %ebp, %ebp
je .LBB2_4
# %bb.1: # %.preheader.lr.ph
movl %ebx, %ecx
movl %ebx, %eax
movq %rax, 16(%rsp) # 8-byte Spill
xorl %ebx, %ebx
xorl %ebp, %ebp
movl %ecx, 8(%rsp) # 4-byte Spill
jmp .LBB2_2
.p2align 4, 0x90
.LBB2_3: # %._crit_edge
# in Loop: Header=BB2_2 Depth=1
movl $10, %edi
movq %r15, %rsi
callq fputc@PLT
incl %ebp
movl 8(%rsp), %ecx # 4-byte Reload
addl %ecx, %ebx
cmpl 12(%rsp), %ebp # 4-byte Folded Reload
je .LBB2_4
.LBB2_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB2_5 Depth 2
movq 16(%rsp), %r12 # 8-byte Reload
movl %ebx, %r13d
testl %ecx, %ecx
je .LBB2_3
.p2align 4, 0x90
.LBB2_5: # Parent Loop BB2_2 Depth=1
# => This Inner Loop Header: Depth=2
movl %r13d, %eax
movsd (%r14,%rax,8), %xmm0 # xmm0 = mem[0],zero
movl $.L.str.4, %esi
movq %r15, %rdi
movb $1, %al
callq fprintf
incl %r13d
decq %r12
jne .LBB2_5
jmp .LBB2_3
.LBB2_4: # %._crit_edge17
movq %r15, %rdi
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
jmp fclose # TAILCALL
.Lfunc_end2:
.size _Z20print_matrix_to_filePdjj, .Lfunc_end2-_Z20print_matrix_to_filePdjj
.cfi_endproc
# -- End function
.globl _Z24__device_stub__matrixMulPdS_S_iii # -- Begin function _Z24__device_stub__matrixMulPdS_S_iii
.p2align 4, 0x90
.type _Z24__device_stub__matrixMulPdS_S_iii,@function
_Z24__device_stub__matrixMulPdS_S_iii: # @_Z24__device_stub__matrixMulPdS_S_iii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z9matrixMulPdS_S_iii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end3:
.size _Z24__device_stub__matrixMulPdS_S_iii, .Lfunc_end3-_Z24__device_stub__matrixMulPdS_S_iii
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI4_0:
.long 0x40066666 # float 2.0999999
.LCPI4_1:
.long 0x404ccccd # float 3.20000005
.LCPI4_2:
.long 0x447a0000 # float 1000
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $200, %rsp
.cfi_def_cfa_offset 256
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
cmpl $1, %edi
jne .LBB4_29
# %bb.1:
movabsq $4294967296, %r12 # imm = 0x100000000
leaq 56(%rsp), %rdi
callq hipEventCreate
leaq 8(%rsp), %rdi
callq hipEventCreate
movl $1073741824, %edi # imm = 0x40000000
callq malloc
movq %rax, %rbx
movq %r12, %rdi
callq malloc
movq %rax, %r14
movl $2147483648, %edi # imm = 0x80000000
callq malloc
movq %rax, %r15
xorl %eax, %eax
movss .LCPI4_0(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
movss .LCPI4_1(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
movq %rbx, %rcx
.p2align 4, 0x90
.LBB4_2: # %.preheader.i
# =>This Loop Header: Depth=1
# Child Loop BB4_3 Depth 2
movl %eax, %edx
xorps %xmm2, %xmm2
cvtsi2ss %rdx, %xmm2
mulss %xmm0, %xmm2
xorl %edx, %edx
.p2align 4, 0x90
.LBB4_3: # Parent Loop BB4_2 Depth=1
# => This Inner Loop Header: Depth=2
movl %edx, %esi
xorps %xmm3, %xmm3
cvtsi2ss %rsi, %xmm3
mulss %xmm1, %xmm3
addss %xmm2, %xmm3
cvtss2sd %xmm3, %xmm3
movsd %xmm3, (%rcx,%rdx,8)
incq %rdx
cmpq $16384, %rdx # imm = 0x4000
jne .LBB4_3
# %bb.4: # %._crit_edge.i
# in Loop: Header=BB4_2 Depth=1
incl %eax
addq $131072, %rcx # imm = 0x20000
cmpl $8192, %eax # imm = 0x2000
jne .LBB4_2
# %bb.5: # %.preheader.i26.preheader
xorl %eax, %eax
movq %r14, %rcx
.p2align 4, 0x90
.LBB4_6: # %.preheader.i26
# =>This Loop Header: Depth=1
# Child Loop BB4_7 Depth 2
movl %eax, %edx
xorps %xmm2, %xmm2
cvtsi2ss %rdx, %xmm2
mulss %xmm0, %xmm2
xorl %edx, %edx
.p2align 4, 0x90
.LBB4_7: # Parent Loop BB4_6 Depth=1
# => This Inner Loop Header: Depth=2
movl %edx, %esi
xorps %xmm3, %xmm3
cvtsi2ss %rsi, %xmm3
mulss %xmm1, %xmm3
addss %xmm2, %xmm3
cvtss2sd %xmm3, %xmm3
movsd %xmm3, (%rcx,%rdx,8)
incq %rdx
cmpq $32768, %rdx # imm = 0x8000
jne .LBB4_7
# %bb.8: # %._crit_edge.i31
# in Loop: Header=BB4_6 Depth=1
incl %eax
addq $262144, %rcx # imm = 0x40000
cmpl $16384, %eax # imm = 0x4000
jne .LBB4_6
# %bb.9: # %_Z11fill_matrixPdjj.exit33
leaq 32(%rsp), %rdi
movl $1073741824, %esi # imm = 0x40000000
callq hipMalloc
testl %eax, %eax
jne .LBB4_10
# %bb.12: # %_Z13error_handler10hipError_ti.exit
leaq 24(%rsp), %rdi
movq %r12, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB4_13
# %bb.14: # %_Z13error_handler10hipError_ti.exit35
leaq 16(%rsp), %rdi
movl $2147483648, %esi # imm = 0x80000000
callq hipMalloc
testl %eax, %eax
jne .LBB4_15
# %bb.16: # %_Z13error_handler10hipError_ti.exit37
movq 32(%rsp), %rdi
movl $1073741824, %edx # imm = 0x40000000
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB4_17
# %bb.18: # %_Z13error_handler10hipError_ti.exit39
movq 24(%rsp), %rdi
movq %r14, %rsi
movq %r12, %rdx
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB4_19
# %bb.20: # %_Z13error_handler10hipError_ti.exit41
movq %rbx, 64(%rsp) # 8-byte Spill
movq 56(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movabsq $1099511628800, %rdi # imm = 0x10000000400
movabsq $137438953504, %rdx # imm = 0x2000000020
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_22
# %bb.21:
movq 32(%rsp), %rax
movq 24(%rsp), %rcx
movq 16(%rsp), %rdx
movq %rax, 136(%rsp)
movq %rcx, 128(%rsp)
movq %rdx, 120(%rsp)
movl $8192, 52(%rsp) # imm = 0x2000
movl $32768, 48(%rsp) # imm = 0x8000
movl $16384, 44(%rsp) # imm = 0x4000
leaq 136(%rsp), %rax
movq %rax, 144(%rsp)
leaq 128(%rsp), %rax
movq %rax, 152(%rsp)
leaq 120(%rsp), %rax
movq %rax, 160(%rsp)
leaq 52(%rsp), %rax
movq %rax, 168(%rsp)
leaq 48(%rsp), %rax
movq %rax, 176(%rsp)
leaq 44(%rsp), %rax
movq %rax, 184(%rsp)
leaq 104(%rsp), %rdi
leaq 88(%rsp), %rsi
leaq 80(%rsp), %rdx
leaq 72(%rsp), %rcx
callq __hipPopCallConfiguration
movq 104(%rsp), %rsi
movl 112(%rsp), %edx
movq 88(%rsp), %rcx
movl 96(%rsp), %r8d
leaq 144(%rsp), %r9
movl $_Z9matrixMulPdS_S_iii, %edi
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
pushq 88(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_22:
movq 8(%rsp), %rdi
xorl %r13d, %r13d
xorl %esi, %esi
callq hipEventRecord
movq 16(%rsp), %rsi
movl $2147483648, %edx # imm = 0x80000000
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB4_23
# %bb.24: # %_Z13error_handler10hipError_ti.exit43
movq 8(%rsp), %rdi
callq hipEventSynchronize
movl $0, 144(%rsp)
movq 56(%rsp), %rsi
movq 8(%rsp), %rdx
leaq 144(%rsp), %rdi
callq hipEventElapsedTime
movss 144(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
divss .LCPI4_2(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movl $.L.str.7, %edi
movb $1, %al
callq printf
movl $.L.str.2, %edi
movl $.L.str.3, %esi
callq fopen
movq %rax, %r12
movq %r15, %rbp
.p2align 4, 0x90
.LBB4_25: # %.preheader.i44
# =>This Loop Header: Depth=1
# Child Loop BB4_26 Depth 2
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB4_26: # Parent Loop BB4_25 Depth=1
# => This Inner Loop Header: Depth=2
movsd (%rbp,%rbx,8), %xmm0 # xmm0 = mem[0],zero
movl $.L.str.4, %esi
movq %r12, %rdi
movb $1, %al
callq fprintf
incq %rbx
cmpq $32768, %rbx # imm = 0x8000
jne .LBB4_26
# %bb.27: # %._crit_edge.i48
# in Loop: Header=BB4_25 Depth=1
movl $10, %edi
movq %r12, %rsi
callq fputc@PLT
incl %r13d
addq $262144, %rbp # imm = 0x40000
cmpl $8192, %r13d # imm = 0x2000
jne .LBB4_25
# %bb.28: # %_Z20print_matrix_to_filePdjj.exit
movq %r12, %rdi
callq fclose
movq 32(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 64(%rsp), %rdi # 8-byte Reload
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
xorl %eax, %eax
addq $200, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB4_29:
.cfi_def_cfa_offset 256
movl $.Lstr, %edi
callq puts@PLT
movl $1, %edi
callq exit
.LBB4_10:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.1, %edx
movq %rax, %rsi
movl $118, %ecx
jmp .LBB4_11
.LBB4_13:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.1, %edx
movq %rax, %rsi
movl $119, %ecx
jmp .LBB4_11
.LBB4_15:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.1, %edx
movq %rax, %rsi
movl $120, %ecx
jmp .LBB4_11
.LBB4_17:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.1, %edx
movq %rax, %rsi
movl $124, %ecx
jmp .LBB4_11
.LBB4_19:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.1, %edx
movq %rax, %rsi
movl $125, %ecx
jmp .LBB4_11
.LBB4_23:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.1, %edx
movq %rax, %rsi
movl $136, %ecx
.LBB4_11:
xorl %eax, %eax
callq printf
movl $1, %edi
callq exit
.Lfunc_end4:
.size main, .Lfunc_end4-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9matrixMulPdS_S_iii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%s in %s at %d"
.size .L.str, 15
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/anantshah200/CS6023/master/Assignment2/ee16b105_7.hip"
.size .L.str.1, 111
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "assignment2_out"
.size .L.str.2, 16
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "a"
.size .L.str.3, 2
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "%4.4f "
.size .L.str.4, 7
.type _Z9matrixMulPdS_S_iii,@object # @_Z9matrixMulPdS_S_iii
.section .rodata,"a",@progbits
.globl _Z9matrixMulPdS_S_iii
.p2align 3, 0x0
_Z9matrixMulPdS_S_iii:
.quad _Z24__device_stub__matrixMulPdS_S_iii
.size _Z9matrixMulPdS_S_iii, 8
.type .L.str.7,@object # @.str.7
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.7:
.asciz "Run-Time(seconds) : %.4f"
.size .L.str.7, 25
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z9matrixMulPdS_S_iii"
.size .L__unnamed_1, 22
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "error : Invalid number of arguments"
.size .Lstr, 36
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__matrixMulPdS_S_iii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9matrixMulPdS_S_iii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z9matrixMulPdS_S_iii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e220000002600 */
/*0020*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x180] ; /* 0x00006000ff027624 */
/* 0x000fe200078e00ff */
/*0030*/ HFMA2.MMA R17, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff117435 */
/* 0x000fe200000001ff */
/*0040*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*0050*/ S2R R7, SR_TID.Y ; /* 0x0000000000077919 */
/* 0x000e220000002200 */
/*0060*/ CS2R R10, SRZ ; /* 0x00000000000a7805 */
/* 0x000fe2000001ff00 */
/*0070*/ ISETP.GE.AND P0, PT, R2, 0x1, PT ; /* 0x000000010200780c */
/* 0x000fe40003f06270 */
/*0080*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x000e680000002500 */
/*0090*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e620000002100 */
/*00a0*/ IMAD R3, R3, c[0x0][0x4], R7 ; /* 0x0000010003037a24 */
/* 0x001fc400078e0207 */
/*00b0*/ IMAD R4, R5, c[0x0][0x0], R0 ; /* 0x0000000005047a24 */
/* 0x002fc800078e0200 */
/*00c0*/ IMAD R16, R3, c[0x0][0x17c], R4 ; /* 0x00005f0003107a24 */
/* 0x000fc800078e0204 */
/*00d0*/ IMAD.WIDE R16, R16, R17, c[0x0][0x170] ; /* 0x00005c0010107625 */
/* 0x000fe200078e0211 */
/*00e0*/ @!P0 BRA 0x7d0 ; /* 0x000006e000008947 */
/* 0x000fea0003800000 */
/*00f0*/ IADD3 R5, R2, 0x1f, RZ ; /* 0x0000001f02057810 */
/* 0x000fe20007ffe0ff */
/*0100*/ IMAD.MOV.U32 R18, RZ, RZ, 0x8 ; /* 0x00000008ff127424 */
/* 0x000fe200078e00ff */
/*0110*/ CS2R R10, SRZ ; /* 0x00000000000a7805 */
/* 0x000fe2000001ff00 */
/*0120*/ IMAD R3, R3, c[0x0][0x180], R0 ; /* 0x0000600003037a24 */
/* 0x000fe200078e0200 */
/*0130*/ SHF.R.S32.HI R6, RZ, 0x1f, R5 ; /* 0x0000001fff067819 */
/* 0x000fe20000011405 */
/*0140*/ IMAD R4, R7.reuse, c[0x0][0x17c], R4 ; /* 0x00005f0007047a24 */
/* 0x040fe200078e0204 */
/*0150*/ SHF.L.U32 R7, R7, 0x8, RZ ; /* 0x0000000807077819 */
/* 0x000fe200000006ff */
/*0160*/ IMAD.WIDE R2, R3, R18.reuse, c[0x0][0x160] ; /* 0x0000580003027625 */
/* 0x080fe200078e0212 */
/*0170*/ LEA.HI R8, R6, R5, RZ, 0x5 ; /* 0x0000000506087211 */
/* 0x000fe200078f28ff */
/*0180*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*0190*/ LEA R6, R0, R7, 0x3 ; /* 0x0000000700067211 */
/* 0x000fe200078e18ff */
/*01a0*/ IMAD.WIDE R18, R4, R18, c[0x0][0x168] ; /* 0x00005a0004127625 */
/* 0x000fe200078e0212 */
/*01b0*/ MOV R5, R3 ; /* 0x0000000300057202 */
/* 0x000fc60000000f00 */
/*01c0*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x17c] ; /* 0x00005f00ff037624 */
/* 0x000fc800078e00ff */
/*01d0*/ IMAD.SHL.U32 R4, R3, 0x20, RZ ; /* 0x0000002003047824 */
/* 0x000fe200078e00ff */
/*01e0*/ SHF.R.S32.HI R3, RZ, 0x5, R8 ; /* 0x00000005ff037819 */
/* 0x000fe40000011408 */
/*01f0*/ IMAD.MOV.U32 R26, RZ, RZ, R2 ; /* 0x000000ffff1a7224 */
/* 0x000fe200078e0002 */
/*0200*/ MOV R27, R5 ; /* 0x00000005001b7202 */
/* 0x000fe20000000f00 */
/*0210*/ LDG.E.64 R24, [R18.64] ; /* 0x0000000612187981 */
/* 0x0000aa000c1e1b00 */
/*0220*/ LDG.E.64 R26, [R26.64] ; /* 0x000000061a1a7981 */
/* 0x000ee2000c1e1b00 */
/*0230*/ UIADD3 UR4, UR4, 0x1, URZ ; /* 0x0000000104047890 */
/* 0x000fe2000fffe03f */
/*0240*/ IADD3 R2, P1, R2, 0x100, RZ ; /* 0x0000010002027810 */
/* 0x000fe20007f3e0ff */
/*0250*/ IMAD.WIDE R18, R4, 0x8, R18 ; /* 0x0000000804127825 */
/* 0x001fc600078e0212 */
/*0260*/ IADD3.X R5, RZ, R5, RZ, P1, !PT ; /* 0x00000005ff057210 */
/* 0x000fe40000ffe4ff */
/*0270*/ ISETP.LE.AND P0, PT, R3, UR4, PT ; /* 0x0000000403007c0c */
/* 0x000fe2000bf03270 */
/*0280*/ STS.64 [R6+0x2000], R24 ; /* 0x0020001806007388 */
/* 0x004fe80000000a00 */
/*0290*/ STS.64 [R6], R26 ; /* 0x0000001a06007388 */
/* 0x008fe80000000a00 */
/*02a0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*02b0*/ LDS.64 R8, [R0.X8+0x2000] ; /* 0x0020000000087984 */
/* 0x000fe80000008a00 */
/*02c0*/ LDS.128 R12, [R7] ; /* 0x00000000070c7984 */
/* 0x000e280000000c00 */
/*02d0*/ LDS.64 R20, [R0.X8+0x2100] ; /* 0x0021000000147984 */
/* 0x000e680000008a00 */
/*02e0*/ LDS.64 R22, [R0.X8+0x2200] ; /* 0x0022000000167984 */
/* 0x000fe80000008a00 */
/*02f0*/ LDS.64 R24, [R0.X8+0x2400] ; /* 0x0024000000187984 */
/* 0x000fe20000008a00 */
/*0300*/ DFMA R12, R8, R12, R10 ; /* 0x0000000c080c722b */
/* 0x001046000000000a */
/*0310*/ LDS.128 R8, [R7+0x10] ; /* 0x0000100007087984 */
/* 0x001e260000000c00 */
/*0320*/ DFMA R14, R20, R14, R12 ; /* 0x0000000e140e722b */
/* 0x002224000000000c */
/*0330*/ LDS.64 R20, [R0.X8+0x2300] ; /* 0x0023000000147984 */
/* 0x002e680000008a00 */
/*0340*/ DFMA R8, R22, R8, R14 ; /* 0x000000081608722b */
/* 0x001048000000000e */
/*0350*/ LDS.128 R12, [R7+0x20] ; /* 0x00002000070c7984 */
/* 0x001e240000000c00 */
/*0360*/ DFMA R10, R20, R10, R8 ; /* 0x0000000a140a722b */
/* 0x0022240000000008 */
/*0370*/ LDS.64 R22, [R0.X8+0x2600] ; /* 0x0026000000167984 */
/* 0x000fe80000008a00 */
/*0380*/ LDS.64 R20, [R0.X8+0x2500] ; /* 0x0025000000147984 */
/* 0x002e620000008a00 */
/*0390*/ DFMA R12, R24, R12, R10 ; /* 0x0000000c180c722b */
/* 0x001046000000000a */
/*03a0*/ LDS.128 R8, [R7+0x30] ; /* 0x0000300007087984 */
/* 0x001e280000000c00 */
/*03b0*/ LDS.64 R24, [R0.X8+0x2800] ; /* 0x0028000000187984 */
/* 0x000fe20000008a00 */
/*03c0*/ DFMA R14, R20, R14, R12 ; /* 0x0000000e140e722b */
/* 0x002206000000000c */
/*03d0*/ LDS.64 R20, [R0.X8+0x2700] ; /* 0x0027000000147984 */
/* 0x002e660000008a00 */
/*03e0*/ DFMA R8, R22, R8, R14 ; /* 0x000000081608722b */
/* 0x001048000000000e */
/*03f0*/ LDS.128 R12, [R7+0x40] ; /* 0x00004000070c7984 */
/* 0x001e280000000c00 */
/*0400*/ LDS.64 R22, [R0.X8+0x2a00] ; /* 0x002a000000167984 */
/* 0x000fe20000008a00 */
/*0410*/ DFMA R10, R20, R10, R8 ; /* 0x0000000a140a722b */
/* 0x0022060000000008 */
/*0420*/ LDS.64 R20, [R0.X8+0x2900] ; /* 0x0029000000147984 */
/* 0x002e660000008a00 */
/*0430*/ DFMA R12, R24, R12, R10 ; /* 0x0000000c180c722b */
/* 0x001048000000000a */
/*0440*/ LDS.128 R8, [R7+0x50] ; /* 0x0000500007087984 */
/* 0x001e280000000c00 */
/*0450*/ LDS.64 R24, [R0.X8+0x2c00] ; /* 0x002c000000187984 */
/* 0x000fe20000008a00 */
/*0460*/ DFMA R14, R20, R14, R12 ; /* 0x0000000e140e722b */
/* 0x002206000000000c */
/*0470*/ LDS.64 R20, [R0.X8+0x2b00] ; /* 0x002b000000147984 */
/* 0x002e660000008a00 */
/*0480*/ DFMA R8, R22, R8, R14 ; /* 0x000000081608722b */
/* 0x001048000000000e */
/*0490*/ LDS.128 R12, [R7+0x60] ; /* 0x00006000070c7984 */
/* 0x001e280000000c00 */
/*04a0*/ LDS.64 R22, [R0.X8+0x2e00] ; /* 0x002e000000167984 */
/* 0x000fe20000008a00 */
/*04b0*/ DFMA R10, R20, R10, R8 ; /* 0x0000000a140a722b */
/* 0x0022060000000008 */
/*04c0*/ LDS.64 R20, [R0.X8+0x2d00] ; /* 0x002d000000147984 */
/* 0x002e660000008a00 */
/*04d0*/ DFMA R12, R24, R12, R10 ; /* 0x0000000c180c722b */
/* 0x001048000000000a */
/*04e0*/ LDS.128 R8, [R7+0x70] ; /* 0x0000700007087984 */
/* 0x001e280000000c00 */
/*04f0*/ LDS.64 R24, [R0.X8+0x3000] ; /* 0x0030000000187984 */
/* 0x000fe20000008a00 */
/*0500*/ DFMA R14, R20, R14, R12 ; /* 0x0000000e140e722b */
/* 0x002206000000000c */
/*0510*/ LDS.64 R20, [R0.X8+0x2f00] ; /* 0x002f000000147984 */
/* 0x002e660000008a00 */
/*0520*/ DFMA R8, R22, R8, R14 ; /* 0x000000081608722b */
/* 0x001048000000000e */
/*0530*/ LDS.128 R12, [R7+0x80] ; /* 0x00008000070c7984 */
/* 0x001e280000000c00 */
/*0540*/ LDS.64 R22, [R0.X8+0x3200] ; /* 0x0032000000167984 */
/* 0x000fe20000008a00 */
/*0550*/ DFMA R10, R20, R10, R8 ; /* 0x0000000a140a722b */
/* 0x0022060000000008 */
/*0560*/ LDS.64 R20, [R0.X8+0x3100] ; /* 0x0031000000147984 */
/* 0x002e660000008a00 */
/*0570*/ DFMA R12, R24, R12, R10 ; /* 0x0000000c180c722b */
/* 0x001048000000000a */
/*0580*/ LDS.128 R8, [R7+0x90] ; /* 0x0000900007087984 */
/* 0x001e280000000c00 */
/*0590*/ LDS.64 R24, [R0.X8+0x3400] ; /* 0x0034000000187984 */
/* 0x000fe20000008a00 */
/*05a0*/ DFMA R14, R20, R14, R12 ; /* 0x0000000e140e722b */
/* 0x002206000000000c */
/*05b0*/ LDS.64 R20, [R0.X8+0x3300] ; /* 0x0033000000147984 */
/* 0x002e660000008a00 */
/*05c0*/ DFMA R8, R22, R8, R14 ; /* 0x000000081608722b */
/* 0x001048000000000e */
/*05d0*/ LDS.128 R12, [R7+0xa0] ; /* 0x0000a000070c7984 */
/* 0x001e280000000c00 */
/*05e0*/ LDS.64 R22, [R0.X8+0x3600] ; /* 0x0036000000167984 */
/* 0x000fe20000008a00 */
/*05f0*/ DFMA R10, R20, R10, R8 ; /* 0x0000000a140a722b */
/* 0x0022060000000008 */
/*0600*/ LDS.64 R20, [R0.X8+0x3500] ; /* 0x0035000000147984 */
/* 0x002e660000008a00 */
/*0610*/ DFMA R12, R24, R12, R10 ; /* 0x0000000c180c722b */
/* 0x001048000000000a */
/*0620*/ LDS.128 R8, [R7+0xb0] ; /* 0x0000b00007087984 */
/* 0x001e280000000c00 */
/*0630*/ LDS.64 R24, [R0.X8+0x3800] ; /* 0x0038000000187984 */
/* 0x000fe20000008a00 */
/*0640*/ DFMA R14, R20, R14, R12 ; /* 0x0000000e140e722b */
/* 0x002206000000000c */
/*0650*/ LDS.64 R20, [R0.X8+0x3700] ; /* 0x0037000000147984 */
/* 0x002e660000008a00 */
/*0660*/ DFMA R8, R22, R8, R14 ; /* 0x000000081608722b */
/* 0x001048000000000e */
/*0670*/ LDS.128 R12, [R7+0xc0] ; /* 0x0000c000070c7984 */
/* 0x001e280000000c00 */
/*0680*/ LDS.64 R22, [R0.X8+0x3a00] ; /* 0x003a000000167984 */
/* 0x000fe20000008a00 */
/*0690*/ DFMA R10, R20, R10, R8 ; /* 0x0000000a140a722b */
/* 0x0022060000000008 */
/*06a0*/ LDS.64 R20, [R0.X8+0x3900] ; /* 0x0039000000147984 */
/* 0x002e660000008a00 */
/*06b0*/ DFMA R12, R24, R12, R10 ; /* 0x0000000c180c722b */
/* 0x001048000000000a */
/*06c0*/ LDS.128 R8, [R7+0xd0] ; /* 0x0000d00007087984 */
/* 0x001e280000000c00 */
/*06d0*/ LDS.64 R24, [R0.X8+0x3c00] ; /* 0x003c000000187984 */
/* 0x000fe20000008a00 */
/*06e0*/ DFMA R14, R20, R14, R12 ; /* 0x0000000e140e722b */
/* 0x002206000000000c */
/*06f0*/ LDS.64 R20, [R0.X8+0x3b00] ; /* 0x003b000000147984 */
/* 0x002e660000008a00 */
/*0700*/ DFMA R8, R22, R8, R14 ; /* 0x000000081608722b */
/* 0x001048000000000e */
/*0710*/ LDS.128 R12, [R7+0xe0] ; /* 0x0000e000070c7984 */
/* 0x001e280000000c00 */
/*0720*/ LDS.64 R22, [R0.X8+0x3d00] ; /* 0x003d000000167984 */
/* 0x000ea20000008a00 */
/*0730*/ DFMA R10, R20, R10, R8 ; /* 0x0000000a140a722b */
/* 0x0022060000000008 */
/*0740*/ LDS.64 R20, [R0.X8+0x3e00] ; /* 0x003e000000147984 */
/* 0x002fe60000008a00 */
/*0750*/ DFMA R24, R24, R12, R10 ; /* 0x0000000c1818722b */
/* 0x001088000000000a */
/*0760*/ LDS.128 R8, [R7+0xf0] ; /* 0x0000f00007087984 */
/* 0x001e280000000c00 */
/*0770*/ LDS.64 R12, [R0.X8+0x3f00] ; /* 0x003f0000000c7984 */
/* 0x000e620000008a00 */
/*0780*/ DFMA R14, R22, R14, R24 ; /* 0x0000000e160e722b */
/* 0x004e0c0000000018 */
/*0790*/ DFMA R8, R20, R8, R14 ; /* 0x000000081408722b */
/* 0x001e4c000000000e */
/*07a0*/ DFMA R10, R12, R10, R8 ; /* 0x0000000a0c0a722b */
/* 0x0020620000000008 */
/*07b0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*07c0*/ @!P0 BRA 0x1f0 ; /* 0xfffffa2000008947 */
/* 0x003fea000383ffff */
/*07d0*/ STG.E.64 [R16.64], R10 ; /* 0x0000000a10007986 */
/* 0x000fe2000c101b06 */
/*07e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*07f0*/ BRA 0x7f0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0800*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0810*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0820*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0830*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0840*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0850*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0860*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0870*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9matrixMulPdS_S_iii
.globl _Z9matrixMulPdS_S_iii
.p2align 8
.type _Z9matrixMulPdS_S_iii,@function
_Z9matrixMulPdS_S_iii:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x34
s_load_b64 s[2:3], s[0:1], 0x1c
v_bfe_u32 v3, v0, 10, 10
v_and_b32_e32 v4, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s5, s4, 16
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(VALU_DEP_1)
v_mad_u64_u32 v[0:1], null, s15, s5, v[3:4]
v_mad_u64_u32 v[1:2], null, s14, s4, v[4:5]
s_cmp_lt_i32 s3, 1
s_cbranch_scc1 .LBB0_5
s_load_b128 s[4:7], s[0:1], 0x0
v_lshlrev_b32_e32 v5, 3, v4
v_lshlrev_b32_e32 v2, 8, v3
s_add_i32 s8, s3, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
s_lshr_b32 s8, s8, 5
v_or_b32_e32 v8, 0x2000, v5
v_mad_u64_u32 v[6:7], null, v0, s3, v[4:5]
v_dual_mov_b32 v4, 0 :: v_dual_add_nc_u32 v7, v2, v5
v_mov_b32_e32 v5, 0
s_delay_alu instid0(VALU_DEP_4)
v_add_nc_u32_e32 v9, v8, v2
s_max_i32 s3, s8, 1
s_mov_b32 s8, 0
s_set_inst_prefetch_distance 0x1
.p2align 6
.LBB0_2:
s_lshl_b32 s9, s8, 5
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v11, s9, v3
v_add_nc_u32_e32 v10, s9, v6
s_mov_b32 s9, 0
v_mad_u64_u32 v[12:13], null, v11, s2, v[1:2]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v11, 31, v10
v_lshlrev_b64 v[10:11], 3, v[10:11]
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v13, 31, v12
s_waitcnt lgkmcnt(0)
v_add_co_u32 v10, vcc_lo, s4, v10
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_lshlrev_b64 v[12:13], 3, v[12:13]
v_add_co_ci_u32_e32 v11, vcc_lo, s5, v11, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v12, vcc_lo, s6, v12
v_add_co_ci_u32_e32 v13, vcc_lo, s7, v13, vcc_lo
global_load_b64 v[14:15], v[10:11], off
global_load_b64 v[11:12], v[12:13], off
v_mov_b32_e32 v10, v8
s_waitcnt vmcnt(1)
ds_store_b64 v7, v[14:15]
s_waitcnt vmcnt(0)
ds_store_b64 v9, v[11:12]
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
.LBB0_3:
v_add_nc_u32_e32 v13, s9, v2
s_add_i32 s9, s9, 8
ds_load_b64 v[11:12], v10
ds_load_b64 v[13:14], v13
v_add_nc_u32_e32 v10, 0x100, v10
s_cmpk_eq_i32 s9, 0x100
s_waitcnt lgkmcnt(0)
v_fma_f64 v[4:5], v[13:14], v[11:12], v[4:5]
s_cbranch_scc0 .LBB0_3
s_add_i32 s8, s8, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s8, s3
s_barrier
buffer_gl0_inv
s_cbranch_scc0 .LBB0_2
s_branch .LBB0_6
.LBB0_5:
v_mov_b32_e32 v4, 0
v_mov_b32_e32 v5, 0
.LBB0_6:
s_set_inst_prefetch_distance 0x2
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, v0, s2, v[1:2]
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 3, v[2:3]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b64 v[0:1], v[4:5], off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9matrixMulPdS_S_iii
.amdhsa_group_segment_fixed_size 16384
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 16
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9matrixMulPdS_S_iii, .Lfunc_end0-_Z9matrixMulPdS_S_iii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 16384
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9matrixMulPdS_S_iii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9matrixMulPdS_S_iii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 16
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0013a91f_00000000-6_ee16b105_7.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2063:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2063:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "/home/ubuntu/Datasets/stackv2/train-structured/anantshah200/CS6023/master/Assignment2/ee16b105_7.cu"
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "%s in %s at %d"
.text
.globl _Z13error_handler9cudaErrori
.type _Z13error_handler9cudaErrori, @function
_Z13error_handler9cudaErrori:
.LFB2057:
.cfi_startproc
endbr64
testl %edi, %edi
jne .L8
ret
.L8:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movl %esi, %ebx
call cudaGetErrorString@PLT
movq %rax, %rdx
movl %ebx, %r8d
leaq .LC0(%rip), %rcx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size _Z13error_handler9cudaErrori, .-_Z13error_handler9cudaErrori
.globl _Z11fill_matrixPdjj
.type _Z11fill_matrixPdjj, @function
_Z11fill_matrixPdjj:
.LFB2058:
.cfi_startproc
endbr64
movq %rdi, %r9
movl $0, %r8d
movl $0, %r10d
movss .LC2(%rip), %xmm3
movss .LC3(%rip), %xmm2
testl %esi, %esi
jne .L10
ret
.L17:
movl %r10d, %eax
pxor %xmm1, %xmm1
cvtsi2ssq %rax, %xmm1
mulss %xmm3, %xmm1
movl $0, %eax
.L16:
leal (%r8,%rax), %ecx
movl %eax, %edi
pxor %xmm0, %xmm0
cvtsi2ssq %rdi, %xmm0
mulss %xmm2, %xmm0
addss %xmm1, %xmm0
cvtss2sd %xmm0, %xmm0
movsd %xmm0, (%r9,%rcx,8)
addl $1, %eax
cmpl %eax, %edx
jne .L16
.L18:
addl $1, %r10d
addl %edx, %r8d
cmpl %r10d, %esi
je .L9
.L10:
testl %edx, %edx
jne .L17
jmp .L18
.L9:
ret
.cfi_endproc
.LFE2058:
.size _Z11fill_matrixPdjj, .-_Z11fill_matrixPdjj
.section .rodata.str1.1
.LC4:
.string "a"
.LC5:
.string "assignment2_out"
.LC6:
.string "%4.4f "
.LC7:
.string "\n"
.text
.globl _Z20print_matrix_to_filePdjj
.type _Z20print_matrix_to_filePdjj, @function
_Z20print_matrix_to_filePdjj:
.LFB2059:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $24, %rsp
.cfi_def_cfa_offset 80
movq %rdi, %r13
movl %esi, %ebx
movl %esi, 12(%rsp)
movl %edx, %r15d
leaq .LC4(%rip), %rsi
leaq .LC5(%rip), %rdi
call fopen@PLT
movq %rax, %r12
movl %r15d, %ebp
movl $0, 8(%rsp)
leaq .LC6(%rip), %r14
testl %ebx, %ebx
jne .L23
.L24:
movq %r12, %rdi
call fclose@PLT
addq $24, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L25:
.cfi_restore_state
movl %ebx, %eax
movsd 0(%r13,%rax,8), %xmm0
movq %r14, %rdx
movl $2, %esi
movq %r12, %rdi
movl $1, %eax
call __fprintf_chk@PLT
addl $1, %ebx
cmpl %ebp, %ebx
jne .L25
.L27:
leaq .LC7(%rip), %rdx
movl $2, %esi
movq %r12, %rdi
movl $0, %eax
call __fprintf_chk@PLT
addl $1, 8(%rsp)
movl 8(%rsp), %eax
addl %r15d, %ebp
cmpl %eax, 12(%rsp)
je .L24
.L23:
movl %ebp, %ebx
subl %r15d, %ebx
testl %r15d, %r15d
jne .L25
jmp .L27
.cfi_endproc
.LFE2059:
.size _Z20print_matrix_to_filePdjj, .-_Z20print_matrix_to_filePdjj
.globl _Z35__device_stub__Z9matrixMulPdS_S_iiiPdS_S_iii
.type _Z35__device_stub__Z9matrixMulPdS_S_iiiPdS_S_iii, @function
_Z35__device_stub__Z9matrixMulPdS_S_iiiPdS_S_iii:
.LFB2085:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L37
.L33:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L38
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L37:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z9matrixMulPdS_S_iii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L33
.L38:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2085:
.size _Z35__device_stub__Z9matrixMulPdS_S_iiiPdS_S_iii, .-_Z35__device_stub__Z9matrixMulPdS_S_iiiPdS_S_iii
.globl _Z9matrixMulPdS_S_iii
.type _Z9matrixMulPdS_S_iii, @function
_Z9matrixMulPdS_S_iii:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z9matrixMulPdS_S_iiiPdS_S_iii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _Z9matrixMulPdS_S_iii, .-_Z9matrixMulPdS_S_iii
.section .rodata.str1.8
.align 8
.LC8:
.string "error : Invalid number of arguments\n"
.section .rodata.str1.1
.LC11:
.string "Run-Time(seconds) : %.4f"
.text
.globl main
.type main, @function
main:
.LFB2060:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $80, %rsp
.cfi_def_cfa_offset 128
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
cmpl $1, %edi
jne .L46
leaq 32(%rsp), %rdi
call cudaEventCreate@PLT
leaq 40(%rsp), %rdi
call cudaEventCreate@PLT
movl $1073741824, %edi
call malloc@PLT
movq %rax, %r12
movabsq $4294967296, %r13
movq %r13, %rdi
call malloc@PLT
movq %rax, %rbp
movl $2147483648, %r14d
movq %r14, %rdi
call malloc@PLT
movq %rax, %rbx
movl $16384, %edx
movl $8192, %esi
movq %r12, %rdi
call _Z11fill_matrixPdjj
movl $32768, %edx
movl $16384, %esi
movq %rbp, %rdi
call _Z11fill_matrixPdjj
leaq 8(%rsp), %rdi
movl $1073741824, %esi
call cudaMalloc@PLT
movl %eax, %edi
movl $116, %esi
call _Z13error_handler9cudaErrori
leaq 16(%rsp), %rdi
movq %r13, %rsi
call cudaMalloc@PLT
movl %eax, %edi
movl $117, %esi
call _Z13error_handler9cudaErrori
leaq 24(%rsp), %rdi
movq %r14, %rsi
call cudaMalloc@PLT
movl %eax, %edi
movl $118, %esi
call _Z13error_handler9cudaErrori
movl $1, %ecx
movl $1073741824, %edx
movq %r12, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
movl $122, %esi
call _Z13error_handler9cudaErrori
movl $1, %ecx
movq %r13, %rdx
movq %rbp, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
movl $123, %esi
call _Z13error_handler9cudaErrori
movl $32, 48(%rsp)
movl $32, 52(%rsp)
movl $1, 56(%rsp)
movl $1024, 60(%rsp)
movl $256, 64(%rsp)
movl $1, 68(%rsp)
movl $0, %esi
movq 32(%rsp), %rdi
call cudaEventRecord@PLT
movl 56(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 48(%rsp), %rdx
movq 60(%rsp), %rdi
movl 68(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L47
.L43:
movl $0, %esi
movq 40(%rsp), %rdi
call cudaEventRecord@PLT
movl $2, %ecx
movl $2147483648, %edx
movq 24(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movl %eax, %edi
movl $134, %esi
call _Z13error_handler9cudaErrori
movq 40(%rsp), %rdi
call cudaEventSynchronize@PLT
movl $0x00000000, 4(%rsp)
leaq 4(%rsp), %rdi
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
call cudaEventElapsedTime@PLT
movss 4(%rsp), %xmm0
divss .LC10(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl $32768, %edx
movl $8192, %esi
movq %rbx, %rdi
call _Z20print_matrix_to_filePdjj
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq %r12, %rdi
call free@PLT
movq %rbp, %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L48
movl $0, %eax
addq $80, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L46:
.cfi_restore_state
leaq .LC8(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L47:
movl $16384, %r9d
movl $32768, %r8d
movl $8192, %ecx
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z35__device_stub__Z9matrixMulPdS_S_iiiPdS_S_iii
jmp .L43
.L48:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2060:
.size main, .-main
.section .rodata.str1.1
.LC12:
.string "_Z9matrixMulPdS_S_iii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2088:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC12(%rip), %rdx
movq %rdx, %rcx
leaq _Z9matrixMulPdS_S_iii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2088:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC2:
.long 1074161254
.align 4
.LC3:
.long 1078774989
.align 4
.LC10:
.long 1148846080
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "ee16b105_7.hip"
.globl _Z13error_handler10hipError_ti # -- Begin function _Z13error_handler10hipError_ti
.p2align 4, 0x90
.type _Z13error_handler10hipError_ti,@function
_Z13error_handler10hipError_ti: # @_Z13error_handler10hipError_ti
.cfi_startproc
# %bb.0:
testl %edi, %edi
jne .LBB0_2
# %bb.1:
retq
.LBB0_2:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
movl %esi, %ebx
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.1, %edx
movq %rax, %rsi
movl %ebx, %ecx
xorl %eax, %eax
callq printf
movl $1, %edi
callq exit
.Lfunc_end0:
.size _Z13error_handler10hipError_ti, .Lfunc_end0-_Z13error_handler10hipError_ti
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z11fill_matrixPdjj
.LCPI1_0:
.long 0x40066666 # float 2.0999999
.LCPI1_1:
.long 0x404ccccd # float 3.20000005
.text
.globl _Z11fill_matrixPdjj
.p2align 4, 0x90
.type _Z11fill_matrixPdjj,@function
_Z11fill_matrixPdjj: # @_Z11fill_matrixPdjj
.cfi_startproc
# %bb.0:
testl %esi, %esi
je .LBB1_6
# %bb.1: # %.preheader.lr.ph
movl %edx, %eax
xorl %ecx, %ecx
movss .LCPI1_0(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
movss .LCPI1_1(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
xorl %r8d, %r8d
jmp .LBB1_2
.p2align 4, 0x90
.LBB1_5: # %._crit_edge
# in Loop: Header=BB1_2 Depth=1
incl %r8d
addq %rax, %rcx
cmpl %esi, %r8d
je .LBB1_6
.LBB1_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_4 Depth 2
testl %edx, %edx
je .LBB1_5
# %bb.3: # %.lr.ph
# in Loop: Header=BB1_2 Depth=1
movl %r8d, %r9d
xorps %xmm2, %xmm2
cvtsi2ss %r9, %xmm2
mulss %xmm0, %xmm2
xorl %r9d, %r9d
.p2align 4, 0x90
.LBB1_4: # Parent Loop BB1_2 Depth=1
# => This Inner Loop Header: Depth=2
movl %r9d, %r10d
xorps %xmm3, %xmm3
cvtsi2ss %r10, %xmm3
mulss %xmm1, %xmm3
addss %xmm2, %xmm3
cvtss2sd %xmm3, %xmm3
leal (%rcx,%r9), %r10d
movsd %xmm3, (%rdi,%r10,8)
incq %r9
cmpq %r9, %rax
jne .LBB1_4
jmp .LBB1_5
.LBB1_6: # %._crit_edge15
retq
.Lfunc_end1:
.size _Z11fill_matrixPdjj, .Lfunc_end1-_Z11fill_matrixPdjj
.cfi_endproc
# -- End function
.globl _Z20print_matrix_to_filePdjj # -- Begin function _Z20print_matrix_to_filePdjj
.p2align 4, 0x90
.type _Z20print_matrix_to_filePdjj,@function
_Z20print_matrix_to_filePdjj: # @_Z20print_matrix_to_filePdjj
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $24, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %edx, %ebx
movl %esi, %ebp
movq %rdi, %r14
movl $.L.str.2, %edi
movl $.L.str.3, %esi
callq fopen
movq %rax, %r15
movl %ebp, 12(%rsp) # 4-byte Spill
testl %ebp, %ebp
je .LBB2_4
# %bb.1: # %.preheader.lr.ph
movl %ebx, %ecx
movl %ebx, %eax
movq %rax, 16(%rsp) # 8-byte Spill
xorl %ebx, %ebx
xorl %ebp, %ebp
movl %ecx, 8(%rsp) # 4-byte Spill
jmp .LBB2_2
.p2align 4, 0x90
.LBB2_3: # %._crit_edge
# in Loop: Header=BB2_2 Depth=1
movl $10, %edi
movq %r15, %rsi
callq fputc@PLT
incl %ebp
movl 8(%rsp), %ecx # 4-byte Reload
addl %ecx, %ebx
cmpl 12(%rsp), %ebp # 4-byte Folded Reload
je .LBB2_4
.LBB2_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB2_5 Depth 2
movq 16(%rsp), %r12 # 8-byte Reload
movl %ebx, %r13d
testl %ecx, %ecx
je .LBB2_3
.p2align 4, 0x90
.LBB2_5: # Parent Loop BB2_2 Depth=1
# => This Inner Loop Header: Depth=2
movl %r13d, %eax
movsd (%r14,%rax,8), %xmm0 # xmm0 = mem[0],zero
movl $.L.str.4, %esi
movq %r15, %rdi
movb $1, %al
callq fprintf
incl %r13d
decq %r12
jne .LBB2_5
jmp .LBB2_3
.LBB2_4: # %._crit_edge17
movq %r15, %rdi
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
jmp fclose # TAILCALL
.Lfunc_end2:
.size _Z20print_matrix_to_filePdjj, .Lfunc_end2-_Z20print_matrix_to_filePdjj
.cfi_endproc
# -- End function
.globl _Z24__device_stub__matrixMulPdS_S_iii # -- Begin function _Z24__device_stub__matrixMulPdS_S_iii
.p2align 4, 0x90
.type _Z24__device_stub__matrixMulPdS_S_iii,@function
_Z24__device_stub__matrixMulPdS_S_iii: # @_Z24__device_stub__matrixMulPdS_S_iii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z9matrixMulPdS_S_iii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end3:
.size _Z24__device_stub__matrixMulPdS_S_iii, .Lfunc_end3-_Z24__device_stub__matrixMulPdS_S_iii
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI4_0:
.long 0x40066666 # float 2.0999999
.LCPI4_1:
.long 0x404ccccd # float 3.20000005
.LCPI4_2:
.long 0x447a0000 # float 1000
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $200, %rsp
.cfi_def_cfa_offset 256
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
cmpl $1, %edi
jne .LBB4_29
# %bb.1:
movabsq $4294967296, %r12 # imm = 0x100000000
leaq 56(%rsp), %rdi
callq hipEventCreate
leaq 8(%rsp), %rdi
callq hipEventCreate
movl $1073741824, %edi # imm = 0x40000000
callq malloc
movq %rax, %rbx
movq %r12, %rdi
callq malloc
movq %rax, %r14
movl $2147483648, %edi # imm = 0x80000000
callq malloc
movq %rax, %r15
xorl %eax, %eax
movss .LCPI4_0(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
movss .LCPI4_1(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
movq %rbx, %rcx
.p2align 4, 0x90
.LBB4_2: # %.preheader.i
# =>This Loop Header: Depth=1
# Child Loop BB4_3 Depth 2
movl %eax, %edx
xorps %xmm2, %xmm2
cvtsi2ss %rdx, %xmm2
mulss %xmm0, %xmm2
xorl %edx, %edx
.p2align 4, 0x90
.LBB4_3: # Parent Loop BB4_2 Depth=1
# => This Inner Loop Header: Depth=2
movl %edx, %esi
xorps %xmm3, %xmm3
cvtsi2ss %rsi, %xmm3
mulss %xmm1, %xmm3
addss %xmm2, %xmm3
cvtss2sd %xmm3, %xmm3
movsd %xmm3, (%rcx,%rdx,8)
incq %rdx
cmpq $16384, %rdx # imm = 0x4000
jne .LBB4_3
# %bb.4: # %._crit_edge.i
# in Loop: Header=BB4_2 Depth=1
incl %eax
addq $131072, %rcx # imm = 0x20000
cmpl $8192, %eax # imm = 0x2000
jne .LBB4_2
# %bb.5: # %.preheader.i26.preheader
xorl %eax, %eax
movq %r14, %rcx
.p2align 4, 0x90
.LBB4_6: # %.preheader.i26
# =>This Loop Header: Depth=1
# Child Loop BB4_7 Depth 2
movl %eax, %edx
xorps %xmm2, %xmm2
cvtsi2ss %rdx, %xmm2
mulss %xmm0, %xmm2
xorl %edx, %edx
.p2align 4, 0x90
.LBB4_7: # Parent Loop BB4_6 Depth=1
# => This Inner Loop Header: Depth=2
movl %edx, %esi
xorps %xmm3, %xmm3
cvtsi2ss %rsi, %xmm3
mulss %xmm1, %xmm3
addss %xmm2, %xmm3
cvtss2sd %xmm3, %xmm3
movsd %xmm3, (%rcx,%rdx,8)
incq %rdx
cmpq $32768, %rdx # imm = 0x8000
jne .LBB4_7
# %bb.8: # %._crit_edge.i31
# in Loop: Header=BB4_6 Depth=1
incl %eax
addq $262144, %rcx # imm = 0x40000
cmpl $16384, %eax # imm = 0x4000
jne .LBB4_6
# %bb.9: # %_Z11fill_matrixPdjj.exit33
leaq 32(%rsp), %rdi
movl $1073741824, %esi # imm = 0x40000000
callq hipMalloc
testl %eax, %eax
jne .LBB4_10
# %bb.12: # %_Z13error_handler10hipError_ti.exit
leaq 24(%rsp), %rdi
movq %r12, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB4_13
# %bb.14: # %_Z13error_handler10hipError_ti.exit35
leaq 16(%rsp), %rdi
movl $2147483648, %esi # imm = 0x80000000
callq hipMalloc
testl %eax, %eax
jne .LBB4_15
# %bb.16: # %_Z13error_handler10hipError_ti.exit37
movq 32(%rsp), %rdi
movl $1073741824, %edx # imm = 0x40000000
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB4_17
# %bb.18: # %_Z13error_handler10hipError_ti.exit39
movq 24(%rsp), %rdi
movq %r14, %rsi
movq %r12, %rdx
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB4_19
# %bb.20: # %_Z13error_handler10hipError_ti.exit41
movq %rbx, 64(%rsp) # 8-byte Spill
movq 56(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movabsq $1099511628800, %rdi # imm = 0x10000000400
movabsq $137438953504, %rdx # imm = 0x2000000020
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_22
# %bb.21:
movq 32(%rsp), %rax
movq 24(%rsp), %rcx
movq 16(%rsp), %rdx
movq %rax, 136(%rsp)
movq %rcx, 128(%rsp)
movq %rdx, 120(%rsp)
movl $8192, 52(%rsp) # imm = 0x2000
movl $32768, 48(%rsp) # imm = 0x8000
movl $16384, 44(%rsp) # imm = 0x4000
leaq 136(%rsp), %rax
movq %rax, 144(%rsp)
leaq 128(%rsp), %rax
movq %rax, 152(%rsp)
leaq 120(%rsp), %rax
movq %rax, 160(%rsp)
leaq 52(%rsp), %rax
movq %rax, 168(%rsp)
leaq 48(%rsp), %rax
movq %rax, 176(%rsp)
leaq 44(%rsp), %rax
movq %rax, 184(%rsp)
leaq 104(%rsp), %rdi
leaq 88(%rsp), %rsi
leaq 80(%rsp), %rdx
leaq 72(%rsp), %rcx
callq __hipPopCallConfiguration
movq 104(%rsp), %rsi
movl 112(%rsp), %edx
movq 88(%rsp), %rcx
movl 96(%rsp), %r8d
leaq 144(%rsp), %r9
movl $_Z9matrixMulPdS_S_iii, %edi
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
pushq 88(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_22:
movq 8(%rsp), %rdi
xorl %r13d, %r13d
xorl %esi, %esi
callq hipEventRecord
movq 16(%rsp), %rsi
movl $2147483648, %edx # imm = 0x80000000
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB4_23
# %bb.24: # %_Z13error_handler10hipError_ti.exit43
movq 8(%rsp), %rdi
callq hipEventSynchronize
movl $0, 144(%rsp)
movq 56(%rsp), %rsi
movq 8(%rsp), %rdx
leaq 144(%rsp), %rdi
callq hipEventElapsedTime
movss 144(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
divss .LCPI4_2(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movl $.L.str.7, %edi
movb $1, %al
callq printf
movl $.L.str.2, %edi
movl $.L.str.3, %esi
callq fopen
movq %rax, %r12
movq %r15, %rbp
.p2align 4, 0x90
.LBB4_25: # %.preheader.i44
# =>This Loop Header: Depth=1
# Child Loop BB4_26 Depth 2
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB4_26: # Parent Loop BB4_25 Depth=1
# => This Inner Loop Header: Depth=2
movsd (%rbp,%rbx,8), %xmm0 # xmm0 = mem[0],zero
movl $.L.str.4, %esi
movq %r12, %rdi
movb $1, %al
callq fprintf
incq %rbx
cmpq $32768, %rbx # imm = 0x8000
jne .LBB4_26
# %bb.27: # %._crit_edge.i48
# in Loop: Header=BB4_25 Depth=1
movl $10, %edi
movq %r12, %rsi
callq fputc@PLT
incl %r13d
addq $262144, %rbp # imm = 0x40000
cmpl $8192, %r13d # imm = 0x2000
jne .LBB4_25
# %bb.28: # %_Z20print_matrix_to_filePdjj.exit
movq %r12, %rdi
callq fclose
movq 32(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 64(%rsp), %rdi # 8-byte Reload
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
xorl %eax, %eax
addq $200, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB4_29:
.cfi_def_cfa_offset 256
movl $.Lstr, %edi
callq puts@PLT
movl $1, %edi
callq exit
.LBB4_10:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.1, %edx
movq %rax, %rsi
movl $118, %ecx
jmp .LBB4_11
.LBB4_13:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.1, %edx
movq %rax, %rsi
movl $119, %ecx
jmp .LBB4_11
.LBB4_15:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.1, %edx
movq %rax, %rsi
movl $120, %ecx
jmp .LBB4_11
.LBB4_17:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.1, %edx
movq %rax, %rsi
movl $124, %ecx
jmp .LBB4_11
.LBB4_19:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.1, %edx
movq %rax, %rsi
movl $125, %ecx
jmp .LBB4_11
.LBB4_23:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.1, %edx
movq %rax, %rsi
movl $136, %ecx
.LBB4_11:
xorl %eax, %eax
callq printf
movl $1, %edi
callq exit
.Lfunc_end4:
.size main, .Lfunc_end4-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9matrixMulPdS_S_iii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%s in %s at %d"
.size .L.str, 15
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/anantshah200/CS6023/master/Assignment2/ee16b105_7.hip"
.size .L.str.1, 111
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "assignment2_out"
.size .L.str.2, 16
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "a"
.size .L.str.3, 2
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "%4.4f "
.size .L.str.4, 7
.type _Z9matrixMulPdS_S_iii,@object # @_Z9matrixMulPdS_S_iii
.section .rodata,"a",@progbits
.globl _Z9matrixMulPdS_S_iii
.p2align 3, 0x0
_Z9matrixMulPdS_S_iii:
.quad _Z24__device_stub__matrixMulPdS_S_iii
.size _Z9matrixMulPdS_S_iii, 8
.type .L.str.7,@object # @.str.7
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.7:
.asciz "Run-Time(seconds) : %.4f"
.size .L.str.7, 25
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z9matrixMulPdS_S_iii"
.size .L__unnamed_1, 22
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "error : Invalid number of arguments"
.size .Lstr, 36
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__matrixMulPdS_S_iii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9matrixMulPdS_S_iii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <stdlib.h>
#include <cuda_runtime_api.h>
#define BASE_TYPE float
__global__ void mult(const BASE_TYPE *a, const BASE_TYPE *b, BASE_TYPE *c, const int N, const int M)
{
int i = N * (blockDim.y * blockIdx.y + threadIdx.y);
int j = blockDim.x * blockIdx.x + threadIdx.x;
BASE_TYPE sum = 0;
for (int k = 0; k < N; k++)
{
sum += a[i + k] * b[k * M + j];
}
int id = M * (blockDim.y * blockIdx.y + threadIdx.y) + blockDim.x * blockIdx.x + threadIdx.x;
c[id] = sum;
}
BASE_TYPE* gen_array(const int N)
{
BASE_TYPE *a = new BASE_TYPE[N * N];
for (int i = 0; i < N; i++)
{
for (int j = 0; j < N; j++)
a[i * N + j] = i * N + j;
}
return a;
}
void print_array(BASE_TYPE *a, const int N)
{
for (int i = 0; i < N; i++)
{
for (int j = 0; j < N; j++)
printf("%5.0f ", a[i *N + j]);
printf("\n");
}
printf("\n");
}
void cuda_init_array(BASE_TYPE **dev, const BASE_TYPE *host, const size_t size)
{
cudaError_t err;
err = cudaMalloc((void **)dev, size);
if (err != cudaSuccess)
throw err;
if (host != NULL)
{
err = cudaMemcpy(*dev, host, size, cudaMemcpyHostToDevice);
if (err != cudaSuccess)
throw err;
}
}
void cuda_init_grid_and_block(dim3 *grid, dim3 *block, const int N)
{
*grid = dim3(1);
*block = dim3(N, N, 1);
printf("Block %d %d %d\n", block->x, block->y, block->z);
printf("Grid %d %d %d\n", grid->x, grid->y, grid->z);
}
int main()
{
const int N = 10;
const size_t size = N * N * sizeof(BASE_TYPE);
cudaError_t err;
dim3 threadsPerBlock, blocksPerGrid;
cuda_init_grid_and_block(&blocksPerGrid, &threadsPerBlock, N);
BASE_TYPE *host_a = gen_array(N), *host_b = gen_array(N);
BASE_TYPE *dev_a, *dev_b, *dev_c;
if (host_a == NULL)
{
fprintf(stderr, "Failed to allocate host vectors!\n");
exit(EXIT_FAILURE);
}
print_array(host_a, N);
print_array(host_b, N);
try
{
cuda_init_array(&dev_a, host_a, size);
cuda_init_array(&dev_b, host_b, size);
cuda_init_array(&dev_c, NULL, size);
}
catch (cudaError_t err)
{
fprintf(stderr, "Failed to allocate device (error code: %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
mult<<<blocksPerGrid, threadsPerBlock>>>(dev_a, dev_b, dev_c, N, N);
err = cudaMemcpy(host_a, dev_c, size, cudaMemcpyDeviceToHost);
if (err != cudaSuccess)
{
fprintf(stderr, "Failed to allocate device (error code: %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
print_array(host_a, N);
cudaFree(dev_a);
cudaFree(dev_b);
delete[] host_a;
return 0;
} | code for sm_80
Function : _Z4multPKfS0_Pfii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e220000002600 */
/*0020*/ MOV R4, c[0x0][0x178] ; /* 0x00005e0000047a02 */
/* 0x000fe20000000f00 */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ HFMA2.MMA R24, -RZ, RZ, 0, 0 ; /* 0x00000000ff187435 */
/* 0x000fe200000001ff */
/*0050*/ S2R R3, SR_TID.Y ; /* 0x0000000000037919 */
/* 0x000e220000002200 */
/*0060*/ ISETP.GE.AND P0, PT, R4, 0x1, PT ; /* 0x000000010400780c */
/* 0x000fc60003f06270 */
/*0070*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e680000002500 */
/*0080*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0090*/ IMAD R0, R0, c[0x0][0x4], R3 ; /* 0x0000010000007a24 */
/* 0x001fe400078e0203 */
/*00a0*/ IMAD R3, R2, c[0x0][0x0], R5 ; /* 0x0000000002037a24 */
/* 0x002fc600078e0205 */
/*00b0*/ @!P0 BRA 0xc10 ; /* 0x00000b5000008947 */
/* 0x000fea0003800000 */
/*00c0*/ IADD3 R2, R4, -0x1, RZ ; /* 0xffffffff04027810 */
/* 0x000fe20007ffe0ff */
/*00d0*/ IMAD R5, R0, c[0x0][0x178], RZ ; /* 0x00005e0000057a24 */
/* 0x000fe200078e02ff */
/*00e0*/ LOP3.LUT R4, R4, 0x3, RZ, 0xc0, !PT ; /* 0x0000000304047812 */
/* 0x000fe400078ec0ff */
/*00f0*/ ISETP.GE.U32.AND P0, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fe40003f06070 */
/*0100*/ MOV R24, RZ ; /* 0x000000ff00187202 */
/* 0x000fe40000000f00 */
/*0110*/ MOV R2, RZ ; /* 0x000000ff00027202 */
/* 0x000fd20000000f00 */
/*0120*/ @!P0 BRA 0xb00 ; /* 0x000009d000008947 */
/* 0x000fea0003800000 */
/*0130*/ IADD3 R6, -R4, c[0x0][0x178], RZ ; /* 0x00005e0004067a10 */
/* 0x000fe20007ffe1ff */
/*0140*/ HFMA2.MMA R8, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff087435 */
/* 0x000fe200000001ff */
/*0150*/ ULDC.64 UR6, c[0x0][0x160] ; /* 0x0000580000067ab9 */
/* 0x000fe20000000a00 */
/*0160*/ HFMA2.MMA R2, -RZ, RZ, 0, 0 ; /* 0x00000000ff027435 */
/* 0x000fe200000001ff */
/*0170*/ ISETP.GT.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe40003f04270 */
/*0180*/ MOV R24, RZ ; /* 0x000000ff00187202 */
/* 0x000fca0000000f00 */
/*0190*/ IMAD.WIDE R8, R3, R8, c[0x0][0x168] ; /* 0x00005a0003087625 */
/* 0x000fcc00078e0208 */
/*01a0*/ @!P0 BRA 0x960 ; /* 0x000007b000008947 */
/* 0x000fea0003800000 */
/*01b0*/ ISETP.GT.AND P1, PT, R6, 0xc, PT ; /* 0x0000000c0600780c */
/* 0x000fe40003f24270 */
/*01c0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*01d0*/ @!P1 BRA 0x690 ; /* 0x000004b000009947 */
/* 0x000fea0003800000 */
/*01e0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*01f0*/ MOV R12, UR6 ; /* 0x00000006000c7c02 */
/* 0x000fe20008000f00 */
/*0200*/ LDG.E R21, [R8.64] ; /* 0x0000000408157981 */
/* 0x0000a2000c1e1900 */
/*0210*/ MOV R13, UR7 ; /* 0x00000007000d7c02 */
/* 0x000fca0008000f00 */
/*0220*/ IMAD.WIDE R12, R5, 0x4, R12 ; /* 0x00000004050c7825 */
/* 0x000fca00078e020c */
/*0230*/ LDG.E R20, [R12.64] ; /* 0x000000040c147981 */
/* 0x000ea2000c1e1900 */
/*0240*/ MOV R7, c[0x0][0x17c] ; /* 0x00005f0000077a02 */
/* 0x000fc60000000f00 */
/*0250*/ LDG.E R14, [R12.64+0x4] ; /* 0x000004040c0e7981 */
/* 0x000ee4000c1e1900 */
/*0260*/ IMAD.WIDE R10, R7.reuse, 0x4, R8 ; /* 0x00000004070a7825 */
/* 0x040fe400078e0208 */
/*0270*/ LDG.E R27, [R12.64+0x8] ; /* 0x000008040c1b7981 */
/* 0x000f28000c1e1900 */
/*0280*/ LDG.E R15, [R10.64] ; /* 0x000000040a0f7981 */
/* 0x0002e2000c1e1900 */
/*0290*/ IMAD.WIDE R22, R7, 0x4, R10 ; /* 0x0000000407167825 */
/* 0x000fc600078e020a */
/*02a0*/ LDG.E R18, [R12.64+0xc] ; /* 0x00000c040c127981 */
/* 0x000f66000c1e1900 */
/*02b0*/ IMAD.WIDE R28, R7.reuse, 0x4, R22 ; /* 0x00000004071c7825 */
/* 0x040fe200078e0216 */
/*02c0*/ LDG.E R26, [R22.64] ; /* 0x00000004161a7981 */
/* 0x000328000c1e1900 */
/*02d0*/ LDG.E R19, [R28.64] ; /* 0x000000041c137981 */
/* 0x000362000c1e1900 */
/*02e0*/ IMAD.WIDE R16, R7, 0x4, R28 ; /* 0x0000000407107825 */
/* 0x000fc600078e021c */
/*02f0*/ LDG.E R8, [R12.64+0x10] ; /* 0x000010040c087981 */
/* 0x001f68000c1e1900 */
/*0300*/ LDG.E R9, [R16.64] ; /* 0x0000000410097981 */
/* 0x000168000c1e1900 */
/*0310*/ LDG.E R10, [R12.64+0x14] ; /* 0x000014040c0a7981 */
/* 0x002f68000c1e1900 */
/*0320*/ LDG.E R28, [R12.64+0x1c] ; /* 0x00001c040c1c7981 */
/* 0x000f62000c1e1900 */
/*0330*/ IMAD.WIDE R16, R7, 0x4, R16 ; /* 0x0000000407107825 */
/* 0x001fca00078e0210 */
/*0340*/ LDG.E R11, [R16.64] ; /* 0x00000004100b7981 */
/* 0x000562000c1e1900 */
/*0350*/ IMAD.WIDE R22, R7, 0x4, R16 ; /* 0x0000000407167825 */
/* 0x000fc800078e0210 */
/*0360*/ FFMA R16, R21, R20, R24 ; /* 0x0000001415107223 */
/* 0x004fe40000000018 */
/*0370*/ LDG.E R20, [R12.64+0x18] ; /* 0x000018040c147981 */
/* 0x000ea2000c1e1900 */
/*0380*/ IMAD.WIDE R24, R7, 0x4, R22 ; /* 0x0000000407187825 */
/* 0x000fc600078e0216 */
/*0390*/ LDG.E R21, [R22.64] ; /* 0x0000000416157981 */
/* 0x0000a8000c1e1900 */
/*03a0*/ LDG.E R29, [R24.64] ; /* 0x00000004181d7981 */
/* 0x0002a2000c1e1900 */
/*03b0*/ FFMA R16, R15, R14, R16 ; /* 0x0000000e0f107223 */
/* 0x008fe40000000010 */
/*03c0*/ IMAD.WIDE R14, R7.reuse, 0x4, R24 ; /* 0x00000004070e7825 */
/* 0x040fe200078e0218 */
/*03d0*/ LDG.E R23, [R12.64+0x20] ; /* 0x000020040c177981 */
/* 0x001ee6000c1e1900 */
/*03e0*/ FFMA R26, R26, R27, R16 ; /* 0x0000001b1a1a7223 */
/* 0x010fe20000000010 */
/*03f0*/ LDG.E R25, [R12.64+0x24] ; /* 0x000024040c197981 */
/* 0x002f22000c1e1900 */
/*0400*/ IMAD.WIDE R16, R7, 0x4, R14 ; /* 0x0000000407107825 */
/* 0x000fc600078e020e */
/*0410*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x0000e2000c1e1900 */
/*0420*/ FFMA R26, R19, R18, R26 ; /* 0x00000012131a7223 */
/* 0x020fe4000000001a */
/*0430*/ IMAD.WIDE R18, R7, 0x4, R16 ; /* 0x0000000407127825 */
/* 0x000fe200078e0210 */
/*0440*/ LDG.E R22, [R12.64+0x28] ; /* 0x000028040c167981 */
/* 0x000f66000c1e1900 */
/*0450*/ FFMA R26, R9, R8, R26 ; /* 0x00000008091a7223 */
/* 0x000fe2000000001a */
/*0460*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x000322000c1e1900 */
/*0470*/ IMAD.WIDE R8, R7, 0x4, R18 ; /* 0x0000000407087825 */
/* 0x000fc600078e0212 */
/*0480*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x000368000c1e1900 */
/*0490*/ LDG.E R24, [R8.64] ; /* 0x0000000408187981 */
/* 0x000568000c1e1900 */
/*04a0*/ LDG.E R15, [R12.64+0x2c] ; /* 0x00002c040c0f7981 */
/* 0x001f62000c1e1900 */
/*04b0*/ FFMA R26, R11, R10, R26 ; /* 0x0000000a0b1a7223 */
/* 0x000fe4000000001a */
/*04c0*/ IMAD.WIDE R10, R7, 0x4, R8 ; /* 0x00000004070a7825 */
/* 0x000fe200078e0208 */
/*04d0*/ LDG.E R17, [R12.64+0x30] ; /* 0x000030040c117981 */
/* 0x002f66000c1e1900 */
/*04e0*/ FFMA R26, R21, R20, R26 ; /* 0x00000014151a7223 */
/* 0x004fc4000000001a */
/*04f0*/ IMAD.WIDE R20, R7, 0x4, R10 ; /* 0x0000000407147825 */
/* 0x000fe400078e020a */
/*0500*/ LDG.E R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x0000a4000c1e1900 */
/*0510*/ FFMA R28, R29, R28, R26 ; /* 0x0000001c1d1c7223 */
/* 0x000fe4000000001a */
/*0520*/ IMAD.WIDE R26, R7.reuse, 0x4, R20 ; /* 0x00000004071a7825 */
/* 0x040fe200078e0214 */
/*0530*/ LDG.E R29, [R12.64+0x34] ; /* 0x000034040c1d7981 */
/* 0x000ea8000c1e1900 */
/*0540*/ LDG.E R20, [R20.64] ; /* 0x0000000414147981 */
/* 0x0002a2000c1e1900 */
/*0550*/ IMAD.WIDE R8, R7, 0x4, R26 ; /* 0x0000000407087825 */
/* 0x000fc600078e021a */
/*0560*/ LDG.E R19, [R26.64] ; /* 0x000000041a137981 */
/* 0x0006a8000c1e1900 */
/*0570*/ LDG.E R11, [R8.64] ; /* 0x00000004080b7981 */
/* 0x0010a8000c1e1900 */
/*0580*/ LDG.E R21, [R12.64+0x38] ; /* 0x000038040c157981 */
/* 0x002ea8000c1e1900 */
/*0590*/ LDG.E R26, [R12.64+0x3c] ; /* 0x00003c040c1a7981 */
/* 0x008ee2000c1e1900 */
/*05a0*/ FFMA R14, R14, R23, R28 ; /* 0x000000170e0e7223 */
/* 0x000fc8000000001c */
/*05b0*/ FFMA R25, R16, R25, R14 ; /* 0x0000001910197223 */
/* 0x010fe2000000000e */
/*05c0*/ IADD3 R6, R6, -0x10, RZ ; /* 0xfffffff006067810 */
/* 0x000fc60007ffe0ff */
/*05d0*/ FFMA R18, R18, R22, R25 ; /* 0x0000001612127223 */
/* 0x020fe20000000019 */
/*05e0*/ ISETP.GT.AND P1, PT, R6, 0xc, PT ; /* 0x0000000c0600780c */
/* 0x000fc60003f24270 */
/*05f0*/ FFMA R15, R24, R15, R18 ; /* 0x0000000f180f7223 */
/* 0x000fe20000000012 */
/*0600*/ UIADD3 UR6, UP0, UR6, 0x40, URZ ; /* 0x0000004006067890 */
/* 0x000fe2000ff1e03f */
/*0610*/ IMAD.WIDE R8, R7, 0x4, R8 ; /* 0x0000000407087825 */
/* 0x001fc600078e0208 */
/*0620*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0630*/ IADD3 R2, R2, 0x10, RZ ; /* 0x0000001002027810 */
/* 0x000fe20007ffe0ff */
/*0640*/ FFMA R10, R10, R17, R15 ; /* 0x000000110a0a7223 */
/* 0x004fc8000000000f */
/*0650*/ FFMA R10, R20, R29, R10 ; /* 0x0000001d140a7223 */
/* 0x000fc8000000000a */
/*0660*/ FFMA R10, R19, R21, R10 ; /* 0x00000015130a7223 */
/* 0x000fc8000000000a */
/*0670*/ FFMA R24, R11, R26, R10 ; /* 0x0000001a0b187223 */
/* 0x008fe2000000000a */
/*0680*/ @P1 BRA 0x1f0 ; /* 0xfffffb6000001947 */
/* 0x000fea000383ffff */
/*0690*/ ISETP.GT.AND P1, PT, R6, 0x4, PT ; /* 0x000000040600780c */
/* 0x000fda0003f24270 */
/*06a0*/ @!P1 BRA 0x940 ; /* 0x0000029000009947 */
/* 0x000fea0003800000 */
/*06b0*/ MOV R7, c[0x0][0x17c] ; /* 0x00005f0000077a02 */
/* 0x000fe20000000f00 */
/*06c0*/ LDG.E R23, [R8.64] ; /* 0x0000000408177981 */
/* 0x0000a2000c1e1900 */
/*06d0*/ MOV R10, UR6 ; /* 0x00000006000a7c02 */
/* 0x000fe40008000f00 */
/*06e0*/ MOV R11, UR7 ; /* 0x00000007000b7c02 */
/* 0x000fe20008000f00 */
/*06f0*/ IMAD.WIDE R16, R7, 0x4, R8 ; /* 0x0000000407107825 */
/* 0x000fc800078e0208 */
/*0700*/ IMAD.WIDE R10, R5, 0x4, R10 ; /* 0x00000004050a7825 */
/* 0x000fc800078e020a */
/*0710*/ IMAD.WIDE R12, R7.reuse, 0x4, R16 ; /* 0x00000004070c7825 */
/* 0x040fe200078e0210 */
/*0720*/ LDG.E R22, [R10.64] ; /* 0x000000040a167981 */
/* 0x000ea8000c1e1900 */
/*0730*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x0002e2000c1e1900 */
/*0740*/ IMAD.WIDE R14, R7, 0x4, R12 ; /* 0x00000004070e7825 */
/* 0x000fc600078e020c */
/*0750*/ LDG.E R25, [R10.64+0x4] ; /* 0x000004040a197981 */
/* 0x000ee6000c1e1900 */
/*0760*/ IMAD.WIDE R18, R7.reuse, 0x4, R14 ; /* 0x0000000407127825 */
/* 0x040fe200078e020e */
/*0770*/ LDG.E R26, [R12.64] ; /* 0x000000040c1a7981 */
/* 0x000968000c1e1900 */
/*0780*/ LDG.E R27, [R10.64+0x8] ; /* 0x000008040a1b7981 */
/* 0x000f62000c1e1900 */
/*0790*/ IMAD.WIDE R20, R7, 0x4, R18 ; /* 0x0000000407147825 */
/* 0x000fc600078e0212 */
/*07a0*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000368000c1e1900 */
/*07b0*/ LDG.E R29, [R10.64+0xc] ; /* 0x00000c040a1d7981 */
/* 0x000f62000c1e1900 */
/*07c0*/ IMAD.WIDE R8, R7, 0x4, R20 ; /* 0x0000000407087825 */
/* 0x001fc600078e0214 */
/*07d0*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x000168000c1e1900 */
/*07e0*/ LDG.E R28, [R10.64+0x10] ; /* 0x000010040a1c7981 */
/* 0x000f62000c1e1900 */
/*07f0*/ IMAD.WIDE R12, R7, 0x4, R8 ; /* 0x00000004070c7825 */
/* 0x010fc600078e0208 */
/*0800*/ LDG.E R20, [R20.64] ; /* 0x0000000414147981 */
/* 0x000968000c1e1900 */
/*0810*/ LDG.E R15, [R10.64+0x14] ; /* 0x000014040a0f7981 */
/* 0x002f68000c1e1900 */
/*0820*/ LDG.E R17, [R8.64] ; /* 0x0000000408117981 */
/* 0x000368000c1e1900 */
/*0830*/ LDG.E R21, [R10.64+0x1c] ; /* 0x00001c040a157981 */
/* 0x010f28000c1e1900 */
/*0840*/ LDG.E R19, [R12.64] ; /* 0x000000040c137981 */
/* 0x001f28000c1e1900 */
/*0850*/ LDG.E R8, [R10.64+0x18] ; /* 0x000018040a087981 */
/* 0x002f22000c1e1900 */
/*0860*/ UIADD3 UR6, UP0, UR6, 0x20, URZ ; /* 0x0000002006067890 */
/* 0x000fe2000ff1e03f */
/*0870*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc40003f0e170 */
/*0880*/ IADD3 R2, R2, 0x8, RZ ; /* 0x0000000802027810 */
/* 0x000fe40007ffe0ff */
/*0890*/ IADD3 R6, R6, -0x8, RZ ; /* 0xfffffff806067810 */
/* 0x000fe20007ffe0ff */
/*08a0*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*08b0*/ FFMA R22, R23, R22, R24 ; /* 0x0000001617167223 */
/* 0x004fc80000000018 */
/*08c0*/ FFMA R16, R16, R25, R22 ; /* 0x0000001910107223 */
/* 0x008fc80000000016 */
/*08d0*/ FFMA R16, R26, R27, R16 ; /* 0x0000001b1a107223 */
/* 0x020fc80000000010 */
/*08e0*/ FFMA R29, R14, R29, R16 ; /* 0x0000001d0e1d7223 */
/* 0x000fc80000000010 */
/*08f0*/ FFMA R18, R18, R28, R29 ; /* 0x0000001c12127223 */
/* 0x000fc8000000001d */
/*0900*/ FFMA R15, R20, R15, R18 ; /* 0x0000000f140f7223 */
/* 0x000fc80000000012 */
/*0910*/ FFMA R24, R17, R8, R15 ; /* 0x0000000811187223 */
/* 0x010fe4000000000f */
/*0920*/ IMAD.WIDE R8, R7, 0x4, R12 ; /* 0x0000000407087825 */
/* 0x000fc800078e020c */
/*0930*/ FFMA R24, R19, R21, R24 ; /* 0x0000001513187223 */
/* 0x000fe40000000018 */
/*0940*/ ISETP.NE.OR P0, PT, R6, RZ, P0 ; /* 0x000000ff0600720c */
/* 0x000fda0000705670 */
/*0950*/ @!P0 BRA 0xb00 ; /* 0x000001a000008947 */
/* 0x000fea0003800000 */
/*0960*/ MOV R10, UR6 ; /* 0x00000006000a7c02 */
/* 0x000fe40008000f00 */
/*0970*/ MOV R11, UR7 ; /* 0x00000007000b7c02 */
/* 0x000fe40008000f00 */
/*0980*/ MOV R7, c[0x0][0x17c] ; /* 0x00005f0000077a02 */
/* 0x000fc60000000f00 */
/*0990*/ IMAD.WIDE R10, R5, 0x4, R10 ; /* 0x00000004050a7825 */
/* 0x000fc800078e020a */
/*09a0*/ IMAD.WIDE R16, R7.reuse, 0x4, R8 ; /* 0x0000000407107825 */
/* 0x040fe200078e0208 */
/*09b0*/ LDG.E R18, [R10.64] ; /* 0x000000040a127981 */
/* 0x000ea8000c1e1900 */
/*09c0*/ LDG.E R9, [R8.64] ; /* 0x0000000408097981 */
/* 0x000ea2000c1e1900 */
/*09d0*/ IMAD.WIDE R12, R7, 0x4, R16 ; /* 0x00000004070c7825 */
/* 0x000fc600078e0210 */
/*09e0*/ LDG.E R17, [R16.64] ; /* 0x0000000410117981 */
/* 0x000ee8000c1e1900 */
/*09f0*/ LDG.E R19, [R10.64+0x4] ; /* 0x000004040a137981 */
/* 0x000ee2000c1e1900 */
/*0a00*/ IMAD.WIDE R14, R7, 0x4, R12 ; /* 0x00000004070e7825 */
/* 0x000fc600078e020c */
/*0a10*/ LDG.E R21, [R12.64] ; /* 0x000000040c157981 */
/* 0x000f28000c1e1900 */
/*0a20*/ LDG.E R20, [R10.64+0x8] ; /* 0x000008040a147981 */
/* 0x000f28000c1e1900 */
/*0a30*/ LDG.E R22, [R10.64+0xc] ; /* 0x00000c040a167981 */
/* 0x000f68000c1e1900 */
/*0a40*/ LDG.E R23, [R14.64] ; /* 0x000000040e177981 */
/* 0x000f62000c1e1900 */
/*0a50*/ IADD3 R6, R6, -0x4, RZ ; /* 0xfffffffc06067810 */
/* 0x000fc80007ffe0ff */
/*0a60*/ ISETP.NE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe20003f05270 */
/*0a70*/ UIADD3 UR6, UP0, UR6, 0x10, URZ ; /* 0x0000001006067890 */
/* 0x000fe2000ff1e03f */
/*0a80*/ IADD3 R2, R2, 0x4, RZ ; /* 0x0000000402027810 */
/* 0x000fc60007ffe0ff */
/*0a90*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0aa0*/ FFMA R18, R9, R18, R24 ; /* 0x0000001209127223 */
/* 0x004fc80000000018 */
/*0ab0*/ FFMA R18, R17, R19, R18 ; /* 0x0000001311127223 */
/* 0x008fe40000000012 */
/*0ac0*/ IMAD.WIDE R8, R7, 0x4, R14 ; /* 0x0000000407087825 */
/* 0x000fc800078e020e */
/*0ad0*/ FFMA R18, R21, R20, R18 ; /* 0x0000001415127223 */
/* 0x010fc80000000012 */
/*0ae0*/ FFMA R24, R23, R22, R18 ; /* 0x0000001617187223 */
/* 0x020fe20000000012 */
/*0af0*/ @P0 BRA 0x960 ; /* 0xfffffe6000000947 */
/* 0x000fea000383ffff */
/*0b00*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fda0003f05270 */
/*0b10*/ @!P0 BRA 0xc10 ; /* 0x000000f000008947 */
/* 0x000fea0003800000 */
/*0b20*/ HFMA2.MMA R9, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff097435 */
/* 0x000fe200000001ff */
/*0b30*/ IADD3 R6, R5, R2, RZ ; /* 0x0000000205067210 */
/* 0x000fe20007ffe0ff */
/*0b40*/ IMAD R2, R2, c[0x0][0x17c], R3 ; /* 0x00005f0002027a24 */
/* 0x000fd000078e0203 */
/*0b50*/ IMAD.WIDE R6, R6, R9, c[0x0][0x160] ; /* 0x0000580006067625 */
/* 0x000fc800078e0209 */
/*0b60*/ IMAD.WIDE R8, R2, R9, c[0x0][0x168] ; /* 0x00005a0002087625 */
/* 0x000fca00078e0209 */
/*0b70*/ LDG.E R5, [R8.64] ; /* 0x0000000408057981 */
/* 0x0000a8000c1e1900 */
/*0b80*/ LDG.E R2, [R6.64] ; /* 0x0000000406027981 */
/* 0x0002a2000c1e1900 */
/*0b90*/ IADD3 R4, R4, -0x1, RZ ; /* 0xffffffff04047810 */
/* 0x000fe40007ffe0ff */
/*0ba0*/ MOV R11, c[0x0][0x17c] ; /* 0x00005f00000b7a02 */
/* 0x000fe40000000f00 */
/*0bb0*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fc60003f05270 */
/*0bc0*/ IMAD.WIDE R8, R11, 0x4, R8 ; /* 0x000000040b087825 */
/* 0x001fe200078e0208 */
/*0bd0*/ IADD3 R6, P1, R6, 0x4, RZ ; /* 0x0000000406067810 */
/* 0x002fc80007f3e0ff */
/*0be0*/ IADD3.X R7, RZ, R7, RZ, P1, !PT ; /* 0x00000007ff077210 */
/* 0x000fe20000ffe4ff */
/*0bf0*/ FFMA R24, R5, R2, R24 ; /* 0x0000000205187223 */
/* 0x004fc80000000018 */
/*0c00*/ @P0 BRA 0xb70 ; /* 0xffffff6000000947 */
/* 0x000fea000383ffff */
/*0c10*/ MOV R2, 0x4 ; /* 0x0000000400027802 */
/* 0x000fe20000000f00 */
/*0c20*/ IMAD R3, R0, c[0x0][0x17c], R3 ; /* 0x00005f0000037a24 */
/* 0x000fc800078e0203 */
/*0c30*/ IMAD.WIDE R2, R3, R2, c[0x0][0x170] ; /* 0x00005c0003027625 */
/* 0x000fca00078e0202 */
/*0c40*/ STG.E [R2.64], R24 ; /* 0x0000001802007986 */
/* 0x000fe2000c101904 */
/*0c50*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0c60*/ BRA 0xc60; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0c70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ca0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ce0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <stdlib.h>
#include <cuda_runtime_api.h>
#define BASE_TYPE float
__global__ void mult(const BASE_TYPE *a, const BASE_TYPE *b, BASE_TYPE *c, const int N, const int M)
{
int i = N * (blockDim.y * blockIdx.y + threadIdx.y);
int j = blockDim.x * blockIdx.x + threadIdx.x;
BASE_TYPE sum = 0;
for (int k = 0; k < N; k++)
{
sum += a[i + k] * b[k * M + j];
}
int id = M * (blockDim.y * blockIdx.y + threadIdx.y) + blockDim.x * blockIdx.x + threadIdx.x;
c[id] = sum;
}
BASE_TYPE* gen_array(const int N)
{
BASE_TYPE *a = new BASE_TYPE[N * N];
for (int i = 0; i < N; i++)
{
for (int j = 0; j < N; j++)
a[i * N + j] = i * N + j;
}
return a;
}
void print_array(BASE_TYPE *a, const int N)
{
for (int i = 0; i < N; i++)
{
for (int j = 0; j < N; j++)
printf("%5.0f ", a[i *N + j]);
printf("\n");
}
printf("\n");
}
void cuda_init_array(BASE_TYPE **dev, const BASE_TYPE *host, const size_t size)
{
cudaError_t err;
err = cudaMalloc((void **)dev, size);
if (err != cudaSuccess)
throw err;
if (host != NULL)
{
err = cudaMemcpy(*dev, host, size, cudaMemcpyHostToDevice);
if (err != cudaSuccess)
throw err;
}
}
void cuda_init_grid_and_block(dim3 *grid, dim3 *block, const int N)
{
*grid = dim3(1);
*block = dim3(N, N, 1);
printf("Block %d %d %d\n", block->x, block->y, block->z);
printf("Grid %d %d %d\n", grid->x, grid->y, grid->z);
}
int main()
{
const int N = 10;
const size_t size = N * N * sizeof(BASE_TYPE);
cudaError_t err;
dim3 threadsPerBlock, blocksPerGrid;
cuda_init_grid_and_block(&blocksPerGrid, &threadsPerBlock, N);
BASE_TYPE *host_a = gen_array(N), *host_b = gen_array(N);
BASE_TYPE *dev_a, *dev_b, *dev_c;
if (host_a == NULL)
{
fprintf(stderr, "Failed to allocate host vectors!\n");
exit(EXIT_FAILURE);
}
print_array(host_a, N);
print_array(host_b, N);
try
{
cuda_init_array(&dev_a, host_a, size);
cuda_init_array(&dev_b, host_b, size);
cuda_init_array(&dev_c, NULL, size);
}
catch (cudaError_t err)
{
fprintf(stderr, "Failed to allocate device (error code: %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
mult<<<blocksPerGrid, threadsPerBlock>>>(dev_a, dev_b, dev_c, N, N);
err = cudaMemcpy(host_a, dev_c, size, cudaMemcpyDeviceToHost);
if (err != cudaSuccess)
{
fprintf(stderr, "Failed to allocate device (error code: %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
print_array(host_a, N);
cudaFree(dev_a);
cudaFree(dev_b);
delete[] host_a;
return 0;
} | .file "tmpxft_000904be_00000000-6_main.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2064:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2064:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z9gen_arrayi
.type _Z9gen_arrayi, @function
_Z9gen_arrayi:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movl %edi, %ebx
imull %edi, %edi
movslq %edi, %rdi
salq $2, %rdi
call _Znam@PLT
testl %ebx, %ebx
jle .L3
movslq %ebx, %r10
salq $2, %r10
movq %rax, %r9
movl %ebx, %esi
movl $0, %r8d
movl $0, %edi
.L5:
movq %r9, %rcx
movl %r8d, %edx
.L6:
pxor %xmm0, %xmm0
cvtsi2ssl %edx, %xmm0
movss %xmm0, (%rcx)
addl $1, %edx
addq $4, %rcx
cmpl %esi, %edx
jne .L6
addl $1, %edi
addl %ebx, %r8d
addq %r10, %r9
addl %ebx, %esi
cmpl %edi, %ebx
jne .L5
.L3:
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _Z9gen_arrayi, .-_Z9gen_arrayi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%5.0f "
.LC1:
.string "\n"
.text
.globl _Z11print_arrayPfi
.type _Z11print_arrayPfi, @function
_Z11print_arrayPfi:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $24, %rsp
.cfi_def_cfa_offset 80
movl %esi, 12(%rsp)
testl %esi, %esi
jle .L10
movslq %esi, %r14
leaq 0(,%r14,4), %r15
leaq (%rdi,%r15), %rbp
negq %r14
salq $2, %r14
movl $0, %r13d
leaq .LC0(%rip), %r12
.L11:
leaq 0(%rbp,%r14), %rbx
.L12:
pxor %xmm0, %xmm0
cvtss2sd (%rbx), %xmm0
movq %r12, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %rbp, %rbx
jne .L12
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %r13d
addq %r15, %rbp
cmpl %r13d, 12(%rsp)
jne .L11
.L10:
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _Z11print_arrayPfi, .-_Z11print_arrayPfi
.globl _Z15cuda_init_arrayPPfPKfm
.type _Z15cuda_init_arrayPPfPKfm, @function
_Z15cuda_init_arrayPPfPKfm:
.LFB2059:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $8, %rsp
.cfi_def_cfa_offset 48
movq %rdi, %r12
movq %rsi, %rbx
movq %rdx, %rbp
movq %rdx, %rsi
call cudaMalloc@PLT
testl %eax, %eax
jne .L19
testq %rbx, %rbx
je .L15
movq (%r12), %rdi
movl $1, %ecx
movq %rbp, %rdx
movq %rbx, %rsi
call cudaMemcpy@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L20
.L15:
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
movl %eax, %r13d
movl $4, %edi
call __cxa_allocate_exception@PLT
movq %rax, %rdi
movl %r13d, (%rax)
movl $0, %edx
leaq _ZTI9cudaError(%rip), %rsi
call __cxa_throw@PLT
.L20:
movl $4, %edi
call __cxa_allocate_exception@PLT
movq %rax, %rdi
movl %ebx, (%rax)
movl $0, %edx
leaq _ZTI9cudaError(%rip), %rsi
call __cxa_throw@PLT
.cfi_endproc
.LFE2059:
.size _Z15cuda_init_arrayPPfPKfm, .-_Z15cuda_init_arrayPPfPKfm
.section .rodata.str1.1
.LC2:
.string "Block %d %d %d\n"
.LC3:
.string "Grid %d %d %d\n"
.text
.globl _Z24cuda_init_grid_and_blockP4dim3S0_i
.type _Z24cuda_init_grid_and_blockP4dim3S0_i, @function
_Z24cuda_init_grid_and_blockP4dim3S0_i:
.LFB2060:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movq %rdi, %rbx
movl $1, (%rdi)
movl $1, 4(%rdi)
movl $1, 8(%rdi)
movl %edx, (%rsi)
movl %edx, 4(%rsi)
movl $1, 8(%rsi)
movl $1, %r8d
movl %edx, %ecx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 4(%rbx), %ecx
movl (%rbx), %edx
movl 8(%rbx), %r8d
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _Z24cuda_init_grid_and_blockP4dim3S0_i, .-_Z24cuda_init_grid_and_blockP4dim3S0_i
.globl _Z31__device_stub__Z4multPKfS0_PfiiPKfS0_Pfii
.type _Z31__device_stub__Z4multPKfS0_PfiiPKfS0_Pfii, @function
_Z31__device_stub__Z4multPKfS0_PfiiPKfS0_Pfii:
.LFB2086:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L27
.L23:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L28
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L27:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z4multPKfS0_Pfii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L23
.L28:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2086:
.size _Z31__device_stub__Z4multPKfS0_PfiiPKfS0_Pfii, .-_Z31__device_stub__Z4multPKfS0_PfiiPKfS0_Pfii
.globl _Z4multPKfS0_Pfii
.type _Z4multPKfS0_Pfii, @function
_Z4multPKfS0_Pfii:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z4multPKfS0_PfiiPKfS0_Pfii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _Z4multPKfS0_Pfii, .-_Z4multPKfS0_Pfii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC4:
.string "Failed to allocate host vectors!\n"
.align 8
.LC5:
.string "Failed to allocate device (error code: %s)!\n"
.text
.globl main
.type main, @function
main:
.LFB2061:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA2061
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $72, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 32(%rsp), %rsi
leaq 44(%rsp), %rdi
movl $10, %edx
.LEHB0:
call _Z24cuda_init_grid_and_blockP4dim3S0_i
movl $10, %edi
call _Z9gen_arrayi
movq %rax, %rbx
movl $10, %edi
call _Z9gen_arrayi
testq %rbx, %rbx
je .L45
movq %rax, %rbp
movl $10, %esi
movq %rbx, %rdi
call _Z11print_arrayPfi
movl $10, %esi
movq %rbp, %rdi
call _Z11print_arrayPfi
.LEHE0:
leaq 8(%rsp), %rdi
movl $400, %edx
movq %rbx, %rsi
.LEHB1:
call _Z15cuda_init_arrayPPfPKfm
.LEHE1:
jmp .L46
.L45:
leaq .LC4(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
.LEHB2:
call __fprintf_chk@PLT
.LEHE2:
movl $1, %edi
call exit@PLT
.L46:
leaq 16(%rsp), %rdi
movl $400, %edx
movq %rbp, %rsi
.LEHB3:
call _Z15cuda_init_arrayPPfPKfm
leaq 24(%rsp), %rdi
movl $400, %edx
movl $0, %esi
call _Z15cuda_init_arrayPPfPKfm
.LEHE3:
movl 40(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 32(%rsp), %rdx
movq 44(%rsp), %rdi
movl 52(%rsp), %esi
.LEHB4:
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L47
.L33:
movl $2, %ecx
movl $400, %edx
movq 24(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L48
movl $10, %esi
movq %rbx, %rdi
call _Z11print_arrayPfi
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq %rbx, %rdi
call _ZdaPv@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L49
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L47:
.cfi_restore_state
movl $10, %r8d
movl $10, %ecx
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z31__device_stub__Z4multPKfS0_PfiiPKfS0_Pfii
jmp .L33
.L48:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC5(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L41:
endbr64
movq %rax, %rdi
cmpq $1, %rdx
je .L36
movq 56(%rsp), %rax
subq %fs:40, %rax
je .L37
call __stack_chk_fail@PLT
.L37:
call _Unwind_Resume@PLT
.LEHE4:
.L36:
call __cxa_begin_catch@PLT
movl (%rax), %edi
.LEHB5:
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC5(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
.LEHE5:
movl $1, %edi
call exit@PLT
.L42:
endbr64
movq %rax, %rbx
call __cxa_end_catch@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
je .L39
call __stack_chk_fail@PLT
.L39:
movq %rbx, %rdi
.LEHB6:
call _Unwind_Resume@PLT
.LEHE6:
.L49:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2061:
.globl __gxx_personality_v0
.section .gcc_except_table,"a",@progbits
.align 4
.LLSDA2061:
.byte 0xff
.byte 0x9b
.uleb128 .LLSDATT2061-.LLSDATTD2061
.LLSDATTD2061:
.byte 0x1
.uleb128 .LLSDACSE2061-.LLSDACSB2061
.LLSDACSB2061:
.uleb128 .LEHB0-.LFB2061
.uleb128 .LEHE0-.LEHB0
.uleb128 0
.uleb128 0
.uleb128 .LEHB1-.LFB2061
.uleb128 .LEHE1-.LEHB1
.uleb128 .L41-.LFB2061
.uleb128 0x1
.uleb128 .LEHB2-.LFB2061
.uleb128 .LEHE2-.LEHB2
.uleb128 0
.uleb128 0
.uleb128 .LEHB3-.LFB2061
.uleb128 .LEHE3-.LEHB3
.uleb128 .L41-.LFB2061
.uleb128 0x1
.uleb128 .LEHB4-.LFB2061
.uleb128 .LEHE4-.LEHB4
.uleb128 0
.uleb128 0
.uleb128 .LEHB5-.LFB2061
.uleb128 .LEHE5-.LEHB5
.uleb128 .L42-.LFB2061
.uleb128 0
.uleb128 .LEHB6-.LFB2061
.uleb128 .LEHE6-.LEHB6
.uleb128 0
.uleb128 0
.LLSDACSE2061:
.byte 0x1
.byte 0
.align 4
.long DW.ref._ZTI9cudaError-.
.LLSDATT2061:
.text
.size main, .-main
.section .rodata.str1.1
.LC6:
.string "_Z4multPKfS0_Pfii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2089:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _Z4multPKfS0_Pfii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2089:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.weak _ZTS9cudaError
.section .rodata._ZTS9cudaError,"aG",@progbits,_ZTS9cudaError,comdat
.align 8
.type _ZTS9cudaError, @object
.size _ZTS9cudaError, 11
_ZTS9cudaError:
.string "9cudaError"
.weak _ZTI9cudaError
.section .data.rel.ro._ZTI9cudaError,"awG",@progbits,_ZTI9cudaError,comdat
.align 8
.type _ZTI9cudaError, @object
.size _ZTI9cudaError, 16
_ZTI9cudaError:
.quad _ZTVN10__cxxabiv116__enum_type_infoE+16
.quad _ZTS9cudaError
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.hidden DW.ref._ZTI9cudaError
.weak DW.ref._ZTI9cudaError
.section .data.rel.local.DW.ref._ZTI9cudaError,"awG",@progbits,DW.ref._ZTI9cudaError,comdat
.align 8
.type DW.ref._ZTI9cudaError, @object
.size DW.ref._ZTI9cudaError, 8
DW.ref._ZTI9cudaError:
.quad _ZTI9cudaError
.hidden DW.ref.__gxx_personality_v0
.weak DW.ref.__gxx_personality_v0
.section .data.rel.local.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat
.align 8
.type DW.ref.__gxx_personality_v0, @object
.size DW.ref.__gxx_personality_v0, 8
DW.ref.__gxx_personality_v0:
.quad __gxx_personality_v0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <stdlib.h>
#include <cuda_runtime_api.h>
#define BASE_TYPE float
__global__ void mult(const BASE_TYPE *a, const BASE_TYPE *b, BASE_TYPE *c, const int N, const int M)
{
int i = N * (blockDim.y * blockIdx.y + threadIdx.y);
int j = blockDim.x * blockIdx.x + threadIdx.x;
BASE_TYPE sum = 0;
for (int k = 0; k < N; k++)
{
sum += a[i + k] * b[k * M + j];
}
int id = M * (blockDim.y * blockIdx.y + threadIdx.y) + blockDim.x * blockIdx.x + threadIdx.x;
c[id] = sum;
}
BASE_TYPE* gen_array(const int N)
{
BASE_TYPE *a = new BASE_TYPE[N * N];
for (int i = 0; i < N; i++)
{
for (int j = 0; j < N; j++)
a[i * N + j] = i * N + j;
}
return a;
}
void print_array(BASE_TYPE *a, const int N)
{
for (int i = 0; i < N; i++)
{
for (int j = 0; j < N; j++)
printf("%5.0f ", a[i *N + j]);
printf("\n");
}
printf("\n");
}
void cuda_init_array(BASE_TYPE **dev, const BASE_TYPE *host, const size_t size)
{
cudaError_t err;
err = cudaMalloc((void **)dev, size);
if (err != cudaSuccess)
throw err;
if (host != NULL)
{
err = cudaMemcpy(*dev, host, size, cudaMemcpyHostToDevice);
if (err != cudaSuccess)
throw err;
}
}
void cuda_init_grid_and_block(dim3 *grid, dim3 *block, const int N)
{
*grid = dim3(1);
*block = dim3(N, N, 1);
printf("Block %d %d %d\n", block->x, block->y, block->z);
printf("Grid %d %d %d\n", grid->x, grid->y, grid->z);
}
int main()
{
const int N = 10;
const size_t size = N * N * sizeof(BASE_TYPE);
cudaError_t err;
dim3 threadsPerBlock, blocksPerGrid;
cuda_init_grid_and_block(&blocksPerGrid, &threadsPerBlock, N);
BASE_TYPE *host_a = gen_array(N), *host_b = gen_array(N);
BASE_TYPE *dev_a, *dev_b, *dev_c;
if (host_a == NULL)
{
fprintf(stderr, "Failed to allocate host vectors!\n");
exit(EXIT_FAILURE);
}
print_array(host_a, N);
print_array(host_b, N);
try
{
cuda_init_array(&dev_a, host_a, size);
cuda_init_array(&dev_b, host_b, size);
cuda_init_array(&dev_c, NULL, size);
}
catch (cudaError_t err)
{
fprintf(stderr, "Failed to allocate device (error code: %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
mult<<<blocksPerGrid, threadsPerBlock>>>(dev_a, dev_b, dev_c, N, N);
err = cudaMemcpy(host_a, dev_c, size, cudaMemcpyDeviceToHost);
if (err != cudaSuccess)
{
fprintf(stderr, "Failed to allocate device (error code: %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
print_array(host_a, N);
cudaFree(dev_a);
cudaFree(dev_b);
delete[] host_a;
return 0;
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <hip/hip_runtime_api.h>
#define BASE_TYPE float
__global__ void mult(const BASE_TYPE *a, const BASE_TYPE *b, BASE_TYPE *c, const int N, const int M)
{
int i = N * (blockDim.y * blockIdx.y + threadIdx.y);
int j = blockDim.x * blockIdx.x + threadIdx.x;
BASE_TYPE sum = 0;
for (int k = 0; k < N; k++)
{
sum += a[i + k] * b[k * M + j];
}
int id = M * (blockDim.y * blockIdx.y + threadIdx.y) + blockDim.x * blockIdx.x + threadIdx.x;
c[id] = sum;
}
BASE_TYPE* gen_array(const int N)
{
BASE_TYPE *a = new BASE_TYPE[N * N];
for (int i = 0; i < N; i++)
{
for (int j = 0; j < N; j++)
a[i * N + j] = i * N + j;
}
return a;
}
void print_array(BASE_TYPE *a, const int N)
{
for (int i = 0; i < N; i++)
{
for (int j = 0; j < N; j++)
printf("%5.0f ", a[i *N + j]);
printf("\n");
}
printf("\n");
}
void cuda_init_array(BASE_TYPE **dev, const BASE_TYPE *host, const size_t size)
{
hipError_t err;
err = hipMalloc((void **)dev, size);
if (err != hipSuccess)
throw err;
if (host != NULL)
{
err = hipMemcpy(*dev, host, size, hipMemcpyHostToDevice);
if (err != hipSuccess)
throw err;
}
}
void cuda_init_grid_and_block(dim3 *grid, dim3 *block, const int N)
{
*grid = dim3(1);
*block = dim3(N, N, 1);
printf("Block %d %d %d\n", block->x, block->y, block->z);
printf("Grid %d %d %d\n", grid->x, grid->y, grid->z);
}
int main()
{
const int N = 10;
const size_t size = N * N * sizeof(BASE_TYPE);
hipError_t err;
dim3 threadsPerBlock, blocksPerGrid;
cuda_init_grid_and_block(&blocksPerGrid, &threadsPerBlock, N);
BASE_TYPE *host_a = gen_array(N), *host_b = gen_array(N);
BASE_TYPE *dev_a, *dev_b, *dev_c;
if (host_a == NULL)
{
fprintf(stderr, "Failed to allocate host vectors!\n");
exit(EXIT_FAILURE);
}
print_array(host_a, N);
print_array(host_b, N);
try
{
cuda_init_array(&dev_a, host_a, size);
cuda_init_array(&dev_b, host_b, size);
cuda_init_array(&dev_c, NULL, size);
}
catch (hipError_t err)
{
fprintf(stderr, "Failed to allocate device (error code: %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
mult<<<blocksPerGrid, threadsPerBlock>>>(dev_a, dev_b, dev_c, N, N);
err = hipMemcpy(host_a, dev_c, size, hipMemcpyDeviceToHost);
if (err != hipSuccess)
{
fprintf(stderr, "Failed to allocate device (error code: %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
print_array(host_a, N);
hipFree(dev_a);
hipFree(dev_b);
delete[] host_a;
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <hip/hip_runtime_api.h>
#define BASE_TYPE float
__global__ void mult(const BASE_TYPE *a, const BASE_TYPE *b, BASE_TYPE *c, const int N, const int M)
{
int i = N * (blockDim.y * blockIdx.y + threadIdx.y);
int j = blockDim.x * blockIdx.x + threadIdx.x;
BASE_TYPE sum = 0;
for (int k = 0; k < N; k++)
{
sum += a[i + k] * b[k * M + j];
}
int id = M * (blockDim.y * blockIdx.y + threadIdx.y) + blockDim.x * blockIdx.x + threadIdx.x;
c[id] = sum;
}
BASE_TYPE* gen_array(const int N)
{
BASE_TYPE *a = new BASE_TYPE[N * N];
for (int i = 0; i < N; i++)
{
for (int j = 0; j < N; j++)
a[i * N + j] = i * N + j;
}
return a;
}
void print_array(BASE_TYPE *a, const int N)
{
for (int i = 0; i < N; i++)
{
for (int j = 0; j < N; j++)
printf("%5.0f ", a[i *N + j]);
printf("\n");
}
printf("\n");
}
void cuda_init_array(BASE_TYPE **dev, const BASE_TYPE *host, const size_t size)
{
hipError_t err;
err = hipMalloc((void **)dev, size);
if (err != hipSuccess)
throw err;
if (host != NULL)
{
err = hipMemcpy(*dev, host, size, hipMemcpyHostToDevice);
if (err != hipSuccess)
throw err;
}
}
void cuda_init_grid_and_block(dim3 *grid, dim3 *block, const int N)
{
*grid = dim3(1);
*block = dim3(N, N, 1);
printf("Block %d %d %d\n", block->x, block->y, block->z);
printf("Grid %d %d %d\n", grid->x, grid->y, grid->z);
}
int main()
{
const int N = 10;
const size_t size = N * N * sizeof(BASE_TYPE);
hipError_t err;
dim3 threadsPerBlock, blocksPerGrid;
cuda_init_grid_and_block(&blocksPerGrid, &threadsPerBlock, N);
BASE_TYPE *host_a = gen_array(N), *host_b = gen_array(N);
BASE_TYPE *dev_a, *dev_b, *dev_c;
if (host_a == NULL)
{
fprintf(stderr, "Failed to allocate host vectors!\n");
exit(EXIT_FAILURE);
}
print_array(host_a, N);
print_array(host_b, N);
try
{
cuda_init_array(&dev_a, host_a, size);
cuda_init_array(&dev_b, host_b, size);
cuda_init_array(&dev_c, NULL, size);
}
catch (hipError_t err)
{
fprintf(stderr, "Failed to allocate device (error code: %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
mult<<<blocksPerGrid, threadsPerBlock>>>(dev_a, dev_b, dev_c, N, N);
err = hipMemcpy(host_a, dev_c, size, hipMemcpyDeviceToHost);
if (err != hipSuccess)
{
fprintf(stderr, "Failed to allocate device (error code: %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
print_array(host_a, N);
hipFree(dev_a);
hipFree(dev_b);
delete[] host_a;
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z4multPKfS0_Pfii
.globl _Z4multPKfS0_Pfii
.p2align 8
.type _Z4multPKfS0_Pfii,@function
_Z4multPKfS0_Pfii:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x2c
s_load_b64 s[2:3], s[0:1], 0x18
v_bfe_u32 v3, v0, 10, 10
v_and_b32_e32 v0, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s5, s4, 16
s_and_b32 s4, s4, 0xffff
v_mad_u64_u32 v[1:2], null, s15, s5, v[3:4]
s_cmp_lt_i32 s2, 1
s_mul_i32 s14, s14, s4
s_cbranch_scc1 .LBB0_3
s_load_b128 s[4:7], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_lo_u32 v2, v1, s2
v_mov_b32_e32 v6, 0
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[4:5], 2, v[2:3]
v_add_nc_u32_e32 v2, s14, v0
s_waitcnt lgkmcnt(0)
v_add_co_u32 v4, vcc_lo, s4, v4
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
.p2align 6
.LBB0_2:
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_ashrrev_i32_e32 v3, 31, v2
s_add_i32 s2, s2, -1
s_cmp_eq_u32 s2, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[7:8], 2, v[2:3]
v_add_nc_u32_e32 v2, s3, v2
v_add_co_u32 v7, vcc_lo, s6, v7
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v8, vcc_lo, s7, v8, vcc_lo
global_load_b32 v3, v[4:5], off
global_load_b32 v7, v[7:8], off
v_add_co_u32 v4, vcc_lo, v4, 4
v_add_co_ci_u32_e32 v5, vcc_lo, 0, v5, vcc_lo
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v6, v3, v7
s_cbranch_scc0 .LBB0_2
s_branch .LBB0_4
.LBB0_3:
v_mov_b32_e32 v6, 0
.LBB0_4:
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mul_lo_u32 v1, v1, s3
s_load_b64 s[0:1], s[0:1], 0x10
v_add3_u32 v0, s14, v0, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v6, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z4multPKfS0_Pfii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z4multPKfS0_Pfii, .Lfunc_end0-_Z4multPKfS0_Pfii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z4multPKfS0_Pfii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z4multPKfS0_Pfii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <hip/hip_runtime_api.h>
#define BASE_TYPE float
__global__ void mult(const BASE_TYPE *a, const BASE_TYPE *b, BASE_TYPE *c, const int N, const int M)
{
int i = N * (blockDim.y * blockIdx.y + threadIdx.y);
int j = blockDim.x * blockIdx.x + threadIdx.x;
BASE_TYPE sum = 0;
for (int k = 0; k < N; k++)
{
sum += a[i + k] * b[k * M + j];
}
int id = M * (blockDim.y * blockIdx.y + threadIdx.y) + blockDim.x * blockIdx.x + threadIdx.x;
c[id] = sum;
}
BASE_TYPE* gen_array(const int N)
{
BASE_TYPE *a = new BASE_TYPE[N * N];
for (int i = 0; i < N; i++)
{
for (int j = 0; j < N; j++)
a[i * N + j] = i * N + j;
}
return a;
}
void print_array(BASE_TYPE *a, const int N)
{
for (int i = 0; i < N; i++)
{
for (int j = 0; j < N; j++)
printf("%5.0f ", a[i *N + j]);
printf("\n");
}
printf("\n");
}
void cuda_init_array(BASE_TYPE **dev, const BASE_TYPE *host, const size_t size)
{
hipError_t err;
err = hipMalloc((void **)dev, size);
if (err != hipSuccess)
throw err;
if (host != NULL)
{
err = hipMemcpy(*dev, host, size, hipMemcpyHostToDevice);
if (err != hipSuccess)
throw err;
}
}
void cuda_init_grid_and_block(dim3 *grid, dim3 *block, const int N)
{
*grid = dim3(1);
*block = dim3(N, N, 1);
printf("Block %d %d %d\n", block->x, block->y, block->z);
printf("Grid %d %d %d\n", grid->x, grid->y, grid->z);
}
int main()
{
const int N = 10;
const size_t size = N * N * sizeof(BASE_TYPE);
hipError_t err;
dim3 threadsPerBlock, blocksPerGrid;
cuda_init_grid_and_block(&blocksPerGrid, &threadsPerBlock, N);
BASE_TYPE *host_a = gen_array(N), *host_b = gen_array(N);
BASE_TYPE *dev_a, *dev_b, *dev_c;
if (host_a == NULL)
{
fprintf(stderr, "Failed to allocate host vectors!\n");
exit(EXIT_FAILURE);
}
print_array(host_a, N);
print_array(host_b, N);
try
{
cuda_init_array(&dev_a, host_a, size);
cuda_init_array(&dev_b, host_b, size);
cuda_init_array(&dev_c, NULL, size);
}
catch (hipError_t err)
{
fprintf(stderr, "Failed to allocate device (error code: %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
mult<<<blocksPerGrid, threadsPerBlock>>>(dev_a, dev_b, dev_c, N, N);
err = hipMemcpy(host_a, dev_c, size, hipMemcpyDeviceToHost);
if (err != hipSuccess)
{
fprintf(stderr, "Failed to allocate device (error code: %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
print_array(host_a, N);
hipFree(dev_a);
hipFree(dev_b);
delete[] host_a;
return 0;
} | .text
.file "main.hip"
.globl _Z19__device_stub__multPKfS0_Pfii # -- Begin function _Z19__device_stub__multPKfS0_Pfii
.p2align 4, 0x90
.type _Z19__device_stub__multPKfS0_Pfii,@function
_Z19__device_stub__multPKfS0_Pfii: # @_Z19__device_stub__multPKfS0_Pfii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z4multPKfS0_Pfii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z19__device_stub__multPKfS0_Pfii, .Lfunc_end0-_Z19__device_stub__multPKfS0_Pfii
.cfi_endproc
# -- End function
.globl _Z9gen_arrayi # -- Begin function _Z9gen_arrayi
.p2align 4, 0x90
.type _Z9gen_arrayi,@function
_Z9gen_arrayi: # @_Z9gen_arrayi
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
movl %edi, %ebx
imull %edi, %edi
shlq $2, %rdi
callq _Znam
testl %ebx, %ebx
jle .LBB1_5
# %bb.1: # %.preheader.lr.ph
movl %ebx, %ecx
xorl %edx, %edx
xorl %esi, %esi
.p2align 4, 0x90
.LBB1_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_3 Depth 2
movl %edx, %edi
leaq (%rax,%rdi,4), %rdi
xorl %r8d, %r8d
.p2align 4, 0x90
.LBB1_3: # Parent Loop BB1_2 Depth=1
# => This Inner Loop Header: Depth=2
leal (%rdx,%r8), %r9d
xorps %xmm0, %xmm0
cvtsi2ss %r9d, %xmm0
movss %xmm0, (%rdi,%r8,4)
incq %r8
cmpq %r8, %rcx
jne .LBB1_3
# %bb.4: # %._crit_edge
# in Loop: Header=BB1_2 Depth=1
incq %rsi
addq %rcx, %rdx
cmpq %rcx, %rsi
jne .LBB1_2
.LBB1_5: # %._crit_edge19
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z9gen_arrayi, .Lfunc_end1-_Z9gen_arrayi
.cfi_endproc
# -- End function
.globl _Z11print_arrayPfi # -- Begin function _Z11print_arrayPfi
.p2align 4, 0x90
.type _Z11print_arrayPfi,@function
_Z11print_arrayPfi: # @_Z11print_arrayPfi
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
pushq %rax
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rdi, (%rsp) # 8-byte Spill
testl %esi, %esi
jle .LBB2_5
# %bb.1: # %.preheader.lr.ph
movl %esi, %ebx
movl %esi, %r15d
xorl %r12d, %r12d
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB2_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB2_3 Depth 2
movl %r12d, %eax
movq (%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax,4), %rbp
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB2_3: # Parent Loop BB2_2 Depth=1
# => This Inner Loop Header: Depth=2
movss (%rbp,%r14,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
incq %r14
cmpq %r14, %r15
jne .LBB2_3
# %bb.4: # %._crit_edge
# in Loop: Header=BB2_2 Depth=1
movl $10, %edi
callq putchar@PLT
incq %r13
addl %ebx, %r12d
cmpq %r15, %r13
jne .LBB2_2
.LBB2_5: # %._crit_edge14
movl $10, %edi
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
jmp putchar@PLT # TAILCALL
.Lfunc_end2:
.size _Z11print_arrayPfi, .Lfunc_end2-_Z11print_arrayPfi
.cfi_endproc
# -- End function
.globl _Z15cuda_init_arrayPPfPKfm # -- Begin function _Z15cuda_init_arrayPPfPKfm
.p2align 4, 0x90
.type _Z15cuda_init_arrayPPfPKfm,@function
_Z15cuda_init_arrayPPfPKfm: # @_Z15cuda_init_arrayPPfPKfm
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdx, %rbx
movq %rsi, %r14
movq %rdi, %r15
movq %rdx, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB3_4
# %bb.1:
testq %r14, %r14
je .LBB3_3
# %bb.2:
movq (%r15), %rdi
movq %r14, %rsi
movq %rbx, %rdx
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB3_4
.LBB3_3:
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB3_4:
.cfi_def_cfa_offset 32
movl $4, %edi
movl %eax, %ebx
callq __cxa_allocate_exception
movl %ebx, (%rax)
movl $_ZTI10hipError_t, %esi
movq %rax, %rdi
xorl %edx, %edx
callq __cxa_throw
.Lfunc_end3:
.size _Z15cuda_init_arrayPPfPKfm, .Lfunc_end3-_Z15cuda_init_arrayPPfPKfm
.cfi_endproc
# -- End function
.globl _Z24cuda_init_grid_and_blockP4dim3S0_i # -- Begin function _Z24cuda_init_grid_and_blockP4dim3S0_i
.p2align 4, 0x90
.type _Z24cuda_init_grid_and_blockP4dim3S0_i,@function
_Z24cuda_init_grid_and_blockP4dim3S0_i: # @_Z24cuda_init_grid_and_blockP4dim3S0_i
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
movq %rdi, %rbx
movabsq $4294967297, %rax # imm = 0x100000001
movq %rax, (%rdi)
movl $1, 8(%rdi)
movl %edx, (%rsi)
movl %edx, 4(%rsi)
movl $1, 8(%rsi)
movl $.L.str.2, %edi
movl %edx, %esi
movl $1, %ecx
xorl %eax, %eax
callq printf
movl (%rbx), %esi
movl 4(%rbx), %edx
movl 8(%rbx), %ecx
movl $.L.str.3, %edi
xorl %eax, %eax
popq %rbx
.cfi_def_cfa_offset 8
jmp printf # TAILCALL
.Lfunc_end4:
.size _Z24cuda_init_grid_and_blockP4dim3S0_i, .Lfunc_end4-_Z24cuda_init_grid_and_blockP4dim3S0_i
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.Lfunc_begin0:
.cfi_startproc
.cfi_personality 3, __gxx_personality_v0
.cfi_lsda 3, .Lexception0
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $160, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
.cfi_escape 0x2e, 0x00
xorl %r14d, %r14d
movl $.L.str.2, %edi
movl $10, %esi
movl $10, %edx
movl $1, %ecx
xorl %eax, %eax
callq printf
.cfi_escape 0x2e, 0x00
movl $.L.str.3, %edi
movl $1, %esi
movl $1, %edx
movl $1, %ecx
xorl %eax, %eax
callq printf
.cfi_escape 0x2e, 0x00
movl $400, %edi # imm = 0x190
callq _Znam
movq %rax, %rbx
xorl %eax, %eax
.p2align 4, 0x90
.LBB5_1: # %.preheader.i
# =>This Loop Header: Depth=1
# Child Loop BB5_2 Depth 2
movl $10, %ecx
movq %r14, %rdx
.p2align 4, 0x90
.LBB5_2: # Parent Loop BB5_1 Depth=1
# => This Inner Loop Header: Depth=2
xorps %xmm0, %xmm0
cvtsi2ss %edx, %xmm0
movss %xmm0, (%rbx,%rdx,4)
incq %rdx
decq %rcx
jne .LBB5_2
# %bb.3: # %._crit_edge.i
# in Loop: Header=BB5_1 Depth=1
incq %rax
addq $10, %r14
cmpq $10, %rax
jne .LBB5_1
# %bb.4: # %_Z9gen_arrayi.exit
.cfi_escape 0x2e, 0x00
movl $400, %edi # imm = 0x190
callq _Znam
movq %rax, %r14
xorl %eax, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB5_5: # %.preheader.i25
# =>This Loop Header: Depth=1
# Child Loop BB5_6 Depth 2
movl $10, %edx
movq %rax, %rsi
.p2align 4, 0x90
.LBB5_6: # Parent Loop BB5_5 Depth=1
# => This Inner Loop Header: Depth=2
xorps %xmm0, %xmm0
cvtsi2ss %esi, %xmm0
movss %xmm0, (%r14,%rsi,4)
incq %rsi
decq %rdx
jne .LBB5_6
# %bb.7: # %._crit_edge.i30
# in Loop: Header=BB5_5 Depth=1
incq %rcx
addq $10, %rax
cmpq $10, %rcx
jne .LBB5_5
# %bb.8: # %_Z9gen_arrayi.exit33
xorl %r15d, %r15d
movq %rbx, %r12
.p2align 4, 0x90
.LBB5_9: # %.preheader.i34
# =>This Loop Header: Depth=1
# Child Loop BB5_10 Depth 2
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB5_10: # Parent Loop BB5_9 Depth=1
# => This Inner Loop Header: Depth=2
movss (%r12,%r13,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
.cfi_escape 0x2e, 0x00
movl $.L.str, %edi
movb $1, %al
callq printf
incq %r13
cmpq $10, %r13
jne .LBB5_10
# %bb.11: # %._crit_edge.i38
# in Loop: Header=BB5_9 Depth=1
.cfi_escape 0x2e, 0x00
movl $10, %edi
callq putchar@PLT
incq %r15
addq $40, %r12
cmpq $10, %r15
jne .LBB5_9
# %bb.12: # %_Z11print_arrayPfi.exit
.cfi_escape 0x2e, 0x00
movl $10, %edi
callq putchar@PLT
xorl %r15d, %r15d
movq %r14, %r12
.p2align 4, 0x90
.LBB5_13: # %.preheader.i39
# =>This Loop Header: Depth=1
# Child Loop BB5_14 Depth 2
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB5_14: # Parent Loop BB5_13 Depth=1
# => This Inner Loop Header: Depth=2
movss (%r12,%r13,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
.cfi_escape 0x2e, 0x00
movl $.L.str, %edi
movb $1, %al
callq printf
incq %r13
cmpq $10, %r13
jne .LBB5_14
# %bb.15: # %._crit_edge.i44
# in Loop: Header=BB5_13 Depth=1
.cfi_escape 0x2e, 0x00
movl $10, %edi
callq putchar@PLT
incq %r15
addq $40, %r12
cmpq $10, %r15
jne .LBB5_13
# %bb.16: # %_Z11print_arrayPfi.exit49
.cfi_escape 0x2e, 0x00
movl $10, %edi
callq putchar@PLT
.Ltmp0:
.cfi_escape 0x2e, 0x00
leaq 32(%rsp), %rdi
movl $400, %edx # imm = 0x190
movq %rbx, %rsi
callq _Z15cuda_init_arrayPPfPKfm
.Ltmp1:
# %bb.17:
.Ltmp2:
.cfi_escape 0x2e, 0x00
leaq 24(%rsp), %rdi
movl $400, %edx # imm = 0x190
movq %r14, %rsi
callq _Z15cuda_init_arrayPPfPKfm
.Ltmp3:
# %bb.18:
.Ltmp4:
.cfi_escape 0x2e, 0x00
leaq 16(%rsp), %rdi
movl $400, %esi # imm = 0x190
callq hipMalloc
.Ltmp5:
# %bb.19: # %.noexc
testl %eax, %eax
jne .LBB5_20
# %bb.26: # %_Z15cuda_init_arrayPPfPKfm.exit
.cfi_escape 0x2e, 0x00
movabsq $4294967297, %rdi # imm = 0x100000001
movabsq $42949672970, %rdx # imm = 0xA0000000A
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB5_28
# %bb.27:
movq 32(%rsp), %rax
movq 24(%rsp), %rcx
movq 16(%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
movl $10, 12(%rsp)
movl $10, 8(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
.cfi_escape 0x2e, 0x00
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
.cfi_escape 0x2e, 0x10
leaq 112(%rsp), %r9
movl $_Z4multPKfS0_Pfii, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB5_28:
movq 16(%rsp), %rsi
.cfi_escape 0x2e, 0x00
movl $400, %edx # imm = 0x190
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB5_36
# %bb.29: # %.preheader.i51.preheader
xorl %r14d, %r14d
movq %rbx, %r15
.p2align 4, 0x90
.LBB5_30: # %.preheader.i51
# =>This Loop Header: Depth=1
# Child Loop BB5_31 Depth 2
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB5_31: # Parent Loop BB5_30 Depth=1
# => This Inner Loop Header: Depth=2
movss (%r15,%r12,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
.cfi_escape 0x2e, 0x00
movl $.L.str, %edi
movb $1, %al
callq printf
incq %r12
cmpq $10, %r12
jne .LBB5_31
# %bb.32: # %._crit_edge.i56
# in Loop: Header=BB5_30 Depth=1
.cfi_escape 0x2e, 0x00
movl $10, %edi
callq putchar@PLT
incq %r14
addq $40, %r15
cmpq $10, %r14
jne .LBB5_30
# %bb.33: # %_Z11print_arrayPfi.exit61
.cfi_escape 0x2e, 0x00
movl $10, %edi
callq putchar@PLT
movq 32(%rsp), %rdi
.cfi_escape 0x2e, 0x00
callq hipFree
movq 24(%rsp), %rdi
.cfi_escape 0x2e, 0x00
callq hipFree
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
callq _ZdaPv
xorl %eax, %eax
addq $160, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB5_20:
.cfi_def_cfa_offset 208
.cfi_escape 0x2e, 0x00
movl $4, %edi
movl %eax, %ebx
callq __cxa_allocate_exception
movl %ebx, (%rax)
.Ltmp6:
.cfi_escape 0x2e, 0x00
movl $_ZTI10hipError_t, %esi
movq %rax, %rdi
xorl %edx, %edx
callq __cxa_throw
.Ltmp7:
# %bb.21: # %.noexc50
.LBB5_36:
movq stderr(%rip), %rbx
.cfi_escape 0x2e, 0x00
movl %eax, %edi
callq hipGetErrorString
.cfi_escape 0x2e, 0x00
jmp .LBB5_25
.LBB5_22:
.Ltmp8:
movq %rax, %rbx
cmpl $1, %edx
jne .LBB5_35
# %bb.23:
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
callq __cxa_begin_catch
movl (%rax), %edi
movq stderr(%rip), %rbx
.Ltmp9:
.cfi_escape 0x2e, 0x00
callq hipGetErrorString
.Ltmp10:
# %bb.24:
.cfi_escape 0x2e, 0x00
.LBB5_25:
movl $.L.str.5, %esi
movq %rbx, %rdi
movq %rax, %rdx
xorl %eax, %eax
callq fprintf
.cfi_escape 0x2e, 0x00
movl $1, %edi
callq exit
.LBB5_34:
.Ltmp11:
movq %rax, %rbx
.cfi_escape 0x2e, 0x00
callq __cxa_end_catch
.LBB5_35:
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
callq _Unwind_Resume@PLT
.Lfunc_end5:
.size main, .Lfunc_end5-main
.cfi_endproc
.section .gcc_except_table,"a",@progbits
.p2align 2, 0x0
GCC_except_table5:
.Lexception0:
.byte 255 # @LPStart Encoding = omit
.byte 3 # @TType Encoding = udata4
.uleb128 .Lttbase0-.Lttbaseref0
.Lttbaseref0:
.byte 1 # Call site Encoding = uleb128
.uleb128 .Lcst_end0-.Lcst_begin0
.Lcst_begin0:
.uleb128 .Lfunc_begin0-.Lfunc_begin0 # >> Call Site 1 <<
.uleb128 .Ltmp0-.Lfunc_begin0 # Call between .Lfunc_begin0 and .Ltmp0
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp0-.Lfunc_begin0 # >> Call Site 2 <<
.uleb128 .Ltmp5-.Ltmp0 # Call between .Ltmp0 and .Ltmp5
.uleb128 .Ltmp8-.Lfunc_begin0 # jumps to .Ltmp8
.byte 3 # On action: 2
.uleb128 .Ltmp5-.Lfunc_begin0 # >> Call Site 3 <<
.uleb128 .Ltmp6-.Ltmp5 # Call between .Ltmp5 and .Ltmp6
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp6-.Lfunc_begin0 # >> Call Site 4 <<
.uleb128 .Ltmp7-.Ltmp6 # Call between .Ltmp6 and .Ltmp7
.uleb128 .Ltmp8-.Lfunc_begin0 # jumps to .Ltmp8
.byte 3 # On action: 2
.uleb128 .Ltmp7-.Lfunc_begin0 # >> Call Site 5 <<
.uleb128 .Ltmp9-.Ltmp7 # Call between .Ltmp7 and .Ltmp9
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp9-.Lfunc_begin0 # >> Call Site 6 <<
.uleb128 .Ltmp10-.Ltmp9 # Call between .Ltmp9 and .Ltmp10
.uleb128 .Ltmp11-.Lfunc_begin0 # jumps to .Ltmp11
.byte 0 # On action: cleanup
.uleb128 .Ltmp10-.Lfunc_begin0 # >> Call Site 7 <<
.uleb128 .Lfunc_end5-.Ltmp10 # Call between .Ltmp10 and .Lfunc_end5
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.Lcst_end0:
.byte 0 # >> Action Record 1 <<
# Cleanup
.byte 0 # No further actions
.byte 1 # >> Action Record 2 <<
# Catch TypeInfo 1
.byte 125 # Continue to action 1
.p2align 2, 0x0
# >> Catch TypeInfos <<
.long _ZTI10hipError_t # TypeInfo 1
.Lttbase0:
.p2align 2, 0x0
# -- End function
.text
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB6_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB6_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z4multPKfS0_Pfii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end6:
.size __hip_module_ctor, .Lfunc_end6-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB7_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB7_2:
retq
.Lfunc_end7:
.size __hip_module_dtor, .Lfunc_end7-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z4multPKfS0_Pfii,@object # @_Z4multPKfS0_Pfii
.section .rodata,"a",@progbits
.globl _Z4multPKfS0_Pfii
.p2align 3, 0x0
_Z4multPKfS0_Pfii:
.quad _Z19__device_stub__multPKfS0_Pfii
.size _Z4multPKfS0_Pfii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%5.0f "
.size .L.str, 7
.type _ZTS10hipError_t,@object # @_ZTS10hipError_t
.section .rodata._ZTS10hipError_t,"aG",@progbits,_ZTS10hipError_t,comdat
.weak _ZTS10hipError_t
_ZTS10hipError_t:
.asciz "10hipError_t"
.size _ZTS10hipError_t, 13
.type _ZTI10hipError_t,@object # @_ZTI10hipError_t
.section .rodata._ZTI10hipError_t,"aG",@progbits,_ZTI10hipError_t,comdat
.weak _ZTI10hipError_t
.p2align 3, 0x0
_ZTI10hipError_t:
.quad _ZTVN10__cxxabiv116__enum_type_infoE+16
.quad _ZTS10hipError_t
.size _ZTI10hipError_t, 16
.type .L.str.2,@object # @.str.2
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.2:
.asciz "Block %d %d %d\n"
.size .L.str.2, 16
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Grid %d %d %d\n"
.size .L.str.3, 15
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Failed to allocate device (error code: %s)!\n"
.size .L.str.5, 45
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z4multPKfS0_Pfii"
.size .L__unnamed_1, 18
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z19__device_stub__multPKfS0_Pfii
.addrsig_sym __gxx_personality_v0
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Unwind_Resume
.addrsig_sym _Z4multPKfS0_Pfii
.addrsig_sym _ZTVN10__cxxabiv116__enum_type_infoE
.addrsig_sym _ZTS10hipError_t
.addrsig_sym _ZTI10hipError_t
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z4multPKfS0_Pfii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e220000002600 */
/*0020*/ MOV R4, c[0x0][0x178] ; /* 0x00005e0000047a02 */
/* 0x000fe20000000f00 */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ HFMA2.MMA R24, -RZ, RZ, 0, 0 ; /* 0x00000000ff187435 */
/* 0x000fe200000001ff */
/*0050*/ S2R R3, SR_TID.Y ; /* 0x0000000000037919 */
/* 0x000e220000002200 */
/*0060*/ ISETP.GE.AND P0, PT, R4, 0x1, PT ; /* 0x000000010400780c */
/* 0x000fc60003f06270 */
/*0070*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e680000002500 */
/*0080*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0090*/ IMAD R0, R0, c[0x0][0x4], R3 ; /* 0x0000010000007a24 */
/* 0x001fe400078e0203 */
/*00a0*/ IMAD R3, R2, c[0x0][0x0], R5 ; /* 0x0000000002037a24 */
/* 0x002fc600078e0205 */
/*00b0*/ @!P0 BRA 0xc10 ; /* 0x00000b5000008947 */
/* 0x000fea0003800000 */
/*00c0*/ IADD3 R2, R4, -0x1, RZ ; /* 0xffffffff04027810 */
/* 0x000fe20007ffe0ff */
/*00d0*/ IMAD R5, R0, c[0x0][0x178], RZ ; /* 0x00005e0000057a24 */
/* 0x000fe200078e02ff */
/*00e0*/ LOP3.LUT R4, R4, 0x3, RZ, 0xc0, !PT ; /* 0x0000000304047812 */
/* 0x000fe400078ec0ff */
/*00f0*/ ISETP.GE.U32.AND P0, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fe40003f06070 */
/*0100*/ MOV R24, RZ ; /* 0x000000ff00187202 */
/* 0x000fe40000000f00 */
/*0110*/ MOV R2, RZ ; /* 0x000000ff00027202 */
/* 0x000fd20000000f00 */
/*0120*/ @!P0 BRA 0xb00 ; /* 0x000009d000008947 */
/* 0x000fea0003800000 */
/*0130*/ IADD3 R6, -R4, c[0x0][0x178], RZ ; /* 0x00005e0004067a10 */
/* 0x000fe20007ffe1ff */
/*0140*/ HFMA2.MMA R8, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff087435 */
/* 0x000fe200000001ff */
/*0150*/ ULDC.64 UR6, c[0x0][0x160] ; /* 0x0000580000067ab9 */
/* 0x000fe20000000a00 */
/*0160*/ HFMA2.MMA R2, -RZ, RZ, 0, 0 ; /* 0x00000000ff027435 */
/* 0x000fe200000001ff */
/*0170*/ ISETP.GT.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe40003f04270 */
/*0180*/ MOV R24, RZ ; /* 0x000000ff00187202 */
/* 0x000fca0000000f00 */
/*0190*/ IMAD.WIDE R8, R3, R8, c[0x0][0x168] ; /* 0x00005a0003087625 */
/* 0x000fcc00078e0208 */
/*01a0*/ @!P0 BRA 0x960 ; /* 0x000007b000008947 */
/* 0x000fea0003800000 */
/*01b0*/ ISETP.GT.AND P1, PT, R6, 0xc, PT ; /* 0x0000000c0600780c */
/* 0x000fe40003f24270 */
/*01c0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*01d0*/ @!P1 BRA 0x690 ; /* 0x000004b000009947 */
/* 0x000fea0003800000 */
/*01e0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*01f0*/ MOV R12, UR6 ; /* 0x00000006000c7c02 */
/* 0x000fe20008000f00 */
/*0200*/ LDG.E R21, [R8.64] ; /* 0x0000000408157981 */
/* 0x0000a2000c1e1900 */
/*0210*/ MOV R13, UR7 ; /* 0x00000007000d7c02 */
/* 0x000fca0008000f00 */
/*0220*/ IMAD.WIDE R12, R5, 0x4, R12 ; /* 0x00000004050c7825 */
/* 0x000fca00078e020c */
/*0230*/ LDG.E R20, [R12.64] ; /* 0x000000040c147981 */
/* 0x000ea2000c1e1900 */
/*0240*/ MOV R7, c[0x0][0x17c] ; /* 0x00005f0000077a02 */
/* 0x000fc60000000f00 */
/*0250*/ LDG.E R14, [R12.64+0x4] ; /* 0x000004040c0e7981 */
/* 0x000ee4000c1e1900 */
/*0260*/ IMAD.WIDE R10, R7.reuse, 0x4, R8 ; /* 0x00000004070a7825 */
/* 0x040fe400078e0208 */
/*0270*/ LDG.E R27, [R12.64+0x8] ; /* 0x000008040c1b7981 */
/* 0x000f28000c1e1900 */
/*0280*/ LDG.E R15, [R10.64] ; /* 0x000000040a0f7981 */
/* 0x0002e2000c1e1900 */
/*0290*/ IMAD.WIDE R22, R7, 0x4, R10 ; /* 0x0000000407167825 */
/* 0x000fc600078e020a */
/*02a0*/ LDG.E R18, [R12.64+0xc] ; /* 0x00000c040c127981 */
/* 0x000f66000c1e1900 */
/*02b0*/ IMAD.WIDE R28, R7.reuse, 0x4, R22 ; /* 0x00000004071c7825 */
/* 0x040fe200078e0216 */
/*02c0*/ LDG.E R26, [R22.64] ; /* 0x00000004161a7981 */
/* 0x000328000c1e1900 */
/*02d0*/ LDG.E R19, [R28.64] ; /* 0x000000041c137981 */
/* 0x000362000c1e1900 */
/*02e0*/ IMAD.WIDE R16, R7, 0x4, R28 ; /* 0x0000000407107825 */
/* 0x000fc600078e021c */
/*02f0*/ LDG.E R8, [R12.64+0x10] ; /* 0x000010040c087981 */
/* 0x001f68000c1e1900 */
/*0300*/ LDG.E R9, [R16.64] ; /* 0x0000000410097981 */
/* 0x000168000c1e1900 */
/*0310*/ LDG.E R10, [R12.64+0x14] ; /* 0x000014040c0a7981 */
/* 0x002f68000c1e1900 */
/*0320*/ LDG.E R28, [R12.64+0x1c] ; /* 0x00001c040c1c7981 */
/* 0x000f62000c1e1900 */
/*0330*/ IMAD.WIDE R16, R7, 0x4, R16 ; /* 0x0000000407107825 */
/* 0x001fca00078e0210 */
/*0340*/ LDG.E R11, [R16.64] ; /* 0x00000004100b7981 */
/* 0x000562000c1e1900 */
/*0350*/ IMAD.WIDE R22, R7, 0x4, R16 ; /* 0x0000000407167825 */
/* 0x000fc800078e0210 */
/*0360*/ FFMA R16, R21, R20, R24 ; /* 0x0000001415107223 */
/* 0x004fe40000000018 */
/*0370*/ LDG.E R20, [R12.64+0x18] ; /* 0x000018040c147981 */
/* 0x000ea2000c1e1900 */
/*0380*/ IMAD.WIDE R24, R7, 0x4, R22 ; /* 0x0000000407187825 */
/* 0x000fc600078e0216 */
/*0390*/ LDG.E R21, [R22.64] ; /* 0x0000000416157981 */
/* 0x0000a8000c1e1900 */
/*03a0*/ LDG.E R29, [R24.64] ; /* 0x00000004181d7981 */
/* 0x0002a2000c1e1900 */
/*03b0*/ FFMA R16, R15, R14, R16 ; /* 0x0000000e0f107223 */
/* 0x008fe40000000010 */
/*03c0*/ IMAD.WIDE R14, R7.reuse, 0x4, R24 ; /* 0x00000004070e7825 */
/* 0x040fe200078e0218 */
/*03d0*/ LDG.E R23, [R12.64+0x20] ; /* 0x000020040c177981 */
/* 0x001ee6000c1e1900 */
/*03e0*/ FFMA R26, R26, R27, R16 ; /* 0x0000001b1a1a7223 */
/* 0x010fe20000000010 */
/*03f0*/ LDG.E R25, [R12.64+0x24] ; /* 0x000024040c197981 */
/* 0x002f22000c1e1900 */
/*0400*/ IMAD.WIDE R16, R7, 0x4, R14 ; /* 0x0000000407107825 */
/* 0x000fc600078e020e */
/*0410*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x0000e2000c1e1900 */
/*0420*/ FFMA R26, R19, R18, R26 ; /* 0x00000012131a7223 */
/* 0x020fe4000000001a */
/*0430*/ IMAD.WIDE R18, R7, 0x4, R16 ; /* 0x0000000407127825 */
/* 0x000fe200078e0210 */
/*0440*/ LDG.E R22, [R12.64+0x28] ; /* 0x000028040c167981 */
/* 0x000f66000c1e1900 */
/*0450*/ FFMA R26, R9, R8, R26 ; /* 0x00000008091a7223 */
/* 0x000fe2000000001a */
/*0460*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x000322000c1e1900 */
/*0470*/ IMAD.WIDE R8, R7, 0x4, R18 ; /* 0x0000000407087825 */
/* 0x000fc600078e0212 */
/*0480*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x000368000c1e1900 */
/*0490*/ LDG.E R24, [R8.64] ; /* 0x0000000408187981 */
/* 0x000568000c1e1900 */
/*04a0*/ LDG.E R15, [R12.64+0x2c] ; /* 0x00002c040c0f7981 */
/* 0x001f62000c1e1900 */
/*04b0*/ FFMA R26, R11, R10, R26 ; /* 0x0000000a0b1a7223 */
/* 0x000fe4000000001a */
/*04c0*/ IMAD.WIDE R10, R7, 0x4, R8 ; /* 0x00000004070a7825 */
/* 0x000fe200078e0208 */
/*04d0*/ LDG.E R17, [R12.64+0x30] ; /* 0x000030040c117981 */
/* 0x002f66000c1e1900 */
/*04e0*/ FFMA R26, R21, R20, R26 ; /* 0x00000014151a7223 */
/* 0x004fc4000000001a */
/*04f0*/ IMAD.WIDE R20, R7, 0x4, R10 ; /* 0x0000000407147825 */
/* 0x000fe400078e020a */
/*0500*/ LDG.E R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x0000a4000c1e1900 */
/*0510*/ FFMA R28, R29, R28, R26 ; /* 0x0000001c1d1c7223 */
/* 0x000fe4000000001a */
/*0520*/ IMAD.WIDE R26, R7.reuse, 0x4, R20 ; /* 0x00000004071a7825 */
/* 0x040fe200078e0214 */
/*0530*/ LDG.E R29, [R12.64+0x34] ; /* 0x000034040c1d7981 */
/* 0x000ea8000c1e1900 */
/*0540*/ LDG.E R20, [R20.64] ; /* 0x0000000414147981 */
/* 0x0002a2000c1e1900 */
/*0550*/ IMAD.WIDE R8, R7, 0x4, R26 ; /* 0x0000000407087825 */
/* 0x000fc600078e021a */
/*0560*/ LDG.E R19, [R26.64] ; /* 0x000000041a137981 */
/* 0x0006a8000c1e1900 */
/*0570*/ LDG.E R11, [R8.64] ; /* 0x00000004080b7981 */
/* 0x0010a8000c1e1900 */
/*0580*/ LDG.E R21, [R12.64+0x38] ; /* 0x000038040c157981 */
/* 0x002ea8000c1e1900 */
/*0590*/ LDG.E R26, [R12.64+0x3c] ; /* 0x00003c040c1a7981 */
/* 0x008ee2000c1e1900 */
/*05a0*/ FFMA R14, R14, R23, R28 ; /* 0x000000170e0e7223 */
/* 0x000fc8000000001c */
/*05b0*/ FFMA R25, R16, R25, R14 ; /* 0x0000001910197223 */
/* 0x010fe2000000000e */
/*05c0*/ IADD3 R6, R6, -0x10, RZ ; /* 0xfffffff006067810 */
/* 0x000fc60007ffe0ff */
/*05d0*/ FFMA R18, R18, R22, R25 ; /* 0x0000001612127223 */
/* 0x020fe20000000019 */
/*05e0*/ ISETP.GT.AND P1, PT, R6, 0xc, PT ; /* 0x0000000c0600780c */
/* 0x000fc60003f24270 */
/*05f0*/ FFMA R15, R24, R15, R18 ; /* 0x0000000f180f7223 */
/* 0x000fe20000000012 */
/*0600*/ UIADD3 UR6, UP0, UR6, 0x40, URZ ; /* 0x0000004006067890 */
/* 0x000fe2000ff1e03f */
/*0610*/ IMAD.WIDE R8, R7, 0x4, R8 ; /* 0x0000000407087825 */
/* 0x001fc600078e0208 */
/*0620*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0630*/ IADD3 R2, R2, 0x10, RZ ; /* 0x0000001002027810 */
/* 0x000fe20007ffe0ff */
/*0640*/ FFMA R10, R10, R17, R15 ; /* 0x000000110a0a7223 */
/* 0x004fc8000000000f */
/*0650*/ FFMA R10, R20, R29, R10 ; /* 0x0000001d140a7223 */
/* 0x000fc8000000000a */
/*0660*/ FFMA R10, R19, R21, R10 ; /* 0x00000015130a7223 */
/* 0x000fc8000000000a */
/*0670*/ FFMA R24, R11, R26, R10 ; /* 0x0000001a0b187223 */
/* 0x008fe2000000000a */
/*0680*/ @P1 BRA 0x1f0 ; /* 0xfffffb6000001947 */
/* 0x000fea000383ffff */
/*0690*/ ISETP.GT.AND P1, PT, R6, 0x4, PT ; /* 0x000000040600780c */
/* 0x000fda0003f24270 */
/*06a0*/ @!P1 BRA 0x940 ; /* 0x0000029000009947 */
/* 0x000fea0003800000 */
/*06b0*/ MOV R7, c[0x0][0x17c] ; /* 0x00005f0000077a02 */
/* 0x000fe20000000f00 */
/*06c0*/ LDG.E R23, [R8.64] ; /* 0x0000000408177981 */
/* 0x0000a2000c1e1900 */
/*06d0*/ MOV R10, UR6 ; /* 0x00000006000a7c02 */
/* 0x000fe40008000f00 */
/*06e0*/ MOV R11, UR7 ; /* 0x00000007000b7c02 */
/* 0x000fe20008000f00 */
/*06f0*/ IMAD.WIDE R16, R7, 0x4, R8 ; /* 0x0000000407107825 */
/* 0x000fc800078e0208 */
/*0700*/ IMAD.WIDE R10, R5, 0x4, R10 ; /* 0x00000004050a7825 */
/* 0x000fc800078e020a */
/*0710*/ IMAD.WIDE R12, R7.reuse, 0x4, R16 ; /* 0x00000004070c7825 */
/* 0x040fe200078e0210 */
/*0720*/ LDG.E R22, [R10.64] ; /* 0x000000040a167981 */
/* 0x000ea8000c1e1900 */
/*0730*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x0002e2000c1e1900 */
/*0740*/ IMAD.WIDE R14, R7, 0x4, R12 ; /* 0x00000004070e7825 */
/* 0x000fc600078e020c */
/*0750*/ LDG.E R25, [R10.64+0x4] ; /* 0x000004040a197981 */
/* 0x000ee6000c1e1900 */
/*0760*/ IMAD.WIDE R18, R7.reuse, 0x4, R14 ; /* 0x0000000407127825 */
/* 0x040fe200078e020e */
/*0770*/ LDG.E R26, [R12.64] ; /* 0x000000040c1a7981 */
/* 0x000968000c1e1900 */
/*0780*/ LDG.E R27, [R10.64+0x8] ; /* 0x000008040a1b7981 */
/* 0x000f62000c1e1900 */
/*0790*/ IMAD.WIDE R20, R7, 0x4, R18 ; /* 0x0000000407147825 */
/* 0x000fc600078e0212 */
/*07a0*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000368000c1e1900 */
/*07b0*/ LDG.E R29, [R10.64+0xc] ; /* 0x00000c040a1d7981 */
/* 0x000f62000c1e1900 */
/*07c0*/ IMAD.WIDE R8, R7, 0x4, R20 ; /* 0x0000000407087825 */
/* 0x001fc600078e0214 */
/*07d0*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x000168000c1e1900 */
/*07e0*/ LDG.E R28, [R10.64+0x10] ; /* 0x000010040a1c7981 */
/* 0x000f62000c1e1900 */
/*07f0*/ IMAD.WIDE R12, R7, 0x4, R8 ; /* 0x00000004070c7825 */
/* 0x010fc600078e0208 */
/*0800*/ LDG.E R20, [R20.64] ; /* 0x0000000414147981 */
/* 0x000968000c1e1900 */
/*0810*/ LDG.E R15, [R10.64+0x14] ; /* 0x000014040a0f7981 */
/* 0x002f68000c1e1900 */
/*0820*/ LDG.E R17, [R8.64] ; /* 0x0000000408117981 */
/* 0x000368000c1e1900 */
/*0830*/ LDG.E R21, [R10.64+0x1c] ; /* 0x00001c040a157981 */
/* 0x010f28000c1e1900 */
/*0840*/ LDG.E R19, [R12.64] ; /* 0x000000040c137981 */
/* 0x001f28000c1e1900 */
/*0850*/ LDG.E R8, [R10.64+0x18] ; /* 0x000018040a087981 */
/* 0x002f22000c1e1900 */
/*0860*/ UIADD3 UR6, UP0, UR6, 0x20, URZ ; /* 0x0000002006067890 */
/* 0x000fe2000ff1e03f */
/*0870*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc40003f0e170 */
/*0880*/ IADD3 R2, R2, 0x8, RZ ; /* 0x0000000802027810 */
/* 0x000fe40007ffe0ff */
/*0890*/ IADD3 R6, R6, -0x8, RZ ; /* 0xfffffff806067810 */
/* 0x000fe20007ffe0ff */
/*08a0*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*08b0*/ FFMA R22, R23, R22, R24 ; /* 0x0000001617167223 */
/* 0x004fc80000000018 */
/*08c0*/ FFMA R16, R16, R25, R22 ; /* 0x0000001910107223 */
/* 0x008fc80000000016 */
/*08d0*/ FFMA R16, R26, R27, R16 ; /* 0x0000001b1a107223 */
/* 0x020fc80000000010 */
/*08e0*/ FFMA R29, R14, R29, R16 ; /* 0x0000001d0e1d7223 */
/* 0x000fc80000000010 */
/*08f0*/ FFMA R18, R18, R28, R29 ; /* 0x0000001c12127223 */
/* 0x000fc8000000001d */
/*0900*/ FFMA R15, R20, R15, R18 ; /* 0x0000000f140f7223 */
/* 0x000fc80000000012 */
/*0910*/ FFMA R24, R17, R8, R15 ; /* 0x0000000811187223 */
/* 0x010fe4000000000f */
/*0920*/ IMAD.WIDE R8, R7, 0x4, R12 ; /* 0x0000000407087825 */
/* 0x000fc800078e020c */
/*0930*/ FFMA R24, R19, R21, R24 ; /* 0x0000001513187223 */
/* 0x000fe40000000018 */
/*0940*/ ISETP.NE.OR P0, PT, R6, RZ, P0 ; /* 0x000000ff0600720c */
/* 0x000fda0000705670 */
/*0950*/ @!P0 BRA 0xb00 ; /* 0x000001a000008947 */
/* 0x000fea0003800000 */
/*0960*/ MOV R10, UR6 ; /* 0x00000006000a7c02 */
/* 0x000fe40008000f00 */
/*0970*/ MOV R11, UR7 ; /* 0x00000007000b7c02 */
/* 0x000fe40008000f00 */
/*0980*/ MOV R7, c[0x0][0x17c] ; /* 0x00005f0000077a02 */
/* 0x000fc60000000f00 */
/*0990*/ IMAD.WIDE R10, R5, 0x4, R10 ; /* 0x00000004050a7825 */
/* 0x000fc800078e020a */
/*09a0*/ IMAD.WIDE R16, R7.reuse, 0x4, R8 ; /* 0x0000000407107825 */
/* 0x040fe200078e0208 */
/*09b0*/ LDG.E R18, [R10.64] ; /* 0x000000040a127981 */
/* 0x000ea8000c1e1900 */
/*09c0*/ LDG.E R9, [R8.64] ; /* 0x0000000408097981 */
/* 0x000ea2000c1e1900 */
/*09d0*/ IMAD.WIDE R12, R7, 0x4, R16 ; /* 0x00000004070c7825 */
/* 0x000fc600078e0210 */
/*09e0*/ LDG.E R17, [R16.64] ; /* 0x0000000410117981 */
/* 0x000ee8000c1e1900 */
/*09f0*/ LDG.E R19, [R10.64+0x4] ; /* 0x000004040a137981 */
/* 0x000ee2000c1e1900 */
/*0a00*/ IMAD.WIDE R14, R7, 0x4, R12 ; /* 0x00000004070e7825 */
/* 0x000fc600078e020c */
/*0a10*/ LDG.E R21, [R12.64] ; /* 0x000000040c157981 */
/* 0x000f28000c1e1900 */
/*0a20*/ LDG.E R20, [R10.64+0x8] ; /* 0x000008040a147981 */
/* 0x000f28000c1e1900 */
/*0a30*/ LDG.E R22, [R10.64+0xc] ; /* 0x00000c040a167981 */
/* 0x000f68000c1e1900 */
/*0a40*/ LDG.E R23, [R14.64] ; /* 0x000000040e177981 */
/* 0x000f62000c1e1900 */
/*0a50*/ IADD3 R6, R6, -0x4, RZ ; /* 0xfffffffc06067810 */
/* 0x000fc80007ffe0ff */
/*0a60*/ ISETP.NE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe20003f05270 */
/*0a70*/ UIADD3 UR6, UP0, UR6, 0x10, URZ ; /* 0x0000001006067890 */
/* 0x000fe2000ff1e03f */
/*0a80*/ IADD3 R2, R2, 0x4, RZ ; /* 0x0000000402027810 */
/* 0x000fc60007ffe0ff */
/*0a90*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0aa0*/ FFMA R18, R9, R18, R24 ; /* 0x0000001209127223 */
/* 0x004fc80000000018 */
/*0ab0*/ FFMA R18, R17, R19, R18 ; /* 0x0000001311127223 */
/* 0x008fe40000000012 */
/*0ac0*/ IMAD.WIDE R8, R7, 0x4, R14 ; /* 0x0000000407087825 */
/* 0x000fc800078e020e */
/*0ad0*/ FFMA R18, R21, R20, R18 ; /* 0x0000001415127223 */
/* 0x010fc80000000012 */
/*0ae0*/ FFMA R24, R23, R22, R18 ; /* 0x0000001617187223 */
/* 0x020fe20000000012 */
/*0af0*/ @P0 BRA 0x960 ; /* 0xfffffe6000000947 */
/* 0x000fea000383ffff */
/*0b00*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fda0003f05270 */
/*0b10*/ @!P0 BRA 0xc10 ; /* 0x000000f000008947 */
/* 0x000fea0003800000 */
/*0b20*/ HFMA2.MMA R9, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff097435 */
/* 0x000fe200000001ff */
/*0b30*/ IADD3 R6, R5, R2, RZ ; /* 0x0000000205067210 */
/* 0x000fe20007ffe0ff */
/*0b40*/ IMAD R2, R2, c[0x0][0x17c], R3 ; /* 0x00005f0002027a24 */
/* 0x000fd000078e0203 */
/*0b50*/ IMAD.WIDE R6, R6, R9, c[0x0][0x160] ; /* 0x0000580006067625 */
/* 0x000fc800078e0209 */
/*0b60*/ IMAD.WIDE R8, R2, R9, c[0x0][0x168] ; /* 0x00005a0002087625 */
/* 0x000fca00078e0209 */
/*0b70*/ LDG.E R5, [R8.64] ; /* 0x0000000408057981 */
/* 0x0000a8000c1e1900 */
/*0b80*/ LDG.E R2, [R6.64] ; /* 0x0000000406027981 */
/* 0x0002a2000c1e1900 */
/*0b90*/ IADD3 R4, R4, -0x1, RZ ; /* 0xffffffff04047810 */
/* 0x000fe40007ffe0ff */
/*0ba0*/ MOV R11, c[0x0][0x17c] ; /* 0x00005f00000b7a02 */
/* 0x000fe40000000f00 */
/*0bb0*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fc60003f05270 */
/*0bc0*/ IMAD.WIDE R8, R11, 0x4, R8 ; /* 0x000000040b087825 */
/* 0x001fe200078e0208 */
/*0bd0*/ IADD3 R6, P1, R6, 0x4, RZ ; /* 0x0000000406067810 */
/* 0x002fc80007f3e0ff */
/*0be0*/ IADD3.X R7, RZ, R7, RZ, P1, !PT ; /* 0x00000007ff077210 */
/* 0x000fe20000ffe4ff */
/*0bf0*/ FFMA R24, R5, R2, R24 ; /* 0x0000000205187223 */
/* 0x004fc80000000018 */
/*0c00*/ @P0 BRA 0xb70 ; /* 0xffffff6000000947 */
/* 0x000fea000383ffff */
/*0c10*/ MOV R2, 0x4 ; /* 0x0000000400027802 */
/* 0x000fe20000000f00 */
/*0c20*/ IMAD R3, R0, c[0x0][0x17c], R3 ; /* 0x00005f0000037a24 */
/* 0x000fc800078e0203 */
/*0c30*/ IMAD.WIDE R2, R3, R2, c[0x0][0x170] ; /* 0x00005c0003027625 */
/* 0x000fca00078e0202 */
/*0c40*/ STG.E [R2.64], R24 ; /* 0x0000001802007986 */
/* 0x000fe2000c101904 */
/*0c50*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0c60*/ BRA 0xc60; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0c70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ca0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ce0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z4multPKfS0_Pfii
.globl _Z4multPKfS0_Pfii
.p2align 8
.type _Z4multPKfS0_Pfii,@function
_Z4multPKfS0_Pfii:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x2c
s_load_b64 s[2:3], s[0:1], 0x18
v_bfe_u32 v3, v0, 10, 10
v_and_b32_e32 v0, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s5, s4, 16
s_and_b32 s4, s4, 0xffff
v_mad_u64_u32 v[1:2], null, s15, s5, v[3:4]
s_cmp_lt_i32 s2, 1
s_mul_i32 s14, s14, s4
s_cbranch_scc1 .LBB0_3
s_load_b128 s[4:7], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_lo_u32 v2, v1, s2
v_mov_b32_e32 v6, 0
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[4:5], 2, v[2:3]
v_add_nc_u32_e32 v2, s14, v0
s_waitcnt lgkmcnt(0)
v_add_co_u32 v4, vcc_lo, s4, v4
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
.p2align 6
.LBB0_2:
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_ashrrev_i32_e32 v3, 31, v2
s_add_i32 s2, s2, -1
s_cmp_eq_u32 s2, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[7:8], 2, v[2:3]
v_add_nc_u32_e32 v2, s3, v2
v_add_co_u32 v7, vcc_lo, s6, v7
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v8, vcc_lo, s7, v8, vcc_lo
global_load_b32 v3, v[4:5], off
global_load_b32 v7, v[7:8], off
v_add_co_u32 v4, vcc_lo, v4, 4
v_add_co_ci_u32_e32 v5, vcc_lo, 0, v5, vcc_lo
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v6, v3, v7
s_cbranch_scc0 .LBB0_2
s_branch .LBB0_4
.LBB0_3:
v_mov_b32_e32 v6, 0
.LBB0_4:
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mul_lo_u32 v1, v1, s3
s_load_b64 s[0:1], s[0:1], 0x10
v_add3_u32 v0, s14, v0, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v6, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z4multPKfS0_Pfii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z4multPKfS0_Pfii, .Lfunc_end0-_Z4multPKfS0_Pfii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z4multPKfS0_Pfii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z4multPKfS0_Pfii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000904be_00000000-6_main.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2064:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2064:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z9gen_arrayi
.type _Z9gen_arrayi, @function
_Z9gen_arrayi:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movl %edi, %ebx
imull %edi, %edi
movslq %edi, %rdi
salq $2, %rdi
call _Znam@PLT
testl %ebx, %ebx
jle .L3
movslq %ebx, %r10
salq $2, %r10
movq %rax, %r9
movl %ebx, %esi
movl $0, %r8d
movl $0, %edi
.L5:
movq %r9, %rcx
movl %r8d, %edx
.L6:
pxor %xmm0, %xmm0
cvtsi2ssl %edx, %xmm0
movss %xmm0, (%rcx)
addl $1, %edx
addq $4, %rcx
cmpl %esi, %edx
jne .L6
addl $1, %edi
addl %ebx, %r8d
addq %r10, %r9
addl %ebx, %esi
cmpl %edi, %ebx
jne .L5
.L3:
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _Z9gen_arrayi, .-_Z9gen_arrayi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%5.0f "
.LC1:
.string "\n"
.text
.globl _Z11print_arrayPfi
.type _Z11print_arrayPfi, @function
_Z11print_arrayPfi:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $24, %rsp
.cfi_def_cfa_offset 80
movl %esi, 12(%rsp)
testl %esi, %esi
jle .L10
movslq %esi, %r14
leaq 0(,%r14,4), %r15
leaq (%rdi,%r15), %rbp
negq %r14
salq $2, %r14
movl $0, %r13d
leaq .LC0(%rip), %r12
.L11:
leaq 0(%rbp,%r14), %rbx
.L12:
pxor %xmm0, %xmm0
cvtss2sd (%rbx), %xmm0
movq %r12, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %rbp, %rbx
jne .L12
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %r13d
addq %r15, %rbp
cmpl %r13d, 12(%rsp)
jne .L11
.L10:
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _Z11print_arrayPfi, .-_Z11print_arrayPfi
.globl _Z15cuda_init_arrayPPfPKfm
.type _Z15cuda_init_arrayPPfPKfm, @function
_Z15cuda_init_arrayPPfPKfm:
.LFB2059:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $8, %rsp
.cfi_def_cfa_offset 48
movq %rdi, %r12
movq %rsi, %rbx
movq %rdx, %rbp
movq %rdx, %rsi
call cudaMalloc@PLT
testl %eax, %eax
jne .L19
testq %rbx, %rbx
je .L15
movq (%r12), %rdi
movl $1, %ecx
movq %rbp, %rdx
movq %rbx, %rsi
call cudaMemcpy@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L20
.L15:
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
movl %eax, %r13d
movl $4, %edi
call __cxa_allocate_exception@PLT
movq %rax, %rdi
movl %r13d, (%rax)
movl $0, %edx
leaq _ZTI9cudaError(%rip), %rsi
call __cxa_throw@PLT
.L20:
movl $4, %edi
call __cxa_allocate_exception@PLT
movq %rax, %rdi
movl %ebx, (%rax)
movl $0, %edx
leaq _ZTI9cudaError(%rip), %rsi
call __cxa_throw@PLT
.cfi_endproc
.LFE2059:
.size _Z15cuda_init_arrayPPfPKfm, .-_Z15cuda_init_arrayPPfPKfm
.section .rodata.str1.1
.LC2:
.string "Block %d %d %d\n"
.LC3:
.string "Grid %d %d %d\n"
.text
.globl _Z24cuda_init_grid_and_blockP4dim3S0_i
.type _Z24cuda_init_grid_and_blockP4dim3S0_i, @function
_Z24cuda_init_grid_and_blockP4dim3S0_i:
.LFB2060:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movq %rdi, %rbx
movl $1, (%rdi)
movl $1, 4(%rdi)
movl $1, 8(%rdi)
movl %edx, (%rsi)
movl %edx, 4(%rsi)
movl $1, 8(%rsi)
movl $1, %r8d
movl %edx, %ecx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 4(%rbx), %ecx
movl (%rbx), %edx
movl 8(%rbx), %r8d
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _Z24cuda_init_grid_and_blockP4dim3S0_i, .-_Z24cuda_init_grid_and_blockP4dim3S0_i
.globl _Z31__device_stub__Z4multPKfS0_PfiiPKfS0_Pfii
.type _Z31__device_stub__Z4multPKfS0_PfiiPKfS0_Pfii, @function
_Z31__device_stub__Z4multPKfS0_PfiiPKfS0_Pfii:
.LFB2086:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L27
.L23:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L28
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L27:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z4multPKfS0_Pfii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L23
.L28:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2086:
.size _Z31__device_stub__Z4multPKfS0_PfiiPKfS0_Pfii, .-_Z31__device_stub__Z4multPKfS0_PfiiPKfS0_Pfii
.globl _Z4multPKfS0_Pfii
.type _Z4multPKfS0_Pfii, @function
_Z4multPKfS0_Pfii:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z4multPKfS0_PfiiPKfS0_Pfii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _Z4multPKfS0_Pfii, .-_Z4multPKfS0_Pfii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC4:
.string "Failed to allocate host vectors!\n"
.align 8
.LC5:
.string "Failed to allocate device (error code: %s)!\n"
.text
.globl main
.type main, @function
main:
.LFB2061:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA2061
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $72, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 32(%rsp), %rsi
leaq 44(%rsp), %rdi
movl $10, %edx
.LEHB0:
call _Z24cuda_init_grid_and_blockP4dim3S0_i
movl $10, %edi
call _Z9gen_arrayi
movq %rax, %rbx
movl $10, %edi
call _Z9gen_arrayi
testq %rbx, %rbx
je .L45
movq %rax, %rbp
movl $10, %esi
movq %rbx, %rdi
call _Z11print_arrayPfi
movl $10, %esi
movq %rbp, %rdi
call _Z11print_arrayPfi
.LEHE0:
leaq 8(%rsp), %rdi
movl $400, %edx
movq %rbx, %rsi
.LEHB1:
call _Z15cuda_init_arrayPPfPKfm
.LEHE1:
jmp .L46
.L45:
leaq .LC4(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
.LEHB2:
call __fprintf_chk@PLT
.LEHE2:
movl $1, %edi
call exit@PLT
.L46:
leaq 16(%rsp), %rdi
movl $400, %edx
movq %rbp, %rsi
.LEHB3:
call _Z15cuda_init_arrayPPfPKfm
leaq 24(%rsp), %rdi
movl $400, %edx
movl $0, %esi
call _Z15cuda_init_arrayPPfPKfm
.LEHE3:
movl 40(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 32(%rsp), %rdx
movq 44(%rsp), %rdi
movl 52(%rsp), %esi
.LEHB4:
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L47
.L33:
movl $2, %ecx
movl $400, %edx
movq 24(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L48
movl $10, %esi
movq %rbx, %rdi
call _Z11print_arrayPfi
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq %rbx, %rdi
call _ZdaPv@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L49
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L47:
.cfi_restore_state
movl $10, %r8d
movl $10, %ecx
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z31__device_stub__Z4multPKfS0_PfiiPKfS0_Pfii
jmp .L33
.L48:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC5(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L41:
endbr64
movq %rax, %rdi
cmpq $1, %rdx
je .L36
movq 56(%rsp), %rax
subq %fs:40, %rax
je .L37
call __stack_chk_fail@PLT
.L37:
call _Unwind_Resume@PLT
.LEHE4:
.L36:
call __cxa_begin_catch@PLT
movl (%rax), %edi
.LEHB5:
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC5(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
.LEHE5:
movl $1, %edi
call exit@PLT
.L42:
endbr64
movq %rax, %rbx
call __cxa_end_catch@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
je .L39
call __stack_chk_fail@PLT
.L39:
movq %rbx, %rdi
.LEHB6:
call _Unwind_Resume@PLT
.LEHE6:
.L49:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2061:
.globl __gxx_personality_v0
.section .gcc_except_table,"a",@progbits
.align 4
.LLSDA2061:
.byte 0xff
.byte 0x9b
.uleb128 .LLSDATT2061-.LLSDATTD2061
.LLSDATTD2061:
.byte 0x1
.uleb128 .LLSDACSE2061-.LLSDACSB2061
.LLSDACSB2061:
.uleb128 .LEHB0-.LFB2061
.uleb128 .LEHE0-.LEHB0
.uleb128 0
.uleb128 0
.uleb128 .LEHB1-.LFB2061
.uleb128 .LEHE1-.LEHB1
.uleb128 .L41-.LFB2061
.uleb128 0x1
.uleb128 .LEHB2-.LFB2061
.uleb128 .LEHE2-.LEHB2
.uleb128 0
.uleb128 0
.uleb128 .LEHB3-.LFB2061
.uleb128 .LEHE3-.LEHB3
.uleb128 .L41-.LFB2061
.uleb128 0x1
.uleb128 .LEHB4-.LFB2061
.uleb128 .LEHE4-.LEHB4
.uleb128 0
.uleb128 0
.uleb128 .LEHB5-.LFB2061
.uleb128 .LEHE5-.LEHB5
.uleb128 .L42-.LFB2061
.uleb128 0
.uleb128 .LEHB6-.LFB2061
.uleb128 .LEHE6-.LEHB6
.uleb128 0
.uleb128 0
.LLSDACSE2061:
.byte 0x1
.byte 0
.align 4
.long DW.ref._ZTI9cudaError-.
.LLSDATT2061:
.text
.size main, .-main
.section .rodata.str1.1
.LC6:
.string "_Z4multPKfS0_Pfii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2089:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _Z4multPKfS0_Pfii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2089:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.weak _ZTS9cudaError
.section .rodata._ZTS9cudaError,"aG",@progbits,_ZTS9cudaError,comdat
.align 8
.type _ZTS9cudaError, @object
.size _ZTS9cudaError, 11
_ZTS9cudaError:
.string "9cudaError"
.weak _ZTI9cudaError
.section .data.rel.ro._ZTI9cudaError,"awG",@progbits,_ZTI9cudaError,comdat
.align 8
.type _ZTI9cudaError, @object
.size _ZTI9cudaError, 16
_ZTI9cudaError:
.quad _ZTVN10__cxxabiv116__enum_type_infoE+16
.quad _ZTS9cudaError
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.hidden DW.ref._ZTI9cudaError
.weak DW.ref._ZTI9cudaError
.section .data.rel.local.DW.ref._ZTI9cudaError,"awG",@progbits,DW.ref._ZTI9cudaError,comdat
.align 8
.type DW.ref._ZTI9cudaError, @object
.size DW.ref._ZTI9cudaError, 8
DW.ref._ZTI9cudaError:
.quad _ZTI9cudaError
.hidden DW.ref.__gxx_personality_v0
.weak DW.ref.__gxx_personality_v0
.section .data.rel.local.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat
.align 8
.type DW.ref.__gxx_personality_v0, @object
.size DW.ref.__gxx_personality_v0, 8
DW.ref.__gxx_personality_v0:
.quad __gxx_personality_v0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "main.hip"
.globl _Z19__device_stub__multPKfS0_Pfii # -- Begin function _Z19__device_stub__multPKfS0_Pfii
.p2align 4, 0x90
.type _Z19__device_stub__multPKfS0_Pfii,@function
_Z19__device_stub__multPKfS0_Pfii: # @_Z19__device_stub__multPKfS0_Pfii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z4multPKfS0_Pfii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z19__device_stub__multPKfS0_Pfii, .Lfunc_end0-_Z19__device_stub__multPKfS0_Pfii
.cfi_endproc
# -- End function
.globl _Z9gen_arrayi # -- Begin function _Z9gen_arrayi
.p2align 4, 0x90
.type _Z9gen_arrayi,@function
_Z9gen_arrayi: # @_Z9gen_arrayi
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
movl %edi, %ebx
imull %edi, %edi
shlq $2, %rdi
callq _Znam
testl %ebx, %ebx
jle .LBB1_5
# %bb.1: # %.preheader.lr.ph
movl %ebx, %ecx
xorl %edx, %edx
xorl %esi, %esi
.p2align 4, 0x90
.LBB1_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_3 Depth 2
movl %edx, %edi
leaq (%rax,%rdi,4), %rdi
xorl %r8d, %r8d
.p2align 4, 0x90
.LBB1_3: # Parent Loop BB1_2 Depth=1
# => This Inner Loop Header: Depth=2
leal (%rdx,%r8), %r9d
xorps %xmm0, %xmm0
cvtsi2ss %r9d, %xmm0
movss %xmm0, (%rdi,%r8,4)
incq %r8
cmpq %r8, %rcx
jne .LBB1_3
# %bb.4: # %._crit_edge
# in Loop: Header=BB1_2 Depth=1
incq %rsi
addq %rcx, %rdx
cmpq %rcx, %rsi
jne .LBB1_2
.LBB1_5: # %._crit_edge19
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z9gen_arrayi, .Lfunc_end1-_Z9gen_arrayi
.cfi_endproc
# -- End function
.globl _Z11print_arrayPfi # -- Begin function _Z11print_arrayPfi
.p2align 4, 0x90
.type _Z11print_arrayPfi,@function
_Z11print_arrayPfi: # @_Z11print_arrayPfi
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
pushq %rax
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rdi, (%rsp) # 8-byte Spill
testl %esi, %esi
jle .LBB2_5
# %bb.1: # %.preheader.lr.ph
movl %esi, %ebx
movl %esi, %r15d
xorl %r12d, %r12d
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB2_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB2_3 Depth 2
movl %r12d, %eax
movq (%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax,4), %rbp
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB2_3: # Parent Loop BB2_2 Depth=1
# => This Inner Loop Header: Depth=2
movss (%rbp,%r14,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
incq %r14
cmpq %r14, %r15
jne .LBB2_3
# %bb.4: # %._crit_edge
# in Loop: Header=BB2_2 Depth=1
movl $10, %edi
callq putchar@PLT
incq %r13
addl %ebx, %r12d
cmpq %r15, %r13
jne .LBB2_2
.LBB2_5: # %._crit_edge14
movl $10, %edi
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
jmp putchar@PLT # TAILCALL
.Lfunc_end2:
.size _Z11print_arrayPfi, .Lfunc_end2-_Z11print_arrayPfi
.cfi_endproc
# -- End function
.globl _Z15cuda_init_arrayPPfPKfm # -- Begin function _Z15cuda_init_arrayPPfPKfm
.p2align 4, 0x90
.type _Z15cuda_init_arrayPPfPKfm,@function
_Z15cuda_init_arrayPPfPKfm: # @_Z15cuda_init_arrayPPfPKfm
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdx, %rbx
movq %rsi, %r14
movq %rdi, %r15
movq %rdx, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB3_4
# %bb.1:
testq %r14, %r14
je .LBB3_3
# %bb.2:
movq (%r15), %rdi
movq %r14, %rsi
movq %rbx, %rdx
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB3_4
.LBB3_3:
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB3_4:
.cfi_def_cfa_offset 32
movl $4, %edi
movl %eax, %ebx
callq __cxa_allocate_exception
movl %ebx, (%rax)
movl $_ZTI10hipError_t, %esi
movq %rax, %rdi
xorl %edx, %edx
callq __cxa_throw
.Lfunc_end3:
.size _Z15cuda_init_arrayPPfPKfm, .Lfunc_end3-_Z15cuda_init_arrayPPfPKfm
.cfi_endproc
# -- End function
.globl _Z24cuda_init_grid_and_blockP4dim3S0_i # -- Begin function _Z24cuda_init_grid_and_blockP4dim3S0_i
.p2align 4, 0x90
.type _Z24cuda_init_grid_and_blockP4dim3S0_i,@function
_Z24cuda_init_grid_and_blockP4dim3S0_i: # @_Z24cuda_init_grid_and_blockP4dim3S0_i
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
movq %rdi, %rbx
movabsq $4294967297, %rax # imm = 0x100000001
movq %rax, (%rdi)
movl $1, 8(%rdi)
movl %edx, (%rsi)
movl %edx, 4(%rsi)
movl $1, 8(%rsi)
movl $.L.str.2, %edi
movl %edx, %esi
movl $1, %ecx
xorl %eax, %eax
callq printf
movl (%rbx), %esi
movl 4(%rbx), %edx
movl 8(%rbx), %ecx
movl $.L.str.3, %edi
xorl %eax, %eax
popq %rbx
.cfi_def_cfa_offset 8
jmp printf # TAILCALL
.Lfunc_end4:
.size _Z24cuda_init_grid_and_blockP4dim3S0_i, .Lfunc_end4-_Z24cuda_init_grid_and_blockP4dim3S0_i
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.Lfunc_begin0:
.cfi_startproc
.cfi_personality 3, __gxx_personality_v0
.cfi_lsda 3, .Lexception0
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $160, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
.cfi_escape 0x2e, 0x00
xorl %r14d, %r14d
movl $.L.str.2, %edi
movl $10, %esi
movl $10, %edx
movl $1, %ecx
xorl %eax, %eax
callq printf
.cfi_escape 0x2e, 0x00
movl $.L.str.3, %edi
movl $1, %esi
movl $1, %edx
movl $1, %ecx
xorl %eax, %eax
callq printf
.cfi_escape 0x2e, 0x00
movl $400, %edi # imm = 0x190
callq _Znam
movq %rax, %rbx
xorl %eax, %eax
.p2align 4, 0x90
.LBB5_1: # %.preheader.i
# =>This Loop Header: Depth=1
# Child Loop BB5_2 Depth 2
movl $10, %ecx
movq %r14, %rdx
.p2align 4, 0x90
.LBB5_2: # Parent Loop BB5_1 Depth=1
# => This Inner Loop Header: Depth=2
xorps %xmm0, %xmm0
cvtsi2ss %edx, %xmm0
movss %xmm0, (%rbx,%rdx,4)
incq %rdx
decq %rcx
jne .LBB5_2
# %bb.3: # %._crit_edge.i
# in Loop: Header=BB5_1 Depth=1
incq %rax
addq $10, %r14
cmpq $10, %rax
jne .LBB5_1
# %bb.4: # %_Z9gen_arrayi.exit
.cfi_escape 0x2e, 0x00
movl $400, %edi # imm = 0x190
callq _Znam
movq %rax, %r14
xorl %eax, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB5_5: # %.preheader.i25
# =>This Loop Header: Depth=1
# Child Loop BB5_6 Depth 2
movl $10, %edx
movq %rax, %rsi
.p2align 4, 0x90
.LBB5_6: # Parent Loop BB5_5 Depth=1
# => This Inner Loop Header: Depth=2
xorps %xmm0, %xmm0
cvtsi2ss %esi, %xmm0
movss %xmm0, (%r14,%rsi,4)
incq %rsi
decq %rdx
jne .LBB5_6
# %bb.7: # %._crit_edge.i30
# in Loop: Header=BB5_5 Depth=1
incq %rcx
addq $10, %rax
cmpq $10, %rcx
jne .LBB5_5
# %bb.8: # %_Z9gen_arrayi.exit33
xorl %r15d, %r15d
movq %rbx, %r12
.p2align 4, 0x90
.LBB5_9: # %.preheader.i34
# =>This Loop Header: Depth=1
# Child Loop BB5_10 Depth 2
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB5_10: # Parent Loop BB5_9 Depth=1
# => This Inner Loop Header: Depth=2
movss (%r12,%r13,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
.cfi_escape 0x2e, 0x00
movl $.L.str, %edi
movb $1, %al
callq printf
incq %r13
cmpq $10, %r13
jne .LBB5_10
# %bb.11: # %._crit_edge.i38
# in Loop: Header=BB5_9 Depth=1
.cfi_escape 0x2e, 0x00
movl $10, %edi
callq putchar@PLT
incq %r15
addq $40, %r12
cmpq $10, %r15
jne .LBB5_9
# %bb.12: # %_Z11print_arrayPfi.exit
.cfi_escape 0x2e, 0x00
movl $10, %edi
callq putchar@PLT
xorl %r15d, %r15d
movq %r14, %r12
.p2align 4, 0x90
.LBB5_13: # %.preheader.i39
# =>This Loop Header: Depth=1
# Child Loop BB5_14 Depth 2
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB5_14: # Parent Loop BB5_13 Depth=1
# => This Inner Loop Header: Depth=2
movss (%r12,%r13,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
.cfi_escape 0x2e, 0x00
movl $.L.str, %edi
movb $1, %al
callq printf
incq %r13
cmpq $10, %r13
jne .LBB5_14
# %bb.15: # %._crit_edge.i44
# in Loop: Header=BB5_13 Depth=1
.cfi_escape 0x2e, 0x00
movl $10, %edi
callq putchar@PLT
incq %r15
addq $40, %r12
cmpq $10, %r15
jne .LBB5_13
# %bb.16: # %_Z11print_arrayPfi.exit49
.cfi_escape 0x2e, 0x00
movl $10, %edi
callq putchar@PLT
.Ltmp0:
.cfi_escape 0x2e, 0x00
leaq 32(%rsp), %rdi
movl $400, %edx # imm = 0x190
movq %rbx, %rsi
callq _Z15cuda_init_arrayPPfPKfm
.Ltmp1:
# %bb.17:
.Ltmp2:
.cfi_escape 0x2e, 0x00
leaq 24(%rsp), %rdi
movl $400, %edx # imm = 0x190
movq %r14, %rsi
callq _Z15cuda_init_arrayPPfPKfm
.Ltmp3:
# %bb.18:
.Ltmp4:
.cfi_escape 0x2e, 0x00
leaq 16(%rsp), %rdi
movl $400, %esi # imm = 0x190
callq hipMalloc
.Ltmp5:
# %bb.19: # %.noexc
testl %eax, %eax
jne .LBB5_20
# %bb.26: # %_Z15cuda_init_arrayPPfPKfm.exit
.cfi_escape 0x2e, 0x00
movabsq $4294967297, %rdi # imm = 0x100000001
movabsq $42949672970, %rdx # imm = 0xA0000000A
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB5_28
# %bb.27:
movq 32(%rsp), %rax
movq 24(%rsp), %rcx
movq 16(%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
movl $10, 12(%rsp)
movl $10, 8(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
.cfi_escape 0x2e, 0x00
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
.cfi_escape 0x2e, 0x10
leaq 112(%rsp), %r9
movl $_Z4multPKfS0_Pfii, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB5_28:
movq 16(%rsp), %rsi
.cfi_escape 0x2e, 0x00
movl $400, %edx # imm = 0x190
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB5_36
# %bb.29: # %.preheader.i51.preheader
xorl %r14d, %r14d
movq %rbx, %r15
.p2align 4, 0x90
.LBB5_30: # %.preheader.i51
# =>This Loop Header: Depth=1
# Child Loop BB5_31 Depth 2
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB5_31: # Parent Loop BB5_30 Depth=1
# => This Inner Loop Header: Depth=2
movss (%r15,%r12,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
.cfi_escape 0x2e, 0x00
movl $.L.str, %edi
movb $1, %al
callq printf
incq %r12
cmpq $10, %r12
jne .LBB5_31
# %bb.32: # %._crit_edge.i56
# in Loop: Header=BB5_30 Depth=1
.cfi_escape 0x2e, 0x00
movl $10, %edi
callq putchar@PLT
incq %r14
addq $40, %r15
cmpq $10, %r14
jne .LBB5_30
# %bb.33: # %_Z11print_arrayPfi.exit61
.cfi_escape 0x2e, 0x00
movl $10, %edi
callq putchar@PLT
movq 32(%rsp), %rdi
.cfi_escape 0x2e, 0x00
callq hipFree
movq 24(%rsp), %rdi
.cfi_escape 0x2e, 0x00
callq hipFree
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
callq _ZdaPv
xorl %eax, %eax
addq $160, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB5_20:
.cfi_def_cfa_offset 208
.cfi_escape 0x2e, 0x00
movl $4, %edi
movl %eax, %ebx
callq __cxa_allocate_exception
movl %ebx, (%rax)
.Ltmp6:
.cfi_escape 0x2e, 0x00
movl $_ZTI10hipError_t, %esi
movq %rax, %rdi
xorl %edx, %edx
callq __cxa_throw
.Ltmp7:
# %bb.21: # %.noexc50
.LBB5_36:
movq stderr(%rip), %rbx
.cfi_escape 0x2e, 0x00
movl %eax, %edi
callq hipGetErrorString
.cfi_escape 0x2e, 0x00
jmp .LBB5_25
.LBB5_22:
.Ltmp8:
movq %rax, %rbx
cmpl $1, %edx
jne .LBB5_35
# %bb.23:
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
callq __cxa_begin_catch
movl (%rax), %edi
movq stderr(%rip), %rbx
.Ltmp9:
.cfi_escape 0x2e, 0x00
callq hipGetErrorString
.Ltmp10:
# %bb.24:
.cfi_escape 0x2e, 0x00
.LBB5_25:
movl $.L.str.5, %esi
movq %rbx, %rdi
movq %rax, %rdx
xorl %eax, %eax
callq fprintf
.cfi_escape 0x2e, 0x00
movl $1, %edi
callq exit
.LBB5_34:
.Ltmp11:
movq %rax, %rbx
.cfi_escape 0x2e, 0x00
callq __cxa_end_catch
.LBB5_35:
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
callq _Unwind_Resume@PLT
.Lfunc_end5:
.size main, .Lfunc_end5-main
.cfi_endproc
.section .gcc_except_table,"a",@progbits
.p2align 2, 0x0
GCC_except_table5:
.Lexception0:
.byte 255 # @LPStart Encoding = omit
.byte 3 # @TType Encoding = udata4
.uleb128 .Lttbase0-.Lttbaseref0
.Lttbaseref0:
.byte 1 # Call site Encoding = uleb128
.uleb128 .Lcst_end0-.Lcst_begin0
.Lcst_begin0:
.uleb128 .Lfunc_begin0-.Lfunc_begin0 # >> Call Site 1 <<
.uleb128 .Ltmp0-.Lfunc_begin0 # Call between .Lfunc_begin0 and .Ltmp0
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp0-.Lfunc_begin0 # >> Call Site 2 <<
.uleb128 .Ltmp5-.Ltmp0 # Call between .Ltmp0 and .Ltmp5
.uleb128 .Ltmp8-.Lfunc_begin0 # jumps to .Ltmp8
.byte 3 # On action: 2
.uleb128 .Ltmp5-.Lfunc_begin0 # >> Call Site 3 <<
.uleb128 .Ltmp6-.Ltmp5 # Call between .Ltmp5 and .Ltmp6
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp6-.Lfunc_begin0 # >> Call Site 4 <<
.uleb128 .Ltmp7-.Ltmp6 # Call between .Ltmp6 and .Ltmp7
.uleb128 .Ltmp8-.Lfunc_begin0 # jumps to .Ltmp8
.byte 3 # On action: 2
.uleb128 .Ltmp7-.Lfunc_begin0 # >> Call Site 5 <<
.uleb128 .Ltmp9-.Ltmp7 # Call between .Ltmp7 and .Ltmp9
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp9-.Lfunc_begin0 # >> Call Site 6 <<
.uleb128 .Ltmp10-.Ltmp9 # Call between .Ltmp9 and .Ltmp10
.uleb128 .Ltmp11-.Lfunc_begin0 # jumps to .Ltmp11
.byte 0 # On action: cleanup
.uleb128 .Ltmp10-.Lfunc_begin0 # >> Call Site 7 <<
.uleb128 .Lfunc_end5-.Ltmp10 # Call between .Ltmp10 and .Lfunc_end5
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.Lcst_end0:
.byte 0 # >> Action Record 1 <<
# Cleanup
.byte 0 # No further actions
.byte 1 # >> Action Record 2 <<
# Catch TypeInfo 1
.byte 125 # Continue to action 1
.p2align 2, 0x0
# >> Catch TypeInfos <<
.long _ZTI10hipError_t # TypeInfo 1
.Lttbase0:
.p2align 2, 0x0
# -- End function
.text
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB6_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB6_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z4multPKfS0_Pfii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end6:
.size __hip_module_ctor, .Lfunc_end6-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB7_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB7_2:
retq
.Lfunc_end7:
.size __hip_module_dtor, .Lfunc_end7-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z4multPKfS0_Pfii,@object # @_Z4multPKfS0_Pfii
.section .rodata,"a",@progbits
.globl _Z4multPKfS0_Pfii
.p2align 3, 0x0
_Z4multPKfS0_Pfii:
.quad _Z19__device_stub__multPKfS0_Pfii
.size _Z4multPKfS0_Pfii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%5.0f "
.size .L.str, 7
.type _ZTS10hipError_t,@object # @_ZTS10hipError_t
.section .rodata._ZTS10hipError_t,"aG",@progbits,_ZTS10hipError_t,comdat
.weak _ZTS10hipError_t
_ZTS10hipError_t:
.asciz "10hipError_t"
.size _ZTS10hipError_t, 13
.type _ZTI10hipError_t,@object # @_ZTI10hipError_t
.section .rodata._ZTI10hipError_t,"aG",@progbits,_ZTI10hipError_t,comdat
.weak _ZTI10hipError_t
.p2align 3, 0x0
_ZTI10hipError_t:
.quad _ZTVN10__cxxabiv116__enum_type_infoE+16
.quad _ZTS10hipError_t
.size _ZTI10hipError_t, 16
.type .L.str.2,@object # @.str.2
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.2:
.asciz "Block %d %d %d\n"
.size .L.str.2, 16
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Grid %d %d %d\n"
.size .L.str.3, 15
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Failed to allocate device (error code: %s)!\n"
.size .L.str.5, 45
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z4multPKfS0_Pfii"
.size .L__unnamed_1, 18
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z19__device_stub__multPKfS0_Pfii
.addrsig_sym __gxx_personality_v0
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Unwind_Resume
.addrsig_sym _Z4multPKfS0_Pfii
.addrsig_sym _ZTVN10__cxxabiv116__enum_type_infoE
.addrsig_sym _ZTS10hipError_t
.addrsig_sym _ZTI10hipError_t
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <assert.h>
#include <cuda.h>
#include <cuda_runtime.h>
#define N 512
#define MAX_ERR 1e-6
//__global__ void vector_add(float *out, float *a, float *b, int n) {
// int stride = 1;
// int tid = blockIdx.x * blockDim.x + threadIdx.x;
// 0 * 256 + 1 = 1 | BLOCK0 |
// 0 * 256 + 2 = 2
// 1 * 256 + 1 = 257 | BLOCK1 |
// 1 * 256 + 2 = 258
// out[tid] = a[tid] + b[tid];
//}
void print_results(float *C){
printf("[");
for(int i = 0 ; i < 4; i++){
printf("%f,",C[i]);
}
printf("]\n");
}
__global__ void vector_add(float *CUDA_A, float *CUDA_B, float *CUDA_C, int n) {
int tid = blockIdx.x * blockDim.x + threadIdx.x;
CUDA_C[tid] = CUDA_A[tid] + CUDA_B[tid];
}
__global__ void vector_sub(float *CUDA_A, float *CUDA_B, float *CUDA_C, int n) {
int tid = blockIdx.x * blockDim.x + threadIdx.x;
CUDA_C[tid] = CUDA_A[tid] - CUDA_B[tid];
}
__global__ void vector_dot_product(float *CUDA_A, float *CUDA_B, float *CUDA_C,float *CUDA_K, int n) {
int tid = blockIdx.x * blockDim.x + threadIdx.x;
__shared__ float SHARED_K[1024];
CUDA_C[tid] = CUDA_A[tid] * CUDA_B[tid];
// Only one kernel should apply the dot product
__syncthreads();
SHARED_K[tid] = CUDA_C[tid * 2] + CUDA_C[tid * 2 + 1];
__syncthreads();
if (tid == 0){
*CUDA_K = SHARED_K[0] + SHARED_K[1];
}
}
void print_vectors(){
printf("A = {2.0,4.0,6.0,8.0}\n");
printf("B = {1.0,2.0,3.0,10.0}\n");
};
int main(){
float *C, *K;
float *CUDA_A, *CUDA_B, *CUDA_C, *CUDA_K;
// Allocate host memory
float A[4]= {2.0,4.0,6.0,10.0};
float B[4]= {1.0,2.0,3.0,8.0};
C = (float*)malloc(sizeof(float) * N);
K = (float*)malloc(sizeof(float));
// Allocate device memory
cudaMalloc((void**)&CUDA_A, sizeof(float) * N);
cudaMalloc((void**)&CUDA_B, sizeof(float) * N);
cudaMalloc((void**)&CUDA_C, sizeof(float) * N);
cudaMalloc((void**)&CUDA_C, sizeof(float) * N);
cudaMalloc((void**)&CUDA_K, sizeof(float));
// Transfer data from host to device memory
cudaMemcpy(CUDA_A, A, sizeof(float) * N, cudaMemcpyHostToDevice);
cudaMemcpy(CUDA_B, B, sizeof(float) * N, cudaMemcpyHostToDevice);
// Executing kernel
vector_add<<<1,4>>>(CUDA_A, CUDA_B, CUDA_C, N);
cudaMemcpy(C, CUDA_C, sizeof(float) * N, cudaMemcpyDeviceToHost);
//Executing kernel
puts("ADDING");
print_vectors();
print_results(C);
vector_sub<<<1,4>>>(CUDA_A, CUDA_B, CUDA_C, N);
cudaMemcpy(C, CUDA_C, sizeof(float) * N, cudaMemcpyDeviceToHost);
puts("SUBSTRACTING");
print_vectors();
print_results(C);
vector_dot_product<<<1,4>>>(CUDA_A, CUDA_B, CUDA_C, CUDA_K, N);
cudaMemcpy(C, CUDA_C, sizeof(float) * N, cudaMemcpyDeviceToHost);
puts("DOT_PRODUCT");
print_vectors();
print_results(C);
cudaMemcpy(K, CUDA_K, sizeof(float), cudaMemcpyDeviceToHost);
printf("\nDot product result %f\n", *K);
// Deallocate device memory
cudaFree(CUDA_A);
cudaFree(CUDA_B);
cudaFree(CUDA_C);
// Deallocate host memory
//free(A);
//free(B);
free(C);
} | code for sm_80
Function : _Z18vector_dot_productPfS_S_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R13, SR_CTAID.X ; /* 0x00000000000d7919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R12, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff0c7435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R13, R13, c[0x0][0x0], R0 ; /* 0x000000000d0d7a24 */
/* 0x001fca00078e0200 */
/*0060*/ IMAD.WIDE R4, R13, R12, c[0x0][0x168] ; /* 0x00005a000d047625 */
/* 0x000fc800078e020c */
/*0070*/ IMAD.WIDE R2, R13.reuse, R12.reuse, c[0x0][0x160] ; /* 0x000058000d027625 */
/* 0x0c0fe400078e020c */
/*0080*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*0090*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ IMAD.WIDE R6, R13.reuse, R12, c[0x0][0x170] ; /* 0x00005c000d067625 */
/* 0x040fe200078e020c */
/*00b0*/ SHF.L.U32 R10, R13, 0x1, RZ ; /* 0x000000010d0a7819 */
/* 0x000fca00000006ff */
/*00c0*/ IMAD.WIDE R8, R13, 0x4, R6 ; /* 0x000000040d087825 */
/* 0x000fc800078e0206 */
/*00d0*/ IMAD.WIDE R10, R10, R12, c[0x0][0x170] ; /* 0x00005c000a0a7625 */
/* 0x000fc800078e020c */
/*00e0*/ FMUL R15, R4, R3 ; /* 0x00000003040f7220 */
/* 0x004fca0000400000 */
/*00f0*/ STG.E [R6.64], R15 ; /* 0x0000000f06007986 */
/* 0x0001e8000c101904 */
/*0100*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0110*/ LDG.E R9, [R8.64] ; /* 0x0000000408097981 */
/* 0x000ea8000c1e1900 */
/*0120*/ LDG.E R10, [R10.64+0x4] ; /* 0x000004040a0a7981 */
/* 0x000ea2000c1e1900 */
/*0130*/ ISETP.NE.AND P0, PT, R13, RZ, PT ; /* 0x000000ff0d00720c */
/* 0x000fe20003f05270 */
/*0140*/ FADD R0, R10, R9 ; /* 0x000000090a007221 */
/* 0x004fca0000000000 */
/*0150*/ STS [R13.X4], R0 ; /* 0x000000000d007388 */
/* 0x0001e80000004800 */
/*0160*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0170*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0180*/ LDS.64 R4, [RZ] ; /* 0x00000000ff047984 */
/* 0x001e220000000a00 */
/*0190*/ MOV R2, c[0x0][0x178] ; /* 0x00005e0000027a02 */
/* 0x000fc40000000f00 */
/*01a0*/ MOV R3, c[0x0][0x17c] ; /* 0x00005f0000037a02 */
/* 0x000fe20000000f00 */
/*01b0*/ FADD R5, R5, R4 ; /* 0x0000000405057221 */
/* 0x001fca0000000000 */
/*01c0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*01d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01e0*/ BRA 0x1e0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z10vector_subPfS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R6, R6, c[0x0][0x0], R3 ; /* 0x0000000006067a24 */
/* 0x001fca00078e0203 */
/*0060*/ IMAD.WIDE R2, R6, R7, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x000fc800078e0207 */
/*0070*/ IMAD.WIDE R4, R6.reuse, R7.reuse, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x0c0fe400078e0207 */
/*0080*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*0090*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fc800078e0207 */
/*00b0*/ FADD R9, R2, -R5 ; /* 0x8000000502097221 */
/* 0x004fca0000000000 */
/*00c0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00e0*/ BRA 0xe0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z10vector_addPfS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R6, R6, c[0x0][0x0], R3 ; /* 0x0000000006067a24 */
/* 0x001fca00078e0203 */
/*0060*/ IMAD.WIDE R2, R6, R7, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x000fc800078e0207 */
/*0070*/ IMAD.WIDE R4, R6.reuse, R7.reuse, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x0c0fe400078e0207 */
/*0080*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*0090*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fc800078e0207 */
/*00b0*/ FADD R9, R2, R5 ; /* 0x0000000502097221 */
/* 0x004fca0000000000 */
/*00c0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00e0*/ BRA 0xe0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <assert.h>
#include <cuda.h>
#include <cuda_runtime.h>
#define N 512
#define MAX_ERR 1e-6
//__global__ void vector_add(float *out, float *a, float *b, int n) {
// int stride = 1;
// int tid = blockIdx.x * blockDim.x + threadIdx.x;
// 0 * 256 + 1 = 1 | BLOCK0 |
// 0 * 256 + 2 = 2
// 1 * 256 + 1 = 257 | BLOCK1 |
// 1 * 256 + 2 = 258
// out[tid] = a[tid] + b[tid];
//}
void print_results(float *C){
printf("[");
for(int i = 0 ; i < 4; i++){
printf("%f,",C[i]);
}
printf("]\n");
}
__global__ void vector_add(float *CUDA_A, float *CUDA_B, float *CUDA_C, int n) {
int tid = blockIdx.x * blockDim.x + threadIdx.x;
CUDA_C[tid] = CUDA_A[tid] + CUDA_B[tid];
}
__global__ void vector_sub(float *CUDA_A, float *CUDA_B, float *CUDA_C, int n) {
int tid = blockIdx.x * blockDim.x + threadIdx.x;
CUDA_C[tid] = CUDA_A[tid] - CUDA_B[tid];
}
__global__ void vector_dot_product(float *CUDA_A, float *CUDA_B, float *CUDA_C,float *CUDA_K, int n) {
int tid = blockIdx.x * blockDim.x + threadIdx.x;
__shared__ float SHARED_K[1024];
CUDA_C[tid] = CUDA_A[tid] * CUDA_B[tid];
// Only one kernel should apply the dot product
__syncthreads();
SHARED_K[tid] = CUDA_C[tid * 2] + CUDA_C[tid * 2 + 1];
__syncthreads();
if (tid == 0){
*CUDA_K = SHARED_K[0] + SHARED_K[1];
}
}
void print_vectors(){
printf("A = {2.0,4.0,6.0,8.0}\n");
printf("B = {1.0,2.0,3.0,10.0}\n");
};
int main(){
float *C, *K;
float *CUDA_A, *CUDA_B, *CUDA_C, *CUDA_K;
// Allocate host memory
float A[4]= {2.0,4.0,6.0,10.0};
float B[4]= {1.0,2.0,3.0,8.0};
C = (float*)malloc(sizeof(float) * N);
K = (float*)malloc(sizeof(float));
// Allocate device memory
cudaMalloc((void**)&CUDA_A, sizeof(float) * N);
cudaMalloc((void**)&CUDA_B, sizeof(float) * N);
cudaMalloc((void**)&CUDA_C, sizeof(float) * N);
cudaMalloc((void**)&CUDA_C, sizeof(float) * N);
cudaMalloc((void**)&CUDA_K, sizeof(float));
// Transfer data from host to device memory
cudaMemcpy(CUDA_A, A, sizeof(float) * N, cudaMemcpyHostToDevice);
cudaMemcpy(CUDA_B, B, sizeof(float) * N, cudaMemcpyHostToDevice);
// Executing kernel
vector_add<<<1,4>>>(CUDA_A, CUDA_B, CUDA_C, N);
cudaMemcpy(C, CUDA_C, sizeof(float) * N, cudaMemcpyDeviceToHost);
//Executing kernel
puts("ADDING");
print_vectors();
print_results(C);
vector_sub<<<1,4>>>(CUDA_A, CUDA_B, CUDA_C, N);
cudaMemcpy(C, CUDA_C, sizeof(float) * N, cudaMemcpyDeviceToHost);
puts("SUBSTRACTING");
print_vectors();
print_results(C);
vector_dot_product<<<1,4>>>(CUDA_A, CUDA_B, CUDA_C, CUDA_K, N);
cudaMemcpy(C, CUDA_C, sizeof(float) * N, cudaMemcpyDeviceToHost);
puts("DOT_PRODUCT");
print_vectors();
print_results(C);
cudaMemcpy(K, CUDA_K, sizeof(float), cudaMemcpyDeviceToHost);
printf("\nDot product result %f\n", *K);
// Deallocate device memory
cudaFree(CUDA_A);
cudaFree(CUDA_B);
cudaFree(CUDA_C);
// Deallocate host memory
//free(A);
//free(B);
free(C);
} | .file "tmpxft_000e082e_00000000-6_matrix.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "["
.LC1:
.string "%f,"
.LC2:
.string "]\n"
.text
.globl _Z13print_resultsPf
.type _Z13print_resultsPf, @function
_Z13print_resultsPf:
.LFB2057:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
movq %rdi, %rbp
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rbp, %rbx
addq $16, %rbp
leaq .LC1(%rip), %r12
.L4:
pxor %xmm0, %xmm0
cvtss2sd (%rbx), %xmm0
movq %r12, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %rbp, %rbx
jne .L4
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _Z13print_resultsPf, .-_Z13print_resultsPf
.section .rodata.str1.1
.LC3:
.string "A = {2.0,4.0,6.0,8.0}\n"
.LC4:
.string "B = {1.0,2.0,3.0,10.0}\n"
.text
.globl _Z13print_vectorsv
.type _Z13print_vectorsv, @function
_Z13print_vectorsv:
.LFB2058:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _Z13print_vectorsv, .-_Z13print_vectorsv
.globl _Z35__device_stub__Z10vector_addPfS_S_iPfS_S_i
.type _Z35__device_stub__Z10vector_addPfS_S_iPfS_S_i, @function
_Z35__device_stub__Z10vector_addPfS_S_iPfS_S_i:
.LFB2084:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L13
.L9:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L14
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L13:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z10vector_addPfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L9
.L14:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z35__device_stub__Z10vector_addPfS_S_iPfS_S_i, .-_Z35__device_stub__Z10vector_addPfS_S_iPfS_S_i
.globl _Z10vector_addPfS_S_i
.type _Z10vector_addPfS_S_i, @function
_Z10vector_addPfS_S_i:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z10vector_addPfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z10vector_addPfS_S_i, .-_Z10vector_addPfS_S_i
.globl _Z35__device_stub__Z10vector_subPfS_S_iPfS_S_i
.type _Z35__device_stub__Z10vector_subPfS_S_iPfS_S_i, @function
_Z35__device_stub__Z10vector_subPfS_S_iPfS_S_i:
.LFB2086:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L21
.L17:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L22
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L21:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z10vector_subPfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L17
.L22:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2086:
.size _Z35__device_stub__Z10vector_subPfS_S_iPfS_S_i, .-_Z35__device_stub__Z10vector_subPfS_S_iPfS_S_i
.globl _Z10vector_subPfS_S_i
.type _Z10vector_subPfS_S_i, @function
_Z10vector_subPfS_S_i:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z10vector_subPfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _Z10vector_subPfS_S_i, .-_Z10vector_subPfS_S_i
.globl _Z45__device_stub__Z18vector_dot_productPfS_S_S_iPfS_S_S_i
.type _Z45__device_stub__Z18vector_dot_productPfS_S_S_iPfS_S_S_i, @function
_Z45__device_stub__Z18vector_dot_productPfS_S_S_iPfS_S_S_i:
.LFB2088:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movl %r8d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 12(%rsp), %rax
movq %rax, 144(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L29
.L25:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L30
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L29:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 184
pushq 56(%rsp)
.cfi_def_cfa_offset 192
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z18vector_dot_productPfS_S_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L25
.L30:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2088:
.size _Z45__device_stub__Z18vector_dot_productPfS_S_S_iPfS_S_S_i, .-_Z45__device_stub__Z18vector_dot_productPfS_S_S_iPfS_S_S_i
.globl _Z18vector_dot_productPfS_S_S_i
.type _Z18vector_dot_productPfS_S_S_i, @function
_Z18vector_dot_productPfS_S_S_i:
.LFB2089:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z45__device_stub__Z18vector_dot_productPfS_S_S_iPfS_S_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2089:
.size _Z18vector_dot_productPfS_S_S_i, .-_Z18vector_dot_productPfS_S_S_i
.section .rodata.str1.1
.LC12:
.string "ADDING"
.LC13:
.string "SUBSTRACTING"
.LC14:
.string "DOT_PRODUCT"
.LC15:
.string "\nDot product result %f\n"
.text
.globl main
.type main, @function
main:
.LFB2059:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $112, %rsp
.cfi_def_cfa_offset 144
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
movss .LC5(%rip), %xmm0
movss %xmm0, 64(%rsp)
movl $0x40800000, 68(%rsp)
movl $0x40c00000, 72(%rsp)
movl $0x41200000, 76(%rsp)
movl $0x3f800000, 80(%rsp)
movss %xmm0, 84(%rsp)
movl $0x40400000, 88(%rsp)
movl $0x41000000, 92(%rsp)
movl $2048, %edi
call malloc@PLT
movq %rax, %rbx
movl $4, %edi
call malloc@PLT
movq %rax, %rbp
leaq 8(%rsp), %rdi
movl $2048, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $2048, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %r12
movl $2048, %esi
movq %r12, %rdi
call cudaMalloc@PLT
movl $2048, %esi
movq %r12, %rdi
call cudaMalloc@PLT
leaq 32(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
leaq 64(%rsp), %rsi
movl $1, %ecx
movl $2048, %edx
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
leaq 80(%rsp), %rsi
movl $1, %ecx
movl $2048, %edx
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $4, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 52(%rsp), %rdx
movl $1, %ecx
movq 40(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L39
.L34:
movl $2, %ecx
movl $2048, %edx
movq 24(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
leaq .LC12(%rip), %rdi
call puts@PLT
call _Z13print_vectorsv
movq %rbx, %rdi
call _Z13print_resultsPf
movl $4, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 52(%rsp), %rdx
movl $1, %ecx
movq 40(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L40
.L35:
movl $2, %ecx
movl $2048, %edx
movq 24(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
leaq .LC13(%rip), %rdi
call puts@PLT
call _Z13print_vectorsv
movq %rbx, %rdi
call _Z13print_resultsPf
movl $4, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 52(%rsp), %rdx
movl $1, %ecx
movq 40(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L41
.L36:
movl $2, %ecx
movl $2048, %edx
movq 24(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
leaq .LC14(%rip), %rdi
call puts@PLT
call _Z13print_vectorsv
movq %rbx, %rdi
call _Z13print_resultsPf
movl $2, %ecx
movl $4, %edx
movq 32(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
pxor %xmm0, %xmm0
cvtss2sd 0(%rbp), %xmm0
leaq .LC15(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq %rbx, %rdi
call free@PLT
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L42
movl $0, %eax
addq $112, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L39:
.cfi_restore_state
movl $512, %ecx
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z35__device_stub__Z10vector_addPfS_S_iPfS_S_i
jmp .L34
.L40:
movl $512, %ecx
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z35__device_stub__Z10vector_subPfS_S_iPfS_S_i
jmp .L35
.L41:
movl $512, %r8d
movq 32(%rsp), %rcx
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z45__device_stub__Z18vector_dot_productPfS_S_S_iPfS_S_S_i
jmp .L36
.L42:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size main, .-main
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC16:
.string "_Z18vector_dot_productPfS_S_S_i"
.section .rodata.str1.1
.LC17:
.string "_Z10vector_subPfS_S_i"
.LC18:
.string "_Z10vector_addPfS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2091:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC16(%rip), %rdx
movq %rdx, %rcx
leaq _Z18vector_dot_productPfS_S_S_i(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC17(%rip), %rdx
movq %rdx, %rcx
leaq _Z10vector_subPfS_S_i(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC18(%rip), %rdx
movq %rdx, %rcx
leaq _Z10vector_addPfS_S_i(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2091:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC5:
.long 1073741824
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <assert.h>
#include <cuda.h>
#include <cuda_runtime.h>
#define N 512
#define MAX_ERR 1e-6
//__global__ void vector_add(float *out, float *a, float *b, int n) {
// int stride = 1;
// int tid = blockIdx.x * blockDim.x + threadIdx.x;
// 0 * 256 + 1 = 1 | BLOCK0 |
// 0 * 256 + 2 = 2
// 1 * 256 + 1 = 257 | BLOCK1 |
// 1 * 256 + 2 = 258
// out[tid] = a[tid] + b[tid];
//}
void print_results(float *C){
printf("[");
for(int i = 0 ; i < 4; i++){
printf("%f,",C[i]);
}
printf("]\n");
}
__global__ void vector_add(float *CUDA_A, float *CUDA_B, float *CUDA_C, int n) {
int tid = blockIdx.x * blockDim.x + threadIdx.x;
CUDA_C[tid] = CUDA_A[tid] + CUDA_B[tid];
}
__global__ void vector_sub(float *CUDA_A, float *CUDA_B, float *CUDA_C, int n) {
int tid = blockIdx.x * blockDim.x + threadIdx.x;
CUDA_C[tid] = CUDA_A[tid] - CUDA_B[tid];
}
__global__ void vector_dot_product(float *CUDA_A, float *CUDA_B, float *CUDA_C,float *CUDA_K, int n) {
int tid = blockIdx.x * blockDim.x + threadIdx.x;
__shared__ float SHARED_K[1024];
CUDA_C[tid] = CUDA_A[tid] * CUDA_B[tid];
// Only one kernel should apply the dot product
__syncthreads();
SHARED_K[tid] = CUDA_C[tid * 2] + CUDA_C[tid * 2 + 1];
__syncthreads();
if (tid == 0){
*CUDA_K = SHARED_K[0] + SHARED_K[1];
}
}
void print_vectors(){
printf("A = {2.0,4.0,6.0,8.0}\n");
printf("B = {1.0,2.0,3.0,10.0}\n");
};
int main(){
float *C, *K;
float *CUDA_A, *CUDA_B, *CUDA_C, *CUDA_K;
// Allocate host memory
float A[4]= {2.0,4.0,6.0,10.0};
float B[4]= {1.0,2.0,3.0,8.0};
C = (float*)malloc(sizeof(float) * N);
K = (float*)malloc(sizeof(float));
// Allocate device memory
cudaMalloc((void**)&CUDA_A, sizeof(float) * N);
cudaMalloc((void**)&CUDA_B, sizeof(float) * N);
cudaMalloc((void**)&CUDA_C, sizeof(float) * N);
cudaMalloc((void**)&CUDA_C, sizeof(float) * N);
cudaMalloc((void**)&CUDA_K, sizeof(float));
// Transfer data from host to device memory
cudaMemcpy(CUDA_A, A, sizeof(float) * N, cudaMemcpyHostToDevice);
cudaMemcpy(CUDA_B, B, sizeof(float) * N, cudaMemcpyHostToDevice);
// Executing kernel
vector_add<<<1,4>>>(CUDA_A, CUDA_B, CUDA_C, N);
cudaMemcpy(C, CUDA_C, sizeof(float) * N, cudaMemcpyDeviceToHost);
//Executing kernel
puts("ADDING");
print_vectors();
print_results(C);
vector_sub<<<1,4>>>(CUDA_A, CUDA_B, CUDA_C, N);
cudaMemcpy(C, CUDA_C, sizeof(float) * N, cudaMemcpyDeviceToHost);
puts("SUBSTRACTING");
print_vectors();
print_results(C);
vector_dot_product<<<1,4>>>(CUDA_A, CUDA_B, CUDA_C, CUDA_K, N);
cudaMemcpy(C, CUDA_C, sizeof(float) * N, cudaMemcpyDeviceToHost);
puts("DOT_PRODUCT");
print_vectors();
print_results(C);
cudaMemcpy(K, CUDA_K, sizeof(float), cudaMemcpyDeviceToHost);
printf("\nDot product result %f\n", *K);
// Deallocate device memory
cudaFree(CUDA_A);
cudaFree(CUDA_B);
cudaFree(CUDA_C);
// Deallocate host memory
//free(A);
//free(B);
free(C);
} | #include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <assert.h>
#include <hip/hip_runtime.h>
#define N 512
#define MAX_ERR 1e-6
//__global__ void vector_add(float *out, float *a, float *b, int n) {
// int stride = 1;
// int tid = blockIdx.x * blockDim.x + threadIdx.x;
// 0 * 256 + 1 = 1 | BLOCK0 |
// 0 * 256 + 2 = 2
// 1 * 256 + 1 = 257 | BLOCK1 |
// 1 * 256 + 2 = 258
// out[tid] = a[tid] + b[tid];
//}
void print_results(float *C){
printf("[");
for(int i = 0 ; i < 4; i++){
printf("%f,",C[i]);
}
printf("]\n");
}
__global__ void vector_add(float *CUDA_A, float *CUDA_B, float *CUDA_C, int n) {
int tid = blockIdx.x * blockDim.x + threadIdx.x;
CUDA_C[tid] = CUDA_A[tid] + CUDA_B[tid];
}
__global__ void vector_sub(float *CUDA_A, float *CUDA_B, float *CUDA_C, int n) {
int tid = blockIdx.x * blockDim.x + threadIdx.x;
CUDA_C[tid] = CUDA_A[tid] - CUDA_B[tid];
}
__global__ void vector_dot_product(float *CUDA_A, float *CUDA_B, float *CUDA_C,float *CUDA_K, int n) {
int tid = blockIdx.x * blockDim.x + threadIdx.x;
__shared__ float SHARED_K[1024];
CUDA_C[tid] = CUDA_A[tid] * CUDA_B[tid];
// Only one kernel should apply the dot product
__syncthreads();
SHARED_K[tid] = CUDA_C[tid * 2] + CUDA_C[tid * 2 + 1];
__syncthreads();
if (tid == 0){
*CUDA_K = SHARED_K[0] + SHARED_K[1];
}
}
void print_vectors(){
printf("A = {2.0,4.0,6.0,8.0}\n");
printf("B = {1.0,2.0,3.0,10.0}\n");
};
int main(){
float *C, *K;
float *CUDA_A, *CUDA_B, *CUDA_C, *CUDA_K;
// Allocate host memory
float A[4]= {2.0,4.0,6.0,10.0};
float B[4]= {1.0,2.0,3.0,8.0};
C = (float*)malloc(sizeof(float) * N);
K = (float*)malloc(sizeof(float));
// Allocate device memory
hipMalloc((void**)&CUDA_A, sizeof(float) * N);
hipMalloc((void**)&CUDA_B, sizeof(float) * N);
hipMalloc((void**)&CUDA_C, sizeof(float) * N);
hipMalloc((void**)&CUDA_C, sizeof(float) * N);
hipMalloc((void**)&CUDA_K, sizeof(float));
// Transfer data from host to device memory
hipMemcpy(CUDA_A, A, sizeof(float) * N, hipMemcpyHostToDevice);
hipMemcpy(CUDA_B, B, sizeof(float) * N, hipMemcpyHostToDevice);
// Executing kernel
vector_add<<<1,4>>>(CUDA_A, CUDA_B, CUDA_C, N);
hipMemcpy(C, CUDA_C, sizeof(float) * N, hipMemcpyDeviceToHost);
//Executing kernel
puts("ADDING");
print_vectors();
print_results(C);
vector_sub<<<1,4>>>(CUDA_A, CUDA_B, CUDA_C, N);
hipMemcpy(C, CUDA_C, sizeof(float) * N, hipMemcpyDeviceToHost);
puts("SUBSTRACTING");
print_vectors();
print_results(C);
vector_dot_product<<<1,4>>>(CUDA_A, CUDA_B, CUDA_C, CUDA_K, N);
hipMemcpy(C, CUDA_C, sizeof(float) * N, hipMemcpyDeviceToHost);
puts("DOT_PRODUCT");
print_vectors();
print_results(C);
hipMemcpy(K, CUDA_K, sizeof(float), hipMemcpyDeviceToHost);
printf("\nDot product result %f\n", *K);
// Deallocate device memory
hipFree(CUDA_A);
hipFree(CUDA_B);
hipFree(CUDA_C);
// Deallocate host memory
//free(A);
//free(B);
free(C);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <assert.h>
#include <hip/hip_runtime.h>
#define N 512
#define MAX_ERR 1e-6
//__global__ void vector_add(float *out, float *a, float *b, int n) {
// int stride = 1;
// int tid = blockIdx.x * blockDim.x + threadIdx.x;
// 0 * 256 + 1 = 1 | BLOCK0 |
// 0 * 256 + 2 = 2
// 1 * 256 + 1 = 257 | BLOCK1 |
// 1 * 256 + 2 = 258
// out[tid] = a[tid] + b[tid];
//}
void print_results(float *C){
printf("[");
for(int i = 0 ; i < 4; i++){
printf("%f,",C[i]);
}
printf("]\n");
}
__global__ void vector_add(float *CUDA_A, float *CUDA_B, float *CUDA_C, int n) {
int tid = blockIdx.x * blockDim.x + threadIdx.x;
CUDA_C[tid] = CUDA_A[tid] + CUDA_B[tid];
}
__global__ void vector_sub(float *CUDA_A, float *CUDA_B, float *CUDA_C, int n) {
int tid = blockIdx.x * blockDim.x + threadIdx.x;
CUDA_C[tid] = CUDA_A[tid] - CUDA_B[tid];
}
__global__ void vector_dot_product(float *CUDA_A, float *CUDA_B, float *CUDA_C,float *CUDA_K, int n) {
int tid = blockIdx.x * blockDim.x + threadIdx.x;
__shared__ float SHARED_K[1024];
CUDA_C[tid] = CUDA_A[tid] * CUDA_B[tid];
// Only one kernel should apply the dot product
__syncthreads();
SHARED_K[tid] = CUDA_C[tid * 2] + CUDA_C[tid * 2 + 1];
__syncthreads();
if (tid == 0){
*CUDA_K = SHARED_K[0] + SHARED_K[1];
}
}
void print_vectors(){
printf("A = {2.0,4.0,6.0,8.0}\n");
printf("B = {1.0,2.0,3.0,10.0}\n");
};
int main(){
float *C, *K;
float *CUDA_A, *CUDA_B, *CUDA_C, *CUDA_K;
// Allocate host memory
float A[4]= {2.0,4.0,6.0,10.0};
float B[4]= {1.0,2.0,3.0,8.0};
C = (float*)malloc(sizeof(float) * N);
K = (float*)malloc(sizeof(float));
// Allocate device memory
hipMalloc((void**)&CUDA_A, sizeof(float) * N);
hipMalloc((void**)&CUDA_B, sizeof(float) * N);
hipMalloc((void**)&CUDA_C, sizeof(float) * N);
hipMalloc((void**)&CUDA_C, sizeof(float) * N);
hipMalloc((void**)&CUDA_K, sizeof(float));
// Transfer data from host to device memory
hipMemcpy(CUDA_A, A, sizeof(float) * N, hipMemcpyHostToDevice);
hipMemcpy(CUDA_B, B, sizeof(float) * N, hipMemcpyHostToDevice);
// Executing kernel
vector_add<<<1,4>>>(CUDA_A, CUDA_B, CUDA_C, N);
hipMemcpy(C, CUDA_C, sizeof(float) * N, hipMemcpyDeviceToHost);
//Executing kernel
puts("ADDING");
print_vectors();
print_results(C);
vector_sub<<<1,4>>>(CUDA_A, CUDA_B, CUDA_C, N);
hipMemcpy(C, CUDA_C, sizeof(float) * N, hipMemcpyDeviceToHost);
puts("SUBSTRACTING");
print_vectors();
print_results(C);
vector_dot_product<<<1,4>>>(CUDA_A, CUDA_B, CUDA_C, CUDA_K, N);
hipMemcpy(C, CUDA_C, sizeof(float) * N, hipMemcpyDeviceToHost);
puts("DOT_PRODUCT");
print_vectors();
print_results(C);
hipMemcpy(K, CUDA_K, sizeof(float), hipMemcpyDeviceToHost);
printf("\nDot product result %f\n", *K);
// Deallocate device memory
hipFree(CUDA_A);
hipFree(CUDA_B);
hipFree(CUDA_C);
// Deallocate host memory
//free(A);
//free(B);
free(C);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10vector_addPfS_S_i
.globl _Z10vector_addPfS_S_i
.p2align 8
.type _Z10vector_addPfS_S_i,@function
_Z10vector_addPfS_S_i:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x2c
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v2, v3
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10vector_addPfS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10vector_addPfS_S_i, .Lfunc_end0-_Z10vector_addPfS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z10vector_subPfS_S_i
.globl _Z10vector_subPfS_S_i
.p2align 8
.type _Z10vector_subPfS_S_i,@function
_Z10vector_subPfS_S_i:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x2c
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_sub_f32_e32 v2, v2, v3
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10vector_subPfS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z10vector_subPfS_S_i, .Lfunc_end1-_Z10vector_subPfS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z18vector_dot_productPfS_S_S_i
.globl _Z18vector_dot_productPfS_S_S_i
.p2align 8
.type _Z18vector_dot_productPfS_S_S_i,@function
_Z18vector_dot_productPfS_S_S_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x34
s_load_b128 s[4:7], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_load_b64 s[2:3], s[0:1], 0x10
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
v_add_co_u32 v4, vcc_lo, s4, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v3, vcc_lo
v_add_co_u32 v6, vcc_lo, s6, v2
v_add_co_ci_u32_e32 v7, vcc_lo, s7, v3, vcc_lo
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s2, v2
global_load_b32 v0, v[4:5], off
global_load_b32 v8, v[6:7], off
v_lshlrev_b32_e32 v4, 1, v1
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_or_b32_e32 v6, 1, v4
v_ashrrev_i32_e32 v5, 31, v4
v_ashrrev_i32_e32 v7, 31, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[4:5], 2, v[4:5]
v_lshlrev_b64 v[6:7], 2, v[6:7]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v4, vcc_lo, s2, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v6, vcc_lo, s2, v6
v_add_co_ci_u32_e32 v7, vcc_lo, s3, v7, vcc_lo
s_mov_b32 s2, exec_lo
s_waitcnt vmcnt(0)
v_mul_f32_e32 v0, v0, v8
global_store_b32 v[2:3], v0, off
v_lshlrev_b32_e32 v3, 2, v1
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
s_clause 0x1
global_load_b32 v0, v[4:5], off
global_load_b32 v2, v[6:7], off
s_waitcnt vmcnt(0)
v_add_f32_e32 v0, v0, v2
ds_store_b32 v3, v0
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_eq_u32_e32 0, v1
s_cbranch_execz .LBB2_2
v_mov_b32_e32 v2, 0
s_load_b64 s[0:1], s[0:1], 0x18
ds_load_2addr_b32 v[0:1], v2 offset1:1
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v0, v0, v1
global_store_b32 v2, v0, s[0:1]
.LBB2_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z18vector_dot_productPfS_S_S_i
.amdhsa_group_segment_fixed_size 4096
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end2:
.size _Z18vector_dot_productPfS_S_S_i, .Lfunc_end2-_Z18vector_dot_productPfS_S_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10vector_addPfS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z10vector_addPfS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10vector_subPfS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z10vector_subPfS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 4096
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z18vector_dot_productPfS_S_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z18vector_dot_productPfS_S_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <assert.h>
#include <hip/hip_runtime.h>
#define N 512
#define MAX_ERR 1e-6
//__global__ void vector_add(float *out, float *a, float *b, int n) {
// int stride = 1;
// int tid = blockIdx.x * blockDim.x + threadIdx.x;
// 0 * 256 + 1 = 1 | BLOCK0 |
// 0 * 256 + 2 = 2
// 1 * 256 + 1 = 257 | BLOCK1 |
// 1 * 256 + 2 = 258
// out[tid] = a[tid] + b[tid];
//}
void print_results(float *C){
printf("[");
for(int i = 0 ; i < 4; i++){
printf("%f,",C[i]);
}
printf("]\n");
}
__global__ void vector_add(float *CUDA_A, float *CUDA_B, float *CUDA_C, int n) {
int tid = blockIdx.x * blockDim.x + threadIdx.x;
CUDA_C[tid] = CUDA_A[tid] + CUDA_B[tid];
}
__global__ void vector_sub(float *CUDA_A, float *CUDA_B, float *CUDA_C, int n) {
int tid = blockIdx.x * blockDim.x + threadIdx.x;
CUDA_C[tid] = CUDA_A[tid] - CUDA_B[tid];
}
__global__ void vector_dot_product(float *CUDA_A, float *CUDA_B, float *CUDA_C,float *CUDA_K, int n) {
int tid = blockIdx.x * blockDim.x + threadIdx.x;
__shared__ float SHARED_K[1024];
CUDA_C[tid] = CUDA_A[tid] * CUDA_B[tid];
// Only one kernel should apply the dot product
__syncthreads();
SHARED_K[tid] = CUDA_C[tid * 2] + CUDA_C[tid * 2 + 1];
__syncthreads();
if (tid == 0){
*CUDA_K = SHARED_K[0] + SHARED_K[1];
}
}
void print_vectors(){
printf("A = {2.0,4.0,6.0,8.0}\n");
printf("B = {1.0,2.0,3.0,10.0}\n");
};
int main(){
float *C, *K;
float *CUDA_A, *CUDA_B, *CUDA_C, *CUDA_K;
// Allocate host memory
float A[4]= {2.0,4.0,6.0,10.0};
float B[4]= {1.0,2.0,3.0,8.0};
C = (float*)malloc(sizeof(float) * N);
K = (float*)malloc(sizeof(float));
// Allocate device memory
hipMalloc((void**)&CUDA_A, sizeof(float) * N);
hipMalloc((void**)&CUDA_B, sizeof(float) * N);
hipMalloc((void**)&CUDA_C, sizeof(float) * N);
hipMalloc((void**)&CUDA_C, sizeof(float) * N);
hipMalloc((void**)&CUDA_K, sizeof(float));
// Transfer data from host to device memory
hipMemcpy(CUDA_A, A, sizeof(float) * N, hipMemcpyHostToDevice);
hipMemcpy(CUDA_B, B, sizeof(float) * N, hipMemcpyHostToDevice);
// Executing kernel
vector_add<<<1,4>>>(CUDA_A, CUDA_B, CUDA_C, N);
hipMemcpy(C, CUDA_C, sizeof(float) * N, hipMemcpyDeviceToHost);
//Executing kernel
puts("ADDING");
print_vectors();
print_results(C);
vector_sub<<<1,4>>>(CUDA_A, CUDA_B, CUDA_C, N);
hipMemcpy(C, CUDA_C, sizeof(float) * N, hipMemcpyDeviceToHost);
puts("SUBSTRACTING");
print_vectors();
print_results(C);
vector_dot_product<<<1,4>>>(CUDA_A, CUDA_B, CUDA_C, CUDA_K, N);
hipMemcpy(C, CUDA_C, sizeof(float) * N, hipMemcpyDeviceToHost);
puts("DOT_PRODUCT");
print_vectors();
print_results(C);
hipMemcpy(K, CUDA_K, sizeof(float), hipMemcpyDeviceToHost);
printf("\nDot product result %f\n", *K);
// Deallocate device memory
hipFree(CUDA_A);
hipFree(CUDA_B);
hipFree(CUDA_C);
// Deallocate host memory
//free(A);
//free(B);
free(C);
} | .text
.file "matrix.hip"
.globl _Z13print_resultsPf # -- Begin function _Z13print_resultsPf
.p2align 4, 0x90
.type _Z13print_resultsPf,@function
_Z13print_resultsPf: # @_Z13print_resultsPf
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movq %rdi, %rbx
movl $91, %edi
callq putchar@PLT
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB0_1: # =>This Inner Loop Header: Depth=1
movss (%rbx,%r14,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.1, %edi
movb $1, %al
callq printf
incq %r14
cmpq $4, %r14
jne .LBB0_1
# %bb.2:
movl $.Lstr, %edi
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
jmp puts # TAILCALL
.Lfunc_end0:
.size _Z13print_resultsPf, .Lfunc_end0-_Z13print_resultsPf
.cfi_endproc
# -- End function
.globl _Z25__device_stub__vector_addPfS_S_i # -- Begin function _Z25__device_stub__vector_addPfS_S_i
.p2align 4, 0x90
.type _Z25__device_stub__vector_addPfS_S_i,@function
_Z25__device_stub__vector_addPfS_S_i: # @_Z25__device_stub__vector_addPfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10vector_addPfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end1:
.size _Z25__device_stub__vector_addPfS_S_i, .Lfunc_end1-_Z25__device_stub__vector_addPfS_S_i
.cfi_endproc
# -- End function
.globl _Z25__device_stub__vector_subPfS_S_i # -- Begin function _Z25__device_stub__vector_subPfS_S_i
.p2align 4, 0x90
.type _Z25__device_stub__vector_subPfS_S_i,@function
_Z25__device_stub__vector_subPfS_S_i: # @_Z25__device_stub__vector_subPfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10vector_subPfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end2:
.size _Z25__device_stub__vector_subPfS_S_i, .Lfunc_end2-_Z25__device_stub__vector_subPfS_S_i
.cfi_endproc
# -- End function
.globl _Z33__device_stub__vector_dot_productPfS_S_S_i # -- Begin function _Z33__device_stub__vector_dot_productPfS_S_S_i
.p2align 4, 0x90
.type _Z33__device_stub__vector_dot_productPfS_S_S_i,@function
_Z33__device_stub__vector_dot_productPfS_S_S_i: # @_Z33__device_stub__vector_dot_productPfS_S_S_i
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movl %r8d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 12(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z18vector_dot_productPfS_S_S_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end3:
.size _Z33__device_stub__vector_dot_productPfS_S_S_i, .Lfunc_end3-_Z33__device_stub__vector_dot_productPfS_S_S_i
.cfi_endproc
# -- End function
.globl _Z13print_vectorsv # -- Begin function _Z13print_vectorsv
.p2align 4, 0x90
.type _Z13print_vectorsv,@function
_Z13print_vectorsv: # @_Z13print_vectorsv
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
movl $.Lstr.1, %edi
callq puts
movl $.Lstr.2, %edi
popq %rax
.cfi_def_cfa_offset 8
jmp puts # TAILCALL
.Lfunc_end4:
.size _Z13print_vectorsv, .Lfunc_end4-_Z13print_vectorsv
.cfi_endproc
# -- End function
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function main
.LCPI5_0:
.long 0x40000000 # float 2
.long 0x40800000 # float 4
.long 0x40c00000 # float 6
.long 0x41200000 # float 10
.LCPI5_1:
.long 0x3f800000 # float 1
.long 0x40000000 # float 2
.long 0x40400000 # float 3
.long 0x41000000 # float 8
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $192, %rsp
.cfi_def_cfa_offset 240
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movabsq $4294967297, %r15 # imm = 0x100000001
movaps .LCPI5_0(%rip), %xmm0 # xmm0 = [2.0E+0,4.0E+0,6.0E+0,1.0E+1]
movaps %xmm0, 176(%rsp)
movaps .LCPI5_1(%rip), %xmm0 # xmm0 = [1.0E+0,2.0E+0,3.0E+0,8.0E+0]
movaps %xmm0, 160(%rsp)
movl $2048, %edi # imm = 0x800
callq malloc
movq %rax, %rbx
movl $4, %edi
callq malloc
movq %rax, %r14
leaq 16(%rsp), %rdi
movl $2048, %esi # imm = 0x800
callq hipMalloc
leaq 8(%rsp), %rdi
movl $2048, %esi # imm = 0x800
callq hipMalloc
movq %rsp, %r12
movl $2048, %esi # imm = 0x800
movq %r12, %rdi
callq hipMalloc
movl $2048, %esi # imm = 0x800
movq %r12, %rdi
callq hipMalloc
leaq 152(%rsp), %rdi
movl $4, %esi
callq hipMalloc
movq 16(%rsp), %rdi
leaq 176(%rsp), %rsi
movl $2048, %edx # imm = 0x800
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
leaq 160(%rsp), %rsi
movl $2048, %edx # imm = 0x800
movl $1, %ecx
callq hipMemcpy
leaq 3(%r15), %r12
movq %r15, %rdi
movl $1, %esi
movq %r12, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB5_2
# %bb.1:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq (%rsp), %rdx
movq %rax, 96(%rsp)
movq %rcx, 88(%rsp)
movq %rdx, 80(%rsp)
movl $512, 24(%rsp) # imm = 0x200
leaq 96(%rsp), %rax
movq %rax, 112(%rsp)
leaq 88(%rsp), %rax
movq %rax, 120(%rsp)
leaq 80(%rsp), %rax
movq %rax, 128(%rsp)
leaq 24(%rsp), %rax
movq %rax, 136(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 72(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z10vector_addPfS_S_i, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 80(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB5_2:
movq (%rsp), %rsi
movl $2048, %edx # imm = 0x800
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
movl $.L.str.5, %edi
callq puts
movl $.Lstr.1, %edi
callq puts
movl $.Lstr.2, %edi
callq puts
movl $91, %edi
callq putchar@PLT
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB5_3: # =>This Inner Loop Header: Depth=1
movss (%rbx,%r13,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.1, %edi
movb $1, %al
callq printf
incq %r13
cmpq $4, %r13
jne .LBB5_3
# %bb.4: # %_Z13print_resultsPf.exit
movl $.Lstr, %edi
callq puts
movq %r15, %rdi
movl $1, %esi
movq %r12, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB5_6
# %bb.5:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq (%rsp), %rdx
movq %rax, 96(%rsp)
movq %rcx, 88(%rsp)
movq %rdx, 80(%rsp)
movl $512, 24(%rsp) # imm = 0x200
leaq 96(%rsp), %rax
movq %rax, 112(%rsp)
leaq 88(%rsp), %rax
movq %rax, 120(%rsp)
leaq 80(%rsp), %rax
movq %rax, 128(%rsp)
leaq 24(%rsp), %rax
movq %rax, 136(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 72(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z10vector_subPfS_S_i, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 80(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB5_6:
movq (%rsp), %rsi
movl $2048, %edx # imm = 0x800
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
movl $.L.str.6, %edi
callq puts
movl $.Lstr.1, %edi
callq puts
movl $.Lstr.2, %edi
callq puts
movl $91, %edi
callq putchar@PLT
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB5_7: # =>This Inner Loop Header: Depth=1
movss (%rbx,%r13,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.1, %edi
movb $1, %al
callq printf
incq %r13
cmpq $4, %r13
jne .LBB5_7
# %bb.8: # %_Z13print_resultsPf.exit35
movl $.Lstr, %edi
callq puts
movq %r15, %rdi
movl $1, %esi
movq %r12, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB5_10
# %bb.9:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq (%rsp), %rdx
movq 152(%rsp), %rsi
movq %rax, 96(%rsp)
movq %rcx, 88(%rsp)
movq %rdx, 80(%rsp)
movq %rsi, 72(%rsp)
movl $512, 108(%rsp) # imm = 0x200
leaq 96(%rsp), %rax
movq %rax, 112(%rsp)
leaq 88(%rsp), %rax
movq %rax, 120(%rsp)
leaq 80(%rsp), %rax
movq %rax, 128(%rsp)
leaq 72(%rsp), %rax
movq %rax, 136(%rsp)
leaq 108(%rsp), %rax
movq %rax, 144(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z18vector_dot_productPfS_S_S_i, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB5_10:
movq (%rsp), %rsi
movl $2048, %edx # imm = 0x800
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
movl $.L.str.7, %edi
callq puts
movl $.Lstr.1, %edi
callq puts
movl $.Lstr.2, %edi
callq puts
movl $91, %edi
callq putchar@PLT
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB5_11: # =>This Inner Loop Header: Depth=1
movss (%rbx,%r15,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.1, %edi
movb $1, %al
callq printf
incq %r15
cmpq $4, %r15
jne .LBB5_11
# %bb.12: # %_Z13print_resultsPf.exit49
movl $.Lstr, %edi
callq puts
movq 152(%rsp), %rsi
movl $4, %edx
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
movss (%r14), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.8, %edi
movb $1, %al
callq printf
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq free
xorl %eax, %eax
addq $192, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end5:
.size main, .Lfunc_end5-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB6_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB6_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10vector_addPfS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10vector_subPfS_S_i, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z18vector_dot_productPfS_S_S_i, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end6:
.size __hip_module_ctor, .Lfunc_end6-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB7_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB7_2:
retq
.Lfunc_end7:
.size __hip_module_dtor, .Lfunc_end7-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "%f,"
.size .L.str.1, 4
.type _Z10vector_addPfS_S_i,@object # @_Z10vector_addPfS_S_i
.section .rodata,"a",@progbits
.globl _Z10vector_addPfS_S_i
.p2align 3, 0x0
_Z10vector_addPfS_S_i:
.quad _Z25__device_stub__vector_addPfS_S_i
.size _Z10vector_addPfS_S_i, 8
.type _Z10vector_subPfS_S_i,@object # @_Z10vector_subPfS_S_i
.globl _Z10vector_subPfS_S_i
.p2align 3, 0x0
_Z10vector_subPfS_S_i:
.quad _Z25__device_stub__vector_subPfS_S_i
.size _Z10vector_subPfS_S_i, 8
.type _Z18vector_dot_productPfS_S_S_i,@object # @_Z18vector_dot_productPfS_S_S_i
.globl _Z18vector_dot_productPfS_S_S_i
.p2align 3, 0x0
_Z18vector_dot_productPfS_S_S_i:
.quad _Z33__device_stub__vector_dot_productPfS_S_S_i
.size _Z18vector_dot_productPfS_S_S_i, 8
.type .L.str.5,@object # @.str.5
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.5:
.asciz "ADDING"
.size .L.str.5, 7
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "SUBSTRACTING"
.size .L.str.6, 13
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "DOT_PRODUCT"
.size .L.str.7, 12
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "\nDot product result %f\n"
.size .L.str.8, 24
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z10vector_addPfS_S_i"
.size .L__unnamed_1, 22
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z10vector_subPfS_S_i"
.size .L__unnamed_2, 22
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z18vector_dot_productPfS_S_S_i"
.size .L__unnamed_3, 32
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "]"
.size .Lstr, 2
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "A = {2.0,4.0,6.0,8.0}"
.size .Lstr.1, 22
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "B = {1.0,2.0,3.0,10.0}"
.size .Lstr.2, 23
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__vector_addPfS_S_i
.addrsig_sym _Z25__device_stub__vector_subPfS_S_i
.addrsig_sym _Z33__device_stub__vector_dot_productPfS_S_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10vector_addPfS_S_i
.addrsig_sym _Z10vector_subPfS_S_i
.addrsig_sym _Z18vector_dot_productPfS_S_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z18vector_dot_productPfS_S_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R13, SR_CTAID.X ; /* 0x00000000000d7919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R12, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff0c7435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R13, R13, c[0x0][0x0], R0 ; /* 0x000000000d0d7a24 */
/* 0x001fca00078e0200 */
/*0060*/ IMAD.WIDE R4, R13, R12, c[0x0][0x168] ; /* 0x00005a000d047625 */
/* 0x000fc800078e020c */
/*0070*/ IMAD.WIDE R2, R13.reuse, R12.reuse, c[0x0][0x160] ; /* 0x000058000d027625 */
/* 0x0c0fe400078e020c */
/*0080*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*0090*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ IMAD.WIDE R6, R13.reuse, R12, c[0x0][0x170] ; /* 0x00005c000d067625 */
/* 0x040fe200078e020c */
/*00b0*/ SHF.L.U32 R10, R13, 0x1, RZ ; /* 0x000000010d0a7819 */
/* 0x000fca00000006ff */
/*00c0*/ IMAD.WIDE R8, R13, 0x4, R6 ; /* 0x000000040d087825 */
/* 0x000fc800078e0206 */
/*00d0*/ IMAD.WIDE R10, R10, R12, c[0x0][0x170] ; /* 0x00005c000a0a7625 */
/* 0x000fc800078e020c */
/*00e0*/ FMUL R15, R4, R3 ; /* 0x00000003040f7220 */
/* 0x004fca0000400000 */
/*00f0*/ STG.E [R6.64], R15 ; /* 0x0000000f06007986 */
/* 0x0001e8000c101904 */
/*0100*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0110*/ LDG.E R9, [R8.64] ; /* 0x0000000408097981 */
/* 0x000ea8000c1e1900 */
/*0120*/ LDG.E R10, [R10.64+0x4] ; /* 0x000004040a0a7981 */
/* 0x000ea2000c1e1900 */
/*0130*/ ISETP.NE.AND P0, PT, R13, RZ, PT ; /* 0x000000ff0d00720c */
/* 0x000fe20003f05270 */
/*0140*/ FADD R0, R10, R9 ; /* 0x000000090a007221 */
/* 0x004fca0000000000 */
/*0150*/ STS [R13.X4], R0 ; /* 0x000000000d007388 */
/* 0x0001e80000004800 */
/*0160*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0170*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0180*/ LDS.64 R4, [RZ] ; /* 0x00000000ff047984 */
/* 0x001e220000000a00 */
/*0190*/ MOV R2, c[0x0][0x178] ; /* 0x00005e0000027a02 */
/* 0x000fc40000000f00 */
/*01a0*/ MOV R3, c[0x0][0x17c] ; /* 0x00005f0000037a02 */
/* 0x000fe20000000f00 */
/*01b0*/ FADD R5, R5, R4 ; /* 0x0000000405057221 */
/* 0x001fca0000000000 */
/*01c0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*01d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01e0*/ BRA 0x1e0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z10vector_subPfS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R6, R6, c[0x0][0x0], R3 ; /* 0x0000000006067a24 */
/* 0x001fca00078e0203 */
/*0060*/ IMAD.WIDE R2, R6, R7, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x000fc800078e0207 */
/*0070*/ IMAD.WIDE R4, R6.reuse, R7.reuse, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x0c0fe400078e0207 */
/*0080*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*0090*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fc800078e0207 */
/*00b0*/ FADD R9, R2, -R5 ; /* 0x8000000502097221 */
/* 0x004fca0000000000 */
/*00c0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00e0*/ BRA 0xe0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z10vector_addPfS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R6, R6, c[0x0][0x0], R3 ; /* 0x0000000006067a24 */
/* 0x001fca00078e0203 */
/*0060*/ IMAD.WIDE R2, R6, R7, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x000fc800078e0207 */
/*0070*/ IMAD.WIDE R4, R6.reuse, R7.reuse, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x0c0fe400078e0207 */
/*0080*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*0090*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fc800078e0207 */
/*00b0*/ FADD R9, R2, R5 ; /* 0x0000000502097221 */
/* 0x004fca0000000000 */
/*00c0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00e0*/ BRA 0xe0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10vector_addPfS_S_i
.globl _Z10vector_addPfS_S_i
.p2align 8
.type _Z10vector_addPfS_S_i,@function
_Z10vector_addPfS_S_i:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x2c
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v2, v3
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10vector_addPfS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10vector_addPfS_S_i, .Lfunc_end0-_Z10vector_addPfS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z10vector_subPfS_S_i
.globl _Z10vector_subPfS_S_i
.p2align 8
.type _Z10vector_subPfS_S_i,@function
_Z10vector_subPfS_S_i:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x2c
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_sub_f32_e32 v2, v2, v3
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10vector_subPfS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z10vector_subPfS_S_i, .Lfunc_end1-_Z10vector_subPfS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z18vector_dot_productPfS_S_S_i
.globl _Z18vector_dot_productPfS_S_S_i
.p2align 8
.type _Z18vector_dot_productPfS_S_S_i,@function
_Z18vector_dot_productPfS_S_S_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x34
s_load_b128 s[4:7], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_load_b64 s[2:3], s[0:1], 0x10
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
v_add_co_u32 v4, vcc_lo, s4, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v3, vcc_lo
v_add_co_u32 v6, vcc_lo, s6, v2
v_add_co_ci_u32_e32 v7, vcc_lo, s7, v3, vcc_lo
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s2, v2
global_load_b32 v0, v[4:5], off
global_load_b32 v8, v[6:7], off
v_lshlrev_b32_e32 v4, 1, v1
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_or_b32_e32 v6, 1, v4
v_ashrrev_i32_e32 v5, 31, v4
v_ashrrev_i32_e32 v7, 31, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[4:5], 2, v[4:5]
v_lshlrev_b64 v[6:7], 2, v[6:7]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v4, vcc_lo, s2, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v6, vcc_lo, s2, v6
v_add_co_ci_u32_e32 v7, vcc_lo, s3, v7, vcc_lo
s_mov_b32 s2, exec_lo
s_waitcnt vmcnt(0)
v_mul_f32_e32 v0, v0, v8
global_store_b32 v[2:3], v0, off
v_lshlrev_b32_e32 v3, 2, v1
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
s_clause 0x1
global_load_b32 v0, v[4:5], off
global_load_b32 v2, v[6:7], off
s_waitcnt vmcnt(0)
v_add_f32_e32 v0, v0, v2
ds_store_b32 v3, v0
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_eq_u32_e32 0, v1
s_cbranch_execz .LBB2_2
v_mov_b32_e32 v2, 0
s_load_b64 s[0:1], s[0:1], 0x18
ds_load_2addr_b32 v[0:1], v2 offset1:1
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v0, v0, v1
global_store_b32 v2, v0, s[0:1]
.LBB2_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z18vector_dot_productPfS_S_S_i
.amdhsa_group_segment_fixed_size 4096
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end2:
.size _Z18vector_dot_productPfS_S_S_i, .Lfunc_end2-_Z18vector_dot_productPfS_S_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10vector_addPfS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z10vector_addPfS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10vector_subPfS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z10vector_subPfS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 4096
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z18vector_dot_productPfS_S_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z18vector_dot_productPfS_S_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000e082e_00000000-6_matrix.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "["
.LC1:
.string "%f,"
.LC2:
.string "]\n"
.text
.globl _Z13print_resultsPf
.type _Z13print_resultsPf, @function
_Z13print_resultsPf:
.LFB2057:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
movq %rdi, %rbp
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rbp, %rbx
addq $16, %rbp
leaq .LC1(%rip), %r12
.L4:
pxor %xmm0, %xmm0
cvtss2sd (%rbx), %xmm0
movq %r12, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %rbp, %rbx
jne .L4
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _Z13print_resultsPf, .-_Z13print_resultsPf
.section .rodata.str1.1
.LC3:
.string "A = {2.0,4.0,6.0,8.0}\n"
.LC4:
.string "B = {1.0,2.0,3.0,10.0}\n"
.text
.globl _Z13print_vectorsv
.type _Z13print_vectorsv, @function
_Z13print_vectorsv:
.LFB2058:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _Z13print_vectorsv, .-_Z13print_vectorsv
.globl _Z35__device_stub__Z10vector_addPfS_S_iPfS_S_i
.type _Z35__device_stub__Z10vector_addPfS_S_iPfS_S_i, @function
_Z35__device_stub__Z10vector_addPfS_S_iPfS_S_i:
.LFB2084:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L13
.L9:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L14
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L13:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z10vector_addPfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L9
.L14:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z35__device_stub__Z10vector_addPfS_S_iPfS_S_i, .-_Z35__device_stub__Z10vector_addPfS_S_iPfS_S_i
.globl _Z10vector_addPfS_S_i
.type _Z10vector_addPfS_S_i, @function
_Z10vector_addPfS_S_i:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z10vector_addPfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z10vector_addPfS_S_i, .-_Z10vector_addPfS_S_i
.globl _Z35__device_stub__Z10vector_subPfS_S_iPfS_S_i
.type _Z35__device_stub__Z10vector_subPfS_S_iPfS_S_i, @function
_Z35__device_stub__Z10vector_subPfS_S_iPfS_S_i:
.LFB2086:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L21
.L17:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L22
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L21:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z10vector_subPfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L17
.L22:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2086:
.size _Z35__device_stub__Z10vector_subPfS_S_iPfS_S_i, .-_Z35__device_stub__Z10vector_subPfS_S_iPfS_S_i
.globl _Z10vector_subPfS_S_i
.type _Z10vector_subPfS_S_i, @function
_Z10vector_subPfS_S_i:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z10vector_subPfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _Z10vector_subPfS_S_i, .-_Z10vector_subPfS_S_i
.globl _Z45__device_stub__Z18vector_dot_productPfS_S_S_iPfS_S_S_i
.type _Z45__device_stub__Z18vector_dot_productPfS_S_S_iPfS_S_S_i, @function
_Z45__device_stub__Z18vector_dot_productPfS_S_S_iPfS_S_S_i:
.LFB2088:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movl %r8d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 12(%rsp), %rax
movq %rax, 144(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L29
.L25:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L30
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L29:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 184
pushq 56(%rsp)
.cfi_def_cfa_offset 192
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z18vector_dot_productPfS_S_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L25
.L30:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2088:
.size _Z45__device_stub__Z18vector_dot_productPfS_S_S_iPfS_S_S_i, .-_Z45__device_stub__Z18vector_dot_productPfS_S_S_iPfS_S_S_i
.globl _Z18vector_dot_productPfS_S_S_i
.type _Z18vector_dot_productPfS_S_S_i, @function
_Z18vector_dot_productPfS_S_S_i:
.LFB2089:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z45__device_stub__Z18vector_dot_productPfS_S_S_iPfS_S_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2089:
.size _Z18vector_dot_productPfS_S_S_i, .-_Z18vector_dot_productPfS_S_S_i
.section .rodata.str1.1
.LC12:
.string "ADDING"
.LC13:
.string "SUBSTRACTING"
.LC14:
.string "DOT_PRODUCT"
.LC15:
.string "\nDot product result %f\n"
.text
.globl main
.type main, @function
main:
.LFB2059:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $112, %rsp
.cfi_def_cfa_offset 144
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
movss .LC5(%rip), %xmm0
movss %xmm0, 64(%rsp)
movl $0x40800000, 68(%rsp)
movl $0x40c00000, 72(%rsp)
movl $0x41200000, 76(%rsp)
movl $0x3f800000, 80(%rsp)
movss %xmm0, 84(%rsp)
movl $0x40400000, 88(%rsp)
movl $0x41000000, 92(%rsp)
movl $2048, %edi
call malloc@PLT
movq %rax, %rbx
movl $4, %edi
call malloc@PLT
movq %rax, %rbp
leaq 8(%rsp), %rdi
movl $2048, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $2048, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %r12
movl $2048, %esi
movq %r12, %rdi
call cudaMalloc@PLT
movl $2048, %esi
movq %r12, %rdi
call cudaMalloc@PLT
leaq 32(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
leaq 64(%rsp), %rsi
movl $1, %ecx
movl $2048, %edx
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
leaq 80(%rsp), %rsi
movl $1, %ecx
movl $2048, %edx
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $4, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 52(%rsp), %rdx
movl $1, %ecx
movq 40(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L39
.L34:
movl $2, %ecx
movl $2048, %edx
movq 24(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
leaq .LC12(%rip), %rdi
call puts@PLT
call _Z13print_vectorsv
movq %rbx, %rdi
call _Z13print_resultsPf
movl $4, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 52(%rsp), %rdx
movl $1, %ecx
movq 40(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L40
.L35:
movl $2, %ecx
movl $2048, %edx
movq 24(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
leaq .LC13(%rip), %rdi
call puts@PLT
call _Z13print_vectorsv
movq %rbx, %rdi
call _Z13print_resultsPf
movl $4, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 52(%rsp), %rdx
movl $1, %ecx
movq 40(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L41
.L36:
movl $2, %ecx
movl $2048, %edx
movq 24(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
leaq .LC14(%rip), %rdi
call puts@PLT
call _Z13print_vectorsv
movq %rbx, %rdi
call _Z13print_resultsPf
movl $2, %ecx
movl $4, %edx
movq 32(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
pxor %xmm0, %xmm0
cvtss2sd 0(%rbp), %xmm0
leaq .LC15(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq %rbx, %rdi
call free@PLT
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L42
movl $0, %eax
addq $112, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L39:
.cfi_restore_state
movl $512, %ecx
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z35__device_stub__Z10vector_addPfS_S_iPfS_S_i
jmp .L34
.L40:
movl $512, %ecx
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z35__device_stub__Z10vector_subPfS_S_iPfS_S_i
jmp .L35
.L41:
movl $512, %r8d
movq 32(%rsp), %rcx
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z45__device_stub__Z18vector_dot_productPfS_S_S_iPfS_S_S_i
jmp .L36
.L42:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size main, .-main
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC16:
.string "_Z18vector_dot_productPfS_S_S_i"
.section .rodata.str1.1
.LC17:
.string "_Z10vector_subPfS_S_i"
.LC18:
.string "_Z10vector_addPfS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2091:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC16(%rip), %rdx
movq %rdx, %rcx
leaq _Z18vector_dot_productPfS_S_S_i(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC17(%rip), %rdx
movq %rdx, %rcx
leaq _Z10vector_subPfS_S_i(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC18(%rip), %rdx
movq %rdx, %rcx
leaq _Z10vector_addPfS_S_i(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2091:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC5:
.long 1073741824
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "matrix.hip"
.globl _Z13print_resultsPf # -- Begin function _Z13print_resultsPf
.p2align 4, 0x90
.type _Z13print_resultsPf,@function
_Z13print_resultsPf: # @_Z13print_resultsPf
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movq %rdi, %rbx
movl $91, %edi
callq putchar@PLT
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB0_1: # =>This Inner Loop Header: Depth=1
movss (%rbx,%r14,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.1, %edi
movb $1, %al
callq printf
incq %r14
cmpq $4, %r14
jne .LBB0_1
# %bb.2:
movl $.Lstr, %edi
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
jmp puts # TAILCALL
.Lfunc_end0:
.size _Z13print_resultsPf, .Lfunc_end0-_Z13print_resultsPf
.cfi_endproc
# -- End function
.globl _Z25__device_stub__vector_addPfS_S_i # -- Begin function _Z25__device_stub__vector_addPfS_S_i
.p2align 4, 0x90
.type _Z25__device_stub__vector_addPfS_S_i,@function
_Z25__device_stub__vector_addPfS_S_i: # @_Z25__device_stub__vector_addPfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10vector_addPfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end1:
.size _Z25__device_stub__vector_addPfS_S_i, .Lfunc_end1-_Z25__device_stub__vector_addPfS_S_i
.cfi_endproc
# -- End function
.globl _Z25__device_stub__vector_subPfS_S_i # -- Begin function _Z25__device_stub__vector_subPfS_S_i
.p2align 4, 0x90
.type _Z25__device_stub__vector_subPfS_S_i,@function
_Z25__device_stub__vector_subPfS_S_i: # @_Z25__device_stub__vector_subPfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10vector_subPfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end2:
.size _Z25__device_stub__vector_subPfS_S_i, .Lfunc_end2-_Z25__device_stub__vector_subPfS_S_i
.cfi_endproc
# -- End function
.globl _Z33__device_stub__vector_dot_productPfS_S_S_i # -- Begin function _Z33__device_stub__vector_dot_productPfS_S_S_i
.p2align 4, 0x90
.type _Z33__device_stub__vector_dot_productPfS_S_S_i,@function
_Z33__device_stub__vector_dot_productPfS_S_S_i: # @_Z33__device_stub__vector_dot_productPfS_S_S_i
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movl %r8d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 12(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z18vector_dot_productPfS_S_S_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end3:
.size _Z33__device_stub__vector_dot_productPfS_S_S_i, .Lfunc_end3-_Z33__device_stub__vector_dot_productPfS_S_S_i
.cfi_endproc
# -- End function
.globl _Z13print_vectorsv # -- Begin function _Z13print_vectorsv
.p2align 4, 0x90
.type _Z13print_vectorsv,@function
_Z13print_vectorsv: # @_Z13print_vectorsv
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
movl $.Lstr.1, %edi
callq puts
movl $.Lstr.2, %edi
popq %rax
.cfi_def_cfa_offset 8
jmp puts # TAILCALL
.Lfunc_end4:
.size _Z13print_vectorsv, .Lfunc_end4-_Z13print_vectorsv
.cfi_endproc
# -- End function
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function main
.LCPI5_0:
.long 0x40000000 # float 2
.long 0x40800000 # float 4
.long 0x40c00000 # float 6
.long 0x41200000 # float 10
.LCPI5_1:
.long 0x3f800000 # float 1
.long 0x40000000 # float 2
.long 0x40400000 # float 3
.long 0x41000000 # float 8
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $192, %rsp
.cfi_def_cfa_offset 240
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movabsq $4294967297, %r15 # imm = 0x100000001
movaps .LCPI5_0(%rip), %xmm0 # xmm0 = [2.0E+0,4.0E+0,6.0E+0,1.0E+1]
movaps %xmm0, 176(%rsp)
movaps .LCPI5_1(%rip), %xmm0 # xmm0 = [1.0E+0,2.0E+0,3.0E+0,8.0E+0]
movaps %xmm0, 160(%rsp)
movl $2048, %edi # imm = 0x800
callq malloc
movq %rax, %rbx
movl $4, %edi
callq malloc
movq %rax, %r14
leaq 16(%rsp), %rdi
movl $2048, %esi # imm = 0x800
callq hipMalloc
leaq 8(%rsp), %rdi
movl $2048, %esi # imm = 0x800
callq hipMalloc
movq %rsp, %r12
movl $2048, %esi # imm = 0x800
movq %r12, %rdi
callq hipMalloc
movl $2048, %esi # imm = 0x800
movq %r12, %rdi
callq hipMalloc
leaq 152(%rsp), %rdi
movl $4, %esi
callq hipMalloc
movq 16(%rsp), %rdi
leaq 176(%rsp), %rsi
movl $2048, %edx # imm = 0x800
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
leaq 160(%rsp), %rsi
movl $2048, %edx # imm = 0x800
movl $1, %ecx
callq hipMemcpy
leaq 3(%r15), %r12
movq %r15, %rdi
movl $1, %esi
movq %r12, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB5_2
# %bb.1:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq (%rsp), %rdx
movq %rax, 96(%rsp)
movq %rcx, 88(%rsp)
movq %rdx, 80(%rsp)
movl $512, 24(%rsp) # imm = 0x200
leaq 96(%rsp), %rax
movq %rax, 112(%rsp)
leaq 88(%rsp), %rax
movq %rax, 120(%rsp)
leaq 80(%rsp), %rax
movq %rax, 128(%rsp)
leaq 24(%rsp), %rax
movq %rax, 136(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 72(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z10vector_addPfS_S_i, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 80(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB5_2:
movq (%rsp), %rsi
movl $2048, %edx # imm = 0x800
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
movl $.L.str.5, %edi
callq puts
movl $.Lstr.1, %edi
callq puts
movl $.Lstr.2, %edi
callq puts
movl $91, %edi
callq putchar@PLT
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB5_3: # =>This Inner Loop Header: Depth=1
movss (%rbx,%r13,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.1, %edi
movb $1, %al
callq printf
incq %r13
cmpq $4, %r13
jne .LBB5_3
# %bb.4: # %_Z13print_resultsPf.exit
movl $.Lstr, %edi
callq puts
movq %r15, %rdi
movl $1, %esi
movq %r12, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB5_6
# %bb.5:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq (%rsp), %rdx
movq %rax, 96(%rsp)
movq %rcx, 88(%rsp)
movq %rdx, 80(%rsp)
movl $512, 24(%rsp) # imm = 0x200
leaq 96(%rsp), %rax
movq %rax, 112(%rsp)
leaq 88(%rsp), %rax
movq %rax, 120(%rsp)
leaq 80(%rsp), %rax
movq %rax, 128(%rsp)
leaq 24(%rsp), %rax
movq %rax, 136(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 72(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z10vector_subPfS_S_i, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 80(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB5_6:
movq (%rsp), %rsi
movl $2048, %edx # imm = 0x800
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
movl $.L.str.6, %edi
callq puts
movl $.Lstr.1, %edi
callq puts
movl $.Lstr.2, %edi
callq puts
movl $91, %edi
callq putchar@PLT
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB5_7: # =>This Inner Loop Header: Depth=1
movss (%rbx,%r13,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.1, %edi
movb $1, %al
callq printf
incq %r13
cmpq $4, %r13
jne .LBB5_7
# %bb.8: # %_Z13print_resultsPf.exit35
movl $.Lstr, %edi
callq puts
movq %r15, %rdi
movl $1, %esi
movq %r12, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB5_10
# %bb.9:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq (%rsp), %rdx
movq 152(%rsp), %rsi
movq %rax, 96(%rsp)
movq %rcx, 88(%rsp)
movq %rdx, 80(%rsp)
movq %rsi, 72(%rsp)
movl $512, 108(%rsp) # imm = 0x200
leaq 96(%rsp), %rax
movq %rax, 112(%rsp)
leaq 88(%rsp), %rax
movq %rax, 120(%rsp)
leaq 80(%rsp), %rax
movq %rax, 128(%rsp)
leaq 72(%rsp), %rax
movq %rax, 136(%rsp)
leaq 108(%rsp), %rax
movq %rax, 144(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z18vector_dot_productPfS_S_S_i, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB5_10:
movq (%rsp), %rsi
movl $2048, %edx # imm = 0x800
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
movl $.L.str.7, %edi
callq puts
movl $.Lstr.1, %edi
callq puts
movl $.Lstr.2, %edi
callq puts
movl $91, %edi
callq putchar@PLT
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB5_11: # =>This Inner Loop Header: Depth=1
movss (%rbx,%r15,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.1, %edi
movb $1, %al
callq printf
incq %r15
cmpq $4, %r15
jne .LBB5_11
# %bb.12: # %_Z13print_resultsPf.exit49
movl $.Lstr, %edi
callq puts
movq 152(%rsp), %rsi
movl $4, %edx
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
movss (%r14), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.8, %edi
movb $1, %al
callq printf
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq free
xorl %eax, %eax
addq $192, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end5:
.size main, .Lfunc_end5-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB6_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB6_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10vector_addPfS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10vector_subPfS_S_i, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z18vector_dot_productPfS_S_S_i, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end6:
.size __hip_module_ctor, .Lfunc_end6-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB7_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB7_2:
retq
.Lfunc_end7:
.size __hip_module_dtor, .Lfunc_end7-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "%f,"
.size .L.str.1, 4
.type _Z10vector_addPfS_S_i,@object # @_Z10vector_addPfS_S_i
.section .rodata,"a",@progbits
.globl _Z10vector_addPfS_S_i
.p2align 3, 0x0
_Z10vector_addPfS_S_i:
.quad _Z25__device_stub__vector_addPfS_S_i
.size _Z10vector_addPfS_S_i, 8
.type _Z10vector_subPfS_S_i,@object # @_Z10vector_subPfS_S_i
.globl _Z10vector_subPfS_S_i
.p2align 3, 0x0
_Z10vector_subPfS_S_i:
.quad _Z25__device_stub__vector_subPfS_S_i
.size _Z10vector_subPfS_S_i, 8
.type _Z18vector_dot_productPfS_S_S_i,@object # @_Z18vector_dot_productPfS_S_S_i
.globl _Z18vector_dot_productPfS_S_S_i
.p2align 3, 0x0
_Z18vector_dot_productPfS_S_S_i:
.quad _Z33__device_stub__vector_dot_productPfS_S_S_i
.size _Z18vector_dot_productPfS_S_S_i, 8
.type .L.str.5,@object # @.str.5
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.5:
.asciz "ADDING"
.size .L.str.5, 7
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "SUBSTRACTING"
.size .L.str.6, 13
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "DOT_PRODUCT"
.size .L.str.7, 12
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "\nDot product result %f\n"
.size .L.str.8, 24
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z10vector_addPfS_S_i"
.size .L__unnamed_1, 22
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z10vector_subPfS_S_i"
.size .L__unnamed_2, 22
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z18vector_dot_productPfS_S_S_i"
.size .L__unnamed_3, 32
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "]"
.size .Lstr, 2
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "A = {2.0,4.0,6.0,8.0}"
.size .Lstr.1, 22
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "B = {1.0,2.0,3.0,10.0}"
.size .Lstr.2, 23
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__vector_addPfS_S_i
.addrsig_sym _Z25__device_stub__vector_subPfS_S_i
.addrsig_sym _Z33__device_stub__vector_dot_productPfS_S_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10vector_addPfS_S_i
.addrsig_sym _Z10vector_subPfS_S_i
.addrsig_sym _Z18vector_dot_productPfS_S_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdlib.h>
#include <unistd.h>
#include <iostream>
#include <string>
#include <sstream>
using namespace std;
#include "cuda_runtime_api.h"
#define SIZE_OF_MATRIX 1000
#define SIZE_OF_BLOCK 16
#define M SIZE_OF_MATRIX
unsigned int m = SIZE_OF_MATRIX;
#define idx(i,j,lda) ((j) + ((i)*(lda)))
__global__ void multiply_matrices(float *d_a, float *d_b, float *d_c, int lda)
{
unsigned int row = threadIdx.y + blockDim.y * blockIdx.y;
unsigned int col = threadIdx.x + blockDim.x * blockIdx.x;
unsigned int id = idx(row,col,lda);
float ctemp = 0.0;
if (row < M && col < M)
{
for (unsigned int j=0; j<M; j++)
{
ctemp = ctemp + d_a[idx(row,j,lda)] * d_b[idx(j,col,lda)];
}
d_c[id] = ctemp;
}
}
__global__ void multiply_matrices_shared_blocks(float *d_a, float *d_b, float *d_c,
int lda)
{
int bs = SIZE_OF_BLOCK;
unsigned int row = threadIdx.y + blockDim.y * blockIdx.y;
unsigned int col = threadIdx.x + blockDim.x * blockIdx.x;
unsigned int id = idx(row,col,lda);
//submatrices
float *sub_a, *sub_b;
//shared submatrices
__shared__ float a[SIZE_OF_BLOCK][SIZE_OF_BLOCK], b[SIZE_OF_BLOCK][SIZE_OF_BLOCK];
//temp element of d_c
float c = 0;
//top-level row,col of block
int block_row = blockIdx.y * bs;
int block_col = blockIdx.x * bs;
//id inside each block
int sub_row = threadIdx.y;
int sub_col = threadIdx.x;
//for each block
for (int k = 0; k < (M / bs); k++)
{
sub_a = &d_a[idx(block_row, bs*k, lda)];
sub_b = &d_b[idx(bs*k, block_col, lda)];
a[sub_row][sub_col] = sub_a[idx(sub_row, sub_col, lda)];
b[sub_row][sub_col] = sub_b[idx(sub_row, sub_col, lda)];
//wait for all threads to complete copy to shared memory.
__syncthreads();
//multiply each submatrix
for (int j=0; j < bs; j++)
{
c = c + a[sub_row][j] * b[j][sub_col];
}
// move results to device memory.
d_c[id] = c;
// wait for multiplication to finish before moving onto the next submatrix.
__syncthreads();
}
}
void multiply_by_element(dim3 grid, dim3 threads, float *d_a, float *d_b, float *d_c, int m, cudaStream_t cStream)
{
cudaError err;
unsigned int matsize = SIZE_OF_MATRIX*SIZE_OF_MATRIX*sizeof(float);
float* c = (float*)malloc(matsize);
multiply_matrices<<< grid, threads, 0, cStream >>>(d_a, d_b, d_c, m);
err = cudaGetLastError();
if (err != cudaSuccess)
{
cout << "error in kernel, " << cudaGetErrorString(err) << endl;
}
cudaStreamSynchronize(cStream);
err = cudaMemcpyAsync(c, d_c, matsize, cudaMemcpyDeviceToHost, cStream);
if (err != cudaSuccess)
{
cout << "error in memcpy, #=" << cudaGetErrorString(err) << endl;
}
}
void multiply_by_block(dim3 grid, dim3 threads, float *d_a, float *d_b, float *d_c, int m, cudaStream_t cStream)
{
cudaError err;
unsigned int matsize = SIZE_OF_MATRIX*SIZE_OF_MATRIX*sizeof(float);
float* c = (float*)malloc(matsize);
multiply_matrices_shared_blocks<<< grid, threads, 0, cStream >>>(d_a, d_b, d_c, m);
err = cudaGetLastError();
if (err != cudaSuccess)
{
cout << "error in kernel, " << cudaGetErrorString(err) << endl;
}
cudaStreamSynchronize(cStream);
err = cudaMemcpyAsync(c, d_c, matsize, cudaMemcpyDeviceToHost, cStream);
if (err != cudaSuccess)
{
cout << "error in memcpy, #=" << cudaGetErrorString(err) << endl;
}
}
#define STREAM_INDEX(_d,_i) ((_d*number_of_iterations) + _i)
int main(int argc, char** argv)
{
unsigned int number_of_threads = min(SIZE_OF_MATRIX, SIZE_OF_BLOCK);
unsigned int number_of_blocks;
if (SIZE_OF_MATRIX > SIZE_OF_BLOCK)
number_of_blocks = ceil(SIZE_OF_MATRIX / ((float) SIZE_OF_BLOCK));
else
number_of_blocks = 1;
unsigned int matsize = SIZE_OF_MATRIX*SIZE_OF_MATRIX*sizeof(float);
//cout << "blocks: " << number_of_blocks << " threads: " <<
//number_of_threads << endl;
//cout.flush();
float* a = (float*)malloc(matsize);
float* b = (float*)malloc(matsize);
float* c = (float*)malloc(matsize);
//initalize matrices
for (int i=0; i<m; i++) {
for (int j=0; j<m; j++) {
//a[i*m+j] = i;
//b[i*m+j] = i;
a[i*m+j] = i-j*2 + i-j+1 + 1;
b[i*m+j] = i-j*2 + i-j+1 + 1;
c[i*m+j] = 0;
//cout << a[i*m+j] << ", ";
}
//cout << endl;
}
cudaError_t err;
int count = 0;
err = cudaGetDeviceCount(&count);
cout << count << " devices found." << endl;
string device_list("");
int number_of_iterations = 1;
int opt = getopt(argc, argv, "d:i:");
while(opt != -1) {
stringstream str;
switch(opt) {
case 'd':
device_list = string(optarg);
break;
case 'i':
str << optarg;
str >> number_of_iterations;
cout << "Doing " << number_of_iterations << " iterations." << std::endl;
break;
case '?':
if (optopt == 'd')
cerr << "Error, option -d requires argument: comma delimted list of devices to run on." << endl;
else if (optopt == 'i')
cerr << "Error, option -i requires argument: number of iterations to run." << endl;
else
cerr << "Error, unknow option. Usage:\nmatmult [-d <device id>,...] [-i <number of iterations]" << endl;
return 1;
default:
break;
}
opt = getopt(argc, argv, "d:i:");
}
int devices[count];
int nDevices = 0;
//default: use all the devices
if (device_list.compare("") == 0)
{
for (int d=0;d<count;d++)
{
devices[d] = d;
}
nDevices = count;
}
else
{
for (int d=0;d<count;d++)
{
stringstream str;
str << d;
char c = 0;
if (str >> c) {
if (device_list.find(c) != string::npos) {
devices[nDevices++] = d;
}
}
}
}
//cout << "finnished mapping devices." << endl;
float *d_a[nDevices], *d_b[nDevices], *d_c[nDevices];
cudaStream_t streams[nDevices * number_of_iterations];
for (int d=0;d<nDevices;d++)
{
cudaSetDevice(devices[d]);
cudaDeviceProp deviceProp;
cudaGetDeviceProperties(&deviceProp, devices[d]);
cout << "Using device " << devices[d] << ", name: " << deviceProp.name << endl;
err = cudaSetDevice(devices[d]);
if (err != cudaSuccess)
{
cout << "error setting device, #=" << cudaGetErrorString(err) << endl;
}
for (int i=0; i<number_of_iterations; i++)
{
err = cudaStreamCreate(&streams[STREAM_INDEX(d,i)]);
if (err != cudaSuccess)
{
cout << "error in stream creation, #=" << cudaGetErrorString(err) << endl;
}
}
err = cudaMalloc((void **) &d_a[d], matsize);
if (err != cudaSuccess)
{
cout << "error in malloc, #=" << cudaGetErrorString(err) << endl;
}
err = cudaMalloc((void **) &d_b[d], matsize);
if (err != cudaSuccess)
{
cout << "error in malloc, #=" << cudaGetErrorString(err) << endl;
}
err = cudaMalloc((void **) &d_c[d], matsize);
if (err != cudaSuccess)
{
cout << "error in malloc, #=" << cudaGetErrorString(err) << endl;
}
}
for (int d=0; d<nDevices; d++)
{
for (int i=0; i<number_of_iterations; i++)
{
cout << "Running on device " << d << ", stream " << i << endl;
int cDevice = d;
cudaStream_t cStream = streams[STREAM_INDEX(d,i)];
cudaSetDevice(devices[cDevice]);
if (err != cudaSuccess) {
cout << "error setting device: " << devices[i%nDevices] << " #=" << cudaGetErrorString(err) << endl;
}
err = cudaMemcpyAsync(d_a[cDevice], a, matsize, cudaMemcpyHostToDevice, cStream);
if (err != cudaSuccess) {
cout << "error in memcpy, #=" << cudaGetErrorString(err) << endl;
}
err = cudaMemcpyAsync(d_b[cDevice], b, matsize, cudaMemcpyHostToDevice, cStream);
if (err != cudaSuccess) {
cout << "error in memcpy, #=" << cudaGetErrorString(err) << endl;
}
//cout << "running on device " << cDevice << endl;
dim3 grid(number_of_blocks, number_of_blocks);
dim3 threads(number_of_threads, number_of_threads, 1);
//multiply each element at a time.
multiply_by_element(grid, threads, d_a[cDevice], d_b[cDevice], d_c[cDevice], m, cStream);
//multiply by first load a 16x16 submatrix into shared memory.
multiply_by_block(grid, threads, d_a[cDevice], d_b[cDevice], d_c[cDevice], m, cStream);
}
}
cout << "Finished " << number_of_iterations << " iterations on " << nDevices << " devices." << endl;
for (int d=0;d<nDevices;d++) {
cudaSetDevice(devices[d]);
for (int i=0; i<number_of_iterations; i++) {
cudaStreamSynchronize(streams[STREAM_INDEX(d,i)]);
}
}
for (int d=0;d<nDevices;d++) {
for (int i=0; i<number_of_iterations; i++) {
cudaStreamDestroy(streams[STREAM_INDEX(d,i)]);
}
}
//print c
/*
cout << " results: " << endl;
for (int i=0; i<m; i++) {
for (int j=0; j<m; j++) {
cout << c[i*m+j] << ", ";
}
cout << endl;
}
*/
//print c
/*
cout << " results: " << endl;
for (int i=0; i<m; i++) {
for (int j=0; j<m; j++) {
cout << c[i*m+j] << ", ";
}
cout << endl;
}
*/
cudaFree(d_a);
cudaFree(d_b);
cudaFree(d_c);
} | code for sm_80
Function : _Z31multiply_matrices_shared_blocksPfS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.Y ; /* 0x0000000000067919 */
/* 0x000e220000002600 */
/*0020*/ MOV R21, c[0x0][0x178] ; /* 0x00005e0000157a02 */
/* 0x000fe20000000f00 */
/*0030*/ HFMA2.MMA R23, -RZ, RZ, 0, 0 ; /* 0x00000000ff177435 */
/* 0x000fe200000001ff */
/*0040*/ MOV R16, RZ ; /* 0x000000ff00107202 */
/* 0x000fe20000000f00 */
/*0050*/ S2R R19, SR_TID.Y ; /* 0x0000000000137919 */
/* 0x000e620000002200 */
/*0060*/ SHF.L.U32 R21, R21, 0x4, RZ ; /* 0x0000000415157819 */
/* 0x000fe200000006ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0080*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e680000002100 */
/*0090*/ S2R R7, SR_CTAID.X ; /* 0x0000000000077919 */
/* 0x000ea20000002500 */
/*00a0*/ IMAD R4, R6, c[0x0][0x178], RZ ; /* 0x00005e0006047a24 */
/* 0x001fca00078e02ff */
/*00b0*/ SHF.L.U32 R5, R4, 0x4, RZ ; /* 0x0000000404057819 */
/* 0x000fe200000006ff */
/*00c0*/ IMAD R2, R19, c[0x0][0x178], R0 ; /* 0x00005e0013027a24 */
/* 0x002fe200078e0200 */
/*00d0*/ SHF.L.U32 R3, R7, 0x4, RZ ; /* 0x0000000407037819 */
/* 0x004fc800000006ff */
/*00e0*/ SHF.R.S32.HI R4, RZ, 0x1f, R2 ; /* 0x0000001fff047819 */
/* 0x000fe40000011402 */
/*00f0*/ IADD3 R13, P0, R3.reuse, R2, RZ ; /* 0x00000002030d7210 */
/* 0x040fe40007f1e0ff */
/*0100*/ IADD3 R17, P1, R2, R5, RZ ; /* 0x0000000502117210 */
/* 0x000fe20007f3e0ff */
/*0110*/ IMAD R2, R6, c[0x0][0x4], R19 ; /* 0x0000010006027a24 */
/* 0x000fe200078e0213 */
/*0120*/ LEA.HI.X.SX32 R6, R3, R4.reuse, 0x1, P0 ; /* 0x0000000403067211 */
/* 0x080fe200000f0eff */
/*0130*/ IMAD R3, R7, c[0x0][0x0], R0 ; /* 0x0000000007037a24 */
/* 0x000fe200078e0200 */
/*0140*/ LEA.HI.X.SX32 R4, R5, R4, 0x1, P1 ; /* 0x0000000405047211 */
/* 0x000fe400008f0eff */
/*0150*/ LEA R12, P0, R13, c[0x0][0x168], 0x2 ; /* 0x00005a000d0c7a11 */
/* 0x000fe200078010ff */
/*0160*/ IMAD R2, R2, c[0x0][0x178], R3 ; /* 0x00005e0002027a24 */
/* 0x000fe200078e0203 */
/*0170*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0180*/ LEA R14, P1, R17, c[0x0][0x160], 0x2 ; /* 0x00005800110e7a11 */
/* 0x000fc400078210ff */
/*0190*/ SHF.L.U32 R19, R19, 0x6, RZ ; /* 0x0000000613137819 */
/* 0x000fe400000006ff */
/*01a0*/ LEA.HI.X R13, R13, c[0x0][0x16c], R6, 0x2, P0 ; /* 0x00005b000d0d7a11 */
/* 0x000fe400000f1406 */
/*01b0*/ LEA.HI.X R17, R17, c[0x0][0x164], R4, 0x2, P1 ; /* 0x0000590011117a11 */
/* 0x000fe400008f1404 */
/*01c0*/ LEA R15, R0, R19, 0x2 ; /* 0x00000013000f7211 */
/* 0x000fe200078e10ff */
/*01d0*/ IMAD.WIDE.U32 R2, R2, R3, c[0x0][0x170] ; /* 0x00005c0002027625 */
/* 0x000fc800078e0003 */
/*01e0*/ MOV R4, R14 ; /* 0x0000000e00047202 */
/* 0x000fe20000000f00 */
/*01f0*/ LDG.E R24, [R12.64] ; /* 0x000000040c187981 */
/* 0x0010a2000c1e1900 */
/*0200*/ MOV R5, R17 ; /* 0x0000001100057202 */
/* 0x000fca0000000f00 */
/*0210*/ LDG.E R20, [R4.64] ; /* 0x0000000404147981 */
/* 0x000ee2000c1e1900 */
/*0220*/ IADD3 R16, R16, 0x1, RZ ; /* 0x0000000110107810 */
/* 0x000fc80007ffe0ff */
/*0230*/ ISETP.NE.AND P0, PT, R16, 0x3e, PT ; /* 0x0000003e1000780c */
/* 0x000fe40003f05270 */
/*0240*/ IADD3 R14, P1, R14, 0x40, RZ ; /* 0x000000400e0e7810 */
/* 0x000fe20007f3e0ff */
/*0250*/ IMAD.WIDE R12, R21, 0x4, R12 ; /* 0x00000004150c7825 */
/* 0x001fc600078e020c */
/*0260*/ IADD3.X R17, RZ, R17, RZ, P1, !PT ; /* 0x00000011ff117210 */
/* 0x000fe20000ffe4ff */
/*0270*/ STS [R15+0x400], R24 ; /* 0x000400180f007388 */
/* 0x004fe80000000800 */
/*0280*/ STS [R15], R20 ; /* 0x000000140f007388 */
/* 0x008fe80000000800 */
/*0290*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*02a0*/ LDS R26, [R0.X4+0x400] ; /* 0x00040000001a7984 */
/* 0x000fe80000004800 */
/*02b0*/ LDS.128 R8, [R19] ; /* 0x0000000013087984 */
/* 0x000e280000000c00 */
/*02c0*/ LDS R28, [R0.X4+0x440] ; /* 0x00044000001c7984 */
/* 0x000e680000004800 */
/*02d0*/ LDS R29, [R0.X4+0x480] ; /* 0x00048000001d7984 */
/* 0x000ea80000004800 */
/*02e0*/ LDS R22, [R0.X4+0x4c0] ; /* 0x0004c00000167984 */
/* 0x000ee80000004800 */
/*02f0*/ LDS R25, [R0.X4+0x500] ; /* 0x0005000000197984 */
/* 0x000fe80000004800 */
/*0300*/ LDS.128 R4, [R19+0x10] ; /* 0x0000100013047984 */
/* 0x000f280000000c00 */
/*0310*/ LDS R18, [R0.X4+0x540] ; /* 0x0005400000127984 */
/* 0x000f680000004800 */
/*0320*/ LDS R27, [R0.X4+0x580] ; /* 0x00058000001b7984 */
/* 0x000f680000004800 */
/*0330*/ LDS R20, [R0.X4+0x5c0] ; /* 0x0005c00000147984 */
/* 0x000f620000004800 */
/*0340*/ FFMA R8, R26, R8, R23 ; /* 0x000000081a087223 */
/* 0x001fc60000000017 */
/*0350*/ LDS R23, [R0.X4+0x600] ; /* 0x0006000000177984 */
/* 0x000fe20000004800 */
/*0360*/ FFMA R8, R28, R9, R8 ; /* 0x000000091c087223 */
/* 0x002fc80000000008 */
/*0370*/ FFMA R8, R29, R10, R8 ; /* 0x0000000a1d087223 */
/* 0x004fc80000000008 */
/*0380*/ FFMA R22, R22, R11, R8 ; /* 0x0000000b16167223 */
/* 0x008fe40000000008 */
/*0390*/ LDS.128 R8, [R19+0x20] ; /* 0x0000200013087984 */
/* 0x000e240000000c00 */
/*03a0*/ FFMA R4, R25, R4, R22 ; /* 0x0000000419047223 */
/* 0x010fe40000000016 */
/*03b0*/ LDS R22, [R0.X4+0x640] ; /* 0x0006400000167984 */
/* 0x000e640000004800 */
/*03c0*/ FFMA R4, R18, R5, R4 ; /* 0x0000000512047223 */
/* 0x020fe40000000004 */
/*03d0*/ LDS R25, [R0.X4+0x680] ; /* 0x0006800000197984 */
/* 0x000ea40000004800 */
/*03e0*/ FFMA R4, R27, R6, R4 ; /* 0x000000061b047223 */
/* 0x000fc40000000004 */
/*03f0*/ LDS R18, [R0.X4+0x6c0] ; /* 0x0006c00000127984 */
/* 0x000ee40000004800 */
/*0400*/ FFMA R24, R20, R7, R4 ; /* 0x0000000714187223 */
/* 0x000fe40000000004 */
/*0410*/ LDS R27, [R0.X4+0x700] ; /* 0x00070000001b7984 */
/* 0x000fe80000004800 */
/*0420*/ LDS.128 R4, [R19+0x30] ; /* 0x0000300013047984 */
/* 0x000f280000000c00 */
/*0430*/ LDS R20, [R0.X4+0x740] ; /* 0x0007400000147984 */
/* 0x000f620000004800 */
/*0440*/ FFMA R24, R23, R8, R24 ; /* 0x0000000817187223 */
/* 0x001fc60000000018 */
/*0450*/ LDS R23, [R0.X4+0x780] ; /* 0x0007800000177984 */
/* 0x000e280000004800 */
/*0460*/ LDS R8, [R0.X4+0x7c0] ; /* 0x0007c00000087984 */
/* 0x000e220000004800 */
/*0470*/ FFMA R9, R22, R9, R24 ; /* 0x0000000916097223 */
/* 0x002fc80000000018 */
/*0480*/ FFMA R9, R25, R10, R9 ; /* 0x0000000a19097223 */
/* 0x004fc80000000009 */
/*0490*/ FFMA R9, R18, R11, R9 ; /* 0x0000000b12097223 */
/* 0x008fc80000000009 */
/*04a0*/ FFMA R4, R27, R4, R9 ; /* 0x000000041b047223 */
/* 0x010fc80000000009 */
/*04b0*/ FFMA R4, R20, R5, R4 ; /* 0x0000000514047223 */
/* 0x020fc80000000004 */
/*04c0*/ FFMA R23, R23, R6, R4 ; /* 0x0000000617177223 */
/* 0x001fc80000000004 */
/*04d0*/ FFMA R23, R8, R7, R23 ; /* 0x0000000708177223 */
/* 0x000fca0000000017 */
/*04e0*/ STG.E [R2.64], R23 ; /* 0x0000001702007986 */
/* 0x0001e8000c101904 */
/*04f0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0500*/ @P0 BRA 0x1e0 ; /* 0xfffffcd000000947 */
/* 0x000fea000383ffff */
/*0510*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0520*/ BRA 0x520; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0530*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0540*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0550*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0560*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0570*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0580*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0590*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z17multiply_matricesPfS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R9, SR_CTAID.X ; /* 0x0000000000097919 */
/* 0x000e280000002500 */
/*0020*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e280000002100 */
/*0030*/ S2R R5, SR_CTAID.Y ; /* 0x0000000000057919 */
/* 0x000e680000002600 */
/*0040*/ S2R R0, SR_TID.Y ; /* 0x0000000000007919 */
/* 0x000e620000002200 */
/*0050*/ IMAD R9, R9, c[0x0][0x0], R2 ; /* 0x0000000009097a24 */
/* 0x001fca00078e0202 */
/*0060*/ ISETP.GT.U32.AND P0, PT, R9, 0x3e7, PT ; /* 0x000003e70900780c */
/* 0x000fe20003f04070 */
/*0070*/ IMAD R5, R5, c[0x0][0x4], R0 ; /* 0x0000010005057a24 */
/* 0x002fca00078e0200 */
/*0080*/ ISETP.GT.U32.OR P0, PT, R5, 0x3e7, P0 ; /* 0x000003e70500780c */
/* 0x000fda0000704470 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ HFMA2.MMA R0, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff007435 */
/* 0x000fe200000001ff */
/*00b0*/ IMAD R5, R5, c[0x0][0x178], RZ ; /* 0x00005e0005057a24 */
/* 0x000fe200078e02ff */
/*00c0*/ IADD3 R15, R9, c[0x0][0x178], RZ ; /* 0x00005e00090f7a10 */
/* 0x000fe20007ffe0ff */
/*00d0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00e0*/ MOV R2, c[0x0][0x178] ; /* 0x00005e0000027a02 */
/* 0x000fe40000000f00 */
/*00f0*/ IADD3 R13, R5, 0x1, RZ ; /* 0x00000001050d7810 */
/* 0x000fc80007ffe0ff */
/*0100*/ IMAD.WIDE.U32 R6, R9, R0, c[0x0][0x168] ; /* 0x00005a0009067625 */
/* 0x000fe200078e0000 */
/*0110*/ IADD3 R17, R5, 0x2, RZ ; /* 0x0000000205117810 */
/* 0x000fc60007ffe0ff */
/*0120*/ IMAD.WIDE.U32 R10, R5, R0.reuse, c[0x0][0x160] ; /* 0x00005800050a7625 */
/* 0x080fe200078e0000 */
/*0130*/ LEA R19, R2, R9, 0x1 ; /* 0x0000000902137211 */
/* 0x000fe200078e08ff */
/*0140*/ LDG.E R4, [R6.64] ; /* 0x0000000406047981 */
/* 0x0000a4000c1e1900 */
/*0150*/ IMAD.WIDE.U32 R14, R15, R0.reuse, c[0x0][0x168] ; /* 0x00005a000f0e7625 */
/* 0x080fe400078e0000 */
/*0160*/ LDG.E R3, [R10.64] ; /* 0x000000040a037981 */
/* 0x0002a4000c1e1900 */
/*0170*/ IMAD.WIDE.U32 R12, R13, R0.reuse, c[0x0][0x160] ; /* 0x000058000d0c7625 */
/* 0x080fe400078e0000 */
/*0180*/ LDG.E R21, [R14.64] ; /* 0x000000040e157981 */
/* 0x000722000c1e1900 */
/*0190*/ IADD3 R7, R5, 0x3, RZ ; /* 0x0000000305077810 */
/* 0x001fe20007ffe0ff */
/*01a0*/ IMAD.WIDE.U32 R16, R17, R0, c[0x0][0x160] ; /* 0x0000580011107625 */
/* 0x000fc400078e0000 */
/*01b0*/ LDG.E R8, [R12.64] ; /* 0x000000040c087981 */
/* 0x000124000c1e1900 */
/*01c0*/ IMAD.WIDE.U32 R18, R19, R0.reuse, c[0x0][0x168] ; /* 0x00005a0013127625 */
/* 0x080fe200078e0000 */
/*01d0*/ IADD3 R23, R5, 0x4, RZ ; /* 0x0000000405177810 */
/* 0x000fe20007ffe0ff */
/*01e0*/ LDG.E R25, [R16.64] ; /* 0x0000000410197981 */
/* 0x000b24000c1e1900 */
/*01f0*/ IMAD R29, R2.reuse, 0x3, R9 ; /* 0x00000003021d7824 */
/* 0x040fe200078e0209 */
/*0200*/ LEA R27, R2, R9, 0x2 ; /* 0x00000009021b7211 */
/* 0x000fe200078e10ff */
/*0210*/ IMAD.WIDE.U32 R6, R7, R0, c[0x0][0x160] ; /* 0x0000580007067625 */
/* 0x000fe200078e0000 */
/*0220*/ LDG.E R22, [R18.64] ; /* 0x0000000412167981 */
/* 0x000122000c1e1900 */
/*0230*/ IADD3 R15, R5, 0x5, RZ ; /* 0x00000005050f7810 */
/* 0x008fc40007ffe0ff */
/*0240*/ IMAD.WIDE.U32 R28, R29, R0, c[0x0][0x168] ; /* 0x00005a001d1c7625 */
/* 0x000fc800078e0000 */
/*0250*/ IMAD R17, R2, 0x5, R9 ; /* 0x0000000502117824 */
/* 0x020fe200078e0209 */
/*0260*/ LDG.E R20, [R28.64] ; /* 0x000000041c147981 */
/* 0x000762000c1e1900 */
/*0270*/ IMAD.WIDE.U32 R10, R23, R0.reuse, c[0x0][0x160] ; /* 0x00005800170a7625 */
/* 0x082fe200078e0000 */
/*0280*/ IADD3 R19, R5, 0x6, RZ ; /* 0x0000000605137810 */
/* 0x001fe40007ffe0ff */
/*0290*/ LDG.E R23, [R6.64] ; /* 0x0000000406177981 */
/* 0x000162000c1e1900 */
/*02a0*/ IMAD.WIDE.U32 R12, R27, R0, c[0x0][0x168] ; /* 0x00005a001b0c7625 */
/* 0x000fc600078e0000 */
/*02b0*/ LDG.E R24, [R10.64] ; /* 0x000000040a187981 */
/* 0x000362000c1e1900 */
/*02c0*/ IMAD.WIDE.U32 R14, R15, R0.reuse, c[0x0][0x160] ; /* 0x000058000f0e7625 */
/* 0x080fe200078e0000 */
/*02d0*/ IADD3 R29, R5, 0x7, RZ ; /* 0x00000007051d7810 */
/* 0x008fe40007ffe0ff */
/*02e0*/ LDG.E R27, [R12.64] ; /* 0x000000040c1b7981 */
/* 0x000762000c1e1900 */
/*02f0*/ IMAD R26, R2, 0x6, R9 ; /* 0x00000006021a7824 */
/* 0x000fe400078e0209 */
/*0300*/ IMAD.WIDE.U32 R16, R17, R0.reuse, c[0x0][0x168] ; /* 0x00005a0011107625 */
/* 0x080fe200078e0000 */
/*0310*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000f66000c1e1900 */
/*0320*/ IMAD.WIDE.U32 R18, R19, R0, c[0x0][0x160] ; /* 0x0000580013127625 */
/* 0x000fc400078e0000 */
/*0330*/ LDG.E R17, [R16.64] ; /* 0x0000000410117981 */
/* 0x000f64000c1e1900 */
/*0340*/ IMAD R28, R2, 0x7, R9 ; /* 0x00000007021c7824 */
/* 0x000fe400078e0209 */
/*0350*/ IMAD.WIDE.U32 R6, R26, R0.reuse, c[0x0][0x168] ; /* 0x00005a001a067625 */
/* 0x081fe200078e0000 */
/*0360*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x000f66000c1e1900 */
/*0370*/ IMAD.WIDE.U32 R10, R29, R0.reuse, c[0x0][0x160] ; /* 0x000058001d0a7625 */
/* 0x082fe400078e0000 */
/*0380*/ LDG.E R7, [R6.64] ; /* 0x0000000406077981 */
/* 0x000164000c1e1900 */
/*0390*/ IMAD.WIDE.U32 R12, R28, R0, c[0x0][0x168] ; /* 0x00005a001c0c7625 */
/* 0x008fc400078e0000 */
/*03a0*/ LDG.E R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x000ee8000c1e1900 */
/*03b0*/ LDG.E R12, [R12.64] ; /* 0x000000040c0c7981 */
/* 0x000ee2000c1e1900 */
/*03c0*/ IADD3 R6, R5, 0xf, RZ ; /* 0x0000000f05067810 */
/* 0x001fe20007ffe0ff */
/*03d0*/ FFMA R3, R4, R3, RZ ; /* 0x0000000304037223 */
/* 0x004fc800000000ff */
/*03e0*/ FFMA R3, R21, R8, R3 ; /* 0x0000000815037223 */
/* 0x010fc80000000003 */
/*03f0*/ FFMA R3, R22, R25, R3 ; /* 0x0000001916037223 */
/* 0x000fc80000000003 */
/*0400*/ FFMA R3, R20, R23, R3 ; /* 0x0000001714037223 */
/* 0x020fc80000000003 */
/*0410*/ FFMA R3, R27, R24, R3 ; /* 0x000000181b037223 */
/* 0x000fe20000000003 */
/*0420*/ IADD3 R4, R9, R5, RZ ; /* 0x0000000509047210 */
/* 0x000fc60007ffe0ff */
/*0430*/ FFMA R3, R17, R14, R3 ; /* 0x0000000e11037223 */
/* 0x000fe20000000003 */
/*0440*/ IADD3 R5, R5, 0x8, RZ ; /* 0x0000000805057810 */
/* 0x000fc60007ffe0ff */
/*0450*/ FFMA R15, R7, R18, R3 ; /* 0x00000012070f7223 */
/* 0x000fe20000000003 */
/*0460*/ HFMA2.MMA R3, -RZ, RZ, 0, 8.94069671630859375e-07 ; /* 0x0000000fff037435 */
/* 0x000fe200000001ff */
/*0470*/ LEA R18, R2, R9, 0x3 ; /* 0x0000000902127211 */
/* 0x000fe400078e18ff */
/*0480*/ FFMA R10, R12, R10, R15 ; /* 0x0000000a0c0a7223 */
/* 0x008fe4000000000f */
/*0490*/ IADD3 R29, R6, -0x6, RZ ; /* 0xfffffffa061d7810 */
/* 0x000fe20007ffe0ff */
/*04a0*/ IMAD.WIDE.U32 R12, R5, R0, c[0x0][0x160] ; /* 0x00005800050c7625 */
/* 0x000fe200078e0000 */
/*04b0*/ IADD3 R23, R18, c[0x0][0x178], RZ ; /* 0x00005e0012177a10 */
/* 0x000fc60007ffe0ff */
/*04c0*/ IMAD.WIDE.U32 R14, R18, R0, c[0x0][0x168] ; /* 0x00005a00120e7625 */
/* 0x000fe200078e0000 */
/*04d0*/ IADD3 R27, R6, -0x5, RZ ; /* 0xfffffffb061b7810 */
/* 0x000fe20007ffe0ff */
/*04e0*/ LDG.E R9, [R12.64] ; /* 0x000000040c097981 */
/* 0x0000a2000c1e1900 */
/*04f0*/ LEA R25, R2, R18, 0x1 ; /* 0x0000001202197211 */
/* 0x000fe200078e08ff */
/*0500*/ IMAD.WIDE.U32 R28, R29, R0.reuse, c[0x0][0x160] ; /* 0x000058001d1c7625 */
/* 0x080fe400078e0000 */
/*0510*/ LDG.E R8, [R14.64] ; /* 0x000000040e087981 */
/* 0x0002a4000c1e1900 */
/*0520*/ IMAD.WIDE.U32 R22, R23, R0.reuse, c[0x0][0x168] ; /* 0x00005a0017167625 */
/* 0x080fe200078e0000 */
/*0530*/ IADD3 R17, R6, -0x4, RZ ; /* 0xfffffffc06117810 */
/* 0x000fe20007ffe0ff */
/*0540*/ LDG.E R20, [R28.64] ; /* 0x000000041c147981 */
/* 0x000724000c1e1900 */
/*0550*/ IMAD R7, R2, 0x3, R18 ; /* 0x0000000302077824 */
/* 0x000fe200078e0212 */
/*0560*/ IADD3 R19, R6, -0x3, RZ ; /* 0xfffffffd06137810 */
/* 0x000fe20007ffe0ff */
/*0570*/ IMAD.WIDE.U32 R26, R27, R0.reuse, c[0x0][0x160] ; /* 0x000058001b1a7625 */
/* 0x080fe200078e0000 */
/*0580*/ LDG.E R13, [R22.64] ; /* 0x00000004160d7981 */
/* 0x001126000c1e1900 */
/*0590*/ IMAD.WIDE.U32 R24, R25, R0, c[0x0][0x168] ; /* 0x00005a0019187625 */
/* 0x000fe200078e0000 */
/*05a0*/ LDG.E R12, [R26.64] ; /* 0x000000041a0c7981 */
/* 0x000b22000c1e1900 */
/*05b0*/ LEA R29, R2, R18, 0x2 ; /* 0x00000012021d7211 */
/* 0x008fc400078e10ff */
/*05c0*/ IMAD.WIDE.U32 R14, R7, R0.reuse, c[0x0][0x168] ; /* 0x00005a00070e7625 */
/* 0x082fe200078e0000 */
/*05d0*/ LDG.E R21, [R24.64] ; /* 0x0000000418157981 */
/* 0x0002e6000c1e1900 */
/*05e0*/ IMAD.WIDE.U32 R16, R17, R0.reuse, c[0x0][0x160] ; /* 0x0000580011107625 */
/* 0x080fe200078e0000 */
/*05f0*/ LDG.E R11, [R14.64] ; /* 0x000000040e0b7981 */
/* 0x0002e2000c1e1900 */
/*0600*/ IADD3 R28, R6, -0x2, RZ ; /* 0xfffffffe061c7810 */
/* 0x000fe40007ffe0ff */
/*0610*/ IMAD.WIDE.U32 R22, R29, R0.reuse, c[0x0][0x168] ; /* 0x00005a001d167625 */
/* 0x081fe200078e0000 */
/*0620*/ LDG.E R7, [R16.64] ; /* 0x0000000410077981 */
/* 0x0000e6000c1e1900 */
/*0630*/ IMAD R27, R2, 0x5, R18 ; /* 0x00000005021b7824 */
/* 0x020fe200078e0212 */
/*0640*/ IADD3 R25, R6, -0x1, RZ ; /* 0xffffffff06197810 */
/* 0x002fe20007ffe0ff */
/*0650*/ LDG.E R22, [R22.64] ; /* 0x0000000416167981 */
/* 0x000362000c1e1900 */
/*0660*/ IMAD.WIDE.U32 R14, R19, R0, c[0x0][0x160] ; /* 0x00005800130e7625 */
/* 0x000fc800078e0000 */
/*0670*/ IMAD.WIDE.U32 R16, R28, R0.reuse, c[0x0][0x160] ; /* 0x000058001c107625 */
/* 0x081fe200078e0000 */
/*0680*/ LDG.E R19, [R14.64] ; /* 0x000000040e137981 */
/* 0x000168000c1e1900 */
/*0690*/ LDG.E R23, [R16.64] ; /* 0x0000000410177981 */
/* 0x002362000c1e1900 */
/*06a0*/ IMAD.WIDE.U32 R14, R27, R0, c[0x0][0x168] ; /* 0x00005a001b0e7625 */
/* 0x001fc800078e0000 */
/*06b0*/ IMAD R27, R2, 0x6, R18 ; /* 0x00000006021b7824 */
/* 0x000fe200078e0212 */
/*06c0*/ LDG.E R24, [R14.64] ; /* 0x000000040e187981 */
/* 0x000166000c1e1900 */
/*06d0*/ IMAD.WIDE.U32 R16, R27, R0, c[0x0][0x168] ; /* 0x00005a001b107625 */
/* 0x002fc800078e0000 */
/*06e0*/ IMAD R27, R2, 0x7, R18 ; /* 0x00000007021b7824 */
/* 0x000fe200078e0212 */
/*06f0*/ LDG.E R26, [R16.64] ; /* 0x00000004101a7981 */
/* 0x000362000c1e1900 */
/*0700*/ IMAD.WIDE.U32 R14, R25, R0, c[0x0][0x160] ; /* 0x00005800190e7625 */
/* 0x001fca00078e0000 */
/*0710*/ LDG.E R25, [R14.64] ; /* 0x000000040e197981 */
/* 0x000162000c1e1900 */
/*0720*/ IMAD.WIDE.U32 R16, R27, R0, c[0x0][0x168] ; /* 0x00005a001b107625 */
/* 0x002fcc00078e0000 */
/*0730*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x000362000c1e1900 */
/*0740*/ IMAD.WIDE.U32 R14, R6, R0, c[0x0][0x160] ; /* 0x00005800060e7625 */
/* 0x001fcc00078e0000 */
/*0750*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000162000c1e1900 */
/*0760*/ IADD3 R27, R5, 0x8, RZ ; /* 0x00000008051b7810 */
/* 0x000fe40007ffe0ff */
/*0770*/ LEA R18, R2, R18, 0x3 ; /* 0x0000001202127211 */
/* 0x000fc800078e18ff */
/*0780*/ IADD3 R17, R18.reuse, c[0x0][0x178], RZ ; /* 0x00005e0012117a10 */
/* 0x042fe20007ffe0ff */
/*0790*/ IMAD.WIDE.U32 R28, R18, R0, c[0x0][0x168] ; /* 0x00005a00121c7625 */
/* 0x000fc800078e0000 */
/*07a0*/ FFMA R10, R8, R9, R10 ; /* 0x00000009080a7223 */
/* 0x004fc8000000000a */
/*07b0*/ FFMA R10, R13, R20, R10 ; /* 0x000000140d0a7223 */
/* 0x010fe2000000000a */
/*07c0*/ IADD3 R13, R6.reuse, 0x3, RZ ; /* 0x00000003060d7810 */
/* 0x040fe20007ffe0ff */
/*07d0*/ IMAD.WIDE.U32 R8, R27, R0, c[0x0][0x160] ; /* 0x000058001b087625 */
/* 0x000fe200078e0000 */
/*07e0*/ IADD3 R27, R6, 0x4, RZ ; /* 0x00000004061b7810 */
/* 0x000fc60007ffe0ff */
/*07f0*/ FFMA R10, R21, R12, R10 ; /* 0x0000000c150a7223 */
/* 0x008fe2000000000a */
/*0800*/ IADD3 R21, R6, 0x2, RZ ; /* 0x0000000206157810 */
/* 0x000fe20007ffe0ff */
/*0810*/ LDG.E R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x0002a4000c1e1900 */
/*0820*/ FFMA R15, R11, R7, R10 ; /* 0x000000070b0f7223 */
/* 0x001fe4000000000a */
/*0830*/ IMAD.WIDE.U32 R20, R21, R0.reuse, c[0x0][0x160] ; /* 0x0000580015147625 */
/* 0x080fe200078e0000 */
/*0840*/ LDG.E R7, [R28.64] ; /* 0x000000041c077981 */
/* 0x0000a6000c1e1900 */
/*0850*/ IMAD.WIDE.U32 R10, R13, R0.reuse, c[0x0][0x160] ; /* 0x000058000d0a7625 */
/* 0x080fe200078e0000 */
/*0860*/ LDG.E R9, [R20.64] ; /* 0x0000000414097981 */
/* 0x0022e6000c1e1900 */
/*0870*/ FFMA R22, R22, R19, R15 ; /* 0x0000001316167223 */
/* 0x020fe2000000000f */
/*0880*/ IADD3 R19, R6, 0x5, RZ ; /* 0x0000000506137810 */
/* 0x000fe20007ffe0ff */
/*0890*/ IMAD.WIDE.U32 R12, R27, R0, c[0x0][0x160] ; /* 0x000058001b0c7625 */
/* 0x000fe200078e0000 */
/*08a0*/ LEA R15, R2, R18, 0x1 ; /* 0x00000012020f7211 */
/* 0x000fe200078e08ff */
/*08b0*/ LDG.E R11, [R10.64] ; /* 0x000000040a0b7981 */
/* 0x000962000c1e1900 */
/*08c0*/ IADD3 R27, R6, 0x6, RZ ; /* 0x00000006061b7810 */
/* 0x000fe20007ffe0ff */
/*08d0*/ IMAD.WIDE.U32 R20, R19, R0, c[0x0][0x160] ; /* 0x0000580013147625 */
/* 0x002fc800078e0000 */
/*08e0*/ FFMA R24, R24, R23, R22 ; /* 0x0000001718187223 */
/* 0x000fe20000000016 */
/*08f0*/ LDG.E R10, [R12.64] ; /* 0x000000040c0a7981 */
/* 0x010322000c1e1900 */
/*0900*/ IMAD.WIDE.U32 R22, R17, R0, c[0x0][0x168] ; /* 0x00005a0011167625 */
/* 0x000fc600078e0000 */
/*0910*/ LDG.E R20, [R20.64] ; /* 0x0000000414147981 */
/* 0x0002e2000c1e1900 */
/*0920*/ IMAD.WIDE.U32 R28, R27, R0, c[0x0][0x160] ; /* 0x000058001b1c7625 */
/* 0x001fc600078e0000 */
/*0930*/ LDG.E R22, [R22.64] ; /* 0x0000000416167981 */
/* 0x0000e2000c1e1900 */
/*0940*/ IMAD.WIDE.U32 R12, R15, R0, c[0x0][0x168] ; /* 0x00005a000f0c7625 */
/* 0x002fe200078e0000 */
/*0950*/ IADD3 R17, R6, 0x7, RZ ; /* 0x0000000706117810 */
/* 0x000fe40007ffe0ff */
/*0960*/ LDG.E R19, [R28.64] ; /* 0x000000041c137981 */
/* 0x000322000c1e1900 */
/*0970*/ IMAD R15, R2, 0x3, R18 ; /* 0x00000003020f7824 */
/* 0x000fe400078e0212 */
/*0980*/ FFMA R27, R26, R25, R24 ; /* 0x000000191a1b7223 */
/* 0x000fe20000000018 */
/*0990*/ LDG.E R21, [R12.64] ; /* 0x000000040c157981 */
/* 0x000162000c1e1900 */
/*09a0*/ LEA R25, R2, R18, 0x2 ; /* 0x0000001202197211 */
/* 0x000fe200078e10ff */
/*09b0*/ IMAD.WIDE.U32 R12, R15, R0, c[0x0][0x168] ; /* 0x00005a000f0c7625 */
/* 0x001fc800078e0000 */
/*09c0*/ FFMA R23, R16, R14, R27 ; /* 0x0000000e10177223 */
/* 0x000fe2000000001b */
/*09d0*/ LDG.E R24, [R12.64] ; /* 0x000000040c187981 */
/* 0x000122000c1e1900 */
/*09e0*/ IMAD R27, R2, 0x5, R18 ; /* 0x00000005021b7824 */
/* 0x000fe400078e0212 */
/*09f0*/ IMAD.WIDE.U32 R14, R25, R0, c[0x0][0x168] ; /* 0x00005a00190e7625 */
/* 0x000fc800078e0000 */
/*0a00*/ IMAD R29, R2, 0x6, R18 ; /* 0x00000006021d7824 */
/* 0x002fe200078e0212 */
/*0a10*/ LDG.E R25, [R14.64] ; /* 0x000000040e197981 */
/* 0x000322000c1e1900 */
/*0a20*/ IMAD.WIDE.U32 R12, R27, R0, c[0x0][0x168] ; /* 0x00005a001b0c7625 */
/* 0x001fe200078e0000 */
/*0a30*/ IADD3 R28, R6, 0x8, RZ ; /* 0x00000008061c7810 */
/* 0x000fc60007ffe0ff */
/*0a40*/ IMAD.WIDE.U32 R16, R17, R0.reuse, c[0x0][0x160] ; /* 0x0000580011107625 */
/* 0x080fe200078e0000 */
/*0a50*/ LDG.E R26, [R12.64] ; /* 0x000000040c1a7981 */
/* 0x000126000c1e1900 */
/*0a60*/ IMAD.WIDE.U32 R14, R29, R0.reuse, c[0x0][0x168] ; /* 0x00005a001d0e7625 */
/* 0x082fe400078e0000 */
/*0a70*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x000f24000c1e1900 */
/*0a80*/ IMAD R29, R2, 0x7, R18 ; /* 0x00000007021d7824 */
/* 0x000fe400078e0212 */
/*0a90*/ LDG.E R27, [R14.64] ; /* 0x000000040e1b7981 */
/* 0x000324000c1e1900 */
/*0aa0*/ IMAD.WIDE.U32 R12, R29, R0, c[0x0][0x168] ; /* 0x00005a001d0c7625 */
/* 0x001fca00078e0000 */
/*0ab0*/ LDG.E R29, [R12.64] ; /* 0x000000040c1d7981 */
/* 0x000f22000c1e1900 */
/*0ac0*/ IMAD.WIDE.U32 R14, R28, R0, c[0x0][0x160] ; /* 0x000058001c0e7625 */
/* 0x002fca00078e0000 */
/*0ad0*/ LDG.E R28, [R14.64] ; /* 0x000000040e1c7981 */
/* 0x000f22000c1e1900 */
/*0ae0*/ IADD3 R3, R3, 0x10, RZ ; /* 0x0000001003037810 */
/* 0x000fc80007ffe0ff */
/*0af0*/ ISETP.NE.AND P0, PT, R3, 0x3ef, PT ; /* 0x000003ef0300780c */
/* 0x000fe40003f05270 */
/*0b00*/ IADD3 R6, R6, 0x10, RZ ; /* 0x0000001006067810 */
/* 0x000fe40007ffe0ff */
/*0b10*/ IADD3 R5, R5, 0x10, RZ ; /* 0x0000001005057810 */
/* 0x000fe40007ffe0ff */
/*0b20*/ LEA R18, R2, R18, 0x3 ; /* 0x0000001202127211 */
/* 0x000fe200078e18ff */
/*0b30*/ FFMA R7, R7, R8, R23 ; /* 0x0000000807077223 */
/* 0x004fc80000000017 */
/*0b40*/ FFMA R22, R22, R9, R7 ; /* 0x0000000916167223 */
/* 0x008fc80000000007 */
/*0b50*/ FFMA R11, R21, R11, R22 ; /* 0x0000000b150b7223 */
/* 0x020fc80000000016 */
/*0b60*/ FFMA R10, R24, R10, R11 ; /* 0x0000000a180a7223 */
/* 0x010fc8000000000b */
/*0b70*/ FFMA R10, R25, R20, R10 ; /* 0x00000014190a7223 */
/* 0x000fc8000000000a */
/*0b80*/ FFMA R10, R26, R19, R10 ; /* 0x000000131a0a7223 */
/* 0x000fc8000000000a */
/*0b90*/ FFMA R10, R27, R16, R10 ; /* 0x000000101b0a7223 */
/* 0x000fc8000000000a */
/*0ba0*/ FFMA R10, R29, R28, R10 ; /* 0x0000001c1d0a7223 */
/* 0x000fe2000000000a */
/*0bb0*/ @P0 BRA 0x490 ; /* 0xfffff8d000000947 */
/* 0x000fea000383ffff */
/*0bc0*/ IMAD.WIDE.U32 R4, R4, R0, c[0x0][0x170] ; /* 0x00005c0004047625 */
/* 0x000fca00078e0000 */
/*0bd0*/ STG.E [R4.64], R10 ; /* 0x0000000a04007986 */
/* 0x000fe2000c101904 */
/*0be0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0bf0*/ BRA 0xbf0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0c00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdlib.h>
#include <unistd.h>
#include <iostream>
#include <string>
#include <sstream>
using namespace std;
#include "cuda_runtime_api.h"
#define SIZE_OF_MATRIX 1000
#define SIZE_OF_BLOCK 16
#define M SIZE_OF_MATRIX
unsigned int m = SIZE_OF_MATRIX;
#define idx(i,j,lda) ((j) + ((i)*(lda)))
__global__ void multiply_matrices(float *d_a, float *d_b, float *d_c, int lda)
{
unsigned int row = threadIdx.y + blockDim.y * blockIdx.y;
unsigned int col = threadIdx.x + blockDim.x * blockIdx.x;
unsigned int id = idx(row,col,lda);
float ctemp = 0.0;
if (row < M && col < M)
{
for (unsigned int j=0; j<M; j++)
{
ctemp = ctemp + d_a[idx(row,j,lda)] * d_b[idx(j,col,lda)];
}
d_c[id] = ctemp;
}
}
__global__ void multiply_matrices_shared_blocks(float *d_a, float *d_b, float *d_c,
int lda)
{
int bs = SIZE_OF_BLOCK;
unsigned int row = threadIdx.y + blockDim.y * blockIdx.y;
unsigned int col = threadIdx.x + blockDim.x * blockIdx.x;
unsigned int id = idx(row,col,lda);
//submatrices
float *sub_a, *sub_b;
//shared submatrices
__shared__ float a[SIZE_OF_BLOCK][SIZE_OF_BLOCK], b[SIZE_OF_BLOCK][SIZE_OF_BLOCK];
//temp element of d_c
float c = 0;
//top-level row,col of block
int block_row = blockIdx.y * bs;
int block_col = blockIdx.x * bs;
//id inside each block
int sub_row = threadIdx.y;
int sub_col = threadIdx.x;
//for each block
for (int k = 0; k < (M / bs); k++)
{
sub_a = &d_a[idx(block_row, bs*k, lda)];
sub_b = &d_b[idx(bs*k, block_col, lda)];
a[sub_row][sub_col] = sub_a[idx(sub_row, sub_col, lda)];
b[sub_row][sub_col] = sub_b[idx(sub_row, sub_col, lda)];
//wait for all threads to complete copy to shared memory.
__syncthreads();
//multiply each submatrix
for (int j=0; j < bs; j++)
{
c = c + a[sub_row][j] * b[j][sub_col];
}
// move results to device memory.
d_c[id] = c;
// wait for multiplication to finish before moving onto the next submatrix.
__syncthreads();
}
}
void multiply_by_element(dim3 grid, dim3 threads, float *d_a, float *d_b, float *d_c, int m, cudaStream_t cStream)
{
cudaError err;
unsigned int matsize = SIZE_OF_MATRIX*SIZE_OF_MATRIX*sizeof(float);
float* c = (float*)malloc(matsize);
multiply_matrices<<< grid, threads, 0, cStream >>>(d_a, d_b, d_c, m);
err = cudaGetLastError();
if (err != cudaSuccess)
{
cout << "error in kernel, " << cudaGetErrorString(err) << endl;
}
cudaStreamSynchronize(cStream);
err = cudaMemcpyAsync(c, d_c, matsize, cudaMemcpyDeviceToHost, cStream);
if (err != cudaSuccess)
{
cout << "error in memcpy, #=" << cudaGetErrorString(err) << endl;
}
}
void multiply_by_block(dim3 grid, dim3 threads, float *d_a, float *d_b, float *d_c, int m, cudaStream_t cStream)
{
cudaError err;
unsigned int matsize = SIZE_OF_MATRIX*SIZE_OF_MATRIX*sizeof(float);
float* c = (float*)malloc(matsize);
multiply_matrices_shared_blocks<<< grid, threads, 0, cStream >>>(d_a, d_b, d_c, m);
err = cudaGetLastError();
if (err != cudaSuccess)
{
cout << "error in kernel, " << cudaGetErrorString(err) << endl;
}
cudaStreamSynchronize(cStream);
err = cudaMemcpyAsync(c, d_c, matsize, cudaMemcpyDeviceToHost, cStream);
if (err != cudaSuccess)
{
cout << "error in memcpy, #=" << cudaGetErrorString(err) << endl;
}
}
#define STREAM_INDEX(_d,_i) ((_d*number_of_iterations) + _i)
int main(int argc, char** argv)
{
unsigned int number_of_threads = min(SIZE_OF_MATRIX, SIZE_OF_BLOCK);
unsigned int number_of_blocks;
if (SIZE_OF_MATRIX > SIZE_OF_BLOCK)
number_of_blocks = ceil(SIZE_OF_MATRIX / ((float) SIZE_OF_BLOCK));
else
number_of_blocks = 1;
unsigned int matsize = SIZE_OF_MATRIX*SIZE_OF_MATRIX*sizeof(float);
//cout << "blocks: " << number_of_blocks << " threads: " <<
//number_of_threads << endl;
//cout.flush();
float* a = (float*)malloc(matsize);
float* b = (float*)malloc(matsize);
float* c = (float*)malloc(matsize);
//initalize matrices
for (int i=0; i<m; i++) {
for (int j=0; j<m; j++) {
//a[i*m+j] = i;
//b[i*m+j] = i;
a[i*m+j] = i-j*2 + i-j+1 + 1;
b[i*m+j] = i-j*2 + i-j+1 + 1;
c[i*m+j] = 0;
//cout << a[i*m+j] << ", ";
}
//cout << endl;
}
cudaError_t err;
int count = 0;
err = cudaGetDeviceCount(&count);
cout << count << " devices found." << endl;
string device_list("");
int number_of_iterations = 1;
int opt = getopt(argc, argv, "d:i:");
while(opt != -1) {
stringstream str;
switch(opt) {
case 'd':
device_list = string(optarg);
break;
case 'i':
str << optarg;
str >> number_of_iterations;
cout << "Doing " << number_of_iterations << " iterations." << std::endl;
break;
case '?':
if (optopt == 'd')
cerr << "Error, option -d requires argument: comma delimted list of devices to run on." << endl;
else if (optopt == 'i')
cerr << "Error, option -i requires argument: number of iterations to run." << endl;
else
cerr << "Error, unknow option. Usage:\nmatmult [-d <device id>,...] [-i <number of iterations]" << endl;
return 1;
default:
break;
}
opt = getopt(argc, argv, "d:i:");
}
int devices[count];
int nDevices = 0;
//default: use all the devices
if (device_list.compare("") == 0)
{
for (int d=0;d<count;d++)
{
devices[d] = d;
}
nDevices = count;
}
else
{
for (int d=0;d<count;d++)
{
stringstream str;
str << d;
char c = 0;
if (str >> c) {
if (device_list.find(c) != string::npos) {
devices[nDevices++] = d;
}
}
}
}
//cout << "finnished mapping devices." << endl;
float *d_a[nDevices], *d_b[nDevices], *d_c[nDevices];
cudaStream_t streams[nDevices * number_of_iterations];
for (int d=0;d<nDevices;d++)
{
cudaSetDevice(devices[d]);
cudaDeviceProp deviceProp;
cudaGetDeviceProperties(&deviceProp, devices[d]);
cout << "Using device " << devices[d] << ", name: " << deviceProp.name << endl;
err = cudaSetDevice(devices[d]);
if (err != cudaSuccess)
{
cout << "error setting device, #=" << cudaGetErrorString(err) << endl;
}
for (int i=0; i<number_of_iterations; i++)
{
err = cudaStreamCreate(&streams[STREAM_INDEX(d,i)]);
if (err != cudaSuccess)
{
cout << "error in stream creation, #=" << cudaGetErrorString(err) << endl;
}
}
err = cudaMalloc((void **) &d_a[d], matsize);
if (err != cudaSuccess)
{
cout << "error in malloc, #=" << cudaGetErrorString(err) << endl;
}
err = cudaMalloc((void **) &d_b[d], matsize);
if (err != cudaSuccess)
{
cout << "error in malloc, #=" << cudaGetErrorString(err) << endl;
}
err = cudaMalloc((void **) &d_c[d], matsize);
if (err != cudaSuccess)
{
cout << "error in malloc, #=" << cudaGetErrorString(err) << endl;
}
}
for (int d=0; d<nDevices; d++)
{
for (int i=0; i<number_of_iterations; i++)
{
cout << "Running on device " << d << ", stream " << i << endl;
int cDevice = d;
cudaStream_t cStream = streams[STREAM_INDEX(d,i)];
cudaSetDevice(devices[cDevice]);
if (err != cudaSuccess) {
cout << "error setting device: " << devices[i%nDevices] << " #=" << cudaGetErrorString(err) << endl;
}
err = cudaMemcpyAsync(d_a[cDevice], a, matsize, cudaMemcpyHostToDevice, cStream);
if (err != cudaSuccess) {
cout << "error in memcpy, #=" << cudaGetErrorString(err) << endl;
}
err = cudaMemcpyAsync(d_b[cDevice], b, matsize, cudaMemcpyHostToDevice, cStream);
if (err != cudaSuccess) {
cout << "error in memcpy, #=" << cudaGetErrorString(err) << endl;
}
//cout << "running on device " << cDevice << endl;
dim3 grid(number_of_blocks, number_of_blocks);
dim3 threads(number_of_threads, number_of_threads, 1);
//multiply each element at a time.
multiply_by_element(grid, threads, d_a[cDevice], d_b[cDevice], d_c[cDevice], m, cStream);
//multiply by first load a 16x16 submatrix into shared memory.
multiply_by_block(grid, threads, d_a[cDevice], d_b[cDevice], d_c[cDevice], m, cStream);
}
}
cout << "Finished " << number_of_iterations << " iterations on " << nDevices << " devices." << endl;
for (int d=0;d<nDevices;d++) {
cudaSetDevice(devices[d]);
for (int i=0; i<number_of_iterations; i++) {
cudaStreamSynchronize(streams[STREAM_INDEX(d,i)]);
}
}
for (int d=0;d<nDevices;d++) {
for (int i=0; i<number_of_iterations; i++) {
cudaStreamDestroy(streams[STREAM_INDEX(d,i)]);
}
}
//print c
/*
cout << " results: " << endl;
for (int i=0; i<m; i++) {
for (int j=0; j<m; j++) {
cout << c[i*m+j] << ", ";
}
cout << endl;
}
*/
//print c
/*
cout << " results: " << endl;
for (int i=0; i<m; i++) {
for (int j=0; j<m; j++) {
cout << c[i*m+j] << ", ";
}
cout << endl;
}
*/
cudaFree(d_a);
cudaFree(d_b);
cudaFree(d_c);
} | #include <hip/hip_runtime.h>
#include <stdlib.h>
#include <unistd.h>
#include <iostream>
#include <string>
#include <sstream>
using namespace std;
#include "hip/hip_runtime_api.h"
#define SIZE_OF_MATRIX 1000
#define SIZE_OF_BLOCK 16
#define M SIZE_OF_MATRIX
unsigned int m = SIZE_OF_MATRIX;
#define idx(i,j,lda) ((j) + ((i)*(lda)))
__global__ void multiply_matrices(float *d_a, float *d_b, float *d_c, int lda)
{
unsigned int row = threadIdx.y + blockDim.y * blockIdx.y;
unsigned int col = threadIdx.x + blockDim.x * blockIdx.x;
unsigned int id = idx(row,col,lda);
float ctemp = 0.0;
if (row < M && col < M)
{
for (unsigned int j=0; j<M; j++)
{
ctemp = ctemp + d_a[idx(row,j,lda)] * d_b[idx(j,col,lda)];
}
d_c[id] = ctemp;
}
}
__global__ void multiply_matrices_shared_blocks(float *d_a, float *d_b, float *d_c,
int lda)
{
int bs = SIZE_OF_BLOCK;
unsigned int row = threadIdx.y + blockDim.y * blockIdx.y;
unsigned int col = threadIdx.x + blockDim.x * blockIdx.x;
unsigned int id = idx(row,col,lda);
//submatrices
float *sub_a, *sub_b;
//shared submatrices
__shared__ float a[SIZE_OF_BLOCK][SIZE_OF_BLOCK], b[SIZE_OF_BLOCK][SIZE_OF_BLOCK];
//temp element of d_c
float c = 0;
//top-level row,col of block
int block_row = blockIdx.y * bs;
int block_col = blockIdx.x * bs;
//id inside each block
int sub_row = threadIdx.y;
int sub_col = threadIdx.x;
//for each block
for (int k = 0; k < (M / bs); k++)
{
sub_a = &d_a[idx(block_row, bs*k, lda)];
sub_b = &d_b[idx(bs*k, block_col, lda)];
a[sub_row][sub_col] = sub_a[idx(sub_row, sub_col, lda)];
b[sub_row][sub_col] = sub_b[idx(sub_row, sub_col, lda)];
//wait for all threads to complete copy to shared memory.
__syncthreads();
//multiply each submatrix
for (int j=0; j < bs; j++)
{
c = c + a[sub_row][j] * b[j][sub_col];
}
// move results to device memory.
d_c[id] = c;
// wait for multiplication to finish before moving onto the next submatrix.
__syncthreads();
}
}
void multiply_by_element(dim3 grid, dim3 threads, float *d_a, float *d_b, float *d_c, int m, hipStream_t cStream)
{
hipError_t err;
unsigned int matsize = SIZE_OF_MATRIX*SIZE_OF_MATRIX*sizeof(float);
float* c = (float*)malloc(matsize);
multiply_matrices<<< grid, threads, 0, cStream >>>(d_a, d_b, d_c, m);
err = hipGetLastError();
if (err != hipSuccess)
{
cout << "error in kernel, " << hipGetErrorString(err) << endl;
}
hipStreamSynchronize(cStream);
err = hipMemcpyAsync(c, d_c, matsize, hipMemcpyDeviceToHost, cStream);
if (err != hipSuccess)
{
cout << "error in memcpy, #=" << hipGetErrorString(err) << endl;
}
}
void multiply_by_block(dim3 grid, dim3 threads, float *d_a, float *d_b, float *d_c, int m, hipStream_t cStream)
{
hipError_t err;
unsigned int matsize = SIZE_OF_MATRIX*SIZE_OF_MATRIX*sizeof(float);
float* c = (float*)malloc(matsize);
multiply_matrices_shared_blocks<<< grid, threads, 0, cStream >>>(d_a, d_b, d_c, m);
err = hipGetLastError();
if (err != hipSuccess)
{
cout << "error in kernel, " << hipGetErrorString(err) << endl;
}
hipStreamSynchronize(cStream);
err = hipMemcpyAsync(c, d_c, matsize, hipMemcpyDeviceToHost, cStream);
if (err != hipSuccess)
{
cout << "error in memcpy, #=" << hipGetErrorString(err) << endl;
}
}
#define STREAM_INDEX(_d,_i) ((_d*number_of_iterations) + _i)
int main(int argc, char** argv)
{
unsigned int number_of_threads = min(SIZE_OF_MATRIX, SIZE_OF_BLOCK);
unsigned int number_of_blocks;
if (SIZE_OF_MATRIX > SIZE_OF_BLOCK)
number_of_blocks = ceil(SIZE_OF_MATRIX / ((float) SIZE_OF_BLOCK));
else
number_of_blocks = 1;
unsigned int matsize = SIZE_OF_MATRIX*SIZE_OF_MATRIX*sizeof(float);
//cout << "blocks: " << number_of_blocks << " threads: " <<
//number_of_threads << endl;
//cout.flush();
float* a = (float*)malloc(matsize);
float* b = (float*)malloc(matsize);
float* c = (float*)malloc(matsize);
//initalize matrices
for (int i=0; i<m; i++) {
for (int j=0; j<m; j++) {
//a[i*m+j] = i;
//b[i*m+j] = i;
a[i*m+j] = i-j*2 + i-j+1 + 1;
b[i*m+j] = i-j*2 + i-j+1 + 1;
c[i*m+j] = 0;
//cout << a[i*m+j] << ", ";
}
//cout << endl;
}
hipError_t err;
int count = 0;
err = hipGetDeviceCount(&count);
cout << count << " devices found." << endl;
string device_list("");
int number_of_iterations = 1;
int opt = getopt(argc, argv, "d:i:");
while(opt != -1) {
stringstream str;
switch(opt) {
case 'd':
device_list = string(optarg);
break;
case 'i':
str << optarg;
str >> number_of_iterations;
cout << "Doing " << number_of_iterations << " iterations." << std::endl;
break;
case '?':
if (optopt == 'd')
cerr << "Error, option -d requires argument: comma delimted list of devices to run on." << endl;
else if (optopt == 'i')
cerr << "Error, option -i requires argument: number of iterations to run." << endl;
else
cerr << "Error, unknow option. Usage:\nmatmult [-d <device id>,...] [-i <number of iterations]" << endl;
return 1;
default:
break;
}
opt = getopt(argc, argv, "d:i:");
}
int devices[count];
int nDevices = 0;
//default: use all the devices
if (device_list.compare("") == 0)
{
for (int d=0;d<count;d++)
{
devices[d] = d;
}
nDevices = count;
}
else
{
for (int d=0;d<count;d++)
{
stringstream str;
str << d;
char c = 0;
if (str >> c) {
if (device_list.find(c) != string::npos) {
devices[nDevices++] = d;
}
}
}
}
//cout << "finnished mapping devices." << endl;
float *d_a[nDevices], *d_b[nDevices], *d_c[nDevices];
hipStream_t streams[nDevices * number_of_iterations];
for (int d=0;d<nDevices;d++)
{
hipSetDevice(devices[d]);
hipDeviceProp_t deviceProp;
hipGetDeviceProperties(&deviceProp, devices[d]);
cout << "Using device " << devices[d] << ", name: " << deviceProp.name << endl;
err = hipSetDevice(devices[d]);
if (err != hipSuccess)
{
cout << "error setting device, #=" << hipGetErrorString(err) << endl;
}
for (int i=0; i<number_of_iterations; i++)
{
err = hipStreamCreate(&streams[STREAM_INDEX(d,i)]);
if (err != hipSuccess)
{
cout << "error in stream creation, #=" << hipGetErrorString(err) << endl;
}
}
err = hipMalloc((void **) &d_a[d], matsize);
if (err != hipSuccess)
{
cout << "error in malloc, #=" << hipGetErrorString(err) << endl;
}
err = hipMalloc((void **) &d_b[d], matsize);
if (err != hipSuccess)
{
cout << "error in malloc, #=" << hipGetErrorString(err) << endl;
}
err = hipMalloc((void **) &d_c[d], matsize);
if (err != hipSuccess)
{
cout << "error in malloc, #=" << hipGetErrorString(err) << endl;
}
}
for (int d=0; d<nDevices; d++)
{
for (int i=0; i<number_of_iterations; i++)
{
cout << "Running on device " << d << ", stream " << i << endl;
int cDevice = d;
hipStream_t cStream = streams[STREAM_INDEX(d,i)];
hipSetDevice(devices[cDevice]);
if (err != hipSuccess) {
cout << "error setting device: " << devices[i%nDevices] << " #=" << hipGetErrorString(err) << endl;
}
err = hipMemcpyAsync(d_a[cDevice], a, matsize, hipMemcpyHostToDevice, cStream);
if (err != hipSuccess) {
cout << "error in memcpy, #=" << hipGetErrorString(err) << endl;
}
err = hipMemcpyAsync(d_b[cDevice], b, matsize, hipMemcpyHostToDevice, cStream);
if (err != hipSuccess) {
cout << "error in memcpy, #=" << hipGetErrorString(err) << endl;
}
//cout << "running on device " << cDevice << endl;
dim3 grid(number_of_blocks, number_of_blocks);
dim3 threads(number_of_threads, number_of_threads, 1);
//multiply each element at a time.
multiply_by_element(grid, threads, d_a[cDevice], d_b[cDevice], d_c[cDevice], m, cStream);
//multiply by first load a 16x16 submatrix into shared memory.
multiply_by_block(grid, threads, d_a[cDevice], d_b[cDevice], d_c[cDevice], m, cStream);
}
}
cout << "Finished " << number_of_iterations << " iterations on " << nDevices << " devices." << endl;
for (int d=0;d<nDevices;d++) {
hipSetDevice(devices[d]);
for (int i=0; i<number_of_iterations; i++) {
hipStreamSynchronize(streams[STREAM_INDEX(d,i)]);
}
}
for (int d=0;d<nDevices;d++) {
for (int i=0; i<number_of_iterations; i++) {
hipStreamDestroy(streams[STREAM_INDEX(d,i)]);
}
}
//print c
/*
cout << " results: " << endl;
for (int i=0; i<m; i++) {
for (int j=0; j<m; j++) {
cout << c[i*m+j] << ", ";
}
cout << endl;
}
*/
//print c
/*
cout << " results: " << endl;
for (int i=0; i<m; i++) {
for (int j=0; j<m; j++) {
cout << c[i*m+j] << ", ";
}
cout << endl;
}
*/
hipFree(d_a);
hipFree(d_b);
hipFree(d_c);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdlib.h>
#include <unistd.h>
#include <iostream>
#include <string>
#include <sstream>
using namespace std;
#include "hip/hip_runtime_api.h"
#define SIZE_OF_MATRIX 1000
#define SIZE_OF_BLOCK 16
#define M SIZE_OF_MATRIX
unsigned int m = SIZE_OF_MATRIX;
#define idx(i,j,lda) ((j) + ((i)*(lda)))
__global__ void multiply_matrices(float *d_a, float *d_b, float *d_c, int lda)
{
unsigned int row = threadIdx.y + blockDim.y * blockIdx.y;
unsigned int col = threadIdx.x + blockDim.x * blockIdx.x;
unsigned int id = idx(row,col,lda);
float ctemp = 0.0;
if (row < M && col < M)
{
for (unsigned int j=0; j<M; j++)
{
ctemp = ctemp + d_a[idx(row,j,lda)] * d_b[idx(j,col,lda)];
}
d_c[id] = ctemp;
}
}
__global__ void multiply_matrices_shared_blocks(float *d_a, float *d_b, float *d_c,
int lda)
{
int bs = SIZE_OF_BLOCK;
unsigned int row = threadIdx.y + blockDim.y * blockIdx.y;
unsigned int col = threadIdx.x + blockDim.x * blockIdx.x;
unsigned int id = idx(row,col,lda);
//submatrices
float *sub_a, *sub_b;
//shared submatrices
__shared__ float a[SIZE_OF_BLOCK][SIZE_OF_BLOCK], b[SIZE_OF_BLOCK][SIZE_OF_BLOCK];
//temp element of d_c
float c = 0;
//top-level row,col of block
int block_row = blockIdx.y * bs;
int block_col = blockIdx.x * bs;
//id inside each block
int sub_row = threadIdx.y;
int sub_col = threadIdx.x;
//for each block
for (int k = 0; k < (M / bs); k++)
{
sub_a = &d_a[idx(block_row, bs*k, lda)];
sub_b = &d_b[idx(bs*k, block_col, lda)];
a[sub_row][sub_col] = sub_a[idx(sub_row, sub_col, lda)];
b[sub_row][sub_col] = sub_b[idx(sub_row, sub_col, lda)];
//wait for all threads to complete copy to shared memory.
__syncthreads();
//multiply each submatrix
for (int j=0; j < bs; j++)
{
c = c + a[sub_row][j] * b[j][sub_col];
}
// move results to device memory.
d_c[id] = c;
// wait for multiplication to finish before moving onto the next submatrix.
__syncthreads();
}
}
void multiply_by_element(dim3 grid, dim3 threads, float *d_a, float *d_b, float *d_c, int m, hipStream_t cStream)
{
hipError_t err;
unsigned int matsize = SIZE_OF_MATRIX*SIZE_OF_MATRIX*sizeof(float);
float* c = (float*)malloc(matsize);
multiply_matrices<<< grid, threads, 0, cStream >>>(d_a, d_b, d_c, m);
err = hipGetLastError();
if (err != hipSuccess)
{
cout << "error in kernel, " << hipGetErrorString(err) << endl;
}
hipStreamSynchronize(cStream);
err = hipMemcpyAsync(c, d_c, matsize, hipMemcpyDeviceToHost, cStream);
if (err != hipSuccess)
{
cout << "error in memcpy, #=" << hipGetErrorString(err) << endl;
}
}
void multiply_by_block(dim3 grid, dim3 threads, float *d_a, float *d_b, float *d_c, int m, hipStream_t cStream)
{
hipError_t err;
unsigned int matsize = SIZE_OF_MATRIX*SIZE_OF_MATRIX*sizeof(float);
float* c = (float*)malloc(matsize);
multiply_matrices_shared_blocks<<< grid, threads, 0, cStream >>>(d_a, d_b, d_c, m);
err = hipGetLastError();
if (err != hipSuccess)
{
cout << "error in kernel, " << hipGetErrorString(err) << endl;
}
hipStreamSynchronize(cStream);
err = hipMemcpyAsync(c, d_c, matsize, hipMemcpyDeviceToHost, cStream);
if (err != hipSuccess)
{
cout << "error in memcpy, #=" << hipGetErrorString(err) << endl;
}
}
#define STREAM_INDEX(_d,_i) ((_d*number_of_iterations) + _i)
int main(int argc, char** argv)
{
unsigned int number_of_threads = min(SIZE_OF_MATRIX, SIZE_OF_BLOCK);
unsigned int number_of_blocks;
if (SIZE_OF_MATRIX > SIZE_OF_BLOCK)
number_of_blocks = ceil(SIZE_OF_MATRIX / ((float) SIZE_OF_BLOCK));
else
number_of_blocks = 1;
unsigned int matsize = SIZE_OF_MATRIX*SIZE_OF_MATRIX*sizeof(float);
//cout << "blocks: " << number_of_blocks << " threads: " <<
//number_of_threads << endl;
//cout.flush();
float* a = (float*)malloc(matsize);
float* b = (float*)malloc(matsize);
float* c = (float*)malloc(matsize);
//initalize matrices
for (int i=0; i<m; i++) {
for (int j=0; j<m; j++) {
//a[i*m+j] = i;
//b[i*m+j] = i;
a[i*m+j] = i-j*2 + i-j+1 + 1;
b[i*m+j] = i-j*2 + i-j+1 + 1;
c[i*m+j] = 0;
//cout << a[i*m+j] << ", ";
}
//cout << endl;
}
hipError_t err;
int count = 0;
err = hipGetDeviceCount(&count);
cout << count << " devices found." << endl;
string device_list("");
int number_of_iterations = 1;
int opt = getopt(argc, argv, "d:i:");
while(opt != -1) {
stringstream str;
switch(opt) {
case 'd':
device_list = string(optarg);
break;
case 'i':
str << optarg;
str >> number_of_iterations;
cout << "Doing " << number_of_iterations << " iterations." << std::endl;
break;
case '?':
if (optopt == 'd')
cerr << "Error, option -d requires argument: comma delimted list of devices to run on." << endl;
else if (optopt == 'i')
cerr << "Error, option -i requires argument: number of iterations to run." << endl;
else
cerr << "Error, unknow option. Usage:\nmatmult [-d <device id>,...] [-i <number of iterations]" << endl;
return 1;
default:
break;
}
opt = getopt(argc, argv, "d:i:");
}
int devices[count];
int nDevices = 0;
//default: use all the devices
if (device_list.compare("") == 0)
{
for (int d=0;d<count;d++)
{
devices[d] = d;
}
nDevices = count;
}
else
{
for (int d=0;d<count;d++)
{
stringstream str;
str << d;
char c = 0;
if (str >> c) {
if (device_list.find(c) != string::npos) {
devices[nDevices++] = d;
}
}
}
}
//cout << "finnished mapping devices." << endl;
float *d_a[nDevices], *d_b[nDevices], *d_c[nDevices];
hipStream_t streams[nDevices * number_of_iterations];
for (int d=0;d<nDevices;d++)
{
hipSetDevice(devices[d]);
hipDeviceProp_t deviceProp;
hipGetDeviceProperties(&deviceProp, devices[d]);
cout << "Using device " << devices[d] << ", name: " << deviceProp.name << endl;
err = hipSetDevice(devices[d]);
if (err != hipSuccess)
{
cout << "error setting device, #=" << hipGetErrorString(err) << endl;
}
for (int i=0; i<number_of_iterations; i++)
{
err = hipStreamCreate(&streams[STREAM_INDEX(d,i)]);
if (err != hipSuccess)
{
cout << "error in stream creation, #=" << hipGetErrorString(err) << endl;
}
}
err = hipMalloc((void **) &d_a[d], matsize);
if (err != hipSuccess)
{
cout << "error in malloc, #=" << hipGetErrorString(err) << endl;
}
err = hipMalloc((void **) &d_b[d], matsize);
if (err != hipSuccess)
{
cout << "error in malloc, #=" << hipGetErrorString(err) << endl;
}
err = hipMalloc((void **) &d_c[d], matsize);
if (err != hipSuccess)
{
cout << "error in malloc, #=" << hipGetErrorString(err) << endl;
}
}
for (int d=0; d<nDevices; d++)
{
for (int i=0; i<number_of_iterations; i++)
{
cout << "Running on device " << d << ", stream " << i << endl;
int cDevice = d;
hipStream_t cStream = streams[STREAM_INDEX(d,i)];
hipSetDevice(devices[cDevice]);
if (err != hipSuccess) {
cout << "error setting device: " << devices[i%nDevices] << " #=" << hipGetErrorString(err) << endl;
}
err = hipMemcpyAsync(d_a[cDevice], a, matsize, hipMemcpyHostToDevice, cStream);
if (err != hipSuccess) {
cout << "error in memcpy, #=" << hipGetErrorString(err) << endl;
}
err = hipMemcpyAsync(d_b[cDevice], b, matsize, hipMemcpyHostToDevice, cStream);
if (err != hipSuccess) {
cout << "error in memcpy, #=" << hipGetErrorString(err) << endl;
}
//cout << "running on device " << cDevice << endl;
dim3 grid(number_of_blocks, number_of_blocks);
dim3 threads(number_of_threads, number_of_threads, 1);
//multiply each element at a time.
multiply_by_element(grid, threads, d_a[cDevice], d_b[cDevice], d_c[cDevice], m, cStream);
//multiply by first load a 16x16 submatrix into shared memory.
multiply_by_block(grid, threads, d_a[cDevice], d_b[cDevice], d_c[cDevice], m, cStream);
}
}
cout << "Finished " << number_of_iterations << " iterations on " << nDevices << " devices." << endl;
for (int d=0;d<nDevices;d++) {
hipSetDevice(devices[d]);
for (int i=0; i<number_of_iterations; i++) {
hipStreamSynchronize(streams[STREAM_INDEX(d,i)]);
}
}
for (int d=0;d<nDevices;d++) {
for (int i=0; i<number_of_iterations; i++) {
hipStreamDestroy(streams[STREAM_INDEX(d,i)]);
}
}
//print c
/*
cout << " results: " << endl;
for (int i=0; i<m; i++) {
for (int j=0; j<m; j++) {
cout << c[i*m+j] << ", ";
}
cout << endl;
}
*/
//print c
/*
cout << " results: " << endl;
for (int i=0; i<m; i++) {
for (int j=0; j<m; j++) {
cout << c[i*m+j] << ", ";
}
cout << endl;
}
*/
hipFree(d_a);
hipFree(d_b);
hipFree(d_c);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z17multiply_matricesPfS_S_i
.globl _Z17multiply_matricesPfS_S_i
.p2align 8
.type _Z17multiply_matricesPfS_S_i,@function
_Z17multiply_matricesPfS_S_i:
s_load_b32 s2, s[0:1], 0x2c
v_bfe_u32 v1, v0, 10, 10
v_and_b32_e32 v4, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s3, s2, 16
s_and_b32 s2, s2, 0xffff
v_mad_u64_u32 v[2:3], null, s15, s3, v[1:2]
v_mad_u64_u32 v[0:1], null, s14, s2, v[4:5]
s_mov_b32 s2, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_max_u32_e32 v1, v2, v0
v_cmpx_gt_u32_e32 0x3e8, v1
s_cbranch_execz .LBB0_4
s_clause 0x1
s_load_b32 s2, s[0:1], 0x18
s_load_b128 s[4:7], s[0:1], 0x0
v_mov_b32_e32 v3, 0
v_mov_b32_e32 v1, v0
s_mov_b32 s3, 0
s_waitcnt lgkmcnt(0)
v_mul_lo_u32 v4, v2, s2
.p2align 6
.LBB0_2:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_dual_mov_b32 v6, 0 :: v_dual_add_nc_u32 v5, s3, v4
s_add_i32 s3, s3, 1
s_cmpk_eq_i32 s3, 0x3e8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mov_b32_e32 v2, v6
v_lshlrev_b64 v[5:6], 2, v[5:6]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[7:8], 2, v[1:2]
v_add_nc_u32_e32 v1, s2, v1
v_add_co_u32 v5, vcc_lo, s4, v5
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_ci_u32_e32 v6, vcc_lo, s5, v6, vcc_lo
v_add_co_u32 v7, vcc_lo, s6, v7
v_add_co_ci_u32_e32 v8, vcc_lo, s7, v8, vcc_lo
global_load_b32 v2, v[5:6], off
global_load_b32 v5, v[7:8], off
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v3, v2, v5
s_cbranch_scc0 .LBB0_2
s_load_b64 s[0:1], s[0:1], 0x10
v_dual_mov_b32 v1, 0 :: v_dual_add_nc_u32 v0, v0, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v3, off
.LBB0_4:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z17multiply_matricesPfS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z17multiply_matricesPfS_S_i, .Lfunc_end0-_Z17multiply_matricesPfS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z31multiply_matrices_shared_blocksPfS_S_i
.globl _Z31multiply_matrices_shared_blocksPfS_S_i
.p2align 8
.type _Z31multiply_matrices_shared_blocksPfS_S_i,@function
_Z31multiply_matrices_shared_blocksPfS_S_i:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x2c
s_load_b32 s2, s[0:1], 0x18
v_bfe_u32 v1, v0, 10, 10
v_and_b32_e32 v0, 0x3ff, v0
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
v_lshlrev_b32_e32 v4, 6, v1
s_waitcnt lgkmcnt(0)
s_lshr_b32 s8, s3, 16
v_mad_u64_u32 v[2:3], null, v1, s2, v[0:1]
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_mul_i32 s3, s14, s3
v_mad_u64_u32 v[6:7], null, s15, s8, v[1:2]
v_mov_b32_e32 v1, 0
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b32_e32 v7, 2, v0
s_mul_i32 s15, s15, s2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[2:3], 2, v[2:3]
v_mul_lo_u32 v8, v6, s2
v_add_nc_u32_e32 v5, 0x400, v7
v_add_nc_u32_e32 v6, v4, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_nc_u32_e32 v7, v5, v4
v_add3_u32 v0, s3, v0, v8
v_add_co_u32 v8, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v9, vcc_lo, s5, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[11:12], 2, v[0:1]
v_add_co_u32 v0, vcc_lo, s6, v2
v_add_co_ci_u32_e32 v10, vcc_lo, s7, v3, vcc_lo
s_mov_b32 s3, 0
v_add_co_u32 v2, vcc_lo, s0, v11
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v12, vcc_lo
s_lshl_b32 s0, s14, 4
s_lshl_b32 s1, s15, 4
s_set_inst_prefetch_distance 0x1
.p2align 6
.LBB1_1:
s_lshl_b32 s4, s3, 4
s_delay_alu instid0(SALU_CYCLE_1)
s_mul_i32 s5, s4, s2
s_add_i32 s4, s4, s1
s_add_i32 s6, s5, s0
s_ashr_i32 s5, s4, 31
s_ashr_i32 s7, s6, 31
s_lshl_b64 s[4:5], s[4:5], 2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_add_co_u32 v11, vcc_lo, v8, s4
v_add_co_ci_u32_e32 v12, vcc_lo, s5, v9, vcc_lo
s_lshl_b64 s[4:5], s[6:7], 2
v_add_co_u32 v13, vcc_lo, v0, s4
v_add_co_ci_u32_e32 v14, vcc_lo, s5, v10, vcc_lo
global_load_b32 v12, v[11:12], off
global_load_b32 v13, v[13:14], off
v_mov_b32_e32 v11, v5
s_mov_b32 s4, 0
s_waitcnt vmcnt(1)
ds_store_b32 v6, v12
s_waitcnt vmcnt(0)
ds_store_b32 v7, v13
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
.LBB1_2:
v_add_nc_u32_e32 v12, s4, v4
s_add_i32 s4, s4, 4
ds_load_b32 v13, v11
ds_load_b32 v12, v12
v_add_nc_u32_e32 v11, 64, v11
s_cmp_eq_u32 s4, 64
s_waitcnt lgkmcnt(0)
v_fmac_f32_e32 v1, v12, v13
s_cbranch_scc0 .LBB1_2
s_add_i32 s3, s3, 1
global_store_b32 v[2:3], v1, off
s_cmp_eq_u32 s3, 62
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
s_cbranch_scc0 .LBB1_1
s_set_inst_prefetch_distance 0x2
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z31multiply_matrices_shared_blocksPfS_S_i
.amdhsa_group_segment_fixed_size 2048
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 15
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z31multiply_matrices_shared_blocksPfS_S_i, .Lfunc_end1-_Z31multiply_matrices_shared_blocksPfS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z17multiply_matricesPfS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z17multiply_matricesPfS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 2048
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z31multiply_matrices_shared_blocksPfS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z31multiply_matrices_shared_blocksPfS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 15
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
__global__ void mykernel(void) {
int i = blockDim.x * blockIdx.x + threadIdx.x;
printf("***blockDim=%d\n",blockDim.x);
printf("***blockIdx=%d\n",blockIdx.x);
printf("***threadIdx=%d\n",threadIdx.x);
printf("***index=%d\n",i);
}
int main() {
mykernel<<<1,1>>>();
return 0;
} | code for sm_80
Function : _Z8mykernelv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fca00078e00ff */
/*0010*/ IADD3 R1, R1, -0x8, RZ ; /* 0xfffffff801017810 */
/* 0x000fe20007ffe0ff */
/*0020*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff007624 */
/* 0x000fe200078e00ff */
/*0030*/ S2R R19, SR_CTAID.X ; /* 0x0000000000137919 */
/* 0x000e220000002500 */
/*0040*/ MOV R18, 0x0 ; /* 0x0000000000127802 */
/* 0x000fe20000000f00 */
/*0050*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x8] ; /* 0x01000200ff047624 */
/* 0x000fe200078e00ff */
/*0060*/ IADD3 R17, P0, R1, c[0x0][0x20], RZ ; /* 0x0000080001117a10 */
/* 0x000fe20007f1e0ff */
/*0070*/ S2R R22, SR_TID.X ; /* 0x0000000000167919 */
/* 0x000e220000002100 */
/*0080*/ LDC.64 R8, c[0x4][R18] ; /* 0x0100000012087b82 */
/* 0x0002a20000000a00 */
/*0090*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0xc] ; /* 0x01000300ff057624 */
/* 0x000fe400078e00ff */
/*00a0*/ STL [R1], R0 ; /* 0x0000000001007387 */
/* 0x0003e20000100800 */
/*00b0*/ IMAD.X R16, RZ, RZ, c[0x0][0x24], P0 ; /* 0x00000900ff107624 */
/* 0x000fc400000e06ff */
/*00c0*/ IMAD.MOV.U32 R6, RZ, RZ, R17 ; /* 0x000000ffff067224 */
/* 0x000fe400078e0011 */
/*00d0*/ IMAD.MOV.U32 R7, RZ, RZ, R16 ; /* 0x000000ffff077224 */
/* 0x000fe400078e0010 */
/*00e0*/ IMAD R2, R19, c[0x0][0x0], R22 ; /* 0x0000000013027a24 */
/* 0x001fe400078e0216 */
/*00f0*/ LEPC R10 ; /* 0x00000000000a734e */
/* 0x002fca0000000000 */
/*0100*/ MOV R3, 0x170 ; /* 0x0000017000037802 */
/* 0x000fe40000000f00 */
/*0110*/ MOV R20, 0xf0 ; /* 0x000000f000147802 */
/* 0x000fe40000000f00 */
/*0120*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*0130*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fc40000000f00 */
/*0140*/ IADD3 R20, P0, P1, -R20, R3, R10 ; /* 0x0000000314147210 */
/* 0x000fc8000791e10a */
/*0150*/ IADD3.X R21, ~R0, R21, R11, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e250b */
/*0160*/ CALL.ABS.NOINC R8 ; /* 0x0000000008007343 */
/* 0x004fea0003c00000 */
/*0170*/ STL [R1], R19 ; /* 0x0000001301007387 */
/* 0x0001e20000100800 */
/*0180*/ LDC.64 R8, c[0x4][R18] ; /* 0x0100000012087b82 */
/* 0x0000620000000a00 */
/*0190*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x10] ; /* 0x01000400ff047624 */
/* 0x000fe400078e00ff */
/*01a0*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0x14] ; /* 0x01000500ff057624 */
/* 0x000fe400078e00ff */
/*01b0*/ IMAD.MOV.U32 R6, RZ, RZ, R17 ; /* 0x000000ffff067224 */
/* 0x000fe400078e0011 */
/*01c0*/ IMAD.MOV.U32 R7, RZ, RZ, R16 ; /* 0x000000ffff077224 */
/* 0x000fe400078e0010 */
/*01d0*/ LEPC R10 ; /* 0x00000000000a734e */
/* 0x000fca0000000000 */
/*01e0*/ MOV R3, 0x250 ; /* 0x0000025000037802 */
/* 0x000fe40000000f00 */
/*01f0*/ MOV R20, 0x1d0 ; /* 0x000001d000147802 */
/* 0x000fc40000000f00 */
/*0200*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*0210*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe40000000f00 */
/*0220*/ IADD3 R20, P0, P1, -R20, R3, R10 ; /* 0x0000000314147210 */
/* 0x000fc8000791e10a */
/*0230*/ IADD3.X R21, ~R0, R21, R11, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e250b */
/*0240*/ CALL.ABS.NOINC R8 ; /* 0x0000000008007343 */
/* 0x003fea0003c00000 */
/*0250*/ STL [R1], R22 ; /* 0x0000001601007387 */
/* 0x0001e20000100800 */
/*0260*/ LDC.64 R8, c[0x4][R18] ; /* 0x0100000012087b82 */
/* 0x0000620000000a00 */
/*0270*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x18] ; /* 0x01000600ff047624 */
/* 0x000fe400078e00ff */
/*0280*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0x1c] ; /* 0x01000700ff057624 */
/* 0x000fe400078e00ff */
/*0290*/ IMAD.MOV.U32 R6, RZ, RZ, R17 ; /* 0x000000ffff067224 */
/* 0x000fe400078e0011 */
/*02a0*/ IMAD.MOV.U32 R7, RZ, RZ, R16 ; /* 0x000000ffff077224 */
/* 0x000fe400078e0010 */
/*02b0*/ LEPC R10 ; /* 0x00000000000a734e */
/* 0x000fca0000000000 */
/*02c0*/ MOV R3, 0x330 ; /* 0x0000033000037802 */
/* 0x000fe40000000f00 */
/*02d0*/ MOV R20, 0x2b0 ; /* 0x000002b000147802 */
/* 0x000fc40000000f00 */
/*02e0*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*02f0*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe40000000f00 */
/*0300*/ IADD3 R20, P0, P1, -R20, R3, R10 ; /* 0x0000000314147210 */
/* 0x000fc8000791e10a */
/*0310*/ IADD3.X R21, ~R0, R21, R11, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e250b */
/*0320*/ CALL.ABS.NOINC R8 ; /* 0x0000000008007343 */
/* 0x003fea0003c00000 */
/*0330*/ STL [R1], R2 ; /* 0x0000000201007387 */
/* 0x0001e20000100800 */
/*0340*/ LDC.64 R18, c[0x4][R18] ; /* 0x0100000012127b82 */
/* 0x000e620000000a00 */
/*0350*/ IMAD.MOV.U32 R6, RZ, RZ, R17 ; /* 0x000000ffff067224 */
/* 0x000fe400078e0011 */
/*0360*/ IMAD.MOV.U32 R7, RZ, RZ, R16 ; /* 0x000000ffff077224 */
/* 0x000fe400078e0010 */
/*0370*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x20] ; /* 0x01000800ff047624 */
/* 0x000fe400078e00ff */
/*0380*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0x24] ; /* 0x01000900ff057624 */
/* 0x000fe400078e00ff */
/*0390*/ LEPC R2 ; /* 0x000000000002734e */
/* 0x001fca0000000000 */
/*03a0*/ MOV R9, 0x410 ; /* 0x0000041000097802 */
/* 0x000fe40000000f00 */
/*03b0*/ MOV R20, 0x390 ; /* 0x0000039000147802 */
/* 0x000fc40000000f00 */
/*03c0*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*03d0*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe40000000f00 */
/*03e0*/ IADD3 R20, P0, P1, -R20, R9, R2 ; /* 0x0000000914147210 */
/* 0x000fc8000791e102 */
/*03f0*/ IADD3.X R21, ~R0, R21, R3, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2503 */
/*0400*/ CALL.ABS.NOINC R18 ; /* 0x0000000012007343 */
/* 0x002fea0003c00000 */
/*0410*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0420*/ BRA 0x420; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0430*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0440*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0450*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0460*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0470*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0480*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0490*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
__global__ void mykernel(void) {
int i = blockDim.x * blockIdx.x + threadIdx.x;
printf("***blockDim=%d\n",blockDim.x);
printf("***blockIdx=%d\n",blockIdx.x);
printf("***threadIdx=%d\n",threadIdx.x);
printf("***index=%d\n",i);
}
int main() {
mykernel<<<1,1>>>();
return 0;
} | .file "tmpxft_0017da40_00000000-6_index.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z26__device_stub__Z8mykernelvv
.type _Z26__device_stub__Z8mykernelvv, @function
_Z26__device_stub__Z8mykernelvv:
.LFB2082:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z8mykernelv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z26__device_stub__Z8mykernelvv, .-_Z26__device_stub__Z8mykernelvv
.globl _Z8mykernelv
.type _Z8mykernelv, @function
_Z8mykernelv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z8mykernelvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z8mykernelv, .-_Z8mykernelv
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L12:
movl $0, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
call _Z26__device_stub__Z8mykernelvv
jmp .L12
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z8mykernelv"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z8mykernelv(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
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