system stringclasses 7 values | input stringlengths 10 94.5k | output stringlengths 14 55.5k |
|---|---|---|
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
__global__ void mykernel(void) {
int i = blockDim.x * blockIdx.x + threadIdx.x;
printf("***blockDim=%d\n",blockDim.x);
printf("***blockIdx=%d\n",blockIdx.x);
printf("***threadIdx=%d\n",threadIdx.x);
printf("***index=%d\n",i);
}
int main() {
mykernel<<<1,1>>>();
return 0;
} | #include <hip/hip_runtime.h>
#include <stdio.h>
__global__ void mykernel(void) {
int i = blockDim.x * blockIdx.x + threadIdx.x;
printf("***blockDim=%d\n",blockDim.x);
printf("***blockIdx=%d\n",blockIdx.x);
printf("***threadIdx=%d\n",threadIdx.x);
printf("***index=%d\n",i);
}
int main() {
mykernel<<<1,1>>>();
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
__global__ void mykernel(void) {
int i = blockDim.x * blockIdx.x + threadIdx.x;
printf("***blockDim=%d\n",blockDim.x);
printf("***blockIdx=%d\n",blockIdx.x);
printf("***threadIdx=%d\n",threadIdx.x);
printf("***index=%d\n",i);
}
int main() {
mykernel<<<1,1>>>();
return 0;
} | .text
.file "index.hip"
.globl _Z23__device_stub__mykernelv # -- Begin function _Z23__device_stub__mykernelv
.p2align 4, 0x90
.type _Z23__device_stub__mykernelv,@function
_Z23__device_stub__mykernelv: # @_Z23__device_stub__mykernelv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z8mykernelv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z23__device_stub__mykernelv, .Lfunc_end0-_Z23__device_stub__mykernelv
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z8mykernelv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
xorl %eax, %eax
addq $56, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8mykernelv, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z8mykernelv,@object # @_Z8mykernelv
.section .rodata,"a",@progbits
.globl _Z8mykernelv
.p2align 3, 0x0
_Z8mykernelv:
.quad _Z23__device_stub__mykernelv
.size _Z8mykernelv, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z8mykernelv"
.size .L__unnamed_1, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__mykernelv
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8mykernelv
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0017da40_00000000-6_index.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z26__device_stub__Z8mykernelvv
.type _Z26__device_stub__Z8mykernelvv, @function
_Z26__device_stub__Z8mykernelvv:
.LFB2082:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z8mykernelv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z26__device_stub__Z8mykernelvv, .-_Z26__device_stub__Z8mykernelvv
.globl _Z8mykernelv
.type _Z8mykernelv, @function
_Z8mykernelv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z8mykernelvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z8mykernelv, .-_Z8mykernelv
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L12:
movl $0, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
call _Z26__device_stub__Z8mykernelvv
jmp .L12
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z8mykernelv"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z8mykernelv(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "index.hip"
.globl _Z23__device_stub__mykernelv # -- Begin function _Z23__device_stub__mykernelv
.p2align 4, 0x90
.type _Z23__device_stub__mykernelv,@function
_Z23__device_stub__mykernelv: # @_Z23__device_stub__mykernelv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z8mykernelv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z23__device_stub__mykernelv, .Lfunc_end0-_Z23__device_stub__mykernelv
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z8mykernelv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
xorl %eax, %eax
addq $56, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8mykernelv, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z8mykernelv,@object # @_Z8mykernelv
.section .rodata,"a",@progbits
.globl _Z8mykernelv
.p2align 3, 0x0
_Z8mykernelv:
.quad _Z23__device_stub__mykernelv
.size _Z8mykernelv, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z8mykernelv"
.size .L__unnamed_1, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__mykernelv
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8mykernelv
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | /* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
* DESCRIPTION :
*
Serial Concurrent Wave Equation - C Version
*
This program implements the concurrent wave equation
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
# include <stdio.h>
# include <stdlib.h>
# include <math.h>
# include <time.h>
# include <cuda_runtime.h>
# define MAXPOINTS 1000000
# define MAXSTEPS 1000000
# define MINPOINTS 20
# define PI 3.14159265
# define DIM_GRID 1
# define BLOCK_SIZE 256
void check_param ( void ) ;
void init_line ( void ) ;
void update ( void ) ;
void printfinal ( void ) ;
int nsteps , /*number of time steps */
tpoints , /*total points along string */
rcode ; /*generic return code */
float values [ MAXPOINTS +2], /*values at time t */
oldval [ MAXPOINTS +2], /*values at time (t - dt ) */
newval [ MAXPOINTS +2]; /*values at time ( t + dt ) */
float *d_values, *d_oldval, *d_newval;
/* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
* Checks input values from parameters
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
void check_param ( void )
{
char tchar [20];
/* check number of points , number of iterations */
while (( tpoints < MINPOINTS ) || ( tpoints > MAXPOINTS ) ) {
printf ( "Enter number of points along vibrating string [%d-%d]: "
, MINPOINTS , MAXPOINTS ) ;
scanf ( "%s" , tchar ) ;
tpoints = atoi ( tchar ) ;
if (( tpoints < MINPOINTS ) || ( tpoints > MAXPOINTS ) )
printf ( "Invalid. Please enter value between %d and %d\n" ,
MINPOINTS , MAXPOINTS ) ;
}
while (( nsteps < 1) || ( nsteps > MAXSTEPS ) ) {
printf ( "Enter number of time steps [1-%d]: " , MAXSTEPS ) ;
scanf ( "%s" , tchar ) ;
nsteps = atoi ( tchar ) ;
if (( nsteps < 1) || ( nsteps > MAXSTEPS ) )
printf ( "Invalid. Please enter value between 1 and %d\n" ,
MAXSTEPS ) ;
}
printf ( "Using points = %d, steps = %d\n", tpoints, nsteps) ;
}
/* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
* Initialize points on line
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
__global__ void init_line (float* values_d, float* oldvalue_d, int tpoints)
{
int idx = blockIdx.x * blockDim.x + threadIdx.x;
int stride = blockDim.x * gridDim.x;
float fac = 2.0 * PI;
float x;
for ( int i = idx; i <= tpoints; i+=stride) {
x = (float)(i-1)/(tpoints-1); //might loss some precision.
values_d[i] = __sinf(fac * x);
oldvalue_d [i] = values_d[i];
}
}
/* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
* Calculate new values using wave equation
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
/* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
* Update all values along line a specified number of times
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
__global__ void update(float* values_d, float* oldvalue_d, int tpoints, int nsteps)
{
int i, j;
int index = blockIdx.x * blockDim.x + threadIdx.x;
int stride = gridDim.x * blockDim.x;
float newval;
/* Update values for each time step */
for ( i = 1; i <= nsteps ; i++) {
/* Update points along line for this time step */
for ( j = index; j <= tpoints; j+=stride) {
if (( j == 1) || ( j == tpoints ) )
newval = 0.0;
else
newval = (1.82)*values_d[j] - oldvalue_d[j];
oldvalue_d [ j ] = values_d [ j ]; /* Update old values with new values */
values_d [ j ] = newval;
}
}
}
/* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
* Print final results
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
void printfinal()
{
int i ;
for( i = 1; i <= tpoints ; i ++){
printf("%6.4f ", values[i]);
if( i %10 == 0)
printf("\n");
}
}
/* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
* Main program
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
int main (int argc, char *argv[])
{
sscanf (argv[1],"%d" ,&tpoints);
sscanf (argv[2],"%d" ,&nsteps);
int numBlock = (tpoints+1+BLOCK_SIZE)/BLOCK_SIZE;
cudaMalloc(&d_values, (MAXPOINTS+2) * sizeof(float));
cudaMalloc(&d_oldval, (MAXPOINTS+2) * sizeof(float));
check_param();
printf("Initializing points on the line...\n");
init_line<<<numBlock, BLOCK_SIZE>>>(d_values, d_oldval, tpoints);
cudaMemcpy(values, d_values, (MAXPOINTS+2) * sizeof(float), cudaMemcpyDeviceToHost);
for(int i = 1; i<=tpoints; i++){
printf("%f\n", *(values+i));
}
printf("Updating all points for all time steps...\n");
update<<<numBlock, BLOCK_SIZE>>>(d_values, d_oldval, tpoints, nsteps);
printf("Printing final results...\n");
cudaMemcpy(values, d_values, (MAXPOINTS+2) * sizeof(float), cudaMemcpyDeviceToHost);
printfinal();
printf("\nDone.\n\n");
return 0;
} | code for sm_80
Function : _Z6updatePfS_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ HFMA2.MMA R2, -RZ, RZ, 0, 5.9604644775390625e-08 ; /* 0x00000001ff027435 */
/* 0x000fe200000001ff */
/*0020*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0030*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e6a0000002100 */
/*0040*/ ISETP.LE.AND P0, PT, R2, c[0x0][0x174], PT ; /* 0x00005d0002007a0c */
/* 0x000fda0003f03270 */
/*0050*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0060*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x003fe200078e0203 */
/*0070*/ UMOV UR4, 0x1 ; /* 0x0000000100047882 */
/* 0x000fe40000000000 */
/*0080*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe40000000a00 */
/*0090*/ ISETP.GT.AND P0, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x000fe20003f04270 */
/*00a0*/ IMAD.U32 R2, RZ, RZ, UR4 ; /* 0x00000004ff027e24 */
/* 0x000fe2000f8e00ff */
/*00b0*/ UIADD3 UR4, UR4, 0x1, URZ ; /* 0x0000000104047890 */
/* 0x000fe2000fffe03f */
/*00c0*/ BSSY B0, 0x230 ; /* 0x0000016000007945 */
/* 0x000fe60003800000 */
/*00d0*/ ISETP.GE.AND P1, PT, R2, c[0x0][0x174], PT ; /* 0x00005d0002007a0c */
/* 0x000fce0003f26270 */
/*00e0*/ @P0 BRA 0x220 ; /* 0x0000013000000947 */
/* 0x001fea0003800000 */
/*00f0*/ MOV R10, R0 ; /* 0x00000000000a7202 */
/* 0x000fc80000000f00 */
/*0100*/ ISETP.NE.AND P0, PT, R10, c[0x0][0x170], PT ; /* 0x00005c000a007a0c */
/* 0x000fe20003f05270 */
/*0110*/ IMAD.MOV.U32 R9, RZ, RZ, 0x4 ; /* 0x00000004ff097424 */
/* 0x001fc600078e00ff */
/*0120*/ ISETP.EQ.OR P0, PT, R10.reuse, 0x1, !P0 ; /* 0x000000010a00780c */
/* 0x040fe20004702670 */
/*0130*/ IMAD.WIDE R6, R10, R9, c[0x0][0x160] ; /* 0x000058000a067625 */
/* 0x000fc800078e0209 */
/*0140*/ IMAD.WIDE R8, R10, R9, c[0x0][0x168] ; /* 0x00005a000a087625 */
/* 0x000fe200078e0209 */
/*0150*/ LDG.E R13, [R6.64] ; /* 0x00000006060d7981 */
/* 0x000eae000c1e1900 */
/*0160*/ @!P0 LDG.E R4, [R8.64] ; /* 0x0000000608048981 */
/* 0x000ee2000c1e1900 */
/*0170*/ IMAD.MOV.U32 R11, RZ, RZ, c[0x0][0xc] ; /* 0x00000300ff0b7624 */
/* 0x000fc800078e00ff */
/*0180*/ IMAD R10, R11, c[0x0][0x0], R10 ; /* 0x000000000b0a7a24 */
/* 0x000fe200078e020a */
/*0190*/ @!P0 F2F.F64.F32 R2, R13 ; /* 0x0000000d00028310 */
/* 0x004fe20000201800 */
/*01a0*/ STG.E [R8.64], R13 ; /* 0x0000000d08007986 */
/* 0x0001ee000c101906 */
/*01b0*/ @!P0 F2F.F64.F32 R4, R4 ; /* 0x0000000400048310 */
/* 0x008e640000201800 */
/*01c0*/ @!P0 DFMA R2, R2, c[0x2][0x0], -R4 ; /* 0x0080000002028a2b */
/* 0x002e4c0000000804 */
/*01d0*/ @!P0 F2F.F32.F64 R5, R2 ; /* 0x0000000200058310 */
/* 0x002e620000301000 */
/*01e0*/ @P0 MOV R5, RZ ; /* 0x000000ff00050202 */
/* 0x000fe40000000f00 */
/*01f0*/ ISETP.GT.AND P0, PT, R10, c[0x0][0x170], PT ; /* 0x00005c000a007a0c */
/* 0x000fc60003f04270 */
/*0200*/ STG.E [R6.64], R5 ; /* 0x0000000506007986 */
/* 0x0021f4000c101906 */
/*0210*/ @!P0 BRA 0x100 ; /* 0xfffffee000008947 */
/* 0x000fea000383ffff */
/*0220*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0230*/ @!P1 BRA 0x90 ; /* 0xfffffe5000009947 */
/* 0x000fea000383ffff */
/*0240*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0250*/ BRA 0x250; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z9init_linePfS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R2, R2, c[0x0][0x0], R3 ; /* 0x0000000002027a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GT.AND P0, PT, R2, c[0x0][0x170], PT ; /* 0x00005c0002007a0c */
/* 0x000fda0003f04270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ ULDC UR4, c[0x0][0x170] ; /* 0x00005c0000047ab9 */
/* 0x000fe40000000800 */
/*0070*/ UIADD3 UR4, UR4, -0x1, URZ ; /* 0xffffffff04047890 */
/* 0x000fd2000fffe03f */
/*0080*/ I2F R0, UR4 ; /* 0x0000000400007d06 */
/* 0x000e220008201400 */
/*0090*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fca0000000a00 */
/*00a0*/ IADD3 R3, R2, -0x1, RZ ; /* 0xffffffff02037810 */
/* 0x001fe20007ffe0ff */
/*00b0*/ MUFU.RCP R5, R0 ; /* 0x0000000000057308 */
/* 0x001e220000001000 */
/*00c0*/ BSSY B0, 0x190 ; /* 0x000000c000007945 */
/* 0x000fee0003800000 */
/*00d0*/ I2F R9, R3 ; /* 0x0000000300097306 */
/* 0x000e620000201400 */
/*00e0*/ FFMA R4, -R0, R5, 1 ; /* 0x3f80000000047423 */
/* 0x001fc80000000105 */
/*00f0*/ FFMA R4, R5, R4, R5 ; /* 0x0000000405047223 */
/* 0x000fc60000000005 */
/*0100*/ FCHK P0, R9, R0 ; /* 0x0000000009007302 */
/* 0x002e220000000000 */
/*0110*/ FFMA R5, R9, R4, RZ ; /* 0x0000000409057223 */
/* 0x000fc800000000ff */
/*0120*/ FFMA R6, -R0, R5, R9 ; /* 0x0000000500067223 */
/* 0x000fc80000000109 */
/*0130*/ FFMA R4, R4, R6, R5 ; /* 0x0000000604047223 */
/* 0x000fe20000000005 */
/*0140*/ @!P0 BRA 0x180 ; /* 0x0000003000008947 */
/* 0x001fea0003800000 */
/*0150*/ MOV R4, 0x170 ; /* 0x0000017000047802 */
/* 0x000fe40000000f00 */
/*0160*/ CALL.REL.NOINC 0x260 ; /* 0x000000f000007944 */
/* 0x000fea0003c00000 */
/*0170*/ IMAD.MOV.U32 R4, RZ, RZ, R3 ; /* 0x000000ffff047224 */
/* 0x001fe400078e0003 */
/*0180*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0190*/ FMUL R4, R4, 6.2831854820251464844 ; /* 0x40c90fdb04047820 */
/* 0x000fe40000400000 */
/*01a0*/ IMAD.MOV.U32 R7, RZ, RZ, 0x4 ; /* 0x00000004ff077424 */
/* 0x000fe400078e00ff */
/*01b0*/ FMUL.RZ R3, R4, 0.15915493667125701904 ; /* 0x3e22f98304037820 */
/* 0x000fe4000040c000 */
/*01c0*/ IMAD.WIDE R4, R2, R7, c[0x0][0x160] ; /* 0x0000580002047625 */
/* 0x000fc800078e0207 */
/*01d0*/ MUFU.SIN R3, R3 ; /* 0x0000000300037308 */
/* 0x000e220000000400 */
/*01e0*/ IMAD.WIDE R6, R2, R7, c[0x0][0x168] ; /* 0x00005a0002067625 */
/* 0x000fc800078e0207 */
/*01f0*/ IMAD.MOV.U32 R9, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff097624 */
/* 0x000fc800078e00ff */
/*0200*/ IMAD R2, R9, c[0x0][0xc], R2 ; /* 0x0000030009027a24 */
/* 0x000fca00078e0202 */
/*0210*/ ISETP.GT.AND P0, PT, R2, c[0x0][0x170], PT ; /* 0x00005c0002007a0c */
/* 0x000fe20003f04270 */
/*0220*/ STG.E [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x0011e8000c101904 */
/*0230*/ STG.E [R6.64], R3 ; /* 0x0000000306007986 */
/* 0x0001f0000c101904 */
/*0240*/ @!P0 BRA 0xa0 ; /* 0xfffffe5000008947 */
/* 0x000fea000383ffff */
/*0250*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0260*/ SHF.R.U32.HI R5, RZ, 0x17, R0.reuse ; /* 0x00000017ff057819 */
/* 0x100fe20000011600 */
/*0270*/ BSSY B1, 0x8d0 ; /* 0x0000065000017945 */
/* 0x000fe20003800000 */
/*0280*/ SHF.R.U32.HI R3, RZ, 0x17, R9.reuse ; /* 0x00000017ff037819 */
/* 0x100fe20000011609 */
/*0290*/ IMAD.MOV.U32 R6, RZ, RZ, R9 ; /* 0x000000ffff067224 */
/* 0x000fe200078e0009 */
/*02a0*/ LOP3.LUT R5, R5, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff05057812 */
/* 0x000fe200078ec0ff */
/*02b0*/ IMAD.MOV.U32 R7, RZ, RZ, R0 ; /* 0x000000ffff077224 */
/* 0x000fe200078e0000 */
/*02c0*/ LOP3.LUT R11, R3, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff030b7812 */
/* 0x000fc400078ec0ff */
/*02d0*/ IADD3 R10, R5, -0x1, RZ ; /* 0xffffffff050a7810 */
/* 0x000fe40007ffe0ff */
/*02e0*/ IADD3 R12, R11, -0x1, RZ ; /* 0xffffffff0b0c7810 */
/* 0x000fe40007ffe0ff */
/*02f0*/ ISETP.GT.U32.AND P0, PT, R10, 0xfd, PT ; /* 0x000000fd0a00780c */
/* 0x000fc80003f04070 */
/*0300*/ ISETP.GT.U32.OR P0, PT, R12, 0xfd, P0 ; /* 0x000000fd0c00780c */
/* 0x000fda0000704470 */
/*0310*/ @!P0 IMAD.MOV.U32 R8, RZ, RZ, RZ ; /* 0x000000ffff088224 */
/* 0x000fe200078e00ff */
/*0320*/ @!P0 BRA 0x4b0 ; /* 0x0000018000008947 */
/* 0x000fea0003800000 */
/*0330*/ FSETP.GTU.FTZ.AND P1, PT, |R0|, +INF , PT ; /* 0x7f8000000000780b */
/* 0x000fe20003f3c200 */
/*0340*/ IMAD.MOV.U32 R3, RZ, RZ, R9 ; /* 0x000000ffff037224 */
/* 0x000fe200078e0009 */
/*0350*/ FSETP.GTU.FTZ.AND P0, PT, |R9|, +INF , PT ; /* 0x7f8000000900780b */
/* 0x000fc80003f1c200 */
/*0360*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000703570 */
/*0370*/ @P0 BRA 0x8b0 ; /* 0x0000053000000947 */
/* 0x000fea0003800000 */
/*0380*/ LOP3.LUT P0, RZ, R7, 0x7fffffff, R6, 0xc8, !PT ; /* 0x7fffffff07ff7812 */
/* 0x000fda000780c806 */
/*0390*/ @!P0 BRA 0x890 ; /* 0x000004f000008947 */
/* 0x000fea0003800000 */
/*03a0*/ FSETP.NEU.FTZ.AND P2, PT, |R3|.reuse, +INF , PT ; /* 0x7f8000000300780b */
/* 0x040fe40003f5d200 */
/*03b0*/ FSETP.NEU.FTZ.AND P1, PT, |R0|, +INF , PT ; /* 0x7f8000000000780b */
/* 0x000fe40003f3d200 */
/*03c0*/ FSETP.NEU.FTZ.AND P0, PT, |R3|, +INF , PT ; /* 0x7f8000000300780b */
/* 0x000fd60003f1d200 */
/*03d0*/ @!P1 BRA !P2, 0x890 ; /* 0x000004b000009947 */
/* 0x000fea0005000000 */
/*03e0*/ LOP3.LUT P2, RZ, R6, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff06ff7812 */
/* 0x000fc8000784c0ff */
/*03f0*/ PLOP3.LUT P1, PT, P1, P2, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000f24572 */
/*0400*/ @P1 BRA 0x870 ; /* 0x0000046000001947 */
/* 0x000fea0003800000 */
/*0410*/ LOP3.LUT P1, RZ, R7, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff07ff7812 */
/* 0x000fc8000782c0ff */
/*0420*/ PLOP3.LUT P0, PT, P0, P1, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000702572 */
/*0430*/ @P0 BRA 0x840 ; /* 0x0000040000000947 */
/* 0x000fea0003800000 */
/*0440*/ ISETP.GE.AND P0, PT, R12, RZ, PT ; /* 0x000000ff0c00720c */
/* 0x000fe40003f06270 */
/*0450*/ ISETP.GE.AND P1, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fd60003f26270 */
/*0460*/ @P0 IMAD.MOV.U32 R8, RZ, RZ, RZ ; /* 0x000000ffff080224 */
/* 0x000fe400078e00ff */
/*0470*/ @!P0 IMAD.MOV.U32 R8, RZ, RZ, -0x40 ; /* 0xffffffc0ff088424 */
/* 0x000fe400078e00ff */
/*0480*/ @!P0 FFMA R6, R3, 1.84467440737095516160e+19, RZ ; /* 0x5f80000003068823 */
/* 0x000fe400000000ff */
/*0490*/ @!P1 FFMA R7, R0, 1.84467440737095516160e+19, RZ ; /* 0x5f80000000079823 */
/* 0x000fe200000000ff */
/*04a0*/ @!P1 IADD3 R8, R8, 0x40, RZ ; /* 0x0000004008089810 */
/* 0x000fe40007ffe0ff */
/*04b0*/ LEA R10, R5, 0xc0800000, 0x17 ; /* 0xc0800000050a7811 */
/* 0x000fe200078eb8ff */
/*04c0*/ BSSY B2, 0x830 ; /* 0x0000036000027945 */
/* 0x000fe80003800000 */
/*04d0*/ IMAD.IADD R10, R7, 0x1, -R10 ; /* 0x00000001070a7824 */
/* 0x000fe200078e0a0a */
/*04e0*/ IADD3 R7, R11, -0x7f, RZ ; /* 0xffffff810b077810 */
/* 0x000fc60007ffe0ff */
/*04f0*/ MUFU.RCP R3, R10 ; /* 0x0000000a00037308 */
/* 0x000e220000001000 */
/*0500*/ FADD.FTZ R9, -R10, -RZ ; /* 0x800000ff0a097221 */
/* 0x000fe40000010100 */
/*0510*/ IMAD R6, R7.reuse, -0x800000, R6 ; /* 0xff80000007067824 */
/* 0x040fe200078e0206 */
/*0520*/ IADD3 R7, R7, 0x7f, -R5 ; /* 0x0000007f07077810 */
/* 0x000fca0007ffe805 */
/*0530*/ IMAD.IADD R8, R7, 0x1, R8 ; /* 0x0000000107087824 */
/* 0x000fe400078e0208 */
/*0540*/ FFMA R12, R3, R9, 1 ; /* 0x3f800000030c7423 */
/* 0x001fc80000000009 */
/*0550*/ FFMA R11, R3, R12, R3 ; /* 0x0000000c030b7223 */
/* 0x000fc80000000003 */
/*0560*/ FFMA R3, R6, R11, RZ ; /* 0x0000000b06037223 */
/* 0x000fc800000000ff */
/*0570*/ FFMA R12, R9, R3, R6 ; /* 0x00000003090c7223 */
/* 0x000fc80000000006 */
/*0580*/ FFMA R12, R11, R12, R3 ; /* 0x0000000c0b0c7223 */
/* 0x000fc80000000003 */
/*0590*/ FFMA R6, R9, R12, R6 ; /* 0x0000000c09067223 */
/* 0x000fc80000000006 */
/*05a0*/ FFMA R3, R11, R6, R12 ; /* 0x000000060b037223 */
/* 0x000fca000000000c */
/*05b0*/ SHF.R.U32.HI R5, RZ, 0x17, R3 ; /* 0x00000017ff057819 */
/* 0x000fc80000011603 */
/*05c0*/ LOP3.LUT R5, R5, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff05057812 */
/* 0x000fca00078ec0ff */
/*05d0*/ IMAD.IADD R9, R5, 0x1, R8 ; /* 0x0000000105097824 */
/* 0x000fca00078e0208 */
/*05e0*/ IADD3 R5, R9, -0x1, RZ ; /* 0xffffffff09057810 */
/* 0x000fc80007ffe0ff */
/*05f0*/ ISETP.GE.U32.AND P0, PT, R5, 0xfe, PT ; /* 0x000000fe0500780c */
/* 0x000fda0003f06070 */
/*0600*/ @!P0 BRA 0x810 ; /* 0x0000020000008947 */
/* 0x000fea0003800000 */
/*0610*/ ISETP.GT.AND P0, PT, R9, 0xfe, PT ; /* 0x000000fe0900780c */
/* 0x000fda0003f04270 */
/*0620*/ @P0 BRA 0x7e0 ; /* 0x000001b000000947 */
/* 0x000fea0003800000 */
/*0630*/ ISETP.GE.AND P0, PT, R9, 0x1, PT ; /* 0x000000010900780c */
/* 0x000fda0003f06270 */
/*0640*/ @P0 BRA 0x820 ; /* 0x000001d000000947 */
/* 0x000fea0003800000 */
/*0650*/ ISETP.GE.AND P0, PT, R9, -0x18, PT ; /* 0xffffffe80900780c */
/* 0x000fe40003f06270 */
/*0660*/ LOP3.LUT R3, R3, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000003037812 */
/* 0x000fd600078ec0ff */
/*0670*/ @!P0 BRA 0x820 ; /* 0x000001a000008947 */
/* 0x000fea0003800000 */
/*0680*/ FFMA.RZ R5, R11, R6.reuse, R12.reuse ; /* 0x000000060b057223 */
/* 0x180fe2000000c00c */
/*0690*/ IADD3 R8, R9.reuse, 0x20, RZ ; /* 0x0000002009087810 */
/* 0x040fe40007ffe0ff */
/*06a0*/ ISETP.NE.AND P2, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x000fe40003f45270 */
/*06b0*/ LOP3.LUT R7, R5, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff05077812 */
/* 0x000fe200078ec0ff */
/*06c0*/ FFMA.RP R5, R11, R6.reuse, R12.reuse ; /* 0x000000060b057223 */
/* 0x180fe2000000800c */
/*06d0*/ ISETP.NE.AND P1, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x000fe20003f25270 */
/*06e0*/ FFMA.RM R6, R11, R6, R12 ; /* 0x000000060b067223 */
/* 0x000fe2000000400c */
/*06f0*/ LOP3.LUT R7, R7, 0x800000, RZ, 0xfc, !PT ; /* 0x0080000007077812 */
/* 0x000fe200078efcff */
/*0700*/ IMAD.MOV R9, RZ, RZ, -R9 ; /* 0x000000ffff097224 */
/* 0x000fc600078e0a09 */
/*0710*/ SHF.L.U32 R8, R7, R8, RZ ; /* 0x0000000807087219 */
/* 0x000fe400000006ff */
/*0720*/ FSETP.NEU.FTZ.AND P0, PT, R5, R6, PT ; /* 0x000000060500720b */
/* 0x000fe40003f1d000 */
/*0730*/ SEL R6, R9, RZ, P2 ; /* 0x000000ff09067207 */
/* 0x000fe40001000000 */
/*0740*/ ISETP.NE.AND P1, PT, R8, RZ, P1 ; /* 0x000000ff0800720c */
/* 0x000fe40000f25270 */
/*0750*/ SHF.R.U32.HI R6, RZ, R6, R7 ; /* 0x00000006ff067219 */
/* 0x000fe40000011607 */
/*0760*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc40000703570 */
/*0770*/ SHF.R.U32.HI R8, RZ, 0x1, R6 ; /* 0x00000001ff087819 */
/* 0x000fe40000011606 */
/*0780*/ SEL R5, RZ, 0x1, !P0 ; /* 0x00000001ff057807 */
/* 0x000fc80004000000 */
/*0790*/ LOP3.LUT R5, R5, 0x1, R8, 0xf8, !PT ; /* 0x0000000105057812 */
/* 0x000fc800078ef808 */
/*07a0*/ LOP3.LUT R5, R5, R6, RZ, 0xc0, !PT ; /* 0x0000000605057212 */
/* 0x000fca00078ec0ff */
/*07b0*/ IMAD.IADD R8, R8, 0x1, R5 ; /* 0x0000000108087824 */
/* 0x000fca00078e0205 */
/*07c0*/ LOP3.LUT R3, R8, R3, RZ, 0xfc, !PT ; /* 0x0000000308037212 */
/* 0x000fe200078efcff */
/*07d0*/ BRA 0x820 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*07e0*/ LOP3.LUT R3, R3, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000003037812 */
/* 0x000fc800078ec0ff */
/*07f0*/ LOP3.LUT R3, R3, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000003037812 */
/* 0x000fe200078efcff */
/*0800*/ BRA 0x820 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0810*/ IMAD R3, R8, 0x800000, R3 ; /* 0x0080000008037824 */
/* 0x000fe400078e0203 */
/*0820*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*0830*/ BRA 0x8c0 ; /* 0x0000008000007947 */
/* 0x000fea0003800000 */
/*0840*/ LOP3.LUT R3, R7, 0x80000000, R6, 0x48, !PT ; /* 0x8000000007037812 */
/* 0x000fc800078e4806 */
/*0850*/ LOP3.LUT R3, R3, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000003037812 */
/* 0x000fe200078efcff */
/*0860*/ BRA 0x8c0 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*0870*/ LOP3.LUT R3, R7, 0x80000000, R6, 0x48, !PT ; /* 0x8000000007037812 */
/* 0x000fe200078e4806 */
/*0880*/ BRA 0x8c0 ; /* 0x0000003000007947 */
/* 0x000fea0003800000 */
/*0890*/ MUFU.RSQ R3, -QNAN ; /* 0xffc0000000037908 */
/* 0x000e220000001400 */
/*08a0*/ BRA 0x8c0 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*08b0*/ FADD.FTZ R3, R3, R0 ; /* 0x0000000003037221 */
/* 0x000fe40000010000 */
/*08c0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*08d0*/ IMAD.MOV.U32 R5, RZ, RZ, 0x0 ; /* 0x00000000ff057424 */
/* 0x000fc800078e00ff */
/*08e0*/ RET.REL.NODEC R4 0x0 ; /* 0xfffff71004007950 */
/* 0x000fea0003c3ffff */
/*08f0*/ BRA 0x8f0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0900*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0910*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0920*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0930*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0940*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0950*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0960*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0970*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
* DESCRIPTION :
*
Serial Concurrent Wave Equation - C Version
*
This program implements the concurrent wave equation
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
# include <stdio.h>
# include <stdlib.h>
# include <math.h>
# include <time.h>
# include <cuda_runtime.h>
# define MAXPOINTS 1000000
# define MAXSTEPS 1000000
# define MINPOINTS 20
# define PI 3.14159265
# define DIM_GRID 1
# define BLOCK_SIZE 256
void check_param ( void ) ;
void init_line ( void ) ;
void update ( void ) ;
void printfinal ( void ) ;
int nsteps , /*number of time steps */
tpoints , /*total points along string */
rcode ; /*generic return code */
float values [ MAXPOINTS +2], /*values at time t */
oldval [ MAXPOINTS +2], /*values at time (t - dt ) */
newval [ MAXPOINTS +2]; /*values at time ( t + dt ) */
float *d_values, *d_oldval, *d_newval;
/* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
* Checks input values from parameters
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
void check_param ( void )
{
char tchar [20];
/* check number of points , number of iterations */
while (( tpoints < MINPOINTS ) || ( tpoints > MAXPOINTS ) ) {
printf ( "Enter number of points along vibrating string [%d-%d]: "
, MINPOINTS , MAXPOINTS ) ;
scanf ( "%s" , tchar ) ;
tpoints = atoi ( tchar ) ;
if (( tpoints < MINPOINTS ) || ( tpoints > MAXPOINTS ) )
printf ( "Invalid. Please enter value between %d and %d\n" ,
MINPOINTS , MAXPOINTS ) ;
}
while (( nsteps < 1) || ( nsteps > MAXSTEPS ) ) {
printf ( "Enter number of time steps [1-%d]: " , MAXSTEPS ) ;
scanf ( "%s" , tchar ) ;
nsteps = atoi ( tchar ) ;
if (( nsteps < 1) || ( nsteps > MAXSTEPS ) )
printf ( "Invalid. Please enter value between 1 and %d\n" ,
MAXSTEPS ) ;
}
printf ( "Using points = %d, steps = %d\n", tpoints, nsteps) ;
}
/* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
* Initialize points on line
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
__global__ void init_line (float* values_d, float* oldvalue_d, int tpoints)
{
int idx = blockIdx.x * blockDim.x + threadIdx.x;
int stride = blockDim.x * gridDim.x;
float fac = 2.0 * PI;
float x;
for ( int i = idx; i <= tpoints; i+=stride) {
x = (float)(i-1)/(tpoints-1); //might loss some precision.
values_d[i] = __sinf(fac * x);
oldvalue_d [i] = values_d[i];
}
}
/* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
* Calculate new values using wave equation
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
/* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
* Update all values along line a specified number of times
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
__global__ void update(float* values_d, float* oldvalue_d, int tpoints, int nsteps)
{
int i, j;
int index = blockIdx.x * blockDim.x + threadIdx.x;
int stride = gridDim.x * blockDim.x;
float newval;
/* Update values for each time step */
for ( i = 1; i <= nsteps ; i++) {
/* Update points along line for this time step */
for ( j = index; j <= tpoints; j+=stride) {
if (( j == 1) || ( j == tpoints ) )
newval = 0.0;
else
newval = (1.82)*values_d[j] - oldvalue_d[j];
oldvalue_d [ j ] = values_d [ j ]; /* Update old values with new values */
values_d [ j ] = newval;
}
}
}
/* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
* Print final results
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
void printfinal()
{
int i ;
for( i = 1; i <= tpoints ; i ++){
printf("%6.4f ", values[i]);
if( i %10 == 0)
printf("\n");
}
}
/* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
* Main program
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
int main (int argc, char *argv[])
{
sscanf (argv[1],"%d" ,&tpoints);
sscanf (argv[2],"%d" ,&nsteps);
int numBlock = (tpoints+1+BLOCK_SIZE)/BLOCK_SIZE;
cudaMalloc(&d_values, (MAXPOINTS+2) * sizeof(float));
cudaMalloc(&d_oldval, (MAXPOINTS+2) * sizeof(float));
check_param();
printf("Initializing points on the line...\n");
init_line<<<numBlock, BLOCK_SIZE>>>(d_values, d_oldval, tpoints);
cudaMemcpy(values, d_values, (MAXPOINTS+2) * sizeof(float), cudaMemcpyDeviceToHost);
for(int i = 1; i<=tpoints; i++){
printf("%f\n", *(values+i));
}
printf("Updating all points for all time steps...\n");
update<<<numBlock, BLOCK_SIZE>>>(d_values, d_oldval, tpoints, nsteps);
printf("Printing final results...\n");
cudaMemcpy(values, d_values, (MAXPOINTS+2) * sizeof(float), cudaMemcpyDeviceToHost);
printfinal();
printf("\nDone.\n\n");
return 0;
} | .file "tmpxft_00128a74_00000000-6_0856148.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "Enter number of points along vibrating string [%d-%d]: "
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "%s"
.section .rodata.str1.8
.align 8
.LC2:
.string "Invalid. Please enter value between %d and %d\n"
.align 8
.LC3:
.string "Enter number of time steps [1-%d]: "
.align 8
.LC4:
.string "Invalid. Please enter value between 1 and %d\n"
.align 8
.LC5:
.string "Using points = %d, steps = %d\n"
.text
.globl _Z11check_paramv
.type _Z11check_paramv, @function
_Z11check_paramv:
.LFB2057:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $32, %rsp
.cfi_def_cfa_offset 64
movq %fs:40, %rax
movq %rax, 24(%rsp)
xorl %eax, %eax
leaq .LC0(%rip), %r12
movq %rsp, %rbx
leaq .LC1(%rip), %rbp
.L5:
movl tpoints(%rip), %eax
subl $20, %eax
cmpl $999980, %eax
jbe .L14
movl $1000000, %ecx
movl $20, %edx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rbx, %rsi
movq %rbp, %rdi
movl $0, %eax
call __isoc23_scanf@PLT
movl $10, %edx
movl $0, %esi
movq %rbx, %rdi
call __isoc23_strtol@PLT
movl %eax, tpoints(%rip)
subl $20, %eax
cmpl $999980, %eax
jbe .L5
movl $1000000, %ecx
movl $20, %edx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L5
.L14:
leaq .LC3(%rip), %r12
movq %rsp, %rbx
leaq .LC1(%rip), %rbp
.L8:
movl nsteps(%rip), %ecx
leal -1(%rcx), %eax
cmpl $999999, %eax
jbe .L15
movl $1000000, %edx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rbx, %rsi
movq %rbp, %rdi
movl $0, %eax
call __isoc23_scanf@PLT
movl $10, %edx
movl $0, %esi
movq %rbx, %rdi
call __isoc23_strtol@PLT
movl %eax, nsteps(%rip)
subl $1, %eax
cmpl $999999, %eax
jbe .L8
movl $1000000, %edx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L8
.L15:
movl tpoints(%rip), %edx
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 24(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $32, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L16:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size _Z11check_paramv, .-_Z11check_paramv
.section .rodata.str1.1
.LC6:
.string "%6.4f "
.LC7:
.string "\n"
.text
.globl _Z10printfinalv
.type _Z10printfinalv, @function
_Z10printfinalv:
.LFB2058:
.cfi_startproc
endbr64
cmpl $0, tpoints(%rip)
jle .L23
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $8, %rsp
.cfi_def_cfa_offset 48
movl $1, %ebx
leaq values(%rip), %r12
leaq .LC6(%rip), %rbp
leaq .LC7(%rip), %r13
jmp .L20
.L19:
addq $1, %rbx
cmpl %ebx, tpoints(%rip)
jl .L26
.L20:
pxor %xmm0, %xmm0
cvtss2sd (%r12,%rbx,4), %xmm0
movq %rbp, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movslq %ebx, %rax
imulq $1717986919, %rax, %rax
sarq $34, %rax
movl %ebx, %edx
sarl $31, %edx
subl %edx, %eax
leal (%rax,%rax,4), %eax
addl %eax, %eax
cmpl %ebx, %eax
jne .L19
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L19
.L26:
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore 3
.cfi_restore 6
.cfi_restore 12
.cfi_restore 13
ret
.cfi_endproc
.LFE2058:
.size _Z10printfinalv, .-_Z10printfinalv
.globl _Z31__device_stub__Z9init_linePfS_iPfS_i
.type _Z31__device_stub__Z9init_linePfS_iPfS_i, @function
_Z31__device_stub__Z9init_linePfS_iPfS_i:
.LFB2084:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L31
.L27:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L32
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L31:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9init_linePfS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L27
.L32:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z31__device_stub__Z9init_linePfS_iPfS_i, .-_Z31__device_stub__Z9init_linePfS_iPfS_i
.globl _Z9init_linePfS_i
.type _Z9init_linePfS_i, @function
_Z9init_linePfS_i:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z9init_linePfS_iPfS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z9init_linePfS_i, .-_Z9init_linePfS_i
.globl _Z29__device_stub__Z6updatePfS_iiPfS_ii
.type _Z29__device_stub__Z6updatePfS_iiPfS_ii, @function
_Z29__device_stub__Z6updatePfS_iiPfS_ii:
.LFB2086:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L39
.L35:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L40
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L39:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6updatePfS_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L35
.L40:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2086:
.size _Z29__device_stub__Z6updatePfS_iiPfS_ii, .-_Z29__device_stub__Z6updatePfS_iiPfS_ii
.globl _Z6updatePfS_ii
.type _Z6updatePfS_ii, @function
_Z6updatePfS_ii:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z6updatePfS_iiPfS_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _Z6updatePfS_ii, .-_Z6updatePfS_ii
.section .rodata.str1.1
.LC8:
.string "%d"
.section .rodata.str1.8
.align 8
.LC9:
.string "Initializing points on the line...\n"
.section .rodata.str1.1
.LC10:
.string "%f\n"
.section .rodata.str1.8
.align 8
.LC11:
.string "Updating all points for all time steps...\n"
.section .rodata.str1.1
.LC12:
.string "Printing final results...\n"
.LC13:
.string "\nDone.\n\n"
.text
.globl main
.type main, @function
main:
.LFB2059:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $40, %rsp
.cfi_def_cfa_offset 80
movq %rsi, %rbx
movq 8(%rsi), %rdi
leaq tpoints(%rip), %rdx
leaq .LC8(%rip), %rbp
movq %rbp, %rsi
movl $0, %eax
call __isoc23_sscanf@PLT
movq 16(%rbx), %rdi
leaq nsteps(%rip), %rdx
movq %rbp, %rsi
movl $0, %eax
call __isoc23_sscanf@PLT
movl tpoints(%rip), %eax
leal 512(%rax), %r13d
addl $257, %eax
cmovns %eax, %r13d
sarl $8, %r13d
movl $4000008, %esi
leaq d_values(%rip), %rdi
call cudaMalloc@PLT
movl $4000008, %esi
leaq d_oldval(%rip), %rdi
call cudaMalloc@PLT
call _Z11check_paramv
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $256, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl %r13d, 8(%rsp)
movl $1, 12(%rsp)
movl $1, 16(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L50
.L44:
movl $2, %ecx
movl $4000008, %edx
movq d_values(%rip), %rsi
leaq values(%rip), %rdi
call cudaMemcpy@PLT
cmpl $0, tpoints(%rip)
jle .L45
movl $1, %ebx
leaq values(%rip), %r12
leaq .LC10(%rip), %rbp
.L46:
pxor %xmm0, %xmm0
cvtss2sd (%r12,%rbx,4), %xmm0
movq %rbp, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpl %ebx, tpoints(%rip)
jge .L46
.L45:
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $256, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl %r13d, 8(%rsp)
movl $1, 12(%rsp)
movl $1, 16(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L51
.L47:
leaq .LC12(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $2, %ecx
movl $4000008, %edx
movq d_values(%rip), %rsi
leaq values(%rip), %rdi
call cudaMemcpy@PLT
call _Z10printfinalv
leaq .LC13(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L50:
.cfi_restore_state
movl tpoints(%rip), %edx
movq d_oldval(%rip), %rsi
movq d_values(%rip), %rdi
call _Z31__device_stub__Z9init_linePfS_iPfS_i
jmp .L44
.L51:
movl nsteps(%rip), %ecx
movl tpoints(%rip), %edx
movq d_oldval(%rip), %rsi
movq d_values(%rip), %rdi
call _Z29__device_stub__Z6updatePfS_iiPfS_ii
jmp .L47
.cfi_endproc
.LFE2059:
.size main, .-main
.section .rodata.str1.1
.LC14:
.string "_Z6updatePfS_ii"
.LC15:
.string "_Z9init_linePfS_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2089:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC14(%rip), %rdx
movq %rdx, %rcx
leaq _Z6updatePfS_ii(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC15(%rip), %rdx
movq %rdx, %rcx
leaq _Z9init_linePfS_i(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2089:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl d_newval
.bss
.align 8
.type d_newval, @object
.size d_newval, 8
d_newval:
.zero 8
.globl d_oldval
.align 8
.type d_oldval, @object
.size d_oldval, 8
d_oldval:
.zero 8
.globl d_values
.align 8
.type d_values, @object
.size d_values, 8
d_values:
.zero 8
.globl newval
.align 32
.type newval, @object
.size newval, 4000008
newval:
.zero 4000008
.globl oldval
.align 32
.type oldval, @object
.size oldval, 4000008
oldval:
.zero 4000008
.globl values
.align 32
.type values, @object
.size values, 4000008
values:
.zero 4000008
.globl rcode
.align 4
.type rcode, @object
.size rcode, 4
rcode:
.zero 4
.globl tpoints
.align 4
.type tpoints, @object
.size tpoints, 4
tpoints:
.zero 4
.globl nsteps
.align 4
.type nsteps, @object
.size nsteps, 4
nsteps:
.zero 4
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
* DESCRIPTION :
*
Serial Concurrent Wave Equation - C Version
*
This program implements the concurrent wave equation
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
# include <stdio.h>
# include <stdlib.h>
# include <math.h>
# include <time.h>
# include <cuda_runtime.h>
# define MAXPOINTS 1000000
# define MAXSTEPS 1000000
# define MINPOINTS 20
# define PI 3.14159265
# define DIM_GRID 1
# define BLOCK_SIZE 256
void check_param ( void ) ;
void init_line ( void ) ;
void update ( void ) ;
void printfinal ( void ) ;
int nsteps , /*number of time steps */
tpoints , /*total points along string */
rcode ; /*generic return code */
float values [ MAXPOINTS +2], /*values at time t */
oldval [ MAXPOINTS +2], /*values at time (t - dt ) */
newval [ MAXPOINTS +2]; /*values at time ( t + dt ) */
float *d_values, *d_oldval, *d_newval;
/* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
* Checks input values from parameters
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
void check_param ( void )
{
char tchar [20];
/* check number of points , number of iterations */
while (( tpoints < MINPOINTS ) || ( tpoints > MAXPOINTS ) ) {
printf ( "Enter number of points along vibrating string [%d-%d]: "
, MINPOINTS , MAXPOINTS ) ;
scanf ( "%s" , tchar ) ;
tpoints = atoi ( tchar ) ;
if (( tpoints < MINPOINTS ) || ( tpoints > MAXPOINTS ) )
printf ( "Invalid. Please enter value between %d and %d\n" ,
MINPOINTS , MAXPOINTS ) ;
}
while (( nsteps < 1) || ( nsteps > MAXSTEPS ) ) {
printf ( "Enter number of time steps [1-%d]: " , MAXSTEPS ) ;
scanf ( "%s" , tchar ) ;
nsteps = atoi ( tchar ) ;
if (( nsteps < 1) || ( nsteps > MAXSTEPS ) )
printf ( "Invalid. Please enter value between 1 and %d\n" ,
MAXSTEPS ) ;
}
printf ( "Using points = %d, steps = %d\n", tpoints, nsteps) ;
}
/* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
* Initialize points on line
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
__global__ void init_line (float* values_d, float* oldvalue_d, int tpoints)
{
int idx = blockIdx.x * blockDim.x + threadIdx.x;
int stride = blockDim.x * gridDim.x;
float fac = 2.0 * PI;
float x;
for ( int i = idx; i <= tpoints; i+=stride) {
x = (float)(i-1)/(tpoints-1); //might loss some precision.
values_d[i] = __sinf(fac * x);
oldvalue_d [i] = values_d[i];
}
}
/* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
* Calculate new values using wave equation
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
/* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
* Update all values along line a specified number of times
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
__global__ void update(float* values_d, float* oldvalue_d, int tpoints, int nsteps)
{
int i, j;
int index = blockIdx.x * blockDim.x + threadIdx.x;
int stride = gridDim.x * blockDim.x;
float newval;
/* Update values for each time step */
for ( i = 1; i <= nsteps ; i++) {
/* Update points along line for this time step */
for ( j = index; j <= tpoints; j+=stride) {
if (( j == 1) || ( j == tpoints ) )
newval = 0.0;
else
newval = (1.82)*values_d[j] - oldvalue_d[j];
oldvalue_d [ j ] = values_d [ j ]; /* Update old values with new values */
values_d [ j ] = newval;
}
}
}
/* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
* Print final results
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
void printfinal()
{
int i ;
for( i = 1; i <= tpoints ; i ++){
printf("%6.4f ", values[i]);
if( i %10 == 0)
printf("\n");
}
}
/* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
* Main program
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
int main (int argc, char *argv[])
{
sscanf (argv[1],"%d" ,&tpoints);
sscanf (argv[2],"%d" ,&nsteps);
int numBlock = (tpoints+1+BLOCK_SIZE)/BLOCK_SIZE;
cudaMalloc(&d_values, (MAXPOINTS+2) * sizeof(float));
cudaMalloc(&d_oldval, (MAXPOINTS+2) * sizeof(float));
check_param();
printf("Initializing points on the line...\n");
init_line<<<numBlock, BLOCK_SIZE>>>(d_values, d_oldval, tpoints);
cudaMemcpy(values, d_values, (MAXPOINTS+2) * sizeof(float), cudaMemcpyDeviceToHost);
for(int i = 1; i<=tpoints; i++){
printf("%f\n", *(values+i));
}
printf("Updating all points for all time steps...\n");
update<<<numBlock, BLOCK_SIZE>>>(d_values, d_oldval, tpoints, nsteps);
printf("Printing final results...\n");
cudaMemcpy(values, d_values, (MAXPOINTS+2) * sizeof(float), cudaMemcpyDeviceToHost);
printfinal();
printf("\nDone.\n\n");
return 0;
} | /* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
* DESCRIPTION :
*
Serial Concurrent Wave Equation - C Version
*
This program implements the concurrent wave equation
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
# include <stdio.h>
# include <stdlib.h>
# include <math.h>
# include <time.h>
# include <hip/hip_runtime.h>
# define MAXPOINTS 1000000
# define MAXSTEPS 1000000
# define MINPOINTS 20
# define PI 3.14159265
# define DIM_GRID 1
# define BLOCK_SIZE 256
void check_param ( void ) ;
void init_line ( void ) ;
void update ( void ) ;
void printfinal ( void ) ;
int nsteps , /*number of time steps */
tpoints , /*total points along string */
rcode ; /*generic return code */
float values [ MAXPOINTS +2], /*values at time t */
oldval [ MAXPOINTS +2], /*values at time (t - dt ) */
newval [ MAXPOINTS +2]; /*values at time ( t + dt ) */
float *d_values, *d_oldval, *d_newval;
/* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
* Checks input values from parameters
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
void check_param ( void )
{
char tchar [20];
/* check number of points , number of iterations */
while (( tpoints < MINPOINTS ) || ( tpoints > MAXPOINTS ) ) {
printf ( "Enter number of points along vibrating string [%d-%d]: "
, MINPOINTS , MAXPOINTS ) ;
scanf ( "%s" , tchar ) ;
tpoints = atoi ( tchar ) ;
if (( tpoints < MINPOINTS ) || ( tpoints > MAXPOINTS ) )
printf ( "Invalid. Please enter value between %d and %d\n" ,
MINPOINTS , MAXPOINTS ) ;
}
while (( nsteps < 1) || ( nsteps > MAXSTEPS ) ) {
printf ( "Enter number of time steps [1-%d]: " , MAXSTEPS ) ;
scanf ( "%s" , tchar ) ;
nsteps = atoi ( tchar ) ;
if (( nsteps < 1) || ( nsteps > MAXSTEPS ) )
printf ( "Invalid. Please enter value between 1 and %d\n" ,
MAXSTEPS ) ;
}
printf ( "Using points = %d, steps = %d\n", tpoints, nsteps) ;
}
/* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
* Initialize points on line
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
__global__ void init_line (float* values_d, float* oldvalue_d, int tpoints)
{
int idx = blockIdx.x * blockDim.x + threadIdx.x;
int stride = blockDim.x * gridDim.x;
float fac = 2.0 * PI;
float x;
for ( int i = idx; i <= tpoints; i+=stride) {
x = (float)(i-1)/(tpoints-1); //might loss some precision.
values_d[i] = __sinf(fac * x);
oldvalue_d [i] = values_d[i];
}
}
/* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
* Calculate new values using wave equation
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
/* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
* Update all values along line a specified number of times
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
__global__ void update(float* values_d, float* oldvalue_d, int tpoints, int nsteps)
{
int i, j;
int index = blockIdx.x * blockDim.x + threadIdx.x;
int stride = gridDim.x * blockDim.x;
float newval;
/* Update values for each time step */
for ( i = 1; i <= nsteps ; i++) {
/* Update points along line for this time step */
for ( j = index; j <= tpoints; j+=stride) {
if (( j == 1) || ( j == tpoints ) )
newval = 0.0;
else
newval = (1.82)*values_d[j] - oldvalue_d[j];
oldvalue_d [ j ] = values_d [ j ]; /* Update old values with new values */
values_d [ j ] = newval;
}
}
}
/* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
* Print final results
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
void printfinal()
{
int i ;
for( i = 1; i <= tpoints ; i ++){
printf("%6.4f ", values[i]);
if( i %10 == 0)
printf("\n");
}
}
/* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
* Main program
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
int main (int argc, char *argv[])
{
sscanf (argv[1],"%d" ,&tpoints);
sscanf (argv[2],"%d" ,&nsteps);
int numBlock = (tpoints+1+BLOCK_SIZE)/BLOCK_SIZE;
hipMalloc(&d_values, (MAXPOINTS+2) * sizeof(float));
hipMalloc(&d_oldval, (MAXPOINTS+2) * sizeof(float));
check_param();
printf("Initializing points on the line...\n");
init_line<<<numBlock, BLOCK_SIZE>>>(d_values, d_oldval, tpoints);
hipMemcpy(values, d_values, (MAXPOINTS+2) * sizeof(float), hipMemcpyDeviceToHost);
for(int i = 1; i<=tpoints; i++){
printf("%f\n", *(values+i));
}
printf("Updating all points for all time steps...\n");
update<<<numBlock, BLOCK_SIZE>>>(d_values, d_oldval, tpoints, nsteps);
printf("Printing final results...\n");
hipMemcpy(values, d_values, (MAXPOINTS+2) * sizeof(float), hipMemcpyDeviceToHost);
printfinal();
printf("\nDone.\n\n");
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | /* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
* DESCRIPTION :
*
Serial Concurrent Wave Equation - C Version
*
This program implements the concurrent wave equation
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
# include <stdio.h>
# include <stdlib.h>
# include <math.h>
# include <time.h>
# include <hip/hip_runtime.h>
# define MAXPOINTS 1000000
# define MAXSTEPS 1000000
# define MINPOINTS 20
# define PI 3.14159265
# define DIM_GRID 1
# define BLOCK_SIZE 256
void check_param ( void ) ;
void init_line ( void ) ;
void update ( void ) ;
void printfinal ( void ) ;
int nsteps , /*number of time steps */
tpoints , /*total points along string */
rcode ; /*generic return code */
float values [ MAXPOINTS +2], /*values at time t */
oldval [ MAXPOINTS +2], /*values at time (t - dt ) */
newval [ MAXPOINTS +2]; /*values at time ( t + dt ) */
float *d_values, *d_oldval, *d_newval;
/* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
* Checks input values from parameters
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
void check_param ( void )
{
char tchar [20];
/* check number of points , number of iterations */
while (( tpoints < MINPOINTS ) || ( tpoints > MAXPOINTS ) ) {
printf ( "Enter number of points along vibrating string [%d-%d]: "
, MINPOINTS , MAXPOINTS ) ;
scanf ( "%s" , tchar ) ;
tpoints = atoi ( tchar ) ;
if (( tpoints < MINPOINTS ) || ( tpoints > MAXPOINTS ) )
printf ( "Invalid. Please enter value between %d and %d\n" ,
MINPOINTS , MAXPOINTS ) ;
}
while (( nsteps < 1) || ( nsteps > MAXSTEPS ) ) {
printf ( "Enter number of time steps [1-%d]: " , MAXSTEPS ) ;
scanf ( "%s" , tchar ) ;
nsteps = atoi ( tchar ) ;
if (( nsteps < 1) || ( nsteps > MAXSTEPS ) )
printf ( "Invalid. Please enter value between 1 and %d\n" ,
MAXSTEPS ) ;
}
printf ( "Using points = %d, steps = %d\n", tpoints, nsteps) ;
}
/* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
* Initialize points on line
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
__global__ void init_line (float* values_d, float* oldvalue_d, int tpoints)
{
int idx = blockIdx.x * blockDim.x + threadIdx.x;
int stride = blockDim.x * gridDim.x;
float fac = 2.0 * PI;
float x;
for ( int i = idx; i <= tpoints; i+=stride) {
x = (float)(i-1)/(tpoints-1); //might loss some precision.
values_d[i] = __sinf(fac * x);
oldvalue_d [i] = values_d[i];
}
}
/* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
* Calculate new values using wave equation
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
/* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
* Update all values along line a specified number of times
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
__global__ void update(float* values_d, float* oldvalue_d, int tpoints, int nsteps)
{
int i, j;
int index = blockIdx.x * blockDim.x + threadIdx.x;
int stride = gridDim.x * blockDim.x;
float newval;
/* Update values for each time step */
for ( i = 1; i <= nsteps ; i++) {
/* Update points along line for this time step */
for ( j = index; j <= tpoints; j+=stride) {
if (( j == 1) || ( j == tpoints ) )
newval = 0.0;
else
newval = (1.82)*values_d[j] - oldvalue_d[j];
oldvalue_d [ j ] = values_d [ j ]; /* Update old values with new values */
values_d [ j ] = newval;
}
}
}
/* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
* Print final results
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
void printfinal()
{
int i ;
for( i = 1; i <= tpoints ; i ++){
printf("%6.4f ", values[i]);
if( i %10 == 0)
printf("\n");
}
}
/* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
* Main program
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
int main (int argc, char *argv[])
{
sscanf (argv[1],"%d" ,&tpoints);
sscanf (argv[2],"%d" ,&nsteps);
int numBlock = (tpoints+1+BLOCK_SIZE)/BLOCK_SIZE;
hipMalloc(&d_values, (MAXPOINTS+2) * sizeof(float));
hipMalloc(&d_oldval, (MAXPOINTS+2) * sizeof(float));
check_param();
printf("Initializing points on the line...\n");
init_line<<<numBlock, BLOCK_SIZE>>>(d_values, d_oldval, tpoints);
hipMemcpy(values, d_values, (MAXPOINTS+2) * sizeof(float), hipMemcpyDeviceToHost);
for(int i = 1; i<=tpoints; i++){
printf("%f\n", *(values+i));
}
printf("Updating all points for all time steps...\n");
update<<<numBlock, BLOCK_SIZE>>>(d_values, d_oldval, tpoints, nsteps);
printf("Printing final results...\n");
hipMemcpy(values, d_values, (MAXPOINTS+2) * sizeof(float), hipMemcpyDeviceToHost);
printfinal();
printf("\nDone.\n\n");
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9init_linePfS_i
.globl _Z9init_linePfS_i
.p2align 8
.type _Z9init_linePfS_i,@function
_Z9init_linePfS_i:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x24
s_load_b32 s10, s[0:1], 0x10
s_add_u32 s2, s0, 24
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s8, s4, 0xffff
s_mov_b32 s4, exec_lo
v_mad_u64_u32 v[1:2], null, s15, s8, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_ge_i32_e64 s10, v1
s_cbranch_execz .LBB0_3
s_load_b32 s2, s[2:3], 0x0
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_add_i32 s0, s10, -1
s_mov_b32 s1, 0
v_cvt_f32_i32_e32 v0, s0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_mul_i32 s2, s2, s8
s_ashr_i32 s3, s2, 31
s_delay_alu instid0(SALU_CYCLE_1)
s_lshl_b64 s[8:9], s[2:3], 2
s_set_inst_prefetch_distance 0x1
.p2align 6
.LBB0_2:
v_add_nc_u32_e32 v4, -1, v1
v_add_nc_u32_e32 v1, s2, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_f32_i32_e32 v4, v4
v_div_scale_f32 v5, null, v0, v0, v4
v_div_scale_f32 v8, vcc_lo, v4, v0, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v6, v5
s_waitcnt_depctr 0xfff
v_fma_f32 v7, -v5, v6, 1.0
v_fmac_f32_e32 v6, v7, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v7, v8, v6
v_fma_f32 v9, -v5, v7, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v7, v9, v6
v_fma_f32 v5, -v5, v7, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fmas_f32 v5, v5, v6, v7
v_div_fixup_f32 v4, v5, v0, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_mul_f32_e32 v6, 0x40c90fdb, v4
v_add_co_u32 v4, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v3, vcc_lo
v_mul_f32_e32 v7, 0.15915494, v6
v_add_co_u32 v6, vcc_lo, s6, v2
v_add_co_u32 v2, s0, v2, s8
s_delay_alu instid0(VALU_DEP_3)
v_sin_f32_e32 v8, v7
v_add_co_ci_u32_e32 v7, vcc_lo, s7, v3, vcc_lo
v_cmp_lt_i32_e32 vcc_lo, s10, v1
v_add_co_ci_u32_e64 v3, s0, s9, v3, s0
global_store_b32 v[4:5], v8, off
global_store_b32 v[6:7], v8, off
s_or_b32 s1, vcc_lo, s1
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s1
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_set_inst_prefetch_distance 0x2
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9init_linePfS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 10
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9init_linePfS_i, .Lfunc_end0-_Z9init_linePfS_i
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z6updatePfS_ii
.globl _Z6updatePfS_ii
.p2align 8
.type _Z6updatePfS_ii,@function
_Z6updatePfS_ii:
s_load_b32 s12, s[0:1], 0x14
s_mov_b32 s13, 1
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s12, 1
s_cbranch_scc1 .LBB1_8
s_clause 0x3
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x18
s_load_b32 s14, s[0:1], 0x10
s_load_b128 s[4:7], s[0:1], 0x0
s_mov_b32 s11, 0x3ffd1eb8
s_mov_b32 s10, 0x51eb851f
s_waitcnt lgkmcnt(0)
s_and_b32 s0, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[1:2], null, s15, s0, v[0:1]
s_mul_i32 s2, s3, s0
s_ashr_i32 s3, s2, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_lshl_b64 s[8:9], s[2:3], 2
v_ashrrev_i32_e32 v2, 31, v1
v_cmp_ge_i32_e32 vcc_lo, s14, v1
s_delay_alu instid0(VALU_DEP_2)
v_lshlrev_b64 v[2:3], 2, v[1:2]
s_branch .LBB1_3
.LBB1_2:
s_or_b32 exec_lo, exec_lo, s3
s_add_i32 s0, s13, 1
s_cmp_lg_u32 s13, s12
s_mov_b32 s13, s0
s_cbranch_scc0 .LBB1_8
.LBB1_3:
s_and_saveexec_b32 s3, vcc_lo
s_cbranch_execz .LBB1_2
s_delay_alu instid0(VALU_DEP_1)
v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
v_mov_b32_e32 v0, v1
s_mov_b32 s15, 0
s_branch .LBB1_6
.LBB1_5:
s_or_b32 exec_lo, exec_lo, s1
v_add_co_u32 v7, s0, s4, v4
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v8, s0, s5, v5, s0
v_add_nc_u32_e32 v0, s2, v0
v_add_co_u32 v9, s0, s6, v4
global_load_b32 v11, v[7:8], off
v_add_co_ci_u32_e64 v10, s0, s7, v5, s0
v_cmp_lt_i32_e64 s0, s14, v0
v_add_co_u32 v4, s1, v4, s8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e64 v5, s1, s9, v5, s1
s_or_b32 s15, s0, s15
s_waitcnt vmcnt(0)
global_store_b32 v[9:10], v11, off
global_store_b32 v[7:8], v6, off
s_and_not1_b32 exec_lo, exec_lo, s15
s_cbranch_execz .LBB1_2
.LBB1_6:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_cmp_ne_u32_e64 s0, 1, v0
v_cmp_ne_u32_e64 s1, s14, v0
v_mov_b32_e32 v6, 0
s_and_b32 s0, s0, s1
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB1_5
v_add_co_u32 v6, s0, s4, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e64 v7, s0, s5, v5, s0
v_add_co_u32 v8, s0, s6, v4
v_add_co_ci_u32_e64 v9, s0, s7, v5, s0
global_load_b32 v6, v[6:7], off
global_load_b32 v8, v[8:9], off
s_waitcnt vmcnt(1)
v_cvt_f64_f32_e32 v[6:7], v6
s_waitcnt vmcnt(0)
v_cvt_f64_f32_e32 v[8:9], v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[6:7], v[6:7], s[10:11], -v[8:9]
v_cvt_f32_f64_e32 v6, v[6:7]
s_branch .LBB1_5
.LBB1_8:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6updatePfS_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 12
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z6updatePfS_ii, .Lfunc_end1-_Z6updatePfS_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9init_linePfS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9init_linePfS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 10
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6updatePfS_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6updatePfS_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 12
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | /* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
* DESCRIPTION :
*
Serial Concurrent Wave Equation - C Version
*
This program implements the concurrent wave equation
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
# include <stdio.h>
# include <stdlib.h>
# include <math.h>
# include <time.h>
# include <hip/hip_runtime.h>
# define MAXPOINTS 1000000
# define MAXSTEPS 1000000
# define MINPOINTS 20
# define PI 3.14159265
# define DIM_GRID 1
# define BLOCK_SIZE 256
void check_param ( void ) ;
void init_line ( void ) ;
void update ( void ) ;
void printfinal ( void ) ;
int nsteps , /*number of time steps */
tpoints , /*total points along string */
rcode ; /*generic return code */
float values [ MAXPOINTS +2], /*values at time t */
oldval [ MAXPOINTS +2], /*values at time (t - dt ) */
newval [ MAXPOINTS +2]; /*values at time ( t + dt ) */
float *d_values, *d_oldval, *d_newval;
/* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
* Checks input values from parameters
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
void check_param ( void )
{
char tchar [20];
/* check number of points , number of iterations */
while (( tpoints < MINPOINTS ) || ( tpoints > MAXPOINTS ) ) {
printf ( "Enter number of points along vibrating string [%d-%d]: "
, MINPOINTS , MAXPOINTS ) ;
scanf ( "%s" , tchar ) ;
tpoints = atoi ( tchar ) ;
if (( tpoints < MINPOINTS ) || ( tpoints > MAXPOINTS ) )
printf ( "Invalid. Please enter value between %d and %d\n" ,
MINPOINTS , MAXPOINTS ) ;
}
while (( nsteps < 1) || ( nsteps > MAXSTEPS ) ) {
printf ( "Enter number of time steps [1-%d]: " , MAXSTEPS ) ;
scanf ( "%s" , tchar ) ;
nsteps = atoi ( tchar ) ;
if (( nsteps < 1) || ( nsteps > MAXSTEPS ) )
printf ( "Invalid. Please enter value between 1 and %d\n" ,
MAXSTEPS ) ;
}
printf ( "Using points = %d, steps = %d\n", tpoints, nsteps) ;
}
/* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
* Initialize points on line
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
__global__ void init_line (float* values_d, float* oldvalue_d, int tpoints)
{
int idx = blockIdx.x * blockDim.x + threadIdx.x;
int stride = blockDim.x * gridDim.x;
float fac = 2.0 * PI;
float x;
for ( int i = idx; i <= tpoints; i+=stride) {
x = (float)(i-1)/(tpoints-1); //might loss some precision.
values_d[i] = __sinf(fac * x);
oldvalue_d [i] = values_d[i];
}
}
/* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
* Calculate new values using wave equation
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
/* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
* Update all values along line a specified number of times
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
__global__ void update(float* values_d, float* oldvalue_d, int tpoints, int nsteps)
{
int i, j;
int index = blockIdx.x * blockDim.x + threadIdx.x;
int stride = gridDim.x * blockDim.x;
float newval;
/* Update values for each time step */
for ( i = 1; i <= nsteps ; i++) {
/* Update points along line for this time step */
for ( j = index; j <= tpoints; j+=stride) {
if (( j == 1) || ( j == tpoints ) )
newval = 0.0;
else
newval = (1.82)*values_d[j] - oldvalue_d[j];
oldvalue_d [ j ] = values_d [ j ]; /* Update old values with new values */
values_d [ j ] = newval;
}
}
}
/* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
* Print final results
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
void printfinal()
{
int i ;
for( i = 1; i <= tpoints ; i ++){
printf("%6.4f ", values[i]);
if( i %10 == 0)
printf("\n");
}
}
/* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
* Main program
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
int main (int argc, char *argv[])
{
sscanf (argv[1],"%d" ,&tpoints);
sscanf (argv[2],"%d" ,&nsteps);
int numBlock = (tpoints+1+BLOCK_SIZE)/BLOCK_SIZE;
hipMalloc(&d_values, (MAXPOINTS+2) * sizeof(float));
hipMalloc(&d_oldval, (MAXPOINTS+2) * sizeof(float));
check_param();
printf("Initializing points on the line...\n");
init_line<<<numBlock, BLOCK_SIZE>>>(d_values, d_oldval, tpoints);
hipMemcpy(values, d_values, (MAXPOINTS+2) * sizeof(float), hipMemcpyDeviceToHost);
for(int i = 1; i<=tpoints; i++){
printf("%f\n", *(values+i));
}
printf("Updating all points for all time steps...\n");
update<<<numBlock, BLOCK_SIZE>>>(d_values, d_oldval, tpoints, nsteps);
printf("Printing final results...\n");
hipMemcpy(values, d_values, (MAXPOINTS+2) * sizeof(float), hipMemcpyDeviceToHost);
printfinal();
printf("\nDone.\n\n");
return 0;
} | .text
.file "0856148.hip"
.globl _Z11check_paramv # -- Begin function _Z11check_paramv
.p2align 4, 0x90
.type _Z11check_paramv,@function
_Z11check_paramv: # @_Z11check_paramv
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $24, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -24
.cfi_offset %rbp, -16
movl $-1000001, %ebp # imm = 0xFFF0BDBF
movl tpoints(%rip), %eax
addl %ebp, %eax
cmpl $-999982, %eax # imm = 0xFFF0BDD2
ja .LBB0_5
# %bb.1:
movq %rsp, %rbx
jmp .LBB0_2
.p2align 4, 0x90
.LBB0_4: # in Loop: Header=BB0_2 Depth=1
movl tpoints(%rip), %eax
addl %ebp, %eax
cmpl $-999981, %eax # imm = 0xFFF0BDD3
jae .LBB0_5
.LBB0_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl $.L.str, %edi
movl $20, %esi
movl $1000000, %edx # imm = 0xF4240
xorl %eax, %eax
callq printf
movl $.L.str.1, %edi
movq %rbx, %rsi
xorl %eax, %eax
callq __isoc23_scanf
movq %rbx, %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movl %eax, tpoints(%rip)
addl $-1000001, %eax # imm = 0xFFF0BDBF
cmpl $-999982, %eax # imm = 0xFFF0BDD2
ja .LBB0_4
# %bb.3: # in Loop: Header=BB0_2 Depth=1
movl $.L.str.2, %edi
movl $20, %esi
movl $1000000, %edx # imm = 0xF4240
xorl %eax, %eax
callq printf
jmp .LBB0_4
.LBB0_5: # %.preheader
movl nsteps(%rip), %edx
leal -1000001(%rdx), %eax
cmpl $-1000001, %eax # imm = 0xFFF0BDBF
ja .LBB0_10
# %bb.6:
movq %rsp, %rbx
jmp .LBB0_7
.p2align 4, 0x90
.LBB0_9: # in Loop: Header=BB0_7 Depth=1
movl nsteps(%rip), %edx
leal -1000001(%rdx), %eax
cmpl $-1000000, %eax # imm = 0xFFF0BDC0
jae .LBB0_10
.LBB0_7: # %.lr.ph4
# =>This Inner Loop Header: Depth=1
movl $.L.str.3, %edi
movl $1000000, %esi # imm = 0xF4240
xorl %eax, %eax
callq printf
movl $.L.str.1, %edi
movq %rbx, %rsi
xorl %eax, %eax
callq __isoc23_scanf
movq %rbx, %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movl %eax, nsteps(%rip)
addl $-1000001, %eax # imm = 0xFFF0BDBF
cmpl $-1000001, %eax # imm = 0xFFF0BDBF
ja .LBB0_9
# %bb.8: # in Loop: Header=BB0_7 Depth=1
movl $.L.str.4, %edi
movl $1000000, %esi # imm = 0xF4240
xorl %eax, %eax
callq printf
jmp .LBB0_9
.LBB0_10: # %._crit_edge
movl tpoints(%rip), %esi
movl $.L.str.5, %edi
# kill: def $edx killed $edx killed $rdx
xorl %eax, %eax
callq printf
addq $24, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z11check_paramv, .Lfunc_end0-_Z11check_paramv
.cfi_endproc
# -- End function
.globl _Z24__device_stub__init_linePfS_i # -- Begin function _Z24__device_stub__init_linePfS_i
.p2align 4, 0x90
.type _Z24__device_stub__init_linePfS_i,@function
_Z24__device_stub__init_linePfS_i: # @_Z24__device_stub__init_linePfS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9init_linePfS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end1:
.size _Z24__device_stub__init_linePfS_i, .Lfunc_end1-_Z24__device_stub__init_linePfS_i
.cfi_endproc
# -- End function
.globl _Z21__device_stub__updatePfS_ii # -- Begin function _Z21__device_stub__updatePfS_ii
.p2align 4, 0x90
.type _Z21__device_stub__updatePfS_ii,@function
_Z21__device_stub__updatePfS_ii: # @_Z21__device_stub__updatePfS_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6updatePfS_ii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end2:
.size _Z21__device_stub__updatePfS_ii, .Lfunc_end2-_Z21__device_stub__updatePfS_ii
.cfi_endproc
# -- End function
.globl _Z10printfinalv # -- Begin function _Z10printfinalv
.p2align 4, 0x90
.type _Z10printfinalv,@function
_Z10printfinalv: # @_Z10printfinalv
.cfi_startproc
# %bb.0:
cmpl $0, tpoints(%rip)
jle .LBB3_6
# %bb.1: # %.lr.ph.preheader
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
pushq %rax
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $1, %ebx
xorl %r14d, %r14d
movl $3435973837, %r15d # imm = 0xCCCCCCCD
jmp .LBB3_2
.p2align 4, 0x90
.LBB3_4: # in Loop: Header=BB3_2 Depth=1
movslq tpoints(%rip), %rax
incq %r14
incl %ebx
cmpq %rax, %r14
jge .LBB3_5
.LBB3_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl %ebx, %eax
imulq %r15, %rax
shrq $35, %rax
leal (%rax,%rax,4), %eax
leal -1(,%rax,2), %ebp
movss values+4(,%r14,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.6, %edi
movb $1, %al
callq printf
cmpl %r14d, %ebp
jne .LBB3_4
# %bb.3: # in Loop: Header=BB3_2 Depth=1
movl $10, %edi
callq putchar@PLT
jmp .LBB3_4
.LBB3_5:
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r14
.cfi_restore %r15
.cfi_restore %rbp
.LBB3_6: # %._crit_edge
retq
.Lfunc_end3:
.size _Z10printfinalv, .Lfunc_end3-_Z10printfinalv
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $120, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %r14
movabsq $4294967552, %rbx # imm = 0x100000100
movq 8(%rsi), %rdi
movl $.L.str.8, %esi
movl $tpoints, %edx
xorl %eax, %eax
callq __isoc23_sscanf
movq 16(%r14), %rdi
movl $.L.str.8, %esi
movl $nsteps, %edx
xorl %eax, %eax
callq __isoc23_sscanf
movl tpoints(%rip), %r14d
leal 257(%r14), %eax
addl $512, %r14d # imm = 0x200
testl %eax, %eax
cmovnsl %eax, %r14d
sarl $8, %r14d
movl $d_values, %edi
movl $4000008, %esi # imm = 0x3D0908
callq hipMalloc
movl $d_oldval, %edi
movl $4000008, %esi # imm = 0x3D0908
callq hipMalloc
callq _Z11check_paramv
movl $.Lstr, %edi
callq puts@PLT
addq %rbx, %r14
addq $-256, %r14
movq %r14, %rdi
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_2
# %bb.1:
movq d_values(%rip), %rax
movq d_oldval(%rip), %rcx
movl tpoints(%rip), %edx
movq %rax, 64(%rsp)
movq %rcx, 56(%rsp)
movl %edx, 4(%rsp)
leaq 64(%rsp), %rax
movq %rax, 80(%rsp)
leaq 56(%rsp), %rax
movq %rax, 88(%rsp)
leaq 4(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9init_linePfS_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_2:
movq d_values(%rip), %rsi
movl $values, %edi
movl $4000008, %edx # imm = 0x3D0908
movl $2, %ecx
callq hipMemcpy
cmpl $0, tpoints(%rip)
jle .LBB4_5
# %bb.3: # %.lr.ph.preheader
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB4_4: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movss values+4(,%r15,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.10, %edi
movb $1, %al
callq printf
movslq tpoints(%rip), %rax
incq %r15
cmpq %rax, %r15
jl .LBB4_4
.LBB4_5: # %._crit_edge
movl $.Lstr.1, %edi
callq puts@PLT
movq %r14, %rdi
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_7
# %bb.6:
movq d_values(%rip), %rax
movq d_oldval(%rip), %rcx
movl tpoints(%rip), %edx
movl nsteps(%rip), %esi
movq %rax, 64(%rsp)
movq %rcx, 56(%rsp)
movl %edx, 4(%rsp)
movl %esi, 76(%rsp)
leaq 64(%rsp), %rax
movq %rax, 80(%rsp)
leaq 56(%rsp), %rax
movq %rax, 88(%rsp)
leaq 4(%rsp), %rax
movq %rax, 96(%rsp)
leaq 76(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6updatePfS_ii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_7:
movl $.Lstr.2, %edi
callq puts@PLT
movq d_values(%rip), %rsi
movl $values, %edi
movl $4000008, %edx # imm = 0x3D0908
movl $2, %ecx
callq hipMemcpy
cmpl $0, tpoints(%rip)
jle .LBB4_12
# %bb.8: # %.lr.ph.i.preheader
movl $1, %ebx
xorl %r14d, %r14d
movl $3435973837, %r15d # imm = 0xCCCCCCCD
jmp .LBB4_9
.p2align 4, 0x90
.LBB4_11: # in Loop: Header=BB4_9 Depth=1
movslq tpoints(%rip), %rax
incq %r14
incl %ebx
cmpq %rax, %r14
jge .LBB4_12
.LBB4_9: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
movl %ebx, %eax
imulq %r15, %rax
shrq $35, %rax
leal (%rax,%rax,4), %eax
leal -1(,%rax,2), %ebp
movss values+4(,%r14,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.6, %edi
movb $1, %al
callq printf
cmpl %r14d, %ebp
jne .LBB4_11
# %bb.10: # in Loop: Header=BB4_9 Depth=1
movl $10, %edi
callq putchar@PLT
jmp .LBB4_11
.LBB4_12: # %_Z10printfinalv.exit
movl $.Lstr.3, %edi
callq puts@PLT
xorl %eax, %eax
addq $120, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end4:
.size main, .Lfunc_end4-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9init_linePfS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6updatePfS_ii, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type nsteps,@object # @nsteps
.bss
.globl nsteps
.p2align 2, 0x0
nsteps:
.long 0 # 0x0
.size nsteps, 4
.type tpoints,@object # @tpoints
.globl tpoints
.p2align 2, 0x0
tpoints:
.long 0 # 0x0
.size tpoints, 4
.type rcode,@object # @rcode
.globl rcode
.p2align 2, 0x0
rcode:
.long 0 # 0x0
.size rcode, 4
.type values,@object # @values
.globl values
.p2align 4, 0x0
values:
.zero 4000008
.size values, 4000008
.type oldval,@object # @oldval
.globl oldval
.p2align 4, 0x0
oldval:
.zero 4000008
.size oldval, 4000008
.type newval,@object # @newval
.globl newval
.p2align 4, 0x0
newval:
.zero 4000008
.size newval, 4000008
.type d_values,@object # @d_values
.globl d_values
.p2align 3, 0x0
d_values:
.quad 0
.size d_values, 8
.type d_oldval,@object # @d_oldval
.globl d_oldval
.p2align 3, 0x0
d_oldval:
.quad 0
.size d_oldval, 8
.type d_newval,@object # @d_newval
.globl d_newval
.p2align 3, 0x0
d_newval:
.quad 0
.size d_newval, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Enter number of points along vibrating string [%d-%d]: "
.size .L.str, 56
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "%s"
.size .L.str.1, 3
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Invalid. Please enter value between %d and %d\n"
.size .L.str.2, 47
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Enter number of time steps [1-%d]: "
.size .L.str.3, 36
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Invalid. Please enter value between 1 and %d\n"
.size .L.str.4, 46
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Using points = %d, steps = %d\n"
.size .L.str.5, 31
.type _Z9init_linePfS_i,@object # @_Z9init_linePfS_i
.section .rodata,"a",@progbits
.globl _Z9init_linePfS_i
.p2align 3, 0x0
_Z9init_linePfS_i:
.quad _Z24__device_stub__init_linePfS_i
.size _Z9init_linePfS_i, 8
.type _Z6updatePfS_ii,@object # @_Z6updatePfS_ii
.globl _Z6updatePfS_ii
.p2align 3, 0x0
_Z6updatePfS_ii:
.quad _Z21__device_stub__updatePfS_ii
.size _Z6updatePfS_ii, 8
.type .L.str.6,@object # @.str.6
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.6:
.asciz "%6.4f "
.size .L.str.6, 7
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "%d"
.size .L.str.8, 3
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "%f\n"
.size .L.str.10, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z9init_linePfS_i"
.size .L__unnamed_1, 18
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z6updatePfS_ii"
.size .L__unnamed_2, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Initializing points on the line..."
.size .Lstr, 35
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "Updating all points for all time steps..."
.size .Lstr.1, 42
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "Printing final results..."
.size .Lstr.2, 26
.type .Lstr.3,@object # @str.3
.Lstr.3:
.asciz "\nDone.\n"
.size .Lstr.3, 8
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__init_linePfS_i
.addrsig_sym _Z21__device_stub__updatePfS_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym nsteps
.addrsig_sym tpoints
.addrsig_sym values
.addrsig_sym d_values
.addrsig_sym d_oldval
.addrsig_sym _Z9init_linePfS_i
.addrsig_sym _Z6updatePfS_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z6updatePfS_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ HFMA2.MMA R2, -RZ, RZ, 0, 5.9604644775390625e-08 ; /* 0x00000001ff027435 */
/* 0x000fe200000001ff */
/*0020*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0030*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e6a0000002100 */
/*0040*/ ISETP.LE.AND P0, PT, R2, c[0x0][0x174], PT ; /* 0x00005d0002007a0c */
/* 0x000fda0003f03270 */
/*0050*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0060*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x003fe200078e0203 */
/*0070*/ UMOV UR4, 0x1 ; /* 0x0000000100047882 */
/* 0x000fe40000000000 */
/*0080*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe40000000a00 */
/*0090*/ ISETP.GT.AND P0, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x000fe20003f04270 */
/*00a0*/ IMAD.U32 R2, RZ, RZ, UR4 ; /* 0x00000004ff027e24 */
/* 0x000fe2000f8e00ff */
/*00b0*/ UIADD3 UR4, UR4, 0x1, URZ ; /* 0x0000000104047890 */
/* 0x000fe2000fffe03f */
/*00c0*/ BSSY B0, 0x230 ; /* 0x0000016000007945 */
/* 0x000fe60003800000 */
/*00d0*/ ISETP.GE.AND P1, PT, R2, c[0x0][0x174], PT ; /* 0x00005d0002007a0c */
/* 0x000fce0003f26270 */
/*00e0*/ @P0 BRA 0x220 ; /* 0x0000013000000947 */
/* 0x001fea0003800000 */
/*00f0*/ MOV R10, R0 ; /* 0x00000000000a7202 */
/* 0x000fc80000000f00 */
/*0100*/ ISETP.NE.AND P0, PT, R10, c[0x0][0x170], PT ; /* 0x00005c000a007a0c */
/* 0x000fe20003f05270 */
/*0110*/ IMAD.MOV.U32 R9, RZ, RZ, 0x4 ; /* 0x00000004ff097424 */
/* 0x001fc600078e00ff */
/*0120*/ ISETP.EQ.OR P0, PT, R10.reuse, 0x1, !P0 ; /* 0x000000010a00780c */
/* 0x040fe20004702670 */
/*0130*/ IMAD.WIDE R6, R10, R9, c[0x0][0x160] ; /* 0x000058000a067625 */
/* 0x000fc800078e0209 */
/*0140*/ IMAD.WIDE R8, R10, R9, c[0x0][0x168] ; /* 0x00005a000a087625 */
/* 0x000fe200078e0209 */
/*0150*/ LDG.E R13, [R6.64] ; /* 0x00000006060d7981 */
/* 0x000eae000c1e1900 */
/*0160*/ @!P0 LDG.E R4, [R8.64] ; /* 0x0000000608048981 */
/* 0x000ee2000c1e1900 */
/*0170*/ IMAD.MOV.U32 R11, RZ, RZ, c[0x0][0xc] ; /* 0x00000300ff0b7624 */
/* 0x000fc800078e00ff */
/*0180*/ IMAD R10, R11, c[0x0][0x0], R10 ; /* 0x000000000b0a7a24 */
/* 0x000fe200078e020a */
/*0190*/ @!P0 F2F.F64.F32 R2, R13 ; /* 0x0000000d00028310 */
/* 0x004fe20000201800 */
/*01a0*/ STG.E [R8.64], R13 ; /* 0x0000000d08007986 */
/* 0x0001ee000c101906 */
/*01b0*/ @!P0 F2F.F64.F32 R4, R4 ; /* 0x0000000400048310 */
/* 0x008e640000201800 */
/*01c0*/ @!P0 DFMA R2, R2, c[0x2][0x0], -R4 ; /* 0x0080000002028a2b */
/* 0x002e4c0000000804 */
/*01d0*/ @!P0 F2F.F32.F64 R5, R2 ; /* 0x0000000200058310 */
/* 0x002e620000301000 */
/*01e0*/ @P0 MOV R5, RZ ; /* 0x000000ff00050202 */
/* 0x000fe40000000f00 */
/*01f0*/ ISETP.GT.AND P0, PT, R10, c[0x0][0x170], PT ; /* 0x00005c000a007a0c */
/* 0x000fc60003f04270 */
/*0200*/ STG.E [R6.64], R5 ; /* 0x0000000506007986 */
/* 0x0021f4000c101906 */
/*0210*/ @!P0 BRA 0x100 ; /* 0xfffffee000008947 */
/* 0x000fea000383ffff */
/*0220*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0230*/ @!P1 BRA 0x90 ; /* 0xfffffe5000009947 */
/* 0x000fea000383ffff */
/*0240*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0250*/ BRA 0x250; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z9init_linePfS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R2, R2, c[0x0][0x0], R3 ; /* 0x0000000002027a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GT.AND P0, PT, R2, c[0x0][0x170], PT ; /* 0x00005c0002007a0c */
/* 0x000fda0003f04270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ ULDC UR4, c[0x0][0x170] ; /* 0x00005c0000047ab9 */
/* 0x000fe40000000800 */
/*0070*/ UIADD3 UR4, UR4, -0x1, URZ ; /* 0xffffffff04047890 */
/* 0x000fd2000fffe03f */
/*0080*/ I2F R0, UR4 ; /* 0x0000000400007d06 */
/* 0x000e220008201400 */
/*0090*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fca0000000a00 */
/*00a0*/ IADD3 R3, R2, -0x1, RZ ; /* 0xffffffff02037810 */
/* 0x001fe20007ffe0ff */
/*00b0*/ MUFU.RCP R5, R0 ; /* 0x0000000000057308 */
/* 0x001e220000001000 */
/*00c0*/ BSSY B0, 0x190 ; /* 0x000000c000007945 */
/* 0x000fee0003800000 */
/*00d0*/ I2F R9, R3 ; /* 0x0000000300097306 */
/* 0x000e620000201400 */
/*00e0*/ FFMA R4, -R0, R5, 1 ; /* 0x3f80000000047423 */
/* 0x001fc80000000105 */
/*00f0*/ FFMA R4, R5, R4, R5 ; /* 0x0000000405047223 */
/* 0x000fc60000000005 */
/*0100*/ FCHK P0, R9, R0 ; /* 0x0000000009007302 */
/* 0x002e220000000000 */
/*0110*/ FFMA R5, R9, R4, RZ ; /* 0x0000000409057223 */
/* 0x000fc800000000ff */
/*0120*/ FFMA R6, -R0, R5, R9 ; /* 0x0000000500067223 */
/* 0x000fc80000000109 */
/*0130*/ FFMA R4, R4, R6, R5 ; /* 0x0000000604047223 */
/* 0x000fe20000000005 */
/*0140*/ @!P0 BRA 0x180 ; /* 0x0000003000008947 */
/* 0x001fea0003800000 */
/*0150*/ MOV R4, 0x170 ; /* 0x0000017000047802 */
/* 0x000fe40000000f00 */
/*0160*/ CALL.REL.NOINC 0x260 ; /* 0x000000f000007944 */
/* 0x000fea0003c00000 */
/*0170*/ IMAD.MOV.U32 R4, RZ, RZ, R3 ; /* 0x000000ffff047224 */
/* 0x001fe400078e0003 */
/*0180*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0190*/ FMUL R4, R4, 6.2831854820251464844 ; /* 0x40c90fdb04047820 */
/* 0x000fe40000400000 */
/*01a0*/ IMAD.MOV.U32 R7, RZ, RZ, 0x4 ; /* 0x00000004ff077424 */
/* 0x000fe400078e00ff */
/*01b0*/ FMUL.RZ R3, R4, 0.15915493667125701904 ; /* 0x3e22f98304037820 */
/* 0x000fe4000040c000 */
/*01c0*/ IMAD.WIDE R4, R2, R7, c[0x0][0x160] ; /* 0x0000580002047625 */
/* 0x000fc800078e0207 */
/*01d0*/ MUFU.SIN R3, R3 ; /* 0x0000000300037308 */
/* 0x000e220000000400 */
/*01e0*/ IMAD.WIDE R6, R2, R7, c[0x0][0x168] ; /* 0x00005a0002067625 */
/* 0x000fc800078e0207 */
/*01f0*/ IMAD.MOV.U32 R9, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff097624 */
/* 0x000fc800078e00ff */
/*0200*/ IMAD R2, R9, c[0x0][0xc], R2 ; /* 0x0000030009027a24 */
/* 0x000fca00078e0202 */
/*0210*/ ISETP.GT.AND P0, PT, R2, c[0x0][0x170], PT ; /* 0x00005c0002007a0c */
/* 0x000fe20003f04270 */
/*0220*/ STG.E [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x0011e8000c101904 */
/*0230*/ STG.E [R6.64], R3 ; /* 0x0000000306007986 */
/* 0x0001f0000c101904 */
/*0240*/ @!P0 BRA 0xa0 ; /* 0xfffffe5000008947 */
/* 0x000fea000383ffff */
/*0250*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0260*/ SHF.R.U32.HI R5, RZ, 0x17, R0.reuse ; /* 0x00000017ff057819 */
/* 0x100fe20000011600 */
/*0270*/ BSSY B1, 0x8d0 ; /* 0x0000065000017945 */
/* 0x000fe20003800000 */
/*0280*/ SHF.R.U32.HI R3, RZ, 0x17, R9.reuse ; /* 0x00000017ff037819 */
/* 0x100fe20000011609 */
/*0290*/ IMAD.MOV.U32 R6, RZ, RZ, R9 ; /* 0x000000ffff067224 */
/* 0x000fe200078e0009 */
/*02a0*/ LOP3.LUT R5, R5, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff05057812 */
/* 0x000fe200078ec0ff */
/*02b0*/ IMAD.MOV.U32 R7, RZ, RZ, R0 ; /* 0x000000ffff077224 */
/* 0x000fe200078e0000 */
/*02c0*/ LOP3.LUT R11, R3, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff030b7812 */
/* 0x000fc400078ec0ff */
/*02d0*/ IADD3 R10, R5, -0x1, RZ ; /* 0xffffffff050a7810 */
/* 0x000fe40007ffe0ff */
/*02e0*/ IADD3 R12, R11, -0x1, RZ ; /* 0xffffffff0b0c7810 */
/* 0x000fe40007ffe0ff */
/*02f0*/ ISETP.GT.U32.AND P0, PT, R10, 0xfd, PT ; /* 0x000000fd0a00780c */
/* 0x000fc80003f04070 */
/*0300*/ ISETP.GT.U32.OR P0, PT, R12, 0xfd, P0 ; /* 0x000000fd0c00780c */
/* 0x000fda0000704470 */
/*0310*/ @!P0 IMAD.MOV.U32 R8, RZ, RZ, RZ ; /* 0x000000ffff088224 */
/* 0x000fe200078e00ff */
/*0320*/ @!P0 BRA 0x4b0 ; /* 0x0000018000008947 */
/* 0x000fea0003800000 */
/*0330*/ FSETP.GTU.FTZ.AND P1, PT, |R0|, +INF , PT ; /* 0x7f8000000000780b */
/* 0x000fe20003f3c200 */
/*0340*/ IMAD.MOV.U32 R3, RZ, RZ, R9 ; /* 0x000000ffff037224 */
/* 0x000fe200078e0009 */
/*0350*/ FSETP.GTU.FTZ.AND P0, PT, |R9|, +INF , PT ; /* 0x7f8000000900780b */
/* 0x000fc80003f1c200 */
/*0360*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000703570 */
/*0370*/ @P0 BRA 0x8b0 ; /* 0x0000053000000947 */
/* 0x000fea0003800000 */
/*0380*/ LOP3.LUT P0, RZ, R7, 0x7fffffff, R6, 0xc8, !PT ; /* 0x7fffffff07ff7812 */
/* 0x000fda000780c806 */
/*0390*/ @!P0 BRA 0x890 ; /* 0x000004f000008947 */
/* 0x000fea0003800000 */
/*03a0*/ FSETP.NEU.FTZ.AND P2, PT, |R3|.reuse, +INF , PT ; /* 0x7f8000000300780b */
/* 0x040fe40003f5d200 */
/*03b0*/ FSETP.NEU.FTZ.AND P1, PT, |R0|, +INF , PT ; /* 0x7f8000000000780b */
/* 0x000fe40003f3d200 */
/*03c0*/ FSETP.NEU.FTZ.AND P0, PT, |R3|, +INF , PT ; /* 0x7f8000000300780b */
/* 0x000fd60003f1d200 */
/*03d0*/ @!P1 BRA !P2, 0x890 ; /* 0x000004b000009947 */
/* 0x000fea0005000000 */
/*03e0*/ LOP3.LUT P2, RZ, R6, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff06ff7812 */
/* 0x000fc8000784c0ff */
/*03f0*/ PLOP3.LUT P1, PT, P1, P2, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000f24572 */
/*0400*/ @P1 BRA 0x870 ; /* 0x0000046000001947 */
/* 0x000fea0003800000 */
/*0410*/ LOP3.LUT P1, RZ, R7, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff07ff7812 */
/* 0x000fc8000782c0ff */
/*0420*/ PLOP3.LUT P0, PT, P0, P1, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000702572 */
/*0430*/ @P0 BRA 0x840 ; /* 0x0000040000000947 */
/* 0x000fea0003800000 */
/*0440*/ ISETP.GE.AND P0, PT, R12, RZ, PT ; /* 0x000000ff0c00720c */
/* 0x000fe40003f06270 */
/*0450*/ ISETP.GE.AND P1, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fd60003f26270 */
/*0460*/ @P0 IMAD.MOV.U32 R8, RZ, RZ, RZ ; /* 0x000000ffff080224 */
/* 0x000fe400078e00ff */
/*0470*/ @!P0 IMAD.MOV.U32 R8, RZ, RZ, -0x40 ; /* 0xffffffc0ff088424 */
/* 0x000fe400078e00ff */
/*0480*/ @!P0 FFMA R6, R3, 1.84467440737095516160e+19, RZ ; /* 0x5f80000003068823 */
/* 0x000fe400000000ff */
/*0490*/ @!P1 FFMA R7, R0, 1.84467440737095516160e+19, RZ ; /* 0x5f80000000079823 */
/* 0x000fe200000000ff */
/*04a0*/ @!P1 IADD3 R8, R8, 0x40, RZ ; /* 0x0000004008089810 */
/* 0x000fe40007ffe0ff */
/*04b0*/ LEA R10, R5, 0xc0800000, 0x17 ; /* 0xc0800000050a7811 */
/* 0x000fe200078eb8ff */
/*04c0*/ BSSY B2, 0x830 ; /* 0x0000036000027945 */
/* 0x000fe80003800000 */
/*04d0*/ IMAD.IADD R10, R7, 0x1, -R10 ; /* 0x00000001070a7824 */
/* 0x000fe200078e0a0a */
/*04e0*/ IADD3 R7, R11, -0x7f, RZ ; /* 0xffffff810b077810 */
/* 0x000fc60007ffe0ff */
/*04f0*/ MUFU.RCP R3, R10 ; /* 0x0000000a00037308 */
/* 0x000e220000001000 */
/*0500*/ FADD.FTZ R9, -R10, -RZ ; /* 0x800000ff0a097221 */
/* 0x000fe40000010100 */
/*0510*/ IMAD R6, R7.reuse, -0x800000, R6 ; /* 0xff80000007067824 */
/* 0x040fe200078e0206 */
/*0520*/ IADD3 R7, R7, 0x7f, -R5 ; /* 0x0000007f07077810 */
/* 0x000fca0007ffe805 */
/*0530*/ IMAD.IADD R8, R7, 0x1, R8 ; /* 0x0000000107087824 */
/* 0x000fe400078e0208 */
/*0540*/ FFMA R12, R3, R9, 1 ; /* 0x3f800000030c7423 */
/* 0x001fc80000000009 */
/*0550*/ FFMA R11, R3, R12, R3 ; /* 0x0000000c030b7223 */
/* 0x000fc80000000003 */
/*0560*/ FFMA R3, R6, R11, RZ ; /* 0x0000000b06037223 */
/* 0x000fc800000000ff */
/*0570*/ FFMA R12, R9, R3, R6 ; /* 0x00000003090c7223 */
/* 0x000fc80000000006 */
/*0580*/ FFMA R12, R11, R12, R3 ; /* 0x0000000c0b0c7223 */
/* 0x000fc80000000003 */
/*0590*/ FFMA R6, R9, R12, R6 ; /* 0x0000000c09067223 */
/* 0x000fc80000000006 */
/*05a0*/ FFMA R3, R11, R6, R12 ; /* 0x000000060b037223 */
/* 0x000fca000000000c */
/*05b0*/ SHF.R.U32.HI R5, RZ, 0x17, R3 ; /* 0x00000017ff057819 */
/* 0x000fc80000011603 */
/*05c0*/ LOP3.LUT R5, R5, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff05057812 */
/* 0x000fca00078ec0ff */
/*05d0*/ IMAD.IADD R9, R5, 0x1, R8 ; /* 0x0000000105097824 */
/* 0x000fca00078e0208 */
/*05e0*/ IADD3 R5, R9, -0x1, RZ ; /* 0xffffffff09057810 */
/* 0x000fc80007ffe0ff */
/*05f0*/ ISETP.GE.U32.AND P0, PT, R5, 0xfe, PT ; /* 0x000000fe0500780c */
/* 0x000fda0003f06070 */
/*0600*/ @!P0 BRA 0x810 ; /* 0x0000020000008947 */
/* 0x000fea0003800000 */
/*0610*/ ISETP.GT.AND P0, PT, R9, 0xfe, PT ; /* 0x000000fe0900780c */
/* 0x000fda0003f04270 */
/*0620*/ @P0 BRA 0x7e0 ; /* 0x000001b000000947 */
/* 0x000fea0003800000 */
/*0630*/ ISETP.GE.AND P0, PT, R9, 0x1, PT ; /* 0x000000010900780c */
/* 0x000fda0003f06270 */
/*0640*/ @P0 BRA 0x820 ; /* 0x000001d000000947 */
/* 0x000fea0003800000 */
/*0650*/ ISETP.GE.AND P0, PT, R9, -0x18, PT ; /* 0xffffffe80900780c */
/* 0x000fe40003f06270 */
/*0660*/ LOP3.LUT R3, R3, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000003037812 */
/* 0x000fd600078ec0ff */
/*0670*/ @!P0 BRA 0x820 ; /* 0x000001a000008947 */
/* 0x000fea0003800000 */
/*0680*/ FFMA.RZ R5, R11, R6.reuse, R12.reuse ; /* 0x000000060b057223 */
/* 0x180fe2000000c00c */
/*0690*/ IADD3 R8, R9.reuse, 0x20, RZ ; /* 0x0000002009087810 */
/* 0x040fe40007ffe0ff */
/*06a0*/ ISETP.NE.AND P2, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x000fe40003f45270 */
/*06b0*/ LOP3.LUT R7, R5, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff05077812 */
/* 0x000fe200078ec0ff */
/*06c0*/ FFMA.RP R5, R11, R6.reuse, R12.reuse ; /* 0x000000060b057223 */
/* 0x180fe2000000800c */
/*06d0*/ ISETP.NE.AND P1, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x000fe20003f25270 */
/*06e0*/ FFMA.RM R6, R11, R6, R12 ; /* 0x000000060b067223 */
/* 0x000fe2000000400c */
/*06f0*/ LOP3.LUT R7, R7, 0x800000, RZ, 0xfc, !PT ; /* 0x0080000007077812 */
/* 0x000fe200078efcff */
/*0700*/ IMAD.MOV R9, RZ, RZ, -R9 ; /* 0x000000ffff097224 */
/* 0x000fc600078e0a09 */
/*0710*/ SHF.L.U32 R8, R7, R8, RZ ; /* 0x0000000807087219 */
/* 0x000fe400000006ff */
/*0720*/ FSETP.NEU.FTZ.AND P0, PT, R5, R6, PT ; /* 0x000000060500720b */
/* 0x000fe40003f1d000 */
/*0730*/ SEL R6, R9, RZ, P2 ; /* 0x000000ff09067207 */
/* 0x000fe40001000000 */
/*0740*/ ISETP.NE.AND P1, PT, R8, RZ, P1 ; /* 0x000000ff0800720c */
/* 0x000fe40000f25270 */
/*0750*/ SHF.R.U32.HI R6, RZ, R6, R7 ; /* 0x00000006ff067219 */
/* 0x000fe40000011607 */
/*0760*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc40000703570 */
/*0770*/ SHF.R.U32.HI R8, RZ, 0x1, R6 ; /* 0x00000001ff087819 */
/* 0x000fe40000011606 */
/*0780*/ SEL R5, RZ, 0x1, !P0 ; /* 0x00000001ff057807 */
/* 0x000fc80004000000 */
/*0790*/ LOP3.LUT R5, R5, 0x1, R8, 0xf8, !PT ; /* 0x0000000105057812 */
/* 0x000fc800078ef808 */
/*07a0*/ LOP3.LUT R5, R5, R6, RZ, 0xc0, !PT ; /* 0x0000000605057212 */
/* 0x000fca00078ec0ff */
/*07b0*/ IMAD.IADD R8, R8, 0x1, R5 ; /* 0x0000000108087824 */
/* 0x000fca00078e0205 */
/*07c0*/ LOP3.LUT R3, R8, R3, RZ, 0xfc, !PT ; /* 0x0000000308037212 */
/* 0x000fe200078efcff */
/*07d0*/ BRA 0x820 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*07e0*/ LOP3.LUT R3, R3, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000003037812 */
/* 0x000fc800078ec0ff */
/*07f0*/ LOP3.LUT R3, R3, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000003037812 */
/* 0x000fe200078efcff */
/*0800*/ BRA 0x820 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0810*/ IMAD R3, R8, 0x800000, R3 ; /* 0x0080000008037824 */
/* 0x000fe400078e0203 */
/*0820*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*0830*/ BRA 0x8c0 ; /* 0x0000008000007947 */
/* 0x000fea0003800000 */
/*0840*/ LOP3.LUT R3, R7, 0x80000000, R6, 0x48, !PT ; /* 0x8000000007037812 */
/* 0x000fc800078e4806 */
/*0850*/ LOP3.LUT R3, R3, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000003037812 */
/* 0x000fe200078efcff */
/*0860*/ BRA 0x8c0 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*0870*/ LOP3.LUT R3, R7, 0x80000000, R6, 0x48, !PT ; /* 0x8000000007037812 */
/* 0x000fe200078e4806 */
/*0880*/ BRA 0x8c0 ; /* 0x0000003000007947 */
/* 0x000fea0003800000 */
/*0890*/ MUFU.RSQ R3, -QNAN ; /* 0xffc0000000037908 */
/* 0x000e220000001400 */
/*08a0*/ BRA 0x8c0 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*08b0*/ FADD.FTZ R3, R3, R0 ; /* 0x0000000003037221 */
/* 0x000fe40000010000 */
/*08c0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*08d0*/ IMAD.MOV.U32 R5, RZ, RZ, 0x0 ; /* 0x00000000ff057424 */
/* 0x000fc800078e00ff */
/*08e0*/ RET.REL.NODEC R4 0x0 ; /* 0xfffff71004007950 */
/* 0x000fea0003c3ffff */
/*08f0*/ BRA 0x8f0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0900*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0910*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0920*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0930*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0940*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0950*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0960*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0970*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9init_linePfS_i
.globl _Z9init_linePfS_i
.p2align 8
.type _Z9init_linePfS_i,@function
_Z9init_linePfS_i:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x24
s_load_b32 s10, s[0:1], 0x10
s_add_u32 s2, s0, 24
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s8, s4, 0xffff
s_mov_b32 s4, exec_lo
v_mad_u64_u32 v[1:2], null, s15, s8, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_ge_i32_e64 s10, v1
s_cbranch_execz .LBB0_3
s_load_b32 s2, s[2:3], 0x0
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_add_i32 s0, s10, -1
s_mov_b32 s1, 0
v_cvt_f32_i32_e32 v0, s0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_mul_i32 s2, s2, s8
s_ashr_i32 s3, s2, 31
s_delay_alu instid0(SALU_CYCLE_1)
s_lshl_b64 s[8:9], s[2:3], 2
s_set_inst_prefetch_distance 0x1
.p2align 6
.LBB0_2:
v_add_nc_u32_e32 v4, -1, v1
v_add_nc_u32_e32 v1, s2, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_f32_i32_e32 v4, v4
v_div_scale_f32 v5, null, v0, v0, v4
v_div_scale_f32 v8, vcc_lo, v4, v0, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v6, v5
s_waitcnt_depctr 0xfff
v_fma_f32 v7, -v5, v6, 1.0
v_fmac_f32_e32 v6, v7, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v7, v8, v6
v_fma_f32 v9, -v5, v7, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v7, v9, v6
v_fma_f32 v5, -v5, v7, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fmas_f32 v5, v5, v6, v7
v_div_fixup_f32 v4, v5, v0, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_mul_f32_e32 v6, 0x40c90fdb, v4
v_add_co_u32 v4, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v3, vcc_lo
v_mul_f32_e32 v7, 0.15915494, v6
v_add_co_u32 v6, vcc_lo, s6, v2
v_add_co_u32 v2, s0, v2, s8
s_delay_alu instid0(VALU_DEP_3)
v_sin_f32_e32 v8, v7
v_add_co_ci_u32_e32 v7, vcc_lo, s7, v3, vcc_lo
v_cmp_lt_i32_e32 vcc_lo, s10, v1
v_add_co_ci_u32_e64 v3, s0, s9, v3, s0
global_store_b32 v[4:5], v8, off
global_store_b32 v[6:7], v8, off
s_or_b32 s1, vcc_lo, s1
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s1
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_set_inst_prefetch_distance 0x2
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9init_linePfS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 10
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9init_linePfS_i, .Lfunc_end0-_Z9init_linePfS_i
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z6updatePfS_ii
.globl _Z6updatePfS_ii
.p2align 8
.type _Z6updatePfS_ii,@function
_Z6updatePfS_ii:
s_load_b32 s12, s[0:1], 0x14
s_mov_b32 s13, 1
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s12, 1
s_cbranch_scc1 .LBB1_8
s_clause 0x3
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x18
s_load_b32 s14, s[0:1], 0x10
s_load_b128 s[4:7], s[0:1], 0x0
s_mov_b32 s11, 0x3ffd1eb8
s_mov_b32 s10, 0x51eb851f
s_waitcnt lgkmcnt(0)
s_and_b32 s0, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[1:2], null, s15, s0, v[0:1]
s_mul_i32 s2, s3, s0
s_ashr_i32 s3, s2, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_lshl_b64 s[8:9], s[2:3], 2
v_ashrrev_i32_e32 v2, 31, v1
v_cmp_ge_i32_e32 vcc_lo, s14, v1
s_delay_alu instid0(VALU_DEP_2)
v_lshlrev_b64 v[2:3], 2, v[1:2]
s_branch .LBB1_3
.LBB1_2:
s_or_b32 exec_lo, exec_lo, s3
s_add_i32 s0, s13, 1
s_cmp_lg_u32 s13, s12
s_mov_b32 s13, s0
s_cbranch_scc0 .LBB1_8
.LBB1_3:
s_and_saveexec_b32 s3, vcc_lo
s_cbranch_execz .LBB1_2
s_delay_alu instid0(VALU_DEP_1)
v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
v_mov_b32_e32 v0, v1
s_mov_b32 s15, 0
s_branch .LBB1_6
.LBB1_5:
s_or_b32 exec_lo, exec_lo, s1
v_add_co_u32 v7, s0, s4, v4
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v8, s0, s5, v5, s0
v_add_nc_u32_e32 v0, s2, v0
v_add_co_u32 v9, s0, s6, v4
global_load_b32 v11, v[7:8], off
v_add_co_ci_u32_e64 v10, s0, s7, v5, s0
v_cmp_lt_i32_e64 s0, s14, v0
v_add_co_u32 v4, s1, v4, s8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e64 v5, s1, s9, v5, s1
s_or_b32 s15, s0, s15
s_waitcnt vmcnt(0)
global_store_b32 v[9:10], v11, off
global_store_b32 v[7:8], v6, off
s_and_not1_b32 exec_lo, exec_lo, s15
s_cbranch_execz .LBB1_2
.LBB1_6:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_cmp_ne_u32_e64 s0, 1, v0
v_cmp_ne_u32_e64 s1, s14, v0
v_mov_b32_e32 v6, 0
s_and_b32 s0, s0, s1
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB1_5
v_add_co_u32 v6, s0, s4, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e64 v7, s0, s5, v5, s0
v_add_co_u32 v8, s0, s6, v4
v_add_co_ci_u32_e64 v9, s0, s7, v5, s0
global_load_b32 v6, v[6:7], off
global_load_b32 v8, v[8:9], off
s_waitcnt vmcnt(1)
v_cvt_f64_f32_e32 v[6:7], v6
s_waitcnt vmcnt(0)
v_cvt_f64_f32_e32 v[8:9], v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[6:7], v[6:7], s[10:11], -v[8:9]
v_cvt_f32_f64_e32 v6, v[6:7]
s_branch .LBB1_5
.LBB1_8:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6updatePfS_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 12
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z6updatePfS_ii, .Lfunc_end1-_Z6updatePfS_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9init_linePfS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9init_linePfS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 10
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6updatePfS_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6updatePfS_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 12
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00128a74_00000000-6_0856148.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "Enter number of points along vibrating string [%d-%d]: "
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "%s"
.section .rodata.str1.8
.align 8
.LC2:
.string "Invalid. Please enter value between %d and %d\n"
.align 8
.LC3:
.string "Enter number of time steps [1-%d]: "
.align 8
.LC4:
.string "Invalid. Please enter value between 1 and %d\n"
.align 8
.LC5:
.string "Using points = %d, steps = %d\n"
.text
.globl _Z11check_paramv
.type _Z11check_paramv, @function
_Z11check_paramv:
.LFB2057:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $32, %rsp
.cfi_def_cfa_offset 64
movq %fs:40, %rax
movq %rax, 24(%rsp)
xorl %eax, %eax
leaq .LC0(%rip), %r12
movq %rsp, %rbx
leaq .LC1(%rip), %rbp
.L5:
movl tpoints(%rip), %eax
subl $20, %eax
cmpl $999980, %eax
jbe .L14
movl $1000000, %ecx
movl $20, %edx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rbx, %rsi
movq %rbp, %rdi
movl $0, %eax
call __isoc23_scanf@PLT
movl $10, %edx
movl $0, %esi
movq %rbx, %rdi
call __isoc23_strtol@PLT
movl %eax, tpoints(%rip)
subl $20, %eax
cmpl $999980, %eax
jbe .L5
movl $1000000, %ecx
movl $20, %edx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L5
.L14:
leaq .LC3(%rip), %r12
movq %rsp, %rbx
leaq .LC1(%rip), %rbp
.L8:
movl nsteps(%rip), %ecx
leal -1(%rcx), %eax
cmpl $999999, %eax
jbe .L15
movl $1000000, %edx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rbx, %rsi
movq %rbp, %rdi
movl $0, %eax
call __isoc23_scanf@PLT
movl $10, %edx
movl $0, %esi
movq %rbx, %rdi
call __isoc23_strtol@PLT
movl %eax, nsteps(%rip)
subl $1, %eax
cmpl $999999, %eax
jbe .L8
movl $1000000, %edx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L8
.L15:
movl tpoints(%rip), %edx
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 24(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $32, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L16:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size _Z11check_paramv, .-_Z11check_paramv
.section .rodata.str1.1
.LC6:
.string "%6.4f "
.LC7:
.string "\n"
.text
.globl _Z10printfinalv
.type _Z10printfinalv, @function
_Z10printfinalv:
.LFB2058:
.cfi_startproc
endbr64
cmpl $0, tpoints(%rip)
jle .L23
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $8, %rsp
.cfi_def_cfa_offset 48
movl $1, %ebx
leaq values(%rip), %r12
leaq .LC6(%rip), %rbp
leaq .LC7(%rip), %r13
jmp .L20
.L19:
addq $1, %rbx
cmpl %ebx, tpoints(%rip)
jl .L26
.L20:
pxor %xmm0, %xmm0
cvtss2sd (%r12,%rbx,4), %xmm0
movq %rbp, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movslq %ebx, %rax
imulq $1717986919, %rax, %rax
sarq $34, %rax
movl %ebx, %edx
sarl $31, %edx
subl %edx, %eax
leal (%rax,%rax,4), %eax
addl %eax, %eax
cmpl %ebx, %eax
jne .L19
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L19
.L26:
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore 3
.cfi_restore 6
.cfi_restore 12
.cfi_restore 13
ret
.cfi_endproc
.LFE2058:
.size _Z10printfinalv, .-_Z10printfinalv
.globl _Z31__device_stub__Z9init_linePfS_iPfS_i
.type _Z31__device_stub__Z9init_linePfS_iPfS_i, @function
_Z31__device_stub__Z9init_linePfS_iPfS_i:
.LFB2084:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L31
.L27:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L32
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L31:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9init_linePfS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L27
.L32:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z31__device_stub__Z9init_linePfS_iPfS_i, .-_Z31__device_stub__Z9init_linePfS_iPfS_i
.globl _Z9init_linePfS_i
.type _Z9init_linePfS_i, @function
_Z9init_linePfS_i:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z9init_linePfS_iPfS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z9init_linePfS_i, .-_Z9init_linePfS_i
.globl _Z29__device_stub__Z6updatePfS_iiPfS_ii
.type _Z29__device_stub__Z6updatePfS_iiPfS_ii, @function
_Z29__device_stub__Z6updatePfS_iiPfS_ii:
.LFB2086:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L39
.L35:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L40
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L39:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6updatePfS_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L35
.L40:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2086:
.size _Z29__device_stub__Z6updatePfS_iiPfS_ii, .-_Z29__device_stub__Z6updatePfS_iiPfS_ii
.globl _Z6updatePfS_ii
.type _Z6updatePfS_ii, @function
_Z6updatePfS_ii:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z6updatePfS_iiPfS_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _Z6updatePfS_ii, .-_Z6updatePfS_ii
.section .rodata.str1.1
.LC8:
.string "%d"
.section .rodata.str1.8
.align 8
.LC9:
.string "Initializing points on the line...\n"
.section .rodata.str1.1
.LC10:
.string "%f\n"
.section .rodata.str1.8
.align 8
.LC11:
.string "Updating all points for all time steps...\n"
.section .rodata.str1.1
.LC12:
.string "Printing final results...\n"
.LC13:
.string "\nDone.\n\n"
.text
.globl main
.type main, @function
main:
.LFB2059:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $40, %rsp
.cfi_def_cfa_offset 80
movq %rsi, %rbx
movq 8(%rsi), %rdi
leaq tpoints(%rip), %rdx
leaq .LC8(%rip), %rbp
movq %rbp, %rsi
movl $0, %eax
call __isoc23_sscanf@PLT
movq 16(%rbx), %rdi
leaq nsteps(%rip), %rdx
movq %rbp, %rsi
movl $0, %eax
call __isoc23_sscanf@PLT
movl tpoints(%rip), %eax
leal 512(%rax), %r13d
addl $257, %eax
cmovns %eax, %r13d
sarl $8, %r13d
movl $4000008, %esi
leaq d_values(%rip), %rdi
call cudaMalloc@PLT
movl $4000008, %esi
leaq d_oldval(%rip), %rdi
call cudaMalloc@PLT
call _Z11check_paramv
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $256, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl %r13d, 8(%rsp)
movl $1, 12(%rsp)
movl $1, 16(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L50
.L44:
movl $2, %ecx
movl $4000008, %edx
movq d_values(%rip), %rsi
leaq values(%rip), %rdi
call cudaMemcpy@PLT
cmpl $0, tpoints(%rip)
jle .L45
movl $1, %ebx
leaq values(%rip), %r12
leaq .LC10(%rip), %rbp
.L46:
pxor %xmm0, %xmm0
cvtss2sd (%r12,%rbx,4), %xmm0
movq %rbp, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpl %ebx, tpoints(%rip)
jge .L46
.L45:
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $256, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl %r13d, 8(%rsp)
movl $1, 12(%rsp)
movl $1, 16(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L51
.L47:
leaq .LC12(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $2, %ecx
movl $4000008, %edx
movq d_values(%rip), %rsi
leaq values(%rip), %rdi
call cudaMemcpy@PLT
call _Z10printfinalv
leaq .LC13(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L50:
.cfi_restore_state
movl tpoints(%rip), %edx
movq d_oldval(%rip), %rsi
movq d_values(%rip), %rdi
call _Z31__device_stub__Z9init_linePfS_iPfS_i
jmp .L44
.L51:
movl nsteps(%rip), %ecx
movl tpoints(%rip), %edx
movq d_oldval(%rip), %rsi
movq d_values(%rip), %rdi
call _Z29__device_stub__Z6updatePfS_iiPfS_ii
jmp .L47
.cfi_endproc
.LFE2059:
.size main, .-main
.section .rodata.str1.1
.LC14:
.string "_Z6updatePfS_ii"
.LC15:
.string "_Z9init_linePfS_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2089:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC14(%rip), %rdx
movq %rdx, %rcx
leaq _Z6updatePfS_ii(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC15(%rip), %rdx
movq %rdx, %rcx
leaq _Z9init_linePfS_i(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2089:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl d_newval
.bss
.align 8
.type d_newval, @object
.size d_newval, 8
d_newval:
.zero 8
.globl d_oldval
.align 8
.type d_oldval, @object
.size d_oldval, 8
d_oldval:
.zero 8
.globl d_values
.align 8
.type d_values, @object
.size d_values, 8
d_values:
.zero 8
.globl newval
.align 32
.type newval, @object
.size newval, 4000008
newval:
.zero 4000008
.globl oldval
.align 32
.type oldval, @object
.size oldval, 4000008
oldval:
.zero 4000008
.globl values
.align 32
.type values, @object
.size values, 4000008
values:
.zero 4000008
.globl rcode
.align 4
.type rcode, @object
.size rcode, 4
rcode:
.zero 4
.globl tpoints
.align 4
.type tpoints, @object
.size tpoints, 4
tpoints:
.zero 4
.globl nsteps
.align 4
.type nsteps, @object
.size nsteps, 4
nsteps:
.zero 4
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "0856148.hip"
.globl _Z11check_paramv # -- Begin function _Z11check_paramv
.p2align 4, 0x90
.type _Z11check_paramv,@function
_Z11check_paramv: # @_Z11check_paramv
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $24, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -24
.cfi_offset %rbp, -16
movl $-1000001, %ebp # imm = 0xFFF0BDBF
movl tpoints(%rip), %eax
addl %ebp, %eax
cmpl $-999982, %eax # imm = 0xFFF0BDD2
ja .LBB0_5
# %bb.1:
movq %rsp, %rbx
jmp .LBB0_2
.p2align 4, 0x90
.LBB0_4: # in Loop: Header=BB0_2 Depth=1
movl tpoints(%rip), %eax
addl %ebp, %eax
cmpl $-999981, %eax # imm = 0xFFF0BDD3
jae .LBB0_5
.LBB0_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl $.L.str, %edi
movl $20, %esi
movl $1000000, %edx # imm = 0xF4240
xorl %eax, %eax
callq printf
movl $.L.str.1, %edi
movq %rbx, %rsi
xorl %eax, %eax
callq __isoc23_scanf
movq %rbx, %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movl %eax, tpoints(%rip)
addl $-1000001, %eax # imm = 0xFFF0BDBF
cmpl $-999982, %eax # imm = 0xFFF0BDD2
ja .LBB0_4
# %bb.3: # in Loop: Header=BB0_2 Depth=1
movl $.L.str.2, %edi
movl $20, %esi
movl $1000000, %edx # imm = 0xF4240
xorl %eax, %eax
callq printf
jmp .LBB0_4
.LBB0_5: # %.preheader
movl nsteps(%rip), %edx
leal -1000001(%rdx), %eax
cmpl $-1000001, %eax # imm = 0xFFF0BDBF
ja .LBB0_10
# %bb.6:
movq %rsp, %rbx
jmp .LBB0_7
.p2align 4, 0x90
.LBB0_9: # in Loop: Header=BB0_7 Depth=1
movl nsteps(%rip), %edx
leal -1000001(%rdx), %eax
cmpl $-1000000, %eax # imm = 0xFFF0BDC0
jae .LBB0_10
.LBB0_7: # %.lr.ph4
# =>This Inner Loop Header: Depth=1
movl $.L.str.3, %edi
movl $1000000, %esi # imm = 0xF4240
xorl %eax, %eax
callq printf
movl $.L.str.1, %edi
movq %rbx, %rsi
xorl %eax, %eax
callq __isoc23_scanf
movq %rbx, %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movl %eax, nsteps(%rip)
addl $-1000001, %eax # imm = 0xFFF0BDBF
cmpl $-1000001, %eax # imm = 0xFFF0BDBF
ja .LBB0_9
# %bb.8: # in Loop: Header=BB0_7 Depth=1
movl $.L.str.4, %edi
movl $1000000, %esi # imm = 0xF4240
xorl %eax, %eax
callq printf
jmp .LBB0_9
.LBB0_10: # %._crit_edge
movl tpoints(%rip), %esi
movl $.L.str.5, %edi
# kill: def $edx killed $edx killed $rdx
xorl %eax, %eax
callq printf
addq $24, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z11check_paramv, .Lfunc_end0-_Z11check_paramv
.cfi_endproc
# -- End function
.globl _Z24__device_stub__init_linePfS_i # -- Begin function _Z24__device_stub__init_linePfS_i
.p2align 4, 0x90
.type _Z24__device_stub__init_linePfS_i,@function
_Z24__device_stub__init_linePfS_i: # @_Z24__device_stub__init_linePfS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9init_linePfS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end1:
.size _Z24__device_stub__init_linePfS_i, .Lfunc_end1-_Z24__device_stub__init_linePfS_i
.cfi_endproc
# -- End function
.globl _Z21__device_stub__updatePfS_ii # -- Begin function _Z21__device_stub__updatePfS_ii
.p2align 4, 0x90
.type _Z21__device_stub__updatePfS_ii,@function
_Z21__device_stub__updatePfS_ii: # @_Z21__device_stub__updatePfS_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6updatePfS_ii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end2:
.size _Z21__device_stub__updatePfS_ii, .Lfunc_end2-_Z21__device_stub__updatePfS_ii
.cfi_endproc
# -- End function
.globl _Z10printfinalv # -- Begin function _Z10printfinalv
.p2align 4, 0x90
.type _Z10printfinalv,@function
_Z10printfinalv: # @_Z10printfinalv
.cfi_startproc
# %bb.0:
cmpl $0, tpoints(%rip)
jle .LBB3_6
# %bb.1: # %.lr.ph.preheader
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
pushq %rax
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $1, %ebx
xorl %r14d, %r14d
movl $3435973837, %r15d # imm = 0xCCCCCCCD
jmp .LBB3_2
.p2align 4, 0x90
.LBB3_4: # in Loop: Header=BB3_2 Depth=1
movslq tpoints(%rip), %rax
incq %r14
incl %ebx
cmpq %rax, %r14
jge .LBB3_5
.LBB3_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl %ebx, %eax
imulq %r15, %rax
shrq $35, %rax
leal (%rax,%rax,4), %eax
leal -1(,%rax,2), %ebp
movss values+4(,%r14,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.6, %edi
movb $1, %al
callq printf
cmpl %r14d, %ebp
jne .LBB3_4
# %bb.3: # in Loop: Header=BB3_2 Depth=1
movl $10, %edi
callq putchar@PLT
jmp .LBB3_4
.LBB3_5:
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r14
.cfi_restore %r15
.cfi_restore %rbp
.LBB3_6: # %._crit_edge
retq
.Lfunc_end3:
.size _Z10printfinalv, .Lfunc_end3-_Z10printfinalv
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $120, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %r14
movabsq $4294967552, %rbx # imm = 0x100000100
movq 8(%rsi), %rdi
movl $.L.str.8, %esi
movl $tpoints, %edx
xorl %eax, %eax
callq __isoc23_sscanf
movq 16(%r14), %rdi
movl $.L.str.8, %esi
movl $nsteps, %edx
xorl %eax, %eax
callq __isoc23_sscanf
movl tpoints(%rip), %r14d
leal 257(%r14), %eax
addl $512, %r14d # imm = 0x200
testl %eax, %eax
cmovnsl %eax, %r14d
sarl $8, %r14d
movl $d_values, %edi
movl $4000008, %esi # imm = 0x3D0908
callq hipMalloc
movl $d_oldval, %edi
movl $4000008, %esi # imm = 0x3D0908
callq hipMalloc
callq _Z11check_paramv
movl $.Lstr, %edi
callq puts@PLT
addq %rbx, %r14
addq $-256, %r14
movq %r14, %rdi
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_2
# %bb.1:
movq d_values(%rip), %rax
movq d_oldval(%rip), %rcx
movl tpoints(%rip), %edx
movq %rax, 64(%rsp)
movq %rcx, 56(%rsp)
movl %edx, 4(%rsp)
leaq 64(%rsp), %rax
movq %rax, 80(%rsp)
leaq 56(%rsp), %rax
movq %rax, 88(%rsp)
leaq 4(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9init_linePfS_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_2:
movq d_values(%rip), %rsi
movl $values, %edi
movl $4000008, %edx # imm = 0x3D0908
movl $2, %ecx
callq hipMemcpy
cmpl $0, tpoints(%rip)
jle .LBB4_5
# %bb.3: # %.lr.ph.preheader
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB4_4: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movss values+4(,%r15,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.10, %edi
movb $1, %al
callq printf
movslq tpoints(%rip), %rax
incq %r15
cmpq %rax, %r15
jl .LBB4_4
.LBB4_5: # %._crit_edge
movl $.Lstr.1, %edi
callq puts@PLT
movq %r14, %rdi
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_7
# %bb.6:
movq d_values(%rip), %rax
movq d_oldval(%rip), %rcx
movl tpoints(%rip), %edx
movl nsteps(%rip), %esi
movq %rax, 64(%rsp)
movq %rcx, 56(%rsp)
movl %edx, 4(%rsp)
movl %esi, 76(%rsp)
leaq 64(%rsp), %rax
movq %rax, 80(%rsp)
leaq 56(%rsp), %rax
movq %rax, 88(%rsp)
leaq 4(%rsp), %rax
movq %rax, 96(%rsp)
leaq 76(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6updatePfS_ii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_7:
movl $.Lstr.2, %edi
callq puts@PLT
movq d_values(%rip), %rsi
movl $values, %edi
movl $4000008, %edx # imm = 0x3D0908
movl $2, %ecx
callq hipMemcpy
cmpl $0, tpoints(%rip)
jle .LBB4_12
# %bb.8: # %.lr.ph.i.preheader
movl $1, %ebx
xorl %r14d, %r14d
movl $3435973837, %r15d # imm = 0xCCCCCCCD
jmp .LBB4_9
.p2align 4, 0x90
.LBB4_11: # in Loop: Header=BB4_9 Depth=1
movslq tpoints(%rip), %rax
incq %r14
incl %ebx
cmpq %rax, %r14
jge .LBB4_12
.LBB4_9: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
movl %ebx, %eax
imulq %r15, %rax
shrq $35, %rax
leal (%rax,%rax,4), %eax
leal -1(,%rax,2), %ebp
movss values+4(,%r14,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.6, %edi
movb $1, %al
callq printf
cmpl %r14d, %ebp
jne .LBB4_11
# %bb.10: # in Loop: Header=BB4_9 Depth=1
movl $10, %edi
callq putchar@PLT
jmp .LBB4_11
.LBB4_12: # %_Z10printfinalv.exit
movl $.Lstr.3, %edi
callq puts@PLT
xorl %eax, %eax
addq $120, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end4:
.size main, .Lfunc_end4-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9init_linePfS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6updatePfS_ii, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type nsteps,@object # @nsteps
.bss
.globl nsteps
.p2align 2, 0x0
nsteps:
.long 0 # 0x0
.size nsteps, 4
.type tpoints,@object # @tpoints
.globl tpoints
.p2align 2, 0x0
tpoints:
.long 0 # 0x0
.size tpoints, 4
.type rcode,@object # @rcode
.globl rcode
.p2align 2, 0x0
rcode:
.long 0 # 0x0
.size rcode, 4
.type values,@object # @values
.globl values
.p2align 4, 0x0
values:
.zero 4000008
.size values, 4000008
.type oldval,@object # @oldval
.globl oldval
.p2align 4, 0x0
oldval:
.zero 4000008
.size oldval, 4000008
.type newval,@object # @newval
.globl newval
.p2align 4, 0x0
newval:
.zero 4000008
.size newval, 4000008
.type d_values,@object # @d_values
.globl d_values
.p2align 3, 0x0
d_values:
.quad 0
.size d_values, 8
.type d_oldval,@object # @d_oldval
.globl d_oldval
.p2align 3, 0x0
d_oldval:
.quad 0
.size d_oldval, 8
.type d_newval,@object # @d_newval
.globl d_newval
.p2align 3, 0x0
d_newval:
.quad 0
.size d_newval, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Enter number of points along vibrating string [%d-%d]: "
.size .L.str, 56
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "%s"
.size .L.str.1, 3
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Invalid. Please enter value between %d and %d\n"
.size .L.str.2, 47
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Enter number of time steps [1-%d]: "
.size .L.str.3, 36
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Invalid. Please enter value between 1 and %d\n"
.size .L.str.4, 46
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Using points = %d, steps = %d\n"
.size .L.str.5, 31
.type _Z9init_linePfS_i,@object # @_Z9init_linePfS_i
.section .rodata,"a",@progbits
.globl _Z9init_linePfS_i
.p2align 3, 0x0
_Z9init_linePfS_i:
.quad _Z24__device_stub__init_linePfS_i
.size _Z9init_linePfS_i, 8
.type _Z6updatePfS_ii,@object # @_Z6updatePfS_ii
.globl _Z6updatePfS_ii
.p2align 3, 0x0
_Z6updatePfS_ii:
.quad _Z21__device_stub__updatePfS_ii
.size _Z6updatePfS_ii, 8
.type .L.str.6,@object # @.str.6
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.6:
.asciz "%6.4f "
.size .L.str.6, 7
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "%d"
.size .L.str.8, 3
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "%f\n"
.size .L.str.10, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z9init_linePfS_i"
.size .L__unnamed_1, 18
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z6updatePfS_ii"
.size .L__unnamed_2, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Initializing points on the line..."
.size .Lstr, 35
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "Updating all points for all time steps..."
.size .Lstr.1, 42
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "Printing final results..."
.size .Lstr.2, 26
.type .Lstr.3,@object # @str.3
.Lstr.3:
.asciz "\nDone.\n"
.size .Lstr.3, 8
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__init_linePfS_i
.addrsig_sym _Z21__device_stub__updatePfS_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym nsteps
.addrsig_sym tpoints
.addrsig_sym values
.addrsig_sym d_values
.addrsig_sym d_oldval
.addrsig_sym _Z9init_linePfS_i
.addrsig_sym _Z6updatePfS_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | // REQUIRES: clang-driver
// RUN: %clang -### -emit-llvm --cuda-device-only \
// RUN: -nocudalib -nocudainc --offload=spirv32-unknown-unknown -c %s 2>&1 | FileCheck %s
// CHECK: "-cc1" "-triple" "spirv32-unknown-unknown" {{.*}} "-fcuda-is-device" {{.*}} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | // REQUIRES: clang-driver
// RUN: %clang -### -emit-llvm --cuda-device-only \
// RUN: -nocudalib -nocudainc --offload=spirv32-unknown-unknown -c %s 2>&1 | FileCheck %s
// CHECK: "-cc1" "-triple" "spirv32-unknown-unknown" {{.*}} "-fcuda-is-device" {{.*}} | .file "tmpxft_0016a9d4_00000000-6_cuda-device-triple.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | // REQUIRES: clang-driver
// RUN: %clang -### -emit-llvm --cuda-device-only \
// RUN: -nocudalib -nocudainc --offload=spirv32-unknown-unknown -c %s 2>&1 | FileCheck %s
// CHECK: "-cc1" "-triple" "spirv32-unknown-unknown" {{.*}} "-fcuda-is-device" {{.*}} | #include <hip/hip_runtime.h>
// REQUIRES: clang-driver
// RUN: %clang -### -emit-llvm --cuda-device-only \
// RUN: -nocudalib -nocudainc --offload=spirv32-unknown-unknown -c %s 2>&1 | FileCheck %s
// CHECK: "-cc1" "-triple" "spirv32-unknown-unknown" {{.*}} "-fcuda-is-device" {{.*}} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
// REQUIRES: clang-driver
// RUN: %clang -### -emit-llvm --cuda-device-only \
// RUN: -nocudalib -nocudainc --offload=spirv32-unknown-unknown -c %s 2>&1 | FileCheck %s
// CHECK: "-cc1" "-triple" "spirv32-unknown-unknown" {{.*}} "-fcuda-is-device" {{.*}} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
// REQUIRES: clang-driver
// RUN: %clang -### -emit-llvm --cuda-device-only \
// RUN: -nocudalib -nocudainc --offload=spirv32-unknown-unknown -c %s 2>&1 | FileCheck %s
// CHECK: "-cc1" "-triple" "spirv32-unknown-unknown" {{.*}} "-fcuda-is-device" {{.*}} | .text
.file "cuda-device-triple.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0016a9d4_00000000-6_cuda-device-triple.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "cuda-device-triple.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void Saxx_device(float* x, float* c, float xb, int n)
{
int i = threadIdx.x;
if (i < n)
c[i] = (x[i] - xb) * (x[i] - xb);
} | code for sm_80
Function : _Z11Saxx_devicePfS_fi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_TID.X ; /* 0x0000000000047919 */
/* 0x000e240000002100 */
/*0020*/ ISETP.GE.AND P0, PT, R4, c[0x0][0x174], PT ; /* 0x00005d0004007a0c */
/* 0x001fda0003f06270 */
/*0030*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0040*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0050*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0060*/ IMAD.WIDE R2, R4, R5, c[0x0][0x160] ; /* 0x0000580004027625 */
/* 0x000fcc00078e0205 */
/*0070*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*0080*/ IMAD.WIDE R4, R4, R5, c[0x0][0x168] ; /* 0x00005a0004047625 */
/* 0x000fc800078e0205 */
/*0090*/ FADD R0, R2, -c[0x0][0x170] ; /* 0x80005c0002007621 */
/* 0x004fc80000000000 */
/*00a0*/ FMUL R7, R0, R0 ; /* 0x0000000000077220 */
/* 0x000fca0000400000 */
/*00b0*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x000fe2000c101904 */
/*00c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00d0*/ BRA 0xd0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void Saxx_device(float* x, float* c, float xb, int n)
{
int i = threadIdx.x;
if (i < n)
c[i] = (x[i] - xb) * (x[i] - xb);
} | .file "tmpxft_0015518e_00000000-6_Saxx_device.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z35__device_stub__Z11Saxx_devicePfS_fiPfS_fi
.type _Z35__device_stub__Z11Saxx_devicePfS_fiPfS_fi, @function
_Z35__device_stub__Z11Saxx_devicePfS_fiPfS_fi:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movss %xmm0, 12(%rsp)
movl %edx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z11Saxx_devicePfS_fi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z35__device_stub__Z11Saxx_devicePfS_fiPfS_fi, .-_Z35__device_stub__Z11Saxx_devicePfS_fiPfS_fi
.globl _Z11Saxx_devicePfS_fi
.type _Z11Saxx_devicePfS_fi, @function
_Z11Saxx_devicePfS_fi:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z11Saxx_devicePfS_fiPfS_fi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z11Saxx_devicePfS_fi, .-_Z11Saxx_devicePfS_fi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z11Saxx_devicePfS_fi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z11Saxx_devicePfS_fi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void Saxx_device(float* x, float* c, float xb, int n)
{
int i = threadIdx.x;
if (i < n)
c[i] = (x[i] - xb) * (x[i] - xb);
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void Saxx_device(float* x, float* c, float xb, int n)
{
int i = threadIdx.x;
if (i < n)
c[i] = (x[i] - xb) * (x[i] - xb);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void Saxx_device(float* x, float* c, float xb, int n)
{
int i = threadIdx.x;
if (i < n)
c[i] = (x[i] - xb) * (x[i] - xb);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11Saxx_devicePfS_fi
.globl _Z11Saxx_devicePfS_fi
.p2align 8
.type _Z11Saxx_devicePfS_fi,@function
_Z11Saxx_devicePfS_fi:
s_load_b32 s2, s[0:1], 0x14
s_waitcnt lgkmcnt(0)
v_cmp_gt_i32_e32 vcc_lo, s2, v0
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_2
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b32 s0, s[0:1], 0x10
v_lshlrev_b32_e32 v0, 2, v0
s_waitcnt lgkmcnt(0)
global_load_b32 v1, v0, s[4:5]
s_waitcnt vmcnt(0)
v_subrev_f32_e32 v1, s0, v1
s_delay_alu instid0(VALU_DEP_1)
v_mul_f32_e32 v1, v1, v1
global_store_b32 v0, v1, s[6:7]
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11Saxx_devicePfS_fi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 8
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z11Saxx_devicePfS_fi, .Lfunc_end0-_Z11Saxx_devicePfS_fi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11Saxx_devicePfS_fi
.private_segment_fixed_size: 0
.sgpr_count: 10
.sgpr_spill_count: 0
.symbol: _Z11Saxx_devicePfS_fi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void Saxx_device(float* x, float* c, float xb, int n)
{
int i = threadIdx.x;
if (i < n)
c[i] = (x[i] - xb) * (x[i] - xb);
} | .text
.file "Saxx_device.hip"
.globl _Z26__device_stub__Saxx_devicePfS_fi # -- Begin function _Z26__device_stub__Saxx_devicePfS_fi
.p2align 4, 0x90
.type _Z26__device_stub__Saxx_devicePfS_fi,@function
_Z26__device_stub__Saxx_devicePfS_fi: # @_Z26__device_stub__Saxx_devicePfS_fi
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movss %xmm0, 12(%rsp)
movl %edx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z11Saxx_devicePfS_fi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z26__device_stub__Saxx_devicePfS_fi, .Lfunc_end0-_Z26__device_stub__Saxx_devicePfS_fi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11Saxx_devicePfS_fi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z11Saxx_devicePfS_fi,@object # @_Z11Saxx_devicePfS_fi
.section .rodata,"a",@progbits
.globl _Z11Saxx_devicePfS_fi
.p2align 3, 0x0
_Z11Saxx_devicePfS_fi:
.quad _Z26__device_stub__Saxx_devicePfS_fi
.size _Z11Saxx_devicePfS_fi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z11Saxx_devicePfS_fi"
.size .L__unnamed_1, 22
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__Saxx_devicePfS_fi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11Saxx_devicePfS_fi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z11Saxx_devicePfS_fi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_TID.X ; /* 0x0000000000047919 */
/* 0x000e240000002100 */
/*0020*/ ISETP.GE.AND P0, PT, R4, c[0x0][0x174], PT ; /* 0x00005d0004007a0c */
/* 0x001fda0003f06270 */
/*0030*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0040*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0050*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0060*/ IMAD.WIDE R2, R4, R5, c[0x0][0x160] ; /* 0x0000580004027625 */
/* 0x000fcc00078e0205 */
/*0070*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*0080*/ IMAD.WIDE R4, R4, R5, c[0x0][0x168] ; /* 0x00005a0004047625 */
/* 0x000fc800078e0205 */
/*0090*/ FADD R0, R2, -c[0x0][0x170] ; /* 0x80005c0002007621 */
/* 0x004fc80000000000 */
/*00a0*/ FMUL R7, R0, R0 ; /* 0x0000000000077220 */
/* 0x000fca0000400000 */
/*00b0*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x000fe2000c101904 */
/*00c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00d0*/ BRA 0xd0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11Saxx_devicePfS_fi
.globl _Z11Saxx_devicePfS_fi
.p2align 8
.type _Z11Saxx_devicePfS_fi,@function
_Z11Saxx_devicePfS_fi:
s_load_b32 s2, s[0:1], 0x14
s_waitcnt lgkmcnt(0)
v_cmp_gt_i32_e32 vcc_lo, s2, v0
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_2
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b32 s0, s[0:1], 0x10
v_lshlrev_b32_e32 v0, 2, v0
s_waitcnt lgkmcnt(0)
global_load_b32 v1, v0, s[4:5]
s_waitcnt vmcnt(0)
v_subrev_f32_e32 v1, s0, v1
s_delay_alu instid0(VALU_DEP_1)
v_mul_f32_e32 v1, v1, v1
global_store_b32 v0, v1, s[6:7]
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11Saxx_devicePfS_fi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 8
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z11Saxx_devicePfS_fi, .Lfunc_end0-_Z11Saxx_devicePfS_fi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11Saxx_devicePfS_fi
.private_segment_fixed_size: 0
.sgpr_count: 10
.sgpr_spill_count: 0
.symbol: _Z11Saxx_devicePfS_fi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0015518e_00000000-6_Saxx_device.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z35__device_stub__Z11Saxx_devicePfS_fiPfS_fi
.type _Z35__device_stub__Z11Saxx_devicePfS_fiPfS_fi, @function
_Z35__device_stub__Z11Saxx_devicePfS_fiPfS_fi:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movss %xmm0, 12(%rsp)
movl %edx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z11Saxx_devicePfS_fi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z35__device_stub__Z11Saxx_devicePfS_fiPfS_fi, .-_Z35__device_stub__Z11Saxx_devicePfS_fiPfS_fi
.globl _Z11Saxx_devicePfS_fi
.type _Z11Saxx_devicePfS_fi, @function
_Z11Saxx_devicePfS_fi:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z11Saxx_devicePfS_fiPfS_fi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z11Saxx_devicePfS_fi, .-_Z11Saxx_devicePfS_fi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z11Saxx_devicePfS_fi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z11Saxx_devicePfS_fi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "Saxx_device.hip"
.globl _Z26__device_stub__Saxx_devicePfS_fi # -- Begin function _Z26__device_stub__Saxx_devicePfS_fi
.p2align 4, 0x90
.type _Z26__device_stub__Saxx_devicePfS_fi,@function
_Z26__device_stub__Saxx_devicePfS_fi: # @_Z26__device_stub__Saxx_devicePfS_fi
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movss %xmm0, 12(%rsp)
movl %edx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z11Saxx_devicePfS_fi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z26__device_stub__Saxx_devicePfS_fi, .Lfunc_end0-_Z26__device_stub__Saxx_devicePfS_fi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11Saxx_devicePfS_fi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z11Saxx_devicePfS_fi,@object # @_Z11Saxx_devicePfS_fi
.section .rodata,"a",@progbits
.globl _Z11Saxx_devicePfS_fi
.p2align 3, 0x0
_Z11Saxx_devicePfS_fi:
.quad _Z26__device_stub__Saxx_devicePfS_fi
.size _Z11Saxx_devicePfS_fi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z11Saxx_devicePfS_fi"
.size .L__unnamed_1, 22
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__Saxx_devicePfS_fi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11Saxx_devicePfS_fi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <iostream>
#include <stdio.h>
#include <time.h>
#include <cuda_runtime.h>
#include <math.h>
__global__ void matrixMultiplicationKernel(int* A,int* B,int* C,int N)
{
int ROW = blockIdx.y*blockDim.y+threadIdx.y;
int COL = blockIdx.x*blockDim.x+threadIdx.x;
float tmp_sum = 0.0f;
if(ROW < N && COL < N){
for(int i=0;i<N;i++){
tmp_sum += A[ROW*N+i] *B[i*N+COL];
}
}
C[ROW*N+COL] = tmp_sum;
}
void matrixMultiplication(int* A,int* B,int* C,int N);
int main()
{
int N = 16;
//Host i/o vectors
int *h_A;
int *h_B;
int *h_C;
//Device i/o vector
int *d_A;
int *d_B;
int *d_C;
size_t bytes = N*N*sizeof(int);
h_A = (int*)malloc(bytes);
h_B = (int*)malloc(bytes);
h_C = (int*)malloc(bytes);
cudaMalloc(&d_A,bytes);
cudaMalloc(&d_B,bytes);
cudaMalloc(&d_C,bytes);
// Initialize matricies on the host
for(int i=0;i<N;i++){
for(int j=0;j<N;j++){
h_A[i*N+j] = 2;
h_B[i*N+j] = 3;
}
}
//Copy host vectors to device
cudaMemcpy(d_A,h_A,bytes,cudaMemcpyHostToDevice);
cudaMemcpy(d_B,h_B,bytes,cudaMemcpyHostToDevice);
matrixMultiplication(d_A,d_B,d_C,N);
cudaMemcpy(h_C,d_C,bytes,cudaMemcpyDeviceToHost);
//check result
for(int i=0;i<4;i++){
for(int j=0;j<4;j++){
printf(" %d",h_C[i*N+j]);
}
printf("\n");
}
// Free device memory
cudaFree(d_A);
cudaFree(d_B);
cudaFree(d_C);
//free host memory
free(h_A);
free(h_B);
free(h_C);
return 0;
}
void matrixMultiplication(int* A,int* B,int* C,int N)
{
dim3 threadsPerBlock(N,N);
dim3 blocksPerGrid(1,1);
if(N*N>512){
threadsPerBlock.x = 512;
threadsPerBlock.y = 512;
blocksPerGrid.x = ceil(int(N)/double(threadsPerBlock.x));
blocksPerGrid.y = ceil(int(N)/double(threadsPerBlock.y));
}
matrixMultiplicationKernel<<<blocksPerGrid,threadsPerBlock>>>(A,B,C,N);
} | code for sm_80
Function : _Z26matrixMultiplicationKernelPiS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0030*/ BSSY B0, 0xfd0 ; /* 0x00000f9000007945 */
/* 0x000fe20003800000 */
/*0040*/ HFMA2.MMA R11, -RZ, RZ, 0, 0 ; /* 0x00000000ff0b7435 */
/* 0x000fe200000001ff */
/*0050*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e280000002100 */
/*0060*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e680000002600 */
/*0070*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e620000002200 */
/*0080*/ IMAD R0, R0, c[0x0][0x0], R5 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0205 */
/*0090*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x178], PT ; /* 0x00005e0000007a0c */
/* 0x000fe20003f06270 */
/*00a0*/ IMAD R3, R3, c[0x0][0x4], R2 ; /* 0x0000010003037a24 */
/* 0x002fe200078e0202 */
/*00b0*/ MOV R2, c[0x0][0x178] ; /* 0x00005e0000027a02 */
/* 0x000fc80000000f00 */
/*00c0*/ ISETP.GE.OR P0, PT, R3, c[0x0][0x178], P0 ; /* 0x00005e0003007a0c */
/* 0x000fc80000706670 */
/*00d0*/ ISETP.LT.OR P0, PT, R2, 0x1, P0 ; /* 0x000000010200780c */
/* 0x000fda0000701670 */
/*00e0*/ @P0 BRA 0xfc0 ; /* 0x00000ed000000947 */
/* 0x000fea0003800000 */
/*00f0*/ IADD3 R4, R2.reuse, -0x1, RZ ; /* 0xffffffff02047810 */
/* 0x040fe40007ffe0ff */
/*0100*/ LOP3.LUT R5, R2, 0x3, RZ, 0xc0, !PT ; /* 0x0000000302057812 */
/* 0x000fe400078ec0ff */
/*0110*/ ISETP.GE.U32.AND P0, PT, R4, 0x3, PT ; /* 0x000000030400780c */
/* 0x000fe40003f06070 */
/*0120*/ MOV R11, RZ ; /* 0x000000ff000b7202 */
/* 0x000fe40000000f00 */
/*0130*/ MOV R4, RZ ; /* 0x000000ff00047202 */
/* 0x000fd20000000f00 */
/*0140*/ @!P0 BRA 0xe80 ; /* 0x00000d3000008947 */
/* 0x000fea0003800000 */
/*0150*/ IADD3 R7, -R5, c[0x0][0x178], RZ ; /* 0x00005e0005077a10 */
/* 0x000fe20007ffe1ff */
/*0160*/ HFMA2.MMA R23, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff177435 */
/* 0x000fe200000001ff */
/*0170*/ ULDC.64 UR6, c[0x0][0x160] ; /* 0x0000580000067ab9 */
/* 0x000fe20000000a00 */
/*0180*/ HFMA2.MMA R4, -RZ, RZ, 0, 0 ; /* 0x00000000ff047435 */
/* 0x000fe200000001ff */
/*0190*/ ISETP.GT.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fe20003f04270 */
/*01a0*/ IMAD R6, R3, c[0x0][0x178], RZ ; /* 0x00005e0003067a24 */
/* 0x000fe200078e02ff */
/*01b0*/ MOV R11, RZ ; /* 0x000000ff000b7202 */
/* 0x000fca0000000f00 */
/*01c0*/ IMAD.WIDE R22, R0, R23, c[0x0][0x168] ; /* 0x00005a0000167625 */
/* 0x000fcc00078e0217 */
/*01d0*/ @!P0 BRA 0xc70 ; /* 0x00000a9000008947 */
/* 0x000fea0003800000 */
/*01e0*/ ISETP.GT.AND P1, PT, R7, 0xc, PT ; /* 0x0000000c0700780c */
/* 0x000fe40003f24270 */
/*01f0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*0200*/ @!P1 BRA 0x8b0 ; /* 0x000006a000009947 */
/* 0x000fea0003800000 */
/*0210*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0220*/ MOV R14, UR6 ; /* 0x00000006000e7c02 */
/* 0x000fe20008000f00 */
/*0230*/ IMAD.WIDE R16, R2, 0x4, R22 ; /* 0x0000000402107825 */
/* 0x000fe200078e0216 */
/*0240*/ MOV R15, UR7 ; /* 0x00000007000f7c02 */
/* 0x000fe20008000f00 */
/*0250*/ LDG.E R8, [R22.64] ; /* 0x0000000416087981 */
/* 0x0000a8000c1e1900 */
/*0260*/ IMAD.WIDE R14, R6, 0x4, R14 ; /* 0x00000004060e7825 */
/* 0x000fe200078e020e */
/*0270*/ LDG.E R10, [R16.64] ; /* 0x00000004100a7981 */
/* 0x0002e8000c1e1900 */
/*0280*/ LDG.E R9, [R14.64] ; /* 0x000000040e097981 */
/* 0x000ea2000c1e1900 */
/*0290*/ IMAD.WIDE R12, R2, 0x4, R16 ; /* 0x00000004020c7825 */
/* 0x000fc600078e0210 */
/*02a0*/ LDG.E R29, [R14.64+0x4] ; /* 0x000004040e1d7981 */
/* 0x000ee8000c1e1900 */
/*02b0*/ LDG.E R26, [R12.64] ; /* 0x000000040c1a7981 */
/* 0x000968000c1e1900 */
/*02c0*/ LDG.E R27, [R14.64+0x8] ; /* 0x000008040e1b7981 */
/* 0x000f68000c1e1900 */
/*02d0*/ LDG.E R21, [R14.64+0xc] ; /* 0x00000c040e157981 */
/* 0x000f62000c1e1900 */
/*02e0*/ IMAD.WIDE R12, R2, 0x4, R12 ; /* 0x00000004020c7825 */
/* 0x010fc600078e020c */
/*02f0*/ LDG.E R23, [R14.64+0x14] ; /* 0x000014040e177981 */
/* 0x001f28000c1e1900 */
/*0300*/ LDG.E R20, [R12.64] ; /* 0x000000040c147981 */
/* 0x000122000c1e1900 */
/*0310*/ IMAD.WIDE R18, R2, 0x4, R12 ; /* 0x0000000402127825 */
/* 0x000fc600078e020c */
/*0320*/ LDG.E R25, [R14.64+0x10] ; /* 0x000010040e197981 */
/* 0x000f26000c1e1900 */
/*0330*/ IMAD.WIDE R16, R2.reuse, 0x4, R18 ; /* 0x0000000402107825 */
/* 0x042fe200078e0212 */
/*0340*/ LDG.E R22, [R18.64] ; /* 0x0000000412167981 */
/* 0x000328000c1e1900 */
/*0350*/ LDG.E R24, [R16.64] ; /* 0x0000000410187981 */
/* 0x000322000c1e1900 */
/*0360*/ IMAD.WIDE R12, R2, 0x4, R16 ; /* 0x00000004020c7825 */
/* 0x001fc800078e0210 */
/*0370*/ IMAD R8, R8, R9, RZ ; /* 0x0000000908087224 */
/* 0x004fe400078e02ff */
/*0380*/ IMAD R10, R10, R29, RZ ; /* 0x0000001d0a0a7224 */
/* 0x008fc800078e02ff */
/*0390*/ I2F R8, R8 ; /* 0x0000000800087306 */
/* 0x000e220000201400 */
/*03a0*/ IMAD R26, R26, R27, RZ ; /* 0x0000001b1a1a7224 */
/* 0x020fce00078e02ff */
/*03b0*/ I2F R18, R10 ; /* 0x0000000a00127306 */
/* 0x0028620000201400 */
/*03c0*/ IMAD.WIDE R28, R2, 0x4, R12 ; /* 0x00000004021c7825 */
/* 0x000fe200078e020c */
/*03d0*/ LDG.E R27, [R12.64] ; /* 0x000000040c1b7981 */
/* 0x0004ec000c1e1900 */
/*03e0*/ I2F R26, R26 ; /* 0x0000001a001a7306 */
/* 0x000f620000201400 */
/*03f0*/ IMAD R10, R20, R21, RZ ; /* 0x00000015140a7224 */
/* 0x010fe400078e02ff */
/*0400*/ FADD R11, R8, R11 ; /* 0x0000000b080b7221 */
/* 0x001fe20000000000 */
/*0410*/ LDG.E R20, [R14.64+0x18] ; /* 0x000018040e147981 */
/* 0x000ee2000c1e1900 */
/*0420*/ IMAD.WIDE R8, R2, 0x4, R28 ; /* 0x0000000402087825 */
/* 0x000fc600078e021c */
/*0430*/ I2F R10, R10 ; /* 0x0000000a000a7306 */
/* 0x000e220000201400 */
/*0440*/ LDG.E R28, [R28.64] ; /* 0x000000041c1c7981 */
/* 0x000f22000c1e1900 */
/*0450*/ FADD R11, R11, R18 ; /* 0x000000120b0b7221 */
/* 0x002fe40000000000 */
/*0460*/ IMAD.WIDE R18, R2.reuse, 0x4, R8 ; /* 0x0000000402127825 */
/* 0x040fe200078e0208 */
/*0470*/ LDG.E R21, [R14.64+0x1c] ; /* 0x00001c040e157981 */
/* 0x000f26000c1e1900 */
/*0480*/ FADD R11, R11, R26 ; /* 0x0000001a0b0b7221 */
/* 0x020fe20000000000 */
/*0490*/ LDG.E R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x000362000c1e1900 */
/*04a0*/ IMAD.WIDE R16, R2, 0x4, R18 ; /* 0x0000000402107825 */
/* 0x000fc600078e0212 */
/*04b0*/ LDG.E R12, [R14.64+0x24] ; /* 0x000024040e0c7981 */
/* 0x004ea2000c1e1900 */
/*04c0*/ FADD R10, R11, R10 ; /* 0x0000000a0b0a7221 */
/* 0x001fc60000000000 */
/*04d0*/ LDG.E R13, [R16.64] ; /* 0x00000004100d7981 */
/* 0x0000a8000c1e1900 */
/*04e0*/ LDG.E R9, [R18.64] ; /* 0x0000000412097981 */
/* 0x0022a8000c1e1900 */
/*04f0*/ LDG.E R11, [R14.64+0x20] ; /* 0x000020040e0b7981 */
/* 0x000f62000c1e1900 */
/*0500*/ IMAD.WIDE R16, R2, 0x4, R16 ; /* 0x0000000402107825 */
/* 0x001fc800078e0210 */
/*0510*/ IMAD R23, R24, R23, RZ ; /* 0x0000001718177224 */
/* 0x000fe200078e02ff */
/*0520*/ LDG.E R26, [R16.64] ; /* 0x00000004101a7981 */
/* 0x000162000c1e1900 */
/*0530*/ IMAD R22, R22, R25, RZ ; /* 0x0000001916167224 */
/* 0x000fc600078e02ff */
/*0540*/ LDG.E R24, [R14.64+0x28] ; /* 0x000028040e187981 */
/* 0x000f68000c1e1900 */
/*0550*/ LDG.E R25, [R14.64+0x2c] ; /* 0x00002c040e197981 */
/* 0x000f62000c1e1900 */
/*0560*/ IMAD.WIDE R18, R2, 0x4, R16 ; /* 0x0000000402127825 */
/* 0x002fc600078e0210 */
/*0570*/ LDG.E R17, [R14.64+0x30] ; /* 0x000030040e117981 */
/* 0x001162000c1e1900 */
/*0580*/ IMAD R27, R27, R20, RZ ; /* 0x000000141b1b7224 */
/* 0x008fe400078e02ff */
/*0590*/ IMAD R29, R28, R21, RZ ; /* 0x000000151c1d7224 */
/* 0x010fe400078e02ff */
/*05a0*/ IMAD.WIDE R20, R2, 0x4, R18 ; /* 0x0000000402147825 */
/* 0x000fe200078e0212 */
/*05b0*/ LDG.E R28, [R18.64] ; /* 0x00000004121c7981 */
/* 0x0002e8000c1e1900 */
/*05c0*/ LDG.E R18, [R20.64] ; /* 0x0000000414127981 */
/* 0x002322000c1e1900 */
/*05d0*/ IMAD R16, R9, R12, RZ ; /* 0x0000000c09107224 */
/* 0x004fc600078e02ff */
/*05e0*/ LDG.E R19, [R14.64+0x34] ; /* 0x000034040e137981 */
/* 0x000122000c1e1900 */
/*05f0*/ IMAD R11, R8, R11, RZ ; /* 0x0000000b080b7224 */
/* 0x020fe400078e02ff */
/*0600*/ IMAD.WIDE R8, R2, 0x4, R20 ; /* 0x0000000402087825 */
/* 0x000fc800078e0214 */
/*0610*/ IMAD R24, R13, R24, RZ ; /* 0x000000180d187224 */
/* 0x000fe400078e02ff */
/*0620*/ IMAD.WIDE R12, R2, 0x4, R8 ; /* 0x00000004020c7825 */
/* 0x000fc800078e0208 */
/*0630*/ IMAD R26, R26, R25, RZ ; /* 0x000000191a1a7224 */
/* 0x000fe200078e02ff */
/*0640*/ LDG.E R20, [R12.64] ; /* 0x000000040c147981 */
/* 0x002ea8000c1e1900 */
/*0650*/ LDG.E R25, [R8.64] ; /* 0x0000000408197981 */
/* 0x000368000c1e1900 */
/*0660*/ LDG.E R8, [R14.64+0x38] ; /* 0x000038040e087981 */
/* 0x002168000c1e1900 */
/*0670*/ LDG.E R9, [R14.64+0x3c] ; /* 0x00003c040e097981 */
/* 0x0000a2000c1e1900 */
/*0680*/ I2F R22, R22 ; /* 0x0000001600167306 */
/* 0x000e700000201400 */
/*0690*/ I2F R23, R23 ; /* 0x0000001700177306 */
/* 0x000e300000201400 */
/*06a0*/ I2F R27, R27 ; /* 0x0000001b001b7306 */
/* 0x000e220000201400 */
/*06b0*/ FADD R10, R10, R22 ; /* 0x000000160a0a7221 */
/* 0x002fce0000000000 */
/*06c0*/ I2F R29, R29 ; /* 0x0000001d001d7306 */
/* 0x000e620000201400 */
/*06d0*/ FADD R14, R10, R23 ; /* 0x000000170a0e7221 */
/* 0x001fce0000000000 */
/*06e0*/ I2F R11, R11 ; /* 0x0000000b000b7306 */
/* 0x000e220000201400 */
/*06f0*/ FADD R14, R14, R27 ; /* 0x0000001b0e0e7221 */
/* 0x000fce0000000000 */
/*0700*/ I2F R16, R16 ; /* 0x0000001000107306 */
/* 0x000e220000201400 */
/*0710*/ FADD R14, R14, R29 ; /* 0x0000001d0e0e7221 */
/* 0x002fce0000000000 */
/*0720*/ I2F R24, R24 ; /* 0x0000001800187306 */
/* 0x000e620000201400 */
/*0730*/ FADD R11, R14, R11 ; /* 0x0000000b0e0b7221 */
/* 0x001fce0000000000 */
/*0740*/ I2F R26, R26 ; /* 0x0000001a001a7306 */
/* 0x000e220000201400 */
/*0750*/ FADD R11, R11, R16 ; /* 0x000000100b0b7221 */
/* 0x000fe20000000000 */
/*0760*/ IADD3 R7, R7, -0x10, RZ ; /* 0xfffffff007077810 */
/* 0x000fc60007ffe0ff */
/*0770*/ FADD R11, R11, R24 ; /* 0x000000180b0b7221 */
/* 0x002fe20000000000 */
/*0780*/ ISETP.GT.AND P1, PT, R7, 0xc, PT ; /* 0x0000000c0700780c */
/* 0x000fc60003f24270 */
/*0790*/ FADD R11, R11, R26 ; /* 0x0000001a0b0b7221 */
/* 0x001fe20000000000 */
/*07a0*/ UIADD3 UR6, UP0, UR6, 0x40, URZ ; /* 0x0000004006067890 */
/* 0x000fe2000ff1e03f */
/*07b0*/ IADD3 R4, R4, 0x10, RZ ; /* 0x0000001004047810 */
/* 0x000fc60007ffe0ff */
/*07c0*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*07d0*/ IMAD.WIDE R22, R2, 0x4, R12 ; /* 0x0000000402167825 */
/* 0x000fc800078e020c */
/*07e0*/ IMAD R17, R28, R17, RZ ; /* 0x000000111c117224 */
/* 0x008fc800078e02ff */
/*07f0*/ I2F R10, R17 ; /* 0x00000011000a7306 */
/* 0x000e220000201400 */
/*0800*/ IMAD R18, R18, R19, RZ ; /* 0x0000001312127224 */
/* 0x010fce00078e02ff */
/*0810*/ I2F R15, R18 ; /* 0x00000012000f7306 */
/* 0x000e620000201400 */
/*0820*/ FADD R10, R11, R10 ; /* 0x0000000a0b0a7221 */
/* 0x001fe40000000000 */
/*0830*/ IMAD R8, R25, R8, RZ ; /* 0x0000000819087224 */
/* 0x020fe400078e02ff */
/*0840*/ IMAD R9, R20, R9, RZ ; /* 0x0000000914097224 */
/* 0x004fc600078e02ff */
/*0850*/ I2F R19, R8 ; /* 0x0000000800137306 */
/* 0x000e300000201400 */
/*0860*/ I2F R9, R9 ; /* 0x0000000900097306 */
/* 0x000ea20000201400 */
/*0870*/ FADD R10, R10, R15 ; /* 0x0000000f0a0a7221 */
/* 0x002fc80000000000 */
/*0880*/ FADD R10, R10, R19 ; /* 0x000000130a0a7221 */
/* 0x001fc80000000000 */
/*0890*/ FADD R11, R10, R9 ; /* 0x000000090a0b7221 */
/* 0x004fe20000000000 */
/*08a0*/ @P1 BRA 0x220 ; /* 0xfffff97000001947 */
/* 0x000fea000383ffff */
/*08b0*/ ISETP.GT.AND P1, PT, R7, 0x4, PT ; /* 0x000000040700780c */
/* 0x000fda0003f24270 */
/*08c0*/ @!P1 BRA 0xc50 ; /* 0x0000038000009947 */
/* 0x000fea0003800000 */
/*08d0*/ IMAD.WIDE R20, R2, 0x4, R22 ; /* 0x0000000402147825 */
/* 0x000fe200078e0216 */
/*08e0*/ MOV R8, UR6 ; /* 0x0000000600087c02 */
/* 0x000fe20008000f00 */
/*08f0*/ LDG.E R22, [R22.64] ; /* 0x0000000416167981 */
/* 0x0000a2000c1e1900 */
/*0900*/ MOV R9, UR7 ; /* 0x0000000700097c02 */
/* 0x000fc60008000f00 */
/*0910*/ IMAD.WIDE R12, R2, 0x4, R20 ; /* 0x00000004020c7825 */
/* 0x000fe200078e0214 */
/*0920*/ LDG.E R10, [R20.64] ; /* 0x00000004140a7981 */
/* 0x0002e6000c1e1900 */
/*0930*/ IMAD.WIDE R8, R6, 0x4, R8 ; /* 0x0000000406087825 */
/* 0x000fe200078e0208 */
/*0940*/ LDG.E R27, [R12.64] ; /* 0x000000040c1b7981 */
/* 0x000966000c1e1900 */
/*0950*/ IMAD.WIDE R14, R2.reuse, 0x4, R12 ; /* 0x00000004020e7825 */
/* 0x040fe200078e020c */
/*0960*/ LDG.E R25, [R8.64] ; /* 0x0000000408197981 */
/* 0x000ea8000c1e1900 */
/*0970*/ LDG.E R23, [R8.64+0x4] ; /* 0x0000040408177981 */
/* 0x001ee2000c1e1900 */
/*0980*/ IMAD.WIDE R16, R2, 0x4, R14 ; /* 0x0000000402107825 */
/* 0x000fc600078e020e */
/*0990*/ LDG.E R26, [R8.64+0x8] ; /* 0x00000804081a7981 */
/* 0x000f66000c1e1900 */
/*09a0*/ IMAD.WIDE R18, R2.reuse, 0x4, R16 ; /* 0x0000000402127825 */
/* 0x040fe200078e0210 */
/*09b0*/ LDG.E R24, [R14.64] ; /* 0x000000040e187981 */
/* 0x000168000c1e1900 */
/*09c0*/ LDG.E R29, [R8.64+0xc] ; /* 0x00000c04081d7981 */
/* 0x000f62000c1e1900 */
/*09d0*/ IMAD.WIDE R20, R2, 0x4, R18 ; /* 0x0000000402147825 */
/* 0x002fc600078e0212 */
/*09e0*/ LDG.E R28, [R8.64+0x10] ; /* 0x00001004081c7981 */
/* 0x000f68000c1e1900 */
/*09f0*/ LDG.E R15, [R16.64] ; /* 0x00000004100f7981 */
/* 0x001162000c1e1900 */
/*0a00*/ IMAD.WIDE R12, R2, 0x4, R20 ; /* 0x00000004020c7825 */
/* 0x010fc600078e0214 */
/*0a10*/ LDG.E R14, [R8.64+0x14] ; /* 0x00001404080e7981 */
/* 0x000f28000c1e1900 */
/*0a20*/ LDG.E R17, [R18.64] ; /* 0x0000000412117981 */
/* 0x001128000c1e1900 */
/*0a30*/ LDG.E R16, [R20.64] ; /* 0x0000000414107981 */
/* 0x000328000c1e1900 */
/*0a40*/ LDG.E R19, [R8.64+0x18] ; /* 0x0000180408137981 */
/* 0x001128000c1e1900 */
/*0a50*/ LDG.E R18, [R8.64+0x1c] ; /* 0x00001c0408127981 */
/* 0x000128000c1e1900 */
/*0a60*/ LDG.E R21, [R12.64] ; /* 0x000000040c157981 */
/* 0x002f22000c1e1900 */
/*0a70*/ UIADD3 UR6, UP0, UR6, 0x20, URZ ; /* 0x0000002006067890 */
/* 0x000fe2000ff1e03f */
/*0a80*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc40003f0e170 */
/*0a90*/ IADD3 R4, R4, 0x8, RZ ; /* 0x0000000804047810 */
/* 0x000fe40007ffe0ff */
/*0aa0*/ IADD3 R7, R7, -0x8, RZ ; /* 0xfffffff807077810 */
/* 0x000fe20007ffe0ff */
/*0ab0*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0ac0*/ IMAD R22, R22, R25, RZ ; /* 0x0000001916167224 */
/* 0x004fe400078e02ff */
/*0ad0*/ IMAD R10, R10, R23, RZ ; /* 0x000000170a0a7224 */
/* 0x008fc800078e02ff */
/*0ae0*/ I2F R22, R22 ; /* 0x0000001600167306 */
/* 0x000e620000201400 */
/*0af0*/ IMAD R23, R27, R26, RZ ; /* 0x0000001a1b177224 */
/* 0x020fce00078e02ff */
/*0b00*/ I2F R10, R10 ; /* 0x0000000a000a7306 */
/* 0x000ea20000201400 */
/*0b10*/ IMAD R20, R24, R29, RZ ; /* 0x0000001d18147224 */
/* 0x000fce00078e02ff */
/*0b20*/ I2F R23, R23 ; /* 0x0000001700177306 */
/* 0x000ee20000201400 */
/*0b30*/ IMAD R15, R15, R28, RZ ; /* 0x0000001c0f0f7224 */
/* 0x000fe400078e02ff */
/*0b40*/ FADD R11, R11, R22 ; /* 0x000000160b0b7221 */
/* 0x002fca0000000000 */
/*0b50*/ I2F R20, R20 ; /* 0x0000001400147306 */
/* 0x000e620000201400 */
/*0b60*/ IMAD R14, R17, R14, RZ ; /* 0x0000000e110e7224 */
/* 0x010fce00078e02ff */
/*0b70*/ I2F R8, R15 ; /* 0x0000000f00087306 */
/* 0x001e220000201400 */
/*0b80*/ FADD R10, R11, R10 ; /* 0x0000000a0b0a7221 */
/* 0x004fe40000000000 */
/*0b90*/ IMAD R16, R16, R19, RZ ; /* 0x0000001310107224 */
/* 0x000fca00078e02ff */
/*0ba0*/ I2F R9, R14 ; /* 0x0000000e00097306 */
/* 0x000ea20000201400 */
/*0bb0*/ FADD R23, R10, R23 ; /* 0x000000170a177221 */
/* 0x008fe40000000000 */
/*0bc0*/ IMAD R18, R21, R18, RZ ; /* 0x0000001215127224 */
/* 0x000fca00078e02ff */
/*0bd0*/ I2F R11, R16 ; /* 0x00000010000b7306 */
/* 0x000ee20000201400 */
/*0be0*/ FADD R23, R23, R20 ; /* 0x0000001417177221 */
/* 0x002fce0000000000 */
/*0bf0*/ I2F R18, R18 ; /* 0x0000001200127306 */
/* 0x000e620000201400 */
/*0c00*/ FADD R8, R23, R8 ; /* 0x0000000817087221 */
/* 0x001fc80000000000 */
/*0c10*/ FADD R8, R8, R9 ; /* 0x0000000908087221 */
/* 0x004fc80000000000 */
/*0c20*/ FADD R11, R8, R11 ; /* 0x0000000b080b7221 */
/* 0x008fe40000000000 */
/*0c30*/ IMAD.WIDE R22, R2, 0x4, R12 ; /* 0x0000000402167825 */
/* 0x000fc800078e020c */
/*0c40*/ FADD R11, R11, R18 ; /* 0x000000120b0b7221 */
/* 0x002fe40000000000 */
/*0c50*/ ISETP.NE.OR P0, PT, R7, RZ, P0 ; /* 0x000000ff0700720c */
/* 0x000fda0000705670 */
/*0c60*/ @!P0 BRA 0xe80 ; /* 0x0000021000008947 */
/* 0x000fea0003800000 */
/*0c70*/ MOV R8, UR6 ; /* 0x0000000600087c02 */
/* 0x000fe20008000f00 */
/*0c80*/ IMAD.WIDE R16, R2, 0x4, R22 ; /* 0x0000000402107825 */
/* 0x000fe200078e0216 */
/*0c90*/ MOV R9, UR7 ; /* 0x0000000700097c02 */
/* 0x000fe20008000f00 */
/*0ca0*/ LDG.E R22, [R22.64] ; /* 0x0000000416167981 */
/* 0x000ea8000c1e1900 */
/*0cb0*/ IMAD.WIDE R8, R6, 0x4, R8 ; /* 0x0000000406087825 */
/* 0x000fc800078e0208 */
/*0cc0*/ IMAD.WIDE R14, R2.reuse, 0x4, R16 ; /* 0x00000004020e7825 */
/* 0x040fe200078e0210 */
/*0cd0*/ LDG.E R19, [R8.64] ; /* 0x0000000408137981 */
/* 0x000ea8000c1e1900 */
/*0ce0*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x000ee8000c1e1900 */
/*0cf0*/ LDG.E R21, [R8.64+0x4] ; /* 0x0000040408157981 */
/* 0x000ee2000c1e1900 */
/*0d00*/ IMAD.WIDE R12, R2, 0x4, R14 ; /* 0x00000004020c7825 */
/* 0x000fc600078e020e */
/*0d10*/ LDG.E R18, [R14.64] ; /* 0x000000040e127981 */
/* 0x000f28000c1e1900 */
/*0d20*/ LDG.E R25, [R8.64+0x8] ; /* 0x0000080408197981 */
/* 0x000f28000c1e1900 */
/*0d30*/ LDG.E R27, [R8.64+0xc] ; /* 0x00000c04081b7981 */
/* 0x000f68000c1e1900 */
/*0d40*/ LDG.E R20, [R12.64] ; /* 0x000000040c147981 */
/* 0x000f62000c1e1900 */
/*0d50*/ IADD3 R7, R7, -0x4, RZ ; /* 0xfffffffc07077810 */
/* 0x000fc80007ffe0ff */
/*0d60*/ ISETP.NE.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fe20003f05270 */
/*0d70*/ UIADD3 UR6, UP0, UR6, 0x10, URZ ; /* 0x0000001006067890 */
/* 0x000fe2000ff1e03f */
/*0d80*/ IADD3 R4, R4, 0x4, RZ ; /* 0x0000000404047810 */
/* 0x000fc60007ffe0ff */
/*0d90*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0da0*/ IMAD R19, R22, R19, RZ ; /* 0x0000001316137224 */
/* 0x004fc800078e02ff */
/*0db0*/ I2F R10, R19 ; /* 0x00000013000a7306 */
/* 0x000e220000201400 */
/*0dc0*/ IMAD R21, R16, R21, RZ ; /* 0x0000001510157224 */
/* 0x008fce00078e02ff */
/*0dd0*/ I2F R21, R21 ; /* 0x0000001500157306 */
/* 0x000e620000201400 */
/*0de0*/ IMAD R18, R18, R25, RZ ; /* 0x0000001912127224 */
/* 0x010fce00078e02ff */
/*0df0*/ I2F R17, R18 ; /* 0x0000001200117306 */
/* 0x000ea20000201400 */
/*0e00*/ IMAD R20, R20, R27, RZ ; /* 0x0000001b14147224 */
/* 0x020fe400078e02ff */
/*0e10*/ FADD R10, R10, R11 ; /* 0x0000000b0a0a7221 */
/* 0x001fca0000000000 */
/*0e20*/ I2F R15, R20 ; /* 0x00000014000f7306 */
/* 0x000e220000201400 */
/*0e30*/ FADD R10, R10, R21 ; /* 0x000000150a0a7221 */
/* 0x002fe40000000000 */
/*0e40*/ IMAD.WIDE R22, R2, 0x4, R12 ; /* 0x0000000402167825 */
/* 0x000fc800078e020c */
/*0e50*/ FADD R10, R10, R17 ; /* 0x000000110a0a7221 */
/* 0x004fc80000000000 */
/*0e60*/ FADD R11, R10, R15 ; /* 0x0000000f0a0b7221 */
/* 0x001fe20000000000 */
/*0e70*/ @P0 BRA 0xc70 ; /* 0xfffffdf000000947 */
/* 0x000fea000383ffff */
/*0e80*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fda0003f05270 */
/*0e90*/ @!P0 BRA 0xfc0 ; /* 0x0000012000008947 */
/* 0x000fea0003800000 */
/*0ea0*/ HFMA2.MMA R9, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff097435 */
/* 0x000fe200000001ff */
/*0eb0*/ IMAD R6, R3, c[0x0][0x178], R4 ; /* 0x00005e0003067a24 */
/* 0x000fe400078e0204 */
/*0ec0*/ IMAD R4, R4, c[0x0][0x178], R0 ; /* 0x00005e0004047a24 */
/* 0x000fce00078e0200 */
/*0ed0*/ IMAD.WIDE R6, R6, R9, c[0x0][0x160] ; /* 0x0000580006067625 */
/* 0x000fc800078e0209 */
/*0ee0*/ IMAD.WIDE R8, R4, R9, c[0x0][0x168] ; /* 0x00005a0004087625 */
/* 0x000fe200078e0209 */
/*0ef0*/ MOV R13, R7 ; /* 0x00000007000d7202 */
/* 0x000fc80000000f00 */
/*0f00*/ MOV R7, R13 ; /* 0x0000000d00077202 */
/* 0x000fe20000000f00 */
/*0f10*/ LDG.E R4, [R8.64] ; /* 0x0000000408047981 */
/* 0x0000aa000c1e1900 */
/*0f20*/ LDG.E R7, [R6.64] ; /* 0x0000000406077981 */
/* 0x0002a2000c1e1900 */
/*0f30*/ IADD3 R5, R5, -0x1, RZ ; /* 0xffffffff05057810 */
/* 0x000fc80007ffe0ff */
/*0f40*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe20003f05270 */
/*0f50*/ IMAD.WIDE R8, R2, 0x4, R8 ; /* 0x0000000402087825 */
/* 0x001fe200078e0208 */
/*0f60*/ IADD3 R6, P1, R6, 0x4, RZ ; /* 0x0000000406067810 */
/* 0x002fc80007f3e0ff */
/*0f70*/ IADD3.X R13, RZ, R13, RZ, P1, !PT ; /* 0x0000000dff0d7210 */
/* 0x000fe20000ffe4ff */
/*0f80*/ IMAD R4, R4, R7, RZ ; /* 0x0000000704047224 */
/* 0x004fcc00078e02ff */
/*0f90*/ I2F R4, R4 ; /* 0x0000000400047306 */
/* 0x000e240000201400 */
/*0fa0*/ FADD R11, R4, R11 ; /* 0x0000000b040b7221 */
/* 0x001fe20000000000 */
/*0fb0*/ @P0 BRA 0xf00 ; /* 0xffffff4000000947 */
/* 0x000fea000383ffff */
/*0fc0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0fd0*/ F2I.TRUNC.NTZ R11, R11 ; /* 0x0000000b000b7305 */
/* 0x000e22000020f100 */
/*0fe0*/ HFMA2.MMA R2, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff027435 */
/* 0x000fe200000001ff */
/*0ff0*/ IMAD R3, R3, c[0x0][0x178], R0 ; /* 0x00005e0003037a24 */
/* 0x000fd200078e0200 */
/*1000*/ IMAD.WIDE R2, R3, R2, c[0x0][0x170] ; /* 0x00005c0003027625 */
/* 0x000fca00078e0202 */
/*1010*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x001fe2000c101904 */
/*1020*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*1030*/ BRA 0x1030; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*1040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*10a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*10b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*10c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*10d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*10e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*10f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <iostream>
#include <stdio.h>
#include <time.h>
#include <cuda_runtime.h>
#include <math.h>
__global__ void matrixMultiplicationKernel(int* A,int* B,int* C,int N)
{
int ROW = blockIdx.y*blockDim.y+threadIdx.y;
int COL = blockIdx.x*blockDim.x+threadIdx.x;
float tmp_sum = 0.0f;
if(ROW < N && COL < N){
for(int i=0;i<N;i++){
tmp_sum += A[ROW*N+i] *B[i*N+COL];
}
}
C[ROW*N+COL] = tmp_sum;
}
void matrixMultiplication(int* A,int* B,int* C,int N);
int main()
{
int N = 16;
//Host i/o vectors
int *h_A;
int *h_B;
int *h_C;
//Device i/o vector
int *d_A;
int *d_B;
int *d_C;
size_t bytes = N*N*sizeof(int);
h_A = (int*)malloc(bytes);
h_B = (int*)malloc(bytes);
h_C = (int*)malloc(bytes);
cudaMalloc(&d_A,bytes);
cudaMalloc(&d_B,bytes);
cudaMalloc(&d_C,bytes);
// Initialize matricies on the host
for(int i=0;i<N;i++){
for(int j=0;j<N;j++){
h_A[i*N+j] = 2;
h_B[i*N+j] = 3;
}
}
//Copy host vectors to device
cudaMemcpy(d_A,h_A,bytes,cudaMemcpyHostToDevice);
cudaMemcpy(d_B,h_B,bytes,cudaMemcpyHostToDevice);
matrixMultiplication(d_A,d_B,d_C,N);
cudaMemcpy(h_C,d_C,bytes,cudaMemcpyDeviceToHost);
//check result
for(int i=0;i<4;i++){
for(int j=0;j<4;j++){
printf(" %d",h_C[i*N+j]);
}
printf("\n");
}
// Free device memory
cudaFree(d_A);
cudaFree(d_B);
cudaFree(d_C);
//free host memory
free(h_A);
free(h_B);
free(h_C);
return 0;
}
void matrixMultiplication(int* A,int* B,int* C,int N)
{
dim3 threadsPerBlock(N,N);
dim3 blocksPerGrid(1,1);
if(N*N>512){
threadsPerBlock.x = 512;
threadsPerBlock.y = 512;
blocksPerGrid.x = ceil(int(N)/double(threadsPerBlock.x));
blocksPerGrid.y = ceil(int(N)/double(threadsPerBlock.y));
}
matrixMultiplicationKernel<<<blocksPerGrid,threadsPerBlock>>>(A,B,C,N);
} | .file "tmpxft_00155131_00000000-6_mm.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3673:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3673:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z51__device_stub__Z26matrixMultiplicationKernelPiS_S_iPiS_S_i
.type _Z51__device_stub__Z26matrixMultiplicationKernelPiS_S_iPiS_S_i, @function
_Z51__device_stub__Z26matrixMultiplicationKernelPiS_S_iPiS_S_i:
.LFB3695:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z26matrixMultiplicationKernelPiS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3695:
.size _Z51__device_stub__Z26matrixMultiplicationKernelPiS_S_iPiS_S_i, .-_Z51__device_stub__Z26matrixMultiplicationKernelPiS_S_iPiS_S_i
.globl _Z26matrixMultiplicationKernelPiS_S_i
.type _Z26matrixMultiplicationKernelPiS_S_i, @function
_Z26matrixMultiplicationKernelPiS_S_i:
.LFB3696:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z51__device_stub__Z26matrixMultiplicationKernelPiS_S_iPiS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3696:
.size _Z26matrixMultiplicationKernelPiS_S_i, .-_Z26matrixMultiplicationKernelPiS_S_i
.globl _Z20matrixMultiplicationPiS_S_i
.type _Z20matrixMultiplicationPiS_S_i, @function
_Z20matrixMultiplicationPiS_S_i:
.LFB3670:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $40, %rsp
.cfi_def_cfa_offset 80
movq %rdi, %rbp
movq %rsi, %r12
movq %rdx, %r13
movl %ecx, %ebx
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl %ecx, %eax
imull %ecx, %eax
cmpl $512, %eax
jg .L12
movl %ecx, %eax
jmp .L13
.L12:
pxor %xmm0, %xmm0
cvtsi2sdl %ecx, %xmm0
mulsd .LC0(%rip), %xmm0
movapd %xmm0, %xmm3
movsd .LC4(%rip), %xmm2
movapd %xmm0, %xmm1
andpd %xmm2, %xmm1
movsd .LC1(%rip), %xmm4
ucomisd %xmm1, %xmm4
jbe .L14
cvttsd2siq %xmm0, %rax
pxor %xmm1, %xmm1
cvtsi2sdq %rax, %xmm1
cmpnlesd %xmm1, %xmm3
movsd .LC3(%rip), %xmm4
andpd %xmm4, %xmm3
addsd %xmm1, %xmm3
andnpd %xmm0, %xmm2
orpd %xmm2, %xmm3
.L14:
cvttsd2siq %xmm3, %rax
movl %eax, 20(%rsp)
movl %eax, 24(%rsp)
movl $512, %eax
.L13:
movl %eax, 8(%rsp)
movl %eax, 12(%rsp)
movl 16(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 8(%rsp), %rdx
movq 20(%rsp), %rdi
movl 28(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L17
.L11:
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
movl %ebx, %ecx
movq %r13, %rdx
movq %r12, %rsi
movq %rbp, %rdi
call _Z51__device_stub__Z26matrixMultiplicationKernelPiS_S_iPiS_S_i
jmp .L11
.cfi_endproc
.LFE3670:
.size _Z20matrixMultiplicationPiS_S_i, .-_Z20matrixMultiplicationPiS_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC5:
.string " %d"
.LC6:
.string "\n"
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $56, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movl $1024, %edi
call malloc@PLT
movq %rax, %rbp
movl $1024, %edi
call malloc@PLT
movq %rax, %rbx
movl $1024, %edi
call malloc@PLT
movq %rax, 8(%rsp)
leaq 16(%rsp), %rdi
movl $1024, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $1024, %esi
call cudaMalloc@PLT
leaq 32(%rsp), %rdi
movl $1024, %esi
call cudaMalloc@PLT
movl $64, %edx
.L19:
leaq -64(%rdx), %rax
.L20:
movl $2, 0(%rbp,%rax)
movl $3, (%rbx,%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L20
addq $64, %rdx
cmpq $1088, %rdx
jne .L19
movl $1, %ecx
movl $1024, %edx
movq %rbp, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $1024, %edx
movq %rbx, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl $16, %ecx
movq 32(%rsp), %rdx
movq 24(%rsp), %rsi
movq 16(%rsp), %rdi
call _Z20matrixMultiplicationPiS_S_i
movl $2, %ecx
movl $1024, %edx
movq 32(%rsp), %rsi
movq 8(%rsp), %r15
movq %r15, %rdi
call cudaMemcpy@PLT
leaq 16(%r15), %r13
movl $0, %r15d
leaq .LC5(%rip), %r14
.L22:
leaq -16(%r13), %r12
.L23:
movl (%r12), %edx
movq %r14, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %r12
cmpq %r13, %r12
jne .L23
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $16, %r15d
addq $64, %r13
cmpl $64, %r15d
jne .L22
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq %rbp, %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movq 8(%rsp), %rdi
call free@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L29
movl $0, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L29:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size main, .-main
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC7:
.string "_Z26matrixMultiplicationKernelPiS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3698:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _Z26matrixMultiplicationKernelPiS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3698:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long 0
.long 1063256064
.align 8
.LC1:
.long 0
.long 1127219200
.align 8
.LC3:
.long 0
.long 1072693248
.align 8
.LC4:
.long -1
.long 2147483647
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <iostream>
#include <stdio.h>
#include <time.h>
#include <cuda_runtime.h>
#include <math.h>
__global__ void matrixMultiplicationKernel(int* A,int* B,int* C,int N)
{
int ROW = blockIdx.y*blockDim.y+threadIdx.y;
int COL = blockIdx.x*blockDim.x+threadIdx.x;
float tmp_sum = 0.0f;
if(ROW < N && COL < N){
for(int i=0;i<N;i++){
tmp_sum += A[ROW*N+i] *B[i*N+COL];
}
}
C[ROW*N+COL] = tmp_sum;
}
void matrixMultiplication(int* A,int* B,int* C,int N);
int main()
{
int N = 16;
//Host i/o vectors
int *h_A;
int *h_B;
int *h_C;
//Device i/o vector
int *d_A;
int *d_B;
int *d_C;
size_t bytes = N*N*sizeof(int);
h_A = (int*)malloc(bytes);
h_B = (int*)malloc(bytes);
h_C = (int*)malloc(bytes);
cudaMalloc(&d_A,bytes);
cudaMalloc(&d_B,bytes);
cudaMalloc(&d_C,bytes);
// Initialize matricies on the host
for(int i=0;i<N;i++){
for(int j=0;j<N;j++){
h_A[i*N+j] = 2;
h_B[i*N+j] = 3;
}
}
//Copy host vectors to device
cudaMemcpy(d_A,h_A,bytes,cudaMemcpyHostToDevice);
cudaMemcpy(d_B,h_B,bytes,cudaMemcpyHostToDevice);
matrixMultiplication(d_A,d_B,d_C,N);
cudaMemcpy(h_C,d_C,bytes,cudaMemcpyDeviceToHost);
//check result
for(int i=0;i<4;i++){
for(int j=0;j<4;j++){
printf(" %d",h_C[i*N+j]);
}
printf("\n");
}
// Free device memory
cudaFree(d_A);
cudaFree(d_B);
cudaFree(d_C);
//free host memory
free(h_A);
free(h_B);
free(h_C);
return 0;
}
void matrixMultiplication(int* A,int* B,int* C,int N)
{
dim3 threadsPerBlock(N,N);
dim3 blocksPerGrid(1,1);
if(N*N>512){
threadsPerBlock.x = 512;
threadsPerBlock.y = 512;
blocksPerGrid.x = ceil(int(N)/double(threadsPerBlock.x));
blocksPerGrid.y = ceil(int(N)/double(threadsPerBlock.y));
}
matrixMultiplicationKernel<<<blocksPerGrid,threadsPerBlock>>>(A,B,C,N);
} | #include <iostream>
#include <stdio.h>
#include <time.h>
#include <hip/hip_runtime.h>
#include <math.h>
__global__ void matrixMultiplicationKernel(int* A,int* B,int* C,int N)
{
int ROW = blockIdx.y*blockDim.y+threadIdx.y;
int COL = blockIdx.x*blockDim.x+threadIdx.x;
float tmp_sum = 0.0f;
if(ROW < N && COL < N){
for(int i=0;i<N;i++){
tmp_sum += A[ROW*N+i] *B[i*N+COL];
}
}
C[ROW*N+COL] = tmp_sum;
}
void matrixMultiplication(int* A,int* B,int* C,int N);
int main()
{
int N = 16;
//Host i/o vectors
int *h_A;
int *h_B;
int *h_C;
//Device i/o vector
int *d_A;
int *d_B;
int *d_C;
size_t bytes = N*N*sizeof(int);
h_A = (int*)malloc(bytes);
h_B = (int*)malloc(bytes);
h_C = (int*)malloc(bytes);
hipMalloc(&d_A,bytes);
hipMalloc(&d_B,bytes);
hipMalloc(&d_C,bytes);
// Initialize matricies on the host
for(int i=0;i<N;i++){
for(int j=0;j<N;j++){
h_A[i*N+j] = 2;
h_B[i*N+j] = 3;
}
}
//Copy host vectors to device
hipMemcpy(d_A,h_A,bytes,hipMemcpyHostToDevice);
hipMemcpy(d_B,h_B,bytes,hipMemcpyHostToDevice);
matrixMultiplication(d_A,d_B,d_C,N);
hipMemcpy(h_C,d_C,bytes,hipMemcpyDeviceToHost);
//check result
for(int i=0;i<4;i++){
for(int j=0;j<4;j++){
printf(" %d",h_C[i*N+j]);
}
printf("\n");
}
// Free device memory
hipFree(d_A);
hipFree(d_B);
hipFree(d_C);
//free host memory
free(h_A);
free(h_B);
free(h_C);
return 0;
}
void matrixMultiplication(int* A,int* B,int* C,int N)
{
dim3 threadsPerBlock(N,N);
dim3 blocksPerGrid(1,1);
if(N*N>512){
threadsPerBlock.x = 512;
threadsPerBlock.y = 512;
blocksPerGrid.x = ceil(int(N)/double(threadsPerBlock.x));
blocksPerGrid.y = ceil(int(N)/double(threadsPerBlock.y));
}
matrixMultiplicationKernel<<<blocksPerGrid,threadsPerBlock>>>(A,B,C,N);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <iostream>
#include <stdio.h>
#include <time.h>
#include <hip/hip_runtime.h>
#include <math.h>
__global__ void matrixMultiplicationKernel(int* A,int* B,int* C,int N)
{
int ROW = blockIdx.y*blockDim.y+threadIdx.y;
int COL = blockIdx.x*blockDim.x+threadIdx.x;
float tmp_sum = 0.0f;
if(ROW < N && COL < N){
for(int i=0;i<N;i++){
tmp_sum += A[ROW*N+i] *B[i*N+COL];
}
}
C[ROW*N+COL] = tmp_sum;
}
void matrixMultiplication(int* A,int* B,int* C,int N);
int main()
{
int N = 16;
//Host i/o vectors
int *h_A;
int *h_B;
int *h_C;
//Device i/o vector
int *d_A;
int *d_B;
int *d_C;
size_t bytes = N*N*sizeof(int);
h_A = (int*)malloc(bytes);
h_B = (int*)malloc(bytes);
h_C = (int*)malloc(bytes);
hipMalloc(&d_A,bytes);
hipMalloc(&d_B,bytes);
hipMalloc(&d_C,bytes);
// Initialize matricies on the host
for(int i=0;i<N;i++){
for(int j=0;j<N;j++){
h_A[i*N+j] = 2;
h_B[i*N+j] = 3;
}
}
//Copy host vectors to device
hipMemcpy(d_A,h_A,bytes,hipMemcpyHostToDevice);
hipMemcpy(d_B,h_B,bytes,hipMemcpyHostToDevice);
matrixMultiplication(d_A,d_B,d_C,N);
hipMemcpy(h_C,d_C,bytes,hipMemcpyDeviceToHost);
//check result
for(int i=0;i<4;i++){
for(int j=0;j<4;j++){
printf(" %d",h_C[i*N+j]);
}
printf("\n");
}
// Free device memory
hipFree(d_A);
hipFree(d_B);
hipFree(d_C);
//free host memory
free(h_A);
free(h_B);
free(h_C);
return 0;
}
void matrixMultiplication(int* A,int* B,int* C,int N)
{
dim3 threadsPerBlock(N,N);
dim3 blocksPerGrid(1,1);
if(N*N>512){
threadsPerBlock.x = 512;
threadsPerBlock.y = 512;
blocksPerGrid.x = ceil(int(N)/double(threadsPerBlock.x));
blocksPerGrid.y = ceil(int(N)/double(threadsPerBlock.y));
}
matrixMultiplicationKernel<<<blocksPerGrid,threadsPerBlock>>>(A,B,C,N);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z26matrixMultiplicationKernelPiS_S_i
.globl _Z26matrixMultiplicationKernelPiS_S_i
.p2align 8
.type _Z26matrixMultiplicationKernelPiS_S_i,@function
_Z26matrixMultiplicationKernelPiS_S_i:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x2c
s_load_b32 s2, s[0:1], 0x18
v_bfe_u32 v2, v0, 10, 10
v_and_b32_e32 v3, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s4, s3, 16
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[0:1], null, s15, s4, v[2:3]
v_mad_u64_u32 v[1:2], null, s14, s3, v[3:4]
v_max3_i32 v2, v0, v1, 0
s_delay_alu instid0(VALU_DEP_1)
v_cmp_gt_i32_e32 vcc_lo, s2, v2
v_mov_b32_e32 v2, 0
s_and_saveexec_b32 s3, vcc_lo
s_cbranch_execz .LBB0_4
s_load_b128 s[4:7], s[0:1], 0x0
v_mul_lo_u32 v2, v0, s2
v_mov_b32_e32 v6, 0
v_mov_b32_e32 v4, v1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
s_mov_b32 s4, s2
.p2align 6
.LBB0_2:
v_ashrrev_i32_e32 v5, 31, v4
s_add_i32 s4, s4, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_cmp_eq_u32 s4, 0
v_lshlrev_b64 v[7:8], 2, v[4:5]
v_add_nc_u32_e32 v4, s2, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v7, vcc_lo, s6, v7
v_add_co_ci_u32_e32 v8, vcc_lo, s7, v8, vcc_lo
global_load_b32 v5, v[2:3], off
global_load_b32 v7, v[7:8], off
v_add_co_u32 v2, vcc_lo, v2, 4
v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
s_waitcnt vmcnt(0)
v_mul_lo_u32 v5, v7, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_f32_i32_e32 v5, v5
v_add_f32_e32 v6, v6, v5
s_cbranch_scc0 .LBB0_2
s_delay_alu instid0(VALU_DEP_1)
v_cvt_i32_f32_e32 v2, v6
.LBB0_4:
s_or_b32 exec_lo, exec_lo, s3
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[3:4], null, v0, s2, v[1:2]
v_ashrrev_i32_e32 v4, 31, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[3:4]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z26matrixMultiplicationKernelPiS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z26matrixMultiplicationKernelPiS_S_i, .Lfunc_end0-_Z26matrixMultiplicationKernelPiS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z26matrixMultiplicationKernelPiS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z26matrixMultiplicationKernelPiS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <iostream>
#include <stdio.h>
#include <time.h>
#include <hip/hip_runtime.h>
#include <math.h>
__global__ void matrixMultiplicationKernel(int* A,int* B,int* C,int N)
{
int ROW = blockIdx.y*blockDim.y+threadIdx.y;
int COL = blockIdx.x*blockDim.x+threadIdx.x;
float tmp_sum = 0.0f;
if(ROW < N && COL < N){
for(int i=0;i<N;i++){
tmp_sum += A[ROW*N+i] *B[i*N+COL];
}
}
C[ROW*N+COL] = tmp_sum;
}
void matrixMultiplication(int* A,int* B,int* C,int N);
int main()
{
int N = 16;
//Host i/o vectors
int *h_A;
int *h_B;
int *h_C;
//Device i/o vector
int *d_A;
int *d_B;
int *d_C;
size_t bytes = N*N*sizeof(int);
h_A = (int*)malloc(bytes);
h_B = (int*)malloc(bytes);
h_C = (int*)malloc(bytes);
hipMalloc(&d_A,bytes);
hipMalloc(&d_B,bytes);
hipMalloc(&d_C,bytes);
// Initialize matricies on the host
for(int i=0;i<N;i++){
for(int j=0;j<N;j++){
h_A[i*N+j] = 2;
h_B[i*N+j] = 3;
}
}
//Copy host vectors to device
hipMemcpy(d_A,h_A,bytes,hipMemcpyHostToDevice);
hipMemcpy(d_B,h_B,bytes,hipMemcpyHostToDevice);
matrixMultiplication(d_A,d_B,d_C,N);
hipMemcpy(h_C,d_C,bytes,hipMemcpyDeviceToHost);
//check result
for(int i=0;i<4;i++){
for(int j=0;j<4;j++){
printf(" %d",h_C[i*N+j]);
}
printf("\n");
}
// Free device memory
hipFree(d_A);
hipFree(d_B);
hipFree(d_C);
//free host memory
free(h_A);
free(h_B);
free(h_C);
return 0;
}
void matrixMultiplication(int* A,int* B,int* C,int N)
{
dim3 threadsPerBlock(N,N);
dim3 blocksPerGrid(1,1);
if(N*N>512){
threadsPerBlock.x = 512;
threadsPerBlock.y = 512;
blocksPerGrid.x = ceil(int(N)/double(threadsPerBlock.x));
blocksPerGrid.y = ceil(int(N)/double(threadsPerBlock.y));
}
matrixMultiplicationKernel<<<blocksPerGrid,threadsPerBlock>>>(A,B,C,N);
} | .text
.file "mm.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z41__device_stub__matrixMultiplicationKernelPiS_S_i # -- Begin function _Z41__device_stub__matrixMultiplicationKernelPiS_S_i
.p2align 4, 0x90
.type _Z41__device_stub__matrixMultiplicationKernelPiS_S_i,@function
_Z41__device_stub__matrixMultiplicationKernelPiS_S_i: # @_Z41__device_stub__matrixMultiplicationKernelPiS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z26matrixMultiplicationKernelPiS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z41__device_stub__matrixMultiplicationKernelPiS_S_i, .Lfunc_end0-_Z41__device_stub__matrixMultiplicationKernelPiS_S_i
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $24, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $1024, %edi # imm = 0x400
callq malloc
movq %rax, %rbx
movl $1024, %edi # imm = 0x400
callq malloc
movq %rax, %r14
movl $1024, %edi # imm = 0x400
callq malloc
movq %rax, %r15
leaq 16(%rsp), %rdi
movl $1024, %esi # imm = 0x400
callq hipMalloc
leaq 8(%rsp), %rdi
movl $1024, %esi # imm = 0x400
callq hipMalloc
movq %rsp, %rdi
movl $1024, %esi # imm = 0x400
callq hipMalloc
xorl %eax, %eax
movq %rbx, %rcx
movq %r14, %rdx
.p2align 4, 0x90
.LBB1_1: # %.preheader43
# =>This Loop Header: Depth=1
# Child Loop BB1_2 Depth 2
xorl %esi, %esi
.p2align 4, 0x90
.LBB1_2: # Parent Loop BB1_1 Depth=1
# => This Inner Loop Header: Depth=2
movl $2, (%rcx,%rsi,4)
movl $3, (%rdx,%rsi,4)
incq %rsi
cmpq $16, %rsi
jne .LBB1_2
# %bb.3: # in Loop: Header=BB1_1 Depth=1
incq %rax
addq $64, %rdx
addq $64, %rcx
cmpq $16, %rax
jne .LBB1_1
# %bb.4:
movq 16(%rsp), %rdi
movl $1024, %edx # imm = 0x400
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
movl $1024, %edx # imm = 0x400
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
movq 8(%rsp), %rsi
movq (%rsp), %rdx
movl $16, %ecx
callq _Z20matrixMultiplicationPiS_S_i
movq (%rsp), %rsi
movl $1024, %edx # imm = 0x400
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
movq %r15, %r12
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB1_5: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_6 Depth 2
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB1_6: # Parent Loop BB1_5 Depth=1
# => This Inner Loop Header: Depth=2
movl (%r12,%rbp,4), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
incq %rbp
cmpq $4, %rbp
jne .LBB1_6
# %bb.7: # in Loop: Header=BB1_5 Depth=1
movl $10, %edi
callq putchar@PLT
incq %r13
addq $64, %r12
cmpq $4, %r13
jne .LBB1_5
# %bb.8:
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
xorl %eax, %eax
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z20matrixMultiplicationPiS_S_i
.LCPI2_0:
.quad 0x3f60000000000000 # double 0.001953125
.text
.globl _Z20matrixMultiplicationPiS_S_i
.p2align 4, 0x90
.type _Z20matrixMultiplicationPiS_S_i,@function
_Z20matrixMultiplicationPiS_S_i: # @_Z20matrixMultiplicationPiS_S_i
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $112, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl %ecx, %ebx
movq %rdx, %r14
movq %rsi, %r15
movq %rdi, %r12
movabsq $4294967297, %r13 # imm = 0x100000001
movl %ecx, %eax
imull %ecx, %eax
cmpl $513, %eax # imm = 0x201
jb .LBB2_1
# %bb.2:
cvtsi2sd %ebx, %xmm0
mulsd .LCPI2_0(%rip), %xmm0
callq ceil@PLT
cvttsd2si %xmm0, %rax
movl %eax, %eax
imulq %rax, %r13
movabsq $2199023256064, %rdx # imm = 0x20000000200
jmp .LBB2_3
.LBB2_1:
movl %ebx, %eax
movq %rax, %rdx
shlq $32, %rdx
orq %rax, %rdx
.LBB2_3:
movq %r13, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_5
# %bb.4:
movq %r12, 72(%rsp)
movq %r15, 64(%rsp)
movq %r14, 56(%rsp)
movl %ebx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z26matrixMultiplicationKernelPiS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_5:
addq $112, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z20matrixMultiplicationPiS_S_i, .Lfunc_end2-_Z20matrixMultiplicationPiS_S_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z26matrixMultiplicationKernelPiS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z26matrixMultiplicationKernelPiS_S_i,@object # @_Z26matrixMultiplicationKernelPiS_S_i
.section .rodata,"a",@progbits
.globl _Z26matrixMultiplicationKernelPiS_S_i
.p2align 3, 0x0
_Z26matrixMultiplicationKernelPiS_S_i:
.quad _Z41__device_stub__matrixMultiplicationKernelPiS_S_i
.size _Z26matrixMultiplicationKernelPiS_S_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz " %d"
.size .L.str, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z26matrixMultiplicationKernelPiS_S_i"
.size .L__unnamed_1, 38
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z41__device_stub__matrixMultiplicationKernelPiS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z26matrixMultiplicationKernelPiS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z26matrixMultiplicationKernelPiS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0030*/ BSSY B0, 0xfd0 ; /* 0x00000f9000007945 */
/* 0x000fe20003800000 */
/*0040*/ HFMA2.MMA R11, -RZ, RZ, 0, 0 ; /* 0x00000000ff0b7435 */
/* 0x000fe200000001ff */
/*0050*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e280000002100 */
/*0060*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e680000002600 */
/*0070*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e620000002200 */
/*0080*/ IMAD R0, R0, c[0x0][0x0], R5 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0205 */
/*0090*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x178], PT ; /* 0x00005e0000007a0c */
/* 0x000fe20003f06270 */
/*00a0*/ IMAD R3, R3, c[0x0][0x4], R2 ; /* 0x0000010003037a24 */
/* 0x002fe200078e0202 */
/*00b0*/ MOV R2, c[0x0][0x178] ; /* 0x00005e0000027a02 */
/* 0x000fc80000000f00 */
/*00c0*/ ISETP.GE.OR P0, PT, R3, c[0x0][0x178], P0 ; /* 0x00005e0003007a0c */
/* 0x000fc80000706670 */
/*00d0*/ ISETP.LT.OR P0, PT, R2, 0x1, P0 ; /* 0x000000010200780c */
/* 0x000fda0000701670 */
/*00e0*/ @P0 BRA 0xfc0 ; /* 0x00000ed000000947 */
/* 0x000fea0003800000 */
/*00f0*/ IADD3 R4, R2.reuse, -0x1, RZ ; /* 0xffffffff02047810 */
/* 0x040fe40007ffe0ff */
/*0100*/ LOP3.LUT R5, R2, 0x3, RZ, 0xc0, !PT ; /* 0x0000000302057812 */
/* 0x000fe400078ec0ff */
/*0110*/ ISETP.GE.U32.AND P0, PT, R4, 0x3, PT ; /* 0x000000030400780c */
/* 0x000fe40003f06070 */
/*0120*/ MOV R11, RZ ; /* 0x000000ff000b7202 */
/* 0x000fe40000000f00 */
/*0130*/ MOV R4, RZ ; /* 0x000000ff00047202 */
/* 0x000fd20000000f00 */
/*0140*/ @!P0 BRA 0xe80 ; /* 0x00000d3000008947 */
/* 0x000fea0003800000 */
/*0150*/ IADD3 R7, -R5, c[0x0][0x178], RZ ; /* 0x00005e0005077a10 */
/* 0x000fe20007ffe1ff */
/*0160*/ HFMA2.MMA R23, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff177435 */
/* 0x000fe200000001ff */
/*0170*/ ULDC.64 UR6, c[0x0][0x160] ; /* 0x0000580000067ab9 */
/* 0x000fe20000000a00 */
/*0180*/ HFMA2.MMA R4, -RZ, RZ, 0, 0 ; /* 0x00000000ff047435 */
/* 0x000fe200000001ff */
/*0190*/ ISETP.GT.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fe20003f04270 */
/*01a0*/ IMAD R6, R3, c[0x0][0x178], RZ ; /* 0x00005e0003067a24 */
/* 0x000fe200078e02ff */
/*01b0*/ MOV R11, RZ ; /* 0x000000ff000b7202 */
/* 0x000fca0000000f00 */
/*01c0*/ IMAD.WIDE R22, R0, R23, c[0x0][0x168] ; /* 0x00005a0000167625 */
/* 0x000fcc00078e0217 */
/*01d0*/ @!P0 BRA 0xc70 ; /* 0x00000a9000008947 */
/* 0x000fea0003800000 */
/*01e0*/ ISETP.GT.AND P1, PT, R7, 0xc, PT ; /* 0x0000000c0700780c */
/* 0x000fe40003f24270 */
/*01f0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*0200*/ @!P1 BRA 0x8b0 ; /* 0x000006a000009947 */
/* 0x000fea0003800000 */
/*0210*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0220*/ MOV R14, UR6 ; /* 0x00000006000e7c02 */
/* 0x000fe20008000f00 */
/*0230*/ IMAD.WIDE R16, R2, 0x4, R22 ; /* 0x0000000402107825 */
/* 0x000fe200078e0216 */
/*0240*/ MOV R15, UR7 ; /* 0x00000007000f7c02 */
/* 0x000fe20008000f00 */
/*0250*/ LDG.E R8, [R22.64] ; /* 0x0000000416087981 */
/* 0x0000a8000c1e1900 */
/*0260*/ IMAD.WIDE R14, R6, 0x4, R14 ; /* 0x00000004060e7825 */
/* 0x000fe200078e020e */
/*0270*/ LDG.E R10, [R16.64] ; /* 0x00000004100a7981 */
/* 0x0002e8000c1e1900 */
/*0280*/ LDG.E R9, [R14.64] ; /* 0x000000040e097981 */
/* 0x000ea2000c1e1900 */
/*0290*/ IMAD.WIDE R12, R2, 0x4, R16 ; /* 0x00000004020c7825 */
/* 0x000fc600078e0210 */
/*02a0*/ LDG.E R29, [R14.64+0x4] ; /* 0x000004040e1d7981 */
/* 0x000ee8000c1e1900 */
/*02b0*/ LDG.E R26, [R12.64] ; /* 0x000000040c1a7981 */
/* 0x000968000c1e1900 */
/*02c0*/ LDG.E R27, [R14.64+0x8] ; /* 0x000008040e1b7981 */
/* 0x000f68000c1e1900 */
/*02d0*/ LDG.E R21, [R14.64+0xc] ; /* 0x00000c040e157981 */
/* 0x000f62000c1e1900 */
/*02e0*/ IMAD.WIDE R12, R2, 0x4, R12 ; /* 0x00000004020c7825 */
/* 0x010fc600078e020c */
/*02f0*/ LDG.E R23, [R14.64+0x14] ; /* 0x000014040e177981 */
/* 0x001f28000c1e1900 */
/*0300*/ LDG.E R20, [R12.64] ; /* 0x000000040c147981 */
/* 0x000122000c1e1900 */
/*0310*/ IMAD.WIDE R18, R2, 0x4, R12 ; /* 0x0000000402127825 */
/* 0x000fc600078e020c */
/*0320*/ LDG.E R25, [R14.64+0x10] ; /* 0x000010040e197981 */
/* 0x000f26000c1e1900 */
/*0330*/ IMAD.WIDE R16, R2.reuse, 0x4, R18 ; /* 0x0000000402107825 */
/* 0x042fe200078e0212 */
/*0340*/ LDG.E R22, [R18.64] ; /* 0x0000000412167981 */
/* 0x000328000c1e1900 */
/*0350*/ LDG.E R24, [R16.64] ; /* 0x0000000410187981 */
/* 0x000322000c1e1900 */
/*0360*/ IMAD.WIDE R12, R2, 0x4, R16 ; /* 0x00000004020c7825 */
/* 0x001fc800078e0210 */
/*0370*/ IMAD R8, R8, R9, RZ ; /* 0x0000000908087224 */
/* 0x004fe400078e02ff */
/*0380*/ IMAD R10, R10, R29, RZ ; /* 0x0000001d0a0a7224 */
/* 0x008fc800078e02ff */
/*0390*/ I2F R8, R8 ; /* 0x0000000800087306 */
/* 0x000e220000201400 */
/*03a0*/ IMAD R26, R26, R27, RZ ; /* 0x0000001b1a1a7224 */
/* 0x020fce00078e02ff */
/*03b0*/ I2F R18, R10 ; /* 0x0000000a00127306 */
/* 0x0028620000201400 */
/*03c0*/ IMAD.WIDE R28, R2, 0x4, R12 ; /* 0x00000004021c7825 */
/* 0x000fe200078e020c */
/*03d0*/ LDG.E R27, [R12.64] ; /* 0x000000040c1b7981 */
/* 0x0004ec000c1e1900 */
/*03e0*/ I2F R26, R26 ; /* 0x0000001a001a7306 */
/* 0x000f620000201400 */
/*03f0*/ IMAD R10, R20, R21, RZ ; /* 0x00000015140a7224 */
/* 0x010fe400078e02ff */
/*0400*/ FADD R11, R8, R11 ; /* 0x0000000b080b7221 */
/* 0x001fe20000000000 */
/*0410*/ LDG.E R20, [R14.64+0x18] ; /* 0x000018040e147981 */
/* 0x000ee2000c1e1900 */
/*0420*/ IMAD.WIDE R8, R2, 0x4, R28 ; /* 0x0000000402087825 */
/* 0x000fc600078e021c */
/*0430*/ I2F R10, R10 ; /* 0x0000000a000a7306 */
/* 0x000e220000201400 */
/*0440*/ LDG.E R28, [R28.64] ; /* 0x000000041c1c7981 */
/* 0x000f22000c1e1900 */
/*0450*/ FADD R11, R11, R18 ; /* 0x000000120b0b7221 */
/* 0x002fe40000000000 */
/*0460*/ IMAD.WIDE R18, R2.reuse, 0x4, R8 ; /* 0x0000000402127825 */
/* 0x040fe200078e0208 */
/*0470*/ LDG.E R21, [R14.64+0x1c] ; /* 0x00001c040e157981 */
/* 0x000f26000c1e1900 */
/*0480*/ FADD R11, R11, R26 ; /* 0x0000001a0b0b7221 */
/* 0x020fe20000000000 */
/*0490*/ LDG.E R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x000362000c1e1900 */
/*04a0*/ IMAD.WIDE R16, R2, 0x4, R18 ; /* 0x0000000402107825 */
/* 0x000fc600078e0212 */
/*04b0*/ LDG.E R12, [R14.64+0x24] ; /* 0x000024040e0c7981 */
/* 0x004ea2000c1e1900 */
/*04c0*/ FADD R10, R11, R10 ; /* 0x0000000a0b0a7221 */
/* 0x001fc60000000000 */
/*04d0*/ LDG.E R13, [R16.64] ; /* 0x00000004100d7981 */
/* 0x0000a8000c1e1900 */
/*04e0*/ LDG.E R9, [R18.64] ; /* 0x0000000412097981 */
/* 0x0022a8000c1e1900 */
/*04f0*/ LDG.E R11, [R14.64+0x20] ; /* 0x000020040e0b7981 */
/* 0x000f62000c1e1900 */
/*0500*/ IMAD.WIDE R16, R2, 0x4, R16 ; /* 0x0000000402107825 */
/* 0x001fc800078e0210 */
/*0510*/ IMAD R23, R24, R23, RZ ; /* 0x0000001718177224 */
/* 0x000fe200078e02ff */
/*0520*/ LDG.E R26, [R16.64] ; /* 0x00000004101a7981 */
/* 0x000162000c1e1900 */
/*0530*/ IMAD R22, R22, R25, RZ ; /* 0x0000001916167224 */
/* 0x000fc600078e02ff */
/*0540*/ LDG.E R24, [R14.64+0x28] ; /* 0x000028040e187981 */
/* 0x000f68000c1e1900 */
/*0550*/ LDG.E R25, [R14.64+0x2c] ; /* 0x00002c040e197981 */
/* 0x000f62000c1e1900 */
/*0560*/ IMAD.WIDE R18, R2, 0x4, R16 ; /* 0x0000000402127825 */
/* 0x002fc600078e0210 */
/*0570*/ LDG.E R17, [R14.64+0x30] ; /* 0x000030040e117981 */
/* 0x001162000c1e1900 */
/*0580*/ IMAD R27, R27, R20, RZ ; /* 0x000000141b1b7224 */
/* 0x008fe400078e02ff */
/*0590*/ IMAD R29, R28, R21, RZ ; /* 0x000000151c1d7224 */
/* 0x010fe400078e02ff */
/*05a0*/ IMAD.WIDE R20, R2, 0x4, R18 ; /* 0x0000000402147825 */
/* 0x000fe200078e0212 */
/*05b0*/ LDG.E R28, [R18.64] ; /* 0x00000004121c7981 */
/* 0x0002e8000c1e1900 */
/*05c0*/ LDG.E R18, [R20.64] ; /* 0x0000000414127981 */
/* 0x002322000c1e1900 */
/*05d0*/ IMAD R16, R9, R12, RZ ; /* 0x0000000c09107224 */
/* 0x004fc600078e02ff */
/*05e0*/ LDG.E R19, [R14.64+0x34] ; /* 0x000034040e137981 */
/* 0x000122000c1e1900 */
/*05f0*/ IMAD R11, R8, R11, RZ ; /* 0x0000000b080b7224 */
/* 0x020fe400078e02ff */
/*0600*/ IMAD.WIDE R8, R2, 0x4, R20 ; /* 0x0000000402087825 */
/* 0x000fc800078e0214 */
/*0610*/ IMAD R24, R13, R24, RZ ; /* 0x000000180d187224 */
/* 0x000fe400078e02ff */
/*0620*/ IMAD.WIDE R12, R2, 0x4, R8 ; /* 0x00000004020c7825 */
/* 0x000fc800078e0208 */
/*0630*/ IMAD R26, R26, R25, RZ ; /* 0x000000191a1a7224 */
/* 0x000fe200078e02ff */
/*0640*/ LDG.E R20, [R12.64] ; /* 0x000000040c147981 */
/* 0x002ea8000c1e1900 */
/*0650*/ LDG.E R25, [R8.64] ; /* 0x0000000408197981 */
/* 0x000368000c1e1900 */
/*0660*/ LDG.E R8, [R14.64+0x38] ; /* 0x000038040e087981 */
/* 0x002168000c1e1900 */
/*0670*/ LDG.E R9, [R14.64+0x3c] ; /* 0x00003c040e097981 */
/* 0x0000a2000c1e1900 */
/*0680*/ I2F R22, R22 ; /* 0x0000001600167306 */
/* 0x000e700000201400 */
/*0690*/ I2F R23, R23 ; /* 0x0000001700177306 */
/* 0x000e300000201400 */
/*06a0*/ I2F R27, R27 ; /* 0x0000001b001b7306 */
/* 0x000e220000201400 */
/*06b0*/ FADD R10, R10, R22 ; /* 0x000000160a0a7221 */
/* 0x002fce0000000000 */
/*06c0*/ I2F R29, R29 ; /* 0x0000001d001d7306 */
/* 0x000e620000201400 */
/*06d0*/ FADD R14, R10, R23 ; /* 0x000000170a0e7221 */
/* 0x001fce0000000000 */
/*06e0*/ I2F R11, R11 ; /* 0x0000000b000b7306 */
/* 0x000e220000201400 */
/*06f0*/ FADD R14, R14, R27 ; /* 0x0000001b0e0e7221 */
/* 0x000fce0000000000 */
/*0700*/ I2F R16, R16 ; /* 0x0000001000107306 */
/* 0x000e220000201400 */
/*0710*/ FADD R14, R14, R29 ; /* 0x0000001d0e0e7221 */
/* 0x002fce0000000000 */
/*0720*/ I2F R24, R24 ; /* 0x0000001800187306 */
/* 0x000e620000201400 */
/*0730*/ FADD R11, R14, R11 ; /* 0x0000000b0e0b7221 */
/* 0x001fce0000000000 */
/*0740*/ I2F R26, R26 ; /* 0x0000001a001a7306 */
/* 0x000e220000201400 */
/*0750*/ FADD R11, R11, R16 ; /* 0x000000100b0b7221 */
/* 0x000fe20000000000 */
/*0760*/ IADD3 R7, R7, -0x10, RZ ; /* 0xfffffff007077810 */
/* 0x000fc60007ffe0ff */
/*0770*/ FADD R11, R11, R24 ; /* 0x000000180b0b7221 */
/* 0x002fe20000000000 */
/*0780*/ ISETP.GT.AND P1, PT, R7, 0xc, PT ; /* 0x0000000c0700780c */
/* 0x000fc60003f24270 */
/*0790*/ FADD R11, R11, R26 ; /* 0x0000001a0b0b7221 */
/* 0x001fe20000000000 */
/*07a0*/ UIADD3 UR6, UP0, UR6, 0x40, URZ ; /* 0x0000004006067890 */
/* 0x000fe2000ff1e03f */
/*07b0*/ IADD3 R4, R4, 0x10, RZ ; /* 0x0000001004047810 */
/* 0x000fc60007ffe0ff */
/*07c0*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*07d0*/ IMAD.WIDE R22, R2, 0x4, R12 ; /* 0x0000000402167825 */
/* 0x000fc800078e020c */
/*07e0*/ IMAD R17, R28, R17, RZ ; /* 0x000000111c117224 */
/* 0x008fc800078e02ff */
/*07f0*/ I2F R10, R17 ; /* 0x00000011000a7306 */
/* 0x000e220000201400 */
/*0800*/ IMAD R18, R18, R19, RZ ; /* 0x0000001312127224 */
/* 0x010fce00078e02ff */
/*0810*/ I2F R15, R18 ; /* 0x00000012000f7306 */
/* 0x000e620000201400 */
/*0820*/ FADD R10, R11, R10 ; /* 0x0000000a0b0a7221 */
/* 0x001fe40000000000 */
/*0830*/ IMAD R8, R25, R8, RZ ; /* 0x0000000819087224 */
/* 0x020fe400078e02ff */
/*0840*/ IMAD R9, R20, R9, RZ ; /* 0x0000000914097224 */
/* 0x004fc600078e02ff */
/*0850*/ I2F R19, R8 ; /* 0x0000000800137306 */
/* 0x000e300000201400 */
/*0860*/ I2F R9, R9 ; /* 0x0000000900097306 */
/* 0x000ea20000201400 */
/*0870*/ FADD R10, R10, R15 ; /* 0x0000000f0a0a7221 */
/* 0x002fc80000000000 */
/*0880*/ FADD R10, R10, R19 ; /* 0x000000130a0a7221 */
/* 0x001fc80000000000 */
/*0890*/ FADD R11, R10, R9 ; /* 0x000000090a0b7221 */
/* 0x004fe20000000000 */
/*08a0*/ @P1 BRA 0x220 ; /* 0xfffff97000001947 */
/* 0x000fea000383ffff */
/*08b0*/ ISETP.GT.AND P1, PT, R7, 0x4, PT ; /* 0x000000040700780c */
/* 0x000fda0003f24270 */
/*08c0*/ @!P1 BRA 0xc50 ; /* 0x0000038000009947 */
/* 0x000fea0003800000 */
/*08d0*/ IMAD.WIDE R20, R2, 0x4, R22 ; /* 0x0000000402147825 */
/* 0x000fe200078e0216 */
/*08e0*/ MOV R8, UR6 ; /* 0x0000000600087c02 */
/* 0x000fe20008000f00 */
/*08f0*/ LDG.E R22, [R22.64] ; /* 0x0000000416167981 */
/* 0x0000a2000c1e1900 */
/*0900*/ MOV R9, UR7 ; /* 0x0000000700097c02 */
/* 0x000fc60008000f00 */
/*0910*/ IMAD.WIDE R12, R2, 0x4, R20 ; /* 0x00000004020c7825 */
/* 0x000fe200078e0214 */
/*0920*/ LDG.E R10, [R20.64] ; /* 0x00000004140a7981 */
/* 0x0002e6000c1e1900 */
/*0930*/ IMAD.WIDE R8, R6, 0x4, R8 ; /* 0x0000000406087825 */
/* 0x000fe200078e0208 */
/*0940*/ LDG.E R27, [R12.64] ; /* 0x000000040c1b7981 */
/* 0x000966000c1e1900 */
/*0950*/ IMAD.WIDE R14, R2.reuse, 0x4, R12 ; /* 0x00000004020e7825 */
/* 0x040fe200078e020c */
/*0960*/ LDG.E R25, [R8.64] ; /* 0x0000000408197981 */
/* 0x000ea8000c1e1900 */
/*0970*/ LDG.E R23, [R8.64+0x4] ; /* 0x0000040408177981 */
/* 0x001ee2000c1e1900 */
/*0980*/ IMAD.WIDE R16, R2, 0x4, R14 ; /* 0x0000000402107825 */
/* 0x000fc600078e020e */
/*0990*/ LDG.E R26, [R8.64+0x8] ; /* 0x00000804081a7981 */
/* 0x000f66000c1e1900 */
/*09a0*/ IMAD.WIDE R18, R2.reuse, 0x4, R16 ; /* 0x0000000402127825 */
/* 0x040fe200078e0210 */
/*09b0*/ LDG.E R24, [R14.64] ; /* 0x000000040e187981 */
/* 0x000168000c1e1900 */
/*09c0*/ LDG.E R29, [R8.64+0xc] ; /* 0x00000c04081d7981 */
/* 0x000f62000c1e1900 */
/*09d0*/ IMAD.WIDE R20, R2, 0x4, R18 ; /* 0x0000000402147825 */
/* 0x002fc600078e0212 */
/*09e0*/ LDG.E R28, [R8.64+0x10] ; /* 0x00001004081c7981 */
/* 0x000f68000c1e1900 */
/*09f0*/ LDG.E R15, [R16.64] ; /* 0x00000004100f7981 */
/* 0x001162000c1e1900 */
/*0a00*/ IMAD.WIDE R12, R2, 0x4, R20 ; /* 0x00000004020c7825 */
/* 0x010fc600078e0214 */
/*0a10*/ LDG.E R14, [R8.64+0x14] ; /* 0x00001404080e7981 */
/* 0x000f28000c1e1900 */
/*0a20*/ LDG.E R17, [R18.64] ; /* 0x0000000412117981 */
/* 0x001128000c1e1900 */
/*0a30*/ LDG.E R16, [R20.64] ; /* 0x0000000414107981 */
/* 0x000328000c1e1900 */
/*0a40*/ LDG.E R19, [R8.64+0x18] ; /* 0x0000180408137981 */
/* 0x001128000c1e1900 */
/*0a50*/ LDG.E R18, [R8.64+0x1c] ; /* 0x00001c0408127981 */
/* 0x000128000c1e1900 */
/*0a60*/ LDG.E R21, [R12.64] ; /* 0x000000040c157981 */
/* 0x002f22000c1e1900 */
/*0a70*/ UIADD3 UR6, UP0, UR6, 0x20, URZ ; /* 0x0000002006067890 */
/* 0x000fe2000ff1e03f */
/*0a80*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc40003f0e170 */
/*0a90*/ IADD3 R4, R4, 0x8, RZ ; /* 0x0000000804047810 */
/* 0x000fe40007ffe0ff */
/*0aa0*/ IADD3 R7, R7, -0x8, RZ ; /* 0xfffffff807077810 */
/* 0x000fe20007ffe0ff */
/*0ab0*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0ac0*/ IMAD R22, R22, R25, RZ ; /* 0x0000001916167224 */
/* 0x004fe400078e02ff */
/*0ad0*/ IMAD R10, R10, R23, RZ ; /* 0x000000170a0a7224 */
/* 0x008fc800078e02ff */
/*0ae0*/ I2F R22, R22 ; /* 0x0000001600167306 */
/* 0x000e620000201400 */
/*0af0*/ IMAD R23, R27, R26, RZ ; /* 0x0000001a1b177224 */
/* 0x020fce00078e02ff */
/*0b00*/ I2F R10, R10 ; /* 0x0000000a000a7306 */
/* 0x000ea20000201400 */
/*0b10*/ IMAD R20, R24, R29, RZ ; /* 0x0000001d18147224 */
/* 0x000fce00078e02ff */
/*0b20*/ I2F R23, R23 ; /* 0x0000001700177306 */
/* 0x000ee20000201400 */
/*0b30*/ IMAD R15, R15, R28, RZ ; /* 0x0000001c0f0f7224 */
/* 0x000fe400078e02ff */
/*0b40*/ FADD R11, R11, R22 ; /* 0x000000160b0b7221 */
/* 0x002fca0000000000 */
/*0b50*/ I2F R20, R20 ; /* 0x0000001400147306 */
/* 0x000e620000201400 */
/*0b60*/ IMAD R14, R17, R14, RZ ; /* 0x0000000e110e7224 */
/* 0x010fce00078e02ff */
/*0b70*/ I2F R8, R15 ; /* 0x0000000f00087306 */
/* 0x001e220000201400 */
/*0b80*/ FADD R10, R11, R10 ; /* 0x0000000a0b0a7221 */
/* 0x004fe40000000000 */
/*0b90*/ IMAD R16, R16, R19, RZ ; /* 0x0000001310107224 */
/* 0x000fca00078e02ff */
/*0ba0*/ I2F R9, R14 ; /* 0x0000000e00097306 */
/* 0x000ea20000201400 */
/*0bb0*/ FADD R23, R10, R23 ; /* 0x000000170a177221 */
/* 0x008fe40000000000 */
/*0bc0*/ IMAD R18, R21, R18, RZ ; /* 0x0000001215127224 */
/* 0x000fca00078e02ff */
/*0bd0*/ I2F R11, R16 ; /* 0x00000010000b7306 */
/* 0x000ee20000201400 */
/*0be0*/ FADD R23, R23, R20 ; /* 0x0000001417177221 */
/* 0x002fce0000000000 */
/*0bf0*/ I2F R18, R18 ; /* 0x0000001200127306 */
/* 0x000e620000201400 */
/*0c00*/ FADD R8, R23, R8 ; /* 0x0000000817087221 */
/* 0x001fc80000000000 */
/*0c10*/ FADD R8, R8, R9 ; /* 0x0000000908087221 */
/* 0x004fc80000000000 */
/*0c20*/ FADD R11, R8, R11 ; /* 0x0000000b080b7221 */
/* 0x008fe40000000000 */
/*0c30*/ IMAD.WIDE R22, R2, 0x4, R12 ; /* 0x0000000402167825 */
/* 0x000fc800078e020c */
/*0c40*/ FADD R11, R11, R18 ; /* 0x000000120b0b7221 */
/* 0x002fe40000000000 */
/*0c50*/ ISETP.NE.OR P0, PT, R7, RZ, P0 ; /* 0x000000ff0700720c */
/* 0x000fda0000705670 */
/*0c60*/ @!P0 BRA 0xe80 ; /* 0x0000021000008947 */
/* 0x000fea0003800000 */
/*0c70*/ MOV R8, UR6 ; /* 0x0000000600087c02 */
/* 0x000fe20008000f00 */
/*0c80*/ IMAD.WIDE R16, R2, 0x4, R22 ; /* 0x0000000402107825 */
/* 0x000fe200078e0216 */
/*0c90*/ MOV R9, UR7 ; /* 0x0000000700097c02 */
/* 0x000fe20008000f00 */
/*0ca0*/ LDG.E R22, [R22.64] ; /* 0x0000000416167981 */
/* 0x000ea8000c1e1900 */
/*0cb0*/ IMAD.WIDE R8, R6, 0x4, R8 ; /* 0x0000000406087825 */
/* 0x000fc800078e0208 */
/*0cc0*/ IMAD.WIDE R14, R2.reuse, 0x4, R16 ; /* 0x00000004020e7825 */
/* 0x040fe200078e0210 */
/*0cd0*/ LDG.E R19, [R8.64] ; /* 0x0000000408137981 */
/* 0x000ea8000c1e1900 */
/*0ce0*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x000ee8000c1e1900 */
/*0cf0*/ LDG.E R21, [R8.64+0x4] ; /* 0x0000040408157981 */
/* 0x000ee2000c1e1900 */
/*0d00*/ IMAD.WIDE R12, R2, 0x4, R14 ; /* 0x00000004020c7825 */
/* 0x000fc600078e020e */
/*0d10*/ LDG.E R18, [R14.64] ; /* 0x000000040e127981 */
/* 0x000f28000c1e1900 */
/*0d20*/ LDG.E R25, [R8.64+0x8] ; /* 0x0000080408197981 */
/* 0x000f28000c1e1900 */
/*0d30*/ LDG.E R27, [R8.64+0xc] ; /* 0x00000c04081b7981 */
/* 0x000f68000c1e1900 */
/*0d40*/ LDG.E R20, [R12.64] ; /* 0x000000040c147981 */
/* 0x000f62000c1e1900 */
/*0d50*/ IADD3 R7, R7, -0x4, RZ ; /* 0xfffffffc07077810 */
/* 0x000fc80007ffe0ff */
/*0d60*/ ISETP.NE.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fe20003f05270 */
/*0d70*/ UIADD3 UR6, UP0, UR6, 0x10, URZ ; /* 0x0000001006067890 */
/* 0x000fe2000ff1e03f */
/*0d80*/ IADD3 R4, R4, 0x4, RZ ; /* 0x0000000404047810 */
/* 0x000fc60007ffe0ff */
/*0d90*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0da0*/ IMAD R19, R22, R19, RZ ; /* 0x0000001316137224 */
/* 0x004fc800078e02ff */
/*0db0*/ I2F R10, R19 ; /* 0x00000013000a7306 */
/* 0x000e220000201400 */
/*0dc0*/ IMAD R21, R16, R21, RZ ; /* 0x0000001510157224 */
/* 0x008fce00078e02ff */
/*0dd0*/ I2F R21, R21 ; /* 0x0000001500157306 */
/* 0x000e620000201400 */
/*0de0*/ IMAD R18, R18, R25, RZ ; /* 0x0000001912127224 */
/* 0x010fce00078e02ff */
/*0df0*/ I2F R17, R18 ; /* 0x0000001200117306 */
/* 0x000ea20000201400 */
/*0e00*/ IMAD R20, R20, R27, RZ ; /* 0x0000001b14147224 */
/* 0x020fe400078e02ff */
/*0e10*/ FADD R10, R10, R11 ; /* 0x0000000b0a0a7221 */
/* 0x001fca0000000000 */
/*0e20*/ I2F R15, R20 ; /* 0x00000014000f7306 */
/* 0x000e220000201400 */
/*0e30*/ FADD R10, R10, R21 ; /* 0x000000150a0a7221 */
/* 0x002fe40000000000 */
/*0e40*/ IMAD.WIDE R22, R2, 0x4, R12 ; /* 0x0000000402167825 */
/* 0x000fc800078e020c */
/*0e50*/ FADD R10, R10, R17 ; /* 0x000000110a0a7221 */
/* 0x004fc80000000000 */
/*0e60*/ FADD R11, R10, R15 ; /* 0x0000000f0a0b7221 */
/* 0x001fe20000000000 */
/*0e70*/ @P0 BRA 0xc70 ; /* 0xfffffdf000000947 */
/* 0x000fea000383ffff */
/*0e80*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fda0003f05270 */
/*0e90*/ @!P0 BRA 0xfc0 ; /* 0x0000012000008947 */
/* 0x000fea0003800000 */
/*0ea0*/ HFMA2.MMA R9, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff097435 */
/* 0x000fe200000001ff */
/*0eb0*/ IMAD R6, R3, c[0x0][0x178], R4 ; /* 0x00005e0003067a24 */
/* 0x000fe400078e0204 */
/*0ec0*/ IMAD R4, R4, c[0x0][0x178], R0 ; /* 0x00005e0004047a24 */
/* 0x000fce00078e0200 */
/*0ed0*/ IMAD.WIDE R6, R6, R9, c[0x0][0x160] ; /* 0x0000580006067625 */
/* 0x000fc800078e0209 */
/*0ee0*/ IMAD.WIDE R8, R4, R9, c[0x0][0x168] ; /* 0x00005a0004087625 */
/* 0x000fe200078e0209 */
/*0ef0*/ MOV R13, R7 ; /* 0x00000007000d7202 */
/* 0x000fc80000000f00 */
/*0f00*/ MOV R7, R13 ; /* 0x0000000d00077202 */
/* 0x000fe20000000f00 */
/*0f10*/ LDG.E R4, [R8.64] ; /* 0x0000000408047981 */
/* 0x0000aa000c1e1900 */
/*0f20*/ LDG.E R7, [R6.64] ; /* 0x0000000406077981 */
/* 0x0002a2000c1e1900 */
/*0f30*/ IADD3 R5, R5, -0x1, RZ ; /* 0xffffffff05057810 */
/* 0x000fc80007ffe0ff */
/*0f40*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe20003f05270 */
/*0f50*/ IMAD.WIDE R8, R2, 0x4, R8 ; /* 0x0000000402087825 */
/* 0x001fe200078e0208 */
/*0f60*/ IADD3 R6, P1, R6, 0x4, RZ ; /* 0x0000000406067810 */
/* 0x002fc80007f3e0ff */
/*0f70*/ IADD3.X R13, RZ, R13, RZ, P1, !PT ; /* 0x0000000dff0d7210 */
/* 0x000fe20000ffe4ff */
/*0f80*/ IMAD R4, R4, R7, RZ ; /* 0x0000000704047224 */
/* 0x004fcc00078e02ff */
/*0f90*/ I2F R4, R4 ; /* 0x0000000400047306 */
/* 0x000e240000201400 */
/*0fa0*/ FADD R11, R4, R11 ; /* 0x0000000b040b7221 */
/* 0x001fe20000000000 */
/*0fb0*/ @P0 BRA 0xf00 ; /* 0xffffff4000000947 */
/* 0x000fea000383ffff */
/*0fc0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0fd0*/ F2I.TRUNC.NTZ R11, R11 ; /* 0x0000000b000b7305 */
/* 0x000e22000020f100 */
/*0fe0*/ HFMA2.MMA R2, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff027435 */
/* 0x000fe200000001ff */
/*0ff0*/ IMAD R3, R3, c[0x0][0x178], R0 ; /* 0x00005e0003037a24 */
/* 0x000fd200078e0200 */
/*1000*/ IMAD.WIDE R2, R3, R2, c[0x0][0x170] ; /* 0x00005c0003027625 */
/* 0x000fca00078e0202 */
/*1010*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x001fe2000c101904 */
/*1020*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*1030*/ BRA 0x1030; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*1040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*10a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*10b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*10c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*10d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*10e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*10f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z26matrixMultiplicationKernelPiS_S_i
.globl _Z26matrixMultiplicationKernelPiS_S_i
.p2align 8
.type _Z26matrixMultiplicationKernelPiS_S_i,@function
_Z26matrixMultiplicationKernelPiS_S_i:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x2c
s_load_b32 s2, s[0:1], 0x18
v_bfe_u32 v2, v0, 10, 10
v_and_b32_e32 v3, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s4, s3, 16
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[0:1], null, s15, s4, v[2:3]
v_mad_u64_u32 v[1:2], null, s14, s3, v[3:4]
v_max3_i32 v2, v0, v1, 0
s_delay_alu instid0(VALU_DEP_1)
v_cmp_gt_i32_e32 vcc_lo, s2, v2
v_mov_b32_e32 v2, 0
s_and_saveexec_b32 s3, vcc_lo
s_cbranch_execz .LBB0_4
s_load_b128 s[4:7], s[0:1], 0x0
v_mul_lo_u32 v2, v0, s2
v_mov_b32_e32 v6, 0
v_mov_b32_e32 v4, v1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
s_mov_b32 s4, s2
.p2align 6
.LBB0_2:
v_ashrrev_i32_e32 v5, 31, v4
s_add_i32 s4, s4, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_cmp_eq_u32 s4, 0
v_lshlrev_b64 v[7:8], 2, v[4:5]
v_add_nc_u32_e32 v4, s2, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v7, vcc_lo, s6, v7
v_add_co_ci_u32_e32 v8, vcc_lo, s7, v8, vcc_lo
global_load_b32 v5, v[2:3], off
global_load_b32 v7, v[7:8], off
v_add_co_u32 v2, vcc_lo, v2, 4
v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
s_waitcnt vmcnt(0)
v_mul_lo_u32 v5, v7, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_f32_i32_e32 v5, v5
v_add_f32_e32 v6, v6, v5
s_cbranch_scc0 .LBB0_2
s_delay_alu instid0(VALU_DEP_1)
v_cvt_i32_f32_e32 v2, v6
.LBB0_4:
s_or_b32 exec_lo, exec_lo, s3
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[3:4], null, v0, s2, v[1:2]
v_ashrrev_i32_e32 v4, 31, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[3:4]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z26matrixMultiplicationKernelPiS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z26matrixMultiplicationKernelPiS_S_i, .Lfunc_end0-_Z26matrixMultiplicationKernelPiS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z26matrixMultiplicationKernelPiS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z26matrixMultiplicationKernelPiS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00155131_00000000-6_mm.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3673:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3673:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z51__device_stub__Z26matrixMultiplicationKernelPiS_S_iPiS_S_i
.type _Z51__device_stub__Z26matrixMultiplicationKernelPiS_S_iPiS_S_i, @function
_Z51__device_stub__Z26matrixMultiplicationKernelPiS_S_iPiS_S_i:
.LFB3695:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z26matrixMultiplicationKernelPiS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3695:
.size _Z51__device_stub__Z26matrixMultiplicationKernelPiS_S_iPiS_S_i, .-_Z51__device_stub__Z26matrixMultiplicationKernelPiS_S_iPiS_S_i
.globl _Z26matrixMultiplicationKernelPiS_S_i
.type _Z26matrixMultiplicationKernelPiS_S_i, @function
_Z26matrixMultiplicationKernelPiS_S_i:
.LFB3696:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z51__device_stub__Z26matrixMultiplicationKernelPiS_S_iPiS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3696:
.size _Z26matrixMultiplicationKernelPiS_S_i, .-_Z26matrixMultiplicationKernelPiS_S_i
.globl _Z20matrixMultiplicationPiS_S_i
.type _Z20matrixMultiplicationPiS_S_i, @function
_Z20matrixMultiplicationPiS_S_i:
.LFB3670:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $40, %rsp
.cfi_def_cfa_offset 80
movq %rdi, %rbp
movq %rsi, %r12
movq %rdx, %r13
movl %ecx, %ebx
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl %ecx, %eax
imull %ecx, %eax
cmpl $512, %eax
jg .L12
movl %ecx, %eax
jmp .L13
.L12:
pxor %xmm0, %xmm0
cvtsi2sdl %ecx, %xmm0
mulsd .LC0(%rip), %xmm0
movapd %xmm0, %xmm3
movsd .LC4(%rip), %xmm2
movapd %xmm0, %xmm1
andpd %xmm2, %xmm1
movsd .LC1(%rip), %xmm4
ucomisd %xmm1, %xmm4
jbe .L14
cvttsd2siq %xmm0, %rax
pxor %xmm1, %xmm1
cvtsi2sdq %rax, %xmm1
cmpnlesd %xmm1, %xmm3
movsd .LC3(%rip), %xmm4
andpd %xmm4, %xmm3
addsd %xmm1, %xmm3
andnpd %xmm0, %xmm2
orpd %xmm2, %xmm3
.L14:
cvttsd2siq %xmm3, %rax
movl %eax, 20(%rsp)
movl %eax, 24(%rsp)
movl $512, %eax
.L13:
movl %eax, 8(%rsp)
movl %eax, 12(%rsp)
movl 16(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 8(%rsp), %rdx
movq 20(%rsp), %rdi
movl 28(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L17
.L11:
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
movl %ebx, %ecx
movq %r13, %rdx
movq %r12, %rsi
movq %rbp, %rdi
call _Z51__device_stub__Z26matrixMultiplicationKernelPiS_S_iPiS_S_i
jmp .L11
.cfi_endproc
.LFE3670:
.size _Z20matrixMultiplicationPiS_S_i, .-_Z20matrixMultiplicationPiS_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC5:
.string " %d"
.LC6:
.string "\n"
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $56, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movl $1024, %edi
call malloc@PLT
movq %rax, %rbp
movl $1024, %edi
call malloc@PLT
movq %rax, %rbx
movl $1024, %edi
call malloc@PLT
movq %rax, 8(%rsp)
leaq 16(%rsp), %rdi
movl $1024, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $1024, %esi
call cudaMalloc@PLT
leaq 32(%rsp), %rdi
movl $1024, %esi
call cudaMalloc@PLT
movl $64, %edx
.L19:
leaq -64(%rdx), %rax
.L20:
movl $2, 0(%rbp,%rax)
movl $3, (%rbx,%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L20
addq $64, %rdx
cmpq $1088, %rdx
jne .L19
movl $1, %ecx
movl $1024, %edx
movq %rbp, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $1024, %edx
movq %rbx, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl $16, %ecx
movq 32(%rsp), %rdx
movq 24(%rsp), %rsi
movq 16(%rsp), %rdi
call _Z20matrixMultiplicationPiS_S_i
movl $2, %ecx
movl $1024, %edx
movq 32(%rsp), %rsi
movq 8(%rsp), %r15
movq %r15, %rdi
call cudaMemcpy@PLT
leaq 16(%r15), %r13
movl $0, %r15d
leaq .LC5(%rip), %r14
.L22:
leaq -16(%r13), %r12
.L23:
movl (%r12), %edx
movq %r14, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %r12
cmpq %r13, %r12
jne .L23
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $16, %r15d
addq $64, %r13
cmpl $64, %r15d
jne .L22
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq %rbp, %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movq 8(%rsp), %rdi
call free@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L29
movl $0, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L29:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size main, .-main
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC7:
.string "_Z26matrixMultiplicationKernelPiS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3698:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _Z26matrixMultiplicationKernelPiS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3698:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long 0
.long 1063256064
.align 8
.LC1:
.long 0
.long 1127219200
.align 8
.LC3:
.long 0
.long 1072693248
.align 8
.LC4:
.long -1
.long 2147483647
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "mm.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z41__device_stub__matrixMultiplicationKernelPiS_S_i # -- Begin function _Z41__device_stub__matrixMultiplicationKernelPiS_S_i
.p2align 4, 0x90
.type _Z41__device_stub__matrixMultiplicationKernelPiS_S_i,@function
_Z41__device_stub__matrixMultiplicationKernelPiS_S_i: # @_Z41__device_stub__matrixMultiplicationKernelPiS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z26matrixMultiplicationKernelPiS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z41__device_stub__matrixMultiplicationKernelPiS_S_i, .Lfunc_end0-_Z41__device_stub__matrixMultiplicationKernelPiS_S_i
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $24, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $1024, %edi # imm = 0x400
callq malloc
movq %rax, %rbx
movl $1024, %edi # imm = 0x400
callq malloc
movq %rax, %r14
movl $1024, %edi # imm = 0x400
callq malloc
movq %rax, %r15
leaq 16(%rsp), %rdi
movl $1024, %esi # imm = 0x400
callq hipMalloc
leaq 8(%rsp), %rdi
movl $1024, %esi # imm = 0x400
callq hipMalloc
movq %rsp, %rdi
movl $1024, %esi # imm = 0x400
callq hipMalloc
xorl %eax, %eax
movq %rbx, %rcx
movq %r14, %rdx
.p2align 4, 0x90
.LBB1_1: # %.preheader43
# =>This Loop Header: Depth=1
# Child Loop BB1_2 Depth 2
xorl %esi, %esi
.p2align 4, 0x90
.LBB1_2: # Parent Loop BB1_1 Depth=1
# => This Inner Loop Header: Depth=2
movl $2, (%rcx,%rsi,4)
movl $3, (%rdx,%rsi,4)
incq %rsi
cmpq $16, %rsi
jne .LBB1_2
# %bb.3: # in Loop: Header=BB1_1 Depth=1
incq %rax
addq $64, %rdx
addq $64, %rcx
cmpq $16, %rax
jne .LBB1_1
# %bb.4:
movq 16(%rsp), %rdi
movl $1024, %edx # imm = 0x400
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
movl $1024, %edx # imm = 0x400
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
movq 8(%rsp), %rsi
movq (%rsp), %rdx
movl $16, %ecx
callq _Z20matrixMultiplicationPiS_S_i
movq (%rsp), %rsi
movl $1024, %edx # imm = 0x400
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
movq %r15, %r12
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB1_5: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_6 Depth 2
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB1_6: # Parent Loop BB1_5 Depth=1
# => This Inner Loop Header: Depth=2
movl (%r12,%rbp,4), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
incq %rbp
cmpq $4, %rbp
jne .LBB1_6
# %bb.7: # in Loop: Header=BB1_5 Depth=1
movl $10, %edi
callq putchar@PLT
incq %r13
addq $64, %r12
cmpq $4, %r13
jne .LBB1_5
# %bb.8:
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
xorl %eax, %eax
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z20matrixMultiplicationPiS_S_i
.LCPI2_0:
.quad 0x3f60000000000000 # double 0.001953125
.text
.globl _Z20matrixMultiplicationPiS_S_i
.p2align 4, 0x90
.type _Z20matrixMultiplicationPiS_S_i,@function
_Z20matrixMultiplicationPiS_S_i: # @_Z20matrixMultiplicationPiS_S_i
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $112, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl %ecx, %ebx
movq %rdx, %r14
movq %rsi, %r15
movq %rdi, %r12
movabsq $4294967297, %r13 # imm = 0x100000001
movl %ecx, %eax
imull %ecx, %eax
cmpl $513, %eax # imm = 0x201
jb .LBB2_1
# %bb.2:
cvtsi2sd %ebx, %xmm0
mulsd .LCPI2_0(%rip), %xmm0
callq ceil@PLT
cvttsd2si %xmm0, %rax
movl %eax, %eax
imulq %rax, %r13
movabsq $2199023256064, %rdx # imm = 0x20000000200
jmp .LBB2_3
.LBB2_1:
movl %ebx, %eax
movq %rax, %rdx
shlq $32, %rdx
orq %rax, %rdx
.LBB2_3:
movq %r13, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_5
# %bb.4:
movq %r12, 72(%rsp)
movq %r15, 64(%rsp)
movq %r14, 56(%rsp)
movl %ebx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z26matrixMultiplicationKernelPiS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_5:
addq $112, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z20matrixMultiplicationPiS_S_i, .Lfunc_end2-_Z20matrixMultiplicationPiS_S_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z26matrixMultiplicationKernelPiS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z26matrixMultiplicationKernelPiS_S_i,@object # @_Z26matrixMultiplicationKernelPiS_S_i
.section .rodata,"a",@progbits
.globl _Z26matrixMultiplicationKernelPiS_S_i
.p2align 3, 0x0
_Z26matrixMultiplicationKernelPiS_S_i:
.quad _Z41__device_stub__matrixMultiplicationKernelPiS_S_i
.size _Z26matrixMultiplicationKernelPiS_S_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz " %d"
.size .L.str, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z26matrixMultiplicationKernelPiS_S_i"
.size .L__unnamed_1, 38
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z41__device_stub__matrixMultiplicationKernelPiS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z26matrixMultiplicationKernelPiS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void mirrorImage_kernel(uint width, uint height, uint border, uint borderWidth, uint borderHeight, float* devInput, float* devOutput) {
int x0 = blockDim.x * blockIdx.x + threadIdx.x;
int y0 = blockDim.y * blockIdx.y + threadIdx.y;
if ((x0 < borderWidth) && (y0 < borderHeight)) {
int x1 = 0;
int y1 = 0;
if (x0 < border) {
x1 = border - x0 - 1;
} else if (x0 < border + width) {
x1 = x0 - border;
} else {
x1 = border + 2 * width - x0 - 1;
}
if (y0 < border) {
y1 = border - y0 - 1;
} else if (y0 < border + height) {
y1 = y0 - border;
} else {
y1 = border + 2 * height - y0 - 1;
}
devOutput[y0 * borderWidth + x0] = devInput[y1 * width + x1];
}
} | code for sm_80
Function : _Z18mirrorImage_kerneljjjjjPfS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R5, SR_CTAID.Y ; /* 0x0000000000057919 */
/* 0x000e280000002600 */
/*0020*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e280000002200 */
/*0030*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e680000002500 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e620000002100 */
/*0050*/ IMAD R5, R5, c[0x0][0x4], R2 ; /* 0x0000010005057a24 */
/* 0x001fca00078e0202 */
/*0060*/ ISETP.GE.U32.AND P0, PT, R5, c[0x0][0x170], PT ; /* 0x00005c0005007a0c */
/* 0x000fe20003f06070 */
/*0070*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x002fca00078e0203 */
/*0080*/ ISETP.GE.U32.OR P0, PT, R0, c[0x0][0x16c], P0 ; /* 0x00005b0000007a0c */
/* 0x000fda0000706470 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x168], PT ; /* 0x00005a0000007a0c */
/* 0x000fe20003f06070 */
/*00b0*/ BSSY B0, 0x180 ; /* 0x000000c000007945 */
/* 0x000fd80003800000 */
/*00c0*/ @!P0 BRA 0x150 ; /* 0x0000008000008947 */
/* 0x000fea0003800000 */
/*00d0*/ IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff077624 */
/* 0x000fe200078e00ff */
/*00e0*/ LOP3.LUT R2, RZ, R0, RZ, 0x33, !PT ; /* 0x00000000ff027212 */
/* 0x000fc800078e33ff */
/*00f0*/ IADD3 R3, R7.reuse, c[0x0][0x168], RZ ; /* 0x00005a0007037a10 */
/* 0x040fe20007ffe0ff */
/*0100*/ IMAD R2, R7, 0x2, R2 ; /* 0x0000000207027824 */
/* 0x000fc600078e0202 */
/*0110*/ ISETP.GE.U32.AND P0, PT, R0, R3, PT ; /* 0x000000030000720c */
/* 0x000fe40003f06070 */
/*0120*/ IADD3 R2, R2, c[0x0][0x168], RZ ; /* 0x00005a0002027a10 */
/* 0x000fd60007ffe0ff */
/*0130*/ @!P0 IADD3 R2, R0, -c[0x0][0x168], RZ ; /* 0x80005a0000028a10 */
/* 0x000fe20007ffe0ff */
/*0140*/ BRA 0x170 ; /* 0x0000002000007947 */
/* 0x000fea0003800000 */
/*0150*/ LOP3.LUT R2, RZ, R0, RZ, 0x33, !PT ; /* 0x00000000ff027212 */
/* 0x000fc800078e33ff */
/*0160*/ IADD3 R2, R2, c[0x0][0x168], RZ ; /* 0x00005a0002027a10 */
/* 0x000fe40007ffe0ff */
/*0170*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0180*/ ISETP.GE.U32.AND P0, PT, R5, c[0x0][0x168], PT ; /* 0x00005a0005007a0c */
/* 0x000fe20003f06070 */
/*0190*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*01a0*/ BSSY B0, 0x290 ; /* 0x000000e000007945 */
/* 0x000ff60003800000 */
/*01b0*/ @!P0 BRA 0x260 ; /* 0x000000a000008947 */
/* 0x000fea0003800000 */
/*01c0*/ ULDC UR4, c[0x0][0x168] ; /* 0x00005a0000047ab9 */
/* 0x000fe20000000800 */
/*01d0*/ LOP3.LUT R3, RZ, R5, RZ, 0x33, !PT ; /* 0x00000005ff037212 */
/* 0x000fe200078e33ff */
/*01e0*/ ULDC UR5, c[0x0][0x164] ; /* 0x0000590000057ab9 */
/* 0x000fe20000000800 */
/*01f0*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff047624 */
/* 0x000fe200078e00ff */
/*0200*/ UIADD3 UR4, UR4, UR5, URZ ; /* 0x0000000504047290 */
/* 0x000fe2000fffe03f */
/*0210*/ IADD3 R3, R3, c[0x0][0x168], RZ ; /* 0x00005a0003037a10 */
/* 0x000fca0007ffe0ff */
/*0220*/ ISETP.GE.U32.AND P0, PT, R5, UR4, PT ; /* 0x0000000405007c0c */
/* 0x000fe2000bf06070 */
/*0230*/ IMAD R3, R4, 0x2, R3 ; /* 0x0000000204037824 */
/* 0x000fd800078e0203 */
/*0240*/ @!P0 IADD3 R3, R5, -c[0x0][0x168], RZ ; /* 0x80005a0005038a10 */
/* 0x000fe20007ffe0ff */
/*0250*/ BRA 0x280 ; /* 0x0000002000007947 */
/* 0x000fea0003800000 */
/*0260*/ LOP3.LUT R3, RZ, R5, RZ, 0x33, !PT ; /* 0x00000005ff037212 */
/* 0x000fc800078e33ff */
/*0270*/ IADD3 R3, R3, c[0x0][0x168], RZ ; /* 0x00005a0003037a10 */
/* 0x000fe40007ffe0ff */
/*0280*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0290*/ IMAD.MOV.U32 R4, RZ, RZ, 0x4 ; /* 0x00000004ff047424 */
/* 0x000fe400078e00ff */
/*02a0*/ IMAD R2, R3, c[0x0][0x160], R2 ; /* 0x0000580003027a24 */
/* 0x000fc800078e0202 */
/*02b0*/ IMAD.WIDE.U32 R2, R2, R4, c[0x0][0x178] ; /* 0x00005e0002027625 */
/* 0x000fcc00078e0004 */
/*02c0*/ LDG.E R3, [R2.64] ; /* 0x0000000602037981 */
/* 0x000ea2000c1e1900 */
/*02d0*/ IMAD R5, R5, c[0x0][0x16c], R0 ; /* 0x00005b0005057a24 */
/* 0x000fc800078e0200 */
/*02e0*/ IMAD.WIDE.U32 R4, R5, R4, c[0x0][0x180] ; /* 0x0000600005047625 */
/* 0x000fca00078e0004 */
/*02f0*/ STG.E [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x004fe2000c101906 */
/*0300*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0310*/ BRA 0x310; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0320*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0380*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0390*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void mirrorImage_kernel(uint width, uint height, uint border, uint borderWidth, uint borderHeight, float* devInput, float* devOutput) {
int x0 = blockDim.x * blockIdx.x + threadIdx.x;
int y0 = blockDim.y * blockIdx.y + threadIdx.y;
if ((x0 < borderWidth) && (y0 < borderHeight)) {
int x1 = 0;
int y1 = 0;
if (x0 < border) {
x1 = border - x0 - 1;
} else if (x0 < border + width) {
x1 = x0 - border;
} else {
x1 = border + 2 * width - x0 - 1;
}
if (y0 < border) {
y1 = border - y0 - 1;
} else if (y0 < border + height) {
y1 = y0 - border;
} else {
y1 = border + 2 * height - y0 - 1;
}
devOutput[y0 * borderWidth + x0] = devInput[y1 * width + x1];
}
} | .file "tmpxft_0004faf2_00000000-6_mirrorImage_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z45__device_stub__Z18mirrorImage_kerneljjjjjPfS_jjjjjPfS_
.type _Z45__device_stub__Z18mirrorImage_kerneljjjjjPfS_jjjjjPfS_, @function
_Z45__device_stub__Z18mirrorImage_kerneljjjjjPfS_jjjjjPfS_:
.LFB2051:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movl %edi, 44(%rsp)
movl %esi, 40(%rsp)
movl %edx, 36(%rsp)
movl %ecx, 32(%rsp)
movl %r8d, 28(%rsp)
movq %r9, 16(%rsp)
movq 192(%rsp), %rax
movq %rax, 8(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 44(%rsp), %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rax
movq %rax, 120(%rsp)
leaq 36(%rsp), %rax
movq %rax, 128(%rsp)
leaq 32(%rsp), %rax
movq %rax, 136(%rsp)
leaq 28(%rsp), %rax
movq %rax, 144(%rsp)
leaq 16(%rsp), %rax
movq %rax, 152(%rsp)
leaq 8(%rsp), %rax
movq %rax, 160(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z18mirrorImage_kerneljjjjjPfS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z45__device_stub__Z18mirrorImage_kerneljjjjjPfS_jjjjjPfS_, .-_Z45__device_stub__Z18mirrorImage_kerneljjjjjPfS_jjjjjPfS_
.globl _Z18mirrorImage_kerneljjjjjPfS_
.type _Z18mirrorImage_kerneljjjjjPfS_, @function
_Z18mirrorImage_kerneljjjjjPfS_:
.LFB2052:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
pushq 24(%rsp)
.cfi_def_cfa_offset 32
call _Z45__device_stub__Z18mirrorImage_kerneljjjjjPfS_jjjjjPfS_
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z18mirrorImage_kerneljjjjjPfS_, .-_Z18mirrorImage_kerneljjjjjPfS_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z18mirrorImage_kerneljjjjjPfS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z18mirrorImage_kerneljjjjjPfS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void mirrorImage_kernel(uint width, uint height, uint border, uint borderWidth, uint borderHeight, float* devInput, float* devOutput) {
int x0 = blockDim.x * blockIdx.x + threadIdx.x;
int y0 = blockDim.y * blockIdx.y + threadIdx.y;
if ((x0 < borderWidth) && (y0 < borderHeight)) {
int x1 = 0;
int y1 = 0;
if (x0 < border) {
x1 = border - x0 - 1;
} else if (x0 < border + width) {
x1 = x0 - border;
} else {
x1 = border + 2 * width - x0 - 1;
}
if (y0 < border) {
y1 = border - y0 - 1;
} else if (y0 < border + height) {
y1 = y0 - border;
} else {
y1 = border + 2 * height - y0 - 1;
}
devOutput[y0 * borderWidth + x0] = devInput[y1 * width + x1];
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void mirrorImage_kernel(uint width, uint height, uint border, uint borderWidth, uint borderHeight, float* devInput, float* devOutput) {
int x0 = blockDim.x * blockIdx.x + threadIdx.x;
int y0 = blockDim.y * blockIdx.y + threadIdx.y;
if ((x0 < borderWidth) && (y0 < borderHeight)) {
int x1 = 0;
int y1 = 0;
if (x0 < border) {
x1 = border - x0 - 1;
} else if (x0 < border + width) {
x1 = x0 - border;
} else {
x1 = border + 2 * width - x0 - 1;
}
if (y0 < border) {
y1 = border - y0 - 1;
} else if (y0 < border + height) {
y1 = y0 - border;
} else {
y1 = border + 2 * height - y0 - 1;
}
devOutput[y0 * borderWidth + x0] = devInput[y1 * width + x1];
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void mirrorImage_kernel(uint width, uint height, uint border, uint borderWidth, uint borderHeight, float* devInput, float* devOutput) {
int x0 = blockDim.x * blockIdx.x + threadIdx.x;
int y0 = blockDim.y * blockIdx.y + threadIdx.y;
if ((x0 < borderWidth) && (y0 < borderHeight)) {
int x1 = 0;
int y1 = 0;
if (x0 < border) {
x1 = border - x0 - 1;
} else if (x0 < border + width) {
x1 = x0 - border;
} else {
x1 = border + 2 * width - x0 - 1;
}
if (y0 < border) {
y1 = border - y0 - 1;
} else if (y0 < border + height) {
y1 = y0 - border;
} else {
y1 = border + 2 * height - y0 - 1;
}
devOutput[y0 * borderWidth + x0] = devInput[y1 * width + x1];
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z18mirrorImage_kerneljjjjjPfS_
.globl _Z18mirrorImage_kerneljjjjjPfS_
.p2align 8
.type _Z18mirrorImage_kerneljjjjjPfS_,@function
_Z18mirrorImage_kerneljjjjjPfS_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x34
s_load_b64 s[4:5], s[0:1], 0xc
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_lshr_b32 s2, s2, 16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[0:1], null, s14, s3, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s2, v[3:4]
v_cmp_gt_u32_e32 vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_u32_e64 s2, s5, v1
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_18
s_clause 0x1
s_load_b32 s3, s[0:1], 0x8
s_load_b32 s2, s[0:1], 0x0
s_mov_b32 s5, exec_lo
s_waitcnt lgkmcnt(0)
v_cmpx_le_u32_e64 s3, v0
s_xor_b32 s5, exec_lo, s5
s_cbranch_execz .LBB0_7
s_add_i32 s6, s3, s2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_le_u32_e32 vcc_lo, s6, v0
s_and_saveexec_b32 s6, vcc_lo
s_xor_b32 s6, exec_lo, s6
v_not_b32_e32 v2, v0
s_lshl_b32 s7, s2, 1
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_add3_u32 v2, s7, s3, v2
s_and_not1_saveexec_b32 s6, s6
v_subrev_nc_u32_e32 v2, s3, v0
s_or_b32 exec_lo, exec_lo, s6
.LBB0_7:
s_and_not1_saveexec_b32 s5, s5
v_xad_u32 v2, v0, -1, s3
s_or_b32 exec_lo, exec_lo, s5
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 s5, exec_lo
v_cmpx_le_u32_e64 s3, v1
s_xor_b32 s5, exec_lo, s5
s_cbranch_execz .LBB0_15
s_load_b32 s6, s[0:1], 0x4
s_waitcnt lgkmcnt(0)
s_add_i32 s7, s3, s6
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_le_u32_e32 vcc_lo, s7, v1
s_and_saveexec_b32 s7, vcc_lo
s_xor_b32 s7, exec_lo, s7
v_not_b32_e32 v3, v1
s_lshl_b32 s6, s6, 1
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_add3_u32 v3, s6, s3, v3
s_and_not1_saveexec_b32 s6, s7
v_subrev_nc_u32_e32 v3, s3, v1
s_or_b32 exec_lo, exec_lo, s6
.LBB0_15:
s_and_not1_saveexec_b32 s5, s5
v_xad_u32 v3, v1, -1, s3
s_or_b32 exec_lo, exec_lo, s5
s_load_b128 s[8:11], s[0:1], 0x18
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[4:5], null, v3, s2, v[2:3]
v_mov_b32_e32 v5, 0
v_lshlrev_b64 v[2:3], 2, v[4:5]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s8, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s9, v3, vcc_lo
global_load_b32 v4, v[2:3], off
v_mad_u64_u32 v[2:3], null, v1, s4, v[0:1]
v_mov_b32_e32 v3, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[2:3]
v_add_co_u32 v0, vcc_lo, s10, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s11, v1, vcc_lo
s_waitcnt vmcnt(0)
global_store_b32 v[0:1], v4, off
.LBB0_18:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z18mirrorImage_kerneljjjjjPfS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z18mirrorImage_kerneljjjjjPfS_, .Lfunc_end0-_Z18mirrorImage_kerneljjjjjPfS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z18mirrorImage_kerneljjjjjPfS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z18mirrorImage_kerneljjjjjPfS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void mirrorImage_kernel(uint width, uint height, uint border, uint borderWidth, uint borderHeight, float* devInput, float* devOutput) {
int x0 = blockDim.x * blockIdx.x + threadIdx.x;
int y0 = blockDim.y * blockIdx.y + threadIdx.y;
if ((x0 < borderWidth) && (y0 < borderHeight)) {
int x1 = 0;
int y1 = 0;
if (x0 < border) {
x1 = border - x0 - 1;
} else if (x0 < border + width) {
x1 = x0 - border;
} else {
x1 = border + 2 * width - x0 - 1;
}
if (y0 < border) {
y1 = border - y0 - 1;
} else if (y0 < border + height) {
y1 = y0 - border;
} else {
y1 = border + 2 * height - y0 - 1;
}
devOutput[y0 * borderWidth + x0] = devInput[y1 * width + x1];
}
} | .text
.file "mirrorImage_kernel.hip"
.globl _Z33__device_stub__mirrorImage_kerneljjjjjPfS_ # -- Begin function _Z33__device_stub__mirrorImage_kerneljjjjjPfS_
.p2align 4, 0x90
.type _Z33__device_stub__mirrorImage_kerneljjjjjPfS_,@function
_Z33__device_stub__mirrorImage_kerneljjjjjPfS_: # @_Z33__device_stub__mirrorImage_kerneljjjjjPfS_
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movl %edi, 20(%rsp)
movl %esi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movq %r9, 72(%rsp)
leaq 20(%rsp), %rax
movq %rax, 80(%rsp)
leaq 16(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
leaq 72(%rsp), %rax
movq %rax, 120(%rsp)
leaq 144(%rsp), %rax
movq %rax, 128(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z18mirrorImage_kerneljjjjjPfS_, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end0:
.size _Z33__device_stub__mirrorImage_kerneljjjjjPfS_, .Lfunc_end0-_Z33__device_stub__mirrorImage_kerneljjjjjPfS_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z18mirrorImage_kerneljjjjjPfS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z18mirrorImage_kerneljjjjjPfS_,@object # @_Z18mirrorImage_kerneljjjjjPfS_
.section .rodata,"a",@progbits
.globl _Z18mirrorImage_kerneljjjjjPfS_
.p2align 3, 0x0
_Z18mirrorImage_kerneljjjjjPfS_:
.quad _Z33__device_stub__mirrorImage_kerneljjjjjPfS_
.size _Z18mirrorImage_kerneljjjjjPfS_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z18mirrorImage_kerneljjjjjPfS_"
.size .L__unnamed_1, 32
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z33__device_stub__mirrorImage_kerneljjjjjPfS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z18mirrorImage_kerneljjjjjPfS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z18mirrorImage_kerneljjjjjPfS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R5, SR_CTAID.Y ; /* 0x0000000000057919 */
/* 0x000e280000002600 */
/*0020*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e280000002200 */
/*0030*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e680000002500 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e620000002100 */
/*0050*/ IMAD R5, R5, c[0x0][0x4], R2 ; /* 0x0000010005057a24 */
/* 0x001fca00078e0202 */
/*0060*/ ISETP.GE.U32.AND P0, PT, R5, c[0x0][0x170], PT ; /* 0x00005c0005007a0c */
/* 0x000fe20003f06070 */
/*0070*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x002fca00078e0203 */
/*0080*/ ISETP.GE.U32.OR P0, PT, R0, c[0x0][0x16c], P0 ; /* 0x00005b0000007a0c */
/* 0x000fda0000706470 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x168], PT ; /* 0x00005a0000007a0c */
/* 0x000fe20003f06070 */
/*00b0*/ BSSY B0, 0x180 ; /* 0x000000c000007945 */
/* 0x000fd80003800000 */
/*00c0*/ @!P0 BRA 0x150 ; /* 0x0000008000008947 */
/* 0x000fea0003800000 */
/*00d0*/ IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff077624 */
/* 0x000fe200078e00ff */
/*00e0*/ LOP3.LUT R2, RZ, R0, RZ, 0x33, !PT ; /* 0x00000000ff027212 */
/* 0x000fc800078e33ff */
/*00f0*/ IADD3 R3, R7.reuse, c[0x0][0x168], RZ ; /* 0x00005a0007037a10 */
/* 0x040fe20007ffe0ff */
/*0100*/ IMAD R2, R7, 0x2, R2 ; /* 0x0000000207027824 */
/* 0x000fc600078e0202 */
/*0110*/ ISETP.GE.U32.AND P0, PT, R0, R3, PT ; /* 0x000000030000720c */
/* 0x000fe40003f06070 */
/*0120*/ IADD3 R2, R2, c[0x0][0x168], RZ ; /* 0x00005a0002027a10 */
/* 0x000fd60007ffe0ff */
/*0130*/ @!P0 IADD3 R2, R0, -c[0x0][0x168], RZ ; /* 0x80005a0000028a10 */
/* 0x000fe20007ffe0ff */
/*0140*/ BRA 0x170 ; /* 0x0000002000007947 */
/* 0x000fea0003800000 */
/*0150*/ LOP3.LUT R2, RZ, R0, RZ, 0x33, !PT ; /* 0x00000000ff027212 */
/* 0x000fc800078e33ff */
/*0160*/ IADD3 R2, R2, c[0x0][0x168], RZ ; /* 0x00005a0002027a10 */
/* 0x000fe40007ffe0ff */
/*0170*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0180*/ ISETP.GE.U32.AND P0, PT, R5, c[0x0][0x168], PT ; /* 0x00005a0005007a0c */
/* 0x000fe20003f06070 */
/*0190*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*01a0*/ BSSY B0, 0x290 ; /* 0x000000e000007945 */
/* 0x000ff60003800000 */
/*01b0*/ @!P0 BRA 0x260 ; /* 0x000000a000008947 */
/* 0x000fea0003800000 */
/*01c0*/ ULDC UR4, c[0x0][0x168] ; /* 0x00005a0000047ab9 */
/* 0x000fe20000000800 */
/*01d0*/ LOP3.LUT R3, RZ, R5, RZ, 0x33, !PT ; /* 0x00000005ff037212 */
/* 0x000fe200078e33ff */
/*01e0*/ ULDC UR5, c[0x0][0x164] ; /* 0x0000590000057ab9 */
/* 0x000fe20000000800 */
/*01f0*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff047624 */
/* 0x000fe200078e00ff */
/*0200*/ UIADD3 UR4, UR4, UR5, URZ ; /* 0x0000000504047290 */
/* 0x000fe2000fffe03f */
/*0210*/ IADD3 R3, R3, c[0x0][0x168], RZ ; /* 0x00005a0003037a10 */
/* 0x000fca0007ffe0ff */
/*0220*/ ISETP.GE.U32.AND P0, PT, R5, UR4, PT ; /* 0x0000000405007c0c */
/* 0x000fe2000bf06070 */
/*0230*/ IMAD R3, R4, 0x2, R3 ; /* 0x0000000204037824 */
/* 0x000fd800078e0203 */
/*0240*/ @!P0 IADD3 R3, R5, -c[0x0][0x168], RZ ; /* 0x80005a0005038a10 */
/* 0x000fe20007ffe0ff */
/*0250*/ BRA 0x280 ; /* 0x0000002000007947 */
/* 0x000fea0003800000 */
/*0260*/ LOP3.LUT R3, RZ, R5, RZ, 0x33, !PT ; /* 0x00000005ff037212 */
/* 0x000fc800078e33ff */
/*0270*/ IADD3 R3, R3, c[0x0][0x168], RZ ; /* 0x00005a0003037a10 */
/* 0x000fe40007ffe0ff */
/*0280*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0290*/ IMAD.MOV.U32 R4, RZ, RZ, 0x4 ; /* 0x00000004ff047424 */
/* 0x000fe400078e00ff */
/*02a0*/ IMAD R2, R3, c[0x0][0x160], R2 ; /* 0x0000580003027a24 */
/* 0x000fc800078e0202 */
/*02b0*/ IMAD.WIDE.U32 R2, R2, R4, c[0x0][0x178] ; /* 0x00005e0002027625 */
/* 0x000fcc00078e0004 */
/*02c0*/ LDG.E R3, [R2.64] ; /* 0x0000000602037981 */
/* 0x000ea2000c1e1900 */
/*02d0*/ IMAD R5, R5, c[0x0][0x16c], R0 ; /* 0x00005b0005057a24 */
/* 0x000fc800078e0200 */
/*02e0*/ IMAD.WIDE.U32 R4, R5, R4, c[0x0][0x180] ; /* 0x0000600005047625 */
/* 0x000fca00078e0004 */
/*02f0*/ STG.E [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x004fe2000c101906 */
/*0300*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0310*/ BRA 0x310; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0320*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0380*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0390*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z18mirrorImage_kerneljjjjjPfS_
.globl _Z18mirrorImage_kerneljjjjjPfS_
.p2align 8
.type _Z18mirrorImage_kerneljjjjjPfS_,@function
_Z18mirrorImage_kerneljjjjjPfS_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x34
s_load_b64 s[4:5], s[0:1], 0xc
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_lshr_b32 s2, s2, 16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[0:1], null, s14, s3, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s2, v[3:4]
v_cmp_gt_u32_e32 vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_u32_e64 s2, s5, v1
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_18
s_clause 0x1
s_load_b32 s3, s[0:1], 0x8
s_load_b32 s2, s[0:1], 0x0
s_mov_b32 s5, exec_lo
s_waitcnt lgkmcnt(0)
v_cmpx_le_u32_e64 s3, v0
s_xor_b32 s5, exec_lo, s5
s_cbranch_execz .LBB0_7
s_add_i32 s6, s3, s2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_le_u32_e32 vcc_lo, s6, v0
s_and_saveexec_b32 s6, vcc_lo
s_xor_b32 s6, exec_lo, s6
v_not_b32_e32 v2, v0
s_lshl_b32 s7, s2, 1
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_add3_u32 v2, s7, s3, v2
s_and_not1_saveexec_b32 s6, s6
v_subrev_nc_u32_e32 v2, s3, v0
s_or_b32 exec_lo, exec_lo, s6
.LBB0_7:
s_and_not1_saveexec_b32 s5, s5
v_xad_u32 v2, v0, -1, s3
s_or_b32 exec_lo, exec_lo, s5
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 s5, exec_lo
v_cmpx_le_u32_e64 s3, v1
s_xor_b32 s5, exec_lo, s5
s_cbranch_execz .LBB0_15
s_load_b32 s6, s[0:1], 0x4
s_waitcnt lgkmcnt(0)
s_add_i32 s7, s3, s6
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_le_u32_e32 vcc_lo, s7, v1
s_and_saveexec_b32 s7, vcc_lo
s_xor_b32 s7, exec_lo, s7
v_not_b32_e32 v3, v1
s_lshl_b32 s6, s6, 1
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_add3_u32 v3, s6, s3, v3
s_and_not1_saveexec_b32 s6, s7
v_subrev_nc_u32_e32 v3, s3, v1
s_or_b32 exec_lo, exec_lo, s6
.LBB0_15:
s_and_not1_saveexec_b32 s5, s5
v_xad_u32 v3, v1, -1, s3
s_or_b32 exec_lo, exec_lo, s5
s_load_b128 s[8:11], s[0:1], 0x18
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[4:5], null, v3, s2, v[2:3]
v_mov_b32_e32 v5, 0
v_lshlrev_b64 v[2:3], 2, v[4:5]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s8, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s9, v3, vcc_lo
global_load_b32 v4, v[2:3], off
v_mad_u64_u32 v[2:3], null, v1, s4, v[0:1]
v_mov_b32_e32 v3, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[2:3]
v_add_co_u32 v0, vcc_lo, s10, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s11, v1, vcc_lo
s_waitcnt vmcnt(0)
global_store_b32 v[0:1], v4, off
.LBB0_18:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z18mirrorImage_kerneljjjjjPfS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z18mirrorImage_kerneljjjjjPfS_, .Lfunc_end0-_Z18mirrorImage_kerneljjjjjPfS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z18mirrorImage_kerneljjjjjPfS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z18mirrorImage_kerneljjjjjPfS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0004faf2_00000000-6_mirrorImage_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z45__device_stub__Z18mirrorImage_kerneljjjjjPfS_jjjjjPfS_
.type _Z45__device_stub__Z18mirrorImage_kerneljjjjjPfS_jjjjjPfS_, @function
_Z45__device_stub__Z18mirrorImage_kerneljjjjjPfS_jjjjjPfS_:
.LFB2051:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movl %edi, 44(%rsp)
movl %esi, 40(%rsp)
movl %edx, 36(%rsp)
movl %ecx, 32(%rsp)
movl %r8d, 28(%rsp)
movq %r9, 16(%rsp)
movq 192(%rsp), %rax
movq %rax, 8(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 44(%rsp), %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rax
movq %rax, 120(%rsp)
leaq 36(%rsp), %rax
movq %rax, 128(%rsp)
leaq 32(%rsp), %rax
movq %rax, 136(%rsp)
leaq 28(%rsp), %rax
movq %rax, 144(%rsp)
leaq 16(%rsp), %rax
movq %rax, 152(%rsp)
leaq 8(%rsp), %rax
movq %rax, 160(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z18mirrorImage_kerneljjjjjPfS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z45__device_stub__Z18mirrorImage_kerneljjjjjPfS_jjjjjPfS_, .-_Z45__device_stub__Z18mirrorImage_kerneljjjjjPfS_jjjjjPfS_
.globl _Z18mirrorImage_kerneljjjjjPfS_
.type _Z18mirrorImage_kerneljjjjjPfS_, @function
_Z18mirrorImage_kerneljjjjjPfS_:
.LFB2052:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
pushq 24(%rsp)
.cfi_def_cfa_offset 32
call _Z45__device_stub__Z18mirrorImage_kerneljjjjjPfS_jjjjjPfS_
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z18mirrorImage_kerneljjjjjPfS_, .-_Z18mirrorImage_kerneljjjjjPfS_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z18mirrorImage_kerneljjjjjPfS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z18mirrorImage_kerneljjjjjPfS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "mirrorImage_kernel.hip"
.globl _Z33__device_stub__mirrorImage_kerneljjjjjPfS_ # -- Begin function _Z33__device_stub__mirrorImage_kerneljjjjjPfS_
.p2align 4, 0x90
.type _Z33__device_stub__mirrorImage_kerneljjjjjPfS_,@function
_Z33__device_stub__mirrorImage_kerneljjjjjPfS_: # @_Z33__device_stub__mirrorImage_kerneljjjjjPfS_
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movl %edi, 20(%rsp)
movl %esi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movq %r9, 72(%rsp)
leaq 20(%rsp), %rax
movq %rax, 80(%rsp)
leaq 16(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
leaq 72(%rsp), %rax
movq %rax, 120(%rsp)
leaq 144(%rsp), %rax
movq %rax, 128(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z18mirrorImage_kerneljjjjjPfS_, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end0:
.size _Z33__device_stub__mirrorImage_kerneljjjjjPfS_, .Lfunc_end0-_Z33__device_stub__mirrorImage_kerneljjjjjPfS_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z18mirrorImage_kerneljjjjjPfS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z18mirrorImage_kerneljjjjjPfS_,@object # @_Z18mirrorImage_kerneljjjjjPfS_
.section .rodata,"a",@progbits
.globl _Z18mirrorImage_kerneljjjjjPfS_
.p2align 3, 0x0
_Z18mirrorImage_kerneljjjjjPfS_:
.quad _Z33__device_stub__mirrorImage_kerneljjjjjPfS_
.size _Z18mirrorImage_kerneljjjjjPfS_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z18mirrorImage_kerneljjjjjPfS_"
.size .L__unnamed_1, 32
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z33__device_stub__mirrorImage_kerneljjjjjPfS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z18mirrorImage_kerneljjjjjPfS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
__global__ void kernel() {
printf("Hello World!\n");
}
int main () {
kernel<<<1,2>>>();
kernel<<<3,1>>>();
printf("Hello from CPU!\n");
cudaDeviceSynchronize();
return 0;
} | code for sm_80
Function : _Z6kernelv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe20000000f00 */
/*0020*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x8] ; /* 0x01000200ff047624 */
/* 0x000fe200078e00ff */
/*0030*/ CS2R R6, SRZ ; /* 0x0000000000067805 */
/* 0x000fe2000001ff00 */
/*0040*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0xc] ; /* 0x01000300ff057624 */
/* 0x000fe200078e00ff */
/*0050*/ LDC.64 R2, c[0x4][R0] ; /* 0x0100000000027b82 */
/* 0x00006c0000000a00 */
/*0060*/ LEPC R8 ; /* 0x000000000008734e */
/* 0x000fe40000000000 */
/*0070*/ MOV R11, 0xe0 ; /* 0x000000e0000b7802 */
/* 0x000fe40000000f00 */
/*0080*/ MOV R20, 0x60 ; /* 0x0000006000147802 */
/* 0x000fe40000000f00 */
/*0090*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*00a0*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x001fc40000000f00 */
/*00b0*/ IADD3 R20, P0, P1, -R20, R11, R8 ; /* 0x0000000b14147210 */
/* 0x000fc8000791e108 */
/*00c0*/ IADD3.X R21, ~R0, R21, R9, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2509 */
/*00d0*/ CALL.ABS.NOINC R2 ; /* 0x0000000002007343 */
/* 0x002fea0003c00000 */
/*00e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00f0*/ BRA 0xf0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
__global__ void kernel() {
printf("Hello World!\n");
}
int main () {
kernel<<<1,2>>>();
kernel<<<3,1>>>();
printf("Hello from CPU!\n");
cudaDeviceSynchronize();
return 0;
} | .file "tmpxft_0010318c_00000000-6_lab1_1.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z24__device_stub__Z6kernelvv
.type _Z24__device_stub__Z6kernelvv, @function
_Z24__device_stub__Z6kernelvv:
.LFB2082:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z6kernelv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z24__device_stub__Z6kernelvv, .-_Z24__device_stub__Z6kernelvv
.globl _Z6kernelv
.type _Z6kernelv, @function
_Z6kernelv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z24__device_stub__Z6kernelvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z6kernelv, .-_Z6kernelv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Hello from CPU!\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movl $2, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $1, 16(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L15
.L12:
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $3, 8(%rsp)
movl $1, 12(%rsp)
movl $1, 16(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L16
.L13:
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
call cudaDeviceSynchronize@PLT
movl $0, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
call _Z24__device_stub__Z6kernelvv
jmp .L12
.L16:
call _Z24__device_stub__Z6kernelvv
jmp .L13
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z6kernelv"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z6kernelv(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
__global__ void kernel() {
printf("Hello World!\n");
}
int main () {
kernel<<<1,2>>>();
kernel<<<3,1>>>();
printf("Hello from CPU!\n");
cudaDeviceSynchronize();
return 0;
} | #include <hip/hip_runtime.h>
#include <stdio.h>
__global__ void kernel() {
printf("Hello World!\n");
}
int main () {
kernel<<<1,2>>>();
kernel<<<3,1>>>();
printf("Hello from CPU!\n");
hipDeviceSynchronize();
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
__global__ void kernel() {
printf("Hello World!\n");
}
int main () {
kernel<<<1,2>>>();
kernel<<<3,1>>>();
printf("Hello from CPU!\n");
hipDeviceSynchronize();
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6kernelv
.globl _Z6kernelv
.p2align 8
.type _Z6kernelv,@function
_Z6kernelv:
s_load_b64 s[2:3], s[0:1], 0x50
v_mbcnt_lo_u32_b32 v20, -1, 0
v_mov_b32_e32 v6, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_dual_mov_b32 v7, 0 :: v_dual_mov_b32 v4, v20
v_readfirstlane_b32 s0, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_eq_u32_e64 s0, s0, v4
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_6
v_mov_b32_e32 v0, 0
s_mov_b32 s4, exec_lo
s_waitcnt lgkmcnt(0)
global_load_b64 v[8:9], v0, s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
s_clause 0x1
global_load_b64 v[1:2], v0, s[2:3] offset:40
global_load_b64 v[5:6], v0, s[2:3]
s_waitcnt vmcnt(1)
v_and_b32_e32 v1, v1, v8
v_and_b32_e32 v2, v2, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_hi_u32 v3, v1, 24
v_mul_lo_u32 v2, v2, 24
v_mul_lo_u32 v1, v1, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v2, v3, v2
s_waitcnt vmcnt(0)
v_add_co_u32 v1, vcc_lo, v5, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, v6, v2, vcc_lo
global_load_b64 v[6:7], v[1:2], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[6:7], v0, v[6:9], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmpx_ne_u64_e64 v[6:7], v[8:9]
s_cbranch_execz .LBB0_5
s_mov_b32 s5, 0
.p2align 6
.LBB0_3:
s_sleep 1
s_clause 0x1
global_load_b64 v[1:2], v0, s[2:3] offset:40
global_load_b64 v[10:11], v0, s[2:3]
v_dual_mov_b32 v9, v7 :: v_dual_mov_b32 v8, v6
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_and_b32_e32 v1, v1, v8
v_and_b32_e32 v7, v2, v9
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[5:6], null, v1, 24, v[10:11]
v_mov_b32_e32 v1, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, v7, 24, v[1:2]
v_mov_b32_e32 v6, v2
global_load_b64 v[6:7], v[5:6], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[6:7], v0, v[6:9], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmp_eq_u64_e32 vcc_lo, v[6:7], v[8:9]
s_or_b32 s5, vcc_lo, s5
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s5
s_cbranch_execnz .LBB0_3
s_or_b32 exec_lo, exec_lo, s5
.LBB0_5:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s4
.LBB0_6:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s1
v_mov_b32_e32 v5, 0
v_readfirstlane_b32 s4, v6
v_readfirstlane_b32 s5, v7
s_mov_b32 s8, exec_lo
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_load_b64 v[8:9], v5, s[2:3] offset:40
global_load_b128 v[0:3], v5, s[2:3]
s_waitcnt vmcnt(1)
v_readfirstlane_b32 s6, v8
v_readfirstlane_b32 s7, v9
s_delay_alu instid0(VALU_DEP_1)
s_and_b64 s[6:7], s[4:5], s[6:7]
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_8
v_dual_mov_b32 v6, s8 :: v_dual_mov_b32 v7, 0
s_mul_i32 s8, s7, 24
s_mul_hi_u32 s9, s6, 24
v_dual_mov_b32 v8, 2 :: v_dual_mov_b32 v9, 1
s_add_i32 s9, s9, s8
s_mul_i32 s8, s6, 24
s_waitcnt vmcnt(0)
v_add_co_u32 v10, vcc_lo, v0, s8
v_add_co_ci_u32_e32 v11, vcc_lo, s9, v1, vcc_lo
global_store_b128 v[10:11], v[6:9], off offset:8
.LBB0_8:
s_or_b32 exec_lo, exec_lo, s1
s_lshl_b64 s[8:9], s[6:7], 12
v_lshlrev_b64 v[4:5], 6, v[4:5]
s_waitcnt vmcnt(0)
v_add_co_u32 v2, vcc_lo, v2, s8
v_add_co_ci_u32_e32 v7, vcc_lo, s9, v3, vcc_lo
v_mov_b32_e32 v3, 0
s_mov_b32 s8, 0
s_delay_alu instid0(VALU_DEP_3)
v_add_co_u32 v6, vcc_lo, v2, v4
v_mov_b32_e32 v2, 33
s_mov_b32 s9, s8
s_mov_b32 s10, s8
s_mov_b32 s11, s8
v_add_co_ci_u32_e32 v7, vcc_lo, v7, v5, vcc_lo
v_mov_b32_e32 v4, v3
v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v8, s8
v_dual_mov_b32 v9, s9 :: v_dual_mov_b32 v10, s10
v_mov_b32_e32 v11, s11
s_clause 0x3
global_store_b128 v[6:7], v[2:5], off
global_store_b128 v[6:7], v[8:11], off offset:16
global_store_b128 v[6:7], v[8:11], off offset:32
global_store_b128 v[6:7], v[8:11], off offset:48
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_16
v_dual_mov_b32 v10, 0 :: v_dual_mov_b32 v11, s4
v_mov_b32_e32 v12, s5
s_clause 0x1
global_load_b64 v[13:14], v10, s[2:3] offset:32 glc
global_load_b64 v[2:3], v10, s[2:3] offset:40
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s8, v2
v_readfirstlane_b32 s9, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b64 s[8:9], s[8:9], s[4:5]
s_mul_i32 s9, s9, 24
s_mul_hi_u32 s10, s8, 24
s_mul_i32 s8, s8, 24
s_add_i32 s10, s10, s9
v_add_co_u32 v8, vcc_lo, v0, s8
v_add_co_ci_u32_e32 v9, vcc_lo, s10, v1, vcc_lo
s_mov_b32 s8, exec_lo
global_store_b64 v[8:9], v[13:14], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[4:5], v10, v[11:14], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmpx_ne_u64_e64 v[4:5], v[13:14]
s_cbranch_execz .LBB0_12
s_mov_b32 s9, 0
.LBB0_11:
v_dual_mov_b32 v2, s4 :: v_dual_mov_b32 v3, s5
s_sleep 1
global_store_b64 v[8:9], v[4:5], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v10, v[2:5], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5]
v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
s_or_b32 s9, vcc_lo, s9
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s9
s_cbranch_execnz .LBB0_11
.LBB0_12:
s_or_b32 exec_lo, exec_lo, s8
v_mov_b32_e32 v2, 0
s_mov_b32 s9, exec_lo
s_mov_b32 s8, exec_lo
v_mbcnt_lo_u32_b32 v4, s9, 0
global_load_b64 v[2:3], v2, s[2:3] offset:16
v_cmpx_eq_u32_e32 0, v4
s_cbranch_execz .LBB0_14
s_bcnt1_i32_b32 s9, s9
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v5, 0 :: v_dual_mov_b32 v4, s9
s_waitcnt vmcnt(0)
global_atomic_add_u64 v[2:3], v[4:5], off offset:8
.LBB0_14:
s_or_b32 exec_lo, exec_lo, s8
s_waitcnt vmcnt(0)
global_load_b64 v[4:5], v[2:3], off offset:16
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, 0, v[4:5]
s_cbranch_vccnz .LBB0_16
global_load_b32 v2, v[2:3], off offset:24
v_mov_b32_e32 v3, 0
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s8, v2
s_waitcnt_vscnt null, 0x0
global_store_b64 v[4:5], v[2:3], off
s_and_b32 m0, s8, 0xff
s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_16:
s_or_b32 exec_lo, exec_lo, s1
s_mul_i32 s1, s7, 24
s_mul_hi_u32 s7, s6, 24
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_add_i32 s7, s7, s1
s_mul_i32 s1, s6, 24
v_add_co_u32 v0, vcc_lo, v0, s1
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v0, 20
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
s_branch .LBB0_20
.p2align 6
.LBB0_17:
s_or_b32 exec_lo, exec_lo, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s1, v2
s_cmp_eq_u32 s1, 0
s_cbranch_scc1 .LBB0_19
s_sleep 1
s_cbranch_execnz .LBB0_20
s_branch .LBB0_22
.p2align 6
.LBB0_19:
s_branch .LBB0_22
.LBB0_20:
v_mov_b32_e32 v2, 1
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_17
global_load_b32 v2, v[0:1], off glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_and_b32_e32 v2, 1, v2
s_branch .LBB0_17
.LBB0_22:
global_load_b64 v[22:23], v[6:7], off
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_26
v_mov_b32_e32 v6, 0
s_clause 0x2
global_load_b64 v[2:3], v6, s[2:3] offset:40
global_load_b64 v[7:8], v6, s[2:3] offset:24 glc
global_load_b64 v[4:5], v6, s[2:3]
s_waitcnt vmcnt(2)
v_add_co_u32 v9, vcc_lo, v2, 1
v_add_co_ci_u32_e32 v10, vcc_lo, 0, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v9, s4
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v10, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_eq_u64_e32 vcc_lo, 0, v[0:1]
v_dual_cndmask_b32 v1, v1, v10 :: v_dual_cndmask_b32 v0, v0, v9
v_and_b32_e32 v3, v1, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_and_b32_e32 v2, v0, v2
v_mul_lo_u32 v3, v3, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_hi_u32 v9, v2, 24
v_mul_lo_u32 v2, v2, 24
v_add_nc_u32_e32 v3, v9, v3
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_u32 v4, vcc_lo, v4, v2
v_mov_b32_e32 v2, v7
v_add_co_ci_u32_e32 v5, vcc_lo, v5, v3, vcc_lo
v_mov_b32_e32 v3, v8
global_store_b64 v[4:5], v[7:8], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v6, v[0:3], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_ne_u64_e32 vcc_lo, v[2:3], v[7:8]
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_26
s_mov_b32 s0, 0
.LBB0_25:
s_sleep 1
global_store_b64 v[4:5], v[2:3], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[7:8], v6, v[0:3], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[7:8], v[2:3]
v_dual_mov_b32 v2, v7 :: v_dual_mov_b32 v3, v8
s_or_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB0_25
.LBB0_26:
s_or_b32 exec_lo, exec_lo, s1
s_getpc_b64 s[4:5]
s_add_u32 s4, s4, .str@rel32@lo+4
s_addc_u32 s5, s5, .str@rel32@hi+12
s_mov_b32 s0, -1
s_cmp_lg_u64 s[4:5], 0
s_cbranch_scc0 .LBB0_105
s_waitcnt vmcnt(0)
v_dual_mov_b32 v1, v23 :: v_dual_and_b32 v0, -3, v22
v_mov_b32_e32 v25, 0
s_mov_b64 s[6:7], 14
s_branch .LBB0_29
.LBB0_28:
s_or_b32 exec_lo, exec_lo, s1
s_sub_u32 s6, s6, s8
s_subb_u32 s7, s7, s9
s_add_u32 s4, s4, s8
s_addc_u32 s5, s5, s9
s_cmp_lg_u64 s[6:7], 0
s_cbranch_scc0 .LBB0_104
.LBB0_29:
v_cmp_lt_u64_e64 s0, s[6:7], 56
s_delay_alu instid0(VALU_DEP_1)
s_and_b32 s0, s0, exec_lo
s_cselect_b32 s8, s6, 56
s_cselect_b32 s9, s7, 0
s_cmp_gt_u32 s8, 7
s_mov_b32 s0, -1
s_cbranch_scc1 .LBB0_34
v_mov_b32_e32 v2, 0
v_mov_b32_e32 v3, 0
s_cmp_eq_u32 s8, 0
s_cbranch_scc1 .LBB0_33
s_lshl_b64 s[0:1], s[8:9], 3
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], s[4:5]
.LBB0_32:
global_load_u8 v4, v25, s[12:13]
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v4
s_delay_alu instid0(VALU_DEP_1)
v_lshlrev_b64 v[4:5], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_add_u32 s12, s12, 1
s_addc_u32 s13, s13, 0
s_cmp_lg_u32 s0, s10
v_or_b32_e32 v2, v4, v2
v_or_b32_e32 v3, v5, v3
s_cbranch_scc1 .LBB0_32
.LBB0_33:
s_mov_b32 s0, 0
s_mov_b32 s15, 0
.LBB0_34:
s_and_not1_b32 vcc_lo, exec_lo, s0
s_mov_b64 s[0:1], s[4:5]
s_cbranch_vccnz .LBB0_36
global_load_b64 v[2:3], v25, s[4:5]
s_add_i32 s15, s8, -8
s_add_u32 s0, s4, 8
s_addc_u32 s1, s5, 0
.LBB0_36:
s_cmp_gt_u32 s15, 7
s_cbranch_scc1 .LBB0_41
v_mov_b32_e32 v4, 0
v_mov_b32_e32 v5, 0
s_cmp_eq_u32 s15, 0
s_cbranch_scc1 .LBB0_40
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_39:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v6, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[6:7], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s15, s12
v_or_b32_e32 v4, v6, v4
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v5, v7, v5
s_cbranch_scc1 .LBB0_39
.LBB0_40:
s_mov_b32 s14, 0
s_cbranch_execz .LBB0_42
s_branch .LBB0_43
.LBB0_41:
.LBB0_42:
global_load_b64 v[4:5], v25, s[0:1]
s_add_i32 s14, s15, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_43:
s_cmp_gt_u32 s14, 7
s_cbranch_scc1 .LBB0_48
v_mov_b32_e32 v6, 0
v_mov_b32_e32 v7, 0
s_cmp_eq_u32 s14, 0
s_cbranch_scc1 .LBB0_47
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_46:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v8, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[8:9], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s14, s12
v_or_b32_e32 v6, v8, v6
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v7, v9, v7
s_cbranch_scc1 .LBB0_46
.LBB0_47:
s_mov_b32 s15, 0
s_cbranch_execz .LBB0_49
s_branch .LBB0_50
.LBB0_48:
.LBB0_49:
global_load_b64 v[6:7], v25, s[0:1]
s_add_i32 s15, s14, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_50:
s_cmp_gt_u32 s15, 7
s_cbranch_scc1 .LBB0_55
v_mov_b32_e32 v8, 0
v_mov_b32_e32 v9, 0
s_cmp_eq_u32 s15, 0
s_cbranch_scc1 .LBB0_54
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_53:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v10, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[10:11], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s15, s12
v_or_b32_e32 v8, v10, v8
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v9, v11, v9
s_cbranch_scc1 .LBB0_53
.LBB0_54:
s_mov_b32 s14, 0
s_cbranch_execz .LBB0_56
s_branch .LBB0_57
.LBB0_55:
.LBB0_56:
global_load_b64 v[8:9], v25, s[0:1]
s_add_i32 s14, s15, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_57:
s_cmp_gt_u32 s14, 7
s_cbranch_scc1 .LBB0_62
v_mov_b32_e32 v10, 0
v_mov_b32_e32 v11, 0
s_cmp_eq_u32 s14, 0
s_cbranch_scc1 .LBB0_61
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_60:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v12, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[12:13], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s14, s12
v_or_b32_e32 v10, v12, v10
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v11, v13, v11
s_cbranch_scc1 .LBB0_60
.LBB0_61:
s_mov_b32 s15, 0
s_cbranch_execz .LBB0_63
s_branch .LBB0_64
.LBB0_62:
.LBB0_63:
global_load_b64 v[10:11], v25, s[0:1]
s_add_i32 s15, s14, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_64:
s_cmp_gt_u32 s15, 7
s_cbranch_scc1 .LBB0_69
v_mov_b32_e32 v12, 0
v_mov_b32_e32 v13, 0
s_cmp_eq_u32 s15, 0
s_cbranch_scc1 .LBB0_68
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_67:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v14, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v14
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[14:15], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s15, s12
v_or_b32_e32 v12, v14, v12
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v13, v15, v13
s_cbranch_scc1 .LBB0_67
.LBB0_68:
s_mov_b32 s14, 0
s_cbranch_execz .LBB0_70
s_branch .LBB0_71
.LBB0_69:
.LBB0_70:
global_load_b64 v[12:13], v25, s[0:1]
s_add_i32 s14, s15, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_71:
s_cmp_gt_u32 s14, 7
s_cbranch_scc1 .LBB0_76
v_mov_b32_e32 v14, 0
v_mov_b32_e32 v15, 0
s_cmp_eq_u32 s14, 0
s_cbranch_scc1 .LBB0_75
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], s[0:1]
.LBB0_74:
global_load_u8 v16, v25, s[12:13]
s_add_i32 s14, s14, -1
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v16
s_delay_alu instid0(VALU_DEP_1)
v_lshlrev_b64 v[16:17], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_add_u32 s12, s12, 1
s_addc_u32 s13, s13, 0
s_cmp_lg_u32 s14, 0
v_or_b32_e32 v14, v16, v14
v_or_b32_e32 v15, v17, v15
s_cbranch_scc1 .LBB0_74
.LBB0_75:
s_cbranch_execz .LBB0_77
s_branch .LBB0_78
.LBB0_76:
.LBB0_77:
global_load_b64 v[14:15], v25, s[0:1]
.LBB0_78:
v_mov_b32_e32 v24, v20
v_mov_b32_e32 v26, 0
v_mov_b32_e32 v27, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s0, v24
v_cmp_eq_u32_e64 s0, s0, v24
s_delay_alu instid0(VALU_DEP_1)
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_84
global_load_b64 v[18:19], v25, s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
s_clause 0x1
global_load_b64 v[16:17], v25, s[2:3] offset:40
global_load_b64 v[26:27], v25, s[2:3]
s_mov_b32 s10, exec_lo
s_waitcnt vmcnt(1)
v_and_b32_e32 v17, v17, v19
v_and_b32_e32 v16, v16, v18
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_lo_u32 v17, v17, 24
v_mul_hi_u32 v21, v16, 24
v_mul_lo_u32 v16, v16, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v17, v21, v17
s_waitcnt vmcnt(0)
v_add_co_u32 v16, vcc_lo, v26, v16
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v17, vcc_lo, v27, v17, vcc_lo
global_load_b64 v[16:17], v[16:17], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[26:27], v25, v[16:19], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmpx_ne_u64_e64 v[26:27], v[18:19]
s_cbranch_execz .LBB0_83
s_mov_b32 s11, 0
.p2align 6
.LBB0_81:
s_sleep 1
s_clause 0x1
global_load_b64 v[16:17], v25, s[2:3] offset:40
global_load_b64 v[28:29], v25, s[2:3]
v_dual_mov_b32 v18, v26 :: v_dual_mov_b32 v19, v27
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_and_b32_e32 v16, v16, v18
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[26:27], null, v16, 24, v[28:29]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mov_b32 v16, v27 :: v_dual_and_b32 v17, v17, v19
v_mad_u64_u32 v[27:28], null, v17, 24, v[16:17]
global_load_b64 v[16:17], v[26:27], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[26:27], v25, v[16:19], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmp_eq_u64_e32 vcc_lo, v[26:27], v[18:19]
s_or_b32 s11, vcc_lo, s11
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s11
s_cbranch_execnz .LBB0_81
s_or_b32 exec_lo, exec_lo, s11
.LBB0_83:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s10
.LBB0_84:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s1
s_clause 0x1
global_load_b64 v[28:29], v25, s[2:3] offset:40
global_load_b128 v[16:19], v25, s[2:3]
v_readfirstlane_b32 s10, v26
v_readfirstlane_b32 s11, v27
s_mov_b32 s14, exec_lo
s_waitcnt vmcnt(1)
v_readfirstlane_b32 s12, v28
v_readfirstlane_b32 s13, v29
s_delay_alu instid0(VALU_DEP_1)
s_and_b64 s[12:13], s[10:11], s[12:13]
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_86
v_dual_mov_b32 v26, s14 :: v_dual_mov_b32 v27, 0
s_mul_i32 s14, s13, 24
s_mul_hi_u32 s15, s12, 24
v_dual_mov_b32 v28, 2 :: v_dual_mov_b32 v29, 1
s_add_i32 s15, s15, s14
s_mul_i32 s14, s12, 24
s_waitcnt vmcnt(0)
v_add_co_u32 v30, vcc_lo, v16, s14
v_add_co_ci_u32_e32 v31, vcc_lo, s15, v17, vcc_lo
global_store_b128 v[30:31], v[26:29], off offset:8
.LBB0_86:
s_or_b32 exec_lo, exec_lo, s1
v_cmp_gt_u64_e64 vcc_lo, s[6:7], 56
v_or_b32_e32 v21, 2, v0
s_lshl_b64 s[14:15], s[12:13], 12
v_lshlrev_b64 v[26:27], 6, v[24:25]
s_lshl_b32 s1, s8, 2
s_delay_alu instid0(SALU_CYCLE_1)
s_add_i32 s1, s1, 28
v_cndmask_b32_e32 v0, v21, v0, vcc_lo
s_waitcnt vmcnt(0)
v_add_co_u32 v18, vcc_lo, v18, s14
v_add_co_ci_u32_e32 v19, vcc_lo, s15, v19, vcc_lo
s_and_b32 s1, s1, 0x1e0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_u32 v18, vcc_lo, v18, v26
v_and_or_b32 v0, v0, 0xffffff1f, s1
v_add_co_ci_u32_e32 v19, vcc_lo, v19, v27, vcc_lo
s_clause 0x3
global_store_b128 v[18:19], v[0:3], off
global_store_b128 v[18:19], v[4:7], off offset:16
global_store_b128 v[18:19], v[8:11], off offset:32
global_store_b128 v[18:19], v[12:15], off offset:48
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_94
s_clause 0x1
global_load_b64 v[8:9], v25, s[2:3] offset:32 glc
global_load_b64 v[0:1], v25, s[2:3] offset:40
v_dual_mov_b32 v6, s10 :: v_dual_mov_b32 v7, s11
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s14, v0
v_readfirstlane_b32 s15, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b64 s[14:15], s[14:15], s[10:11]
s_mul_i32 s15, s15, 24
s_mul_hi_u32 s16, s14, 24
s_mul_i32 s14, s14, 24
s_add_i32 s16, s16, s15
v_add_co_u32 v4, vcc_lo, v16, s14
v_add_co_ci_u32_e32 v5, vcc_lo, s16, v17, vcc_lo
s_mov_b32 s14, exec_lo
global_store_b64 v[4:5], v[8:9], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v25, v[6:9], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmpx_ne_u64_e64 v[2:3], v[8:9]
s_cbranch_execz .LBB0_90
s_mov_b32 s15, 0
.LBB0_89:
v_dual_mov_b32 v0, s10 :: v_dual_mov_b32 v1, s11
s_sleep 1
global_store_b64 v[4:5], v[2:3], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[0:1], v25, v[0:3], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[2:3]
v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0
s_or_b32 s15, vcc_lo, s15
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s15
s_cbranch_execnz .LBB0_89
.LBB0_90:
s_or_b32 exec_lo, exec_lo, s14
global_load_b64 v[0:1], v25, s[2:3] offset:16
s_mov_b32 s15, exec_lo
s_mov_b32 s14, exec_lo
v_mbcnt_lo_u32_b32 v2, s15, 0
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_eq_u32_e32 0, v2
s_cbranch_execz .LBB0_92
s_bcnt1_i32_b32 s15, s15
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v2, s15
s_waitcnt vmcnt(0)
global_atomic_add_u64 v[0:1], v[2:3], off offset:8
.LBB0_92:
s_or_b32 exec_lo, exec_lo, s14
s_waitcnt vmcnt(0)
global_load_b64 v[2:3], v[0:1], off offset:16
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
s_cbranch_vccnz .LBB0_94
global_load_b32 v24, v[0:1], off offset:24
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s14, v24
s_waitcnt_vscnt null, 0x0
global_store_b64 v[2:3], v[24:25], off
s_and_b32 m0, s14, 0xff
s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_94:
s_or_b32 exec_lo, exec_lo, s1
s_mul_i32 s1, s13, 24
s_mul_hi_u32 s13, s12, 24
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_add_i32 s13, s13, s1
s_mul_i32 s1, s12, 24
v_add_co_u32 v0, vcc_lo, v16, s1
v_add_co_ci_u32_e32 v1, vcc_lo, s13, v17, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v0, 20
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
s_branch .LBB0_98
.p2align 6
.LBB0_95:
s_or_b32 exec_lo, exec_lo, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s1, v2
s_cmp_eq_u32 s1, 0
s_cbranch_scc1 .LBB0_97
s_sleep 1
s_cbranch_execnz .LBB0_98
s_branch .LBB0_100
.p2align 6
.LBB0_97:
s_branch .LBB0_100
.LBB0_98:
v_mov_b32_e32 v2, 1
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_95
global_load_b32 v2, v[0:1], off glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_and_b32_e32 v2, 1, v2
s_branch .LBB0_95
.LBB0_100:
global_load_b64 v[0:1], v[18:19], off
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_28
s_clause 0x2
global_load_b64 v[4:5], v25, s[2:3] offset:40
global_load_b64 v[8:9], v25, s[2:3] offset:24 glc
global_load_b64 v[6:7], v25, s[2:3]
s_waitcnt vmcnt(2)
v_add_co_u32 v10, vcc_lo, v4, 1
v_add_co_ci_u32_e32 v11, vcc_lo, 0, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, v10, s10
v_add_co_ci_u32_e32 v3, vcc_lo, s11, v11, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
v_dual_cndmask_b32 v3, v3, v11 :: v_dual_cndmask_b32 v2, v2, v10
v_and_b32_e32 v5, v3, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_and_b32_e32 v4, v2, v4
v_mul_hi_u32 v10, v4, 24
v_mul_lo_u32 v4, v4, 24
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_add_co_u32 v6, vcc_lo, v6, v4
v_mov_b32_e32 v4, v8
v_mul_lo_u32 v5, v5, 24
v_add_nc_u32_e32 v5, v10, v5
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e32 v7, vcc_lo, v7, v5, vcc_lo
v_mov_b32_e32 v5, v9
global_store_b64 v[6:7], v[8:9], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[4:5], v25, v[2:5], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_ne_u64_e32 vcc_lo, v[4:5], v[8:9]
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_28
s_mov_b32 s0, 0
.LBB0_103:
s_sleep 1
global_store_b64 v[6:7], v[4:5], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[8:9], v25, v[2:5], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[8:9], v[4:5]
v_dual_mov_b32 v4, v8 :: v_dual_mov_b32 v5, v9
s_or_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB0_103
s_branch .LBB0_28
.LBB0_104:
s_mov_b32 s0, 0
.LBB0_105:
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 vcc_lo, exec_lo, s0
s_cbranch_vccz .LBB0_132
v_readfirstlane_b32 s0, v20
v_mov_b32_e32 v4, 0
v_mov_b32_e32 v5, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_eq_u32_e64 s0, s0, v20
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_112
s_waitcnt vmcnt(0)
v_mov_b32_e32 v0, 0
s_mov_b32 s4, exec_lo
global_load_b64 v[6:7], v0, s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
s_clause 0x1
global_load_b64 v[1:2], v0, s[2:3] offset:40
global_load_b64 v[3:4], v0, s[2:3]
s_waitcnt vmcnt(1)
v_and_b32_e32 v1, v1, v6
v_and_b32_e32 v2, v2, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_hi_u32 v5, v1, 24
v_mul_lo_u32 v2, v2, 24
v_mul_lo_u32 v1, v1, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v2, v5, v2
s_waitcnt vmcnt(0)
v_add_co_u32 v1, vcc_lo, v3, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, v4, v2, vcc_lo
global_load_b64 v[4:5], v[1:2], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[4:5], v0, v[4:7], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmpx_ne_u64_e64 v[4:5], v[6:7]
s_cbranch_execz .LBB0_111
s_mov_b32 s5, 0
.p2align 6
.LBB0_109:
s_sleep 1
s_clause 0x1
global_load_b64 v[1:2], v0, s[2:3] offset:40
global_load_b64 v[8:9], v0, s[2:3]
v_dual_mov_b32 v7, v5 :: v_dual_mov_b32 v6, v4
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_and_b32_e32 v1, v1, v6
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[3:4], null, v1, 24, v[8:9]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mov_b32 v1, v4 :: v_dual_and_b32 v2, v2, v7
v_mad_u64_u32 v[4:5], null, v2, 24, v[1:2]
global_load_b64 v[4:5], v[3:4], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[4:5], v0, v[4:7], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmp_eq_u64_e32 vcc_lo, v[4:5], v[6:7]
s_or_b32 s5, vcc_lo, s5
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s5
s_cbranch_execnz .LBB0_109
s_or_b32 exec_lo, exec_lo, s5
.LBB0_111:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s4
.LBB0_112:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s1
v_mov_b32_e32 v21, 0
v_readfirstlane_b32 s4, v4
v_readfirstlane_b32 s5, v5
s_mov_b32 s8, exec_lo
s_clause 0x1
global_load_b64 v[6:7], v21, s[2:3] offset:40
global_load_b128 v[0:3], v21, s[2:3]
s_waitcnt vmcnt(1)
v_readfirstlane_b32 s6, v6
v_readfirstlane_b32 s7, v7
s_delay_alu instid0(VALU_DEP_1)
s_and_b64 s[6:7], s[4:5], s[6:7]
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_114
v_dual_mov_b32 v4, s8 :: v_dual_mov_b32 v5, 0
s_mul_i32 s8, s7, 24
s_mul_hi_u32 s9, s6, 24
v_dual_mov_b32 v6, 2 :: v_dual_mov_b32 v7, 1
s_add_i32 s9, s9, s8
s_mul_i32 s8, s6, 24
s_waitcnt vmcnt(0)
v_add_co_u32 v8, vcc_lo, v0, s8
v_add_co_ci_u32_e32 v9, vcc_lo, s9, v1, vcc_lo
global_store_b128 v[8:9], v[4:7], off offset:8
.LBB0_114:
s_or_b32 exec_lo, exec_lo, s1
s_lshl_b64 s[8:9], s[6:7], 12
v_and_or_b32 v22, v22, 0xffffff1d, 34
s_waitcnt vmcnt(0)
v_add_co_u32 v4, vcc_lo, v2, s8
v_add_co_ci_u32_e32 v5, vcc_lo, s9, v3, vcc_lo
v_lshlrev_b64 v[2:3], 6, v[20:21]
s_mov_b32 s8, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
s_mov_b32 s9, s8
s_mov_b32 s10, s8
s_mov_b32 s11, s8
v_add_co_u32 v8, vcc_lo, v4, v2
v_mov_b32_e32 v6, 0
v_add_co_ci_u32_e32 v9, vcc_lo, v5, v3, vcc_lo
v_dual_mov_b32 v2, s8 :: v_dual_mov_b32 v5, s11
v_dual_mov_b32 v3, s9 :: v_dual_mov_b32 v4, s10
s_delay_alu instid0(VALU_DEP_4)
v_mov_b32_e32 v7, v6
s_clause 0x4
global_store_b64 v[8:9], v[22:23], off
global_store_b128 v[8:9], v[2:5], off offset:8
global_store_b128 v[8:9], v[2:5], off offset:24
global_store_b128 v[8:9], v[2:5], off offset:40
global_store_b64 v[8:9], v[6:7], off offset:56
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_122
v_dual_mov_b32 v8, 0 :: v_dual_mov_b32 v9, s4
v_mov_b32_e32 v10, s5
s_clause 0x1
global_load_b64 v[11:12], v8, s[2:3] offset:32 glc
global_load_b64 v[2:3], v8, s[2:3] offset:40
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s8, v2
v_readfirstlane_b32 s9, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b64 s[8:9], s[8:9], s[4:5]
s_mul_i32 s9, s9, 24
s_mul_hi_u32 s10, s8, 24
s_mul_i32 s8, s8, 24
s_add_i32 s10, s10, s9
v_add_co_u32 v6, vcc_lo, v0, s8
v_add_co_ci_u32_e32 v7, vcc_lo, s10, v1, vcc_lo
s_mov_b32 s8, exec_lo
global_store_b64 v[6:7], v[11:12], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[4:5], v8, v[9:12], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmpx_ne_u64_e64 v[4:5], v[11:12]
s_cbranch_execz .LBB0_118
s_mov_b32 s9, 0
.LBB0_117:
v_dual_mov_b32 v2, s4 :: v_dual_mov_b32 v3, s5
s_sleep 1
global_store_b64 v[6:7], v[4:5], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v8, v[2:5], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5]
v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
s_or_b32 s9, vcc_lo, s9
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s9
s_cbranch_execnz .LBB0_117
.LBB0_118:
s_or_b32 exec_lo, exec_lo, s8
v_mov_b32_e32 v2, 0
s_mov_b32 s9, exec_lo
s_mov_b32 s8, exec_lo
v_mbcnt_lo_u32_b32 v4, s9, 0
global_load_b64 v[2:3], v2, s[2:3] offset:16
v_cmpx_eq_u32_e32 0, v4
s_cbranch_execz .LBB0_120
s_bcnt1_i32_b32 s9, s9
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v5, 0 :: v_dual_mov_b32 v4, s9
s_waitcnt vmcnt(0)
global_atomic_add_u64 v[2:3], v[4:5], off offset:8
.LBB0_120:
s_or_b32 exec_lo, exec_lo, s8
s_waitcnt vmcnt(0)
global_load_b64 v[4:5], v[2:3], off offset:16
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, 0, v[4:5]
s_cbranch_vccnz .LBB0_122
global_load_b32 v2, v[2:3], off offset:24
v_mov_b32_e32 v3, 0
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s8, v2
s_waitcnt_vscnt null, 0x0
global_store_b64 v[4:5], v[2:3], off
s_and_b32 m0, s8, 0xff
s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_122:
s_or_b32 exec_lo, exec_lo, s1
s_mul_i32 s1, s7, 24
s_mul_hi_u32 s7, s6, 24
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_add_i32 s7, s7, s1
s_mul_i32 s1, s6, 24
v_add_co_u32 v0, vcc_lo, v0, s1
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v0, 20
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
s_branch .LBB0_126
.p2align 6
.LBB0_123:
s_or_b32 exec_lo, exec_lo, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s1, v2
s_cmp_eq_u32 s1, 0
s_cbranch_scc1 .LBB0_125
s_sleep 1
s_cbranch_execnz .LBB0_126
s_branch .LBB0_128
.p2align 6
.LBB0_125:
s_branch .LBB0_128
.LBB0_126:
v_mov_b32_e32 v2, 1
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_123
global_load_b32 v2, v[0:1], off glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_and_b32_e32 v2, 1, v2
s_branch .LBB0_123
.LBB0_128:
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_132
v_mov_b32_e32 v6, 0
s_clause 0x2
global_load_b64 v[2:3], v6, s[2:3] offset:40
global_load_b64 v[7:8], v6, s[2:3] offset:24 glc
global_load_b64 v[4:5], v6, s[2:3]
s_waitcnt vmcnt(2)
v_add_co_u32 v9, vcc_lo, v2, 1
v_add_co_ci_u32_e32 v10, vcc_lo, 0, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v9, s4
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v10, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_eq_u64_e32 vcc_lo, 0, v[0:1]
v_dual_cndmask_b32 v1, v1, v10 :: v_dual_cndmask_b32 v0, v0, v9
v_and_b32_e32 v3, v1, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_and_b32_e32 v2, v0, v2
v_mul_lo_u32 v3, v3, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_hi_u32 v9, v2, 24
v_mul_lo_u32 v2, v2, 24
v_add_nc_u32_e32 v3, v9, v3
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_u32 v4, vcc_lo, v4, v2
v_mov_b32_e32 v2, v7
v_add_co_ci_u32_e32 v5, vcc_lo, v5, v3, vcc_lo
v_mov_b32_e32 v3, v8
global_store_b64 v[4:5], v[7:8], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v6, v[0:3], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_ne_u64_e32 vcc_lo, v[2:3], v[7:8]
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_132
s_mov_b32 s0, 0
.LBB0_131:
s_sleep 1
global_store_b64 v[4:5], v[2:3], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[7:8], v6, v[0:3], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[7:8], v[2:3]
v_dual_mov_b32 v2, v7 :: v_dual_mov_b32 v3, v8
s_or_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB0_131
.LBB0_132:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6kernelv
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 256
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 32
.amdhsa_next_free_sgpr 18
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6kernelv, .Lfunc_end0-_Z6kernelv
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type .str,@object
.section .rodata.str1.1,"aMS",@progbits,1
.str:
.asciz "Hello World!\n"
.size .str, 14
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: hidden_block_count_x
- .offset: 4
.size: 4
.value_kind: hidden_block_count_y
- .offset: 8
.size: 4
.value_kind: hidden_block_count_z
- .offset: 12
.size: 2
.value_kind: hidden_group_size_x
- .offset: 14
.size: 2
.value_kind: hidden_group_size_y
- .offset: 16
.size: 2
.value_kind: hidden_group_size_z
- .offset: 18
.size: 2
.value_kind: hidden_remainder_x
- .offset: 20
.size: 2
.value_kind: hidden_remainder_y
- .offset: 22
.size: 2
.value_kind: hidden_remainder_z
- .offset: 40
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 48
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 64
.size: 2
.value_kind: hidden_grid_dims
- .offset: 80
.size: 8
.value_kind: hidden_hostcall_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 256
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6kernelv
.private_segment_fixed_size: 0
.sgpr_count: 20
.sgpr_spill_count: 0
.symbol: _Z6kernelv.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 32
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
__global__ void kernel() {
printf("Hello World!\n");
}
int main () {
kernel<<<1,2>>>();
kernel<<<3,1>>>();
printf("Hello from CPU!\n");
hipDeviceSynchronize();
return 0;
} | .text
.file "lab1_1.hip"
.globl _Z21__device_stub__kernelv # -- Begin function _Z21__device_stub__kernelv
.p2align 4, 0x90
.type _Z21__device_stub__kernelv,@function
_Z21__device_stub__kernelv: # @_Z21__device_stub__kernelv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z6kernelv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z21__device_stub__kernelv, .Lfunc_end0-_Z21__device_stub__kernelv
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $64, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -16
movabsq $4294967297, %rbx # imm = 0x100000001
leaq 1(%rbx), %rdx
movq %rbx, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z6kernelv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
leaq 2(%rbx), %rdi
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z6kernelv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
movl $.Lstr, %edi
callq puts@PLT
callq hipDeviceSynchronize
xorl %eax, %eax
addq $64, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6kernelv, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6kernelv,@object # @_Z6kernelv
.section .rodata,"a",@progbits
.globl _Z6kernelv
.p2align 3, 0x0
_Z6kernelv:
.quad _Z21__device_stub__kernelv
.size _Z6kernelv, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z6kernelv"
.size .L__unnamed_1, 11
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Hello from CPU!"
.size .Lstr, 16
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__kernelv
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6kernelv
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z6kernelv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe20000000f00 */
/*0020*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x8] ; /* 0x01000200ff047624 */
/* 0x000fe200078e00ff */
/*0030*/ CS2R R6, SRZ ; /* 0x0000000000067805 */
/* 0x000fe2000001ff00 */
/*0040*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0xc] ; /* 0x01000300ff057624 */
/* 0x000fe200078e00ff */
/*0050*/ LDC.64 R2, c[0x4][R0] ; /* 0x0100000000027b82 */
/* 0x00006c0000000a00 */
/*0060*/ LEPC R8 ; /* 0x000000000008734e */
/* 0x000fe40000000000 */
/*0070*/ MOV R11, 0xe0 ; /* 0x000000e0000b7802 */
/* 0x000fe40000000f00 */
/*0080*/ MOV R20, 0x60 ; /* 0x0000006000147802 */
/* 0x000fe40000000f00 */
/*0090*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*00a0*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x001fc40000000f00 */
/*00b0*/ IADD3 R20, P0, P1, -R20, R11, R8 ; /* 0x0000000b14147210 */
/* 0x000fc8000791e108 */
/*00c0*/ IADD3.X R21, ~R0, R21, R9, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2509 */
/*00d0*/ CALL.ABS.NOINC R2 ; /* 0x0000000002007343 */
/* 0x002fea0003c00000 */
/*00e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00f0*/ BRA 0xf0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6kernelv
.globl _Z6kernelv
.p2align 8
.type _Z6kernelv,@function
_Z6kernelv:
s_load_b64 s[2:3], s[0:1], 0x50
v_mbcnt_lo_u32_b32 v20, -1, 0
v_mov_b32_e32 v6, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_dual_mov_b32 v7, 0 :: v_dual_mov_b32 v4, v20
v_readfirstlane_b32 s0, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_eq_u32_e64 s0, s0, v4
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_6
v_mov_b32_e32 v0, 0
s_mov_b32 s4, exec_lo
s_waitcnt lgkmcnt(0)
global_load_b64 v[8:9], v0, s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
s_clause 0x1
global_load_b64 v[1:2], v0, s[2:3] offset:40
global_load_b64 v[5:6], v0, s[2:3]
s_waitcnt vmcnt(1)
v_and_b32_e32 v1, v1, v8
v_and_b32_e32 v2, v2, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_hi_u32 v3, v1, 24
v_mul_lo_u32 v2, v2, 24
v_mul_lo_u32 v1, v1, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v2, v3, v2
s_waitcnt vmcnt(0)
v_add_co_u32 v1, vcc_lo, v5, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, v6, v2, vcc_lo
global_load_b64 v[6:7], v[1:2], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[6:7], v0, v[6:9], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmpx_ne_u64_e64 v[6:7], v[8:9]
s_cbranch_execz .LBB0_5
s_mov_b32 s5, 0
.p2align 6
.LBB0_3:
s_sleep 1
s_clause 0x1
global_load_b64 v[1:2], v0, s[2:3] offset:40
global_load_b64 v[10:11], v0, s[2:3]
v_dual_mov_b32 v9, v7 :: v_dual_mov_b32 v8, v6
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_and_b32_e32 v1, v1, v8
v_and_b32_e32 v7, v2, v9
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[5:6], null, v1, 24, v[10:11]
v_mov_b32_e32 v1, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, v7, 24, v[1:2]
v_mov_b32_e32 v6, v2
global_load_b64 v[6:7], v[5:6], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[6:7], v0, v[6:9], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmp_eq_u64_e32 vcc_lo, v[6:7], v[8:9]
s_or_b32 s5, vcc_lo, s5
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s5
s_cbranch_execnz .LBB0_3
s_or_b32 exec_lo, exec_lo, s5
.LBB0_5:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s4
.LBB0_6:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s1
v_mov_b32_e32 v5, 0
v_readfirstlane_b32 s4, v6
v_readfirstlane_b32 s5, v7
s_mov_b32 s8, exec_lo
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_load_b64 v[8:9], v5, s[2:3] offset:40
global_load_b128 v[0:3], v5, s[2:3]
s_waitcnt vmcnt(1)
v_readfirstlane_b32 s6, v8
v_readfirstlane_b32 s7, v9
s_delay_alu instid0(VALU_DEP_1)
s_and_b64 s[6:7], s[4:5], s[6:7]
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_8
v_dual_mov_b32 v6, s8 :: v_dual_mov_b32 v7, 0
s_mul_i32 s8, s7, 24
s_mul_hi_u32 s9, s6, 24
v_dual_mov_b32 v8, 2 :: v_dual_mov_b32 v9, 1
s_add_i32 s9, s9, s8
s_mul_i32 s8, s6, 24
s_waitcnt vmcnt(0)
v_add_co_u32 v10, vcc_lo, v0, s8
v_add_co_ci_u32_e32 v11, vcc_lo, s9, v1, vcc_lo
global_store_b128 v[10:11], v[6:9], off offset:8
.LBB0_8:
s_or_b32 exec_lo, exec_lo, s1
s_lshl_b64 s[8:9], s[6:7], 12
v_lshlrev_b64 v[4:5], 6, v[4:5]
s_waitcnt vmcnt(0)
v_add_co_u32 v2, vcc_lo, v2, s8
v_add_co_ci_u32_e32 v7, vcc_lo, s9, v3, vcc_lo
v_mov_b32_e32 v3, 0
s_mov_b32 s8, 0
s_delay_alu instid0(VALU_DEP_3)
v_add_co_u32 v6, vcc_lo, v2, v4
v_mov_b32_e32 v2, 33
s_mov_b32 s9, s8
s_mov_b32 s10, s8
s_mov_b32 s11, s8
v_add_co_ci_u32_e32 v7, vcc_lo, v7, v5, vcc_lo
v_mov_b32_e32 v4, v3
v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v8, s8
v_dual_mov_b32 v9, s9 :: v_dual_mov_b32 v10, s10
v_mov_b32_e32 v11, s11
s_clause 0x3
global_store_b128 v[6:7], v[2:5], off
global_store_b128 v[6:7], v[8:11], off offset:16
global_store_b128 v[6:7], v[8:11], off offset:32
global_store_b128 v[6:7], v[8:11], off offset:48
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_16
v_dual_mov_b32 v10, 0 :: v_dual_mov_b32 v11, s4
v_mov_b32_e32 v12, s5
s_clause 0x1
global_load_b64 v[13:14], v10, s[2:3] offset:32 glc
global_load_b64 v[2:3], v10, s[2:3] offset:40
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s8, v2
v_readfirstlane_b32 s9, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b64 s[8:9], s[8:9], s[4:5]
s_mul_i32 s9, s9, 24
s_mul_hi_u32 s10, s8, 24
s_mul_i32 s8, s8, 24
s_add_i32 s10, s10, s9
v_add_co_u32 v8, vcc_lo, v0, s8
v_add_co_ci_u32_e32 v9, vcc_lo, s10, v1, vcc_lo
s_mov_b32 s8, exec_lo
global_store_b64 v[8:9], v[13:14], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[4:5], v10, v[11:14], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmpx_ne_u64_e64 v[4:5], v[13:14]
s_cbranch_execz .LBB0_12
s_mov_b32 s9, 0
.LBB0_11:
v_dual_mov_b32 v2, s4 :: v_dual_mov_b32 v3, s5
s_sleep 1
global_store_b64 v[8:9], v[4:5], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v10, v[2:5], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5]
v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
s_or_b32 s9, vcc_lo, s9
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s9
s_cbranch_execnz .LBB0_11
.LBB0_12:
s_or_b32 exec_lo, exec_lo, s8
v_mov_b32_e32 v2, 0
s_mov_b32 s9, exec_lo
s_mov_b32 s8, exec_lo
v_mbcnt_lo_u32_b32 v4, s9, 0
global_load_b64 v[2:3], v2, s[2:3] offset:16
v_cmpx_eq_u32_e32 0, v4
s_cbranch_execz .LBB0_14
s_bcnt1_i32_b32 s9, s9
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v5, 0 :: v_dual_mov_b32 v4, s9
s_waitcnt vmcnt(0)
global_atomic_add_u64 v[2:3], v[4:5], off offset:8
.LBB0_14:
s_or_b32 exec_lo, exec_lo, s8
s_waitcnt vmcnt(0)
global_load_b64 v[4:5], v[2:3], off offset:16
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, 0, v[4:5]
s_cbranch_vccnz .LBB0_16
global_load_b32 v2, v[2:3], off offset:24
v_mov_b32_e32 v3, 0
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s8, v2
s_waitcnt_vscnt null, 0x0
global_store_b64 v[4:5], v[2:3], off
s_and_b32 m0, s8, 0xff
s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_16:
s_or_b32 exec_lo, exec_lo, s1
s_mul_i32 s1, s7, 24
s_mul_hi_u32 s7, s6, 24
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_add_i32 s7, s7, s1
s_mul_i32 s1, s6, 24
v_add_co_u32 v0, vcc_lo, v0, s1
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v0, 20
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
s_branch .LBB0_20
.p2align 6
.LBB0_17:
s_or_b32 exec_lo, exec_lo, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s1, v2
s_cmp_eq_u32 s1, 0
s_cbranch_scc1 .LBB0_19
s_sleep 1
s_cbranch_execnz .LBB0_20
s_branch .LBB0_22
.p2align 6
.LBB0_19:
s_branch .LBB0_22
.LBB0_20:
v_mov_b32_e32 v2, 1
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_17
global_load_b32 v2, v[0:1], off glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_and_b32_e32 v2, 1, v2
s_branch .LBB0_17
.LBB0_22:
global_load_b64 v[22:23], v[6:7], off
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_26
v_mov_b32_e32 v6, 0
s_clause 0x2
global_load_b64 v[2:3], v6, s[2:3] offset:40
global_load_b64 v[7:8], v6, s[2:3] offset:24 glc
global_load_b64 v[4:5], v6, s[2:3]
s_waitcnt vmcnt(2)
v_add_co_u32 v9, vcc_lo, v2, 1
v_add_co_ci_u32_e32 v10, vcc_lo, 0, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v9, s4
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v10, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_eq_u64_e32 vcc_lo, 0, v[0:1]
v_dual_cndmask_b32 v1, v1, v10 :: v_dual_cndmask_b32 v0, v0, v9
v_and_b32_e32 v3, v1, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_and_b32_e32 v2, v0, v2
v_mul_lo_u32 v3, v3, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_hi_u32 v9, v2, 24
v_mul_lo_u32 v2, v2, 24
v_add_nc_u32_e32 v3, v9, v3
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_u32 v4, vcc_lo, v4, v2
v_mov_b32_e32 v2, v7
v_add_co_ci_u32_e32 v5, vcc_lo, v5, v3, vcc_lo
v_mov_b32_e32 v3, v8
global_store_b64 v[4:5], v[7:8], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v6, v[0:3], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_ne_u64_e32 vcc_lo, v[2:3], v[7:8]
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_26
s_mov_b32 s0, 0
.LBB0_25:
s_sleep 1
global_store_b64 v[4:5], v[2:3], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[7:8], v6, v[0:3], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[7:8], v[2:3]
v_dual_mov_b32 v2, v7 :: v_dual_mov_b32 v3, v8
s_or_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB0_25
.LBB0_26:
s_or_b32 exec_lo, exec_lo, s1
s_getpc_b64 s[4:5]
s_add_u32 s4, s4, .str@rel32@lo+4
s_addc_u32 s5, s5, .str@rel32@hi+12
s_mov_b32 s0, -1
s_cmp_lg_u64 s[4:5], 0
s_cbranch_scc0 .LBB0_105
s_waitcnt vmcnt(0)
v_dual_mov_b32 v1, v23 :: v_dual_and_b32 v0, -3, v22
v_mov_b32_e32 v25, 0
s_mov_b64 s[6:7], 14
s_branch .LBB0_29
.LBB0_28:
s_or_b32 exec_lo, exec_lo, s1
s_sub_u32 s6, s6, s8
s_subb_u32 s7, s7, s9
s_add_u32 s4, s4, s8
s_addc_u32 s5, s5, s9
s_cmp_lg_u64 s[6:7], 0
s_cbranch_scc0 .LBB0_104
.LBB0_29:
v_cmp_lt_u64_e64 s0, s[6:7], 56
s_delay_alu instid0(VALU_DEP_1)
s_and_b32 s0, s0, exec_lo
s_cselect_b32 s8, s6, 56
s_cselect_b32 s9, s7, 0
s_cmp_gt_u32 s8, 7
s_mov_b32 s0, -1
s_cbranch_scc1 .LBB0_34
v_mov_b32_e32 v2, 0
v_mov_b32_e32 v3, 0
s_cmp_eq_u32 s8, 0
s_cbranch_scc1 .LBB0_33
s_lshl_b64 s[0:1], s[8:9], 3
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], s[4:5]
.LBB0_32:
global_load_u8 v4, v25, s[12:13]
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v4
s_delay_alu instid0(VALU_DEP_1)
v_lshlrev_b64 v[4:5], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_add_u32 s12, s12, 1
s_addc_u32 s13, s13, 0
s_cmp_lg_u32 s0, s10
v_or_b32_e32 v2, v4, v2
v_or_b32_e32 v3, v5, v3
s_cbranch_scc1 .LBB0_32
.LBB0_33:
s_mov_b32 s0, 0
s_mov_b32 s15, 0
.LBB0_34:
s_and_not1_b32 vcc_lo, exec_lo, s0
s_mov_b64 s[0:1], s[4:5]
s_cbranch_vccnz .LBB0_36
global_load_b64 v[2:3], v25, s[4:5]
s_add_i32 s15, s8, -8
s_add_u32 s0, s4, 8
s_addc_u32 s1, s5, 0
.LBB0_36:
s_cmp_gt_u32 s15, 7
s_cbranch_scc1 .LBB0_41
v_mov_b32_e32 v4, 0
v_mov_b32_e32 v5, 0
s_cmp_eq_u32 s15, 0
s_cbranch_scc1 .LBB0_40
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_39:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v6, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[6:7], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s15, s12
v_or_b32_e32 v4, v6, v4
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v5, v7, v5
s_cbranch_scc1 .LBB0_39
.LBB0_40:
s_mov_b32 s14, 0
s_cbranch_execz .LBB0_42
s_branch .LBB0_43
.LBB0_41:
.LBB0_42:
global_load_b64 v[4:5], v25, s[0:1]
s_add_i32 s14, s15, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_43:
s_cmp_gt_u32 s14, 7
s_cbranch_scc1 .LBB0_48
v_mov_b32_e32 v6, 0
v_mov_b32_e32 v7, 0
s_cmp_eq_u32 s14, 0
s_cbranch_scc1 .LBB0_47
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_46:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v8, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[8:9], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s14, s12
v_or_b32_e32 v6, v8, v6
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v7, v9, v7
s_cbranch_scc1 .LBB0_46
.LBB0_47:
s_mov_b32 s15, 0
s_cbranch_execz .LBB0_49
s_branch .LBB0_50
.LBB0_48:
.LBB0_49:
global_load_b64 v[6:7], v25, s[0:1]
s_add_i32 s15, s14, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_50:
s_cmp_gt_u32 s15, 7
s_cbranch_scc1 .LBB0_55
v_mov_b32_e32 v8, 0
v_mov_b32_e32 v9, 0
s_cmp_eq_u32 s15, 0
s_cbranch_scc1 .LBB0_54
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_53:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v10, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[10:11], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s15, s12
v_or_b32_e32 v8, v10, v8
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v9, v11, v9
s_cbranch_scc1 .LBB0_53
.LBB0_54:
s_mov_b32 s14, 0
s_cbranch_execz .LBB0_56
s_branch .LBB0_57
.LBB0_55:
.LBB0_56:
global_load_b64 v[8:9], v25, s[0:1]
s_add_i32 s14, s15, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_57:
s_cmp_gt_u32 s14, 7
s_cbranch_scc1 .LBB0_62
v_mov_b32_e32 v10, 0
v_mov_b32_e32 v11, 0
s_cmp_eq_u32 s14, 0
s_cbranch_scc1 .LBB0_61
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_60:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v12, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[12:13], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s14, s12
v_or_b32_e32 v10, v12, v10
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v11, v13, v11
s_cbranch_scc1 .LBB0_60
.LBB0_61:
s_mov_b32 s15, 0
s_cbranch_execz .LBB0_63
s_branch .LBB0_64
.LBB0_62:
.LBB0_63:
global_load_b64 v[10:11], v25, s[0:1]
s_add_i32 s15, s14, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_64:
s_cmp_gt_u32 s15, 7
s_cbranch_scc1 .LBB0_69
v_mov_b32_e32 v12, 0
v_mov_b32_e32 v13, 0
s_cmp_eq_u32 s15, 0
s_cbranch_scc1 .LBB0_68
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_67:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v14, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v14
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[14:15], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s15, s12
v_or_b32_e32 v12, v14, v12
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v13, v15, v13
s_cbranch_scc1 .LBB0_67
.LBB0_68:
s_mov_b32 s14, 0
s_cbranch_execz .LBB0_70
s_branch .LBB0_71
.LBB0_69:
.LBB0_70:
global_load_b64 v[12:13], v25, s[0:1]
s_add_i32 s14, s15, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_71:
s_cmp_gt_u32 s14, 7
s_cbranch_scc1 .LBB0_76
v_mov_b32_e32 v14, 0
v_mov_b32_e32 v15, 0
s_cmp_eq_u32 s14, 0
s_cbranch_scc1 .LBB0_75
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], s[0:1]
.LBB0_74:
global_load_u8 v16, v25, s[12:13]
s_add_i32 s14, s14, -1
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v16
s_delay_alu instid0(VALU_DEP_1)
v_lshlrev_b64 v[16:17], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_add_u32 s12, s12, 1
s_addc_u32 s13, s13, 0
s_cmp_lg_u32 s14, 0
v_or_b32_e32 v14, v16, v14
v_or_b32_e32 v15, v17, v15
s_cbranch_scc1 .LBB0_74
.LBB0_75:
s_cbranch_execz .LBB0_77
s_branch .LBB0_78
.LBB0_76:
.LBB0_77:
global_load_b64 v[14:15], v25, s[0:1]
.LBB0_78:
v_mov_b32_e32 v24, v20
v_mov_b32_e32 v26, 0
v_mov_b32_e32 v27, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s0, v24
v_cmp_eq_u32_e64 s0, s0, v24
s_delay_alu instid0(VALU_DEP_1)
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_84
global_load_b64 v[18:19], v25, s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
s_clause 0x1
global_load_b64 v[16:17], v25, s[2:3] offset:40
global_load_b64 v[26:27], v25, s[2:3]
s_mov_b32 s10, exec_lo
s_waitcnt vmcnt(1)
v_and_b32_e32 v17, v17, v19
v_and_b32_e32 v16, v16, v18
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_lo_u32 v17, v17, 24
v_mul_hi_u32 v21, v16, 24
v_mul_lo_u32 v16, v16, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v17, v21, v17
s_waitcnt vmcnt(0)
v_add_co_u32 v16, vcc_lo, v26, v16
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v17, vcc_lo, v27, v17, vcc_lo
global_load_b64 v[16:17], v[16:17], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[26:27], v25, v[16:19], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmpx_ne_u64_e64 v[26:27], v[18:19]
s_cbranch_execz .LBB0_83
s_mov_b32 s11, 0
.p2align 6
.LBB0_81:
s_sleep 1
s_clause 0x1
global_load_b64 v[16:17], v25, s[2:3] offset:40
global_load_b64 v[28:29], v25, s[2:3]
v_dual_mov_b32 v18, v26 :: v_dual_mov_b32 v19, v27
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_and_b32_e32 v16, v16, v18
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[26:27], null, v16, 24, v[28:29]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mov_b32 v16, v27 :: v_dual_and_b32 v17, v17, v19
v_mad_u64_u32 v[27:28], null, v17, 24, v[16:17]
global_load_b64 v[16:17], v[26:27], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[26:27], v25, v[16:19], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmp_eq_u64_e32 vcc_lo, v[26:27], v[18:19]
s_or_b32 s11, vcc_lo, s11
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s11
s_cbranch_execnz .LBB0_81
s_or_b32 exec_lo, exec_lo, s11
.LBB0_83:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s10
.LBB0_84:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s1
s_clause 0x1
global_load_b64 v[28:29], v25, s[2:3] offset:40
global_load_b128 v[16:19], v25, s[2:3]
v_readfirstlane_b32 s10, v26
v_readfirstlane_b32 s11, v27
s_mov_b32 s14, exec_lo
s_waitcnt vmcnt(1)
v_readfirstlane_b32 s12, v28
v_readfirstlane_b32 s13, v29
s_delay_alu instid0(VALU_DEP_1)
s_and_b64 s[12:13], s[10:11], s[12:13]
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_86
v_dual_mov_b32 v26, s14 :: v_dual_mov_b32 v27, 0
s_mul_i32 s14, s13, 24
s_mul_hi_u32 s15, s12, 24
v_dual_mov_b32 v28, 2 :: v_dual_mov_b32 v29, 1
s_add_i32 s15, s15, s14
s_mul_i32 s14, s12, 24
s_waitcnt vmcnt(0)
v_add_co_u32 v30, vcc_lo, v16, s14
v_add_co_ci_u32_e32 v31, vcc_lo, s15, v17, vcc_lo
global_store_b128 v[30:31], v[26:29], off offset:8
.LBB0_86:
s_or_b32 exec_lo, exec_lo, s1
v_cmp_gt_u64_e64 vcc_lo, s[6:7], 56
v_or_b32_e32 v21, 2, v0
s_lshl_b64 s[14:15], s[12:13], 12
v_lshlrev_b64 v[26:27], 6, v[24:25]
s_lshl_b32 s1, s8, 2
s_delay_alu instid0(SALU_CYCLE_1)
s_add_i32 s1, s1, 28
v_cndmask_b32_e32 v0, v21, v0, vcc_lo
s_waitcnt vmcnt(0)
v_add_co_u32 v18, vcc_lo, v18, s14
v_add_co_ci_u32_e32 v19, vcc_lo, s15, v19, vcc_lo
s_and_b32 s1, s1, 0x1e0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_u32 v18, vcc_lo, v18, v26
v_and_or_b32 v0, v0, 0xffffff1f, s1
v_add_co_ci_u32_e32 v19, vcc_lo, v19, v27, vcc_lo
s_clause 0x3
global_store_b128 v[18:19], v[0:3], off
global_store_b128 v[18:19], v[4:7], off offset:16
global_store_b128 v[18:19], v[8:11], off offset:32
global_store_b128 v[18:19], v[12:15], off offset:48
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_94
s_clause 0x1
global_load_b64 v[8:9], v25, s[2:3] offset:32 glc
global_load_b64 v[0:1], v25, s[2:3] offset:40
v_dual_mov_b32 v6, s10 :: v_dual_mov_b32 v7, s11
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s14, v0
v_readfirstlane_b32 s15, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b64 s[14:15], s[14:15], s[10:11]
s_mul_i32 s15, s15, 24
s_mul_hi_u32 s16, s14, 24
s_mul_i32 s14, s14, 24
s_add_i32 s16, s16, s15
v_add_co_u32 v4, vcc_lo, v16, s14
v_add_co_ci_u32_e32 v5, vcc_lo, s16, v17, vcc_lo
s_mov_b32 s14, exec_lo
global_store_b64 v[4:5], v[8:9], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v25, v[6:9], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmpx_ne_u64_e64 v[2:3], v[8:9]
s_cbranch_execz .LBB0_90
s_mov_b32 s15, 0
.LBB0_89:
v_dual_mov_b32 v0, s10 :: v_dual_mov_b32 v1, s11
s_sleep 1
global_store_b64 v[4:5], v[2:3], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[0:1], v25, v[0:3], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[2:3]
v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0
s_or_b32 s15, vcc_lo, s15
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s15
s_cbranch_execnz .LBB0_89
.LBB0_90:
s_or_b32 exec_lo, exec_lo, s14
global_load_b64 v[0:1], v25, s[2:3] offset:16
s_mov_b32 s15, exec_lo
s_mov_b32 s14, exec_lo
v_mbcnt_lo_u32_b32 v2, s15, 0
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_eq_u32_e32 0, v2
s_cbranch_execz .LBB0_92
s_bcnt1_i32_b32 s15, s15
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v2, s15
s_waitcnt vmcnt(0)
global_atomic_add_u64 v[0:1], v[2:3], off offset:8
.LBB0_92:
s_or_b32 exec_lo, exec_lo, s14
s_waitcnt vmcnt(0)
global_load_b64 v[2:3], v[0:1], off offset:16
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
s_cbranch_vccnz .LBB0_94
global_load_b32 v24, v[0:1], off offset:24
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s14, v24
s_waitcnt_vscnt null, 0x0
global_store_b64 v[2:3], v[24:25], off
s_and_b32 m0, s14, 0xff
s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_94:
s_or_b32 exec_lo, exec_lo, s1
s_mul_i32 s1, s13, 24
s_mul_hi_u32 s13, s12, 24
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_add_i32 s13, s13, s1
s_mul_i32 s1, s12, 24
v_add_co_u32 v0, vcc_lo, v16, s1
v_add_co_ci_u32_e32 v1, vcc_lo, s13, v17, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v0, 20
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
s_branch .LBB0_98
.p2align 6
.LBB0_95:
s_or_b32 exec_lo, exec_lo, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s1, v2
s_cmp_eq_u32 s1, 0
s_cbranch_scc1 .LBB0_97
s_sleep 1
s_cbranch_execnz .LBB0_98
s_branch .LBB0_100
.p2align 6
.LBB0_97:
s_branch .LBB0_100
.LBB0_98:
v_mov_b32_e32 v2, 1
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_95
global_load_b32 v2, v[0:1], off glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_and_b32_e32 v2, 1, v2
s_branch .LBB0_95
.LBB0_100:
global_load_b64 v[0:1], v[18:19], off
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_28
s_clause 0x2
global_load_b64 v[4:5], v25, s[2:3] offset:40
global_load_b64 v[8:9], v25, s[2:3] offset:24 glc
global_load_b64 v[6:7], v25, s[2:3]
s_waitcnt vmcnt(2)
v_add_co_u32 v10, vcc_lo, v4, 1
v_add_co_ci_u32_e32 v11, vcc_lo, 0, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, v10, s10
v_add_co_ci_u32_e32 v3, vcc_lo, s11, v11, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
v_dual_cndmask_b32 v3, v3, v11 :: v_dual_cndmask_b32 v2, v2, v10
v_and_b32_e32 v5, v3, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_and_b32_e32 v4, v2, v4
v_mul_hi_u32 v10, v4, 24
v_mul_lo_u32 v4, v4, 24
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_add_co_u32 v6, vcc_lo, v6, v4
v_mov_b32_e32 v4, v8
v_mul_lo_u32 v5, v5, 24
v_add_nc_u32_e32 v5, v10, v5
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e32 v7, vcc_lo, v7, v5, vcc_lo
v_mov_b32_e32 v5, v9
global_store_b64 v[6:7], v[8:9], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[4:5], v25, v[2:5], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_ne_u64_e32 vcc_lo, v[4:5], v[8:9]
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_28
s_mov_b32 s0, 0
.LBB0_103:
s_sleep 1
global_store_b64 v[6:7], v[4:5], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[8:9], v25, v[2:5], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[8:9], v[4:5]
v_dual_mov_b32 v4, v8 :: v_dual_mov_b32 v5, v9
s_or_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB0_103
s_branch .LBB0_28
.LBB0_104:
s_mov_b32 s0, 0
.LBB0_105:
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 vcc_lo, exec_lo, s0
s_cbranch_vccz .LBB0_132
v_readfirstlane_b32 s0, v20
v_mov_b32_e32 v4, 0
v_mov_b32_e32 v5, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_eq_u32_e64 s0, s0, v20
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_112
s_waitcnt vmcnt(0)
v_mov_b32_e32 v0, 0
s_mov_b32 s4, exec_lo
global_load_b64 v[6:7], v0, s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
s_clause 0x1
global_load_b64 v[1:2], v0, s[2:3] offset:40
global_load_b64 v[3:4], v0, s[2:3]
s_waitcnt vmcnt(1)
v_and_b32_e32 v1, v1, v6
v_and_b32_e32 v2, v2, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_hi_u32 v5, v1, 24
v_mul_lo_u32 v2, v2, 24
v_mul_lo_u32 v1, v1, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v2, v5, v2
s_waitcnt vmcnt(0)
v_add_co_u32 v1, vcc_lo, v3, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, v4, v2, vcc_lo
global_load_b64 v[4:5], v[1:2], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[4:5], v0, v[4:7], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmpx_ne_u64_e64 v[4:5], v[6:7]
s_cbranch_execz .LBB0_111
s_mov_b32 s5, 0
.p2align 6
.LBB0_109:
s_sleep 1
s_clause 0x1
global_load_b64 v[1:2], v0, s[2:3] offset:40
global_load_b64 v[8:9], v0, s[2:3]
v_dual_mov_b32 v7, v5 :: v_dual_mov_b32 v6, v4
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_and_b32_e32 v1, v1, v6
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[3:4], null, v1, 24, v[8:9]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mov_b32 v1, v4 :: v_dual_and_b32 v2, v2, v7
v_mad_u64_u32 v[4:5], null, v2, 24, v[1:2]
global_load_b64 v[4:5], v[3:4], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[4:5], v0, v[4:7], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmp_eq_u64_e32 vcc_lo, v[4:5], v[6:7]
s_or_b32 s5, vcc_lo, s5
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s5
s_cbranch_execnz .LBB0_109
s_or_b32 exec_lo, exec_lo, s5
.LBB0_111:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s4
.LBB0_112:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s1
v_mov_b32_e32 v21, 0
v_readfirstlane_b32 s4, v4
v_readfirstlane_b32 s5, v5
s_mov_b32 s8, exec_lo
s_clause 0x1
global_load_b64 v[6:7], v21, s[2:3] offset:40
global_load_b128 v[0:3], v21, s[2:3]
s_waitcnt vmcnt(1)
v_readfirstlane_b32 s6, v6
v_readfirstlane_b32 s7, v7
s_delay_alu instid0(VALU_DEP_1)
s_and_b64 s[6:7], s[4:5], s[6:7]
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_114
v_dual_mov_b32 v4, s8 :: v_dual_mov_b32 v5, 0
s_mul_i32 s8, s7, 24
s_mul_hi_u32 s9, s6, 24
v_dual_mov_b32 v6, 2 :: v_dual_mov_b32 v7, 1
s_add_i32 s9, s9, s8
s_mul_i32 s8, s6, 24
s_waitcnt vmcnt(0)
v_add_co_u32 v8, vcc_lo, v0, s8
v_add_co_ci_u32_e32 v9, vcc_lo, s9, v1, vcc_lo
global_store_b128 v[8:9], v[4:7], off offset:8
.LBB0_114:
s_or_b32 exec_lo, exec_lo, s1
s_lshl_b64 s[8:9], s[6:7], 12
v_and_or_b32 v22, v22, 0xffffff1d, 34
s_waitcnt vmcnt(0)
v_add_co_u32 v4, vcc_lo, v2, s8
v_add_co_ci_u32_e32 v5, vcc_lo, s9, v3, vcc_lo
v_lshlrev_b64 v[2:3], 6, v[20:21]
s_mov_b32 s8, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
s_mov_b32 s9, s8
s_mov_b32 s10, s8
s_mov_b32 s11, s8
v_add_co_u32 v8, vcc_lo, v4, v2
v_mov_b32_e32 v6, 0
v_add_co_ci_u32_e32 v9, vcc_lo, v5, v3, vcc_lo
v_dual_mov_b32 v2, s8 :: v_dual_mov_b32 v5, s11
v_dual_mov_b32 v3, s9 :: v_dual_mov_b32 v4, s10
s_delay_alu instid0(VALU_DEP_4)
v_mov_b32_e32 v7, v6
s_clause 0x4
global_store_b64 v[8:9], v[22:23], off
global_store_b128 v[8:9], v[2:5], off offset:8
global_store_b128 v[8:9], v[2:5], off offset:24
global_store_b128 v[8:9], v[2:5], off offset:40
global_store_b64 v[8:9], v[6:7], off offset:56
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_122
v_dual_mov_b32 v8, 0 :: v_dual_mov_b32 v9, s4
v_mov_b32_e32 v10, s5
s_clause 0x1
global_load_b64 v[11:12], v8, s[2:3] offset:32 glc
global_load_b64 v[2:3], v8, s[2:3] offset:40
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s8, v2
v_readfirstlane_b32 s9, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b64 s[8:9], s[8:9], s[4:5]
s_mul_i32 s9, s9, 24
s_mul_hi_u32 s10, s8, 24
s_mul_i32 s8, s8, 24
s_add_i32 s10, s10, s9
v_add_co_u32 v6, vcc_lo, v0, s8
v_add_co_ci_u32_e32 v7, vcc_lo, s10, v1, vcc_lo
s_mov_b32 s8, exec_lo
global_store_b64 v[6:7], v[11:12], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[4:5], v8, v[9:12], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmpx_ne_u64_e64 v[4:5], v[11:12]
s_cbranch_execz .LBB0_118
s_mov_b32 s9, 0
.LBB0_117:
v_dual_mov_b32 v2, s4 :: v_dual_mov_b32 v3, s5
s_sleep 1
global_store_b64 v[6:7], v[4:5], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v8, v[2:5], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5]
v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
s_or_b32 s9, vcc_lo, s9
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s9
s_cbranch_execnz .LBB0_117
.LBB0_118:
s_or_b32 exec_lo, exec_lo, s8
v_mov_b32_e32 v2, 0
s_mov_b32 s9, exec_lo
s_mov_b32 s8, exec_lo
v_mbcnt_lo_u32_b32 v4, s9, 0
global_load_b64 v[2:3], v2, s[2:3] offset:16
v_cmpx_eq_u32_e32 0, v4
s_cbranch_execz .LBB0_120
s_bcnt1_i32_b32 s9, s9
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v5, 0 :: v_dual_mov_b32 v4, s9
s_waitcnt vmcnt(0)
global_atomic_add_u64 v[2:3], v[4:5], off offset:8
.LBB0_120:
s_or_b32 exec_lo, exec_lo, s8
s_waitcnt vmcnt(0)
global_load_b64 v[4:5], v[2:3], off offset:16
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, 0, v[4:5]
s_cbranch_vccnz .LBB0_122
global_load_b32 v2, v[2:3], off offset:24
v_mov_b32_e32 v3, 0
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s8, v2
s_waitcnt_vscnt null, 0x0
global_store_b64 v[4:5], v[2:3], off
s_and_b32 m0, s8, 0xff
s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_122:
s_or_b32 exec_lo, exec_lo, s1
s_mul_i32 s1, s7, 24
s_mul_hi_u32 s7, s6, 24
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_add_i32 s7, s7, s1
s_mul_i32 s1, s6, 24
v_add_co_u32 v0, vcc_lo, v0, s1
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v0, 20
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
s_branch .LBB0_126
.p2align 6
.LBB0_123:
s_or_b32 exec_lo, exec_lo, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s1, v2
s_cmp_eq_u32 s1, 0
s_cbranch_scc1 .LBB0_125
s_sleep 1
s_cbranch_execnz .LBB0_126
s_branch .LBB0_128
.p2align 6
.LBB0_125:
s_branch .LBB0_128
.LBB0_126:
v_mov_b32_e32 v2, 1
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_123
global_load_b32 v2, v[0:1], off glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_and_b32_e32 v2, 1, v2
s_branch .LBB0_123
.LBB0_128:
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_132
v_mov_b32_e32 v6, 0
s_clause 0x2
global_load_b64 v[2:3], v6, s[2:3] offset:40
global_load_b64 v[7:8], v6, s[2:3] offset:24 glc
global_load_b64 v[4:5], v6, s[2:3]
s_waitcnt vmcnt(2)
v_add_co_u32 v9, vcc_lo, v2, 1
v_add_co_ci_u32_e32 v10, vcc_lo, 0, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v9, s4
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v10, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_eq_u64_e32 vcc_lo, 0, v[0:1]
v_dual_cndmask_b32 v1, v1, v10 :: v_dual_cndmask_b32 v0, v0, v9
v_and_b32_e32 v3, v1, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_and_b32_e32 v2, v0, v2
v_mul_lo_u32 v3, v3, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_hi_u32 v9, v2, 24
v_mul_lo_u32 v2, v2, 24
v_add_nc_u32_e32 v3, v9, v3
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_u32 v4, vcc_lo, v4, v2
v_mov_b32_e32 v2, v7
v_add_co_ci_u32_e32 v5, vcc_lo, v5, v3, vcc_lo
v_mov_b32_e32 v3, v8
global_store_b64 v[4:5], v[7:8], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v6, v[0:3], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_ne_u64_e32 vcc_lo, v[2:3], v[7:8]
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_132
s_mov_b32 s0, 0
.LBB0_131:
s_sleep 1
global_store_b64 v[4:5], v[2:3], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[7:8], v6, v[0:3], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[7:8], v[2:3]
v_dual_mov_b32 v2, v7 :: v_dual_mov_b32 v3, v8
s_or_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB0_131
.LBB0_132:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6kernelv
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 256
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 32
.amdhsa_next_free_sgpr 18
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6kernelv, .Lfunc_end0-_Z6kernelv
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type .str,@object
.section .rodata.str1.1,"aMS",@progbits,1
.str:
.asciz "Hello World!\n"
.size .str, 14
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: hidden_block_count_x
- .offset: 4
.size: 4
.value_kind: hidden_block_count_y
- .offset: 8
.size: 4
.value_kind: hidden_block_count_z
- .offset: 12
.size: 2
.value_kind: hidden_group_size_x
- .offset: 14
.size: 2
.value_kind: hidden_group_size_y
- .offset: 16
.size: 2
.value_kind: hidden_group_size_z
- .offset: 18
.size: 2
.value_kind: hidden_remainder_x
- .offset: 20
.size: 2
.value_kind: hidden_remainder_y
- .offset: 22
.size: 2
.value_kind: hidden_remainder_z
- .offset: 40
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 48
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 64
.size: 2
.value_kind: hidden_grid_dims
- .offset: 80
.size: 8
.value_kind: hidden_hostcall_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 256
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6kernelv
.private_segment_fixed_size: 0
.sgpr_count: 20
.sgpr_spill_count: 0
.symbol: _Z6kernelv.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 32
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0010318c_00000000-6_lab1_1.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z24__device_stub__Z6kernelvv
.type _Z24__device_stub__Z6kernelvv, @function
_Z24__device_stub__Z6kernelvv:
.LFB2082:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z6kernelv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z24__device_stub__Z6kernelvv, .-_Z24__device_stub__Z6kernelvv
.globl _Z6kernelv
.type _Z6kernelv, @function
_Z6kernelv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z24__device_stub__Z6kernelvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z6kernelv, .-_Z6kernelv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Hello from CPU!\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movl $2, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $1, 16(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L15
.L12:
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $3, 8(%rsp)
movl $1, 12(%rsp)
movl $1, 16(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L16
.L13:
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
call cudaDeviceSynchronize@PLT
movl $0, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
call _Z24__device_stub__Z6kernelvv
jmp .L12
.L16:
call _Z24__device_stub__Z6kernelvv
jmp .L13
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z6kernelv"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z6kernelv(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "lab1_1.hip"
.globl _Z21__device_stub__kernelv # -- Begin function _Z21__device_stub__kernelv
.p2align 4, 0x90
.type _Z21__device_stub__kernelv,@function
_Z21__device_stub__kernelv: # @_Z21__device_stub__kernelv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z6kernelv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z21__device_stub__kernelv, .Lfunc_end0-_Z21__device_stub__kernelv
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $64, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -16
movabsq $4294967297, %rbx # imm = 0x100000001
leaq 1(%rbx), %rdx
movq %rbx, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z6kernelv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
leaq 2(%rbx), %rdi
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z6kernelv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
movl $.Lstr, %edi
callq puts@PLT
callq hipDeviceSynchronize
xorl %eax, %eax
addq $64, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6kernelv, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6kernelv,@object # @_Z6kernelv
.section .rodata,"a",@progbits
.globl _Z6kernelv
.p2align 3, 0x0
_Z6kernelv:
.quad _Z21__device_stub__kernelv
.size _Z6kernelv, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z6kernelv"
.size .L__unnamed_1, 11
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Hello from CPU!"
.size .Lstr, 16
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__kernelv
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6kernelv
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <cuda.h>
#include <cuda_runtime.h>
#include <iostream>
using namespace std;
//DEVICE
__global__ void kernelVector_suma_constante(float* array, int _size, int _constant){
int idx= blockIdx.x * blockDim.x + threadIdx.x;
if(idx < _size){
array[idx] = array[idx]+_constant;
}
}
//HOST
int main(){
int size = 1000000;
float* arr = new float[size];
float* arr_DEVICE= NULL;
for (int index = 0; index < size; index++){
arr[index] = index;
}
cudaMalloc((void**)&arr_DEVICE,size * sizeof(float));
cudaMemcpy(arr_DEVICE, arr,size * sizeof(float), cudaMemcpyHostToDevice);
kernelVector_suma_constante <<< ceil(size/512),512>>>(arr_DEVICE,size,65);
cudaMemcpy(arr,arr_DEVICE,size * sizeof (float), cudaMemcpyDeviceToHost);
for ( int index = 0; index<100; index++){
cout<<arr[index]<<endl;
}
cudaFree(arr_DEVICE);
delete[] arr;
} | code for sm_80
Function : _Z27kernelVector_suma_constantePfii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R2, R2, c[0x0][0x0], R3 ; /* 0x0000000002027a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R2, c[0x0][0x168], PT ; /* 0x00005a0002007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0203 */
/*0090*/ LDG.E R5, [R2.64] ; /* 0x0000000402057981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ I2F R0, c[0x0][0x16c] ; /* 0x00005b0000007b06 */
/* 0x000ea40000201400 */
/*00b0*/ FADD R5, R0, R5 ; /* 0x0000000500057221 */
/* 0x004fca0000000000 */
/*00c0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*00d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00e0*/ BRA 0xe0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <cuda.h>
#include <cuda_runtime.h>
#include <iostream>
using namespace std;
//DEVICE
__global__ void kernelVector_suma_constante(float* array, int _size, int _constant){
int idx= blockIdx.x * blockDim.x + threadIdx.x;
if(idx < _size){
array[idx] = array[idx]+_constant;
}
}
//HOST
int main(){
int size = 1000000;
float* arr = new float[size];
float* arr_DEVICE= NULL;
for (int index = 0; index < size; index++){
arr[index] = index;
}
cudaMalloc((void**)&arr_DEVICE,size * sizeof(float));
cudaMemcpy(arr_DEVICE, arr,size * sizeof(float), cudaMemcpyHostToDevice);
kernelVector_suma_constante <<< ceil(size/512),512>>>(arr_DEVICE,size,65);
cudaMemcpy(arr,arr_DEVICE,size * sizeof (float), cudaMemcpyDeviceToHost);
for ( int index = 0; index<100; index++){
cout<<arr[index]<<endl;
}
cudaFree(arr_DEVICE);
delete[] arr;
} | .file "tmpxft_0002f421_00000000-6_vector_suma_constante.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z49__device_stub__Z27kernelVector_suma_constantePfiiPfii
.type _Z49__device_stub__Z27kernelVector_suma_constantePfiiPfii, @function
_Z49__device_stub__Z27kernelVector_suma_constantePfiiPfii:
.LFB3694:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z27kernelVector_suma_constantePfii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3694:
.size _Z49__device_stub__Z27kernelVector_suma_constantePfiiPfii, .-_Z49__device_stub__Z27kernelVector_suma_constantePfiiPfii
.globl _Z27kernelVector_suma_constantePfii
.type _Z27kernelVector_suma_constantePfii, @function
_Z27kernelVector_suma_constantePfii:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z49__device_stub__Z27kernelVector_suma_constantePfiiPfii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _Z27kernelVector_suma_constantePfii, .-_Z27kernelVector_suma_constantePfii
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $56, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movl $4000000, %edi
call _Znam@PLT
movq %rax, %r13
movq $0, 8(%rsp)
movl $0, %eax
.L12:
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, 0(%r13,%rax,4)
addq $1, %rax
cmpq $1000000, %rax
jne .L12
leaq 8(%rsp), %rdi
movl $4000000, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $4000000, %edx
movq %r13, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $512, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1953, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L23
.L13:
movl $2, %ecx
movl $4000000, %edx
movq 8(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
movq %r13, %r12
leaq 400(%r13), %r15
leaq _ZSt4cout(%rip), %r14
jmp .L18
.L23:
movl $65, %edx
movl $1000000, %esi
movq 8(%rsp), %rdi
call _Z49__device_stub__Z27kernelVector_suma_constantePfiiPfii
jmp .L13
.L26:
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L24
call _ZSt16__throw_bad_castv@PLT
.L24:
call __stack_chk_fail@PLT
.L16:
movq %rbp, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq 0(%rbp), %rax
movl $10, %esi
movq %rbp, %rdi
call *48(%rax)
movl %eax, %esi
.L17:
movsbl %sil, %esi
movq %rbx, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
addq $4, %r12
cmpq %r12, %r15
je .L25
.L18:
pxor %xmm0, %xmm0
cvtss2sd (%r12), %xmm0
movq %r14, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rbx
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %rbp
testq %rbp, %rbp
je .L26
cmpb $0, 56(%rbp)
je .L16
movzbl 67(%rbp), %esi
jmp .L17
.L25:
movq 8(%rsp), %rdi
call cudaFree@PLT
movq %r13, %rdi
call _ZdaPv@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L27
movl $0, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L27:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size main, .-main
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z27kernelVector_suma_constantePfii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z27kernelVector_suma_constantePfii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <cuda.h>
#include <cuda_runtime.h>
#include <iostream>
using namespace std;
//DEVICE
__global__ void kernelVector_suma_constante(float* array, int _size, int _constant){
int idx= blockIdx.x * blockDim.x + threadIdx.x;
if(idx < _size){
array[idx] = array[idx]+_constant;
}
}
//HOST
int main(){
int size = 1000000;
float* arr = new float[size];
float* arr_DEVICE= NULL;
for (int index = 0; index < size; index++){
arr[index] = index;
}
cudaMalloc((void**)&arr_DEVICE,size * sizeof(float));
cudaMemcpy(arr_DEVICE, arr,size * sizeof(float), cudaMemcpyHostToDevice);
kernelVector_suma_constante <<< ceil(size/512),512>>>(arr_DEVICE,size,65);
cudaMemcpy(arr,arr_DEVICE,size * sizeof (float), cudaMemcpyDeviceToHost);
for ( int index = 0; index<100; index++){
cout<<arr[index]<<endl;
}
cudaFree(arr_DEVICE);
delete[] arr;
} | #include <hip/hip_runtime.h>
#include <iostream>
using namespace std;
//DEVICE
__global__ void kernelVector_suma_constante(float* array, int _size, int _constant){
int idx= blockIdx.x * blockDim.x + threadIdx.x;
if(idx < _size){
array[idx] = array[idx]+_constant;
}
}
//HOST
int main(){
int size = 1000000;
float* arr = new float[size];
float* arr_DEVICE= NULL;
for (int index = 0; index < size; index++){
arr[index] = index;
}
hipMalloc((void**)&arr_DEVICE,size * sizeof(float));
hipMemcpy(arr_DEVICE, arr,size * sizeof(float), hipMemcpyHostToDevice);
kernelVector_suma_constante <<< ceil(size/512),512>>>(arr_DEVICE,size,65);
hipMemcpy(arr,arr_DEVICE,size * sizeof (float), hipMemcpyDeviceToHost);
for ( int index = 0; index<100; index++){
cout<<arr[index]<<endl;
}
hipFree(arr_DEVICE);
delete[] arr;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <iostream>
using namespace std;
//DEVICE
__global__ void kernelVector_suma_constante(float* array, int _size, int _constant){
int idx= blockIdx.x * blockDim.x + threadIdx.x;
if(idx < _size){
array[idx] = array[idx]+_constant;
}
}
//HOST
int main(){
int size = 1000000;
float* arr = new float[size];
float* arr_DEVICE= NULL;
for (int index = 0; index < size; index++){
arr[index] = index;
}
hipMalloc((void**)&arr_DEVICE,size * sizeof(float));
hipMemcpy(arr_DEVICE, arr,size * sizeof(float), hipMemcpyHostToDevice);
kernelVector_suma_constante <<< ceil(size/512),512>>>(arr_DEVICE,size,65);
hipMemcpy(arr,arr_DEVICE,size * sizeof (float), hipMemcpyDeviceToHost);
for ( int index = 0; index<100; index++){
cout<<arr[index]<<endl;
}
hipFree(arr_DEVICE);
delete[] arr;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z27kernelVector_suma_constantePfii
.globl _Z27kernelVector_suma_constantePfii
.p2align 8
.type _Z27kernelVector_suma_constantePfii,@function
_Z27kernelVector_suma_constantePfii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x1c
s_load_b32 s3, s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b64 s[2:3], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b32 s0, s[0:1], 0xc
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
v_cvt_f32_i32_e32 v3, s0
global_load_b32 v2, v[0:1], off
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v2, v3
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z27kernelVector_suma_constantePfii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z27kernelVector_suma_constantePfii, .Lfunc_end0-_Z27kernelVector_suma_constantePfii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z27kernelVector_suma_constantePfii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z27kernelVector_suma_constantePfii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <iostream>
using namespace std;
//DEVICE
__global__ void kernelVector_suma_constante(float* array, int _size, int _constant){
int idx= blockIdx.x * blockDim.x + threadIdx.x;
if(idx < _size){
array[idx] = array[idx]+_constant;
}
}
//HOST
int main(){
int size = 1000000;
float* arr = new float[size];
float* arr_DEVICE= NULL;
for (int index = 0; index < size; index++){
arr[index] = index;
}
hipMalloc((void**)&arr_DEVICE,size * sizeof(float));
hipMemcpy(arr_DEVICE, arr,size * sizeof(float), hipMemcpyHostToDevice);
kernelVector_suma_constante <<< ceil(size/512),512>>>(arr_DEVICE,size,65);
hipMemcpy(arr,arr_DEVICE,size * sizeof (float), hipMemcpyDeviceToHost);
for ( int index = 0; index<100; index++){
cout<<arr[index]<<endl;
}
hipFree(arr_DEVICE);
delete[] arr;
} | .text
.file "vector_suma_constante.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z42__device_stub__kernelVector_suma_constantePfii # -- Begin function _Z42__device_stub__kernelVector_suma_constantePfii
.p2align 4, 0x90
.type _Z42__device_stub__kernelVector_suma_constantePfii,@function
_Z42__device_stub__kernelVector_suma_constantePfii: # @_Z42__device_stub__kernelVector_suma_constantePfii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z27kernelVector_suma_constantePfii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z42__device_stub__kernelVector_suma_constantePfii, .Lfunc_end0-_Z42__device_stub__kernelVector_suma_constantePfii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $104, %rsp
.cfi_def_cfa_offset 144
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $4000000, %edi # imm = 0x3D0900
callq _Znam
movq %rax, %rbx
movq $0, 8(%rsp)
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, (%rbx,%rax,4)
incq %rax
cmpq $1000000, %rax # imm = 0xF4240
jne .LBB1_1
# %bb.2:
leaq 8(%rsp), %rdi
movl $4000000, %esi # imm = 0x3D0900
callq hipMalloc
movq 8(%rsp), %rdi
movl $4000000, %edx # imm = 0x3D0900
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967808, %rdx # imm = 0x100000200
leaq 1441(%rdx), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 8(%rsp), %rax
movq %rax, 72(%rsp)
movl $1000000, 20(%rsp) # imm = 0xF4240
movl $65, 16(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 20(%rsp), %rax
movq %rax, 88(%rsp)
leaq 16(%rsp), %rax
movq %rax, 96(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z27kernelVector_suma_constantePfii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
movq 8(%rsp), %rsi
movl $4000000, %edx # imm = 0x3D0900
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
xorl %r15d, %r15d
jmp .LBB1_5
.p2align 4, 0x90
.LBB1_8: # in Loop: Header=BB1_5 Depth=1
movq %r14, %rdi
movq %rax, %r12
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r12, %rax
.LBB1_9: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
# in Loop: Header=BB1_5 Depth=1
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
incq %r15
cmpq $100, %r15
je .LBB1_10
.LBB1_5: # =>This Inner Loop Header: Depth=1
movss (%rbx,%r15,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r14
testq %r14, %r14
je .LBB1_11
# %bb.6: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
# in Loop: Header=BB1_5 Depth=1
cmpb $0, 56(%r14)
je .LBB1_8
# %bb.7: # in Loop: Header=BB1_5 Depth=1
movzbl 67(%r14), %ecx
jmp .LBB1_9
.LBB1_10:
movq 8(%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq _ZdaPv
xorl %eax, %eax
addq $104, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB1_11:
.cfi_def_cfa_offset 144
callq _ZSt16__throw_bad_castv
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z27kernelVector_suma_constantePfii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z27kernelVector_suma_constantePfii,@object # @_Z27kernelVector_suma_constantePfii
.section .rodata,"a",@progbits
.globl _Z27kernelVector_suma_constantePfii
.p2align 3, 0x0
_Z27kernelVector_suma_constantePfii:
.quad _Z42__device_stub__kernelVector_suma_constantePfii
.size _Z27kernelVector_suma_constantePfii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z27kernelVector_suma_constantePfii"
.size .L__unnamed_1, 36
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z42__device_stub__kernelVector_suma_constantePfii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z27kernelVector_suma_constantePfii
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z27kernelVector_suma_constantePfii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R2, R2, c[0x0][0x0], R3 ; /* 0x0000000002027a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R2, c[0x0][0x168], PT ; /* 0x00005a0002007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0203 */
/*0090*/ LDG.E R5, [R2.64] ; /* 0x0000000402057981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ I2F R0, c[0x0][0x16c] ; /* 0x00005b0000007b06 */
/* 0x000ea40000201400 */
/*00b0*/ FADD R5, R0, R5 ; /* 0x0000000500057221 */
/* 0x004fca0000000000 */
/*00c0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*00d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00e0*/ BRA 0xe0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z27kernelVector_suma_constantePfii
.globl _Z27kernelVector_suma_constantePfii
.p2align 8
.type _Z27kernelVector_suma_constantePfii,@function
_Z27kernelVector_suma_constantePfii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x1c
s_load_b32 s3, s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b64 s[2:3], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b32 s0, s[0:1], 0xc
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
v_cvt_f32_i32_e32 v3, s0
global_load_b32 v2, v[0:1], off
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v2, v3
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z27kernelVector_suma_constantePfii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z27kernelVector_suma_constantePfii, .Lfunc_end0-_Z27kernelVector_suma_constantePfii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z27kernelVector_suma_constantePfii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z27kernelVector_suma_constantePfii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0002f421_00000000-6_vector_suma_constante.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z49__device_stub__Z27kernelVector_suma_constantePfiiPfii
.type _Z49__device_stub__Z27kernelVector_suma_constantePfiiPfii, @function
_Z49__device_stub__Z27kernelVector_suma_constantePfiiPfii:
.LFB3694:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z27kernelVector_suma_constantePfii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3694:
.size _Z49__device_stub__Z27kernelVector_suma_constantePfiiPfii, .-_Z49__device_stub__Z27kernelVector_suma_constantePfiiPfii
.globl _Z27kernelVector_suma_constantePfii
.type _Z27kernelVector_suma_constantePfii, @function
_Z27kernelVector_suma_constantePfii:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z49__device_stub__Z27kernelVector_suma_constantePfiiPfii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _Z27kernelVector_suma_constantePfii, .-_Z27kernelVector_suma_constantePfii
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $56, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movl $4000000, %edi
call _Znam@PLT
movq %rax, %r13
movq $0, 8(%rsp)
movl $0, %eax
.L12:
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, 0(%r13,%rax,4)
addq $1, %rax
cmpq $1000000, %rax
jne .L12
leaq 8(%rsp), %rdi
movl $4000000, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $4000000, %edx
movq %r13, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $512, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1953, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L23
.L13:
movl $2, %ecx
movl $4000000, %edx
movq 8(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
movq %r13, %r12
leaq 400(%r13), %r15
leaq _ZSt4cout(%rip), %r14
jmp .L18
.L23:
movl $65, %edx
movl $1000000, %esi
movq 8(%rsp), %rdi
call _Z49__device_stub__Z27kernelVector_suma_constantePfiiPfii
jmp .L13
.L26:
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L24
call _ZSt16__throw_bad_castv@PLT
.L24:
call __stack_chk_fail@PLT
.L16:
movq %rbp, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq 0(%rbp), %rax
movl $10, %esi
movq %rbp, %rdi
call *48(%rax)
movl %eax, %esi
.L17:
movsbl %sil, %esi
movq %rbx, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
addq $4, %r12
cmpq %r12, %r15
je .L25
.L18:
pxor %xmm0, %xmm0
cvtss2sd (%r12), %xmm0
movq %r14, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rbx
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %rbp
testq %rbp, %rbp
je .L26
cmpb $0, 56(%rbp)
je .L16
movzbl 67(%rbp), %esi
jmp .L17
.L25:
movq 8(%rsp), %rdi
call cudaFree@PLT
movq %r13, %rdi
call _ZdaPv@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L27
movl $0, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L27:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size main, .-main
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z27kernelVector_suma_constantePfii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z27kernelVector_suma_constantePfii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "vector_suma_constante.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z42__device_stub__kernelVector_suma_constantePfii # -- Begin function _Z42__device_stub__kernelVector_suma_constantePfii
.p2align 4, 0x90
.type _Z42__device_stub__kernelVector_suma_constantePfii,@function
_Z42__device_stub__kernelVector_suma_constantePfii: # @_Z42__device_stub__kernelVector_suma_constantePfii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z27kernelVector_suma_constantePfii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z42__device_stub__kernelVector_suma_constantePfii, .Lfunc_end0-_Z42__device_stub__kernelVector_suma_constantePfii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $104, %rsp
.cfi_def_cfa_offset 144
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $4000000, %edi # imm = 0x3D0900
callq _Znam
movq %rax, %rbx
movq $0, 8(%rsp)
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, (%rbx,%rax,4)
incq %rax
cmpq $1000000, %rax # imm = 0xF4240
jne .LBB1_1
# %bb.2:
leaq 8(%rsp), %rdi
movl $4000000, %esi # imm = 0x3D0900
callq hipMalloc
movq 8(%rsp), %rdi
movl $4000000, %edx # imm = 0x3D0900
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967808, %rdx # imm = 0x100000200
leaq 1441(%rdx), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 8(%rsp), %rax
movq %rax, 72(%rsp)
movl $1000000, 20(%rsp) # imm = 0xF4240
movl $65, 16(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 20(%rsp), %rax
movq %rax, 88(%rsp)
leaq 16(%rsp), %rax
movq %rax, 96(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z27kernelVector_suma_constantePfii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
movq 8(%rsp), %rsi
movl $4000000, %edx # imm = 0x3D0900
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
xorl %r15d, %r15d
jmp .LBB1_5
.p2align 4, 0x90
.LBB1_8: # in Loop: Header=BB1_5 Depth=1
movq %r14, %rdi
movq %rax, %r12
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r12, %rax
.LBB1_9: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
# in Loop: Header=BB1_5 Depth=1
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
incq %r15
cmpq $100, %r15
je .LBB1_10
.LBB1_5: # =>This Inner Loop Header: Depth=1
movss (%rbx,%r15,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r14
testq %r14, %r14
je .LBB1_11
# %bb.6: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
# in Loop: Header=BB1_5 Depth=1
cmpb $0, 56(%r14)
je .LBB1_8
# %bb.7: # in Loop: Header=BB1_5 Depth=1
movzbl 67(%r14), %ecx
jmp .LBB1_9
.LBB1_10:
movq 8(%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq _ZdaPv
xorl %eax, %eax
addq $104, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB1_11:
.cfi_def_cfa_offset 144
callq _ZSt16__throw_bad_castv
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z27kernelVector_suma_constantePfii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z27kernelVector_suma_constantePfii,@object # @_Z27kernelVector_suma_constantePfii
.section .rodata,"a",@progbits
.globl _Z27kernelVector_suma_constantePfii
.p2align 3, 0x0
_Z27kernelVector_suma_constantePfii:
.quad _Z42__device_stub__kernelVector_suma_constantePfii
.size _Z27kernelVector_suma_constantePfii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z27kernelVector_suma_constantePfii"
.size .L__unnamed_1, 36
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z42__device_stub__kernelVector_suma_constantePfii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z27kernelVector_suma_constantePfii
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#ifndef THREADS_PER_BLOCK
#define THREADS_PER_BLOCK 1024
#endif
__global__ void myKernel(int64_t *dA, size_t N) {
int id = blockIdx.x * blockDim.x + threadIdx.x;
if (id < N) {
dA[id] = dA[id] + 1;
}
}
extern "C" {
void kernel(int64_t *ptr, size_t N) {
myKernel<<<ceil(((float)N)/THREADS_PER_BLOCK), THREADS_PER_BLOCK>>>(ptr, N);
}
} | code for sm_80
Function : _Z8myKernelPlm
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x168], PT ; /* 0x00005a0000007a0c */
/* 0x000fe40003f06070 */
/*0050*/ SHF.R.S32.HI R3, RZ, 0x1f, R0 ; /* 0x0000001fff037819 */
/* 0x000fc80000011400 */
/*0060*/ ISETP.GE.U32.AND.EX P0, PT, R3, c[0x0][0x16c], PT, P0 ; /* 0x00005b0003007a0c */
/* 0x000fda0003f06100 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ LEA R2, P0, R0, c[0x0][0x160], 0x3 ; /* 0x0000580000027a11 */
/* 0x000fe200078018ff */
/*0090*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*00a0*/ LEA.HI.X R3, R0, c[0x0][0x164], R3, 0x3, P0 ; /* 0x0000590000037a11 */
/* 0x000fca00000f1c03 */
/*00b0*/ LDG.E.64 R4, [R2.64] ; /* 0x0000000402047981 */
/* 0x000ea4000c1e1b00 */
/*00c0*/ IADD3 R4, P0, R4, 0x1, RZ ; /* 0x0000000104047810 */
/* 0x004fca0007f1e0ff */
/*00d0*/ IMAD.X R5, RZ, RZ, R5, P0 ; /* 0x000000ffff057224 */
/* 0x000fca00000e0605 */
/*00e0*/ STG.E.64 [R2.64], R4 ; /* 0x0000000402007986 */
/* 0x000fe2000c101b04 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#ifndef THREADS_PER_BLOCK
#define THREADS_PER_BLOCK 1024
#endif
__global__ void myKernel(int64_t *dA, size_t N) {
int id = blockIdx.x * blockDim.x + threadIdx.x;
if (id < N) {
dA[id] = dA[id] + 1;
}
}
extern "C" {
void kernel(int64_t *ptr, size_t N) {
myKernel<<<ceil(((float)N)/THREADS_PER_BLOCK), THREADS_PER_BLOCK>>>(ptr, N);
}
} | .file "tmpxft_0019c3a4_00000000-6_1d.kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z28__device_stub__Z8myKernelPlmPlm
.type _Z28__device_stub__Z8myKernelPlmPlm, @function
_Z28__device_stub__Z8myKernelPlmPlm:
.LFB2082:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z8myKernelPlm(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z28__device_stub__Z8myKernelPlmPlm, .-_Z28__device_stub__Z8myKernelPlmPlm
.globl _Z8myKernelPlm
.type _Z8myKernelPlm, @function
_Z8myKernelPlm:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z28__device_stub__Z8myKernelPlmPlm
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z8myKernelPlm, .-_Z8myKernelPlm
.globl kernel
.type kernel, @function
kernel:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $40, %rsp
.cfi_def_cfa_offset 64
movq %rdi, %rbp
movq %rsi, %rbx
movl $1024, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
testq %rsi, %rsi
js .L12
pxor %xmm0, %xmm0
cvtsi2ssq %rsi, %xmm0
.L13:
mulss .LC0(%rip), %xmm0
movaps %xmm0, %xmm3
movss .LC4(%rip), %xmm2
movaps %xmm0, %xmm1
andps %xmm2, %xmm1
movss .LC1(%rip), %xmm4
ucomiss %xmm1, %xmm4
jbe .L14
cvttss2sil %xmm0, %eax
pxor %xmm1, %xmm1
cvtsi2ssl %eax, %xmm1
cmpnless %xmm1, %xmm3
movss .LC3(%rip), %xmm4
andps %xmm4, %xmm3
addss %xmm1, %xmm3
andnps %xmm0, %xmm2
orps %xmm2, %xmm3
.L14:
cvttss2siq %xmm3, %rax
movl %eax, 8(%rsp)
movl $1, 12(%rsp)
movl 28(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L17
.L11:
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L12:
.cfi_restore_state
movq %rsi, %rax
shrq %rax
movq %rsi, %rdx
andl $1, %edx
orq %rdx, %rax
pxor %xmm0, %xmm0
cvtsi2ssq %rax, %xmm0
addss %xmm0, %xmm0
jmp .L13
.L17:
movq %rbx, %rsi
movq %rbp, %rdi
call _Z28__device_stub__Z8myKernelPlmPlm
jmp .L11
.cfi_endproc
.LFE2057:
.size kernel, .-kernel
.section .rodata.str1.1,"aMS",@progbits,1
.LC5:
.string "_Z8myKernelPlm"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z8myKernelPlm(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC0:
.long 981467136
.align 4
.LC1:
.long 1258291200
.align 4
.LC3:
.long 1065353216
.align 4
.LC4:
.long 2147483647
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#ifndef THREADS_PER_BLOCK
#define THREADS_PER_BLOCK 1024
#endif
__global__ void myKernel(int64_t *dA, size_t N) {
int id = blockIdx.x * blockDim.x + threadIdx.x;
if (id < N) {
dA[id] = dA[id] + 1;
}
}
extern "C" {
void kernel(int64_t *ptr, size_t N) {
myKernel<<<ceil(((float)N)/THREADS_PER_BLOCK), THREADS_PER_BLOCK>>>(ptr, N);
}
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#ifndef THREADS_PER_BLOCK
#define THREADS_PER_BLOCK 1024
#endif
__global__ void myKernel(int64_t *dA, size_t N) {
int id = blockIdx.x * blockDim.x + threadIdx.x;
if (id < N) {
dA[id] = dA[id] + 1;
}
}
extern "C" {
void kernel(int64_t *ptr, size_t N) {
myKernel<<<ceil(((float)N)/THREADS_PER_BLOCK), THREADS_PER_BLOCK>>>(ptr, N);
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#ifndef THREADS_PER_BLOCK
#define THREADS_PER_BLOCK 1024
#endif
__global__ void myKernel(int64_t *dA, size_t N) {
int id = blockIdx.x * blockDim.x + threadIdx.x;
if (id < N) {
dA[id] = dA[id] + 1;
}
}
extern "C" {
void kernel(int64_t *ptr, size_t N) {
myKernel<<<ceil(((float)N)/THREADS_PER_BLOCK), THREADS_PER_BLOCK>>>(ptr, N);
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z8myKernelPlm
.globl _Z8myKernelPlm
.p2align 8
.type _Z8myKernelPlm,@function
_Z8myKernelPlm:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x1c
s_load_b64 s[2:3], s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1)
v_cmp_gt_u64_e32 vcc_lo, s[2:3], v[1:2]
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_2
s_load_b64 s[0:1], s[0:1], 0x0
v_lshlrev_b64 v[0:1], 3, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b64 v[2:3], v[0:1], off
s_waitcnt vmcnt(0)
v_add_co_u32 v2, vcc_lo, v2, 1
v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
global_store_b64 v[0:1], v[2:3], off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8myKernelPlm
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z8myKernelPlm, .Lfunc_end0-_Z8myKernelPlm
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 8
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8myKernelPlm
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z8myKernelPlm.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#ifndef THREADS_PER_BLOCK
#define THREADS_PER_BLOCK 1024
#endif
__global__ void myKernel(int64_t *dA, size_t N) {
int id = blockIdx.x * blockDim.x + threadIdx.x;
if (id < N) {
dA[id] = dA[id] + 1;
}
}
extern "C" {
void kernel(int64_t *ptr, size_t N) {
myKernel<<<ceil(((float)N)/THREADS_PER_BLOCK), THREADS_PER_BLOCK>>>(ptr, N);
}
} | .text
.file "1d.kernel.hip"
.globl _Z23__device_stub__myKernelPlm # -- Begin function _Z23__device_stub__myKernelPlm
.p2align 4, 0x90
.type _Z23__device_stub__myKernelPlm,@function
_Z23__device_stub__myKernelPlm: # @_Z23__device_stub__myKernelPlm
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z8myKernelPlm, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z23__device_stub__myKernelPlm, .Lfunc_end0-_Z23__device_stub__myKernelPlm
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function kernel
.LCPI1_0:
.long 0x3a800000 # float 9.765625E-4
.text
.globl kernel
.p2align 4, 0x90
.type kernel,@function
kernel: # @kernel
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $88, %rsp
.cfi_def_cfa_offset 112
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movq %rsi, %rbx
movq %rdi, %r14
testq %rsi, %rsi
js .LBB1_1
# %bb.2:
cvtsi2ss %rbx, %xmm0
jmp .LBB1_3
.LBB1_1:
movq %rbx, %rax
shrq %rax
movl %ebx, %ecx
andl $1, %ecx
orq %rax, %rcx
cvtsi2ss %rcx, %xmm0
addss %xmm0, %xmm0
.LBB1_3:
mulss .LCPI1_0(%rip), %xmm0
callq ceilf@PLT
cvttss2si %xmm0, %rax
movl %eax, %edi
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %rdi
orq $1024, %rdx # imm = 0x400
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_5
# %bb.4:
movq %r14, 56(%rsp)
movq %rbx, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z8myKernelPlm, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_5:
addq $88, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size kernel, .Lfunc_end1-kernel
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8myKernelPlm, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z8myKernelPlm,@object # @_Z8myKernelPlm
.section .rodata,"a",@progbits
.globl _Z8myKernelPlm
.p2align 3, 0x0
_Z8myKernelPlm:
.quad _Z23__device_stub__myKernelPlm
.size _Z8myKernelPlm, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z8myKernelPlm"
.size .L__unnamed_1, 15
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__myKernelPlm
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8myKernelPlm
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z8myKernelPlm
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x168], PT ; /* 0x00005a0000007a0c */
/* 0x000fe40003f06070 */
/*0050*/ SHF.R.S32.HI R3, RZ, 0x1f, R0 ; /* 0x0000001fff037819 */
/* 0x000fc80000011400 */
/*0060*/ ISETP.GE.U32.AND.EX P0, PT, R3, c[0x0][0x16c], PT, P0 ; /* 0x00005b0003007a0c */
/* 0x000fda0003f06100 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ LEA R2, P0, R0, c[0x0][0x160], 0x3 ; /* 0x0000580000027a11 */
/* 0x000fe200078018ff */
/*0090*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*00a0*/ LEA.HI.X R3, R0, c[0x0][0x164], R3, 0x3, P0 ; /* 0x0000590000037a11 */
/* 0x000fca00000f1c03 */
/*00b0*/ LDG.E.64 R4, [R2.64] ; /* 0x0000000402047981 */
/* 0x000ea4000c1e1b00 */
/*00c0*/ IADD3 R4, P0, R4, 0x1, RZ ; /* 0x0000000104047810 */
/* 0x004fca0007f1e0ff */
/*00d0*/ IMAD.X R5, RZ, RZ, R5, P0 ; /* 0x000000ffff057224 */
/* 0x000fca00000e0605 */
/*00e0*/ STG.E.64 [R2.64], R4 ; /* 0x0000000402007986 */
/* 0x000fe2000c101b04 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z8myKernelPlm
.globl _Z8myKernelPlm
.p2align 8
.type _Z8myKernelPlm,@function
_Z8myKernelPlm:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x1c
s_load_b64 s[2:3], s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1)
v_cmp_gt_u64_e32 vcc_lo, s[2:3], v[1:2]
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_2
s_load_b64 s[0:1], s[0:1], 0x0
v_lshlrev_b64 v[0:1], 3, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b64 v[2:3], v[0:1], off
s_waitcnt vmcnt(0)
v_add_co_u32 v2, vcc_lo, v2, 1
v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
global_store_b64 v[0:1], v[2:3], off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8myKernelPlm
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z8myKernelPlm, .Lfunc_end0-_Z8myKernelPlm
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 8
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8myKernelPlm
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z8myKernelPlm.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0019c3a4_00000000-6_1d.kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z28__device_stub__Z8myKernelPlmPlm
.type _Z28__device_stub__Z8myKernelPlmPlm, @function
_Z28__device_stub__Z8myKernelPlmPlm:
.LFB2082:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z8myKernelPlm(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z28__device_stub__Z8myKernelPlmPlm, .-_Z28__device_stub__Z8myKernelPlmPlm
.globl _Z8myKernelPlm
.type _Z8myKernelPlm, @function
_Z8myKernelPlm:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z28__device_stub__Z8myKernelPlmPlm
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z8myKernelPlm, .-_Z8myKernelPlm
.globl kernel
.type kernel, @function
kernel:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $40, %rsp
.cfi_def_cfa_offset 64
movq %rdi, %rbp
movq %rsi, %rbx
movl $1024, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
testq %rsi, %rsi
js .L12
pxor %xmm0, %xmm0
cvtsi2ssq %rsi, %xmm0
.L13:
mulss .LC0(%rip), %xmm0
movaps %xmm0, %xmm3
movss .LC4(%rip), %xmm2
movaps %xmm0, %xmm1
andps %xmm2, %xmm1
movss .LC1(%rip), %xmm4
ucomiss %xmm1, %xmm4
jbe .L14
cvttss2sil %xmm0, %eax
pxor %xmm1, %xmm1
cvtsi2ssl %eax, %xmm1
cmpnless %xmm1, %xmm3
movss .LC3(%rip), %xmm4
andps %xmm4, %xmm3
addss %xmm1, %xmm3
andnps %xmm0, %xmm2
orps %xmm2, %xmm3
.L14:
cvttss2siq %xmm3, %rax
movl %eax, 8(%rsp)
movl $1, 12(%rsp)
movl 28(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L17
.L11:
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L12:
.cfi_restore_state
movq %rsi, %rax
shrq %rax
movq %rsi, %rdx
andl $1, %edx
orq %rdx, %rax
pxor %xmm0, %xmm0
cvtsi2ssq %rax, %xmm0
addss %xmm0, %xmm0
jmp .L13
.L17:
movq %rbx, %rsi
movq %rbp, %rdi
call _Z28__device_stub__Z8myKernelPlmPlm
jmp .L11
.cfi_endproc
.LFE2057:
.size kernel, .-kernel
.section .rodata.str1.1,"aMS",@progbits,1
.LC5:
.string "_Z8myKernelPlm"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z8myKernelPlm(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC0:
.long 981467136
.align 4
.LC1:
.long 1258291200
.align 4
.LC3:
.long 1065353216
.align 4
.LC4:
.long 2147483647
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "1d.kernel.hip"
.globl _Z23__device_stub__myKernelPlm # -- Begin function _Z23__device_stub__myKernelPlm
.p2align 4, 0x90
.type _Z23__device_stub__myKernelPlm,@function
_Z23__device_stub__myKernelPlm: # @_Z23__device_stub__myKernelPlm
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z8myKernelPlm, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z23__device_stub__myKernelPlm, .Lfunc_end0-_Z23__device_stub__myKernelPlm
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function kernel
.LCPI1_0:
.long 0x3a800000 # float 9.765625E-4
.text
.globl kernel
.p2align 4, 0x90
.type kernel,@function
kernel: # @kernel
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $88, %rsp
.cfi_def_cfa_offset 112
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movq %rsi, %rbx
movq %rdi, %r14
testq %rsi, %rsi
js .LBB1_1
# %bb.2:
cvtsi2ss %rbx, %xmm0
jmp .LBB1_3
.LBB1_1:
movq %rbx, %rax
shrq %rax
movl %ebx, %ecx
andl $1, %ecx
orq %rax, %rcx
cvtsi2ss %rcx, %xmm0
addss %xmm0, %xmm0
.LBB1_3:
mulss .LCPI1_0(%rip), %xmm0
callq ceilf@PLT
cvttss2si %xmm0, %rax
movl %eax, %edi
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %rdi
orq $1024, %rdx # imm = 0x400
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_5
# %bb.4:
movq %r14, 56(%rsp)
movq %rbx, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z8myKernelPlm, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_5:
addq $88, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size kernel, .Lfunc_end1-kernel
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8myKernelPlm, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z8myKernelPlm,@object # @_Z8myKernelPlm
.section .rodata,"a",@progbits
.globl _Z8myKernelPlm
.p2align 3, 0x0
_Z8myKernelPlm:
.quad _Z23__device_stub__myKernelPlm
.size _Z8myKernelPlm, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z8myKernelPlm"
.size .L__unnamed_1, 15
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__myKernelPlm
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8myKernelPlm
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #pragma once
#include <limits>
#include <curand.h>
#include <curand_kernel.h>
#define INF FLT_MAX
#define EPS 1e-8
#define INT_INF INT_MAX
namespace RayTracing
{
float DegreesToRadians(const float degrees);
__host__ __device__
float Clamp(
const float x,
const float xMin,
const float xMax
);
// uniform distribution
float GenRandom();
// uniform distribution
float GenRandom(
const float a,
const float b
);
} // namespace RayTracing | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #pragma once
#include <limits>
#include <curand.h>
#include <curand_kernel.h>
#define INF FLT_MAX
#define EPS 1e-8
#define INT_INF INT_MAX
namespace RayTracing
{
float DegreesToRadians(const float degrees);
__host__ __device__
float Clamp(
const float x,
const float xMin,
const float xMax
);
// uniform distribution
float GenRandom();
// uniform distribution
float GenRandom(
const float a,
const float b
);
} // namespace RayTracing | .file "tmpxft_000585ab_00000000-6_utils.cuh.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2243:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2243:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "precalc_xorwow_matrix"
.LC1:
.string "precalc_xorwow_offset_matrix"
.LC2:
.string "mrg32k3aM1"
.LC3:
.string "mrg32k3aM2"
.LC4:
.string "mrg32k3aM1SubSeq"
.LC5:
.string "mrg32k3aM2SubSeq"
.LC6:
.string "mrg32k3aM1Seq"
.LC7:
.string "mrg32k3aM2Seq"
.LC8:
.string "__cr_lgamma_table"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2266:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $102400, %r9d
movl $0, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _ZL21precalc_xorwow_matrix(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $102400, %r9d
movl $0, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _ZL28precalc_xorwow_offset_matrix(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _ZL10mrg32k3aM1(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _ZL10mrg32k3aM2(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2016, %r9d
movl $0, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _ZL16mrg32k3aM1SubSeq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2016, %r9d
movl $0, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _ZL16mrg32k3aM2SubSeq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _ZL13mrg32k3aM1Seq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _ZL13mrg32k3aM2Seq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $72, %r9d
movl $0, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _ZL17__cr_lgamma_table(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2266:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL17__cr_lgamma_table
.comm _ZL17__cr_lgamma_table,72,32
.local _ZL13mrg32k3aM2Seq
.comm _ZL13mrg32k3aM2Seq,2304,32
.local _ZL13mrg32k3aM1Seq
.comm _ZL13mrg32k3aM1Seq,2304,32
.local _ZL16mrg32k3aM2SubSeq
.comm _ZL16mrg32k3aM2SubSeq,2016,32
.local _ZL16mrg32k3aM1SubSeq
.comm _ZL16mrg32k3aM1SubSeq,2016,32
.local _ZL10mrg32k3aM2
.comm _ZL10mrg32k3aM2,2304,32
.local _ZL10mrg32k3aM1
.comm _ZL10mrg32k3aM1,2304,32
.local _ZL28precalc_xorwow_offset_matrix
.comm _ZL28precalc_xorwow_offset_matrix,102400,32
.local _ZL21precalc_xorwow_matrix
.comm _ZL21precalc_xorwow_matrix,102400,32
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #pragma once
#include <limits>
#include <curand.h>
#include <curand_kernel.h>
#define INF FLT_MAX
#define EPS 1e-8
#define INT_INF INT_MAX
namespace RayTracing
{
float DegreesToRadians(const float degrees);
__host__ __device__
float Clamp(
const float x,
const float xMin,
const float xMax
);
// uniform distribution
float GenRandom();
// uniform distribution
float GenRandom(
const float a,
const float b
);
} // namespace RayTracing | #pragma once
#include <hip/hip_runtime.h>
#include <limits>
#include <hiprand/hiprand.h>
#include <hiprand/hiprand_kernel.h>
#define INF FLT_MAX
#define EPS 1e-8
#define INT_INF INT_MAX
namespace RayTracing
{
float DegreesToRadians(const float degrees);
__host__ __device__
float Clamp(
const float x,
const float xMin,
const float xMax
);
// uniform distribution
float GenRandom();
// uniform distribution
float GenRandom(
const float a,
const float b
);
} // namespace RayTracing |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #pragma once
#include <hip/hip_runtime.h>
#include <limits>
#include <hiprand/hiprand.h>
#include <hiprand/hiprand_kernel.h>
#define INF FLT_MAX
#define EPS 1e-8
#define INT_INF INT_MAX
namespace RayTracing
{
float DegreesToRadians(const float degrees);
__host__ __device__
float Clamp(
const float x,
const float xMin,
const float xMax
);
// uniform distribution
float GenRandom();
// uniform distribution
float GenRandom(
const float a,
const float b
);
} // namespace RayTracing | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #pragma once
#include <hip/hip_runtime.h>
#include <limits>
#include <hiprand/hiprand.h>
#include <hiprand/hiprand_kernel.h>
#define INF FLT_MAX
#define EPS 1e-8
#define INT_INF INT_MAX
namespace RayTracing
{
float DegreesToRadians(const float degrees);
__host__ __device__
float Clamp(
const float x,
const float xMin,
const float xMax
);
// uniform distribution
float GenRandom();
// uniform distribution
float GenRandom(
const float a,
const float b
);
} // namespace RayTracing | .text
.file "utils.cuh.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000585ab_00000000-6_utils.cuh.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2243:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2243:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "precalc_xorwow_matrix"
.LC1:
.string "precalc_xorwow_offset_matrix"
.LC2:
.string "mrg32k3aM1"
.LC3:
.string "mrg32k3aM2"
.LC4:
.string "mrg32k3aM1SubSeq"
.LC5:
.string "mrg32k3aM2SubSeq"
.LC6:
.string "mrg32k3aM1Seq"
.LC7:
.string "mrg32k3aM2Seq"
.LC8:
.string "__cr_lgamma_table"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2266:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $102400, %r9d
movl $0, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _ZL21precalc_xorwow_matrix(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $102400, %r9d
movl $0, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _ZL28precalc_xorwow_offset_matrix(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _ZL10mrg32k3aM1(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _ZL10mrg32k3aM2(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2016, %r9d
movl $0, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _ZL16mrg32k3aM1SubSeq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2016, %r9d
movl $0, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _ZL16mrg32k3aM2SubSeq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _ZL13mrg32k3aM1Seq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _ZL13mrg32k3aM2Seq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $72, %r9d
movl $0, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _ZL17__cr_lgamma_table(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2266:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL17__cr_lgamma_table
.comm _ZL17__cr_lgamma_table,72,32
.local _ZL13mrg32k3aM2Seq
.comm _ZL13mrg32k3aM2Seq,2304,32
.local _ZL13mrg32k3aM1Seq
.comm _ZL13mrg32k3aM1Seq,2304,32
.local _ZL16mrg32k3aM2SubSeq
.comm _ZL16mrg32k3aM2SubSeq,2016,32
.local _ZL16mrg32k3aM1SubSeq
.comm _ZL16mrg32k3aM1SubSeq,2016,32
.local _ZL10mrg32k3aM2
.comm _ZL10mrg32k3aM2,2304,32
.local _ZL10mrg32k3aM1
.comm _ZL10mrg32k3aM1,2304,32
.local _ZL28precalc_xorwow_offset_matrix
.comm _ZL28precalc_xorwow_offset_matrix,102400,32
.local _ZL21precalc_xorwow_matrix
.comm _ZL21precalc_xorwow_matrix,102400,32
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "utils.cuh.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <cuda_runtime.h>
#define M_SIZE 32
#define BLOCK_SIZE 16
//Calculate the multiplication of two 32*32 matrices A and B in gpu and store the result in C.
//Each block calculate 16*16 submaxtrix of C.
__global__ void Mul(int *A,int *B,int *C,int width_A,int width_B)
{
// Block index
int bx = blockIdx.x;
int by = blockIdx.y;
// Thread index
int tx = threadIdx.x;
int ty = threadIdx.y;
//Index of the first sub-matrix of A and B processed by the block
int aBegin=width_A*BLOCK_SIZE*by;
int bBegin=BLOCK_SIZE*bx;
//Csub of each thread stores corresponding element of the block sub-matrix.
int Csub=0;
int a=aBegin,b=bBegin;
// Shared memory for the sub-matrix of A
__shared__ int As[BLOCK_SIZE][BLOCK_SIZE];
// Shared memory for the sub-matrix of B
__shared__ int Bs[BLOCK_SIZE][BLOCK_SIZE];
for (;a<aBegin+width_A-1;a+=BLOCK_SIZE,b+=BLOCK_SIZE*width_B)
{
// Load the matrices from global memory to shared memory;
// each thread loads one element of each matrix
As[ty][tx] = A[a+width_A*ty + tx];
Bs[ty][tx] = B[b+width_B*ty + tx];
// Synchronize to make sure the matrices are loaded
__syncthreads();
for (int k=0;k<BLOCK_SIZE;k++)
Csub+=As[ty][k]*Bs[k][tx];
//Make sure computation is done before loading new matrices for global memory.
__syncthreads();
}
//Write the block sub-matrix to global memory.
int c=width_B*BLOCK_SIZE*by+BLOCK_SIZE*bx;
C[c+width_B*ty+tx] = Csub;
}
int main()
{
int size = M_SIZE*M_SIZE*sizeof(int);
int *h_A=(int*)malloc(size);
int *h_B=(int*)malloc(size);
int *h_C=(int*)malloc(size);
int *d_A,*d_B,*d_C;
int i, j;
//Intialize A,B,C
for(i=0;i<M_SIZE*M_SIZE;i++)
{
h_A[i]=1;
h_B[i]=1;
h_C[i]=0;
}
//Allocate the memory in GPU to store the content of A,B,C
cudaMalloc((void **)&d_A, size);
cudaMalloc((void **)&d_B, size);
cudaMalloc((void **)&d_C, size);
//Copy h_A, h_B to d_A,d_B
cudaMemcpy(d_A, h_A, size, cudaMemcpyHostToDevice);
cudaMemcpy(d_B, h_B, size, cudaMemcpyHostToDevice);
//Allocate 4 blocks and 256 threads per block.
dim3 dimBlock(BLOCK_SIZE, BLOCK_SIZE);
dim3 dimGrid(2,2);
Mul<<<dimGrid,dimBlock>>>(d_A, d_B, d_C, M_SIZE, M_SIZE);
cudaMemcpy(h_C, d_C, size, cudaMemcpyDeviceToHost);
//print the result
for(i=0; i<M_SIZE; i++)
{
for(j=0; j<M_SIZE; j++)
{
printf("%d ", h_C[i*M_SIZE+j]);
}
printf("\n");
}
printf("Press Enter to stop\n");
getchar();
cudaFree(d_A);
cudaFree(d_B);
cudaFree(d_C);
free(h_A);
free(h_B);
free(h_C);
return 0;
} | code for sm_80
Function : _Z3MulPiS_S_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_CTAID.Y ; /* 0x0000000000047919 */
/* 0x000e220000002600 */
/*0020*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e680000002100 */
/*0050*/ S2R R15, SR_TID.Y ; /* 0x00000000000f7919 */
/* 0x000ea80000002200 */
/*0060*/ S2R R7, SR_CTAID.X ; /* 0x0000000000077919 */
/* 0x000e620000002500 */
/*0070*/ IMAD R2, R4, c[0x0][0x178], RZ ; /* 0x00005e0004027a24 */
/* 0x001fca00078e02ff */
/*0080*/ SHF.L.U32 R19, R2, 0x4, RZ ; /* 0x0000000402137819 */
/* 0x000fe400000006ff */
/*0090*/ LEA R3, R4, R15, 0x4 ; /* 0x0000000f04037211 */
/* 0x004fe400078e20ff */
/*00a0*/ IADD3 R14, R19, c[0x0][0x178], RZ ; /* 0x00005e00130e7a10 */
/* 0x000fe40007ffe0ff */
/*00b0*/ LEA R2, R7, R0, 0x4 ; /* 0x0000000007027211 */
/* 0x002fe400078e20ff */
/*00c0*/ IADD3 R14, R14, -0x1, RZ ; /* 0xffffffff0e0e7810 */
/* 0x000fc60007ffe0ff */
/*00d0*/ IMAD R2, R3, c[0x0][0x17c], R2 ; /* 0x00005f0003027a24 */
/* 0x000fe200078e0202 */
/*00e0*/ ISETP.GE.AND P0, PT, R19, R14, PT ; /* 0x0000000e1300720c */
/* 0x000fc60003f06270 */
/*00f0*/ IMAD.WIDE R2, R2, R5, c[0x0][0x170] ; /* 0x00005c0002027625 */
/* 0x000fd400078e0205 */
/*0100*/ @P0 MOV R23, RZ ; /* 0x000000ff00170202 */
/* 0x000fe20000000f00 */
/*0110*/ @P0 BRA 0x4e0 ; /* 0x000003c000000947 */
/* 0x000fea0003800000 */
/*0120*/ LEA R5, R4, R15, 0x4 ; /* 0x0000000f04057211 */
/* 0x000fe200078e20ff */
/*0130*/ IMAD R4, R15, c[0x0][0x17c], R0.reuse ; /* 0x00005f000f047a24 */
/* 0x100fe200078e0200 */
/*0140*/ MOV R12, 0x4 ; /* 0x00000004000c7802 */
/* 0x000fe40000000f00 */
/*0150*/ MOV R21, c[0x0][0x17c] ; /* 0x00005f0000157a02 */
/* 0x000fe20000000f00 */
/*0160*/ IMAD R5, R5, c[0x0][0x178], R0 ; /* 0x00005e0005057a24 */
/* 0x000fe200078e0200 */
/*0170*/ LEA R4, R7, R4, 0x4 ; /* 0x0000000407047211 */
/* 0x000fe400078e20ff */
/*0180*/ SHF.L.U32 R15, R15, 0x6, RZ ; /* 0x000000060f0f7819 */
/* 0x000fe200000006ff */
/*0190*/ IMAD.WIDE R16, R5, R12, c[0x0][0x160] ; /* 0x0000580005107625 */
/* 0x000fe200078e020c */
/*01a0*/ MOV R23, RZ ; /* 0x000000ff00177202 */
/* 0x000fc40000000f00 */
/*01b0*/ SHF.L.U32 R21, R21, 0x4, RZ ; /* 0x0000000415157819 */
/* 0x000fe200000006ff */
/*01c0*/ IMAD.WIDE R12, R4, R12, c[0x0][0x168] ; /* 0x00005a00040c7625 */
/* 0x000fe200078e020c */
/*01d0*/ LEA R18, R0, R15, 0x2 ; /* 0x0000000f00127211 */
/* 0x000fc800078e10ff */
/*01e0*/ LDG.E R22, [R12.64] ; /* 0x000000040c167981 */
/* 0x0000a8000c1e1900 */
/*01f0*/ LDG.E R27, [R16.64] ; /* 0x00000004101b7981 */
/* 0x0002e2000c1e1900 */
/*0200*/ IADD3 R19, R19, 0x10, RZ ; /* 0x0000001013137810 */
/* 0x000fc80007ffe0ff */
/*0210*/ ISETP.GE.AND P0, PT, R19, R14, PT ; /* 0x0000000e1300720c */
/* 0x000fe20003f06270 */
/*0220*/ IMAD.WIDE R12, R21, 0x4, R12 ; /* 0x00000004150c7825 */
/* 0x001fe200078e020c */
/*0230*/ IADD3 R16, P1, R16, 0x40, RZ ; /* 0x0000004010107810 */
/* 0x002fc80007f3e0ff */
/*0240*/ IADD3.X R17, RZ, R17, RZ, P1, !PT ; /* 0x00000011ff117210 */
/* 0x000fe20000ffe4ff */
/*0250*/ STS [R18+0x400], R22 ; /* 0x0004001612007388 */
/* 0x004fe80000000800 */
/*0260*/ STS [R18], R27 ; /* 0x0000001b12007388 */
/* 0x008fe80000000800 */
/*0270*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0280*/ LDS R24, [R0.X4+0x400] ; /* 0x0004000000187984 */
/* 0x000fe80000004800 */
/*0290*/ LDS.128 R8, [R15] ; /* 0x000000000f087984 */
/* 0x000e280000000c00 */
/*02a0*/ LDS R26, [R0.X4+0x440] ; /* 0x00044000001a7984 */
/* 0x000e680000004800 */
/*02b0*/ LDS R29, [R0.X4+0x480] ; /* 0x00048000001d7984 */
/* 0x000ea80000004800 */
/*02c0*/ LDS R20, [R0.X4+0x4c0] ; /* 0x0004c00000147984 */
/* 0x000ee80000004800 */
/*02d0*/ LDS R25, [R0.X4+0x500] ; /* 0x0005000000197984 */
/* 0x000fe80000004800 */
/*02e0*/ LDS.128 R4, [R15+0x10] ; /* 0x000010000f047984 */
/* 0x000f280000000c00 */
/*02f0*/ LDS R22, [R0.X4+0x540] ; /* 0x0005400000167984 */
/* 0x000f680000004800 */
/*0300*/ LDS R27, [R0.X4+0x580] ; /* 0x00058000001b7984 */
/* 0x000f620000004800 */
/*0310*/ IMAD R8, R24, R8, R23 ; /* 0x0000000818087224 */
/* 0x001fc600078e0217 */
/*0320*/ LDS R24, [R0.X4+0x5c0] ; /* 0x0005c00000187984 */
/* 0x000e220000004800 */
/*0330*/ IMAD R8, R26, R9, R8 ; /* 0x000000091a087224 */
/* 0x002fc600078e0208 */
/*0340*/ LDS R23, [R0.X4+0x600] ; /* 0x0006000000177984 */
/* 0x000fe20000004800 */
/*0350*/ IMAD R8, R29, R10, R8 ; /* 0x0000000a1d087224 */
/* 0x004fc800078e0208 */
/*0360*/ IMAD R20, R20, R11, R8 ; /* 0x0000000b14147224 */
/* 0x008fe400078e0208 */
/*0370*/ LDS.128 R8, [R15+0x20] ; /* 0x000020000f087984 */
/* 0x000e640000000c00 */
/*0380*/ IMAD R4, R25, R4, R20 ; /* 0x0000000419047224 */
/* 0x010fe400078e0214 */
/*0390*/ LDS R20, [R0.X4+0x640] ; /* 0x0006400000147984 */
/* 0x000ea40000004800 */
/*03a0*/ IMAD R4, R22, R5, R4 ; /* 0x0000000516047224 */
/* 0x020fe400078e0204 */
/*03b0*/ LDS R25, [R0.X4+0x680] ; /* 0x0006800000197984 */
/* 0x000ee40000004800 */
/*03c0*/ IMAD R4, R27, R6, R4 ; /* 0x000000061b047224 */
/* 0x000fc400078e0204 */
/*03d0*/ LDS R22, [R0.X4+0x6c0] ; /* 0x0006c00000167984 */
/* 0x000f280000004800 */
/*03e0*/ LDS R27, [R0.X4+0x700] ; /* 0x00070000001b7984 */
/* 0x000fe20000004800 */
/*03f0*/ IMAD R24, R24, R7, R4 ; /* 0x0000000718187224 */
/* 0x001fc600078e0204 */
/*0400*/ LDS.128 R4, [R15+0x30] ; /* 0x000030000f047984 */
/* 0x000e220000000c00 */
/*0410*/ IMAD R24, R23, R8, R24 ; /* 0x0000000817187224 */
/* 0x002fc600078e0218 */
/*0420*/ LDS R8, [R0.X4+0x740] ; /* 0x0007400000087984 */
/* 0x000e680000004800 */
/*0430*/ LDS R23, [R0.X4+0x780] ; /* 0x0007800000177984 */
/* 0x000f620000004800 */
/*0440*/ IMAD R9, R20, R9, R24 ; /* 0x0000000914097224 */
/* 0x004fc600078e0218 */
/*0450*/ LDS R20, [R0.X4+0x7c0] ; /* 0x0007c00000147984 */
/* 0x000ea20000004800 */
/*0460*/ IMAD R9, R25, R10, R9 ; /* 0x0000000a19097224 */
/* 0x008fc800078e0209 */
/*0470*/ IMAD R9, R22, R11, R9 ; /* 0x0000000b16097224 */
/* 0x010fc800078e0209 */
/*0480*/ IMAD R4, R27, R4, R9 ; /* 0x000000041b047224 */
/* 0x001fc800078e0209 */
/*0490*/ IMAD R4, R8, R5, R4 ; /* 0x0000000508047224 */
/* 0x002fc800078e0204 */
/*04a0*/ IMAD R23, R23, R6, R4 ; /* 0x0000000617177224 */
/* 0x020fc800078e0204 */
/*04b0*/ IMAD R23, R20, R7, R23 ; /* 0x0000000714177224 */
/* 0x004fe200078e0217 */
/*04c0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*04d0*/ @!P0 BRA 0x1e0 ; /* 0xfffffd0000008947 */
/* 0x000fea000383ffff */
/*04e0*/ STG.E [R2.64], R23 ; /* 0x0000001702007986 */
/* 0x000fe2000c101904 */
/*04f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0500*/ BRA 0x500; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0510*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0520*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0530*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0540*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0550*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0560*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0570*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0580*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0590*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <cuda_runtime.h>
#define M_SIZE 32
#define BLOCK_SIZE 16
//Calculate the multiplication of two 32*32 matrices A and B in gpu and store the result in C.
//Each block calculate 16*16 submaxtrix of C.
__global__ void Mul(int *A,int *B,int *C,int width_A,int width_B)
{
// Block index
int bx = blockIdx.x;
int by = blockIdx.y;
// Thread index
int tx = threadIdx.x;
int ty = threadIdx.y;
//Index of the first sub-matrix of A and B processed by the block
int aBegin=width_A*BLOCK_SIZE*by;
int bBegin=BLOCK_SIZE*bx;
//Csub of each thread stores corresponding element of the block sub-matrix.
int Csub=0;
int a=aBegin,b=bBegin;
// Shared memory for the sub-matrix of A
__shared__ int As[BLOCK_SIZE][BLOCK_SIZE];
// Shared memory for the sub-matrix of B
__shared__ int Bs[BLOCK_SIZE][BLOCK_SIZE];
for (;a<aBegin+width_A-1;a+=BLOCK_SIZE,b+=BLOCK_SIZE*width_B)
{
// Load the matrices from global memory to shared memory;
// each thread loads one element of each matrix
As[ty][tx] = A[a+width_A*ty + tx];
Bs[ty][tx] = B[b+width_B*ty + tx];
// Synchronize to make sure the matrices are loaded
__syncthreads();
for (int k=0;k<BLOCK_SIZE;k++)
Csub+=As[ty][k]*Bs[k][tx];
//Make sure computation is done before loading new matrices for global memory.
__syncthreads();
}
//Write the block sub-matrix to global memory.
int c=width_B*BLOCK_SIZE*by+BLOCK_SIZE*bx;
C[c+width_B*ty+tx] = Csub;
}
int main()
{
int size = M_SIZE*M_SIZE*sizeof(int);
int *h_A=(int*)malloc(size);
int *h_B=(int*)malloc(size);
int *h_C=(int*)malloc(size);
int *d_A,*d_B,*d_C;
int i, j;
//Intialize A,B,C
for(i=0;i<M_SIZE*M_SIZE;i++)
{
h_A[i]=1;
h_B[i]=1;
h_C[i]=0;
}
//Allocate the memory in GPU to store the content of A,B,C
cudaMalloc((void **)&d_A, size);
cudaMalloc((void **)&d_B, size);
cudaMalloc((void **)&d_C, size);
//Copy h_A, h_B to d_A,d_B
cudaMemcpy(d_A, h_A, size, cudaMemcpyHostToDevice);
cudaMemcpy(d_B, h_B, size, cudaMemcpyHostToDevice);
//Allocate 4 blocks and 256 threads per block.
dim3 dimBlock(BLOCK_SIZE, BLOCK_SIZE);
dim3 dimGrid(2,2);
Mul<<<dimGrid,dimBlock>>>(d_A, d_B, d_C, M_SIZE, M_SIZE);
cudaMemcpy(h_C, d_C, size, cudaMemcpyDeviceToHost);
//print the result
for(i=0; i<M_SIZE; i++)
{
for(j=0; j<M_SIZE; j++)
{
printf("%d ", h_C[i*M_SIZE+j]);
}
printf("\n");
}
printf("Press Enter to stop\n");
getchar();
cudaFree(d_A);
cudaFree(d_B);
cudaFree(d_C);
free(h_A);
free(h_B);
free(h_C);
return 0;
} | .file "tmpxft_00090e1d_00000000-6_matrix_mul.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z28__device_stub__Z3MulPiS_S_iiPiS_S_ii
.type _Z28__device_stub__Z3MulPiS_S_iiPiS_S_ii, @function
_Z28__device_stub__Z3MulPiS_S_iiPiS_S_ii:
.LFB2082:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3MulPiS_S_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z28__device_stub__Z3MulPiS_S_iiPiS_S_ii, .-_Z28__device_stub__Z3MulPiS_S_iiPiS_S_ii
.globl _Z3MulPiS_S_ii
.type _Z3MulPiS_S_ii, @function
_Z3MulPiS_S_ii:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z28__device_stub__Z3MulPiS_S_iiPiS_S_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z3MulPiS_S_ii, .-_Z3MulPiS_S_ii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%d "
.LC1:
.string "\n"
.LC2:
.string "Press Enter to stop\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $88, %rsp
.cfi_def_cfa_offset 144
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $4096, %edi
call malloc@PLT
movq %rax, %r15
movl $4096, %edi
call malloc@PLT
movq %rax, %r14
movl $4096, %edi
call malloc@PLT
movq %rax, %r13
movl $0, %eax
.L12:
movl $1, (%r15,%rax)
movl $1, (%r14,%rax)
movl $0, 0(%r13,%rax)
addq $4, %rax
cmpq $4096, %rax
jne .L12
leaq 24(%rsp), %rdi
movl $4096, %esi
call cudaMalloc@PLT
leaq 32(%rsp), %rdi
movl $4096, %esi
call cudaMalloc@PLT
leaq 40(%rsp), %rdi
movl $4096, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $4096, %edx
movq %r15, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $4096, %edx
movq %r14, %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
movl $16, 48(%rsp)
movl $16, 52(%rsp)
movl $2, 60(%rsp)
movl $2, 64(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 48(%rsp), %rdx
movl $1, %ecx
movq 60(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L21
.L13:
movl $2, %ecx
movl $4096, %edx
movq 40(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
leaq 128(%r13), %rbp
leaq 4224(%r13), %rax
movq %rax, 8(%rsp)
leaq .LC0(%rip), %r12
.L14:
leaq -128(%rbp), %rbx
.L15:
movl (%rbx), %edx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %rbp, %rbx
jne .L15
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
subq $-128, %rbp
movq 8(%rsp), %rax
cmpq %rax, %rbp
jne .L14
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq stdin(%rip), %rdi
call getc@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq %r15, %rdi
call free@PLT
movq %r14, %rdi
call free@PLT
movq %r13, %rdi
call free@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L22
movl $0, %eax
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L21:
.cfi_restore_state
movl $32, %r8d
movl $32, %ecx
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z28__device_stub__Z3MulPiS_S_iiPiS_S_ii
jmp .L13
.L22:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC3:
.string "_Z3MulPiS_S_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z3MulPiS_S_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <cuda_runtime.h>
#define M_SIZE 32
#define BLOCK_SIZE 16
//Calculate the multiplication of two 32*32 matrices A and B in gpu and store the result in C.
//Each block calculate 16*16 submaxtrix of C.
__global__ void Mul(int *A,int *B,int *C,int width_A,int width_B)
{
// Block index
int bx = blockIdx.x;
int by = blockIdx.y;
// Thread index
int tx = threadIdx.x;
int ty = threadIdx.y;
//Index of the first sub-matrix of A and B processed by the block
int aBegin=width_A*BLOCK_SIZE*by;
int bBegin=BLOCK_SIZE*bx;
//Csub of each thread stores corresponding element of the block sub-matrix.
int Csub=0;
int a=aBegin,b=bBegin;
// Shared memory for the sub-matrix of A
__shared__ int As[BLOCK_SIZE][BLOCK_SIZE];
// Shared memory for the sub-matrix of B
__shared__ int Bs[BLOCK_SIZE][BLOCK_SIZE];
for (;a<aBegin+width_A-1;a+=BLOCK_SIZE,b+=BLOCK_SIZE*width_B)
{
// Load the matrices from global memory to shared memory;
// each thread loads one element of each matrix
As[ty][tx] = A[a+width_A*ty + tx];
Bs[ty][tx] = B[b+width_B*ty + tx];
// Synchronize to make sure the matrices are loaded
__syncthreads();
for (int k=0;k<BLOCK_SIZE;k++)
Csub+=As[ty][k]*Bs[k][tx];
//Make sure computation is done before loading new matrices for global memory.
__syncthreads();
}
//Write the block sub-matrix to global memory.
int c=width_B*BLOCK_SIZE*by+BLOCK_SIZE*bx;
C[c+width_B*ty+tx] = Csub;
}
int main()
{
int size = M_SIZE*M_SIZE*sizeof(int);
int *h_A=(int*)malloc(size);
int *h_B=(int*)malloc(size);
int *h_C=(int*)malloc(size);
int *d_A,*d_B,*d_C;
int i, j;
//Intialize A,B,C
for(i=0;i<M_SIZE*M_SIZE;i++)
{
h_A[i]=1;
h_B[i]=1;
h_C[i]=0;
}
//Allocate the memory in GPU to store the content of A,B,C
cudaMalloc((void **)&d_A, size);
cudaMalloc((void **)&d_B, size);
cudaMalloc((void **)&d_C, size);
//Copy h_A, h_B to d_A,d_B
cudaMemcpy(d_A, h_A, size, cudaMemcpyHostToDevice);
cudaMemcpy(d_B, h_B, size, cudaMemcpyHostToDevice);
//Allocate 4 blocks and 256 threads per block.
dim3 dimBlock(BLOCK_SIZE, BLOCK_SIZE);
dim3 dimGrid(2,2);
Mul<<<dimGrid,dimBlock>>>(d_A, d_B, d_C, M_SIZE, M_SIZE);
cudaMemcpy(h_C, d_C, size, cudaMemcpyDeviceToHost);
//print the result
for(i=0; i<M_SIZE; i++)
{
for(j=0; j<M_SIZE; j++)
{
printf("%d ", h_C[i*M_SIZE+j]);
}
printf("\n");
}
printf("Press Enter to stop\n");
getchar();
cudaFree(d_A);
cudaFree(d_B);
cudaFree(d_C);
free(h_A);
free(h_B);
free(h_C);
return 0;
} | #include <stdio.h>
#include <hip/hip_runtime.h>
#define M_SIZE 32
#define BLOCK_SIZE 16
//Calculate the multiplication of two 32*32 matrices A and B in gpu and store the result in C.
//Each block calculate 16*16 submaxtrix of C.
__global__ void Mul(int *A,int *B,int *C,int width_A,int width_B)
{
// Block index
int bx = blockIdx.x;
int by = blockIdx.y;
// Thread index
int tx = threadIdx.x;
int ty = threadIdx.y;
//Index of the first sub-matrix of A and B processed by the block
int aBegin=width_A*BLOCK_SIZE*by;
int bBegin=BLOCK_SIZE*bx;
//Csub of each thread stores corresponding element of the block sub-matrix.
int Csub=0;
int a=aBegin,b=bBegin;
// Shared memory for the sub-matrix of A
__shared__ int As[BLOCK_SIZE][BLOCK_SIZE];
// Shared memory for the sub-matrix of B
__shared__ int Bs[BLOCK_SIZE][BLOCK_SIZE];
for (;a<aBegin+width_A-1;a+=BLOCK_SIZE,b+=BLOCK_SIZE*width_B)
{
// Load the matrices from global memory to shared memory;
// each thread loads one element of each matrix
As[ty][tx] = A[a+width_A*ty + tx];
Bs[ty][tx] = B[b+width_B*ty + tx];
// Synchronize to make sure the matrices are loaded
__syncthreads();
for (int k=0;k<BLOCK_SIZE;k++)
Csub+=As[ty][k]*Bs[k][tx];
//Make sure computation is done before loading new matrices for global memory.
__syncthreads();
}
//Write the block sub-matrix to global memory.
int c=width_B*BLOCK_SIZE*by+BLOCK_SIZE*bx;
C[c+width_B*ty+tx] = Csub;
}
int main()
{
int size = M_SIZE*M_SIZE*sizeof(int);
int *h_A=(int*)malloc(size);
int *h_B=(int*)malloc(size);
int *h_C=(int*)malloc(size);
int *d_A,*d_B,*d_C;
int i, j;
//Intialize A,B,C
for(i=0;i<M_SIZE*M_SIZE;i++)
{
h_A[i]=1;
h_B[i]=1;
h_C[i]=0;
}
//Allocate the memory in GPU to store the content of A,B,C
hipMalloc((void **)&d_A, size);
hipMalloc((void **)&d_B, size);
hipMalloc((void **)&d_C, size);
//Copy h_A, h_B to d_A,d_B
hipMemcpy(d_A, h_A, size, hipMemcpyHostToDevice);
hipMemcpy(d_B, h_B, size, hipMemcpyHostToDevice);
//Allocate 4 blocks and 256 threads per block.
dim3 dimBlock(BLOCK_SIZE, BLOCK_SIZE);
dim3 dimGrid(2,2);
Mul<<<dimGrid,dimBlock>>>(d_A, d_B, d_C, M_SIZE, M_SIZE);
hipMemcpy(h_C, d_C, size, hipMemcpyDeviceToHost);
//print the result
for(i=0; i<M_SIZE; i++)
{
for(j=0; j<M_SIZE; j++)
{
printf("%d ", h_C[i*M_SIZE+j]);
}
printf("\n");
}
printf("Press Enter to stop\n");
getchar();
hipFree(d_A);
hipFree(d_B);
hipFree(d_C);
free(h_A);
free(h_B);
free(h_C);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <stdio.h>
#include <hip/hip_runtime.h>
#define M_SIZE 32
#define BLOCK_SIZE 16
//Calculate the multiplication of two 32*32 matrices A and B in gpu and store the result in C.
//Each block calculate 16*16 submaxtrix of C.
__global__ void Mul(int *A,int *B,int *C,int width_A,int width_B)
{
// Block index
int bx = blockIdx.x;
int by = blockIdx.y;
// Thread index
int tx = threadIdx.x;
int ty = threadIdx.y;
//Index of the first sub-matrix of A and B processed by the block
int aBegin=width_A*BLOCK_SIZE*by;
int bBegin=BLOCK_SIZE*bx;
//Csub of each thread stores corresponding element of the block sub-matrix.
int Csub=0;
int a=aBegin,b=bBegin;
// Shared memory for the sub-matrix of A
__shared__ int As[BLOCK_SIZE][BLOCK_SIZE];
// Shared memory for the sub-matrix of B
__shared__ int Bs[BLOCK_SIZE][BLOCK_SIZE];
for (;a<aBegin+width_A-1;a+=BLOCK_SIZE,b+=BLOCK_SIZE*width_B)
{
// Load the matrices from global memory to shared memory;
// each thread loads one element of each matrix
As[ty][tx] = A[a+width_A*ty + tx];
Bs[ty][tx] = B[b+width_B*ty + tx];
// Synchronize to make sure the matrices are loaded
__syncthreads();
for (int k=0;k<BLOCK_SIZE;k++)
Csub+=As[ty][k]*Bs[k][tx];
//Make sure computation is done before loading new matrices for global memory.
__syncthreads();
}
//Write the block sub-matrix to global memory.
int c=width_B*BLOCK_SIZE*by+BLOCK_SIZE*bx;
C[c+width_B*ty+tx] = Csub;
}
int main()
{
int size = M_SIZE*M_SIZE*sizeof(int);
int *h_A=(int*)malloc(size);
int *h_B=(int*)malloc(size);
int *h_C=(int*)malloc(size);
int *d_A,*d_B,*d_C;
int i, j;
//Intialize A,B,C
for(i=0;i<M_SIZE*M_SIZE;i++)
{
h_A[i]=1;
h_B[i]=1;
h_C[i]=0;
}
//Allocate the memory in GPU to store the content of A,B,C
hipMalloc((void **)&d_A, size);
hipMalloc((void **)&d_B, size);
hipMalloc((void **)&d_C, size);
//Copy h_A, h_B to d_A,d_B
hipMemcpy(d_A, h_A, size, hipMemcpyHostToDevice);
hipMemcpy(d_B, h_B, size, hipMemcpyHostToDevice);
//Allocate 4 blocks and 256 threads per block.
dim3 dimBlock(BLOCK_SIZE, BLOCK_SIZE);
dim3 dimGrid(2,2);
Mul<<<dimGrid,dimBlock>>>(d_A, d_B, d_C, M_SIZE, M_SIZE);
hipMemcpy(h_C, d_C, size, hipMemcpyDeviceToHost);
//print the result
for(i=0; i<M_SIZE; i++)
{
for(j=0; j<M_SIZE; j++)
{
printf("%d ", h_C[i*M_SIZE+j]);
}
printf("\n");
}
printf("Press Enter to stop\n");
getchar();
hipFree(d_A);
hipFree(d_B);
hipFree(d_C);
free(h_A);
free(h_B);
free(h_C);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3MulPiS_S_ii
.globl _Z3MulPiS_S_ii
.p2align 8
.type _Z3MulPiS_S_ii,@function
_Z3MulPiS_S_ii:
s_load_b64 s[2:3], s[0:1], 0x18
v_and_b32_e32 v1, 0x3ff, v0
v_bfe_u32 v5, v0, 10, 10
v_mov_b32_e32 v0, 0
s_lshl_b32 s8, s14, 4
s_waitcnt lgkmcnt(0)
s_mul_i32 s4, s2, s15
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_lshl_b32 s9, s4, 4
s_add_i32 s10, s2, s9
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s10, s10, -1
s_cmp_ge_i32 s9, s10
s_cbranch_scc1 .LBB0_5
s_load_b128 s[4:7], s[0:1], 0x0
v_mad_u64_u32 v[2:3], null, v5, s2, v[1:2]
v_lshlrev_b32_e32 v0, 2, v1
v_lshlrev_b32_e32 v6, 6, v5
s_lshl_b32 s2, s3, 4
s_mov_b32 s11, s8
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_nc_u32_e32 v7, 0x400, v0
v_mad_u64_u32 v[3:4], null, v5, s3, v[1:2]
v_add_nc_u32_e32 v4, v6, v0
v_mov_b32_e32 v0, 0
s_delay_alu instid0(VALU_DEP_4)
v_add_nc_u32_e32 v8, v7, v6
s_set_inst_prefetch_distance 0x1
.p2align 6
.LBB0_2:
v_add_nc_u32_e32 v9, s9, v2
v_add_nc_u32_e32 v11, s11, v3
s_mov_b32 s12, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v10, 31, v9
v_ashrrev_i32_e32 v12, 31, v11
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[9:10], 2, v[9:10]
v_lshlrev_b64 v[11:12], 2, v[11:12]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v9, vcc_lo, s4, v9
v_add_co_ci_u32_e32 v10, vcc_lo, s5, v10, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v11, vcc_lo, s6, v11
v_add_co_ci_u32_e32 v12, vcc_lo, s7, v12, vcc_lo
global_load_b32 v10, v[9:10], off
global_load_b32 v11, v[11:12], off
v_mov_b32_e32 v9, v7
s_waitcnt vmcnt(1)
ds_store_b32 v4, v10
s_waitcnt vmcnt(0)
ds_store_b32 v8, v11
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
.LBB0_3:
v_add_nc_u32_e32 v10, s12, v6
s_add_i32 s12, s12, 4
ds_load_b32 v12, v9
ds_load_b32 v13, v10
s_cmp_eq_u32 s12, 64
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[10:11], null, v12, v13, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_dual_mov_b32 v0, v10 :: v_dual_add_nc_u32 v9, 64, v9
s_cbranch_scc0 .LBB0_3
s_add_i32 s9, s9, 16
s_add_i32 s11, s11, s2
s_cmp_ge_i32 s9, s10
s_barrier
buffer_gl0_inv
s_cbranch_scc0 .LBB0_2
.LBB0_5:
s_set_inst_prefetch_distance 0x2
v_lshl_add_u32 v2, s15, 4, v5
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v2, v2, s3
v_add3_u32 v1, s8, v1, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v1, vcc_lo, s0, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
global_store_b32 v[1:2], v0, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3MulPiS_S_ii
.amdhsa_group_segment_fixed_size 2048
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 32
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 14
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3MulPiS_S_ii, .Lfunc_end0-_Z3MulPiS_S_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 2048
.kernarg_segment_align: 8
.kernarg_segment_size: 32
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3MulPiS_S_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z3MulPiS_S_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 14
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <stdio.h>
#include <hip/hip_runtime.h>
#define M_SIZE 32
#define BLOCK_SIZE 16
//Calculate the multiplication of two 32*32 matrices A and B in gpu and store the result in C.
//Each block calculate 16*16 submaxtrix of C.
__global__ void Mul(int *A,int *B,int *C,int width_A,int width_B)
{
// Block index
int bx = blockIdx.x;
int by = blockIdx.y;
// Thread index
int tx = threadIdx.x;
int ty = threadIdx.y;
//Index of the first sub-matrix of A and B processed by the block
int aBegin=width_A*BLOCK_SIZE*by;
int bBegin=BLOCK_SIZE*bx;
//Csub of each thread stores corresponding element of the block sub-matrix.
int Csub=0;
int a=aBegin,b=bBegin;
// Shared memory for the sub-matrix of A
__shared__ int As[BLOCK_SIZE][BLOCK_SIZE];
// Shared memory for the sub-matrix of B
__shared__ int Bs[BLOCK_SIZE][BLOCK_SIZE];
for (;a<aBegin+width_A-1;a+=BLOCK_SIZE,b+=BLOCK_SIZE*width_B)
{
// Load the matrices from global memory to shared memory;
// each thread loads one element of each matrix
As[ty][tx] = A[a+width_A*ty + tx];
Bs[ty][tx] = B[b+width_B*ty + tx];
// Synchronize to make sure the matrices are loaded
__syncthreads();
for (int k=0;k<BLOCK_SIZE;k++)
Csub+=As[ty][k]*Bs[k][tx];
//Make sure computation is done before loading new matrices for global memory.
__syncthreads();
}
//Write the block sub-matrix to global memory.
int c=width_B*BLOCK_SIZE*by+BLOCK_SIZE*bx;
C[c+width_B*ty+tx] = Csub;
}
int main()
{
int size = M_SIZE*M_SIZE*sizeof(int);
int *h_A=(int*)malloc(size);
int *h_B=(int*)malloc(size);
int *h_C=(int*)malloc(size);
int *d_A,*d_B,*d_C;
int i, j;
//Intialize A,B,C
for(i=0;i<M_SIZE*M_SIZE;i++)
{
h_A[i]=1;
h_B[i]=1;
h_C[i]=0;
}
//Allocate the memory in GPU to store the content of A,B,C
hipMalloc((void **)&d_A, size);
hipMalloc((void **)&d_B, size);
hipMalloc((void **)&d_C, size);
//Copy h_A, h_B to d_A,d_B
hipMemcpy(d_A, h_A, size, hipMemcpyHostToDevice);
hipMemcpy(d_B, h_B, size, hipMemcpyHostToDevice);
//Allocate 4 blocks and 256 threads per block.
dim3 dimBlock(BLOCK_SIZE, BLOCK_SIZE);
dim3 dimGrid(2,2);
Mul<<<dimGrid,dimBlock>>>(d_A, d_B, d_C, M_SIZE, M_SIZE);
hipMemcpy(h_C, d_C, size, hipMemcpyDeviceToHost);
//print the result
for(i=0; i<M_SIZE; i++)
{
for(j=0; j<M_SIZE; j++)
{
printf("%d ", h_C[i*M_SIZE+j]);
}
printf("\n");
}
printf("Press Enter to stop\n");
getchar();
hipFree(d_A);
hipFree(d_B);
hipFree(d_C);
free(h_A);
free(h_B);
free(h_C);
return 0;
} | .text
.file "matrix_mul.hip"
.globl _Z18__device_stub__MulPiS_S_ii # -- Begin function _Z18__device_stub__MulPiS_S_ii
.p2align 4, 0x90
.type _Z18__device_stub__MulPiS_S_ii,@function
_Z18__device_stub__MulPiS_S_ii: # @_Z18__device_stub__MulPiS_S_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3MulPiS_S_ii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z18__device_stub__MulPiS_S_ii, .Lfunc_end0-_Z18__device_stub__MulPiS_S_ii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $152, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $4096, %edi # imm = 0x1000
callq malloc
movq %rax, %rbx
movl $4096, %edi # imm = 0x1000
callq malloc
movq %rax, %r14
movl $4096, %edi # imm = 0x1000
callq malloc
movq %rax, %r15
xorl %r12d, %r12d
movl $4096, %edx # imm = 0x1000
movq %rax, %rdi
xorl %esi, %esi
callq memset@PLT
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movl $1, (%rbx,%r12,4)
movl $1, (%r14,%r12,4)
incq %r12
cmpq $1024, %r12 # imm = 0x400
jne .LBB1_1
# %bb.2:
leaq 24(%rsp), %rdi
movl $4096, %esi # imm = 0x1000
callq hipMalloc
leaq 16(%rsp), %rdi
movl $4096, %esi # imm = 0x1000
callq hipMalloc
leaq 8(%rsp), %rdi
movl $4096, %esi # imm = 0x1000
callq hipMalloc
movq 24(%rsp), %rdi
movl $4096, %edx # imm = 0x1000
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
movl $4096, %edx # imm = 0x1000
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $8589934594, %rdi # imm = 0x200000002
movabsq $68719476752, %rdx # imm = 0x1000000010
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
movl $32, 36(%rsp)
movl $32, 32(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 36(%rsp), %rax
movq %rax, 136(%rsp)
leaq 32(%rsp), %rax
movq %rax, 144(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z3MulPiS_S_ii, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
movq 8(%rsp), %rsi
movl $4096, %edx # imm = 0x1000
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
movq %r15, %r12
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB1_5: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_6 Depth 2
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB1_6: # Parent Loop BB1_5 Depth=1
# => This Inner Loop Header: Depth=2
movl (%r12,%rbp,4), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
incq %rbp
cmpq $32, %rbp
jne .LBB1_6
# %bb.7: # in Loop: Header=BB1_5 Depth=1
movl $10, %edi
callq putchar@PLT
incq %r13
subq $-128, %r12
cmpq $32, %r13
jne .LBB1_5
# %bb.8:
movl $.Lstr, %edi
callq puts@PLT
movq stdin(%rip), %rdi
callq getc
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
xorl %eax, %eax
addq $152, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3MulPiS_S_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3MulPiS_S_ii,@object # @_Z3MulPiS_S_ii
.section .rodata,"a",@progbits
.globl _Z3MulPiS_S_ii
.p2align 3, 0x0
_Z3MulPiS_S_ii:
.quad _Z18__device_stub__MulPiS_S_ii
.size _Z3MulPiS_S_ii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%d "
.size .L.str, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z3MulPiS_S_ii"
.size .L__unnamed_1, 15
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Press Enter to stop"
.size .Lstr, 20
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__MulPiS_S_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3MulPiS_S_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z3MulPiS_S_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_CTAID.Y ; /* 0x0000000000047919 */
/* 0x000e220000002600 */
/*0020*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e680000002100 */
/*0050*/ S2R R15, SR_TID.Y ; /* 0x00000000000f7919 */
/* 0x000ea80000002200 */
/*0060*/ S2R R7, SR_CTAID.X ; /* 0x0000000000077919 */
/* 0x000e620000002500 */
/*0070*/ IMAD R2, R4, c[0x0][0x178], RZ ; /* 0x00005e0004027a24 */
/* 0x001fca00078e02ff */
/*0080*/ SHF.L.U32 R19, R2, 0x4, RZ ; /* 0x0000000402137819 */
/* 0x000fe400000006ff */
/*0090*/ LEA R3, R4, R15, 0x4 ; /* 0x0000000f04037211 */
/* 0x004fe400078e20ff */
/*00a0*/ IADD3 R14, R19, c[0x0][0x178], RZ ; /* 0x00005e00130e7a10 */
/* 0x000fe40007ffe0ff */
/*00b0*/ LEA R2, R7, R0, 0x4 ; /* 0x0000000007027211 */
/* 0x002fe400078e20ff */
/*00c0*/ IADD3 R14, R14, -0x1, RZ ; /* 0xffffffff0e0e7810 */
/* 0x000fc60007ffe0ff */
/*00d0*/ IMAD R2, R3, c[0x0][0x17c], R2 ; /* 0x00005f0003027a24 */
/* 0x000fe200078e0202 */
/*00e0*/ ISETP.GE.AND P0, PT, R19, R14, PT ; /* 0x0000000e1300720c */
/* 0x000fc60003f06270 */
/*00f0*/ IMAD.WIDE R2, R2, R5, c[0x0][0x170] ; /* 0x00005c0002027625 */
/* 0x000fd400078e0205 */
/*0100*/ @P0 MOV R23, RZ ; /* 0x000000ff00170202 */
/* 0x000fe20000000f00 */
/*0110*/ @P0 BRA 0x4e0 ; /* 0x000003c000000947 */
/* 0x000fea0003800000 */
/*0120*/ LEA R5, R4, R15, 0x4 ; /* 0x0000000f04057211 */
/* 0x000fe200078e20ff */
/*0130*/ IMAD R4, R15, c[0x0][0x17c], R0.reuse ; /* 0x00005f000f047a24 */
/* 0x100fe200078e0200 */
/*0140*/ MOV R12, 0x4 ; /* 0x00000004000c7802 */
/* 0x000fe40000000f00 */
/*0150*/ MOV R21, c[0x0][0x17c] ; /* 0x00005f0000157a02 */
/* 0x000fe20000000f00 */
/*0160*/ IMAD R5, R5, c[0x0][0x178], R0 ; /* 0x00005e0005057a24 */
/* 0x000fe200078e0200 */
/*0170*/ LEA R4, R7, R4, 0x4 ; /* 0x0000000407047211 */
/* 0x000fe400078e20ff */
/*0180*/ SHF.L.U32 R15, R15, 0x6, RZ ; /* 0x000000060f0f7819 */
/* 0x000fe200000006ff */
/*0190*/ IMAD.WIDE R16, R5, R12, c[0x0][0x160] ; /* 0x0000580005107625 */
/* 0x000fe200078e020c */
/*01a0*/ MOV R23, RZ ; /* 0x000000ff00177202 */
/* 0x000fc40000000f00 */
/*01b0*/ SHF.L.U32 R21, R21, 0x4, RZ ; /* 0x0000000415157819 */
/* 0x000fe200000006ff */
/*01c0*/ IMAD.WIDE R12, R4, R12, c[0x0][0x168] ; /* 0x00005a00040c7625 */
/* 0x000fe200078e020c */
/*01d0*/ LEA R18, R0, R15, 0x2 ; /* 0x0000000f00127211 */
/* 0x000fc800078e10ff */
/*01e0*/ LDG.E R22, [R12.64] ; /* 0x000000040c167981 */
/* 0x0000a8000c1e1900 */
/*01f0*/ LDG.E R27, [R16.64] ; /* 0x00000004101b7981 */
/* 0x0002e2000c1e1900 */
/*0200*/ IADD3 R19, R19, 0x10, RZ ; /* 0x0000001013137810 */
/* 0x000fc80007ffe0ff */
/*0210*/ ISETP.GE.AND P0, PT, R19, R14, PT ; /* 0x0000000e1300720c */
/* 0x000fe20003f06270 */
/*0220*/ IMAD.WIDE R12, R21, 0x4, R12 ; /* 0x00000004150c7825 */
/* 0x001fe200078e020c */
/*0230*/ IADD3 R16, P1, R16, 0x40, RZ ; /* 0x0000004010107810 */
/* 0x002fc80007f3e0ff */
/*0240*/ IADD3.X R17, RZ, R17, RZ, P1, !PT ; /* 0x00000011ff117210 */
/* 0x000fe20000ffe4ff */
/*0250*/ STS [R18+0x400], R22 ; /* 0x0004001612007388 */
/* 0x004fe80000000800 */
/*0260*/ STS [R18], R27 ; /* 0x0000001b12007388 */
/* 0x008fe80000000800 */
/*0270*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0280*/ LDS R24, [R0.X4+0x400] ; /* 0x0004000000187984 */
/* 0x000fe80000004800 */
/*0290*/ LDS.128 R8, [R15] ; /* 0x000000000f087984 */
/* 0x000e280000000c00 */
/*02a0*/ LDS R26, [R0.X4+0x440] ; /* 0x00044000001a7984 */
/* 0x000e680000004800 */
/*02b0*/ LDS R29, [R0.X4+0x480] ; /* 0x00048000001d7984 */
/* 0x000ea80000004800 */
/*02c0*/ LDS R20, [R0.X4+0x4c0] ; /* 0x0004c00000147984 */
/* 0x000ee80000004800 */
/*02d0*/ LDS R25, [R0.X4+0x500] ; /* 0x0005000000197984 */
/* 0x000fe80000004800 */
/*02e0*/ LDS.128 R4, [R15+0x10] ; /* 0x000010000f047984 */
/* 0x000f280000000c00 */
/*02f0*/ LDS R22, [R0.X4+0x540] ; /* 0x0005400000167984 */
/* 0x000f680000004800 */
/*0300*/ LDS R27, [R0.X4+0x580] ; /* 0x00058000001b7984 */
/* 0x000f620000004800 */
/*0310*/ IMAD R8, R24, R8, R23 ; /* 0x0000000818087224 */
/* 0x001fc600078e0217 */
/*0320*/ LDS R24, [R0.X4+0x5c0] ; /* 0x0005c00000187984 */
/* 0x000e220000004800 */
/*0330*/ IMAD R8, R26, R9, R8 ; /* 0x000000091a087224 */
/* 0x002fc600078e0208 */
/*0340*/ LDS R23, [R0.X4+0x600] ; /* 0x0006000000177984 */
/* 0x000fe20000004800 */
/*0350*/ IMAD R8, R29, R10, R8 ; /* 0x0000000a1d087224 */
/* 0x004fc800078e0208 */
/*0360*/ IMAD R20, R20, R11, R8 ; /* 0x0000000b14147224 */
/* 0x008fe400078e0208 */
/*0370*/ LDS.128 R8, [R15+0x20] ; /* 0x000020000f087984 */
/* 0x000e640000000c00 */
/*0380*/ IMAD R4, R25, R4, R20 ; /* 0x0000000419047224 */
/* 0x010fe400078e0214 */
/*0390*/ LDS R20, [R0.X4+0x640] ; /* 0x0006400000147984 */
/* 0x000ea40000004800 */
/*03a0*/ IMAD R4, R22, R5, R4 ; /* 0x0000000516047224 */
/* 0x020fe400078e0204 */
/*03b0*/ LDS R25, [R0.X4+0x680] ; /* 0x0006800000197984 */
/* 0x000ee40000004800 */
/*03c0*/ IMAD R4, R27, R6, R4 ; /* 0x000000061b047224 */
/* 0x000fc400078e0204 */
/*03d0*/ LDS R22, [R0.X4+0x6c0] ; /* 0x0006c00000167984 */
/* 0x000f280000004800 */
/*03e0*/ LDS R27, [R0.X4+0x700] ; /* 0x00070000001b7984 */
/* 0x000fe20000004800 */
/*03f0*/ IMAD R24, R24, R7, R4 ; /* 0x0000000718187224 */
/* 0x001fc600078e0204 */
/*0400*/ LDS.128 R4, [R15+0x30] ; /* 0x000030000f047984 */
/* 0x000e220000000c00 */
/*0410*/ IMAD R24, R23, R8, R24 ; /* 0x0000000817187224 */
/* 0x002fc600078e0218 */
/*0420*/ LDS R8, [R0.X4+0x740] ; /* 0x0007400000087984 */
/* 0x000e680000004800 */
/*0430*/ LDS R23, [R0.X4+0x780] ; /* 0x0007800000177984 */
/* 0x000f620000004800 */
/*0440*/ IMAD R9, R20, R9, R24 ; /* 0x0000000914097224 */
/* 0x004fc600078e0218 */
/*0450*/ LDS R20, [R0.X4+0x7c0] ; /* 0x0007c00000147984 */
/* 0x000ea20000004800 */
/*0460*/ IMAD R9, R25, R10, R9 ; /* 0x0000000a19097224 */
/* 0x008fc800078e0209 */
/*0470*/ IMAD R9, R22, R11, R9 ; /* 0x0000000b16097224 */
/* 0x010fc800078e0209 */
/*0480*/ IMAD R4, R27, R4, R9 ; /* 0x000000041b047224 */
/* 0x001fc800078e0209 */
/*0490*/ IMAD R4, R8, R5, R4 ; /* 0x0000000508047224 */
/* 0x002fc800078e0204 */
/*04a0*/ IMAD R23, R23, R6, R4 ; /* 0x0000000617177224 */
/* 0x020fc800078e0204 */
/*04b0*/ IMAD R23, R20, R7, R23 ; /* 0x0000000714177224 */
/* 0x004fe200078e0217 */
/*04c0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*04d0*/ @!P0 BRA 0x1e0 ; /* 0xfffffd0000008947 */
/* 0x000fea000383ffff */
/*04e0*/ STG.E [R2.64], R23 ; /* 0x0000001702007986 */
/* 0x000fe2000c101904 */
/*04f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0500*/ BRA 0x500; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0510*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0520*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0530*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0540*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0550*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0560*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0570*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0580*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0590*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3MulPiS_S_ii
.globl _Z3MulPiS_S_ii
.p2align 8
.type _Z3MulPiS_S_ii,@function
_Z3MulPiS_S_ii:
s_load_b64 s[2:3], s[0:1], 0x18
v_and_b32_e32 v1, 0x3ff, v0
v_bfe_u32 v5, v0, 10, 10
v_mov_b32_e32 v0, 0
s_lshl_b32 s8, s14, 4
s_waitcnt lgkmcnt(0)
s_mul_i32 s4, s2, s15
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_lshl_b32 s9, s4, 4
s_add_i32 s10, s2, s9
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s10, s10, -1
s_cmp_ge_i32 s9, s10
s_cbranch_scc1 .LBB0_5
s_load_b128 s[4:7], s[0:1], 0x0
v_mad_u64_u32 v[2:3], null, v5, s2, v[1:2]
v_lshlrev_b32_e32 v0, 2, v1
v_lshlrev_b32_e32 v6, 6, v5
s_lshl_b32 s2, s3, 4
s_mov_b32 s11, s8
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_nc_u32_e32 v7, 0x400, v0
v_mad_u64_u32 v[3:4], null, v5, s3, v[1:2]
v_add_nc_u32_e32 v4, v6, v0
v_mov_b32_e32 v0, 0
s_delay_alu instid0(VALU_DEP_4)
v_add_nc_u32_e32 v8, v7, v6
s_set_inst_prefetch_distance 0x1
.p2align 6
.LBB0_2:
v_add_nc_u32_e32 v9, s9, v2
v_add_nc_u32_e32 v11, s11, v3
s_mov_b32 s12, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v10, 31, v9
v_ashrrev_i32_e32 v12, 31, v11
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[9:10], 2, v[9:10]
v_lshlrev_b64 v[11:12], 2, v[11:12]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v9, vcc_lo, s4, v9
v_add_co_ci_u32_e32 v10, vcc_lo, s5, v10, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v11, vcc_lo, s6, v11
v_add_co_ci_u32_e32 v12, vcc_lo, s7, v12, vcc_lo
global_load_b32 v10, v[9:10], off
global_load_b32 v11, v[11:12], off
v_mov_b32_e32 v9, v7
s_waitcnt vmcnt(1)
ds_store_b32 v4, v10
s_waitcnt vmcnt(0)
ds_store_b32 v8, v11
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
.LBB0_3:
v_add_nc_u32_e32 v10, s12, v6
s_add_i32 s12, s12, 4
ds_load_b32 v12, v9
ds_load_b32 v13, v10
s_cmp_eq_u32 s12, 64
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[10:11], null, v12, v13, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_dual_mov_b32 v0, v10 :: v_dual_add_nc_u32 v9, 64, v9
s_cbranch_scc0 .LBB0_3
s_add_i32 s9, s9, 16
s_add_i32 s11, s11, s2
s_cmp_ge_i32 s9, s10
s_barrier
buffer_gl0_inv
s_cbranch_scc0 .LBB0_2
.LBB0_5:
s_set_inst_prefetch_distance 0x2
v_lshl_add_u32 v2, s15, 4, v5
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v2, v2, s3
v_add3_u32 v1, s8, v1, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v1, vcc_lo, s0, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
global_store_b32 v[1:2], v0, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3MulPiS_S_ii
.amdhsa_group_segment_fixed_size 2048
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 32
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 14
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3MulPiS_S_ii, .Lfunc_end0-_Z3MulPiS_S_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 2048
.kernarg_segment_align: 8
.kernarg_segment_size: 32
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3MulPiS_S_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z3MulPiS_S_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 14
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00090e1d_00000000-6_matrix_mul.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z28__device_stub__Z3MulPiS_S_iiPiS_S_ii
.type _Z28__device_stub__Z3MulPiS_S_iiPiS_S_ii, @function
_Z28__device_stub__Z3MulPiS_S_iiPiS_S_ii:
.LFB2082:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3MulPiS_S_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z28__device_stub__Z3MulPiS_S_iiPiS_S_ii, .-_Z28__device_stub__Z3MulPiS_S_iiPiS_S_ii
.globl _Z3MulPiS_S_ii
.type _Z3MulPiS_S_ii, @function
_Z3MulPiS_S_ii:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z28__device_stub__Z3MulPiS_S_iiPiS_S_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z3MulPiS_S_ii, .-_Z3MulPiS_S_ii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%d "
.LC1:
.string "\n"
.LC2:
.string "Press Enter to stop\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $88, %rsp
.cfi_def_cfa_offset 144
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $4096, %edi
call malloc@PLT
movq %rax, %r15
movl $4096, %edi
call malloc@PLT
movq %rax, %r14
movl $4096, %edi
call malloc@PLT
movq %rax, %r13
movl $0, %eax
.L12:
movl $1, (%r15,%rax)
movl $1, (%r14,%rax)
movl $0, 0(%r13,%rax)
addq $4, %rax
cmpq $4096, %rax
jne .L12
leaq 24(%rsp), %rdi
movl $4096, %esi
call cudaMalloc@PLT
leaq 32(%rsp), %rdi
movl $4096, %esi
call cudaMalloc@PLT
leaq 40(%rsp), %rdi
movl $4096, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $4096, %edx
movq %r15, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $4096, %edx
movq %r14, %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
movl $16, 48(%rsp)
movl $16, 52(%rsp)
movl $2, 60(%rsp)
movl $2, 64(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 48(%rsp), %rdx
movl $1, %ecx
movq 60(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L21
.L13:
movl $2, %ecx
movl $4096, %edx
movq 40(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
leaq 128(%r13), %rbp
leaq 4224(%r13), %rax
movq %rax, 8(%rsp)
leaq .LC0(%rip), %r12
.L14:
leaq -128(%rbp), %rbx
.L15:
movl (%rbx), %edx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %rbp, %rbx
jne .L15
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
subq $-128, %rbp
movq 8(%rsp), %rax
cmpq %rax, %rbp
jne .L14
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq stdin(%rip), %rdi
call getc@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq %r15, %rdi
call free@PLT
movq %r14, %rdi
call free@PLT
movq %r13, %rdi
call free@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L22
movl $0, %eax
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L21:
.cfi_restore_state
movl $32, %r8d
movl $32, %ecx
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z28__device_stub__Z3MulPiS_S_iiPiS_S_ii
jmp .L13
.L22:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC3:
.string "_Z3MulPiS_S_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z3MulPiS_S_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "matrix_mul.hip"
.globl _Z18__device_stub__MulPiS_S_ii # -- Begin function _Z18__device_stub__MulPiS_S_ii
.p2align 4, 0x90
.type _Z18__device_stub__MulPiS_S_ii,@function
_Z18__device_stub__MulPiS_S_ii: # @_Z18__device_stub__MulPiS_S_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3MulPiS_S_ii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z18__device_stub__MulPiS_S_ii, .Lfunc_end0-_Z18__device_stub__MulPiS_S_ii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $152, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $4096, %edi # imm = 0x1000
callq malloc
movq %rax, %rbx
movl $4096, %edi # imm = 0x1000
callq malloc
movq %rax, %r14
movl $4096, %edi # imm = 0x1000
callq malloc
movq %rax, %r15
xorl %r12d, %r12d
movl $4096, %edx # imm = 0x1000
movq %rax, %rdi
xorl %esi, %esi
callq memset@PLT
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movl $1, (%rbx,%r12,4)
movl $1, (%r14,%r12,4)
incq %r12
cmpq $1024, %r12 # imm = 0x400
jne .LBB1_1
# %bb.2:
leaq 24(%rsp), %rdi
movl $4096, %esi # imm = 0x1000
callq hipMalloc
leaq 16(%rsp), %rdi
movl $4096, %esi # imm = 0x1000
callq hipMalloc
leaq 8(%rsp), %rdi
movl $4096, %esi # imm = 0x1000
callq hipMalloc
movq 24(%rsp), %rdi
movl $4096, %edx # imm = 0x1000
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
movl $4096, %edx # imm = 0x1000
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $8589934594, %rdi # imm = 0x200000002
movabsq $68719476752, %rdx # imm = 0x1000000010
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
movl $32, 36(%rsp)
movl $32, 32(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 36(%rsp), %rax
movq %rax, 136(%rsp)
leaq 32(%rsp), %rax
movq %rax, 144(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z3MulPiS_S_ii, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
movq 8(%rsp), %rsi
movl $4096, %edx # imm = 0x1000
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
movq %r15, %r12
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB1_5: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_6 Depth 2
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB1_6: # Parent Loop BB1_5 Depth=1
# => This Inner Loop Header: Depth=2
movl (%r12,%rbp,4), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
incq %rbp
cmpq $32, %rbp
jne .LBB1_6
# %bb.7: # in Loop: Header=BB1_5 Depth=1
movl $10, %edi
callq putchar@PLT
incq %r13
subq $-128, %r12
cmpq $32, %r13
jne .LBB1_5
# %bb.8:
movl $.Lstr, %edi
callq puts@PLT
movq stdin(%rip), %rdi
callq getc
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
xorl %eax, %eax
addq $152, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3MulPiS_S_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3MulPiS_S_ii,@object # @_Z3MulPiS_S_ii
.section .rodata,"a",@progbits
.globl _Z3MulPiS_S_ii
.p2align 3, 0x0
_Z3MulPiS_S_ii:
.quad _Z18__device_stub__MulPiS_S_ii
.size _Z3MulPiS_S_ii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%d "
.size .L.str, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z3MulPiS_S_ii"
.size .L__unnamed_1, 15
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Press Enter to stop"
.size .Lstr, 20
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__MulPiS_S_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3MulPiS_S_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <stdlib.h>
#include <cuda.h>
#include <time.h>
//************variables globales***************
int msk=3, dimx=1040, dimy=1388, tam_imag=1388*1040;
// [i][j] = i*dimy+j
//************** Kernel CUDA *********************
__global__ void Varianza (int *G_d, float *var_d){
int idx = threadIdx.x + blockIdx.x*blockDim.x;
int idy = threadIdx.y + blockIdx.y*blockDim.y;
int id = idx + idy*blockDim.x*gridDim.x;
int M_d[9], i, dimx=1040, dimy=1388, tam_imag=1388*1040, msk=3;
float X=0.f,Xprom=0.f,Y=0.f;
var_d[id]=0;
//printf("prueba\n");
if(id<tam_imag){
//M_d[0]=((i<1 || j<1) ? 0:A[i-1][j-1]);
/*
M_d[0]=((idx<1 || idy<1) ? 0:G_d[(idx-1)+(idy-1)*blockDim.x*gridDim.x]);
M_d[1]=((idx<1) ? 0:G_d[(idx-1)+(idy)*blockDim.x*gridDim.x]);
M_d[2]=((idx<1 || idy>dimy-2) ? 0:G_d[(idx-1)+(idy+1)*blockDim.x*gridDim.x]);
M_d[3]=((idy<1) ? 0:G_d[(idx)+(idy-1)*blockDim.x*gridDim.x]);
M_d[4]=G_d[(idx)+(idy)*blockDim.x*gridDim.x];
M_d[5]=((idy>dimy-2) ? 0:G_d[(idx)+(idy+1)*blockDim.x*gridDim.x]);
M_d[6]=((idx>dimx-2 || idy<1) ? 0:G_d[(idx+1)+(idy-1)*blockDim.x*gridDim.x]);
M_d[7]=((idx>dimx-2) ? 0:G_d[(idx+1)+(idy)*blockDim.x*gridDim.x]);
M_d[8]=((idx>dimx-2 || idy>dimy-1) ? 0:G_d[(idx+1)+(idy+1)*blockDim.x*gridDim.x]);
*/
if (idx==0 || idy==0){
M_d[0]=0;
}else{
M_d[0]=G_d[id-1-dimy];
}
/*
if ((idx==0)){
M_d[1]=0;
}else{
M_d[1]=G_d[id-dimy];
//M_d[1]=8;
}
/*
if (idx==0 || idy==dimy){
M_d[2]=0;
}else{
M_d[2]=G_d[id+1-dimy];
}
*/
if (idy==0){
M_d[3]=0;
}else{
M_d[3]=G_d[id-1];
}
M_d[4]=G_d[id];
if (idy==dimy){
M_d[5]=0;
}else{
M_d[5]=G_d[id+1];
}
/*
if (id==dimx || idy==0){
M_d[6]=0;
}else{
M_d[6]=G_d[id-1+dimy];
}
*//*
if (idx==dimx){
M_d[7]=0;
}else{
M_d[7]=G_d[id+dimy];
}
*//*
if (idx==dimx || idy==dimy){
M_d[8]=0;
}else{
M_d[8]=G_d[id+1+dimy];
}
*/
//M_d[0]=1;
M_d[1]=5;
M_d[2]=8;
//M_d[3]=1;
//M_d[4]=1;
//M_d[5]=1;
M_d[6]=2;
M_d[7]=5;
M_d[8]=4;
for(i=0;i<msk*msk;i++)
X+=M_d[i];
Xprom=((float)X)/(msk*msk);
for(i=0;i<msk*msk;i++)
Y+=(Xprom-M_d[i])*(Xprom-M_d[i]);
var_d[id]=Y/(msk*msk);
}
}
//*****************Funcion main**********************
int main(int argc,char* argv[]){
//***************Declaracion de variables**************
int i,j,init,fin,d;
init=atoi(argv[1]);
fin=atoi(argv[2]);
//init=1;
//fin=328;
FILE *matrizR, *matrizG, *matrizB;
float t;
clock_t tinicio, t_GPU;
tinicio=clock();
int *topof_h, *R_h, *G_h, *B_h, *Rf_h, *Gf_h, *Bf_h;
float *max_h, *var_h;
int *topof_d, *R_d, *G_d, *B_d, *Rf_d, *Gf_d, *Bf_d;
float *max_d, *var_d;
//************Inicializacion de variables en el host y en el device ***************
/* // Declaracion tipo MATRIZ
max_h=(float **)malloc(sizeof(float)*dimx);
topof_h=(int **)malloc(sizeof(int)*dimx);
R_h=(int **)malloc(sizeof(int)*dimx);
G_h=(int **)malloc(sizeof(int)*dimx);
B_h=(int **)malloc(sizeof(int)*dimx);
Rf_h=(int **)malloc(sizeof(int)*dimx);
Gf_h=(int **)malloc(sizeof(int)*dimx);
Bf_h=(int **)malloc(sizeof(int)*dimx);
for(i=0;i<dimx;i++){
max_h[i]=(float*)malloc(sizeof(float)*dimy);
topof_h[i]=(int*)malloc(sizeof(int)*dimy);
R_h[i]=(int*)malloc(sizeof(int)*dimy);
G_h[i]=(int*)malloc(sizeof(int)*dimy);
B_h[i]=(int*)malloc(sizeof(int)*dimy);
Rf_h[i]=(int*)malloc(sizeof(int)*dimy);
Gf_h[i]=(int*)malloc(sizeof(int)*dimy);
Bf_h[i]=(int*)malloc(sizeof(int)*dimy);
}
var_h=(float *)malloc(sizeof(float)*tam_imag);
*/
R_h=(int *)malloc(sizeof(int)*tam_imag);
cudaMalloc((void**)&R_d, tam_imag*sizeof(int));
G_h=(int *)malloc(sizeof(int)*tam_imag);
cudaMalloc((void**)&G_d, tam_imag*sizeof(int));
B_h=(int *)malloc(sizeof(int)*tam_imag);
cudaMalloc((void**)&B_d, tam_imag*sizeof(int));
Rf_h=(int *)malloc(sizeof(int)*tam_imag);
cudaMalloc((void**)&Rf_d, tam_imag*sizeof(int));
Gf_h=(int *)malloc(sizeof(int)*tam_imag);
cudaMalloc((void**)&Gf_d, tam_imag*sizeof(int));
Bf_h=(int *)malloc(sizeof(int)*tam_imag);
cudaMalloc((void**)&Bf_d, tam_imag*sizeof(int));
topof_h=(int *)malloc(sizeof(int)*tam_imag);
cudaMalloc((void**)&topof_d, tam_imag*sizeof(int));
max_h=(float *)malloc(sizeof(float)*tam_imag);
cudaMalloc((void**)&max_d, tam_imag*sizeof(float));
var_h=(float *)malloc(sizeof(float)*tam_imag);
cudaMalloc((void**)&var_d,tam_imag*sizeof(float));
//*************** For cálculo EDF ****************
for(d=init;d<=fin;d++){
printf("d=%d \n", d);
//*****************Lecura de matrices RGB en el host****************
char rutaR[]="";
sprintf(rutaR, "%s%d%s","RGB/",d,"/R");
matrizR=fopen(rutaR,"r+");
char rutaG[]="";
sprintf(rutaG, "%s%d%s","RGB/",d,"/G");
matrizG=fopen(rutaG,"r+");
char rutaB[]="";
sprintf(rutaB, "%s%d%s","RGB/",d,"/B");
matrizB=fopen(rutaB,"r+");
for(i=0;i<dimx;i++){
for(j=0;j<dimy;j++){
fscanf(matrizR, "%d", &R_h[i*dimy+j]);
fscanf(matrizG, "%d", &G_h[i*dimy+j]);
fscanf(matrizB, "%d", &B_h[i*dimy+j]);
}
}
fclose(matrizR);
fclose(matrizG);
fclose(matrizB);
//***************** Kernel Varianza *******************
cudaMemcpy(G_d,G_h,sizeof(int)*tam_imag,cudaMemcpyHostToDevice);
dim3 Grid(347,20);
dim3 Block(13,16);
Varianza<<<Grid,Block>>>(B_d,var_d);
printf("Despues de kernel \n");
cudaMemcpy(var_h,var_d,sizeof(float)*tam_imag,cudaMemcpyDeviceToHost);
printf("Despues de resultado a host \n");
//***************** Kernel Varianza *******************
/*
cudaMemcpy(R_d,R_h,sizeof(int)*tam_imag,cudaMemcpyHostToDevice);
cudaMemcpy(G_d,G_h,sizeof(int)*tam_imag,cudaMemcpyHostToDevice);
cudaMemcpy(B_d,B_h,sizeof(int)*tam_imag,cudaMemcpyHostToDevice);
cudaMemcpy(Rf_d,Rf_h,sizeof(int)*tam_imag,cudaMemcpyHostToDevice);
cudaMemcpy(Gf_d,Gf_h,sizeof(int)*tam_imag,cudaMemcpyHostToDevice);
cudaMemcpy(Bf_d,Bf_h,sizeof(int)*tam_imag,cudaMemcpyHostToDevice);
cudaMemcpy(topof_d,topof_h,sizeof(int)*tam_imag,cudaMemcpyHostToDevice);
cudaMemcpy(max_d,max_h,sizeof(float)*tam_imag,cudaMemcpyHostToDevice);
cudaMemcpy(var_d,var_h,sizeof(float)*tam_imag,cudaMemcpyHostToDevice);
dim3 Grid(347,20);
dim3 Block(13,16);
TopoRGB<<<Grid,Block>>>(R_d,G_d,B_d,Rf_d,Gf_d,Bf_d,topof_d,max_d,var_d);
cudaMemcpy(Rf_h,Rf_d,sizeof(int)*tam_imag,cudaMemcpyDeviceToHost);
cudaMemcpy(Gf_h,Gf_d,sizeof(int)*tam_imag,cudaMemcpyDeviceToHost);
cudaMemcpy(Bf_h,Bf_d,sizeof(int)*tam_imag,cudaMemcpyDeviceToHost);
cudaMemcpy(topof_h,topof_d,sizeof(int)*tam_imag,cudaMemcpyDeviceToHost);
cudaMemcpy(max_h,max_d,sizeof(float)*tam_imag,cudaMemcpyDeviceToHost);
*/
//*********************Calculo de TODO ********************
} //Finaliza For cálculo EDF
printf("***Sale del for \n");
/*
// ***************** Generacion de archivos de resultados ************************
FILE *archTopo, *archR, *archG, *archB;
archTopo=fopen("Resultados/topos10","w+");
archR=fopen("Resultados/R10","w+");
archG=fopen("Resultados/G10","w+");
archB=fopen("Resultados/B10","w+");
for(i=0;i<dimx;i++){
for(j=0;j<dimy;j++){
fprintf(archTopo,"%d ",topof_h[i*dimy+j]);
fprintf(archR,"%d ",Rf_h[i*dimy+j]);
fprintf(archG,"%d ",Gf_h[i*dimy+j]);
fprintf(archB,"%d ",Bf_h[i*dimy+j]);
}
fprintf(archTopo,"\n");
fprintf(archR,"\n");
fprintf(archG,"\n");
fprintf(archB,"\n");
}
fclose(archTopo);
fclose(archR);
fclose(archG);
fclose(archB);
*/
//***************** Archivo de varianza final
FILE *archVar;
archVar=fopen("Resultados/VarUltima","w+");
for(i=0;i<dimx;i++){
for(j=0;j<dimy;j++){
fprintf(archVar,"%f ",var_h[i*dimy+j]);
}
fprintf(archVar,"\n");
}
fclose(archVar);
free(var_h);
free(max_h);
free(topof_h);
free(R_h);
free(G_h);
free(B_h);
free(Rf_h);
free(Gf_h);
free(Bf_h);
cudaFree(var_d);
cudaFree(max_d);
cudaFree(topof_d);
cudaFree(R_d);
cudaFree(G_d);
cudaFree(B_d);
cudaFree(Rf_d);
cudaFree(Gf_d);
cudaFree(Bf_d);
t_GPU=clock();
t = ((float)t_GPU-(float)tinicio)/CLOCKS_PER_SEC;
printf("\ntiempo de procesamiento de varianzas: %6.3fs\n",t);
//getchar ();
return 0;
}//FIN funcion main() | code for sm_80
Function : _Z8VarianzaPiPf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ ULDC UR4, c[0x0][0xc] ; /* 0x0000030000047ab9 */
/* 0x000fe40000000800 */
/*0030*/ ULDC UR5, c[0x0][0x0] ; /* 0x0000000000057ab9 */
/* 0x000fe20000000800 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e220000002100 */
/*0050*/ UIMAD UR4, UR4, UR5, URZ ; /* 0x00000005040472a4 */
/* 0x000fc6000f8e023f */
/*0060*/ S2R R5, SR_CTAID.Y ; /* 0x0000000000057919 */
/* 0x000e680000002600 */
/*0070*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e620000002200 */
/*0080*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fe400078e0203 */
/*0090*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fe400078e00ff */
/*00a0*/ IMAD R5, R5, c[0x0][0x4], R2 ; /* 0x0000010005057a24 */
/* 0x002fc800078e0202 */
/*00b0*/ IMAD R4, R5, UR4, R0 ; /* 0x0000000405047c24 */
/* 0x000fe2000f8e0200 */
/*00c0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*00d0*/ IMAD.WIDE R2, R4.reuse, R3, c[0x0][0x168] ; /* 0x00005a0004027625 */
/* 0x040fe200078e0203 */
/*00e0*/ ISETP.GT.AND P0, PT, R4, 0x1606bf, PT ; /* 0x001606bf0400780c */
/* 0x000fc80003f04270 */
/*00f0*/ STG.E [R2.64], RZ ; /* 0x000000ff02007986 */
/* 0x0001f2000c101904 */
/*0100*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0110*/ ISETP.NE.AND P1, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe40003f25270 */
/*0120*/ SHF.R.S32.HI R7, RZ, 0x1f, R4 ; /* 0x0000001fff077819 */
/* 0x000fc40000011404 */
/*0130*/ ISETP.EQ.OR P0, PT, R0, RZ, !P1 ; /* 0x000000ff0000720c */
/* 0x000fe40004f02670 */
/*0140*/ LEA R8, P2, R4, c[0x0][0x160], 0x2 ; /* 0x0000580004087a11 */
/* 0x000fc800078410ff */
/*0150*/ LEA.HI.X R9, R4, c[0x0][0x164], R7, 0x2, P2 ; /* 0x0000590004097a11 */
/* 0x000fe400010f1407 */
/*0160*/ ISETP.NE.AND P2, PT, R5, 0x56c, PT ; /* 0x0000056c0500780c */
/* 0x000fc60003f45270 */
/*0170*/ @P1 LDG.E R10, [R8.64+-0x4] ; /* 0xfffffc04080a1981 */
/* 0x000ea8000c1e1900 */
/*0180*/ @!P0 LDG.E R7, [R8.64+-0x15b4] ; /* 0xffea4c0408078981 */
/* 0x000ee8000c1e1900 */
/*0190*/ LDG.E R5, [R8.64] ; /* 0x0000000408057981 */
/* 0x000f28000c1e1900 */
/*01a0*/ @P2 LDG.E R11, [R8.64+0x4] ; /* 0x00000404080b2981 */
/* 0x000f62000c1e1900 */
/*01b0*/ IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff067224 */
/* 0x000fe200078e00ff */
/*01c0*/ HFMA2.MMA R0, -RZ, RZ, 0, 0 ; /* 0x00000000ff007435 */
/* 0x000fe200000001ff */
/*01d0*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x000fe200078e00ff */
/*01e0*/ BSSY B0, 0x380 ; /* 0x0000019000007945 */
/* 0x000fe60003800000 */
/*01f0*/ @!P0 I2F R6, R7 ; /* 0x0000000700068306 */
/* 0x008e700000201400 */
/*0200*/ @P1 I2F R0, R10 ; /* 0x0000000a00001306 */
/* 0x004eb00000201400 */
/*0210*/ I2F R5, R5 ; /* 0x0000000500057306 */
/* 0x010ee20000201400 */
/*0220*/ FADD R12, R6, 5 ; /* 0x40a00000060c7421 */
/* 0x002fce0000000000 */
/*0230*/ @P2 I2F R4, R11 ; /* 0x0000000b00042306 */
/* 0x020e620000201400 */
/*0240*/ FADD R13, R12, 8 ; /* 0x410000000c0d7421 */
/* 0x000fc80000000000 */
/*0250*/ FADD R12, R13, R0 ; /* 0x000000000d0c7221 */
/* 0x004fc80000000000 */
/*0260*/ FADD R9, R12, R5 ; /* 0x000000050c097221 */
/* 0x008fc80000000000 */
/*0270*/ FADD R9, R9, R4 ; /* 0x0000000409097221 */
/* 0x002fc80000000000 */
/*0280*/ FADD R9, R9, 2 ; /* 0x4000000009097421 */
/* 0x000fc80000000000 */
/*0290*/ FADD R9, R9, 5 ; /* 0x40a0000009097421 */
/* 0x000fe20000000000 */
/*02a0*/ MOV R7, 0x41100000 ; /* 0x4110000000077802 */
/* 0x000fe20000000f00 */
/*02b0*/ IMAD.MOV.U32 R12, RZ, RZ, 0x3de38e39 ; /* 0x3de38e39ff0c7424 */
/* 0x000fe400078e00ff */
/*02c0*/ FADD R11, R9, 4 ; /* 0x40800000090b7421 */
/* 0x000fe40000000000 */
/*02d0*/ FFMA R8, R12, -R7, 1 ; /* 0x3f8000000c087423 */
/* 0x000fe40000000807 */
/*02e0*/ FCHK P0, R11, 9 ; /* 0x411000000b007902 */
/* 0x000e640000000000 */
/*02f0*/ FFMA R8, R8, R12, 0.11111111193895339966 ; /* 0x3de38e3908087423 */
/* 0x000fc8000000000c */
/*0300*/ FFMA R9, R11, R8, RZ ; /* 0x000000080b097223 */
/* 0x000fc800000000ff */
/*0310*/ FFMA R10, R9, -9, R11 ; /* 0xc1100000090a7823 */
/* 0x000fc8000000000b */
/*0320*/ FFMA R9, R8, R10, R9 ; /* 0x0000000a08097223 */
/* 0x000fe20000000009 */
/*0330*/ @!P0 BRA 0x370 ; /* 0x0000003000008947 */
/* 0x002fea0003800000 */
/*0340*/ MOV R8, 0x360 ; /* 0x0000036000087802 */
/* 0x000fe40000000f00 */
/*0350*/ CALL.REL.NOINC 0x590 ; /* 0x0000023000007944 */
/* 0x001fea0003c00000 */
/*0360*/ IMAD.MOV.U32 R9, RZ, RZ, R7 ; /* 0x000000ffff097224 */
/* 0x001fe400078e0007 */
/*0370*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0380*/ FADD R6, R9.reuse, -R6 ; /* 0x8000000609067221 */
/* 0x040fe20000000000 */
/*0390*/ BSSY B0, 0x570 ; /* 0x000001d000007945 */
/* 0x000fe20003800000 */
/*03a0*/ FADD R11, R9.reuse, -5 ; /* 0xc0a00000090b7421 */
/* 0x040fe40000000000 */
/*03b0*/ FFMA R6, R6, R6, RZ ; /* 0x0000000606067223 */
/* 0x000fe400000000ff */
/*03c0*/ FADD R7, R9, -8 ; /* 0xc100000009077421 */
/* 0x000fe40000000000 */
/*03d0*/ FFMA R6, R11, R11, R6 ; /* 0x0000000b0b067223 */
/* 0x000fe40000000006 */
/*03e0*/ FADD R13, R9, -R0 ; /* 0x80000000090d7221 */
/* 0x000fc40000000000 */
/*03f0*/ FFMA R6, R7, R7, R6 ; /* 0x0000000707067223 */
/* 0x000fe40000000006 */
/*0400*/ FADD R5, -R5, R9 ; /* 0x0000000905057221 */
/* 0x000fe40000000100 */
/*0410*/ FFMA R6, R13, R13, R6 ; /* 0x0000000d0d067223 */
/* 0x000fe40000000006 */
/*0420*/ FADD R7, R9, -R4 ; /* 0x8000000409077221 */
/* 0x000fe40000000000 */
/*0430*/ FFMA R6, R5, R5, R6 ; /* 0x0000000505067223 */
/* 0x000fe40000000006 */
/*0440*/ FADD R5, R9, -2 ; /* 0xc000000009057421 */
/* 0x000fc40000000000 */
/*0450*/ FFMA R6, R7, R7, R6 ; /* 0x0000000707067223 */
/* 0x000fe20000000006 */
/*0460*/ HFMA2.MMA R7, -RZ, RZ, 2.53125, 0 ; /* 0x41100000ff077435 */
/* 0x000fe200000001ff */
/*0470*/ FADD R9, R9, -4 ; /* 0xc080000009097421 */
/* 0x000fe40000000000 */
/*0480*/ FFMA R6, R5, R5, R6 ; /* 0x0000000505067223 */
/* 0x000fe40000000006 */
/*0490*/ IMAD.MOV.U32 R0, RZ, RZ, 0x3de38e39 ; /* 0x3de38e39ff007424 */
/* 0x000fe400078e00ff */
/*04a0*/ FFMA R6, R11, R11, R6 ; /* 0x0000000b0b067223 */
/* 0x000fc60000000006 */
/*04b0*/ FFMA R5, R0, -R7, 1 ; /* 0x3f80000000057423 */
/* 0x000fe40000000807 */
/*04c0*/ FFMA R11, R9, R9, R6 ; /* 0x00000009090b7223 */
/* 0x000fe40000000006 */
/*04d0*/ FFMA R4, R5, R0, 0.11111111193895339966 ; /* 0x3de38e3905047423 */
/* 0x000fe40000000000 */
/*04e0*/ FCHK P0, R11, 9 ; /* 0x411000000b007902 */
/* 0x000e640000000000 */
/*04f0*/ FFMA R0, R4, R11, RZ ; /* 0x0000000b04007223 */
/* 0x000fc800000000ff */
/*0500*/ FFMA R5, R0, -9, R11 ; /* 0xc110000000057823 */
/* 0x000fc8000000000b */
/*0510*/ FFMA R5, R4, R5, R0 ; /* 0x0000000504057223 */
/* 0x000fe20000000000 */
/*0520*/ @!P0 BRA 0x560 ; /* 0x0000003000008947 */
/* 0x002fea0003800000 */
/*0530*/ MOV R8, 0x550 ; /* 0x0000055000087802 */
/* 0x000fe40000000f00 */
/*0540*/ CALL.REL.NOINC 0x590 ; /* 0x0000004000007944 */
/* 0x001fea0003c00000 */
/*0550*/ IMAD.MOV.U32 R5, RZ, RZ, R7 ; /* 0x000000ffff057224 */
/* 0x001fe400078e0007 */
/*0560*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0570*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*0580*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0590*/ SHF.R.U32.HI R10, RZ, 0x17, R7 ; /* 0x00000017ff0a7819 */
/* 0x000fe20000011607 */
/*05a0*/ BSSY B1, 0xbd0 ; /* 0x0000062000017945 */
/* 0x000fe20003800000 */
/*05b0*/ SHF.R.U32.HI R9, RZ, 0x17, R11 ; /* 0x00000017ff097819 */
/* 0x000fe4000001160b */
/*05c0*/ LOP3.LUT R10, R10, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff0a0a7812 */
/* 0x000fe400078ec0ff */
/*05d0*/ LOP3.LUT R15, R9, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff090f7812 */
/* 0x000fe400078ec0ff */
/*05e0*/ IADD3 R12, R10, -0x1, RZ ; /* 0xffffffff0a0c7810 */
/* 0x000fc40007ffe0ff */
/*05f0*/ IADD3 R13, R15, -0x1, RZ ; /* 0xffffffff0f0d7810 */
/* 0x000fe40007ffe0ff */
/*0600*/ ISETP.GT.U32.AND P0, PT, R12, 0xfd, PT ; /* 0x000000fd0c00780c */
/* 0x000fc80003f04070 */
/*0610*/ ISETP.GT.U32.OR P0, PT, R13, 0xfd, P0 ; /* 0x000000fd0d00780c */
/* 0x000fda0000704470 */
/*0620*/ @!P0 IMAD.MOV.U32 R9, RZ, RZ, RZ ; /* 0x000000ffff098224 */
/* 0x000fe200078e00ff */
/*0630*/ @!P0 BRA 0x7b0 ; /* 0x0000017000008947 */
/* 0x000fea0003800000 */
/*0640*/ FSETP.GTU.FTZ.AND P0, PT, |R11|, +INF , PT ; /* 0x7f8000000b00780b */
/* 0x000fe40003f1c200 */
/*0650*/ FSETP.GTU.FTZ.AND P1, PT, |R7|, +INF , PT ; /* 0x7f8000000700780b */
/* 0x000fc80003f3c200 */
/*0660*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000703570 */
/*0670*/ @P0 BRA 0xbb0 ; /* 0x0000053000000947 */
/* 0x000fea0003800000 */
/*0680*/ LOP3.LUT P0, RZ, R7, 0x7fffffff, R11, 0xc8, !PT ; /* 0x7fffffff07ff7812 */
/* 0x000fda000780c80b */
/*0690*/ @!P0 BRA 0xb90 ; /* 0x000004f000008947 */
/* 0x000fea0003800000 */
/*06a0*/ FSETP.NEU.FTZ.AND P2, PT, |R11|, +INF , PT ; /* 0x7f8000000b00780b */
/* 0x000fe40003f5d200 */
/*06b0*/ FSETP.NEU.FTZ.AND P1, PT, |R7|, +INF , PT ; /* 0x7f8000000700780b */
/* 0x000fe40003f3d200 */
/*06c0*/ FSETP.NEU.FTZ.AND P0, PT, |R11|, +INF , PT ; /* 0x7f8000000b00780b */
/* 0x000fd60003f1d200 */
/*06d0*/ @!P1 BRA !P2, 0xb90 ; /* 0x000004b000009947 */
/* 0x000fea0005000000 */
/*06e0*/ LOP3.LUT P2, RZ, R11, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff0bff7812 */
/* 0x000fc8000784c0ff */
/*06f0*/ PLOP3.LUT P1, PT, P1, P2, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000f24572 */
/*0700*/ @P1 BRA 0xb70 ; /* 0x0000046000001947 */
/* 0x000fea0003800000 */
/*0710*/ LOP3.LUT P1, RZ, R7, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff07ff7812 */
/* 0x000fc8000782c0ff */
/*0720*/ PLOP3.LUT P0, PT, P0, P1, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000702572 */
/*0730*/ @P0 BRA 0xb40 ; /* 0x0000040000000947 */
/* 0x000fea0003800000 */
/*0740*/ ISETP.GE.AND P0, PT, R13, RZ, PT ; /* 0x000000ff0d00720c */
/* 0x000fe40003f06270 */
/*0750*/ ISETP.GE.AND P1, PT, R12, RZ, PT ; /* 0x000000ff0c00720c */
/* 0x000fd60003f26270 */
/*0760*/ @P0 MOV R9, RZ ; /* 0x000000ff00090202 */
/* 0x000fe20000000f00 */
/*0770*/ @!P0 IMAD.MOV.U32 R9, RZ, RZ, -0x40 ; /* 0xffffffc0ff098424 */
/* 0x000fe400078e00ff */
/*0780*/ @!P0 FFMA R11, R11, 1.84467440737095516160e+19, RZ ; /* 0x5f8000000b0b8823 */
/* 0x000fe400000000ff */
/*0790*/ @!P1 FFMA R7, R7, 1.84467440737095516160e+19, RZ ; /* 0x5f80000007079823 */
/* 0x000fe200000000ff */
/*07a0*/ @!P1 IADD3 R9, R9, 0x40, RZ ; /* 0x0000004009099810 */
/* 0x000fe40007ffe0ff */
/*07b0*/ LEA R12, R10, 0xc0800000, 0x17 ; /* 0xc08000000a0c7811 */
/* 0x000fe200078eb8ff */
/*07c0*/ BSSY B2, 0xb30 ; /* 0x0000036000027945 */
/* 0x000fe80003800000 */
/*07d0*/ IMAD.IADD R13, R7, 0x1, -R12 ; /* 0x00000001070d7824 */
/* 0x000fe200078e0a0c */
/*07e0*/ IADD3 R12, R15, -0x7f, RZ ; /* 0xffffff810f0c7810 */
/* 0x000fc60007ffe0ff */
/*07f0*/ MUFU.RCP R7, R13 ; /* 0x0000000d00077308 */
/* 0x000e220000001000 */
/*0800*/ FADD.FTZ R14, -R13, -RZ ; /* 0x800000ff0d0e7221 */
/* 0x000fe40000010100 */
/*0810*/ IMAD R11, R12.reuse, -0x800000, R11 ; /* 0xff8000000c0b7824 */
/* 0x040fe200078e020b */
/*0820*/ IADD3 R12, R12, 0x7f, -R10 ; /* 0x0000007f0c0c7810 */
/* 0x000fc80007ffe80a */
/*0830*/ IADD3 R12, R12, R9, RZ ; /* 0x000000090c0c7210 */
/* 0x000fe20007ffe0ff */
/*0840*/ FFMA R16, R7, R14, 1 ; /* 0x3f80000007107423 */
/* 0x001fc8000000000e */
/*0850*/ FFMA R18, R7, R16, R7 ; /* 0x0000001007127223 */
/* 0x000fc80000000007 */
/*0860*/ FFMA R7, R11, R18, RZ ; /* 0x000000120b077223 */
/* 0x000fc800000000ff */
/*0870*/ FFMA R16, R14, R7, R11 ; /* 0x000000070e107223 */
/* 0x000fc8000000000b */
/*0880*/ FFMA R15, R18, R16, R7 ; /* 0x00000010120f7223 */
/* 0x000fc80000000007 */
/*0890*/ FFMA R14, R14, R15, R11 ; /* 0x0000000f0e0e7223 */
/* 0x000fc8000000000b */
/*08a0*/ FFMA R7, R18, R14, R15 ; /* 0x0000000e12077223 */
/* 0x000fca000000000f */
/*08b0*/ SHF.R.U32.HI R10, RZ, 0x17, R7 ; /* 0x00000017ff0a7819 */
/* 0x000fc80000011607 */
/*08c0*/ LOP3.LUT R10, R10, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff0a0a7812 */
/* 0x000fca00078ec0ff */
/*08d0*/ IMAD.IADD R13, R10, 0x1, R12 ; /* 0x000000010a0d7824 */
/* 0x000fca00078e020c */
/*08e0*/ IADD3 R9, R13, -0x1, RZ ; /* 0xffffffff0d097810 */
/* 0x000fc80007ffe0ff */
/*08f0*/ ISETP.GE.U32.AND P0, PT, R9, 0xfe, PT ; /* 0x000000fe0900780c */
/* 0x000fda0003f06070 */
/*0900*/ @!P0 BRA 0xb10 ; /* 0x0000020000008947 */
/* 0x000fea0003800000 */
/*0910*/ ISETP.GT.AND P0, PT, R13, 0xfe, PT ; /* 0x000000fe0d00780c */
/* 0x000fda0003f04270 */
/*0920*/ @P0 BRA 0xae0 ; /* 0x000001b000000947 */
/* 0x000fea0003800000 */
/*0930*/ ISETP.GE.AND P0, PT, R13, 0x1, PT ; /* 0x000000010d00780c */
/* 0x000fda0003f06270 */
/*0940*/ @P0 BRA 0xb20 ; /* 0x000001d000000947 */
/* 0x000fea0003800000 */
/*0950*/ ISETP.GE.AND P0, PT, R13, -0x18, PT ; /* 0xffffffe80d00780c */
/* 0x000fe40003f06270 */
/*0960*/ LOP3.LUT R7, R7, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000007077812 */
/* 0x000fd600078ec0ff */
/*0970*/ @!P0 BRA 0xb20 ; /* 0x000001a000008947 */
/* 0x000fea0003800000 */
/*0980*/ FFMA.RZ R9, R18.reuse, R14.reuse, R15.reuse ; /* 0x0000000e12097223 */
/* 0x1c0fe2000000c00f */
/*0990*/ IADD3 R12, R13.reuse, 0x20, RZ ; /* 0x000000200d0c7810 */
/* 0x040fe20007ffe0ff */
/*09a0*/ FFMA.RM R10, R18.reuse, R14.reuse, R15.reuse ; /* 0x0000000e120a7223 */
/* 0x1c0fe2000000400f */
/*09b0*/ ISETP.NE.AND P2, PT, R13, RZ, PT ; /* 0x000000ff0d00720c */
/* 0x000fe40003f45270 */
/*09c0*/ LOP3.LUT R11, R9, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff090b7812 */
/* 0x000fe200078ec0ff */
/*09d0*/ FFMA.RP R9, R18, R14, R15 ; /* 0x0000000e12097223 */
/* 0x000fe2000000800f */
/*09e0*/ ISETP.NE.AND P1, PT, R13, RZ, PT ; /* 0x000000ff0d00720c */
/* 0x000fe20003f25270 */
/*09f0*/ IMAD.MOV R13, RZ, RZ, -R13 ; /* 0x000000ffff0d7224 */
/* 0x000fe200078e0a0d */
/*0a00*/ LOP3.LUT R11, R11, 0x800000, RZ, 0xfc, !PT ; /* 0x008000000b0b7812 */
/* 0x000fe400078efcff */
/*0a10*/ FSETP.NEU.FTZ.AND P0, PT, R9, R10, PT ; /* 0x0000000a0900720b */
/* 0x000fc40003f1d000 */
/*0a20*/ SHF.L.U32 R12, R11, R12, RZ ; /* 0x0000000c0b0c7219 */
/* 0x000fe400000006ff */
/*0a30*/ SEL R10, R13, RZ, P2 ; /* 0x000000ff0d0a7207 */
/* 0x000fe40001000000 */
/*0a40*/ ISETP.NE.AND P1, PT, R12, RZ, P1 ; /* 0x000000ff0c00720c */
/* 0x000fe40000f25270 */
/*0a50*/ SHF.R.U32.HI R10, RZ, R10, R11 ; /* 0x0000000aff0a7219 */
/* 0x000fe4000001160b */
/*0a60*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40000703570 */
/*0a70*/ SHF.R.U32.HI R12, RZ, 0x1, R10 ; /* 0x00000001ff0c7819 */
/* 0x000fc4000001160a */
/*0a80*/ SEL R9, RZ, 0x1, !P0 ; /* 0x00000001ff097807 */
/* 0x000fc80004000000 */
/*0a90*/ LOP3.LUT R9, R9, 0x1, R12, 0xf8, !PT ; /* 0x0000000109097812 */
/* 0x000fc800078ef80c */
/*0aa0*/ LOP3.LUT R9, R9, R10, RZ, 0xc0, !PT ; /* 0x0000000a09097212 */
/* 0x000fc800078ec0ff */
/*0ab0*/ IADD3 R12, R12, R9, RZ ; /* 0x000000090c0c7210 */
/* 0x000fc80007ffe0ff */
/*0ac0*/ LOP3.LUT R7, R12, R7, RZ, 0xfc, !PT ; /* 0x000000070c077212 */
/* 0x000fe200078efcff */
/*0ad0*/ BRA 0xb20 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*0ae0*/ LOP3.LUT R7, R7, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000007077812 */
/* 0x000fc800078ec0ff */
/*0af0*/ LOP3.LUT R7, R7, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000007077812 */
/* 0x000fe200078efcff */
/*0b00*/ BRA 0xb20 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0b10*/ IMAD R7, R12, 0x800000, R7 ; /* 0x008000000c077824 */
/* 0x000fe400078e0207 */
/*0b20*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*0b30*/ BRA 0xbc0 ; /* 0x0000008000007947 */
/* 0x000fea0003800000 */
/*0b40*/ LOP3.LUT R7, R7, 0x80000000, R11, 0x48, !PT ; /* 0x8000000007077812 */
/* 0x000fc800078e480b */
/*0b50*/ LOP3.LUT R7, R7, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000007077812 */
/* 0x000fe200078efcff */
/*0b60*/ BRA 0xbc0 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*0b70*/ LOP3.LUT R7, R7, 0x80000000, R11, 0x48, !PT ; /* 0x8000000007077812 */
/* 0x000fe200078e480b */
/*0b80*/ BRA 0xbc0 ; /* 0x0000003000007947 */
/* 0x000fea0003800000 */
/*0b90*/ MUFU.RSQ R7, -QNAN ; /* 0xffc0000000077908 */
/* 0x000e220000001400 */
/*0ba0*/ BRA 0xbc0 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0bb0*/ FADD.FTZ R7, R11, R7 ; /* 0x000000070b077221 */
/* 0x000fe40000010000 */
/*0bc0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0bd0*/ HFMA2.MMA R9, -RZ, RZ, 0, 0 ; /* 0x00000000ff097435 */
/* 0x000fcc00000001ff */
/*0be0*/ RET.REL.NODEC R8 0x0 ; /* 0xfffff41008007950 */
/* 0x000fea0003c3ffff */
/*0bf0*/ BRA 0xbf0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0c00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <stdlib.h>
#include <cuda.h>
#include <time.h>
//************variables globales***************
int msk=3, dimx=1040, dimy=1388, tam_imag=1388*1040;
// [i][j] = i*dimy+j
//************** Kernel CUDA *********************
__global__ void Varianza (int *G_d, float *var_d){
int idx = threadIdx.x + blockIdx.x*blockDim.x;
int idy = threadIdx.y + blockIdx.y*blockDim.y;
int id = idx + idy*blockDim.x*gridDim.x;
int M_d[9], i, dimx=1040, dimy=1388, tam_imag=1388*1040, msk=3;
float X=0.f,Xprom=0.f,Y=0.f;
var_d[id]=0;
//printf("prueba\n");
if(id<tam_imag){
//M_d[0]=((i<1 || j<1) ? 0:A[i-1][j-1]);
/*
M_d[0]=((idx<1 || idy<1) ? 0:G_d[(idx-1)+(idy-1)*blockDim.x*gridDim.x]);
M_d[1]=((idx<1) ? 0:G_d[(idx-1)+(idy)*blockDim.x*gridDim.x]);
M_d[2]=((idx<1 || idy>dimy-2) ? 0:G_d[(idx-1)+(idy+1)*blockDim.x*gridDim.x]);
M_d[3]=((idy<1) ? 0:G_d[(idx)+(idy-1)*blockDim.x*gridDim.x]);
M_d[4]=G_d[(idx)+(idy)*blockDim.x*gridDim.x];
M_d[5]=((idy>dimy-2) ? 0:G_d[(idx)+(idy+1)*blockDim.x*gridDim.x]);
M_d[6]=((idx>dimx-2 || idy<1) ? 0:G_d[(idx+1)+(idy-1)*blockDim.x*gridDim.x]);
M_d[7]=((idx>dimx-2) ? 0:G_d[(idx+1)+(idy)*blockDim.x*gridDim.x]);
M_d[8]=((idx>dimx-2 || idy>dimy-1) ? 0:G_d[(idx+1)+(idy+1)*blockDim.x*gridDim.x]);
*/
if (idx==0 || idy==0){
M_d[0]=0;
}else{
M_d[0]=G_d[id-1-dimy];
}
/*
if ((idx==0)){
M_d[1]=0;
}else{
M_d[1]=G_d[id-dimy];
//M_d[1]=8;
}
/*
if (idx==0 || idy==dimy){
M_d[2]=0;
}else{
M_d[2]=G_d[id+1-dimy];
}
*/
if (idy==0){
M_d[3]=0;
}else{
M_d[3]=G_d[id-1];
}
M_d[4]=G_d[id];
if (idy==dimy){
M_d[5]=0;
}else{
M_d[5]=G_d[id+1];
}
/*
if (id==dimx || idy==0){
M_d[6]=0;
}else{
M_d[6]=G_d[id-1+dimy];
}
*//*
if (idx==dimx){
M_d[7]=0;
}else{
M_d[7]=G_d[id+dimy];
}
*//*
if (idx==dimx || idy==dimy){
M_d[8]=0;
}else{
M_d[8]=G_d[id+1+dimy];
}
*/
//M_d[0]=1;
M_d[1]=5;
M_d[2]=8;
//M_d[3]=1;
//M_d[4]=1;
//M_d[5]=1;
M_d[6]=2;
M_d[7]=5;
M_d[8]=4;
for(i=0;i<msk*msk;i++)
X+=M_d[i];
Xprom=((float)X)/(msk*msk);
for(i=0;i<msk*msk;i++)
Y+=(Xprom-M_d[i])*(Xprom-M_d[i]);
var_d[id]=Y/(msk*msk);
}
}
//*****************Funcion main**********************
int main(int argc,char* argv[]){
//***************Declaracion de variables**************
int i,j,init,fin,d;
init=atoi(argv[1]);
fin=atoi(argv[2]);
//init=1;
//fin=328;
FILE *matrizR, *matrizG, *matrizB;
float t;
clock_t tinicio, t_GPU;
tinicio=clock();
int *topof_h, *R_h, *G_h, *B_h, *Rf_h, *Gf_h, *Bf_h;
float *max_h, *var_h;
int *topof_d, *R_d, *G_d, *B_d, *Rf_d, *Gf_d, *Bf_d;
float *max_d, *var_d;
//************Inicializacion de variables en el host y en el device ***************
/* // Declaracion tipo MATRIZ
max_h=(float **)malloc(sizeof(float)*dimx);
topof_h=(int **)malloc(sizeof(int)*dimx);
R_h=(int **)malloc(sizeof(int)*dimx);
G_h=(int **)malloc(sizeof(int)*dimx);
B_h=(int **)malloc(sizeof(int)*dimx);
Rf_h=(int **)malloc(sizeof(int)*dimx);
Gf_h=(int **)malloc(sizeof(int)*dimx);
Bf_h=(int **)malloc(sizeof(int)*dimx);
for(i=0;i<dimx;i++){
max_h[i]=(float*)malloc(sizeof(float)*dimy);
topof_h[i]=(int*)malloc(sizeof(int)*dimy);
R_h[i]=(int*)malloc(sizeof(int)*dimy);
G_h[i]=(int*)malloc(sizeof(int)*dimy);
B_h[i]=(int*)malloc(sizeof(int)*dimy);
Rf_h[i]=(int*)malloc(sizeof(int)*dimy);
Gf_h[i]=(int*)malloc(sizeof(int)*dimy);
Bf_h[i]=(int*)malloc(sizeof(int)*dimy);
}
var_h=(float *)malloc(sizeof(float)*tam_imag);
*/
R_h=(int *)malloc(sizeof(int)*tam_imag);
cudaMalloc((void**)&R_d, tam_imag*sizeof(int));
G_h=(int *)malloc(sizeof(int)*tam_imag);
cudaMalloc((void**)&G_d, tam_imag*sizeof(int));
B_h=(int *)malloc(sizeof(int)*tam_imag);
cudaMalloc((void**)&B_d, tam_imag*sizeof(int));
Rf_h=(int *)malloc(sizeof(int)*tam_imag);
cudaMalloc((void**)&Rf_d, tam_imag*sizeof(int));
Gf_h=(int *)malloc(sizeof(int)*tam_imag);
cudaMalloc((void**)&Gf_d, tam_imag*sizeof(int));
Bf_h=(int *)malloc(sizeof(int)*tam_imag);
cudaMalloc((void**)&Bf_d, tam_imag*sizeof(int));
topof_h=(int *)malloc(sizeof(int)*tam_imag);
cudaMalloc((void**)&topof_d, tam_imag*sizeof(int));
max_h=(float *)malloc(sizeof(float)*tam_imag);
cudaMalloc((void**)&max_d, tam_imag*sizeof(float));
var_h=(float *)malloc(sizeof(float)*tam_imag);
cudaMalloc((void**)&var_d,tam_imag*sizeof(float));
//*************** For cálculo EDF ****************
for(d=init;d<=fin;d++){
printf("d=%d \n", d);
//*****************Lecura de matrices RGB en el host****************
char rutaR[]="";
sprintf(rutaR, "%s%d%s","RGB/",d,"/R");
matrizR=fopen(rutaR,"r+");
char rutaG[]="";
sprintf(rutaG, "%s%d%s","RGB/",d,"/G");
matrizG=fopen(rutaG,"r+");
char rutaB[]="";
sprintf(rutaB, "%s%d%s","RGB/",d,"/B");
matrizB=fopen(rutaB,"r+");
for(i=0;i<dimx;i++){
for(j=0;j<dimy;j++){
fscanf(matrizR, "%d", &R_h[i*dimy+j]);
fscanf(matrizG, "%d", &G_h[i*dimy+j]);
fscanf(matrizB, "%d", &B_h[i*dimy+j]);
}
}
fclose(matrizR);
fclose(matrizG);
fclose(matrizB);
//***************** Kernel Varianza *******************
cudaMemcpy(G_d,G_h,sizeof(int)*tam_imag,cudaMemcpyHostToDevice);
dim3 Grid(347,20);
dim3 Block(13,16);
Varianza<<<Grid,Block>>>(B_d,var_d);
printf("Despues de kernel \n");
cudaMemcpy(var_h,var_d,sizeof(float)*tam_imag,cudaMemcpyDeviceToHost);
printf("Despues de resultado a host \n");
//***************** Kernel Varianza *******************
/*
cudaMemcpy(R_d,R_h,sizeof(int)*tam_imag,cudaMemcpyHostToDevice);
cudaMemcpy(G_d,G_h,sizeof(int)*tam_imag,cudaMemcpyHostToDevice);
cudaMemcpy(B_d,B_h,sizeof(int)*tam_imag,cudaMemcpyHostToDevice);
cudaMemcpy(Rf_d,Rf_h,sizeof(int)*tam_imag,cudaMemcpyHostToDevice);
cudaMemcpy(Gf_d,Gf_h,sizeof(int)*tam_imag,cudaMemcpyHostToDevice);
cudaMemcpy(Bf_d,Bf_h,sizeof(int)*tam_imag,cudaMemcpyHostToDevice);
cudaMemcpy(topof_d,topof_h,sizeof(int)*tam_imag,cudaMemcpyHostToDevice);
cudaMemcpy(max_d,max_h,sizeof(float)*tam_imag,cudaMemcpyHostToDevice);
cudaMemcpy(var_d,var_h,sizeof(float)*tam_imag,cudaMemcpyHostToDevice);
dim3 Grid(347,20);
dim3 Block(13,16);
TopoRGB<<<Grid,Block>>>(R_d,G_d,B_d,Rf_d,Gf_d,Bf_d,topof_d,max_d,var_d);
cudaMemcpy(Rf_h,Rf_d,sizeof(int)*tam_imag,cudaMemcpyDeviceToHost);
cudaMemcpy(Gf_h,Gf_d,sizeof(int)*tam_imag,cudaMemcpyDeviceToHost);
cudaMemcpy(Bf_h,Bf_d,sizeof(int)*tam_imag,cudaMemcpyDeviceToHost);
cudaMemcpy(topof_h,topof_d,sizeof(int)*tam_imag,cudaMemcpyDeviceToHost);
cudaMemcpy(max_h,max_d,sizeof(float)*tam_imag,cudaMemcpyDeviceToHost);
*/
//*********************Calculo de TODO ********************
} //Finaliza For cálculo EDF
printf("***Sale del for \n");
/*
// ***************** Generacion de archivos de resultados ************************
FILE *archTopo, *archR, *archG, *archB;
archTopo=fopen("Resultados/topos10","w+");
archR=fopen("Resultados/R10","w+");
archG=fopen("Resultados/G10","w+");
archB=fopen("Resultados/B10","w+");
for(i=0;i<dimx;i++){
for(j=0;j<dimy;j++){
fprintf(archTopo,"%d ",topof_h[i*dimy+j]);
fprintf(archR,"%d ",Rf_h[i*dimy+j]);
fprintf(archG,"%d ",Gf_h[i*dimy+j]);
fprintf(archB,"%d ",Bf_h[i*dimy+j]);
}
fprintf(archTopo,"\n");
fprintf(archR,"\n");
fprintf(archG,"\n");
fprintf(archB,"\n");
}
fclose(archTopo);
fclose(archR);
fclose(archG);
fclose(archB);
*/
//***************** Archivo de varianza final
FILE *archVar;
archVar=fopen("Resultados/VarUltima","w+");
for(i=0;i<dimx;i++){
for(j=0;j<dimy;j++){
fprintf(archVar,"%f ",var_h[i*dimy+j]);
}
fprintf(archVar,"\n");
}
fclose(archVar);
free(var_h);
free(max_h);
free(topof_h);
free(R_h);
free(G_h);
free(B_h);
free(Rf_h);
free(Gf_h);
free(Bf_h);
cudaFree(var_d);
cudaFree(max_d);
cudaFree(topof_d);
cudaFree(R_d);
cudaFree(G_d);
cudaFree(B_d);
cudaFree(Rf_d);
cudaFree(Gf_d);
cudaFree(Bf_d);
t_GPU=clock();
t = ((float)t_GPU-(float)tinicio)/CLOCKS_PER_SEC;
printf("\ntiempo de procesamiento de varianzas: %6.3fs\n",t);
//getchar ();
return 0;
}//FIN funcion main() | .file "tmpxft_00089181_00000000-6_10_var--topo+RGB-CUDA.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z29__device_stub__Z8VarianzaPiPfPiPf
.type _Z29__device_stub__Z8VarianzaPiPfPiPf, @function
_Z29__device_stub__Z8VarianzaPiPfPiPf:
.LFB2082:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z8VarianzaPiPf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z29__device_stub__Z8VarianzaPiPfPiPf, .-_Z29__device_stub__Z8VarianzaPiPfPiPf
.globl _Z8VarianzaPiPf
.type _Z8VarianzaPiPf, @function
_Z8VarianzaPiPf:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z8VarianzaPiPfPiPf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z8VarianzaPiPf, .-_Z8VarianzaPiPf
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "d=%d \n"
.LC1:
.string "RGB/"
.LC2:
.string "%s%d%s"
.LC3:
.string "/R"
.LC4:
.string "r+"
.LC5:
.string "/G"
.LC6:
.string "/B"
.LC7:
.string "%d"
.LC8:
.string "Despues de kernel \n"
.LC9:
.string "Despues de resultado a host \n"
.LC10:
.string "***Sale del for \n"
.LC11:
.string "w+"
.LC12:
.string "Resultados/VarUltima"
.LC13:
.string "%f "
.LC14:
.string "\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC16:
.string "\ntiempo de procesamiento de varianzas: %6.3fs\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $184, %rsp
.cfi_def_cfa_offset 240
movq %rsi, %rbp
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %rbx
movl %eax, 32(%rsp)
movq 16(%rbp), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %rbp
movl %eax, 52(%rsp)
call clock@PLT
movq %rax, %r13
movslq tam_imag(%rip), %r12
salq $2, %r12
movq %r12, %rdi
call malloc@PLT
movq %rax, 16(%rsp)
leaq 72(%rsp), %rdi
movq %r12, %rsi
call cudaMalloc@PLT
movslq tam_imag(%rip), %r12
salq $2, %r12
movq %r12, %rdi
call malloc@PLT
movq %rax, 8(%rsp)
leaq 80(%rsp), %rdi
movq %r12, %rsi
call cudaMalloc@PLT
movslq tam_imag(%rip), %r12
salq $2, %r12
movq %r12, %rdi
call malloc@PLT
movq %rax, 24(%rsp)
leaq 88(%rsp), %rdi
movq %r12, %rsi
call cudaMalloc@PLT
movslq tam_imag(%rip), %rsi
salq $2, %rsi
leaq 96(%rsp), %rdi
call cudaMalloc@PLT
movslq tam_imag(%rip), %rsi
salq $2, %rsi
leaq 104(%rsp), %rdi
call cudaMalloc@PLT
movslq tam_imag(%rip), %rsi
salq $2, %rsi
leaq 112(%rsp), %rdi
call cudaMalloc@PLT
movslq tam_imag(%rip), %rsi
salq $2, %rsi
leaq 64(%rsp), %rdi
call cudaMalloc@PLT
movslq tam_imag(%rip), %rsi
salq $2, %rsi
leaq 120(%rsp), %rdi
call cudaMalloc@PLT
movslq tam_imag(%rip), %r12
salq $2, %r12
movq %r12, %rdi
call malloc@PLT
movq %rax, 40(%rsp)
leaq 128(%rsp), %rdi
movq %r12, %rsi
call cudaMalloc@PLT
cmpl %ebx, %ebp
jl .L12
leaq .LC7(%rip), %rbx
movq %r13, 56(%rsp)
jmp .L18
.L15:
imull %r15d, %eax
addl %ebp, %eax
cltq
movq 16(%rsp), %rcx
leaq (%rcx,%rax,4), %rdx
movq %rbx, %rsi
movq %r14, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
movl %r15d, %eax
imull dimy(%rip), %eax
addl %ebp, %eax
cltq
movq 8(%rsp), %rcx
leaq (%rcx,%rax,4), %rdx
movq %rbx, %rsi
movq %r13, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
movl %r15d, %eax
imull dimy(%rip), %eax
addl %ebp, %eax
cltq
movq 24(%rsp), %rsi
leaq (%rsi,%rax,4), %rdx
movq %rbx, %rsi
movq %r12, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
addl $1, %ebp
movl dimy(%rip), %eax
cmpl %ebp, %eax
jg .L15
.L16:
addl $1, %r15d
cmpl %r15d, dimx(%rip)
jle .L14
.L13:
movl dimy(%rip), %eax
movl $0, %ebp
testl %eax, %eax
jg .L15
jmp .L16
.L14:
movq %r14, %rdi
call fclose@PLT
movq %r13, %rdi
call fclose@PLT
movq %r12, %rdi
call fclose@PLT
movslq tam_imag(%rip), %rdx
salq $2, %rdx
movl $1, %ecx
movq 8(%rsp), %rsi
movq 80(%rsp), %rdi
call cudaMemcpy@PLT
movl $347, 140(%rsp)
movl $20, 144(%rsp)
movl $13, 152(%rsp)
movl $16, 156(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 152(%rsp), %rdx
movl $1, %ecx
movq 140(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L41
.L17:
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movslq tam_imag(%rip), %rdx
salq $2, %rdx
movl $2, %ecx
movq 128(%rsp), %rsi
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, 32(%rsp)
movl 32(%rsp), %eax
movl 52(%rsp), %edi
cmpl %edi, %eax
jg .L42
.L18:
movl 32(%rsp), %r13d
movl %r13d, %edx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movb $0, 165(%rsp)
leaq 165(%rsp), %rbp
subq $8, %rsp
.cfi_def_cfa_offset 248
leaq .LC3(%rip), %rax
pushq %rax
.cfi_def_cfa_offset 256
movl %r13d, %r9d
leaq .LC1(%rip), %r8
leaq .LC2(%rip), %r12
movq %r12, %rcx
movl $1, %edx
movl $2, %esi
movq %rbp, %rdi
movl $0, %eax
call __sprintf_chk@PLT
addq $16, %rsp
.cfi_def_cfa_offset 240
leaq .LC4(%rip), %r15
movq %r15, %rsi
movq %rbp, %rdi
call fopen@PLT
movq %rax, %r14
movb $0, 166(%rsp)
leaq 166(%rsp), %rbp
subq $8, %rsp
.cfi_def_cfa_offset 248
leaq .LC5(%rip), %rax
pushq %rax
.cfi_def_cfa_offset 256
movl %r13d, 48(%rsp)
movl %r13d, %r9d
leaq .LC1(%rip), %r8
movq %r12, %rcx
movl $1, %edx
movl $2, %esi
movq %rbp, %rdi
movl $0, %eax
call __sprintf_chk@PLT
addq $16, %rsp
.cfi_def_cfa_offset 240
movq %r15, %rsi
movq %rbp, %rdi
call fopen@PLT
movq %rax, %r13
movb $0, 167(%rsp)
leaq 167(%rsp), %rbp
subq $8, %rsp
.cfi_def_cfa_offset 248
leaq .LC6(%rip), %rax
pushq %rax
.cfi_def_cfa_offset 256
movl 48(%rsp), %r9d
leaq .LC1(%rip), %r8
movq %r12, %rcx
movl $1, %edx
movl $2, %esi
movq %rbp, %rdi
movl $0, %eax
call __sprintf_chk@PLT
addq $16, %rsp
.cfi_def_cfa_offset 240
movq %r15, %rsi
movq %rbp, %rdi
call fopen@PLT
movq %rax, %r12
movl $0, %r15d
cmpl $0, dimx(%rip)
jg .L13
jmp .L14
.L41:
movq 128(%rsp), %rsi
movq 88(%rsp), %rdi
call _Z29__device_stub__Z8VarianzaPiPfPiPf
jmp .L17
.L42:
movq 56(%rsp), %r13
.L12:
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC11(%rip), %rsi
leaq .LC12(%rip), %rdi
call fopen@PLT
movq %rax, %r12
movl $0, %ebp
leaq .LC13(%rip), %r15
leaq .LC14(%rip), %r14
cmpl $0, dimx(%rip)
jle .L20
movq %r13, 32(%rsp)
movq 40(%rsp), %r13
jmp .L19
.L21:
imull %ebp, %eax
addl %ebx, %eax
cltq
pxor %xmm0, %xmm0
cvtss2sd 0(%r13,%rax,4), %xmm0
movq %r15, %rdx
movl $2, %esi
movq %r12, %rdi
movl $1, %eax
call __fprintf_chk@PLT
addl $1, %ebx
movl dimy(%rip), %eax
cmpl %ebx, %eax
jg .L21
.L22:
movq %r14, %rdx
movl $2, %esi
movq %r12, %rdi
movl $0, %eax
call __fprintf_chk@PLT
addl $1, %ebp
cmpl %ebp, dimx(%rip)
jle .L39
.L19:
movl dimy(%rip), %eax
movl $0, %ebx
testl %eax, %eax
jg .L21
jmp .L22
.L39:
movq 32(%rsp), %r13
.L20:
movq %r12, %rdi
call fclose@PLT
movq 40(%rsp), %rdi
call free@PLT
movq 16(%rsp), %rdi
call free@PLT
movq 8(%rsp), %rdi
call free@PLT
movq 24(%rsp), %rdi
call free@PLT
movq 128(%rsp), %rdi
call cudaFree@PLT
movq 120(%rsp), %rdi
call cudaFree@PLT
movq 64(%rsp), %rdi
call cudaFree@PLT
movq 72(%rsp), %rdi
call cudaFree@PLT
movq 80(%rsp), %rdi
call cudaFree@PLT
movq 88(%rsp), %rdi
call cudaFree@PLT
movq 96(%rsp), %rdi
call cudaFree@PLT
movq 104(%rsp), %rdi
call cudaFree@PLT
movq 112(%rsp), %rdi
call cudaFree@PLT
call clock@PLT
pxor %xmm0, %xmm0
cvtsi2ssq %rax, %xmm0
pxor %xmm1, %xmm1
cvtsi2ssq %r13, %xmm1
subss %xmm1, %xmm0
divss .LC15(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
leaq .LC16(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L43
movl $0, %eax
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L43:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC17:
.string "_Z8VarianzaPiPf"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC17(%rip), %rdx
movq %rdx, %rcx
leaq _Z8VarianzaPiPf(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl tam_imag
.data
.align 4
.type tam_imag, @object
.size tam_imag, 4
tam_imag:
.long 1443520
.globl dimy
.align 4
.type dimy, @object
.size dimy, 4
dimy:
.long 1388
.globl dimx
.align 4
.type dimx, @object
.size dimx, 4
dimx:
.long 1040
.globl msk
.align 4
.type msk, @object
.size msk, 4
msk:
.long 3
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC15:
.long 1232348160
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <stdlib.h>
#include <cuda.h>
#include <time.h>
//************variables globales***************
int msk=3, dimx=1040, dimy=1388, tam_imag=1388*1040;
// [i][j] = i*dimy+j
//************** Kernel CUDA *********************
__global__ void Varianza (int *G_d, float *var_d){
int idx = threadIdx.x + blockIdx.x*blockDim.x;
int idy = threadIdx.y + blockIdx.y*blockDim.y;
int id = idx + idy*blockDim.x*gridDim.x;
int M_d[9], i, dimx=1040, dimy=1388, tam_imag=1388*1040, msk=3;
float X=0.f,Xprom=0.f,Y=0.f;
var_d[id]=0;
//printf("prueba\n");
if(id<tam_imag){
//M_d[0]=((i<1 || j<1) ? 0:A[i-1][j-1]);
/*
M_d[0]=((idx<1 || idy<1) ? 0:G_d[(idx-1)+(idy-1)*blockDim.x*gridDim.x]);
M_d[1]=((idx<1) ? 0:G_d[(idx-1)+(idy)*blockDim.x*gridDim.x]);
M_d[2]=((idx<1 || idy>dimy-2) ? 0:G_d[(idx-1)+(idy+1)*blockDim.x*gridDim.x]);
M_d[3]=((idy<1) ? 0:G_d[(idx)+(idy-1)*blockDim.x*gridDim.x]);
M_d[4]=G_d[(idx)+(idy)*blockDim.x*gridDim.x];
M_d[5]=((idy>dimy-2) ? 0:G_d[(idx)+(idy+1)*blockDim.x*gridDim.x]);
M_d[6]=((idx>dimx-2 || idy<1) ? 0:G_d[(idx+1)+(idy-1)*blockDim.x*gridDim.x]);
M_d[7]=((idx>dimx-2) ? 0:G_d[(idx+1)+(idy)*blockDim.x*gridDim.x]);
M_d[8]=((idx>dimx-2 || idy>dimy-1) ? 0:G_d[(idx+1)+(idy+1)*blockDim.x*gridDim.x]);
*/
if (idx==0 || idy==0){
M_d[0]=0;
}else{
M_d[0]=G_d[id-1-dimy];
}
/*
if ((idx==0)){
M_d[1]=0;
}else{
M_d[1]=G_d[id-dimy];
//M_d[1]=8;
}
/*
if (idx==0 || idy==dimy){
M_d[2]=0;
}else{
M_d[2]=G_d[id+1-dimy];
}
*/
if (idy==0){
M_d[3]=0;
}else{
M_d[3]=G_d[id-1];
}
M_d[4]=G_d[id];
if (idy==dimy){
M_d[5]=0;
}else{
M_d[5]=G_d[id+1];
}
/*
if (id==dimx || idy==0){
M_d[6]=0;
}else{
M_d[6]=G_d[id-1+dimy];
}
*//*
if (idx==dimx){
M_d[7]=0;
}else{
M_d[7]=G_d[id+dimy];
}
*//*
if (idx==dimx || idy==dimy){
M_d[8]=0;
}else{
M_d[8]=G_d[id+1+dimy];
}
*/
//M_d[0]=1;
M_d[1]=5;
M_d[2]=8;
//M_d[3]=1;
//M_d[4]=1;
//M_d[5]=1;
M_d[6]=2;
M_d[7]=5;
M_d[8]=4;
for(i=0;i<msk*msk;i++)
X+=M_d[i];
Xprom=((float)X)/(msk*msk);
for(i=0;i<msk*msk;i++)
Y+=(Xprom-M_d[i])*(Xprom-M_d[i]);
var_d[id]=Y/(msk*msk);
}
}
//*****************Funcion main**********************
int main(int argc,char* argv[]){
//***************Declaracion de variables**************
int i,j,init,fin,d;
init=atoi(argv[1]);
fin=atoi(argv[2]);
//init=1;
//fin=328;
FILE *matrizR, *matrizG, *matrizB;
float t;
clock_t tinicio, t_GPU;
tinicio=clock();
int *topof_h, *R_h, *G_h, *B_h, *Rf_h, *Gf_h, *Bf_h;
float *max_h, *var_h;
int *topof_d, *R_d, *G_d, *B_d, *Rf_d, *Gf_d, *Bf_d;
float *max_d, *var_d;
//************Inicializacion de variables en el host y en el device ***************
/* // Declaracion tipo MATRIZ
max_h=(float **)malloc(sizeof(float)*dimx);
topof_h=(int **)malloc(sizeof(int)*dimx);
R_h=(int **)malloc(sizeof(int)*dimx);
G_h=(int **)malloc(sizeof(int)*dimx);
B_h=(int **)malloc(sizeof(int)*dimx);
Rf_h=(int **)malloc(sizeof(int)*dimx);
Gf_h=(int **)malloc(sizeof(int)*dimx);
Bf_h=(int **)malloc(sizeof(int)*dimx);
for(i=0;i<dimx;i++){
max_h[i]=(float*)malloc(sizeof(float)*dimy);
topof_h[i]=(int*)malloc(sizeof(int)*dimy);
R_h[i]=(int*)malloc(sizeof(int)*dimy);
G_h[i]=(int*)malloc(sizeof(int)*dimy);
B_h[i]=(int*)malloc(sizeof(int)*dimy);
Rf_h[i]=(int*)malloc(sizeof(int)*dimy);
Gf_h[i]=(int*)malloc(sizeof(int)*dimy);
Bf_h[i]=(int*)malloc(sizeof(int)*dimy);
}
var_h=(float *)malloc(sizeof(float)*tam_imag);
*/
R_h=(int *)malloc(sizeof(int)*tam_imag);
cudaMalloc((void**)&R_d, tam_imag*sizeof(int));
G_h=(int *)malloc(sizeof(int)*tam_imag);
cudaMalloc((void**)&G_d, tam_imag*sizeof(int));
B_h=(int *)malloc(sizeof(int)*tam_imag);
cudaMalloc((void**)&B_d, tam_imag*sizeof(int));
Rf_h=(int *)malloc(sizeof(int)*tam_imag);
cudaMalloc((void**)&Rf_d, tam_imag*sizeof(int));
Gf_h=(int *)malloc(sizeof(int)*tam_imag);
cudaMalloc((void**)&Gf_d, tam_imag*sizeof(int));
Bf_h=(int *)malloc(sizeof(int)*tam_imag);
cudaMalloc((void**)&Bf_d, tam_imag*sizeof(int));
topof_h=(int *)malloc(sizeof(int)*tam_imag);
cudaMalloc((void**)&topof_d, tam_imag*sizeof(int));
max_h=(float *)malloc(sizeof(float)*tam_imag);
cudaMalloc((void**)&max_d, tam_imag*sizeof(float));
var_h=(float *)malloc(sizeof(float)*tam_imag);
cudaMalloc((void**)&var_d,tam_imag*sizeof(float));
//*************** For cálculo EDF ****************
for(d=init;d<=fin;d++){
printf("d=%d \n", d);
//*****************Lecura de matrices RGB en el host****************
char rutaR[]="";
sprintf(rutaR, "%s%d%s","RGB/",d,"/R");
matrizR=fopen(rutaR,"r+");
char rutaG[]="";
sprintf(rutaG, "%s%d%s","RGB/",d,"/G");
matrizG=fopen(rutaG,"r+");
char rutaB[]="";
sprintf(rutaB, "%s%d%s","RGB/",d,"/B");
matrizB=fopen(rutaB,"r+");
for(i=0;i<dimx;i++){
for(j=0;j<dimy;j++){
fscanf(matrizR, "%d", &R_h[i*dimy+j]);
fscanf(matrizG, "%d", &G_h[i*dimy+j]);
fscanf(matrizB, "%d", &B_h[i*dimy+j]);
}
}
fclose(matrizR);
fclose(matrizG);
fclose(matrizB);
//***************** Kernel Varianza *******************
cudaMemcpy(G_d,G_h,sizeof(int)*tam_imag,cudaMemcpyHostToDevice);
dim3 Grid(347,20);
dim3 Block(13,16);
Varianza<<<Grid,Block>>>(B_d,var_d);
printf("Despues de kernel \n");
cudaMemcpy(var_h,var_d,sizeof(float)*tam_imag,cudaMemcpyDeviceToHost);
printf("Despues de resultado a host \n");
//***************** Kernel Varianza *******************
/*
cudaMemcpy(R_d,R_h,sizeof(int)*tam_imag,cudaMemcpyHostToDevice);
cudaMemcpy(G_d,G_h,sizeof(int)*tam_imag,cudaMemcpyHostToDevice);
cudaMemcpy(B_d,B_h,sizeof(int)*tam_imag,cudaMemcpyHostToDevice);
cudaMemcpy(Rf_d,Rf_h,sizeof(int)*tam_imag,cudaMemcpyHostToDevice);
cudaMemcpy(Gf_d,Gf_h,sizeof(int)*tam_imag,cudaMemcpyHostToDevice);
cudaMemcpy(Bf_d,Bf_h,sizeof(int)*tam_imag,cudaMemcpyHostToDevice);
cudaMemcpy(topof_d,topof_h,sizeof(int)*tam_imag,cudaMemcpyHostToDevice);
cudaMemcpy(max_d,max_h,sizeof(float)*tam_imag,cudaMemcpyHostToDevice);
cudaMemcpy(var_d,var_h,sizeof(float)*tam_imag,cudaMemcpyHostToDevice);
dim3 Grid(347,20);
dim3 Block(13,16);
TopoRGB<<<Grid,Block>>>(R_d,G_d,B_d,Rf_d,Gf_d,Bf_d,topof_d,max_d,var_d);
cudaMemcpy(Rf_h,Rf_d,sizeof(int)*tam_imag,cudaMemcpyDeviceToHost);
cudaMemcpy(Gf_h,Gf_d,sizeof(int)*tam_imag,cudaMemcpyDeviceToHost);
cudaMemcpy(Bf_h,Bf_d,sizeof(int)*tam_imag,cudaMemcpyDeviceToHost);
cudaMemcpy(topof_h,topof_d,sizeof(int)*tam_imag,cudaMemcpyDeviceToHost);
cudaMemcpy(max_h,max_d,sizeof(float)*tam_imag,cudaMemcpyDeviceToHost);
*/
//*********************Calculo de TODO ********************
} //Finaliza For cálculo EDF
printf("***Sale del for \n");
/*
// ***************** Generacion de archivos de resultados ************************
FILE *archTopo, *archR, *archG, *archB;
archTopo=fopen("Resultados/topos10","w+");
archR=fopen("Resultados/R10","w+");
archG=fopen("Resultados/G10","w+");
archB=fopen("Resultados/B10","w+");
for(i=0;i<dimx;i++){
for(j=0;j<dimy;j++){
fprintf(archTopo,"%d ",topof_h[i*dimy+j]);
fprintf(archR,"%d ",Rf_h[i*dimy+j]);
fprintf(archG,"%d ",Gf_h[i*dimy+j]);
fprintf(archB,"%d ",Bf_h[i*dimy+j]);
}
fprintf(archTopo,"\n");
fprintf(archR,"\n");
fprintf(archG,"\n");
fprintf(archB,"\n");
}
fclose(archTopo);
fclose(archR);
fclose(archG);
fclose(archB);
*/
//***************** Archivo de varianza final
FILE *archVar;
archVar=fopen("Resultados/VarUltima","w+");
for(i=0;i<dimx;i++){
for(j=0;j<dimy;j++){
fprintf(archVar,"%f ",var_h[i*dimy+j]);
}
fprintf(archVar,"\n");
}
fclose(archVar);
free(var_h);
free(max_h);
free(topof_h);
free(R_h);
free(G_h);
free(B_h);
free(Rf_h);
free(Gf_h);
free(Bf_h);
cudaFree(var_d);
cudaFree(max_d);
cudaFree(topof_d);
cudaFree(R_d);
cudaFree(G_d);
cudaFree(B_d);
cudaFree(Rf_d);
cudaFree(Gf_d);
cudaFree(Bf_d);
t_GPU=clock();
t = ((float)t_GPU-(float)tinicio)/CLOCKS_PER_SEC;
printf("\ntiempo de procesamiento de varianzas: %6.3fs\n",t);
//getchar ();
return 0;
}//FIN funcion main() | #include <stdio.h>
#include <stdlib.h>
#include <hip/hip_runtime.h>
#include <time.h>
//************variables globales***************
int msk=3, dimx=1040, dimy=1388, tam_imag=1388*1040;
// [i][j] = i*dimy+j
//************** Kernel CUDA *********************
__global__ void Varianza (int *G_d, float *var_d){
int idx = threadIdx.x + blockIdx.x*blockDim.x;
int idy = threadIdx.y + blockIdx.y*blockDim.y;
int id = idx + idy*blockDim.x*gridDim.x;
int M_d[9], i, dimx=1040, dimy=1388, tam_imag=1388*1040, msk=3;
float X=0.f,Xprom=0.f,Y=0.f;
var_d[id]=0;
//printf("prueba\n");
if(id<tam_imag){
//M_d[0]=((i<1 || j<1) ? 0:A[i-1][j-1]);
/*
M_d[0]=((idx<1 || idy<1) ? 0:G_d[(idx-1)+(idy-1)*blockDim.x*gridDim.x]);
M_d[1]=((idx<1) ? 0:G_d[(idx-1)+(idy)*blockDim.x*gridDim.x]);
M_d[2]=((idx<1 || idy>dimy-2) ? 0:G_d[(idx-1)+(idy+1)*blockDim.x*gridDim.x]);
M_d[3]=((idy<1) ? 0:G_d[(idx)+(idy-1)*blockDim.x*gridDim.x]);
M_d[4]=G_d[(idx)+(idy)*blockDim.x*gridDim.x];
M_d[5]=((idy>dimy-2) ? 0:G_d[(idx)+(idy+1)*blockDim.x*gridDim.x]);
M_d[6]=((idx>dimx-2 || idy<1) ? 0:G_d[(idx+1)+(idy-1)*blockDim.x*gridDim.x]);
M_d[7]=((idx>dimx-2) ? 0:G_d[(idx+1)+(idy)*blockDim.x*gridDim.x]);
M_d[8]=((idx>dimx-2 || idy>dimy-1) ? 0:G_d[(idx+1)+(idy+1)*blockDim.x*gridDim.x]);
*/
if (idx==0 || idy==0){
M_d[0]=0;
}else{
M_d[0]=G_d[id-1-dimy];
}
/*
if ((idx==0)){
M_d[1]=0;
}else{
M_d[1]=G_d[id-dimy];
//M_d[1]=8;
}
/*
if (idx==0 || idy==dimy){
M_d[2]=0;
}else{
M_d[2]=G_d[id+1-dimy];
}
*/
if (idy==0){
M_d[3]=0;
}else{
M_d[3]=G_d[id-1];
}
M_d[4]=G_d[id];
if (idy==dimy){
M_d[5]=0;
}else{
M_d[5]=G_d[id+1];
}
/*
if (id==dimx || idy==0){
M_d[6]=0;
}else{
M_d[6]=G_d[id-1+dimy];
}
*//*
if (idx==dimx){
M_d[7]=0;
}else{
M_d[7]=G_d[id+dimy];
}
*//*
if (idx==dimx || idy==dimy){
M_d[8]=0;
}else{
M_d[8]=G_d[id+1+dimy];
}
*/
//M_d[0]=1;
M_d[1]=5;
M_d[2]=8;
//M_d[3]=1;
//M_d[4]=1;
//M_d[5]=1;
M_d[6]=2;
M_d[7]=5;
M_d[8]=4;
for(i=0;i<msk*msk;i++)
X+=M_d[i];
Xprom=((float)X)/(msk*msk);
for(i=0;i<msk*msk;i++)
Y+=(Xprom-M_d[i])*(Xprom-M_d[i]);
var_d[id]=Y/(msk*msk);
}
}
//*****************Funcion main**********************
int main(int argc,char* argv[]){
//***************Declaracion de variables**************
int i,j,init,fin,d;
init=atoi(argv[1]);
fin=atoi(argv[2]);
//init=1;
//fin=328;
FILE *matrizR, *matrizG, *matrizB;
float t;
clock_t tinicio, t_GPU;
tinicio=clock();
int *topof_h, *R_h, *G_h, *B_h, *Rf_h, *Gf_h, *Bf_h;
float *max_h, *var_h;
int *topof_d, *R_d, *G_d, *B_d, *Rf_d, *Gf_d, *Bf_d;
float *max_d, *var_d;
//************Inicializacion de variables en el host y en el device ***************
/* // Declaracion tipo MATRIZ
max_h=(float **)malloc(sizeof(float)*dimx);
topof_h=(int **)malloc(sizeof(int)*dimx);
R_h=(int **)malloc(sizeof(int)*dimx);
G_h=(int **)malloc(sizeof(int)*dimx);
B_h=(int **)malloc(sizeof(int)*dimx);
Rf_h=(int **)malloc(sizeof(int)*dimx);
Gf_h=(int **)malloc(sizeof(int)*dimx);
Bf_h=(int **)malloc(sizeof(int)*dimx);
for(i=0;i<dimx;i++){
max_h[i]=(float*)malloc(sizeof(float)*dimy);
topof_h[i]=(int*)malloc(sizeof(int)*dimy);
R_h[i]=(int*)malloc(sizeof(int)*dimy);
G_h[i]=(int*)malloc(sizeof(int)*dimy);
B_h[i]=(int*)malloc(sizeof(int)*dimy);
Rf_h[i]=(int*)malloc(sizeof(int)*dimy);
Gf_h[i]=(int*)malloc(sizeof(int)*dimy);
Bf_h[i]=(int*)malloc(sizeof(int)*dimy);
}
var_h=(float *)malloc(sizeof(float)*tam_imag);
*/
R_h=(int *)malloc(sizeof(int)*tam_imag);
hipMalloc((void**)&R_d, tam_imag*sizeof(int));
G_h=(int *)malloc(sizeof(int)*tam_imag);
hipMalloc((void**)&G_d, tam_imag*sizeof(int));
B_h=(int *)malloc(sizeof(int)*tam_imag);
hipMalloc((void**)&B_d, tam_imag*sizeof(int));
Rf_h=(int *)malloc(sizeof(int)*tam_imag);
hipMalloc((void**)&Rf_d, tam_imag*sizeof(int));
Gf_h=(int *)malloc(sizeof(int)*tam_imag);
hipMalloc((void**)&Gf_d, tam_imag*sizeof(int));
Bf_h=(int *)malloc(sizeof(int)*tam_imag);
hipMalloc((void**)&Bf_d, tam_imag*sizeof(int));
topof_h=(int *)malloc(sizeof(int)*tam_imag);
hipMalloc((void**)&topof_d, tam_imag*sizeof(int));
max_h=(float *)malloc(sizeof(float)*tam_imag);
hipMalloc((void**)&max_d, tam_imag*sizeof(float));
var_h=(float *)malloc(sizeof(float)*tam_imag);
hipMalloc((void**)&var_d,tam_imag*sizeof(float));
//*************** For cálculo EDF ****************
for(d=init;d<=fin;d++){
printf("d=%d \n", d);
//*****************Lecura de matrices RGB en el host****************
char rutaR[]="";
sprintf(rutaR, "%s%d%s","RGB/",d,"/R");
matrizR=fopen(rutaR,"r+");
char rutaG[]="";
sprintf(rutaG, "%s%d%s","RGB/",d,"/G");
matrizG=fopen(rutaG,"r+");
char rutaB[]="";
sprintf(rutaB, "%s%d%s","RGB/",d,"/B");
matrizB=fopen(rutaB,"r+");
for(i=0;i<dimx;i++){
for(j=0;j<dimy;j++){
fscanf(matrizR, "%d", &R_h[i*dimy+j]);
fscanf(matrizG, "%d", &G_h[i*dimy+j]);
fscanf(matrizB, "%d", &B_h[i*dimy+j]);
}
}
fclose(matrizR);
fclose(matrizG);
fclose(matrizB);
//***************** Kernel Varianza *******************
hipMemcpy(G_d,G_h,sizeof(int)*tam_imag,hipMemcpyHostToDevice);
dim3 Grid(347,20);
dim3 Block(13,16);
Varianza<<<Grid,Block>>>(B_d,var_d);
printf("Despues de kernel \n");
hipMemcpy(var_h,var_d,sizeof(float)*tam_imag,hipMemcpyDeviceToHost);
printf("Despues de resultado a host \n");
//***************** Kernel Varianza *******************
/*
cudaMemcpy(R_d,R_h,sizeof(int)*tam_imag,cudaMemcpyHostToDevice);
cudaMemcpy(G_d,G_h,sizeof(int)*tam_imag,cudaMemcpyHostToDevice);
cudaMemcpy(B_d,B_h,sizeof(int)*tam_imag,cudaMemcpyHostToDevice);
cudaMemcpy(Rf_d,Rf_h,sizeof(int)*tam_imag,cudaMemcpyHostToDevice);
cudaMemcpy(Gf_d,Gf_h,sizeof(int)*tam_imag,cudaMemcpyHostToDevice);
cudaMemcpy(Bf_d,Bf_h,sizeof(int)*tam_imag,cudaMemcpyHostToDevice);
cudaMemcpy(topof_d,topof_h,sizeof(int)*tam_imag,cudaMemcpyHostToDevice);
cudaMemcpy(max_d,max_h,sizeof(float)*tam_imag,cudaMemcpyHostToDevice);
cudaMemcpy(var_d,var_h,sizeof(float)*tam_imag,cudaMemcpyHostToDevice);
dim3 Grid(347,20);
dim3 Block(13,16);
TopoRGB<<<Grid,Block>>>(R_d,G_d,B_d,Rf_d,Gf_d,Bf_d,topof_d,max_d,var_d);
cudaMemcpy(Rf_h,Rf_d,sizeof(int)*tam_imag,cudaMemcpyDeviceToHost);
cudaMemcpy(Gf_h,Gf_d,sizeof(int)*tam_imag,cudaMemcpyDeviceToHost);
cudaMemcpy(Bf_h,Bf_d,sizeof(int)*tam_imag,cudaMemcpyDeviceToHost);
cudaMemcpy(topof_h,topof_d,sizeof(int)*tam_imag,cudaMemcpyDeviceToHost);
cudaMemcpy(max_h,max_d,sizeof(float)*tam_imag,cudaMemcpyDeviceToHost);
*/
//*********************Calculo de TODO ********************
} //Finaliza For cálculo EDF
printf("***Sale del for \n");
/*
// ***************** Generacion de archivos de resultados ************************
FILE *archTopo, *archR, *archG, *archB;
archTopo=fopen("Resultados/topos10","w+");
archR=fopen("Resultados/R10","w+");
archG=fopen("Resultados/G10","w+");
archB=fopen("Resultados/B10","w+");
for(i=0;i<dimx;i++){
for(j=0;j<dimy;j++){
fprintf(archTopo,"%d ",topof_h[i*dimy+j]);
fprintf(archR,"%d ",Rf_h[i*dimy+j]);
fprintf(archG,"%d ",Gf_h[i*dimy+j]);
fprintf(archB,"%d ",Bf_h[i*dimy+j]);
}
fprintf(archTopo,"\n");
fprintf(archR,"\n");
fprintf(archG,"\n");
fprintf(archB,"\n");
}
fclose(archTopo);
fclose(archR);
fclose(archG);
fclose(archB);
*/
//***************** Archivo de varianza final
FILE *archVar;
archVar=fopen("Resultados/VarUltima","w+");
for(i=0;i<dimx;i++){
for(j=0;j<dimy;j++){
fprintf(archVar,"%f ",var_h[i*dimy+j]);
}
fprintf(archVar,"\n");
}
fclose(archVar);
free(var_h);
free(max_h);
free(topof_h);
free(R_h);
free(G_h);
free(B_h);
free(Rf_h);
free(Gf_h);
free(Bf_h);
hipFree(var_d);
hipFree(max_d);
hipFree(topof_d);
hipFree(R_d);
hipFree(G_d);
hipFree(B_d);
hipFree(Rf_d);
hipFree(Gf_d);
hipFree(Bf_d);
t_GPU=clock();
t = ((float)t_GPU-(float)tinicio)/CLOCKS_PER_SEC;
printf("\ntiempo de procesamiento de varianzas: %6.3fs\n",t);
//getchar ();
return 0;
}//FIN funcion main() |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <stdio.h>
#include <stdlib.h>
#include <hip/hip_runtime.h>
#include <time.h>
//************variables globales***************
int msk=3, dimx=1040, dimy=1388, tam_imag=1388*1040;
// [i][j] = i*dimy+j
//************** Kernel CUDA *********************
__global__ void Varianza (int *G_d, float *var_d){
int idx = threadIdx.x + blockIdx.x*blockDim.x;
int idy = threadIdx.y + blockIdx.y*blockDim.y;
int id = idx + idy*blockDim.x*gridDim.x;
int M_d[9], i, dimx=1040, dimy=1388, tam_imag=1388*1040, msk=3;
float X=0.f,Xprom=0.f,Y=0.f;
var_d[id]=0;
//printf("prueba\n");
if(id<tam_imag){
//M_d[0]=((i<1 || j<1) ? 0:A[i-1][j-1]);
/*
M_d[0]=((idx<1 || idy<1) ? 0:G_d[(idx-1)+(idy-1)*blockDim.x*gridDim.x]);
M_d[1]=((idx<1) ? 0:G_d[(idx-1)+(idy)*blockDim.x*gridDim.x]);
M_d[2]=((idx<1 || idy>dimy-2) ? 0:G_d[(idx-1)+(idy+1)*blockDim.x*gridDim.x]);
M_d[3]=((idy<1) ? 0:G_d[(idx)+(idy-1)*blockDim.x*gridDim.x]);
M_d[4]=G_d[(idx)+(idy)*blockDim.x*gridDim.x];
M_d[5]=((idy>dimy-2) ? 0:G_d[(idx)+(idy+1)*blockDim.x*gridDim.x]);
M_d[6]=((idx>dimx-2 || idy<1) ? 0:G_d[(idx+1)+(idy-1)*blockDim.x*gridDim.x]);
M_d[7]=((idx>dimx-2) ? 0:G_d[(idx+1)+(idy)*blockDim.x*gridDim.x]);
M_d[8]=((idx>dimx-2 || idy>dimy-1) ? 0:G_d[(idx+1)+(idy+1)*blockDim.x*gridDim.x]);
*/
if (idx==0 || idy==0){
M_d[0]=0;
}else{
M_d[0]=G_d[id-1-dimy];
}
/*
if ((idx==0)){
M_d[1]=0;
}else{
M_d[1]=G_d[id-dimy];
//M_d[1]=8;
}
/*
if (idx==0 || idy==dimy){
M_d[2]=0;
}else{
M_d[2]=G_d[id+1-dimy];
}
*/
if (idy==0){
M_d[3]=0;
}else{
M_d[3]=G_d[id-1];
}
M_d[4]=G_d[id];
if (idy==dimy){
M_d[5]=0;
}else{
M_d[5]=G_d[id+1];
}
/*
if (id==dimx || idy==0){
M_d[6]=0;
}else{
M_d[6]=G_d[id-1+dimy];
}
*//*
if (idx==dimx){
M_d[7]=0;
}else{
M_d[7]=G_d[id+dimy];
}
*//*
if (idx==dimx || idy==dimy){
M_d[8]=0;
}else{
M_d[8]=G_d[id+1+dimy];
}
*/
//M_d[0]=1;
M_d[1]=5;
M_d[2]=8;
//M_d[3]=1;
//M_d[4]=1;
//M_d[5]=1;
M_d[6]=2;
M_d[7]=5;
M_d[8]=4;
for(i=0;i<msk*msk;i++)
X+=M_d[i];
Xprom=((float)X)/(msk*msk);
for(i=0;i<msk*msk;i++)
Y+=(Xprom-M_d[i])*(Xprom-M_d[i]);
var_d[id]=Y/(msk*msk);
}
}
//*****************Funcion main**********************
int main(int argc,char* argv[]){
//***************Declaracion de variables**************
int i,j,init,fin,d;
init=atoi(argv[1]);
fin=atoi(argv[2]);
//init=1;
//fin=328;
FILE *matrizR, *matrizG, *matrizB;
float t;
clock_t tinicio, t_GPU;
tinicio=clock();
int *topof_h, *R_h, *G_h, *B_h, *Rf_h, *Gf_h, *Bf_h;
float *max_h, *var_h;
int *topof_d, *R_d, *G_d, *B_d, *Rf_d, *Gf_d, *Bf_d;
float *max_d, *var_d;
//************Inicializacion de variables en el host y en el device ***************
/* // Declaracion tipo MATRIZ
max_h=(float **)malloc(sizeof(float)*dimx);
topof_h=(int **)malloc(sizeof(int)*dimx);
R_h=(int **)malloc(sizeof(int)*dimx);
G_h=(int **)malloc(sizeof(int)*dimx);
B_h=(int **)malloc(sizeof(int)*dimx);
Rf_h=(int **)malloc(sizeof(int)*dimx);
Gf_h=(int **)malloc(sizeof(int)*dimx);
Bf_h=(int **)malloc(sizeof(int)*dimx);
for(i=0;i<dimx;i++){
max_h[i]=(float*)malloc(sizeof(float)*dimy);
topof_h[i]=(int*)malloc(sizeof(int)*dimy);
R_h[i]=(int*)malloc(sizeof(int)*dimy);
G_h[i]=(int*)malloc(sizeof(int)*dimy);
B_h[i]=(int*)malloc(sizeof(int)*dimy);
Rf_h[i]=(int*)malloc(sizeof(int)*dimy);
Gf_h[i]=(int*)malloc(sizeof(int)*dimy);
Bf_h[i]=(int*)malloc(sizeof(int)*dimy);
}
var_h=(float *)malloc(sizeof(float)*tam_imag);
*/
R_h=(int *)malloc(sizeof(int)*tam_imag);
hipMalloc((void**)&R_d, tam_imag*sizeof(int));
G_h=(int *)malloc(sizeof(int)*tam_imag);
hipMalloc((void**)&G_d, tam_imag*sizeof(int));
B_h=(int *)malloc(sizeof(int)*tam_imag);
hipMalloc((void**)&B_d, tam_imag*sizeof(int));
Rf_h=(int *)malloc(sizeof(int)*tam_imag);
hipMalloc((void**)&Rf_d, tam_imag*sizeof(int));
Gf_h=(int *)malloc(sizeof(int)*tam_imag);
hipMalloc((void**)&Gf_d, tam_imag*sizeof(int));
Bf_h=(int *)malloc(sizeof(int)*tam_imag);
hipMalloc((void**)&Bf_d, tam_imag*sizeof(int));
topof_h=(int *)malloc(sizeof(int)*tam_imag);
hipMalloc((void**)&topof_d, tam_imag*sizeof(int));
max_h=(float *)malloc(sizeof(float)*tam_imag);
hipMalloc((void**)&max_d, tam_imag*sizeof(float));
var_h=(float *)malloc(sizeof(float)*tam_imag);
hipMalloc((void**)&var_d,tam_imag*sizeof(float));
//*************** For cálculo EDF ****************
for(d=init;d<=fin;d++){
printf("d=%d \n", d);
//*****************Lecura de matrices RGB en el host****************
char rutaR[]="";
sprintf(rutaR, "%s%d%s","RGB/",d,"/R");
matrizR=fopen(rutaR,"r+");
char rutaG[]="";
sprintf(rutaG, "%s%d%s","RGB/",d,"/G");
matrizG=fopen(rutaG,"r+");
char rutaB[]="";
sprintf(rutaB, "%s%d%s","RGB/",d,"/B");
matrizB=fopen(rutaB,"r+");
for(i=0;i<dimx;i++){
for(j=0;j<dimy;j++){
fscanf(matrizR, "%d", &R_h[i*dimy+j]);
fscanf(matrizG, "%d", &G_h[i*dimy+j]);
fscanf(matrizB, "%d", &B_h[i*dimy+j]);
}
}
fclose(matrizR);
fclose(matrizG);
fclose(matrizB);
//***************** Kernel Varianza *******************
hipMemcpy(G_d,G_h,sizeof(int)*tam_imag,hipMemcpyHostToDevice);
dim3 Grid(347,20);
dim3 Block(13,16);
Varianza<<<Grid,Block>>>(B_d,var_d);
printf("Despues de kernel \n");
hipMemcpy(var_h,var_d,sizeof(float)*tam_imag,hipMemcpyDeviceToHost);
printf("Despues de resultado a host \n");
//***************** Kernel Varianza *******************
/*
cudaMemcpy(R_d,R_h,sizeof(int)*tam_imag,cudaMemcpyHostToDevice);
cudaMemcpy(G_d,G_h,sizeof(int)*tam_imag,cudaMemcpyHostToDevice);
cudaMemcpy(B_d,B_h,sizeof(int)*tam_imag,cudaMemcpyHostToDevice);
cudaMemcpy(Rf_d,Rf_h,sizeof(int)*tam_imag,cudaMemcpyHostToDevice);
cudaMemcpy(Gf_d,Gf_h,sizeof(int)*tam_imag,cudaMemcpyHostToDevice);
cudaMemcpy(Bf_d,Bf_h,sizeof(int)*tam_imag,cudaMemcpyHostToDevice);
cudaMemcpy(topof_d,topof_h,sizeof(int)*tam_imag,cudaMemcpyHostToDevice);
cudaMemcpy(max_d,max_h,sizeof(float)*tam_imag,cudaMemcpyHostToDevice);
cudaMemcpy(var_d,var_h,sizeof(float)*tam_imag,cudaMemcpyHostToDevice);
dim3 Grid(347,20);
dim3 Block(13,16);
TopoRGB<<<Grid,Block>>>(R_d,G_d,B_d,Rf_d,Gf_d,Bf_d,topof_d,max_d,var_d);
cudaMemcpy(Rf_h,Rf_d,sizeof(int)*tam_imag,cudaMemcpyDeviceToHost);
cudaMemcpy(Gf_h,Gf_d,sizeof(int)*tam_imag,cudaMemcpyDeviceToHost);
cudaMemcpy(Bf_h,Bf_d,sizeof(int)*tam_imag,cudaMemcpyDeviceToHost);
cudaMemcpy(topof_h,topof_d,sizeof(int)*tam_imag,cudaMemcpyDeviceToHost);
cudaMemcpy(max_h,max_d,sizeof(float)*tam_imag,cudaMemcpyDeviceToHost);
*/
//*********************Calculo de TODO ********************
} //Finaliza For cálculo EDF
printf("***Sale del for \n");
/*
// ***************** Generacion de archivos de resultados ************************
FILE *archTopo, *archR, *archG, *archB;
archTopo=fopen("Resultados/topos10","w+");
archR=fopen("Resultados/R10","w+");
archG=fopen("Resultados/G10","w+");
archB=fopen("Resultados/B10","w+");
for(i=0;i<dimx;i++){
for(j=0;j<dimy;j++){
fprintf(archTopo,"%d ",topof_h[i*dimy+j]);
fprintf(archR,"%d ",Rf_h[i*dimy+j]);
fprintf(archG,"%d ",Gf_h[i*dimy+j]);
fprintf(archB,"%d ",Bf_h[i*dimy+j]);
}
fprintf(archTopo,"\n");
fprintf(archR,"\n");
fprintf(archG,"\n");
fprintf(archB,"\n");
}
fclose(archTopo);
fclose(archR);
fclose(archG);
fclose(archB);
*/
//***************** Archivo de varianza final
FILE *archVar;
archVar=fopen("Resultados/VarUltima","w+");
for(i=0;i<dimx;i++){
for(j=0;j<dimy;j++){
fprintf(archVar,"%f ",var_h[i*dimy+j]);
}
fprintf(archVar,"\n");
}
fclose(archVar);
free(var_h);
free(max_h);
free(topof_h);
free(R_h);
free(G_h);
free(B_h);
free(Rf_h);
free(Gf_h);
free(Bf_h);
hipFree(var_d);
hipFree(max_d);
hipFree(topof_d);
hipFree(R_d);
hipFree(G_d);
hipFree(B_d);
hipFree(Rf_d);
hipFree(Gf_d);
hipFree(Bf_d);
t_GPU=clock();
t = ((float)t_GPU-(float)tinicio)/CLOCKS_PER_SEC;
printf("\ntiempo de procesamiento de varianzas: %6.3fs\n",t);
//getchar ();
return 0;
}//FIN funcion main() | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z8VarianzaPiPf
.globl _Z8VarianzaPiPf
.p2align 8
.type _Z8VarianzaPiPf,@function
_Z8VarianzaPiPf:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x1c
s_load_b32 s4, s[0:1], 0x10
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s5, s2, 0xffff
s_lshr_b32 s2, s2, 16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[0:1], null, s14, s5, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s2, v[3:4]
s_mul_i32 s4, s4, s5
s_load_b64 s[2:3], s[0:1], 0x8
v_mad_u64_u32 v[6:7], null, s4, v1, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v7, 31, v6
v_lshlrev_b64 v[2:3], 2, v[6:7]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v9, vcc_lo, s2, v2
v_add_co_ci_u32_e32 v10, vcc_lo, s3, v3, vcc_lo
v_mov_b32_e32 v2, 0
s_mov_b32 s2, exec_lo
global_store_b32 v[9:10], v2, off
v_cmpx_gt_i32_e32 0x1606c0, v6
s_cbranch_execz .LBB0_12
s_load_b64 s[2:3], s[0:1], 0x0
v_cmp_ne_u32_e64 s0, 0, v0
v_cmp_ne_u32_e32 vcc_lo, 0, v1
v_mov_b32_e32 v0, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s0, s0, vcc_lo
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_3
v_lshlrev_b64 v[2:3], 2, v[6:7]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v0, s0, s2, v2
v_add_co_ci_u32_e64 v3, s0, s3, v3, s0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v2, s0, 0xfffff000, v0
v_add_co_ci_u32_e64 v3, s0, -1, v3, s0
global_load_b32 v0, v[2:3], off offset:-1460
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s1
v_mov_b32_e32 v5, 0
v_mov_b32_e32 v3, 0
s_and_saveexec_b32 s0, vcc_lo
s_cbranch_execz .LBB0_5
v_lshlrev_b64 v[2:3], 2, v[6:7]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s2, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
global_load_b32 v3, v[2:3], off offset:-4
.LBB0_5:
s_or_b32 exec_lo, exec_lo, s0
v_lshlrev_b64 v[6:7], 2, v[6:7]
s_mov_b32 s0, exec_lo
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v6, vcc_lo, s2, v6
v_add_co_ci_u32_e32 v7, vcc_lo, s3, v7, vcc_lo
global_load_b32 v4, v[6:7], off
v_cmpx_ne_u32_e32 0x56c, v1
s_cbranch_execz .LBB0_7
global_load_b32 v5, v[6:7], off offset:4
.LBB0_7:
s_or_b32 exec_lo, exec_lo, s0
v_dual_mov_b32 v1, 5 :: v_dual_mov_b32 v2, 8
v_mov_b32_e32 v6, 2
v_dual_mov_b32 v8, 4 :: v_dual_mov_b32 v11, 0
s_delay_alu instid0(VALU_DEP_3)
v_mov_b32_e32 v7, v1
s_mov_b64 s[0:1], 0
.LBB0_8:
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 m0, s0
s_add_u32 s0, s0, 1
s_waitcnt vmcnt(0)
v_movrels_b32_e32 v12, v0
s_addc_u32 s1, s1, 0
s_cmp_lg_u32 s0, 9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_f32_i32_e32 v12, v12
v_add_f32_e32 v11, v11, v12
s_cbranch_scc1 .LBB0_8
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_div_scale_f32 v12, null, 0x41100000, 0x41100000, v11
v_div_scale_f32 v15, vcc_lo, v11, 0x41100000, v11
s_mov_b64 s[0:1], 0
v_rcp_f32_e32 v13, v12
s_waitcnt_depctr 0xfff
v_fma_f32 v14, -v12, v13, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v13, v14, v13
v_mul_f32_e32 v14, v15, v13
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v16, -v12, v14, v15
v_fmac_f32_e32 v14, v16, v13
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v12, -v12, v14, v15
v_div_fmas_f32 v12, v12, v13, v14
s_delay_alu instid0(VALU_DEP_1)
v_div_fixup_f32 v12, v12, 0x41100000, v11
v_mov_b32_e32 v11, 0
.LBB0_10:
s_mov_b32 m0, s0
s_add_u32 s0, s0, 1
v_movrels_b32_e32 v13, v0
s_addc_u32 s1, s1, 0
s_cmp_lg_u32 s0, 9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_f32_i32_e32 v13, v13
v_sub_f32_e32 v13, v12, v13
s_delay_alu instid0(VALU_DEP_1)
v_fmac_f32_e32 v11, v13, v13
s_cbranch_scc1 .LBB0_10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_scale_f32 v0, null, 0x41100000, 0x41100000, v11
v_rcp_f32_e32 v1, v0
s_waitcnt_depctr 0xfff
v_fma_f32 v2, -v0, v1, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v1, v2, v1
v_div_scale_f32 v2, vcc_lo, v11, 0x41100000, v11
v_mul_f32_e32 v3, v2, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v4, -v0, v3, v2
v_fmac_f32_e32 v3, v4, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v0, -v0, v3, v2
v_div_fmas_f32 v0, v0, v1, v3
s_delay_alu instid0(VALU_DEP_1)
v_div_fixup_f32 v0, v0, 0x41100000, v11
global_store_b32 v[9:10], v0, off
.LBB0_12:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8VarianzaPiPf
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 17
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z8VarianzaPiPf, .Lfunc_end0-_Z8VarianzaPiPf
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8VarianzaPiPf
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z8VarianzaPiPf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 17
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <stdio.h>
#include <stdlib.h>
#include <hip/hip_runtime.h>
#include <time.h>
//************variables globales***************
int msk=3, dimx=1040, dimy=1388, tam_imag=1388*1040;
// [i][j] = i*dimy+j
//************** Kernel CUDA *********************
__global__ void Varianza (int *G_d, float *var_d){
int idx = threadIdx.x + blockIdx.x*blockDim.x;
int idy = threadIdx.y + blockIdx.y*blockDim.y;
int id = idx + idy*blockDim.x*gridDim.x;
int M_d[9], i, dimx=1040, dimy=1388, tam_imag=1388*1040, msk=3;
float X=0.f,Xprom=0.f,Y=0.f;
var_d[id]=0;
//printf("prueba\n");
if(id<tam_imag){
//M_d[0]=((i<1 || j<1) ? 0:A[i-1][j-1]);
/*
M_d[0]=((idx<1 || idy<1) ? 0:G_d[(idx-1)+(idy-1)*blockDim.x*gridDim.x]);
M_d[1]=((idx<1) ? 0:G_d[(idx-1)+(idy)*blockDim.x*gridDim.x]);
M_d[2]=((idx<1 || idy>dimy-2) ? 0:G_d[(idx-1)+(idy+1)*blockDim.x*gridDim.x]);
M_d[3]=((idy<1) ? 0:G_d[(idx)+(idy-1)*blockDim.x*gridDim.x]);
M_d[4]=G_d[(idx)+(idy)*blockDim.x*gridDim.x];
M_d[5]=((idy>dimy-2) ? 0:G_d[(idx)+(idy+1)*blockDim.x*gridDim.x]);
M_d[6]=((idx>dimx-2 || idy<1) ? 0:G_d[(idx+1)+(idy-1)*blockDim.x*gridDim.x]);
M_d[7]=((idx>dimx-2) ? 0:G_d[(idx+1)+(idy)*blockDim.x*gridDim.x]);
M_d[8]=((idx>dimx-2 || idy>dimy-1) ? 0:G_d[(idx+1)+(idy+1)*blockDim.x*gridDim.x]);
*/
if (idx==0 || idy==0){
M_d[0]=0;
}else{
M_d[0]=G_d[id-1-dimy];
}
/*
if ((idx==0)){
M_d[1]=0;
}else{
M_d[1]=G_d[id-dimy];
//M_d[1]=8;
}
/*
if (idx==0 || idy==dimy){
M_d[2]=0;
}else{
M_d[2]=G_d[id+1-dimy];
}
*/
if (idy==0){
M_d[3]=0;
}else{
M_d[3]=G_d[id-1];
}
M_d[4]=G_d[id];
if (idy==dimy){
M_d[5]=0;
}else{
M_d[5]=G_d[id+1];
}
/*
if (id==dimx || idy==0){
M_d[6]=0;
}else{
M_d[6]=G_d[id-1+dimy];
}
*//*
if (idx==dimx){
M_d[7]=0;
}else{
M_d[7]=G_d[id+dimy];
}
*//*
if (idx==dimx || idy==dimy){
M_d[8]=0;
}else{
M_d[8]=G_d[id+1+dimy];
}
*/
//M_d[0]=1;
M_d[1]=5;
M_d[2]=8;
//M_d[3]=1;
//M_d[4]=1;
//M_d[5]=1;
M_d[6]=2;
M_d[7]=5;
M_d[8]=4;
for(i=0;i<msk*msk;i++)
X+=M_d[i];
Xprom=((float)X)/(msk*msk);
for(i=0;i<msk*msk;i++)
Y+=(Xprom-M_d[i])*(Xprom-M_d[i]);
var_d[id]=Y/(msk*msk);
}
}
//*****************Funcion main**********************
int main(int argc,char* argv[]){
//***************Declaracion de variables**************
int i,j,init,fin,d;
init=atoi(argv[1]);
fin=atoi(argv[2]);
//init=1;
//fin=328;
FILE *matrizR, *matrizG, *matrizB;
float t;
clock_t tinicio, t_GPU;
tinicio=clock();
int *topof_h, *R_h, *G_h, *B_h, *Rf_h, *Gf_h, *Bf_h;
float *max_h, *var_h;
int *topof_d, *R_d, *G_d, *B_d, *Rf_d, *Gf_d, *Bf_d;
float *max_d, *var_d;
//************Inicializacion de variables en el host y en el device ***************
/* // Declaracion tipo MATRIZ
max_h=(float **)malloc(sizeof(float)*dimx);
topof_h=(int **)malloc(sizeof(int)*dimx);
R_h=(int **)malloc(sizeof(int)*dimx);
G_h=(int **)malloc(sizeof(int)*dimx);
B_h=(int **)malloc(sizeof(int)*dimx);
Rf_h=(int **)malloc(sizeof(int)*dimx);
Gf_h=(int **)malloc(sizeof(int)*dimx);
Bf_h=(int **)malloc(sizeof(int)*dimx);
for(i=0;i<dimx;i++){
max_h[i]=(float*)malloc(sizeof(float)*dimy);
topof_h[i]=(int*)malloc(sizeof(int)*dimy);
R_h[i]=(int*)malloc(sizeof(int)*dimy);
G_h[i]=(int*)malloc(sizeof(int)*dimy);
B_h[i]=(int*)malloc(sizeof(int)*dimy);
Rf_h[i]=(int*)malloc(sizeof(int)*dimy);
Gf_h[i]=(int*)malloc(sizeof(int)*dimy);
Bf_h[i]=(int*)malloc(sizeof(int)*dimy);
}
var_h=(float *)malloc(sizeof(float)*tam_imag);
*/
R_h=(int *)malloc(sizeof(int)*tam_imag);
hipMalloc((void**)&R_d, tam_imag*sizeof(int));
G_h=(int *)malloc(sizeof(int)*tam_imag);
hipMalloc((void**)&G_d, tam_imag*sizeof(int));
B_h=(int *)malloc(sizeof(int)*tam_imag);
hipMalloc((void**)&B_d, tam_imag*sizeof(int));
Rf_h=(int *)malloc(sizeof(int)*tam_imag);
hipMalloc((void**)&Rf_d, tam_imag*sizeof(int));
Gf_h=(int *)malloc(sizeof(int)*tam_imag);
hipMalloc((void**)&Gf_d, tam_imag*sizeof(int));
Bf_h=(int *)malloc(sizeof(int)*tam_imag);
hipMalloc((void**)&Bf_d, tam_imag*sizeof(int));
topof_h=(int *)malloc(sizeof(int)*tam_imag);
hipMalloc((void**)&topof_d, tam_imag*sizeof(int));
max_h=(float *)malloc(sizeof(float)*tam_imag);
hipMalloc((void**)&max_d, tam_imag*sizeof(float));
var_h=(float *)malloc(sizeof(float)*tam_imag);
hipMalloc((void**)&var_d,tam_imag*sizeof(float));
//*************** For cálculo EDF ****************
for(d=init;d<=fin;d++){
printf("d=%d \n", d);
//*****************Lecura de matrices RGB en el host****************
char rutaR[]="";
sprintf(rutaR, "%s%d%s","RGB/",d,"/R");
matrizR=fopen(rutaR,"r+");
char rutaG[]="";
sprintf(rutaG, "%s%d%s","RGB/",d,"/G");
matrizG=fopen(rutaG,"r+");
char rutaB[]="";
sprintf(rutaB, "%s%d%s","RGB/",d,"/B");
matrizB=fopen(rutaB,"r+");
for(i=0;i<dimx;i++){
for(j=0;j<dimy;j++){
fscanf(matrizR, "%d", &R_h[i*dimy+j]);
fscanf(matrizG, "%d", &G_h[i*dimy+j]);
fscanf(matrizB, "%d", &B_h[i*dimy+j]);
}
}
fclose(matrizR);
fclose(matrizG);
fclose(matrizB);
//***************** Kernel Varianza *******************
hipMemcpy(G_d,G_h,sizeof(int)*tam_imag,hipMemcpyHostToDevice);
dim3 Grid(347,20);
dim3 Block(13,16);
Varianza<<<Grid,Block>>>(B_d,var_d);
printf("Despues de kernel \n");
hipMemcpy(var_h,var_d,sizeof(float)*tam_imag,hipMemcpyDeviceToHost);
printf("Despues de resultado a host \n");
//***************** Kernel Varianza *******************
/*
cudaMemcpy(R_d,R_h,sizeof(int)*tam_imag,cudaMemcpyHostToDevice);
cudaMemcpy(G_d,G_h,sizeof(int)*tam_imag,cudaMemcpyHostToDevice);
cudaMemcpy(B_d,B_h,sizeof(int)*tam_imag,cudaMemcpyHostToDevice);
cudaMemcpy(Rf_d,Rf_h,sizeof(int)*tam_imag,cudaMemcpyHostToDevice);
cudaMemcpy(Gf_d,Gf_h,sizeof(int)*tam_imag,cudaMemcpyHostToDevice);
cudaMemcpy(Bf_d,Bf_h,sizeof(int)*tam_imag,cudaMemcpyHostToDevice);
cudaMemcpy(topof_d,topof_h,sizeof(int)*tam_imag,cudaMemcpyHostToDevice);
cudaMemcpy(max_d,max_h,sizeof(float)*tam_imag,cudaMemcpyHostToDevice);
cudaMemcpy(var_d,var_h,sizeof(float)*tam_imag,cudaMemcpyHostToDevice);
dim3 Grid(347,20);
dim3 Block(13,16);
TopoRGB<<<Grid,Block>>>(R_d,G_d,B_d,Rf_d,Gf_d,Bf_d,topof_d,max_d,var_d);
cudaMemcpy(Rf_h,Rf_d,sizeof(int)*tam_imag,cudaMemcpyDeviceToHost);
cudaMemcpy(Gf_h,Gf_d,sizeof(int)*tam_imag,cudaMemcpyDeviceToHost);
cudaMemcpy(Bf_h,Bf_d,sizeof(int)*tam_imag,cudaMemcpyDeviceToHost);
cudaMemcpy(topof_h,topof_d,sizeof(int)*tam_imag,cudaMemcpyDeviceToHost);
cudaMemcpy(max_h,max_d,sizeof(float)*tam_imag,cudaMemcpyDeviceToHost);
*/
//*********************Calculo de TODO ********************
} //Finaliza For cálculo EDF
printf("***Sale del for \n");
/*
// ***************** Generacion de archivos de resultados ************************
FILE *archTopo, *archR, *archG, *archB;
archTopo=fopen("Resultados/topos10","w+");
archR=fopen("Resultados/R10","w+");
archG=fopen("Resultados/G10","w+");
archB=fopen("Resultados/B10","w+");
for(i=0;i<dimx;i++){
for(j=0;j<dimy;j++){
fprintf(archTopo,"%d ",topof_h[i*dimy+j]);
fprintf(archR,"%d ",Rf_h[i*dimy+j]);
fprintf(archG,"%d ",Gf_h[i*dimy+j]);
fprintf(archB,"%d ",Bf_h[i*dimy+j]);
}
fprintf(archTopo,"\n");
fprintf(archR,"\n");
fprintf(archG,"\n");
fprintf(archB,"\n");
}
fclose(archTopo);
fclose(archR);
fclose(archG);
fclose(archB);
*/
//***************** Archivo de varianza final
FILE *archVar;
archVar=fopen("Resultados/VarUltima","w+");
for(i=0;i<dimx;i++){
for(j=0;j<dimy;j++){
fprintf(archVar,"%f ",var_h[i*dimy+j]);
}
fprintf(archVar,"\n");
}
fclose(archVar);
free(var_h);
free(max_h);
free(topof_h);
free(R_h);
free(G_h);
free(B_h);
free(Rf_h);
free(Gf_h);
free(Bf_h);
hipFree(var_d);
hipFree(max_d);
hipFree(topof_d);
hipFree(R_d);
hipFree(G_d);
hipFree(B_d);
hipFree(Rf_d);
hipFree(Gf_d);
hipFree(Bf_d);
t_GPU=clock();
t = ((float)t_GPU-(float)tinicio)/CLOCKS_PER_SEC;
printf("\ntiempo de procesamiento de varianzas: %6.3fs\n",t);
//getchar ();
return 0;
}//FIN funcion main() | .text
.file "10_var--topo+RGB-CUDA.hip"
.globl _Z23__device_stub__VarianzaPiPf # -- Begin function _Z23__device_stub__VarianzaPiPf
.p2align 4, 0x90
.type _Z23__device_stub__VarianzaPiPf,@function
_Z23__device_stub__VarianzaPiPf: # @_Z23__device_stub__VarianzaPiPf
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z8VarianzaPiPf, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z23__device_stub__VarianzaPiPf, .Lfunc_end0-_Z23__device_stub__VarianzaPiPf
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI1_0:
.long 0x49742400 # float 1.0E+6
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $248, %rsp
.cfi_def_cfa_offset 304
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %rbx
movq 8(%rsi), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r14
movq 16(%rbx), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r15
callq clock
movq %rax, 88(%rsp) # 8-byte Spill
movslq tam_imag(%rip), %rbx
shlq $2, %rbx
movq %rbx, %rdi
callq malloc
movq %rax, 24(%rsp) # 8-byte Spill
leaq 144(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
movslq tam_imag(%rip), %rbx
shlq $2, %rbx
movq %rbx, %rdi
callq malloc
movq %rax, %r13
leaq 80(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
movslq tam_imag(%rip), %rbx
shlq $2, %rbx
movq %rbx, %rdi
callq malloc
movq %rax, 48(%rsp) # 8-byte Spill
leaq 72(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
movslq tam_imag(%rip), %rsi
shlq $2, %rsi
leaq 136(%rsp), %rdi
callq hipMalloc
movslq tam_imag(%rip), %rsi
shlq $2, %rsi
leaq 128(%rsp), %rdi
callq hipMalloc
movslq tam_imag(%rip), %rsi
shlq $2, %rsi
leaq 120(%rsp), %rdi
callq hipMalloc
movslq tam_imag(%rip), %rsi
shlq $2, %rsi
leaq 152(%rsp), %rdi
callq hipMalloc
movslq tam_imag(%rip), %rsi
shlq $2, %rsi
leaq 112(%rsp), %rdi
callq hipMalloc
movslq tam_imag(%rip), %rbx
shlq $2, %rbx
movq %rbx, %rdi
callq malloc
movq %rax, 8(%rsp) # 8-byte Spill
leaq 16(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
movq %r15, 96(%rsp) # 8-byte Spill
cmpl %r15d, %r14d
jle .LBB1_1
.LBB1_11: # %._crit_edge76
movl $.Lstr, %edi
callq puts@PLT
movl $.L.str.11, %edi
movl $.L.str.12, %esi
callq fopen
movq %rax, %rbx
cmpl $0, dimx(%rip)
movq 24(%rsp), %r12 # 8-byte Reload
jle .LBB1_17
# %bb.12: # %.preheader.preheader
xorl %r14d, %r14d
movq 8(%rsp), %rbp # 8-byte Reload
jmp .LBB1_13
.p2align 4, 0x90
.LBB1_16: # %._crit_edge79
# in Loop: Header=BB1_13 Depth=1
movl $10, %edi
movq %rbx, %rsi
callq fputc@PLT
incl %r14d
cmpl dimx(%rip), %r14d
jge .LBB1_17
.LBB1_13: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_15 Depth 2
movl dimy(%rip), %eax
testl %eax, %eax
jle .LBB1_16
# %bb.14: # %.lr.ph78.preheader
# in Loop: Header=BB1_13 Depth=1
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB1_15: # %.lr.ph78
# Parent Loop BB1_13 Depth=1
# => This Inner Loop Header: Depth=2
imull %r14d, %eax
cltq
addq %r15, %rax
movss (%rbp,%rax,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.13, %esi
movq %rbx, %rdi
movb $1, %al
callq fprintf
movl dimy(%rip), %eax
incq %r15
cmpl %eax, %r15d
jl .LBB1_15
jmp .LBB1_16
.LBB1_17: # %._crit_edge81
movq %rbx, %rdi
callq fclose
movq 8(%rsp), %rdi # 8-byte Reload
callq free
movq %r12, %rdi
callq free
movq %r13, %rdi
callq free
movq 48(%rsp), %rdi # 8-byte Reload
callq free
movq 16(%rsp), %rdi
callq hipFree
movq 112(%rsp), %rdi
callq hipFree
movq 152(%rsp), %rdi
callq hipFree
movq 144(%rsp), %rdi
callq hipFree
movq 80(%rsp), %rdi
callq hipFree
movq 72(%rsp), %rdi
callq hipFree
movq 136(%rsp), %rdi
callq hipFree
movq 128(%rsp), %rdi
callq hipFree
movq 120(%rsp), %rdi
callq hipFree
callq clock
xorps %xmm0, %xmm0
cvtsi2ss %rax, %xmm0
cvtsi2ssq 88(%rsp), %xmm1 # 8-byte Folded Reload
subss %xmm1, %xmm0
divss .LCPI1_0(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movl $.L.str.15, %edi
movb $1, %al
callq printf
xorl %eax, %eax
addq $248, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_1: # %.lr.ph75
.cfi_def_cfa_offset 304
movq %r13, 56(%rsp) # 8-byte Spill
movq 24(%rsp), %rbp # 8-byte Reload
jmp .LBB1_2
.p2align 4, 0x90
.LBB1_8: # %._crit_edge71
# in Loop: Header=BB1_2 Depth=1
movq 40(%rsp), %rdi # 8-byte Reload
callq fclose
movq 64(%rsp), %rdi # 8-byte Reload
callq fclose
movq 32(%rsp), %rdi # 8-byte Reload
callq fclose
movq 80(%rsp), %rdi
movslq tam_imag(%rip), %rdx
shlq $2, %rdx
movq 56(%rsp), %r13 # 8-byte Reload
movq %r13, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $85899346267, %rdi # imm = 0x140000015B
movl $1, %esi
movabsq $68719476749, %rdx # imm = 0x100000000D
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
je .LBB1_9
.LBB1_10: # in Loop: Header=BB1_2 Depth=1
movl $.Lstr.1, %edi
callq puts@PLT
movq 16(%rsp), %rsi
movslq tam_imag(%rip), %rdx
shlq $2, %rdx
movq 8(%rsp), %rdi # 8-byte Reload
movl $2, %ecx
callq hipMemcpy
movl $.Lstr.2, %edi
callq puts@PLT
movq 104(%rsp), %rcx # 8-byte Reload
leal 1(%rcx), %eax
cmpl 96(%rsp), %ecx # 4-byte Folded Reload
movl %eax, %r14d
je .LBB1_11
.LBB1_2: # =>This Loop Header: Depth=1
# Child Loop BB1_4 Depth 2
# Child Loop BB1_6 Depth 3
movl $.L.str, %edi
movl %r14d, %esi
xorl %eax, %eax
callq printf
movb $0, 7(%rsp)
movl $.L.str.1, %esi
movl $.L.str.2, %edx
movl $.L.str.3, %r8d
leaq 7(%rsp), %rbx
movq %rbx, %rdi
movl %r14d, %ecx
xorl %eax, %eax
callq sprintf
movl $.L.str.4, %esi
movq %rbx, %rdi
callq fopen
movq %rax, 40(%rsp) # 8-byte Spill
movb $0, 6(%rsp)
movl $.L.str.1, %esi
movl $.L.str.2, %edx
movl $.L.str.5, %r8d
leaq 6(%rsp), %rbx
movq %rbx, %rdi
movl %r14d, %ecx
xorl %eax, %eax
callq sprintf
movl $.L.str.4, %esi
movq %rbx, %rdi
callq fopen
movq %rax, 64(%rsp) # 8-byte Spill
movb $0, 5(%rsp)
movl $.L.str.1, %esi
movl $.L.str.2, %edx
movl $.L.str.6, %r8d
leaq 5(%rsp), %rbx
movq %rbx, %rdi
movq %r14, 104(%rsp) # 8-byte Spill
movl %r14d, %ecx
xorl %eax, %eax
callq sprintf
movl $.L.str.4, %esi
movq %rbx, %rdi
callq fopen
movq %rax, 32(%rsp) # 8-byte Spill
cmpl $0, dimx(%rip)
jle .LBB1_8
# %bb.3: # %.preheader68.preheader
# in Loop: Header=BB1_2 Depth=1
xorl %r14d, %r14d
jmp .LBB1_4
.p2align 4, 0x90
.LBB1_7: # %._crit_edge
# in Loop: Header=BB1_4 Depth=2
incl %r14d
cmpl dimx(%rip), %r14d
jge .LBB1_8
.LBB1_4: # %.preheader68
# Parent Loop BB1_2 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB1_6 Depth 3
movl dimy(%rip), %eax
testl %eax, %eax
movq 40(%rsp), %r13 # 8-byte Reload
movq 32(%rsp), %rbx # 8-byte Reload
jle .LBB1_7
# %bb.5: # %.lr.ph.preheader
# in Loop: Header=BB1_4 Depth=2
movslq %r14d, %r15
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB1_6: # %.lr.ph
# Parent Loop BB1_2 Depth=1
# Parent Loop BB1_4 Depth=2
# => This Inner Loop Header: Depth=3
imull %r14d, %eax
cltq
addq %r12, %rax
leaq (,%rax,4), %rdx
addq %rbp, %rdx
movl $.L.str.7, %esi
movq %r13, %rdi
xorl %eax, %eax
callq __isoc23_fscanf
movslq dimy(%rip), %rax
imulq %r15, %rax
addq %r12, %rax
movq 56(%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax,4), %rdx
movl $.L.str.7, %esi
movq 64(%rsp), %rdi # 8-byte Reload
xorl %eax, %eax
callq __isoc23_fscanf
movslq dimy(%rip), %rax
imulq %r15, %rax
addq %r12, %rax
movq 48(%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax,4), %rdx
movl $.L.str.7, %esi
movq %rbx, %rdi
xorl %eax, %eax
callq __isoc23_fscanf
movl dimy(%rip), %eax
incq %r12
cmpl %eax, %r12d
jl .LBB1_6
jmp .LBB1_7
.p2align 4, 0x90
.LBB1_9: # in Loop: Header=BB1_2 Depth=1
movq 72(%rsp), %rax
movq 16(%rsp), %rcx
movq %rax, 216(%rsp)
movq %rcx, 208(%rsp)
leaq 216(%rsp), %rax
movq %rax, 224(%rsp)
leaq 208(%rsp), %rax
movq %rax, 232(%rsp)
leaq 192(%rsp), %rdi
leaq 176(%rsp), %rsi
leaq 168(%rsp), %rdx
leaq 160(%rsp), %rcx
callq __hipPopCallConfiguration
movq 192(%rsp), %rsi
movl 200(%rsp), %edx
movq 176(%rsp), %rcx
movl 184(%rsp), %r8d
movl $_Z8VarianzaPiPf, %edi
leaq 224(%rsp), %r9
pushq 160(%rsp)
.cfi_adjust_cfa_offset 8
pushq 176(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB1_10
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8VarianzaPiPf, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type msk,@object # @msk
.data
.globl msk
.p2align 2, 0x0
msk:
.long 3 # 0x3
.size msk, 4
.type dimx,@object # @dimx
.globl dimx
.p2align 2, 0x0
dimx:
.long 1040 # 0x410
.size dimx, 4
.type dimy,@object # @dimy
.globl dimy
.p2align 2, 0x0
dimy:
.long 1388 # 0x56c
.size dimy, 4
.type tam_imag,@object # @tam_imag
.globl tam_imag
.p2align 2, 0x0
tam_imag:
.long 1443520 # 0x1606c0
.size tam_imag, 4
.type _Z8VarianzaPiPf,@object # @_Z8VarianzaPiPf
.section .rodata,"a",@progbits
.globl _Z8VarianzaPiPf
.p2align 3, 0x0
_Z8VarianzaPiPf:
.quad _Z23__device_stub__VarianzaPiPf
.size _Z8VarianzaPiPf, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "d=%d \n"
.size .L.str, 7
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "%s%d%s"
.size .L.str.1, 7
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "RGB/"
.size .L.str.2, 5
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "/R"
.size .L.str.3, 3
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "r+"
.size .L.str.4, 3
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "/G"
.size .L.str.5, 3
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "/B"
.size .L.str.6, 3
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "%d"
.size .L.str.7, 3
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz "Resultados/VarUltima"
.size .L.str.11, 21
.type .L.str.12,@object # @.str.12
.L.str.12:
.asciz "w+"
.size .L.str.12, 3
.type .L.str.13,@object # @.str.13
.L.str.13:
.asciz "%f "
.size .L.str.13, 4
.type .L.str.15,@object # @.str.15
.L.str.15:
.asciz "\ntiempo de procesamiento de varianzas: %6.3fs\n"
.size .L.str.15, 47
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z8VarianzaPiPf"
.size .L__unnamed_1, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "***Sale del for "
.size .Lstr, 17
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "Despues de kernel "
.size .Lstr.1, 19
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "Despues de resultado a host "
.size .Lstr.2, 29
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__VarianzaPiPf
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8VarianzaPiPf
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z8VarianzaPiPf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ ULDC UR4, c[0x0][0xc] ; /* 0x0000030000047ab9 */
/* 0x000fe40000000800 */
/*0030*/ ULDC UR5, c[0x0][0x0] ; /* 0x0000000000057ab9 */
/* 0x000fe20000000800 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e220000002100 */
/*0050*/ UIMAD UR4, UR4, UR5, URZ ; /* 0x00000005040472a4 */
/* 0x000fc6000f8e023f */
/*0060*/ S2R R5, SR_CTAID.Y ; /* 0x0000000000057919 */
/* 0x000e680000002600 */
/*0070*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e620000002200 */
/*0080*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fe400078e0203 */
/*0090*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fe400078e00ff */
/*00a0*/ IMAD R5, R5, c[0x0][0x4], R2 ; /* 0x0000010005057a24 */
/* 0x002fc800078e0202 */
/*00b0*/ IMAD R4, R5, UR4, R0 ; /* 0x0000000405047c24 */
/* 0x000fe2000f8e0200 */
/*00c0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*00d0*/ IMAD.WIDE R2, R4.reuse, R3, c[0x0][0x168] ; /* 0x00005a0004027625 */
/* 0x040fe200078e0203 */
/*00e0*/ ISETP.GT.AND P0, PT, R4, 0x1606bf, PT ; /* 0x001606bf0400780c */
/* 0x000fc80003f04270 */
/*00f0*/ STG.E [R2.64], RZ ; /* 0x000000ff02007986 */
/* 0x0001f2000c101904 */
/*0100*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0110*/ ISETP.NE.AND P1, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe40003f25270 */
/*0120*/ SHF.R.S32.HI R7, RZ, 0x1f, R4 ; /* 0x0000001fff077819 */
/* 0x000fc40000011404 */
/*0130*/ ISETP.EQ.OR P0, PT, R0, RZ, !P1 ; /* 0x000000ff0000720c */
/* 0x000fe40004f02670 */
/*0140*/ LEA R8, P2, R4, c[0x0][0x160], 0x2 ; /* 0x0000580004087a11 */
/* 0x000fc800078410ff */
/*0150*/ LEA.HI.X R9, R4, c[0x0][0x164], R7, 0x2, P2 ; /* 0x0000590004097a11 */
/* 0x000fe400010f1407 */
/*0160*/ ISETP.NE.AND P2, PT, R5, 0x56c, PT ; /* 0x0000056c0500780c */
/* 0x000fc60003f45270 */
/*0170*/ @P1 LDG.E R10, [R8.64+-0x4] ; /* 0xfffffc04080a1981 */
/* 0x000ea8000c1e1900 */
/*0180*/ @!P0 LDG.E R7, [R8.64+-0x15b4] ; /* 0xffea4c0408078981 */
/* 0x000ee8000c1e1900 */
/*0190*/ LDG.E R5, [R8.64] ; /* 0x0000000408057981 */
/* 0x000f28000c1e1900 */
/*01a0*/ @P2 LDG.E R11, [R8.64+0x4] ; /* 0x00000404080b2981 */
/* 0x000f62000c1e1900 */
/*01b0*/ IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff067224 */
/* 0x000fe200078e00ff */
/*01c0*/ HFMA2.MMA R0, -RZ, RZ, 0, 0 ; /* 0x00000000ff007435 */
/* 0x000fe200000001ff */
/*01d0*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x000fe200078e00ff */
/*01e0*/ BSSY B0, 0x380 ; /* 0x0000019000007945 */
/* 0x000fe60003800000 */
/*01f0*/ @!P0 I2F R6, R7 ; /* 0x0000000700068306 */
/* 0x008e700000201400 */
/*0200*/ @P1 I2F R0, R10 ; /* 0x0000000a00001306 */
/* 0x004eb00000201400 */
/*0210*/ I2F R5, R5 ; /* 0x0000000500057306 */
/* 0x010ee20000201400 */
/*0220*/ FADD R12, R6, 5 ; /* 0x40a00000060c7421 */
/* 0x002fce0000000000 */
/*0230*/ @P2 I2F R4, R11 ; /* 0x0000000b00042306 */
/* 0x020e620000201400 */
/*0240*/ FADD R13, R12, 8 ; /* 0x410000000c0d7421 */
/* 0x000fc80000000000 */
/*0250*/ FADD R12, R13, R0 ; /* 0x000000000d0c7221 */
/* 0x004fc80000000000 */
/*0260*/ FADD R9, R12, R5 ; /* 0x000000050c097221 */
/* 0x008fc80000000000 */
/*0270*/ FADD R9, R9, R4 ; /* 0x0000000409097221 */
/* 0x002fc80000000000 */
/*0280*/ FADD R9, R9, 2 ; /* 0x4000000009097421 */
/* 0x000fc80000000000 */
/*0290*/ FADD R9, R9, 5 ; /* 0x40a0000009097421 */
/* 0x000fe20000000000 */
/*02a0*/ MOV R7, 0x41100000 ; /* 0x4110000000077802 */
/* 0x000fe20000000f00 */
/*02b0*/ IMAD.MOV.U32 R12, RZ, RZ, 0x3de38e39 ; /* 0x3de38e39ff0c7424 */
/* 0x000fe400078e00ff */
/*02c0*/ FADD R11, R9, 4 ; /* 0x40800000090b7421 */
/* 0x000fe40000000000 */
/*02d0*/ FFMA R8, R12, -R7, 1 ; /* 0x3f8000000c087423 */
/* 0x000fe40000000807 */
/*02e0*/ FCHK P0, R11, 9 ; /* 0x411000000b007902 */
/* 0x000e640000000000 */
/*02f0*/ FFMA R8, R8, R12, 0.11111111193895339966 ; /* 0x3de38e3908087423 */
/* 0x000fc8000000000c */
/*0300*/ FFMA R9, R11, R8, RZ ; /* 0x000000080b097223 */
/* 0x000fc800000000ff */
/*0310*/ FFMA R10, R9, -9, R11 ; /* 0xc1100000090a7823 */
/* 0x000fc8000000000b */
/*0320*/ FFMA R9, R8, R10, R9 ; /* 0x0000000a08097223 */
/* 0x000fe20000000009 */
/*0330*/ @!P0 BRA 0x370 ; /* 0x0000003000008947 */
/* 0x002fea0003800000 */
/*0340*/ MOV R8, 0x360 ; /* 0x0000036000087802 */
/* 0x000fe40000000f00 */
/*0350*/ CALL.REL.NOINC 0x590 ; /* 0x0000023000007944 */
/* 0x001fea0003c00000 */
/*0360*/ IMAD.MOV.U32 R9, RZ, RZ, R7 ; /* 0x000000ffff097224 */
/* 0x001fe400078e0007 */
/*0370*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0380*/ FADD R6, R9.reuse, -R6 ; /* 0x8000000609067221 */
/* 0x040fe20000000000 */
/*0390*/ BSSY B0, 0x570 ; /* 0x000001d000007945 */
/* 0x000fe20003800000 */
/*03a0*/ FADD R11, R9.reuse, -5 ; /* 0xc0a00000090b7421 */
/* 0x040fe40000000000 */
/*03b0*/ FFMA R6, R6, R6, RZ ; /* 0x0000000606067223 */
/* 0x000fe400000000ff */
/*03c0*/ FADD R7, R9, -8 ; /* 0xc100000009077421 */
/* 0x000fe40000000000 */
/*03d0*/ FFMA R6, R11, R11, R6 ; /* 0x0000000b0b067223 */
/* 0x000fe40000000006 */
/*03e0*/ FADD R13, R9, -R0 ; /* 0x80000000090d7221 */
/* 0x000fc40000000000 */
/*03f0*/ FFMA R6, R7, R7, R6 ; /* 0x0000000707067223 */
/* 0x000fe40000000006 */
/*0400*/ FADD R5, -R5, R9 ; /* 0x0000000905057221 */
/* 0x000fe40000000100 */
/*0410*/ FFMA R6, R13, R13, R6 ; /* 0x0000000d0d067223 */
/* 0x000fe40000000006 */
/*0420*/ FADD R7, R9, -R4 ; /* 0x8000000409077221 */
/* 0x000fe40000000000 */
/*0430*/ FFMA R6, R5, R5, R6 ; /* 0x0000000505067223 */
/* 0x000fe40000000006 */
/*0440*/ FADD R5, R9, -2 ; /* 0xc000000009057421 */
/* 0x000fc40000000000 */
/*0450*/ FFMA R6, R7, R7, R6 ; /* 0x0000000707067223 */
/* 0x000fe20000000006 */
/*0460*/ HFMA2.MMA R7, -RZ, RZ, 2.53125, 0 ; /* 0x41100000ff077435 */
/* 0x000fe200000001ff */
/*0470*/ FADD R9, R9, -4 ; /* 0xc080000009097421 */
/* 0x000fe40000000000 */
/*0480*/ FFMA R6, R5, R5, R6 ; /* 0x0000000505067223 */
/* 0x000fe40000000006 */
/*0490*/ IMAD.MOV.U32 R0, RZ, RZ, 0x3de38e39 ; /* 0x3de38e39ff007424 */
/* 0x000fe400078e00ff */
/*04a0*/ FFMA R6, R11, R11, R6 ; /* 0x0000000b0b067223 */
/* 0x000fc60000000006 */
/*04b0*/ FFMA R5, R0, -R7, 1 ; /* 0x3f80000000057423 */
/* 0x000fe40000000807 */
/*04c0*/ FFMA R11, R9, R9, R6 ; /* 0x00000009090b7223 */
/* 0x000fe40000000006 */
/*04d0*/ FFMA R4, R5, R0, 0.11111111193895339966 ; /* 0x3de38e3905047423 */
/* 0x000fe40000000000 */
/*04e0*/ FCHK P0, R11, 9 ; /* 0x411000000b007902 */
/* 0x000e640000000000 */
/*04f0*/ FFMA R0, R4, R11, RZ ; /* 0x0000000b04007223 */
/* 0x000fc800000000ff */
/*0500*/ FFMA R5, R0, -9, R11 ; /* 0xc110000000057823 */
/* 0x000fc8000000000b */
/*0510*/ FFMA R5, R4, R5, R0 ; /* 0x0000000504057223 */
/* 0x000fe20000000000 */
/*0520*/ @!P0 BRA 0x560 ; /* 0x0000003000008947 */
/* 0x002fea0003800000 */
/*0530*/ MOV R8, 0x550 ; /* 0x0000055000087802 */
/* 0x000fe40000000f00 */
/*0540*/ CALL.REL.NOINC 0x590 ; /* 0x0000004000007944 */
/* 0x001fea0003c00000 */
/*0550*/ IMAD.MOV.U32 R5, RZ, RZ, R7 ; /* 0x000000ffff057224 */
/* 0x001fe400078e0007 */
/*0560*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0570*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*0580*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0590*/ SHF.R.U32.HI R10, RZ, 0x17, R7 ; /* 0x00000017ff0a7819 */
/* 0x000fe20000011607 */
/*05a0*/ BSSY B1, 0xbd0 ; /* 0x0000062000017945 */
/* 0x000fe20003800000 */
/*05b0*/ SHF.R.U32.HI R9, RZ, 0x17, R11 ; /* 0x00000017ff097819 */
/* 0x000fe4000001160b */
/*05c0*/ LOP3.LUT R10, R10, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff0a0a7812 */
/* 0x000fe400078ec0ff */
/*05d0*/ LOP3.LUT R15, R9, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff090f7812 */
/* 0x000fe400078ec0ff */
/*05e0*/ IADD3 R12, R10, -0x1, RZ ; /* 0xffffffff0a0c7810 */
/* 0x000fc40007ffe0ff */
/*05f0*/ IADD3 R13, R15, -0x1, RZ ; /* 0xffffffff0f0d7810 */
/* 0x000fe40007ffe0ff */
/*0600*/ ISETP.GT.U32.AND P0, PT, R12, 0xfd, PT ; /* 0x000000fd0c00780c */
/* 0x000fc80003f04070 */
/*0610*/ ISETP.GT.U32.OR P0, PT, R13, 0xfd, P0 ; /* 0x000000fd0d00780c */
/* 0x000fda0000704470 */
/*0620*/ @!P0 IMAD.MOV.U32 R9, RZ, RZ, RZ ; /* 0x000000ffff098224 */
/* 0x000fe200078e00ff */
/*0630*/ @!P0 BRA 0x7b0 ; /* 0x0000017000008947 */
/* 0x000fea0003800000 */
/*0640*/ FSETP.GTU.FTZ.AND P0, PT, |R11|, +INF , PT ; /* 0x7f8000000b00780b */
/* 0x000fe40003f1c200 */
/*0650*/ FSETP.GTU.FTZ.AND P1, PT, |R7|, +INF , PT ; /* 0x7f8000000700780b */
/* 0x000fc80003f3c200 */
/*0660*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000703570 */
/*0670*/ @P0 BRA 0xbb0 ; /* 0x0000053000000947 */
/* 0x000fea0003800000 */
/*0680*/ LOP3.LUT P0, RZ, R7, 0x7fffffff, R11, 0xc8, !PT ; /* 0x7fffffff07ff7812 */
/* 0x000fda000780c80b */
/*0690*/ @!P0 BRA 0xb90 ; /* 0x000004f000008947 */
/* 0x000fea0003800000 */
/*06a0*/ FSETP.NEU.FTZ.AND P2, PT, |R11|, +INF , PT ; /* 0x7f8000000b00780b */
/* 0x000fe40003f5d200 */
/*06b0*/ FSETP.NEU.FTZ.AND P1, PT, |R7|, +INF , PT ; /* 0x7f8000000700780b */
/* 0x000fe40003f3d200 */
/*06c0*/ FSETP.NEU.FTZ.AND P0, PT, |R11|, +INF , PT ; /* 0x7f8000000b00780b */
/* 0x000fd60003f1d200 */
/*06d0*/ @!P1 BRA !P2, 0xb90 ; /* 0x000004b000009947 */
/* 0x000fea0005000000 */
/*06e0*/ LOP3.LUT P2, RZ, R11, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff0bff7812 */
/* 0x000fc8000784c0ff */
/*06f0*/ PLOP3.LUT P1, PT, P1, P2, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000f24572 */
/*0700*/ @P1 BRA 0xb70 ; /* 0x0000046000001947 */
/* 0x000fea0003800000 */
/*0710*/ LOP3.LUT P1, RZ, R7, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff07ff7812 */
/* 0x000fc8000782c0ff */
/*0720*/ PLOP3.LUT P0, PT, P0, P1, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000702572 */
/*0730*/ @P0 BRA 0xb40 ; /* 0x0000040000000947 */
/* 0x000fea0003800000 */
/*0740*/ ISETP.GE.AND P0, PT, R13, RZ, PT ; /* 0x000000ff0d00720c */
/* 0x000fe40003f06270 */
/*0750*/ ISETP.GE.AND P1, PT, R12, RZ, PT ; /* 0x000000ff0c00720c */
/* 0x000fd60003f26270 */
/*0760*/ @P0 MOV R9, RZ ; /* 0x000000ff00090202 */
/* 0x000fe20000000f00 */
/*0770*/ @!P0 IMAD.MOV.U32 R9, RZ, RZ, -0x40 ; /* 0xffffffc0ff098424 */
/* 0x000fe400078e00ff */
/*0780*/ @!P0 FFMA R11, R11, 1.84467440737095516160e+19, RZ ; /* 0x5f8000000b0b8823 */
/* 0x000fe400000000ff */
/*0790*/ @!P1 FFMA R7, R7, 1.84467440737095516160e+19, RZ ; /* 0x5f80000007079823 */
/* 0x000fe200000000ff */
/*07a0*/ @!P1 IADD3 R9, R9, 0x40, RZ ; /* 0x0000004009099810 */
/* 0x000fe40007ffe0ff */
/*07b0*/ LEA R12, R10, 0xc0800000, 0x17 ; /* 0xc08000000a0c7811 */
/* 0x000fe200078eb8ff */
/*07c0*/ BSSY B2, 0xb30 ; /* 0x0000036000027945 */
/* 0x000fe80003800000 */
/*07d0*/ IMAD.IADD R13, R7, 0x1, -R12 ; /* 0x00000001070d7824 */
/* 0x000fe200078e0a0c */
/*07e0*/ IADD3 R12, R15, -0x7f, RZ ; /* 0xffffff810f0c7810 */
/* 0x000fc60007ffe0ff */
/*07f0*/ MUFU.RCP R7, R13 ; /* 0x0000000d00077308 */
/* 0x000e220000001000 */
/*0800*/ FADD.FTZ R14, -R13, -RZ ; /* 0x800000ff0d0e7221 */
/* 0x000fe40000010100 */
/*0810*/ IMAD R11, R12.reuse, -0x800000, R11 ; /* 0xff8000000c0b7824 */
/* 0x040fe200078e020b */
/*0820*/ IADD3 R12, R12, 0x7f, -R10 ; /* 0x0000007f0c0c7810 */
/* 0x000fc80007ffe80a */
/*0830*/ IADD3 R12, R12, R9, RZ ; /* 0x000000090c0c7210 */
/* 0x000fe20007ffe0ff */
/*0840*/ FFMA R16, R7, R14, 1 ; /* 0x3f80000007107423 */
/* 0x001fc8000000000e */
/*0850*/ FFMA R18, R7, R16, R7 ; /* 0x0000001007127223 */
/* 0x000fc80000000007 */
/*0860*/ FFMA R7, R11, R18, RZ ; /* 0x000000120b077223 */
/* 0x000fc800000000ff */
/*0870*/ FFMA R16, R14, R7, R11 ; /* 0x000000070e107223 */
/* 0x000fc8000000000b */
/*0880*/ FFMA R15, R18, R16, R7 ; /* 0x00000010120f7223 */
/* 0x000fc80000000007 */
/*0890*/ FFMA R14, R14, R15, R11 ; /* 0x0000000f0e0e7223 */
/* 0x000fc8000000000b */
/*08a0*/ FFMA R7, R18, R14, R15 ; /* 0x0000000e12077223 */
/* 0x000fca000000000f */
/*08b0*/ SHF.R.U32.HI R10, RZ, 0x17, R7 ; /* 0x00000017ff0a7819 */
/* 0x000fc80000011607 */
/*08c0*/ LOP3.LUT R10, R10, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff0a0a7812 */
/* 0x000fca00078ec0ff */
/*08d0*/ IMAD.IADD R13, R10, 0x1, R12 ; /* 0x000000010a0d7824 */
/* 0x000fca00078e020c */
/*08e0*/ IADD3 R9, R13, -0x1, RZ ; /* 0xffffffff0d097810 */
/* 0x000fc80007ffe0ff */
/*08f0*/ ISETP.GE.U32.AND P0, PT, R9, 0xfe, PT ; /* 0x000000fe0900780c */
/* 0x000fda0003f06070 */
/*0900*/ @!P0 BRA 0xb10 ; /* 0x0000020000008947 */
/* 0x000fea0003800000 */
/*0910*/ ISETP.GT.AND P0, PT, R13, 0xfe, PT ; /* 0x000000fe0d00780c */
/* 0x000fda0003f04270 */
/*0920*/ @P0 BRA 0xae0 ; /* 0x000001b000000947 */
/* 0x000fea0003800000 */
/*0930*/ ISETP.GE.AND P0, PT, R13, 0x1, PT ; /* 0x000000010d00780c */
/* 0x000fda0003f06270 */
/*0940*/ @P0 BRA 0xb20 ; /* 0x000001d000000947 */
/* 0x000fea0003800000 */
/*0950*/ ISETP.GE.AND P0, PT, R13, -0x18, PT ; /* 0xffffffe80d00780c */
/* 0x000fe40003f06270 */
/*0960*/ LOP3.LUT R7, R7, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000007077812 */
/* 0x000fd600078ec0ff */
/*0970*/ @!P0 BRA 0xb20 ; /* 0x000001a000008947 */
/* 0x000fea0003800000 */
/*0980*/ FFMA.RZ R9, R18.reuse, R14.reuse, R15.reuse ; /* 0x0000000e12097223 */
/* 0x1c0fe2000000c00f */
/*0990*/ IADD3 R12, R13.reuse, 0x20, RZ ; /* 0x000000200d0c7810 */
/* 0x040fe20007ffe0ff */
/*09a0*/ FFMA.RM R10, R18.reuse, R14.reuse, R15.reuse ; /* 0x0000000e120a7223 */
/* 0x1c0fe2000000400f */
/*09b0*/ ISETP.NE.AND P2, PT, R13, RZ, PT ; /* 0x000000ff0d00720c */
/* 0x000fe40003f45270 */
/*09c0*/ LOP3.LUT R11, R9, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff090b7812 */
/* 0x000fe200078ec0ff */
/*09d0*/ FFMA.RP R9, R18, R14, R15 ; /* 0x0000000e12097223 */
/* 0x000fe2000000800f */
/*09e0*/ ISETP.NE.AND P1, PT, R13, RZ, PT ; /* 0x000000ff0d00720c */
/* 0x000fe20003f25270 */
/*09f0*/ IMAD.MOV R13, RZ, RZ, -R13 ; /* 0x000000ffff0d7224 */
/* 0x000fe200078e0a0d */
/*0a00*/ LOP3.LUT R11, R11, 0x800000, RZ, 0xfc, !PT ; /* 0x008000000b0b7812 */
/* 0x000fe400078efcff */
/*0a10*/ FSETP.NEU.FTZ.AND P0, PT, R9, R10, PT ; /* 0x0000000a0900720b */
/* 0x000fc40003f1d000 */
/*0a20*/ SHF.L.U32 R12, R11, R12, RZ ; /* 0x0000000c0b0c7219 */
/* 0x000fe400000006ff */
/*0a30*/ SEL R10, R13, RZ, P2 ; /* 0x000000ff0d0a7207 */
/* 0x000fe40001000000 */
/*0a40*/ ISETP.NE.AND P1, PT, R12, RZ, P1 ; /* 0x000000ff0c00720c */
/* 0x000fe40000f25270 */
/*0a50*/ SHF.R.U32.HI R10, RZ, R10, R11 ; /* 0x0000000aff0a7219 */
/* 0x000fe4000001160b */
/*0a60*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40000703570 */
/*0a70*/ SHF.R.U32.HI R12, RZ, 0x1, R10 ; /* 0x00000001ff0c7819 */
/* 0x000fc4000001160a */
/*0a80*/ SEL R9, RZ, 0x1, !P0 ; /* 0x00000001ff097807 */
/* 0x000fc80004000000 */
/*0a90*/ LOP3.LUT R9, R9, 0x1, R12, 0xf8, !PT ; /* 0x0000000109097812 */
/* 0x000fc800078ef80c */
/*0aa0*/ LOP3.LUT R9, R9, R10, RZ, 0xc0, !PT ; /* 0x0000000a09097212 */
/* 0x000fc800078ec0ff */
/*0ab0*/ IADD3 R12, R12, R9, RZ ; /* 0x000000090c0c7210 */
/* 0x000fc80007ffe0ff */
/*0ac0*/ LOP3.LUT R7, R12, R7, RZ, 0xfc, !PT ; /* 0x000000070c077212 */
/* 0x000fe200078efcff */
/*0ad0*/ BRA 0xb20 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*0ae0*/ LOP3.LUT R7, R7, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000007077812 */
/* 0x000fc800078ec0ff */
/*0af0*/ LOP3.LUT R7, R7, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000007077812 */
/* 0x000fe200078efcff */
/*0b00*/ BRA 0xb20 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0b10*/ IMAD R7, R12, 0x800000, R7 ; /* 0x008000000c077824 */
/* 0x000fe400078e0207 */
/*0b20*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*0b30*/ BRA 0xbc0 ; /* 0x0000008000007947 */
/* 0x000fea0003800000 */
/*0b40*/ LOP3.LUT R7, R7, 0x80000000, R11, 0x48, !PT ; /* 0x8000000007077812 */
/* 0x000fc800078e480b */
/*0b50*/ LOP3.LUT R7, R7, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000007077812 */
/* 0x000fe200078efcff */
/*0b60*/ BRA 0xbc0 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*0b70*/ LOP3.LUT R7, R7, 0x80000000, R11, 0x48, !PT ; /* 0x8000000007077812 */
/* 0x000fe200078e480b */
/*0b80*/ BRA 0xbc0 ; /* 0x0000003000007947 */
/* 0x000fea0003800000 */
/*0b90*/ MUFU.RSQ R7, -QNAN ; /* 0xffc0000000077908 */
/* 0x000e220000001400 */
/*0ba0*/ BRA 0xbc0 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0bb0*/ FADD.FTZ R7, R11, R7 ; /* 0x000000070b077221 */
/* 0x000fe40000010000 */
/*0bc0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0bd0*/ HFMA2.MMA R9, -RZ, RZ, 0, 0 ; /* 0x00000000ff097435 */
/* 0x000fcc00000001ff */
/*0be0*/ RET.REL.NODEC R8 0x0 ; /* 0xfffff41008007950 */
/* 0x000fea0003c3ffff */
/*0bf0*/ BRA 0xbf0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0c00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z8VarianzaPiPf
.globl _Z8VarianzaPiPf
.p2align 8
.type _Z8VarianzaPiPf,@function
_Z8VarianzaPiPf:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x1c
s_load_b32 s4, s[0:1], 0x10
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s5, s2, 0xffff
s_lshr_b32 s2, s2, 16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[0:1], null, s14, s5, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s2, v[3:4]
s_mul_i32 s4, s4, s5
s_load_b64 s[2:3], s[0:1], 0x8
v_mad_u64_u32 v[6:7], null, s4, v1, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v7, 31, v6
v_lshlrev_b64 v[2:3], 2, v[6:7]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v9, vcc_lo, s2, v2
v_add_co_ci_u32_e32 v10, vcc_lo, s3, v3, vcc_lo
v_mov_b32_e32 v2, 0
s_mov_b32 s2, exec_lo
global_store_b32 v[9:10], v2, off
v_cmpx_gt_i32_e32 0x1606c0, v6
s_cbranch_execz .LBB0_12
s_load_b64 s[2:3], s[0:1], 0x0
v_cmp_ne_u32_e64 s0, 0, v0
v_cmp_ne_u32_e32 vcc_lo, 0, v1
v_mov_b32_e32 v0, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s0, s0, vcc_lo
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_3
v_lshlrev_b64 v[2:3], 2, v[6:7]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v0, s0, s2, v2
v_add_co_ci_u32_e64 v3, s0, s3, v3, s0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v2, s0, 0xfffff000, v0
v_add_co_ci_u32_e64 v3, s0, -1, v3, s0
global_load_b32 v0, v[2:3], off offset:-1460
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s1
v_mov_b32_e32 v5, 0
v_mov_b32_e32 v3, 0
s_and_saveexec_b32 s0, vcc_lo
s_cbranch_execz .LBB0_5
v_lshlrev_b64 v[2:3], 2, v[6:7]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s2, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
global_load_b32 v3, v[2:3], off offset:-4
.LBB0_5:
s_or_b32 exec_lo, exec_lo, s0
v_lshlrev_b64 v[6:7], 2, v[6:7]
s_mov_b32 s0, exec_lo
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v6, vcc_lo, s2, v6
v_add_co_ci_u32_e32 v7, vcc_lo, s3, v7, vcc_lo
global_load_b32 v4, v[6:7], off
v_cmpx_ne_u32_e32 0x56c, v1
s_cbranch_execz .LBB0_7
global_load_b32 v5, v[6:7], off offset:4
.LBB0_7:
s_or_b32 exec_lo, exec_lo, s0
v_dual_mov_b32 v1, 5 :: v_dual_mov_b32 v2, 8
v_mov_b32_e32 v6, 2
v_dual_mov_b32 v8, 4 :: v_dual_mov_b32 v11, 0
s_delay_alu instid0(VALU_DEP_3)
v_mov_b32_e32 v7, v1
s_mov_b64 s[0:1], 0
.LBB0_8:
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 m0, s0
s_add_u32 s0, s0, 1
s_waitcnt vmcnt(0)
v_movrels_b32_e32 v12, v0
s_addc_u32 s1, s1, 0
s_cmp_lg_u32 s0, 9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_f32_i32_e32 v12, v12
v_add_f32_e32 v11, v11, v12
s_cbranch_scc1 .LBB0_8
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_div_scale_f32 v12, null, 0x41100000, 0x41100000, v11
v_div_scale_f32 v15, vcc_lo, v11, 0x41100000, v11
s_mov_b64 s[0:1], 0
v_rcp_f32_e32 v13, v12
s_waitcnt_depctr 0xfff
v_fma_f32 v14, -v12, v13, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v13, v14, v13
v_mul_f32_e32 v14, v15, v13
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v16, -v12, v14, v15
v_fmac_f32_e32 v14, v16, v13
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v12, -v12, v14, v15
v_div_fmas_f32 v12, v12, v13, v14
s_delay_alu instid0(VALU_DEP_1)
v_div_fixup_f32 v12, v12, 0x41100000, v11
v_mov_b32_e32 v11, 0
.LBB0_10:
s_mov_b32 m0, s0
s_add_u32 s0, s0, 1
v_movrels_b32_e32 v13, v0
s_addc_u32 s1, s1, 0
s_cmp_lg_u32 s0, 9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_f32_i32_e32 v13, v13
v_sub_f32_e32 v13, v12, v13
s_delay_alu instid0(VALU_DEP_1)
v_fmac_f32_e32 v11, v13, v13
s_cbranch_scc1 .LBB0_10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_scale_f32 v0, null, 0x41100000, 0x41100000, v11
v_rcp_f32_e32 v1, v0
s_waitcnt_depctr 0xfff
v_fma_f32 v2, -v0, v1, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v1, v2, v1
v_div_scale_f32 v2, vcc_lo, v11, 0x41100000, v11
v_mul_f32_e32 v3, v2, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v4, -v0, v3, v2
v_fmac_f32_e32 v3, v4, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v0, -v0, v3, v2
v_div_fmas_f32 v0, v0, v1, v3
s_delay_alu instid0(VALU_DEP_1)
v_div_fixup_f32 v0, v0, 0x41100000, v11
global_store_b32 v[9:10], v0, off
.LBB0_12:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8VarianzaPiPf
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 17
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z8VarianzaPiPf, .Lfunc_end0-_Z8VarianzaPiPf
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8VarianzaPiPf
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z8VarianzaPiPf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 17
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00089181_00000000-6_10_var--topo+RGB-CUDA.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z29__device_stub__Z8VarianzaPiPfPiPf
.type _Z29__device_stub__Z8VarianzaPiPfPiPf, @function
_Z29__device_stub__Z8VarianzaPiPfPiPf:
.LFB2082:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z8VarianzaPiPf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z29__device_stub__Z8VarianzaPiPfPiPf, .-_Z29__device_stub__Z8VarianzaPiPfPiPf
.globl _Z8VarianzaPiPf
.type _Z8VarianzaPiPf, @function
_Z8VarianzaPiPf:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z8VarianzaPiPfPiPf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z8VarianzaPiPf, .-_Z8VarianzaPiPf
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "d=%d \n"
.LC1:
.string "RGB/"
.LC2:
.string "%s%d%s"
.LC3:
.string "/R"
.LC4:
.string "r+"
.LC5:
.string "/G"
.LC6:
.string "/B"
.LC7:
.string "%d"
.LC8:
.string "Despues de kernel \n"
.LC9:
.string "Despues de resultado a host \n"
.LC10:
.string "***Sale del for \n"
.LC11:
.string "w+"
.LC12:
.string "Resultados/VarUltima"
.LC13:
.string "%f "
.LC14:
.string "\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC16:
.string "\ntiempo de procesamiento de varianzas: %6.3fs\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $184, %rsp
.cfi_def_cfa_offset 240
movq %rsi, %rbp
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %rbx
movl %eax, 32(%rsp)
movq 16(%rbp), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %rbp
movl %eax, 52(%rsp)
call clock@PLT
movq %rax, %r13
movslq tam_imag(%rip), %r12
salq $2, %r12
movq %r12, %rdi
call malloc@PLT
movq %rax, 16(%rsp)
leaq 72(%rsp), %rdi
movq %r12, %rsi
call cudaMalloc@PLT
movslq tam_imag(%rip), %r12
salq $2, %r12
movq %r12, %rdi
call malloc@PLT
movq %rax, 8(%rsp)
leaq 80(%rsp), %rdi
movq %r12, %rsi
call cudaMalloc@PLT
movslq tam_imag(%rip), %r12
salq $2, %r12
movq %r12, %rdi
call malloc@PLT
movq %rax, 24(%rsp)
leaq 88(%rsp), %rdi
movq %r12, %rsi
call cudaMalloc@PLT
movslq tam_imag(%rip), %rsi
salq $2, %rsi
leaq 96(%rsp), %rdi
call cudaMalloc@PLT
movslq tam_imag(%rip), %rsi
salq $2, %rsi
leaq 104(%rsp), %rdi
call cudaMalloc@PLT
movslq tam_imag(%rip), %rsi
salq $2, %rsi
leaq 112(%rsp), %rdi
call cudaMalloc@PLT
movslq tam_imag(%rip), %rsi
salq $2, %rsi
leaq 64(%rsp), %rdi
call cudaMalloc@PLT
movslq tam_imag(%rip), %rsi
salq $2, %rsi
leaq 120(%rsp), %rdi
call cudaMalloc@PLT
movslq tam_imag(%rip), %r12
salq $2, %r12
movq %r12, %rdi
call malloc@PLT
movq %rax, 40(%rsp)
leaq 128(%rsp), %rdi
movq %r12, %rsi
call cudaMalloc@PLT
cmpl %ebx, %ebp
jl .L12
leaq .LC7(%rip), %rbx
movq %r13, 56(%rsp)
jmp .L18
.L15:
imull %r15d, %eax
addl %ebp, %eax
cltq
movq 16(%rsp), %rcx
leaq (%rcx,%rax,4), %rdx
movq %rbx, %rsi
movq %r14, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
movl %r15d, %eax
imull dimy(%rip), %eax
addl %ebp, %eax
cltq
movq 8(%rsp), %rcx
leaq (%rcx,%rax,4), %rdx
movq %rbx, %rsi
movq %r13, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
movl %r15d, %eax
imull dimy(%rip), %eax
addl %ebp, %eax
cltq
movq 24(%rsp), %rsi
leaq (%rsi,%rax,4), %rdx
movq %rbx, %rsi
movq %r12, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
addl $1, %ebp
movl dimy(%rip), %eax
cmpl %ebp, %eax
jg .L15
.L16:
addl $1, %r15d
cmpl %r15d, dimx(%rip)
jle .L14
.L13:
movl dimy(%rip), %eax
movl $0, %ebp
testl %eax, %eax
jg .L15
jmp .L16
.L14:
movq %r14, %rdi
call fclose@PLT
movq %r13, %rdi
call fclose@PLT
movq %r12, %rdi
call fclose@PLT
movslq tam_imag(%rip), %rdx
salq $2, %rdx
movl $1, %ecx
movq 8(%rsp), %rsi
movq 80(%rsp), %rdi
call cudaMemcpy@PLT
movl $347, 140(%rsp)
movl $20, 144(%rsp)
movl $13, 152(%rsp)
movl $16, 156(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 152(%rsp), %rdx
movl $1, %ecx
movq 140(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L41
.L17:
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movslq tam_imag(%rip), %rdx
salq $2, %rdx
movl $2, %ecx
movq 128(%rsp), %rsi
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, 32(%rsp)
movl 32(%rsp), %eax
movl 52(%rsp), %edi
cmpl %edi, %eax
jg .L42
.L18:
movl 32(%rsp), %r13d
movl %r13d, %edx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movb $0, 165(%rsp)
leaq 165(%rsp), %rbp
subq $8, %rsp
.cfi_def_cfa_offset 248
leaq .LC3(%rip), %rax
pushq %rax
.cfi_def_cfa_offset 256
movl %r13d, %r9d
leaq .LC1(%rip), %r8
leaq .LC2(%rip), %r12
movq %r12, %rcx
movl $1, %edx
movl $2, %esi
movq %rbp, %rdi
movl $0, %eax
call __sprintf_chk@PLT
addq $16, %rsp
.cfi_def_cfa_offset 240
leaq .LC4(%rip), %r15
movq %r15, %rsi
movq %rbp, %rdi
call fopen@PLT
movq %rax, %r14
movb $0, 166(%rsp)
leaq 166(%rsp), %rbp
subq $8, %rsp
.cfi_def_cfa_offset 248
leaq .LC5(%rip), %rax
pushq %rax
.cfi_def_cfa_offset 256
movl %r13d, 48(%rsp)
movl %r13d, %r9d
leaq .LC1(%rip), %r8
movq %r12, %rcx
movl $1, %edx
movl $2, %esi
movq %rbp, %rdi
movl $0, %eax
call __sprintf_chk@PLT
addq $16, %rsp
.cfi_def_cfa_offset 240
movq %r15, %rsi
movq %rbp, %rdi
call fopen@PLT
movq %rax, %r13
movb $0, 167(%rsp)
leaq 167(%rsp), %rbp
subq $8, %rsp
.cfi_def_cfa_offset 248
leaq .LC6(%rip), %rax
pushq %rax
.cfi_def_cfa_offset 256
movl 48(%rsp), %r9d
leaq .LC1(%rip), %r8
movq %r12, %rcx
movl $1, %edx
movl $2, %esi
movq %rbp, %rdi
movl $0, %eax
call __sprintf_chk@PLT
addq $16, %rsp
.cfi_def_cfa_offset 240
movq %r15, %rsi
movq %rbp, %rdi
call fopen@PLT
movq %rax, %r12
movl $0, %r15d
cmpl $0, dimx(%rip)
jg .L13
jmp .L14
.L41:
movq 128(%rsp), %rsi
movq 88(%rsp), %rdi
call _Z29__device_stub__Z8VarianzaPiPfPiPf
jmp .L17
.L42:
movq 56(%rsp), %r13
.L12:
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC11(%rip), %rsi
leaq .LC12(%rip), %rdi
call fopen@PLT
movq %rax, %r12
movl $0, %ebp
leaq .LC13(%rip), %r15
leaq .LC14(%rip), %r14
cmpl $0, dimx(%rip)
jle .L20
movq %r13, 32(%rsp)
movq 40(%rsp), %r13
jmp .L19
.L21:
imull %ebp, %eax
addl %ebx, %eax
cltq
pxor %xmm0, %xmm0
cvtss2sd 0(%r13,%rax,4), %xmm0
movq %r15, %rdx
movl $2, %esi
movq %r12, %rdi
movl $1, %eax
call __fprintf_chk@PLT
addl $1, %ebx
movl dimy(%rip), %eax
cmpl %ebx, %eax
jg .L21
.L22:
movq %r14, %rdx
movl $2, %esi
movq %r12, %rdi
movl $0, %eax
call __fprintf_chk@PLT
addl $1, %ebp
cmpl %ebp, dimx(%rip)
jle .L39
.L19:
movl dimy(%rip), %eax
movl $0, %ebx
testl %eax, %eax
jg .L21
jmp .L22
.L39:
movq 32(%rsp), %r13
.L20:
movq %r12, %rdi
call fclose@PLT
movq 40(%rsp), %rdi
call free@PLT
movq 16(%rsp), %rdi
call free@PLT
movq 8(%rsp), %rdi
call free@PLT
movq 24(%rsp), %rdi
call free@PLT
movq 128(%rsp), %rdi
call cudaFree@PLT
movq 120(%rsp), %rdi
call cudaFree@PLT
movq 64(%rsp), %rdi
call cudaFree@PLT
movq 72(%rsp), %rdi
call cudaFree@PLT
movq 80(%rsp), %rdi
call cudaFree@PLT
movq 88(%rsp), %rdi
call cudaFree@PLT
movq 96(%rsp), %rdi
call cudaFree@PLT
movq 104(%rsp), %rdi
call cudaFree@PLT
movq 112(%rsp), %rdi
call cudaFree@PLT
call clock@PLT
pxor %xmm0, %xmm0
cvtsi2ssq %rax, %xmm0
pxor %xmm1, %xmm1
cvtsi2ssq %r13, %xmm1
subss %xmm1, %xmm0
divss .LC15(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
leaq .LC16(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L43
movl $0, %eax
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L43:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC17:
.string "_Z8VarianzaPiPf"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC17(%rip), %rdx
movq %rdx, %rcx
leaq _Z8VarianzaPiPf(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl tam_imag
.data
.align 4
.type tam_imag, @object
.size tam_imag, 4
tam_imag:
.long 1443520
.globl dimy
.align 4
.type dimy, @object
.size dimy, 4
dimy:
.long 1388
.globl dimx
.align 4
.type dimx, @object
.size dimx, 4
dimx:
.long 1040
.globl msk
.align 4
.type msk, @object
.size msk, 4
msk:
.long 3
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC15:
.long 1232348160
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "10_var--topo+RGB-CUDA.hip"
.globl _Z23__device_stub__VarianzaPiPf # -- Begin function _Z23__device_stub__VarianzaPiPf
.p2align 4, 0x90
.type _Z23__device_stub__VarianzaPiPf,@function
_Z23__device_stub__VarianzaPiPf: # @_Z23__device_stub__VarianzaPiPf
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z8VarianzaPiPf, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z23__device_stub__VarianzaPiPf, .Lfunc_end0-_Z23__device_stub__VarianzaPiPf
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI1_0:
.long 0x49742400 # float 1.0E+6
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $248, %rsp
.cfi_def_cfa_offset 304
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %rbx
movq 8(%rsi), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r14
movq 16(%rbx), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r15
callq clock
movq %rax, 88(%rsp) # 8-byte Spill
movslq tam_imag(%rip), %rbx
shlq $2, %rbx
movq %rbx, %rdi
callq malloc
movq %rax, 24(%rsp) # 8-byte Spill
leaq 144(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
movslq tam_imag(%rip), %rbx
shlq $2, %rbx
movq %rbx, %rdi
callq malloc
movq %rax, %r13
leaq 80(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
movslq tam_imag(%rip), %rbx
shlq $2, %rbx
movq %rbx, %rdi
callq malloc
movq %rax, 48(%rsp) # 8-byte Spill
leaq 72(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
movslq tam_imag(%rip), %rsi
shlq $2, %rsi
leaq 136(%rsp), %rdi
callq hipMalloc
movslq tam_imag(%rip), %rsi
shlq $2, %rsi
leaq 128(%rsp), %rdi
callq hipMalloc
movslq tam_imag(%rip), %rsi
shlq $2, %rsi
leaq 120(%rsp), %rdi
callq hipMalloc
movslq tam_imag(%rip), %rsi
shlq $2, %rsi
leaq 152(%rsp), %rdi
callq hipMalloc
movslq tam_imag(%rip), %rsi
shlq $2, %rsi
leaq 112(%rsp), %rdi
callq hipMalloc
movslq tam_imag(%rip), %rbx
shlq $2, %rbx
movq %rbx, %rdi
callq malloc
movq %rax, 8(%rsp) # 8-byte Spill
leaq 16(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
movq %r15, 96(%rsp) # 8-byte Spill
cmpl %r15d, %r14d
jle .LBB1_1
.LBB1_11: # %._crit_edge76
movl $.Lstr, %edi
callq puts@PLT
movl $.L.str.11, %edi
movl $.L.str.12, %esi
callq fopen
movq %rax, %rbx
cmpl $0, dimx(%rip)
movq 24(%rsp), %r12 # 8-byte Reload
jle .LBB1_17
# %bb.12: # %.preheader.preheader
xorl %r14d, %r14d
movq 8(%rsp), %rbp # 8-byte Reload
jmp .LBB1_13
.p2align 4, 0x90
.LBB1_16: # %._crit_edge79
# in Loop: Header=BB1_13 Depth=1
movl $10, %edi
movq %rbx, %rsi
callq fputc@PLT
incl %r14d
cmpl dimx(%rip), %r14d
jge .LBB1_17
.LBB1_13: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_15 Depth 2
movl dimy(%rip), %eax
testl %eax, %eax
jle .LBB1_16
# %bb.14: # %.lr.ph78.preheader
# in Loop: Header=BB1_13 Depth=1
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB1_15: # %.lr.ph78
# Parent Loop BB1_13 Depth=1
# => This Inner Loop Header: Depth=2
imull %r14d, %eax
cltq
addq %r15, %rax
movss (%rbp,%rax,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.13, %esi
movq %rbx, %rdi
movb $1, %al
callq fprintf
movl dimy(%rip), %eax
incq %r15
cmpl %eax, %r15d
jl .LBB1_15
jmp .LBB1_16
.LBB1_17: # %._crit_edge81
movq %rbx, %rdi
callq fclose
movq 8(%rsp), %rdi # 8-byte Reload
callq free
movq %r12, %rdi
callq free
movq %r13, %rdi
callq free
movq 48(%rsp), %rdi # 8-byte Reload
callq free
movq 16(%rsp), %rdi
callq hipFree
movq 112(%rsp), %rdi
callq hipFree
movq 152(%rsp), %rdi
callq hipFree
movq 144(%rsp), %rdi
callq hipFree
movq 80(%rsp), %rdi
callq hipFree
movq 72(%rsp), %rdi
callq hipFree
movq 136(%rsp), %rdi
callq hipFree
movq 128(%rsp), %rdi
callq hipFree
movq 120(%rsp), %rdi
callq hipFree
callq clock
xorps %xmm0, %xmm0
cvtsi2ss %rax, %xmm0
cvtsi2ssq 88(%rsp), %xmm1 # 8-byte Folded Reload
subss %xmm1, %xmm0
divss .LCPI1_0(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movl $.L.str.15, %edi
movb $1, %al
callq printf
xorl %eax, %eax
addq $248, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_1: # %.lr.ph75
.cfi_def_cfa_offset 304
movq %r13, 56(%rsp) # 8-byte Spill
movq 24(%rsp), %rbp # 8-byte Reload
jmp .LBB1_2
.p2align 4, 0x90
.LBB1_8: # %._crit_edge71
# in Loop: Header=BB1_2 Depth=1
movq 40(%rsp), %rdi # 8-byte Reload
callq fclose
movq 64(%rsp), %rdi # 8-byte Reload
callq fclose
movq 32(%rsp), %rdi # 8-byte Reload
callq fclose
movq 80(%rsp), %rdi
movslq tam_imag(%rip), %rdx
shlq $2, %rdx
movq 56(%rsp), %r13 # 8-byte Reload
movq %r13, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $85899346267, %rdi # imm = 0x140000015B
movl $1, %esi
movabsq $68719476749, %rdx # imm = 0x100000000D
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
je .LBB1_9
.LBB1_10: # in Loop: Header=BB1_2 Depth=1
movl $.Lstr.1, %edi
callq puts@PLT
movq 16(%rsp), %rsi
movslq tam_imag(%rip), %rdx
shlq $2, %rdx
movq 8(%rsp), %rdi # 8-byte Reload
movl $2, %ecx
callq hipMemcpy
movl $.Lstr.2, %edi
callq puts@PLT
movq 104(%rsp), %rcx # 8-byte Reload
leal 1(%rcx), %eax
cmpl 96(%rsp), %ecx # 4-byte Folded Reload
movl %eax, %r14d
je .LBB1_11
.LBB1_2: # =>This Loop Header: Depth=1
# Child Loop BB1_4 Depth 2
# Child Loop BB1_6 Depth 3
movl $.L.str, %edi
movl %r14d, %esi
xorl %eax, %eax
callq printf
movb $0, 7(%rsp)
movl $.L.str.1, %esi
movl $.L.str.2, %edx
movl $.L.str.3, %r8d
leaq 7(%rsp), %rbx
movq %rbx, %rdi
movl %r14d, %ecx
xorl %eax, %eax
callq sprintf
movl $.L.str.4, %esi
movq %rbx, %rdi
callq fopen
movq %rax, 40(%rsp) # 8-byte Spill
movb $0, 6(%rsp)
movl $.L.str.1, %esi
movl $.L.str.2, %edx
movl $.L.str.5, %r8d
leaq 6(%rsp), %rbx
movq %rbx, %rdi
movl %r14d, %ecx
xorl %eax, %eax
callq sprintf
movl $.L.str.4, %esi
movq %rbx, %rdi
callq fopen
movq %rax, 64(%rsp) # 8-byte Spill
movb $0, 5(%rsp)
movl $.L.str.1, %esi
movl $.L.str.2, %edx
movl $.L.str.6, %r8d
leaq 5(%rsp), %rbx
movq %rbx, %rdi
movq %r14, 104(%rsp) # 8-byte Spill
movl %r14d, %ecx
xorl %eax, %eax
callq sprintf
movl $.L.str.4, %esi
movq %rbx, %rdi
callq fopen
movq %rax, 32(%rsp) # 8-byte Spill
cmpl $0, dimx(%rip)
jle .LBB1_8
# %bb.3: # %.preheader68.preheader
# in Loop: Header=BB1_2 Depth=1
xorl %r14d, %r14d
jmp .LBB1_4
.p2align 4, 0x90
.LBB1_7: # %._crit_edge
# in Loop: Header=BB1_4 Depth=2
incl %r14d
cmpl dimx(%rip), %r14d
jge .LBB1_8
.LBB1_4: # %.preheader68
# Parent Loop BB1_2 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB1_6 Depth 3
movl dimy(%rip), %eax
testl %eax, %eax
movq 40(%rsp), %r13 # 8-byte Reload
movq 32(%rsp), %rbx # 8-byte Reload
jle .LBB1_7
# %bb.5: # %.lr.ph.preheader
# in Loop: Header=BB1_4 Depth=2
movslq %r14d, %r15
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB1_6: # %.lr.ph
# Parent Loop BB1_2 Depth=1
# Parent Loop BB1_4 Depth=2
# => This Inner Loop Header: Depth=3
imull %r14d, %eax
cltq
addq %r12, %rax
leaq (,%rax,4), %rdx
addq %rbp, %rdx
movl $.L.str.7, %esi
movq %r13, %rdi
xorl %eax, %eax
callq __isoc23_fscanf
movslq dimy(%rip), %rax
imulq %r15, %rax
addq %r12, %rax
movq 56(%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax,4), %rdx
movl $.L.str.7, %esi
movq 64(%rsp), %rdi # 8-byte Reload
xorl %eax, %eax
callq __isoc23_fscanf
movslq dimy(%rip), %rax
imulq %r15, %rax
addq %r12, %rax
movq 48(%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax,4), %rdx
movl $.L.str.7, %esi
movq %rbx, %rdi
xorl %eax, %eax
callq __isoc23_fscanf
movl dimy(%rip), %eax
incq %r12
cmpl %eax, %r12d
jl .LBB1_6
jmp .LBB1_7
.p2align 4, 0x90
.LBB1_9: # in Loop: Header=BB1_2 Depth=1
movq 72(%rsp), %rax
movq 16(%rsp), %rcx
movq %rax, 216(%rsp)
movq %rcx, 208(%rsp)
leaq 216(%rsp), %rax
movq %rax, 224(%rsp)
leaq 208(%rsp), %rax
movq %rax, 232(%rsp)
leaq 192(%rsp), %rdi
leaq 176(%rsp), %rsi
leaq 168(%rsp), %rdx
leaq 160(%rsp), %rcx
callq __hipPopCallConfiguration
movq 192(%rsp), %rsi
movl 200(%rsp), %edx
movq 176(%rsp), %rcx
movl 184(%rsp), %r8d
movl $_Z8VarianzaPiPf, %edi
leaq 224(%rsp), %r9
pushq 160(%rsp)
.cfi_adjust_cfa_offset 8
pushq 176(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB1_10
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8VarianzaPiPf, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type msk,@object # @msk
.data
.globl msk
.p2align 2, 0x0
msk:
.long 3 # 0x3
.size msk, 4
.type dimx,@object # @dimx
.globl dimx
.p2align 2, 0x0
dimx:
.long 1040 # 0x410
.size dimx, 4
.type dimy,@object # @dimy
.globl dimy
.p2align 2, 0x0
dimy:
.long 1388 # 0x56c
.size dimy, 4
.type tam_imag,@object # @tam_imag
.globl tam_imag
.p2align 2, 0x0
tam_imag:
.long 1443520 # 0x1606c0
.size tam_imag, 4
.type _Z8VarianzaPiPf,@object # @_Z8VarianzaPiPf
.section .rodata,"a",@progbits
.globl _Z8VarianzaPiPf
.p2align 3, 0x0
_Z8VarianzaPiPf:
.quad _Z23__device_stub__VarianzaPiPf
.size _Z8VarianzaPiPf, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "d=%d \n"
.size .L.str, 7
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "%s%d%s"
.size .L.str.1, 7
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "RGB/"
.size .L.str.2, 5
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "/R"
.size .L.str.3, 3
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "r+"
.size .L.str.4, 3
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "/G"
.size .L.str.5, 3
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "/B"
.size .L.str.6, 3
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "%d"
.size .L.str.7, 3
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz "Resultados/VarUltima"
.size .L.str.11, 21
.type .L.str.12,@object # @.str.12
.L.str.12:
.asciz "w+"
.size .L.str.12, 3
.type .L.str.13,@object # @.str.13
.L.str.13:
.asciz "%f "
.size .L.str.13, 4
.type .L.str.15,@object # @.str.15
.L.str.15:
.asciz "\ntiempo de procesamiento de varianzas: %6.3fs\n"
.size .L.str.15, 47
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z8VarianzaPiPf"
.size .L__unnamed_1, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "***Sale del for "
.size .Lstr, 17
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "Despues de kernel "
.size .Lstr.1, 19
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "Despues de resultado a host "
.size .Lstr.2, 29
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__VarianzaPiPf
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8VarianzaPiPf
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void __word2vecPos(int nrows, int ncols, int *W, int *LB, int *UB, float *A, float *B, float lrate, float vexp) {} | code for sm_80
Function : _Z13__word2vecPosiiPiS_S_PfS0_ff
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void __word2vecPos(int nrows, int ncols, int *W, int *LB, int *UB, float *A, float *B, float lrate, float vexp) {} | .file "tmpxft_000fd9ba_00000000-6___word2vecPos.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z46__device_stub__Z13__word2vecPosiiPiS_S_PfS0_ffiiPiS_S_PfS0_ff
.type _Z46__device_stub__Z13__word2vecPosiiPiS_S_PfS0_ffiiPiS_S_PfS0_ff, @function
_Z46__device_stub__Z13__word2vecPosiiPiS_S_PfS0_ffiiPiS_S_PfS0_ff:
.LFB2051:
.cfi_startproc
endbr64
subq $216, %rsp
.cfi_def_cfa_offset 224
movl %edi, 60(%rsp)
movl %esi, 56(%rsp)
movq %rdx, 48(%rsp)
movq %rcx, 40(%rsp)
movq %r8, 32(%rsp)
movq %r9, 24(%rsp)
movss %xmm0, 12(%rsp)
movss %xmm1, 8(%rsp)
movq 224(%rsp), %rax
movq %rax, 16(%rsp)
movq %fs:40, %rax
movq %rax, 200(%rsp)
xorl %eax, %eax
leaq 60(%rsp), %rax
movq %rax, 128(%rsp)
leaq 56(%rsp), %rax
movq %rax, 136(%rsp)
leaq 48(%rsp), %rax
movq %rax, 144(%rsp)
leaq 40(%rsp), %rax
movq %rax, 152(%rsp)
leaq 32(%rsp), %rax
movq %rax, 160(%rsp)
leaq 24(%rsp), %rax
movq %rax, 168(%rsp)
leaq 16(%rsp), %rax
movq %rax, 176(%rsp)
leaq 12(%rsp), %rax
movq %rax, 184(%rsp)
leaq 8(%rsp), %rax
movq %rax, 192(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 200(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $216, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 232
pushq 72(%rsp)
.cfi_def_cfa_offset 240
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq _Z13__word2vecPosiiPiS_S_PfS0_ff(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 224
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z46__device_stub__Z13__word2vecPosiiPiS_S_PfS0_ffiiPiS_S_PfS0_ff, .-_Z46__device_stub__Z13__word2vecPosiiPiS_S_PfS0_ffiiPiS_S_PfS0_ff
.globl _Z13__word2vecPosiiPiS_S_PfS0_ff
.type _Z13__word2vecPosiiPiS_S_PfS0_ff, @function
_Z13__word2vecPosiiPiS_S_PfS0_ff:
.LFB2052:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
pushq 24(%rsp)
.cfi_def_cfa_offset 32
call _Z46__device_stub__Z13__word2vecPosiiPiS_S_PfS0_ffiiPiS_S_PfS0_ff
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z13__word2vecPosiiPiS_S_PfS0_ff, .-_Z13__word2vecPosiiPiS_S_PfS0_ff
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z13__word2vecPosiiPiS_S_PfS0_ff"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z13__word2vecPosiiPiS_S_PfS0_ff(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void __word2vecPos(int nrows, int ncols, int *W, int *LB, int *UB, float *A, float *B, float lrate, float vexp) {} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void __word2vecPos(int nrows, int ncols, int *W, int *LB, int *UB, float *A, float *B, float lrate, float vexp) {} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void __word2vecPos(int nrows, int ncols, int *W, int *LB, int *UB, float *A, float *B, float lrate, float vexp) {} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z13__word2vecPosiiPiS_S_PfS0_ff
.globl _Z13__word2vecPosiiPiS_S_PfS0_ff
.p2align 8
.type _Z13__word2vecPosiiPiS_S_PfS0_ff,@function
_Z13__word2vecPosiiPiS_S_PfS0_ff:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13__word2vecPosiiPiS_S_PfS0_ff
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 56
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 1
.amdhsa_next_free_sgpr 1
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z13__word2vecPosiiPiS_S_PfS0_ff, .Lfunc_end0-_Z13__word2vecPosiiPiS_S_PfS0_ff
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
- .offset: 48
.size: 4
.value_kind: by_value
- .offset: 52
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 56
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13__word2vecPosiiPiS_S_PfS0_ff
.private_segment_fixed_size: 0
.sgpr_count: 0
.sgpr_spill_count: 0
.symbol: _Z13__word2vecPosiiPiS_S_PfS0_ff.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 0
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void __word2vecPos(int nrows, int ncols, int *W, int *LB, int *UB, float *A, float *B, float lrate, float vexp) {} | .text
.file "__word2vecPos.hip"
.globl _Z28__device_stub____word2vecPosiiPiS_S_PfS0_ff # -- Begin function _Z28__device_stub____word2vecPosiiPiS_S_PfS0_ff
.p2align 4, 0x90
.type _Z28__device_stub____word2vecPosiiPiS_S_PfS0_ff,@function
_Z28__device_stub____word2vecPosiiPiS_S_PfS0_ff: # @_Z28__device_stub____word2vecPosiiPiS_S_PfS0_ff
.cfi_startproc
# %bb.0:
subq $168, %rsp
.cfi_def_cfa_offset 176
movl %edi, 12(%rsp)
movl %esi, 8(%rsp)
movq %rdx, 88(%rsp)
movq %rcx, 80(%rsp)
movq %r8, 72(%rsp)
movq %r9, 64(%rsp)
movss %xmm0, 4(%rsp)
movss %xmm1, (%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 88(%rsp), %rax
movq %rax, 112(%rsp)
leaq 80(%rsp), %rax
movq %rax, 120(%rsp)
leaq 72(%rsp), %rax
movq %rax, 128(%rsp)
leaq 64(%rsp), %rax
movq %rax, 136(%rsp)
leaq 176(%rsp), %rax
movq %rax, 144(%rsp)
leaq 4(%rsp), %rax
movq %rax, 152(%rsp)
movq %rsp, %rax
movq %rax, 160(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z13__word2vecPosiiPiS_S_PfS0_ff, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $184, %rsp
.cfi_adjust_cfa_offset -184
retq
.Lfunc_end0:
.size _Z28__device_stub____word2vecPosiiPiS_S_PfS0_ff, .Lfunc_end0-_Z28__device_stub____word2vecPosiiPiS_S_PfS0_ff
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13__word2vecPosiiPiS_S_PfS0_ff, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z13__word2vecPosiiPiS_S_PfS0_ff,@object # @_Z13__word2vecPosiiPiS_S_PfS0_ff
.section .rodata,"a",@progbits
.globl _Z13__word2vecPosiiPiS_S_PfS0_ff
.p2align 3, 0x0
_Z13__word2vecPosiiPiS_S_PfS0_ff:
.quad _Z28__device_stub____word2vecPosiiPiS_S_PfS0_ff
.size _Z13__word2vecPosiiPiS_S_PfS0_ff, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z13__word2vecPosiiPiS_S_PfS0_ff"
.size .L__unnamed_1, 33
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub____word2vecPosiiPiS_S_PfS0_ff
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z13__word2vecPosiiPiS_S_PfS0_ff
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z13__word2vecPosiiPiS_S_PfS0_ff
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z13__word2vecPosiiPiS_S_PfS0_ff
.globl _Z13__word2vecPosiiPiS_S_PfS0_ff
.p2align 8
.type _Z13__word2vecPosiiPiS_S_PfS0_ff,@function
_Z13__word2vecPosiiPiS_S_PfS0_ff:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13__word2vecPosiiPiS_S_PfS0_ff
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 56
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 1
.amdhsa_next_free_sgpr 1
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z13__word2vecPosiiPiS_S_PfS0_ff, .Lfunc_end0-_Z13__word2vecPosiiPiS_S_PfS0_ff
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
- .offset: 48
.size: 4
.value_kind: by_value
- .offset: 52
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 56
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13__word2vecPosiiPiS_S_PfS0_ff
.private_segment_fixed_size: 0
.sgpr_count: 0
.sgpr_spill_count: 0
.symbol: _Z13__word2vecPosiiPiS_S_PfS0_ff.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 0
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000fd9ba_00000000-6___word2vecPos.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z46__device_stub__Z13__word2vecPosiiPiS_S_PfS0_ffiiPiS_S_PfS0_ff
.type _Z46__device_stub__Z13__word2vecPosiiPiS_S_PfS0_ffiiPiS_S_PfS0_ff, @function
_Z46__device_stub__Z13__word2vecPosiiPiS_S_PfS0_ffiiPiS_S_PfS0_ff:
.LFB2051:
.cfi_startproc
endbr64
subq $216, %rsp
.cfi_def_cfa_offset 224
movl %edi, 60(%rsp)
movl %esi, 56(%rsp)
movq %rdx, 48(%rsp)
movq %rcx, 40(%rsp)
movq %r8, 32(%rsp)
movq %r9, 24(%rsp)
movss %xmm0, 12(%rsp)
movss %xmm1, 8(%rsp)
movq 224(%rsp), %rax
movq %rax, 16(%rsp)
movq %fs:40, %rax
movq %rax, 200(%rsp)
xorl %eax, %eax
leaq 60(%rsp), %rax
movq %rax, 128(%rsp)
leaq 56(%rsp), %rax
movq %rax, 136(%rsp)
leaq 48(%rsp), %rax
movq %rax, 144(%rsp)
leaq 40(%rsp), %rax
movq %rax, 152(%rsp)
leaq 32(%rsp), %rax
movq %rax, 160(%rsp)
leaq 24(%rsp), %rax
movq %rax, 168(%rsp)
leaq 16(%rsp), %rax
movq %rax, 176(%rsp)
leaq 12(%rsp), %rax
movq %rax, 184(%rsp)
leaq 8(%rsp), %rax
movq %rax, 192(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 200(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $216, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 232
pushq 72(%rsp)
.cfi_def_cfa_offset 240
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq _Z13__word2vecPosiiPiS_S_PfS0_ff(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 224
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z46__device_stub__Z13__word2vecPosiiPiS_S_PfS0_ffiiPiS_S_PfS0_ff, .-_Z46__device_stub__Z13__word2vecPosiiPiS_S_PfS0_ffiiPiS_S_PfS0_ff
.globl _Z13__word2vecPosiiPiS_S_PfS0_ff
.type _Z13__word2vecPosiiPiS_S_PfS0_ff, @function
_Z13__word2vecPosiiPiS_S_PfS0_ff:
.LFB2052:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
pushq 24(%rsp)
.cfi_def_cfa_offset 32
call _Z46__device_stub__Z13__word2vecPosiiPiS_S_PfS0_ffiiPiS_S_PfS0_ff
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z13__word2vecPosiiPiS_S_PfS0_ff, .-_Z13__word2vecPosiiPiS_S_PfS0_ff
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z13__word2vecPosiiPiS_S_PfS0_ff"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z13__word2vecPosiiPiS_S_PfS0_ff(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "__word2vecPos.hip"
.globl _Z28__device_stub____word2vecPosiiPiS_S_PfS0_ff # -- Begin function _Z28__device_stub____word2vecPosiiPiS_S_PfS0_ff
.p2align 4, 0x90
.type _Z28__device_stub____word2vecPosiiPiS_S_PfS0_ff,@function
_Z28__device_stub____word2vecPosiiPiS_S_PfS0_ff: # @_Z28__device_stub____word2vecPosiiPiS_S_PfS0_ff
.cfi_startproc
# %bb.0:
subq $168, %rsp
.cfi_def_cfa_offset 176
movl %edi, 12(%rsp)
movl %esi, 8(%rsp)
movq %rdx, 88(%rsp)
movq %rcx, 80(%rsp)
movq %r8, 72(%rsp)
movq %r9, 64(%rsp)
movss %xmm0, 4(%rsp)
movss %xmm1, (%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 88(%rsp), %rax
movq %rax, 112(%rsp)
leaq 80(%rsp), %rax
movq %rax, 120(%rsp)
leaq 72(%rsp), %rax
movq %rax, 128(%rsp)
leaq 64(%rsp), %rax
movq %rax, 136(%rsp)
leaq 176(%rsp), %rax
movq %rax, 144(%rsp)
leaq 4(%rsp), %rax
movq %rax, 152(%rsp)
movq %rsp, %rax
movq %rax, 160(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z13__word2vecPosiiPiS_S_PfS0_ff, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $184, %rsp
.cfi_adjust_cfa_offset -184
retq
.Lfunc_end0:
.size _Z28__device_stub____word2vecPosiiPiS_S_PfS0_ff, .Lfunc_end0-_Z28__device_stub____word2vecPosiiPiS_S_PfS0_ff
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13__word2vecPosiiPiS_S_PfS0_ff, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z13__word2vecPosiiPiS_S_PfS0_ff,@object # @_Z13__word2vecPosiiPiS_S_PfS0_ff
.section .rodata,"a",@progbits
.globl _Z13__word2vecPosiiPiS_S_PfS0_ff
.p2align 3, 0x0
_Z13__word2vecPosiiPiS_S_PfS0_ff:
.quad _Z28__device_stub____word2vecPosiiPiS_S_PfS0_ff
.size _Z13__word2vecPosiiPiS_S_PfS0_ff, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z13__word2vecPosiiPiS_S_PfS0_ff"
.size .L__unnamed_1, 33
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub____word2vecPosiiPiS_S_PfS0_ff
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z13__word2vecPosiiPiS_S_PfS0_ff
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void nllLoss(float *x, int x_stride, float *y, int* target) {
int tid = threadIdx.x + blockIdx.x * blockDim.x;
int offset = tid * x_stride + target[tid];
y[tid] = -1 * x[offset];
} | code for sm_80
Function : _Z7nllLossPfiS_Pi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0050*/ IMAD R6, R3, c[0x0][0x0], R6 ; /* 0x0000000003067a24 */
/* 0x001fca00078e0206 */
/*0060*/ IMAD.WIDE R2, R6, R7, c[0x0][0x178] ; /* 0x00005e0006027625 */
/* 0x000fcc00078e0207 */
/*0070*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea4000c1e1900 */
/*0080*/ IMAD R4, R6, c[0x0][0x168], R3 ; /* 0x00005a0006047a24 */
/* 0x004fc800078e0203 */
/*0090*/ IMAD.WIDE R4, R4, R7, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fcc00078e0207 */
/*00a0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea2000c1e1900 */
/*00b0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fc800078e0207 */
/*00c0*/ FADD R9, -R4, -RZ ; /* 0x800000ff04097221 */
/* 0x004fca0000000100 */
/*00d0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00f0*/ BRA 0xf0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void nllLoss(float *x, int x_stride, float *y, int* target) {
int tid = threadIdx.x + blockIdx.x * blockDim.x;
int offset = tid * x_stride + target[tid];
y[tid] = -1 * x[offset];
} | .file "tmpxft_000e29c1_00000000-6_nllLoss.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z31__device_stub__Z7nllLossPfiS_PiPfiS_Pi
.type _Z31__device_stub__Z7nllLossPfiS_PiPfiS_Pi, @function
_Z31__device_stub__Z7nllLossPfiS_PiPfiS_Pi:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movq %rdx, 8(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z7nllLossPfiS_Pi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z31__device_stub__Z7nllLossPfiS_PiPfiS_Pi, .-_Z31__device_stub__Z7nllLossPfiS_PiPfiS_Pi
.globl _Z7nllLossPfiS_Pi
.type _Z7nllLossPfiS_Pi, @function
_Z7nllLossPfiS_Pi:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z7nllLossPfiS_PiPfiS_Pi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z7nllLossPfiS_Pi, .-_Z7nllLossPfiS_Pi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z7nllLossPfiS_Pi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z7nllLossPfiS_Pi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void nllLoss(float *x, int x_stride, float *y, int* target) {
int tid = threadIdx.x + blockIdx.x * blockDim.x;
int offset = tid * x_stride + target[tid];
y[tid] = -1 * x[offset];
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void nllLoss(float *x, int x_stride, float *y, int* target) {
int tid = threadIdx.x + blockIdx.x * blockDim.x;
int offset = tid * x_stride + target[tid];
y[tid] = -1 * x[offset];
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void nllLoss(float *x, int x_stride, float *y, int* target) {
int tid = threadIdx.x + blockIdx.x * blockDim.x;
int offset = tid * x_stride + target[tid];
y[tid] = -1 * x[offset];
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z7nllLossPfiS_Pi
.globl _Z7nllLossPfiS_Pi
.p2align 8
.type _Z7nllLossPfiS_Pi,@function
_Z7nllLossPfiS_Pi:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b128 s[4:7], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
v_add_co_u32 v4, vcc_lo, s6, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v3, vcc_lo
global_load_b32 v0, v[4:5], off
s_clause 0x1
s_load_b32 s2, s[0:1], 0x8
s_load_b64 s[0:1], s[0:1], 0x0
s_waitcnt vmcnt(0) lgkmcnt(0)
v_mad_u64_u32 v[4:5], null, v1, s2, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v5, 31, v4
v_lshlrev_b64 v[0:1], 2, v[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b32 v0, v[0:1], off
s_waitcnt vmcnt(0)
v_xor_b32_e32 v4, 0x80000000, v0
v_add_co_u32 v0, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v3, vcc_lo
global_store_b32 v[0:1], v4, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7nllLossPfiS_Pi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z7nllLossPfiS_Pi, .Lfunc_end0-_Z7nllLossPfiS_Pi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7nllLossPfiS_Pi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z7nllLossPfiS_Pi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void nllLoss(float *x, int x_stride, float *y, int* target) {
int tid = threadIdx.x + blockIdx.x * blockDim.x;
int offset = tid * x_stride + target[tid];
y[tid] = -1 * x[offset];
} | .text
.file "nllLoss.hip"
.globl _Z22__device_stub__nllLossPfiS_Pi # -- Begin function _Z22__device_stub__nllLossPfiS_Pi
.p2align 4, 0x90
.type _Z22__device_stub__nllLossPfiS_Pi,@function
_Z22__device_stub__nllLossPfiS_Pi: # @_Z22__device_stub__nllLossPfiS_Pi
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movl %esi, 4(%rsp)
movq %rdx, 64(%rsp)
movq %rcx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 56(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z7nllLossPfiS_Pi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z22__device_stub__nllLossPfiS_Pi, .Lfunc_end0-_Z22__device_stub__nllLossPfiS_Pi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7nllLossPfiS_Pi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z7nllLossPfiS_Pi,@object # @_Z7nllLossPfiS_Pi
.section .rodata,"a",@progbits
.globl _Z7nllLossPfiS_Pi
.p2align 3, 0x0
_Z7nllLossPfiS_Pi:
.quad _Z22__device_stub__nllLossPfiS_Pi
.size _Z7nllLossPfiS_Pi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z7nllLossPfiS_Pi"
.size .L__unnamed_1, 18
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__nllLossPfiS_Pi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7nllLossPfiS_Pi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z7nllLossPfiS_Pi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0050*/ IMAD R6, R3, c[0x0][0x0], R6 ; /* 0x0000000003067a24 */
/* 0x001fca00078e0206 */
/*0060*/ IMAD.WIDE R2, R6, R7, c[0x0][0x178] ; /* 0x00005e0006027625 */
/* 0x000fcc00078e0207 */
/*0070*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea4000c1e1900 */
/*0080*/ IMAD R4, R6, c[0x0][0x168], R3 ; /* 0x00005a0006047a24 */
/* 0x004fc800078e0203 */
/*0090*/ IMAD.WIDE R4, R4, R7, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fcc00078e0207 */
/*00a0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea2000c1e1900 */
/*00b0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fc800078e0207 */
/*00c0*/ FADD R9, -R4, -RZ ; /* 0x800000ff04097221 */
/* 0x004fca0000000100 */
/*00d0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00f0*/ BRA 0xf0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z7nllLossPfiS_Pi
.globl _Z7nllLossPfiS_Pi
.p2align 8
.type _Z7nllLossPfiS_Pi,@function
_Z7nllLossPfiS_Pi:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b128 s[4:7], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
v_add_co_u32 v4, vcc_lo, s6, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v3, vcc_lo
global_load_b32 v0, v[4:5], off
s_clause 0x1
s_load_b32 s2, s[0:1], 0x8
s_load_b64 s[0:1], s[0:1], 0x0
s_waitcnt vmcnt(0) lgkmcnt(0)
v_mad_u64_u32 v[4:5], null, v1, s2, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v5, 31, v4
v_lshlrev_b64 v[0:1], 2, v[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b32 v0, v[0:1], off
s_waitcnt vmcnt(0)
v_xor_b32_e32 v4, 0x80000000, v0
v_add_co_u32 v0, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v3, vcc_lo
global_store_b32 v[0:1], v4, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7nllLossPfiS_Pi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z7nllLossPfiS_Pi, .Lfunc_end0-_Z7nllLossPfiS_Pi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7nllLossPfiS_Pi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z7nllLossPfiS_Pi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000e29c1_00000000-6_nllLoss.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z31__device_stub__Z7nllLossPfiS_PiPfiS_Pi
.type _Z31__device_stub__Z7nllLossPfiS_PiPfiS_Pi, @function
_Z31__device_stub__Z7nllLossPfiS_PiPfiS_Pi:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movq %rdx, 8(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z7nllLossPfiS_Pi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z31__device_stub__Z7nllLossPfiS_PiPfiS_Pi, .-_Z31__device_stub__Z7nllLossPfiS_PiPfiS_Pi
.globl _Z7nllLossPfiS_Pi
.type _Z7nllLossPfiS_Pi, @function
_Z7nllLossPfiS_Pi:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z7nllLossPfiS_PiPfiS_Pi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z7nllLossPfiS_Pi, .-_Z7nllLossPfiS_Pi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z7nllLossPfiS_Pi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z7nllLossPfiS_Pi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "nllLoss.hip"
.globl _Z22__device_stub__nllLossPfiS_Pi # -- Begin function _Z22__device_stub__nllLossPfiS_Pi
.p2align 4, 0x90
.type _Z22__device_stub__nllLossPfiS_Pi,@function
_Z22__device_stub__nllLossPfiS_Pi: # @_Z22__device_stub__nllLossPfiS_Pi
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movl %esi, 4(%rsp)
movq %rdx, 64(%rsp)
movq %rcx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 56(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z7nllLossPfiS_Pi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z22__device_stub__nllLossPfiS_Pi, .Lfunc_end0-_Z22__device_stub__nllLossPfiS_Pi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7nllLossPfiS_Pi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z7nllLossPfiS_Pi,@object # @_Z7nllLossPfiS_Pi
.section .rodata,"a",@progbits
.globl _Z7nllLossPfiS_Pi
.p2align 3, 0x0
_Z7nllLossPfiS_Pi:
.quad _Z22__device_stub__nllLossPfiS_Pi
.size _Z7nllLossPfiS_Pi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z7nllLossPfiS_Pi"
.size .L__unnamed_1, 18
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__nllLossPfiS_Pi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7nllLossPfiS_Pi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | // #CSCS CUDA Training
//
// #Example 3.1 - transpose matrix
//
// #Author: Ugo Varetto
//
// #Goal: compute the transpose of a matrix and time operation using
// GPU's on-board performance counters through streams; print the result in ms (10^-3 s)
//
// #Rationale: shows how to time GPU computation
//
// #Solution: straightworwad, simply compute the thread id associated with the element
// and copy the transposed data into the output matrix; wrap kernel calls with event
// recording and print time information
//
// #Code: typical flow + timing:
// 1) compute launch grid configuration
// 2) allocate data on host(cpu) and device(gpu)
// 3) initialize data directly on the GPU
// 4) create events
// 5) record start time
// 6) launch kernel
// 7) synchronize events to guarantee that kernel execution is finished
// 8) record stop time
// 9) read data back
// 10) print timing information as stop - start time
// 11) delete events
// 12) free memory
// The code uses the default stream 0; streams are used to sychronize operations
// to guarantee that all operations in the same stream are executed sequentially.
//
// #Compilation: nvcc -arch=sm_13 3_1_transpose-timing.cu -o transpose-timing
//
// #Execution: ./transpose-timing
//
// #Note: kernel invocations ( foo<<<...>>>(...) ) are *always* asynchronous and a call to
// cudaThreadSynchronize() is required to wait for the end of kernel execution from
// a host thread; in case of synchronous copy operations like cudaMemcpy(...,cudaDeviceToHost)
// kernel execution is guaranteed to be terminated before data are copied
//
// #Note: the code is C++ also because the default compilation mode for CUDA is C++, all functions
// are named with C++ convention and the syntax is checked by default against C++ grammar rules
//
// #Note: -arch=sm_13 allows the code to run on every card with hw architecture GT200 (gtx 2xx) or better
//
// #Note: -arch=sm_13 is the lowest architecture version that supports double precision
//
// #Note: the example can be extended to read configuration data and matrix size from the command line
//#include <cuda_runtime.h> // automatically added by nvcc
#include <vector>
#include <iostream>
typedef float real_t;
__global__ void transpose( const real_t* in, real_t *out, int num_rows, int num_columns ) {
const int col = blockIdx.x * blockDim.x + threadIdx.x;
const int row = blockIdx.y * blockDim.y + threadIdx.y;
const int input_index = row * num_columns + col;
const int output_index = col * num_rows + row;
out[ output_index ] = in[ input_index ];
}
__global__ void init_matrix( real_t* in ) {
const int c = threadIdx.x + blockDim.x * blockIdx.x;
const int r = threadIdx.y + blockDim.y * blockIdx.y;
const int idx = c + gridDim.x * blockDim.x * r;
in[ idx ] = (real_t) idx;
}
void print_matrix( const real_t* m, int r, int c, int stride ) {
for( int i = 0; i != r; ++i ) {
for( int j = 0; j != c; ++j ) std::cout << m[ i * stride + j ] << ' ';
std::cout << '\n';
}
std::cout << std::endl;
}
//------------------------------------------------------------------------------
int main(int argc, char** argv ) {
const dim3 BLOCKS( 512, 512 );
const dim3 THREADS_PER_BLOCK( 16, 16 );
const int ROWS = 512 * 16; // 8192
const int COLUMNS = 512 * 16; // 8192
const size_t SIZE = ROWS * COLUMNS * sizeof( real_t );
// device storage
real_t* dev_in = 0;
real_t* dev_out = 0;
cudaMalloc( &dev_in, SIZE );
cudaMalloc( &dev_out, SIZE );
// host storage
std::vector< real_t > outmatrix( ROWS * COLUMNS );
// initialize matrix with kernel; much faster than using
// for loops on the cpu
init_matrix<<<dim3( COLUMNS, ROWS ), 1>>>( dev_in );
cudaMemcpy( &outmatrix[ 0 ], dev_in, SIZE, cudaMemcpyDeviceToHost );
// print upper 4x4 left corner of input matrix
std::cout << "INPUT MATRIX - " << ROWS << " rows, " << COLUMNS << " columns" << std::endl;
print_matrix( &outmatrix[ 0 ], 4, 4, COLUMNS );
// create events for timing execution
cudaEvent_t start = cudaEvent_t();
cudaEvent_t stop = cudaEvent_t();
cudaEventCreate( &start );
cudaEventCreate( &stop );
// record time into start event
cudaEventRecord( start, 0 ); // 0 is the default stream id
// execute kernel
transpose<<<BLOCKS, THREADS_PER_BLOCK>>>( dev_in, dev_out, ROWS, COLUMNS );
// issue request to record time into stop event
cudaEventRecord( stop, 0 );
// synchronize stop event to wait for end of kernel execution on stream 0
cudaEventSynchronize( stop );
// compute elapsed time (done by CUDA run-time)
float elapsed = 0.f;
cudaEventElapsedTime( &elapsed, start, stop );
std::cout << "Elapsed time (ms): " << elapsed << std::endl;
// copy output data from device(gpu) to host(cpu)
cudaMemcpy( &outmatrix[ 0 ], dev_out, SIZE, cudaMemcpyDeviceToHost );
// print upper 4x4 corner of transposed matrix
std::cout << "\nOUTPUT MATRIX - " << COLUMNS << " rows, " << ROWS << " columns" << std::endl;
print_matrix( &outmatrix[ 0 ], 4, 4, ROWS );
// free memory
cudaFree( dev_in );
cudaFree( dev_out );
// release events
cudaEventDestroy( start );
cudaEventDestroy( stop );
return 0;
} | code for sm_80
Function : _Z11init_matrixPf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_TID.Y ; /* 0x0000000000007919 */
/* 0x000e220000002200 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0030*/ S2R R7, SR_CTAID.Y ; /* 0x0000000000077919 */
/* 0x000e280000002600 */
/*0040*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x000e680000002500 */
/*0050*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000ea20000002100 */
/*0060*/ IMAD R0, R7, c[0x0][0x4], R0 ; /* 0x0000010007007a24 */
/* 0x001fc800078e0200 */
/*0070*/ IMAD R0, R0, c[0x0][0xc], R5 ; /* 0x0000030000007a24 */
/* 0x002fc800078e0205 */
/*0080*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x004fe200078e0203 */
/*0090*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fc600000001ff */
/*00a0*/ I2F R5, R0 ; /* 0x0000000000057306 */
/* 0x000e2e0000201400 */
/*00b0*/ IMAD.WIDE R2, R0, R3, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fca00078e0203 */
/*00c0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x001fe2000c101904 */
/*00d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00e0*/ BRA 0xe0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z9transposePKfPfii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R4, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff047435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e280000002100 */
/*0050*/ S2R R5, SR_CTAID.Y ; /* 0x0000000000057919 */
/* 0x000e680000002600 */
/*0060*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e620000002200 */
/*0070*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fc400078e0203 */
/*0080*/ IMAD R5, R5, c[0x0][0x4], R2 ; /* 0x0000010005057a24 */
/* 0x002fc800078e0202 */
/*0090*/ IMAD R2, R5, c[0x0][0x174], R0 ; /* 0x00005d0005027a24 */
/* 0x000fc800078e0200 */
/*00a0*/ IMAD.WIDE R2, R2, R4, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fcc00078e0204 */
/*00b0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ IMAD R5, R0, c[0x0][0x170], R5 ; /* 0x00005c0000057a24 */
/* 0x000fc800078e0205 */
/*00d0*/ IMAD.WIDE R4, R5, R4, c[0x0][0x168] ; /* 0x00005a0005047625 */
/* 0x000fca00078e0204 */
/*00e0*/ STG.E [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x004fe2000c101904 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | // #CSCS CUDA Training
//
// #Example 3.1 - transpose matrix
//
// #Author: Ugo Varetto
//
// #Goal: compute the transpose of a matrix and time operation using
// GPU's on-board performance counters through streams; print the result in ms (10^-3 s)
//
// #Rationale: shows how to time GPU computation
//
// #Solution: straightworwad, simply compute the thread id associated with the element
// and copy the transposed data into the output matrix; wrap kernel calls with event
// recording and print time information
//
// #Code: typical flow + timing:
// 1) compute launch grid configuration
// 2) allocate data on host(cpu) and device(gpu)
// 3) initialize data directly on the GPU
// 4) create events
// 5) record start time
// 6) launch kernel
// 7) synchronize events to guarantee that kernel execution is finished
// 8) record stop time
// 9) read data back
// 10) print timing information as stop - start time
// 11) delete events
// 12) free memory
// The code uses the default stream 0; streams are used to sychronize operations
// to guarantee that all operations in the same stream are executed sequentially.
//
// #Compilation: nvcc -arch=sm_13 3_1_transpose-timing.cu -o transpose-timing
//
// #Execution: ./transpose-timing
//
// #Note: kernel invocations ( foo<<<...>>>(...) ) are *always* asynchronous and a call to
// cudaThreadSynchronize() is required to wait for the end of kernel execution from
// a host thread; in case of synchronous copy operations like cudaMemcpy(...,cudaDeviceToHost)
// kernel execution is guaranteed to be terminated before data are copied
//
// #Note: the code is C++ also because the default compilation mode for CUDA is C++, all functions
// are named with C++ convention and the syntax is checked by default against C++ grammar rules
//
// #Note: -arch=sm_13 allows the code to run on every card with hw architecture GT200 (gtx 2xx) or better
//
// #Note: -arch=sm_13 is the lowest architecture version that supports double precision
//
// #Note: the example can be extended to read configuration data and matrix size from the command line
//#include <cuda_runtime.h> // automatically added by nvcc
#include <vector>
#include <iostream>
typedef float real_t;
__global__ void transpose( const real_t* in, real_t *out, int num_rows, int num_columns ) {
const int col = blockIdx.x * blockDim.x + threadIdx.x;
const int row = blockIdx.y * blockDim.y + threadIdx.y;
const int input_index = row * num_columns + col;
const int output_index = col * num_rows + row;
out[ output_index ] = in[ input_index ];
}
__global__ void init_matrix( real_t* in ) {
const int c = threadIdx.x + blockDim.x * blockIdx.x;
const int r = threadIdx.y + blockDim.y * blockIdx.y;
const int idx = c + gridDim.x * blockDim.x * r;
in[ idx ] = (real_t) idx;
}
void print_matrix( const real_t* m, int r, int c, int stride ) {
for( int i = 0; i != r; ++i ) {
for( int j = 0; j != c; ++j ) std::cout << m[ i * stride + j ] << ' ';
std::cout << '\n';
}
std::cout << std::endl;
}
//------------------------------------------------------------------------------
int main(int argc, char** argv ) {
const dim3 BLOCKS( 512, 512 );
const dim3 THREADS_PER_BLOCK( 16, 16 );
const int ROWS = 512 * 16; // 8192
const int COLUMNS = 512 * 16; // 8192
const size_t SIZE = ROWS * COLUMNS * sizeof( real_t );
// device storage
real_t* dev_in = 0;
real_t* dev_out = 0;
cudaMalloc( &dev_in, SIZE );
cudaMalloc( &dev_out, SIZE );
// host storage
std::vector< real_t > outmatrix( ROWS * COLUMNS );
// initialize matrix with kernel; much faster than using
// for loops on the cpu
init_matrix<<<dim3( COLUMNS, ROWS ), 1>>>( dev_in );
cudaMemcpy( &outmatrix[ 0 ], dev_in, SIZE, cudaMemcpyDeviceToHost );
// print upper 4x4 left corner of input matrix
std::cout << "INPUT MATRIX - " << ROWS << " rows, " << COLUMNS << " columns" << std::endl;
print_matrix( &outmatrix[ 0 ], 4, 4, COLUMNS );
// create events for timing execution
cudaEvent_t start = cudaEvent_t();
cudaEvent_t stop = cudaEvent_t();
cudaEventCreate( &start );
cudaEventCreate( &stop );
// record time into start event
cudaEventRecord( start, 0 ); // 0 is the default stream id
// execute kernel
transpose<<<BLOCKS, THREADS_PER_BLOCK>>>( dev_in, dev_out, ROWS, COLUMNS );
// issue request to record time into stop event
cudaEventRecord( stop, 0 );
// synchronize stop event to wait for end of kernel execution on stream 0
cudaEventSynchronize( stop );
// compute elapsed time (done by CUDA run-time)
float elapsed = 0.f;
cudaEventElapsedTime( &elapsed, start, stop );
std::cout << "Elapsed time (ms): " << elapsed << std::endl;
// copy output data from device(gpu) to host(cpu)
cudaMemcpy( &outmatrix[ 0 ], dev_out, SIZE, cudaMemcpyDeviceToHost );
// print upper 4x4 corner of transposed matrix
std::cout << "\nOUTPUT MATRIX - " << COLUMNS << " rows, " << ROWS << " columns" << std::endl;
print_matrix( &outmatrix[ 0 ], 4, 4, ROWS );
// free memory
cudaFree( dev_in );
cudaFree( dev_out );
// release events
cudaEventDestroy( start );
cudaEventDestroy( stop );
return 0;
} | .file "tmpxft_001ac9d4_00000000-6_003_1_transpose-timing.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB4036:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4036:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z12print_matrixPKfiii
.type _Z12print_matrixPKfiii, @function
_Z12print_matrixPKfiii:
.LFB4032:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $40, %rsp
.cfi_def_cfa_offset 96
movl %edx, (%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 24(%rsp)
xorl %eax, %eax
testl %esi, %esi
je .L4
movq %rdi, %r15
movslq %esi, %rax
movq %rax, 8(%rsp)
movl $0, %r14d
movl $0, %r13d
leaq _ZSt4cout(%rip), %rbp
jmp .L5
.L6:
movl $32, %esi
call _ZNSo3putEc@PLT
.L7:
addq $4, %rbx
cmpq %r12, %rbx
je .L12
.L8:
pxor %xmm0, %xmm0
cvtss2sd (%rbx), %xmm0
movq %rbp, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
movb $32, 23(%rsp)
movq (%rax), %rax
movq -24(%rax), %rax
cmpq $0, 16(%rdi,%rax)
je .L6
leaq 23(%rsp), %rsi
movl $1, %edx
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
jmp .L7
.L12:
movb $10, 23(%rsp)
movq 0(%rbp), %rax
movq -24(%rax), %rax
cmpq $0, 16(%rbp,%rax)
je .L9
leaq 23(%rsp), %rsi
movl $1, %edx
movq %rbp, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
.L10:
addq $1, %r13
movl 4(%rsp), %eax
addl %eax, %r14d
movq 8(%rsp), %rax
cmpq %rax, %r13
je .L4
.L5:
cmpl $0, (%rsp)
je .L12
movslq %r14d, %rdx
leaq (%r15,%rdx,4), %rbx
movslq (%rsp), %rax
addq %rdx, %rax
leaq (%r15,%rax,4), %r12
jmp .L8
.L9:
movl $10, %esi
movq %rbp, %rdi
call _ZNSo3putEc@PLT
jmp .L10
.L4:
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
leaq _ZSt4cout(%rip), %rdx
movq 240(%rdx,%rax), %rbx
testq %rbx, %rbx
je .L20
cmpb $0, 56(%rbx)
je .L15
movzbl 67(%rbx), %eax
.L16:
movsbl %al, %esi
leaq _ZSt4cout(%rip), %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movq 24(%rsp), %rax
subq %fs:40, %rax
jne .L21
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L20:
.cfi_restore_state
movq 24(%rsp), %rax
subq %fs:40, %rax
jne .L22
call _ZSt16__throw_bad_castv@PLT
.L22:
call __stack_chk_fail@PLT
.L15:
movq %rbx, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%rbx), %rax
movl $10, %esi
movq %rbx, %rdi
call *48(%rax)
jmp .L16
.L21:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4032:
.size _Z12print_matrixPKfiii, .-_Z12print_matrixPKfiii
.globl _Z33__device_stub__Z9transposePKfPfiiPKfPfii
.type _Z33__device_stub__Z9transposePKfPfiiPKfPfii, @function
_Z33__device_stub__Z9transposePKfPfiiPKfPfii:
.LFB4058:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L27
.L23:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L28
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L27:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9transposePKfPfii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L23
.L28:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4058:
.size _Z33__device_stub__Z9transposePKfPfiiPKfPfii, .-_Z33__device_stub__Z9transposePKfPfiiPKfPfii
.globl _Z9transposePKfPfii
.type _Z9transposePKfPfii, @function
_Z9transposePKfPfii:
.LFB4059:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z9transposePKfPfiiPKfPfii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4059:
.size _Z9transposePKfPfii, .-_Z9transposePKfPfii
.globl _Z31__device_stub__Z11init_matrixPfPf
.type _Z31__device_stub__Z11init_matrixPfPf, @function
_Z31__device_stub__Z11init_matrixPfPf:
.LFB4060:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L35
.L31:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L36
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L35:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z11init_matrixPf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L31
.L36:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4060:
.size _Z31__device_stub__Z11init_matrixPfPf, .-_Z31__device_stub__Z11init_matrixPfPf
.globl _Z11init_matrixPf
.type _Z11init_matrixPf, @function
_Z11init_matrixPf:
.LFB4061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z11init_matrixPfPf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4061:
.size _Z11init_matrixPf, .-_Z11init_matrixPf
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z11init_matrixPf"
.LC1:
.string "_Z9transposePKfPfii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB4063:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z11init_matrixPf(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z9transposePKfPfii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4063:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .text._ZNSt6vectorIfSaIfEED2Ev,"axG",@progbits,_ZNSt6vectorIfSaIfEED5Ev,comdat
.align 2
.weak _ZNSt6vectorIfSaIfEED2Ev
.type _ZNSt6vectorIfSaIfEED2Ev, @function
_ZNSt6vectorIfSaIfEED2Ev:
.LFB4378:
.cfi_startproc
endbr64
movq (%rdi), %rax
testq %rax, %rax
je .L44
subq $8, %rsp
.cfi_def_cfa_offset 16
movq 16(%rdi), %rsi
subq %rax, %rsi
movq %rax, %rdi
call _ZdlPvm@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.L44:
ret
.cfi_endproc
.LFE4378:
.size _ZNSt6vectorIfSaIfEED2Ev, .-_ZNSt6vectorIfSaIfEED2Ev
.weak _ZNSt6vectorIfSaIfEED1Ev
.set _ZNSt6vectorIfSaIfEED1Ev,_ZNSt6vectorIfSaIfEED2Ev
.section .rodata.str1.1
.LC3:
.string "INPUT MATRIX - "
.LC4:
.string " rows, "
.LC5:
.string " columns"
.LC6:
.string "Elapsed time (ms): "
.LC7:
.string "\nOUTPUT MATRIX - "
.text
.globl main
.type main, @function
main:
.LFB4033:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA4033
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $112, %rsp
.cfi_def_cfa_offset 128
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
movl $512, 24(%rsp)
movl $512, 28(%rsp)
movl $1, 32(%rsp)
movl $16, 36(%rsp)
movl $16, 40(%rsp)
movl $1, 44(%rsp)
movq $0, 8(%rsp)
movq $0, 16(%rsp)
leaq 8(%rsp), %rdi
movl $268435456, %esi
.LEHB0:
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $268435456, %esi
call cudaMalloc@PLT
movl $268435456, %edi
call _Znwm@PLT
.LEHE0:
movq %rax, %rbx
movq %rax, 80(%rsp)
leaq 268435456(%rax), %rdx
movq %rdx, 96(%rsp)
movl $0x00000000, (%rax)
leaq 4(%rax), %rax
.L48:
movl $0x00000000, (%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L48
movq %rdx, 88(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $8192, 48(%rsp)
movl $8192, 52(%rsp)
movl $1, 56(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 64(%rsp), %rdx
movl $1, %ecx
movq 48(%rsp), %rdi
movl $1, %esi
.LEHB1:
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L49
movq 8(%rsp), %rdi
call _Z31__device_stub__Z11init_matrixPfPf
.L49:
movl $2, %ecx
movl $268435456, %edx
movq 8(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
leaq .LC3(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl $8192, %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
leaq .LC4(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl $8192, %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
leaq .LC5(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $8192, %ecx
movl $4, %edx
movl $4, %esi
movq %rbx, %rdi
call _Z12print_matrixPKfiii
movq $0, 48(%rsp)
movq $0, 64(%rsp)
leaq 48(%rsp), %rdi
call cudaEventCreate@PLT
leaq 64(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 48(%rsp), %rdi
call cudaEventRecord@PLT
movl 44(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movq 24(%rsp), %rdi
movl 32(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L50
movl $8192, %ecx
movl $8192, %edx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z33__device_stub__Z9transposePKfPfiiPKfPfii
.L50:
movl $0, %esi
movq 64(%rsp), %rdi
call cudaEventRecord@PLT
movq 64(%rsp), %rdi
call cudaEventSynchronize@PLT
movl $0x00000000, 4(%rsp)
leaq 4(%rsp), %rdi
movq 64(%rsp), %rdx
movq 48(%rsp), %rsi
call cudaEventElapsedTime@PLT
leaq .LC6(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
pxor %xmm0, %xmm0
cvtss2sd 4(%rsp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $2, %ecx
movl $268435456, %edx
movq 16(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
leaq .LC7(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl $8192, %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
leaq .LC4(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl $8192, %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
leaq .LC5(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $8192, %ecx
movl $4, %edx
movl $4, %esi
movq %rbx, %rdi
call _Z12print_matrixPKfiii
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 48(%rsp), %rdi
call cudaEventDestroy@PLT
movq 64(%rsp), %rdi
call cudaEventDestroy@PLT
.LEHE1:
leaq 80(%rsp), %rdi
call _ZNSt6vectorIfSaIfEED1Ev
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L58
movl $0, %eax
addq $112, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L54:
.cfi_restore_state
endbr64
movq %rax, %rbx
leaq 80(%rsp), %rdi
call _ZNSt6vectorIfSaIfEED1Ev
movq 104(%rsp), %rax
subq %fs:40, %rax
je .L52
call __stack_chk_fail@PLT
.L52:
movq %rbx, %rdi
.LEHB2:
call _Unwind_Resume@PLT
.LEHE2:
.L58:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4033:
.globl __gxx_personality_v0
.section .gcc_except_table,"a",@progbits
.LLSDA4033:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE4033-.LLSDACSB4033
.LLSDACSB4033:
.uleb128 .LEHB0-.LFB4033
.uleb128 .LEHE0-.LEHB0
.uleb128 0
.uleb128 0
.uleb128 .LEHB1-.LFB4033
.uleb128 .LEHE1-.LEHB1
.uleb128 .L54-.LFB4033
.uleb128 0
.uleb128 .LEHB2-.LFB4033
.uleb128 .LEHE2-.LEHB2
.uleb128 0
.uleb128 0
.LLSDACSE4033:
.text
.size main, .-main
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.hidden DW.ref.__gxx_personality_v0
.weak DW.ref.__gxx_personality_v0
.section .data.rel.local.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat
.align 8
.type DW.ref.__gxx_personality_v0, @object
.size DW.ref.__gxx_personality_v0, 8
DW.ref.__gxx_personality_v0:
.quad __gxx_personality_v0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | // #CSCS CUDA Training
//
// #Example 3.1 - transpose matrix
//
// #Author: Ugo Varetto
//
// #Goal: compute the transpose of a matrix and time operation using
// GPU's on-board performance counters through streams; print the result in ms (10^-3 s)
//
// #Rationale: shows how to time GPU computation
//
// #Solution: straightworwad, simply compute the thread id associated with the element
// and copy the transposed data into the output matrix; wrap kernel calls with event
// recording and print time information
//
// #Code: typical flow + timing:
// 1) compute launch grid configuration
// 2) allocate data on host(cpu) and device(gpu)
// 3) initialize data directly on the GPU
// 4) create events
// 5) record start time
// 6) launch kernel
// 7) synchronize events to guarantee that kernel execution is finished
// 8) record stop time
// 9) read data back
// 10) print timing information as stop - start time
// 11) delete events
// 12) free memory
// The code uses the default stream 0; streams are used to sychronize operations
// to guarantee that all operations in the same stream are executed sequentially.
//
// #Compilation: nvcc -arch=sm_13 3_1_transpose-timing.cu -o transpose-timing
//
// #Execution: ./transpose-timing
//
// #Note: kernel invocations ( foo<<<...>>>(...) ) are *always* asynchronous and a call to
// cudaThreadSynchronize() is required to wait for the end of kernel execution from
// a host thread; in case of synchronous copy operations like cudaMemcpy(...,cudaDeviceToHost)
// kernel execution is guaranteed to be terminated before data are copied
//
// #Note: the code is C++ also because the default compilation mode for CUDA is C++, all functions
// are named with C++ convention and the syntax is checked by default against C++ grammar rules
//
// #Note: -arch=sm_13 allows the code to run on every card with hw architecture GT200 (gtx 2xx) or better
//
// #Note: -arch=sm_13 is the lowest architecture version that supports double precision
//
// #Note: the example can be extended to read configuration data and matrix size from the command line
//#include <cuda_runtime.h> // automatically added by nvcc
#include <vector>
#include <iostream>
typedef float real_t;
__global__ void transpose( const real_t* in, real_t *out, int num_rows, int num_columns ) {
const int col = blockIdx.x * blockDim.x + threadIdx.x;
const int row = blockIdx.y * blockDim.y + threadIdx.y;
const int input_index = row * num_columns + col;
const int output_index = col * num_rows + row;
out[ output_index ] = in[ input_index ];
}
__global__ void init_matrix( real_t* in ) {
const int c = threadIdx.x + blockDim.x * blockIdx.x;
const int r = threadIdx.y + blockDim.y * blockIdx.y;
const int idx = c + gridDim.x * blockDim.x * r;
in[ idx ] = (real_t) idx;
}
void print_matrix( const real_t* m, int r, int c, int stride ) {
for( int i = 0; i != r; ++i ) {
for( int j = 0; j != c; ++j ) std::cout << m[ i * stride + j ] << ' ';
std::cout << '\n';
}
std::cout << std::endl;
}
//------------------------------------------------------------------------------
int main(int argc, char** argv ) {
const dim3 BLOCKS( 512, 512 );
const dim3 THREADS_PER_BLOCK( 16, 16 );
const int ROWS = 512 * 16; // 8192
const int COLUMNS = 512 * 16; // 8192
const size_t SIZE = ROWS * COLUMNS * sizeof( real_t );
// device storage
real_t* dev_in = 0;
real_t* dev_out = 0;
cudaMalloc( &dev_in, SIZE );
cudaMalloc( &dev_out, SIZE );
// host storage
std::vector< real_t > outmatrix( ROWS * COLUMNS );
// initialize matrix with kernel; much faster than using
// for loops on the cpu
init_matrix<<<dim3( COLUMNS, ROWS ), 1>>>( dev_in );
cudaMemcpy( &outmatrix[ 0 ], dev_in, SIZE, cudaMemcpyDeviceToHost );
// print upper 4x4 left corner of input matrix
std::cout << "INPUT MATRIX - " << ROWS << " rows, " << COLUMNS << " columns" << std::endl;
print_matrix( &outmatrix[ 0 ], 4, 4, COLUMNS );
// create events for timing execution
cudaEvent_t start = cudaEvent_t();
cudaEvent_t stop = cudaEvent_t();
cudaEventCreate( &start );
cudaEventCreate( &stop );
// record time into start event
cudaEventRecord( start, 0 ); // 0 is the default stream id
// execute kernel
transpose<<<BLOCKS, THREADS_PER_BLOCK>>>( dev_in, dev_out, ROWS, COLUMNS );
// issue request to record time into stop event
cudaEventRecord( stop, 0 );
// synchronize stop event to wait for end of kernel execution on stream 0
cudaEventSynchronize( stop );
// compute elapsed time (done by CUDA run-time)
float elapsed = 0.f;
cudaEventElapsedTime( &elapsed, start, stop );
std::cout << "Elapsed time (ms): " << elapsed << std::endl;
// copy output data from device(gpu) to host(cpu)
cudaMemcpy( &outmatrix[ 0 ], dev_out, SIZE, cudaMemcpyDeviceToHost );
// print upper 4x4 corner of transposed matrix
std::cout << "\nOUTPUT MATRIX - " << COLUMNS << " rows, " << ROWS << " columns" << std::endl;
print_matrix( &outmatrix[ 0 ], 4, 4, ROWS );
// free memory
cudaFree( dev_in );
cudaFree( dev_out );
// release events
cudaEventDestroy( start );
cudaEventDestroy( stop );
return 0;
} | // #CSCS CUDA Training
//
// #Example 3.1 - transpose matrix
//
// #Author: Ugo Varetto
//
// #Goal: compute the transpose of a matrix and time operation using
// GPU's on-board performance counters through streams; print the result in ms (10^-3 s)
//
// #Rationale: shows how to time GPU computation
//
// #Solution: straightworwad, simply compute the thread id associated with the element
// and copy the transposed data into the output matrix; wrap kernel calls with event
// recording and print time information
//
// #Code: typical flow + timing:
// 1) compute launch grid configuration
// 2) allocate data on host(cpu) and device(gpu)
// 3) initialize data directly on the GPU
// 4) create events
// 5) record start time
// 6) launch kernel
// 7) synchronize events to guarantee that kernel execution is finished
// 8) record stop time
// 9) read data back
// 10) print timing information as stop - start time
// 11) delete events
// 12) free memory
// The code uses the default stream 0; streams are used to sychronize operations
// to guarantee that all operations in the same stream are executed sequentially.
//
// #Compilation: nvcc -arch=sm_13 3_1_transpose-timing.cu -o transpose-timing
//
// #Execution: ./transpose-timing
//
// #Note: kernel invocations ( foo<<<...>>>(...) ) are *always* asynchronous and a call to
// cudaThreadSynchronize() is required to wait for the end of kernel execution from
// a host thread; in case of synchronous copy operations like cudaMemcpy(...,cudaDeviceToHost)
// kernel execution is guaranteed to be terminated before data are copied
//
// #Note: the code is C++ also because the default compilation mode for CUDA is C++, all functions
// are named with C++ convention and the syntax is checked by default against C++ grammar rules
//
// #Note: -arch=sm_13 allows the code to run on every card with hw architecture GT200 (gtx 2xx) or better
//
// #Note: -arch=sm_13 is the lowest architecture version that supports double precision
//
// #Note: the example can be extended to read configuration data and matrix size from the command line
//#include <cuda_runtime.h> // automatically added by nvcc
#include <hip/hip_runtime.h>
#include <vector>
#include <iostream>
typedef float real_t;
__global__ void transpose( const real_t* in, real_t *out, int num_rows, int num_columns ) {
const int col = blockIdx.x * blockDim.x + threadIdx.x;
const int row = blockIdx.y * blockDim.y + threadIdx.y;
const int input_index = row * num_columns + col;
const int output_index = col * num_rows + row;
out[ output_index ] = in[ input_index ];
}
__global__ void init_matrix( real_t* in ) {
const int c = threadIdx.x + blockDim.x * blockIdx.x;
const int r = threadIdx.y + blockDim.y * blockIdx.y;
const int idx = c + gridDim.x * blockDim.x * r;
in[ idx ] = (real_t) idx;
}
void print_matrix( const real_t* m, int r, int c, int stride ) {
for( int i = 0; i != r; ++i ) {
for( int j = 0; j != c; ++j ) std::cout << m[ i * stride + j ] << ' ';
std::cout << '\n';
}
std::cout << std::endl;
}
//------------------------------------------------------------------------------
int main(int argc, char** argv ) {
const dim3 BLOCKS( 512, 512 );
const dim3 THREADS_PER_BLOCK( 16, 16 );
const int ROWS = 512 * 16; // 8192
const int COLUMNS = 512 * 16; // 8192
const size_t SIZE = ROWS * COLUMNS * sizeof( real_t );
// device storage
real_t* dev_in = 0;
real_t* dev_out = 0;
hipMalloc( &dev_in, SIZE );
hipMalloc( &dev_out, SIZE );
// host storage
std::vector< real_t > outmatrix( ROWS * COLUMNS );
// initialize matrix with kernel; much faster than using
// for loops on the cpu
init_matrix<<<dim3( COLUMNS, ROWS ), 1>>>( dev_in );
hipMemcpy( &outmatrix[ 0 ], dev_in, SIZE, hipMemcpyDeviceToHost );
// print upper 4x4 left corner of input matrix
std::cout << "INPUT MATRIX - " << ROWS << " rows, " << COLUMNS << " columns" << std::endl;
print_matrix( &outmatrix[ 0 ], 4, 4, COLUMNS );
// create events for timing execution
hipEvent_t start = hipEvent_t();
hipEvent_t stop = hipEvent_t();
hipEventCreate( &start );
hipEventCreate( &stop );
// record time into start event
hipEventRecord( start, 0 ); // 0 is the default stream id
// execute kernel
transpose<<<BLOCKS, THREADS_PER_BLOCK>>>( dev_in, dev_out, ROWS, COLUMNS );
// issue request to record time into stop event
hipEventRecord( stop, 0 );
// synchronize stop event to wait for end of kernel execution on stream 0
hipEventSynchronize( stop );
// compute elapsed time (done by CUDA run-time)
float elapsed = 0.f;
hipEventElapsedTime( &elapsed, start, stop );
std::cout << "Elapsed time (ms): " << elapsed << std::endl;
// copy output data from device(gpu) to host(cpu)
hipMemcpy( &outmatrix[ 0 ], dev_out, SIZE, hipMemcpyDeviceToHost );
// print upper 4x4 corner of transposed matrix
std::cout << "\nOUTPUT MATRIX - " << COLUMNS << " rows, " << ROWS << " columns" << std::endl;
print_matrix( &outmatrix[ 0 ], 4, 4, ROWS );
// free memory
hipFree( dev_in );
hipFree( dev_out );
// release events
hipEventDestroy( start );
hipEventDestroy( stop );
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | // #CSCS CUDA Training
//
// #Example 3.1 - transpose matrix
//
// #Author: Ugo Varetto
//
// #Goal: compute the transpose of a matrix and time operation using
// GPU's on-board performance counters through streams; print the result in ms (10^-3 s)
//
// #Rationale: shows how to time GPU computation
//
// #Solution: straightworwad, simply compute the thread id associated with the element
// and copy the transposed data into the output matrix; wrap kernel calls with event
// recording and print time information
//
// #Code: typical flow + timing:
// 1) compute launch grid configuration
// 2) allocate data on host(cpu) and device(gpu)
// 3) initialize data directly on the GPU
// 4) create events
// 5) record start time
// 6) launch kernel
// 7) synchronize events to guarantee that kernel execution is finished
// 8) record stop time
// 9) read data back
// 10) print timing information as stop - start time
// 11) delete events
// 12) free memory
// The code uses the default stream 0; streams are used to sychronize operations
// to guarantee that all operations in the same stream are executed sequentially.
//
// #Compilation: nvcc -arch=sm_13 3_1_transpose-timing.cu -o transpose-timing
//
// #Execution: ./transpose-timing
//
// #Note: kernel invocations ( foo<<<...>>>(...) ) are *always* asynchronous and a call to
// cudaThreadSynchronize() is required to wait for the end of kernel execution from
// a host thread; in case of synchronous copy operations like cudaMemcpy(...,cudaDeviceToHost)
// kernel execution is guaranteed to be terminated before data are copied
//
// #Note: the code is C++ also because the default compilation mode for CUDA is C++, all functions
// are named with C++ convention and the syntax is checked by default against C++ grammar rules
//
// #Note: -arch=sm_13 allows the code to run on every card with hw architecture GT200 (gtx 2xx) or better
//
// #Note: -arch=sm_13 is the lowest architecture version that supports double precision
//
// #Note: the example can be extended to read configuration data and matrix size from the command line
//#include <cuda_runtime.h> // automatically added by nvcc
#include <hip/hip_runtime.h>
#include <vector>
#include <iostream>
typedef float real_t;
__global__ void transpose( const real_t* in, real_t *out, int num_rows, int num_columns ) {
const int col = blockIdx.x * blockDim.x + threadIdx.x;
const int row = blockIdx.y * blockDim.y + threadIdx.y;
const int input_index = row * num_columns + col;
const int output_index = col * num_rows + row;
out[ output_index ] = in[ input_index ];
}
__global__ void init_matrix( real_t* in ) {
const int c = threadIdx.x + blockDim.x * blockIdx.x;
const int r = threadIdx.y + blockDim.y * blockIdx.y;
const int idx = c + gridDim.x * blockDim.x * r;
in[ idx ] = (real_t) idx;
}
void print_matrix( const real_t* m, int r, int c, int stride ) {
for( int i = 0; i != r; ++i ) {
for( int j = 0; j != c; ++j ) std::cout << m[ i * stride + j ] << ' ';
std::cout << '\n';
}
std::cout << std::endl;
}
//------------------------------------------------------------------------------
int main(int argc, char** argv ) {
const dim3 BLOCKS( 512, 512 );
const dim3 THREADS_PER_BLOCK( 16, 16 );
const int ROWS = 512 * 16; // 8192
const int COLUMNS = 512 * 16; // 8192
const size_t SIZE = ROWS * COLUMNS * sizeof( real_t );
// device storage
real_t* dev_in = 0;
real_t* dev_out = 0;
hipMalloc( &dev_in, SIZE );
hipMalloc( &dev_out, SIZE );
// host storage
std::vector< real_t > outmatrix( ROWS * COLUMNS );
// initialize matrix with kernel; much faster than using
// for loops on the cpu
init_matrix<<<dim3( COLUMNS, ROWS ), 1>>>( dev_in );
hipMemcpy( &outmatrix[ 0 ], dev_in, SIZE, hipMemcpyDeviceToHost );
// print upper 4x4 left corner of input matrix
std::cout << "INPUT MATRIX - " << ROWS << " rows, " << COLUMNS << " columns" << std::endl;
print_matrix( &outmatrix[ 0 ], 4, 4, COLUMNS );
// create events for timing execution
hipEvent_t start = hipEvent_t();
hipEvent_t stop = hipEvent_t();
hipEventCreate( &start );
hipEventCreate( &stop );
// record time into start event
hipEventRecord( start, 0 ); // 0 is the default stream id
// execute kernel
transpose<<<BLOCKS, THREADS_PER_BLOCK>>>( dev_in, dev_out, ROWS, COLUMNS );
// issue request to record time into stop event
hipEventRecord( stop, 0 );
// synchronize stop event to wait for end of kernel execution on stream 0
hipEventSynchronize( stop );
// compute elapsed time (done by CUDA run-time)
float elapsed = 0.f;
hipEventElapsedTime( &elapsed, start, stop );
std::cout << "Elapsed time (ms): " << elapsed << std::endl;
// copy output data from device(gpu) to host(cpu)
hipMemcpy( &outmatrix[ 0 ], dev_out, SIZE, hipMemcpyDeviceToHost );
// print upper 4x4 corner of transposed matrix
std::cout << "\nOUTPUT MATRIX - " << COLUMNS << " rows, " << ROWS << " columns" << std::endl;
print_matrix( &outmatrix[ 0 ], 4, 4, ROWS );
// free memory
hipFree( dev_in );
hipFree( dev_out );
// release events
hipEventDestroy( start );
hipEventDestroy( stop );
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9transposePKfPfii
.globl _Z9transposePKfPfii
.p2align 8
.type _Z9transposePKfPfii,@function
_Z9transposePKfPfii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b64 s[4:5], s[0:1], 0x10
v_and_b32_e32 v1, 0x3ff, v0
v_bfe_u32 v0, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_lshr_b32 s2, s2, 16
v_mad_u64_u32 v[2:3], null, s14, s3, v[1:2]
v_mad_u64_u32 v[3:4], null, s15, s2, v[0:1]
s_load_b128 s[0:3], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[0:1], null, v3, s5, v[2:3]
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b32 v4, v[0:1], off
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[0:1], null, v2, s4, v[3:4]
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[0:1]
v_add_co_u32 v0, vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_store_b32 v[0:1], v4, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9transposePKfPfii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9transposePKfPfii, .Lfunc_end0-_Z9transposePKfPfii
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z11init_matrixPf
.globl _Z11init_matrixPf
.p2align 8
.type _Z11init_matrixPf,@function
_Z11init_matrixPf:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x14
s_load_b32 s3, s[0:1], 0x8
v_bfe_u32 v1, v0, 10, 10
v_and_b32_e32 v0, 0x3ff, v0
s_load_b64 s[0:1], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s4, s2, 16
s_and_b32 s2, s2, 0xffff
v_mad_u64_u32 v[2:3], null, s15, s4, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[3:4], null, v2, s3, s[14:15]
v_mad_u64_u32 v[1:2], null, v3, s2, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v2, 31, v1
v_cvt_f32_i32_e32 v4, v1
v_lshlrev_b64 v[2:3], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v2
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v3, vcc_lo
global_store_b32 v[0:1], v4, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11init_matrixPf
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 264
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z11init_matrixPf, .Lfunc_end1-_Z11init_matrixPf
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9transposePKfPfii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9transposePKfPfii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: hidden_block_count_x
- .offset: 12
.size: 4
.value_kind: hidden_block_count_y
- .offset: 16
.size: 4
.value_kind: hidden_block_count_z
- .offset: 20
.size: 2
.value_kind: hidden_group_size_x
- .offset: 22
.size: 2
.value_kind: hidden_group_size_y
- .offset: 24
.size: 2
.value_kind: hidden_group_size_z
- .offset: 26
.size: 2
.value_kind: hidden_remainder_x
- .offset: 28
.size: 2
.value_kind: hidden_remainder_y
- .offset: 30
.size: 2
.value_kind: hidden_remainder_z
- .offset: 48
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 72
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 264
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11init_matrixPf
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z11init_matrixPf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | // #CSCS CUDA Training
//
// #Example 3.1 - transpose matrix
//
// #Author: Ugo Varetto
//
// #Goal: compute the transpose of a matrix and time operation using
// GPU's on-board performance counters through streams; print the result in ms (10^-3 s)
//
// #Rationale: shows how to time GPU computation
//
// #Solution: straightworwad, simply compute the thread id associated with the element
// and copy the transposed data into the output matrix; wrap kernel calls with event
// recording and print time information
//
// #Code: typical flow + timing:
// 1) compute launch grid configuration
// 2) allocate data on host(cpu) and device(gpu)
// 3) initialize data directly on the GPU
// 4) create events
// 5) record start time
// 6) launch kernel
// 7) synchronize events to guarantee that kernel execution is finished
// 8) record stop time
// 9) read data back
// 10) print timing information as stop - start time
// 11) delete events
// 12) free memory
// The code uses the default stream 0; streams are used to sychronize operations
// to guarantee that all operations in the same stream are executed sequentially.
//
// #Compilation: nvcc -arch=sm_13 3_1_transpose-timing.cu -o transpose-timing
//
// #Execution: ./transpose-timing
//
// #Note: kernel invocations ( foo<<<...>>>(...) ) are *always* asynchronous and a call to
// cudaThreadSynchronize() is required to wait for the end of kernel execution from
// a host thread; in case of synchronous copy operations like cudaMemcpy(...,cudaDeviceToHost)
// kernel execution is guaranteed to be terminated before data are copied
//
// #Note: the code is C++ also because the default compilation mode for CUDA is C++, all functions
// are named with C++ convention and the syntax is checked by default against C++ grammar rules
//
// #Note: -arch=sm_13 allows the code to run on every card with hw architecture GT200 (gtx 2xx) or better
//
// #Note: -arch=sm_13 is the lowest architecture version that supports double precision
//
// #Note: the example can be extended to read configuration data and matrix size from the command line
//#include <cuda_runtime.h> // automatically added by nvcc
#include <hip/hip_runtime.h>
#include <vector>
#include <iostream>
typedef float real_t;
__global__ void transpose( const real_t* in, real_t *out, int num_rows, int num_columns ) {
const int col = blockIdx.x * blockDim.x + threadIdx.x;
const int row = blockIdx.y * blockDim.y + threadIdx.y;
const int input_index = row * num_columns + col;
const int output_index = col * num_rows + row;
out[ output_index ] = in[ input_index ];
}
__global__ void init_matrix( real_t* in ) {
const int c = threadIdx.x + blockDim.x * blockIdx.x;
const int r = threadIdx.y + blockDim.y * blockIdx.y;
const int idx = c + gridDim.x * blockDim.x * r;
in[ idx ] = (real_t) idx;
}
void print_matrix( const real_t* m, int r, int c, int stride ) {
for( int i = 0; i != r; ++i ) {
for( int j = 0; j != c; ++j ) std::cout << m[ i * stride + j ] << ' ';
std::cout << '\n';
}
std::cout << std::endl;
}
//------------------------------------------------------------------------------
int main(int argc, char** argv ) {
const dim3 BLOCKS( 512, 512 );
const dim3 THREADS_PER_BLOCK( 16, 16 );
const int ROWS = 512 * 16; // 8192
const int COLUMNS = 512 * 16; // 8192
const size_t SIZE = ROWS * COLUMNS * sizeof( real_t );
// device storage
real_t* dev_in = 0;
real_t* dev_out = 0;
hipMalloc( &dev_in, SIZE );
hipMalloc( &dev_out, SIZE );
// host storage
std::vector< real_t > outmatrix( ROWS * COLUMNS );
// initialize matrix with kernel; much faster than using
// for loops on the cpu
init_matrix<<<dim3( COLUMNS, ROWS ), 1>>>( dev_in );
hipMemcpy( &outmatrix[ 0 ], dev_in, SIZE, hipMemcpyDeviceToHost );
// print upper 4x4 left corner of input matrix
std::cout << "INPUT MATRIX - " << ROWS << " rows, " << COLUMNS << " columns" << std::endl;
print_matrix( &outmatrix[ 0 ], 4, 4, COLUMNS );
// create events for timing execution
hipEvent_t start = hipEvent_t();
hipEvent_t stop = hipEvent_t();
hipEventCreate( &start );
hipEventCreate( &stop );
// record time into start event
hipEventRecord( start, 0 ); // 0 is the default stream id
// execute kernel
transpose<<<BLOCKS, THREADS_PER_BLOCK>>>( dev_in, dev_out, ROWS, COLUMNS );
// issue request to record time into stop event
hipEventRecord( stop, 0 );
// synchronize stop event to wait for end of kernel execution on stream 0
hipEventSynchronize( stop );
// compute elapsed time (done by CUDA run-time)
float elapsed = 0.f;
hipEventElapsedTime( &elapsed, start, stop );
std::cout << "Elapsed time (ms): " << elapsed << std::endl;
// copy output data from device(gpu) to host(cpu)
hipMemcpy( &outmatrix[ 0 ], dev_out, SIZE, hipMemcpyDeviceToHost );
// print upper 4x4 corner of transposed matrix
std::cout << "\nOUTPUT MATRIX - " << COLUMNS << " rows, " << ROWS << " columns" << std::endl;
print_matrix( &outmatrix[ 0 ], 4, 4, ROWS );
// free memory
hipFree( dev_in );
hipFree( dev_out );
// release events
hipEventDestroy( start );
hipEventDestroy( stop );
return 0;
} | .text
.file "003_1_transpose-timing.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z24__device_stub__transposePKfPfii # -- Begin function _Z24__device_stub__transposePKfPfii
.p2align 4, 0x90
.type _Z24__device_stub__transposePKfPfii,@function
_Z24__device_stub__transposePKfPfii: # @_Z24__device_stub__transposePKfPfii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9transposePKfPfii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z24__device_stub__transposePKfPfii, .Lfunc_end0-_Z24__device_stub__transposePKfPfii
.cfi_endproc
# -- End function
.globl _Z26__device_stub__init_matrixPf # -- Begin function _Z26__device_stub__init_matrixPf
.p2align 4, 0x90
.type _Z26__device_stub__init_matrixPf,@function
_Z26__device_stub__init_matrixPf: # @_Z26__device_stub__init_matrixPf
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z11init_matrixPf, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end1:
.size _Z26__device_stub__init_matrixPf, .Lfunc_end1-_Z26__device_stub__init_matrixPf
.cfi_endproc
# -- End function
.globl _Z12print_matrixPKfiii # -- Begin function _Z12print_matrixPKfiii
.p2align 4, 0x90
.type _Z12print_matrixPKfiii,@function
_Z12print_matrixPKfiii: # @_Z12print_matrixPKfiii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $24, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %edx, 12(%rsp) # 4-byte Spill
testl %esi, %esi
je .LBB2_6
# %bb.1: # %.preheader.lr.ph
movq %rdi, %r14
movslq %ecx, %r13
movl %esi, %eax
movq %rax, 16(%rsp) # 8-byte Spill
movl 12(%rsp), %r15d # 4-byte Reload
shlq $2, %r13
xorl %ebx, %ebx
leaq 11(%rsp), %r12
jmp .LBB2_2
.p2align 4, 0x90
.LBB2_11: # %._crit_edge
# in Loop: Header=BB2_2 Depth=1
movb $10, 10(%rsp)
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
cmpq $0, _ZSt4cout+16(%rax)
je .LBB2_13
# %bb.12: # in Loop: Header=BB2_2 Depth=1
movl $_ZSt4cout, %edi
movl $1, %edx
leaq 10(%rsp), %rsi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.LBB2_14: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c.exit
# in Loop: Header=BB2_2 Depth=1
incq %rbx
addq %r13, %r14
cmpq 16(%rsp), %rbx # 8-byte Folded Reload
je .LBB2_6
.LBB2_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB2_4 Depth 2
cmpl $0, 12(%rsp) # 4-byte Folded Reload
je .LBB2_11
# %bb.3: # %.lr.ph
# in Loop: Header=BB2_2 Depth=1
xorl %ebp, %ebp
jmp .LBB2_4
.p2align 4, 0x90
.LBB2_15: # in Loop: Header=BB2_4 Depth=2
movq %rax, %rdi
movl $32, %esi
callq _ZNSo3putEc
.LBB2_16: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c.exit13
# in Loop: Header=BB2_4 Depth=2
incq %rbp
cmpq %rbp, %r15
je .LBB2_11
.LBB2_4: # Parent Loop BB2_2 Depth=1
# => This Inner Loop Header: Depth=2
movss (%r14,%rbp,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movb $32, 11(%rsp)
movq (%rax), %rcx
movq -24(%rcx), %rcx
cmpq $0, 16(%rax,%rcx)
je .LBB2_15
# %bb.5: # in Loop: Header=BB2_4 Depth=2
movl $1, %edx
movq %rax, %rdi
movq %r12, %rsi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
jmp .LBB2_16
.p2align 4, 0x90
.LBB2_13: # in Loop: Header=BB2_2 Depth=1
movl $_ZSt4cout, %edi
movl $10, %esi
callq _ZNSo3putEc
jmp .LBB2_14
.LBB2_6: # %._crit_edge18
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB2_17
# %bb.7: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB2_9
# %bb.8:
movzbl 67(%rbx), %eax
jmp .LBB2_10
.LBB2_9:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB2_10: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB2_17:
.cfi_def_cfa_offset 80
callq _ZSt16__throw_bad_castv
.Lfunc_end2:
.size _Z12print_matrixPKfiii, .Lfunc_end2-_Z12print_matrixPKfiii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.Lfunc_begin0:
.cfi_startproc
.cfi_personality 3, __gxx_personality_v0
.cfi_lsda 3, .Lexception0
# %bb.0: # %_ZNSt6vectorIfSaIfEEC2EmRKS0_.exit
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $144, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq $0, 8(%rsp)
movq $0, 24(%rsp)
.cfi_escape 0x2e, 0x00
leaq 8(%rsp), %rdi
movl $268435456, %esi # imm = 0x10000000
callq hipMalloc
.cfi_escape 0x2e, 0x00
leaq 24(%rsp), %rdi
movl $268435456, %esi # imm = 0x10000000
callq hipMalloc
.cfi_escape 0x2e, 0x00
movl $268435456, %edi # imm = 0x10000000
callq _Znwm
movq %rax, %rbx
.cfi_escape 0x2e, 0x00
movl $268435456, %edx # imm = 0x10000000
movq %rax, %rdi
xorl %esi, %esi
callq memset@PLT
.Ltmp0:
.cfi_escape 0x2e, 0x00
movabsq $35184372097024, %rdi # imm = 0x200000002000
movabsq $4294967297, %rdx # imm = 0x100000001
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
.Ltmp1:
# %bb.1:
testl %eax, %eax
jne .LBB3_4
# %bb.2:
movq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 80(%rsp), %rax
movq %rax, 32(%rsp)
.Ltmp2:
.cfi_escape 0x2e, 0x00
leaq 96(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 64(%rsp), %rdx
leaq 56(%rsp), %rcx
callq __hipPopCallConfiguration
.Ltmp3:
# %bb.3: # %.noexc
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
.Ltmp4:
.cfi_escape 0x2e, 0x10
leaq 32(%rsp), %r9
movl $_Z11init_matrixPf, %edi
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.Ltmp5:
.LBB3_4:
movq 8(%rsp), %rsi
.Ltmp6:
.cfi_escape 0x2e, 0x00
movl $268435456, %edx # imm = 0x10000000
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
.Ltmp7:
# %bb.5:
.Ltmp8:
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $15, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp9:
# %bb.6: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit
.Ltmp10:
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
movl $8192, %esi # imm = 0x2000
callq _ZNSolsEi
.Ltmp11:
# %bb.7:
.Ltmp12:
movq %rax, %r14
.cfi_escape 0x2e, 0x00
movl $.L.str.1, %esi
movl $7, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp13:
# %bb.8: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit22
.Ltmp14:
.cfi_escape 0x2e, 0x00
movq %r14, %rdi
movl $8192, %esi # imm = 0x2000
callq _ZNSolsEi
.Ltmp15:
# %bb.9:
.Ltmp16:
movq %rax, %r14
.cfi_escape 0x2e, 0x00
movl $.L.str.2, %esi
movl $8, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp17:
# %bb.10: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit24
movq (%r14), %rax
movq -24(%rax), %rax
movq 240(%r14,%rax), %r15
testq %r15, %r15
je .LBB3_11
# %bb.13: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%r15)
je .LBB3_15
# %bb.14:
movzbl 67(%r15), %eax
jmp .LBB3_17
.LBB3_15:
.Ltmp18:
.cfi_escape 0x2e, 0x00
movq %r15, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
.Ltmp19:
# %bb.16: # %.noexc51
movq (%r15), %rax
.Ltmp20:
.cfi_escape 0x2e, 0x00
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
.Ltmp21:
.LBB3_17: # %_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc.exit.i
.Ltmp22:
.cfi_escape 0x2e, 0x00
movsbl %al, %esi
movq %r14, %rdi
callq _ZNSo3putEc
.Ltmp23:
# %bb.18: # %.noexc53
.Ltmp24:
.cfi_escape 0x2e, 0x00
movq %rax, %rdi
callq _ZNSo5flushEv
.Ltmp25:
# %bb.19: # %_ZNSolsEPFRSoS_E.exit
.Ltmp26:
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
movl $4, %esi
movl $4, %edx
movl $8192, %ecx # imm = 0x2000
callq _Z12print_matrixPKfiii
.Ltmp27:
# %bb.20:
movq $0, 16(%rsp)
movq $0, (%rsp)
.Ltmp28:
.cfi_escape 0x2e, 0x00
leaq 16(%rsp), %rdi
callq hipEventCreate
.Ltmp29:
# %bb.21:
.Ltmp30:
.cfi_escape 0x2e, 0x00
movq %rsp, %rdi
callq hipEventCreate
.Ltmp31:
# %bb.22:
movq 16(%rsp), %rdi
.Ltmp32:
.cfi_escape 0x2e, 0x00
xorl %esi, %esi
callq hipEventRecord
.Ltmp33:
# %bb.23:
.Ltmp34:
.cfi_escape 0x2e, 0x00
movabsq $2199023256064, %rdi # imm = 0x20000000200
movabsq $68719476752, %rdx # imm = 0x1000000010
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
.Ltmp35:
# %bb.24:
testl %eax, %eax
jne .LBB3_27
# %bb.25:
movq 8(%rsp), %rax
movq 24(%rsp), %rcx
movq %rax, 64(%rsp)
movq %rcx, 56(%rsp)
movl $8192, 76(%rsp) # imm = 0x2000
movl $8192, 72(%rsp) # imm = 0x2000
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 56(%rsp), %rax
movq %rax, 104(%rsp)
leaq 76(%rsp), %rax
movq %rax, 112(%rsp)
leaq 72(%rsp), %rax
movq %rax, 120(%rsp)
.Ltmp36:
.cfi_escape 0x2e, 0x00
leaq 40(%rsp), %rdi
leaq 80(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 136(%rsp), %rcx
callq __hipPopCallConfiguration
.Ltmp37:
# %bb.26: # %.noexc32
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 80(%rsp), %rcx
movl 88(%rsp), %r8d
.Ltmp38:
.cfi_escape 0x2e, 0x10
leaq 96(%rsp), %r9
movl $_Z9transposePKfPfii, %edi
pushq 136(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.Ltmp39:
.LBB3_27:
movq (%rsp), %rdi
.Ltmp40:
.cfi_escape 0x2e, 0x00
xorl %esi, %esi
callq hipEventRecord
.Ltmp41:
# %bb.28:
movq (%rsp), %rdi
.Ltmp42:
.cfi_escape 0x2e, 0x00
callq hipEventSynchronize
.Ltmp43:
# %bb.29:
movl $0, 96(%rsp)
movq 16(%rsp), %rsi
movq (%rsp), %rdx
.Ltmp45:
.cfi_escape 0x2e, 0x00
leaq 96(%rsp), %rdi
callq hipEventElapsedTime
.Ltmp46:
# %bb.30:
.Ltmp47:
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
movl $.L.str.3, %esi
movl $19, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp48:
# %bb.31: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit35
movss 96(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
.Ltmp49:
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
.Ltmp50:
# %bb.32: # %_ZNSolsEf.exit
movq %rax, %r14
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%r14,%rax), %r15
testq %r15, %r15
je .LBB3_46
# %bb.33: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i56
cmpb $0, 56(%r15)
je .LBB3_35
# %bb.34:
movzbl 67(%r15), %eax
jmp .LBB3_37
.LBB3_35:
.Ltmp51:
.cfi_escape 0x2e, 0x00
movq %r15, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
.Ltmp52:
# %bb.36: # %.noexc61
movq (%r15), %rax
.Ltmp53:
.cfi_escape 0x2e, 0x00
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
.Ltmp54:
.LBB3_37: # %_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc.exit.i58
.Ltmp55:
.cfi_escape 0x2e, 0x00
movsbl %al, %esi
movq %r14, %rdi
callq _ZNSo3putEc
.Ltmp56:
# %bb.38: # %.noexc63
.Ltmp57:
.cfi_escape 0x2e, 0x00
movq %rax, %rdi
callq _ZNSo5flushEv
.Ltmp58:
# %bb.39: # %_ZNSolsEPFRSoS_E.exit38
movq 24(%rsp), %rsi
.Ltmp59:
.cfi_escape 0x2e, 0x00
movl $268435456, %edx # imm = 0x10000000
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
.Ltmp60:
# %bb.40:
.Ltmp61:
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
movl $.L.str.4, %esi
movl $17, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp62:
# %bb.41: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit40
.Ltmp63:
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
movl $8192, %esi # imm = 0x2000
callq _ZNSolsEi
.Ltmp64:
# %bb.42:
.Ltmp65:
movq %rax, %r14
.cfi_escape 0x2e, 0x00
movl $.L.str.1, %esi
movl $7, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp66:
# %bb.43: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit42
.Ltmp67:
.cfi_escape 0x2e, 0x00
movq %r14, %rdi
movl $8192, %esi # imm = 0x2000
callq _ZNSolsEi
.Ltmp68:
# %bb.44:
.Ltmp69:
movq %rax, %r14
.cfi_escape 0x2e, 0x00
movl $.L.str.2, %esi
movl $8, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp70:
# %bb.45: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit44
movq (%r14), %rax
movq -24(%rax), %rax
movq 240(%r14,%rax), %r15
testq %r15, %r15
je .LBB3_46
# %bb.48: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i67
cmpb $0, 56(%r15)
je .LBB3_50
# %bb.49:
movzbl 67(%r15), %eax
jmp .LBB3_52
.LBB3_50:
.Ltmp71:
.cfi_escape 0x2e, 0x00
movq %r15, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
.Ltmp72:
# %bb.51: # %.noexc72
movq (%r15), %rax
.Ltmp73:
.cfi_escape 0x2e, 0x00
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
.Ltmp74:
.LBB3_52: # %_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc.exit.i69
.Ltmp75:
.cfi_escape 0x2e, 0x00
movsbl %al, %esi
movq %r14, %rdi
callq _ZNSo3putEc
.Ltmp76:
# %bb.53: # %.noexc74
.Ltmp77:
.cfi_escape 0x2e, 0x00
movq %rax, %rdi
callq _ZNSo5flushEv
.Ltmp78:
# %bb.54: # %_ZNSolsEPFRSoS_E.exit46
.Ltmp79:
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
movl $4, %esi
movl $4, %edx
movl $8192, %ecx # imm = 0x2000
callq _Z12print_matrixPKfiii
.Ltmp80:
# %bb.55:
movq 8(%rsp), %rdi
.Ltmp81:
.cfi_escape 0x2e, 0x00
callq hipFree
.Ltmp82:
# %bb.56:
movq 24(%rsp), %rdi
.Ltmp83:
.cfi_escape 0x2e, 0x00
callq hipFree
.Ltmp84:
# %bb.57:
movq 16(%rsp), %rdi
.Ltmp85:
.cfi_escape 0x2e, 0x00
callq hipEventDestroy
.Ltmp86:
# %bb.58:
movq (%rsp), %rdi
.Ltmp87:
.cfi_escape 0x2e, 0x00
callq hipEventDestroy
.Ltmp88:
# %bb.59: # %_ZNSt6vectorIfSaIfEED2Ev.exit
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
callq _ZdlPv
xorl %eax, %eax
addq $144, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB3_46: # %.invoke
.cfi_def_cfa_offset 176
.Ltmp89:
.cfi_escape 0x2e, 0x00
callq _ZSt16__throw_bad_castv
.Ltmp90:
# %bb.47: # %.cont
.LBB3_11:
.Ltmp92:
.cfi_escape 0x2e, 0x00
callq _ZSt16__throw_bad_castv
.Ltmp93:
# %bb.12: # %.noexc50
.LBB3_63:
.Ltmp44:
jmp .LBB3_61
.LBB3_62:
.Ltmp94:
jmp .LBB3_61
.LBB3_60:
.Ltmp91:
.LBB3_61:
movq %rax, %r14
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
callq _ZdlPv
.cfi_escape 0x2e, 0x00
movq %r14, %rdi
callq _Unwind_Resume@PLT
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
.section .gcc_except_table,"a",@progbits
.p2align 2, 0x0
GCC_except_table3:
.Lexception0:
.byte 255 # @LPStart Encoding = omit
.byte 255 # @TType Encoding = omit
.byte 1 # Call site Encoding = uleb128
.uleb128 .Lcst_end0-.Lcst_begin0
.Lcst_begin0:
.uleb128 .Lfunc_begin0-.Lfunc_begin0 # >> Call Site 1 <<
.uleb128 .Ltmp0-.Lfunc_begin0 # Call between .Lfunc_begin0 and .Ltmp0
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp0-.Lfunc_begin0 # >> Call Site 2 <<
.uleb128 .Ltmp27-.Ltmp0 # Call between .Ltmp0 and .Ltmp27
.uleb128 .Ltmp94-.Lfunc_begin0 # jumps to .Ltmp94
.byte 0 # On action: cleanup
.uleb128 .Ltmp28-.Lfunc_begin0 # >> Call Site 3 <<
.uleb128 .Ltmp43-.Ltmp28 # Call between .Ltmp28 and .Ltmp43
.uleb128 .Ltmp44-.Lfunc_begin0 # jumps to .Ltmp44
.byte 0 # On action: cleanup
.uleb128 .Ltmp45-.Lfunc_begin0 # >> Call Site 4 <<
.uleb128 .Ltmp90-.Ltmp45 # Call between .Ltmp45 and .Ltmp90
.uleb128 .Ltmp91-.Lfunc_begin0 # jumps to .Ltmp91
.byte 0 # On action: cleanup
.uleb128 .Ltmp92-.Lfunc_begin0 # >> Call Site 5 <<
.uleb128 .Ltmp93-.Ltmp92 # Call between .Ltmp92 and .Ltmp93
.uleb128 .Ltmp94-.Lfunc_begin0 # jumps to .Ltmp94
.byte 0 # On action: cleanup
.uleb128 .Ltmp93-.Lfunc_begin0 # >> Call Site 6 <<
.uleb128 .Lfunc_end3-.Ltmp93 # Call between .Ltmp93 and .Lfunc_end3
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.Lcst_end0:
.p2align 2, 0x0
# -- End function
.text
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9transposePKfPfii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11init_matrixPf, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9transposePKfPfii,@object # @_Z9transposePKfPfii
.section .rodata,"a",@progbits
.globl _Z9transposePKfPfii
.p2align 3, 0x0
_Z9transposePKfPfii:
.quad _Z24__device_stub__transposePKfPfii
.size _Z9transposePKfPfii, 8
.type _Z11init_matrixPf,@object # @_Z11init_matrixPf
.globl _Z11init_matrixPf
.p2align 3, 0x0
_Z11init_matrixPf:
.quad _Z26__device_stub__init_matrixPf
.size _Z11init_matrixPf, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "INPUT MATRIX - "
.size .L.str, 16
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz " rows, "
.size .L.str.1, 8
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz " columns"
.size .L.str.2, 9
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Elapsed time (ms): "
.size .L.str.3, 20
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "\nOUTPUT MATRIX - "
.size .L.str.4, 18
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z9transposePKfPfii"
.size .L__unnamed_1, 20
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z11init_matrixPf"
.size .L__unnamed_2, 18
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__transposePKfPfii
.addrsig_sym _Z26__device_stub__init_matrixPf
.addrsig_sym __gxx_personality_v0
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Unwind_Resume
.addrsig_sym _Z9transposePKfPfii
.addrsig_sym _Z11init_matrixPf
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z11init_matrixPf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_TID.Y ; /* 0x0000000000007919 */
/* 0x000e220000002200 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0030*/ S2R R7, SR_CTAID.Y ; /* 0x0000000000077919 */
/* 0x000e280000002600 */
/*0040*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x000e680000002500 */
/*0050*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000ea20000002100 */
/*0060*/ IMAD R0, R7, c[0x0][0x4], R0 ; /* 0x0000010007007a24 */
/* 0x001fc800078e0200 */
/*0070*/ IMAD R0, R0, c[0x0][0xc], R5 ; /* 0x0000030000007a24 */
/* 0x002fc800078e0205 */
/*0080*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x004fe200078e0203 */
/*0090*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fc600000001ff */
/*00a0*/ I2F R5, R0 ; /* 0x0000000000057306 */
/* 0x000e2e0000201400 */
/*00b0*/ IMAD.WIDE R2, R0, R3, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fca00078e0203 */
/*00c0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x001fe2000c101904 */
/*00d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00e0*/ BRA 0xe0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z9transposePKfPfii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R4, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff047435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e280000002100 */
/*0050*/ S2R R5, SR_CTAID.Y ; /* 0x0000000000057919 */
/* 0x000e680000002600 */
/*0060*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e620000002200 */
/*0070*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fc400078e0203 */
/*0080*/ IMAD R5, R5, c[0x0][0x4], R2 ; /* 0x0000010005057a24 */
/* 0x002fc800078e0202 */
/*0090*/ IMAD R2, R5, c[0x0][0x174], R0 ; /* 0x00005d0005027a24 */
/* 0x000fc800078e0200 */
/*00a0*/ IMAD.WIDE R2, R2, R4, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fcc00078e0204 */
/*00b0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ IMAD R5, R0, c[0x0][0x170], R5 ; /* 0x00005c0000057a24 */
/* 0x000fc800078e0205 */
/*00d0*/ IMAD.WIDE R4, R5, R4, c[0x0][0x168] ; /* 0x00005a0005047625 */
/* 0x000fca00078e0204 */
/*00e0*/ STG.E [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x004fe2000c101904 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9transposePKfPfii
.globl _Z9transposePKfPfii
.p2align 8
.type _Z9transposePKfPfii,@function
_Z9transposePKfPfii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b64 s[4:5], s[0:1], 0x10
v_and_b32_e32 v1, 0x3ff, v0
v_bfe_u32 v0, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_lshr_b32 s2, s2, 16
v_mad_u64_u32 v[2:3], null, s14, s3, v[1:2]
v_mad_u64_u32 v[3:4], null, s15, s2, v[0:1]
s_load_b128 s[0:3], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[0:1], null, v3, s5, v[2:3]
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b32 v4, v[0:1], off
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[0:1], null, v2, s4, v[3:4]
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[0:1]
v_add_co_u32 v0, vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_store_b32 v[0:1], v4, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9transposePKfPfii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9transposePKfPfii, .Lfunc_end0-_Z9transposePKfPfii
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z11init_matrixPf
.globl _Z11init_matrixPf
.p2align 8
.type _Z11init_matrixPf,@function
_Z11init_matrixPf:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x14
s_load_b32 s3, s[0:1], 0x8
v_bfe_u32 v1, v0, 10, 10
v_and_b32_e32 v0, 0x3ff, v0
s_load_b64 s[0:1], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s4, s2, 16
s_and_b32 s2, s2, 0xffff
v_mad_u64_u32 v[2:3], null, s15, s4, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[3:4], null, v2, s3, s[14:15]
v_mad_u64_u32 v[1:2], null, v3, s2, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v2, 31, v1
v_cvt_f32_i32_e32 v4, v1
v_lshlrev_b64 v[2:3], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v2
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v3, vcc_lo
global_store_b32 v[0:1], v4, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11init_matrixPf
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 264
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z11init_matrixPf, .Lfunc_end1-_Z11init_matrixPf
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9transposePKfPfii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9transposePKfPfii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: hidden_block_count_x
- .offset: 12
.size: 4
.value_kind: hidden_block_count_y
- .offset: 16
.size: 4
.value_kind: hidden_block_count_z
- .offset: 20
.size: 2
.value_kind: hidden_group_size_x
- .offset: 22
.size: 2
.value_kind: hidden_group_size_y
- .offset: 24
.size: 2
.value_kind: hidden_group_size_z
- .offset: 26
.size: 2
.value_kind: hidden_remainder_x
- .offset: 28
.size: 2
.value_kind: hidden_remainder_y
- .offset: 30
.size: 2
.value_kind: hidden_remainder_z
- .offset: 48
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 72
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 264
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11init_matrixPf
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z11init_matrixPf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
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