system stringclasses 7 values | input stringlengths 10 94.5k | output stringlengths 14 55.5k |
|---|---|---|
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001ac9d4_00000000-6_003_1_transpose-timing.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB4036:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4036:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z12print_matrixPKfiii
.type _Z12print_matrixPKfiii, @function
_Z12print_matrixPKfiii:
.LFB4032:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $40, %rsp
.cfi_def_cfa_offset 96
movl %edx, (%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 24(%rsp)
xorl %eax, %eax
testl %esi, %esi
je .L4
movq %rdi, %r15
movslq %esi, %rax
movq %rax, 8(%rsp)
movl $0, %r14d
movl $0, %r13d
leaq _ZSt4cout(%rip), %rbp
jmp .L5
.L6:
movl $32, %esi
call _ZNSo3putEc@PLT
.L7:
addq $4, %rbx
cmpq %r12, %rbx
je .L12
.L8:
pxor %xmm0, %xmm0
cvtss2sd (%rbx), %xmm0
movq %rbp, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
movb $32, 23(%rsp)
movq (%rax), %rax
movq -24(%rax), %rax
cmpq $0, 16(%rdi,%rax)
je .L6
leaq 23(%rsp), %rsi
movl $1, %edx
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
jmp .L7
.L12:
movb $10, 23(%rsp)
movq 0(%rbp), %rax
movq -24(%rax), %rax
cmpq $0, 16(%rbp,%rax)
je .L9
leaq 23(%rsp), %rsi
movl $1, %edx
movq %rbp, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
.L10:
addq $1, %r13
movl 4(%rsp), %eax
addl %eax, %r14d
movq 8(%rsp), %rax
cmpq %rax, %r13
je .L4
.L5:
cmpl $0, (%rsp)
je .L12
movslq %r14d, %rdx
leaq (%r15,%rdx,4), %rbx
movslq (%rsp), %rax
addq %rdx, %rax
leaq (%r15,%rax,4), %r12
jmp .L8
.L9:
movl $10, %esi
movq %rbp, %rdi
call _ZNSo3putEc@PLT
jmp .L10
.L4:
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
leaq _ZSt4cout(%rip), %rdx
movq 240(%rdx,%rax), %rbx
testq %rbx, %rbx
je .L20
cmpb $0, 56(%rbx)
je .L15
movzbl 67(%rbx), %eax
.L16:
movsbl %al, %esi
leaq _ZSt4cout(%rip), %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movq 24(%rsp), %rax
subq %fs:40, %rax
jne .L21
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L20:
.cfi_restore_state
movq 24(%rsp), %rax
subq %fs:40, %rax
jne .L22
call _ZSt16__throw_bad_castv@PLT
.L22:
call __stack_chk_fail@PLT
.L15:
movq %rbx, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%rbx), %rax
movl $10, %esi
movq %rbx, %rdi
call *48(%rax)
jmp .L16
.L21:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4032:
.size _Z12print_matrixPKfiii, .-_Z12print_matrixPKfiii
.globl _Z33__device_stub__Z9transposePKfPfiiPKfPfii
.type _Z33__device_stub__Z9transposePKfPfiiPKfPfii, @function
_Z33__device_stub__Z9transposePKfPfiiPKfPfii:
.LFB4058:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L27
.L23:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L28
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L27:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9transposePKfPfii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L23
.L28:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4058:
.size _Z33__device_stub__Z9transposePKfPfiiPKfPfii, .-_Z33__device_stub__Z9transposePKfPfiiPKfPfii
.globl _Z9transposePKfPfii
.type _Z9transposePKfPfii, @function
_Z9transposePKfPfii:
.LFB4059:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z9transposePKfPfiiPKfPfii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4059:
.size _Z9transposePKfPfii, .-_Z9transposePKfPfii
.globl _Z31__device_stub__Z11init_matrixPfPf
.type _Z31__device_stub__Z11init_matrixPfPf, @function
_Z31__device_stub__Z11init_matrixPfPf:
.LFB4060:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L35
.L31:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L36
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L35:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z11init_matrixPf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L31
.L36:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4060:
.size _Z31__device_stub__Z11init_matrixPfPf, .-_Z31__device_stub__Z11init_matrixPfPf
.globl _Z11init_matrixPf
.type _Z11init_matrixPf, @function
_Z11init_matrixPf:
.LFB4061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z11init_matrixPfPf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4061:
.size _Z11init_matrixPf, .-_Z11init_matrixPf
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z11init_matrixPf"
.LC1:
.string "_Z9transposePKfPfii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB4063:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z11init_matrixPf(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z9transposePKfPfii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4063:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .text._ZNSt6vectorIfSaIfEED2Ev,"axG",@progbits,_ZNSt6vectorIfSaIfEED5Ev,comdat
.align 2
.weak _ZNSt6vectorIfSaIfEED2Ev
.type _ZNSt6vectorIfSaIfEED2Ev, @function
_ZNSt6vectorIfSaIfEED2Ev:
.LFB4378:
.cfi_startproc
endbr64
movq (%rdi), %rax
testq %rax, %rax
je .L44
subq $8, %rsp
.cfi_def_cfa_offset 16
movq 16(%rdi), %rsi
subq %rax, %rsi
movq %rax, %rdi
call _ZdlPvm@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.L44:
ret
.cfi_endproc
.LFE4378:
.size _ZNSt6vectorIfSaIfEED2Ev, .-_ZNSt6vectorIfSaIfEED2Ev
.weak _ZNSt6vectorIfSaIfEED1Ev
.set _ZNSt6vectorIfSaIfEED1Ev,_ZNSt6vectorIfSaIfEED2Ev
.section .rodata.str1.1
.LC3:
.string "INPUT MATRIX - "
.LC4:
.string " rows, "
.LC5:
.string " columns"
.LC6:
.string "Elapsed time (ms): "
.LC7:
.string "\nOUTPUT MATRIX - "
.text
.globl main
.type main, @function
main:
.LFB4033:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA4033
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $112, %rsp
.cfi_def_cfa_offset 128
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
movl $512, 24(%rsp)
movl $512, 28(%rsp)
movl $1, 32(%rsp)
movl $16, 36(%rsp)
movl $16, 40(%rsp)
movl $1, 44(%rsp)
movq $0, 8(%rsp)
movq $0, 16(%rsp)
leaq 8(%rsp), %rdi
movl $268435456, %esi
.LEHB0:
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $268435456, %esi
call cudaMalloc@PLT
movl $268435456, %edi
call _Znwm@PLT
.LEHE0:
movq %rax, %rbx
movq %rax, 80(%rsp)
leaq 268435456(%rax), %rdx
movq %rdx, 96(%rsp)
movl $0x00000000, (%rax)
leaq 4(%rax), %rax
.L48:
movl $0x00000000, (%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L48
movq %rdx, 88(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $8192, 48(%rsp)
movl $8192, 52(%rsp)
movl $1, 56(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 64(%rsp), %rdx
movl $1, %ecx
movq 48(%rsp), %rdi
movl $1, %esi
.LEHB1:
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L49
movq 8(%rsp), %rdi
call _Z31__device_stub__Z11init_matrixPfPf
.L49:
movl $2, %ecx
movl $268435456, %edx
movq 8(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
leaq .LC3(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl $8192, %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
leaq .LC4(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl $8192, %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
leaq .LC5(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $8192, %ecx
movl $4, %edx
movl $4, %esi
movq %rbx, %rdi
call _Z12print_matrixPKfiii
movq $0, 48(%rsp)
movq $0, 64(%rsp)
leaq 48(%rsp), %rdi
call cudaEventCreate@PLT
leaq 64(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 48(%rsp), %rdi
call cudaEventRecord@PLT
movl 44(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movq 24(%rsp), %rdi
movl 32(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L50
movl $8192, %ecx
movl $8192, %edx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z33__device_stub__Z9transposePKfPfiiPKfPfii
.L50:
movl $0, %esi
movq 64(%rsp), %rdi
call cudaEventRecord@PLT
movq 64(%rsp), %rdi
call cudaEventSynchronize@PLT
movl $0x00000000, 4(%rsp)
leaq 4(%rsp), %rdi
movq 64(%rsp), %rdx
movq 48(%rsp), %rsi
call cudaEventElapsedTime@PLT
leaq .LC6(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
pxor %xmm0, %xmm0
cvtss2sd 4(%rsp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $2, %ecx
movl $268435456, %edx
movq 16(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
leaq .LC7(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl $8192, %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
leaq .LC4(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl $8192, %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
leaq .LC5(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $8192, %ecx
movl $4, %edx
movl $4, %esi
movq %rbx, %rdi
call _Z12print_matrixPKfiii
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 48(%rsp), %rdi
call cudaEventDestroy@PLT
movq 64(%rsp), %rdi
call cudaEventDestroy@PLT
.LEHE1:
leaq 80(%rsp), %rdi
call _ZNSt6vectorIfSaIfEED1Ev
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L58
movl $0, %eax
addq $112, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L54:
.cfi_restore_state
endbr64
movq %rax, %rbx
leaq 80(%rsp), %rdi
call _ZNSt6vectorIfSaIfEED1Ev
movq 104(%rsp), %rax
subq %fs:40, %rax
je .L52
call __stack_chk_fail@PLT
.L52:
movq %rbx, %rdi
.LEHB2:
call _Unwind_Resume@PLT
.LEHE2:
.L58:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4033:
.globl __gxx_personality_v0
.section .gcc_except_table,"a",@progbits
.LLSDA4033:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE4033-.LLSDACSB4033
.LLSDACSB4033:
.uleb128 .LEHB0-.LFB4033
.uleb128 .LEHE0-.LEHB0
.uleb128 0
.uleb128 0
.uleb128 .LEHB1-.LFB4033
.uleb128 .LEHE1-.LEHB1
.uleb128 .L54-.LFB4033
.uleb128 0
.uleb128 .LEHB2-.LFB4033
.uleb128 .LEHE2-.LEHB2
.uleb128 0
.uleb128 0
.LLSDACSE4033:
.text
.size main, .-main
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.hidden DW.ref.__gxx_personality_v0
.weak DW.ref.__gxx_personality_v0
.section .data.rel.local.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat
.align 8
.type DW.ref.__gxx_personality_v0, @object
.size DW.ref.__gxx_personality_v0, 8
DW.ref.__gxx_personality_v0:
.quad __gxx_personality_v0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "003_1_transpose-timing.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z24__device_stub__transposePKfPfii # -- Begin function _Z24__device_stub__transposePKfPfii
.p2align 4, 0x90
.type _Z24__device_stub__transposePKfPfii,@function
_Z24__device_stub__transposePKfPfii: # @_Z24__device_stub__transposePKfPfii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9transposePKfPfii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z24__device_stub__transposePKfPfii, .Lfunc_end0-_Z24__device_stub__transposePKfPfii
.cfi_endproc
# -- End function
.globl _Z26__device_stub__init_matrixPf # -- Begin function _Z26__device_stub__init_matrixPf
.p2align 4, 0x90
.type _Z26__device_stub__init_matrixPf,@function
_Z26__device_stub__init_matrixPf: # @_Z26__device_stub__init_matrixPf
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z11init_matrixPf, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end1:
.size _Z26__device_stub__init_matrixPf, .Lfunc_end1-_Z26__device_stub__init_matrixPf
.cfi_endproc
# -- End function
.globl _Z12print_matrixPKfiii # -- Begin function _Z12print_matrixPKfiii
.p2align 4, 0x90
.type _Z12print_matrixPKfiii,@function
_Z12print_matrixPKfiii: # @_Z12print_matrixPKfiii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $24, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %edx, 12(%rsp) # 4-byte Spill
testl %esi, %esi
je .LBB2_6
# %bb.1: # %.preheader.lr.ph
movq %rdi, %r14
movslq %ecx, %r13
movl %esi, %eax
movq %rax, 16(%rsp) # 8-byte Spill
movl 12(%rsp), %r15d # 4-byte Reload
shlq $2, %r13
xorl %ebx, %ebx
leaq 11(%rsp), %r12
jmp .LBB2_2
.p2align 4, 0x90
.LBB2_11: # %._crit_edge
# in Loop: Header=BB2_2 Depth=1
movb $10, 10(%rsp)
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
cmpq $0, _ZSt4cout+16(%rax)
je .LBB2_13
# %bb.12: # in Loop: Header=BB2_2 Depth=1
movl $_ZSt4cout, %edi
movl $1, %edx
leaq 10(%rsp), %rsi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.LBB2_14: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c.exit
# in Loop: Header=BB2_2 Depth=1
incq %rbx
addq %r13, %r14
cmpq 16(%rsp), %rbx # 8-byte Folded Reload
je .LBB2_6
.LBB2_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB2_4 Depth 2
cmpl $0, 12(%rsp) # 4-byte Folded Reload
je .LBB2_11
# %bb.3: # %.lr.ph
# in Loop: Header=BB2_2 Depth=1
xorl %ebp, %ebp
jmp .LBB2_4
.p2align 4, 0x90
.LBB2_15: # in Loop: Header=BB2_4 Depth=2
movq %rax, %rdi
movl $32, %esi
callq _ZNSo3putEc
.LBB2_16: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c.exit13
# in Loop: Header=BB2_4 Depth=2
incq %rbp
cmpq %rbp, %r15
je .LBB2_11
.LBB2_4: # Parent Loop BB2_2 Depth=1
# => This Inner Loop Header: Depth=2
movss (%r14,%rbp,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movb $32, 11(%rsp)
movq (%rax), %rcx
movq -24(%rcx), %rcx
cmpq $0, 16(%rax,%rcx)
je .LBB2_15
# %bb.5: # in Loop: Header=BB2_4 Depth=2
movl $1, %edx
movq %rax, %rdi
movq %r12, %rsi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
jmp .LBB2_16
.p2align 4, 0x90
.LBB2_13: # in Loop: Header=BB2_2 Depth=1
movl $_ZSt4cout, %edi
movl $10, %esi
callq _ZNSo3putEc
jmp .LBB2_14
.LBB2_6: # %._crit_edge18
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB2_17
# %bb.7: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB2_9
# %bb.8:
movzbl 67(%rbx), %eax
jmp .LBB2_10
.LBB2_9:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB2_10: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB2_17:
.cfi_def_cfa_offset 80
callq _ZSt16__throw_bad_castv
.Lfunc_end2:
.size _Z12print_matrixPKfiii, .Lfunc_end2-_Z12print_matrixPKfiii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.Lfunc_begin0:
.cfi_startproc
.cfi_personality 3, __gxx_personality_v0
.cfi_lsda 3, .Lexception0
# %bb.0: # %_ZNSt6vectorIfSaIfEEC2EmRKS0_.exit
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $144, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq $0, 8(%rsp)
movq $0, 24(%rsp)
.cfi_escape 0x2e, 0x00
leaq 8(%rsp), %rdi
movl $268435456, %esi # imm = 0x10000000
callq hipMalloc
.cfi_escape 0x2e, 0x00
leaq 24(%rsp), %rdi
movl $268435456, %esi # imm = 0x10000000
callq hipMalloc
.cfi_escape 0x2e, 0x00
movl $268435456, %edi # imm = 0x10000000
callq _Znwm
movq %rax, %rbx
.cfi_escape 0x2e, 0x00
movl $268435456, %edx # imm = 0x10000000
movq %rax, %rdi
xorl %esi, %esi
callq memset@PLT
.Ltmp0:
.cfi_escape 0x2e, 0x00
movabsq $35184372097024, %rdi # imm = 0x200000002000
movabsq $4294967297, %rdx # imm = 0x100000001
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
.Ltmp1:
# %bb.1:
testl %eax, %eax
jne .LBB3_4
# %bb.2:
movq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 80(%rsp), %rax
movq %rax, 32(%rsp)
.Ltmp2:
.cfi_escape 0x2e, 0x00
leaq 96(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 64(%rsp), %rdx
leaq 56(%rsp), %rcx
callq __hipPopCallConfiguration
.Ltmp3:
# %bb.3: # %.noexc
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
.Ltmp4:
.cfi_escape 0x2e, 0x10
leaq 32(%rsp), %r9
movl $_Z11init_matrixPf, %edi
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.Ltmp5:
.LBB3_4:
movq 8(%rsp), %rsi
.Ltmp6:
.cfi_escape 0x2e, 0x00
movl $268435456, %edx # imm = 0x10000000
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
.Ltmp7:
# %bb.5:
.Ltmp8:
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $15, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp9:
# %bb.6: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit
.Ltmp10:
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
movl $8192, %esi # imm = 0x2000
callq _ZNSolsEi
.Ltmp11:
# %bb.7:
.Ltmp12:
movq %rax, %r14
.cfi_escape 0x2e, 0x00
movl $.L.str.1, %esi
movl $7, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp13:
# %bb.8: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit22
.Ltmp14:
.cfi_escape 0x2e, 0x00
movq %r14, %rdi
movl $8192, %esi # imm = 0x2000
callq _ZNSolsEi
.Ltmp15:
# %bb.9:
.Ltmp16:
movq %rax, %r14
.cfi_escape 0x2e, 0x00
movl $.L.str.2, %esi
movl $8, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp17:
# %bb.10: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit24
movq (%r14), %rax
movq -24(%rax), %rax
movq 240(%r14,%rax), %r15
testq %r15, %r15
je .LBB3_11
# %bb.13: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%r15)
je .LBB3_15
# %bb.14:
movzbl 67(%r15), %eax
jmp .LBB3_17
.LBB3_15:
.Ltmp18:
.cfi_escape 0x2e, 0x00
movq %r15, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
.Ltmp19:
# %bb.16: # %.noexc51
movq (%r15), %rax
.Ltmp20:
.cfi_escape 0x2e, 0x00
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
.Ltmp21:
.LBB3_17: # %_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc.exit.i
.Ltmp22:
.cfi_escape 0x2e, 0x00
movsbl %al, %esi
movq %r14, %rdi
callq _ZNSo3putEc
.Ltmp23:
# %bb.18: # %.noexc53
.Ltmp24:
.cfi_escape 0x2e, 0x00
movq %rax, %rdi
callq _ZNSo5flushEv
.Ltmp25:
# %bb.19: # %_ZNSolsEPFRSoS_E.exit
.Ltmp26:
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
movl $4, %esi
movl $4, %edx
movl $8192, %ecx # imm = 0x2000
callq _Z12print_matrixPKfiii
.Ltmp27:
# %bb.20:
movq $0, 16(%rsp)
movq $0, (%rsp)
.Ltmp28:
.cfi_escape 0x2e, 0x00
leaq 16(%rsp), %rdi
callq hipEventCreate
.Ltmp29:
# %bb.21:
.Ltmp30:
.cfi_escape 0x2e, 0x00
movq %rsp, %rdi
callq hipEventCreate
.Ltmp31:
# %bb.22:
movq 16(%rsp), %rdi
.Ltmp32:
.cfi_escape 0x2e, 0x00
xorl %esi, %esi
callq hipEventRecord
.Ltmp33:
# %bb.23:
.Ltmp34:
.cfi_escape 0x2e, 0x00
movabsq $2199023256064, %rdi # imm = 0x20000000200
movabsq $68719476752, %rdx # imm = 0x1000000010
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
.Ltmp35:
# %bb.24:
testl %eax, %eax
jne .LBB3_27
# %bb.25:
movq 8(%rsp), %rax
movq 24(%rsp), %rcx
movq %rax, 64(%rsp)
movq %rcx, 56(%rsp)
movl $8192, 76(%rsp) # imm = 0x2000
movl $8192, 72(%rsp) # imm = 0x2000
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 56(%rsp), %rax
movq %rax, 104(%rsp)
leaq 76(%rsp), %rax
movq %rax, 112(%rsp)
leaq 72(%rsp), %rax
movq %rax, 120(%rsp)
.Ltmp36:
.cfi_escape 0x2e, 0x00
leaq 40(%rsp), %rdi
leaq 80(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 136(%rsp), %rcx
callq __hipPopCallConfiguration
.Ltmp37:
# %bb.26: # %.noexc32
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 80(%rsp), %rcx
movl 88(%rsp), %r8d
.Ltmp38:
.cfi_escape 0x2e, 0x10
leaq 96(%rsp), %r9
movl $_Z9transposePKfPfii, %edi
pushq 136(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.Ltmp39:
.LBB3_27:
movq (%rsp), %rdi
.Ltmp40:
.cfi_escape 0x2e, 0x00
xorl %esi, %esi
callq hipEventRecord
.Ltmp41:
# %bb.28:
movq (%rsp), %rdi
.Ltmp42:
.cfi_escape 0x2e, 0x00
callq hipEventSynchronize
.Ltmp43:
# %bb.29:
movl $0, 96(%rsp)
movq 16(%rsp), %rsi
movq (%rsp), %rdx
.Ltmp45:
.cfi_escape 0x2e, 0x00
leaq 96(%rsp), %rdi
callq hipEventElapsedTime
.Ltmp46:
# %bb.30:
.Ltmp47:
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
movl $.L.str.3, %esi
movl $19, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp48:
# %bb.31: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit35
movss 96(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
.Ltmp49:
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
.Ltmp50:
# %bb.32: # %_ZNSolsEf.exit
movq %rax, %r14
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%r14,%rax), %r15
testq %r15, %r15
je .LBB3_46
# %bb.33: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i56
cmpb $0, 56(%r15)
je .LBB3_35
# %bb.34:
movzbl 67(%r15), %eax
jmp .LBB3_37
.LBB3_35:
.Ltmp51:
.cfi_escape 0x2e, 0x00
movq %r15, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
.Ltmp52:
# %bb.36: # %.noexc61
movq (%r15), %rax
.Ltmp53:
.cfi_escape 0x2e, 0x00
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
.Ltmp54:
.LBB3_37: # %_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc.exit.i58
.Ltmp55:
.cfi_escape 0x2e, 0x00
movsbl %al, %esi
movq %r14, %rdi
callq _ZNSo3putEc
.Ltmp56:
# %bb.38: # %.noexc63
.Ltmp57:
.cfi_escape 0x2e, 0x00
movq %rax, %rdi
callq _ZNSo5flushEv
.Ltmp58:
# %bb.39: # %_ZNSolsEPFRSoS_E.exit38
movq 24(%rsp), %rsi
.Ltmp59:
.cfi_escape 0x2e, 0x00
movl $268435456, %edx # imm = 0x10000000
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
.Ltmp60:
# %bb.40:
.Ltmp61:
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
movl $.L.str.4, %esi
movl $17, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp62:
# %bb.41: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit40
.Ltmp63:
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
movl $8192, %esi # imm = 0x2000
callq _ZNSolsEi
.Ltmp64:
# %bb.42:
.Ltmp65:
movq %rax, %r14
.cfi_escape 0x2e, 0x00
movl $.L.str.1, %esi
movl $7, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp66:
# %bb.43: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit42
.Ltmp67:
.cfi_escape 0x2e, 0x00
movq %r14, %rdi
movl $8192, %esi # imm = 0x2000
callq _ZNSolsEi
.Ltmp68:
# %bb.44:
.Ltmp69:
movq %rax, %r14
.cfi_escape 0x2e, 0x00
movl $.L.str.2, %esi
movl $8, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp70:
# %bb.45: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit44
movq (%r14), %rax
movq -24(%rax), %rax
movq 240(%r14,%rax), %r15
testq %r15, %r15
je .LBB3_46
# %bb.48: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i67
cmpb $0, 56(%r15)
je .LBB3_50
# %bb.49:
movzbl 67(%r15), %eax
jmp .LBB3_52
.LBB3_50:
.Ltmp71:
.cfi_escape 0x2e, 0x00
movq %r15, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
.Ltmp72:
# %bb.51: # %.noexc72
movq (%r15), %rax
.Ltmp73:
.cfi_escape 0x2e, 0x00
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
.Ltmp74:
.LBB3_52: # %_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc.exit.i69
.Ltmp75:
.cfi_escape 0x2e, 0x00
movsbl %al, %esi
movq %r14, %rdi
callq _ZNSo3putEc
.Ltmp76:
# %bb.53: # %.noexc74
.Ltmp77:
.cfi_escape 0x2e, 0x00
movq %rax, %rdi
callq _ZNSo5flushEv
.Ltmp78:
# %bb.54: # %_ZNSolsEPFRSoS_E.exit46
.Ltmp79:
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
movl $4, %esi
movl $4, %edx
movl $8192, %ecx # imm = 0x2000
callq _Z12print_matrixPKfiii
.Ltmp80:
# %bb.55:
movq 8(%rsp), %rdi
.Ltmp81:
.cfi_escape 0x2e, 0x00
callq hipFree
.Ltmp82:
# %bb.56:
movq 24(%rsp), %rdi
.Ltmp83:
.cfi_escape 0x2e, 0x00
callq hipFree
.Ltmp84:
# %bb.57:
movq 16(%rsp), %rdi
.Ltmp85:
.cfi_escape 0x2e, 0x00
callq hipEventDestroy
.Ltmp86:
# %bb.58:
movq (%rsp), %rdi
.Ltmp87:
.cfi_escape 0x2e, 0x00
callq hipEventDestroy
.Ltmp88:
# %bb.59: # %_ZNSt6vectorIfSaIfEED2Ev.exit
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
callq _ZdlPv
xorl %eax, %eax
addq $144, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB3_46: # %.invoke
.cfi_def_cfa_offset 176
.Ltmp89:
.cfi_escape 0x2e, 0x00
callq _ZSt16__throw_bad_castv
.Ltmp90:
# %bb.47: # %.cont
.LBB3_11:
.Ltmp92:
.cfi_escape 0x2e, 0x00
callq _ZSt16__throw_bad_castv
.Ltmp93:
# %bb.12: # %.noexc50
.LBB3_63:
.Ltmp44:
jmp .LBB3_61
.LBB3_62:
.Ltmp94:
jmp .LBB3_61
.LBB3_60:
.Ltmp91:
.LBB3_61:
movq %rax, %r14
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
callq _ZdlPv
.cfi_escape 0x2e, 0x00
movq %r14, %rdi
callq _Unwind_Resume@PLT
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
.section .gcc_except_table,"a",@progbits
.p2align 2, 0x0
GCC_except_table3:
.Lexception0:
.byte 255 # @LPStart Encoding = omit
.byte 255 # @TType Encoding = omit
.byte 1 # Call site Encoding = uleb128
.uleb128 .Lcst_end0-.Lcst_begin0
.Lcst_begin0:
.uleb128 .Lfunc_begin0-.Lfunc_begin0 # >> Call Site 1 <<
.uleb128 .Ltmp0-.Lfunc_begin0 # Call between .Lfunc_begin0 and .Ltmp0
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp0-.Lfunc_begin0 # >> Call Site 2 <<
.uleb128 .Ltmp27-.Ltmp0 # Call between .Ltmp0 and .Ltmp27
.uleb128 .Ltmp94-.Lfunc_begin0 # jumps to .Ltmp94
.byte 0 # On action: cleanup
.uleb128 .Ltmp28-.Lfunc_begin0 # >> Call Site 3 <<
.uleb128 .Ltmp43-.Ltmp28 # Call between .Ltmp28 and .Ltmp43
.uleb128 .Ltmp44-.Lfunc_begin0 # jumps to .Ltmp44
.byte 0 # On action: cleanup
.uleb128 .Ltmp45-.Lfunc_begin0 # >> Call Site 4 <<
.uleb128 .Ltmp90-.Ltmp45 # Call between .Ltmp45 and .Ltmp90
.uleb128 .Ltmp91-.Lfunc_begin0 # jumps to .Ltmp91
.byte 0 # On action: cleanup
.uleb128 .Ltmp92-.Lfunc_begin0 # >> Call Site 5 <<
.uleb128 .Ltmp93-.Ltmp92 # Call between .Ltmp92 and .Ltmp93
.uleb128 .Ltmp94-.Lfunc_begin0 # jumps to .Ltmp94
.byte 0 # On action: cleanup
.uleb128 .Ltmp93-.Lfunc_begin0 # >> Call Site 6 <<
.uleb128 .Lfunc_end3-.Ltmp93 # Call between .Ltmp93 and .Lfunc_end3
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.Lcst_end0:
.p2align 2, 0x0
# -- End function
.text
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9transposePKfPfii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11init_matrixPf, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9transposePKfPfii,@object # @_Z9transposePKfPfii
.section .rodata,"a",@progbits
.globl _Z9transposePKfPfii
.p2align 3, 0x0
_Z9transposePKfPfii:
.quad _Z24__device_stub__transposePKfPfii
.size _Z9transposePKfPfii, 8
.type _Z11init_matrixPf,@object # @_Z11init_matrixPf
.globl _Z11init_matrixPf
.p2align 3, 0x0
_Z11init_matrixPf:
.quad _Z26__device_stub__init_matrixPf
.size _Z11init_matrixPf, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "INPUT MATRIX - "
.size .L.str, 16
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz " rows, "
.size .L.str.1, 8
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz " columns"
.size .L.str.2, 9
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Elapsed time (ms): "
.size .L.str.3, 20
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "\nOUTPUT MATRIX - "
.size .L.str.4, 18
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z9transposePKfPfii"
.size .L__unnamed_1, 20
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z11init_matrixPf"
.size .L__unnamed_2, 18
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__transposePKfPfii
.addrsig_sym _Z26__device_stub__init_matrixPf
.addrsig_sym __gxx_personality_v0
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Unwind_Resume
.addrsig_sym _Z9transposePKfPfii
.addrsig_sym _Z11init_matrixPf
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void meshgrid_create(float* xx, float* yy, int w, int h, float K02, float K12) {
int i = blockIdx.x*blockDim.x + threadIdx.x;
int j = blockIdx.y*blockDim.y + threadIdx.y;
if (i < h && j < w) {
xx[j*h + i] = j - K02;
yy[j*h + i] = i - K12;
}
} | code for sm_80
Function : _Z15meshgrid_createPfS_iiff
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e280000002100 */
/*0030*/ S2R R7, SR_CTAID.Y ; /* 0x0000000000077919 */
/* 0x000e680000002600 */
/*0040*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e620000002200 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0060*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x174], PT ; /* 0x00005d0000007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R7, R7, c[0x0][0x4], R2 ; /* 0x0000010007077a24 */
/* 0x002fca00078e0202 */
/*0080*/ ISETP.GE.OR P0, PT, R7, c[0x0][0x170], P0 ; /* 0x00005c0007007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ I2F R2, R7 ; /* 0x0000000700027306 */
/* 0x000e220000201400 */
/*00b0*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*00c0*/ IMAD R4, R7, c[0x0][0x174], R0 ; /* 0x00005d0007047a24 */
/* 0x000fe200078e0200 */
/*00d0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fca0000000a00 */
/*00e0*/ I2F R3, R0 ; /* 0x0000000000037306 */
/* 0x000e620000201400 */
/*00f0*/ FADD R9, R2, -c[0x0][0x178] ; /* 0x80005e0002097621 */
/* 0x001fe40000000000 */
/*0100*/ FADD R11, R3, -c[0x0][0x17c] ; /* 0x80005f00030b7621 */
/* 0x002fe40000000000 */
/*0110*/ IMAD.WIDE R2, R4, R5, c[0x0][0x160] ; /* 0x0000580004027625 */
/* 0x000fc800078e0205 */
/*0120*/ IMAD.WIDE R4, R4, R5, c[0x0][0x168] ; /* 0x00005a0004047625 */
/* 0x000fe200078e0205 */
/*0130*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x000fe8000c101904 */
/*0140*/ STG.E [R4.64], R11 ; /* 0x0000000b04007986 */
/* 0x000fe2000c101904 */
/*0150*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0160*/ BRA 0x160; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void meshgrid_create(float* xx, float* yy, int w, int h, float K02, float K12) {
int i = blockIdx.x*blockDim.x + threadIdx.x;
int j = blockIdx.y*blockDim.y + threadIdx.y;
if (i < h && j < w) {
xx[j*h + i] = j - K02;
yy[j*h + i] = i - K12;
}
} | .file "tmpxft_00078e43_00000000-6_meshgrid_create.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z41__device_stub__Z15meshgrid_createPfS_iiffPfS_iiff
.type _Z41__device_stub__Z15meshgrid_createPfS_iiffPfS_iiff, @function
_Z41__device_stub__Z15meshgrid_createPfS_iiffPfS_iiff:
.LFB2051:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movss %xmm0, 4(%rsp)
movss %xmm1, (%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
movq %rsp, %rax
movq %rax, 136(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 184
pushq 40(%rsp)
.cfi_def_cfa_offset 192
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z15meshgrid_createPfS_iiff(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z41__device_stub__Z15meshgrid_createPfS_iiffPfS_iiff, .-_Z41__device_stub__Z15meshgrid_createPfS_iiffPfS_iiff
.globl _Z15meshgrid_createPfS_iiff
.type _Z15meshgrid_createPfS_iiff, @function
_Z15meshgrid_createPfS_iiff:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z41__device_stub__Z15meshgrid_createPfS_iiffPfS_iiff
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z15meshgrid_createPfS_iiff, .-_Z15meshgrid_createPfS_iiff
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z15meshgrid_createPfS_iiff"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z15meshgrid_createPfS_iiff(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void meshgrid_create(float* xx, float* yy, int w, int h, float K02, float K12) {
int i = blockIdx.x*blockDim.x + threadIdx.x;
int j = blockIdx.y*blockDim.y + threadIdx.y;
if (i < h && j < w) {
xx[j*h + i] = j - K02;
yy[j*h + i] = i - K12;
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void meshgrid_create(float* xx, float* yy, int w, int h, float K02, float K12) {
int i = blockIdx.x*blockDim.x + threadIdx.x;
int j = blockIdx.y*blockDim.y + threadIdx.y;
if (i < h && j < w) {
xx[j*h + i] = j - K02;
yy[j*h + i] = i - K12;
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void meshgrid_create(float* xx, float* yy, int w, int h, float K02, float K12) {
int i = blockIdx.x*blockDim.x + threadIdx.x;
int j = blockIdx.y*blockDim.y + threadIdx.y;
if (i < h && j < w) {
xx[j*h + i] = j - K02;
yy[j*h + i] = i - K12;
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z15meshgrid_createPfS_iiff
.globl _Z15meshgrid_createPfS_iiff
.p2align 8
.type _Z15meshgrid_createPfS_iiff,@function
_Z15meshgrid_createPfS_iiff:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x2c
s_load_b64 s[2:3], s[0:1], 0x10
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s5, s4, 0xffff
s_lshr_b32 s4, s4, 16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[0:1], null, s14, s5, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s4, v[3:4]
v_cmp_gt_i32_e32 vcc_lo, s3, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i32_e64 s2, s2, v1
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s4, s2
s_cbranch_execz .LBB0_2
s_clause 0x1
s_load_b64 s[8:9], s[0:1], 0x18
s_load_b128 s[4:7], s[0:1], 0x0
v_mad_u64_u32 v[2:3], null, v1, s3, v[0:1]
v_cvt_f32_i32_e32 v4, v1
v_cvt_f32_i32_e32 v0, v0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[1:2], 2, v[2:3]
s_waitcnt lgkmcnt(0)
v_subrev_f32_e32 v5, s8, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v3, vcc_lo, s4, v1
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v2, vcc_lo
v_subrev_f32_e32 v6, s9, v0
v_add_co_u32 v0, vcc_lo, s6, v1
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v2, vcc_lo
global_store_b32 v[3:4], v5, off
global_store_b32 v[0:1], v6, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z15meshgrid_createPfS_iiff
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z15meshgrid_createPfS_iiff, .Lfunc_end0-_Z15meshgrid_createPfS_iiff
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z15meshgrid_createPfS_iiff
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z15meshgrid_createPfS_iiff.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void meshgrid_create(float* xx, float* yy, int w, int h, float K02, float K12) {
int i = blockIdx.x*blockDim.x + threadIdx.x;
int j = blockIdx.y*blockDim.y + threadIdx.y;
if (i < h && j < w) {
xx[j*h + i] = j - K02;
yy[j*h + i] = i - K12;
}
} | .text
.file "meshgrid_create.hip"
.globl _Z30__device_stub__meshgrid_createPfS_iiff # -- Begin function _Z30__device_stub__meshgrid_createPfS_iiff
.p2align 4, 0x90
.type _Z30__device_stub__meshgrid_createPfS_iiff,@function
_Z30__device_stub__meshgrid_createPfS_iiff: # @_Z30__device_stub__meshgrid_createPfS_iiff
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movss %xmm0, 4(%rsp)
movss %xmm1, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z15meshgrid_createPfS_iiff, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end0:
.size _Z30__device_stub__meshgrid_createPfS_iiff, .Lfunc_end0-_Z30__device_stub__meshgrid_createPfS_iiff
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15meshgrid_createPfS_iiff, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z15meshgrid_createPfS_iiff,@object # @_Z15meshgrid_createPfS_iiff
.section .rodata,"a",@progbits
.globl _Z15meshgrid_createPfS_iiff
.p2align 3, 0x0
_Z15meshgrid_createPfS_iiff:
.quad _Z30__device_stub__meshgrid_createPfS_iiff
.size _Z15meshgrid_createPfS_iiff, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z15meshgrid_createPfS_iiff"
.size .L__unnamed_1, 28
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z30__device_stub__meshgrid_createPfS_iiff
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z15meshgrid_createPfS_iiff
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z15meshgrid_createPfS_iiff
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e280000002100 */
/*0030*/ S2R R7, SR_CTAID.Y ; /* 0x0000000000077919 */
/* 0x000e680000002600 */
/*0040*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e620000002200 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0060*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x174], PT ; /* 0x00005d0000007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R7, R7, c[0x0][0x4], R2 ; /* 0x0000010007077a24 */
/* 0x002fca00078e0202 */
/*0080*/ ISETP.GE.OR P0, PT, R7, c[0x0][0x170], P0 ; /* 0x00005c0007007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ I2F R2, R7 ; /* 0x0000000700027306 */
/* 0x000e220000201400 */
/*00b0*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*00c0*/ IMAD R4, R7, c[0x0][0x174], R0 ; /* 0x00005d0007047a24 */
/* 0x000fe200078e0200 */
/*00d0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fca0000000a00 */
/*00e0*/ I2F R3, R0 ; /* 0x0000000000037306 */
/* 0x000e620000201400 */
/*00f0*/ FADD R9, R2, -c[0x0][0x178] ; /* 0x80005e0002097621 */
/* 0x001fe40000000000 */
/*0100*/ FADD R11, R3, -c[0x0][0x17c] ; /* 0x80005f00030b7621 */
/* 0x002fe40000000000 */
/*0110*/ IMAD.WIDE R2, R4, R5, c[0x0][0x160] ; /* 0x0000580004027625 */
/* 0x000fc800078e0205 */
/*0120*/ IMAD.WIDE R4, R4, R5, c[0x0][0x168] ; /* 0x00005a0004047625 */
/* 0x000fe200078e0205 */
/*0130*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x000fe8000c101904 */
/*0140*/ STG.E [R4.64], R11 ; /* 0x0000000b04007986 */
/* 0x000fe2000c101904 */
/*0150*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0160*/ BRA 0x160; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z15meshgrid_createPfS_iiff
.globl _Z15meshgrid_createPfS_iiff
.p2align 8
.type _Z15meshgrid_createPfS_iiff,@function
_Z15meshgrid_createPfS_iiff:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x2c
s_load_b64 s[2:3], s[0:1], 0x10
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s5, s4, 0xffff
s_lshr_b32 s4, s4, 16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[0:1], null, s14, s5, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s4, v[3:4]
v_cmp_gt_i32_e32 vcc_lo, s3, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i32_e64 s2, s2, v1
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s4, s2
s_cbranch_execz .LBB0_2
s_clause 0x1
s_load_b64 s[8:9], s[0:1], 0x18
s_load_b128 s[4:7], s[0:1], 0x0
v_mad_u64_u32 v[2:3], null, v1, s3, v[0:1]
v_cvt_f32_i32_e32 v4, v1
v_cvt_f32_i32_e32 v0, v0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[1:2], 2, v[2:3]
s_waitcnt lgkmcnt(0)
v_subrev_f32_e32 v5, s8, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v3, vcc_lo, s4, v1
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v2, vcc_lo
v_subrev_f32_e32 v6, s9, v0
v_add_co_u32 v0, vcc_lo, s6, v1
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v2, vcc_lo
global_store_b32 v[3:4], v5, off
global_store_b32 v[0:1], v6, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z15meshgrid_createPfS_iiff
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z15meshgrid_createPfS_iiff, .Lfunc_end0-_Z15meshgrid_createPfS_iiff
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z15meshgrid_createPfS_iiff
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z15meshgrid_createPfS_iiff.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00078e43_00000000-6_meshgrid_create.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z41__device_stub__Z15meshgrid_createPfS_iiffPfS_iiff
.type _Z41__device_stub__Z15meshgrid_createPfS_iiffPfS_iiff, @function
_Z41__device_stub__Z15meshgrid_createPfS_iiffPfS_iiff:
.LFB2051:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movss %xmm0, 4(%rsp)
movss %xmm1, (%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
movq %rsp, %rax
movq %rax, 136(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 184
pushq 40(%rsp)
.cfi_def_cfa_offset 192
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z15meshgrid_createPfS_iiff(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z41__device_stub__Z15meshgrid_createPfS_iiffPfS_iiff, .-_Z41__device_stub__Z15meshgrid_createPfS_iiffPfS_iiff
.globl _Z15meshgrid_createPfS_iiff
.type _Z15meshgrid_createPfS_iiff, @function
_Z15meshgrid_createPfS_iiff:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z41__device_stub__Z15meshgrid_createPfS_iiffPfS_iiff
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z15meshgrid_createPfS_iiff, .-_Z15meshgrid_createPfS_iiff
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z15meshgrid_createPfS_iiff"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z15meshgrid_createPfS_iiff(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "meshgrid_create.hip"
.globl _Z30__device_stub__meshgrid_createPfS_iiff # -- Begin function _Z30__device_stub__meshgrid_createPfS_iiff
.p2align 4, 0x90
.type _Z30__device_stub__meshgrid_createPfS_iiff,@function
_Z30__device_stub__meshgrid_createPfS_iiff: # @_Z30__device_stub__meshgrid_createPfS_iiff
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movss %xmm0, 4(%rsp)
movss %xmm1, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z15meshgrid_createPfS_iiff, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end0:
.size _Z30__device_stub__meshgrid_createPfS_iiff, .Lfunc_end0-_Z30__device_stub__meshgrid_createPfS_iiff
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15meshgrid_createPfS_iiff, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z15meshgrid_createPfS_iiff,@object # @_Z15meshgrid_createPfS_iiff
.section .rodata,"a",@progbits
.globl _Z15meshgrid_createPfS_iiff
.p2align 3, 0x0
_Z15meshgrid_createPfS_iiff:
.quad _Z30__device_stub__meshgrid_createPfS_iiff
.size _Z15meshgrid_createPfS_iiff, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z15meshgrid_createPfS_iiff"
.size .L__unnamed_1, 28
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z30__device_stub__meshgrid_createPfS_iiff
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z15meshgrid_createPfS_iiff
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | /* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *\
* Copyright (c) 2019 <GTEP> - All Rights Reserved *
* This file is part of HERMES Project. *
* Unauthorized copying of this file, via any medium is strictly prohibited. *
* Proprietary and confidential. *
* *
* Developers: *
* - Bismarck G. Souza Jr <bismarck@puc-rio.br> *
* - Nelson Inoue <inoue@puc-rio.br> *
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
//
// o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o
// o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o
//
// C C C C C C U U U U D D D D D D D D D A A A A A A
// C C C C C C C C U U U U D D D D D D D D D D A A A A A A A A
// C C C C U U U U D D D D A A A A
// C C C C U U U U D D D D A A A A
// C C U U U U D D D D A A A A
// C C U U U U D D D D A A A A
// C C U U U U D D D D A A A A A A A A A A A A
// C C U U U U D D D D A A A A A A A A A A A A
// C C U U U U D D D D A A A A
// C C C C U U U U D D D D A A A A
// C C C C C C C C U U U U U U U U D D D D D D D D D D A A A A
// C C C C C C U U U U U U D D D D D D D D D A A A A
//
// o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o
// o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o
// includes, system
#include <stdlib.h>
#include <stdio.h>
#include <string.h>
#include <iostream>
#include <fstream>
#include <iomanip>
#include <time.h>
#include <cuda_runtime.h>
//----------------------------------------------------
// External Functions for one GPU Implementation
//----------------------------------------------------
extern "C" void ImpositionBoundaryCondition(int Id, int BlockSizeX, int _iNumMeshNodes, int _iNumSuppNodes, int _inumDiaPart, int *supp, double *K, double *B);
extern "C" void ImpositionBoundaryConditionNeumann(int Id, int BlockSizeX, int _iNumMeshNodes, int _iNumSuppNodes, int *supp, double *B);
//==============================================================================
__global__ void ImpositionBoundaryConditionKernel(int _iNumMeshNodes, int _iNumSuppNodes, int _inumDiaPart, int *supp, double *K, double *B)
{
// _iNumSuppNodes = total number of supports
int i;
const int xIndex = blockIdx.x*blockDim.x + threadIdx.x;
const int yIndex = blockIdx.y*blockDim.y + threadIdx.y;
const int thread_id = (gridDim.x*blockDim.x)*yIndex + xIndex;
if(thread_id < _iNumSuppNodes) { // -----------------------
for(i=0; i<_inumDiaPart; i++) {
if(supp[thread_id+1*_iNumSuppNodes] == 1) K[3*(supp[thread_id]-1) + i*3*_iNumMeshNodes] = 0.;
if(supp[thread_id+2*_iNumSuppNodes] == 1) K[3*(supp[thread_id]-1)+1 + i*3*_iNumMeshNodes] = 0.;
if(supp[thread_id+3*_iNumSuppNodes] == 1) K[3*(supp[thread_id]-1)+2 + i*3*_iNumMeshNodes] = 0.;
}
if(supp[thread_id+1*_iNumSuppNodes] == 1) B[3*(supp[thread_id]-1) ] = 0.;
if(supp[thread_id+2*_iNumSuppNodes] == 1) B[3*(supp[thread_id]-1)+1] = 0.;
if(supp[thread_id+3*_iNumSuppNodes] == 1) B[3*(supp[thread_id]-1)+2] = 0.;
}
}
//=====================================================================================================================
void ImpositionBoundaryCondition(int Id, int BlockSizeX, int _iNumMeshNodes, int _iNumSuppNodes, int _inumDiaPart, int *supp, double *K, double *B)
{
double time;
cudaSetDevice(Id);
dim3 threadsPerBlock(BlockSizeX, BlockSizeX);
dim3 blocksPerGrid(int(sqrt(double(_iNumSuppNodes))/BlockSizeX)+1, int(sqrt(double(_iNumSuppNodes))/BlockSizeX)+1);
time = clock();
ImpositionBoundaryConditionKernel<<<blocksPerGrid, threadsPerBlock>>>(_iNumMeshNodes, _iNumSuppNodes, _inumDiaPart, supp, K, B);
cudaDeviceSynchronize();
//printf(" Time Execution : %0.3f s \n", (clock()-time)/CLOCKS_PER_SEC);
}
//==============================================================================
__global__ void ImpositionBoundaryConditionNeumannKernel(int _iNumMeshNodes, int _iNumSuppNodes, int *supp, double *B)
{
// _iNumSuppNodes = total number of supports
int i;
const int xIndex = blockIdx.x*blockDim.x + threadIdx.x;
const int yIndex = blockIdx.y*blockDim.y + threadIdx.y;
const int thread_id = (gridDim.x*blockDim.x)*yIndex + xIndex;
if(thread_id < _iNumSuppNodes) { // -----------------------
if(supp[thread_id+1*_iNumSuppNodes] == 1) B[3*(supp[thread_id]-1) ] = 0.;
if(supp[thread_id+2*_iNumSuppNodes] == 1) B[3*(supp[thread_id]-1)+1] = 0.;
if(supp[thread_id+3*_iNumSuppNodes] == 1) B[3*(supp[thread_id]-1)+2] = 0.;
}
}
//=====================================================================================================================
void ImpositionBoundaryConditionNeumann(int Id, int BlockSizeX, int _iNumMeshNodes, int _iNumSuppNodes, int *supp, double *B)
{
double time;
cudaSetDevice(Id);
dim3 threadsPerBlock(BlockSizeX, BlockSizeX);
dim3 blocksPerGrid(int(sqrt(double(_iNumSuppNodes))/BlockSizeX)+1, int(sqrt(double(_iNumSuppNodes))/BlockSizeX)+1);
time = clock();
ImpositionBoundaryConditionNeumannKernel<<<blocksPerGrid, threadsPerBlock>>>(_iNumMeshNodes, _iNumSuppNodes, supp, B);
cudaDeviceSynchronize();
//printf(" Time Execution : %0.3f s \n", (clock()-time)/CLOCKS_PER_SEC);
}
//============================================================================== | code for sm_80
Function : _Z40ImpositionBoundaryConditionNeumannKerneliiPiPd
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e280000002600 */
/*0020*/ S2R R3, SR_TID.Y ; /* 0x0000000000037919 */
/* 0x000e280000002200 */
/*0030*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x000e680000002500 */
/*0040*/ S2R R7, SR_TID.X ; /* 0x0000000000077919 */
/* 0x000ea20000002100 */
/*0050*/ IMAD R0, R0, c[0x0][0x4], R3 ; /* 0x0000010000007a24 */
/* 0x001fc800078e0203 */
/*0060*/ IMAD R0, R0, c[0x0][0xc], R5 ; /* 0x0000030000007a24 */
/* 0x002fc800078e0205 */
/*0070*/ IMAD R0, R0, c[0x0][0x0], R7 ; /* 0x0000000000007a24 */
/* 0x004fca00078e0207 */
/*0080*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x164], PT ; /* 0x0000590000007a0c */
/* 0x000fda0003f06270 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ HFMA2.MMA R11, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff0b7435 */
/* 0x000fe200000001ff */
/*00b0*/ IADD3 R6, R0, c[0x0][0x164], RZ ; /* 0x0000590000067a10 */
/* 0x000fe20007ffe0ff */
/*00c0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd00000000a00 */
/*00d0*/ IMAD.WIDE R4, R6, R11, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x000fcc00078e020b */
/*00e0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea2000c1e1900 */
/*00f0*/ IMAD.WIDE R2, R0, R11, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x000fe200078e020b */
/*0100*/ ISETP.NE.AND P0, PT, R4, 0x1, PT ; /* 0x000000010400780c */
/* 0x004fda0003f05270 */
/*0110*/ @!P0 LDG.E R0, [R2.64] ; /* 0x0000000402008981 */
/* 0x000ea2000c1e1900 */
/*0120*/ @!P0 MOV R7, 0x3 ; /* 0x0000000300078802 */
/* 0x000fe40000000f00 */
/*0130*/ @!P0 MOV R9, 0x8 ; /* 0x0000000800098802 */
/* 0x000fe40000000f00 */
/*0140*/ IADD3 R10, R6, c[0x0][0x164], RZ ; /* 0x00005900060a7a10 */
/* 0x000fe20007ffe0ff */
/*0150*/ @!P0 IMAD R0, R0, R7, -0x3 ; /* 0xfffffffd00008424 */
/* 0x004fc800078e0207 */
/*0160*/ @!P0 IMAD.WIDE R6, R0, R9, c[0x0][0x170] ; /* 0x00005c0000068625 */
/* 0x000fc800078e0209 */
/*0170*/ IMAD.WIDE R8, R10, R11, c[0x0][0x168] ; /* 0x00005a000a087625 */
/* 0x000fe200078e020b */
/*0180*/ @!P0 STG.E.64 [R6.64], RZ ; /* 0x000000ff06008986 */
/* 0x0001ea000c101b04 */
/*0190*/ LDG.E R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x000ea4000c1e1900 */
/*01a0*/ ISETP.NE.AND P0, PT, R8, 0x1, PT ; /* 0x000000010800780c */
/* 0x004fda0003f05270 */
/*01b0*/ @!P0 LDG.E R0, [R2.64] ; /* 0x0000000402008981 */
/* 0x000ea2000c1e1900 */
/*01c0*/ @!P0 MOV R5, 0x3 ; /* 0x0000000300058802 */
/* 0x000fe40000000f00 */
/*01d0*/ IADD3 R10, R10, c[0x0][0x164], RZ ; /* 0x000059000a0a7a10 */
/* 0x000fe40007ffe0ff */
/*01e0*/ @!P0 MOV R13, 0x8 ; /* 0x00000008000d8802 */
/* 0x000fc60000000f00 */
/*01f0*/ IMAD.WIDE R10, R10, R11, c[0x0][0x168] ; /* 0x00005a000a0a7625 */
/* 0x000fc800078e020b */
/*0200*/ @!P0 IMAD R0, R0, R5, -0x2 ; /* 0xfffffffe00008424 */
/* 0x004fc800078e0205 */
/*0210*/ @!P0 IMAD.WIDE R4, R0, R13, c[0x0][0x170] ; /* 0x00005c0000048625 */
/* 0x000fca00078e020d */
/*0220*/ @!P0 STG.E.64 [R4.64], RZ ; /* 0x000000ff04008986 */
/* 0x0001e8000c101b04 */
/*0230*/ LDG.E R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x000ea4000c1e1900 */
/*0240*/ ISETP.NE.AND P0, PT, R10, 0x1, PT ; /* 0x000000010a00780c */
/* 0x004fda0003f05270 */
/*0250*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0260*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x001ea2000c1e1900 */
/*0270*/ MOV R5, 0x3 ; /* 0x0000000300057802 */
/* 0x000fe40000000f00 */
/*0280*/ MOV R7, 0x8 ; /* 0x0000000800077802 */
/* 0x000fc60000000f00 */
/*0290*/ IMAD R4, R2, R5, -0x1 ; /* 0xffffffff02047424 */
/* 0x004fc800078e0205 */
/*02a0*/ IMAD.WIDE R4, R4, R7, c[0x0][0x170] ; /* 0x00005c0004047625 */
/* 0x000fca00078e0207 */
/*02b0*/ STG.E.64 [R4.64], RZ ; /* 0x000000ff04007986 */
/* 0x000fe2000c101b04 */
/*02c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*02d0*/ BRA 0x2d0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0300*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0310*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0320*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z33ImpositionBoundaryConditionKerneliiiPiPdS0_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e280000002600 */
/*0020*/ S2R R3, SR_TID.Y ; /* 0x0000000000037919 */
/* 0x000e280000002200 */
/*0030*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x000e680000002500 */
/*0040*/ S2R R7, SR_TID.X ; /* 0x0000000000077919 */
/* 0x000ea20000002100 */
/*0050*/ IMAD R0, R0, c[0x0][0x4], R3 ; /* 0x0000010000007a24 */
/* 0x001fc800078e0203 */
/*0060*/ IMAD R0, R0, c[0x0][0xc], R5 ; /* 0x0000030000007a24 */
/* 0x002fc800078e0205 */
/*0070*/ IMAD R0, R0, c[0x0][0x0], R7 ; /* 0x0000000000007a24 */
/* 0x004fca00078e0207 */
/*0080*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x164], PT ; /* 0x0000590000007a0c */
/* 0x000fda0003f06270 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ IADD3 R2, R0, c[0x0][0x164], RZ ; /* 0x0000590000027a10 */
/* 0x000fe20007ffe0ff */
/*00b0*/ IMAD.MOV.U32 R19, RZ, RZ, 0x4 ; /* 0x00000004ff137424 */
/* 0x000fe200078e00ff */
/*00c0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*00d0*/ IMAD.WIDE R8, R2, R19, c[0x0][0x170] ; /* 0x00005c0002087625 */
/* 0x000fca00078e0213 */
/*00e0*/ LDG.E R4, [R8.64] ; /* 0x0000000408047981 */
/* 0x000ea2000c1e1900 */
/*00f0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x1 ; /* 0x00000001ff037424 */
/* 0x000fe200078e00ff */
/*0100*/ MOV R5, c[0x0][0x164] ; /* 0x0000590000057a02 */
/* 0x000fe20000000f00 */
/*0110*/ IMAD.WIDE R10, R0, R19, c[0x0][0x170] ; /* 0x00005c00000a7625 */
/* 0x000fc600078e0213 */
/*0120*/ ISETP.LE.AND P1, PT, R3, c[0x0][0x168], PT ; /* 0x00005a0003007a0c */
/* 0x000fe40003f23270 */
/*0130*/ LEA R12, R5, R0, 0x1 ; /* 0x00000000050c7211 */
/* 0x000fc800078e08ff */
/*0140*/ IADD3 R14, R12.reuse, c[0x0][0x164], RZ ; /* 0x000059000c0e7a10 */
/* 0x040fe20007ffe0ff */
/*0150*/ IMAD.WIDE R12, R12, R19, c[0x0][0x170] ; /* 0x00005c000c0c7625 */
/* 0x000fc800078e0213 */
/*0160*/ IMAD.WIDE R14, R14, R19, c[0x0][0x170] ; /* 0x00005c000e0e7625 */
/* 0x000fe200078e0213 */
/*0170*/ ISETP.EQ.AND P0, PT, R4, 0x1, PT ; /* 0x000000010400780c */
/* 0x004fe20003f02270 */
/*0180*/ @!P1 BRA 0xba0 ; /* 0x00000a1000009947 */
/* 0x000ff60003800000 */
/*0190*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff007624 */
/* 0x000fe200078e00ff */
/*01a0*/ MOV R3, c[0x0][0x164] ; /* 0x0000590000037a02 */
/* 0x000fc80000000f00 */
/*01b0*/ IADD3 R4, R0.reuse, -0x1, RZ ; /* 0xffffffff00047810 */
/* 0x040fe20007ffe0ff */
/*01c0*/ IMAD R18, R3, 0x2, R2 ; /* 0x0000000203127824 */
/* 0x000fe200078e0202 */
/*01d0*/ LOP3.LUT R0, R0, 0x3, RZ, 0xc0, !PT ; /* 0x0000000300007812 */
/* 0x000fe400078ec0ff */
/*01e0*/ ISETP.GE.U32.AND P2, PT, R4, 0x3, PT ; /* 0x000000030400780c */
/* 0x000fe20003f46070 */
/*01f0*/ HFMA2.MMA R4, -RZ, RZ, 0, 0 ; /* 0x00000000ff047435 */
/* 0x000fe200000001ff */
/*0200*/ ISETP.NE.AND P1, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe20003f25270 */
/*0210*/ IMAD.WIDE R18, R18, R19, c[0x0][0x170] ; /* 0x00005c0012127625 */
/* 0x000fd400078e0213 */
/*0220*/ @!P2 BRA 0x960 ; /* 0x000007300000a947 */
/* 0x000fea0003800000 */
/*0230*/ IMAD.MOV R17, RZ, RZ, -c[0x0][0x164] ; /* 0x80005900ff117624 */
/* 0x000fe200078e02ff */
/*0240*/ MOV R6, c[0x0][0x160] ; /* 0x0000580000067a02 */
/* 0x000fe20000000f00 */
/*0250*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x000fe200078e00ff */
/*0260*/ IADD3 R7, -R0, c[0x0][0x168], RZ ; /* 0x00005a0000077a10 */
/* 0x000fe20007ffe1ff */
/*0270*/ IMAD.WIDE R18, R17, 0x4, R18 ; /* 0x0000000411127825 */
/* 0x000fe200078e0212 */
/*0280*/ MOV R4, RZ ; /* 0x000000ff00047202 */
/* 0x000fc60000000f00 */
/*0290*/ IMAD R5, R6, 0x9, RZ ; /* 0x0000000906057824 */
/* 0x000fe400078e02ff */
/*02a0*/ IMAD.WIDE R20, R17, 0x4, R18 ; /* 0x0000000411147825 */
/* 0x000fc800078e0212 */
/*02b0*/ IMAD R3, R6.reuse, 0x6, RZ ; /* 0x0000000606037824 */
/* 0x040fe400078e02ff */
/*02c0*/ IMAD R6, R6, 0x3, RZ ; /* 0x0000000306067824 */
/* 0x000fe400078e02ff */
/*02d0*/ IMAD.WIDE R16, R17, 0x4, R20 ; /* 0x0000000411107825 */
/* 0x000fc800078e0214 */
/*02e0*/ @P0 LDG.E R23, [R10.64] ; /* 0x000000040a170981 */
/* 0x000ea2000c1e1900 */
/*02f0*/ @P0 IMAD.MOV.U32 R22, RZ, RZ, 0x8 ; /* 0x00000008ff160424 */
/* 0x000fe400078e00ff */
/*0300*/ @P0 IMAD R23, R23, 0x3, R2 ; /* 0x0000000317170824 */
/* 0x004fca00078e0202 */
/*0310*/ @P0 IADD3 R23, R23, -0x3, RZ ; /* 0xfffffffd17170810 */
/* 0x000fca0007ffe0ff */
/*0320*/ @P0 IMAD.WIDE R22, R23, R22, c[0x0][0x178] ; /* 0x00005e0017160625 */
/* 0x000fca00078e0216 */
/*0330*/ @P0 STG.E.64 [R22.64], RZ ; /* 0x000000ff16000986 */
/* 0x0001e8000c101b04 */
/*0340*/ LDG.E R24, [R12.64] ; /* 0x000000040c187981 */
/* 0x000ea4000c1e1900 */
/*0350*/ ISETP.NE.AND P0, PT, R24, 0x1, PT ; /* 0x000000011800780c */
/* 0x004fda0003f05270 */
/*0360*/ @!P0 LDG.E R25, [R10.64] ; /* 0x000000040a198981 */
/* 0x000ea2000c1e1900 */
/*0370*/ @!P0 MOV R24, 0x8 ; /* 0x0000000800188802 */
/* 0x000fe20000000f00 */
/*0380*/ @!P0 IMAD R25, R25, 0x3, R2 ; /* 0x0000000319198824 */
/* 0x004fca00078e0202 */
/*0390*/ @!P0 IADD3 R25, R25, -0x2, RZ ; /* 0xfffffffe19198810 */
/* 0x000fca0007ffe0ff */
/*03a0*/ @!P0 IMAD.WIDE R24, R25, R24, c[0x0][0x178] ; /* 0x00005e0019188625 */
/* 0x000fca00078e0218 */
/*03b0*/ @!P0 STG.E.64 [R24.64], RZ ; /* 0x000000ff18008986 */
/* 0x0003e8000c101b04 */
/*03c0*/ LDG.E R26, [R14.64] ; /* 0x000000040e1a7981 */
/* 0x000ea4000c1e1900 */
/*03d0*/ ISETP.NE.AND P0, PT, R26, 0x1, PT ; /* 0x000000011a00780c */
/* 0x004fda0003f05270 */
/*03e0*/ @!P0 LDG.E R23, [R10.64] ; /* 0x000000040a178981 */
/* 0x001ea2000c1e1900 */
/*03f0*/ @!P0 MOV R22, 0x8 ; /* 0x0000000800168802 */
/* 0x000fe20000000f00 */
/*0400*/ @!P0 IMAD R23, R23, 0x3, R2 ; /* 0x0000000317178824 */
/* 0x004fca00078e0202 */
/*0410*/ @!P0 IADD3 R23, R23, -0x1, RZ ; /* 0xffffffff17178810 */
/* 0x000fca0007ffe0ff */
/*0420*/ @!P0 IMAD.WIDE R22, R23, R22, c[0x0][0x178] ; /* 0x00005e0017168625 */
/* 0x000fca00078e0216 */
/*0430*/ @!P0 STG.E.64 [R22.64], RZ ; /* 0x000000ff16008986 */
/* 0x0001e8000c101b04 */
/*0440*/ LDG.E R26, [R8.64] ; /* 0x00000004081a7981 */
/* 0x000ea4000c1e1900 */
/*0450*/ ISETP.NE.AND P0, PT, R26, 0x1, PT ; /* 0x000000011a00780c */
/* 0x004fda0003f05270 */
/*0460*/ @!P0 LDG.E R25, [R10.64] ; /* 0x000000040a198981 */
/* 0x002ea2000c1e1900 */
/*0470*/ @!P0 IMAD.MOV.U32 R24, RZ, RZ, 0x8 ; /* 0x00000008ff188424 */
/* 0x000fe400078e00ff */
/*0480*/ @!P0 IMAD R25, R25, 0x3, R6 ; /* 0x0000000319198824 */
/* 0x004fca00078e0206 */
/*0490*/ @!P0 IADD3 R25, R2, -0x3, R25 ; /* 0xfffffffd02198810 */
/* 0x000fca0007ffe019 */
/*04a0*/ @!P0 IMAD.WIDE R24, R25, R24, c[0x0][0x178] ; /* 0x00005e0019188625 */
/* 0x000fca00078e0218 */
/*04b0*/ @!P0 STG.E.64 [R24.64], RZ ; /* 0x000000ff18008986 */
/* 0x0003e8000c101b04 */
/*04c0*/ LDG.E R26, [R18.64] ; /* 0x00000004121a7981 */
/* 0x000ea4000c1e1900 */
/*04d0*/ ISETP.NE.AND P0, PT, R26, 0x1, PT ; /* 0x000000011a00780c */
/* 0x004fda0003f05270 */
/*04e0*/ @!P0 LDG.E R23, [R10.64] ; /* 0x000000040a178981 */
/* 0x001ea2000c1e1900 */
/*04f0*/ @!P0 MOV R22, 0x8 ; /* 0x0000000800168802 */
/* 0x000fe20000000f00 */
/*0500*/ @!P0 IMAD R23, R23, 0x3, R6 ; /* 0x0000000317178824 */
/* 0x004fca00078e0206 */
/*0510*/ @!P0 IADD3 R23, R2, -0x2, R23 ; /* 0xfffffffe02178810 */
/* 0x000fca0007ffe017 */
/*0520*/ @!P0 IMAD.WIDE R22, R23, R22, c[0x0][0x178] ; /* 0x00005e0017168625 */
/* 0x000fca00078e0216 */
/*0530*/ @!P0 STG.E.64 [R22.64], RZ ; /* 0x000000ff16008986 */
/* 0x0001e8000c101b04 */
/*0540*/ LDG.E R26, [R14.64] ; /* 0x000000040e1a7981 */
/* 0x000ea4000c1e1900 */
/*0550*/ ISETP.NE.AND P0, PT, R26, 0x1, PT ; /* 0x000000011a00780c */
/* 0x004fda0003f05270 */
/*0560*/ @!P0 LDG.E R25, [R10.64] ; /* 0x000000040a198981 */
/* 0x002ea2000c1e1900 */
/*0570*/ @!P0 MOV R24, 0x8 ; /* 0x0000000800188802 */
/* 0x000fe20000000f00 */
/*0580*/ @!P0 IMAD R25, R25, 0x3, R6 ; /* 0x0000000319198824 */
/* 0x004fca00078e0206 */
/*0590*/ @!P0 IADD3 R25, R2, -0x1, R25 ; /* 0xffffffff02198810 */
/* 0x000fca0007ffe019 */
/*05a0*/ @!P0 IMAD.WIDE R24, R25, R24, c[0x0][0x178] ; /* 0x00005e0019188625 */
/* 0x000fca00078e0218 */
/*05b0*/ @!P0 STG.E.64 [R24.64], RZ ; /* 0x000000ff18008986 */
/* 0x0003e8000c101b04 */
/*05c0*/ LDG.E R26, [R20.64] ; /* 0x00000004141a7981 */
/* 0x000ea4000c1e1900 */
/*05d0*/ ISETP.NE.AND P0, PT, R26, 0x1, PT ; /* 0x000000011a00780c */
/* 0x004fda0003f05270 */
/*05e0*/ @!P0 LDG.E R22, [R10.64] ; /* 0x000000040a168981 */
/* 0x001ea2000c1e1900 */
/*05f0*/ @!P0 IMAD.MOV.U32 R23, RZ, RZ, 0x8 ; /* 0x00000008ff178424 */
/* 0x000fe400078e00ff */
/*0600*/ @!P0 IMAD R22, R22, 0x3, R3 ; /* 0x0000000316168824 */
/* 0x004fca00078e0203 */
/*0610*/ @!P0 IADD3 R22, R22, -0x3, RZ ; /* 0xfffffffd16168810 */
/* 0x000fca0007ffe0ff */
/*0620*/ @!P0 IMAD.WIDE R22, R22, R23, c[0x0][0x178] ; /* 0x00005e0016168625 */
/* 0x000fca00078e0217 */
/*0630*/ @!P0 STG.E.64 [R22.64], RZ ; /* 0x000000ff16008986 */
/* 0x0001e8000c101b04 */
/*0640*/ LDG.E R26, [R12.64] ; /* 0x000000040c1a7981 */
/* 0x000ea4000c1e1900 */
/*0650*/ ISETP.NE.AND P0, PT, R26, 0x1, PT ; /* 0x000000011a00780c */
/* 0x004fda0003f05270 */
/*0660*/ @!P0 LDG.E R24, [R16.64] ; /* 0x0000000410188981 */
/* 0x002ea2000c1e1900 */
/*0670*/ @!P0 MOV R25, 0x8 ; /* 0x0000000800198802 */
/* 0x000fe20000000f00 */
/*0680*/ @!P0 IMAD R24, R24, 0x3, R3 ; /* 0x0000000318188824 */
/* 0x004fca00078e0203 */
/*0690*/ @!P0 IADD3 R24, R24, -0x2, RZ ; /* 0xfffffffe18188810 */
/* 0x000fca0007ffe0ff */
/*06a0*/ @!P0 IMAD.WIDE R24, R24, R25, c[0x0][0x178] ; /* 0x00005e0018188625 */
/* 0x000fca00078e0219 */
/*06b0*/ @!P0 STG.E.64 [R24.64], RZ ; /* 0x000000ff18008986 */
/* 0x0003e8000c101b04 */
/*06c0*/ LDG.E R26, [R14.64] ; /* 0x000000040e1a7981 */
/* 0x000ea4000c1e1900 */
/*06d0*/ ISETP.NE.AND P0, PT, R26, 0x1, PT ; /* 0x000000011a00780c */
/* 0x004fda0003f05270 */
/*06e0*/ @!P0 LDG.E R22, [R10.64] ; /* 0x000000040a168981 */
/* 0x001ea2000c1e1900 */
/*06f0*/ @!P0 MOV R23, 0x8 ; /* 0x0000000800178802 */
/* 0x000fe20000000f00 */
/*0700*/ @!P0 IMAD R22, R22, 0x3, R3 ; /* 0x0000000316168824 */
/* 0x004fca00078e0203 */
/*0710*/ @!P0 IADD3 R22, R22, -0x1, RZ ; /* 0xffffffff16168810 */
/* 0x000fca0007ffe0ff */
/*0720*/ @!P0 IMAD.WIDE R22, R22, R23, c[0x0][0x178] ; /* 0x00005e0016168625 */
/* 0x000fca00078e0217 */
/*0730*/ @!P0 STG.E.64 [R22.64], RZ ; /* 0x000000ff16008986 */
/* 0x0001e8000c101b04 */
/*0740*/ LDG.E R26, [R8.64] ; /* 0x00000004081a7981 */
/* 0x000ea4000c1e1900 */
/*0750*/ ISETP.NE.AND P0, PT, R26, 0x1, PT ; /* 0x000000011a00780c */
/* 0x004fda0003f05270 */
/*0760*/ @!P0 LDG.E R24, [R10.64] ; /* 0x000000040a188981 */
/* 0x002ea2000c1e1900 */
/*0770*/ @!P0 IMAD.MOV.U32 R25, RZ, RZ, 0x8 ; /* 0x00000008ff198424 */
/* 0x000fe400078e00ff */
/*0780*/ @!P0 IMAD R24, R24, 0x3, R5 ; /* 0x0000000318188824 */
/* 0x004fca00078e0205 */
/*0790*/ @!P0 IADD3 R24, R24, -0x3, RZ ; /* 0xfffffffd18188810 */
/* 0x000fca0007ffe0ff */
/*07a0*/ @!P0 IMAD.WIDE R24, R24, R25, c[0x0][0x178] ; /* 0x00005e0018188625 */
/* 0x000fca00078e0219 */
/*07b0*/ @!P0 STG.E.64 [R24.64], RZ ; /* 0x000000ff18008986 */
/* 0x0003e8000c101b04 */
/*07c0*/ LDG.E R26, [R12.64] ; /* 0x000000040c1a7981 */
/* 0x000ea4000c1e1900 */
/*07d0*/ ISETP.NE.AND P0, PT, R26, 0x1, PT ; /* 0x000000011a00780c */
/* 0x004fda0003f05270 */
/*07e0*/ @!P0 LDG.E R22, [R10.64] ; /* 0x000000040a168981 */
/* 0x001ea2000c1e1900 */
/*07f0*/ @!P0 MOV R23, 0x8 ; /* 0x0000000800178802 */
/* 0x000fe20000000f00 */
/*0800*/ @!P0 IMAD R22, R22, 0x3, R5 ; /* 0x0000000316168824 */
/* 0x004fca00078e0205 */
/*0810*/ @!P0 IADD3 R22, R22, -0x2, RZ ; /* 0xfffffffe16168810 */
/* 0x000fca0007ffe0ff */
/*0820*/ @!P0 IMAD.WIDE R22, R22, R23, c[0x0][0x178] ; /* 0x00005e0016168625 */
/* 0x000fca00078e0217 */
/*0830*/ @!P0 STG.E.64 [R22.64], RZ ; /* 0x000000ff16008986 */
/* 0x0001e8000c101b04 */
/*0840*/ LDG.E R26, [R14.64] ; /* 0x000000040e1a7981 */
/* 0x000ea4000c1e1900 */
/*0850*/ ISETP.NE.AND P0, PT, R26, 0x1, PT ; /* 0x000000011a00780c */
/* 0x004fda0003f05270 */
/*0860*/ @!P0 LDG.E R24, [R10.64] ; /* 0x000000040a188981 */
/* 0x002ea2000c1e1900 */
/*0870*/ @!P0 MOV R25, 0x8 ; /* 0x0000000800198802 */
/* 0x000fe40000000f00 */
/*0880*/ IADD3 R7, R7, -0x4, RZ ; /* 0xfffffffc07077810 */
/* 0x000fe20007ffe0ff */
/*0890*/ @!P0 IMAD R24, R24, 0x3, R5 ; /* 0x0000000318188824 */
/* 0x004fca00078e0205 */
/*08a0*/ @!P0 IADD3 R24, R24, -0x1, RZ ; /* 0xffffffff18188810 */
/* 0x000fca0007ffe0ff */
/*08b0*/ @!P0 IMAD.WIDE R24, R24, R25, c[0x0][0x178] ; /* 0x00005e0018188625 */
/* 0x000fca00078e0219 */
/*08c0*/ @!P0 STG.E.64 [R24.64], RZ ; /* 0x000000ff18008986 */
/* 0x0003e8000c101b04 */
/*08d0*/ LDG.E R26, [R8.64] ; /* 0x00000004081a7981 */
/* 0x000ea2000c1e1900 */
/*08e0*/ ISETP.NE.AND P2, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fe20003f45270 */
/*08f0*/ IMAD.MOV.U32 R22, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff167624 */
/* 0x001fe200078e00ff */
/*0900*/ IADD3 R4, R4, 0x4, RZ ; /* 0x0000000404047810 */
/* 0x000fc60007ffe0ff */
/*0910*/ IMAD R2, R22.reuse, 0xc, R2 ; /* 0x0000000c16027824 */
/* 0x040fe400078e0202 */
/*0920*/ IMAD R3, R22.reuse, 0xc, R3 ; /* 0x0000000c16037824 */
/* 0x040fe400078e0203 */
/*0930*/ IMAD R5, R22, 0xc, R5 ; /* 0x0000000c16057824 */
/* 0x000fe200078e0205 */
/*0940*/ ISETP.EQ.AND P0, PT, R26, 0x1, PT ; /* 0x000000011a00780c */
/* 0x004fc60003f02270 */
/*0950*/ @P2 BRA 0x2e0 ; /* 0xfffff98000002947 */
/* 0x002ff4000383ffff */
/*0960*/ @!P1 BRA 0xba0 ; /* 0x0000023000009947 */
/* 0x000fea0003800000 */
/*0970*/ IMAD R3, R4, c[0x0][0x160], RZ ; /* 0x0000580004037a24 */
/* 0x000fe200078e02ff */
/*0980*/ HFMA2.MMA R2, -RZ, RZ, 0, 0 ; /* 0x00000000ff027435 */
/* 0x000fc600000001ff */
/*0990*/ IMAD R3, R3, 0x3, RZ ; /* 0x0000000303037824 */
/* 0x000fe400078e02ff */
/*09a0*/ BSSY B0, 0xa30 ; /* 0x0000008000007945 */
/* 0x000fe20003800000 */
/*09b0*/ @!P0 BRA 0xa20 ; /* 0x0000006000008947 */
/* 0x000fea0003800000 */
/*09c0*/ LDG.E R4, [R10.64] ; /* 0x000000040a047981 */
/* 0x000ea4000c1e1900 */
/*09d0*/ IMAD R5, R4, 0x3, R3 ; /* 0x0000000304057824 */
/* 0x004fe200078e0203 */
/*09e0*/ MOV R4, 0x8 ; /* 0x0000000800047802 */
/* 0x000fc80000000f00 */
/*09f0*/ IADD3 R5, R2, -0x3, R5 ; /* 0xfffffffd02057810 */
/* 0x000fca0007ffe005 */
/*0a00*/ IMAD.WIDE R4, R5, R4, c[0x0][0x178] ; /* 0x00005e0005047625 */
/* 0x000fca00078e0204 */
/*0a10*/ STG.E.64 [R4.64], RZ ; /* 0x000000ff04007986 */
/* 0x0001e4000c101b04 */
/*0a20*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0a30*/ LDG.E R4, [R12.64] ; /* 0x000000040c047981 */
/* 0x001ea4000c1e1900 */
/*0a40*/ ISETP.NE.AND P0, PT, R4, 0x1, PT ; /* 0x000000010400780c */
/* 0x004fda0003f05270 */
/*0a50*/ @!P0 LDG.E R4, [R10.64] ; /* 0x000000040a048981 */
/* 0x000ea4000c1e1900 */
/*0a60*/ @!P0 IMAD R5, R4, 0x3, R3 ; /* 0x0000000304058824 */
/* 0x004fe400078e0203 */
/*0a70*/ @!P0 IMAD.MOV.U32 R4, RZ, RZ, 0x8 ; /* 0x00000008ff048424 */
/* 0x000fc600078e00ff */
/*0a80*/ @!P0 IADD3 R5, R2, -0x2, R5 ; /* 0xfffffffe02058810 */
/* 0x000fca0007ffe005 */
/*0a90*/ @!P0 IMAD.WIDE R4, R5, R4, c[0x0][0x178] ; /* 0x00005e0005048625 */
/* 0x000fca00078e0204 */
/*0aa0*/ @!P0 STG.E.64 [R4.64], RZ ; /* 0x000000ff04008986 */
/* 0x0001e8000c101b04 */
/*0ab0*/ LDG.E R6, [R14.64] ; /* 0x000000040e067981 */
/* 0x000ea4000c1e1900 */
/*0ac0*/ ISETP.NE.AND P0, PT, R6, 0x1, PT ; /* 0x000000010600780c */
/* 0x004fda0003f05270 */
/*0ad0*/ @!P0 LDG.E R6, [R10.64] ; /* 0x000000040a068981 */
/* 0x000ea2000c1e1900 */
/*0ae0*/ IADD3 R0, R0, -0x1, RZ ; /* 0xffffffff00007810 */
/* 0x000fe20007ffe0ff */
/*0af0*/ @!P0 IMAD R7, R6, 0x3, R3 ; /* 0x0000000306078824 */
/* 0x004fe200078e0203 */
/*0b00*/ @!P0 MOV R6, 0x8 ; /* 0x0000000800068802 */
/* 0x000fc80000000f00 */
/*0b10*/ @!P0 IADD3 R7, R2, -0x1, R7 ; /* 0xffffffff02078810 */
/* 0x000fca0007ffe007 */
/*0b20*/ @!P0 IMAD.WIDE R6, R7, R6, c[0x0][0x178] ; /* 0x00005e0007068625 */
/* 0x000fca00078e0206 */
/*0b30*/ @!P0 STG.E.64 [R6.64], RZ ; /* 0x000000ff06008986 */
/* 0x0003e8000c101b04 */
/*0b40*/ LDG.E R16, [R8.64] ; /* 0x0000000408107981 */
/* 0x000ea2000c1e1900 */
/*0b50*/ ISETP.NE.AND P1, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe40003f25270 */
/*0b60*/ MOV R5, c[0x0][0x160] ; /* 0x0000580000057a02 */
/* 0x001fca0000000f00 */
/*0b70*/ IMAD R2, R5, 0x3, R2 ; /* 0x0000000305027824 */
/* 0x000fe200078e0202 */
/*0b80*/ ISETP.EQ.AND P0, PT, R16, 0x1, PT ; /* 0x000000011000780c */
/* 0x004fca0003f02270 */
/*0b90*/ @P1 BRA 0x9a0 ; /* 0xfffffe0000001947 */
/* 0x002fee000383ffff */
/*0ba0*/ BSSY B0, 0xc30 ; /* 0x0000008000007945 */
/* 0x000fe20003800000 */
/*0bb0*/ @!P0 BRA 0xc20 ; /* 0x0000006000008947 */
/* 0x000fea0003800000 */
/*0bc0*/ LDG.E R0, [R10.64] ; /* 0x000000040a007981 */
/* 0x000ea2000c1e1900 */
/*0bd0*/ HFMA2.MMA R5, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff057435 */
/* 0x000fe200000001ff */
/*0be0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x3 ; /* 0x00000003ff037424 */
/* 0x000fc800078e00ff */
/*0bf0*/ IMAD R0, R0, R3, -0x3 ; /* 0xfffffffd00007424 */
/* 0x004fca00078e0203 */
/*0c00*/ IMAD.WIDE R2, R0, R5, c[0x0][0x180] ; /* 0x0000600000027625 */
/* 0x000fca00078e0205 */
/*0c10*/ STG.E.64 [R2.64], RZ ; /* 0x000000ff02007986 */
/* 0x0001e4000c101b04 */
/*0c20*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0c30*/ LDG.E R12, [R12.64] ; /* 0x000000040c0c7981 */
/* 0x000ea4000c1e1900 */
/*0c40*/ ISETP.NE.AND P0, PT, R12, 0x1, PT ; /* 0x000000010c00780c */
/* 0x004fda0003f05270 */
/*0c50*/ @!P0 LDG.E R0, [R10.64] ; /* 0x000000040a008981 */
/* 0x000ea2000c1e1900 */
/*0c60*/ @!P0 MOV R3, 0x3 ; /* 0x0000000300038802 */
/* 0x001fe20000000f00 */
/*0c70*/ @!P0 IMAD.MOV.U32 R5, RZ, RZ, 0x8 ; /* 0x00000008ff058424 */
/* 0x000fc800078e00ff */
/*0c80*/ @!P0 IMAD R0, R0, R3, -0x2 ; /* 0xfffffffe00008424 */
/* 0x004fc800078e0203 */
/*0c90*/ @!P0 IMAD.WIDE R2, R0, R5, c[0x0][0x180] ; /* 0x0000600000028625 */
/* 0x000fca00078e0205 */
/*0ca0*/ @!P0 STG.E.64 [R2.64], RZ ; /* 0x000000ff02008986 */
/* 0x0001e8000c101b04 */
/*0cb0*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000ea4000c1e1900 */
/*0cc0*/ ISETP.NE.AND P0, PT, R14, 0x1, PT ; /* 0x000000010e00780c */
/* 0x004fda0003f05270 */
/*0cd0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0ce0*/ LDG.E R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x001ea2000c1e1900 */
/*0cf0*/ HFMA2.MMA R3, -RZ, RZ, 0, 1.78813934326171875e-07 ; /* 0x00000003ff037435 */
/* 0x000fe200000001ff */
/*0d00*/ MOV R5, 0x8 ; /* 0x0000000800057802 */
/* 0x000fd20000000f00 */
/*0d10*/ IMAD R2, R10, R3, -0x1 ; /* 0xffffffff0a027424 */
/* 0x004fc800078e0203 */
/*0d20*/ IMAD.WIDE R2, R2, R5, c[0x0][0x180] ; /* 0x0000600002027625 */
/* 0x000fca00078e0205 */
/*0d30*/ STG.E.64 [R2.64], RZ ; /* 0x000000ff02007986 */
/* 0x000fe2000c101b04 */
/*0d40*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0d50*/ BRA 0xd50; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0d60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0da0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0db0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0dc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0dd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0de0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0df0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *\
* Copyright (c) 2019 <GTEP> - All Rights Reserved *
* This file is part of HERMES Project. *
* Unauthorized copying of this file, via any medium is strictly prohibited. *
* Proprietary and confidential. *
* *
* Developers: *
* - Bismarck G. Souza Jr <bismarck@puc-rio.br> *
* - Nelson Inoue <inoue@puc-rio.br> *
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
//
// o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o
// o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o
//
// C C C C C C U U U U D D D D D D D D D A A A A A A
// C C C C C C C C U U U U D D D D D D D D D D A A A A A A A A
// C C C C U U U U D D D D A A A A
// C C C C U U U U D D D D A A A A
// C C U U U U D D D D A A A A
// C C U U U U D D D D A A A A
// C C U U U U D D D D A A A A A A A A A A A A
// C C U U U U D D D D A A A A A A A A A A A A
// C C U U U U D D D D A A A A
// C C C C U U U U D D D D A A A A
// C C C C C C C C U U U U U U U U D D D D D D D D D D A A A A
// C C C C C C U U U U U U D D D D D D D D D A A A A
//
// o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o
// o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o
// includes, system
#include <stdlib.h>
#include <stdio.h>
#include <string.h>
#include <iostream>
#include <fstream>
#include <iomanip>
#include <time.h>
#include <cuda_runtime.h>
//----------------------------------------------------
// External Functions for one GPU Implementation
//----------------------------------------------------
extern "C" void ImpositionBoundaryCondition(int Id, int BlockSizeX, int _iNumMeshNodes, int _iNumSuppNodes, int _inumDiaPart, int *supp, double *K, double *B);
extern "C" void ImpositionBoundaryConditionNeumann(int Id, int BlockSizeX, int _iNumMeshNodes, int _iNumSuppNodes, int *supp, double *B);
//==============================================================================
__global__ void ImpositionBoundaryConditionKernel(int _iNumMeshNodes, int _iNumSuppNodes, int _inumDiaPart, int *supp, double *K, double *B)
{
// _iNumSuppNodes = total number of supports
int i;
const int xIndex = blockIdx.x*blockDim.x + threadIdx.x;
const int yIndex = blockIdx.y*blockDim.y + threadIdx.y;
const int thread_id = (gridDim.x*blockDim.x)*yIndex + xIndex;
if(thread_id < _iNumSuppNodes) { // -----------------------
for(i=0; i<_inumDiaPart; i++) {
if(supp[thread_id+1*_iNumSuppNodes] == 1) K[3*(supp[thread_id]-1) + i*3*_iNumMeshNodes] = 0.;
if(supp[thread_id+2*_iNumSuppNodes] == 1) K[3*(supp[thread_id]-1)+1 + i*3*_iNumMeshNodes] = 0.;
if(supp[thread_id+3*_iNumSuppNodes] == 1) K[3*(supp[thread_id]-1)+2 + i*3*_iNumMeshNodes] = 0.;
}
if(supp[thread_id+1*_iNumSuppNodes] == 1) B[3*(supp[thread_id]-1) ] = 0.;
if(supp[thread_id+2*_iNumSuppNodes] == 1) B[3*(supp[thread_id]-1)+1] = 0.;
if(supp[thread_id+3*_iNumSuppNodes] == 1) B[3*(supp[thread_id]-1)+2] = 0.;
}
}
//=====================================================================================================================
void ImpositionBoundaryCondition(int Id, int BlockSizeX, int _iNumMeshNodes, int _iNumSuppNodes, int _inumDiaPart, int *supp, double *K, double *B)
{
double time;
cudaSetDevice(Id);
dim3 threadsPerBlock(BlockSizeX, BlockSizeX);
dim3 blocksPerGrid(int(sqrt(double(_iNumSuppNodes))/BlockSizeX)+1, int(sqrt(double(_iNumSuppNodes))/BlockSizeX)+1);
time = clock();
ImpositionBoundaryConditionKernel<<<blocksPerGrid, threadsPerBlock>>>(_iNumMeshNodes, _iNumSuppNodes, _inumDiaPart, supp, K, B);
cudaDeviceSynchronize();
//printf(" Time Execution : %0.3f s \n", (clock()-time)/CLOCKS_PER_SEC);
}
//==============================================================================
__global__ void ImpositionBoundaryConditionNeumannKernel(int _iNumMeshNodes, int _iNumSuppNodes, int *supp, double *B)
{
// _iNumSuppNodes = total number of supports
int i;
const int xIndex = blockIdx.x*blockDim.x + threadIdx.x;
const int yIndex = blockIdx.y*blockDim.y + threadIdx.y;
const int thread_id = (gridDim.x*blockDim.x)*yIndex + xIndex;
if(thread_id < _iNumSuppNodes) { // -----------------------
if(supp[thread_id+1*_iNumSuppNodes] == 1) B[3*(supp[thread_id]-1) ] = 0.;
if(supp[thread_id+2*_iNumSuppNodes] == 1) B[3*(supp[thread_id]-1)+1] = 0.;
if(supp[thread_id+3*_iNumSuppNodes] == 1) B[3*(supp[thread_id]-1)+2] = 0.;
}
}
//=====================================================================================================================
void ImpositionBoundaryConditionNeumann(int Id, int BlockSizeX, int _iNumMeshNodes, int _iNumSuppNodes, int *supp, double *B)
{
double time;
cudaSetDevice(Id);
dim3 threadsPerBlock(BlockSizeX, BlockSizeX);
dim3 blocksPerGrid(int(sqrt(double(_iNumSuppNodes))/BlockSizeX)+1, int(sqrt(double(_iNumSuppNodes))/BlockSizeX)+1);
time = clock();
ImpositionBoundaryConditionNeumannKernel<<<blocksPerGrid, threadsPerBlock>>>(_iNumMeshNodes, _iNumSuppNodes, supp, B);
cudaDeviceSynchronize();
//printf(" Time Execution : %0.3f s \n", (clock()-time)/CLOCKS_PER_SEC);
}
//============================================================================== | .file "tmpxft_0007a6f4_00000000-6_boundaryCond.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB4043:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4043:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z61__device_stub__Z33ImpositionBoundaryConditionKerneliiiPiPdS0_iiiPiPdS0_
.type _Z61__device_stub__Z33ImpositionBoundaryConditionKerneliiiPiPdS0_iiiPiPdS0_, @function
_Z61__device_stub__Z33ImpositionBoundaryConditionKerneliiiPiPdS0_iiiPiPdS0_:
.LFB4065:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movl %edi, 44(%rsp)
movl %esi, 40(%rsp)
movl %edx, 36(%rsp)
movq %rcx, 24(%rsp)
movq %r8, 16(%rsp)
movq %r9, 8(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 44(%rsp), %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rax
movq %rax, 120(%rsp)
leaq 36(%rsp), %rax
movq %rax, 128(%rsp)
leaq 24(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z33ImpositionBoundaryConditionKerneliiiPiPdS0_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4065:
.size _Z61__device_stub__Z33ImpositionBoundaryConditionKerneliiiPiPdS0_iiiPiPdS0_, .-_Z61__device_stub__Z33ImpositionBoundaryConditionKerneliiiPiPdS0_iiiPiPdS0_
.globl _Z33ImpositionBoundaryConditionKerneliiiPiPdS0_
.type _Z33ImpositionBoundaryConditionKerneliiiPiPdS0_, @function
_Z33ImpositionBoundaryConditionKerneliiiPiPdS0_:
.LFB4066:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z61__device_stub__Z33ImpositionBoundaryConditionKerneliiiPiPdS0_iiiPiPdS0_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4066:
.size _Z33ImpositionBoundaryConditionKerneliiiPiPdS0_, .-_Z33ImpositionBoundaryConditionKerneliiiPiPdS0_
.globl ImpositionBoundaryCondition
.type ImpositionBoundaryCondition, @function
ImpositionBoundaryCondition:
.LFB4039:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $48, %rsp
.cfi_def_cfa_offset 96
movl %esi, %ebx
movl %edx, %r12d
movl %ecx, %ebp
movl %r8d, %r13d
movq %r9, %r14
call cudaSetDevice@PLT
movl %ebx, 24(%rsp)
movl %ebx, 28(%rsp)
movl $1, 32(%rsp)
pxor %xmm2, %xmm2
cvtsi2sdl %ebp, %xmm2
movsd %xmm2, 8(%rsp)
pxor %xmm0, %xmm0
ucomisd %xmm2, %xmm0
ja .L17
sqrtsd %xmm2, %xmm2
movapd %xmm2, %xmm0
pxor %xmm3, %xmm3
cvtsi2sdl %ebx, %xmm3
movsd %xmm3, (%rsp)
movapd %xmm2, %xmm1
divsd %xmm3, %xmm1
cvttsd2sil %xmm1, %ebx
addl $1, %ebx
.L14:
divsd (%rsp), %xmm0
cvttsd2sil %xmm0, %eax
addl $1, %eax
movl %eax, 36(%rsp)
movl %ebx, 40(%rsp)
movl $1, 44(%rsp)
call clock@PLT
movl 32(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 24(%rsp), %rdx
movq 36(%rsp), %rdi
movl 44(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L19
.L15:
call cudaDeviceSynchronize@PLT
addq $48, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
movsd 8(%rsp), %xmm0
call sqrt@PLT
pxor %xmm5, %xmm5
cvtsi2sdl %ebx, %xmm5
movsd %xmm5, (%rsp)
divsd %xmm5, %xmm0
cvttsd2sil %xmm0, %ebx
addl $1, %ebx
movsd 8(%rsp), %xmm0
call sqrt@PLT
jmp .L14
.L19:
movq 104(%rsp), %r9
movq 96(%rsp), %r8
movq %r14, %rcx
movl %r13d, %edx
movl %ebp, %esi
movl %r12d, %edi
call _Z61__device_stub__Z33ImpositionBoundaryConditionKerneliiiPiPdS0_iiiPiPdS0_
jmp .L15
.cfi_endproc
.LFE4039:
.size ImpositionBoundaryCondition, .-ImpositionBoundaryCondition
.globl _Z64__device_stub__Z40ImpositionBoundaryConditionNeumannKerneliiPiPdiiPiPd
.type _Z64__device_stub__Z40ImpositionBoundaryConditionNeumannKerneliiPiPdiiPiPd, @function
_Z64__device_stub__Z40ImpositionBoundaryConditionNeumannKerneliiPiPdiiPiPd:
.LFB4067:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movl %esi, 24(%rsp)
movq %rdx, 16(%rsp)
movq %rcx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L24
.L20:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L25
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L24:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z40ImpositionBoundaryConditionNeumannKerneliiPiPd(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L20
.L25:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4067:
.size _Z64__device_stub__Z40ImpositionBoundaryConditionNeumannKerneliiPiPdiiPiPd, .-_Z64__device_stub__Z40ImpositionBoundaryConditionNeumannKerneliiPiPdiiPiPd
.globl _Z40ImpositionBoundaryConditionNeumannKerneliiPiPd
.type _Z40ImpositionBoundaryConditionNeumannKerneliiPiPd, @function
_Z40ImpositionBoundaryConditionNeumannKerneliiPiPd:
.LFB4068:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z64__device_stub__Z40ImpositionBoundaryConditionNeumannKerneliiPiPdiiPiPd
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4068:
.size _Z40ImpositionBoundaryConditionNeumannKerneliiPiPd, .-_Z40ImpositionBoundaryConditionNeumannKerneliiPiPd
.globl ImpositionBoundaryConditionNeumann
.type ImpositionBoundaryConditionNeumann, @function
ImpositionBoundaryConditionNeumann:
.LFB4040:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $48, %rsp
.cfi_def_cfa_offset 96
movl %esi, %ebx
movl %edx, %r12d
movl %ecx, %ebp
movq %r8, %r13
movq %r9, %r14
call cudaSetDevice@PLT
movl %ebx, 24(%rsp)
movl %ebx, 28(%rsp)
movl $1, 32(%rsp)
pxor %xmm2, %xmm2
cvtsi2sdl %ebp, %xmm2
movsd %xmm2, 8(%rsp)
pxor %xmm0, %xmm0
ucomisd %xmm2, %xmm0
ja .L34
sqrtsd %xmm2, %xmm2
movapd %xmm2, %xmm0
pxor %xmm3, %xmm3
cvtsi2sdl %ebx, %xmm3
movsd %xmm3, (%rsp)
movapd %xmm2, %xmm1
divsd %xmm3, %xmm1
cvttsd2sil %xmm1, %ebx
addl $1, %ebx
.L31:
divsd (%rsp), %xmm0
cvttsd2sil %xmm0, %eax
addl $1, %eax
movl %eax, 36(%rsp)
movl %ebx, 40(%rsp)
movl $1, 44(%rsp)
call clock@PLT
movl 32(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 24(%rsp), %rdx
movq 36(%rsp), %rdi
movl 44(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L36
.L32:
call cudaDeviceSynchronize@PLT
addq $48, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L34:
.cfi_restore_state
movsd 8(%rsp), %xmm0
call sqrt@PLT
pxor %xmm5, %xmm5
cvtsi2sdl %ebx, %xmm5
movsd %xmm5, (%rsp)
divsd %xmm5, %xmm0
cvttsd2sil %xmm0, %ebx
addl $1, %ebx
movsd 8(%rsp), %xmm0
call sqrt@PLT
jmp .L31
.L36:
movq %r14, %rcx
movq %r13, %rdx
movl %ebp, %esi
movl %r12d, %edi
call _Z64__device_stub__Z40ImpositionBoundaryConditionNeumannKerneliiPiPdiiPiPd
jmp .L32
.cfi_endproc
.LFE4040:
.size ImpositionBoundaryConditionNeumann, .-ImpositionBoundaryConditionNeumann
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "_Z40ImpositionBoundaryConditionNeumannKerneliiPiPd"
.align 8
.LC2:
.string "_Z33ImpositionBoundaryConditionKerneliiiPiPdS0_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB4070:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z40ImpositionBoundaryConditionNeumannKerneliiPiPd(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z33ImpositionBoundaryConditionKerneliiiPiPdS0_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4070:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *\
* Copyright (c) 2019 <GTEP> - All Rights Reserved *
* This file is part of HERMES Project. *
* Unauthorized copying of this file, via any medium is strictly prohibited. *
* Proprietary and confidential. *
* *
* Developers: *
* - Bismarck G. Souza Jr <bismarck@puc-rio.br> *
* - Nelson Inoue <inoue@puc-rio.br> *
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
//
// o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o
// o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o
//
// C C C C C C U U U U D D D D D D D D D A A A A A A
// C C C C C C C C U U U U D D D D D D D D D D A A A A A A A A
// C C C C U U U U D D D D A A A A
// C C C C U U U U D D D D A A A A
// C C U U U U D D D D A A A A
// C C U U U U D D D D A A A A
// C C U U U U D D D D A A A A A A A A A A A A
// C C U U U U D D D D A A A A A A A A A A A A
// C C U U U U D D D D A A A A
// C C C C U U U U D D D D A A A A
// C C C C C C C C U U U U U U U U D D D D D D D D D D A A A A
// C C C C C C U U U U U U D D D D D D D D D A A A A
//
// o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o
// o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o
// includes, system
#include <stdlib.h>
#include <stdio.h>
#include <string.h>
#include <iostream>
#include <fstream>
#include <iomanip>
#include <time.h>
#include <cuda_runtime.h>
//----------------------------------------------------
// External Functions for one GPU Implementation
//----------------------------------------------------
extern "C" void ImpositionBoundaryCondition(int Id, int BlockSizeX, int _iNumMeshNodes, int _iNumSuppNodes, int _inumDiaPart, int *supp, double *K, double *B);
extern "C" void ImpositionBoundaryConditionNeumann(int Id, int BlockSizeX, int _iNumMeshNodes, int _iNumSuppNodes, int *supp, double *B);
//==============================================================================
__global__ void ImpositionBoundaryConditionKernel(int _iNumMeshNodes, int _iNumSuppNodes, int _inumDiaPart, int *supp, double *K, double *B)
{
// _iNumSuppNodes = total number of supports
int i;
const int xIndex = blockIdx.x*blockDim.x + threadIdx.x;
const int yIndex = blockIdx.y*blockDim.y + threadIdx.y;
const int thread_id = (gridDim.x*blockDim.x)*yIndex + xIndex;
if(thread_id < _iNumSuppNodes) { // -----------------------
for(i=0; i<_inumDiaPart; i++) {
if(supp[thread_id+1*_iNumSuppNodes] == 1) K[3*(supp[thread_id]-1) + i*3*_iNumMeshNodes] = 0.;
if(supp[thread_id+2*_iNumSuppNodes] == 1) K[3*(supp[thread_id]-1)+1 + i*3*_iNumMeshNodes] = 0.;
if(supp[thread_id+3*_iNumSuppNodes] == 1) K[3*(supp[thread_id]-1)+2 + i*3*_iNumMeshNodes] = 0.;
}
if(supp[thread_id+1*_iNumSuppNodes] == 1) B[3*(supp[thread_id]-1) ] = 0.;
if(supp[thread_id+2*_iNumSuppNodes] == 1) B[3*(supp[thread_id]-1)+1] = 0.;
if(supp[thread_id+3*_iNumSuppNodes] == 1) B[3*(supp[thread_id]-1)+2] = 0.;
}
}
//=====================================================================================================================
void ImpositionBoundaryCondition(int Id, int BlockSizeX, int _iNumMeshNodes, int _iNumSuppNodes, int _inumDiaPart, int *supp, double *K, double *B)
{
double time;
cudaSetDevice(Id);
dim3 threadsPerBlock(BlockSizeX, BlockSizeX);
dim3 blocksPerGrid(int(sqrt(double(_iNumSuppNodes))/BlockSizeX)+1, int(sqrt(double(_iNumSuppNodes))/BlockSizeX)+1);
time = clock();
ImpositionBoundaryConditionKernel<<<blocksPerGrid, threadsPerBlock>>>(_iNumMeshNodes, _iNumSuppNodes, _inumDiaPart, supp, K, B);
cudaDeviceSynchronize();
//printf(" Time Execution : %0.3f s \n", (clock()-time)/CLOCKS_PER_SEC);
}
//==============================================================================
__global__ void ImpositionBoundaryConditionNeumannKernel(int _iNumMeshNodes, int _iNumSuppNodes, int *supp, double *B)
{
// _iNumSuppNodes = total number of supports
int i;
const int xIndex = blockIdx.x*blockDim.x + threadIdx.x;
const int yIndex = blockIdx.y*blockDim.y + threadIdx.y;
const int thread_id = (gridDim.x*blockDim.x)*yIndex + xIndex;
if(thread_id < _iNumSuppNodes) { // -----------------------
if(supp[thread_id+1*_iNumSuppNodes] == 1) B[3*(supp[thread_id]-1) ] = 0.;
if(supp[thread_id+2*_iNumSuppNodes] == 1) B[3*(supp[thread_id]-1)+1] = 0.;
if(supp[thread_id+3*_iNumSuppNodes] == 1) B[3*(supp[thread_id]-1)+2] = 0.;
}
}
//=====================================================================================================================
void ImpositionBoundaryConditionNeumann(int Id, int BlockSizeX, int _iNumMeshNodes, int _iNumSuppNodes, int *supp, double *B)
{
double time;
cudaSetDevice(Id);
dim3 threadsPerBlock(BlockSizeX, BlockSizeX);
dim3 blocksPerGrid(int(sqrt(double(_iNumSuppNodes))/BlockSizeX)+1, int(sqrt(double(_iNumSuppNodes))/BlockSizeX)+1);
time = clock();
ImpositionBoundaryConditionNeumannKernel<<<blocksPerGrid, threadsPerBlock>>>(_iNumMeshNodes, _iNumSuppNodes, supp, B);
cudaDeviceSynchronize();
//printf(" Time Execution : %0.3f s \n", (clock()-time)/CLOCKS_PER_SEC);
}
//============================================================================== | /* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *\
* Copyright (c) 2019 <GTEP> - All Rights Reserved *
* This file is part of HERMES Project. *
* Unauthorized copying of this file, via any medium is strictly prohibited. *
* Proprietary and confidential. *
* *
* Developers: *
* - Bismarck G. Souza Jr <bismarck@puc-rio.br> *
* - Nelson Inoue <inoue@puc-rio.br> *
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
//
// o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o
// o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o
//
// C C C C C C U U U U D D D D D D D D D A A A A A A
// C C C C C C C C U U U U D D D D D D D D D D A A A A A A A A
// C C C C U U U U D D D D A A A A
// C C C C U U U U D D D D A A A A
// C C U U U U D D D D A A A A
// C C U U U U D D D D A A A A
// C C U U U U D D D D A A A A A A A A A A A A
// C C U U U U D D D D A A A A A A A A A A A A
// C C U U U U D D D D A A A A
// C C C C U U U U D D D D A A A A
// C C C C C C C C U U U U U U U U D D D D D D D D D D A A A A
// C C C C C C U U U U U U D D D D D D D D D A A A A
//
// o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o
// o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o
// includes, system
#include <stdlib.h>
#include <stdio.h>
#include <string.h>
#include <iostream>
#include <fstream>
#include <iomanip>
#include <time.h>
#include <hip/hip_runtime.h>
//----------------------------------------------------
// External Functions for one GPU Implementation
//----------------------------------------------------
extern "C" void ImpositionBoundaryCondition(int Id, int BlockSizeX, int _iNumMeshNodes, int _iNumSuppNodes, int _inumDiaPart, int *supp, double *K, double *B);
extern "C" void ImpositionBoundaryConditionNeumann(int Id, int BlockSizeX, int _iNumMeshNodes, int _iNumSuppNodes, int *supp, double *B);
//==============================================================================
__global__ void ImpositionBoundaryConditionKernel(int _iNumMeshNodes, int _iNumSuppNodes, int _inumDiaPart, int *supp, double *K, double *B)
{
// _iNumSuppNodes = total number of supports
int i;
const int xIndex = blockIdx.x*blockDim.x + threadIdx.x;
const int yIndex = blockIdx.y*blockDim.y + threadIdx.y;
const int thread_id = (gridDim.x*blockDim.x)*yIndex + xIndex;
if(thread_id < _iNumSuppNodes) { // -----------------------
for(i=0; i<_inumDiaPart; i++) {
if(supp[thread_id+1*_iNumSuppNodes] == 1) K[3*(supp[thread_id]-1) + i*3*_iNumMeshNodes] = 0.;
if(supp[thread_id+2*_iNumSuppNodes] == 1) K[3*(supp[thread_id]-1)+1 + i*3*_iNumMeshNodes] = 0.;
if(supp[thread_id+3*_iNumSuppNodes] == 1) K[3*(supp[thread_id]-1)+2 + i*3*_iNumMeshNodes] = 0.;
}
if(supp[thread_id+1*_iNumSuppNodes] == 1) B[3*(supp[thread_id]-1) ] = 0.;
if(supp[thread_id+2*_iNumSuppNodes] == 1) B[3*(supp[thread_id]-1)+1] = 0.;
if(supp[thread_id+3*_iNumSuppNodes] == 1) B[3*(supp[thread_id]-1)+2] = 0.;
}
}
//=====================================================================================================================
void ImpositionBoundaryCondition(int Id, int BlockSizeX, int _iNumMeshNodes, int _iNumSuppNodes, int _inumDiaPart, int *supp, double *K, double *B)
{
double time;
hipSetDevice(Id);
dim3 threadsPerBlock(BlockSizeX, BlockSizeX);
dim3 blocksPerGrid(int(sqrt(double(_iNumSuppNodes))/BlockSizeX)+1, int(sqrt(double(_iNumSuppNodes))/BlockSizeX)+1);
time = clock();
ImpositionBoundaryConditionKernel<<<blocksPerGrid, threadsPerBlock>>>(_iNumMeshNodes, _iNumSuppNodes, _inumDiaPart, supp, K, B);
hipDeviceSynchronize();
//printf(" Time Execution : %0.3f s \n", (clock()-time)/CLOCKS_PER_SEC);
}
//==============================================================================
__global__ void ImpositionBoundaryConditionNeumannKernel(int _iNumMeshNodes, int _iNumSuppNodes, int *supp, double *B)
{
// _iNumSuppNodes = total number of supports
int i;
const int xIndex = blockIdx.x*blockDim.x + threadIdx.x;
const int yIndex = blockIdx.y*blockDim.y + threadIdx.y;
const int thread_id = (gridDim.x*blockDim.x)*yIndex + xIndex;
if(thread_id < _iNumSuppNodes) { // -----------------------
if(supp[thread_id+1*_iNumSuppNodes] == 1) B[3*(supp[thread_id]-1) ] = 0.;
if(supp[thread_id+2*_iNumSuppNodes] == 1) B[3*(supp[thread_id]-1)+1] = 0.;
if(supp[thread_id+3*_iNumSuppNodes] == 1) B[3*(supp[thread_id]-1)+2] = 0.;
}
}
//=====================================================================================================================
void ImpositionBoundaryConditionNeumann(int Id, int BlockSizeX, int _iNumMeshNodes, int _iNumSuppNodes, int *supp, double *B)
{
double time;
hipSetDevice(Id);
dim3 threadsPerBlock(BlockSizeX, BlockSizeX);
dim3 blocksPerGrid(int(sqrt(double(_iNumSuppNodes))/BlockSizeX)+1, int(sqrt(double(_iNumSuppNodes))/BlockSizeX)+1);
time = clock();
ImpositionBoundaryConditionNeumannKernel<<<blocksPerGrid, threadsPerBlock>>>(_iNumMeshNodes, _iNumSuppNodes, supp, B);
hipDeviceSynchronize();
//printf(" Time Execution : %0.3f s \n", (clock()-time)/CLOCKS_PER_SEC);
}
//============================================================================== |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | /* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *\
* Copyright (c) 2019 <GTEP> - All Rights Reserved *
* This file is part of HERMES Project. *
* Unauthorized copying of this file, via any medium is strictly prohibited. *
* Proprietary and confidential. *
* *
* Developers: *
* - Bismarck G. Souza Jr <bismarck@puc-rio.br> *
* - Nelson Inoue <inoue@puc-rio.br> *
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
//
// o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o
// o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o
//
// C C C C C C U U U U D D D D D D D D D A A A A A A
// C C C C C C C C U U U U D D D D D D D D D D A A A A A A A A
// C C C C U U U U D D D D A A A A
// C C C C U U U U D D D D A A A A
// C C U U U U D D D D A A A A
// C C U U U U D D D D A A A A
// C C U U U U D D D D A A A A A A A A A A A A
// C C U U U U D D D D A A A A A A A A A A A A
// C C U U U U D D D D A A A A
// C C C C U U U U D D D D A A A A
// C C C C C C C C U U U U U U U U D D D D D D D D D D A A A A
// C C C C C C U U U U U U D D D D D D D D D A A A A
//
// o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o
// o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o
// includes, system
#include <stdlib.h>
#include <stdio.h>
#include <string.h>
#include <iostream>
#include <fstream>
#include <iomanip>
#include <time.h>
#include <hip/hip_runtime.h>
//----------------------------------------------------
// External Functions for one GPU Implementation
//----------------------------------------------------
extern "C" void ImpositionBoundaryCondition(int Id, int BlockSizeX, int _iNumMeshNodes, int _iNumSuppNodes, int _inumDiaPart, int *supp, double *K, double *B);
extern "C" void ImpositionBoundaryConditionNeumann(int Id, int BlockSizeX, int _iNumMeshNodes, int _iNumSuppNodes, int *supp, double *B);
//==============================================================================
__global__ void ImpositionBoundaryConditionKernel(int _iNumMeshNodes, int _iNumSuppNodes, int _inumDiaPart, int *supp, double *K, double *B)
{
// _iNumSuppNodes = total number of supports
int i;
const int xIndex = blockIdx.x*blockDim.x + threadIdx.x;
const int yIndex = blockIdx.y*blockDim.y + threadIdx.y;
const int thread_id = (gridDim.x*blockDim.x)*yIndex + xIndex;
if(thread_id < _iNumSuppNodes) { // -----------------------
for(i=0; i<_inumDiaPart; i++) {
if(supp[thread_id+1*_iNumSuppNodes] == 1) K[3*(supp[thread_id]-1) + i*3*_iNumMeshNodes] = 0.;
if(supp[thread_id+2*_iNumSuppNodes] == 1) K[3*(supp[thread_id]-1)+1 + i*3*_iNumMeshNodes] = 0.;
if(supp[thread_id+3*_iNumSuppNodes] == 1) K[3*(supp[thread_id]-1)+2 + i*3*_iNumMeshNodes] = 0.;
}
if(supp[thread_id+1*_iNumSuppNodes] == 1) B[3*(supp[thread_id]-1) ] = 0.;
if(supp[thread_id+2*_iNumSuppNodes] == 1) B[3*(supp[thread_id]-1)+1] = 0.;
if(supp[thread_id+3*_iNumSuppNodes] == 1) B[3*(supp[thread_id]-1)+2] = 0.;
}
}
//=====================================================================================================================
void ImpositionBoundaryCondition(int Id, int BlockSizeX, int _iNumMeshNodes, int _iNumSuppNodes, int _inumDiaPart, int *supp, double *K, double *B)
{
double time;
hipSetDevice(Id);
dim3 threadsPerBlock(BlockSizeX, BlockSizeX);
dim3 blocksPerGrid(int(sqrt(double(_iNumSuppNodes))/BlockSizeX)+1, int(sqrt(double(_iNumSuppNodes))/BlockSizeX)+1);
time = clock();
ImpositionBoundaryConditionKernel<<<blocksPerGrid, threadsPerBlock>>>(_iNumMeshNodes, _iNumSuppNodes, _inumDiaPart, supp, K, B);
hipDeviceSynchronize();
//printf(" Time Execution : %0.3f s \n", (clock()-time)/CLOCKS_PER_SEC);
}
//==============================================================================
__global__ void ImpositionBoundaryConditionNeumannKernel(int _iNumMeshNodes, int _iNumSuppNodes, int *supp, double *B)
{
// _iNumSuppNodes = total number of supports
int i;
const int xIndex = blockIdx.x*blockDim.x + threadIdx.x;
const int yIndex = blockIdx.y*blockDim.y + threadIdx.y;
const int thread_id = (gridDim.x*blockDim.x)*yIndex + xIndex;
if(thread_id < _iNumSuppNodes) { // -----------------------
if(supp[thread_id+1*_iNumSuppNodes] == 1) B[3*(supp[thread_id]-1) ] = 0.;
if(supp[thread_id+2*_iNumSuppNodes] == 1) B[3*(supp[thread_id]-1)+1] = 0.;
if(supp[thread_id+3*_iNumSuppNodes] == 1) B[3*(supp[thread_id]-1)+2] = 0.;
}
}
//=====================================================================================================================
void ImpositionBoundaryConditionNeumann(int Id, int BlockSizeX, int _iNumMeshNodes, int _iNumSuppNodes, int *supp, double *B)
{
double time;
hipSetDevice(Id);
dim3 threadsPerBlock(BlockSizeX, BlockSizeX);
dim3 blocksPerGrid(int(sqrt(double(_iNumSuppNodes))/BlockSizeX)+1, int(sqrt(double(_iNumSuppNodes))/BlockSizeX)+1);
time = clock();
ImpositionBoundaryConditionNeumannKernel<<<blocksPerGrid, threadsPerBlock>>>(_iNumMeshNodes, _iNumSuppNodes, supp, B);
hipDeviceSynchronize();
//printf(" Time Execution : %0.3f s \n", (clock()-time)/CLOCKS_PER_SEC);
}
//============================================================================== | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z33ImpositionBoundaryConditionKerneliiiPiPdS0_
.globl _Z33ImpositionBoundaryConditionKerneliiiPiPdS0_
.p2align 8
.type _Z33ImpositionBoundaryConditionKerneliiiPiPdS0_,@function
_Z33ImpositionBoundaryConditionKerneliiiPiPdS0_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x34
s_load_b32 s3, s[0:1], 0x28
v_bfe_u32 v1, v0, 10, 10
s_load_b32 s5, s[0:1], 0x4
s_waitcnt lgkmcnt(0)
s_lshr_b32 s4, s2, 16
s_and_b32 s2, s2, 0xffff
v_mad_u64_u32 v[2:3], null, s15, s4, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[3:4], null, v2, s3, s[14:15]
v_and_b32_e32 v2, 0x3ff, v0
v_mad_u64_u32 v[0:1], null, v3, s2, v[2:3]
s_mov_b32 s2, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s5, v0
s_cbranch_execz .LBB0_16
s_clause 0x1
s_load_b32 s10, s[0:1], 0x8
s_load_b64 s[6:7], s[0:1], 0x10
v_add_nc_u32_e32 v2, s5, v0
v_ashrrev_i32_e32 v1, 31, v0
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s10, 1
s_cbranch_scc1 .LBB0_10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[4:5], null, s5, 3, v[0:1]
v_lshl_add_u32 v6, s5, 1, v0
v_ashrrev_i32_e32 v3, 31, v2
s_mov_b32 s12, 0
v_ashrrev_i32_e32 v7, 31, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[8:9], 2, v[2:3]
v_ashrrev_i32_e32 v5, 31, v4
v_lshlrev_b64 v[6:7], 2, v[6:7]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v8, vcc_lo, s6, v8
v_lshlrev_b64 v[3:4], 2, v[4:5]
v_add_co_ci_u32_e32 v9, vcc_lo, s7, v9, vcc_lo
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_add_co_u32 v5, vcc_lo, s6, v6
v_add_co_ci_u32_e32 v6, vcc_lo, s7, v7, vcc_lo
v_add_co_u32 v3, vcc_lo, s6, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s7, v4, vcc_lo
s_clause 0x2
global_load_b32 v8, v[8:9], off
global_load_b32 v5, v[5:6], off
global_load_b32 v6, v[3:4], off
s_clause 0x1
s_load_b32 s11, s[0:1], 0x0
s_load_b64 s[8:9], s[0:1], 0x18
v_lshlrev_b64 v[3:4], 2, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v3, s2, s6, v3
v_add_co_ci_u32_e64 v4, s2, s7, v4, s2
s_waitcnt vmcnt(2)
v_cmp_eq_u32_e32 vcc_lo, 1, v8
s_waitcnt vmcnt(1)
v_cmp_eq_u32_e64 s2, 1, v5
s_waitcnt vmcnt(0)
v_cmp_eq_u32_e64 s3, 1, v6
s_branch .LBB0_4
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s13
s_add_i32 s10, s10, -1
s_waitcnt lgkmcnt(0)
s_add_i32 s12, s12, s11
s_cmp_lg_u32 s10, 0
s_cbranch_scc0 .LBB0_10
.LBB0_4:
s_and_saveexec_b32 s13, vcc_lo
s_cbranch_execz .LBB0_6
global_load_b32 v5, v[3:4], off
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v7, s12, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[5:6], null, v7, 3, -3
v_mov_b32_e32 v7, 0
v_mov_b32_e32 v8, v7
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v6, 31, v5
v_lshlrev_b64 v[5:6], 3, v[5:6]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v5, s4, s8, v5
v_add_co_ci_u32_e64 v6, s4, s9, v6, s4
global_store_b64 v[5:6], v[7:8], off
.LBB0_6:
s_or_b32 exec_lo, exec_lo, s13
s_and_saveexec_b32 s13, s2
s_cbranch_execz .LBB0_8
global_load_b32 v5, v[3:4], off
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v7, s12, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[5:6], null, v7, 3, -2
v_mov_b32_e32 v7, 0
v_mov_b32_e32 v8, v7
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v6, 31, v5
v_lshlrev_b64 v[5:6], 3, v[5:6]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v5, s4, s8, v5
v_add_co_ci_u32_e64 v6, s4, s9, v6, s4
global_store_b64 v[5:6], v[7:8], off
.LBB0_8:
s_or_b32 exec_lo, exec_lo, s13
s_and_saveexec_b32 s13, s3
s_cbranch_execz .LBB0_3
global_load_b32 v5, v[3:4], off
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v7, s12, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[5:6], null, v7, 3, -1
v_mov_b32_e32 v7, 0
v_mov_b32_e32 v8, v7
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v6, 31, v5
v_lshlrev_b64 v[5:6], 3, v[5:6]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v5, s4, s8, v5
v_add_co_ci_u32_e64 v6, s4, s9, v6, s4
global_store_b64 v[5:6], v[7:8], off
s_branch .LBB0_3
.LBB0_10:
v_ashrrev_i32_e32 v3, 31, v2
s_load_b64 s[0:1], s[0:1], 0x20
s_mov_b32 s2, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[2:3]
v_add_co_u32 v2, vcc_lo, s6, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v3, vcc_lo
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(0)
v_cmpx_eq_u32_e32 1, v2
s_cbranch_execz .LBB0_12
v_lshlrev_b64 v[2:3], 2, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s6, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v3, vcc_lo
global_load_b32 v4, v[2:3], off
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[2:3], null, v4, 3, -3
v_mov_b32_e32 v4, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_mov_b32_e32 v5, v4
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 3, v[2:3]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s0, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
global_store_b64 v[2:3], v[4:5], off
.LBB0_12:
s_or_b32 exec_lo, exec_lo, s2
v_lshl_add_u32 v2, s5, 1, v0
s_mov_b32 s2, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s6, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v3, vcc_lo
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(0)
v_cmpx_eq_u32_e32 1, v2
s_cbranch_execz .LBB0_14
v_lshlrev_b64 v[2:3], 2, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s6, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v3, vcc_lo
global_load_b32 v4, v[2:3], off
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[2:3], null, v4, 3, -2
v_mov_b32_e32 v4, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_mov_b32_e32 v5, v4
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 3, v[2:3]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s0, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
global_store_b64 v[2:3], v[4:5], off
.LBB0_14:
s_or_b32 exec_lo, exec_lo, s2
v_mad_u64_u32 v[2:3], null, s5, 3, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s6, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v3, vcc_lo
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(0)
v_cmp_eq_u32_e32 vcc_lo, 1, v2
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_16
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
global_load_b32 v2, v[0:1], off
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[0:1], null, v2, 3, -1
v_mov_b32_e32 v2, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_mov_b32_e32 v3, v2
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 3, v[0:1]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b64 v[0:1], v[2:3], off
.LBB0_16:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z33ImpositionBoundaryConditionKerneliiiPiPdS0_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 10
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z33ImpositionBoundaryConditionKerneliiiPiPdS0_, .Lfunc_end0-_Z33ImpositionBoundaryConditionKerneliiiPiPdS0_
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z40ImpositionBoundaryConditionNeumannKerneliiPiPd
.globl _Z40ImpositionBoundaryConditionNeumannKerneliiPiPd
.p2align 8
.type _Z40ImpositionBoundaryConditionNeumannKerneliiPiPd,@function
_Z40ImpositionBoundaryConditionNeumannKerneliiPiPd:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x18
v_bfe_u32 v1, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_lshr_b32 s4, s2, 16
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, s15, s4, v[1:2]
s_load_b32 s4, s[0:1], 0x4
v_mad_u64_u32 v[3:4], null, v2, s3, s[14:15]
v_and_b32_e32 v2, 0x3ff, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[0:1], null, v3, s2, v[2:3]
s_mov_b32 s2, exec_lo
s_waitcnt lgkmcnt(0)
v_cmpx_gt_i32_e64 s4, v0
s_cbranch_execz .LBB1_7
s_load_b128 s[0:3], s[0:1], 0x8
v_add_nc_u32_e32 v1, s4, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v1, vcc_lo, s0, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
global_load_b32 v1, v[1:2], off
s_waitcnt vmcnt(0)
v_cmp_eq_u32_e32 vcc_lo, 1, v1
v_ashrrev_i32_e32 v1, 31, v0
s_and_saveexec_b32 s5, vcc_lo
s_cbranch_execz .LBB1_3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[0:1]
v_add_co_u32 v2, vcc_lo, s0, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
global_load_b32 v4, v[2:3], off
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[2:3], null, v4, 3, -3
v_mov_b32_e32 v4, 0
v_mov_b32_e32 v5, v4
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[2:3], 3, v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s2, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
global_store_b64 v[2:3], v[4:5], off
.LBB1_3:
s_or_b32 exec_lo, exec_lo, s5
v_lshl_add_u32 v2, s4, 1, v0
s_mov_b32 s5, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s0, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(0)
v_cmpx_eq_u32_e32 1, v2
s_cbranch_execz .LBB1_5
v_lshlrev_b64 v[2:3], 2, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s0, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
global_load_b32 v4, v[2:3], off
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[2:3], null, v4, 3, -2
v_mov_b32_e32 v4, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_mov_b32_e32 v5, v4
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 3, v[2:3]
v_add_co_u32 v2, vcc_lo, s2, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
global_store_b64 v[2:3], v[4:5], off
.LBB1_5:
s_or_b32 exec_lo, exec_lo, s5
v_mad_u64_u32 v[2:3], null, s4, 3, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s0, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(0)
v_cmp_eq_u32_e32 vcc_lo, 1, v2
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB1_7
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b32 v2, v[0:1], off
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[0:1], null, v2, 3, -1
v_mov_b32_e32 v2, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_mov_b32_e32 v3, v2
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 3, v[0:1]
v_add_co_u32 v0, vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_store_b64 v[0:1], v[2:3], off
.LBB1_7:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z40ImpositionBoundaryConditionNeumannKerneliiPiPd
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z40ImpositionBoundaryConditionNeumannKerneliiPiPd, .Lfunc_end1-_Z40ImpositionBoundaryConditionNeumannKerneliiPiPd
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .offset: 8
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z33ImpositionBoundaryConditionKerneliiiPiPdS0_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z33ImpositionBoundaryConditionKerneliiiPiPdS0_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 10
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z40ImpositionBoundaryConditionNeumannKerneliiPiPd
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z40ImpositionBoundaryConditionNeumannKerneliiPiPd.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | /* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *\
* Copyright (c) 2019 <GTEP> - All Rights Reserved *
* This file is part of HERMES Project. *
* Unauthorized copying of this file, via any medium is strictly prohibited. *
* Proprietary and confidential. *
* *
* Developers: *
* - Bismarck G. Souza Jr <bismarck@puc-rio.br> *
* - Nelson Inoue <inoue@puc-rio.br> *
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
//
// o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o
// o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o
//
// C C C C C C U U U U D D D D D D D D D A A A A A A
// C C C C C C C C U U U U D D D D D D D D D D A A A A A A A A
// C C C C U U U U D D D D A A A A
// C C C C U U U U D D D D A A A A
// C C U U U U D D D D A A A A
// C C U U U U D D D D A A A A
// C C U U U U D D D D A A A A A A A A A A A A
// C C U U U U D D D D A A A A A A A A A A A A
// C C U U U U D D D D A A A A
// C C C C U U U U D D D D A A A A
// C C C C C C C C U U U U U U U U D D D D D D D D D D A A A A
// C C C C C C U U U U U U D D D D D D D D D A A A A
//
// o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o
// o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o+o
// includes, system
#include <stdlib.h>
#include <stdio.h>
#include <string.h>
#include <iostream>
#include <fstream>
#include <iomanip>
#include <time.h>
#include <hip/hip_runtime.h>
//----------------------------------------------------
// External Functions for one GPU Implementation
//----------------------------------------------------
extern "C" void ImpositionBoundaryCondition(int Id, int BlockSizeX, int _iNumMeshNodes, int _iNumSuppNodes, int _inumDiaPart, int *supp, double *K, double *B);
extern "C" void ImpositionBoundaryConditionNeumann(int Id, int BlockSizeX, int _iNumMeshNodes, int _iNumSuppNodes, int *supp, double *B);
//==============================================================================
__global__ void ImpositionBoundaryConditionKernel(int _iNumMeshNodes, int _iNumSuppNodes, int _inumDiaPart, int *supp, double *K, double *B)
{
// _iNumSuppNodes = total number of supports
int i;
const int xIndex = blockIdx.x*blockDim.x + threadIdx.x;
const int yIndex = blockIdx.y*blockDim.y + threadIdx.y;
const int thread_id = (gridDim.x*blockDim.x)*yIndex + xIndex;
if(thread_id < _iNumSuppNodes) { // -----------------------
for(i=0; i<_inumDiaPart; i++) {
if(supp[thread_id+1*_iNumSuppNodes] == 1) K[3*(supp[thread_id]-1) + i*3*_iNumMeshNodes] = 0.;
if(supp[thread_id+2*_iNumSuppNodes] == 1) K[3*(supp[thread_id]-1)+1 + i*3*_iNumMeshNodes] = 0.;
if(supp[thread_id+3*_iNumSuppNodes] == 1) K[3*(supp[thread_id]-1)+2 + i*3*_iNumMeshNodes] = 0.;
}
if(supp[thread_id+1*_iNumSuppNodes] == 1) B[3*(supp[thread_id]-1) ] = 0.;
if(supp[thread_id+2*_iNumSuppNodes] == 1) B[3*(supp[thread_id]-1)+1] = 0.;
if(supp[thread_id+3*_iNumSuppNodes] == 1) B[3*(supp[thread_id]-1)+2] = 0.;
}
}
//=====================================================================================================================
void ImpositionBoundaryCondition(int Id, int BlockSizeX, int _iNumMeshNodes, int _iNumSuppNodes, int _inumDiaPart, int *supp, double *K, double *B)
{
double time;
hipSetDevice(Id);
dim3 threadsPerBlock(BlockSizeX, BlockSizeX);
dim3 blocksPerGrid(int(sqrt(double(_iNumSuppNodes))/BlockSizeX)+1, int(sqrt(double(_iNumSuppNodes))/BlockSizeX)+1);
time = clock();
ImpositionBoundaryConditionKernel<<<blocksPerGrid, threadsPerBlock>>>(_iNumMeshNodes, _iNumSuppNodes, _inumDiaPart, supp, K, B);
hipDeviceSynchronize();
//printf(" Time Execution : %0.3f s \n", (clock()-time)/CLOCKS_PER_SEC);
}
//==============================================================================
__global__ void ImpositionBoundaryConditionNeumannKernel(int _iNumMeshNodes, int _iNumSuppNodes, int *supp, double *B)
{
// _iNumSuppNodes = total number of supports
int i;
const int xIndex = blockIdx.x*blockDim.x + threadIdx.x;
const int yIndex = blockIdx.y*blockDim.y + threadIdx.y;
const int thread_id = (gridDim.x*blockDim.x)*yIndex + xIndex;
if(thread_id < _iNumSuppNodes) { // -----------------------
if(supp[thread_id+1*_iNumSuppNodes] == 1) B[3*(supp[thread_id]-1) ] = 0.;
if(supp[thread_id+2*_iNumSuppNodes] == 1) B[3*(supp[thread_id]-1)+1] = 0.;
if(supp[thread_id+3*_iNumSuppNodes] == 1) B[3*(supp[thread_id]-1)+2] = 0.;
}
}
//=====================================================================================================================
void ImpositionBoundaryConditionNeumann(int Id, int BlockSizeX, int _iNumMeshNodes, int _iNumSuppNodes, int *supp, double *B)
{
double time;
hipSetDevice(Id);
dim3 threadsPerBlock(BlockSizeX, BlockSizeX);
dim3 blocksPerGrid(int(sqrt(double(_iNumSuppNodes))/BlockSizeX)+1, int(sqrt(double(_iNumSuppNodes))/BlockSizeX)+1);
time = clock();
ImpositionBoundaryConditionNeumannKernel<<<blocksPerGrid, threadsPerBlock>>>(_iNumMeshNodes, _iNumSuppNodes, supp, B);
hipDeviceSynchronize();
//printf(" Time Execution : %0.3f s \n", (clock()-time)/CLOCKS_PER_SEC);
}
//============================================================================== | .text
.file "boundaryCond.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z48__device_stub__ImpositionBoundaryConditionKerneliiiPiPdS0_ # -- Begin function _Z48__device_stub__ImpositionBoundaryConditionKerneliiiPiPdS0_
.p2align 4, 0x90
.type _Z48__device_stub__ImpositionBoundaryConditionKerneliiiPiPdS0_,@function
_Z48__device_stub__ImpositionBoundaryConditionKerneliiiPiPdS0_: # @_Z48__device_stub__ImpositionBoundaryConditionKerneliiiPiPdS0_
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 20(%rsp)
movl %esi, 16(%rsp)
movl %edx, 12(%rsp)
movq %rcx, 88(%rsp)
movq %r8, 80(%rsp)
movq %r9, 72(%rsp)
leaq 20(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 88(%rsp), %rax
movq %rax, 120(%rsp)
leaq 80(%rsp), %rax
movq %rax, 128(%rsp)
leaq 72(%rsp), %rax
movq %rax, 136(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z33ImpositionBoundaryConditionKerneliiiPiPdS0_, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z48__device_stub__ImpositionBoundaryConditionKerneliiiPiPdS0_, .Lfunc_end0-_Z48__device_stub__ImpositionBoundaryConditionKerneliiiPiPdS0_
.cfi_endproc
# -- End function
.globl ImpositionBoundaryCondition # -- Begin function ImpositionBoundaryCondition
.p2align 4, 0x90
.type ImpositionBoundaryCondition,@function
ImpositionBoundaryCondition: # @ImpositionBoundaryCondition
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $168, %rsp
.cfi_def_cfa_offset 224
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %r9, 32(%rsp) # 8-byte Spill
movl %r8d, 8(%rsp) # 4-byte Spill
movl %ecx, %r14d
movl %edx, %r15d
movl %esi, %r13d
callq hipSetDevice
movl %r13d, %ebx
movq %rbx, %r12
shlq $32, %r12
cvtsi2sd %r14d, %xmm2
sqrtsd %xmm2, %xmm1
xorpd %xmm3, %xmm3
ucomisd %xmm3, %xmm2
movapd %xmm1, %xmm0
jae .LBB1_2
# %bb.1: # %call.sqrt
movapd %xmm2, %xmm0
movsd %xmm1, (%rsp) # 8-byte Spill
movsd %xmm2, 24(%rsp) # 8-byte Spill
callq sqrt
xorpd %xmm3, %xmm3
movsd 24(%rsp), %xmm2 # 8-byte Reload
# xmm2 = mem[0],zero
movsd (%rsp), %xmm1 # 8-byte Reload
# xmm1 = mem[0],zero
.LBB1_2: # %.split
cvtsi2sd %r13d, %xmm4
divsd %xmm4, %xmm0
cvttsd2si %xmm0, %ebp
orq %r12, %rbx
incl %ebp
ucomisd %xmm3, %xmm2
jae .LBB1_4
# %bb.3: # %call.sqrt20
movapd %xmm2, %xmm0
movsd %xmm4, (%rsp) # 8-byte Spill
callq sqrt
movsd (%rsp), %xmm4 # 8-byte Reload
# xmm4 = mem[0],zero
movapd %xmm0, %xmm1
.LBB1_4: # %.split.split
divsd %xmm4, %xmm1
cvttsd2si %xmm1, %r13d
incl %r13d
movl %ebp, %eax
shlq $32, %r13
orq %rax, %r13
callq clock
movq %r13, %rdi
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_6
# %bb.5:
movq 232(%rsp), %rax
movq 224(%rsp), %rcx
movl %r15d, 20(%rsp)
movl %r14d, 16(%rsp)
movl 8(%rsp), %edx # 4-byte Reload
movl %edx, 12(%rsp)
movq 32(%rsp), %rdx # 8-byte Reload
movq %rdx, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rax, 88(%rsp)
leaq 20(%rsp), %rax
movq %rax, 112(%rsp)
leaq 16(%rsp), %rax
movq %rax, 120(%rsp)
leaq 12(%rsp), %rax
movq %rax, 128(%rsp)
leaq 104(%rsp), %rax
movq %rax, 136(%rsp)
leaq 96(%rsp), %rax
movq %rax, 144(%rsp)
leaq 88(%rsp), %rax
movq %rax, 152(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z33ImpositionBoundaryConditionKerneliiiPiPdS0_, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_6:
callq hipDeviceSynchronize
addq $168, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size ImpositionBoundaryCondition, .Lfunc_end1-ImpositionBoundaryCondition
.cfi_endproc
# -- End function
.globl _Z55__device_stub__ImpositionBoundaryConditionNeumannKerneliiPiPd # -- Begin function _Z55__device_stub__ImpositionBoundaryConditionNeumannKerneliiPiPd
.p2align 4, 0x90
.type _Z55__device_stub__ImpositionBoundaryConditionNeumannKerneliiPiPd,@function
_Z55__device_stub__ImpositionBoundaryConditionNeumannKerneliiPiPd: # @_Z55__device_stub__ImpositionBoundaryConditionNeumannKerneliiPiPd
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 12(%rsp)
movl %esi, 8(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 8(%rsp), %rax
movq %rax, 88(%rsp)
leaq 72(%rsp), %rax
movq %rax, 96(%rsp)
leaq 64(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z40ImpositionBoundaryConditionNeumannKerneliiPiPd, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end2:
.size _Z55__device_stub__ImpositionBoundaryConditionNeumannKerneliiPiPd, .Lfunc_end2-_Z55__device_stub__ImpositionBoundaryConditionNeumannKerneliiPiPd
.cfi_endproc
# -- End function
.globl ImpositionBoundaryConditionNeumann # -- Begin function ImpositionBoundaryConditionNeumann
.p2align 4, 0x90
.type ImpositionBoundaryConditionNeumann,@function
ImpositionBoundaryConditionNeumann: # @ImpositionBoundaryConditionNeumann
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $152, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %r9, 40(%rsp) # 8-byte Spill
movq %r8, 32(%rsp) # 8-byte Spill
movl %ecx, %ebp
movl %edx, %r15d
movl %esi, %r13d
callq hipSetDevice
movl %r13d, %ebx
movq %rbx, %r12
shlq $32, %r12
cvtsi2sd %ebp, %xmm2
sqrtsd %xmm2, %xmm1
xorpd %xmm3, %xmm3
ucomisd %xmm3, %xmm2
movapd %xmm1, %xmm0
jae .LBB3_2
# %bb.1: # %call.sqrt
movapd %xmm2, %xmm0
movsd %xmm1, 8(%rsp) # 8-byte Spill
movsd %xmm2, 24(%rsp) # 8-byte Spill
callq sqrt
xorpd %xmm3, %xmm3
movsd 24(%rsp), %xmm2 # 8-byte Reload
# xmm2 = mem[0],zero
movsd 8(%rsp), %xmm1 # 8-byte Reload
# xmm1 = mem[0],zero
.LBB3_2: # %.split
cvtsi2sd %r13d, %xmm4
divsd %xmm4, %xmm0
cvttsd2si %xmm0, %r14d
orq %r12, %rbx
incl %r14d
ucomisd %xmm3, %xmm2
jae .LBB3_4
# %bb.3: # %call.sqrt18
movapd %xmm2, %xmm0
movsd %xmm4, 8(%rsp) # 8-byte Spill
callq sqrt
movsd 8(%rsp), %xmm4 # 8-byte Reload
# xmm4 = mem[0],zero
movapd %xmm0, %xmm1
.LBB3_4: # %.split.split
divsd %xmm4, %xmm1
cvttsd2si %xmm1, %r13d
incl %r13d
movl %r14d, %eax
shlq $32, %r13
orq %rax, %r13
callq clock
movq %r13, %rdi
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_6
# %bb.5:
movl %r15d, 20(%rsp)
movl %ebp, 16(%rsp)
movq 32(%rsp), %rax # 8-byte Reload
movq %rax, 104(%rsp)
movq 40(%rsp), %rax # 8-byte Reload
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 112(%rsp)
leaq 16(%rsp), %rax
movq %rax, 120(%rsp)
leaq 104(%rsp), %rax
movq %rax, 128(%rsp)
leaq 96(%rsp), %rax
movq %rax, 136(%rsp)
leaq 80(%rsp), %rdi
leaq 64(%rsp), %rsi
leaq 56(%rsp), %rdx
leaq 48(%rsp), %rcx
callq __hipPopCallConfiguration
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
movq 64(%rsp), %rcx
movl 72(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z40ImpositionBoundaryConditionNeumannKerneliiPiPd, %edi
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_6:
callq hipDeviceSynchronize
addq $152, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size ImpositionBoundaryConditionNeumann, .Lfunc_end3-ImpositionBoundaryConditionNeumann
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z33ImpositionBoundaryConditionKerneliiiPiPdS0_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z40ImpositionBoundaryConditionNeumannKerneliiPiPd, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z33ImpositionBoundaryConditionKerneliiiPiPdS0_,@object # @_Z33ImpositionBoundaryConditionKerneliiiPiPdS0_
.section .rodata,"a",@progbits
.globl _Z33ImpositionBoundaryConditionKerneliiiPiPdS0_
.p2align 3, 0x0
_Z33ImpositionBoundaryConditionKerneliiiPiPdS0_:
.quad _Z48__device_stub__ImpositionBoundaryConditionKerneliiiPiPdS0_
.size _Z33ImpositionBoundaryConditionKerneliiiPiPdS0_, 8
.type _Z40ImpositionBoundaryConditionNeumannKerneliiPiPd,@object # @_Z40ImpositionBoundaryConditionNeumannKerneliiPiPd
.globl _Z40ImpositionBoundaryConditionNeumannKerneliiPiPd
.p2align 3, 0x0
_Z40ImpositionBoundaryConditionNeumannKerneliiPiPd:
.quad _Z55__device_stub__ImpositionBoundaryConditionNeumannKerneliiPiPd
.size _Z40ImpositionBoundaryConditionNeumannKerneliiPiPd, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z33ImpositionBoundaryConditionKerneliiiPiPdS0_"
.size .L__unnamed_1, 48
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z40ImpositionBoundaryConditionNeumannKerneliiPiPd"
.size .L__unnamed_2, 51
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z48__device_stub__ImpositionBoundaryConditionKerneliiiPiPdS0_
.addrsig_sym _Z55__device_stub__ImpositionBoundaryConditionNeumannKerneliiPiPd
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z33ImpositionBoundaryConditionKerneliiiPiPdS0_
.addrsig_sym _Z40ImpositionBoundaryConditionNeumannKerneliiPiPd
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0007a6f4_00000000-6_boundaryCond.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB4043:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4043:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z61__device_stub__Z33ImpositionBoundaryConditionKerneliiiPiPdS0_iiiPiPdS0_
.type _Z61__device_stub__Z33ImpositionBoundaryConditionKerneliiiPiPdS0_iiiPiPdS0_, @function
_Z61__device_stub__Z33ImpositionBoundaryConditionKerneliiiPiPdS0_iiiPiPdS0_:
.LFB4065:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movl %edi, 44(%rsp)
movl %esi, 40(%rsp)
movl %edx, 36(%rsp)
movq %rcx, 24(%rsp)
movq %r8, 16(%rsp)
movq %r9, 8(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 44(%rsp), %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rax
movq %rax, 120(%rsp)
leaq 36(%rsp), %rax
movq %rax, 128(%rsp)
leaq 24(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z33ImpositionBoundaryConditionKerneliiiPiPdS0_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4065:
.size _Z61__device_stub__Z33ImpositionBoundaryConditionKerneliiiPiPdS0_iiiPiPdS0_, .-_Z61__device_stub__Z33ImpositionBoundaryConditionKerneliiiPiPdS0_iiiPiPdS0_
.globl _Z33ImpositionBoundaryConditionKerneliiiPiPdS0_
.type _Z33ImpositionBoundaryConditionKerneliiiPiPdS0_, @function
_Z33ImpositionBoundaryConditionKerneliiiPiPdS0_:
.LFB4066:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z61__device_stub__Z33ImpositionBoundaryConditionKerneliiiPiPdS0_iiiPiPdS0_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4066:
.size _Z33ImpositionBoundaryConditionKerneliiiPiPdS0_, .-_Z33ImpositionBoundaryConditionKerneliiiPiPdS0_
.globl ImpositionBoundaryCondition
.type ImpositionBoundaryCondition, @function
ImpositionBoundaryCondition:
.LFB4039:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $48, %rsp
.cfi_def_cfa_offset 96
movl %esi, %ebx
movl %edx, %r12d
movl %ecx, %ebp
movl %r8d, %r13d
movq %r9, %r14
call cudaSetDevice@PLT
movl %ebx, 24(%rsp)
movl %ebx, 28(%rsp)
movl $1, 32(%rsp)
pxor %xmm2, %xmm2
cvtsi2sdl %ebp, %xmm2
movsd %xmm2, 8(%rsp)
pxor %xmm0, %xmm0
ucomisd %xmm2, %xmm0
ja .L17
sqrtsd %xmm2, %xmm2
movapd %xmm2, %xmm0
pxor %xmm3, %xmm3
cvtsi2sdl %ebx, %xmm3
movsd %xmm3, (%rsp)
movapd %xmm2, %xmm1
divsd %xmm3, %xmm1
cvttsd2sil %xmm1, %ebx
addl $1, %ebx
.L14:
divsd (%rsp), %xmm0
cvttsd2sil %xmm0, %eax
addl $1, %eax
movl %eax, 36(%rsp)
movl %ebx, 40(%rsp)
movl $1, 44(%rsp)
call clock@PLT
movl 32(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 24(%rsp), %rdx
movq 36(%rsp), %rdi
movl 44(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L19
.L15:
call cudaDeviceSynchronize@PLT
addq $48, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
movsd 8(%rsp), %xmm0
call sqrt@PLT
pxor %xmm5, %xmm5
cvtsi2sdl %ebx, %xmm5
movsd %xmm5, (%rsp)
divsd %xmm5, %xmm0
cvttsd2sil %xmm0, %ebx
addl $1, %ebx
movsd 8(%rsp), %xmm0
call sqrt@PLT
jmp .L14
.L19:
movq 104(%rsp), %r9
movq 96(%rsp), %r8
movq %r14, %rcx
movl %r13d, %edx
movl %ebp, %esi
movl %r12d, %edi
call _Z61__device_stub__Z33ImpositionBoundaryConditionKerneliiiPiPdS0_iiiPiPdS0_
jmp .L15
.cfi_endproc
.LFE4039:
.size ImpositionBoundaryCondition, .-ImpositionBoundaryCondition
.globl _Z64__device_stub__Z40ImpositionBoundaryConditionNeumannKerneliiPiPdiiPiPd
.type _Z64__device_stub__Z40ImpositionBoundaryConditionNeumannKerneliiPiPdiiPiPd, @function
_Z64__device_stub__Z40ImpositionBoundaryConditionNeumannKerneliiPiPdiiPiPd:
.LFB4067:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movl %esi, 24(%rsp)
movq %rdx, 16(%rsp)
movq %rcx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L24
.L20:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L25
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L24:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z40ImpositionBoundaryConditionNeumannKerneliiPiPd(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L20
.L25:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4067:
.size _Z64__device_stub__Z40ImpositionBoundaryConditionNeumannKerneliiPiPdiiPiPd, .-_Z64__device_stub__Z40ImpositionBoundaryConditionNeumannKerneliiPiPdiiPiPd
.globl _Z40ImpositionBoundaryConditionNeumannKerneliiPiPd
.type _Z40ImpositionBoundaryConditionNeumannKerneliiPiPd, @function
_Z40ImpositionBoundaryConditionNeumannKerneliiPiPd:
.LFB4068:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z64__device_stub__Z40ImpositionBoundaryConditionNeumannKerneliiPiPdiiPiPd
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4068:
.size _Z40ImpositionBoundaryConditionNeumannKerneliiPiPd, .-_Z40ImpositionBoundaryConditionNeumannKerneliiPiPd
.globl ImpositionBoundaryConditionNeumann
.type ImpositionBoundaryConditionNeumann, @function
ImpositionBoundaryConditionNeumann:
.LFB4040:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $48, %rsp
.cfi_def_cfa_offset 96
movl %esi, %ebx
movl %edx, %r12d
movl %ecx, %ebp
movq %r8, %r13
movq %r9, %r14
call cudaSetDevice@PLT
movl %ebx, 24(%rsp)
movl %ebx, 28(%rsp)
movl $1, 32(%rsp)
pxor %xmm2, %xmm2
cvtsi2sdl %ebp, %xmm2
movsd %xmm2, 8(%rsp)
pxor %xmm0, %xmm0
ucomisd %xmm2, %xmm0
ja .L34
sqrtsd %xmm2, %xmm2
movapd %xmm2, %xmm0
pxor %xmm3, %xmm3
cvtsi2sdl %ebx, %xmm3
movsd %xmm3, (%rsp)
movapd %xmm2, %xmm1
divsd %xmm3, %xmm1
cvttsd2sil %xmm1, %ebx
addl $1, %ebx
.L31:
divsd (%rsp), %xmm0
cvttsd2sil %xmm0, %eax
addl $1, %eax
movl %eax, 36(%rsp)
movl %ebx, 40(%rsp)
movl $1, 44(%rsp)
call clock@PLT
movl 32(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 24(%rsp), %rdx
movq 36(%rsp), %rdi
movl 44(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L36
.L32:
call cudaDeviceSynchronize@PLT
addq $48, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L34:
.cfi_restore_state
movsd 8(%rsp), %xmm0
call sqrt@PLT
pxor %xmm5, %xmm5
cvtsi2sdl %ebx, %xmm5
movsd %xmm5, (%rsp)
divsd %xmm5, %xmm0
cvttsd2sil %xmm0, %ebx
addl $1, %ebx
movsd 8(%rsp), %xmm0
call sqrt@PLT
jmp .L31
.L36:
movq %r14, %rcx
movq %r13, %rdx
movl %ebp, %esi
movl %r12d, %edi
call _Z64__device_stub__Z40ImpositionBoundaryConditionNeumannKerneliiPiPdiiPiPd
jmp .L32
.cfi_endproc
.LFE4040:
.size ImpositionBoundaryConditionNeumann, .-ImpositionBoundaryConditionNeumann
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "_Z40ImpositionBoundaryConditionNeumannKerneliiPiPd"
.align 8
.LC2:
.string "_Z33ImpositionBoundaryConditionKerneliiiPiPdS0_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB4070:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z40ImpositionBoundaryConditionNeumannKerneliiPiPd(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z33ImpositionBoundaryConditionKerneliiiPiPdS0_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4070:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "boundaryCond.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z48__device_stub__ImpositionBoundaryConditionKerneliiiPiPdS0_ # -- Begin function _Z48__device_stub__ImpositionBoundaryConditionKerneliiiPiPdS0_
.p2align 4, 0x90
.type _Z48__device_stub__ImpositionBoundaryConditionKerneliiiPiPdS0_,@function
_Z48__device_stub__ImpositionBoundaryConditionKerneliiiPiPdS0_: # @_Z48__device_stub__ImpositionBoundaryConditionKerneliiiPiPdS0_
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 20(%rsp)
movl %esi, 16(%rsp)
movl %edx, 12(%rsp)
movq %rcx, 88(%rsp)
movq %r8, 80(%rsp)
movq %r9, 72(%rsp)
leaq 20(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 88(%rsp), %rax
movq %rax, 120(%rsp)
leaq 80(%rsp), %rax
movq %rax, 128(%rsp)
leaq 72(%rsp), %rax
movq %rax, 136(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z33ImpositionBoundaryConditionKerneliiiPiPdS0_, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z48__device_stub__ImpositionBoundaryConditionKerneliiiPiPdS0_, .Lfunc_end0-_Z48__device_stub__ImpositionBoundaryConditionKerneliiiPiPdS0_
.cfi_endproc
# -- End function
.globl ImpositionBoundaryCondition # -- Begin function ImpositionBoundaryCondition
.p2align 4, 0x90
.type ImpositionBoundaryCondition,@function
ImpositionBoundaryCondition: # @ImpositionBoundaryCondition
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $168, %rsp
.cfi_def_cfa_offset 224
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %r9, 32(%rsp) # 8-byte Spill
movl %r8d, 8(%rsp) # 4-byte Spill
movl %ecx, %r14d
movl %edx, %r15d
movl %esi, %r13d
callq hipSetDevice
movl %r13d, %ebx
movq %rbx, %r12
shlq $32, %r12
cvtsi2sd %r14d, %xmm2
sqrtsd %xmm2, %xmm1
xorpd %xmm3, %xmm3
ucomisd %xmm3, %xmm2
movapd %xmm1, %xmm0
jae .LBB1_2
# %bb.1: # %call.sqrt
movapd %xmm2, %xmm0
movsd %xmm1, (%rsp) # 8-byte Spill
movsd %xmm2, 24(%rsp) # 8-byte Spill
callq sqrt
xorpd %xmm3, %xmm3
movsd 24(%rsp), %xmm2 # 8-byte Reload
# xmm2 = mem[0],zero
movsd (%rsp), %xmm1 # 8-byte Reload
# xmm1 = mem[0],zero
.LBB1_2: # %.split
cvtsi2sd %r13d, %xmm4
divsd %xmm4, %xmm0
cvttsd2si %xmm0, %ebp
orq %r12, %rbx
incl %ebp
ucomisd %xmm3, %xmm2
jae .LBB1_4
# %bb.3: # %call.sqrt20
movapd %xmm2, %xmm0
movsd %xmm4, (%rsp) # 8-byte Spill
callq sqrt
movsd (%rsp), %xmm4 # 8-byte Reload
# xmm4 = mem[0],zero
movapd %xmm0, %xmm1
.LBB1_4: # %.split.split
divsd %xmm4, %xmm1
cvttsd2si %xmm1, %r13d
incl %r13d
movl %ebp, %eax
shlq $32, %r13
orq %rax, %r13
callq clock
movq %r13, %rdi
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_6
# %bb.5:
movq 232(%rsp), %rax
movq 224(%rsp), %rcx
movl %r15d, 20(%rsp)
movl %r14d, 16(%rsp)
movl 8(%rsp), %edx # 4-byte Reload
movl %edx, 12(%rsp)
movq 32(%rsp), %rdx # 8-byte Reload
movq %rdx, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rax, 88(%rsp)
leaq 20(%rsp), %rax
movq %rax, 112(%rsp)
leaq 16(%rsp), %rax
movq %rax, 120(%rsp)
leaq 12(%rsp), %rax
movq %rax, 128(%rsp)
leaq 104(%rsp), %rax
movq %rax, 136(%rsp)
leaq 96(%rsp), %rax
movq %rax, 144(%rsp)
leaq 88(%rsp), %rax
movq %rax, 152(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z33ImpositionBoundaryConditionKerneliiiPiPdS0_, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_6:
callq hipDeviceSynchronize
addq $168, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size ImpositionBoundaryCondition, .Lfunc_end1-ImpositionBoundaryCondition
.cfi_endproc
# -- End function
.globl _Z55__device_stub__ImpositionBoundaryConditionNeumannKerneliiPiPd # -- Begin function _Z55__device_stub__ImpositionBoundaryConditionNeumannKerneliiPiPd
.p2align 4, 0x90
.type _Z55__device_stub__ImpositionBoundaryConditionNeumannKerneliiPiPd,@function
_Z55__device_stub__ImpositionBoundaryConditionNeumannKerneliiPiPd: # @_Z55__device_stub__ImpositionBoundaryConditionNeumannKerneliiPiPd
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 12(%rsp)
movl %esi, 8(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 8(%rsp), %rax
movq %rax, 88(%rsp)
leaq 72(%rsp), %rax
movq %rax, 96(%rsp)
leaq 64(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z40ImpositionBoundaryConditionNeumannKerneliiPiPd, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end2:
.size _Z55__device_stub__ImpositionBoundaryConditionNeumannKerneliiPiPd, .Lfunc_end2-_Z55__device_stub__ImpositionBoundaryConditionNeumannKerneliiPiPd
.cfi_endproc
# -- End function
.globl ImpositionBoundaryConditionNeumann # -- Begin function ImpositionBoundaryConditionNeumann
.p2align 4, 0x90
.type ImpositionBoundaryConditionNeumann,@function
ImpositionBoundaryConditionNeumann: # @ImpositionBoundaryConditionNeumann
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $152, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %r9, 40(%rsp) # 8-byte Spill
movq %r8, 32(%rsp) # 8-byte Spill
movl %ecx, %ebp
movl %edx, %r15d
movl %esi, %r13d
callq hipSetDevice
movl %r13d, %ebx
movq %rbx, %r12
shlq $32, %r12
cvtsi2sd %ebp, %xmm2
sqrtsd %xmm2, %xmm1
xorpd %xmm3, %xmm3
ucomisd %xmm3, %xmm2
movapd %xmm1, %xmm0
jae .LBB3_2
# %bb.1: # %call.sqrt
movapd %xmm2, %xmm0
movsd %xmm1, 8(%rsp) # 8-byte Spill
movsd %xmm2, 24(%rsp) # 8-byte Spill
callq sqrt
xorpd %xmm3, %xmm3
movsd 24(%rsp), %xmm2 # 8-byte Reload
# xmm2 = mem[0],zero
movsd 8(%rsp), %xmm1 # 8-byte Reload
# xmm1 = mem[0],zero
.LBB3_2: # %.split
cvtsi2sd %r13d, %xmm4
divsd %xmm4, %xmm0
cvttsd2si %xmm0, %r14d
orq %r12, %rbx
incl %r14d
ucomisd %xmm3, %xmm2
jae .LBB3_4
# %bb.3: # %call.sqrt18
movapd %xmm2, %xmm0
movsd %xmm4, 8(%rsp) # 8-byte Spill
callq sqrt
movsd 8(%rsp), %xmm4 # 8-byte Reload
# xmm4 = mem[0],zero
movapd %xmm0, %xmm1
.LBB3_4: # %.split.split
divsd %xmm4, %xmm1
cvttsd2si %xmm1, %r13d
incl %r13d
movl %r14d, %eax
shlq $32, %r13
orq %rax, %r13
callq clock
movq %r13, %rdi
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_6
# %bb.5:
movl %r15d, 20(%rsp)
movl %ebp, 16(%rsp)
movq 32(%rsp), %rax # 8-byte Reload
movq %rax, 104(%rsp)
movq 40(%rsp), %rax # 8-byte Reload
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 112(%rsp)
leaq 16(%rsp), %rax
movq %rax, 120(%rsp)
leaq 104(%rsp), %rax
movq %rax, 128(%rsp)
leaq 96(%rsp), %rax
movq %rax, 136(%rsp)
leaq 80(%rsp), %rdi
leaq 64(%rsp), %rsi
leaq 56(%rsp), %rdx
leaq 48(%rsp), %rcx
callq __hipPopCallConfiguration
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
movq 64(%rsp), %rcx
movl 72(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z40ImpositionBoundaryConditionNeumannKerneliiPiPd, %edi
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_6:
callq hipDeviceSynchronize
addq $152, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size ImpositionBoundaryConditionNeumann, .Lfunc_end3-ImpositionBoundaryConditionNeumann
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z33ImpositionBoundaryConditionKerneliiiPiPdS0_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z40ImpositionBoundaryConditionNeumannKerneliiPiPd, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z33ImpositionBoundaryConditionKerneliiiPiPdS0_,@object # @_Z33ImpositionBoundaryConditionKerneliiiPiPdS0_
.section .rodata,"a",@progbits
.globl _Z33ImpositionBoundaryConditionKerneliiiPiPdS0_
.p2align 3, 0x0
_Z33ImpositionBoundaryConditionKerneliiiPiPdS0_:
.quad _Z48__device_stub__ImpositionBoundaryConditionKerneliiiPiPdS0_
.size _Z33ImpositionBoundaryConditionKerneliiiPiPdS0_, 8
.type _Z40ImpositionBoundaryConditionNeumannKerneliiPiPd,@object # @_Z40ImpositionBoundaryConditionNeumannKerneliiPiPd
.globl _Z40ImpositionBoundaryConditionNeumannKerneliiPiPd
.p2align 3, 0x0
_Z40ImpositionBoundaryConditionNeumannKerneliiPiPd:
.quad _Z55__device_stub__ImpositionBoundaryConditionNeumannKerneliiPiPd
.size _Z40ImpositionBoundaryConditionNeumannKerneliiPiPd, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z33ImpositionBoundaryConditionKerneliiiPiPdS0_"
.size .L__unnamed_1, 48
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z40ImpositionBoundaryConditionNeumannKerneliiPiPd"
.size .L__unnamed_2, 51
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z48__device_stub__ImpositionBoundaryConditionKerneliiiPiPdS0_
.addrsig_sym _Z55__device_stub__ImpositionBoundaryConditionNeumannKerneliiPiPd
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z33ImpositionBoundaryConditionKerneliiiPiPdS0_
.addrsig_sym _Z40ImpositionBoundaryConditionNeumannKerneliiPiPd
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
#define NUM_THREAD 256 // Number of thread blocks
#define print(x) printf("%d",x)
float *matrixMul_float_serial(float vector1[], float vector2[], int size);
float *matrixMul_float_parallel(float vector1[], float vector2[], int size, int thread_count);
float *matrixMul_float_cuda(float* vector1, float* vector2, int num);
double *matrixMul_double_serial(double vector1[], double vector2[], int size);
double *matrixMul_double_parallel(double vector1[], double vector2[], int size, int thread_count);
double *matrixMul_double_cuda(double* vector1, double* vector2, int num);
double doubleGen();
float floatGen();
void operations(int size, int parallel, int serial, int cuda, int verify, int thread_count);
void print_results_float( int size, double time_spent);
void print_results_double( int size, double time_spent);
double verifyVectord(double *vector1, double *vector2, int size);
float verifyVectorf(float *vector1, float *vector2, int size);
__global__ void matMul_CUDA_float(float *sum, int size, float *vector1, float *vector2){
int idx = blockIdx.x*blockDim.x+threadIdx.x; // Sequential thread index across the blocks
int k;
if(idx < size*size){
for(k=0; k< size; k++){
sum[idx] += (*(vector1+(idx-(idx % size)+k))) * (*(vector2+(k*size+(idx % size))));
}
}
} | code for sm_80
Function : _Z17matMul_CUDA_floatPfiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ MOV R11, c[0x0][0x168] ; /* 0x00005a00000b7a02 */
/* 0x000fc60000000f00 */
/*0030*/ S2R R9, SR_TID.X ; /* 0x0000000000097919 */
/* 0x000e220000002100 */
/*0040*/ ISETP.GE.AND P0, PT, R11.reuse, 0x1, PT ; /* 0x000000010b00780c */
/* 0x040fe20003f06270 */
/*0050*/ IMAD R2, R11, c[0x0][0x168], RZ ; /* 0x00005a000b027a24 */
/* 0x000fe400078e02ff */
/*0060*/ IMAD R15, R0, c[0x0][0x0], R9 ; /* 0x00000000000f7a24 */
/* 0x001fca00078e0209 */
/*0070*/ ISETP.GE.OR P0, PT, R15, R2, !P0 ; /* 0x000000020f00720c */
/* 0x000fda0004706670 */
/*0080*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0090*/ IABS R5, c[0x0][0x168] ; /* 0x00005a0000057a13 */
/* 0x000fe20000000000 */
/*00a0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00b0*/ IABS R8, R15 ; /* 0x0000000f00087213 */
/* 0x000fe20000000000 */
/*00c0*/ HFMA2.MMA R14, -RZ, RZ, 0, 0 ; /* 0x00000000ff0e7435 */
/* 0x000fe200000001ff */
/*00d0*/ I2F.RP R4, R5 ; /* 0x0000000500047306 */
/* 0x000e220000209400 */
/*00e0*/ ISETP.GE.AND P1, PT, R15, RZ, PT ; /* 0x000000ff0f00720c */
/* 0x000fe40003f26270 */
/*00f0*/ MOV R13, 0x4 ; /* 0x00000004000d7802 */
/* 0x000fe40000000f00 */
/*0100*/ LOP3.LUT R10, R11, 0x3, RZ, 0xc0, !PT ; /* 0x000000030b0a7812 */
/* 0x000fc600078ec0ff */
/*0110*/ MUFU.RCP R4, R4 ; /* 0x0000000400047308 */
/* 0x001e240000001000 */
/*0120*/ IADD3 R2, R4, 0xffffffe, RZ ; /* 0x0ffffffe04027810 */
/* 0x001fcc0007ffe0ff */
/*0130*/ F2I.FTZ.U32.TRUNC.NTZ R3, R2 ; /* 0x0000000200037305 */
/* 0x000064000021f000 */
/*0140*/ HFMA2.MMA R2, -RZ, RZ, 0, 0 ; /* 0x00000000ff027435 */
/* 0x001fe200000001ff */
/*0150*/ IADD3 R6, RZ, -R3, RZ ; /* 0x80000003ff067210 */
/* 0x002fca0007ffe0ff */
/*0160*/ IMAD R7, R6, R5, RZ ; /* 0x0000000506077224 */
/* 0x000fc800078e02ff */
/*0170*/ IMAD.HI.U32 R3, R3, R7, R2 ; /* 0x0000000703037227 */
/* 0x000fe200078e0002 */
/*0180*/ IADD3 R2, R11, -0x1, RZ ; /* 0xffffffff0b027810 */
/* 0x000fca0007ffe0ff */
/*0190*/ IMAD.HI.U32 R3, R3, R8, RZ ; /* 0x0000000803037227 */
/* 0x000fca00078e00ff */
/*01a0*/ IADD3 R3, -R3, RZ, RZ ; /* 0x000000ff03037210 */
/* 0x000fca0007ffe1ff */
/*01b0*/ IMAD R8, R5, R3, R8 ; /* 0x0000000305087224 */
/* 0x000fca00078e0208 */
/*01c0*/ ISETP.GT.U32.AND P0, PT, R5, R8, PT ; /* 0x000000080500720c */
/* 0x000fda0003f04070 */
/*01d0*/ @!P0 IADD3 R8, R8, -R5, RZ ; /* 0x8000000508088210 */
/* 0x000fe40007ffe0ff */
/*01e0*/ ISETP.NE.AND P0, PT, RZ, c[0x0][0x168], PT ; /* 0x00005a00ff007a0c */
/* 0x000fe40003f05270 */
/*01f0*/ ISETP.GT.U32.AND P2, PT, R5, R8, PT ; /* 0x000000080500720c */
/* 0x000fda0003f44070 */
/*0200*/ @!P2 IADD3 R8, R8, -R5, RZ ; /* 0x800000050808a210 */
/* 0x000fe40007ffe0ff */
/*0210*/ ISETP.GE.U32.AND P2, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fe20003f46070 */
/*0220*/ IMAD.WIDE R2, R15, R13, c[0x0][0x160] ; /* 0x000058000f027625 */
/* 0x000fe200078e020d */
/*0230*/ @!P1 IADD3 R8, -R8, RZ, RZ ; /* 0x000000ff08089210 */
/* 0x000fe40007ffe1ff */
/*0240*/ @!P0 LOP3.LUT R8, RZ, c[0x0][0x168], RZ, 0x33, !PT ; /* 0x00005a00ff088a12 */
/* 0x000fd200078e33ff */
/*0250*/ @!P2 BRA 0xdc0 ; /* 0x00000b600000a947 */
/* 0x000fea0003800000 */
/*0260*/ IADD3 R12, -R10, c[0x0][0x168], RZ ; /* 0x00005a000a0c7a10 */
/* 0x000fe20007ffe1ff */
/*0270*/ LDG.E R17, [R2.64] ; /* 0x0000000402117981 */
/* 0x000162000c1e1900 */
/*0280*/ ULDC.64 UR6, c[0x0][0x170] ; /* 0x00005c0000067ab9 */
/* 0x000fe20000000a00 */
/*0290*/ IADD3 R15, R15, -R8, RZ ; /* 0x800000080f0f7210 */
/* 0x000fe20007ffe0ff */
/*02a0*/ IMAD.WIDE R4, R8, R13, c[0x0][0x178] ; /* 0x00005e0008047625 */
/* 0x000fe200078e020d */
/*02b0*/ ISETP.GT.AND P0, PT, R12, RZ, PT ; /* 0x000000ff0c00720c */
/* 0x000fe40003f04270 */
/*02c0*/ MOV R14, RZ ; /* 0x000000ff000e7202 */
/* 0x000fd60000000f00 */
/*02d0*/ @!P0 BRA 0xbf0 ; /* 0x0000091000008947 */
/* 0x001fea0003800000 */
/*02e0*/ ISETP.GT.AND P1, PT, R12, 0xc, PT ; /* 0x0000000c0c00780c */
/* 0x000fe40003f24270 */
/*02f0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*0300*/ @!P1 BRA 0x8b0 ; /* 0x000005a000009947 */
/* 0x000fea0003800000 */
/*0310*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0320*/ MOV R6, UR6 ; /* 0x0000000600067c02 */
/* 0x000fe20008000f00 */
/*0330*/ LDG.E R16, [R4.64] ; /* 0x0000000404107981 */
/* 0x004ea2000c1e1900 */
/*0340*/ MOV R7, UR7 ; /* 0x0000000700077c02 */
/* 0x000fca0008000f00 */
/*0350*/ IMAD.WIDE R6, R15, 0x4, R6 ; /* 0x000000040f067825 */
/* 0x000fca00078e0206 */
/*0360*/ LDG.E R18, [R6.64] ; /* 0x0000000406127981 */
/* 0x000ea4000c1e1900 */
/*0370*/ FFMA R21, R16, R18, R17 ; /* 0x0000001210157223 */
/* 0x024fe40000000011 */
/*0380*/ IMAD.WIDE R16, R11, 0x4, R4 ; /* 0x000000040b107825 */
/* 0x000fc600078e0204 */
/*0390*/ STG.E [R2.64], R21 ; /* 0x0000001502007986 */
/* 0x0001e8000c101904 */
/*03a0*/ LDG.E R18, [R16.64] ; /* 0x0000000410127981 */
/* 0x000ea8000c1e1900 */
/*03b0*/ LDG.E R19, [R6.64+0x4] ; /* 0x0000040406137981 */
/* 0x000ea4000c1e1900 */
/*03c0*/ FFMA R23, R18, R19, R21 ; /* 0x0000001312177223 */
/* 0x004fc40000000015 */
/*03d0*/ IMAD.WIDE R18, R11, 0x4, R16 ; /* 0x000000040b127825 */
/* 0x000fc600078e0210 */
/*03e0*/ STG.E [R2.64], R23 ; /* 0x0000001702007986 */
/* 0x0003e8000c101904 */
/*03f0*/ LDG.E R20, [R18.64] ; /* 0x0000000412147981 */
/* 0x000ea8000c1e1900 */
/*0400*/ LDG.E R4, [R6.64+0x8] ; /* 0x0000080406047981 */
/* 0x000ea4000c1e1900 */
/*0410*/ FFMA R25, R20, R4, R23 ; /* 0x0000000414197223 */
/* 0x004fc40000000017 */
/*0420*/ IMAD.WIDE R4, R11, 0x4, R18 ; /* 0x000000040b047825 */
/* 0x000fc600078e0212 */
/*0430*/ STG.E [R2.64], R25 ; /* 0x0000001902007986 */
/* 0x0005e8000c101904 */
/*0440*/ LDG.E R20, [R4.64] ; /* 0x0000000404147981 */
/* 0x000e28000c1e1900 */
/*0450*/ LDG.E R16, [R6.64+0xc] ; /* 0x00000c0406107981 */
/* 0x000e24000c1e1900 */
/*0460*/ FFMA R21, R20, R16, R25 ; /* 0x0000001014157223 */
/* 0x001fc40000000019 */
/*0470*/ IMAD.WIDE R16, R11, 0x4, R4 ; /* 0x000000040b107825 */
/* 0x000fc600078e0204 */
/*0480*/ STG.E [R2.64], R21 ; /* 0x0000001502007986 */
/* 0x0001e8000c101904 */
/*0490*/ LDG.E R20, [R16.64] ; /* 0x0000000410147981 */
/* 0x000e68000c1e1900 */
/*04a0*/ LDG.E R18, [R6.64+0x10] ; /* 0x0000100406127981 */
/* 0x000e64000c1e1900 */
/*04b0*/ FFMA R23, R20, R18, R21 ; /* 0x0000001214177223 */
/* 0x002fc40000000015 */
/*04c0*/ IMAD.WIDE R18, R11, 0x4, R16 ; /* 0x000000040b127825 */
/* 0x000fc600078e0210 */
/*04d0*/ STG.E [R2.64], R23 ; /* 0x0000001702007986 */
/* 0x0003e8000c101904 */
/*04e0*/ LDG.E R20, [R18.64] ; /* 0x0000000412147981 */
/* 0x000ea8000c1e1900 */
/*04f0*/ LDG.E R4, [R6.64+0x14] ; /* 0x0000140406047981 */
/* 0x000ea4000c1e1900 */
/*0500*/ FFMA R25, R20, R4, R23 ; /* 0x0000000414197223 */
/* 0x004fc40000000017 */
/*0510*/ IMAD.WIDE R4, R11, 0x4, R18 ; /* 0x000000040b047825 */
/* 0x000fc600078e0212 */
/*0520*/ STG.E [R2.64], R25 ; /* 0x0000001902007986 */
/* 0x0005e8000c101904 */
/*0530*/ LDG.E R20, [R4.64] ; /* 0x0000000404147981 */
/* 0x000e28000c1e1900 */
/*0540*/ LDG.E R16, [R6.64+0x18] ; /* 0x0000180406107981 */
/* 0x000e24000c1e1900 */
/*0550*/ FFMA R21, R20, R16, R25 ; /* 0x0000001014157223 */
/* 0x001fc40000000019 */
/*0560*/ IMAD.WIDE R16, R11, 0x4, R4 ; /* 0x000000040b107825 */
/* 0x000fc600078e0204 */
/*0570*/ STG.E [R2.64], R21 ; /* 0x0000001502007986 */
/* 0x0001e8000c101904 */
/*0580*/ LDG.E R20, [R16.64] ; /* 0x0000000410147981 */
/* 0x000e68000c1e1900 */
/*0590*/ LDG.E R18, [R6.64+0x1c] ; /* 0x00001c0406127981 */
/* 0x000e64000c1e1900 */
/*05a0*/ FFMA R23, R20, R18, R21 ; /* 0x0000001214177223 */
/* 0x002fc40000000015 */
/*05b0*/ IMAD.WIDE R18, R11, 0x4, R16 ; /* 0x000000040b127825 */
/* 0x000fc600078e0210 */
/*05c0*/ STG.E [R2.64], R23 ; /* 0x0000001702007986 */
/* 0x0003e8000c101904 */
/*05d0*/ LDG.E R20, [R18.64] ; /* 0x0000000412147981 */
/* 0x000ea8000c1e1900 */
/*05e0*/ LDG.E R4, [R6.64+0x20] ; /* 0x0000200406047981 */
/* 0x000ea4000c1e1900 */
/*05f0*/ FFMA R25, R20, R4, R23 ; /* 0x0000000414197223 */
/* 0x004fc40000000017 */
/*0600*/ IMAD.WIDE R4, R11, 0x4, R18 ; /* 0x000000040b047825 */
/* 0x000fc600078e0212 */
/*0610*/ STG.E [R2.64], R25 ; /* 0x0000001902007986 */
/* 0x0005e8000c101904 */
/*0620*/ LDG.E R20, [R4.64] ; /* 0x0000000404147981 */
/* 0x000e28000c1e1900 */
/*0630*/ LDG.E R16, [R6.64+0x24] ; /* 0x0000240406107981 */
/* 0x000e24000c1e1900 */
/*0640*/ FFMA R21, R20, R16, R25 ; /* 0x0000001014157223 */
/* 0x001fc40000000019 */
/*0650*/ IMAD.WIDE R16, R11, 0x4, R4 ; /* 0x000000040b107825 */
/* 0x000fc600078e0204 */
/*0660*/ STG.E [R2.64], R21 ; /* 0x0000001502007986 */
/* 0x000fe8000c101904 */
/*0670*/ LDG.E R20, [R16.64] ; /* 0x0000000410147981 */
/* 0x000e68000c1e1900 */
/*0680*/ LDG.E R18, [R6.64+0x28] ; /* 0x0000280406127981 */
/* 0x000e64000c1e1900 */
/*0690*/ FFMA R23, R20, R18, R21 ; /* 0x0000001214177223 */
/* 0x002fc40000000015 */
/*06a0*/ IMAD.WIDE R18, R11, 0x4, R16 ; /* 0x000000040b127825 */
/* 0x000fc600078e0210 */
/*06b0*/ STG.E [R2.64], R23 ; /* 0x0000001702007986 */
/* 0x0001e8000c101904 */
/*06c0*/ LDG.E R20, [R18.64] ; /* 0x0000000412147981 */
/* 0x000ea8000c1e1900 */
/*06d0*/ LDG.E R4, [R6.64+0x2c] ; /* 0x00002c0406047981 */
/* 0x000ea4000c1e1900 */
/*06e0*/ FFMA R25, R20, R4, R23 ; /* 0x0000000414197223 */
/* 0x004fc40000000017 */
/*06f0*/ IMAD.WIDE R4, R11, 0x4, R18 ; /* 0x000000040b047825 */
/* 0x000fc600078e0212 */
/*0700*/ STG.E [R2.64], R25 ; /* 0x0000001902007986 */
/* 0x0003e8000c101904 */
/*0710*/ LDG.E R20, [R4.64] ; /* 0x0000000404147981 */
/* 0x000ea8000c1e1900 */
/*0720*/ LDG.E R16, [R6.64+0x30] ; /* 0x0000300406107981 */
/* 0x000ea4000c1e1900 */
/*0730*/ FFMA R27, R20, R16, R25 ; /* 0x00000010141b7223 */
/* 0x004fc40000000019 */
/*0740*/ IMAD.WIDE R16, R11, 0x4, R4 ; /* 0x000000040b107825 */
/* 0x000fc600078e0204 */
/*0750*/ STG.E [R2.64], R27 ; /* 0x0000001b02007986 */
/* 0x0005e8000c101904 */
/*0760*/ LDG.E R20, [R16.64] ; /* 0x0000000410147981 */
/* 0x000e28000c1e1900 */
/*0770*/ LDG.E R18, [R6.64+0x34] ; /* 0x0000340406127981 */
/* 0x000e24000c1e1900 */
/*0780*/ FFMA R23, R20, R18, R27 ; /* 0x0000001214177223 */
/* 0x001fc4000000001b */
/*0790*/ IMAD.WIDE R18, R11, 0x4, R16 ; /* 0x000000040b127825 */
/* 0x000fc600078e0210 */
/*07a0*/ STG.E [R2.64], R23 ; /* 0x0000001702007986 */
/* 0x0005e8000c101904 */
/*07b0*/ LDG.E R20, [R18.64] ; /* 0x0000000412147981 */
/* 0x000e68000c1e1900 */
/*07c0*/ LDG.E R4, [R6.64+0x38] ; /* 0x0000380406047981 */
/* 0x000e62000c1e1900 */
/*07d0*/ IADD3 R12, R12, -0x10, RZ ; /* 0xfffffff00c0c7810 */
/* 0x000fe20007ffe0ff */
/*07e0*/ FFMA R25, R20, R4, R23 ; /* 0x0000000414197223 */
/* 0x002fc40000000017 */
/*07f0*/ IMAD.WIDE R20, R11, 0x4, R18 ; /* 0x000000040b147825 */
/* 0x000fc600078e0212 */
/*0800*/ STG.E [R2.64], R25 ; /* 0x0000001902007986 */
/* 0x0005e8000c101904 */
/*0810*/ LDG.E R5, [R6.64+0x3c] ; /* 0x00003c0406057981 */
/* 0x000ee8000c1e1900 */
/*0820*/ LDG.E R4, [R20.64] ; /* 0x0000000414047981 */
/* 0x000ee2000c1e1900 */
/*0830*/ ISETP.GT.AND P1, PT, R12, 0xc, PT ; /* 0x0000000c0c00780c */
/* 0x000fe20003f24270 */
/*0840*/ UIADD3 UR6, UP0, UR6, 0x40, URZ ; /* 0x0000004006067890 */
/* 0x000fe2000ff1e03f */
/*0850*/ IADD3 R14, R14, 0x10, RZ ; /* 0x000000100e0e7810 */
/* 0x000fc60007ffe0ff */
/*0860*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0870*/ FFMA R17, R4, R5, R25 ; /* 0x0000000504117223 */
/* 0x008fe40000000019 */
/*0880*/ IMAD.WIDE R4, R11, 0x4, R20 ; /* 0x000000040b047825 */
/* 0x000fc600078e0214 */
/*0890*/ STG.E [R2.64], R17 ; /* 0x0000001102007986 */
/* 0x0005e4000c101904 */
/*08a0*/ @P1 BRA 0x320 ; /* 0xfffffa7000001947 */
/* 0x000fea000383ffff */
/*08b0*/ ISETP.GT.AND P1, PT, R12, 0x4, PT ; /* 0x000000040c00780c */
/* 0x000fda0003f24270 */
/*08c0*/ @!P1 BRA 0xbd0 ; /* 0x0000030000009947 */
/* 0x000fea0003800000 */
/*08d0*/ MOV R6, UR6 ; /* 0x0000000600067c02 */
/* 0x000fe20008000f00 */
/*08e0*/ LDG.E R16, [R4.64] ; /* 0x0000000404107981 */
/* 0x000ee2000c1e1900 */
/*08f0*/ MOV R7, UR7 ; /* 0x0000000700077c02 */
/* 0x000fca0008000f00 */
/*0900*/ IMAD.WIDE R6, R15, 0x4, R6 ; /* 0x000000040f067825 */
/* 0x000fca00078e0206 */
/*0910*/ LDG.E R18, [R6.64] ; /* 0x0000000406127981 */
/* 0x000ee4000c1e1900 */
/*0920*/ FFMA R21, R16, R18, R17 ; /* 0x0000001210157223 */
/* 0x028fe40000000011 */
/*0930*/ IMAD.WIDE R16, R11, 0x4, R4 ; /* 0x000000040b107825 */
/* 0x004fc600078e0204 */
/*0940*/ STG.E [R2.64], R21 ; /* 0x0000001502007986 */
/* 0x0001e8000c101904 */
/*0950*/ LDG.E R18, [R16.64] ; /* 0x0000000410127981 */
/* 0x000ea8000c1e1900 */
/*0960*/ LDG.E R19, [R6.64+0x4] ; /* 0x0000040406137981 */
/* 0x000ea4000c1e1900 */
/*0970*/ FFMA R23, R18, R19, R21 ; /* 0x0000001312177223 */
/* 0x004fc40000000015 */
/*0980*/ IMAD.WIDE R18, R11, 0x4, R16 ; /* 0x000000040b127825 */
/* 0x000fc600078e0210 */
/*0990*/ STG.E [R2.64], R23 ; /* 0x0000001702007986 */
/* 0x0003e8000c101904 */
/*09a0*/ LDG.E R20, [R18.64] ; /* 0x0000000412147981 */
/* 0x000ea8000c1e1900 */
/*09b0*/ LDG.E R4, [R6.64+0x8] ; /* 0x0000080406047981 */
/* 0x000ea4000c1e1900 */
/*09c0*/ FFMA R25, R20, R4, R23 ; /* 0x0000000414197223 */
/* 0x004fc40000000017 */
/*09d0*/ IMAD.WIDE R4, R11, 0x4, R18 ; /* 0x000000040b047825 */
/* 0x000fc600078e0212 */
/*09e0*/ STG.E [R2.64], R25 ; /* 0x0000001902007986 */
/* 0x0005e8000c101904 */
/*09f0*/ LDG.E R20, [R4.64] ; /* 0x0000000404147981 */
/* 0x000e28000c1e1900 */
/*0a00*/ LDG.E R16, [R6.64+0xc] ; /* 0x00000c0406107981 */
/* 0x000e24000c1e1900 */
/*0a10*/ FFMA R21, R20, R16, R25 ; /* 0x0000001014157223 */
/* 0x001fc40000000019 */
/*0a20*/ IMAD.WIDE R16, R11, 0x4, R4 ; /* 0x000000040b107825 */
/* 0x000fc600078e0204 */
/*0a30*/ STG.E [R2.64], R21 ; /* 0x0000001502007986 */
/* 0x0001e8000c101904 */
/*0a40*/ LDG.E R20, [R16.64] ; /* 0x0000000410147981 */
/* 0x000e68000c1e1900 */
/*0a50*/ LDG.E R18, [R6.64+0x10] ; /* 0x0000100406127981 */
/* 0x000e64000c1e1900 */
/*0a60*/ FFMA R23, R20, R18, R21 ; /* 0x0000001214177223 */
/* 0x002fc40000000015 */
/*0a70*/ IMAD.WIDE R18, R11, 0x4, R16 ; /* 0x000000040b127825 */
/* 0x000fc600078e0210 */
/*0a80*/ STG.E [R2.64], R23 ; /* 0x0000001702007986 */
/* 0x0003e8000c101904 */
/*0a90*/ LDG.E R20, [R18.64] ; /* 0x0000000412147981 */
/* 0x000ea8000c1e1900 */
/*0aa0*/ LDG.E R4, [R6.64+0x14] ; /* 0x0000140406047981 */
/* 0x000ea4000c1e1900 */
/*0ab0*/ FFMA R25, R20, R4, R23 ; /* 0x0000000414197223 */
/* 0x004fc40000000017 */
/*0ac0*/ IMAD.WIDE R4, R11, 0x4, R18 ; /* 0x000000040b047825 */
/* 0x000fc600078e0212 */
/*0ad0*/ STG.E [R2.64], R25 ; /* 0x0000001902007986 */
/* 0x0003e8000c101904 */
/*0ae0*/ LDG.E R20, [R4.64] ; /* 0x0000000404147981 */
/* 0x000ea8000c1e1900 */
/*0af0*/ LDG.E R16, [R6.64+0x18] ; /* 0x0000180406107981 */
/* 0x000ea4000c1e1900 */
/*0b00*/ FFMA R27, R20, R16, R25 ; /* 0x00000010141b7223 */
/* 0x004fc40000000019 */
/*0b10*/ IMAD.WIDE R20, R11, 0x4, R4 ; /* 0x000000040b147825 */
/* 0x001fc600078e0204 */
/*0b20*/ STG.E [R2.64], R27 ; /* 0x0000001b02007986 */
/* 0x0003e8000c101904 */
/*0b30*/ LDG.E R17, [R6.64+0x1c] ; /* 0x00001c0406117981 */
/* 0x000ea8000c1e1900 */
/*0b40*/ LDG.E R16, [R20.64] ; /* 0x0000000414107981 */
/* 0x000ea2000c1e1900 */
/*0b50*/ UIADD3 UR6, UP0, UR6, 0x20, URZ ; /* 0x0000002006067890 */
/* 0x000fe2000ff1e03f */
/*0b60*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe20003f0e170 */
/*0b70*/ IMAD.WIDE R4, R11, 0x4, R20 ; /* 0x000000040b047825 */
/* 0x000fe200078e0214 */
/*0b80*/ IADD3 R14, R14, 0x8, RZ ; /* 0x000000080e0e7810 */
/* 0x000fc40007ffe0ff */
/*0b90*/ IADD3 R12, R12, -0x8, RZ ; /* 0xfffffff80c0c7810 */
/* 0x000fe20007ffe0ff */
/*0ba0*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0bb0*/ FFMA R17, R16, R17, R27 ; /* 0x0000001110117223 */
/* 0x004fca000000001b */
/*0bc0*/ STG.E [R2.64], R17 ; /* 0x0000001102007986 */
/* 0x0003e8000c101904 */
/*0bd0*/ ISETP.NE.OR P0, PT, R12, RZ, P0 ; /* 0x000000ff0c00720c */
/* 0x000fda0000705670 */
/*0be0*/ @!P0 BRA 0xdc0 ; /* 0x000001d000008947 */
/* 0x000fea0003800000 */
/*0bf0*/ MOV R6, UR6 ; /* 0x0000000600067c02 */
/* 0x000fe20008000f00 */
/*0c00*/ LDG.E R16, [R4.64] ; /* 0x0000000404107981 */
/* 0x000ee2000c1e1900 */
/*0c10*/ MOV R7, UR7 ; /* 0x0000000700077c02 */
/* 0x000fca0008000f00 */
/*0c20*/ IMAD.WIDE R6, R15, 0x4, R6 ; /* 0x000000040f067825 */
/* 0x000fca00078e0206 */
/*0c30*/ LDG.E R18, [R6.64] ; /* 0x0000000406127981 */
/* 0x000ee4000c1e1900 */
/*0c40*/ FFMA R23, R16, R18, R17 ; /* 0x0000001210177223 */
/* 0x02efe40000000011 */
/*0c50*/ IMAD.WIDE R16, R11, 0x4, R4 ; /* 0x000000040b107825 */
/* 0x000fc600078e0204 */
/*0c60*/ STG.E [R2.64], R23 ; /* 0x0000001702007986 */
/* 0x0001e8000c101904 */
/*0c70*/ LDG.E R18, [R16.64] ; /* 0x0000000410127981 */
/* 0x000ea8000c1e1900 */
/*0c80*/ LDG.E R19, [R6.64+0x4] ; /* 0x0000040406137981 */
/* 0x000ea4000c1e1900 */
/*0c90*/ FFMA R25, R18, R19, R23 ; /* 0x0000001312197223 */
/* 0x004fc40000000017 */
/*0ca0*/ IMAD.WIDE R18, R11, 0x4, R16 ; /* 0x000000040b127825 */
/* 0x000fc600078e0210 */
/*0cb0*/ STG.E [R2.64], R25 ; /* 0x0000001902007986 */
/* 0x0001e8000c101904 */
/*0cc0*/ LDG.E R20, [R18.64] ; /* 0x0000000412147981 */
/* 0x000ea8000c1e1900 */
/*0cd0*/ LDG.E R4, [R6.64+0x8] ; /* 0x0000080406047981 */
/* 0x000ea2000c1e1900 */
/*0ce0*/ IADD3 R12, R12, -0x4, RZ ; /* 0xfffffffc0c0c7810 */
/* 0x000fe20007ffe0ff */
/*0cf0*/ FFMA R27, R20, R4, R25 ; /* 0x00000004141b7223 */
/* 0x004fc40000000019 */
/*0d00*/ IMAD.WIDE R20, R11, 0x4, R18 ; /* 0x000000040b147825 */
/* 0x000fc600078e0212 */
/*0d10*/ STG.E [R2.64], R27 ; /* 0x0000001b02007986 */
/* 0x0001e8000c101904 */
/*0d20*/ LDG.E R5, [R6.64+0xc] ; /* 0x00000c0406057981 */
/* 0x000ea8000c1e1900 */
/*0d30*/ LDG.E R4, [R20.64] ; /* 0x0000000414047981 */
/* 0x000ea2000c1e1900 */
/*0d40*/ ISETP.NE.AND P0, PT, R12, RZ, PT ; /* 0x000000ff0c00720c */
/* 0x000fe20003f05270 */
/*0d50*/ UIADD3 UR6, UP0, UR6, 0x10, URZ ; /* 0x0000001006067890 */
/* 0x000fe2000ff1e03f */
/*0d60*/ IADD3 R14, R14, 0x4, RZ ; /* 0x000000040e0e7810 */
/* 0x000fc60007ffe0ff */
/*0d70*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0d80*/ FFMA R17, R4, R5, R27 ; /* 0x0000000504117223 */
/* 0x004fe4000000001b */
/*0d90*/ IMAD.WIDE R4, R11, 0x4, R20 ; /* 0x000000040b047825 */
/* 0x000fc600078e0214 */
/*0da0*/ STG.E [R2.64], R17 ; /* 0x0000001102007986 */
/* 0x0001e4000c101904 */
/*0db0*/ @P0 BRA 0xbf0 ; /* 0xfffffe3000000947 */
/* 0x001fea000383ffff */
/*0dc0*/ ISETP.NE.AND P0, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fda0003f05270 */
/*0dd0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0de0*/ LDG.E R15, [R2.64] ; /* 0x00000004020f7981 */
/* 0x000162000c1e1900 */
/*0df0*/ IADD3 R9, R9, R14, RZ ; /* 0x0000000e09097210 */
/* 0x000fca0007ffe0ff */
/*0e00*/ IMAD R9, R0, c[0x0][0x0], R9 ; /* 0x0000000000097a24 */
/* 0x000fca00078e0209 */
/*0e10*/ IADD3 R4, -R8, R9, RZ ; /* 0x0000000908047210 */
/* 0x000fe20007ffe1ff */
/*0e20*/ IMAD R8, R14, c[0x0][0x168], R8 ; /* 0x00005a000e087a24 */
/* 0x000fc800078e0208 */
/*0e30*/ IMAD.WIDE R4, R4, R13, c[0x0][0x170] ; /* 0x00005c0004047625 */
/* 0x000fca00078e020d */
/*0e40*/ MOV R9, R4 ; /* 0x0000000400097202 */
/* 0x000fe40000000f00 */
/*0e50*/ MOV R12, R5 ; /* 0x00000005000c7202 */
/* 0x000fe20000000f00 */
/*0e60*/ IMAD.WIDE R4, R8, R13, c[0x0][0x178] ; /* 0x00005e0008047625 */
/* 0x001fc800078e020d */
/*0e70*/ MOV R6, R9 ; /* 0x0000000900067202 */
/* 0x000fe20000000f00 */
/*0e80*/ LDG.E R0, [R4.64] ; /* 0x0000000404007981 */
/* 0x0010e2000c1e1900 */
/*0e90*/ MOV R7, R12 ; /* 0x0000000c00077202 */
/* 0x000fca0000000f00 */
/*0ea0*/ LDG.E R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000ee2000c1e1900 */
/*0eb0*/ IADD3 R10, R10, -0x1, RZ ; /* 0xffffffff0a0a7810 */
/* 0x000fe40007ffe0ff */
/*0ec0*/ IADD3 R9, P1, R9, 0x4, RZ ; /* 0x0000000409097810 */
/* 0x000fe20007f3e0ff */
/*0ed0*/ IMAD.WIDE R4, R11, 0x4, R4 ; /* 0x000000040b047825 */
/* 0x001fe200078e0204 */
/*0ee0*/ ISETP.NE.AND P0, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fe40003f05270 */
/*0ef0*/ IADD3.X R12, RZ, R12, RZ, P1, !PT ; /* 0x0000000cff0c7210 */
/* 0x000fe20000ffe4ff */
/*0f00*/ FFMA R15, R0, R6, R15 ; /* 0x00000006000f7223 */
/* 0x028fca000000000f */
/*0f10*/ STG.E [R2.64], R15 ; /* 0x0000000f02007986 */
/* 0x0001ea000c101904 */
/*0f20*/ @P0 BRA 0xe70 ; /* 0xffffff4000000947 */
/* 0x000fea000383ffff */
/*0f30*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0f40*/ BRA 0xf40; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0f50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0fa0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0fb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0fc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0fd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0fe0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ff0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
#define NUM_THREAD 256 // Number of thread blocks
#define print(x) printf("%d",x)
float *matrixMul_float_serial(float vector1[], float vector2[], int size);
float *matrixMul_float_parallel(float vector1[], float vector2[], int size, int thread_count);
float *matrixMul_float_cuda(float* vector1, float* vector2, int num);
double *matrixMul_double_serial(double vector1[], double vector2[], int size);
double *matrixMul_double_parallel(double vector1[], double vector2[], int size, int thread_count);
double *matrixMul_double_cuda(double* vector1, double* vector2, int num);
double doubleGen();
float floatGen();
void operations(int size, int parallel, int serial, int cuda, int verify, int thread_count);
void print_results_float( int size, double time_spent);
void print_results_double( int size, double time_spent);
double verifyVectord(double *vector1, double *vector2, int size);
float verifyVectorf(float *vector1, float *vector2, int size);
__global__ void matMul_CUDA_float(float *sum, int size, float *vector1, float *vector2){
int idx = blockIdx.x*blockDim.x+threadIdx.x; // Sequential thread index across the blocks
int k;
if(idx < size*size){
for(k=0; k< size; k++){
sum[idx] += (*(vector1+(idx-(idx % size)+k))) * (*(vector2+(k*size+(idx % size))));
}
}
} | .file "tmpxft_000ab2fa_00000000-6_matMul_CUDA_float.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z42__device_stub__Z17matMul_CUDA_floatPfiS_S_PfiS_S_
.type _Z42__device_stub__Z17matMul_CUDA_floatPfiS_S_PfiS_S_, @function
_Z42__device_stub__Z17matMul_CUDA_floatPfiS_S_PfiS_S_:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movq %rdx, 8(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z17matMul_CUDA_floatPfiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z42__device_stub__Z17matMul_CUDA_floatPfiS_S_PfiS_S_, .-_Z42__device_stub__Z17matMul_CUDA_floatPfiS_S_PfiS_S_
.globl _Z17matMul_CUDA_floatPfiS_S_
.type _Z17matMul_CUDA_floatPfiS_S_, @function
_Z17matMul_CUDA_floatPfiS_S_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z42__device_stub__Z17matMul_CUDA_floatPfiS_S_PfiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z17matMul_CUDA_floatPfiS_S_, .-_Z17matMul_CUDA_floatPfiS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z17matMul_CUDA_floatPfiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z17matMul_CUDA_floatPfiS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
#define NUM_THREAD 256 // Number of thread blocks
#define print(x) printf("%d",x)
float *matrixMul_float_serial(float vector1[], float vector2[], int size);
float *matrixMul_float_parallel(float vector1[], float vector2[], int size, int thread_count);
float *matrixMul_float_cuda(float* vector1, float* vector2, int num);
double *matrixMul_double_serial(double vector1[], double vector2[], int size);
double *matrixMul_double_parallel(double vector1[], double vector2[], int size, int thread_count);
double *matrixMul_double_cuda(double* vector1, double* vector2, int num);
double doubleGen();
float floatGen();
void operations(int size, int parallel, int serial, int cuda, int verify, int thread_count);
void print_results_float( int size, double time_spent);
void print_results_double( int size, double time_spent);
double verifyVectord(double *vector1, double *vector2, int size);
float verifyVectorf(float *vector1, float *vector2, int size);
__global__ void matMul_CUDA_float(float *sum, int size, float *vector1, float *vector2){
int idx = blockIdx.x*blockDim.x+threadIdx.x; // Sequential thread index across the blocks
int k;
if(idx < size*size){
for(k=0; k< size; k++){
sum[idx] += (*(vector1+(idx-(idx % size)+k))) * (*(vector2+(k*size+(idx % size))));
}
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
#define NUM_THREAD 256 // Number of thread blocks
#define print(x) printf("%d",x)
float *matrixMul_float_serial(float vector1[], float vector2[], int size);
float *matrixMul_float_parallel(float vector1[], float vector2[], int size, int thread_count);
float *matrixMul_float_cuda(float* vector1, float* vector2, int num);
double *matrixMul_double_serial(double vector1[], double vector2[], int size);
double *matrixMul_double_parallel(double vector1[], double vector2[], int size, int thread_count);
double *matrixMul_double_cuda(double* vector1, double* vector2, int num);
double doubleGen();
float floatGen();
void operations(int size, int parallel, int serial, int cuda, int verify, int thread_count);
void print_results_float( int size, double time_spent);
void print_results_double( int size, double time_spent);
double verifyVectord(double *vector1, double *vector2, int size);
float verifyVectorf(float *vector1, float *vector2, int size);
__global__ void matMul_CUDA_float(float *sum, int size, float *vector1, float *vector2){
int idx = blockIdx.x*blockDim.x+threadIdx.x; // Sequential thread index across the blocks
int k;
if(idx < size*size){
for(k=0; k< size; k++){
sum[idx] += (*(vector1+(idx-(idx % size)+k))) * (*(vector2+(k*size+(idx % size))));
}
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
#define NUM_THREAD 256 // Number of thread blocks
#define print(x) printf("%d",x)
float *matrixMul_float_serial(float vector1[], float vector2[], int size);
float *matrixMul_float_parallel(float vector1[], float vector2[], int size, int thread_count);
float *matrixMul_float_cuda(float* vector1, float* vector2, int num);
double *matrixMul_double_serial(double vector1[], double vector2[], int size);
double *matrixMul_double_parallel(double vector1[], double vector2[], int size, int thread_count);
double *matrixMul_double_cuda(double* vector1, double* vector2, int num);
double doubleGen();
float floatGen();
void operations(int size, int parallel, int serial, int cuda, int verify, int thread_count);
void print_results_float( int size, double time_spent);
void print_results_double( int size, double time_spent);
double verifyVectord(double *vector1, double *vector2, int size);
float verifyVectorf(float *vector1, float *vector2, int size);
__global__ void matMul_CUDA_float(float *sum, int size, float *vector1, float *vector2){
int idx = blockIdx.x*blockDim.x+threadIdx.x; // Sequential thread index across the blocks
int k;
if(idx < size*size){
for(k=0; k< size; k++){
sum[idx] += (*(vector1+(idx-(idx % size)+k))) * (*(vector2+(k*size+(idx % size))));
}
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z17matMul_CUDA_floatPfiS_S_
.globl _Z17matMul_CUDA_floatPfiS_S_
.p2align 8
.type _Z17matMul_CUDA_floatPfiS_S_,@function
_Z17matMul_CUDA_floatPfiS_S_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s4, s[0:1], 0x8
s_mov_b32 s5, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_cmp_gt_i32 s4, 0
s_mul_i32 s15, s15, s2
s_mul_i32 s2, s4, s4
v_add_nc_u32_e32 v3, s15, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_gt_i32_e32 vcc_lo, s2, v3
s_cselect_b32 s2, -1, 0
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_3
s_load_b64 s[6:7], s[0:1], 0x0
v_ashrrev_i32_e32 v4, 31, v3
v_ashrrev_i32_e32 v7, 31, v3
s_load_b128 s[0:3], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[1:2], 2, v[3:4]
v_add3_u32 v0, v0, v7, s15
v_add_nc_u32_e32 v3, v3, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_xor_b32_e32 v3, v3, v7
s_waitcnt lgkmcnt(0)
v_add_co_u32 v1, vcc_lo, s6, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s7, v2, vcc_lo
s_ashr_i32 s6, s4, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
s_add_i32 s7, s4, s6
global_load_b32 v5, v[1:2], off
s_xor_b32 s6, s7, s6
v_cvt_f32_u32_e32 v4, s6
s_sub_i32 s7, 0, s6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v4, v4
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v4, 0x4f7ffffe, v4
v_cvt_u32_f32_e32 v4, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v6, s7, v4
v_mul_hi_u32 v6, v4, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v4, v4, v6
v_mul_hi_u32 v4, v3, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v4, v4, s6
v_sub_nc_u32_e32 v3, v3, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v4, s6, v3
v_cmp_le_u32_e32 vcc_lo, s6, v3
v_cndmask_b32_e32 v3, v3, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v4, s6, v3
v_cmp_le_u32_e32 vcc_lo, s6, v3
v_cndmask_b32_e32 v3, v3, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_xor_b32_e32 v4, v3, v7
v_sub_nc_u32_e32 v3, v4, v7
v_sub_nc_u32_e32 v0, v0, v4
.p2align 6
.LBB0_2:
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_nc_u32_e32 v6, s5, v0
v_ashrrev_i32_e32 v4, 31, v3
s_add_i32 s5, s5, 1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
s_cmp_lg_u32 s4, s5
v_ashrrev_i32_e32 v7, 31, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[8:9], 2, v[3:4]
v_add_nc_u32_e32 v3, s4, v3
v_lshlrev_b64 v[6:7], 2, v[6:7]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v8, vcc_lo, s2, v8
v_add_co_ci_u32_e32 v9, vcc_lo, s3, v9, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v6, vcc_lo, s0, v6
v_add_co_ci_u32_e32 v7, vcc_lo, s1, v7, vcc_lo
global_load_b32 v4, v[8:9], off
global_load_b32 v6, v[6:7], off
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v5, v6, v4
global_store_b32 v[1:2], v5, off
s_cbranch_scc1 .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z17matMul_CUDA_floatPfiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 10
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z17matMul_CUDA_floatPfiS_S_, .Lfunc_end0-_Z17matMul_CUDA_floatPfiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z17matMul_CUDA_floatPfiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z17matMul_CUDA_floatPfiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 10
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
#define NUM_THREAD 256 // Number of thread blocks
#define print(x) printf("%d",x)
float *matrixMul_float_serial(float vector1[], float vector2[], int size);
float *matrixMul_float_parallel(float vector1[], float vector2[], int size, int thread_count);
float *matrixMul_float_cuda(float* vector1, float* vector2, int num);
double *matrixMul_double_serial(double vector1[], double vector2[], int size);
double *matrixMul_double_parallel(double vector1[], double vector2[], int size, int thread_count);
double *matrixMul_double_cuda(double* vector1, double* vector2, int num);
double doubleGen();
float floatGen();
void operations(int size, int parallel, int serial, int cuda, int verify, int thread_count);
void print_results_float( int size, double time_spent);
void print_results_double( int size, double time_spent);
double verifyVectord(double *vector1, double *vector2, int size);
float verifyVectorf(float *vector1, float *vector2, int size);
__global__ void matMul_CUDA_float(float *sum, int size, float *vector1, float *vector2){
int idx = blockIdx.x*blockDim.x+threadIdx.x; // Sequential thread index across the blocks
int k;
if(idx < size*size){
for(k=0; k< size; k++){
sum[idx] += (*(vector1+(idx-(idx % size)+k))) * (*(vector2+(k*size+(idx % size))));
}
}
} | .text
.file "matMul_CUDA_float.hip"
.globl _Z32__device_stub__matMul_CUDA_floatPfiS_S_ # -- Begin function _Z32__device_stub__matMul_CUDA_floatPfiS_S_
.p2align 4, 0x90
.type _Z32__device_stub__matMul_CUDA_floatPfiS_S_,@function
_Z32__device_stub__matMul_CUDA_floatPfiS_S_: # @_Z32__device_stub__matMul_CUDA_floatPfiS_S_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movl %esi, 4(%rsp)
movq %rdx, 64(%rsp)
movq %rcx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 56(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z17matMul_CUDA_floatPfiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z32__device_stub__matMul_CUDA_floatPfiS_S_, .Lfunc_end0-_Z32__device_stub__matMul_CUDA_floatPfiS_S_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z17matMul_CUDA_floatPfiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z17matMul_CUDA_floatPfiS_S_,@object # @_Z17matMul_CUDA_floatPfiS_S_
.section .rodata,"a",@progbits
.globl _Z17matMul_CUDA_floatPfiS_S_
.p2align 3, 0x0
_Z17matMul_CUDA_floatPfiS_S_:
.quad _Z32__device_stub__matMul_CUDA_floatPfiS_S_
.size _Z17matMul_CUDA_floatPfiS_S_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z17matMul_CUDA_floatPfiS_S_"
.size .L__unnamed_1, 29
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z32__device_stub__matMul_CUDA_floatPfiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z17matMul_CUDA_floatPfiS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z17matMul_CUDA_floatPfiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ MOV R11, c[0x0][0x168] ; /* 0x00005a00000b7a02 */
/* 0x000fc60000000f00 */
/*0030*/ S2R R9, SR_TID.X ; /* 0x0000000000097919 */
/* 0x000e220000002100 */
/*0040*/ ISETP.GE.AND P0, PT, R11.reuse, 0x1, PT ; /* 0x000000010b00780c */
/* 0x040fe20003f06270 */
/*0050*/ IMAD R2, R11, c[0x0][0x168], RZ ; /* 0x00005a000b027a24 */
/* 0x000fe400078e02ff */
/*0060*/ IMAD R15, R0, c[0x0][0x0], R9 ; /* 0x00000000000f7a24 */
/* 0x001fca00078e0209 */
/*0070*/ ISETP.GE.OR P0, PT, R15, R2, !P0 ; /* 0x000000020f00720c */
/* 0x000fda0004706670 */
/*0080*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0090*/ IABS R5, c[0x0][0x168] ; /* 0x00005a0000057a13 */
/* 0x000fe20000000000 */
/*00a0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00b0*/ IABS R8, R15 ; /* 0x0000000f00087213 */
/* 0x000fe20000000000 */
/*00c0*/ HFMA2.MMA R14, -RZ, RZ, 0, 0 ; /* 0x00000000ff0e7435 */
/* 0x000fe200000001ff */
/*00d0*/ I2F.RP R4, R5 ; /* 0x0000000500047306 */
/* 0x000e220000209400 */
/*00e0*/ ISETP.GE.AND P1, PT, R15, RZ, PT ; /* 0x000000ff0f00720c */
/* 0x000fe40003f26270 */
/*00f0*/ MOV R13, 0x4 ; /* 0x00000004000d7802 */
/* 0x000fe40000000f00 */
/*0100*/ LOP3.LUT R10, R11, 0x3, RZ, 0xc0, !PT ; /* 0x000000030b0a7812 */
/* 0x000fc600078ec0ff */
/*0110*/ MUFU.RCP R4, R4 ; /* 0x0000000400047308 */
/* 0x001e240000001000 */
/*0120*/ IADD3 R2, R4, 0xffffffe, RZ ; /* 0x0ffffffe04027810 */
/* 0x001fcc0007ffe0ff */
/*0130*/ F2I.FTZ.U32.TRUNC.NTZ R3, R2 ; /* 0x0000000200037305 */
/* 0x000064000021f000 */
/*0140*/ HFMA2.MMA R2, -RZ, RZ, 0, 0 ; /* 0x00000000ff027435 */
/* 0x001fe200000001ff */
/*0150*/ IADD3 R6, RZ, -R3, RZ ; /* 0x80000003ff067210 */
/* 0x002fca0007ffe0ff */
/*0160*/ IMAD R7, R6, R5, RZ ; /* 0x0000000506077224 */
/* 0x000fc800078e02ff */
/*0170*/ IMAD.HI.U32 R3, R3, R7, R2 ; /* 0x0000000703037227 */
/* 0x000fe200078e0002 */
/*0180*/ IADD3 R2, R11, -0x1, RZ ; /* 0xffffffff0b027810 */
/* 0x000fca0007ffe0ff */
/*0190*/ IMAD.HI.U32 R3, R3, R8, RZ ; /* 0x0000000803037227 */
/* 0x000fca00078e00ff */
/*01a0*/ IADD3 R3, -R3, RZ, RZ ; /* 0x000000ff03037210 */
/* 0x000fca0007ffe1ff */
/*01b0*/ IMAD R8, R5, R3, R8 ; /* 0x0000000305087224 */
/* 0x000fca00078e0208 */
/*01c0*/ ISETP.GT.U32.AND P0, PT, R5, R8, PT ; /* 0x000000080500720c */
/* 0x000fda0003f04070 */
/*01d0*/ @!P0 IADD3 R8, R8, -R5, RZ ; /* 0x8000000508088210 */
/* 0x000fe40007ffe0ff */
/*01e0*/ ISETP.NE.AND P0, PT, RZ, c[0x0][0x168], PT ; /* 0x00005a00ff007a0c */
/* 0x000fe40003f05270 */
/*01f0*/ ISETP.GT.U32.AND P2, PT, R5, R8, PT ; /* 0x000000080500720c */
/* 0x000fda0003f44070 */
/*0200*/ @!P2 IADD3 R8, R8, -R5, RZ ; /* 0x800000050808a210 */
/* 0x000fe40007ffe0ff */
/*0210*/ ISETP.GE.U32.AND P2, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fe20003f46070 */
/*0220*/ IMAD.WIDE R2, R15, R13, c[0x0][0x160] ; /* 0x000058000f027625 */
/* 0x000fe200078e020d */
/*0230*/ @!P1 IADD3 R8, -R8, RZ, RZ ; /* 0x000000ff08089210 */
/* 0x000fe40007ffe1ff */
/*0240*/ @!P0 LOP3.LUT R8, RZ, c[0x0][0x168], RZ, 0x33, !PT ; /* 0x00005a00ff088a12 */
/* 0x000fd200078e33ff */
/*0250*/ @!P2 BRA 0xdc0 ; /* 0x00000b600000a947 */
/* 0x000fea0003800000 */
/*0260*/ IADD3 R12, -R10, c[0x0][0x168], RZ ; /* 0x00005a000a0c7a10 */
/* 0x000fe20007ffe1ff */
/*0270*/ LDG.E R17, [R2.64] ; /* 0x0000000402117981 */
/* 0x000162000c1e1900 */
/*0280*/ ULDC.64 UR6, c[0x0][0x170] ; /* 0x00005c0000067ab9 */
/* 0x000fe20000000a00 */
/*0290*/ IADD3 R15, R15, -R8, RZ ; /* 0x800000080f0f7210 */
/* 0x000fe20007ffe0ff */
/*02a0*/ IMAD.WIDE R4, R8, R13, c[0x0][0x178] ; /* 0x00005e0008047625 */
/* 0x000fe200078e020d */
/*02b0*/ ISETP.GT.AND P0, PT, R12, RZ, PT ; /* 0x000000ff0c00720c */
/* 0x000fe40003f04270 */
/*02c0*/ MOV R14, RZ ; /* 0x000000ff000e7202 */
/* 0x000fd60000000f00 */
/*02d0*/ @!P0 BRA 0xbf0 ; /* 0x0000091000008947 */
/* 0x001fea0003800000 */
/*02e0*/ ISETP.GT.AND P1, PT, R12, 0xc, PT ; /* 0x0000000c0c00780c */
/* 0x000fe40003f24270 */
/*02f0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*0300*/ @!P1 BRA 0x8b0 ; /* 0x000005a000009947 */
/* 0x000fea0003800000 */
/*0310*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0320*/ MOV R6, UR6 ; /* 0x0000000600067c02 */
/* 0x000fe20008000f00 */
/*0330*/ LDG.E R16, [R4.64] ; /* 0x0000000404107981 */
/* 0x004ea2000c1e1900 */
/*0340*/ MOV R7, UR7 ; /* 0x0000000700077c02 */
/* 0x000fca0008000f00 */
/*0350*/ IMAD.WIDE R6, R15, 0x4, R6 ; /* 0x000000040f067825 */
/* 0x000fca00078e0206 */
/*0360*/ LDG.E R18, [R6.64] ; /* 0x0000000406127981 */
/* 0x000ea4000c1e1900 */
/*0370*/ FFMA R21, R16, R18, R17 ; /* 0x0000001210157223 */
/* 0x024fe40000000011 */
/*0380*/ IMAD.WIDE R16, R11, 0x4, R4 ; /* 0x000000040b107825 */
/* 0x000fc600078e0204 */
/*0390*/ STG.E [R2.64], R21 ; /* 0x0000001502007986 */
/* 0x0001e8000c101904 */
/*03a0*/ LDG.E R18, [R16.64] ; /* 0x0000000410127981 */
/* 0x000ea8000c1e1900 */
/*03b0*/ LDG.E R19, [R6.64+0x4] ; /* 0x0000040406137981 */
/* 0x000ea4000c1e1900 */
/*03c0*/ FFMA R23, R18, R19, R21 ; /* 0x0000001312177223 */
/* 0x004fc40000000015 */
/*03d0*/ IMAD.WIDE R18, R11, 0x4, R16 ; /* 0x000000040b127825 */
/* 0x000fc600078e0210 */
/*03e0*/ STG.E [R2.64], R23 ; /* 0x0000001702007986 */
/* 0x0003e8000c101904 */
/*03f0*/ LDG.E R20, [R18.64] ; /* 0x0000000412147981 */
/* 0x000ea8000c1e1900 */
/*0400*/ LDG.E R4, [R6.64+0x8] ; /* 0x0000080406047981 */
/* 0x000ea4000c1e1900 */
/*0410*/ FFMA R25, R20, R4, R23 ; /* 0x0000000414197223 */
/* 0x004fc40000000017 */
/*0420*/ IMAD.WIDE R4, R11, 0x4, R18 ; /* 0x000000040b047825 */
/* 0x000fc600078e0212 */
/*0430*/ STG.E [R2.64], R25 ; /* 0x0000001902007986 */
/* 0x0005e8000c101904 */
/*0440*/ LDG.E R20, [R4.64] ; /* 0x0000000404147981 */
/* 0x000e28000c1e1900 */
/*0450*/ LDG.E R16, [R6.64+0xc] ; /* 0x00000c0406107981 */
/* 0x000e24000c1e1900 */
/*0460*/ FFMA R21, R20, R16, R25 ; /* 0x0000001014157223 */
/* 0x001fc40000000019 */
/*0470*/ IMAD.WIDE R16, R11, 0x4, R4 ; /* 0x000000040b107825 */
/* 0x000fc600078e0204 */
/*0480*/ STG.E [R2.64], R21 ; /* 0x0000001502007986 */
/* 0x0001e8000c101904 */
/*0490*/ LDG.E R20, [R16.64] ; /* 0x0000000410147981 */
/* 0x000e68000c1e1900 */
/*04a0*/ LDG.E R18, [R6.64+0x10] ; /* 0x0000100406127981 */
/* 0x000e64000c1e1900 */
/*04b0*/ FFMA R23, R20, R18, R21 ; /* 0x0000001214177223 */
/* 0x002fc40000000015 */
/*04c0*/ IMAD.WIDE R18, R11, 0x4, R16 ; /* 0x000000040b127825 */
/* 0x000fc600078e0210 */
/*04d0*/ STG.E [R2.64], R23 ; /* 0x0000001702007986 */
/* 0x0003e8000c101904 */
/*04e0*/ LDG.E R20, [R18.64] ; /* 0x0000000412147981 */
/* 0x000ea8000c1e1900 */
/*04f0*/ LDG.E R4, [R6.64+0x14] ; /* 0x0000140406047981 */
/* 0x000ea4000c1e1900 */
/*0500*/ FFMA R25, R20, R4, R23 ; /* 0x0000000414197223 */
/* 0x004fc40000000017 */
/*0510*/ IMAD.WIDE R4, R11, 0x4, R18 ; /* 0x000000040b047825 */
/* 0x000fc600078e0212 */
/*0520*/ STG.E [R2.64], R25 ; /* 0x0000001902007986 */
/* 0x0005e8000c101904 */
/*0530*/ LDG.E R20, [R4.64] ; /* 0x0000000404147981 */
/* 0x000e28000c1e1900 */
/*0540*/ LDG.E R16, [R6.64+0x18] ; /* 0x0000180406107981 */
/* 0x000e24000c1e1900 */
/*0550*/ FFMA R21, R20, R16, R25 ; /* 0x0000001014157223 */
/* 0x001fc40000000019 */
/*0560*/ IMAD.WIDE R16, R11, 0x4, R4 ; /* 0x000000040b107825 */
/* 0x000fc600078e0204 */
/*0570*/ STG.E [R2.64], R21 ; /* 0x0000001502007986 */
/* 0x0001e8000c101904 */
/*0580*/ LDG.E R20, [R16.64] ; /* 0x0000000410147981 */
/* 0x000e68000c1e1900 */
/*0590*/ LDG.E R18, [R6.64+0x1c] ; /* 0x00001c0406127981 */
/* 0x000e64000c1e1900 */
/*05a0*/ FFMA R23, R20, R18, R21 ; /* 0x0000001214177223 */
/* 0x002fc40000000015 */
/*05b0*/ IMAD.WIDE R18, R11, 0x4, R16 ; /* 0x000000040b127825 */
/* 0x000fc600078e0210 */
/*05c0*/ STG.E [R2.64], R23 ; /* 0x0000001702007986 */
/* 0x0003e8000c101904 */
/*05d0*/ LDG.E R20, [R18.64] ; /* 0x0000000412147981 */
/* 0x000ea8000c1e1900 */
/*05e0*/ LDG.E R4, [R6.64+0x20] ; /* 0x0000200406047981 */
/* 0x000ea4000c1e1900 */
/*05f0*/ FFMA R25, R20, R4, R23 ; /* 0x0000000414197223 */
/* 0x004fc40000000017 */
/*0600*/ IMAD.WIDE R4, R11, 0x4, R18 ; /* 0x000000040b047825 */
/* 0x000fc600078e0212 */
/*0610*/ STG.E [R2.64], R25 ; /* 0x0000001902007986 */
/* 0x0005e8000c101904 */
/*0620*/ LDG.E R20, [R4.64] ; /* 0x0000000404147981 */
/* 0x000e28000c1e1900 */
/*0630*/ LDG.E R16, [R6.64+0x24] ; /* 0x0000240406107981 */
/* 0x000e24000c1e1900 */
/*0640*/ FFMA R21, R20, R16, R25 ; /* 0x0000001014157223 */
/* 0x001fc40000000019 */
/*0650*/ IMAD.WIDE R16, R11, 0x4, R4 ; /* 0x000000040b107825 */
/* 0x000fc600078e0204 */
/*0660*/ STG.E [R2.64], R21 ; /* 0x0000001502007986 */
/* 0x000fe8000c101904 */
/*0670*/ LDG.E R20, [R16.64] ; /* 0x0000000410147981 */
/* 0x000e68000c1e1900 */
/*0680*/ LDG.E R18, [R6.64+0x28] ; /* 0x0000280406127981 */
/* 0x000e64000c1e1900 */
/*0690*/ FFMA R23, R20, R18, R21 ; /* 0x0000001214177223 */
/* 0x002fc40000000015 */
/*06a0*/ IMAD.WIDE R18, R11, 0x4, R16 ; /* 0x000000040b127825 */
/* 0x000fc600078e0210 */
/*06b0*/ STG.E [R2.64], R23 ; /* 0x0000001702007986 */
/* 0x0001e8000c101904 */
/*06c0*/ LDG.E R20, [R18.64] ; /* 0x0000000412147981 */
/* 0x000ea8000c1e1900 */
/*06d0*/ LDG.E R4, [R6.64+0x2c] ; /* 0x00002c0406047981 */
/* 0x000ea4000c1e1900 */
/*06e0*/ FFMA R25, R20, R4, R23 ; /* 0x0000000414197223 */
/* 0x004fc40000000017 */
/*06f0*/ IMAD.WIDE R4, R11, 0x4, R18 ; /* 0x000000040b047825 */
/* 0x000fc600078e0212 */
/*0700*/ STG.E [R2.64], R25 ; /* 0x0000001902007986 */
/* 0x0003e8000c101904 */
/*0710*/ LDG.E R20, [R4.64] ; /* 0x0000000404147981 */
/* 0x000ea8000c1e1900 */
/*0720*/ LDG.E R16, [R6.64+0x30] ; /* 0x0000300406107981 */
/* 0x000ea4000c1e1900 */
/*0730*/ FFMA R27, R20, R16, R25 ; /* 0x00000010141b7223 */
/* 0x004fc40000000019 */
/*0740*/ IMAD.WIDE R16, R11, 0x4, R4 ; /* 0x000000040b107825 */
/* 0x000fc600078e0204 */
/*0750*/ STG.E [R2.64], R27 ; /* 0x0000001b02007986 */
/* 0x0005e8000c101904 */
/*0760*/ LDG.E R20, [R16.64] ; /* 0x0000000410147981 */
/* 0x000e28000c1e1900 */
/*0770*/ LDG.E R18, [R6.64+0x34] ; /* 0x0000340406127981 */
/* 0x000e24000c1e1900 */
/*0780*/ FFMA R23, R20, R18, R27 ; /* 0x0000001214177223 */
/* 0x001fc4000000001b */
/*0790*/ IMAD.WIDE R18, R11, 0x4, R16 ; /* 0x000000040b127825 */
/* 0x000fc600078e0210 */
/*07a0*/ STG.E [R2.64], R23 ; /* 0x0000001702007986 */
/* 0x0005e8000c101904 */
/*07b0*/ LDG.E R20, [R18.64] ; /* 0x0000000412147981 */
/* 0x000e68000c1e1900 */
/*07c0*/ LDG.E R4, [R6.64+0x38] ; /* 0x0000380406047981 */
/* 0x000e62000c1e1900 */
/*07d0*/ IADD3 R12, R12, -0x10, RZ ; /* 0xfffffff00c0c7810 */
/* 0x000fe20007ffe0ff */
/*07e0*/ FFMA R25, R20, R4, R23 ; /* 0x0000000414197223 */
/* 0x002fc40000000017 */
/*07f0*/ IMAD.WIDE R20, R11, 0x4, R18 ; /* 0x000000040b147825 */
/* 0x000fc600078e0212 */
/*0800*/ STG.E [R2.64], R25 ; /* 0x0000001902007986 */
/* 0x0005e8000c101904 */
/*0810*/ LDG.E R5, [R6.64+0x3c] ; /* 0x00003c0406057981 */
/* 0x000ee8000c1e1900 */
/*0820*/ LDG.E R4, [R20.64] ; /* 0x0000000414047981 */
/* 0x000ee2000c1e1900 */
/*0830*/ ISETP.GT.AND P1, PT, R12, 0xc, PT ; /* 0x0000000c0c00780c */
/* 0x000fe20003f24270 */
/*0840*/ UIADD3 UR6, UP0, UR6, 0x40, URZ ; /* 0x0000004006067890 */
/* 0x000fe2000ff1e03f */
/*0850*/ IADD3 R14, R14, 0x10, RZ ; /* 0x000000100e0e7810 */
/* 0x000fc60007ffe0ff */
/*0860*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0870*/ FFMA R17, R4, R5, R25 ; /* 0x0000000504117223 */
/* 0x008fe40000000019 */
/*0880*/ IMAD.WIDE R4, R11, 0x4, R20 ; /* 0x000000040b047825 */
/* 0x000fc600078e0214 */
/*0890*/ STG.E [R2.64], R17 ; /* 0x0000001102007986 */
/* 0x0005e4000c101904 */
/*08a0*/ @P1 BRA 0x320 ; /* 0xfffffa7000001947 */
/* 0x000fea000383ffff */
/*08b0*/ ISETP.GT.AND P1, PT, R12, 0x4, PT ; /* 0x000000040c00780c */
/* 0x000fda0003f24270 */
/*08c0*/ @!P1 BRA 0xbd0 ; /* 0x0000030000009947 */
/* 0x000fea0003800000 */
/*08d0*/ MOV R6, UR6 ; /* 0x0000000600067c02 */
/* 0x000fe20008000f00 */
/*08e0*/ LDG.E R16, [R4.64] ; /* 0x0000000404107981 */
/* 0x000ee2000c1e1900 */
/*08f0*/ MOV R7, UR7 ; /* 0x0000000700077c02 */
/* 0x000fca0008000f00 */
/*0900*/ IMAD.WIDE R6, R15, 0x4, R6 ; /* 0x000000040f067825 */
/* 0x000fca00078e0206 */
/*0910*/ LDG.E R18, [R6.64] ; /* 0x0000000406127981 */
/* 0x000ee4000c1e1900 */
/*0920*/ FFMA R21, R16, R18, R17 ; /* 0x0000001210157223 */
/* 0x028fe40000000011 */
/*0930*/ IMAD.WIDE R16, R11, 0x4, R4 ; /* 0x000000040b107825 */
/* 0x004fc600078e0204 */
/*0940*/ STG.E [R2.64], R21 ; /* 0x0000001502007986 */
/* 0x0001e8000c101904 */
/*0950*/ LDG.E R18, [R16.64] ; /* 0x0000000410127981 */
/* 0x000ea8000c1e1900 */
/*0960*/ LDG.E R19, [R6.64+0x4] ; /* 0x0000040406137981 */
/* 0x000ea4000c1e1900 */
/*0970*/ FFMA R23, R18, R19, R21 ; /* 0x0000001312177223 */
/* 0x004fc40000000015 */
/*0980*/ IMAD.WIDE R18, R11, 0x4, R16 ; /* 0x000000040b127825 */
/* 0x000fc600078e0210 */
/*0990*/ STG.E [R2.64], R23 ; /* 0x0000001702007986 */
/* 0x0003e8000c101904 */
/*09a0*/ LDG.E R20, [R18.64] ; /* 0x0000000412147981 */
/* 0x000ea8000c1e1900 */
/*09b0*/ LDG.E R4, [R6.64+0x8] ; /* 0x0000080406047981 */
/* 0x000ea4000c1e1900 */
/*09c0*/ FFMA R25, R20, R4, R23 ; /* 0x0000000414197223 */
/* 0x004fc40000000017 */
/*09d0*/ IMAD.WIDE R4, R11, 0x4, R18 ; /* 0x000000040b047825 */
/* 0x000fc600078e0212 */
/*09e0*/ STG.E [R2.64], R25 ; /* 0x0000001902007986 */
/* 0x0005e8000c101904 */
/*09f0*/ LDG.E R20, [R4.64] ; /* 0x0000000404147981 */
/* 0x000e28000c1e1900 */
/*0a00*/ LDG.E R16, [R6.64+0xc] ; /* 0x00000c0406107981 */
/* 0x000e24000c1e1900 */
/*0a10*/ FFMA R21, R20, R16, R25 ; /* 0x0000001014157223 */
/* 0x001fc40000000019 */
/*0a20*/ IMAD.WIDE R16, R11, 0x4, R4 ; /* 0x000000040b107825 */
/* 0x000fc600078e0204 */
/*0a30*/ STG.E [R2.64], R21 ; /* 0x0000001502007986 */
/* 0x0001e8000c101904 */
/*0a40*/ LDG.E R20, [R16.64] ; /* 0x0000000410147981 */
/* 0x000e68000c1e1900 */
/*0a50*/ LDG.E R18, [R6.64+0x10] ; /* 0x0000100406127981 */
/* 0x000e64000c1e1900 */
/*0a60*/ FFMA R23, R20, R18, R21 ; /* 0x0000001214177223 */
/* 0x002fc40000000015 */
/*0a70*/ IMAD.WIDE R18, R11, 0x4, R16 ; /* 0x000000040b127825 */
/* 0x000fc600078e0210 */
/*0a80*/ STG.E [R2.64], R23 ; /* 0x0000001702007986 */
/* 0x0003e8000c101904 */
/*0a90*/ LDG.E R20, [R18.64] ; /* 0x0000000412147981 */
/* 0x000ea8000c1e1900 */
/*0aa0*/ LDG.E R4, [R6.64+0x14] ; /* 0x0000140406047981 */
/* 0x000ea4000c1e1900 */
/*0ab0*/ FFMA R25, R20, R4, R23 ; /* 0x0000000414197223 */
/* 0x004fc40000000017 */
/*0ac0*/ IMAD.WIDE R4, R11, 0x4, R18 ; /* 0x000000040b047825 */
/* 0x000fc600078e0212 */
/*0ad0*/ STG.E [R2.64], R25 ; /* 0x0000001902007986 */
/* 0x0003e8000c101904 */
/*0ae0*/ LDG.E R20, [R4.64] ; /* 0x0000000404147981 */
/* 0x000ea8000c1e1900 */
/*0af0*/ LDG.E R16, [R6.64+0x18] ; /* 0x0000180406107981 */
/* 0x000ea4000c1e1900 */
/*0b00*/ FFMA R27, R20, R16, R25 ; /* 0x00000010141b7223 */
/* 0x004fc40000000019 */
/*0b10*/ IMAD.WIDE R20, R11, 0x4, R4 ; /* 0x000000040b147825 */
/* 0x001fc600078e0204 */
/*0b20*/ STG.E [R2.64], R27 ; /* 0x0000001b02007986 */
/* 0x0003e8000c101904 */
/*0b30*/ LDG.E R17, [R6.64+0x1c] ; /* 0x00001c0406117981 */
/* 0x000ea8000c1e1900 */
/*0b40*/ LDG.E R16, [R20.64] ; /* 0x0000000414107981 */
/* 0x000ea2000c1e1900 */
/*0b50*/ UIADD3 UR6, UP0, UR6, 0x20, URZ ; /* 0x0000002006067890 */
/* 0x000fe2000ff1e03f */
/*0b60*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe20003f0e170 */
/*0b70*/ IMAD.WIDE R4, R11, 0x4, R20 ; /* 0x000000040b047825 */
/* 0x000fe200078e0214 */
/*0b80*/ IADD3 R14, R14, 0x8, RZ ; /* 0x000000080e0e7810 */
/* 0x000fc40007ffe0ff */
/*0b90*/ IADD3 R12, R12, -0x8, RZ ; /* 0xfffffff80c0c7810 */
/* 0x000fe20007ffe0ff */
/*0ba0*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0bb0*/ FFMA R17, R16, R17, R27 ; /* 0x0000001110117223 */
/* 0x004fca000000001b */
/*0bc0*/ STG.E [R2.64], R17 ; /* 0x0000001102007986 */
/* 0x0003e8000c101904 */
/*0bd0*/ ISETP.NE.OR P0, PT, R12, RZ, P0 ; /* 0x000000ff0c00720c */
/* 0x000fda0000705670 */
/*0be0*/ @!P0 BRA 0xdc0 ; /* 0x000001d000008947 */
/* 0x000fea0003800000 */
/*0bf0*/ MOV R6, UR6 ; /* 0x0000000600067c02 */
/* 0x000fe20008000f00 */
/*0c00*/ LDG.E R16, [R4.64] ; /* 0x0000000404107981 */
/* 0x000ee2000c1e1900 */
/*0c10*/ MOV R7, UR7 ; /* 0x0000000700077c02 */
/* 0x000fca0008000f00 */
/*0c20*/ IMAD.WIDE R6, R15, 0x4, R6 ; /* 0x000000040f067825 */
/* 0x000fca00078e0206 */
/*0c30*/ LDG.E R18, [R6.64] ; /* 0x0000000406127981 */
/* 0x000ee4000c1e1900 */
/*0c40*/ FFMA R23, R16, R18, R17 ; /* 0x0000001210177223 */
/* 0x02efe40000000011 */
/*0c50*/ IMAD.WIDE R16, R11, 0x4, R4 ; /* 0x000000040b107825 */
/* 0x000fc600078e0204 */
/*0c60*/ STG.E [R2.64], R23 ; /* 0x0000001702007986 */
/* 0x0001e8000c101904 */
/*0c70*/ LDG.E R18, [R16.64] ; /* 0x0000000410127981 */
/* 0x000ea8000c1e1900 */
/*0c80*/ LDG.E R19, [R6.64+0x4] ; /* 0x0000040406137981 */
/* 0x000ea4000c1e1900 */
/*0c90*/ FFMA R25, R18, R19, R23 ; /* 0x0000001312197223 */
/* 0x004fc40000000017 */
/*0ca0*/ IMAD.WIDE R18, R11, 0x4, R16 ; /* 0x000000040b127825 */
/* 0x000fc600078e0210 */
/*0cb0*/ STG.E [R2.64], R25 ; /* 0x0000001902007986 */
/* 0x0001e8000c101904 */
/*0cc0*/ LDG.E R20, [R18.64] ; /* 0x0000000412147981 */
/* 0x000ea8000c1e1900 */
/*0cd0*/ LDG.E R4, [R6.64+0x8] ; /* 0x0000080406047981 */
/* 0x000ea2000c1e1900 */
/*0ce0*/ IADD3 R12, R12, -0x4, RZ ; /* 0xfffffffc0c0c7810 */
/* 0x000fe20007ffe0ff */
/*0cf0*/ FFMA R27, R20, R4, R25 ; /* 0x00000004141b7223 */
/* 0x004fc40000000019 */
/*0d00*/ IMAD.WIDE R20, R11, 0x4, R18 ; /* 0x000000040b147825 */
/* 0x000fc600078e0212 */
/*0d10*/ STG.E [R2.64], R27 ; /* 0x0000001b02007986 */
/* 0x0001e8000c101904 */
/*0d20*/ LDG.E R5, [R6.64+0xc] ; /* 0x00000c0406057981 */
/* 0x000ea8000c1e1900 */
/*0d30*/ LDG.E R4, [R20.64] ; /* 0x0000000414047981 */
/* 0x000ea2000c1e1900 */
/*0d40*/ ISETP.NE.AND P0, PT, R12, RZ, PT ; /* 0x000000ff0c00720c */
/* 0x000fe20003f05270 */
/*0d50*/ UIADD3 UR6, UP0, UR6, 0x10, URZ ; /* 0x0000001006067890 */
/* 0x000fe2000ff1e03f */
/*0d60*/ IADD3 R14, R14, 0x4, RZ ; /* 0x000000040e0e7810 */
/* 0x000fc60007ffe0ff */
/*0d70*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0d80*/ FFMA R17, R4, R5, R27 ; /* 0x0000000504117223 */
/* 0x004fe4000000001b */
/*0d90*/ IMAD.WIDE R4, R11, 0x4, R20 ; /* 0x000000040b047825 */
/* 0x000fc600078e0214 */
/*0da0*/ STG.E [R2.64], R17 ; /* 0x0000001102007986 */
/* 0x0001e4000c101904 */
/*0db0*/ @P0 BRA 0xbf0 ; /* 0xfffffe3000000947 */
/* 0x001fea000383ffff */
/*0dc0*/ ISETP.NE.AND P0, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fda0003f05270 */
/*0dd0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0de0*/ LDG.E R15, [R2.64] ; /* 0x00000004020f7981 */
/* 0x000162000c1e1900 */
/*0df0*/ IADD3 R9, R9, R14, RZ ; /* 0x0000000e09097210 */
/* 0x000fca0007ffe0ff */
/*0e00*/ IMAD R9, R0, c[0x0][0x0], R9 ; /* 0x0000000000097a24 */
/* 0x000fca00078e0209 */
/*0e10*/ IADD3 R4, -R8, R9, RZ ; /* 0x0000000908047210 */
/* 0x000fe20007ffe1ff */
/*0e20*/ IMAD R8, R14, c[0x0][0x168], R8 ; /* 0x00005a000e087a24 */
/* 0x000fc800078e0208 */
/*0e30*/ IMAD.WIDE R4, R4, R13, c[0x0][0x170] ; /* 0x00005c0004047625 */
/* 0x000fca00078e020d */
/*0e40*/ MOV R9, R4 ; /* 0x0000000400097202 */
/* 0x000fe40000000f00 */
/*0e50*/ MOV R12, R5 ; /* 0x00000005000c7202 */
/* 0x000fe20000000f00 */
/*0e60*/ IMAD.WIDE R4, R8, R13, c[0x0][0x178] ; /* 0x00005e0008047625 */
/* 0x001fc800078e020d */
/*0e70*/ MOV R6, R9 ; /* 0x0000000900067202 */
/* 0x000fe20000000f00 */
/*0e80*/ LDG.E R0, [R4.64] ; /* 0x0000000404007981 */
/* 0x0010e2000c1e1900 */
/*0e90*/ MOV R7, R12 ; /* 0x0000000c00077202 */
/* 0x000fca0000000f00 */
/*0ea0*/ LDG.E R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000ee2000c1e1900 */
/*0eb0*/ IADD3 R10, R10, -0x1, RZ ; /* 0xffffffff0a0a7810 */
/* 0x000fe40007ffe0ff */
/*0ec0*/ IADD3 R9, P1, R9, 0x4, RZ ; /* 0x0000000409097810 */
/* 0x000fe20007f3e0ff */
/*0ed0*/ IMAD.WIDE R4, R11, 0x4, R4 ; /* 0x000000040b047825 */
/* 0x001fe200078e0204 */
/*0ee0*/ ISETP.NE.AND P0, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fe40003f05270 */
/*0ef0*/ IADD3.X R12, RZ, R12, RZ, P1, !PT ; /* 0x0000000cff0c7210 */
/* 0x000fe20000ffe4ff */
/*0f00*/ FFMA R15, R0, R6, R15 ; /* 0x00000006000f7223 */
/* 0x028fca000000000f */
/*0f10*/ STG.E [R2.64], R15 ; /* 0x0000000f02007986 */
/* 0x0001ea000c101904 */
/*0f20*/ @P0 BRA 0xe70 ; /* 0xffffff4000000947 */
/* 0x000fea000383ffff */
/*0f30*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0f40*/ BRA 0xf40; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0f50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0fa0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0fb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0fc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0fd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0fe0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ff0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z17matMul_CUDA_floatPfiS_S_
.globl _Z17matMul_CUDA_floatPfiS_S_
.p2align 8
.type _Z17matMul_CUDA_floatPfiS_S_,@function
_Z17matMul_CUDA_floatPfiS_S_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s4, s[0:1], 0x8
s_mov_b32 s5, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_cmp_gt_i32 s4, 0
s_mul_i32 s15, s15, s2
s_mul_i32 s2, s4, s4
v_add_nc_u32_e32 v3, s15, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_gt_i32_e32 vcc_lo, s2, v3
s_cselect_b32 s2, -1, 0
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_3
s_load_b64 s[6:7], s[0:1], 0x0
v_ashrrev_i32_e32 v4, 31, v3
v_ashrrev_i32_e32 v7, 31, v3
s_load_b128 s[0:3], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[1:2], 2, v[3:4]
v_add3_u32 v0, v0, v7, s15
v_add_nc_u32_e32 v3, v3, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_xor_b32_e32 v3, v3, v7
s_waitcnt lgkmcnt(0)
v_add_co_u32 v1, vcc_lo, s6, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s7, v2, vcc_lo
s_ashr_i32 s6, s4, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
s_add_i32 s7, s4, s6
global_load_b32 v5, v[1:2], off
s_xor_b32 s6, s7, s6
v_cvt_f32_u32_e32 v4, s6
s_sub_i32 s7, 0, s6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v4, v4
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v4, 0x4f7ffffe, v4
v_cvt_u32_f32_e32 v4, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v6, s7, v4
v_mul_hi_u32 v6, v4, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v4, v4, v6
v_mul_hi_u32 v4, v3, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v4, v4, s6
v_sub_nc_u32_e32 v3, v3, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v4, s6, v3
v_cmp_le_u32_e32 vcc_lo, s6, v3
v_cndmask_b32_e32 v3, v3, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v4, s6, v3
v_cmp_le_u32_e32 vcc_lo, s6, v3
v_cndmask_b32_e32 v3, v3, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_xor_b32_e32 v4, v3, v7
v_sub_nc_u32_e32 v3, v4, v7
v_sub_nc_u32_e32 v0, v0, v4
.p2align 6
.LBB0_2:
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_nc_u32_e32 v6, s5, v0
v_ashrrev_i32_e32 v4, 31, v3
s_add_i32 s5, s5, 1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
s_cmp_lg_u32 s4, s5
v_ashrrev_i32_e32 v7, 31, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[8:9], 2, v[3:4]
v_add_nc_u32_e32 v3, s4, v3
v_lshlrev_b64 v[6:7], 2, v[6:7]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v8, vcc_lo, s2, v8
v_add_co_ci_u32_e32 v9, vcc_lo, s3, v9, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v6, vcc_lo, s0, v6
v_add_co_ci_u32_e32 v7, vcc_lo, s1, v7, vcc_lo
global_load_b32 v4, v[8:9], off
global_load_b32 v6, v[6:7], off
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v5, v6, v4
global_store_b32 v[1:2], v5, off
s_cbranch_scc1 .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z17matMul_CUDA_floatPfiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 10
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z17matMul_CUDA_floatPfiS_S_, .Lfunc_end0-_Z17matMul_CUDA_floatPfiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z17matMul_CUDA_floatPfiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z17matMul_CUDA_floatPfiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 10
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000ab2fa_00000000-6_matMul_CUDA_float.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z42__device_stub__Z17matMul_CUDA_floatPfiS_S_PfiS_S_
.type _Z42__device_stub__Z17matMul_CUDA_floatPfiS_S_PfiS_S_, @function
_Z42__device_stub__Z17matMul_CUDA_floatPfiS_S_PfiS_S_:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movq %rdx, 8(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z17matMul_CUDA_floatPfiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z42__device_stub__Z17matMul_CUDA_floatPfiS_S_PfiS_S_, .-_Z42__device_stub__Z17matMul_CUDA_floatPfiS_S_PfiS_S_
.globl _Z17matMul_CUDA_floatPfiS_S_
.type _Z17matMul_CUDA_floatPfiS_S_, @function
_Z17matMul_CUDA_floatPfiS_S_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z42__device_stub__Z17matMul_CUDA_floatPfiS_S_PfiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z17matMul_CUDA_floatPfiS_S_, .-_Z17matMul_CUDA_floatPfiS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z17matMul_CUDA_floatPfiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z17matMul_CUDA_floatPfiS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "matMul_CUDA_float.hip"
.globl _Z32__device_stub__matMul_CUDA_floatPfiS_S_ # -- Begin function _Z32__device_stub__matMul_CUDA_floatPfiS_S_
.p2align 4, 0x90
.type _Z32__device_stub__matMul_CUDA_floatPfiS_S_,@function
_Z32__device_stub__matMul_CUDA_floatPfiS_S_: # @_Z32__device_stub__matMul_CUDA_floatPfiS_S_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movl %esi, 4(%rsp)
movq %rdx, 64(%rsp)
movq %rcx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 56(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z17matMul_CUDA_floatPfiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z32__device_stub__matMul_CUDA_floatPfiS_S_, .Lfunc_end0-_Z32__device_stub__matMul_CUDA_floatPfiS_S_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z17matMul_CUDA_floatPfiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z17matMul_CUDA_floatPfiS_S_,@object # @_Z17matMul_CUDA_floatPfiS_S_
.section .rodata,"a",@progbits
.globl _Z17matMul_CUDA_floatPfiS_S_
.p2align 3, 0x0
_Z17matMul_CUDA_floatPfiS_S_:
.quad _Z32__device_stub__matMul_CUDA_floatPfiS_S_
.size _Z17matMul_CUDA_floatPfiS_S_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z17matMul_CUDA_floatPfiS_S_"
.size .L__unnamed_1, 29
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z32__device_stub__matMul_CUDA_floatPfiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z17matMul_CUDA_floatPfiS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "Vector.cuh"
#include "Normal.cuh"
__host__ __device__ Vector::Vector() :
x(0.0), y(0.0), z(0.0) { }
__host__ __device__ Vector::Vector(float v) :
x(v), y(v), z(v) {}
__host__ __device__ Vector::Vector(const Vector &w) :
x(w.x), y(w.y), z(w.z) { }
__host__ __device__ Vector::Vector(float xx, float yy, float zz) :
x(xx), y(yy), z(zz) { }
__host__ __device__ float Vector::dot(const Vector &w) const {
return this->x * w.x + this->y * w.y + this->z * w.z;
}
__host__ __device__ float Vector::dot(const Normal &n) const {
return this->x * n.x + this->y * n.y + this->z * n.z;
}
__host__ __device__ Vector Vector::cross(const Normal &n) const {
return Vector(this->y * n.z - this->z * n.y, this->z * n.x - this->x * n.z, this->x * n.y - this->y * n.x);
}
__host__ __device__ Vector Vector::cross(const Vector &w) const {
return Vector(this->y * w.z - this->z * w.y, this->z * w.x - this->x * w.z, this->x * w.y - this->y * w.x);
}
__host__ __device__ Vector Vector::operator+(float s) const {
return Vector(this->x + s, this->y + s, this->z + s);
}
__host__ __device__ Vector Vector::operator+(const Vector &w) const {
return Vector(this->x + w.x, this->y + w.y, this->z + w.z);
}
__host__ __device__ Vector& Vector::operator+=(float s) {
x += s; y += s; z += s;
return *this;
}
__host__ __device__ Vector& Vector::operator+=(const Vector &v) {
x += v.x; y += v.y; z += v.z;
return *this;
}
__host__ __device__ Vector Vector::operator-(float s) const {
return Vector(this->x - s, this->y - s, this->z - s);
}
__host__ __device__ Vector Vector::operator-(const Vector &w) const {
return Vector(this->x - w.x, this->y - w.y, this->z - w.z);
}
__host__ __device__ Vector& Vector::operator-=(float s) {
x -= s; y -= s; z -= s;
return *this;
}
__host__ __device__ Vector Vector::operator*(float s) const {
return Vector(s * this->x, s * this->y, s * this->z);
}
__host__ __device__ Vector Vector::operator*(const Vector &w) const {
return Vector(this->x * w.x, this->y * w.y, this->z * w.z);
}
__host__ __device__ Vector& Vector::operator*=(float s) {
x *= s; y *= s; z *= s;
return *this;
}
__host__ __device__ Vector Vector::operator/(float s) const {
return Vector(this->x / s, this->y / s, this->z / s);
}
__host__ __device__ Vector Vector::operator/(const Vector &w) const {
return Vector(this->x / w.x, this->y / w.y, this->z / w.z);
}
__host__ __device__ Vector& Vector::operator/=(float s) {
x /= s; y /= s; z /= s;
return *this;
}
__host__ __device__ float Vector::norm() const {
return sqrtf(this->x*this->x + this->y*this->y + this->z*this->z);
}
__host__ __device__ Vector& Vector::normalize() {
*this /= norm();
return *this;
}
__host__ __device__ Vector Vector::normalized() const {
return *this / norm();
}
__host__ __device__ Vector operator-(const Vector &v) {
return Vector(-v.x, -v.y, -v.z);
}
__host__ __device__ Vector operator*(float s, const Vector &v) {
return v*s;
}
__host__ __device__ void coordinateSystem(const Vector &v1, Vector *v2, Vector *v3) {
*v2 = Vector(0);
if (v1.x == 0 && v1.x == 0)
{
v2->x = -v1.z;
}
else {
v2->x = -v1.y;
v2->y = v1.x;
}
*v3 = v1.cross(*v2);
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "Vector.cuh"
#include "Normal.cuh"
__host__ __device__ Vector::Vector() :
x(0.0), y(0.0), z(0.0) { }
__host__ __device__ Vector::Vector(float v) :
x(v), y(v), z(v) {}
__host__ __device__ Vector::Vector(const Vector &w) :
x(w.x), y(w.y), z(w.z) { }
__host__ __device__ Vector::Vector(float xx, float yy, float zz) :
x(xx), y(yy), z(zz) { }
__host__ __device__ float Vector::dot(const Vector &w) const {
return this->x * w.x + this->y * w.y + this->z * w.z;
}
__host__ __device__ float Vector::dot(const Normal &n) const {
return this->x * n.x + this->y * n.y + this->z * n.z;
}
__host__ __device__ Vector Vector::cross(const Normal &n) const {
return Vector(this->y * n.z - this->z * n.y, this->z * n.x - this->x * n.z, this->x * n.y - this->y * n.x);
}
__host__ __device__ Vector Vector::cross(const Vector &w) const {
return Vector(this->y * w.z - this->z * w.y, this->z * w.x - this->x * w.z, this->x * w.y - this->y * w.x);
}
__host__ __device__ Vector Vector::operator+(float s) const {
return Vector(this->x + s, this->y + s, this->z + s);
}
__host__ __device__ Vector Vector::operator+(const Vector &w) const {
return Vector(this->x + w.x, this->y + w.y, this->z + w.z);
}
__host__ __device__ Vector& Vector::operator+=(float s) {
x += s; y += s; z += s;
return *this;
}
__host__ __device__ Vector& Vector::operator+=(const Vector &v) {
x += v.x; y += v.y; z += v.z;
return *this;
}
__host__ __device__ Vector Vector::operator-(float s) const {
return Vector(this->x - s, this->y - s, this->z - s);
}
__host__ __device__ Vector Vector::operator-(const Vector &w) const {
return Vector(this->x - w.x, this->y - w.y, this->z - w.z);
}
__host__ __device__ Vector& Vector::operator-=(float s) {
x -= s; y -= s; z -= s;
return *this;
}
__host__ __device__ Vector Vector::operator*(float s) const {
return Vector(s * this->x, s * this->y, s * this->z);
}
__host__ __device__ Vector Vector::operator*(const Vector &w) const {
return Vector(this->x * w.x, this->y * w.y, this->z * w.z);
}
__host__ __device__ Vector& Vector::operator*=(float s) {
x *= s; y *= s; z *= s;
return *this;
}
__host__ __device__ Vector Vector::operator/(float s) const {
return Vector(this->x / s, this->y / s, this->z / s);
}
__host__ __device__ Vector Vector::operator/(const Vector &w) const {
return Vector(this->x / w.x, this->y / w.y, this->z / w.z);
}
__host__ __device__ Vector& Vector::operator/=(float s) {
x /= s; y /= s; z /= s;
return *this;
}
__host__ __device__ float Vector::norm() const {
return sqrtf(this->x*this->x + this->y*this->y + this->z*this->z);
}
__host__ __device__ Vector& Vector::normalize() {
*this /= norm();
return *this;
}
__host__ __device__ Vector Vector::normalized() const {
return *this / norm();
}
__host__ __device__ Vector operator-(const Vector &v) {
return Vector(-v.x, -v.y, -v.z);
}
__host__ __device__ Vector operator*(float s, const Vector &v) {
return v*s;
}
__host__ __device__ void coordinateSystem(const Vector &v1, Vector *v2, Vector *v3) {
*v2 = Vector(0);
if (v1.x == 0 && v1.x == 0)
{
v2->x = -v1.z;
}
else {
v2->x = -v1.y;
v2->y = v1.x;
}
*v3 = v1.cross(*v2);
} | .file "tmpxft_0009c3f8_00000000-6_Vector.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2064:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2064:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.align 2
.globl _ZN6VectorC2Ev
.type _ZN6VectorC2Ev, @function
_ZN6VectorC2Ev:
.LFB2028:
.cfi_startproc
endbr64
movl $0x00000000, (%rdi)
movl $0x00000000, 4(%rdi)
movl $0x00000000, 8(%rdi)
ret
.cfi_endproc
.LFE2028:
.size _ZN6VectorC2Ev, .-_ZN6VectorC2Ev
.globl _ZN6VectorC1Ev
.set _ZN6VectorC1Ev,_ZN6VectorC2Ev
.align 2
.globl _ZN6VectorC2Ef
.type _ZN6VectorC2Ef, @function
_ZN6VectorC2Ef:
.LFB2031:
.cfi_startproc
endbr64
movss %xmm0, (%rdi)
movss %xmm0, 4(%rdi)
movss %xmm0, 8(%rdi)
ret
.cfi_endproc
.LFE2031:
.size _ZN6VectorC2Ef, .-_ZN6VectorC2Ef
.globl _ZN6VectorC1Ef
.set _ZN6VectorC1Ef,_ZN6VectorC2Ef
.align 2
.globl _ZN6VectorC2ERKS_
.type _ZN6VectorC2ERKS_, @function
_ZN6VectorC2ERKS_:
.LFB2034:
.cfi_startproc
endbr64
movss (%rsi), %xmm0
movss %xmm0, (%rdi)
movss 4(%rsi), %xmm0
movss %xmm0, 4(%rdi)
movss 8(%rsi), %xmm0
movss %xmm0, 8(%rdi)
ret
.cfi_endproc
.LFE2034:
.size _ZN6VectorC2ERKS_, .-_ZN6VectorC2ERKS_
.globl _ZN6VectorC1ERKS_
.set _ZN6VectorC1ERKS_,_ZN6VectorC2ERKS_
.align 2
.globl _ZN6VectorC2Efff
.type _ZN6VectorC2Efff, @function
_ZN6VectorC2Efff:
.LFB2037:
.cfi_startproc
endbr64
movss %xmm0, (%rdi)
movss %xmm1, 4(%rdi)
movss %xmm2, 8(%rdi)
ret
.cfi_endproc
.LFE2037:
.size _ZN6VectorC2Efff, .-_ZN6VectorC2Efff
.globl _ZN6VectorC1Efff
.set _ZN6VectorC1Efff,_ZN6VectorC2Efff
.align 2
.globl _ZNK6Vector3dotERKS_
.type _ZNK6Vector3dotERKS_, @function
_ZNK6Vector3dotERKS_:
.LFB2039:
.cfi_startproc
endbr64
movss (%rdi), %xmm0
mulss (%rsi), %xmm0
movss 4(%rdi), %xmm1
mulss 4(%rsi), %xmm1
addss %xmm1, %xmm0
movss 8(%rdi), %xmm1
mulss 8(%rsi), %xmm1
addss %xmm1, %xmm0
ret
.cfi_endproc
.LFE2039:
.size _ZNK6Vector3dotERKS_, .-_ZNK6Vector3dotERKS_
.align 2
.globl _ZNK6Vector3dotERK6Normal
.type _ZNK6Vector3dotERK6Normal, @function
_ZNK6Vector3dotERK6Normal:
.LFB2040:
.cfi_startproc
endbr64
movss (%rdi), %xmm0
mulss (%rsi), %xmm0
movss 4(%rdi), %xmm1
mulss 4(%rsi), %xmm1
addss %xmm1, %xmm0
movss 8(%rdi), %xmm1
mulss 8(%rsi), %xmm1
addss %xmm1, %xmm0
ret
.cfi_endproc
.LFE2040:
.size _ZNK6Vector3dotERK6Normal, .-_ZNK6Vector3dotERK6Normal
.align 2
.globl _ZNK6Vector5crossERK6Normal
.type _ZNK6Vector5crossERK6Normal, @function
_ZNK6Vector5crossERK6Normal:
.LFB2041:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movq %rdi, %rbx
movss (%rsi), %xmm3
movss 4(%rdx), %xmm4
movss 4(%rsi), %xmm0
movss (%rdx), %xmm1
movss 8(%rsi), %xmm5
movss 8(%rdx), %xmm6
movaps %xmm3, %xmm2
mulss %xmm4, %xmm2
movaps %xmm0, %xmm7
mulss %xmm1, %xmm7
mulss %xmm5, %xmm1
mulss %xmm6, %xmm3
mulss %xmm6, %xmm0
mulss %xmm5, %xmm4
subss %xmm4, %xmm0
subss %xmm7, %xmm2
subss %xmm3, %xmm1
call _ZN6VectorC1Efff
movq %rbx, %rax
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2041:
.size _ZNK6Vector5crossERK6Normal, .-_ZNK6Vector5crossERK6Normal
.align 2
.globl _ZNK6Vector5crossERKS_
.type _ZNK6Vector5crossERKS_, @function
_ZNK6Vector5crossERKS_:
.LFB2042:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movq %rdi, %rbx
movss (%rsi), %xmm3
movss 4(%rdx), %xmm4
movss 4(%rsi), %xmm0
movss (%rdx), %xmm1
movss 8(%rsi), %xmm5
movss 8(%rdx), %xmm6
movaps %xmm3, %xmm2
mulss %xmm4, %xmm2
movaps %xmm0, %xmm7
mulss %xmm1, %xmm7
mulss %xmm5, %xmm1
mulss %xmm6, %xmm3
mulss %xmm6, %xmm0
mulss %xmm5, %xmm4
subss %xmm4, %xmm0
subss %xmm7, %xmm2
subss %xmm3, %xmm1
call _ZN6VectorC1Efff
movq %rbx, %rax
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2042:
.size _ZNK6Vector5crossERKS_, .-_ZNK6Vector5crossERKS_
.align 2
.globl _ZNK6VectorplEf
.type _ZNK6VectorplEf, @function
_ZNK6VectorplEf:
.LFB2043:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movq %rdi, %rbx
movaps %xmm0, %xmm1
addss (%rsi), %xmm0
movaps %xmm1, %xmm2
addss 8(%rsi), %xmm2
addss 4(%rsi), %xmm1
call _ZN6VectorC1Efff
movq %rbx, %rax
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2043:
.size _ZNK6VectorplEf, .-_ZNK6VectorplEf
.align 2
.globl _ZNK6VectorplERKS_
.type _ZNK6VectorplERKS_, @function
_ZNK6VectorplERKS_:
.LFB2044:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movq %rdi, %rbx
movss 8(%rsi), %xmm2
movss 4(%rsi), %xmm1
movss (%rsi), %xmm0
addss (%rdx), %xmm0
addss 8(%rdx), %xmm2
addss 4(%rdx), %xmm1
call _ZN6VectorC1Efff
movq %rbx, %rax
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2044:
.size _ZNK6VectorplERKS_, .-_ZNK6VectorplERKS_
.align 2
.globl _ZN6VectorpLEf
.type _ZN6VectorpLEf, @function
_ZN6VectorpLEf:
.LFB2045:
.cfi_startproc
endbr64
movq %rdi, %rax
movaps %xmm0, %xmm1
addss (%rdi), %xmm1
movss %xmm1, (%rdi)
movaps %xmm0, %xmm1
addss 4(%rdi), %xmm1
movss %xmm1, 4(%rdi)
addss 8(%rdi), %xmm0
movss %xmm0, 8(%rdi)
ret
.cfi_endproc
.LFE2045:
.size _ZN6VectorpLEf, .-_ZN6VectorpLEf
.align 2
.globl _ZN6VectorpLERKS_
.type _ZN6VectorpLERKS_, @function
_ZN6VectorpLERKS_:
.LFB2046:
.cfi_startproc
endbr64
movq %rdi, %rax
movss (%rdi), %xmm0
addss (%rsi), %xmm0
movss %xmm0, (%rdi)
movss 4(%rdi), %xmm0
addss 4(%rsi), %xmm0
movss %xmm0, 4(%rdi)
movss 8(%rdi), %xmm0
addss 8(%rsi), %xmm0
movss %xmm0, 8(%rdi)
ret
.cfi_endproc
.LFE2046:
.size _ZN6VectorpLERKS_, .-_ZN6VectorpLERKS_
.align 2
.globl _ZNK6VectormiEf
.type _ZNK6VectormiEf, @function
_ZNK6VectormiEf:
.LFB2047:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movq %rdi, %rbx
movaps %xmm0, %xmm3
movss 8(%rsi), %xmm2
movss 4(%rsi), %xmm1
movss (%rsi), %xmm0
subss %xmm3, %xmm0
subss %xmm3, %xmm2
subss %xmm3, %xmm1
call _ZN6VectorC1Efff
movq %rbx, %rax
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2047:
.size _ZNK6VectormiEf, .-_ZNK6VectormiEf
.align 2
.globl _ZNK6VectormiERKS_
.type _ZNK6VectormiERKS_, @function
_ZNK6VectormiERKS_:
.LFB2048:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movq %rdi, %rbx
movss 8(%rsi), %xmm2
movss 4(%rsi), %xmm1
movss (%rsi), %xmm0
subss (%rdx), %xmm0
subss 8(%rdx), %xmm2
subss 4(%rdx), %xmm1
call _ZN6VectorC1Efff
movq %rbx, %rax
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2048:
.size _ZNK6VectormiERKS_, .-_ZNK6VectormiERKS_
.align 2
.globl _ZN6VectormIEf
.type _ZN6VectormIEf, @function
_ZN6VectormIEf:
.LFB2049:
.cfi_startproc
endbr64
movq %rdi, %rax
movss (%rdi), %xmm1
subss %xmm0, %xmm1
movss %xmm1, (%rdi)
movss 4(%rdi), %xmm1
subss %xmm0, %xmm1
movss %xmm1, 4(%rdi)
movss 8(%rdi), %xmm1
subss %xmm0, %xmm1
movss %xmm1, 8(%rdi)
ret
.cfi_endproc
.LFE2049:
.size _ZN6VectormIEf, .-_ZN6VectormIEf
.align 2
.globl _ZNK6VectormlEf
.type _ZNK6VectormlEf, @function
_ZNK6VectormlEf:
.LFB2050:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movq %rdi, %rbx
movaps %xmm0, %xmm1
mulss (%rsi), %xmm0
movaps %xmm1, %xmm2
mulss 8(%rsi), %xmm2
mulss 4(%rsi), %xmm1
call _ZN6VectorC1Efff
movq %rbx, %rax
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2050:
.size _ZNK6VectormlEf, .-_ZNK6VectormlEf
.align 2
.globl _ZNK6VectormlERKS_
.type _ZNK6VectormlERKS_, @function
_ZNK6VectormlERKS_:
.LFB2051:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movq %rdi, %rbx
movss 8(%rsi), %xmm2
movss 4(%rsi), %xmm1
movss (%rsi), %xmm0
mulss (%rdx), %xmm0
mulss 8(%rdx), %xmm2
mulss 4(%rdx), %xmm1
call _ZN6VectorC1Efff
movq %rbx, %rax
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2051:
.size _ZNK6VectormlERKS_, .-_ZNK6VectormlERKS_
.align 2
.globl _ZN6VectormLEf
.type _ZN6VectormLEf, @function
_ZN6VectormLEf:
.LFB2052:
.cfi_startproc
endbr64
movq %rdi, %rax
movaps %xmm0, %xmm1
mulss (%rdi), %xmm1
movss %xmm1, (%rdi)
movaps %xmm0, %xmm1
mulss 4(%rdi), %xmm1
movss %xmm1, 4(%rdi)
mulss 8(%rdi), %xmm0
movss %xmm0, 8(%rdi)
ret
.cfi_endproc
.LFE2052:
.size _ZN6VectormLEf, .-_ZN6VectormLEf
.align 2
.globl _ZNK6VectordvEf
.type _ZNK6VectordvEf, @function
_ZNK6VectordvEf:
.LFB2053:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movq %rdi, %rbx
movaps %xmm0, %xmm3
movss 8(%rsi), %xmm2
movss 4(%rsi), %xmm1
movss (%rsi), %xmm0
divss %xmm3, %xmm0
divss %xmm3, %xmm2
divss %xmm3, %xmm1
call _ZN6VectorC1Efff
movq %rbx, %rax
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _ZNK6VectordvEf, .-_ZNK6VectordvEf
.align 2
.globl _ZNK6VectordvERKS_
.type _ZNK6VectordvERKS_, @function
_ZNK6VectordvERKS_:
.LFB2054:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movq %rdi, %rbx
movss 8(%rsi), %xmm2
movss 4(%rsi), %xmm1
movss (%rsi), %xmm0
divss (%rdx), %xmm0
divss 8(%rdx), %xmm2
divss 4(%rdx), %xmm1
call _ZN6VectorC1Efff
movq %rbx, %rax
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZNK6VectordvERKS_, .-_ZNK6VectordvERKS_
.align 2
.globl _ZN6VectordVEf
.type _ZN6VectordVEf, @function
_ZN6VectordVEf:
.LFB2055:
.cfi_startproc
endbr64
movq %rdi, %rax
movss (%rdi), %xmm1
divss %xmm0, %xmm1
movss %xmm1, (%rdi)
movss 4(%rdi), %xmm1
divss %xmm0, %xmm1
movss %xmm1, 4(%rdi)
movss 8(%rdi), %xmm1
divss %xmm0, %xmm1
movss %xmm1, 8(%rdi)
ret
.cfi_endproc
.LFE2055:
.size _ZN6VectordVEf, .-_ZN6VectordVEf
.align 2
.globl _ZNK6Vector4normEv
.type _ZNK6Vector4normEv, @function
_ZNK6Vector4normEv:
.LFB2056:
.cfi_startproc
endbr64
movss (%rdi), %xmm0
movss 4(%rdi), %xmm2
movss 8(%rdi), %xmm1
mulss %xmm0, %xmm0
mulss %xmm2, %xmm2
addss %xmm2, %xmm0
mulss %xmm1, %xmm1
addss %xmm1, %xmm0
sqrtss %xmm0, %xmm0
ret
.cfi_endproc
.LFE2056:
.size _ZNK6Vector4normEv, .-_ZNK6Vector4normEv
.align 2
.globl _ZN6Vector9normalizeEv
.type _ZN6Vector9normalizeEv, @function
_ZN6Vector9normalizeEv:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movq %rdi, %rbx
call _ZNK6Vector4normEv
movq %rbx, %rdi
call _ZN6VectordVEf
movq %rbx, %rax
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _ZN6Vector9normalizeEv, .-_ZN6Vector9normalizeEv
.align 2
.globl _ZNK6Vector10normalizedEv
.type _ZNK6Vector10normalizedEv, @function
_ZNK6Vector10normalizedEv:
.LFB2058:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $24, %rsp
.cfi_def_cfa_offset 48
movq %rdi, %rbp
movq %rsi, %rbx
movq %fs:40, %rax
movq %rax, 8(%rsp)
xorl %eax, %eax
movq %rsi, %rdi
call _ZNK6Vector4normEv
movq %rbx, %rsi
movq %rbp, %rdi
call _ZNK6VectordvEf
movq 8(%rsp), %rax
subq %fs:40, %rax
jne .L40
movq %rbp, %rax
addq $24, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L40:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size _ZNK6Vector10normalizedEv, .-_ZNK6Vector10normalizedEv
.globl _ZngRK6Vector
.type _ZngRK6Vector, @function
_ZngRK6Vector:
.LFB2059:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movq %rdi, %rbx
movss 8(%rsi), %xmm2
movss .LC1(%rip), %xmm3
xorps %xmm3, %xmm2
movss 4(%rsi), %xmm1
xorps %xmm3, %xmm1
movss (%rsi), %xmm0
xorps %xmm3, %xmm0
call _ZN6VectorC1Efff
movq %rbx, %rax
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size _ZngRK6Vector, .-_ZngRK6Vector
.globl _ZmlfRK6Vector
.type _ZmlfRK6Vector, @function
_ZmlfRK6Vector:
.LFB2060:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $16, %rsp
.cfi_def_cfa_offset 32
movq %rdi, %rbx
movq %fs:40, %rax
movq %rax, 8(%rsp)
xorl %eax, %eax
call _ZNK6VectormlEf
movq 8(%rsp), %rax
subq %fs:40, %rax
jne .L46
movq %rbx, %rax
addq $16, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L46:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2060:
.size _ZmlfRK6Vector, .-_ZmlfRK6Vector
.globl _Z16coordinateSystemRK6VectorPS_S2_
.type _Z16coordinateSystemRK6VectorPS_S2_, @function
_Z16coordinateSystemRK6VectorPS_S2_:
.LFB2061:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $32, %rsp
.cfi_def_cfa_offset 64
movq %rdi, %rbx
movq %rsi, %rbp
movq %rdx, %r12
movq %fs:40, %rax
movq %rax, 24(%rsp)
xorl %eax, %eax
movq %rsp, %rdi
pxor %xmm0, %xmm0
call _ZN6VectorC1Ef
movdqa (%rsp), %xmm1
movups %xmm1, 0(%rbp)
pxor %xmm0, %xmm0
ucomiss (%rbx), %xmm0
jp .L48
jne .L48
movss 8(%rbx), %xmm0
xorps .LC1(%rip), %xmm0
movss %xmm0, 0(%rbp)
.L50:
movq %rsp, %rdi
movq %rbp, %rdx
movq %rbx, %rsi
call _ZNK6Vector5crossERKS_
movdqa (%rsp), %xmm2
movups %xmm2, (%r12)
movq 24(%rsp), %rax
subq %fs:40, %rax
jne .L54
addq $32, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L48:
.cfi_restore_state
movss 4(%rbx), %xmm0
xorps .LC1(%rip), %xmm0
movss %xmm0, 0(%rbp)
movss (%rbx), %xmm0
movss %xmm0, 4(%rbp)
jmp .L50
.L54:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2061:
.size _Z16coordinateSystemRK6VectorPS_S2_, .-_Z16coordinateSystemRK6VectorPS_S2_
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst16,"aM",@progbits,16
.align 16
.LC1:
.long -2147483648
.long 0
.long 0
.long 0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "Vector.cuh"
#include "Normal.cuh"
__host__ __device__ Vector::Vector() :
x(0.0), y(0.0), z(0.0) { }
__host__ __device__ Vector::Vector(float v) :
x(v), y(v), z(v) {}
__host__ __device__ Vector::Vector(const Vector &w) :
x(w.x), y(w.y), z(w.z) { }
__host__ __device__ Vector::Vector(float xx, float yy, float zz) :
x(xx), y(yy), z(zz) { }
__host__ __device__ float Vector::dot(const Vector &w) const {
return this->x * w.x + this->y * w.y + this->z * w.z;
}
__host__ __device__ float Vector::dot(const Normal &n) const {
return this->x * n.x + this->y * n.y + this->z * n.z;
}
__host__ __device__ Vector Vector::cross(const Normal &n) const {
return Vector(this->y * n.z - this->z * n.y, this->z * n.x - this->x * n.z, this->x * n.y - this->y * n.x);
}
__host__ __device__ Vector Vector::cross(const Vector &w) const {
return Vector(this->y * w.z - this->z * w.y, this->z * w.x - this->x * w.z, this->x * w.y - this->y * w.x);
}
__host__ __device__ Vector Vector::operator+(float s) const {
return Vector(this->x + s, this->y + s, this->z + s);
}
__host__ __device__ Vector Vector::operator+(const Vector &w) const {
return Vector(this->x + w.x, this->y + w.y, this->z + w.z);
}
__host__ __device__ Vector& Vector::operator+=(float s) {
x += s; y += s; z += s;
return *this;
}
__host__ __device__ Vector& Vector::operator+=(const Vector &v) {
x += v.x; y += v.y; z += v.z;
return *this;
}
__host__ __device__ Vector Vector::operator-(float s) const {
return Vector(this->x - s, this->y - s, this->z - s);
}
__host__ __device__ Vector Vector::operator-(const Vector &w) const {
return Vector(this->x - w.x, this->y - w.y, this->z - w.z);
}
__host__ __device__ Vector& Vector::operator-=(float s) {
x -= s; y -= s; z -= s;
return *this;
}
__host__ __device__ Vector Vector::operator*(float s) const {
return Vector(s * this->x, s * this->y, s * this->z);
}
__host__ __device__ Vector Vector::operator*(const Vector &w) const {
return Vector(this->x * w.x, this->y * w.y, this->z * w.z);
}
__host__ __device__ Vector& Vector::operator*=(float s) {
x *= s; y *= s; z *= s;
return *this;
}
__host__ __device__ Vector Vector::operator/(float s) const {
return Vector(this->x / s, this->y / s, this->z / s);
}
__host__ __device__ Vector Vector::operator/(const Vector &w) const {
return Vector(this->x / w.x, this->y / w.y, this->z / w.z);
}
__host__ __device__ Vector& Vector::operator/=(float s) {
x /= s; y /= s; z /= s;
return *this;
}
__host__ __device__ float Vector::norm() const {
return sqrtf(this->x*this->x + this->y*this->y + this->z*this->z);
}
__host__ __device__ Vector& Vector::normalize() {
*this /= norm();
return *this;
}
__host__ __device__ Vector Vector::normalized() const {
return *this / norm();
}
__host__ __device__ Vector operator-(const Vector &v) {
return Vector(-v.x, -v.y, -v.z);
}
__host__ __device__ Vector operator*(float s, const Vector &v) {
return v*s;
}
__host__ __device__ void coordinateSystem(const Vector &v1, Vector *v2, Vector *v3) {
*v2 = Vector(0);
if (v1.x == 0 && v1.x == 0)
{
v2->x = -v1.z;
}
else {
v2->x = -v1.y;
v2->y = v1.x;
}
*v3 = v1.cross(*v2);
} | //
// Created by Neil on 01/04/2017.
//
#ifndef CUDARENDERER_Vector_H
#define CUDARENDERER_Vector_H
#include <hip/hip_runtime.h>
#include <hip/hip_runtime_api.h>
#include <cmath>
class Normal;
class Vector {
public:
float x;
float y;
float z;
float padding;
__host__ __device__ Vector();
__host__ __device__ Vector(float v);
__host__ __device__ Vector(const Vector &w);
__host__ __device__ Vector(float xx, float yy, float zz);
__host__ __device__ float dot(const Vector &w) const;
__host__ __device__ float dot(const Normal &n) const;
__host__ __device__ Vector cross(const Vector &w) const;
__host__ __device__ Vector cross(const Normal &n) const;
__host__ __device__ Vector operator+(float s) const;
__host__ __device__ Vector operator+(const Vector &w) const;
__host__ __device__ Vector& operator+=(float s);
__host__ __device__ Vector& operator+=(const Vector &v);
__host__ __device__ Vector operator-(float s) const;
__host__ __device__ Vector operator-(const Vector &w) const;
__host__ __device__ Vector& operator-=(float s);
__host__ __device__ Vector operator*(float s) const;
__host__ __device__ Vector operator*(const Vector &w) const;
__host__ __device__ Vector& operator*=(float s);
__host__ __device__ Vector operator/(float s) const;
__host__ __device__ Vector operator/(const Vector &w) const;
__host__ __device__ Vector& operator/=(float s);
__host__ __device__ float norm() const;
__host__ __device__ Vector& normalize();
__host__ __device__ Vector normalized() const;
};
__host__ __device__ Vector operator-(const Vector &v);
__host__ __device__ Vector operator*(float s, const Vector &v);
__host__ __device__ void coordinateSystem(const Vector &v1, Vector *v2, Vector *v3);
#endif //CUDARENDERER_Vector_H |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | //
// Created by Neil on 01/04/2017.
//
#ifndef CUDARENDERER_Vector_H
#define CUDARENDERER_Vector_H
#include <hip/hip_runtime.h>
#include <hip/hip_runtime_api.h>
#include <cmath>
class Normal;
class Vector {
public:
float x;
float y;
float z;
float padding;
__host__ __device__ Vector();
__host__ __device__ Vector(float v);
__host__ __device__ Vector(const Vector &w);
__host__ __device__ Vector(float xx, float yy, float zz);
__host__ __device__ float dot(const Vector &w) const;
__host__ __device__ float dot(const Normal &n) const;
__host__ __device__ Vector cross(const Vector &w) const;
__host__ __device__ Vector cross(const Normal &n) const;
__host__ __device__ Vector operator+(float s) const;
__host__ __device__ Vector operator+(const Vector &w) const;
__host__ __device__ Vector& operator+=(float s);
__host__ __device__ Vector& operator+=(const Vector &v);
__host__ __device__ Vector operator-(float s) const;
__host__ __device__ Vector operator-(const Vector &w) const;
__host__ __device__ Vector& operator-=(float s);
__host__ __device__ Vector operator*(float s) const;
__host__ __device__ Vector operator*(const Vector &w) const;
__host__ __device__ Vector& operator*=(float s);
__host__ __device__ Vector operator/(float s) const;
__host__ __device__ Vector operator/(const Vector &w) const;
__host__ __device__ Vector& operator/=(float s);
__host__ __device__ float norm() const;
__host__ __device__ Vector& normalize();
__host__ __device__ Vector normalized() const;
};
__host__ __device__ Vector operator-(const Vector &v);
__host__ __device__ Vector operator*(float s, const Vector &v);
__host__ __device__ void coordinateSystem(const Vector &v1, Vector *v2, Vector *v3);
#endif //CUDARENDERER_Vector_H | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | //
// Created by Neil on 01/04/2017.
//
#ifndef CUDARENDERER_Vector_H
#define CUDARENDERER_Vector_H
#include <hip/hip_runtime.h>
#include <hip/hip_runtime_api.h>
#include <cmath>
class Normal;
class Vector {
public:
float x;
float y;
float z;
float padding;
__host__ __device__ Vector();
__host__ __device__ Vector(float v);
__host__ __device__ Vector(const Vector &w);
__host__ __device__ Vector(float xx, float yy, float zz);
__host__ __device__ float dot(const Vector &w) const;
__host__ __device__ float dot(const Normal &n) const;
__host__ __device__ Vector cross(const Vector &w) const;
__host__ __device__ Vector cross(const Normal &n) const;
__host__ __device__ Vector operator+(float s) const;
__host__ __device__ Vector operator+(const Vector &w) const;
__host__ __device__ Vector& operator+=(float s);
__host__ __device__ Vector& operator+=(const Vector &v);
__host__ __device__ Vector operator-(float s) const;
__host__ __device__ Vector operator-(const Vector &w) const;
__host__ __device__ Vector& operator-=(float s);
__host__ __device__ Vector operator*(float s) const;
__host__ __device__ Vector operator*(const Vector &w) const;
__host__ __device__ Vector& operator*=(float s);
__host__ __device__ Vector operator/(float s) const;
__host__ __device__ Vector operator/(const Vector &w) const;
__host__ __device__ Vector& operator/=(float s);
__host__ __device__ float norm() const;
__host__ __device__ Vector& normalize();
__host__ __device__ Vector normalized() const;
};
__host__ __device__ Vector operator-(const Vector &v);
__host__ __device__ Vector operator*(float s, const Vector &v);
__host__ __device__ void coordinateSystem(const Vector &v1, Vector *v2, Vector *v3);
#endif //CUDARENDERER_Vector_H | .text
.file "Vector.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0009c3f8_00000000-6_Vector.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2064:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2064:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.align 2
.globl _ZN6VectorC2Ev
.type _ZN6VectorC2Ev, @function
_ZN6VectorC2Ev:
.LFB2028:
.cfi_startproc
endbr64
movl $0x00000000, (%rdi)
movl $0x00000000, 4(%rdi)
movl $0x00000000, 8(%rdi)
ret
.cfi_endproc
.LFE2028:
.size _ZN6VectorC2Ev, .-_ZN6VectorC2Ev
.globl _ZN6VectorC1Ev
.set _ZN6VectorC1Ev,_ZN6VectorC2Ev
.align 2
.globl _ZN6VectorC2Ef
.type _ZN6VectorC2Ef, @function
_ZN6VectorC2Ef:
.LFB2031:
.cfi_startproc
endbr64
movss %xmm0, (%rdi)
movss %xmm0, 4(%rdi)
movss %xmm0, 8(%rdi)
ret
.cfi_endproc
.LFE2031:
.size _ZN6VectorC2Ef, .-_ZN6VectorC2Ef
.globl _ZN6VectorC1Ef
.set _ZN6VectorC1Ef,_ZN6VectorC2Ef
.align 2
.globl _ZN6VectorC2ERKS_
.type _ZN6VectorC2ERKS_, @function
_ZN6VectorC2ERKS_:
.LFB2034:
.cfi_startproc
endbr64
movss (%rsi), %xmm0
movss %xmm0, (%rdi)
movss 4(%rsi), %xmm0
movss %xmm0, 4(%rdi)
movss 8(%rsi), %xmm0
movss %xmm0, 8(%rdi)
ret
.cfi_endproc
.LFE2034:
.size _ZN6VectorC2ERKS_, .-_ZN6VectorC2ERKS_
.globl _ZN6VectorC1ERKS_
.set _ZN6VectorC1ERKS_,_ZN6VectorC2ERKS_
.align 2
.globl _ZN6VectorC2Efff
.type _ZN6VectorC2Efff, @function
_ZN6VectorC2Efff:
.LFB2037:
.cfi_startproc
endbr64
movss %xmm0, (%rdi)
movss %xmm1, 4(%rdi)
movss %xmm2, 8(%rdi)
ret
.cfi_endproc
.LFE2037:
.size _ZN6VectorC2Efff, .-_ZN6VectorC2Efff
.globl _ZN6VectorC1Efff
.set _ZN6VectorC1Efff,_ZN6VectorC2Efff
.align 2
.globl _ZNK6Vector3dotERKS_
.type _ZNK6Vector3dotERKS_, @function
_ZNK6Vector3dotERKS_:
.LFB2039:
.cfi_startproc
endbr64
movss (%rdi), %xmm0
mulss (%rsi), %xmm0
movss 4(%rdi), %xmm1
mulss 4(%rsi), %xmm1
addss %xmm1, %xmm0
movss 8(%rdi), %xmm1
mulss 8(%rsi), %xmm1
addss %xmm1, %xmm0
ret
.cfi_endproc
.LFE2039:
.size _ZNK6Vector3dotERKS_, .-_ZNK6Vector3dotERKS_
.align 2
.globl _ZNK6Vector3dotERK6Normal
.type _ZNK6Vector3dotERK6Normal, @function
_ZNK6Vector3dotERK6Normal:
.LFB2040:
.cfi_startproc
endbr64
movss (%rdi), %xmm0
mulss (%rsi), %xmm0
movss 4(%rdi), %xmm1
mulss 4(%rsi), %xmm1
addss %xmm1, %xmm0
movss 8(%rdi), %xmm1
mulss 8(%rsi), %xmm1
addss %xmm1, %xmm0
ret
.cfi_endproc
.LFE2040:
.size _ZNK6Vector3dotERK6Normal, .-_ZNK6Vector3dotERK6Normal
.align 2
.globl _ZNK6Vector5crossERK6Normal
.type _ZNK6Vector5crossERK6Normal, @function
_ZNK6Vector5crossERK6Normal:
.LFB2041:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movq %rdi, %rbx
movss (%rsi), %xmm3
movss 4(%rdx), %xmm4
movss 4(%rsi), %xmm0
movss (%rdx), %xmm1
movss 8(%rsi), %xmm5
movss 8(%rdx), %xmm6
movaps %xmm3, %xmm2
mulss %xmm4, %xmm2
movaps %xmm0, %xmm7
mulss %xmm1, %xmm7
mulss %xmm5, %xmm1
mulss %xmm6, %xmm3
mulss %xmm6, %xmm0
mulss %xmm5, %xmm4
subss %xmm4, %xmm0
subss %xmm7, %xmm2
subss %xmm3, %xmm1
call _ZN6VectorC1Efff
movq %rbx, %rax
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2041:
.size _ZNK6Vector5crossERK6Normal, .-_ZNK6Vector5crossERK6Normal
.align 2
.globl _ZNK6Vector5crossERKS_
.type _ZNK6Vector5crossERKS_, @function
_ZNK6Vector5crossERKS_:
.LFB2042:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movq %rdi, %rbx
movss (%rsi), %xmm3
movss 4(%rdx), %xmm4
movss 4(%rsi), %xmm0
movss (%rdx), %xmm1
movss 8(%rsi), %xmm5
movss 8(%rdx), %xmm6
movaps %xmm3, %xmm2
mulss %xmm4, %xmm2
movaps %xmm0, %xmm7
mulss %xmm1, %xmm7
mulss %xmm5, %xmm1
mulss %xmm6, %xmm3
mulss %xmm6, %xmm0
mulss %xmm5, %xmm4
subss %xmm4, %xmm0
subss %xmm7, %xmm2
subss %xmm3, %xmm1
call _ZN6VectorC1Efff
movq %rbx, %rax
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2042:
.size _ZNK6Vector5crossERKS_, .-_ZNK6Vector5crossERKS_
.align 2
.globl _ZNK6VectorplEf
.type _ZNK6VectorplEf, @function
_ZNK6VectorplEf:
.LFB2043:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movq %rdi, %rbx
movaps %xmm0, %xmm1
addss (%rsi), %xmm0
movaps %xmm1, %xmm2
addss 8(%rsi), %xmm2
addss 4(%rsi), %xmm1
call _ZN6VectorC1Efff
movq %rbx, %rax
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2043:
.size _ZNK6VectorplEf, .-_ZNK6VectorplEf
.align 2
.globl _ZNK6VectorplERKS_
.type _ZNK6VectorplERKS_, @function
_ZNK6VectorplERKS_:
.LFB2044:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movq %rdi, %rbx
movss 8(%rsi), %xmm2
movss 4(%rsi), %xmm1
movss (%rsi), %xmm0
addss (%rdx), %xmm0
addss 8(%rdx), %xmm2
addss 4(%rdx), %xmm1
call _ZN6VectorC1Efff
movq %rbx, %rax
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2044:
.size _ZNK6VectorplERKS_, .-_ZNK6VectorplERKS_
.align 2
.globl _ZN6VectorpLEf
.type _ZN6VectorpLEf, @function
_ZN6VectorpLEf:
.LFB2045:
.cfi_startproc
endbr64
movq %rdi, %rax
movaps %xmm0, %xmm1
addss (%rdi), %xmm1
movss %xmm1, (%rdi)
movaps %xmm0, %xmm1
addss 4(%rdi), %xmm1
movss %xmm1, 4(%rdi)
addss 8(%rdi), %xmm0
movss %xmm0, 8(%rdi)
ret
.cfi_endproc
.LFE2045:
.size _ZN6VectorpLEf, .-_ZN6VectorpLEf
.align 2
.globl _ZN6VectorpLERKS_
.type _ZN6VectorpLERKS_, @function
_ZN6VectorpLERKS_:
.LFB2046:
.cfi_startproc
endbr64
movq %rdi, %rax
movss (%rdi), %xmm0
addss (%rsi), %xmm0
movss %xmm0, (%rdi)
movss 4(%rdi), %xmm0
addss 4(%rsi), %xmm0
movss %xmm0, 4(%rdi)
movss 8(%rdi), %xmm0
addss 8(%rsi), %xmm0
movss %xmm0, 8(%rdi)
ret
.cfi_endproc
.LFE2046:
.size _ZN6VectorpLERKS_, .-_ZN6VectorpLERKS_
.align 2
.globl _ZNK6VectormiEf
.type _ZNK6VectormiEf, @function
_ZNK6VectormiEf:
.LFB2047:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movq %rdi, %rbx
movaps %xmm0, %xmm3
movss 8(%rsi), %xmm2
movss 4(%rsi), %xmm1
movss (%rsi), %xmm0
subss %xmm3, %xmm0
subss %xmm3, %xmm2
subss %xmm3, %xmm1
call _ZN6VectorC1Efff
movq %rbx, %rax
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2047:
.size _ZNK6VectormiEf, .-_ZNK6VectormiEf
.align 2
.globl _ZNK6VectormiERKS_
.type _ZNK6VectormiERKS_, @function
_ZNK6VectormiERKS_:
.LFB2048:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movq %rdi, %rbx
movss 8(%rsi), %xmm2
movss 4(%rsi), %xmm1
movss (%rsi), %xmm0
subss (%rdx), %xmm0
subss 8(%rdx), %xmm2
subss 4(%rdx), %xmm1
call _ZN6VectorC1Efff
movq %rbx, %rax
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2048:
.size _ZNK6VectormiERKS_, .-_ZNK6VectormiERKS_
.align 2
.globl _ZN6VectormIEf
.type _ZN6VectormIEf, @function
_ZN6VectormIEf:
.LFB2049:
.cfi_startproc
endbr64
movq %rdi, %rax
movss (%rdi), %xmm1
subss %xmm0, %xmm1
movss %xmm1, (%rdi)
movss 4(%rdi), %xmm1
subss %xmm0, %xmm1
movss %xmm1, 4(%rdi)
movss 8(%rdi), %xmm1
subss %xmm0, %xmm1
movss %xmm1, 8(%rdi)
ret
.cfi_endproc
.LFE2049:
.size _ZN6VectormIEf, .-_ZN6VectormIEf
.align 2
.globl _ZNK6VectormlEf
.type _ZNK6VectormlEf, @function
_ZNK6VectormlEf:
.LFB2050:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movq %rdi, %rbx
movaps %xmm0, %xmm1
mulss (%rsi), %xmm0
movaps %xmm1, %xmm2
mulss 8(%rsi), %xmm2
mulss 4(%rsi), %xmm1
call _ZN6VectorC1Efff
movq %rbx, %rax
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2050:
.size _ZNK6VectormlEf, .-_ZNK6VectormlEf
.align 2
.globl _ZNK6VectormlERKS_
.type _ZNK6VectormlERKS_, @function
_ZNK6VectormlERKS_:
.LFB2051:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movq %rdi, %rbx
movss 8(%rsi), %xmm2
movss 4(%rsi), %xmm1
movss (%rsi), %xmm0
mulss (%rdx), %xmm0
mulss 8(%rdx), %xmm2
mulss 4(%rdx), %xmm1
call _ZN6VectorC1Efff
movq %rbx, %rax
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2051:
.size _ZNK6VectormlERKS_, .-_ZNK6VectormlERKS_
.align 2
.globl _ZN6VectormLEf
.type _ZN6VectormLEf, @function
_ZN6VectormLEf:
.LFB2052:
.cfi_startproc
endbr64
movq %rdi, %rax
movaps %xmm0, %xmm1
mulss (%rdi), %xmm1
movss %xmm1, (%rdi)
movaps %xmm0, %xmm1
mulss 4(%rdi), %xmm1
movss %xmm1, 4(%rdi)
mulss 8(%rdi), %xmm0
movss %xmm0, 8(%rdi)
ret
.cfi_endproc
.LFE2052:
.size _ZN6VectormLEf, .-_ZN6VectormLEf
.align 2
.globl _ZNK6VectordvEf
.type _ZNK6VectordvEf, @function
_ZNK6VectordvEf:
.LFB2053:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movq %rdi, %rbx
movaps %xmm0, %xmm3
movss 8(%rsi), %xmm2
movss 4(%rsi), %xmm1
movss (%rsi), %xmm0
divss %xmm3, %xmm0
divss %xmm3, %xmm2
divss %xmm3, %xmm1
call _ZN6VectorC1Efff
movq %rbx, %rax
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _ZNK6VectordvEf, .-_ZNK6VectordvEf
.align 2
.globl _ZNK6VectordvERKS_
.type _ZNK6VectordvERKS_, @function
_ZNK6VectordvERKS_:
.LFB2054:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movq %rdi, %rbx
movss 8(%rsi), %xmm2
movss 4(%rsi), %xmm1
movss (%rsi), %xmm0
divss (%rdx), %xmm0
divss 8(%rdx), %xmm2
divss 4(%rdx), %xmm1
call _ZN6VectorC1Efff
movq %rbx, %rax
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZNK6VectordvERKS_, .-_ZNK6VectordvERKS_
.align 2
.globl _ZN6VectordVEf
.type _ZN6VectordVEf, @function
_ZN6VectordVEf:
.LFB2055:
.cfi_startproc
endbr64
movq %rdi, %rax
movss (%rdi), %xmm1
divss %xmm0, %xmm1
movss %xmm1, (%rdi)
movss 4(%rdi), %xmm1
divss %xmm0, %xmm1
movss %xmm1, 4(%rdi)
movss 8(%rdi), %xmm1
divss %xmm0, %xmm1
movss %xmm1, 8(%rdi)
ret
.cfi_endproc
.LFE2055:
.size _ZN6VectordVEf, .-_ZN6VectordVEf
.align 2
.globl _ZNK6Vector4normEv
.type _ZNK6Vector4normEv, @function
_ZNK6Vector4normEv:
.LFB2056:
.cfi_startproc
endbr64
movss (%rdi), %xmm0
movss 4(%rdi), %xmm2
movss 8(%rdi), %xmm1
mulss %xmm0, %xmm0
mulss %xmm2, %xmm2
addss %xmm2, %xmm0
mulss %xmm1, %xmm1
addss %xmm1, %xmm0
sqrtss %xmm0, %xmm0
ret
.cfi_endproc
.LFE2056:
.size _ZNK6Vector4normEv, .-_ZNK6Vector4normEv
.align 2
.globl _ZN6Vector9normalizeEv
.type _ZN6Vector9normalizeEv, @function
_ZN6Vector9normalizeEv:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movq %rdi, %rbx
call _ZNK6Vector4normEv
movq %rbx, %rdi
call _ZN6VectordVEf
movq %rbx, %rax
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _ZN6Vector9normalizeEv, .-_ZN6Vector9normalizeEv
.align 2
.globl _ZNK6Vector10normalizedEv
.type _ZNK6Vector10normalizedEv, @function
_ZNK6Vector10normalizedEv:
.LFB2058:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $24, %rsp
.cfi_def_cfa_offset 48
movq %rdi, %rbp
movq %rsi, %rbx
movq %fs:40, %rax
movq %rax, 8(%rsp)
xorl %eax, %eax
movq %rsi, %rdi
call _ZNK6Vector4normEv
movq %rbx, %rsi
movq %rbp, %rdi
call _ZNK6VectordvEf
movq 8(%rsp), %rax
subq %fs:40, %rax
jne .L40
movq %rbp, %rax
addq $24, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L40:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size _ZNK6Vector10normalizedEv, .-_ZNK6Vector10normalizedEv
.globl _ZngRK6Vector
.type _ZngRK6Vector, @function
_ZngRK6Vector:
.LFB2059:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movq %rdi, %rbx
movss 8(%rsi), %xmm2
movss .LC1(%rip), %xmm3
xorps %xmm3, %xmm2
movss 4(%rsi), %xmm1
xorps %xmm3, %xmm1
movss (%rsi), %xmm0
xorps %xmm3, %xmm0
call _ZN6VectorC1Efff
movq %rbx, %rax
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size _ZngRK6Vector, .-_ZngRK6Vector
.globl _ZmlfRK6Vector
.type _ZmlfRK6Vector, @function
_ZmlfRK6Vector:
.LFB2060:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $16, %rsp
.cfi_def_cfa_offset 32
movq %rdi, %rbx
movq %fs:40, %rax
movq %rax, 8(%rsp)
xorl %eax, %eax
call _ZNK6VectormlEf
movq 8(%rsp), %rax
subq %fs:40, %rax
jne .L46
movq %rbx, %rax
addq $16, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L46:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2060:
.size _ZmlfRK6Vector, .-_ZmlfRK6Vector
.globl _Z16coordinateSystemRK6VectorPS_S2_
.type _Z16coordinateSystemRK6VectorPS_S2_, @function
_Z16coordinateSystemRK6VectorPS_S2_:
.LFB2061:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $32, %rsp
.cfi_def_cfa_offset 64
movq %rdi, %rbx
movq %rsi, %rbp
movq %rdx, %r12
movq %fs:40, %rax
movq %rax, 24(%rsp)
xorl %eax, %eax
movq %rsp, %rdi
pxor %xmm0, %xmm0
call _ZN6VectorC1Ef
movdqa (%rsp), %xmm1
movups %xmm1, 0(%rbp)
pxor %xmm0, %xmm0
ucomiss (%rbx), %xmm0
jp .L48
jne .L48
movss 8(%rbx), %xmm0
xorps .LC1(%rip), %xmm0
movss %xmm0, 0(%rbp)
.L50:
movq %rsp, %rdi
movq %rbp, %rdx
movq %rbx, %rsi
call _ZNK6Vector5crossERKS_
movdqa (%rsp), %xmm2
movups %xmm2, (%r12)
movq 24(%rsp), %rax
subq %fs:40, %rax
jne .L54
addq $32, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L48:
.cfi_restore_state
movss 4(%rbx), %xmm0
xorps .LC1(%rip), %xmm0
movss %xmm0, 0(%rbp)
movss (%rbx), %xmm0
movss %xmm0, 4(%rbp)
jmp .L50
.L54:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2061:
.size _Z16coordinateSystemRK6VectorPS_S2_, .-_Z16coordinateSystemRK6VectorPS_S2_
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst16,"aM",@progbits,16
.align 16
.LC1:
.long -2147483648
.long 0
.long 0
.long 0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "Vector.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "cuda.h"
#include "stdio.h"
#include "stdlib.h"
#define LBLK 8
__device__ int get_index(int N, int C, int H, int W, int a, int b, int c, int d) {
return a * C * H * W + b * W * H + c * W + d;
}
__device__ int RM(int i, int j, int N) {
return i * N + j;
}
__global__ void conv_kernel(float *weight, float *inp, float *bias, float *out, int N, int C, int H, int W, int num_filter, int filter_depth, int filter_H, int filter_W, int out_size, int stride) {
int h = blockIdx.y * blockDim.y + threadIdx.y;
int w = blockIdx.x * blockDim.x + threadIdx.x;
int k_d = blockIdx.z * blockDim.z + threadIdx.z;
int n, c, k_h, k_w;
if (h < out_size && w < out_size && k_d < num_filter) {
float my_bias = bias[k_d];
int kernel_x = w * stride;
int kernel_y = h * stride;
for (n = 0; n < N; n ++) {
float cur_val = my_bias;
for (c = 0; c < filter_depth; c ++) {
for (k_h = 0; k_h < filter_H; k_h ++) {
for (k_w = 0; k_w < filter_W; k_w ++) {
float target_weight = weight[get_index(num_filter, filter_depth, filter_H, filter_W, k_d, c, k_h, k_w)];
float target_inp = inp[get_index(N, C, H, W, n, c, kernel_y + k_h, kernel_x + k_w)];
cur_val += target_inp * target_weight;
}
}
}
out[get_index(N, num_filter, out_size, out_size, n, k_d, h, w)] = cur_val;
}
}
}
__global__ void matmul_kernel(float *A, float *B, float *out, int Am, int An, int Bm, int Bn) {
int i = blockIdx.y * blockDim.y + threadIdx.y;
int j = blockIdx.x * blockDim.x + threadIdx.x;
int bi = threadIdx.y;
int bj = threadIdx.x;
__shared__ float subA[LBLK * LBLK];
__shared__ float subB[LBLK * LBLK];
float sum = 0.0;
int k;
for (k = 0; k < An; k += LBLK) {
if (i < Am && k + bj < An) {
subA[RM(bi, bj, LBLK)] = A[RM(i, k + bj, An)];
} else {
subA[RM(bi, bj, LBLK)] = 0.0;
}
if (k + bi < Bm && j < Bn) {
subB[RM(bi, bj, LBLK)] = B[RM(k + bi, j, Bn)];
} else {
subB[RM(bi, bj, LBLK)] = 0.0;
}
__syncthreads();
for (int bk = 0; bk < LBLK; bk++) {
sum += subA[RM(bi, bk, LBLK)] * subB[RM(bk, bj, LBLK)];
}
__syncthreads();
}
if (i < Am && j < Bn) {
out[RM(i, j, Bn)] = sum;
}
}
extern "C" int conv_CUDA_main(float *inp, float *weight, float *bias, float *out, int stride, float *dims) {
int N = (int)dims[0];
int C = (int)dims[1];
int H = (int)dims[2];
int W = (int)dims[3];
int num_filter = (int)dims[4];
int filter_depth = (int)dims[5];
int filter_H = (int)dims[6];
int filter_W = (int)dims[7];
int out_size = (int)dims[8];
float *dev_weight, *dev_inp, *dev_bias, *dev_out;
cudaMalloc(&dev_weight, num_filter * filter_depth * filter_H * filter_W * sizeof(float));
cudaMalloc(&dev_inp, N * C * H * W * sizeof(float));
cudaMalloc(&dev_bias, num_filter * sizeof(float));
cudaMalloc(&dev_out, N * num_filter * out_size * out_size * sizeof(float));
cudaMemcpy(dev_weight, weight, num_filter * filter_depth * filter_H * filter_W * sizeof(float), cudaMemcpyHostToDevice);
cudaMemcpy(dev_inp, inp, N * C * H * W * sizeof(float), cudaMemcpyHostToDevice);
cudaMemcpy(dev_bias, bias, num_filter * sizeof(float), cudaMemcpyHostToDevice);
dim3 blockDim(8, 8, 8);
dim3 gridDim((out_size + blockDim.x - 1) / blockDim.x, (out_size + blockDim.y - 1) / blockDim.y, (num_filter + blockDim.z - 1) / blockDim.z);
conv_kernel<<<gridDim, blockDim>>>(dev_weight, dev_inp, dev_bias, dev_out, N, C, H, W, num_filter, filter_depth, filter_H, filter_W, out_size, stride);
cudaMemcpy(out, dev_out, N * num_filter * out_size * out_size * sizeof(float), cudaMemcpyDeviceToHost);
cudaFree(dev_weight);
cudaFree(dev_inp);
cudaFree(dev_bias);
cudaFree(dev_out);
return 0;
}
extern "C" int matmul_CUDA_main(float *A, float *B, float *out, int Am, int An, int Bm, int Bn) {
float *dev_A, *dev_B, *dev_bias, *dev_out;
cudaMalloc(&dev_A, Am * An * sizeof(float));
cudaMalloc(&dev_B, Bm * Bn * sizeof(float));
cudaMalloc(&dev_out, Am * Bn * sizeof(float));
cudaMemcpy(dev_A, A, Am * An * sizeof(float), cudaMemcpyHostToDevice);
cudaMemcpy(dev_B, B, Bm * Bn * sizeof(float), cudaMemcpyHostToDevice);
dim3 blockDim(8, 8);
dim3 gridDim((Bn + blockDim.x - 1) / blockDim.x, (Am + blockDim.y - 1) / blockDim.y);
matmul_kernel<<<gridDim, blockDim>>>(dev_A, dev_B, dev_out, Am, An, Bm, Bn);
cudaMemcpy(out, dev_out, Am * Bn * sizeof(float), cudaMemcpyDeviceToHost);
cudaFree(dev_A);
cudaFree(dev_B);
cudaFree(dev_out);
return 0;
} | .file "tmpxft_00036cd8_00000000-6_cuda_blockadd.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2063:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2063:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z9get_indexiiiiiiii
.type _Z9get_indexiiiiiiii, @function
_Z9get_indexiiiiiiii:
.LFB2057:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size _Z9get_indexiiiiiiii, .-_Z9get_indexiiiiiiii
.globl _Z2RMiii
.type _Z2RMiii, @function
_Z2RMiii:
.LFB2058:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2058:
.size _Z2RMiii, .-_Z2RMiii
.globl _Z47__device_stub__Z11conv_kernelPfS_S_S_iiiiiiiiiiPfS_S_S_iiiiiiiiii
.type _Z47__device_stub__Z11conv_kernelPfS_S_S_iiiiiiiiiiPfS_S_S_iiiiiiiiii, @function
_Z47__device_stub__Z11conv_kernelPfS_S_S_iiiiiiiiiiPfS_S_S_iiiiiiiiii:
.LFB2085:
.cfi_startproc
endbr64
subq $248, %rsp
.cfi_def_cfa_offset 256
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movl %r8d, 12(%rsp)
movl %r9d, 8(%rsp)
movq %fs:40, %rax
movq %rax, 232(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 12(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
leaq 256(%rsp), %rax
movq %rax, 160(%rsp)
leaq 264(%rsp), %rax
movq %rax, 168(%rsp)
leaq 272(%rsp), %rax
movq %rax, 176(%rsp)
leaq 280(%rsp), %rax
movq %rax, 184(%rsp)
leaq 288(%rsp), %rax
movq %rax, 192(%rsp)
leaq 296(%rsp), %rax
movq %rax, 200(%rsp)
leaq 304(%rsp), %rax
movq %rax, 208(%rsp)
leaq 312(%rsp), %rax
movq %rax, 216(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L11
.L7:
movq 232(%rsp), %rax
subq %fs:40, %rax
jne .L12
addq $248, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 264
pushq 56(%rsp)
.cfi_def_cfa_offset 272
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z11conv_kernelPfS_S_S_iiiiiiiiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 256
jmp .L7
.L12:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2085:
.size _Z47__device_stub__Z11conv_kernelPfS_S_S_iiiiiiiiiiPfS_S_S_iiiiiiiiii, .-_Z47__device_stub__Z11conv_kernelPfS_S_S_iiiiiiiiiiPfS_S_S_iiiiiiiiii
.globl _Z11conv_kernelPfS_S_S_iiiiiiiiii
.type _Z11conv_kernelPfS_S_S_iiiiiiiiii, @function
_Z11conv_kernelPfS_S_S_iiiiiiiiii:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl 72(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 24
movl 72(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
movl 72(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 40
movl 72(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 48
movl 72(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 56
movl 72(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 64
movl 72(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 72
movl 72(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 80
call _Z47__device_stub__Z11conv_kernelPfS_S_S_iiiiiiiiiiPfS_S_S_iiiiiiiiii
addq $72, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _Z11conv_kernelPfS_S_S_iiiiiiiiii, .-_Z11conv_kernelPfS_S_S_iiiiiiiiii
.globl conv_CUDA_main
.type conv_CUDA_main, @function
conv_CUDA_main:
.LFB2059:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $152, %rsp
.cfi_def_cfa_offset 208
movq %rdi, 24(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 40(%rsp)
movq %rcx, 48(%rsp)
movl %r8d, 76(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
cvttss2sil (%r9), %r15d
cvttss2sil 4(%r9), %ebx
movl %ebx, 56(%rsp)
cvttss2sil 8(%r9), %r13d
movl %r13d, 60(%rsp)
cvttss2sil 12(%r9), %eax
movl %eax, 12(%rsp)
cvttss2sil 16(%r9), %r12d
cvttss2sil 20(%r9), %eax
movl %eax, 64(%rsp)
cvttss2sil 24(%r9), %ecx
movl %ecx, 68(%rsp)
cvttss2sil 28(%r9), %r10d
movl %r10d, 72(%rsp)
cvttss2sil 32(%r9), %r14d
imull %r12d, %eax
imull %ecx, %eax
imull %r10d, %eax
cltq
leaq 0(,%rax,4), %rcx
leaq 80(%rsp), %rdi
movq %rcx, 16(%rsp)
movq %rcx, %rsi
call cudaMalloc@PLT
imull %r15d, %ebx
movl %ebx, %ebp
imull %r13d, %ebp
movl 12(%rsp), %eax
imull %eax, %ebp
movslq %ebp, %rbp
salq $2, %rbp
leaq 88(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
movslq %r12d, %r13
salq $2, %r13
leaq 96(%rsp), %rdi
movq %r13, %rsi
call cudaMalloc@PLT
movl %r15d, %ebx
imull %r12d, %ebx
imull %r14d, %ebx
imull %r14d, %ebx
movslq %ebx, %rbx
salq $2, %rbx
leaq 104(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq 16(%rsp), %rdx
movq 32(%rsp), %rsi
movq 80(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %rbp, %rdx
movq 24(%rsp), %rsi
movq 88(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %r13, %rdx
movq 40(%rsp), %rsi
movq 96(%rsp), %rdi
call cudaMemcpy@PLT
leal 7(%r14), %eax
shrl $3, %eax
movl %eax, 124(%rsp)
movl %eax, 128(%rsp)
leal 7(%r12), %esi
shrl $3, %esi
movl $8, 112(%rsp)
movl $8, 116(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 112(%rsp), %rdx
movl $8, %ecx
movq 124(%rsp), %rdi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L19
.L16:
movl $2, %ecx
movq %rbx, %rdx
movq 104(%rsp), %rsi
movq 48(%rsp), %rdi
call cudaMemcpy@PLT
movq 80(%rsp), %rdi
call cudaFree@PLT
movq 88(%rsp), %rdi
call cudaFree@PLT
movq 96(%rsp), %rdi
call cudaFree@PLT
movq 104(%rsp), %rdi
call cudaFree@PLT
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L20
movl $0, %eax
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
movl 76(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 216
pushq %r14
.cfi_def_cfa_offset 224
movl 88(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 232
movl 92(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 240
movl 96(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 248
pushq %r12
.cfi_def_cfa_offset 256
movl 60(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 264
movl 116(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 272
movl 120(%rsp), %r9d
movl %r15d, %r8d
movq 168(%rsp), %rcx
movq 160(%rsp), %rdx
movq 152(%rsp), %rsi
movq 144(%rsp), %rdi
call _Z47__device_stub__Z11conv_kernelPfS_S_S_iiiiiiiiiiPfS_S_S_iiiiiiiiii
addq $64, %rsp
.cfi_def_cfa_offset 208
jmp .L16
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size conv_CUDA_main, .-conv_CUDA_main
.globl _Z41__device_stub__Z13matmul_kernelPfS_S_iiiiPfS_S_iiii
.type _Z41__device_stub__Z13matmul_kernelPfS_S_iiiiPfS_S_iiii, @function
_Z41__device_stub__Z13matmul_kernelPfS_S_iiiiPfS_S_iiii:
.LFB2087:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
leaq 192(%rsp), %rax
movq %rax, 160(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L25
.L21:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L26
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L25:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z13matmul_kernelPfS_S_iiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L21
.L26:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2087:
.size _Z41__device_stub__Z13matmul_kernelPfS_S_iiiiPfS_S_iiii, .-_Z41__device_stub__Z13matmul_kernelPfS_S_iiiiPfS_S_iiii
.globl _Z13matmul_kernelPfS_S_iiii
.type _Z13matmul_kernelPfS_S_iiii, @function
_Z13matmul_kernelPfS_S_iiii:
.LFB2088:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
call _Z41__device_stub__Z13matmul_kernelPfS_S_iiiiPfS_S_iiii
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2088:
.size _Z13matmul_kernelPfS_S_iiii, .-_Z13matmul_kernelPfS_S_iiii
.globl matmul_CUDA_main
.type matmul_CUDA_main, @function
matmul_CUDA_main:
.LFB2060:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $104, %rsp
.cfi_def_cfa_offset 160
movq %rdi, (%rsp)
movq %rsi, 8(%rsp)
movq %rdx, 16(%rsp)
movl %ecx, %r13d
movl %r8d, 28(%rsp)
movl %r9d, %r14d
movl 160(%rsp), %r15d
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
imull %ecx, %r8d
movslq %r8d, %r12
salq $2, %r12
leaq 40(%rsp), %rdi
movq %r12, %rsi
call cudaMalloc@PLT
movl %r14d, %ebp
imull %r15d, %ebp
movslq %ebp, %rbp
salq $2, %rbp
leaq 48(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
movl %r13d, %ebx
imull %r15d, %ebx
movslq %ebx, %rbx
salq $2, %rbx
leaq 56(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %r12, %rdx
movq (%rsp), %rsi
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %rbp, %rdx
movq 8(%rsp), %rsi
movq 48(%rsp), %rdi
call cudaMemcpy@PLT
leal 7(%r15), %eax
shrl $3, %eax
movl %eax, 76(%rsp)
leal 7(%r13), %eax
shrl $3, %eax
movl %eax, 80(%rsp)
movl $8, 64(%rsp)
movl $8, 68(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 64(%rsp), %rdx
movl $1, %ecx
movq 76(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L33
.L30:
movl $2, %ecx
movq %rbx, %rdx
movq 56(%rsp), %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq 48(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rdi
call cudaFree@PLT
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L34
movl $0, %eax
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L33:
.cfi_restore_state
subq $8, %rsp
.cfi_def_cfa_offset 168
pushq %r15
.cfi_def_cfa_offset 176
movl %r14d, %r9d
movl 44(%rsp), %r8d
movl %r13d, %ecx
movq 72(%rsp), %rdx
movq 64(%rsp), %rsi
movq 56(%rsp), %rdi
call _Z41__device_stub__Z13matmul_kernelPfS_S_iiiiPfS_S_iiii
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L30
.L34:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2060:
.size matmul_CUDA_main, .-matmul_CUDA_main
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z13matmul_kernelPfS_S_iiii"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "_Z11conv_kernelPfS_S_S_iiiiiiiiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2090:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z13matmul_kernelPfS_S_iiii(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z11conv_kernelPfS_S_S_iiiiiiiiii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2090:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "cuda.h"
#include "stdio.h"
#include "stdlib.h"
#define LBLK 8
__device__ int get_index(int N, int C, int H, int W, int a, int b, int c, int d) {
return a * C * H * W + b * W * H + c * W + d;
}
__device__ int RM(int i, int j, int N) {
return i * N + j;
}
__global__ void conv_kernel(float *weight, float *inp, float *bias, float *out, int N, int C, int H, int W, int num_filter, int filter_depth, int filter_H, int filter_W, int out_size, int stride) {
int h = blockIdx.y * blockDim.y + threadIdx.y;
int w = blockIdx.x * blockDim.x + threadIdx.x;
int k_d = blockIdx.z * blockDim.z + threadIdx.z;
int n, c, k_h, k_w;
if (h < out_size && w < out_size && k_d < num_filter) {
float my_bias = bias[k_d];
int kernel_x = w * stride;
int kernel_y = h * stride;
for (n = 0; n < N; n ++) {
float cur_val = my_bias;
for (c = 0; c < filter_depth; c ++) {
for (k_h = 0; k_h < filter_H; k_h ++) {
for (k_w = 0; k_w < filter_W; k_w ++) {
float target_weight = weight[get_index(num_filter, filter_depth, filter_H, filter_W, k_d, c, k_h, k_w)];
float target_inp = inp[get_index(N, C, H, W, n, c, kernel_y + k_h, kernel_x + k_w)];
cur_val += target_inp * target_weight;
}
}
}
out[get_index(N, num_filter, out_size, out_size, n, k_d, h, w)] = cur_val;
}
}
}
__global__ void matmul_kernel(float *A, float *B, float *out, int Am, int An, int Bm, int Bn) {
int i = blockIdx.y * blockDim.y + threadIdx.y;
int j = blockIdx.x * blockDim.x + threadIdx.x;
int bi = threadIdx.y;
int bj = threadIdx.x;
__shared__ float subA[LBLK * LBLK];
__shared__ float subB[LBLK * LBLK];
float sum = 0.0;
int k;
for (k = 0; k < An; k += LBLK) {
if (i < Am && k + bj < An) {
subA[RM(bi, bj, LBLK)] = A[RM(i, k + bj, An)];
} else {
subA[RM(bi, bj, LBLK)] = 0.0;
}
if (k + bi < Bm && j < Bn) {
subB[RM(bi, bj, LBLK)] = B[RM(k + bi, j, Bn)];
} else {
subB[RM(bi, bj, LBLK)] = 0.0;
}
__syncthreads();
for (int bk = 0; bk < LBLK; bk++) {
sum += subA[RM(bi, bk, LBLK)] * subB[RM(bk, bj, LBLK)];
}
__syncthreads();
}
if (i < Am && j < Bn) {
out[RM(i, j, Bn)] = sum;
}
}
extern "C" int conv_CUDA_main(float *inp, float *weight, float *bias, float *out, int stride, float *dims) {
int N = (int)dims[0];
int C = (int)dims[1];
int H = (int)dims[2];
int W = (int)dims[3];
int num_filter = (int)dims[4];
int filter_depth = (int)dims[5];
int filter_H = (int)dims[6];
int filter_W = (int)dims[7];
int out_size = (int)dims[8];
float *dev_weight, *dev_inp, *dev_bias, *dev_out;
cudaMalloc(&dev_weight, num_filter * filter_depth * filter_H * filter_W * sizeof(float));
cudaMalloc(&dev_inp, N * C * H * W * sizeof(float));
cudaMalloc(&dev_bias, num_filter * sizeof(float));
cudaMalloc(&dev_out, N * num_filter * out_size * out_size * sizeof(float));
cudaMemcpy(dev_weight, weight, num_filter * filter_depth * filter_H * filter_W * sizeof(float), cudaMemcpyHostToDevice);
cudaMemcpy(dev_inp, inp, N * C * H * W * sizeof(float), cudaMemcpyHostToDevice);
cudaMemcpy(dev_bias, bias, num_filter * sizeof(float), cudaMemcpyHostToDevice);
dim3 blockDim(8, 8, 8);
dim3 gridDim((out_size + blockDim.x - 1) / blockDim.x, (out_size + blockDim.y - 1) / blockDim.y, (num_filter + blockDim.z - 1) / blockDim.z);
conv_kernel<<<gridDim, blockDim>>>(dev_weight, dev_inp, dev_bias, dev_out, N, C, H, W, num_filter, filter_depth, filter_H, filter_W, out_size, stride);
cudaMemcpy(out, dev_out, N * num_filter * out_size * out_size * sizeof(float), cudaMemcpyDeviceToHost);
cudaFree(dev_weight);
cudaFree(dev_inp);
cudaFree(dev_bias);
cudaFree(dev_out);
return 0;
}
extern "C" int matmul_CUDA_main(float *A, float *B, float *out, int Am, int An, int Bm, int Bn) {
float *dev_A, *dev_B, *dev_bias, *dev_out;
cudaMalloc(&dev_A, Am * An * sizeof(float));
cudaMalloc(&dev_B, Bm * Bn * sizeof(float));
cudaMalloc(&dev_out, Am * Bn * sizeof(float));
cudaMemcpy(dev_A, A, Am * An * sizeof(float), cudaMemcpyHostToDevice);
cudaMemcpy(dev_B, B, Bm * Bn * sizeof(float), cudaMemcpyHostToDevice);
dim3 blockDim(8, 8);
dim3 gridDim((Bn + blockDim.x - 1) / blockDim.x, (Am + blockDim.y - 1) / blockDim.y);
matmul_kernel<<<gridDim, blockDim>>>(dev_A, dev_B, dev_out, Am, An, Bm, Bn);
cudaMemcpy(out, dev_out, Am * Bn * sizeof(float), cudaMemcpyDeviceToHost);
cudaFree(dev_A);
cudaFree(dev_B);
cudaFree(dev_out);
return 0;
} | #include "hip/hip_runtime.h"
#include "stdio.h"
#include "stdlib.h"
#define LBLK 8
__device__ int get_index(int N, int C, int H, int W, int a, int b, int c, int d) {
return a * C * H * W + b * W * H + c * W + d;
}
__device__ int RM(int i, int j, int N) {
return i * N + j;
}
__global__ void conv_kernel(float *weight, float *inp, float *bias, float *out, int N, int C, int H, int W, int num_filter, int filter_depth, int filter_H, int filter_W, int out_size, int stride) {
int h = blockIdx.y * blockDim.y + threadIdx.y;
int w = blockIdx.x * blockDim.x + threadIdx.x;
int k_d = blockIdx.z * blockDim.z + threadIdx.z;
int n, c, k_h, k_w;
if (h < out_size && w < out_size && k_d < num_filter) {
float my_bias = bias[k_d];
int kernel_x = w * stride;
int kernel_y = h * stride;
for (n = 0; n < N; n ++) {
float cur_val = my_bias;
for (c = 0; c < filter_depth; c ++) {
for (k_h = 0; k_h < filter_H; k_h ++) {
for (k_w = 0; k_w < filter_W; k_w ++) {
float target_weight = weight[get_index(num_filter, filter_depth, filter_H, filter_W, k_d, c, k_h, k_w)];
float target_inp = inp[get_index(N, C, H, W, n, c, kernel_y + k_h, kernel_x + k_w)];
cur_val += target_inp * target_weight;
}
}
}
out[get_index(N, num_filter, out_size, out_size, n, k_d, h, w)] = cur_val;
}
}
}
__global__ void matmul_kernel(float *A, float *B, float *out, int Am, int An, int Bm, int Bn) {
int i = blockIdx.y * blockDim.y + threadIdx.y;
int j = blockIdx.x * blockDim.x + threadIdx.x;
int bi = threadIdx.y;
int bj = threadIdx.x;
__shared__ float subA[LBLK * LBLK];
__shared__ float subB[LBLK * LBLK];
float sum = 0.0;
int k;
for (k = 0; k < An; k += LBLK) {
if (i < Am && k + bj < An) {
subA[RM(bi, bj, LBLK)] = A[RM(i, k + bj, An)];
} else {
subA[RM(bi, bj, LBLK)] = 0.0;
}
if (k + bi < Bm && j < Bn) {
subB[RM(bi, bj, LBLK)] = B[RM(k + bi, j, Bn)];
} else {
subB[RM(bi, bj, LBLK)] = 0.0;
}
__syncthreads();
for (int bk = 0; bk < LBLK; bk++) {
sum += subA[RM(bi, bk, LBLK)] * subB[RM(bk, bj, LBLK)];
}
__syncthreads();
}
if (i < Am && j < Bn) {
out[RM(i, j, Bn)] = sum;
}
}
extern "C" int conv_CUDA_main(float *inp, float *weight, float *bias, float *out, int stride, float *dims) {
int N = (int)dims[0];
int C = (int)dims[1];
int H = (int)dims[2];
int W = (int)dims[3];
int num_filter = (int)dims[4];
int filter_depth = (int)dims[5];
int filter_H = (int)dims[6];
int filter_W = (int)dims[7];
int out_size = (int)dims[8];
float *dev_weight, *dev_inp, *dev_bias, *dev_out;
hipMalloc(&dev_weight, num_filter * filter_depth * filter_H * filter_W * sizeof(float));
hipMalloc(&dev_inp, N * C * H * W * sizeof(float));
hipMalloc(&dev_bias, num_filter * sizeof(float));
hipMalloc(&dev_out, N * num_filter * out_size * out_size * sizeof(float));
hipMemcpy(dev_weight, weight, num_filter * filter_depth * filter_H * filter_W * sizeof(float), hipMemcpyHostToDevice);
hipMemcpy(dev_inp, inp, N * C * H * W * sizeof(float), hipMemcpyHostToDevice);
hipMemcpy(dev_bias, bias, num_filter * sizeof(float), hipMemcpyHostToDevice);
dim3 blockDim(8, 8, 8);
dim3 gridDim((out_size + blockDim.x - 1) / blockDim.x, (out_size + blockDim.y - 1) / blockDim.y, (num_filter + blockDim.z - 1) / blockDim.z);
conv_kernel<<<gridDim, blockDim>>>(dev_weight, dev_inp, dev_bias, dev_out, N, C, H, W, num_filter, filter_depth, filter_H, filter_W, out_size, stride);
hipMemcpy(out, dev_out, N * num_filter * out_size * out_size * sizeof(float), hipMemcpyDeviceToHost);
hipFree(dev_weight);
hipFree(dev_inp);
hipFree(dev_bias);
hipFree(dev_out);
return 0;
}
extern "C" int matmul_CUDA_main(float *A, float *B, float *out, int Am, int An, int Bm, int Bn) {
float *dev_A, *dev_B, *dev_bias, *dev_out;
hipMalloc(&dev_A, Am * An * sizeof(float));
hipMalloc(&dev_B, Bm * Bn * sizeof(float));
hipMalloc(&dev_out, Am * Bn * sizeof(float));
hipMemcpy(dev_A, A, Am * An * sizeof(float), hipMemcpyHostToDevice);
hipMemcpy(dev_B, B, Bm * Bn * sizeof(float), hipMemcpyHostToDevice);
dim3 blockDim(8, 8);
dim3 gridDim((Bn + blockDim.x - 1) / blockDim.x, (Am + blockDim.y - 1) / blockDim.y);
matmul_kernel<<<gridDim, blockDim>>>(dev_A, dev_B, dev_out, Am, An, Bm, Bn);
hipMemcpy(out, dev_out, Am * Bn * sizeof(float), hipMemcpyDeviceToHost);
hipFree(dev_A);
hipFree(dev_B);
hipFree(dev_out);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include "hip/hip_runtime.h"
#include "stdio.h"
#include "stdlib.h"
#define LBLK 8
__device__ int get_index(int N, int C, int H, int W, int a, int b, int c, int d) {
return a * C * H * W + b * W * H + c * W + d;
}
__device__ int RM(int i, int j, int N) {
return i * N + j;
}
__global__ void conv_kernel(float *weight, float *inp, float *bias, float *out, int N, int C, int H, int W, int num_filter, int filter_depth, int filter_H, int filter_W, int out_size, int stride) {
int h = blockIdx.y * blockDim.y + threadIdx.y;
int w = blockIdx.x * blockDim.x + threadIdx.x;
int k_d = blockIdx.z * blockDim.z + threadIdx.z;
int n, c, k_h, k_w;
if (h < out_size && w < out_size && k_d < num_filter) {
float my_bias = bias[k_d];
int kernel_x = w * stride;
int kernel_y = h * stride;
for (n = 0; n < N; n ++) {
float cur_val = my_bias;
for (c = 0; c < filter_depth; c ++) {
for (k_h = 0; k_h < filter_H; k_h ++) {
for (k_w = 0; k_w < filter_W; k_w ++) {
float target_weight = weight[get_index(num_filter, filter_depth, filter_H, filter_W, k_d, c, k_h, k_w)];
float target_inp = inp[get_index(N, C, H, W, n, c, kernel_y + k_h, kernel_x + k_w)];
cur_val += target_inp * target_weight;
}
}
}
out[get_index(N, num_filter, out_size, out_size, n, k_d, h, w)] = cur_val;
}
}
}
__global__ void matmul_kernel(float *A, float *B, float *out, int Am, int An, int Bm, int Bn) {
int i = blockIdx.y * blockDim.y + threadIdx.y;
int j = blockIdx.x * blockDim.x + threadIdx.x;
int bi = threadIdx.y;
int bj = threadIdx.x;
__shared__ float subA[LBLK * LBLK];
__shared__ float subB[LBLK * LBLK];
float sum = 0.0;
int k;
for (k = 0; k < An; k += LBLK) {
if (i < Am && k + bj < An) {
subA[RM(bi, bj, LBLK)] = A[RM(i, k + bj, An)];
} else {
subA[RM(bi, bj, LBLK)] = 0.0;
}
if (k + bi < Bm && j < Bn) {
subB[RM(bi, bj, LBLK)] = B[RM(k + bi, j, Bn)];
} else {
subB[RM(bi, bj, LBLK)] = 0.0;
}
__syncthreads();
for (int bk = 0; bk < LBLK; bk++) {
sum += subA[RM(bi, bk, LBLK)] * subB[RM(bk, bj, LBLK)];
}
__syncthreads();
}
if (i < Am && j < Bn) {
out[RM(i, j, Bn)] = sum;
}
}
extern "C" int conv_CUDA_main(float *inp, float *weight, float *bias, float *out, int stride, float *dims) {
int N = (int)dims[0];
int C = (int)dims[1];
int H = (int)dims[2];
int W = (int)dims[3];
int num_filter = (int)dims[4];
int filter_depth = (int)dims[5];
int filter_H = (int)dims[6];
int filter_W = (int)dims[7];
int out_size = (int)dims[8];
float *dev_weight, *dev_inp, *dev_bias, *dev_out;
hipMalloc(&dev_weight, num_filter * filter_depth * filter_H * filter_W * sizeof(float));
hipMalloc(&dev_inp, N * C * H * W * sizeof(float));
hipMalloc(&dev_bias, num_filter * sizeof(float));
hipMalloc(&dev_out, N * num_filter * out_size * out_size * sizeof(float));
hipMemcpy(dev_weight, weight, num_filter * filter_depth * filter_H * filter_W * sizeof(float), hipMemcpyHostToDevice);
hipMemcpy(dev_inp, inp, N * C * H * W * sizeof(float), hipMemcpyHostToDevice);
hipMemcpy(dev_bias, bias, num_filter * sizeof(float), hipMemcpyHostToDevice);
dim3 blockDim(8, 8, 8);
dim3 gridDim((out_size + blockDim.x - 1) / blockDim.x, (out_size + blockDim.y - 1) / blockDim.y, (num_filter + blockDim.z - 1) / blockDim.z);
conv_kernel<<<gridDim, blockDim>>>(dev_weight, dev_inp, dev_bias, dev_out, N, C, H, W, num_filter, filter_depth, filter_H, filter_W, out_size, stride);
hipMemcpy(out, dev_out, N * num_filter * out_size * out_size * sizeof(float), hipMemcpyDeviceToHost);
hipFree(dev_weight);
hipFree(dev_inp);
hipFree(dev_bias);
hipFree(dev_out);
return 0;
}
extern "C" int matmul_CUDA_main(float *A, float *B, float *out, int Am, int An, int Bm, int Bn) {
float *dev_A, *dev_B, *dev_bias, *dev_out;
hipMalloc(&dev_A, Am * An * sizeof(float));
hipMalloc(&dev_B, Bm * Bn * sizeof(float));
hipMalloc(&dev_out, Am * Bn * sizeof(float));
hipMemcpy(dev_A, A, Am * An * sizeof(float), hipMemcpyHostToDevice);
hipMemcpy(dev_B, B, Bm * Bn * sizeof(float), hipMemcpyHostToDevice);
dim3 blockDim(8, 8);
dim3 gridDim((Bn + blockDim.x - 1) / blockDim.x, (Am + blockDim.y - 1) / blockDim.y);
matmul_kernel<<<gridDim, blockDim>>>(dev_A, dev_B, dev_out, Am, An, Bm, Bn);
hipMemcpy(out, dev_out, Am * Bn * sizeof(float), hipMemcpyDeviceToHost);
hipFree(dev_A);
hipFree(dev_B);
hipFree(dev_out);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11conv_kernelPfS_S_S_iiiiiiiiii
.globl _Z11conv_kernelPfS_S_S_iiiiiiiiii
.p2align 8
.type _Z11conv_kernelPfS_S_S_iiiiiiiiii,@function
_Z11conv_kernelPfS_S_S_iiiiiiiiii:
s_clause 0x2
s_load_b64 s[2:3], s[0:1], 0x54
s_load_b32 s12, s[0:1], 0x30
s_load_b32 s16, s[0:1], 0x40
v_bfe_u32 v2, v0, 10, 10
v_and_b32_e32 v4, 0x3ff, v0
v_bfe_u32 v5, v0, 20, 10
s_waitcnt lgkmcnt(0)
s_lshr_b32 s4, s2, 16
s_and_b32 s2, s2, 0xffff
v_mad_u64_u32 v[0:1], null, s14, s4, v[2:3]
s_mul_i32 s14, s13, s2
s_and_b32 s2, s3, 0xffff
v_add_nc_u32_e32 v1, s14, v4
v_mad_u64_u32 v[2:3], null, s15, s2, v[5:6]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_max_i32_e32 v3, v0, v1
v_cmp_gt_i32_e64 s2, s12, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_gt_i32_e32 vcc_lo, s16, v3
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_12
s_load_b32 s13, s[0:1], 0x20
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s13, 1
s_cbranch_scc1 .LBB0_12
s_load_b256 s[4:11], s[0:1], 0x0
v_ashrrev_i32_e32 v3, 31, v2
s_mov_b32 s18, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[5:6], 2, v[2:3]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v5, vcc_lo, s8, v5
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v6, vcc_lo, s9, v6, vcc_lo
global_load_b32 v7, v[5:6], off
s_clause 0x4
s_load_b32 s8, s[0:1], 0x2c
s_load_b64 s[2:3], s[0:1], 0x34
s_load_b32 s9, s[0:1], 0x3c
s_load_b32 s15, s[0:1], 0x44
s_load_b64 s[20:21], s[0:1], 0x24
s_waitcnt lgkmcnt(0)
v_mul_lo_u32 v3, s8, v0
s_cmp_gt_i32 s2, 0
s_mul_i32 s1, s9, s3
s_cselect_b32 s0, -1, 0
s_mul_i32 s17, s1, s2
s_cmp_gt_i32 s3, 0
v_mul_lo_u32 v8, s17, v2
s_mul_i32 s17, s8, s21
v_add3_u32 v3, v4, v3, s14
s_cselect_b32 s14, -1, 0
s_cmp_gt_i32 s9, 0
s_mul_i32 s19, s17, s20
s_delay_alu instid0(VALU_DEP_1)
v_mul_lo_u32 v9, s15, v3
s_cselect_b32 s15, -1, 0
s_branch .LBB0_4
.LBB0_3:
s_set_inst_prefetch_distance 0x2
v_mad_u64_u32 v[3:4], null, s18, s12, v[2:3]
v_add_nc_u32_e32 v9, s19, v9
s_add_i32 s18, s18, 1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
s_cmp_lg_u32 s18, s13
v_mad_u64_u32 v[4:5], null, v3, s16, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[5:6], null, v4, s16, v[1:2]
v_ashrrev_i32_e32 v6, 31, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[5:6]
v_add_co_u32 v3, vcc_lo, s10, v3
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, s11, v4, vcc_lo
global_store_b32 v[3:4], v10, off
s_cbranch_scc0 .LBB0_12
.LBB0_4:
s_waitcnt vmcnt(0)
v_mov_b32_e32 v10, v7
s_and_not1_b32 vcc_lo, exec_lo, s0
s_cbranch_vccnz .LBB0_3
s_delay_alu instid0(VALU_DEP_2)
v_dual_mov_b32 v11, v9 :: v_dual_mov_b32 v12, v8
v_mov_b32_e32 v10, v7
s_mov_b32 s20, 0
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_7
.p2align 6
.LBB0_6:
v_add_nc_u32_e32 v12, s1, v12
v_add_nc_u32_e32 v11, s17, v11
s_add_i32 s20, s20, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lg_u32 s20, s2
s_cbranch_scc0 .LBB0_3
.LBB0_7:
s_and_not1_b32 vcc_lo, exec_lo, s14
s_cbranch_vccnz .LBB0_6
v_dual_mov_b32 v13, v11 :: v_dual_mov_b32 v14, v12
s_mov_b32 s21, 0
s_branch .LBB0_10
.p2align 6
.LBB0_9:
v_add_nc_u32_e32 v14, s9, v14
v_add_nc_u32_e32 v13, s8, v13
s_add_i32 s21, s21, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lg_u32 s21, s3
s_cbranch_scc0 .LBB0_6
.LBB0_10:
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mov_b32_e32 v3, v13
v_mov_b32_e32 v5, v14
s_and_not1_b32 vcc_lo, exec_lo, s15
s_mov_b32 s22, s9
s_cbranch_vccnz .LBB0_9
.p2align 6
.LBB0_11:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_ashrrev_i32_e32 v6, 31, v5
v_ashrrev_i32_e32 v4, 31, v3
s_add_i32 s22, s22, -1
s_cmp_lg_u32 s22, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[15:16], 2, v[5:6]
v_lshlrev_b64 v[17:18], 2, v[3:4]
v_add_nc_u32_e32 v3, 1, v3
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v15, vcc_lo, s4, v15
v_add_co_ci_u32_e32 v16, vcc_lo, s5, v16, vcc_lo
s_delay_alu instid0(VALU_DEP_4)
v_add_co_u32 v17, vcc_lo, s6, v17
v_add_co_ci_u32_e32 v18, vcc_lo, s7, v18, vcc_lo
global_load_b32 v4, v[15:16], off
global_load_b32 v6, v[17:18], off
s_waitcnt vmcnt(0)
v_dual_fmac_f32 v10, v4, v6 :: v_dual_add_nc_u32 v5, 1, v5
s_cbranch_scc1 .LBB0_11
s_branch .LBB0_9
.LBB0_12:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11conv_kernelPfS_S_S_iiiiiiiiii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 328
.amdhsa_user_sgpr_count 13
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 1
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 2
.amdhsa_next_free_vgpr 19
.amdhsa_next_free_sgpr 23
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z11conv_kernelPfS_S_S_iiiiiiiiii, .Lfunc_end0-_Z11conv_kernelPfS_S_S_iiiiiiiiii
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z13matmul_kernelPfS_S_iiii
.globl _Z13matmul_kernelPfS_S_iiii
.p2align 8
.type _Z13matmul_kernelPfS_S_iiii,@function
_Z13matmul_kernelPfS_S_iiii:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x34
s_load_b64 s[8:9], s[0:1], 0x18
s_load_b32 s3, s[0:1], 0x24
v_bfe_u32 v3, v0, 10, 10
v_and_b32_e32 v4, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s4, s2, 16
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[0:1], null, s15, s4, v[3:4]
v_mad_u64_u32 v[1:2], null, s14, s2, v[4:5]
s_cmp_lt_i32 s9, 1
v_cmp_gt_i32_e32 vcc_lo, s8, v0
s_delay_alu instid0(VALU_DEP_2)
v_cmp_gt_i32_e64 s2, s3, v1
s_cbranch_scc1 .LBB1_15
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b32 s10, s[0:1], 0x20
v_lshlrev_b32_e32 v2, 3, v3
v_mul_lo_u32 v6, v0, s9
v_cmp_le_i32_e64 s11, s8, v0
v_lshl_add_u32 v8, v4, 2, 0x100
v_lshlrev_b32_e32 v9, 5, v3
v_add_lshl_u32 v5, v2, v4, 2
v_mov_b32_e32 v2, 0
s_mov_b32 s12, 0
s_xor_b32 s13, s2, -1
s_delay_alu instid0(VALU_DEP_2)
v_dual_mov_b32 v10, 0 :: v_dual_add_nc_u32 v7, 0x100, v5
.LBB1_2:
s_mov_b32 s2, s11
s_mov_b32 s14, 0
s_and_saveexec_b32 s15, vcc_lo
v_add_nc_u32_e32 v11, s12, v4
s_and_not1_b32 s16, s11, exec_lo
s_mov_b32 s14, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_le_i32_e64 s2, s9, v11
s_and_b32 s2, s2, exec_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 s2, s16, s2
s_or_b32 exec_lo, exec_lo, s15
s_and_saveexec_b32 s15, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s2, exec_lo, s15
s_cbranch_execz .LBB1_6
s_and_not1_b32 s14, s14, exec_lo
ds_store_b32 v5, v10
.LBB1_6:
s_or_b32 exec_lo, exec_lo, s2
s_and_saveexec_b32 s15, s14
s_cbranch_execz .LBB1_8
v_add_nc_u32_e32 v12, v11, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v13, 31, v12
v_lshlrev_b64 v[12:13], 2, v[12:13]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v12, s2, s4, v12
v_add_co_ci_u32_e64 v13, s2, s5, v13, s2
global_load_b32 v12, v[12:13], off
s_waitcnt vmcnt(0)
ds_store_b32 v5, v12
.LBB1_8:
s_or_b32 exec_lo, exec_lo, s15
v_add_nc_u32_e32 v12, s12, v3
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_le_i32_e64 s2, s10, v12
s_or_b32 s2, s13, s2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_saveexec_b32 s14, s2
s_xor_b32 s2, exec_lo, s14
s_cbranch_execz .LBB1_10
ds_store_b32 v7, v10
.LBB1_10:
s_and_not1_saveexec_b32 s14, s2
s_cbranch_execz .LBB1_12
v_mad_u64_u32 v[13:14], null, v12, s3, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v14, 31, v13
v_lshlrev_b64 v[12:13], 2, v[13:14]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v12, s2, s6, v12
v_add_co_ci_u32_e64 v13, s2, s7, v13, s2
global_load_b32 v12, v[12:13], off
s_waitcnt vmcnt(0)
ds_store_b32 v7, v12
.LBB1_12:
s_or_b32 exec_lo, exec_lo, s14
v_mov_b32_e32 v12, v8
s_mov_b32 s2, 0
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
.LBB1_13:
v_add_nc_u32_e32 v13, s2, v9
s_add_i32 s2, s2, 4
ds_load_b32 v14, v12
ds_load_b32 v13, v13
v_add_nc_u32_e32 v12, 32, v12
s_cmp_eq_u32 s2, 32
s_waitcnt lgkmcnt(0)
v_fmac_f32_e32 v2, v13, v14
s_cbranch_scc0 .LBB1_13
s_add_i32 s12, s12, 8
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_ge_i32 s12, s9
s_barrier
buffer_gl0_inv
s_cbranch_scc0 .LBB1_2
s_branch .LBB1_16
.LBB1_15:
v_mov_b32_e32 v2, 0
.LBB1_16:
v_cmp_gt_i32_e32 vcc_lo, s8, v0
v_cmp_gt_i32_e64 s2, s3, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, vcc_lo, s2
s_and_saveexec_b32 s4, s2
s_cbranch_execz .LBB1_18
s_load_b64 s[0:1], s[0:1], 0x10
v_mad_u64_u32 v[3:4], null, v0, s3, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v4, 31, v3
v_lshlrev_b64 v[0:1], 2, v[3:4]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v2, off
.LBB1_18:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13matmul_kernelPfS_S_iiii
.amdhsa_group_segment_fixed_size 512
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 15
.amdhsa_next_free_sgpr 17
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z13matmul_kernelPfS_S_iiii, .Lfunc_end1-_Z13matmul_kernelPfS_S_iiii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 36
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: by_value
- .offset: 44
.size: 4
.value_kind: by_value
- .offset: 48
.size: 4
.value_kind: by_value
- .offset: 52
.size: 4
.value_kind: by_value
- .offset: 56
.size: 4
.value_kind: by_value
- .offset: 60
.size: 4
.value_kind: by_value
- .offset: 64
.size: 4
.value_kind: by_value
- .offset: 68
.size: 4
.value_kind: by_value
- .offset: 72
.size: 4
.value_kind: hidden_block_count_x
- .offset: 76
.size: 4
.value_kind: hidden_block_count_y
- .offset: 80
.size: 4
.value_kind: hidden_block_count_z
- .offset: 84
.size: 2
.value_kind: hidden_group_size_x
- .offset: 86
.size: 2
.value_kind: hidden_group_size_y
- .offset: 88
.size: 2
.value_kind: hidden_group_size_z
- .offset: 90
.size: 2
.value_kind: hidden_remainder_x
- .offset: 92
.size: 2
.value_kind: hidden_remainder_y
- .offset: 94
.size: 2
.value_kind: hidden_remainder_z
- .offset: 112
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 120
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 128
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 136
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 328
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11conv_kernelPfS_S_S_iiiiiiiiii
.private_segment_fixed_size: 0
.sgpr_count: 25
.sgpr_spill_count: 0
.symbol: _Z11conv_kernelPfS_S_S_iiiiiiiiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 19
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 36
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 512
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13matmul_kernelPfS_S_iiii
.private_segment_fixed_size: 0
.sgpr_count: 19
.sgpr_spill_count: 0
.symbol: _Z13matmul_kernelPfS_S_iiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 15
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include "hip/hip_runtime.h"
#include "stdio.h"
#include "stdlib.h"
#define LBLK 8
__device__ int get_index(int N, int C, int H, int W, int a, int b, int c, int d) {
return a * C * H * W + b * W * H + c * W + d;
}
__device__ int RM(int i, int j, int N) {
return i * N + j;
}
__global__ void conv_kernel(float *weight, float *inp, float *bias, float *out, int N, int C, int H, int W, int num_filter, int filter_depth, int filter_H, int filter_W, int out_size, int stride) {
int h = blockIdx.y * blockDim.y + threadIdx.y;
int w = blockIdx.x * blockDim.x + threadIdx.x;
int k_d = blockIdx.z * blockDim.z + threadIdx.z;
int n, c, k_h, k_w;
if (h < out_size && w < out_size && k_d < num_filter) {
float my_bias = bias[k_d];
int kernel_x = w * stride;
int kernel_y = h * stride;
for (n = 0; n < N; n ++) {
float cur_val = my_bias;
for (c = 0; c < filter_depth; c ++) {
for (k_h = 0; k_h < filter_H; k_h ++) {
for (k_w = 0; k_w < filter_W; k_w ++) {
float target_weight = weight[get_index(num_filter, filter_depth, filter_H, filter_W, k_d, c, k_h, k_w)];
float target_inp = inp[get_index(N, C, H, W, n, c, kernel_y + k_h, kernel_x + k_w)];
cur_val += target_inp * target_weight;
}
}
}
out[get_index(N, num_filter, out_size, out_size, n, k_d, h, w)] = cur_val;
}
}
}
__global__ void matmul_kernel(float *A, float *B, float *out, int Am, int An, int Bm, int Bn) {
int i = blockIdx.y * blockDim.y + threadIdx.y;
int j = blockIdx.x * blockDim.x + threadIdx.x;
int bi = threadIdx.y;
int bj = threadIdx.x;
__shared__ float subA[LBLK * LBLK];
__shared__ float subB[LBLK * LBLK];
float sum = 0.0;
int k;
for (k = 0; k < An; k += LBLK) {
if (i < Am && k + bj < An) {
subA[RM(bi, bj, LBLK)] = A[RM(i, k + bj, An)];
} else {
subA[RM(bi, bj, LBLK)] = 0.0;
}
if (k + bi < Bm && j < Bn) {
subB[RM(bi, bj, LBLK)] = B[RM(k + bi, j, Bn)];
} else {
subB[RM(bi, bj, LBLK)] = 0.0;
}
__syncthreads();
for (int bk = 0; bk < LBLK; bk++) {
sum += subA[RM(bi, bk, LBLK)] * subB[RM(bk, bj, LBLK)];
}
__syncthreads();
}
if (i < Am && j < Bn) {
out[RM(i, j, Bn)] = sum;
}
}
extern "C" int conv_CUDA_main(float *inp, float *weight, float *bias, float *out, int stride, float *dims) {
int N = (int)dims[0];
int C = (int)dims[1];
int H = (int)dims[2];
int W = (int)dims[3];
int num_filter = (int)dims[4];
int filter_depth = (int)dims[5];
int filter_H = (int)dims[6];
int filter_W = (int)dims[7];
int out_size = (int)dims[8];
float *dev_weight, *dev_inp, *dev_bias, *dev_out;
hipMalloc(&dev_weight, num_filter * filter_depth * filter_H * filter_W * sizeof(float));
hipMalloc(&dev_inp, N * C * H * W * sizeof(float));
hipMalloc(&dev_bias, num_filter * sizeof(float));
hipMalloc(&dev_out, N * num_filter * out_size * out_size * sizeof(float));
hipMemcpy(dev_weight, weight, num_filter * filter_depth * filter_H * filter_W * sizeof(float), hipMemcpyHostToDevice);
hipMemcpy(dev_inp, inp, N * C * H * W * sizeof(float), hipMemcpyHostToDevice);
hipMemcpy(dev_bias, bias, num_filter * sizeof(float), hipMemcpyHostToDevice);
dim3 blockDim(8, 8, 8);
dim3 gridDim((out_size + blockDim.x - 1) / blockDim.x, (out_size + blockDim.y - 1) / blockDim.y, (num_filter + blockDim.z - 1) / blockDim.z);
conv_kernel<<<gridDim, blockDim>>>(dev_weight, dev_inp, dev_bias, dev_out, N, C, H, W, num_filter, filter_depth, filter_H, filter_W, out_size, stride);
hipMemcpy(out, dev_out, N * num_filter * out_size * out_size * sizeof(float), hipMemcpyDeviceToHost);
hipFree(dev_weight);
hipFree(dev_inp);
hipFree(dev_bias);
hipFree(dev_out);
return 0;
}
extern "C" int matmul_CUDA_main(float *A, float *B, float *out, int Am, int An, int Bm, int Bn) {
float *dev_A, *dev_B, *dev_bias, *dev_out;
hipMalloc(&dev_A, Am * An * sizeof(float));
hipMalloc(&dev_B, Bm * Bn * sizeof(float));
hipMalloc(&dev_out, Am * Bn * sizeof(float));
hipMemcpy(dev_A, A, Am * An * sizeof(float), hipMemcpyHostToDevice);
hipMemcpy(dev_B, B, Bm * Bn * sizeof(float), hipMemcpyHostToDevice);
dim3 blockDim(8, 8);
dim3 gridDim((Bn + blockDim.x - 1) / blockDim.x, (Am + blockDim.y - 1) / blockDim.y);
matmul_kernel<<<gridDim, blockDim>>>(dev_A, dev_B, dev_out, Am, An, Bm, Bn);
hipMemcpy(out, dev_out, Am * Bn * sizeof(float), hipMemcpyDeviceToHost);
hipFree(dev_A);
hipFree(dev_B);
hipFree(dev_out);
return 0;
} | .text
.file "cuda_blockadd.hip"
.globl _Z26__device_stub__conv_kernelPfS_S_S_iiiiiiiiii # -- Begin function _Z26__device_stub__conv_kernelPfS_S_S_iiiiiiiiii
.p2align 4, 0x90
.type _Z26__device_stub__conv_kernelPfS_S_S_iiiiiiiiii,@function
_Z26__device_stub__conv_kernelPfS_S_S_iiiiiiiiii: # @_Z26__device_stub__conv_kernelPfS_S_S_iiiiiiiiii
.cfi_startproc
# %bb.0:
subq $216, %rsp
.cfi_def_cfa_offset 224
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movl %r8d, 12(%rsp)
movl %r9d, 8(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 12(%rsp), %rax
movq %rax, 128(%rsp)
leaq 8(%rsp), %rax
movq %rax, 136(%rsp)
leaq 224(%rsp), %rax
movq %rax, 144(%rsp)
leaq 232(%rsp), %rax
movq %rax, 152(%rsp)
leaq 240(%rsp), %rax
movq %rax, 160(%rsp)
leaq 248(%rsp), %rax
movq %rax, 168(%rsp)
leaq 256(%rsp), %rax
movq %rax, 176(%rsp)
leaq 264(%rsp), %rax
movq %rax, 184(%rsp)
leaq 272(%rsp), %rax
movq %rax, 192(%rsp)
leaq 280(%rsp), %rax
movq %rax, 200(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z11conv_kernelPfS_S_S_iiiiiiiiii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $232, %rsp
.cfi_adjust_cfa_offset -232
retq
.Lfunc_end0:
.size _Z26__device_stub__conv_kernelPfS_S_S_iiiiiiiiii, .Lfunc_end0-_Z26__device_stub__conv_kernelPfS_S_S_iiiiiiiiii
.cfi_endproc
# -- End function
.globl _Z28__device_stub__matmul_kernelPfS_S_iiii # -- Begin function _Z28__device_stub__matmul_kernelPfS_S_iiii
.p2align 4, 0x90
.type _Z28__device_stub__matmul_kernelPfS_S_iiii,@function
_Z28__device_stub__matmul_kernelPfS_S_iiii: # @_Z28__device_stub__matmul_kernelPfS_S_iiii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 160(%rsp), %rax
movq %rax, 144(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z13matmul_kernelPfS_S_iiii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end1:
.size _Z28__device_stub__matmul_kernelPfS_S_iiii, .Lfunc_end1-_Z28__device_stub__matmul_kernelPfS_S_iiii
.cfi_endproc
# -- End function
.globl conv_CUDA_main # -- Begin function conv_CUDA_main
.p2align 4, 0x90
.type conv_CUDA_main,@function
conv_CUDA_main: # @conv_CUDA_main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $360, %rsp # imm = 0x168
.cfi_def_cfa_offset 416
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
cvttss2si (%r9), %r14d
cvttss2si 4(%r9), %r15d
cvttss2si 8(%r9), %r12d
cvttss2si 12(%r9), %r13d
cvttss2si 16(%r9), %ebp
movl %r8d, 76(%rsp) # 4-byte Spill
cvttss2si 20(%r9), %eax
movq %rcx, 152(%rsp) # 8-byte Spill
cvttss2si 24(%r9), %ecx
movq %rdx, 144(%rsp) # 8-byte Spill
cvttss2si 28(%r9), %edx
movq %rsi, 128(%rsp) # 8-byte Spill
cvttss2si 32(%r9), %esi
movq %rsi, 120(%rsp) # 8-byte Spill
movq %rdi, 136(%rsp) # 8-byte Spill
movl %eax, 56(%rsp) # 4-byte Spill
imull %ebp, %eax
movl %ecx, 52(%rsp) # 4-byte Spill
movl %edx, 48(%rsp) # 4-byte Spill
imull %edx, %ecx
imull %eax, %ecx
movslq %ecx, %rbx
shlq $2, %rbx
leaq 32(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
movl %r15d, 68(%rsp) # 4-byte Spill
movl %r15d, %eax
imull %r14d, %eax
movl %r12d, 64(%rsp) # 4-byte Spill
movl %r12d, %ecx
movl %r13d, 60(%rsp) # 4-byte Spill
imull %r13d, %ecx
imull %eax, %ecx
movslq %ecx, %r15
shlq $2, %r15
leaq 24(%rsp), %rdi
movq %r15, %rsi
callq hipMalloc
movslq %ebp, %r12
leaq (,%r12,4), %r13
leaq 16(%rsp), %rdi
movq %r13, %rsi
callq hipMalloc
movl %ebp, 44(%rsp) # 4-byte Spill
movl %ebp, %eax
movl %r14d, 72(%rsp) # 4-byte Spill
imull %r14d, %eax
movq 120(%rsp), %rbp # 8-byte Reload
movl %ebp, %ecx
imull %ebp, %ecx
imull %eax, %ecx
movslq %ecx, %r14
shlq $2, %r14
leaq 8(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
movq 32(%rsp), %rdi
movq 128(%rsp), %rsi # 8-byte Reload
movq %rbx, %rdx
movq %rbp, %rbx
movl $1, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
movq 136(%rsp), %rsi # 8-byte Reload
movq %r15, %rdx
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
movq 144(%rsp), %rsi # 8-byte Reload
movq %r13, %rdx
movl $1, %ecx
callq hipMemcpy
leal 7(%rbp), %eax
shrl $3, %eax
addl $7, %r12d
shrl $3, %r12d
movq %rax, %rdi
shlq $32, %rdi
orq %rax, %rdi
movabsq $34359738376, %rdx # imm = 0x800000008
movl %r12d, %esi
movl $8, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_2
# %bb.1:
movq 32(%rsp), %rax
movq 24(%rsp), %rcx
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
movq %rax, 232(%rsp)
movq %rcx, 224(%rsp)
movq %rdx, 216(%rsp)
movq %rsi, 208(%rsp)
movl 72(%rsp), %eax # 4-byte Reload
movl %eax, 116(%rsp)
movl 68(%rsp), %eax # 4-byte Reload
movl %eax, 112(%rsp)
movl 64(%rsp), %eax # 4-byte Reload
movl %eax, 108(%rsp)
movl 60(%rsp), %eax # 4-byte Reload
movl %eax, 104(%rsp)
movl 44(%rsp), %eax # 4-byte Reload
movl %eax, 100(%rsp)
movl 56(%rsp), %eax # 4-byte Reload
movl %eax, 96(%rsp)
movl 52(%rsp), %eax # 4-byte Reload
movl %eax, 92(%rsp)
movl 48(%rsp), %eax # 4-byte Reload
movl %eax, 88(%rsp)
movl %ebx, 84(%rsp)
movl 76(%rsp), %eax # 4-byte Reload
movl %eax, 80(%rsp)
leaq 232(%rsp), %rax
movq %rax, 240(%rsp)
leaq 224(%rsp), %rax
movq %rax, 248(%rsp)
leaq 216(%rsp), %rax
movq %rax, 256(%rsp)
leaq 208(%rsp), %rax
movq %rax, 264(%rsp)
leaq 116(%rsp), %rax
movq %rax, 272(%rsp)
leaq 112(%rsp), %rax
movq %rax, 280(%rsp)
leaq 108(%rsp), %rax
movq %rax, 288(%rsp)
leaq 104(%rsp), %rax
movq %rax, 296(%rsp)
leaq 100(%rsp), %rax
movq %rax, 304(%rsp)
leaq 96(%rsp), %rax
movq %rax, 312(%rsp)
leaq 92(%rsp), %rax
movq %rax, 320(%rsp)
leaq 88(%rsp), %rax
movq %rax, 328(%rsp)
leaq 84(%rsp), %rax
movq %rax, 336(%rsp)
leaq 80(%rsp), %rax
movq %rax, 344(%rsp)
leaq 192(%rsp), %rdi
leaq 176(%rsp), %rsi
leaq 168(%rsp), %rdx
leaq 160(%rsp), %rcx
callq __hipPopCallConfiguration
movq 192(%rsp), %rsi
movl 200(%rsp), %edx
movq 176(%rsp), %rcx
movl 184(%rsp), %r8d
leaq 240(%rsp), %r9
movl $_Z11conv_kernelPfS_S_S_iiiiiiiiii, %edi
pushq 160(%rsp)
.cfi_adjust_cfa_offset 8
pushq 176(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_2:
movq 8(%rsp), %rsi
movq 152(%rsp), %rdi # 8-byte Reload
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
movq 32(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $360, %rsp # imm = 0x168
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size conv_CUDA_main, .Lfunc_end2-conv_CUDA_main
.cfi_endproc
# -- End function
.globl matmul_CUDA_main # -- Begin function matmul_CUDA_main
.p2align 4, 0x90
.type matmul_CUDA_main,@function
matmul_CUDA_main: # @matmul_CUDA_main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $200, %rsp
.cfi_def_cfa_offset 256
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %r9d, %r14d
movl %ecx, %r12d
movq %rdx, 64(%rsp) # 8-byte Spill
movq %rsi, 56(%rsp) # 8-byte Spill
movq %rdi, %r13
movl 256(%rsp), %ebx
movl %r8d, 32(%rsp) # 4-byte Spill
movl %r8d, %eax
imull %ecx, %eax
movslq %eax, %rbp
shlq $2, %rbp
leaq 24(%rsp), %rdi
movq %rbp, %rsi
callq hipMalloc
movl %ebx, %eax
movl %r14d, 36(%rsp) # 4-byte Spill
imull %r14d, %eax
movslq %eax, %r15
shlq $2, %r15
leaq 16(%rsp), %rdi
movq %r15, %rsi
callq hipMalloc
movl %ebx, %eax
imull %r12d, %eax
movslq %eax, %r14
shlq $2, %r14
leaq 8(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
movq 24(%rsp), %rdi
movq %r13, %rsi
movq %rbp, %rdx
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
movq 56(%rsp), %rsi # 8-byte Reload
movq %r15, %rdx
movl $1, %ecx
callq hipMemcpy
leal 7(%rbx), %eax
shrl $3, %eax
leal 7(%r12), %edi
shrl $3, %edi
shlq $32, %rdi
orq %rax, %rdi
movabsq $34359738376, %rdx # imm = 0x800000008
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_2
# %bb.1:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 136(%rsp)
movq %rcx, 128(%rsp)
movq %rdx, 120(%rsp)
movl %r12d, 52(%rsp)
movl 32(%rsp), %eax # 4-byte Reload
movl %eax, 48(%rsp)
movl 36(%rsp), %eax # 4-byte Reload
movl %eax, 44(%rsp)
movl %ebx, 40(%rsp)
leaq 136(%rsp), %rax
movq %rax, 144(%rsp)
leaq 128(%rsp), %rax
movq %rax, 152(%rsp)
leaq 120(%rsp), %rax
movq %rax, 160(%rsp)
leaq 52(%rsp), %rax
movq %rax, 168(%rsp)
leaq 48(%rsp), %rax
movq %rax, 176(%rsp)
leaq 44(%rsp), %rax
movq %rax, 184(%rsp)
leaq 40(%rsp), %rax
movq %rax, 192(%rsp)
leaq 104(%rsp), %rdi
leaq 88(%rsp), %rsi
leaq 80(%rsp), %rdx
leaq 72(%rsp), %rcx
callq __hipPopCallConfiguration
movq 104(%rsp), %rsi
movl 112(%rsp), %edx
movq 88(%rsp), %rcx
movl 96(%rsp), %r8d
leaq 144(%rsp), %r9
movl $_Z13matmul_kernelPfS_S_iiii, %edi
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
pushq 88(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_2:
movq 8(%rsp), %rsi
movq 64(%rsp), %rdi # 8-byte Reload
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $200, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size matmul_CUDA_main, .Lfunc_end3-matmul_CUDA_main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11conv_kernelPfS_S_S_iiiiiiiiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13matmul_kernelPfS_S_iiii, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z11conv_kernelPfS_S_S_iiiiiiiiii,@object # @_Z11conv_kernelPfS_S_S_iiiiiiiiii
.section .rodata,"a",@progbits
.globl _Z11conv_kernelPfS_S_S_iiiiiiiiii
.p2align 3, 0x0
_Z11conv_kernelPfS_S_S_iiiiiiiiii:
.quad _Z26__device_stub__conv_kernelPfS_S_S_iiiiiiiiii
.size _Z11conv_kernelPfS_S_S_iiiiiiiiii, 8
.type _Z13matmul_kernelPfS_S_iiii,@object # @_Z13matmul_kernelPfS_S_iiii
.globl _Z13matmul_kernelPfS_S_iiii
.p2align 3, 0x0
_Z13matmul_kernelPfS_S_iiii:
.quad _Z28__device_stub__matmul_kernelPfS_S_iiii
.size _Z13matmul_kernelPfS_S_iiii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z11conv_kernelPfS_S_S_iiiiiiiiii"
.size .L__unnamed_1, 34
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z13matmul_kernelPfS_S_iiii"
.size .L__unnamed_2, 28
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__conv_kernelPfS_S_S_iiiiiiiiii
.addrsig_sym _Z28__device_stub__matmul_kernelPfS_S_iiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11conv_kernelPfS_S_S_iiiiiiiiii
.addrsig_sym _Z13matmul_kernelPfS_S_iiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00036cd8_00000000-6_cuda_blockadd.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2063:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2063:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z9get_indexiiiiiiii
.type _Z9get_indexiiiiiiii, @function
_Z9get_indexiiiiiiii:
.LFB2057:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size _Z9get_indexiiiiiiii, .-_Z9get_indexiiiiiiii
.globl _Z2RMiii
.type _Z2RMiii, @function
_Z2RMiii:
.LFB2058:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2058:
.size _Z2RMiii, .-_Z2RMiii
.globl _Z47__device_stub__Z11conv_kernelPfS_S_S_iiiiiiiiiiPfS_S_S_iiiiiiiiii
.type _Z47__device_stub__Z11conv_kernelPfS_S_S_iiiiiiiiiiPfS_S_S_iiiiiiiiii, @function
_Z47__device_stub__Z11conv_kernelPfS_S_S_iiiiiiiiiiPfS_S_S_iiiiiiiiii:
.LFB2085:
.cfi_startproc
endbr64
subq $248, %rsp
.cfi_def_cfa_offset 256
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movl %r8d, 12(%rsp)
movl %r9d, 8(%rsp)
movq %fs:40, %rax
movq %rax, 232(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 12(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
leaq 256(%rsp), %rax
movq %rax, 160(%rsp)
leaq 264(%rsp), %rax
movq %rax, 168(%rsp)
leaq 272(%rsp), %rax
movq %rax, 176(%rsp)
leaq 280(%rsp), %rax
movq %rax, 184(%rsp)
leaq 288(%rsp), %rax
movq %rax, 192(%rsp)
leaq 296(%rsp), %rax
movq %rax, 200(%rsp)
leaq 304(%rsp), %rax
movq %rax, 208(%rsp)
leaq 312(%rsp), %rax
movq %rax, 216(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L11
.L7:
movq 232(%rsp), %rax
subq %fs:40, %rax
jne .L12
addq $248, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 264
pushq 56(%rsp)
.cfi_def_cfa_offset 272
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z11conv_kernelPfS_S_S_iiiiiiiiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 256
jmp .L7
.L12:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2085:
.size _Z47__device_stub__Z11conv_kernelPfS_S_S_iiiiiiiiiiPfS_S_S_iiiiiiiiii, .-_Z47__device_stub__Z11conv_kernelPfS_S_S_iiiiiiiiiiPfS_S_S_iiiiiiiiii
.globl _Z11conv_kernelPfS_S_S_iiiiiiiiii
.type _Z11conv_kernelPfS_S_S_iiiiiiiiii, @function
_Z11conv_kernelPfS_S_S_iiiiiiiiii:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl 72(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 24
movl 72(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
movl 72(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 40
movl 72(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 48
movl 72(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 56
movl 72(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 64
movl 72(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 72
movl 72(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 80
call _Z47__device_stub__Z11conv_kernelPfS_S_S_iiiiiiiiiiPfS_S_S_iiiiiiiiii
addq $72, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _Z11conv_kernelPfS_S_S_iiiiiiiiii, .-_Z11conv_kernelPfS_S_S_iiiiiiiiii
.globl conv_CUDA_main
.type conv_CUDA_main, @function
conv_CUDA_main:
.LFB2059:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $152, %rsp
.cfi_def_cfa_offset 208
movq %rdi, 24(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 40(%rsp)
movq %rcx, 48(%rsp)
movl %r8d, 76(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
cvttss2sil (%r9), %r15d
cvttss2sil 4(%r9), %ebx
movl %ebx, 56(%rsp)
cvttss2sil 8(%r9), %r13d
movl %r13d, 60(%rsp)
cvttss2sil 12(%r9), %eax
movl %eax, 12(%rsp)
cvttss2sil 16(%r9), %r12d
cvttss2sil 20(%r9), %eax
movl %eax, 64(%rsp)
cvttss2sil 24(%r9), %ecx
movl %ecx, 68(%rsp)
cvttss2sil 28(%r9), %r10d
movl %r10d, 72(%rsp)
cvttss2sil 32(%r9), %r14d
imull %r12d, %eax
imull %ecx, %eax
imull %r10d, %eax
cltq
leaq 0(,%rax,4), %rcx
leaq 80(%rsp), %rdi
movq %rcx, 16(%rsp)
movq %rcx, %rsi
call cudaMalloc@PLT
imull %r15d, %ebx
movl %ebx, %ebp
imull %r13d, %ebp
movl 12(%rsp), %eax
imull %eax, %ebp
movslq %ebp, %rbp
salq $2, %rbp
leaq 88(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
movslq %r12d, %r13
salq $2, %r13
leaq 96(%rsp), %rdi
movq %r13, %rsi
call cudaMalloc@PLT
movl %r15d, %ebx
imull %r12d, %ebx
imull %r14d, %ebx
imull %r14d, %ebx
movslq %ebx, %rbx
salq $2, %rbx
leaq 104(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq 16(%rsp), %rdx
movq 32(%rsp), %rsi
movq 80(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %rbp, %rdx
movq 24(%rsp), %rsi
movq 88(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %r13, %rdx
movq 40(%rsp), %rsi
movq 96(%rsp), %rdi
call cudaMemcpy@PLT
leal 7(%r14), %eax
shrl $3, %eax
movl %eax, 124(%rsp)
movl %eax, 128(%rsp)
leal 7(%r12), %esi
shrl $3, %esi
movl $8, 112(%rsp)
movl $8, 116(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 112(%rsp), %rdx
movl $8, %ecx
movq 124(%rsp), %rdi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L19
.L16:
movl $2, %ecx
movq %rbx, %rdx
movq 104(%rsp), %rsi
movq 48(%rsp), %rdi
call cudaMemcpy@PLT
movq 80(%rsp), %rdi
call cudaFree@PLT
movq 88(%rsp), %rdi
call cudaFree@PLT
movq 96(%rsp), %rdi
call cudaFree@PLT
movq 104(%rsp), %rdi
call cudaFree@PLT
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L20
movl $0, %eax
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
movl 76(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 216
pushq %r14
.cfi_def_cfa_offset 224
movl 88(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 232
movl 92(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 240
movl 96(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 248
pushq %r12
.cfi_def_cfa_offset 256
movl 60(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 264
movl 116(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 272
movl 120(%rsp), %r9d
movl %r15d, %r8d
movq 168(%rsp), %rcx
movq 160(%rsp), %rdx
movq 152(%rsp), %rsi
movq 144(%rsp), %rdi
call _Z47__device_stub__Z11conv_kernelPfS_S_S_iiiiiiiiiiPfS_S_S_iiiiiiiiii
addq $64, %rsp
.cfi_def_cfa_offset 208
jmp .L16
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size conv_CUDA_main, .-conv_CUDA_main
.globl _Z41__device_stub__Z13matmul_kernelPfS_S_iiiiPfS_S_iiii
.type _Z41__device_stub__Z13matmul_kernelPfS_S_iiiiPfS_S_iiii, @function
_Z41__device_stub__Z13matmul_kernelPfS_S_iiiiPfS_S_iiii:
.LFB2087:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
leaq 192(%rsp), %rax
movq %rax, 160(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L25
.L21:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L26
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L25:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z13matmul_kernelPfS_S_iiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L21
.L26:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2087:
.size _Z41__device_stub__Z13matmul_kernelPfS_S_iiiiPfS_S_iiii, .-_Z41__device_stub__Z13matmul_kernelPfS_S_iiiiPfS_S_iiii
.globl _Z13matmul_kernelPfS_S_iiii
.type _Z13matmul_kernelPfS_S_iiii, @function
_Z13matmul_kernelPfS_S_iiii:
.LFB2088:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
call _Z41__device_stub__Z13matmul_kernelPfS_S_iiiiPfS_S_iiii
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2088:
.size _Z13matmul_kernelPfS_S_iiii, .-_Z13matmul_kernelPfS_S_iiii
.globl matmul_CUDA_main
.type matmul_CUDA_main, @function
matmul_CUDA_main:
.LFB2060:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $104, %rsp
.cfi_def_cfa_offset 160
movq %rdi, (%rsp)
movq %rsi, 8(%rsp)
movq %rdx, 16(%rsp)
movl %ecx, %r13d
movl %r8d, 28(%rsp)
movl %r9d, %r14d
movl 160(%rsp), %r15d
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
imull %ecx, %r8d
movslq %r8d, %r12
salq $2, %r12
leaq 40(%rsp), %rdi
movq %r12, %rsi
call cudaMalloc@PLT
movl %r14d, %ebp
imull %r15d, %ebp
movslq %ebp, %rbp
salq $2, %rbp
leaq 48(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
movl %r13d, %ebx
imull %r15d, %ebx
movslq %ebx, %rbx
salq $2, %rbx
leaq 56(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %r12, %rdx
movq (%rsp), %rsi
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %rbp, %rdx
movq 8(%rsp), %rsi
movq 48(%rsp), %rdi
call cudaMemcpy@PLT
leal 7(%r15), %eax
shrl $3, %eax
movl %eax, 76(%rsp)
leal 7(%r13), %eax
shrl $3, %eax
movl %eax, 80(%rsp)
movl $8, 64(%rsp)
movl $8, 68(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 64(%rsp), %rdx
movl $1, %ecx
movq 76(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L33
.L30:
movl $2, %ecx
movq %rbx, %rdx
movq 56(%rsp), %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq 48(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rdi
call cudaFree@PLT
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L34
movl $0, %eax
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L33:
.cfi_restore_state
subq $8, %rsp
.cfi_def_cfa_offset 168
pushq %r15
.cfi_def_cfa_offset 176
movl %r14d, %r9d
movl 44(%rsp), %r8d
movl %r13d, %ecx
movq 72(%rsp), %rdx
movq 64(%rsp), %rsi
movq 56(%rsp), %rdi
call _Z41__device_stub__Z13matmul_kernelPfS_S_iiiiPfS_S_iiii
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L30
.L34:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2060:
.size matmul_CUDA_main, .-matmul_CUDA_main
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z13matmul_kernelPfS_S_iiii"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "_Z11conv_kernelPfS_S_S_iiiiiiiiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2090:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z13matmul_kernelPfS_S_iiii(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z11conv_kernelPfS_S_S_iiiiiiiiii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2090:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "cuda_blockadd.hip"
.globl _Z26__device_stub__conv_kernelPfS_S_S_iiiiiiiiii # -- Begin function _Z26__device_stub__conv_kernelPfS_S_S_iiiiiiiiii
.p2align 4, 0x90
.type _Z26__device_stub__conv_kernelPfS_S_S_iiiiiiiiii,@function
_Z26__device_stub__conv_kernelPfS_S_S_iiiiiiiiii: # @_Z26__device_stub__conv_kernelPfS_S_S_iiiiiiiiii
.cfi_startproc
# %bb.0:
subq $216, %rsp
.cfi_def_cfa_offset 224
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movl %r8d, 12(%rsp)
movl %r9d, 8(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 12(%rsp), %rax
movq %rax, 128(%rsp)
leaq 8(%rsp), %rax
movq %rax, 136(%rsp)
leaq 224(%rsp), %rax
movq %rax, 144(%rsp)
leaq 232(%rsp), %rax
movq %rax, 152(%rsp)
leaq 240(%rsp), %rax
movq %rax, 160(%rsp)
leaq 248(%rsp), %rax
movq %rax, 168(%rsp)
leaq 256(%rsp), %rax
movq %rax, 176(%rsp)
leaq 264(%rsp), %rax
movq %rax, 184(%rsp)
leaq 272(%rsp), %rax
movq %rax, 192(%rsp)
leaq 280(%rsp), %rax
movq %rax, 200(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z11conv_kernelPfS_S_S_iiiiiiiiii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $232, %rsp
.cfi_adjust_cfa_offset -232
retq
.Lfunc_end0:
.size _Z26__device_stub__conv_kernelPfS_S_S_iiiiiiiiii, .Lfunc_end0-_Z26__device_stub__conv_kernelPfS_S_S_iiiiiiiiii
.cfi_endproc
# -- End function
.globl _Z28__device_stub__matmul_kernelPfS_S_iiii # -- Begin function _Z28__device_stub__matmul_kernelPfS_S_iiii
.p2align 4, 0x90
.type _Z28__device_stub__matmul_kernelPfS_S_iiii,@function
_Z28__device_stub__matmul_kernelPfS_S_iiii: # @_Z28__device_stub__matmul_kernelPfS_S_iiii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 160(%rsp), %rax
movq %rax, 144(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z13matmul_kernelPfS_S_iiii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end1:
.size _Z28__device_stub__matmul_kernelPfS_S_iiii, .Lfunc_end1-_Z28__device_stub__matmul_kernelPfS_S_iiii
.cfi_endproc
# -- End function
.globl conv_CUDA_main # -- Begin function conv_CUDA_main
.p2align 4, 0x90
.type conv_CUDA_main,@function
conv_CUDA_main: # @conv_CUDA_main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $360, %rsp # imm = 0x168
.cfi_def_cfa_offset 416
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
cvttss2si (%r9), %r14d
cvttss2si 4(%r9), %r15d
cvttss2si 8(%r9), %r12d
cvttss2si 12(%r9), %r13d
cvttss2si 16(%r9), %ebp
movl %r8d, 76(%rsp) # 4-byte Spill
cvttss2si 20(%r9), %eax
movq %rcx, 152(%rsp) # 8-byte Spill
cvttss2si 24(%r9), %ecx
movq %rdx, 144(%rsp) # 8-byte Spill
cvttss2si 28(%r9), %edx
movq %rsi, 128(%rsp) # 8-byte Spill
cvttss2si 32(%r9), %esi
movq %rsi, 120(%rsp) # 8-byte Spill
movq %rdi, 136(%rsp) # 8-byte Spill
movl %eax, 56(%rsp) # 4-byte Spill
imull %ebp, %eax
movl %ecx, 52(%rsp) # 4-byte Spill
movl %edx, 48(%rsp) # 4-byte Spill
imull %edx, %ecx
imull %eax, %ecx
movslq %ecx, %rbx
shlq $2, %rbx
leaq 32(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
movl %r15d, 68(%rsp) # 4-byte Spill
movl %r15d, %eax
imull %r14d, %eax
movl %r12d, 64(%rsp) # 4-byte Spill
movl %r12d, %ecx
movl %r13d, 60(%rsp) # 4-byte Spill
imull %r13d, %ecx
imull %eax, %ecx
movslq %ecx, %r15
shlq $2, %r15
leaq 24(%rsp), %rdi
movq %r15, %rsi
callq hipMalloc
movslq %ebp, %r12
leaq (,%r12,4), %r13
leaq 16(%rsp), %rdi
movq %r13, %rsi
callq hipMalloc
movl %ebp, 44(%rsp) # 4-byte Spill
movl %ebp, %eax
movl %r14d, 72(%rsp) # 4-byte Spill
imull %r14d, %eax
movq 120(%rsp), %rbp # 8-byte Reload
movl %ebp, %ecx
imull %ebp, %ecx
imull %eax, %ecx
movslq %ecx, %r14
shlq $2, %r14
leaq 8(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
movq 32(%rsp), %rdi
movq 128(%rsp), %rsi # 8-byte Reload
movq %rbx, %rdx
movq %rbp, %rbx
movl $1, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
movq 136(%rsp), %rsi # 8-byte Reload
movq %r15, %rdx
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
movq 144(%rsp), %rsi # 8-byte Reload
movq %r13, %rdx
movl $1, %ecx
callq hipMemcpy
leal 7(%rbp), %eax
shrl $3, %eax
addl $7, %r12d
shrl $3, %r12d
movq %rax, %rdi
shlq $32, %rdi
orq %rax, %rdi
movabsq $34359738376, %rdx # imm = 0x800000008
movl %r12d, %esi
movl $8, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_2
# %bb.1:
movq 32(%rsp), %rax
movq 24(%rsp), %rcx
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
movq %rax, 232(%rsp)
movq %rcx, 224(%rsp)
movq %rdx, 216(%rsp)
movq %rsi, 208(%rsp)
movl 72(%rsp), %eax # 4-byte Reload
movl %eax, 116(%rsp)
movl 68(%rsp), %eax # 4-byte Reload
movl %eax, 112(%rsp)
movl 64(%rsp), %eax # 4-byte Reload
movl %eax, 108(%rsp)
movl 60(%rsp), %eax # 4-byte Reload
movl %eax, 104(%rsp)
movl 44(%rsp), %eax # 4-byte Reload
movl %eax, 100(%rsp)
movl 56(%rsp), %eax # 4-byte Reload
movl %eax, 96(%rsp)
movl 52(%rsp), %eax # 4-byte Reload
movl %eax, 92(%rsp)
movl 48(%rsp), %eax # 4-byte Reload
movl %eax, 88(%rsp)
movl %ebx, 84(%rsp)
movl 76(%rsp), %eax # 4-byte Reload
movl %eax, 80(%rsp)
leaq 232(%rsp), %rax
movq %rax, 240(%rsp)
leaq 224(%rsp), %rax
movq %rax, 248(%rsp)
leaq 216(%rsp), %rax
movq %rax, 256(%rsp)
leaq 208(%rsp), %rax
movq %rax, 264(%rsp)
leaq 116(%rsp), %rax
movq %rax, 272(%rsp)
leaq 112(%rsp), %rax
movq %rax, 280(%rsp)
leaq 108(%rsp), %rax
movq %rax, 288(%rsp)
leaq 104(%rsp), %rax
movq %rax, 296(%rsp)
leaq 100(%rsp), %rax
movq %rax, 304(%rsp)
leaq 96(%rsp), %rax
movq %rax, 312(%rsp)
leaq 92(%rsp), %rax
movq %rax, 320(%rsp)
leaq 88(%rsp), %rax
movq %rax, 328(%rsp)
leaq 84(%rsp), %rax
movq %rax, 336(%rsp)
leaq 80(%rsp), %rax
movq %rax, 344(%rsp)
leaq 192(%rsp), %rdi
leaq 176(%rsp), %rsi
leaq 168(%rsp), %rdx
leaq 160(%rsp), %rcx
callq __hipPopCallConfiguration
movq 192(%rsp), %rsi
movl 200(%rsp), %edx
movq 176(%rsp), %rcx
movl 184(%rsp), %r8d
leaq 240(%rsp), %r9
movl $_Z11conv_kernelPfS_S_S_iiiiiiiiii, %edi
pushq 160(%rsp)
.cfi_adjust_cfa_offset 8
pushq 176(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_2:
movq 8(%rsp), %rsi
movq 152(%rsp), %rdi # 8-byte Reload
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
movq 32(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $360, %rsp # imm = 0x168
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size conv_CUDA_main, .Lfunc_end2-conv_CUDA_main
.cfi_endproc
# -- End function
.globl matmul_CUDA_main # -- Begin function matmul_CUDA_main
.p2align 4, 0x90
.type matmul_CUDA_main,@function
matmul_CUDA_main: # @matmul_CUDA_main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $200, %rsp
.cfi_def_cfa_offset 256
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %r9d, %r14d
movl %ecx, %r12d
movq %rdx, 64(%rsp) # 8-byte Spill
movq %rsi, 56(%rsp) # 8-byte Spill
movq %rdi, %r13
movl 256(%rsp), %ebx
movl %r8d, 32(%rsp) # 4-byte Spill
movl %r8d, %eax
imull %ecx, %eax
movslq %eax, %rbp
shlq $2, %rbp
leaq 24(%rsp), %rdi
movq %rbp, %rsi
callq hipMalloc
movl %ebx, %eax
movl %r14d, 36(%rsp) # 4-byte Spill
imull %r14d, %eax
movslq %eax, %r15
shlq $2, %r15
leaq 16(%rsp), %rdi
movq %r15, %rsi
callq hipMalloc
movl %ebx, %eax
imull %r12d, %eax
movslq %eax, %r14
shlq $2, %r14
leaq 8(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
movq 24(%rsp), %rdi
movq %r13, %rsi
movq %rbp, %rdx
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
movq 56(%rsp), %rsi # 8-byte Reload
movq %r15, %rdx
movl $1, %ecx
callq hipMemcpy
leal 7(%rbx), %eax
shrl $3, %eax
leal 7(%r12), %edi
shrl $3, %edi
shlq $32, %rdi
orq %rax, %rdi
movabsq $34359738376, %rdx # imm = 0x800000008
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_2
# %bb.1:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 136(%rsp)
movq %rcx, 128(%rsp)
movq %rdx, 120(%rsp)
movl %r12d, 52(%rsp)
movl 32(%rsp), %eax # 4-byte Reload
movl %eax, 48(%rsp)
movl 36(%rsp), %eax # 4-byte Reload
movl %eax, 44(%rsp)
movl %ebx, 40(%rsp)
leaq 136(%rsp), %rax
movq %rax, 144(%rsp)
leaq 128(%rsp), %rax
movq %rax, 152(%rsp)
leaq 120(%rsp), %rax
movq %rax, 160(%rsp)
leaq 52(%rsp), %rax
movq %rax, 168(%rsp)
leaq 48(%rsp), %rax
movq %rax, 176(%rsp)
leaq 44(%rsp), %rax
movq %rax, 184(%rsp)
leaq 40(%rsp), %rax
movq %rax, 192(%rsp)
leaq 104(%rsp), %rdi
leaq 88(%rsp), %rsi
leaq 80(%rsp), %rdx
leaq 72(%rsp), %rcx
callq __hipPopCallConfiguration
movq 104(%rsp), %rsi
movl 112(%rsp), %edx
movq 88(%rsp), %rcx
movl 96(%rsp), %r8d
leaq 144(%rsp), %r9
movl $_Z13matmul_kernelPfS_S_iiii, %edi
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
pushq 88(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_2:
movq 8(%rsp), %rsi
movq 64(%rsp), %rdi # 8-byte Reload
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $200, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size matmul_CUDA_main, .Lfunc_end3-matmul_CUDA_main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11conv_kernelPfS_S_S_iiiiiiiiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13matmul_kernelPfS_S_iiii, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z11conv_kernelPfS_S_S_iiiiiiiiii,@object # @_Z11conv_kernelPfS_S_S_iiiiiiiiii
.section .rodata,"a",@progbits
.globl _Z11conv_kernelPfS_S_S_iiiiiiiiii
.p2align 3, 0x0
_Z11conv_kernelPfS_S_S_iiiiiiiiii:
.quad _Z26__device_stub__conv_kernelPfS_S_S_iiiiiiiiii
.size _Z11conv_kernelPfS_S_S_iiiiiiiiii, 8
.type _Z13matmul_kernelPfS_S_iiii,@object # @_Z13matmul_kernelPfS_S_iiii
.globl _Z13matmul_kernelPfS_S_iiii
.p2align 3, 0x0
_Z13matmul_kernelPfS_S_iiii:
.quad _Z28__device_stub__matmul_kernelPfS_S_iiii
.size _Z13matmul_kernelPfS_S_iiii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z11conv_kernelPfS_S_S_iiiiiiiiii"
.size .L__unnamed_1, 34
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z13matmul_kernelPfS_S_iiii"
.size .L__unnamed_2, 28
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__conv_kernelPfS_S_S_iiiiiiiiii
.addrsig_sym _Z28__device_stub__matmul_kernelPfS_S_iiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11conv_kernelPfS_S_S_iiiiiiiiii
.addrsig_sym _Z13matmul_kernelPfS_S_iiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#define N 8192 // Number of rows/columns of the matrix.
#define TILE_DIM 32
#define SIZE N*N // Total size of a matrix.
// Compares two matrices element by element.
int isTransposed (const double* a, const double* b, const int dim) {
for (int i = 0; i < dim; i++) {
for (int j = 0; j < dim; j++) {
if(b[j + i*dim] != a[i + j*dim]) return 0;
}
}
return 1;
}
// Gpu naive transposition.
__global__ void gpuNaiveTrans (double* a, double* b, const int size,
const int brows) {
int col = blockIdx.x * TILE_DIM + threadIdx.x;
int row = blockIdx.y * TILE_DIM + threadIdx.y;
int width = gridDim.x * TILE_DIM;
for(int i = 0; i < TILE_DIM; i += brows) {
b[col * width + (row + i)] = a[(row + i) * width + col];
}
}
// Gpu optimised transposition.
__global__ void gpuOptTrans (double* a, double* b, const int size,
const int brows) {
// Buffer on the shared memory.
__shared__ double tmp[TILE_DIM][TILE_DIM];
int col = blockIdx.x * TILE_DIM + threadIdx.x;
int row = blockIdx.y * TILE_DIM + threadIdx.y;
int width = gridDim.x * TILE_DIM;
// Transposition on buffer.
for(int i = 0; i < TILE_DIM; i += brows) {
tmp[threadIdx.y + i][threadIdx.x] = a[(row + i) * width + col];
}
__syncthreads();
col = blockIdx.y * TILE_DIM + threadIdx.x;
row = blockIdx.x * TILE_DIM + threadIdx.y;
// Writing to output.
for(int i = 0; i < TILE_DIM; i += brows) {
b[col + width * (row + i)] = tmp[threadIdx.x][threadIdx.y + i];
}
}
void matrixFill (double* a, const int dim) {
for(int i = 0; i < dim; i++) {
a[i] = (double) i;
}
}
int main(int argc, char* argv[]) {
double* hostInput, * hostOutput;
double* devInput, * devOutput;
// Allocate host memory.
hostInput = (double* )malloc(SIZE * sizeof(double));
hostOutput = (double* )malloc(SIZE * sizeof(double));
// Allocate device memory.
cudaMalloc((void**)&devInput, SIZE * sizeof(double));
cudaMalloc((void**)&devOutput, SIZE * sizeof(double));
// Dimensions.
dim3 grid, block;
block.x = TILE_DIM;
block.y = atoi(argv[1])/TILE_DIM; // Threads-per-block readed as input.
grid.x = N / TILE_DIM;
grid.y = N / TILE_DIM;
printf("\n--------------------------\n");
printf("--------------------------\n\n");
printf("Threads per block = %d\n\n", atoi(argv[1]));
/// NAIVE TRANSPOSE //
// Initialise matricx.
matrixFill(hostInput, SIZE);
// Copy input to device.
cudaMemcpy(devInput, hostInput, SIZE * sizeof(double),
cudaMemcpyHostToDevice);
// Timing.
float elapsedTime = 0.0;
cudaEvent_t tStart, tEnd;
cudaEventCreate(&tStart);
cudaEventCreate(&tEnd);
cudaEventRecord(tStart);
gpuNaiveTrans<<< grid, block >>>(devInput, devOutput, N, block.y);
cudaEventRecord(tEnd);
cudaEventSynchronize(tEnd);
cudaEventElapsedTime(&elapsedTime, tStart, tEnd);
printf("NAIVE TRANSPOSE: Elapsed time: %fms\n", elapsedTime);
printf("Bandwidth: %f GB/s\n",
2 * SIZE * sizeof(double) / elapsedTime / 1000000);
// Copy output to host.
cudaMemcpy(hostOutput, devOutput, SIZE * sizeof(double),
cudaMemcpyDeviceToHost);
printf("Is the tranposition correct? %s\n",
isTransposed(hostOutput, hostInput, N) ? "CORRECT" : "ERROR!" );
/// OPTIMISED TRANSPOSE //
printf("\n\n");
// Initialise matricx.
matrixFill(hostInput, SIZE);
// Copy input to device.
cudaMemcpy(devInput, hostInput, SIZE * sizeof(double),
cudaMemcpyHostToDevice);
// Timing.
elapsedTime = 0.0;
cudaEventRecord(tStart);
gpuOptTrans<<< grid, block >>>(devInput, devOutput, N, block.y);
cudaEventRecord(tEnd);
cudaEventSynchronize(tEnd);
cudaEventElapsedTime(&elapsedTime, tStart, tEnd);
printf("OPTIMISED TRANSPOSE: Elapsed time: %fms\n", elapsedTime);
printf("Bandwidth: %f GB/s\n",
2 * SIZE * sizeof(double) / elapsedTime / 1000000);
// Copy output to host.
cudaMemcpy(hostOutput, devOutput, SIZE * sizeof(double),
cudaMemcpyDeviceToHost);
printf("Is the tranposition correct? %s\n",
isTransposed(hostOutput, hostInput, N) ? "CORRECT" : "ERROR!" );
// Freeing resources.
free(hostInput);
free(hostOutput);
cudaFree(devInput);
cudaFree(devOutput);
cudaEventDestroy(tStart);
cudaEventDestroy(tEnd);
} | .file "tmpxft_0012c7da_00000000-6_transpose.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z12isTransposedPKdS0_i
.type _Z12isTransposedPKdS0_i, @function
_Z12isTransposedPKdS0_i:
.LFB2057:
.cfi_startproc
endbr64
testl %edx, %edx
jle .L8
movslq %edx, %rax
leaq 0(,%rax,8), %r8
addq %r8, %rsi
negq %rax
leaq 0(,%rax,8), %r9
movl $0, %r10d
.L5:
leaq (%rsi,%r9), %rax
movq %rdi, %rcx
.L7:
movsd (%rax), %xmm0
ucomisd (%rcx), %xmm0
jp .L9
jne .L9
addq $8, %rax
addq %r8, %rcx
cmpq %rsi, %rax
jne .L7
addl $1, %r10d
addq %r8, %rsi
addq $8, %rdi
cmpl %r10d, %edx
jne .L5
movl $1, %eax
ret
.L8:
movl $1, %eax
ret
.L9:
movl $0, %eax
ret
.cfi_endproc
.LFE2057:
.size _Z12isTransposedPKdS0_i, .-_Z12isTransposedPKdS0_i
.globl _Z10matrixFillPdi
.type _Z10matrixFillPdi, @function
_Z10matrixFillPdi:
.LFB2058:
.cfi_startproc
endbr64
testl %esi, %esi
jle .L13
movslq %esi, %rsi
movl $0, %eax
.L15:
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
movsd %xmm0, (%rdi,%rax,8)
addq $1, %rax
cmpq %rsi, %rax
jne .L15
.L13:
ret
.cfi_endproc
.LFE2058:
.size _Z10matrixFillPdi, .-_Z10matrixFillPdi
.globl _Z37__device_stub__Z13gpuNaiveTransPdS_iiPdS_ii
.type _Z37__device_stub__Z13gpuNaiveTransPdS_iiPdS_ii, @function
_Z37__device_stub__Z13gpuNaiveTransPdS_iiPdS_ii:
.LFB2084:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L21
.L17:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L22
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L21:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z13gpuNaiveTransPdS_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L17
.L22:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z37__device_stub__Z13gpuNaiveTransPdS_iiPdS_ii, .-_Z37__device_stub__Z13gpuNaiveTransPdS_iiPdS_ii
.globl _Z13gpuNaiveTransPdS_ii
.type _Z13gpuNaiveTransPdS_ii, @function
_Z13gpuNaiveTransPdS_ii:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z37__device_stub__Z13gpuNaiveTransPdS_iiPdS_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z13gpuNaiveTransPdS_ii, .-_Z13gpuNaiveTransPdS_ii
.globl _Z35__device_stub__Z11gpuOptTransPdS_iiPdS_ii
.type _Z35__device_stub__Z11gpuOptTransPdS_iiPdS_ii, @function
_Z35__device_stub__Z11gpuOptTransPdS_iiPdS_ii:
.LFB2086:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L29
.L25:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L30
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L29:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z11gpuOptTransPdS_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L25
.L30:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2086:
.size _Z35__device_stub__Z11gpuOptTransPdS_iiPdS_ii, .-_Z35__device_stub__Z11gpuOptTransPdS_iiPdS_ii
.globl _Z11gpuOptTransPdS_ii
.type _Z11gpuOptTransPdS_ii, @function
_Z11gpuOptTransPdS_ii:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z11gpuOptTransPdS_iiPdS_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _Z11gpuOptTransPdS_ii, .-_Z11gpuOptTransPdS_ii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "CORRECT"
.LC1:
.string "ERROR!"
.LC2:
.string "\n--------------------------\n"
.LC3:
.string "--------------------------\n\n"
.LC4:
.string "Threads per block = %d\n\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC6:
.string "NAIVE TRANSPOSE: Elapsed time: %fms\n"
.section .rodata.str1.1
.LC9:
.string "Bandwidth: %f GB/s\n"
.section .rodata.str1.8
.align 8
.LC10:
.string "Is the tranposition correct? %s\n"
.section .rodata.str1.1
.LC11:
.string "\n\n"
.section .rodata.str1.8
.align 8
.LC12:
.string "OPTIMISED TRANSPOSE: Elapsed time: %fms\n"
.text
.globl main
.type main, @function
main:
.LFB2059:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $88, %rsp
.cfi_def_cfa_offset 128
movq %rsi, %r13
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $536870912, %edi
call malloc@PLT
movq %rax, %rbx
movl $536870912, %edi
call malloc@PLT
movq %rax, %rbp
leaq 16(%rsp), %rdi
movl $536870912, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $536870912, %esi
call cudaMalloc@PLT
movl $1, 56(%rsp)
movl $1, 68(%rsp)
movl $32, 60(%rsp)
movq 8(%r13), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
leal 31(%rax), %r12d
testl %eax, %eax
cmovns %eax, %r12d
sarl $5, %r12d
movl $256, 48(%rsp)
movl $256, 52(%rsp)
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 8(%r13), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movl %eax, %edx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $67108864, %esi
movq %rbx, %rdi
call _Z10matrixFillPdi
movl $1, %ecx
movl $536870912, %edx
movq %rbx, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $0x00000000, 12(%rsp)
leaq 32(%rsp), %rdi
call cudaEventCreate@PLT
leaq 40(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 32(%rsp), %rdi
call cudaEventRecord@PLT
movl %r12d, 64(%rsp)
movl 68(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movq 48(%rsp), %rdi
movl 56(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L42
.L34:
movl $0, %esi
movq 40(%rsp), %rdi
call cudaEventRecord@PLT
movq 40(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 12(%rsp), %rdi
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtss2sd 12(%rsp), %xmm0
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movss .LC7(%rip), %xmm0
divss 12(%rsp), %xmm0
divss .LC8(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl $2, %ecx
movl $536870912, %edx
movq 24(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
movl $8192, %edx
movq %rbx, %rsi
movq %rbp, %rdi
call _Z12isTransposedPKdS0_i
testl %eax, %eax
leaq .LC1(%rip), %rdx
leaq .LC0(%rip), %rax
cmovne %rax, %rdx
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $67108864, %esi
movq %rbx, %rdi
call _Z10matrixFillPdi
movl $1, %ecx
movl $536870912, %edx
movq %rbx, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $0x00000000, 12(%rsp)
movl $0, %esi
movq 32(%rsp), %rdi
call cudaEventRecord@PLT
movl 68(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movq 48(%rsp), %rdi
movl 56(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L43
.L36:
movl $0, %esi
movq 40(%rsp), %rdi
call cudaEventRecord@PLT
movq 40(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 12(%rsp), %rdi
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtss2sd 12(%rsp), %xmm0
leaq .LC12(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movss .LC7(%rip), %xmm0
divss 12(%rsp), %xmm0
divss .LC8(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl $2, %ecx
movl $536870912, %edx
movq 24(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
movl $8192, %edx
movq %rbx, %rsi
movq %rbp, %rdi
call _Z12isTransposedPKdS0_i
testl %eax, %eax
leaq .LC1(%rip), %rdx
leaq .LC0(%rip), %rax
cmovne %rax, %rdx
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rbx, %rdi
call free@PLT
movq %rbp, %rdi
call free@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaEventDestroy@PLT
movq 40(%rsp), %rdi
call cudaEventDestroy@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L44
movl $0, %eax
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L42:
.cfi_restore_state
movl %r12d, %ecx
movl $8192, %edx
movq 24(%rsp), %rsi
movq 16(%rsp), %rdi
call _Z37__device_stub__Z13gpuNaiveTransPdS_iiPdS_ii
jmp .L34
.L43:
movl %r12d, %ecx
movl $8192, %edx
movq 24(%rsp), %rsi
movq 16(%rsp), %rdi
call _Z35__device_stub__Z11gpuOptTransPdS_iiPdS_ii
jmp .L36
.L44:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size main, .-main
.section .rodata.str1.1
.LC13:
.string "_Z11gpuOptTransPdS_ii"
.LC14:
.string "_Z13gpuNaiveTransPdS_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2089:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC13(%rip), %rdx
movq %rdx, %rcx
leaq _Z11gpuOptTransPdS_ii(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC14(%rip), %rdx
movq %rdx, %rcx
leaq _Z13gpuNaiveTransPdS_ii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2089:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC7:
.long 1317011456
.align 4
.LC8:
.long 1232348160
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#define N 8192 // Number of rows/columns of the matrix.
#define TILE_DIM 32
#define SIZE N*N // Total size of a matrix.
// Compares two matrices element by element.
int isTransposed (const double* a, const double* b, const int dim) {
for (int i = 0; i < dim; i++) {
for (int j = 0; j < dim; j++) {
if(b[j + i*dim] != a[i + j*dim]) return 0;
}
}
return 1;
}
// Gpu naive transposition.
__global__ void gpuNaiveTrans (double* a, double* b, const int size,
const int brows) {
int col = blockIdx.x * TILE_DIM + threadIdx.x;
int row = blockIdx.y * TILE_DIM + threadIdx.y;
int width = gridDim.x * TILE_DIM;
for(int i = 0; i < TILE_DIM; i += brows) {
b[col * width + (row + i)] = a[(row + i) * width + col];
}
}
// Gpu optimised transposition.
__global__ void gpuOptTrans (double* a, double* b, const int size,
const int brows) {
// Buffer on the shared memory.
__shared__ double tmp[TILE_DIM][TILE_DIM];
int col = blockIdx.x * TILE_DIM + threadIdx.x;
int row = blockIdx.y * TILE_DIM + threadIdx.y;
int width = gridDim.x * TILE_DIM;
// Transposition on buffer.
for(int i = 0; i < TILE_DIM; i += brows) {
tmp[threadIdx.y + i][threadIdx.x] = a[(row + i) * width + col];
}
__syncthreads();
col = blockIdx.y * TILE_DIM + threadIdx.x;
row = blockIdx.x * TILE_DIM + threadIdx.y;
// Writing to output.
for(int i = 0; i < TILE_DIM; i += brows) {
b[col + width * (row + i)] = tmp[threadIdx.x][threadIdx.y + i];
}
}
void matrixFill (double* a, const int dim) {
for(int i = 0; i < dim; i++) {
a[i] = (double) i;
}
}
int main(int argc, char* argv[]) {
double* hostInput, * hostOutput;
double* devInput, * devOutput;
// Allocate host memory.
hostInput = (double* )malloc(SIZE * sizeof(double));
hostOutput = (double* )malloc(SIZE * sizeof(double));
// Allocate device memory.
cudaMalloc((void**)&devInput, SIZE * sizeof(double));
cudaMalloc((void**)&devOutput, SIZE * sizeof(double));
// Dimensions.
dim3 grid, block;
block.x = TILE_DIM;
block.y = atoi(argv[1])/TILE_DIM; // Threads-per-block readed as input.
grid.x = N / TILE_DIM;
grid.y = N / TILE_DIM;
printf("\n--------------------------\n");
printf("--------------------------\n\n");
printf("Threads per block = %d\n\n", atoi(argv[1]));
/// NAIVE TRANSPOSE //
// Initialise matricx.
matrixFill(hostInput, SIZE);
// Copy input to device.
cudaMemcpy(devInput, hostInput, SIZE * sizeof(double),
cudaMemcpyHostToDevice);
// Timing.
float elapsedTime = 0.0;
cudaEvent_t tStart, tEnd;
cudaEventCreate(&tStart);
cudaEventCreate(&tEnd);
cudaEventRecord(tStart);
gpuNaiveTrans<<< grid, block >>>(devInput, devOutput, N, block.y);
cudaEventRecord(tEnd);
cudaEventSynchronize(tEnd);
cudaEventElapsedTime(&elapsedTime, tStart, tEnd);
printf("NAIVE TRANSPOSE: Elapsed time: %fms\n", elapsedTime);
printf("Bandwidth: %f GB/s\n",
2 * SIZE * sizeof(double) / elapsedTime / 1000000);
// Copy output to host.
cudaMemcpy(hostOutput, devOutput, SIZE * sizeof(double),
cudaMemcpyDeviceToHost);
printf("Is the tranposition correct? %s\n",
isTransposed(hostOutput, hostInput, N) ? "CORRECT" : "ERROR!" );
/// OPTIMISED TRANSPOSE //
printf("\n\n");
// Initialise matricx.
matrixFill(hostInput, SIZE);
// Copy input to device.
cudaMemcpy(devInput, hostInput, SIZE * sizeof(double),
cudaMemcpyHostToDevice);
// Timing.
elapsedTime = 0.0;
cudaEventRecord(tStart);
gpuOptTrans<<< grid, block >>>(devInput, devOutput, N, block.y);
cudaEventRecord(tEnd);
cudaEventSynchronize(tEnd);
cudaEventElapsedTime(&elapsedTime, tStart, tEnd);
printf("OPTIMISED TRANSPOSE: Elapsed time: %fms\n", elapsedTime);
printf("Bandwidth: %f GB/s\n",
2 * SIZE * sizeof(double) / elapsedTime / 1000000);
// Copy output to host.
cudaMemcpy(hostOutput, devOutput, SIZE * sizeof(double),
cudaMemcpyDeviceToHost);
printf("Is the tranposition correct? %s\n",
isTransposed(hostOutput, hostInput, N) ? "CORRECT" : "ERROR!" );
// Freeing resources.
free(hostInput);
free(hostOutput);
cudaFree(devInput);
cudaFree(devOutput);
cudaEventDestroy(tStart);
cudaEventDestroy(tEnd);
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#define N 8192 // Number of rows/columns of the matrix.
#define TILE_DIM 32
#define SIZE N*N // Total size of a matrix.
// Compares two matrices element by element.
int isTransposed (const double* a, const double* b, const int dim) {
for (int i = 0; i < dim; i++) {
for (int j = 0; j < dim; j++) {
if(b[j + i*dim] != a[i + j*dim]) return 0;
}
}
return 1;
}
// Gpu naive transposition.
__global__ void gpuNaiveTrans (double* a, double* b, const int size,
const int brows) {
int col = blockIdx.x * TILE_DIM + threadIdx.x;
int row = blockIdx.y * TILE_DIM + threadIdx.y;
int width = gridDim.x * TILE_DIM;
for(int i = 0; i < TILE_DIM; i += brows) {
b[col * width + (row + i)] = a[(row + i) * width + col];
}
}
// Gpu optimised transposition.
__global__ void gpuOptTrans (double* a, double* b, const int size,
const int brows) {
// Buffer on the shared memory.
__shared__ double tmp[TILE_DIM][TILE_DIM];
int col = blockIdx.x * TILE_DIM + threadIdx.x;
int row = blockIdx.y * TILE_DIM + threadIdx.y;
int width = gridDim.x * TILE_DIM;
// Transposition on buffer.
for(int i = 0; i < TILE_DIM; i += brows) {
tmp[threadIdx.y + i][threadIdx.x] = a[(row + i) * width + col];
}
__syncthreads();
col = blockIdx.y * TILE_DIM + threadIdx.x;
row = blockIdx.x * TILE_DIM + threadIdx.y;
// Writing to output.
for(int i = 0; i < TILE_DIM; i += brows) {
b[col + width * (row + i)] = tmp[threadIdx.x][threadIdx.y + i];
}
}
void matrixFill (double* a, const int dim) {
for(int i = 0; i < dim; i++) {
a[i] = (double) i;
}
}
int main(int argc, char* argv[]) {
double* hostInput, * hostOutput;
double* devInput, * devOutput;
// Allocate host memory.
hostInput = (double* )malloc(SIZE * sizeof(double));
hostOutput = (double* )malloc(SIZE * sizeof(double));
// Allocate device memory.
hipMalloc((void**)&devInput, SIZE * sizeof(double));
hipMalloc((void**)&devOutput, SIZE * sizeof(double));
// Dimensions.
dim3 grid, block;
block.x = TILE_DIM;
block.y = atoi(argv[1])/TILE_DIM; // Threads-per-block readed as input.
grid.x = N / TILE_DIM;
grid.y = N / TILE_DIM;
printf("\n--------------------------\n");
printf("--------------------------\n\n");
printf("Threads per block = %d\n\n", atoi(argv[1]));
/// NAIVE TRANSPOSE //
// Initialise matricx.
matrixFill(hostInput, SIZE);
// Copy input to device.
hipMemcpy(devInput, hostInput, SIZE * sizeof(double),
hipMemcpyHostToDevice);
// Timing.
float elapsedTime = 0.0;
hipEvent_t tStart, tEnd;
hipEventCreate(&tStart);
hipEventCreate(&tEnd);
hipEventRecord(tStart);
gpuNaiveTrans<<< grid, block >>>(devInput, devOutput, N, block.y);
hipEventRecord(tEnd);
hipEventSynchronize(tEnd);
hipEventElapsedTime(&elapsedTime, tStart, tEnd);
printf("NAIVE TRANSPOSE: Elapsed time: %fms\n", elapsedTime);
printf("Bandwidth: %f GB/s\n",
2 * SIZE * sizeof(double) / elapsedTime / 1000000);
// Copy output to host.
hipMemcpy(hostOutput, devOutput, SIZE * sizeof(double),
hipMemcpyDeviceToHost);
printf("Is the tranposition correct? %s\n",
isTransposed(hostOutput, hostInput, N) ? "CORRECT" : "ERROR!" );
/// OPTIMISED TRANSPOSE //
printf("\n\n");
// Initialise matricx.
matrixFill(hostInput, SIZE);
// Copy input to device.
hipMemcpy(devInput, hostInput, SIZE * sizeof(double),
hipMemcpyHostToDevice);
// Timing.
elapsedTime = 0.0;
hipEventRecord(tStart);
gpuOptTrans<<< grid, block >>>(devInput, devOutput, N, block.y);
hipEventRecord(tEnd);
hipEventSynchronize(tEnd);
hipEventElapsedTime(&elapsedTime, tStart, tEnd);
printf("OPTIMISED TRANSPOSE: Elapsed time: %fms\n", elapsedTime);
printf("Bandwidth: %f GB/s\n",
2 * SIZE * sizeof(double) / elapsedTime / 1000000);
// Copy output to host.
hipMemcpy(hostOutput, devOutput, SIZE * sizeof(double),
hipMemcpyDeviceToHost);
printf("Is the tranposition correct? %s\n",
isTransposed(hostOutput, hostInput, N) ? "CORRECT" : "ERROR!" );
// Freeing resources.
free(hostInput);
free(hostOutput);
hipFree(devInput);
hipFree(devOutput);
hipEventDestroy(tStart);
hipEventDestroy(tEnd);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#define N 8192 // Number of rows/columns of the matrix.
#define TILE_DIM 32
#define SIZE N*N // Total size of a matrix.
// Compares two matrices element by element.
int isTransposed (const double* a, const double* b, const int dim) {
for (int i = 0; i < dim; i++) {
for (int j = 0; j < dim; j++) {
if(b[j + i*dim] != a[i + j*dim]) return 0;
}
}
return 1;
}
// Gpu naive transposition.
__global__ void gpuNaiveTrans (double* a, double* b, const int size,
const int brows) {
int col = blockIdx.x * TILE_DIM + threadIdx.x;
int row = blockIdx.y * TILE_DIM + threadIdx.y;
int width = gridDim.x * TILE_DIM;
for(int i = 0; i < TILE_DIM; i += brows) {
b[col * width + (row + i)] = a[(row + i) * width + col];
}
}
// Gpu optimised transposition.
__global__ void gpuOptTrans (double* a, double* b, const int size,
const int brows) {
// Buffer on the shared memory.
__shared__ double tmp[TILE_DIM][TILE_DIM];
int col = blockIdx.x * TILE_DIM + threadIdx.x;
int row = blockIdx.y * TILE_DIM + threadIdx.y;
int width = gridDim.x * TILE_DIM;
// Transposition on buffer.
for(int i = 0; i < TILE_DIM; i += brows) {
tmp[threadIdx.y + i][threadIdx.x] = a[(row + i) * width + col];
}
__syncthreads();
col = blockIdx.y * TILE_DIM + threadIdx.x;
row = blockIdx.x * TILE_DIM + threadIdx.y;
// Writing to output.
for(int i = 0; i < TILE_DIM; i += brows) {
b[col + width * (row + i)] = tmp[threadIdx.x][threadIdx.y + i];
}
}
void matrixFill (double* a, const int dim) {
for(int i = 0; i < dim; i++) {
a[i] = (double) i;
}
}
int main(int argc, char* argv[]) {
double* hostInput, * hostOutput;
double* devInput, * devOutput;
// Allocate host memory.
hostInput = (double* )malloc(SIZE * sizeof(double));
hostOutput = (double* )malloc(SIZE * sizeof(double));
// Allocate device memory.
hipMalloc((void**)&devInput, SIZE * sizeof(double));
hipMalloc((void**)&devOutput, SIZE * sizeof(double));
// Dimensions.
dim3 grid, block;
block.x = TILE_DIM;
block.y = atoi(argv[1])/TILE_DIM; // Threads-per-block readed as input.
grid.x = N / TILE_DIM;
grid.y = N / TILE_DIM;
printf("\n--------------------------\n");
printf("--------------------------\n\n");
printf("Threads per block = %d\n\n", atoi(argv[1]));
/// NAIVE TRANSPOSE //
// Initialise matricx.
matrixFill(hostInput, SIZE);
// Copy input to device.
hipMemcpy(devInput, hostInput, SIZE * sizeof(double),
hipMemcpyHostToDevice);
// Timing.
float elapsedTime = 0.0;
hipEvent_t tStart, tEnd;
hipEventCreate(&tStart);
hipEventCreate(&tEnd);
hipEventRecord(tStart);
gpuNaiveTrans<<< grid, block >>>(devInput, devOutput, N, block.y);
hipEventRecord(tEnd);
hipEventSynchronize(tEnd);
hipEventElapsedTime(&elapsedTime, tStart, tEnd);
printf("NAIVE TRANSPOSE: Elapsed time: %fms\n", elapsedTime);
printf("Bandwidth: %f GB/s\n",
2 * SIZE * sizeof(double) / elapsedTime / 1000000);
// Copy output to host.
hipMemcpy(hostOutput, devOutput, SIZE * sizeof(double),
hipMemcpyDeviceToHost);
printf("Is the tranposition correct? %s\n",
isTransposed(hostOutput, hostInput, N) ? "CORRECT" : "ERROR!" );
/// OPTIMISED TRANSPOSE //
printf("\n\n");
// Initialise matricx.
matrixFill(hostInput, SIZE);
// Copy input to device.
hipMemcpy(devInput, hostInput, SIZE * sizeof(double),
hipMemcpyHostToDevice);
// Timing.
elapsedTime = 0.0;
hipEventRecord(tStart);
gpuOptTrans<<< grid, block >>>(devInput, devOutput, N, block.y);
hipEventRecord(tEnd);
hipEventSynchronize(tEnd);
hipEventElapsedTime(&elapsedTime, tStart, tEnd);
printf("OPTIMISED TRANSPOSE: Elapsed time: %fms\n", elapsedTime);
printf("Bandwidth: %f GB/s\n",
2 * SIZE * sizeof(double) / elapsedTime / 1000000);
// Copy output to host.
hipMemcpy(hostOutput, devOutput, SIZE * sizeof(double),
hipMemcpyDeviceToHost);
printf("Is the tranposition correct? %s\n",
isTransposed(hostOutput, hostInput, N) ? "CORRECT" : "ERROR!" );
// Freeing resources.
free(hostInput);
free(hostOutput);
hipFree(devInput);
hipFree(devOutput);
hipEventDestroy(tStart);
hipEventDestroy(tEnd);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z13gpuNaiveTransPdS_ii
.globl _Z13gpuNaiveTransPdS_ii
.p2align 8
.type _Z13gpuNaiveTransPdS_ii,@function
_Z13gpuNaiveTransPdS_ii:
s_load_b64 s[4:5], s[0:1], 0x14
v_and_b32_e32 v1, 0x3ff, v0
v_bfe_u32 v0, v0, 10, 10
s_lshl_b32 s6, s14, 5
s_lshl_b32 s7, s15, 5
s_load_b128 s[0:3], s[0:1], 0x0
v_add_nc_u32_e32 v2, s6, v1
v_add_nc_u32_e32 v3, s7, v0
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_lo_u32 v2, s5, v2
v_mul_lo_u32 v3, s5, v3
s_mul_i32 s5, s5, s4
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
s_lshl_b32 s5, s5, 5
v_lshlrev_b32_e32 v2, 5, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b32_e32 v3, 5, v3
v_add3_u32 v2, v0, v2, s7
s_delay_alu instid0(VALU_DEP_2)
v_add3_u32 v0, v1, v3, s6
s_mov_b32 s6, 0
.p2align 6
.LBB0_1:
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_ashrrev_i32_e32 v1, 31, v0
v_add_nc_u32_e32 v5, s6, v2
s_add_i32 s6, s6, s4
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
s_cmp_gt_i32 s6, 31
v_lshlrev_b64 v[3:4], 3, v[0:1]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v6, 31, v5
v_add_nc_u32_e32 v0, s5, v0
v_lshlrev_b64 v[5:6], 3, v[5:6]
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_u32 v3, vcc_lo, s0, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
v_add_co_u32 v5, vcc_lo, s2, v5
global_load_b64 v[3:4], v[3:4], off
v_add_co_ci_u32_e32 v6, vcc_lo, s3, v6, vcc_lo
s_waitcnt vmcnt(0)
global_store_b64 v[5:6], v[3:4], off
s_cbranch_scc0 .LBB0_1
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13gpuNaiveTransPdS_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z13gpuNaiveTransPdS_ii, .Lfunc_end0-_Z13gpuNaiveTransPdS_ii
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z11gpuOptTransPdS_ii
.globl _Z11gpuOptTransPdS_ii
.p2align 8
.type _Z11gpuOptTransPdS_ii,@function
_Z11gpuOptTransPdS_ii:
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x14
s_load_b64 s[4:5], s[0:1], 0x0
v_bfe_u32 v2, v0, 10, 10
s_lshl_b32 s6, s15, 5
v_and_b32_e32 v3, 0x3ff, v0
s_lshl_b32 s8, s14, 5
s_mov_b32 s11, 0
v_add_nc_u32_e32 v1, s6, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b32_e32 v0, 3, v3
v_lshl_add_u32 v4, v2, 8, v0
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_mul_lo_u32 v1, s3, v1
s_mul_i32 s7, s3, s2
s_lshl_b32 s9, s2, 8
s_lshl_b32 s10, s7, 5
v_lshlrev_b32_e32 v1, 5, v1
s_delay_alu instid0(VALU_DEP_1)
v_add3_u32 v0, v3, v1, s8
.LBB1_1:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_ashrrev_i32_e32 v1, 31, v0
s_add_i32 s11, s11, s2
s_cmp_gt_i32 s11, 31
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[5:6], 3, v[0:1]
v_add_nc_u32_e32 v0, s10, v0
v_add_co_u32 v5, vcc_lo, s4, v5
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v6, vcc_lo, s5, v6, vcc_lo
global_load_b64 v[5:6], v[5:6], off
s_waitcnt vmcnt(0)
ds_store_b64 v4, v[5:6]
v_add_nc_u32_e32 v4, s9, v4
s_cbranch_scc0 .LBB1_1
v_add_nc_u32_e32 v0, s8, v2
s_load_b64 s[0:1], s[0:1], 0x8
v_lshlrev_b32_e32 v1, 3, v2
s_lshl_b32 s4, s2, 3
s_mov_b32 s5, 0
v_mul_lo_u32 v0, s3, v0
s_lshl_b32 s3, s7, 5
v_lshl_add_u32 v2, v3, 8, v1
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_lshlrev_b32_e32 v0, 5, v0
s_delay_alu instid0(VALU_DEP_1)
v_add3_u32 v0, v3, v0, s6
.LBB1_3:
ds_load_b64 v[3:4], v2
v_ashrrev_i32_e32 v1, 31, v0
v_add_nc_u32_e32 v2, s4, v2
s_add_i32 s5, s5, s2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
s_cmp_gt_i32 s5, 31
v_lshlrev_b64 v[5:6], 3, v[0:1]
v_add_nc_u32_e32 v0, s3, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v5, vcc_lo, s0, v5
v_add_co_ci_u32_e32 v6, vcc_lo, s1, v6, vcc_lo
s_waitcnt lgkmcnt(0)
global_store_b64 v[5:6], v[3:4], off
s_cbranch_scc0 .LBB1_3
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11gpuOptTransPdS_ii
.amdhsa_group_segment_fixed_size 8192
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z11gpuOptTransPdS_ii, .Lfunc_end1-_Z11gpuOptTransPdS_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13gpuNaiveTransPdS_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z13gpuNaiveTransPdS_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 8192
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11gpuOptTransPdS_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z11gpuOptTransPdS_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#define N 8192 // Number of rows/columns of the matrix.
#define TILE_DIM 32
#define SIZE N*N // Total size of a matrix.
// Compares two matrices element by element.
int isTransposed (const double* a, const double* b, const int dim) {
for (int i = 0; i < dim; i++) {
for (int j = 0; j < dim; j++) {
if(b[j + i*dim] != a[i + j*dim]) return 0;
}
}
return 1;
}
// Gpu naive transposition.
__global__ void gpuNaiveTrans (double* a, double* b, const int size,
const int brows) {
int col = blockIdx.x * TILE_DIM + threadIdx.x;
int row = blockIdx.y * TILE_DIM + threadIdx.y;
int width = gridDim.x * TILE_DIM;
for(int i = 0; i < TILE_DIM; i += brows) {
b[col * width + (row + i)] = a[(row + i) * width + col];
}
}
// Gpu optimised transposition.
__global__ void gpuOptTrans (double* a, double* b, const int size,
const int brows) {
// Buffer on the shared memory.
__shared__ double tmp[TILE_DIM][TILE_DIM];
int col = blockIdx.x * TILE_DIM + threadIdx.x;
int row = blockIdx.y * TILE_DIM + threadIdx.y;
int width = gridDim.x * TILE_DIM;
// Transposition on buffer.
for(int i = 0; i < TILE_DIM; i += brows) {
tmp[threadIdx.y + i][threadIdx.x] = a[(row + i) * width + col];
}
__syncthreads();
col = blockIdx.y * TILE_DIM + threadIdx.x;
row = blockIdx.x * TILE_DIM + threadIdx.y;
// Writing to output.
for(int i = 0; i < TILE_DIM; i += brows) {
b[col + width * (row + i)] = tmp[threadIdx.x][threadIdx.y + i];
}
}
void matrixFill (double* a, const int dim) {
for(int i = 0; i < dim; i++) {
a[i] = (double) i;
}
}
int main(int argc, char* argv[]) {
double* hostInput, * hostOutput;
double* devInput, * devOutput;
// Allocate host memory.
hostInput = (double* )malloc(SIZE * sizeof(double));
hostOutput = (double* )malloc(SIZE * sizeof(double));
// Allocate device memory.
hipMalloc((void**)&devInput, SIZE * sizeof(double));
hipMalloc((void**)&devOutput, SIZE * sizeof(double));
// Dimensions.
dim3 grid, block;
block.x = TILE_DIM;
block.y = atoi(argv[1])/TILE_DIM; // Threads-per-block readed as input.
grid.x = N / TILE_DIM;
grid.y = N / TILE_DIM;
printf("\n--------------------------\n");
printf("--------------------------\n\n");
printf("Threads per block = %d\n\n", atoi(argv[1]));
/// NAIVE TRANSPOSE //
// Initialise matricx.
matrixFill(hostInput, SIZE);
// Copy input to device.
hipMemcpy(devInput, hostInput, SIZE * sizeof(double),
hipMemcpyHostToDevice);
// Timing.
float elapsedTime = 0.0;
hipEvent_t tStart, tEnd;
hipEventCreate(&tStart);
hipEventCreate(&tEnd);
hipEventRecord(tStart);
gpuNaiveTrans<<< grid, block >>>(devInput, devOutput, N, block.y);
hipEventRecord(tEnd);
hipEventSynchronize(tEnd);
hipEventElapsedTime(&elapsedTime, tStart, tEnd);
printf("NAIVE TRANSPOSE: Elapsed time: %fms\n", elapsedTime);
printf("Bandwidth: %f GB/s\n",
2 * SIZE * sizeof(double) / elapsedTime / 1000000);
// Copy output to host.
hipMemcpy(hostOutput, devOutput, SIZE * sizeof(double),
hipMemcpyDeviceToHost);
printf("Is the tranposition correct? %s\n",
isTransposed(hostOutput, hostInput, N) ? "CORRECT" : "ERROR!" );
/// OPTIMISED TRANSPOSE //
printf("\n\n");
// Initialise matricx.
matrixFill(hostInput, SIZE);
// Copy input to device.
hipMemcpy(devInput, hostInput, SIZE * sizeof(double),
hipMemcpyHostToDevice);
// Timing.
elapsedTime = 0.0;
hipEventRecord(tStart);
gpuOptTrans<<< grid, block >>>(devInput, devOutput, N, block.y);
hipEventRecord(tEnd);
hipEventSynchronize(tEnd);
hipEventElapsedTime(&elapsedTime, tStart, tEnd);
printf("OPTIMISED TRANSPOSE: Elapsed time: %fms\n", elapsedTime);
printf("Bandwidth: %f GB/s\n",
2 * SIZE * sizeof(double) / elapsedTime / 1000000);
// Copy output to host.
hipMemcpy(hostOutput, devOutput, SIZE * sizeof(double),
hipMemcpyDeviceToHost);
printf("Is the tranposition correct? %s\n",
isTransposed(hostOutput, hostInput, N) ? "CORRECT" : "ERROR!" );
// Freeing resources.
free(hostInput);
free(hostOutput);
hipFree(devInput);
hipFree(devOutput);
hipEventDestroy(tStart);
hipEventDestroy(tEnd);
} | .text
.file "transpose.hip"
.globl _Z12isTransposedPKdS0_i # -- Begin function _Z12isTransposedPKdS0_i
.p2align 4, 0x90
.type _Z12isTransposedPKdS0_i,@function
_Z12isTransposedPKdS0_i: # @_Z12isTransposedPKdS0_i
.cfi_startproc
# %bb.0:
testl %edx, %edx
setle %al
jle .LBB0_9
# %bb.1: # %.preheader.lr.ph
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movl %edx, %ecx
leaq 8(%rsi), %rdx
leaq (,%rcx,8), %r8
leaq (%rdi,%rcx,8), %r9
leaq -1(%rcx), %r10
xorl %r11d, %r11d
jmp .LBB0_2
.p2align 4, 0x90
.LBB0_7: # %.critedge
# in Loop: Header=BB0_2 Depth=1
incq %r11
cmpq %rcx, %r11
setae %al
addq %r8, %rdx
addq $8, %r9
cmpq %rcx, %r11
je .LBB0_8
.LBB0_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB0_4 Depth 2
movq %r11, %rbx
imulq %rcx, %rbx
movsd (%rsi,%rbx,8), %xmm0 # xmm0 = mem[0],zero
ucomisd (%rdi,%r11,8), %xmm0
jne .LBB0_8
jp .LBB0_8
# %bb.3: # %.lr.ph.preheader
# in Loop: Header=BB0_2 Depth=1
movq %r9, %r14
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB0_4: # %.lr.ph
# Parent Loop BB0_2 Depth=1
# => This Inner Loop Header: Depth=2
cmpq %rbx, %r10
je .LBB0_7
# %bb.5: # in Loop: Header=BB0_4 Depth=2
movsd (%rdx,%rbx,8), %xmm0 # xmm0 = mem[0],zero
incq %rbx
ucomisd (%r14), %xmm0
leaq (%r14,%r8), %r14
jne .LBB0_6
jnp .LBB0_4
.LBB0_6: # %._crit_edge39
# in Loop: Header=BB0_2 Depth=1
cmpq %rcx, %rbx
jae .LBB0_7
.LBB0_8:
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r14
.LBB0_9: # %._crit_edge
movzbl %al, %eax
andl $1, %eax
retq
.Lfunc_end0:
.size _Z12isTransposedPKdS0_i, .Lfunc_end0-_Z12isTransposedPKdS0_i
.cfi_endproc
# -- End function
.globl _Z28__device_stub__gpuNaiveTransPdS_ii # -- Begin function _Z28__device_stub__gpuNaiveTransPdS_ii
.p2align 4, 0x90
.type _Z28__device_stub__gpuNaiveTransPdS_ii,@function
_Z28__device_stub__gpuNaiveTransPdS_ii: # @_Z28__device_stub__gpuNaiveTransPdS_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z13gpuNaiveTransPdS_ii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end1:
.size _Z28__device_stub__gpuNaiveTransPdS_ii, .Lfunc_end1-_Z28__device_stub__gpuNaiveTransPdS_ii
.cfi_endproc
# -- End function
.globl _Z26__device_stub__gpuOptTransPdS_ii # -- Begin function _Z26__device_stub__gpuOptTransPdS_ii
.p2align 4, 0x90
.type _Z26__device_stub__gpuOptTransPdS_ii,@function
_Z26__device_stub__gpuOptTransPdS_ii: # @_Z26__device_stub__gpuOptTransPdS_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z11gpuOptTransPdS_ii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end2:
.size _Z26__device_stub__gpuOptTransPdS_ii, .Lfunc_end2-_Z26__device_stub__gpuOptTransPdS_ii
.cfi_endproc
# -- End function
.globl _Z10matrixFillPdi # -- Begin function _Z10matrixFillPdi
.p2align 4, 0x90
.type _Z10matrixFillPdi,@function
_Z10matrixFillPdi: # @_Z10matrixFillPdi
.cfi_startproc
# %bb.0:
testl %esi, %esi
jle .LBB3_3
# %bb.1: # %.lr.ph.preheader
movl %esi, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB3_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtsi2sd %ecx, %xmm0
movsd %xmm0, (%rdi,%rcx,8)
incq %rcx
cmpq %rcx, %rax
jne .LBB3_2
.LBB3_3: # %._crit_edge
retq
.Lfunc_end3:
.size _Z10matrixFillPdi, .Lfunc_end3-_Z10matrixFillPdi
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI4_0:
.long 0x4e800000 # float 1.07374182E+9
.LCPI4_1:
.long 0x49742400 # float 1.0E+6
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $152, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %r12
movl $536870912, %edi # imm = 0x20000000
callq malloc
movq %rax, %rbx
movl $536870912, %edi # imm = 0x20000000
callq malloc
movq %rax, %r14
leaq 40(%rsp), %rdi
movl $536870912, %esi # imm = 0x20000000
callq hipMalloc
leaq 32(%rsp), %rdi
movl $536870912, %esi # imm = 0x20000000
callq hipMalloc
movq 8(%r12), %rdi
xorl %ebp, %ebp
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
leal 31(%rax), %r13d
testl %eax, %eax
cmovnsl %eax, %r13d
sarl $5, %r13d
movq %r13, %r15
shlq $32, %r15
movl $.Lstr, %edi
callq puts@PLT
movl $.Lstr.1, %edi
callq puts@PLT
movq 8(%r12), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movl $.L.str.2, %edi
movl %eax, %esi
xorl %eax, %eax
callq printf
.p2align 4, 0x90
.LBB4_1: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtsi2sd %ebp, %xmm0
movsd %xmm0, (%rbx,%rbp,8)
incq %rbp
cmpq $67108864, %rbp # imm = 0x4000000
jne .LBB4_1
# %bb.2: # %_Z10matrixFillPdi.exit
movabsq $1099511628032, %r12 # imm = 0x10000000100
orq $32, %r15
movq 40(%rsp), %rdi
movl $536870912, %edx # imm = 0x20000000
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movl $0, 4(%rsp)
leaq 24(%rsp), %rdi
callq hipEventCreate
leaq 8(%rsp), %rdi
callq hipEventCreate
movq 24(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq %r12, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_4
# %bb.3:
movq 40(%rsp), %rax
movq 32(%rsp), %rcx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movl $8192, 20(%rsp) # imm = 0x2000
movl %r13d, 16(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 20(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 80(%rsp), %rdi
leaq 64(%rsp), %rsi
leaq 56(%rsp), %rdx
leaq 48(%rsp), %rcx
callq __hipPopCallConfiguration
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
movq 64(%rsp), %rcx
movl 72(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z13gpuNaiveTransPdS_ii, %edi
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_4:
movq 8(%rsp), %rdi
xorl %ebp, %ebp
xorl %esi, %esi
callq hipEventRecord
movq 8(%rsp), %rdi
callq hipEventSynchronize
movq 24(%rsp), %rsi
movq 8(%rsp), %rdx
leaq 4(%rsp), %rdi
callq hipEventElapsedTime
movss 4(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.3, %edi
movb $1, %al
callq printf
movss .LCPI4_0(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
divss 4(%rsp), %xmm0
divss .LCPI4_1(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movl $.L.str.4, %edi
movb $1, %al
callq printf
movq 32(%rsp), %rsi
movl $536870912, %edx # imm = 0x20000000
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
leaq 65536(%r14), %rcx
movq %rbx, %rdx
xorl %eax, %eax
.LBB4_5: # %.preheader.i
# =>This Loop Header: Depth=1
# Child Loop BB4_7 Depth 2
movq %rbp, %rsi
shlq $16, %rsi
movsd (%rbx,%rsi), %xmm0 # xmm0 = mem[0],zero
ucomisd (%r14,%rbp,8), %xmm0
jne .LBB4_10
jp .LBB4_10
# %bb.6: # %.lr.ph.preheader
# in Loop: Header=BB4_5 Depth=1
movl $1, %esi
movq %rcx, %rdi
.p2align 4, 0x90
.LBB4_7: # %.lr.ph
# Parent Loop BB4_5 Depth=1
# => This Inner Loop Header: Depth=2
cmpq $8192, %rsi # imm = 0x2000
je .LBB4_9
# %bb.8: # in Loop: Header=BB4_7 Depth=2
movsd (%rdx,%rsi,8), %xmm0 # xmm0 = mem[0],zero
incq %rsi
ucomisd (%rdi), %xmm0
leaq 65536(%rdi), %rdi
jne .LBB4_10
jnp .LBB4_7
jmp .LBB4_10
.p2align 4, 0x90
.LBB4_9: # %.critedge.i
# in Loop: Header=BB4_5 Depth=1
cmpq $8191, %rbp # imm = 0x1FFF
leaq 1(%rbp), %rsi
setae %al
addq $8, %rcx
addq $65536, %rdx # imm = 0x10000
movq %rsi, %rbp
cmpq $8192, %rsi # imm = 0x2000
jne .LBB4_5
.LBB4_10: # %_Z12isTransposedPKdS0_i.exit
movl $.L.str.6, %ecx
movl $.L.str.7, %esi
testb $1, %al
cmovneq %rcx, %rsi
xorl %ebp, %ebp
movl $.L.str.5, %edi
xorl %eax, %eax
callq printf
movl $.Lstr.2, %edi
callq puts@PLT
.p2align 4, 0x90
.LBB4_11: # %.lr.ph.i36
# =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtsi2sd %ebp, %xmm0
movsd %xmm0, (%rbx,%rbp,8)
incq %rbp
cmpq $67108864, %rbp # imm = 0x4000000
jne .LBB4_11
# %bb.12: # %_Z10matrixFillPdi.exit40
movq 40(%rsp), %rdi
movl $536870912, %edx # imm = 0x20000000
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movl $0, 4(%rsp)
movq 24(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq %r12, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_14
# %bb.13:
movq 40(%rsp), %rax
movq 32(%rsp), %rcx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movl $8192, 20(%rsp) # imm = 0x2000
movl %r13d, 16(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 20(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 80(%rsp), %rdi
leaq 64(%rsp), %rsi
leaq 56(%rsp), %rdx
leaq 48(%rsp), %rcx
callq __hipPopCallConfiguration
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
movq 64(%rsp), %rcx
movl 72(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z11gpuOptTransPdS_ii, %edi
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_14:
movq 8(%rsp), %rdi
xorl %r15d, %r15d
xorl %esi, %esi
callq hipEventRecord
movq 8(%rsp), %rdi
callq hipEventSynchronize
movq 24(%rsp), %rsi
movq 8(%rsp), %rdx
leaq 4(%rsp), %rdi
callq hipEventElapsedTime
movss 4(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.9, %edi
movb $1, %al
callq printf
movss .LCPI4_0(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
divss 4(%rsp), %xmm0
divss .LCPI4_1(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movl $.L.str.4, %edi
movb $1, %al
callq printf
movq 32(%rsp), %rsi
movl $536870912, %edx # imm = 0x20000000
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
movq %r14, %rax
addq $65536, %rax # imm = 0x10000
movq %rbx, %rdx
xorl %ecx, %ecx
.LBB4_15: # %.preheader.i47
# =>This Loop Header: Depth=1
# Child Loop BB4_17 Depth 2
movq %r15, %rsi
shlq $16, %rsi
movsd (%rbx,%rsi), %xmm0 # xmm0 = mem[0],zero
ucomisd (%r14,%r15,8), %xmm0
jne .LBB4_20
jp .LBB4_20
# %bb.16: # %.lr.ph92.preheader
# in Loop: Header=BB4_15 Depth=1
movl $1, %esi
movq %rax, %rdi
.p2align 4, 0x90
.LBB4_17: # %.lr.ph92
# Parent Loop BB4_15 Depth=1
# => This Inner Loop Header: Depth=2
cmpq $8192, %rsi # imm = 0x2000
je .LBB4_19
# %bb.18: # in Loop: Header=BB4_17 Depth=2
movsd (%rdx,%rsi,8), %xmm0 # xmm0 = mem[0],zero
incq %rsi
ucomisd (%rdi), %xmm0
leaq 65536(%rdi), %rdi
jne .LBB4_20
jnp .LBB4_17
jmp .LBB4_20
.p2align 4, 0x90
.LBB4_19: # %.critedge.i55
# in Loop: Header=BB4_15 Depth=1
cmpq $8191, %r15 # imm = 0x1FFF
leaq 1(%r15), %rsi
setae %cl
addq $8, %rax
addq $65536, %rdx # imm = 0x10000
movq %rsi, %r15
cmpq $8192, %rsi # imm = 0x2000
jne .LBB4_15
.LBB4_20: # %_Z12isTransposedPKdS0_i.exit61
movl $.L.str.6, %eax
movl $.L.str.7, %esi
testb $1, %cl
cmovneq %rax, %rsi
movl $.L.str.5, %edi
xorl %eax, %eax
callq printf
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq 40(%rsp), %rdi
callq hipFree
movq 32(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipEventDestroy
movq 8(%rsp), %rdi
callq hipEventDestroy
xorl %eax, %eax
addq $152, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end4:
.size main, .Lfunc_end4-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13gpuNaiveTransPdS_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11gpuOptTransPdS_ii, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z13gpuNaiveTransPdS_ii,@object # @_Z13gpuNaiveTransPdS_ii
.section .rodata,"a",@progbits
.globl _Z13gpuNaiveTransPdS_ii
.p2align 3, 0x0
_Z13gpuNaiveTransPdS_ii:
.quad _Z28__device_stub__gpuNaiveTransPdS_ii
.size _Z13gpuNaiveTransPdS_ii, 8
.type _Z11gpuOptTransPdS_ii,@object # @_Z11gpuOptTransPdS_ii
.globl _Z11gpuOptTransPdS_ii
.p2align 3, 0x0
_Z11gpuOptTransPdS_ii:
.quad _Z26__device_stub__gpuOptTransPdS_ii
.size _Z11gpuOptTransPdS_ii, 8
.type .L.str.2,@object # @.str.2
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.2:
.asciz "Threads per block = %d\n\n"
.size .L.str.2, 25
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "NAIVE TRANSPOSE: Elapsed time: %fms\n"
.size .L.str.3, 37
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Bandwidth: %f GB/s\n"
.size .L.str.4, 20
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Is the tranposition correct? %s\n"
.size .L.str.5, 33
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "CORRECT"
.size .L.str.6, 8
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "ERROR!"
.size .L.str.7, 7
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "OPTIMISED TRANSPOSE: Elapsed time: %fms\n"
.size .L.str.9, 41
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z13gpuNaiveTransPdS_ii"
.size .L__unnamed_1, 24
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z11gpuOptTransPdS_ii"
.size .L__unnamed_2, 22
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "\n--------------------------"
.size .Lstr, 28
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "--------------------------\n"
.size .Lstr.1, 28
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "\n"
.size .Lstr.2, 2
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__gpuNaiveTransPdS_ii
.addrsig_sym _Z26__device_stub__gpuOptTransPdS_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z13gpuNaiveTransPdS_ii
.addrsig_sym _Z11gpuOptTransPdS_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0012c7da_00000000-6_transpose.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z12isTransposedPKdS0_i
.type _Z12isTransposedPKdS0_i, @function
_Z12isTransposedPKdS0_i:
.LFB2057:
.cfi_startproc
endbr64
testl %edx, %edx
jle .L8
movslq %edx, %rax
leaq 0(,%rax,8), %r8
addq %r8, %rsi
negq %rax
leaq 0(,%rax,8), %r9
movl $0, %r10d
.L5:
leaq (%rsi,%r9), %rax
movq %rdi, %rcx
.L7:
movsd (%rax), %xmm0
ucomisd (%rcx), %xmm0
jp .L9
jne .L9
addq $8, %rax
addq %r8, %rcx
cmpq %rsi, %rax
jne .L7
addl $1, %r10d
addq %r8, %rsi
addq $8, %rdi
cmpl %r10d, %edx
jne .L5
movl $1, %eax
ret
.L8:
movl $1, %eax
ret
.L9:
movl $0, %eax
ret
.cfi_endproc
.LFE2057:
.size _Z12isTransposedPKdS0_i, .-_Z12isTransposedPKdS0_i
.globl _Z10matrixFillPdi
.type _Z10matrixFillPdi, @function
_Z10matrixFillPdi:
.LFB2058:
.cfi_startproc
endbr64
testl %esi, %esi
jle .L13
movslq %esi, %rsi
movl $0, %eax
.L15:
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
movsd %xmm0, (%rdi,%rax,8)
addq $1, %rax
cmpq %rsi, %rax
jne .L15
.L13:
ret
.cfi_endproc
.LFE2058:
.size _Z10matrixFillPdi, .-_Z10matrixFillPdi
.globl _Z37__device_stub__Z13gpuNaiveTransPdS_iiPdS_ii
.type _Z37__device_stub__Z13gpuNaiveTransPdS_iiPdS_ii, @function
_Z37__device_stub__Z13gpuNaiveTransPdS_iiPdS_ii:
.LFB2084:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L21
.L17:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L22
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L21:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z13gpuNaiveTransPdS_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L17
.L22:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z37__device_stub__Z13gpuNaiveTransPdS_iiPdS_ii, .-_Z37__device_stub__Z13gpuNaiveTransPdS_iiPdS_ii
.globl _Z13gpuNaiveTransPdS_ii
.type _Z13gpuNaiveTransPdS_ii, @function
_Z13gpuNaiveTransPdS_ii:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z37__device_stub__Z13gpuNaiveTransPdS_iiPdS_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z13gpuNaiveTransPdS_ii, .-_Z13gpuNaiveTransPdS_ii
.globl _Z35__device_stub__Z11gpuOptTransPdS_iiPdS_ii
.type _Z35__device_stub__Z11gpuOptTransPdS_iiPdS_ii, @function
_Z35__device_stub__Z11gpuOptTransPdS_iiPdS_ii:
.LFB2086:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L29
.L25:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L30
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L29:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z11gpuOptTransPdS_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L25
.L30:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2086:
.size _Z35__device_stub__Z11gpuOptTransPdS_iiPdS_ii, .-_Z35__device_stub__Z11gpuOptTransPdS_iiPdS_ii
.globl _Z11gpuOptTransPdS_ii
.type _Z11gpuOptTransPdS_ii, @function
_Z11gpuOptTransPdS_ii:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z11gpuOptTransPdS_iiPdS_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _Z11gpuOptTransPdS_ii, .-_Z11gpuOptTransPdS_ii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "CORRECT"
.LC1:
.string "ERROR!"
.LC2:
.string "\n--------------------------\n"
.LC3:
.string "--------------------------\n\n"
.LC4:
.string "Threads per block = %d\n\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC6:
.string "NAIVE TRANSPOSE: Elapsed time: %fms\n"
.section .rodata.str1.1
.LC9:
.string "Bandwidth: %f GB/s\n"
.section .rodata.str1.8
.align 8
.LC10:
.string "Is the tranposition correct? %s\n"
.section .rodata.str1.1
.LC11:
.string "\n\n"
.section .rodata.str1.8
.align 8
.LC12:
.string "OPTIMISED TRANSPOSE: Elapsed time: %fms\n"
.text
.globl main
.type main, @function
main:
.LFB2059:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $88, %rsp
.cfi_def_cfa_offset 128
movq %rsi, %r13
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $536870912, %edi
call malloc@PLT
movq %rax, %rbx
movl $536870912, %edi
call malloc@PLT
movq %rax, %rbp
leaq 16(%rsp), %rdi
movl $536870912, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $536870912, %esi
call cudaMalloc@PLT
movl $1, 56(%rsp)
movl $1, 68(%rsp)
movl $32, 60(%rsp)
movq 8(%r13), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
leal 31(%rax), %r12d
testl %eax, %eax
cmovns %eax, %r12d
sarl $5, %r12d
movl $256, 48(%rsp)
movl $256, 52(%rsp)
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 8(%r13), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movl %eax, %edx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $67108864, %esi
movq %rbx, %rdi
call _Z10matrixFillPdi
movl $1, %ecx
movl $536870912, %edx
movq %rbx, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $0x00000000, 12(%rsp)
leaq 32(%rsp), %rdi
call cudaEventCreate@PLT
leaq 40(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 32(%rsp), %rdi
call cudaEventRecord@PLT
movl %r12d, 64(%rsp)
movl 68(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movq 48(%rsp), %rdi
movl 56(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L42
.L34:
movl $0, %esi
movq 40(%rsp), %rdi
call cudaEventRecord@PLT
movq 40(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 12(%rsp), %rdi
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtss2sd 12(%rsp), %xmm0
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movss .LC7(%rip), %xmm0
divss 12(%rsp), %xmm0
divss .LC8(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl $2, %ecx
movl $536870912, %edx
movq 24(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
movl $8192, %edx
movq %rbx, %rsi
movq %rbp, %rdi
call _Z12isTransposedPKdS0_i
testl %eax, %eax
leaq .LC1(%rip), %rdx
leaq .LC0(%rip), %rax
cmovne %rax, %rdx
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $67108864, %esi
movq %rbx, %rdi
call _Z10matrixFillPdi
movl $1, %ecx
movl $536870912, %edx
movq %rbx, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $0x00000000, 12(%rsp)
movl $0, %esi
movq 32(%rsp), %rdi
call cudaEventRecord@PLT
movl 68(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movq 48(%rsp), %rdi
movl 56(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L43
.L36:
movl $0, %esi
movq 40(%rsp), %rdi
call cudaEventRecord@PLT
movq 40(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 12(%rsp), %rdi
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtss2sd 12(%rsp), %xmm0
leaq .LC12(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movss .LC7(%rip), %xmm0
divss 12(%rsp), %xmm0
divss .LC8(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl $2, %ecx
movl $536870912, %edx
movq 24(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
movl $8192, %edx
movq %rbx, %rsi
movq %rbp, %rdi
call _Z12isTransposedPKdS0_i
testl %eax, %eax
leaq .LC1(%rip), %rdx
leaq .LC0(%rip), %rax
cmovne %rax, %rdx
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rbx, %rdi
call free@PLT
movq %rbp, %rdi
call free@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaEventDestroy@PLT
movq 40(%rsp), %rdi
call cudaEventDestroy@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L44
movl $0, %eax
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L42:
.cfi_restore_state
movl %r12d, %ecx
movl $8192, %edx
movq 24(%rsp), %rsi
movq 16(%rsp), %rdi
call _Z37__device_stub__Z13gpuNaiveTransPdS_iiPdS_ii
jmp .L34
.L43:
movl %r12d, %ecx
movl $8192, %edx
movq 24(%rsp), %rsi
movq 16(%rsp), %rdi
call _Z35__device_stub__Z11gpuOptTransPdS_iiPdS_ii
jmp .L36
.L44:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size main, .-main
.section .rodata.str1.1
.LC13:
.string "_Z11gpuOptTransPdS_ii"
.LC14:
.string "_Z13gpuNaiveTransPdS_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2089:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC13(%rip), %rdx
movq %rdx, %rcx
leaq _Z11gpuOptTransPdS_ii(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC14(%rip), %rdx
movq %rdx, %rcx
leaq _Z13gpuNaiveTransPdS_ii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2089:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC7:
.long 1317011456
.align 4
.LC8:
.long 1232348160
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "transpose.hip"
.globl _Z12isTransposedPKdS0_i # -- Begin function _Z12isTransposedPKdS0_i
.p2align 4, 0x90
.type _Z12isTransposedPKdS0_i,@function
_Z12isTransposedPKdS0_i: # @_Z12isTransposedPKdS0_i
.cfi_startproc
# %bb.0:
testl %edx, %edx
setle %al
jle .LBB0_9
# %bb.1: # %.preheader.lr.ph
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movl %edx, %ecx
leaq 8(%rsi), %rdx
leaq (,%rcx,8), %r8
leaq (%rdi,%rcx,8), %r9
leaq -1(%rcx), %r10
xorl %r11d, %r11d
jmp .LBB0_2
.p2align 4, 0x90
.LBB0_7: # %.critedge
# in Loop: Header=BB0_2 Depth=1
incq %r11
cmpq %rcx, %r11
setae %al
addq %r8, %rdx
addq $8, %r9
cmpq %rcx, %r11
je .LBB0_8
.LBB0_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB0_4 Depth 2
movq %r11, %rbx
imulq %rcx, %rbx
movsd (%rsi,%rbx,8), %xmm0 # xmm0 = mem[0],zero
ucomisd (%rdi,%r11,8), %xmm0
jne .LBB0_8
jp .LBB0_8
# %bb.3: # %.lr.ph.preheader
# in Loop: Header=BB0_2 Depth=1
movq %r9, %r14
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB0_4: # %.lr.ph
# Parent Loop BB0_2 Depth=1
# => This Inner Loop Header: Depth=2
cmpq %rbx, %r10
je .LBB0_7
# %bb.5: # in Loop: Header=BB0_4 Depth=2
movsd (%rdx,%rbx,8), %xmm0 # xmm0 = mem[0],zero
incq %rbx
ucomisd (%r14), %xmm0
leaq (%r14,%r8), %r14
jne .LBB0_6
jnp .LBB0_4
.LBB0_6: # %._crit_edge39
# in Loop: Header=BB0_2 Depth=1
cmpq %rcx, %rbx
jae .LBB0_7
.LBB0_8:
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r14
.LBB0_9: # %._crit_edge
movzbl %al, %eax
andl $1, %eax
retq
.Lfunc_end0:
.size _Z12isTransposedPKdS0_i, .Lfunc_end0-_Z12isTransposedPKdS0_i
.cfi_endproc
# -- End function
.globl _Z28__device_stub__gpuNaiveTransPdS_ii # -- Begin function _Z28__device_stub__gpuNaiveTransPdS_ii
.p2align 4, 0x90
.type _Z28__device_stub__gpuNaiveTransPdS_ii,@function
_Z28__device_stub__gpuNaiveTransPdS_ii: # @_Z28__device_stub__gpuNaiveTransPdS_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z13gpuNaiveTransPdS_ii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end1:
.size _Z28__device_stub__gpuNaiveTransPdS_ii, .Lfunc_end1-_Z28__device_stub__gpuNaiveTransPdS_ii
.cfi_endproc
# -- End function
.globl _Z26__device_stub__gpuOptTransPdS_ii # -- Begin function _Z26__device_stub__gpuOptTransPdS_ii
.p2align 4, 0x90
.type _Z26__device_stub__gpuOptTransPdS_ii,@function
_Z26__device_stub__gpuOptTransPdS_ii: # @_Z26__device_stub__gpuOptTransPdS_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z11gpuOptTransPdS_ii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end2:
.size _Z26__device_stub__gpuOptTransPdS_ii, .Lfunc_end2-_Z26__device_stub__gpuOptTransPdS_ii
.cfi_endproc
# -- End function
.globl _Z10matrixFillPdi # -- Begin function _Z10matrixFillPdi
.p2align 4, 0x90
.type _Z10matrixFillPdi,@function
_Z10matrixFillPdi: # @_Z10matrixFillPdi
.cfi_startproc
# %bb.0:
testl %esi, %esi
jle .LBB3_3
# %bb.1: # %.lr.ph.preheader
movl %esi, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB3_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtsi2sd %ecx, %xmm0
movsd %xmm0, (%rdi,%rcx,8)
incq %rcx
cmpq %rcx, %rax
jne .LBB3_2
.LBB3_3: # %._crit_edge
retq
.Lfunc_end3:
.size _Z10matrixFillPdi, .Lfunc_end3-_Z10matrixFillPdi
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI4_0:
.long 0x4e800000 # float 1.07374182E+9
.LCPI4_1:
.long 0x49742400 # float 1.0E+6
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $152, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %r12
movl $536870912, %edi # imm = 0x20000000
callq malloc
movq %rax, %rbx
movl $536870912, %edi # imm = 0x20000000
callq malloc
movq %rax, %r14
leaq 40(%rsp), %rdi
movl $536870912, %esi # imm = 0x20000000
callq hipMalloc
leaq 32(%rsp), %rdi
movl $536870912, %esi # imm = 0x20000000
callq hipMalloc
movq 8(%r12), %rdi
xorl %ebp, %ebp
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
leal 31(%rax), %r13d
testl %eax, %eax
cmovnsl %eax, %r13d
sarl $5, %r13d
movq %r13, %r15
shlq $32, %r15
movl $.Lstr, %edi
callq puts@PLT
movl $.Lstr.1, %edi
callq puts@PLT
movq 8(%r12), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movl $.L.str.2, %edi
movl %eax, %esi
xorl %eax, %eax
callq printf
.p2align 4, 0x90
.LBB4_1: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtsi2sd %ebp, %xmm0
movsd %xmm0, (%rbx,%rbp,8)
incq %rbp
cmpq $67108864, %rbp # imm = 0x4000000
jne .LBB4_1
# %bb.2: # %_Z10matrixFillPdi.exit
movabsq $1099511628032, %r12 # imm = 0x10000000100
orq $32, %r15
movq 40(%rsp), %rdi
movl $536870912, %edx # imm = 0x20000000
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movl $0, 4(%rsp)
leaq 24(%rsp), %rdi
callq hipEventCreate
leaq 8(%rsp), %rdi
callq hipEventCreate
movq 24(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq %r12, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_4
# %bb.3:
movq 40(%rsp), %rax
movq 32(%rsp), %rcx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movl $8192, 20(%rsp) # imm = 0x2000
movl %r13d, 16(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 20(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 80(%rsp), %rdi
leaq 64(%rsp), %rsi
leaq 56(%rsp), %rdx
leaq 48(%rsp), %rcx
callq __hipPopCallConfiguration
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
movq 64(%rsp), %rcx
movl 72(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z13gpuNaiveTransPdS_ii, %edi
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_4:
movq 8(%rsp), %rdi
xorl %ebp, %ebp
xorl %esi, %esi
callq hipEventRecord
movq 8(%rsp), %rdi
callq hipEventSynchronize
movq 24(%rsp), %rsi
movq 8(%rsp), %rdx
leaq 4(%rsp), %rdi
callq hipEventElapsedTime
movss 4(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.3, %edi
movb $1, %al
callq printf
movss .LCPI4_0(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
divss 4(%rsp), %xmm0
divss .LCPI4_1(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movl $.L.str.4, %edi
movb $1, %al
callq printf
movq 32(%rsp), %rsi
movl $536870912, %edx # imm = 0x20000000
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
leaq 65536(%r14), %rcx
movq %rbx, %rdx
xorl %eax, %eax
.LBB4_5: # %.preheader.i
# =>This Loop Header: Depth=1
# Child Loop BB4_7 Depth 2
movq %rbp, %rsi
shlq $16, %rsi
movsd (%rbx,%rsi), %xmm0 # xmm0 = mem[0],zero
ucomisd (%r14,%rbp,8), %xmm0
jne .LBB4_10
jp .LBB4_10
# %bb.6: # %.lr.ph.preheader
# in Loop: Header=BB4_5 Depth=1
movl $1, %esi
movq %rcx, %rdi
.p2align 4, 0x90
.LBB4_7: # %.lr.ph
# Parent Loop BB4_5 Depth=1
# => This Inner Loop Header: Depth=2
cmpq $8192, %rsi # imm = 0x2000
je .LBB4_9
# %bb.8: # in Loop: Header=BB4_7 Depth=2
movsd (%rdx,%rsi,8), %xmm0 # xmm0 = mem[0],zero
incq %rsi
ucomisd (%rdi), %xmm0
leaq 65536(%rdi), %rdi
jne .LBB4_10
jnp .LBB4_7
jmp .LBB4_10
.p2align 4, 0x90
.LBB4_9: # %.critedge.i
# in Loop: Header=BB4_5 Depth=1
cmpq $8191, %rbp # imm = 0x1FFF
leaq 1(%rbp), %rsi
setae %al
addq $8, %rcx
addq $65536, %rdx # imm = 0x10000
movq %rsi, %rbp
cmpq $8192, %rsi # imm = 0x2000
jne .LBB4_5
.LBB4_10: # %_Z12isTransposedPKdS0_i.exit
movl $.L.str.6, %ecx
movl $.L.str.7, %esi
testb $1, %al
cmovneq %rcx, %rsi
xorl %ebp, %ebp
movl $.L.str.5, %edi
xorl %eax, %eax
callq printf
movl $.Lstr.2, %edi
callq puts@PLT
.p2align 4, 0x90
.LBB4_11: # %.lr.ph.i36
# =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtsi2sd %ebp, %xmm0
movsd %xmm0, (%rbx,%rbp,8)
incq %rbp
cmpq $67108864, %rbp # imm = 0x4000000
jne .LBB4_11
# %bb.12: # %_Z10matrixFillPdi.exit40
movq 40(%rsp), %rdi
movl $536870912, %edx # imm = 0x20000000
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movl $0, 4(%rsp)
movq 24(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq %r12, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_14
# %bb.13:
movq 40(%rsp), %rax
movq 32(%rsp), %rcx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movl $8192, 20(%rsp) # imm = 0x2000
movl %r13d, 16(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 20(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 80(%rsp), %rdi
leaq 64(%rsp), %rsi
leaq 56(%rsp), %rdx
leaq 48(%rsp), %rcx
callq __hipPopCallConfiguration
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
movq 64(%rsp), %rcx
movl 72(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z11gpuOptTransPdS_ii, %edi
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_14:
movq 8(%rsp), %rdi
xorl %r15d, %r15d
xorl %esi, %esi
callq hipEventRecord
movq 8(%rsp), %rdi
callq hipEventSynchronize
movq 24(%rsp), %rsi
movq 8(%rsp), %rdx
leaq 4(%rsp), %rdi
callq hipEventElapsedTime
movss 4(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.9, %edi
movb $1, %al
callq printf
movss .LCPI4_0(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
divss 4(%rsp), %xmm0
divss .LCPI4_1(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movl $.L.str.4, %edi
movb $1, %al
callq printf
movq 32(%rsp), %rsi
movl $536870912, %edx # imm = 0x20000000
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
movq %r14, %rax
addq $65536, %rax # imm = 0x10000
movq %rbx, %rdx
xorl %ecx, %ecx
.LBB4_15: # %.preheader.i47
# =>This Loop Header: Depth=1
# Child Loop BB4_17 Depth 2
movq %r15, %rsi
shlq $16, %rsi
movsd (%rbx,%rsi), %xmm0 # xmm0 = mem[0],zero
ucomisd (%r14,%r15,8), %xmm0
jne .LBB4_20
jp .LBB4_20
# %bb.16: # %.lr.ph92.preheader
# in Loop: Header=BB4_15 Depth=1
movl $1, %esi
movq %rax, %rdi
.p2align 4, 0x90
.LBB4_17: # %.lr.ph92
# Parent Loop BB4_15 Depth=1
# => This Inner Loop Header: Depth=2
cmpq $8192, %rsi # imm = 0x2000
je .LBB4_19
# %bb.18: # in Loop: Header=BB4_17 Depth=2
movsd (%rdx,%rsi,8), %xmm0 # xmm0 = mem[0],zero
incq %rsi
ucomisd (%rdi), %xmm0
leaq 65536(%rdi), %rdi
jne .LBB4_20
jnp .LBB4_17
jmp .LBB4_20
.p2align 4, 0x90
.LBB4_19: # %.critedge.i55
# in Loop: Header=BB4_15 Depth=1
cmpq $8191, %r15 # imm = 0x1FFF
leaq 1(%r15), %rsi
setae %cl
addq $8, %rax
addq $65536, %rdx # imm = 0x10000
movq %rsi, %r15
cmpq $8192, %rsi # imm = 0x2000
jne .LBB4_15
.LBB4_20: # %_Z12isTransposedPKdS0_i.exit61
movl $.L.str.6, %eax
movl $.L.str.7, %esi
testb $1, %cl
cmovneq %rax, %rsi
movl $.L.str.5, %edi
xorl %eax, %eax
callq printf
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq 40(%rsp), %rdi
callq hipFree
movq 32(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipEventDestroy
movq 8(%rsp), %rdi
callq hipEventDestroy
xorl %eax, %eax
addq $152, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end4:
.size main, .Lfunc_end4-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13gpuNaiveTransPdS_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11gpuOptTransPdS_ii, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z13gpuNaiveTransPdS_ii,@object # @_Z13gpuNaiveTransPdS_ii
.section .rodata,"a",@progbits
.globl _Z13gpuNaiveTransPdS_ii
.p2align 3, 0x0
_Z13gpuNaiveTransPdS_ii:
.quad _Z28__device_stub__gpuNaiveTransPdS_ii
.size _Z13gpuNaiveTransPdS_ii, 8
.type _Z11gpuOptTransPdS_ii,@object # @_Z11gpuOptTransPdS_ii
.globl _Z11gpuOptTransPdS_ii
.p2align 3, 0x0
_Z11gpuOptTransPdS_ii:
.quad _Z26__device_stub__gpuOptTransPdS_ii
.size _Z11gpuOptTransPdS_ii, 8
.type .L.str.2,@object # @.str.2
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.2:
.asciz "Threads per block = %d\n\n"
.size .L.str.2, 25
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "NAIVE TRANSPOSE: Elapsed time: %fms\n"
.size .L.str.3, 37
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Bandwidth: %f GB/s\n"
.size .L.str.4, 20
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Is the tranposition correct? %s\n"
.size .L.str.5, 33
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "CORRECT"
.size .L.str.6, 8
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "ERROR!"
.size .L.str.7, 7
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "OPTIMISED TRANSPOSE: Elapsed time: %fms\n"
.size .L.str.9, 41
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z13gpuNaiveTransPdS_ii"
.size .L__unnamed_1, 24
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z11gpuOptTransPdS_ii"
.size .L__unnamed_2, 22
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "\n--------------------------"
.size .Lstr, 28
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "--------------------------\n"
.size .Lstr.1, 28
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "\n"
.size .Lstr.2, 2
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__gpuNaiveTransPdS_ii
.addrsig_sym _Z26__device_stub__gpuOptTransPdS_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z13gpuNaiveTransPdS_ii
.addrsig_sym _Z11gpuOptTransPdS_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <time.h>
int generateInitialPrimes(int *intialTempArray, int **PL, int initialPrimesRange);
__global__ void calcPrimes(int *d_IL, int *d_PL, int numOfPrimes, int lenInputList);
#define LEN_IL 1000000
#define LEN_INITIAL_PRIMES 1000
#define THREADS_PER_BLOCK 32
int main() {
int *IL = NULL, *PL = NULL, *tempPL = NULL;
int *d_IL = NULL, *d_PL = NULL;
cudaEvent_t start, stop;
float time;
cudaEventCreate(&start);
cudaEventCreate(&stop);
clock_t t;
//int count = 0;
t = clock();
int numOfInitialPrimes = generateInitialPrimes(tempPL, &PL, LEN_INITIAL_PRIMES);
t = clock() - t;
double time_taken = ((double)t)/CLOCKS_PER_SEC; // in seconds
// Print the initial range of primes calculated in the CPU, which will be passed to the GPU:
printf("\nThe initial primes calculated are:\n");
for(int i=0; i < numOfInitialPrimes; i++) {
printf("%d ", PL[i]);
}
printf("\nNumber of initial primes = %d\n\n", numOfInitialPrimes);
// Space for host copies:
IL = (int*) malloc(LEN_IL * sizeof(int));
//PL = (int*) malloc(LEN_INITIAL_PRIMES * sizeof(int)); // Allocated in the generate function instead
int size_IL = LEN_IL * sizeof(int);
int size_PL = numOfInitialPrimes * sizeof(int);
// Initialize Input list: 0 -> Not prime:
for(int i=0; i<LEN_IL; i++) {
IL[i] = 1;
}
// Space for device copies:
cudaMalloc((void **) &d_IL, size_IL);
cudaMalloc((void **) &d_PL, size_PL);
// Copying the data to the device (GPU):
cudaMemcpy(d_IL, IL, size_IL, cudaMemcpyHostToDevice);
cudaMemcpy(d_PL, PL, size_PL, cudaMemcpyHostToDevice);
// Launching the kernel and measuring the time taken:
cudaEventRecord(start, 0);
calcPrimes<<<(numOfInitialPrimes/THREADS_PER_BLOCK) + 1, THREADS_PER_BLOCK>>> (d_IL, d_PL, numOfInitialPrimes, LEN_IL);
cudaEventRecord(stop, 0);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&time, start, stop);
// Space allocated to store the modified form of input array, with marking for prime and non-prime:
int *result = (int*) malloc(size_IL);
// Copy the result back to the host:
cudaMemcpy(result, d_IL, size_IL, cudaMemcpyDeviceToHost);
// Extract indexes of primes in 'result' to get the actual new prime numbers:
printf("********* New Primes List **********\n");
int *newPrimes = (int*)malloc(LEN_IL / 4 * sizeof(int)); // Arbitrary size; which is '1/4th' of numbers list size
int newPrimesCount = 0;
for(int i=LEN_INITIAL_PRIMES; i<LEN_IL; i++) {
int num = result[i];
if(num == 1) {
newPrimes[newPrimesCount] = num;
newPrimesCount++;
printf("%d ", i);
}
}
printf("\n\nNumber of new primes found = %d\n\n", newPrimesCount);
printf("Time taken to find initial primes on CPU = %f ms\n", time_taken * 1000);
printf("Parallel Job time for current iteration = %f ms\n\n", time);
// Free memory:
cudaFree(d_IL);
cudaFree(d_PL);
free(IL);
free(PL);
free(result);
free(newPrimes);
return 0;
}
// Generate initial prime numbers in the CPU:
// Returns: Number of primes found from 1 to 'LEN_INITIAL_PRIMES'
int generateInitialPrimes(int *intialTempArray, int **PL, int initialPrimesRange) {
int primesCount = 0;
//int intialTempArray[initialPrimesRange];
intialTempArray = (int*) malloc(LEN_INITIAL_PRIMES * sizeof(int));
*PL = (int*) malloc(LEN_INITIAL_PRIMES / 2 * sizeof(int)); // Taking half size of initial (full) primes array
// Initialize array with all 1's:
for(int i=0; i < initialPrimesRange; i++) {
intialTempArray[i] = 1;
}
// Make non-primes as '0':
for(int i=2; i*i <= initialPrimesRange; i++) {
for(int j=2*i; j <= initialPrimesRange; j=j+i) {
intialTempArray[j] = 0;
}
}
// Store the actual primes in a new array which will be copied later to the device (converting 'prime num indexes' to 'prime numbers') :
for(int i=2; i<=initialPrimesRange; i++) {
if(intialTempArray[i] == 1) {
(*PL)[primesCount] = i;
primesCount++;
}
}
free(intialTempArray);
return primesCount;
}
// GPU Kernel (Parallel Processing):
__global__ void calcPrimes(int *d_IL, int *d_PL, int numOfPrimes, int lenInputList) {
int index = threadIdx.x + blockIdx.x * blockDim.x;
if(index < numOfPrimes) {
for(int i = d_PL[numOfPrimes-1]+1; i < lenInputList; i++) {
if(i % d_PL[index] == 0) {
d_IL[i] = 0;
}
}
}
} | code for sm_80
Function : _Z10calcPrimesPiS_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R4, R4, c[0x0][0x0], R3 ; /* 0x0000000004047a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R4, c[0x0][0x170], PT ; /* 0x00005c0004007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff027624 */
/* 0x000fe200078e00ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0080*/ IMAD.MOV.U32 R7, RZ, RZ, 0x4 ; /* 0x00000004ff077424 */
/* 0x000fc600078e00ff */
/*0090*/ IADD3 R2, R2, -0x1, RZ ; /* 0xffffffff02027810 */
/* 0x000fca0007ffe0ff */
/*00a0*/ IMAD.WIDE R2, R2, R7, c[0x0][0x168] ; /* 0x00005a0002027625 */
/* 0x000fcc00078e0207 */
/*00b0*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea4000c1e1900 */
/*00c0*/ IADD3 R0, R2, 0x1, RZ ; /* 0x0000000102007810 */
/* 0x004fc80007ffe0ff */
/*00d0*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x174], PT ; /* 0x00005d0000007a0c */
/* 0x000fda0003f06270 */
/*00e0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00f0*/ LOP3.LUT R3, RZ, R2, RZ, 0x33, !PT ; /* 0x00000002ff037212 */
/* 0x000fe200078e33ff */
/*0100*/ IMAD.MOV.U32 R5, RZ, RZ, 0x2 ; /* 0x00000002ff057424 */
/* 0x000fc600078e00ff */
/*0110*/ IADD3 R3, R3, c[0x0][0x174], RZ ; /* 0x00005d0003037a10 */
/* 0x000fe40007ffe0ff */
/*0120*/ IADD3 R2, -R2, c[0x0][0x174], -R5 ; /* 0x00005d0002027a10 */
/* 0x000fe40007ffe905 */
/*0130*/ LOP3.LUT P1, R5, R3, 0x3, RZ, 0xc0, !PT ; /* 0x0000000303057812 */
/* 0x000fe4000782c0ff */
/*0140*/ ISETP.GE.U32.AND P0, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fe20003f06070 */
/*0150*/ IMAD.WIDE R2, R4, R7, c[0x0][0x168] ; /* 0x00005a0004027625 */
/* 0x000fd400078e0207 */
/*0160*/ @!P1 BRA 0x3b0 ; /* 0x0000024000009947 */
/* 0x000fea0003800000 */
/*0170*/ IMAD.WIDE R6, R0, R7, c[0x0][0x160] ; /* 0x0000580000067625 */
/* 0x000fc800078e0207 */
/*0180*/ IMAD.MOV.U32 R4, RZ, RZ, R6 ; /* 0x000000ffff047224 */
/* 0x000fe400078e0006 */
/*0190*/ IMAD.MOV.U32 R9, RZ, RZ, R7 ; /* 0x000000ffff097224 */
/* 0x000fe400078e0007 */
/*01a0*/ LDG.E R14, [R2.64] ; /* 0x00000004020e7981 */
/* 0x000ea2000c1e1900 */
/*01b0*/ IABS R12, R0 ; /* 0x00000000000c7213 */
/* 0x000fe40000000000 */
/*01c0*/ ISETP.GE.AND P3, PT, R0.reuse, RZ, PT ; /* 0x000000ff0000720c */
/* 0x040fe40003f66270 */
/*01d0*/ IADD3 R5, R5, -0x1, RZ ; /* 0xffffffff05057810 */
/* 0x000fe40007ffe0ff */
/*01e0*/ IADD3 R0, R0, 0x1, RZ ; /* 0x0000000100007810 */
/* 0x000fe40007ffe0ff */
/*01f0*/ IABS R10, R14 ; /* 0x0000000e000a7213 */
/* 0x004fc40000000000 */
/*0200*/ IABS R13, R14 ; /* 0x0000000e000d7213 */
/* 0x000fe40000000000 */
/*0210*/ I2F.RP R8, R10 ; /* 0x0000000a00087306 */
/* 0x001e300000209400 */
/*0220*/ MUFU.RCP R8, R8 ; /* 0x0000000800087308 */
/* 0x001e240000001000 */
/*0230*/ IADD3 R6, R8, 0xffffffe, RZ ; /* 0x0ffffffe08067810 */
/* 0x001fe20007ffe0ff */
/*0240*/ IMAD.MOV R8, RZ, RZ, -R13 ; /* 0x000000ffff087224 */
/* 0x000fca00078e0a0d */
/*0250*/ F2I.FTZ.U32.TRUNC.NTZ R7, R6 ; /* 0x0000000600077305 */
/* 0x000064000021f000 */
/*0260*/ IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff067224 */
/* 0x001fe400078e00ff */
/*0270*/ IMAD.MOV R11, RZ, RZ, -R7 ; /* 0x000000ffff0b7224 */
/* 0x002fc800078e0a07 */
/*0280*/ IMAD R11, R11, R10, RZ ; /* 0x0000000a0b0b7224 */
/* 0x000fc800078e02ff */
/*0290*/ IMAD.HI.U32 R7, R7, R11, R6 ; /* 0x0000000b07077227 */
/* 0x000fcc00078e0006 */
/*02a0*/ IMAD.HI.U32 R7, R7, R12, RZ ; /* 0x0000000c07077227 */
/* 0x000fc800078e00ff */
/*02b0*/ IMAD R7, R7, R8, R12 ; /* 0x0000000807077224 */
/* 0x000fca00078e020c */
/*02c0*/ ISETP.GT.U32.AND P1, PT, R10, R7, PT ; /* 0x000000070a00720c */
/* 0x000fda0003f24070 */
/*02d0*/ @!P1 IMAD.IADD R7, R7, 0x1, -R10 ; /* 0x0000000107079824 */
/* 0x000fe200078e0a0a */
/*02e0*/ ISETP.NE.AND P1, PT, R14, RZ, PT ; /* 0x000000ff0e00720c */
/* 0x000fc80003f25270 */
/*02f0*/ ISETP.GT.U32.AND P2, PT, R10, R7, PT ; /* 0x000000070a00720c */
/* 0x000fda0003f44070 */
/*0300*/ @!P2 IMAD.IADD R7, R7, 0x1, -R10 ; /* 0x000000010707a824 */
/* 0x000fe200078e0a0a */
/*0310*/ ISETP.NE.AND P2, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fc60003f45270 */
/*0320*/ @!P3 IMAD.MOV R7, RZ, RZ, -R7 ; /* 0x000000ffff07b224 */
/* 0x000fe200078e0a07 */
/*0330*/ @!P1 LOP3.LUT R7, RZ, R14, RZ, 0x33, !PT ; /* 0x0000000eff079212 */
/* 0x000fc800078e33ff */
/*0340*/ ISETP.NE.AND P1, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fda0003f25270 */
/*0350*/ @!P1 IMAD.MOV.U32 R6, RZ, RZ, R4 ; /* 0x000000ffff069224 */
/* 0x000fe400078e0004 */
/*0360*/ @!P1 IMAD.MOV.U32 R7, RZ, RZ, R9 ; /* 0x000000ffff079224 */
/* 0x000fca00078e0009 */
/*0370*/ @!P1 STG.E [R6.64], RZ ; /* 0x000000ff06009986 */
/* 0x0001e2000c101904 */
/*0380*/ IADD3 R4, P1, R4, 0x4, RZ ; /* 0x0000000404047810 */
/* 0x000fca0007f3e0ff */
/*0390*/ IMAD.X R9, RZ, RZ, R9, P1 ; /* 0x000000ffff097224 */
/* 0x000fe200008e0609 */
/*03a0*/ @P2 BRA 0x1a0 ; /* 0xfffffdf000002947 */
/* 0x000fea000383ffff */
/*03b0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*03c0*/ IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; /* 0x00000004ff057424 */
/* 0x000fc800078e00ff */
/*03d0*/ IMAD.WIDE R4, R0, R5, c[0x0][0x160] ; /* 0x0000580000047625 */
/* 0x000fc800078e0205 */
/*03e0*/ IMAD.MOV.U32 R8, RZ, RZ, R4 ; /* 0x000000ffff087224 */
/* 0x000fe400078e0004 */
/*03f0*/ IMAD.MOV.U32 R9, RZ, RZ, R5 ; /* 0x000000ffff097224 */
/* 0x000fe400078e0005 */
/*0400*/ LDG.E R6, [R2.64] ; /* 0x0000000402067981 */
/* 0x005ea2000c1e1900 */
/*0410*/ IABS R12, R0 ; /* 0x00000000000c7213 */
/* 0x000fe20000000000 */
/*0420*/ BSSY B0, 0x5f0 ; /* 0x000001c000007945 */
/* 0x000fe20003800000 */
/*0430*/ ISETP.GE.AND P2, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe40003f46270 */
/*0440*/ IABS R10, R6.reuse ; /* 0x00000006000a7213 */
/* 0x084fe40000000000 */
/*0450*/ IABS R13, R6 ; /* 0x00000006000d7213 */
/* 0x000fe40000000000 */
/*0460*/ I2F.RP R7, R10 ; /* 0x0000000a00077306 */
/* 0x000e300000209400 */
/*0470*/ MUFU.RCP R7, R7 ; /* 0x0000000700077308 */
/* 0x001e240000001000 */
/*0480*/ IADD3 R4, R7, 0xffffffe, RZ ; /* 0x0ffffffe07047810 */
/* 0x003fe20007ffe0ff */
/*0490*/ IMAD.MOV R7, RZ, RZ, -R13 ; /* 0x000000ffff077224 */
/* 0x000fca00078e0a0d */
/*04a0*/ F2I.FTZ.U32.TRUNC.NTZ R5, R4 ; /* 0x0000000400057305 */
/* 0x000064000021f000 */
/*04b0*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x001fe400078e00ff */
/*04c0*/ IMAD.MOV R11, RZ, RZ, -R5 ; /* 0x000000ffff0b7224 */
/* 0x002fc800078e0a05 */
/*04d0*/ IMAD R11, R11, R10, RZ ; /* 0x0000000a0b0b7224 */
/* 0x000fc800078e02ff */
/*04e0*/ IMAD.HI.U32 R5, R5, R11, R4 ; /* 0x0000000b05057227 */
/* 0x000fc800078e0004 */
/*04f0*/ IMAD.MOV.U32 R4, RZ, RZ, R8 ; /* 0x000000ffff047224 */
/* 0x000fe400078e0008 */
/*0500*/ IMAD.HI.U32 R5, R5, R12, RZ ; /* 0x0000000c05057227 */
/* 0x000fc800078e00ff */
/*0510*/ IMAD R5, R5, R7, R12 ; /* 0x0000000705057224 */
/* 0x000fca00078e020c */
/*0520*/ ISETP.GT.U32.AND P0, PT, R10, R5, PT ; /* 0x000000050a00720c */
/* 0x000fda0003f04070 */
/*0530*/ @!P0 IMAD.IADD R5, R5, 0x1, -R10 ; /* 0x0000000105058824 */
/* 0x000fe200078e0a0a */
/*0540*/ ISETP.NE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fc80003f05270 */
/*0550*/ ISETP.GT.U32.AND P1, PT, R10, R5, PT ; /* 0x000000050a00720c */
/* 0x000fda0003f24070 */
/*0560*/ @!P1 IMAD.IADD R5, R5, 0x1, -R10 ; /* 0x0000000105059824 */
/* 0x000fca00078e0a0a */
/*0570*/ @!P2 IADD3 R5, -R5, RZ, RZ ; /* 0x000000ff0505a210 */
/* 0x000fe40007ffe1ff */
/*0580*/ @!P0 LOP3.LUT R5, RZ, R6, RZ, 0x33, !PT ; /* 0x00000006ff058212 */
/* 0x000fc800078e33ff */
/*0590*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe20003f05270 */
/*05a0*/ IMAD.MOV.U32 R5, RZ, RZ, R9 ; /* 0x000000ffff057224 */
/* 0x000fd800078e0009 */
/*05b0*/ @P0 BRA 0x5e0 ; /* 0x0000002000000947 */
/* 0x000fea0003800000 */
/*05c0*/ STG.E [R4.64], RZ ; /* 0x000000ff04007986 */
/* 0x0001e8000c101904 */
/*05d0*/ LDG.E R6, [R2.64] ; /* 0x0000000402067981 */
/* 0x000164000c1e1900 */
/*05e0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*05f0*/ IABS R12, R6.reuse ; /* 0x00000006000c7213 */
/* 0x0a0fe20000000000 */
/*0600*/ BSSY B0, 0x7c0 ; /* 0x000001b000007945 */
/* 0x000fe20003800000 */
/*0610*/ IADD3 R7, R0, 0x1, RZ ; /* 0x0000000100077810 */
/* 0x000fe40007ffe0ff */
/*0620*/ I2F.RP R10, R12 ; /* 0x0000000c000a7306 */
/* 0x000e620000209400 */
/*0630*/ IABS R13, R6 ; /* 0x00000006000d7213 */
/* 0x000fe40000000000 */
/*0640*/ IABS R14, R7 ; /* 0x00000007000e7213 */
/* 0x000fc40000000000 */
/*0650*/ ISETP.GE.AND P2, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fc60003f46270 */
/*0660*/ MUFU.RCP R10, R10 ; /* 0x0000000a000a7308 */
/* 0x002e640000001000 */
/*0670*/ IADD3 R8, R10, 0xffffffe, RZ ; /* 0x0ffffffe0a087810 */
/* 0x002fcc0007ffe0ff */
/*0680*/ F2I.FTZ.U32.TRUNC.NTZ R9, R8 ; /* 0x0000000800097305 */
/* 0x0002a4000021f000 */
/*0690*/ IMAD.MOV.U32 R8, RZ, RZ, RZ ; /* 0x000000ffff087224 */
/* 0x002fe400078e00ff */
/*06a0*/ IMAD.MOV R11, RZ, RZ, -R9 ; /* 0x000000ffff0b7224 */
/* 0x004fc800078e0a09 */
/*06b0*/ IMAD R11, R11, R12, RZ ; /* 0x0000000c0b0b7224 */
/* 0x000fc800078e02ff */
/*06c0*/ IMAD.HI.U32 R9, R9, R11, R8 ; /* 0x0000000b09097227 */
/* 0x000fc800078e0008 */
/*06d0*/ IMAD.MOV R8, RZ, RZ, -R13 ; /* 0x000000ffff087224 */
/* 0x000fe400078e0a0d */
/*06e0*/ IMAD.HI.U32 R9, R9, R14, RZ ; /* 0x0000000e09097227 */
/* 0x000fc800078e00ff */
/*06f0*/ IMAD R9, R9, R8, R14 ; /* 0x0000000809097224 */
/* 0x000fca00078e020e */
/*0700*/ ISETP.GT.U32.AND P0, PT, R12, R9, PT ; /* 0x000000090c00720c */
/* 0x000fda0003f04070 */
/*0710*/ @!P0 IMAD.IADD R9, R9, 0x1, -R12 ; /* 0x0000000109098824 */
/* 0x000fe200078e0a0c */
/*0720*/ ISETP.NE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fc80003f05270 */
/*0730*/ ISETP.GT.U32.AND P1, PT, R12, R9, PT ; /* 0x000000090c00720c */
/* 0x000fda0003f24070 */
/*0740*/ @!P1 IMAD.IADD R9, R9, 0x1, -R12 ; /* 0x0000000109099824 */
/* 0x000fc800078e0a0c */
/*0750*/ @!P2 IMAD.MOV R9, RZ, RZ, -R9 ; /* 0x000000ffff09a224 */
/* 0x000fe200078e0a09 */
/*0760*/ @!P0 LOP3.LUT R9, RZ, R6, RZ, 0x33, !PT ; /* 0x00000006ff098212 */
/* 0x000fc800078e33ff */
/*0770*/ ISETP.NE.AND P0, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x000fda0003f05270 */
/*0780*/ @P0 BRA 0x7b0 ; /* 0x0000002000000947 */
/* 0x000fea0003800000 */
/*0790*/ STG.E [R4.64+0x4], RZ ; /* 0x000004ff04007986 */
/* 0x0003e8000c101904 */
/*07a0*/ LDG.E R6, [R2.64] ; /* 0x0000000402067981 */
/* 0x000364000c1e1900 */
/*07b0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*07c0*/ IABS R13, R6 ; /* 0x00000006000d7213 */
/* 0x020fe20000000000 */
/*07d0*/ BSSY B0, 0x990 ; /* 0x000001b000007945 */
/* 0x000fe20003800000 */
/*07e0*/ IADD3 R7, R0, 0x2, RZ ; /* 0x0000000200077810 */
/* 0x000fe40007ffe0ff */
/*07f0*/ I2F.RP R10, R13 ; /* 0x0000000d000a7306 */
/* 0x000ea20000209400 */
/*0800*/ ISETP.NE.AND P2, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe40003f45270 */
/*0810*/ IABS R11, R7 ; /* 0x00000007000b7213 */
/* 0x000fc40000000000 */
/*0820*/ ISETP.GE.AND P1, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fc60003f26270 */
/*0830*/ MUFU.RCP R10, R10 ; /* 0x0000000a000a7308 */
/* 0x004ea40000001000 */
/*0840*/ IADD3 R8, R10, 0xffffffe, RZ ; /* 0x0ffffffe0a087810 */
/* 0x004fcc0007ffe0ff */
/*0850*/ F2I.FTZ.U32.TRUNC.NTZ R9, R8 ; /* 0x0000000800097305 */
/* 0x0004e4000021f000 */
/*0860*/ IMAD.MOV.U32 R8, RZ, RZ, RZ ; /* 0x000000ffff087224 */
/* 0x004fe400078e00ff */
/*0870*/ IMAD.MOV R12, RZ, RZ, -R9 ; /* 0x000000ffff0c7224 */
/* 0x008fc800078e0a09 */
/*0880*/ IMAD R15, R12, R13, RZ ; /* 0x0000000d0c0f7224 */
/* 0x000fe200078e02ff */
/*0890*/ IABS R12, R6 ; /* 0x00000006000c7213 */
/* 0x000fc60000000000 */
/*08a0*/ IMAD.HI.U32 R10, R9, R15, R8 ; /* 0x0000000f090a7227 */
/* 0x000fc800078e0008 */
/*08b0*/ IMAD.MOV R9, RZ, RZ, -R12 ; /* 0x000000ffff097224 */
/* 0x000fe400078e0a0c */
/*08c0*/ IMAD.HI.U32 R8, R10, R11, RZ ; /* 0x0000000b0a087227 */
/* 0x000fc800078e00ff */
/*08d0*/ IMAD R8, R8, R9, R11 ; /* 0x0000000908087224 */
/* 0x000fca00078e020b */
/*08e0*/ ISETP.GT.U32.AND P0, PT, R13, R8, PT ; /* 0x000000080d00720c */
/* 0x000fda0003f04070 */
/*08f0*/ @!P0 IADD3 R8, R8, -R13, RZ ; /* 0x8000000d08088210 */
/* 0x000fc80007ffe0ff */
/*0900*/ ISETP.GT.U32.AND P0, PT, R13, R8, PT ; /* 0x000000080d00720c */
/* 0x000fda0003f04070 */
/*0910*/ @!P0 IMAD.IADD R8, R8, 0x1, -R13 ; /* 0x0000000108088824 */
/* 0x000fc800078e0a0d */
/*0920*/ @!P1 IMAD.MOV R8, RZ, RZ, -R8 ; /* 0x000000ffff089224 */
/* 0x000fe200078e0a08 */
/*0930*/ @!P2 LOP3.LUT R8, RZ, R6, RZ, 0x33, !PT ; /* 0x00000006ff08a212 */
/* 0x000fc800078e33ff */
/*0940*/ ISETP.NE.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fda0003f05270 */
/*0950*/ @P0 BRA 0x980 ; /* 0x0000002000000947 */
/* 0x000fea0003800000 */
/*0960*/ STG.E [R4.64+0x8], RZ ; /* 0x000008ff04007986 */
/* 0x0005e8000c101904 */
/*0970*/ LDG.E R6, [R2.64] ; /* 0x0000000402067981 */
/* 0x000564000c1e1900 */
/*0980*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0990*/ IABS R12, R6.reuse ; /* 0x00000006000c7213 */
/* 0x0a0fe40000000000 */
/*09a0*/ IADD3 R7, R0, 0x3, RZ ; /* 0x0000000300077810 */
/* 0x000fe40007ffe0ff */
/*09b0*/ I2F.RP R10, R12 ; /* 0x0000000c000a7306 */
/* 0x000ee20000209400 */
/*09c0*/ IABS R13, R6 ; /* 0x00000006000d7213 */
/* 0x000fe40000000000 */
/*09d0*/ ISETP.GE.AND P2, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fc40003f46270 */
/*09e0*/ IADD3 R0, R0, 0x4, RZ ; /* 0x0000000400007810 */
/* 0x000fe20007ffe0ff */
/*09f0*/ IMAD.MOV R13, RZ, RZ, -R13 ; /* 0x000000ffff0d7224 */
/* 0x000fe400078e0a0d */
/*0a00*/ MUFU.RCP R10, R10 ; /* 0x0000000a000a7308 */
/* 0x008ee40000001000 */
/*0a10*/ IADD3 R8, R10, 0xffffffe, RZ ; /* 0x0ffffffe0a087810 */
/* 0x008fe40007ffe0ff */
/*0a20*/ IABS R10, R7 ; /* 0x00000007000a7213 */
/* 0x000fc80000000000 */
/*0a30*/ F2I.FTZ.U32.TRUNC.NTZ R9, R8 ; /* 0x0000000800097305 */
/* 0x000724000021f000 */
/*0a40*/ IMAD.MOV.U32 R8, RZ, RZ, RZ ; /* 0x000000ffff087224 */
/* 0x008fe400078e00ff */
/*0a50*/ IMAD.MOV R11, RZ, RZ, -R9 ; /* 0x000000ffff0b7224 */
/* 0x010fc800078e0a09 */
/*0a60*/ IMAD R11, R11, R12, RZ ; /* 0x0000000c0b0b7224 */
/* 0x000fc800078e02ff */
/*0a70*/ IMAD.HI.U32 R9, R9, R11, R8 ; /* 0x0000000b09097227 */
/* 0x000fc800078e0008 */
/*0a80*/ IMAD.MOV.U32 R8, RZ, RZ, R13 ; /* 0x000000ffff087224 */
/* 0x000fe400078e000d */
/*0a90*/ IMAD.HI.U32 R9, R9, R10, RZ ; /* 0x0000000a09097227 */
/* 0x000fc800078e00ff */
/*0aa0*/ IMAD R9, R9, R8, R10 ; /* 0x0000000809097224 */
/* 0x000fca00078e020a */
/*0ab0*/ ISETP.GT.U32.AND P0, PT, R12, R9, PT ; /* 0x000000090c00720c */
/* 0x000fda0003f04070 */
/*0ac0*/ @!P0 IMAD.IADD R9, R9, 0x1, -R12 ; /* 0x0000000109098824 */
/* 0x000fe200078e0a0c */
/*0ad0*/ ISETP.NE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fc80003f05270 */
/*0ae0*/ ISETP.GT.U32.AND P1, PT, R12, R9, PT ; /* 0x000000090c00720c */
/* 0x000fda0003f24070 */
/*0af0*/ @!P1 IMAD.IADD R9, R9, 0x1, -R12 ; /* 0x0000000109099824 */
/* 0x000fe200078e0a0c */
/*0b00*/ IADD3 R8, P1, R4, 0x10, RZ ; /* 0x0000001004087810 */
/* 0x000fc60007f3e0ff */
/*0b10*/ @!P2 IMAD.MOV R9, RZ, RZ, -R9 ; /* 0x000000ffff09a224 */
/* 0x000fe200078e0a09 */
/*0b20*/ @!P0 LOP3.LUT R9, RZ, R6, RZ, 0x33, !PT ; /* 0x00000006ff098212 */
/* 0x000fc800078e33ff */
/*0b30*/ ISETP.NE.AND P0, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x000fe20003f05270 */
/*0b40*/ IMAD.X R9, RZ, RZ, R5, P1 ; /* 0x000000ffff097224 */
/* 0x000fd800008e0605 */
/*0b50*/ @!P0 STG.E [R4.64+0xc], RZ ; /* 0x00000cff04008986 */
/* 0x0007e2000c101904 */
/*0b60*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x174], PT ; /* 0x00005d0000007a0c */
/* 0x000fda0003f06270 */
/*0b70*/ @!P0 BRA 0x400 ; /* 0xfffff88000008947 */
/* 0x008fea000383ffff */
/*0b80*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0b90*/ BRA 0xb90; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0ba0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0be0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <time.h>
int generateInitialPrimes(int *intialTempArray, int **PL, int initialPrimesRange);
__global__ void calcPrimes(int *d_IL, int *d_PL, int numOfPrimes, int lenInputList);
#define LEN_IL 1000000
#define LEN_INITIAL_PRIMES 1000
#define THREADS_PER_BLOCK 32
int main() {
int *IL = NULL, *PL = NULL, *tempPL = NULL;
int *d_IL = NULL, *d_PL = NULL;
cudaEvent_t start, stop;
float time;
cudaEventCreate(&start);
cudaEventCreate(&stop);
clock_t t;
//int count = 0;
t = clock();
int numOfInitialPrimes = generateInitialPrimes(tempPL, &PL, LEN_INITIAL_PRIMES);
t = clock() - t;
double time_taken = ((double)t)/CLOCKS_PER_SEC; // in seconds
// Print the initial range of primes calculated in the CPU, which will be passed to the GPU:
printf("\nThe initial primes calculated are:\n");
for(int i=0; i < numOfInitialPrimes; i++) {
printf("%d ", PL[i]);
}
printf("\nNumber of initial primes = %d\n\n", numOfInitialPrimes);
// Space for host copies:
IL = (int*) malloc(LEN_IL * sizeof(int));
//PL = (int*) malloc(LEN_INITIAL_PRIMES * sizeof(int)); // Allocated in the generate function instead
int size_IL = LEN_IL * sizeof(int);
int size_PL = numOfInitialPrimes * sizeof(int);
// Initialize Input list: 0 -> Not prime:
for(int i=0; i<LEN_IL; i++) {
IL[i] = 1;
}
// Space for device copies:
cudaMalloc((void **) &d_IL, size_IL);
cudaMalloc((void **) &d_PL, size_PL);
// Copying the data to the device (GPU):
cudaMemcpy(d_IL, IL, size_IL, cudaMemcpyHostToDevice);
cudaMemcpy(d_PL, PL, size_PL, cudaMemcpyHostToDevice);
// Launching the kernel and measuring the time taken:
cudaEventRecord(start, 0);
calcPrimes<<<(numOfInitialPrimes/THREADS_PER_BLOCK) + 1, THREADS_PER_BLOCK>>> (d_IL, d_PL, numOfInitialPrimes, LEN_IL);
cudaEventRecord(stop, 0);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&time, start, stop);
// Space allocated to store the modified form of input array, with marking for prime and non-prime:
int *result = (int*) malloc(size_IL);
// Copy the result back to the host:
cudaMemcpy(result, d_IL, size_IL, cudaMemcpyDeviceToHost);
// Extract indexes of primes in 'result' to get the actual new prime numbers:
printf("********* New Primes List **********\n");
int *newPrimes = (int*)malloc(LEN_IL / 4 * sizeof(int)); // Arbitrary size; which is '1/4th' of numbers list size
int newPrimesCount = 0;
for(int i=LEN_INITIAL_PRIMES; i<LEN_IL; i++) {
int num = result[i];
if(num == 1) {
newPrimes[newPrimesCount] = num;
newPrimesCount++;
printf("%d ", i);
}
}
printf("\n\nNumber of new primes found = %d\n\n", newPrimesCount);
printf("Time taken to find initial primes on CPU = %f ms\n", time_taken * 1000);
printf("Parallel Job time for current iteration = %f ms\n\n", time);
// Free memory:
cudaFree(d_IL);
cudaFree(d_PL);
free(IL);
free(PL);
free(result);
free(newPrimes);
return 0;
}
// Generate initial prime numbers in the CPU:
// Returns: Number of primes found from 1 to 'LEN_INITIAL_PRIMES'
int generateInitialPrimes(int *intialTempArray, int **PL, int initialPrimesRange) {
int primesCount = 0;
//int intialTempArray[initialPrimesRange];
intialTempArray = (int*) malloc(LEN_INITIAL_PRIMES * sizeof(int));
*PL = (int*) malloc(LEN_INITIAL_PRIMES / 2 * sizeof(int)); // Taking half size of initial (full) primes array
// Initialize array with all 1's:
for(int i=0; i < initialPrimesRange; i++) {
intialTempArray[i] = 1;
}
// Make non-primes as '0':
for(int i=2; i*i <= initialPrimesRange; i++) {
for(int j=2*i; j <= initialPrimesRange; j=j+i) {
intialTempArray[j] = 0;
}
}
// Store the actual primes in a new array which will be copied later to the device (converting 'prime num indexes' to 'prime numbers') :
for(int i=2; i<=initialPrimesRange; i++) {
if(intialTempArray[i] == 1) {
(*PL)[primesCount] = i;
primesCount++;
}
}
free(intialTempArray);
return primesCount;
}
// GPU Kernel (Parallel Processing):
__global__ void calcPrimes(int *d_IL, int *d_PL, int numOfPrimes, int lenInputList) {
int index = threadIdx.x + blockIdx.x * blockDim.x;
if(index < numOfPrimes) {
for(int i = d_PL[numOfPrimes-1]+1; i < lenInputList; i++) {
if(i % d_PL[index] == 0) {
d_IL[i] = 0;
}
}
}
} | .file "tmpxft_0009131a_00000000-6_primes_v1.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z21generateInitialPrimesPiPS_i
.type _Z21generateInitialPrimesPiPS_i, @function
_Z21generateInitialPrimesPiPS_i:
.LFB2058:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $8, %rsp
.cfi_def_cfa_offset 48
movq %rsi, %r12
movl %edx, %ebx
movl $4000, %edi
call malloc@PLT
movq %rax, %rbp
movl $2000, %edi
call malloc@PLT
movq %rax, (%r12)
testl %ebx, %ebx
jle .L13
movq %rbp, %rax
movslq %ebx, %rdx
leaq 0(%rbp,%rdx,4), %rdx
.L5:
movl $1, (%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L5
cmpl $3, %ebx
jle .L6
movl $2, %edx
movl $4, %esi
.L9:
movl %edx, %ecx
cmpl %esi, %ebx
jl .L7
movslq %esi, %rax
.L8:
movl $0, 0(%rbp,%rax,4)
addq %rdx, %rax
cmpl %eax, %ebx
jge .L8
.L7:
leal 1(%rcx), %eax
addl $2, %esi
addq $1, %rdx
imull %eax, %eax
cmpl %ebx, %eax
jle .L9
.L10:
leal 1(%rbx), %edx
movl $2, %eax
movl $0, %r13d
jmp .L12
.L6:
movl $0, %r13d
cmpl $1, %ebx
jle .L4
jmp .L10
.L11:
addq $1, %rax
cmpq %rdx, %rax
je .L4
.L12:
cmpl $1, 0(%rbp,%rax,4)
jne .L11
movslq %r13d, %rsi
movq (%r12), %rcx
movl %eax, (%rcx,%rsi,4)
addl $1, %r13d
jmp .L11
.L13:
movl $0, %r13d
.L4:
movq %rbp, %rdi
call free@PLT
movl %r13d, %eax
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _Z21generateInitialPrimesPiPS_i, .-_Z21generateInitialPrimesPiPS_i
.globl _Z34__device_stub__Z10calcPrimesPiS_iiPiS_ii
.type _Z34__device_stub__Z10calcPrimesPiS_iiPiS_ii, @function
_Z34__device_stub__Z10calcPrimesPiS_iiPiS_ii:
.LFB2083:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L24
.L20:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L25
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L24:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z10calcPrimesPiS_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L20
.L25:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z34__device_stub__Z10calcPrimesPiS_iiPiS_ii, .-_Z34__device_stub__Z10calcPrimesPiS_iiPiS_ii
.globl _Z10calcPrimesPiS_ii
.type _Z10calcPrimesPiS_ii, @function
_Z10calcPrimesPiS_ii:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z34__device_stub__Z10calcPrimesPiS_iiPiS_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z10calcPrimesPiS_ii, .-_Z10calcPrimesPiS_ii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "\nThe initial primes calculated are:\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "%d "
.section .rodata.str1.8
.align 8
.LC3:
.string "\nNumber of initial primes = %d\n\n"
.align 8
.LC4:
.string "********* New Primes List **********\n"
.align 8
.LC5:
.string "\n\nNumber of new primes found = %d\n\n"
.align 8
.LC7:
.string "Time taken to find initial primes on CPU = %f ms\n"
.align 8
.LC8:
.string "Parallel Job time for current iteration = %f ms\n\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $104, %rsp
.cfi_def_cfa_offset 160
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
movq $0, 24(%rsp)
movq $0, 32(%rsp)
movq $0, 40(%rsp)
leaq 48(%rsp), %rdi
call cudaEventCreate@PLT
leaq 56(%rsp), %rdi
call cudaEventCreate@PLT
call clock@PLT
movq %rax, %rbp
leaq 24(%rsp), %rsi
movl $1000, %edx
movl $0, %edi
call _Z21generateInitialPrimesPiPS_i
movl %eax, %ebx
call clock@PLT
subq %rbp, %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
divsd .LC0(%rip), %xmm0
movsd %xmm0, 8(%rsp)
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
testl %ebx, %ebx
jle .L29
movslq %ebx, %r12
salq $2, %r12
movl $0, %ebp
leaq .LC2(%rip), %r13
.L30:
movq 24(%rsp), %rax
movl (%rax,%rbp), %edx
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbp
cmpq %r12, %rbp
jne .L30
.L29:
movl %ebx, %edx
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $4000000, %edi
call malloc@PLT
movq %rax, %r15
leal 0(,%rbx,4), %ebp
leaq 4000000(%rax), %rdx
.L31:
movl $1, (%rax)
addq $4, %rax
cmpq %rax, %rdx
jne .L31
leaq 32(%rsp), %rdi
movl $4000000, %esi
call cudaMalloc@PLT
movslq %ebp, %rbp
leaq 40(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movl $4000000, %edx
movq %r15, %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
movq 24(%rsp), %rax
movq %rax, (%rsp)
movl $1, %ecx
movq %rbp, %rdx
movq %rax, %rsi
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
movl $0, %esi
movq 48(%rsp), %rdi
call cudaEventRecord@PLT
movl $32, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leal 31(%rbx), %eax
testl %ebx, %ebx
cmovns %ebx, %eax
sarl $5, %eax
addl $1, %eax
movl %eax, 64(%rsp)
movl $1, 68(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 76(%rsp), %rdx
movl $1, %ecx
movq 64(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L40
.L32:
movl $0, %esi
movq 56(%rsp), %rdi
call cudaEventRecord@PLT
movq 56(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 76(%rsp), %rdi
movq 56(%rsp), %rdx
movq 48(%rsp), %rsi
call cudaEventElapsedTime@PLT
movl $4000000, %edi
call malloc@PLT
movq %rax, %rbp
movl $2, %ecx
movl $4000000, %edx
movq 32(%rsp), %rsi
movq %rax, %rdi
call cudaMemcpy@PLT
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1000000, %edi
call malloc@PLT
movq %rax, %r13
movl $1000, %ebx
movl $0, %r12d
leaq .LC2(%rip), %r14
jmp .L34
.L40:
movl $1000000, %ecx
movl %ebx, %edx
movq 40(%rsp), %rsi
movq 32(%rsp), %rdi
call _Z34__device_stub__Z10calcPrimesPiS_iiPiS_ii
jmp .L32
.L33:
addq $1, %rbx
cmpq $1000000, %rbx
je .L41
.L34:
cmpl $1, 0(%rbp,%rbx,4)
jne .L33
movslq %r12d, %rax
movl $1, 0(%r13,%rax,4)
addl $1, %r12d
movl %ebx, %edx
movq %r14, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L33
.L41:
movl %r12d, %edx
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movsd 8(%rsp), %xmm0
mulsd .LC6(%rip), %xmm0
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
pxor %xmm0, %xmm0
cvtss2sd 76(%rsp), %xmm0
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq %r15, %rdi
call free@PLT
movq (%rsp), %rdi
call free@PLT
movq %rbp, %rdi
call free@PLT
movq %r13, %rdi
call free@PLT
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L42
movl $0, %eax
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L42:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC9:
.string "_Z10calcPrimesPiS_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _Z10calcPrimesPiS_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long 0
.long 1093567616
.align 8
.LC6:
.long 0
.long 1083129856
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <time.h>
int generateInitialPrimes(int *intialTempArray, int **PL, int initialPrimesRange);
__global__ void calcPrimes(int *d_IL, int *d_PL, int numOfPrimes, int lenInputList);
#define LEN_IL 1000000
#define LEN_INITIAL_PRIMES 1000
#define THREADS_PER_BLOCK 32
int main() {
int *IL = NULL, *PL = NULL, *tempPL = NULL;
int *d_IL = NULL, *d_PL = NULL;
cudaEvent_t start, stop;
float time;
cudaEventCreate(&start);
cudaEventCreate(&stop);
clock_t t;
//int count = 0;
t = clock();
int numOfInitialPrimes = generateInitialPrimes(tempPL, &PL, LEN_INITIAL_PRIMES);
t = clock() - t;
double time_taken = ((double)t)/CLOCKS_PER_SEC; // in seconds
// Print the initial range of primes calculated in the CPU, which will be passed to the GPU:
printf("\nThe initial primes calculated are:\n");
for(int i=0; i < numOfInitialPrimes; i++) {
printf("%d ", PL[i]);
}
printf("\nNumber of initial primes = %d\n\n", numOfInitialPrimes);
// Space for host copies:
IL = (int*) malloc(LEN_IL * sizeof(int));
//PL = (int*) malloc(LEN_INITIAL_PRIMES * sizeof(int)); // Allocated in the generate function instead
int size_IL = LEN_IL * sizeof(int);
int size_PL = numOfInitialPrimes * sizeof(int);
// Initialize Input list: 0 -> Not prime:
for(int i=0; i<LEN_IL; i++) {
IL[i] = 1;
}
// Space for device copies:
cudaMalloc((void **) &d_IL, size_IL);
cudaMalloc((void **) &d_PL, size_PL);
// Copying the data to the device (GPU):
cudaMemcpy(d_IL, IL, size_IL, cudaMemcpyHostToDevice);
cudaMemcpy(d_PL, PL, size_PL, cudaMemcpyHostToDevice);
// Launching the kernel and measuring the time taken:
cudaEventRecord(start, 0);
calcPrimes<<<(numOfInitialPrimes/THREADS_PER_BLOCK) + 1, THREADS_PER_BLOCK>>> (d_IL, d_PL, numOfInitialPrimes, LEN_IL);
cudaEventRecord(stop, 0);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&time, start, stop);
// Space allocated to store the modified form of input array, with marking for prime and non-prime:
int *result = (int*) malloc(size_IL);
// Copy the result back to the host:
cudaMemcpy(result, d_IL, size_IL, cudaMemcpyDeviceToHost);
// Extract indexes of primes in 'result' to get the actual new prime numbers:
printf("********* New Primes List **********\n");
int *newPrimes = (int*)malloc(LEN_IL / 4 * sizeof(int)); // Arbitrary size; which is '1/4th' of numbers list size
int newPrimesCount = 0;
for(int i=LEN_INITIAL_PRIMES; i<LEN_IL; i++) {
int num = result[i];
if(num == 1) {
newPrimes[newPrimesCount] = num;
newPrimesCount++;
printf("%d ", i);
}
}
printf("\n\nNumber of new primes found = %d\n\n", newPrimesCount);
printf("Time taken to find initial primes on CPU = %f ms\n", time_taken * 1000);
printf("Parallel Job time for current iteration = %f ms\n\n", time);
// Free memory:
cudaFree(d_IL);
cudaFree(d_PL);
free(IL);
free(PL);
free(result);
free(newPrimes);
return 0;
}
// Generate initial prime numbers in the CPU:
// Returns: Number of primes found from 1 to 'LEN_INITIAL_PRIMES'
int generateInitialPrimes(int *intialTempArray, int **PL, int initialPrimesRange) {
int primesCount = 0;
//int intialTempArray[initialPrimesRange];
intialTempArray = (int*) malloc(LEN_INITIAL_PRIMES * sizeof(int));
*PL = (int*) malloc(LEN_INITIAL_PRIMES / 2 * sizeof(int)); // Taking half size of initial (full) primes array
// Initialize array with all 1's:
for(int i=0; i < initialPrimesRange; i++) {
intialTempArray[i] = 1;
}
// Make non-primes as '0':
for(int i=2; i*i <= initialPrimesRange; i++) {
for(int j=2*i; j <= initialPrimesRange; j=j+i) {
intialTempArray[j] = 0;
}
}
// Store the actual primes in a new array which will be copied later to the device (converting 'prime num indexes' to 'prime numbers') :
for(int i=2; i<=initialPrimesRange; i++) {
if(intialTempArray[i] == 1) {
(*PL)[primesCount] = i;
primesCount++;
}
}
free(intialTempArray);
return primesCount;
}
// GPU Kernel (Parallel Processing):
__global__ void calcPrimes(int *d_IL, int *d_PL, int numOfPrimes, int lenInputList) {
int index = threadIdx.x + blockIdx.x * blockDim.x;
if(index < numOfPrimes) {
for(int i = d_PL[numOfPrimes-1]+1; i < lenInputList; i++) {
if(i % d_PL[index] == 0) {
d_IL[i] = 0;
}
}
}
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <time.h>
int generateInitialPrimes(int *intialTempArray, int **PL, int initialPrimesRange);
__global__ void calcPrimes(int *d_IL, int *d_PL, int numOfPrimes, int lenInputList);
#define LEN_IL 1000000
#define LEN_INITIAL_PRIMES 1000
#define THREADS_PER_BLOCK 32
int main() {
int *IL = NULL, *PL = NULL, *tempPL = NULL;
int *d_IL = NULL, *d_PL = NULL;
hipEvent_t start, stop;
float time;
hipEventCreate(&start);
hipEventCreate(&stop);
clock_t t;
//int count = 0;
t = clock();
int numOfInitialPrimes = generateInitialPrimes(tempPL, &PL, LEN_INITIAL_PRIMES);
t = clock() - t;
double time_taken = ((double)t)/CLOCKS_PER_SEC; // in seconds
// Print the initial range of primes calculated in the CPU, which will be passed to the GPU:
printf("\nThe initial primes calculated are:\n");
for(int i=0; i < numOfInitialPrimes; i++) {
printf("%d ", PL[i]);
}
printf("\nNumber of initial primes = %d\n\n", numOfInitialPrimes);
// Space for host copies:
IL = (int*) malloc(LEN_IL * sizeof(int));
//PL = (int*) malloc(LEN_INITIAL_PRIMES * sizeof(int)); // Allocated in the generate function instead
int size_IL = LEN_IL * sizeof(int);
int size_PL = numOfInitialPrimes * sizeof(int);
// Initialize Input list: 0 -> Not prime:
for(int i=0; i<LEN_IL; i++) {
IL[i] = 1;
}
// Space for device copies:
hipMalloc((void **) &d_IL, size_IL);
hipMalloc((void **) &d_PL, size_PL);
// Copying the data to the device (GPU):
hipMemcpy(d_IL, IL, size_IL, hipMemcpyHostToDevice);
hipMemcpy(d_PL, PL, size_PL, hipMemcpyHostToDevice);
// Launching the kernel and measuring the time taken:
hipEventRecord(start, 0);
calcPrimes<<<(numOfInitialPrimes/THREADS_PER_BLOCK) + 1, THREADS_PER_BLOCK>>> (d_IL, d_PL, numOfInitialPrimes, LEN_IL);
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
hipEventElapsedTime(&time, start, stop);
// Space allocated to store the modified form of input array, with marking for prime and non-prime:
int *result = (int*) malloc(size_IL);
// Copy the result back to the host:
hipMemcpy(result, d_IL, size_IL, hipMemcpyDeviceToHost);
// Extract indexes of primes in 'result' to get the actual new prime numbers:
printf("********* New Primes List **********\n");
int *newPrimes = (int*)malloc(LEN_IL / 4 * sizeof(int)); // Arbitrary size; which is '1/4th' of numbers list size
int newPrimesCount = 0;
for(int i=LEN_INITIAL_PRIMES; i<LEN_IL; i++) {
int num = result[i];
if(num == 1) {
newPrimes[newPrimesCount] = num;
newPrimesCount++;
printf("%d ", i);
}
}
printf("\n\nNumber of new primes found = %d\n\n", newPrimesCount);
printf("Time taken to find initial primes on CPU = %f ms\n", time_taken * 1000);
printf("Parallel Job time for current iteration = %f ms\n\n", time);
// Free memory:
hipFree(d_IL);
hipFree(d_PL);
free(IL);
free(PL);
free(result);
free(newPrimes);
return 0;
}
// Generate initial prime numbers in the CPU:
// Returns: Number of primes found from 1 to 'LEN_INITIAL_PRIMES'
int generateInitialPrimes(int *intialTempArray, int **PL, int initialPrimesRange) {
int primesCount = 0;
//int intialTempArray[initialPrimesRange];
intialTempArray = (int*) malloc(LEN_INITIAL_PRIMES * sizeof(int));
*PL = (int*) malloc(LEN_INITIAL_PRIMES / 2 * sizeof(int)); // Taking half size of initial (full) primes array
// Initialize array with all 1's:
for(int i=0; i < initialPrimesRange; i++) {
intialTempArray[i] = 1;
}
// Make non-primes as '0':
for(int i=2; i*i <= initialPrimesRange; i++) {
for(int j=2*i; j <= initialPrimesRange; j=j+i) {
intialTempArray[j] = 0;
}
}
// Store the actual primes in a new array which will be copied later to the device (converting 'prime num indexes' to 'prime numbers') :
for(int i=2; i<=initialPrimesRange; i++) {
if(intialTempArray[i] == 1) {
(*PL)[primesCount] = i;
primesCount++;
}
}
free(intialTempArray);
return primesCount;
}
// GPU Kernel (Parallel Processing):
__global__ void calcPrimes(int *d_IL, int *d_PL, int numOfPrimes, int lenInputList) {
int index = threadIdx.x + blockIdx.x * blockDim.x;
if(index < numOfPrimes) {
for(int i = d_PL[numOfPrimes-1]+1; i < lenInputList; i++) {
if(i % d_PL[index] == 0) {
d_IL[i] = 0;
}
}
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <time.h>
int generateInitialPrimes(int *intialTempArray, int **PL, int initialPrimesRange);
__global__ void calcPrimes(int *d_IL, int *d_PL, int numOfPrimes, int lenInputList);
#define LEN_IL 1000000
#define LEN_INITIAL_PRIMES 1000
#define THREADS_PER_BLOCK 32
int main() {
int *IL = NULL, *PL = NULL, *tempPL = NULL;
int *d_IL = NULL, *d_PL = NULL;
hipEvent_t start, stop;
float time;
hipEventCreate(&start);
hipEventCreate(&stop);
clock_t t;
//int count = 0;
t = clock();
int numOfInitialPrimes = generateInitialPrimes(tempPL, &PL, LEN_INITIAL_PRIMES);
t = clock() - t;
double time_taken = ((double)t)/CLOCKS_PER_SEC; // in seconds
// Print the initial range of primes calculated in the CPU, which will be passed to the GPU:
printf("\nThe initial primes calculated are:\n");
for(int i=0; i < numOfInitialPrimes; i++) {
printf("%d ", PL[i]);
}
printf("\nNumber of initial primes = %d\n\n", numOfInitialPrimes);
// Space for host copies:
IL = (int*) malloc(LEN_IL * sizeof(int));
//PL = (int*) malloc(LEN_INITIAL_PRIMES * sizeof(int)); // Allocated in the generate function instead
int size_IL = LEN_IL * sizeof(int);
int size_PL = numOfInitialPrimes * sizeof(int);
// Initialize Input list: 0 -> Not prime:
for(int i=0; i<LEN_IL; i++) {
IL[i] = 1;
}
// Space for device copies:
hipMalloc((void **) &d_IL, size_IL);
hipMalloc((void **) &d_PL, size_PL);
// Copying the data to the device (GPU):
hipMemcpy(d_IL, IL, size_IL, hipMemcpyHostToDevice);
hipMemcpy(d_PL, PL, size_PL, hipMemcpyHostToDevice);
// Launching the kernel and measuring the time taken:
hipEventRecord(start, 0);
calcPrimes<<<(numOfInitialPrimes/THREADS_PER_BLOCK) + 1, THREADS_PER_BLOCK>>> (d_IL, d_PL, numOfInitialPrimes, LEN_IL);
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
hipEventElapsedTime(&time, start, stop);
// Space allocated to store the modified form of input array, with marking for prime and non-prime:
int *result = (int*) malloc(size_IL);
// Copy the result back to the host:
hipMemcpy(result, d_IL, size_IL, hipMemcpyDeviceToHost);
// Extract indexes of primes in 'result' to get the actual new prime numbers:
printf("********* New Primes List **********\n");
int *newPrimes = (int*)malloc(LEN_IL / 4 * sizeof(int)); // Arbitrary size; which is '1/4th' of numbers list size
int newPrimesCount = 0;
for(int i=LEN_INITIAL_PRIMES; i<LEN_IL; i++) {
int num = result[i];
if(num == 1) {
newPrimes[newPrimesCount] = num;
newPrimesCount++;
printf("%d ", i);
}
}
printf("\n\nNumber of new primes found = %d\n\n", newPrimesCount);
printf("Time taken to find initial primes on CPU = %f ms\n", time_taken * 1000);
printf("Parallel Job time for current iteration = %f ms\n\n", time);
// Free memory:
hipFree(d_IL);
hipFree(d_PL);
free(IL);
free(PL);
free(result);
free(newPrimes);
return 0;
}
// Generate initial prime numbers in the CPU:
// Returns: Number of primes found from 1 to 'LEN_INITIAL_PRIMES'
int generateInitialPrimes(int *intialTempArray, int **PL, int initialPrimesRange) {
int primesCount = 0;
//int intialTempArray[initialPrimesRange];
intialTempArray = (int*) malloc(LEN_INITIAL_PRIMES * sizeof(int));
*PL = (int*) malloc(LEN_INITIAL_PRIMES / 2 * sizeof(int)); // Taking half size of initial (full) primes array
// Initialize array with all 1's:
for(int i=0; i < initialPrimesRange; i++) {
intialTempArray[i] = 1;
}
// Make non-primes as '0':
for(int i=2; i*i <= initialPrimesRange; i++) {
for(int j=2*i; j <= initialPrimesRange; j=j+i) {
intialTempArray[j] = 0;
}
}
// Store the actual primes in a new array which will be copied later to the device (converting 'prime num indexes' to 'prime numbers') :
for(int i=2; i<=initialPrimesRange; i++) {
if(intialTempArray[i] == 1) {
(*PL)[primesCount] = i;
primesCount++;
}
}
free(intialTempArray);
return primesCount;
}
// GPU Kernel (Parallel Processing):
__global__ void calcPrimes(int *d_IL, int *d_PL, int numOfPrimes, int lenInputList) {
int index = threadIdx.x + blockIdx.x * blockDim.x;
if(index < numOfPrimes) {
for(int i = d_PL[numOfPrimes-1]+1; i < lenInputList; i++) {
if(i % d_PL[index] == 0) {
d_IL[i] = 0;
}
}
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10calcPrimesPiS_ii
.globl _Z10calcPrimesPiS_ii
.p2align 8
.type _Z10calcPrimesPiS_ii,@function
_Z10calcPrimesPiS_ii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s4, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s4, v1
s_cbranch_execz .LBB0_6
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x8
s_load_b32 s6, s[0:1], 0x14
s_ashr_i32 s5, s4, 31
s_delay_alu instid0(SALU_CYCLE_1)
s_lshl_b64 s[4:5], s[4:5], 2
s_waitcnt lgkmcnt(0)
s_add_u32 s4, s2, s4
s_addc_u32 s5, s3, s5
s_add_u32 s4, s4, -4
s_addc_u32 s5, s5, -1
s_load_b32 s4, s[4:5], 0x0
s_waitcnt lgkmcnt(0)
s_add_i32 s7, s4, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_ge_i32 s7, s6
s_cbranch_scc1 .LBB0_6
s_load_b64 s[0:1], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_ashr_i32 s5, s4, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_lshl_b64 s[4:5], s[4:5], 2
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_mov_b32_e32 v2, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s4, s0
s_addc_u32 s1, s5, s1
s_add_u32 s0, s0, 4
s_addc_u32 s1, s1, 0
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_4
.p2align 6
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s2
s_add_i32 s7, s7, 1
s_add_u32 s0, s0, 4
s_addc_u32 s1, s1, 0
s_cmp_lt_i32 s7, s6
s_cbranch_scc0 .LBB0_6
.LBB0_4:
global_load_b32 v3, v[0:1], off
s_ashr_i32 s2, s7, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s3, s7, s2
s_xor_b32 s3, s3, s2
s_waitcnt vmcnt(0)
v_ashrrev_i32_e32 v4, 31, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v3, v3, v4
v_xor_b32_e32 v3, v3, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cvt_f32_u32_e32 v4, v3
v_sub_nc_u32_e32 v5, 0, v3
v_rcp_iflag_f32_e32 v4, v4
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v4, 0x4f7ffffe, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_u32_f32_e32 v4, v4
v_mul_lo_u32 v5, v5, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v5, v4, v5
v_add_nc_u32_e32 v4, v4, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v4, s3, v4
v_mul_lo_u32 v4, v4, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v4, s3, v4
v_sub_nc_u32_e32 v5, v4, v3
v_cmp_ge_u32_e32 vcc_lo, v4, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v4, v4, v5, vcc_lo
v_sub_nc_u32_e32 v5, v4, v3
v_cmp_ge_u32_e32 vcc_lo, v4, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v3, v4, v5, vcc_lo
v_xor_b32_e32 v3, s2, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_subrev_nc_u32_e32 v3, s2, v3
s_mov_b32 s2, exec_lo
v_cmpx_eq_u32_e32 0, v3
s_cbranch_execz .LBB0_3
global_store_b32 v2, v2, s[0:1]
s_branch .LBB0_3
.LBB0_6:
s_set_inst_prefetch_distance 0x2
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10calcPrimesPiS_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10calcPrimesPiS_ii, .Lfunc_end0-_Z10calcPrimesPiS_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10calcPrimesPiS_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z10calcPrimesPiS_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <time.h>
int generateInitialPrimes(int *intialTempArray, int **PL, int initialPrimesRange);
__global__ void calcPrimes(int *d_IL, int *d_PL, int numOfPrimes, int lenInputList);
#define LEN_IL 1000000
#define LEN_INITIAL_PRIMES 1000
#define THREADS_PER_BLOCK 32
int main() {
int *IL = NULL, *PL = NULL, *tempPL = NULL;
int *d_IL = NULL, *d_PL = NULL;
hipEvent_t start, stop;
float time;
hipEventCreate(&start);
hipEventCreate(&stop);
clock_t t;
//int count = 0;
t = clock();
int numOfInitialPrimes = generateInitialPrimes(tempPL, &PL, LEN_INITIAL_PRIMES);
t = clock() - t;
double time_taken = ((double)t)/CLOCKS_PER_SEC; // in seconds
// Print the initial range of primes calculated in the CPU, which will be passed to the GPU:
printf("\nThe initial primes calculated are:\n");
for(int i=0; i < numOfInitialPrimes; i++) {
printf("%d ", PL[i]);
}
printf("\nNumber of initial primes = %d\n\n", numOfInitialPrimes);
// Space for host copies:
IL = (int*) malloc(LEN_IL * sizeof(int));
//PL = (int*) malloc(LEN_INITIAL_PRIMES * sizeof(int)); // Allocated in the generate function instead
int size_IL = LEN_IL * sizeof(int);
int size_PL = numOfInitialPrimes * sizeof(int);
// Initialize Input list: 0 -> Not prime:
for(int i=0; i<LEN_IL; i++) {
IL[i] = 1;
}
// Space for device copies:
hipMalloc((void **) &d_IL, size_IL);
hipMalloc((void **) &d_PL, size_PL);
// Copying the data to the device (GPU):
hipMemcpy(d_IL, IL, size_IL, hipMemcpyHostToDevice);
hipMemcpy(d_PL, PL, size_PL, hipMemcpyHostToDevice);
// Launching the kernel and measuring the time taken:
hipEventRecord(start, 0);
calcPrimes<<<(numOfInitialPrimes/THREADS_PER_BLOCK) + 1, THREADS_PER_BLOCK>>> (d_IL, d_PL, numOfInitialPrimes, LEN_IL);
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
hipEventElapsedTime(&time, start, stop);
// Space allocated to store the modified form of input array, with marking for prime and non-prime:
int *result = (int*) malloc(size_IL);
// Copy the result back to the host:
hipMemcpy(result, d_IL, size_IL, hipMemcpyDeviceToHost);
// Extract indexes of primes in 'result' to get the actual new prime numbers:
printf("********* New Primes List **********\n");
int *newPrimes = (int*)malloc(LEN_IL / 4 * sizeof(int)); // Arbitrary size; which is '1/4th' of numbers list size
int newPrimesCount = 0;
for(int i=LEN_INITIAL_PRIMES; i<LEN_IL; i++) {
int num = result[i];
if(num == 1) {
newPrimes[newPrimesCount] = num;
newPrimesCount++;
printf("%d ", i);
}
}
printf("\n\nNumber of new primes found = %d\n\n", newPrimesCount);
printf("Time taken to find initial primes on CPU = %f ms\n", time_taken * 1000);
printf("Parallel Job time for current iteration = %f ms\n\n", time);
// Free memory:
hipFree(d_IL);
hipFree(d_PL);
free(IL);
free(PL);
free(result);
free(newPrimes);
return 0;
}
// Generate initial prime numbers in the CPU:
// Returns: Number of primes found from 1 to 'LEN_INITIAL_PRIMES'
int generateInitialPrimes(int *intialTempArray, int **PL, int initialPrimesRange) {
int primesCount = 0;
//int intialTempArray[initialPrimesRange];
intialTempArray = (int*) malloc(LEN_INITIAL_PRIMES * sizeof(int));
*PL = (int*) malloc(LEN_INITIAL_PRIMES / 2 * sizeof(int)); // Taking half size of initial (full) primes array
// Initialize array with all 1's:
for(int i=0; i < initialPrimesRange; i++) {
intialTempArray[i] = 1;
}
// Make non-primes as '0':
for(int i=2; i*i <= initialPrimesRange; i++) {
for(int j=2*i; j <= initialPrimesRange; j=j+i) {
intialTempArray[j] = 0;
}
}
// Store the actual primes in a new array which will be copied later to the device (converting 'prime num indexes' to 'prime numbers') :
for(int i=2; i<=initialPrimesRange; i++) {
if(intialTempArray[i] == 1) {
(*PL)[primesCount] = i;
primesCount++;
}
}
free(intialTempArray);
return primesCount;
}
// GPU Kernel (Parallel Processing):
__global__ void calcPrimes(int *d_IL, int *d_PL, int numOfPrimes, int lenInputList) {
int index = threadIdx.x + blockIdx.x * blockDim.x;
if(index < numOfPrimes) {
for(int i = d_PL[numOfPrimes-1]+1; i < lenInputList; i++) {
if(i % d_PL[index] == 0) {
d_IL[i] = 0;
}
}
}
} | .text
.file "primes_v1.hip"
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI0_0:
.quad 0x412e848000000000 # double 1.0E+6
.LCPI0_1:
.quad 0x408f400000000000 # double 1000
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $152, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq $0, (%rsp)
movq $0, 8(%rsp)
leaq 40(%rsp), %rdi
callq hipEventCreate
leaq 24(%rsp), %rdi
callq hipEventCreate
callq clock
movq %rax, 16(%rsp) # 8-byte Spill
movl $4000, %edi # imm = 0xFA0
callq malloc
movq %rax, %r15
movl $2000, %edi # imm = 0x7D0
callq malloc
movq %rax, %rbx
xorl %eax, %eax
.p2align 4, 0x90
.LBB0_1: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
movl $1, (%r15,%rax,4)
incq %rax
cmpq $1000, %rax # imm = 0x3E8
jne .LBB0_1
# %bb.2: # %.lr.ph41.i.preheader
movq %r15, %rax
addq $16, %rax
movl $4, %ecx
movl $2, %edx
movl $8, %esi
.p2align 4, 0x90
.LBB0_3: # %.lr.ph41.i
# =>This Loop Header: Depth=1
# Child Loop BB0_4 Depth 2
movq %rax, %rdi
movq %rcx, %r8
.p2align 4, 0x90
.LBB0_4: # %.lr.ph38.i
# Parent Loop BB0_3 Depth=1
# => This Inner Loop Header: Depth=2
movl $0, (%rdi)
addq %rdx, %r8
addq %rsi, %rdi
cmpq $1000, %r8 # imm = 0x3E8
jbe .LBB0_4
# %bb.5: # %._crit_edge.i
# in Loop: Header=BB0_3 Depth=1
incq %rdx
addq $2, %rcx
addq $8, %rax
addq $4, %rsi
cmpq $32, %rdx
jne .LBB0_3
# %bb.6: # %.lr.ph45.i.preheader
xorl %r13d, %r13d
movl $2, %eax
jmp .LBB0_7
.p2align 4, 0x90
.LBB0_9: # in Loop: Header=BB0_7 Depth=1
incq %rax
cmpq $1001, %rax # imm = 0x3E9
je .LBB0_10
.LBB0_7: # %.lr.ph45.i
# =>This Inner Loop Header: Depth=1
cmpl $1, (%r15,%rax,4)
jne .LBB0_9
# %bb.8: # in Loop: Header=BB0_7 Depth=1
movslq %r13d, %r13
movl %eax, (%rbx,%r13,4)
incl %r13d
jmp .LBB0_9
.LBB0_10: # %_Z21generateInitialPrimesPiPS_i.exit
movq %r15, %rdi
callq free
callq clock
movq %rax, %r15
movl $.Lstr, %edi
callq puts@PLT
testl %r13d, %r13d
jle .LBB0_13
# %bb.11: # %.lr.ph.preheader
movl %r13d, %r14d
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB0_12: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl (%rbx,%r12,4), %esi
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
incq %r12
cmpq %r12, %r14
jne .LBB0_12
.LBB0_13: # %._crit_edge
xorl %r14d, %r14d
movl $.L.str.2, %edi
movl %r13d, %esi
xorl %eax, %eax
callq printf
movl $4000000, %edi # imm = 0x3D0900
callq malloc
movq %rax, %r12
.p2align 4, 0x90
.LBB0_14: # =>This Inner Loop Header: Depth=1
movl $1, (%r12,%r14,4)
incq %r14
cmpq $1000000, %r14 # imm = 0xF4240
jne .LBB0_14
# %bb.15:
leal (,%r13,4), %ebp
movq %rsp, %rdi
movl $4000000, %esi # imm = 0x3D0900
callq hipMalloc
movslq %ebp, %r14
leaq 8(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
movq (%rsp), %rdi
movl $4000000, %edx # imm = 0x3D0900
movq %r12, %rsi
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
movq %rbx, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
movq 40(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
leal 31(%r13), %edi
testl %r13d, %r13d
cmovnsl %r13d, %edi
sarl $5, %edi
incl %edi
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %rdi
orq $32, %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB0_17
# %bb.16:
movq (%rsp), %rax
movq 8(%rsp), %rcx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movl %r13d, 36(%rsp)
movl $1000000, 32(%rsp) # imm = 0xF4240
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 36(%rsp), %rax
movq %rax, 128(%rsp)
leaq 32(%rsp), %rax
movq %rax, 136(%rsp)
leaq 80(%rsp), %rdi
leaq 64(%rsp), %rsi
leaq 56(%rsp), %rdx
leaq 48(%rsp), %rcx
callq __hipPopCallConfiguration
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
movq 64(%rsp), %rcx
movl 72(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z10calcPrimesPiS_ii, %edi
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB0_17:
movq 24(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 24(%rsp), %rdi
callq hipEventSynchronize
movq 40(%rsp), %rsi
movq 24(%rsp), %rdx
leaq 112(%rsp), %rdi
callq hipEventElapsedTime
movl $4000000, %edi # imm = 0x3D0900
callq malloc
movq %rax, %r13
movq (%rsp), %rsi
movl $4000000, %edx # imm = 0x3D0900
movq %rax, %rdi
movl $2, %ecx
callq hipMemcpy
movl $.Lstr.1, %edi
callq puts@PLT
movl $1000, %r14d # imm = 0x3E8
xorl %ebp, %ebp
jmp .LBB0_18
.p2align 4, 0x90
.LBB0_20: # in Loop: Header=BB0_18 Depth=1
incq %r14
cmpq $1000000, %r14 # imm = 0xF4240
je .LBB0_21
.LBB0_18: # =>This Inner Loop Header: Depth=1
cmpl $1, (%r13,%r14,4)
jne .LBB0_20
# %bb.19: # in Loop: Header=BB0_18 Depth=1
incl %ebp
movl $.L.str.1, %edi
movl %r14d, %esi
xorl %eax, %eax
callq printf
jmp .LBB0_20
.LBB0_21:
subq 16(%rsp), %r15 # 8-byte Folded Reload
cvtsi2sd %r15, %xmm0
divsd .LCPI0_0(%rip), %xmm0
movsd %xmm0, 16(%rsp) # 8-byte Spill
movl $.L.str.4, %edi
movl %ebp, %esi
xorl %eax, %eax
callq printf
movsd 16(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
mulsd .LCPI0_1(%rip), %xmm0
movl $.L.str.5, %edi
movb $1, %al
callq printf
movss 112(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.6, %edi
movb $1, %al
callq printf
movq (%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq %r12, %rdi
callq free
movq %rbx, %rdi
callq free
movq %r13, %rdi
callq free
xorl %eax, %eax
addq $152, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.globl _Z21generateInitialPrimesPiPS_i # -- Begin function _Z21generateInitialPrimesPiPS_i
.p2align 4, 0x90
.type _Z21generateInitialPrimesPiPS_i,@function
_Z21generateInitialPrimesPiPS_i: # @_Z21generateInitialPrimesPiPS_i
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl %edx, %ebx
movq %rsi, %r15
movl $4000, %edi # imm = 0xFA0
callq malloc
movq %rax, %r14
movl $2000, %edi # imm = 0x7D0
callq malloc
movq %rax, (%r15)
testl %ebx, %ebx
jle .LBB1_3
# %bb.1: # %.lr.ph.preheader
movl %ebx, %ecx
xorl %edx, %edx
.p2align 4, 0x90
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl $1, (%r14,%rdx,4)
incq %rdx
cmpq %rdx, %rcx
jne .LBB1_2
.LBB1_3: # %.preheader34
cmpl $4, %ebx
jge .LBB1_4
.LBB1_7: # %.preheader
xorl %r15d, %r15d
cmpl $2, %ebx
jge .LBB1_8
.LBB1_12: # %._crit_edge46
movq %r14, %rdi
callq free
movl %r15d, %eax
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB1_4: # %.lr.ph41.preheader
.cfi_def_cfa_offset 32
movq %r14, %rcx
addq $16, %rcx
movl $2, %edx
movl $8, %esi
movl $4, %edi
jmp .LBB1_5
.p2align 4, 0x90
.LBB1_6: # %._crit_edge
# in Loop: Header=BB1_5 Depth=1
incq %rdx
movl %edx, %r8d
imull %edx, %r8d
addq $8, %rcx
addq $4, %rsi
addl $2, %edi
cmpl %ebx, %r8d
jg .LBB1_7
.LBB1_5: # %.lr.ph41
# =>This Loop Header: Depth=1
# Child Loop BB1_13 Depth 2
leal (%rdx,%rdx), %r10d
movl %edi, %r8d
movq %rcx, %r9
cmpl %ebx, %r10d
jg .LBB1_6
.p2align 4, 0x90
.LBB1_13: # %.lr.ph38
# Parent Loop BB1_5 Depth=1
# => This Inner Loop Header: Depth=2
movl $0, (%r9)
addq %rsi, %r9
addl %edx, %r8d
cmpl %ebx, %r8d
jle .LBB1_13
jmp .LBB1_6
.LBB1_8: # %.lr.ph45.preheader
incl %ebx
xorl %r15d, %r15d
movl $2, %ecx
jmp .LBB1_9
.p2align 4, 0x90
.LBB1_11: # in Loop: Header=BB1_9 Depth=1
incq %rcx
cmpq %rcx, %rbx
je .LBB1_12
.LBB1_9: # %.lr.ph45
# =>This Inner Loop Header: Depth=1
cmpl $1, (%r14,%rcx,4)
jne .LBB1_11
# %bb.10: # in Loop: Header=BB1_9 Depth=1
movslq %r15d, %r15
movl %ecx, (%rax,%r15,4)
incl %r15d
jmp .LBB1_11
.Lfunc_end1:
.size _Z21generateInitialPrimesPiPS_i, .Lfunc_end1-_Z21generateInitialPrimesPiPS_i
.cfi_endproc
# -- End function
.globl _Z25__device_stub__calcPrimesPiS_ii # -- Begin function _Z25__device_stub__calcPrimesPiS_ii
.p2align 4, 0x90
.type _Z25__device_stub__calcPrimesPiS_ii,@function
_Z25__device_stub__calcPrimesPiS_ii: # @_Z25__device_stub__calcPrimesPiS_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10calcPrimesPiS_ii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end2:
.size _Z25__device_stub__calcPrimesPiS_ii, .Lfunc_end2-_Z25__device_stub__calcPrimesPiS_ii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10calcPrimesPiS_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "%d "
.size .L.str.1, 5
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "\nNumber of initial primes = %d\n\n"
.size .L.str.2, 33
.type _Z10calcPrimesPiS_ii,@object # @_Z10calcPrimesPiS_ii
.section .rodata,"a",@progbits
.globl _Z10calcPrimesPiS_ii
.p2align 3, 0x0
_Z10calcPrimesPiS_ii:
.quad _Z25__device_stub__calcPrimesPiS_ii
.size _Z10calcPrimesPiS_ii, 8
.type .L.str.4,@object # @.str.4
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.4:
.asciz "\n\nNumber of new primes found = %d\n\n"
.size .L.str.4, 36
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Time taken to find initial primes on CPU = %f ms\n"
.size .L.str.5, 50
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "Parallel Job time for current iteration = %f ms\n\n"
.size .L.str.6, 50
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z10calcPrimesPiS_ii"
.size .L__unnamed_1, 21
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "\nThe initial primes calculated are:"
.size .Lstr, 36
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "********* New Primes List **********"
.size .Lstr.1, 37
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__calcPrimesPiS_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10calcPrimesPiS_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z10calcPrimesPiS_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R4, R4, c[0x0][0x0], R3 ; /* 0x0000000004047a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R4, c[0x0][0x170], PT ; /* 0x00005c0004007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff027624 */
/* 0x000fe200078e00ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0080*/ IMAD.MOV.U32 R7, RZ, RZ, 0x4 ; /* 0x00000004ff077424 */
/* 0x000fc600078e00ff */
/*0090*/ IADD3 R2, R2, -0x1, RZ ; /* 0xffffffff02027810 */
/* 0x000fca0007ffe0ff */
/*00a0*/ IMAD.WIDE R2, R2, R7, c[0x0][0x168] ; /* 0x00005a0002027625 */
/* 0x000fcc00078e0207 */
/*00b0*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea4000c1e1900 */
/*00c0*/ IADD3 R0, R2, 0x1, RZ ; /* 0x0000000102007810 */
/* 0x004fc80007ffe0ff */
/*00d0*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x174], PT ; /* 0x00005d0000007a0c */
/* 0x000fda0003f06270 */
/*00e0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00f0*/ LOP3.LUT R3, RZ, R2, RZ, 0x33, !PT ; /* 0x00000002ff037212 */
/* 0x000fe200078e33ff */
/*0100*/ IMAD.MOV.U32 R5, RZ, RZ, 0x2 ; /* 0x00000002ff057424 */
/* 0x000fc600078e00ff */
/*0110*/ IADD3 R3, R3, c[0x0][0x174], RZ ; /* 0x00005d0003037a10 */
/* 0x000fe40007ffe0ff */
/*0120*/ IADD3 R2, -R2, c[0x0][0x174], -R5 ; /* 0x00005d0002027a10 */
/* 0x000fe40007ffe905 */
/*0130*/ LOP3.LUT P1, R5, R3, 0x3, RZ, 0xc0, !PT ; /* 0x0000000303057812 */
/* 0x000fe4000782c0ff */
/*0140*/ ISETP.GE.U32.AND P0, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fe20003f06070 */
/*0150*/ IMAD.WIDE R2, R4, R7, c[0x0][0x168] ; /* 0x00005a0004027625 */
/* 0x000fd400078e0207 */
/*0160*/ @!P1 BRA 0x3b0 ; /* 0x0000024000009947 */
/* 0x000fea0003800000 */
/*0170*/ IMAD.WIDE R6, R0, R7, c[0x0][0x160] ; /* 0x0000580000067625 */
/* 0x000fc800078e0207 */
/*0180*/ IMAD.MOV.U32 R4, RZ, RZ, R6 ; /* 0x000000ffff047224 */
/* 0x000fe400078e0006 */
/*0190*/ IMAD.MOV.U32 R9, RZ, RZ, R7 ; /* 0x000000ffff097224 */
/* 0x000fe400078e0007 */
/*01a0*/ LDG.E R14, [R2.64] ; /* 0x00000004020e7981 */
/* 0x000ea2000c1e1900 */
/*01b0*/ IABS R12, R0 ; /* 0x00000000000c7213 */
/* 0x000fe40000000000 */
/*01c0*/ ISETP.GE.AND P3, PT, R0.reuse, RZ, PT ; /* 0x000000ff0000720c */
/* 0x040fe40003f66270 */
/*01d0*/ IADD3 R5, R5, -0x1, RZ ; /* 0xffffffff05057810 */
/* 0x000fe40007ffe0ff */
/*01e0*/ IADD3 R0, R0, 0x1, RZ ; /* 0x0000000100007810 */
/* 0x000fe40007ffe0ff */
/*01f0*/ IABS R10, R14 ; /* 0x0000000e000a7213 */
/* 0x004fc40000000000 */
/*0200*/ IABS R13, R14 ; /* 0x0000000e000d7213 */
/* 0x000fe40000000000 */
/*0210*/ I2F.RP R8, R10 ; /* 0x0000000a00087306 */
/* 0x001e300000209400 */
/*0220*/ MUFU.RCP R8, R8 ; /* 0x0000000800087308 */
/* 0x001e240000001000 */
/*0230*/ IADD3 R6, R8, 0xffffffe, RZ ; /* 0x0ffffffe08067810 */
/* 0x001fe20007ffe0ff */
/*0240*/ IMAD.MOV R8, RZ, RZ, -R13 ; /* 0x000000ffff087224 */
/* 0x000fca00078e0a0d */
/*0250*/ F2I.FTZ.U32.TRUNC.NTZ R7, R6 ; /* 0x0000000600077305 */
/* 0x000064000021f000 */
/*0260*/ IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff067224 */
/* 0x001fe400078e00ff */
/*0270*/ IMAD.MOV R11, RZ, RZ, -R7 ; /* 0x000000ffff0b7224 */
/* 0x002fc800078e0a07 */
/*0280*/ IMAD R11, R11, R10, RZ ; /* 0x0000000a0b0b7224 */
/* 0x000fc800078e02ff */
/*0290*/ IMAD.HI.U32 R7, R7, R11, R6 ; /* 0x0000000b07077227 */
/* 0x000fcc00078e0006 */
/*02a0*/ IMAD.HI.U32 R7, R7, R12, RZ ; /* 0x0000000c07077227 */
/* 0x000fc800078e00ff */
/*02b0*/ IMAD R7, R7, R8, R12 ; /* 0x0000000807077224 */
/* 0x000fca00078e020c */
/*02c0*/ ISETP.GT.U32.AND P1, PT, R10, R7, PT ; /* 0x000000070a00720c */
/* 0x000fda0003f24070 */
/*02d0*/ @!P1 IMAD.IADD R7, R7, 0x1, -R10 ; /* 0x0000000107079824 */
/* 0x000fe200078e0a0a */
/*02e0*/ ISETP.NE.AND P1, PT, R14, RZ, PT ; /* 0x000000ff0e00720c */
/* 0x000fc80003f25270 */
/*02f0*/ ISETP.GT.U32.AND P2, PT, R10, R7, PT ; /* 0x000000070a00720c */
/* 0x000fda0003f44070 */
/*0300*/ @!P2 IMAD.IADD R7, R7, 0x1, -R10 ; /* 0x000000010707a824 */
/* 0x000fe200078e0a0a */
/*0310*/ ISETP.NE.AND P2, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fc60003f45270 */
/*0320*/ @!P3 IMAD.MOV R7, RZ, RZ, -R7 ; /* 0x000000ffff07b224 */
/* 0x000fe200078e0a07 */
/*0330*/ @!P1 LOP3.LUT R7, RZ, R14, RZ, 0x33, !PT ; /* 0x0000000eff079212 */
/* 0x000fc800078e33ff */
/*0340*/ ISETP.NE.AND P1, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fda0003f25270 */
/*0350*/ @!P1 IMAD.MOV.U32 R6, RZ, RZ, R4 ; /* 0x000000ffff069224 */
/* 0x000fe400078e0004 */
/*0360*/ @!P1 IMAD.MOV.U32 R7, RZ, RZ, R9 ; /* 0x000000ffff079224 */
/* 0x000fca00078e0009 */
/*0370*/ @!P1 STG.E [R6.64], RZ ; /* 0x000000ff06009986 */
/* 0x0001e2000c101904 */
/*0380*/ IADD3 R4, P1, R4, 0x4, RZ ; /* 0x0000000404047810 */
/* 0x000fca0007f3e0ff */
/*0390*/ IMAD.X R9, RZ, RZ, R9, P1 ; /* 0x000000ffff097224 */
/* 0x000fe200008e0609 */
/*03a0*/ @P2 BRA 0x1a0 ; /* 0xfffffdf000002947 */
/* 0x000fea000383ffff */
/*03b0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*03c0*/ IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; /* 0x00000004ff057424 */
/* 0x000fc800078e00ff */
/*03d0*/ IMAD.WIDE R4, R0, R5, c[0x0][0x160] ; /* 0x0000580000047625 */
/* 0x000fc800078e0205 */
/*03e0*/ IMAD.MOV.U32 R8, RZ, RZ, R4 ; /* 0x000000ffff087224 */
/* 0x000fe400078e0004 */
/*03f0*/ IMAD.MOV.U32 R9, RZ, RZ, R5 ; /* 0x000000ffff097224 */
/* 0x000fe400078e0005 */
/*0400*/ LDG.E R6, [R2.64] ; /* 0x0000000402067981 */
/* 0x005ea2000c1e1900 */
/*0410*/ IABS R12, R0 ; /* 0x00000000000c7213 */
/* 0x000fe20000000000 */
/*0420*/ BSSY B0, 0x5f0 ; /* 0x000001c000007945 */
/* 0x000fe20003800000 */
/*0430*/ ISETP.GE.AND P2, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe40003f46270 */
/*0440*/ IABS R10, R6.reuse ; /* 0x00000006000a7213 */
/* 0x084fe40000000000 */
/*0450*/ IABS R13, R6 ; /* 0x00000006000d7213 */
/* 0x000fe40000000000 */
/*0460*/ I2F.RP R7, R10 ; /* 0x0000000a00077306 */
/* 0x000e300000209400 */
/*0470*/ MUFU.RCP R7, R7 ; /* 0x0000000700077308 */
/* 0x001e240000001000 */
/*0480*/ IADD3 R4, R7, 0xffffffe, RZ ; /* 0x0ffffffe07047810 */
/* 0x003fe20007ffe0ff */
/*0490*/ IMAD.MOV R7, RZ, RZ, -R13 ; /* 0x000000ffff077224 */
/* 0x000fca00078e0a0d */
/*04a0*/ F2I.FTZ.U32.TRUNC.NTZ R5, R4 ; /* 0x0000000400057305 */
/* 0x000064000021f000 */
/*04b0*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x001fe400078e00ff */
/*04c0*/ IMAD.MOV R11, RZ, RZ, -R5 ; /* 0x000000ffff0b7224 */
/* 0x002fc800078e0a05 */
/*04d0*/ IMAD R11, R11, R10, RZ ; /* 0x0000000a0b0b7224 */
/* 0x000fc800078e02ff */
/*04e0*/ IMAD.HI.U32 R5, R5, R11, R4 ; /* 0x0000000b05057227 */
/* 0x000fc800078e0004 */
/*04f0*/ IMAD.MOV.U32 R4, RZ, RZ, R8 ; /* 0x000000ffff047224 */
/* 0x000fe400078e0008 */
/*0500*/ IMAD.HI.U32 R5, R5, R12, RZ ; /* 0x0000000c05057227 */
/* 0x000fc800078e00ff */
/*0510*/ IMAD R5, R5, R7, R12 ; /* 0x0000000705057224 */
/* 0x000fca00078e020c */
/*0520*/ ISETP.GT.U32.AND P0, PT, R10, R5, PT ; /* 0x000000050a00720c */
/* 0x000fda0003f04070 */
/*0530*/ @!P0 IMAD.IADD R5, R5, 0x1, -R10 ; /* 0x0000000105058824 */
/* 0x000fe200078e0a0a */
/*0540*/ ISETP.NE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fc80003f05270 */
/*0550*/ ISETP.GT.U32.AND P1, PT, R10, R5, PT ; /* 0x000000050a00720c */
/* 0x000fda0003f24070 */
/*0560*/ @!P1 IMAD.IADD R5, R5, 0x1, -R10 ; /* 0x0000000105059824 */
/* 0x000fca00078e0a0a */
/*0570*/ @!P2 IADD3 R5, -R5, RZ, RZ ; /* 0x000000ff0505a210 */
/* 0x000fe40007ffe1ff */
/*0580*/ @!P0 LOP3.LUT R5, RZ, R6, RZ, 0x33, !PT ; /* 0x00000006ff058212 */
/* 0x000fc800078e33ff */
/*0590*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe20003f05270 */
/*05a0*/ IMAD.MOV.U32 R5, RZ, RZ, R9 ; /* 0x000000ffff057224 */
/* 0x000fd800078e0009 */
/*05b0*/ @P0 BRA 0x5e0 ; /* 0x0000002000000947 */
/* 0x000fea0003800000 */
/*05c0*/ STG.E [R4.64], RZ ; /* 0x000000ff04007986 */
/* 0x0001e8000c101904 */
/*05d0*/ LDG.E R6, [R2.64] ; /* 0x0000000402067981 */
/* 0x000164000c1e1900 */
/*05e0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*05f0*/ IABS R12, R6.reuse ; /* 0x00000006000c7213 */
/* 0x0a0fe20000000000 */
/*0600*/ BSSY B0, 0x7c0 ; /* 0x000001b000007945 */
/* 0x000fe20003800000 */
/*0610*/ IADD3 R7, R0, 0x1, RZ ; /* 0x0000000100077810 */
/* 0x000fe40007ffe0ff */
/*0620*/ I2F.RP R10, R12 ; /* 0x0000000c000a7306 */
/* 0x000e620000209400 */
/*0630*/ IABS R13, R6 ; /* 0x00000006000d7213 */
/* 0x000fe40000000000 */
/*0640*/ IABS R14, R7 ; /* 0x00000007000e7213 */
/* 0x000fc40000000000 */
/*0650*/ ISETP.GE.AND P2, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fc60003f46270 */
/*0660*/ MUFU.RCP R10, R10 ; /* 0x0000000a000a7308 */
/* 0x002e640000001000 */
/*0670*/ IADD3 R8, R10, 0xffffffe, RZ ; /* 0x0ffffffe0a087810 */
/* 0x002fcc0007ffe0ff */
/*0680*/ F2I.FTZ.U32.TRUNC.NTZ R9, R8 ; /* 0x0000000800097305 */
/* 0x0002a4000021f000 */
/*0690*/ IMAD.MOV.U32 R8, RZ, RZ, RZ ; /* 0x000000ffff087224 */
/* 0x002fe400078e00ff */
/*06a0*/ IMAD.MOV R11, RZ, RZ, -R9 ; /* 0x000000ffff0b7224 */
/* 0x004fc800078e0a09 */
/*06b0*/ IMAD R11, R11, R12, RZ ; /* 0x0000000c0b0b7224 */
/* 0x000fc800078e02ff */
/*06c0*/ IMAD.HI.U32 R9, R9, R11, R8 ; /* 0x0000000b09097227 */
/* 0x000fc800078e0008 */
/*06d0*/ IMAD.MOV R8, RZ, RZ, -R13 ; /* 0x000000ffff087224 */
/* 0x000fe400078e0a0d */
/*06e0*/ IMAD.HI.U32 R9, R9, R14, RZ ; /* 0x0000000e09097227 */
/* 0x000fc800078e00ff */
/*06f0*/ IMAD R9, R9, R8, R14 ; /* 0x0000000809097224 */
/* 0x000fca00078e020e */
/*0700*/ ISETP.GT.U32.AND P0, PT, R12, R9, PT ; /* 0x000000090c00720c */
/* 0x000fda0003f04070 */
/*0710*/ @!P0 IMAD.IADD R9, R9, 0x1, -R12 ; /* 0x0000000109098824 */
/* 0x000fe200078e0a0c */
/*0720*/ ISETP.NE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fc80003f05270 */
/*0730*/ ISETP.GT.U32.AND P1, PT, R12, R9, PT ; /* 0x000000090c00720c */
/* 0x000fda0003f24070 */
/*0740*/ @!P1 IMAD.IADD R9, R9, 0x1, -R12 ; /* 0x0000000109099824 */
/* 0x000fc800078e0a0c */
/*0750*/ @!P2 IMAD.MOV R9, RZ, RZ, -R9 ; /* 0x000000ffff09a224 */
/* 0x000fe200078e0a09 */
/*0760*/ @!P0 LOP3.LUT R9, RZ, R6, RZ, 0x33, !PT ; /* 0x00000006ff098212 */
/* 0x000fc800078e33ff */
/*0770*/ ISETP.NE.AND P0, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x000fda0003f05270 */
/*0780*/ @P0 BRA 0x7b0 ; /* 0x0000002000000947 */
/* 0x000fea0003800000 */
/*0790*/ STG.E [R4.64+0x4], RZ ; /* 0x000004ff04007986 */
/* 0x0003e8000c101904 */
/*07a0*/ LDG.E R6, [R2.64] ; /* 0x0000000402067981 */
/* 0x000364000c1e1900 */
/*07b0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*07c0*/ IABS R13, R6 ; /* 0x00000006000d7213 */
/* 0x020fe20000000000 */
/*07d0*/ BSSY B0, 0x990 ; /* 0x000001b000007945 */
/* 0x000fe20003800000 */
/*07e0*/ IADD3 R7, R0, 0x2, RZ ; /* 0x0000000200077810 */
/* 0x000fe40007ffe0ff */
/*07f0*/ I2F.RP R10, R13 ; /* 0x0000000d000a7306 */
/* 0x000ea20000209400 */
/*0800*/ ISETP.NE.AND P2, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe40003f45270 */
/*0810*/ IABS R11, R7 ; /* 0x00000007000b7213 */
/* 0x000fc40000000000 */
/*0820*/ ISETP.GE.AND P1, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fc60003f26270 */
/*0830*/ MUFU.RCP R10, R10 ; /* 0x0000000a000a7308 */
/* 0x004ea40000001000 */
/*0840*/ IADD3 R8, R10, 0xffffffe, RZ ; /* 0x0ffffffe0a087810 */
/* 0x004fcc0007ffe0ff */
/*0850*/ F2I.FTZ.U32.TRUNC.NTZ R9, R8 ; /* 0x0000000800097305 */
/* 0x0004e4000021f000 */
/*0860*/ IMAD.MOV.U32 R8, RZ, RZ, RZ ; /* 0x000000ffff087224 */
/* 0x004fe400078e00ff */
/*0870*/ IMAD.MOV R12, RZ, RZ, -R9 ; /* 0x000000ffff0c7224 */
/* 0x008fc800078e0a09 */
/*0880*/ IMAD R15, R12, R13, RZ ; /* 0x0000000d0c0f7224 */
/* 0x000fe200078e02ff */
/*0890*/ IABS R12, R6 ; /* 0x00000006000c7213 */
/* 0x000fc60000000000 */
/*08a0*/ IMAD.HI.U32 R10, R9, R15, R8 ; /* 0x0000000f090a7227 */
/* 0x000fc800078e0008 */
/*08b0*/ IMAD.MOV R9, RZ, RZ, -R12 ; /* 0x000000ffff097224 */
/* 0x000fe400078e0a0c */
/*08c0*/ IMAD.HI.U32 R8, R10, R11, RZ ; /* 0x0000000b0a087227 */
/* 0x000fc800078e00ff */
/*08d0*/ IMAD R8, R8, R9, R11 ; /* 0x0000000908087224 */
/* 0x000fca00078e020b */
/*08e0*/ ISETP.GT.U32.AND P0, PT, R13, R8, PT ; /* 0x000000080d00720c */
/* 0x000fda0003f04070 */
/*08f0*/ @!P0 IADD3 R8, R8, -R13, RZ ; /* 0x8000000d08088210 */
/* 0x000fc80007ffe0ff */
/*0900*/ ISETP.GT.U32.AND P0, PT, R13, R8, PT ; /* 0x000000080d00720c */
/* 0x000fda0003f04070 */
/*0910*/ @!P0 IMAD.IADD R8, R8, 0x1, -R13 ; /* 0x0000000108088824 */
/* 0x000fc800078e0a0d */
/*0920*/ @!P1 IMAD.MOV R8, RZ, RZ, -R8 ; /* 0x000000ffff089224 */
/* 0x000fe200078e0a08 */
/*0930*/ @!P2 LOP3.LUT R8, RZ, R6, RZ, 0x33, !PT ; /* 0x00000006ff08a212 */
/* 0x000fc800078e33ff */
/*0940*/ ISETP.NE.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fda0003f05270 */
/*0950*/ @P0 BRA 0x980 ; /* 0x0000002000000947 */
/* 0x000fea0003800000 */
/*0960*/ STG.E [R4.64+0x8], RZ ; /* 0x000008ff04007986 */
/* 0x0005e8000c101904 */
/*0970*/ LDG.E R6, [R2.64] ; /* 0x0000000402067981 */
/* 0x000564000c1e1900 */
/*0980*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0990*/ IABS R12, R6.reuse ; /* 0x00000006000c7213 */
/* 0x0a0fe40000000000 */
/*09a0*/ IADD3 R7, R0, 0x3, RZ ; /* 0x0000000300077810 */
/* 0x000fe40007ffe0ff */
/*09b0*/ I2F.RP R10, R12 ; /* 0x0000000c000a7306 */
/* 0x000ee20000209400 */
/*09c0*/ IABS R13, R6 ; /* 0x00000006000d7213 */
/* 0x000fe40000000000 */
/*09d0*/ ISETP.GE.AND P2, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fc40003f46270 */
/*09e0*/ IADD3 R0, R0, 0x4, RZ ; /* 0x0000000400007810 */
/* 0x000fe20007ffe0ff */
/*09f0*/ IMAD.MOV R13, RZ, RZ, -R13 ; /* 0x000000ffff0d7224 */
/* 0x000fe400078e0a0d */
/*0a00*/ MUFU.RCP R10, R10 ; /* 0x0000000a000a7308 */
/* 0x008ee40000001000 */
/*0a10*/ IADD3 R8, R10, 0xffffffe, RZ ; /* 0x0ffffffe0a087810 */
/* 0x008fe40007ffe0ff */
/*0a20*/ IABS R10, R7 ; /* 0x00000007000a7213 */
/* 0x000fc80000000000 */
/*0a30*/ F2I.FTZ.U32.TRUNC.NTZ R9, R8 ; /* 0x0000000800097305 */
/* 0x000724000021f000 */
/*0a40*/ IMAD.MOV.U32 R8, RZ, RZ, RZ ; /* 0x000000ffff087224 */
/* 0x008fe400078e00ff */
/*0a50*/ IMAD.MOV R11, RZ, RZ, -R9 ; /* 0x000000ffff0b7224 */
/* 0x010fc800078e0a09 */
/*0a60*/ IMAD R11, R11, R12, RZ ; /* 0x0000000c0b0b7224 */
/* 0x000fc800078e02ff */
/*0a70*/ IMAD.HI.U32 R9, R9, R11, R8 ; /* 0x0000000b09097227 */
/* 0x000fc800078e0008 */
/*0a80*/ IMAD.MOV.U32 R8, RZ, RZ, R13 ; /* 0x000000ffff087224 */
/* 0x000fe400078e000d */
/*0a90*/ IMAD.HI.U32 R9, R9, R10, RZ ; /* 0x0000000a09097227 */
/* 0x000fc800078e00ff */
/*0aa0*/ IMAD R9, R9, R8, R10 ; /* 0x0000000809097224 */
/* 0x000fca00078e020a */
/*0ab0*/ ISETP.GT.U32.AND P0, PT, R12, R9, PT ; /* 0x000000090c00720c */
/* 0x000fda0003f04070 */
/*0ac0*/ @!P0 IMAD.IADD R9, R9, 0x1, -R12 ; /* 0x0000000109098824 */
/* 0x000fe200078e0a0c */
/*0ad0*/ ISETP.NE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fc80003f05270 */
/*0ae0*/ ISETP.GT.U32.AND P1, PT, R12, R9, PT ; /* 0x000000090c00720c */
/* 0x000fda0003f24070 */
/*0af0*/ @!P1 IMAD.IADD R9, R9, 0x1, -R12 ; /* 0x0000000109099824 */
/* 0x000fe200078e0a0c */
/*0b00*/ IADD3 R8, P1, R4, 0x10, RZ ; /* 0x0000001004087810 */
/* 0x000fc60007f3e0ff */
/*0b10*/ @!P2 IMAD.MOV R9, RZ, RZ, -R9 ; /* 0x000000ffff09a224 */
/* 0x000fe200078e0a09 */
/*0b20*/ @!P0 LOP3.LUT R9, RZ, R6, RZ, 0x33, !PT ; /* 0x00000006ff098212 */
/* 0x000fc800078e33ff */
/*0b30*/ ISETP.NE.AND P0, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x000fe20003f05270 */
/*0b40*/ IMAD.X R9, RZ, RZ, R5, P1 ; /* 0x000000ffff097224 */
/* 0x000fd800008e0605 */
/*0b50*/ @!P0 STG.E [R4.64+0xc], RZ ; /* 0x00000cff04008986 */
/* 0x0007e2000c101904 */
/*0b60*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x174], PT ; /* 0x00005d0000007a0c */
/* 0x000fda0003f06270 */
/*0b70*/ @!P0 BRA 0x400 ; /* 0xfffff88000008947 */
/* 0x008fea000383ffff */
/*0b80*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0b90*/ BRA 0xb90; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0ba0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0be0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10calcPrimesPiS_ii
.globl _Z10calcPrimesPiS_ii
.p2align 8
.type _Z10calcPrimesPiS_ii,@function
_Z10calcPrimesPiS_ii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s4, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s4, v1
s_cbranch_execz .LBB0_6
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x8
s_load_b32 s6, s[0:1], 0x14
s_ashr_i32 s5, s4, 31
s_delay_alu instid0(SALU_CYCLE_1)
s_lshl_b64 s[4:5], s[4:5], 2
s_waitcnt lgkmcnt(0)
s_add_u32 s4, s2, s4
s_addc_u32 s5, s3, s5
s_add_u32 s4, s4, -4
s_addc_u32 s5, s5, -1
s_load_b32 s4, s[4:5], 0x0
s_waitcnt lgkmcnt(0)
s_add_i32 s7, s4, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_ge_i32 s7, s6
s_cbranch_scc1 .LBB0_6
s_load_b64 s[0:1], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_ashr_i32 s5, s4, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_lshl_b64 s[4:5], s[4:5], 2
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_mov_b32_e32 v2, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s4, s0
s_addc_u32 s1, s5, s1
s_add_u32 s0, s0, 4
s_addc_u32 s1, s1, 0
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_4
.p2align 6
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s2
s_add_i32 s7, s7, 1
s_add_u32 s0, s0, 4
s_addc_u32 s1, s1, 0
s_cmp_lt_i32 s7, s6
s_cbranch_scc0 .LBB0_6
.LBB0_4:
global_load_b32 v3, v[0:1], off
s_ashr_i32 s2, s7, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s3, s7, s2
s_xor_b32 s3, s3, s2
s_waitcnt vmcnt(0)
v_ashrrev_i32_e32 v4, 31, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v3, v3, v4
v_xor_b32_e32 v3, v3, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cvt_f32_u32_e32 v4, v3
v_sub_nc_u32_e32 v5, 0, v3
v_rcp_iflag_f32_e32 v4, v4
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v4, 0x4f7ffffe, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_u32_f32_e32 v4, v4
v_mul_lo_u32 v5, v5, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v5, v4, v5
v_add_nc_u32_e32 v4, v4, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v4, s3, v4
v_mul_lo_u32 v4, v4, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v4, s3, v4
v_sub_nc_u32_e32 v5, v4, v3
v_cmp_ge_u32_e32 vcc_lo, v4, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v4, v4, v5, vcc_lo
v_sub_nc_u32_e32 v5, v4, v3
v_cmp_ge_u32_e32 vcc_lo, v4, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v3, v4, v5, vcc_lo
v_xor_b32_e32 v3, s2, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_subrev_nc_u32_e32 v3, s2, v3
s_mov_b32 s2, exec_lo
v_cmpx_eq_u32_e32 0, v3
s_cbranch_execz .LBB0_3
global_store_b32 v2, v2, s[0:1]
s_branch .LBB0_3
.LBB0_6:
s_set_inst_prefetch_distance 0x2
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10calcPrimesPiS_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10calcPrimesPiS_ii, .Lfunc_end0-_Z10calcPrimesPiS_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10calcPrimesPiS_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z10calcPrimesPiS_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0009131a_00000000-6_primes_v1.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z21generateInitialPrimesPiPS_i
.type _Z21generateInitialPrimesPiPS_i, @function
_Z21generateInitialPrimesPiPS_i:
.LFB2058:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $8, %rsp
.cfi_def_cfa_offset 48
movq %rsi, %r12
movl %edx, %ebx
movl $4000, %edi
call malloc@PLT
movq %rax, %rbp
movl $2000, %edi
call malloc@PLT
movq %rax, (%r12)
testl %ebx, %ebx
jle .L13
movq %rbp, %rax
movslq %ebx, %rdx
leaq 0(%rbp,%rdx,4), %rdx
.L5:
movl $1, (%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L5
cmpl $3, %ebx
jle .L6
movl $2, %edx
movl $4, %esi
.L9:
movl %edx, %ecx
cmpl %esi, %ebx
jl .L7
movslq %esi, %rax
.L8:
movl $0, 0(%rbp,%rax,4)
addq %rdx, %rax
cmpl %eax, %ebx
jge .L8
.L7:
leal 1(%rcx), %eax
addl $2, %esi
addq $1, %rdx
imull %eax, %eax
cmpl %ebx, %eax
jle .L9
.L10:
leal 1(%rbx), %edx
movl $2, %eax
movl $0, %r13d
jmp .L12
.L6:
movl $0, %r13d
cmpl $1, %ebx
jle .L4
jmp .L10
.L11:
addq $1, %rax
cmpq %rdx, %rax
je .L4
.L12:
cmpl $1, 0(%rbp,%rax,4)
jne .L11
movslq %r13d, %rsi
movq (%r12), %rcx
movl %eax, (%rcx,%rsi,4)
addl $1, %r13d
jmp .L11
.L13:
movl $0, %r13d
.L4:
movq %rbp, %rdi
call free@PLT
movl %r13d, %eax
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _Z21generateInitialPrimesPiPS_i, .-_Z21generateInitialPrimesPiPS_i
.globl _Z34__device_stub__Z10calcPrimesPiS_iiPiS_ii
.type _Z34__device_stub__Z10calcPrimesPiS_iiPiS_ii, @function
_Z34__device_stub__Z10calcPrimesPiS_iiPiS_ii:
.LFB2083:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L24
.L20:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L25
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L24:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z10calcPrimesPiS_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L20
.L25:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z34__device_stub__Z10calcPrimesPiS_iiPiS_ii, .-_Z34__device_stub__Z10calcPrimesPiS_iiPiS_ii
.globl _Z10calcPrimesPiS_ii
.type _Z10calcPrimesPiS_ii, @function
_Z10calcPrimesPiS_ii:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z34__device_stub__Z10calcPrimesPiS_iiPiS_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z10calcPrimesPiS_ii, .-_Z10calcPrimesPiS_ii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "\nThe initial primes calculated are:\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "%d "
.section .rodata.str1.8
.align 8
.LC3:
.string "\nNumber of initial primes = %d\n\n"
.align 8
.LC4:
.string "********* New Primes List **********\n"
.align 8
.LC5:
.string "\n\nNumber of new primes found = %d\n\n"
.align 8
.LC7:
.string "Time taken to find initial primes on CPU = %f ms\n"
.align 8
.LC8:
.string "Parallel Job time for current iteration = %f ms\n\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $104, %rsp
.cfi_def_cfa_offset 160
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
movq $0, 24(%rsp)
movq $0, 32(%rsp)
movq $0, 40(%rsp)
leaq 48(%rsp), %rdi
call cudaEventCreate@PLT
leaq 56(%rsp), %rdi
call cudaEventCreate@PLT
call clock@PLT
movq %rax, %rbp
leaq 24(%rsp), %rsi
movl $1000, %edx
movl $0, %edi
call _Z21generateInitialPrimesPiPS_i
movl %eax, %ebx
call clock@PLT
subq %rbp, %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
divsd .LC0(%rip), %xmm0
movsd %xmm0, 8(%rsp)
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
testl %ebx, %ebx
jle .L29
movslq %ebx, %r12
salq $2, %r12
movl $0, %ebp
leaq .LC2(%rip), %r13
.L30:
movq 24(%rsp), %rax
movl (%rax,%rbp), %edx
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbp
cmpq %r12, %rbp
jne .L30
.L29:
movl %ebx, %edx
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $4000000, %edi
call malloc@PLT
movq %rax, %r15
leal 0(,%rbx,4), %ebp
leaq 4000000(%rax), %rdx
.L31:
movl $1, (%rax)
addq $4, %rax
cmpq %rax, %rdx
jne .L31
leaq 32(%rsp), %rdi
movl $4000000, %esi
call cudaMalloc@PLT
movslq %ebp, %rbp
leaq 40(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movl $4000000, %edx
movq %r15, %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
movq 24(%rsp), %rax
movq %rax, (%rsp)
movl $1, %ecx
movq %rbp, %rdx
movq %rax, %rsi
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
movl $0, %esi
movq 48(%rsp), %rdi
call cudaEventRecord@PLT
movl $32, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leal 31(%rbx), %eax
testl %ebx, %ebx
cmovns %ebx, %eax
sarl $5, %eax
addl $1, %eax
movl %eax, 64(%rsp)
movl $1, 68(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 76(%rsp), %rdx
movl $1, %ecx
movq 64(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L40
.L32:
movl $0, %esi
movq 56(%rsp), %rdi
call cudaEventRecord@PLT
movq 56(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 76(%rsp), %rdi
movq 56(%rsp), %rdx
movq 48(%rsp), %rsi
call cudaEventElapsedTime@PLT
movl $4000000, %edi
call malloc@PLT
movq %rax, %rbp
movl $2, %ecx
movl $4000000, %edx
movq 32(%rsp), %rsi
movq %rax, %rdi
call cudaMemcpy@PLT
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1000000, %edi
call malloc@PLT
movq %rax, %r13
movl $1000, %ebx
movl $0, %r12d
leaq .LC2(%rip), %r14
jmp .L34
.L40:
movl $1000000, %ecx
movl %ebx, %edx
movq 40(%rsp), %rsi
movq 32(%rsp), %rdi
call _Z34__device_stub__Z10calcPrimesPiS_iiPiS_ii
jmp .L32
.L33:
addq $1, %rbx
cmpq $1000000, %rbx
je .L41
.L34:
cmpl $1, 0(%rbp,%rbx,4)
jne .L33
movslq %r12d, %rax
movl $1, 0(%r13,%rax,4)
addl $1, %r12d
movl %ebx, %edx
movq %r14, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L33
.L41:
movl %r12d, %edx
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movsd 8(%rsp), %xmm0
mulsd .LC6(%rip), %xmm0
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
pxor %xmm0, %xmm0
cvtss2sd 76(%rsp), %xmm0
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq %r15, %rdi
call free@PLT
movq (%rsp), %rdi
call free@PLT
movq %rbp, %rdi
call free@PLT
movq %r13, %rdi
call free@PLT
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L42
movl $0, %eax
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L42:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC9:
.string "_Z10calcPrimesPiS_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _Z10calcPrimesPiS_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long 0
.long 1093567616
.align 8
.LC6:
.long 0
.long 1083129856
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "primes_v1.hip"
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI0_0:
.quad 0x412e848000000000 # double 1.0E+6
.LCPI0_1:
.quad 0x408f400000000000 # double 1000
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $152, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq $0, (%rsp)
movq $0, 8(%rsp)
leaq 40(%rsp), %rdi
callq hipEventCreate
leaq 24(%rsp), %rdi
callq hipEventCreate
callq clock
movq %rax, 16(%rsp) # 8-byte Spill
movl $4000, %edi # imm = 0xFA0
callq malloc
movq %rax, %r15
movl $2000, %edi # imm = 0x7D0
callq malloc
movq %rax, %rbx
xorl %eax, %eax
.p2align 4, 0x90
.LBB0_1: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
movl $1, (%r15,%rax,4)
incq %rax
cmpq $1000, %rax # imm = 0x3E8
jne .LBB0_1
# %bb.2: # %.lr.ph41.i.preheader
movq %r15, %rax
addq $16, %rax
movl $4, %ecx
movl $2, %edx
movl $8, %esi
.p2align 4, 0x90
.LBB0_3: # %.lr.ph41.i
# =>This Loop Header: Depth=1
# Child Loop BB0_4 Depth 2
movq %rax, %rdi
movq %rcx, %r8
.p2align 4, 0x90
.LBB0_4: # %.lr.ph38.i
# Parent Loop BB0_3 Depth=1
# => This Inner Loop Header: Depth=2
movl $0, (%rdi)
addq %rdx, %r8
addq %rsi, %rdi
cmpq $1000, %r8 # imm = 0x3E8
jbe .LBB0_4
# %bb.5: # %._crit_edge.i
# in Loop: Header=BB0_3 Depth=1
incq %rdx
addq $2, %rcx
addq $8, %rax
addq $4, %rsi
cmpq $32, %rdx
jne .LBB0_3
# %bb.6: # %.lr.ph45.i.preheader
xorl %r13d, %r13d
movl $2, %eax
jmp .LBB0_7
.p2align 4, 0x90
.LBB0_9: # in Loop: Header=BB0_7 Depth=1
incq %rax
cmpq $1001, %rax # imm = 0x3E9
je .LBB0_10
.LBB0_7: # %.lr.ph45.i
# =>This Inner Loop Header: Depth=1
cmpl $1, (%r15,%rax,4)
jne .LBB0_9
# %bb.8: # in Loop: Header=BB0_7 Depth=1
movslq %r13d, %r13
movl %eax, (%rbx,%r13,4)
incl %r13d
jmp .LBB0_9
.LBB0_10: # %_Z21generateInitialPrimesPiPS_i.exit
movq %r15, %rdi
callq free
callq clock
movq %rax, %r15
movl $.Lstr, %edi
callq puts@PLT
testl %r13d, %r13d
jle .LBB0_13
# %bb.11: # %.lr.ph.preheader
movl %r13d, %r14d
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB0_12: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl (%rbx,%r12,4), %esi
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
incq %r12
cmpq %r12, %r14
jne .LBB0_12
.LBB0_13: # %._crit_edge
xorl %r14d, %r14d
movl $.L.str.2, %edi
movl %r13d, %esi
xorl %eax, %eax
callq printf
movl $4000000, %edi # imm = 0x3D0900
callq malloc
movq %rax, %r12
.p2align 4, 0x90
.LBB0_14: # =>This Inner Loop Header: Depth=1
movl $1, (%r12,%r14,4)
incq %r14
cmpq $1000000, %r14 # imm = 0xF4240
jne .LBB0_14
# %bb.15:
leal (,%r13,4), %ebp
movq %rsp, %rdi
movl $4000000, %esi # imm = 0x3D0900
callq hipMalloc
movslq %ebp, %r14
leaq 8(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
movq (%rsp), %rdi
movl $4000000, %edx # imm = 0x3D0900
movq %r12, %rsi
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
movq %rbx, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
movq 40(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
leal 31(%r13), %edi
testl %r13d, %r13d
cmovnsl %r13d, %edi
sarl $5, %edi
incl %edi
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %rdi
orq $32, %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB0_17
# %bb.16:
movq (%rsp), %rax
movq 8(%rsp), %rcx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movl %r13d, 36(%rsp)
movl $1000000, 32(%rsp) # imm = 0xF4240
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 36(%rsp), %rax
movq %rax, 128(%rsp)
leaq 32(%rsp), %rax
movq %rax, 136(%rsp)
leaq 80(%rsp), %rdi
leaq 64(%rsp), %rsi
leaq 56(%rsp), %rdx
leaq 48(%rsp), %rcx
callq __hipPopCallConfiguration
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
movq 64(%rsp), %rcx
movl 72(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z10calcPrimesPiS_ii, %edi
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB0_17:
movq 24(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 24(%rsp), %rdi
callq hipEventSynchronize
movq 40(%rsp), %rsi
movq 24(%rsp), %rdx
leaq 112(%rsp), %rdi
callq hipEventElapsedTime
movl $4000000, %edi # imm = 0x3D0900
callq malloc
movq %rax, %r13
movq (%rsp), %rsi
movl $4000000, %edx # imm = 0x3D0900
movq %rax, %rdi
movl $2, %ecx
callq hipMemcpy
movl $.Lstr.1, %edi
callq puts@PLT
movl $1000, %r14d # imm = 0x3E8
xorl %ebp, %ebp
jmp .LBB0_18
.p2align 4, 0x90
.LBB0_20: # in Loop: Header=BB0_18 Depth=1
incq %r14
cmpq $1000000, %r14 # imm = 0xF4240
je .LBB0_21
.LBB0_18: # =>This Inner Loop Header: Depth=1
cmpl $1, (%r13,%r14,4)
jne .LBB0_20
# %bb.19: # in Loop: Header=BB0_18 Depth=1
incl %ebp
movl $.L.str.1, %edi
movl %r14d, %esi
xorl %eax, %eax
callq printf
jmp .LBB0_20
.LBB0_21:
subq 16(%rsp), %r15 # 8-byte Folded Reload
cvtsi2sd %r15, %xmm0
divsd .LCPI0_0(%rip), %xmm0
movsd %xmm0, 16(%rsp) # 8-byte Spill
movl $.L.str.4, %edi
movl %ebp, %esi
xorl %eax, %eax
callq printf
movsd 16(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
mulsd .LCPI0_1(%rip), %xmm0
movl $.L.str.5, %edi
movb $1, %al
callq printf
movss 112(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.6, %edi
movb $1, %al
callq printf
movq (%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq %r12, %rdi
callq free
movq %rbx, %rdi
callq free
movq %r13, %rdi
callq free
xorl %eax, %eax
addq $152, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.globl _Z21generateInitialPrimesPiPS_i # -- Begin function _Z21generateInitialPrimesPiPS_i
.p2align 4, 0x90
.type _Z21generateInitialPrimesPiPS_i,@function
_Z21generateInitialPrimesPiPS_i: # @_Z21generateInitialPrimesPiPS_i
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl %edx, %ebx
movq %rsi, %r15
movl $4000, %edi # imm = 0xFA0
callq malloc
movq %rax, %r14
movl $2000, %edi # imm = 0x7D0
callq malloc
movq %rax, (%r15)
testl %ebx, %ebx
jle .LBB1_3
# %bb.1: # %.lr.ph.preheader
movl %ebx, %ecx
xorl %edx, %edx
.p2align 4, 0x90
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl $1, (%r14,%rdx,4)
incq %rdx
cmpq %rdx, %rcx
jne .LBB1_2
.LBB1_3: # %.preheader34
cmpl $4, %ebx
jge .LBB1_4
.LBB1_7: # %.preheader
xorl %r15d, %r15d
cmpl $2, %ebx
jge .LBB1_8
.LBB1_12: # %._crit_edge46
movq %r14, %rdi
callq free
movl %r15d, %eax
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB1_4: # %.lr.ph41.preheader
.cfi_def_cfa_offset 32
movq %r14, %rcx
addq $16, %rcx
movl $2, %edx
movl $8, %esi
movl $4, %edi
jmp .LBB1_5
.p2align 4, 0x90
.LBB1_6: # %._crit_edge
# in Loop: Header=BB1_5 Depth=1
incq %rdx
movl %edx, %r8d
imull %edx, %r8d
addq $8, %rcx
addq $4, %rsi
addl $2, %edi
cmpl %ebx, %r8d
jg .LBB1_7
.LBB1_5: # %.lr.ph41
# =>This Loop Header: Depth=1
# Child Loop BB1_13 Depth 2
leal (%rdx,%rdx), %r10d
movl %edi, %r8d
movq %rcx, %r9
cmpl %ebx, %r10d
jg .LBB1_6
.p2align 4, 0x90
.LBB1_13: # %.lr.ph38
# Parent Loop BB1_5 Depth=1
# => This Inner Loop Header: Depth=2
movl $0, (%r9)
addq %rsi, %r9
addl %edx, %r8d
cmpl %ebx, %r8d
jle .LBB1_13
jmp .LBB1_6
.LBB1_8: # %.lr.ph45.preheader
incl %ebx
xorl %r15d, %r15d
movl $2, %ecx
jmp .LBB1_9
.p2align 4, 0x90
.LBB1_11: # in Loop: Header=BB1_9 Depth=1
incq %rcx
cmpq %rcx, %rbx
je .LBB1_12
.LBB1_9: # %.lr.ph45
# =>This Inner Loop Header: Depth=1
cmpl $1, (%r14,%rcx,4)
jne .LBB1_11
# %bb.10: # in Loop: Header=BB1_9 Depth=1
movslq %r15d, %r15
movl %ecx, (%rax,%r15,4)
incl %r15d
jmp .LBB1_11
.Lfunc_end1:
.size _Z21generateInitialPrimesPiPS_i, .Lfunc_end1-_Z21generateInitialPrimesPiPS_i
.cfi_endproc
# -- End function
.globl _Z25__device_stub__calcPrimesPiS_ii # -- Begin function _Z25__device_stub__calcPrimesPiS_ii
.p2align 4, 0x90
.type _Z25__device_stub__calcPrimesPiS_ii,@function
_Z25__device_stub__calcPrimesPiS_ii: # @_Z25__device_stub__calcPrimesPiS_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10calcPrimesPiS_ii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end2:
.size _Z25__device_stub__calcPrimesPiS_ii, .Lfunc_end2-_Z25__device_stub__calcPrimesPiS_ii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10calcPrimesPiS_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "%d "
.size .L.str.1, 5
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "\nNumber of initial primes = %d\n\n"
.size .L.str.2, 33
.type _Z10calcPrimesPiS_ii,@object # @_Z10calcPrimesPiS_ii
.section .rodata,"a",@progbits
.globl _Z10calcPrimesPiS_ii
.p2align 3, 0x0
_Z10calcPrimesPiS_ii:
.quad _Z25__device_stub__calcPrimesPiS_ii
.size _Z10calcPrimesPiS_ii, 8
.type .L.str.4,@object # @.str.4
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.4:
.asciz "\n\nNumber of new primes found = %d\n\n"
.size .L.str.4, 36
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Time taken to find initial primes on CPU = %f ms\n"
.size .L.str.5, 50
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "Parallel Job time for current iteration = %f ms\n\n"
.size .L.str.6, 50
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z10calcPrimesPiS_ii"
.size .L__unnamed_1, 21
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "\nThe initial primes calculated are:"
.size .Lstr, 36
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "********* New Primes List **********"
.size .Lstr.1, 37
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__calcPrimesPiS_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10calcPrimesPiS_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <stdlib.h>
#include <cuda.h>
#define THREADS_PER_BLOCK 1
#define THREADS_PER_SM 1
#define BLOCKS_NUM 1
#define TOTAL_THREADS (THREADS_PER_BLOCK*BLOCKS_NUM)
#define WARP_SIZE 32
#define REPEAT_TIMES 4096
// GPU error check
#define gpuErrchk(ans) { gpuAssert((ans), __FILE__, __LINE__); }
inline void gpuAssert(cudaError_t code, const char *file, int line, bool abort=true){
if (code != cudaSuccess) {
fprintf(stderr,"GPUassert: %s %s %d\n", cudaGetErrorString(code), file, line);
if (abort) exit(code);
}
}
template <class T>
__global__ void max_flops(uint32_t *startClk, uint32_t *stopClk, T *data1, T *res) {
int gid = blockIdx.x*blockDim.x + threadIdx.x;
//register T s1 = data1[gid];
//register T s2 = data2[gid];
//register T result = 0;
uint32_t index = 0;
int32_t offset = 10;
// synchronize all threads
asm volatile ("bar.sync 0;");
// start timing
uint32_t start = 0;
asm volatile ("mov.u32 %0, %%clock;" : "=r"(start) :: "memory");
//printf("%ld \n", &data1[0]);
for (int j=0 ; j<REPEAT_TIMES ; ++j) {
index = atomicAdd(&data1[index], offset);
//printf("index = %d", index);
}
// synchronize all threads
asm volatile("bar.sync 0;");
// stop timing
uint32_t stop = 0;
asm volatile("mov.u32 %0, %%clock;" : "=r"(stop) :: "memory");
// write time and data back to memory
startClk[gid] = start;
stopClk[gid] = stop;
res[gid] = data1[0];
}
int main(){
uint32_t *startClk = (uint32_t*) malloc(TOTAL_THREADS*sizeof(uint32_t));
uint32_t *stopClk = (uint32_t*) malloc(TOTAL_THREADS*sizeof(uint32_t));
int32_t *data1 = (int32_t*) malloc(REPEAT_TIMES*sizeof(int32_t));
//int32_t *data2 = (int32_t*) malloc(TOTAL_THREADS*sizeof(int32_t));
int32_t *res = (int32_t*) malloc(TOTAL_THREADS*sizeof(int32_t));
uint32_t *startClk_g;
uint32_t *stopClk_g;
int32_t *data1_g;
//int32_t *data2_g;
int32_t *res_g;
int32_t stride = 1;
for (int32_t i=0; i<(REPEAT_TIMES); i++)
data1[i] = (i+stride)%REPEAT_TIMES;
gpuErrchk( cudaMalloc(&startClk_g, TOTAL_THREADS*sizeof(uint32_t)) );
gpuErrchk( cudaMalloc(&stopClk_g, TOTAL_THREADS*sizeof(uint32_t)) );
gpuErrchk( cudaMalloc(&data1_g, REPEAT_TIMES*sizeof(int32_t)) );
//gpuErrchk( cudaMalloc(&data2_g, TOTAL_THREADS*sizeof(int32_t)) );
gpuErrchk( cudaMalloc(&res_g, TOTAL_THREADS*sizeof(int32_t)) );
//printf("address = %ld\n", (long)data1_g);
gpuErrchk( cudaMemcpy(data1_g, data1, REPEAT_TIMES*sizeof(int32_t), cudaMemcpyHostToDevice) );
//gpuErrchk( cudaMemcpy(data2_g, data2, TOTAL_THREADS*sizeof(int32_t), cudaMemcpyHostToDevice) );
max_flops<int32_t><<<BLOCKS_NUM,THREADS_PER_BLOCK>>>(startClk_g, stopClk_g, data1_g, res_g);
gpuErrchk( cudaPeekAtLastError() );
gpuErrchk( cudaMemcpy(startClk, startClk_g, TOTAL_THREADS*sizeof(uint32_t), cudaMemcpyDeviceToHost) );
gpuErrchk( cudaMemcpy(stopClk, stopClk_g, TOTAL_THREADS*sizeof(uint32_t), cudaMemcpyDeviceToHost) );
gpuErrchk( cudaMemcpy(res, res_g, TOTAL_THREADS*sizeof(int32_t), cudaMemcpyDeviceToHost) );
float latency;
latency = ((float)(stopClk[0]-startClk[0]))/((float)(REPEAT_TIMES));
printf("int32 latency = %f (clk)\n", latency);
printf("Total Clk number = %u \n", stopClk[0]-startClk[0]);
return 0;
} | code for sm_80
Function : _Z9max_flopsIiEvPjS0_PT_S2_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0030*/ CS2R.32 R0, SR_CLOCKLO ; /* 0x0000000000007805 */
/* 0x000fc60000005000 */
/*0040*/ HFMA2.MMA R3, -RZ, RZ, 0, 0 ; /* 0x00000000ff037435 */
/* 0x000fe200000001ff */
/*0050*/ MOV R9, RZ ; /* 0x000000ff00097202 */
/* 0x000fc60000000f00 */
/*0060*/ MOV R2, 0x4 ; /* 0x0000000400027802 */
/* 0x000fe40000000f00 */
/*0070*/ MOV R4, 0xa ; /* 0x0000000a00047802 */
/* 0x001fc60000000f00 */
/*0080*/ IMAD.WIDE.U32 R6, R9, R2, c[0x0][0x170] ; /* 0x00005c0009067625 */
/* 0x020fcc00078e0002 */
/*0090*/ ATOMG.E.ADD.STRONG.GPU PT, R7, [R6.64], R4 ; /* 0x00000004060779a8 */
/* 0x000ea400081ee1c4 */
/*00a0*/ IMAD.WIDE.U32 R8, R7, R2, c[0x0][0x170] ; /* 0x00005c0007087625 */
/* 0x004fcc00078e0002 */
/*00b0*/ ATOMG.E.ADD.STRONG.GPU PT, R9, [R8.64], R4 ; /* 0x00000004080979a8 */
/* 0x000ea400081ee1c4 */
/*00c0*/ IMAD.WIDE.U32 R10, R9, R2, c[0x0][0x170] ; /* 0x00005c00090a7625 */
/* 0x004fcc00078e0002 */
/*00d0*/ ATOMG.E.ADD.STRONG.GPU PT, R11, [R10.64], R4 ; /* 0x000000040a0b79a8 */
/* 0x000ea400081ee1c4 */
/*00e0*/ IMAD.WIDE.U32 R12, R11, R2, c[0x0][0x170] ; /* 0x00005c000b0c7625 */
/* 0x004fcc00078e0002 */
/*00f0*/ ATOMG.E.ADD.STRONG.GPU PT, R13, [R12.64], R4 ; /* 0x000000040c0d79a8 */
/* 0x000ea400081ee1c4 */
/*0100*/ IMAD.WIDE.U32 R14, R13, R2, c[0x0][0x170] ; /* 0x00005c000d0e7625 */
/* 0x004fcc00078e0002 */
/*0110*/ ATOMG.E.ADD.STRONG.GPU PT, R15, [R14.64], R4 ; /* 0x000000040e0f79a8 */
/* 0x000ea400081ee1c4 */
/*0120*/ IMAD.WIDE.U32 R16, R15, R2, c[0x0][0x170] ; /* 0x00005c000f107625 */
/* 0x004fcc00078e0002 */
/*0130*/ ATOMG.E.ADD.STRONG.GPU PT, R17, [R16.64], R4 ; /* 0x00000004101179a8 */
/* 0x000ea400081ee1c4 */
/*0140*/ IMAD.WIDE.U32 R6, R17, R2, c[0x0][0x170] ; /* 0x00005c0011067625 */
/* 0x004fcc00078e0002 */
/*0150*/ ATOMG.E.ADD.STRONG.GPU PT, R7, [R6.64], R4 ; /* 0x00000004060779a8 */
/* 0x000ea400081ee1c4 */
/*0160*/ IMAD.WIDE.U32 R8, R7, R2, c[0x0][0x170] ; /* 0x00005c0007087625 */
/* 0x004fcc00078e0002 */
/*0170*/ ATOMG.E.ADD.STRONG.GPU PT, R9, [R8.64], R4 ; /* 0x00000004080979a8 */
/* 0x000ea400081ee1c4 */
/*0180*/ IMAD.WIDE.U32 R10, R9, R2, c[0x0][0x170] ; /* 0x00005c00090a7625 */
/* 0x004fcc00078e0002 */
/*0190*/ ATOMG.E.ADD.STRONG.GPU PT, R11, [R10.64], R4 ; /* 0x000000040a0b79a8 */
/* 0x000ea400081ee1c4 */
/*01a0*/ IMAD.WIDE.U32 R12, R11, R2, c[0x0][0x170] ; /* 0x00005c000b0c7625 */
/* 0x004fcc00078e0002 */
/*01b0*/ ATOMG.E.ADD.STRONG.GPU PT, R13, [R12.64], R4 ; /* 0x000000040c0d79a8 */
/* 0x000ea400081ee1c4 */
/*01c0*/ IMAD.WIDE.U32 R14, R13, R2, c[0x0][0x170] ; /* 0x00005c000d0e7625 */
/* 0x004fcc00078e0002 */
/*01d0*/ ATOMG.E.ADD.STRONG.GPU PT, R15, [R14.64], R4 ; /* 0x000000040e0f79a8 */
/* 0x000ea400081ee1c4 */
/*01e0*/ IMAD.WIDE.U32 R16, R15, R2, c[0x0][0x170] ; /* 0x00005c000f107625 */
/* 0x004fcc00078e0002 */
/*01f0*/ ATOMG.E.ADD.STRONG.GPU PT, R17, [R16.64], R4 ; /* 0x00000004101179a8 */
/* 0x000ea400081ee1c4 */
/*0200*/ IMAD.WIDE.U32 R6, R17, R2, c[0x0][0x170] ; /* 0x00005c0011067625 */
/* 0x004fcc00078e0002 */
/*0210*/ ATOMG.E.ADD.STRONG.GPU PT, R7, [R6.64], R4 ; /* 0x00000004060779a8 */
/* 0x000ea400081ee1c4 */
/*0220*/ IMAD.WIDE.U32 R8, R7, R2, c[0x0][0x170] ; /* 0x00005c0007087625 */
/* 0x004fcc00078e0002 */
/*0230*/ ATOMG.E.ADD.STRONG.GPU PT, R9, [R8.64], R4 ; /* 0x00000004080979a8 */
/* 0x000ea400081ee1c4 */
/*0240*/ IMAD.WIDE.U32 R10, R9, R2, c[0x0][0x170] ; /* 0x00005c00090a7625 */
/* 0x004fcc00078e0002 */
/*0250*/ ATOMG.E.ADD.STRONG.GPU PT, R11, [R10.64], R4 ; /* 0x000000040a0b79a8 */
/* 0x000ea400081ee1c4 */
/*0260*/ IMAD.WIDE.U32 R12, R11, R2, c[0x0][0x170] ; /* 0x00005c000b0c7625 */
/* 0x004fcc00078e0002 */
/*0270*/ ATOMG.E.ADD.STRONG.GPU PT, R13, [R12.64], R4 ; /* 0x000000040c0d79a8 */
/* 0x000ea400081ee1c4 */
/*0280*/ IMAD.WIDE.U32 R14, R13, R2, c[0x0][0x170] ; /* 0x00005c000d0e7625 */
/* 0x004fcc00078e0002 */
/*0290*/ ATOMG.E.ADD.STRONG.GPU PT, R15, [R14.64], R4 ; /* 0x000000040e0f79a8 */
/* 0x000ea400081ee1c4 */
/*02a0*/ IMAD.WIDE.U32 R16, R15, R2, c[0x0][0x170] ; /* 0x00005c000f107625 */
/* 0x004fcc00078e0002 */
/*02b0*/ ATOMG.E.ADD.STRONG.GPU PT, R17, [R16.64], R4 ; /* 0x00000004101179a8 */
/* 0x000ea400081ee1c4 */
/*02c0*/ IMAD.WIDE.U32 R6, R17, R2, c[0x0][0x170] ; /* 0x00005c0011067625 */
/* 0x004fcc00078e0002 */
/*02d0*/ ATOMG.E.ADD.STRONG.GPU PT, R7, [R6.64], R4 ; /* 0x00000004060779a8 */
/* 0x000ea400081ee1c4 */
/*02e0*/ IMAD.WIDE.U32 R8, R7, R2, c[0x0][0x170] ; /* 0x00005c0007087625 */
/* 0x004fcc00078e0002 */
/*02f0*/ ATOMG.E.ADD.STRONG.GPU PT, R9, [R8.64], R4 ; /* 0x00000004080979a8 */
/* 0x000ea400081ee1c4 */
/*0300*/ IMAD.WIDE.U32 R10, R9, R2, c[0x0][0x170] ; /* 0x00005c00090a7625 */
/* 0x004fcc00078e0002 */
/*0310*/ ATOMG.E.ADD.STRONG.GPU PT, R11, [R10.64], R4 ; /* 0x000000040a0b79a8 */
/* 0x000ea400081ee1c4 */
/*0320*/ IMAD.WIDE.U32 R12, R11, R2, c[0x0][0x170] ; /* 0x00005c000b0c7625 */
/* 0x004fcc00078e0002 */
/*0330*/ ATOMG.E.ADD.STRONG.GPU PT, R13, [R12.64], R4 ; /* 0x000000040c0d79a8 */
/* 0x000ea400081ee1c4 */
/*0340*/ IMAD.WIDE.U32 R14, R13, R2, c[0x0][0x170] ; /* 0x00005c000d0e7625 */
/* 0x004fcc00078e0002 */
/*0350*/ ATOMG.E.ADD.STRONG.GPU PT, R15, [R14.64], R4 ; /* 0x000000040e0f79a8 */
/* 0x000ea400081ee1c4 */
/*0360*/ IMAD.WIDE.U32 R16, R15, R2, c[0x0][0x170] ; /* 0x00005c000f107625 */
/* 0x004fcc00078e0002 */
/*0370*/ ATOMG.E.ADD.STRONG.GPU PT, R17, [R16.64], R4 ; /* 0x00000004101179a8 */
/* 0x000ea400081ee1c4 */
/*0380*/ IMAD.WIDE.U32 R6, R17, R2, c[0x0][0x170] ; /* 0x00005c0011067625 */
/* 0x004fcc00078e0002 */
/*0390*/ ATOMG.E.ADD.STRONG.GPU PT, R7, [R6.64], R4 ; /* 0x00000004060779a8 */
/* 0x000ea400081ee1c4 */
/*03a0*/ IMAD.WIDE.U32 R8, R7, R2, c[0x0][0x170] ; /* 0x00005c0007087625 */
/* 0x004fcc00078e0002 */
/*03b0*/ ATOMG.E.ADD.STRONG.GPU PT, R9, [R8.64], R4 ; /* 0x00000004080979a8 */
/* 0x000ea400081ee1c4 */
/*03c0*/ IMAD.WIDE.U32 R10, R9, R2, c[0x0][0x170] ; /* 0x00005c00090a7625 */
/* 0x004fcc00078e0002 */
/*03d0*/ ATOMG.E.ADD.STRONG.GPU PT, R11, [R10.64], R4 ; /* 0x000000040a0b79a8 */
/* 0x000ea400081ee1c4 */
/*03e0*/ IMAD.WIDE.U32 R12, R11, R2, c[0x0][0x170] ; /* 0x00005c000b0c7625 */
/* 0x004fcc00078e0002 */
/*03f0*/ ATOMG.E.ADD.STRONG.GPU PT, R13, [R12.64], R4 ; /* 0x000000040c0d79a8 */
/* 0x000ea400081ee1c4 */
/*0400*/ IMAD.WIDE.U32 R14, R13, R2, c[0x0][0x170] ; /* 0x00005c000d0e7625 */
/* 0x004fcc00078e0002 */
/*0410*/ ATOMG.E.ADD.STRONG.GPU PT, R15, [R14.64], R4 ; /* 0x000000040e0f79a8 */
/* 0x000ea400081ee1c4 */
/*0420*/ IMAD.WIDE.U32 R16, R15, R2, c[0x0][0x170] ; /* 0x00005c000f107625 */
/* 0x004fcc00078e0002 */
/*0430*/ ATOMG.E.ADD.STRONG.GPU PT, R17, [R16.64], R4 ; /* 0x00000004101179a8 */
/* 0x000ea200081ee1c4 */
/*0440*/ IADD3 R3, R3, 0x20, RZ ; /* 0x0000002003037810 */
/* 0x000fe20007ffe0ff */
/*0450*/ IMAD.WIDE.U32 R6, R17, R2, c[0x0][0x170] ; /* 0x00005c0011067625 */
/* 0x004fcc00078e0002 */
/*0460*/ ATOMG.E.ADD.STRONG.GPU PT, R7, [R6.64], R4 ; /* 0x00000004060779a8 */
/* 0x000ea200081ee1c4 */
/*0470*/ ISETP.NE.AND P0, PT, R3, 0x1000, PT ; /* 0x000010000300780c */
/* 0x000fe20003f05270 */
/*0480*/ IMAD.WIDE.U32 R8, R7, R2, c[0x0][0x170] ; /* 0x00005c0007087625 */
/* 0x004fcc00078e0002 */
/*0490*/ ATOMG.E.ADD.STRONG.GPU PT, R9, [R8.64], R4 ; /* 0x00000004080979a8 */
/* 0x00016c00081ee1c4 */
/*04a0*/ @P0 BRA 0x60 ; /* 0xfffffbb000000947 */
/* 0x000fea000383ffff */
/*04b0*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e680000002500 */
/*04c0*/ S2R R4, SR_TID.X ; /* 0x0000000000047919 */
/* 0x001e680000002100 */
/*04d0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*04e0*/ IMAD R3, R3, c[0x0][0x0], R4 ; /* 0x0000000003037a24 */
/* 0x002fca00078e0204 */
/*04f0*/ CS2R.32 R11, SR_CLOCKLO ; /* 0x00000000000b7805 */
/* 0x000fe40000005000 */
/*0500*/ IMAD.WIDE R4, R3, R2, c[0x0][0x160] ; /* 0x0000580003047625 */
/* 0x000fe200078e0202 */
/*0510*/ MOV R9, c[0x0][0x174] ; /* 0x00005d0000097a02 */
/* 0x020fc40000000f00 */
/*0520*/ MOV R8, c[0x0][0x170] ; /* 0x00005c0000087a02 */
/* 0x000fe20000000f00 */
/*0530*/ IMAD.WIDE R6, R3.reuse, R2.reuse, c[0x0][0x168] ; /* 0x00005a0003067625 */
/* 0x0c0fe200078e0202 */
/*0540*/ STG.E [R4.64], R0 ; /* 0x0000000004007986 */
/* 0x000fe8000c101904 */
/*0550*/ STG.E [R6.64], R11 ; /* 0x0000000b06007986 */
/* 0x000fe8000c101904 */
/*0560*/ LDG.E R9, [R8.64] ; /* 0x0000000408097981 */
/* 0x000ea2000c1e1900 */
/*0570*/ IMAD.WIDE R2, R3, R2, c[0x0][0x178] ; /* 0x00005e0003027625 */
/* 0x000fca00078e0202 */
/*0580*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x004fe2000c101904 */
/*0590*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*05a0*/ BRA 0x5a0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*05b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0600*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0610*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0620*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0630*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0640*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0650*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0660*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0670*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <stdlib.h>
#include <cuda.h>
#define THREADS_PER_BLOCK 1
#define THREADS_PER_SM 1
#define BLOCKS_NUM 1
#define TOTAL_THREADS (THREADS_PER_BLOCK*BLOCKS_NUM)
#define WARP_SIZE 32
#define REPEAT_TIMES 4096
// GPU error check
#define gpuErrchk(ans) { gpuAssert((ans), __FILE__, __LINE__); }
inline void gpuAssert(cudaError_t code, const char *file, int line, bool abort=true){
if (code != cudaSuccess) {
fprintf(stderr,"GPUassert: %s %s %d\n", cudaGetErrorString(code), file, line);
if (abort) exit(code);
}
}
template <class T>
__global__ void max_flops(uint32_t *startClk, uint32_t *stopClk, T *data1, T *res) {
int gid = blockIdx.x*blockDim.x + threadIdx.x;
//register T s1 = data1[gid];
//register T s2 = data2[gid];
//register T result = 0;
uint32_t index = 0;
int32_t offset = 10;
// synchronize all threads
asm volatile ("bar.sync 0;");
// start timing
uint32_t start = 0;
asm volatile ("mov.u32 %0, %%clock;" : "=r"(start) :: "memory");
//printf("%ld \n", &data1[0]);
for (int j=0 ; j<REPEAT_TIMES ; ++j) {
index = atomicAdd(&data1[index], offset);
//printf("index = %d", index);
}
// synchronize all threads
asm volatile("bar.sync 0;");
// stop timing
uint32_t stop = 0;
asm volatile("mov.u32 %0, %%clock;" : "=r"(stop) :: "memory");
// write time and data back to memory
startClk[gid] = start;
stopClk[gid] = stop;
res[gid] = data1[0];
}
int main(){
uint32_t *startClk = (uint32_t*) malloc(TOTAL_THREADS*sizeof(uint32_t));
uint32_t *stopClk = (uint32_t*) malloc(TOTAL_THREADS*sizeof(uint32_t));
int32_t *data1 = (int32_t*) malloc(REPEAT_TIMES*sizeof(int32_t));
//int32_t *data2 = (int32_t*) malloc(TOTAL_THREADS*sizeof(int32_t));
int32_t *res = (int32_t*) malloc(TOTAL_THREADS*sizeof(int32_t));
uint32_t *startClk_g;
uint32_t *stopClk_g;
int32_t *data1_g;
//int32_t *data2_g;
int32_t *res_g;
int32_t stride = 1;
for (int32_t i=0; i<(REPEAT_TIMES); i++)
data1[i] = (i+stride)%REPEAT_TIMES;
gpuErrchk( cudaMalloc(&startClk_g, TOTAL_THREADS*sizeof(uint32_t)) );
gpuErrchk( cudaMalloc(&stopClk_g, TOTAL_THREADS*sizeof(uint32_t)) );
gpuErrchk( cudaMalloc(&data1_g, REPEAT_TIMES*sizeof(int32_t)) );
//gpuErrchk( cudaMalloc(&data2_g, TOTAL_THREADS*sizeof(int32_t)) );
gpuErrchk( cudaMalloc(&res_g, TOTAL_THREADS*sizeof(int32_t)) );
//printf("address = %ld\n", (long)data1_g);
gpuErrchk( cudaMemcpy(data1_g, data1, REPEAT_TIMES*sizeof(int32_t), cudaMemcpyHostToDevice) );
//gpuErrchk( cudaMemcpy(data2_g, data2, TOTAL_THREADS*sizeof(int32_t), cudaMemcpyHostToDevice) );
max_flops<int32_t><<<BLOCKS_NUM,THREADS_PER_BLOCK>>>(startClk_g, stopClk_g, data1_g, res_g);
gpuErrchk( cudaPeekAtLastError() );
gpuErrchk( cudaMemcpy(startClk, startClk_g, TOTAL_THREADS*sizeof(uint32_t), cudaMemcpyDeviceToHost) );
gpuErrchk( cudaMemcpy(stopClk, stopClk_g, TOTAL_THREADS*sizeof(uint32_t), cudaMemcpyDeviceToHost) );
gpuErrchk( cudaMemcpy(res, res_g, TOTAL_THREADS*sizeof(int32_t), cudaMemcpyDeviceToHost) );
float latency;
latency = ((float)(stopClk[0]-startClk[0]))/((float)(REPEAT_TIMES));
printf("int32 latency = %f (clk)\n", latency);
printf("Total Clk number = %u \n", stopClk[0]-startClk[0]);
return 0;
} | .file "tmpxft_0005f1e6_00000000-6_atomic_add_lat.cudafe1.cpp"
.text
#APP
#NO_APP
.section .text._Z9max_flopsIiEvPjS0_PT_S2_,"axG",@progbits,_Z9max_flopsIiEvPjS0_PT_S2_,comdat
.weak _Z9max_flopsIiEvPjS0_PT_S2_
.type _Z9max_flopsIiEvPjS0_PT_S2_, @function
_Z9max_flopsIiEvPjS0_PT_S2_:
.LFB2136:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
movq %rdi, (%rsp)
movq %rsi, 8(%rsp)
movq %rdx, 16(%rsp)
movq %rcx, 24(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 24(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L5
.L1:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L6
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L5:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9max_flopsIiEvPjS0_PT_S2_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L1
.L6:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2136:
.size _Z9max_flopsIiEvPjS0_PT_S2_, .-_Z9max_flopsIiEvPjS0_PT_S2_
.text
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2063:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2063:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata._Z9gpuAssert9cudaErrorPKcib.str1.1,"aMS",@progbits,1
.LC0:
.string "GPUassert: %s %s %d\n"
.section .text._Z9gpuAssert9cudaErrorPKcib,"axG",@progbits,_Z9gpuAssert9cudaErrorPKcib,comdat
.weak _Z9gpuAssert9cudaErrorPKcib
.type _Z9gpuAssert9cudaErrorPKcib, @function
_Z9gpuAssert9cudaErrorPKcib:
.LFB2057:
.cfi_startproc
endbr64
testl %edi, %edi
jne .L15
ret
.L15:
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $8, %rsp
.cfi_def_cfa_offset 48
movl %edi, %ebx
movq %rsi, %r13
movl %edx, %r12d
movl %ecx, %ebp
call cudaGetErrorString@PLT
movq %rax, %rcx
movl %r12d, %r9d
movq %r13, %r8
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
testb %bpl, %bpl
jne .L16
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L16:
.cfi_restore_state
movl %ebx, %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size _Z9gpuAssert9cudaErrorPKcib, .-_Z9gpuAssert9cudaErrorPKcib
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "/home/ubuntu/Datasets/stackv2/train-structured/purdue-aalp/gpgpu-sim_simulations/master/benchmarks/src/cuda/GPU_Microbenchmark/Atomic_ubench/Atomic_add/Atomic_add_lat/atomic_add_lat.cu"
.section .rodata.str1.1,"aMS",@progbits,1
.LC3:
.string "int32 latency = %f (clk)\n"
.LC4:
.string "Total Clk number = %u \n"
.text
.globl main
.type main, @function
main:
.LFB2060:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $64, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $4, %edi
call malloc@PLT
movq %rax, %rbx
movl $4, %edi
call malloc@PLT
movq %rax, %rbp
movl $16384, %edi
call malloc@PLT
movq %rax, %r12
movl $4, %edi
call malloc@PLT
movq %rax, %r13
movq %r12, %rsi
movl $0, %edx
.L18:
addl $1, %edx
movl %edx, %ecx
sarl $31, %ecx
shrl $20, %ecx
leal (%rdx,%rcx), %eax
andl $4095, %eax
subl %ecx, %eax
movl %eax, (%rsi)
addq $4, %rsi
cmpl $4096, %edx
jne .L18
movq %rsp, %rdi
movl $4, %esi
call cudaMalloc@PLT
movl %eax, %edi
movl $1, %ecx
movl $73, %edx
leaq .LC1(%rip), %r14
movq %r14, %rsi
call _Z9gpuAssert9cudaErrorPKcib
leaq 8(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
movl %eax, %edi
movl $1, %ecx
movl $74, %edx
movq %r14, %rsi
call _Z9gpuAssert9cudaErrorPKcib
leaq 16(%rsp), %rdi
movl $16384, %esi
call cudaMalloc@PLT
movl %eax, %edi
movl $1, %ecx
movl $75, %edx
movq %r14, %rsi
call _Z9gpuAssert9cudaErrorPKcib
leaq 24(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
movl %eax, %edi
movl $1, %ecx
movl $77, %edx
movq %r14, %rsi
call _Z9gpuAssert9cudaErrorPKcib
movl $1, %ecx
movl $16384, %edx
movq %r12, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
movl $1, %ecx
movl $79, %edx
movq %r14, %rsi
call _Z9gpuAssert9cudaErrorPKcib
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L25
.L19:
call cudaPeekAtLastError@PLT
movl %eax, %edi
movl $1, %ecx
movl $83, %edx
leaq .LC1(%rip), %r12
movq %r12, %rsi
call _Z9gpuAssert9cudaErrorPKcib
movl $2, %ecx
movl $4, %edx
movq (%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movl %eax, %edi
movl $1, %ecx
movl $85, %edx
movq %r12, %rsi
call _Z9gpuAssert9cudaErrorPKcib
movl $2, %ecx
movl $4, %edx
movq 8(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
movl %eax, %edi
movl $1, %ecx
movl $86, %edx
movq %r12, %rsi
call _Z9gpuAssert9cudaErrorPKcib
movl $2, %ecx
movl $4, %edx
movq 24(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
movl %eax, %edi
movl $1, %ecx
movl $87, %edx
movq %r12, %rsi
call _Z9gpuAssert9cudaErrorPKcib
movl 0(%rbp), %eax
subl (%rbx), %eax
pxor %xmm0, %xmm0
cvtsi2ssq %rax, %xmm0
mulss .LC2(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl 0(%rbp), %edx
subl (%rbx), %edx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L26
movl $0, %eax
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L25:
.cfi_restore_state
movq 24(%rsp), %rcx
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z9max_flopsIiEvPjS0_PT_S2_
jmp .L19
.L26:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2060:
.size main, .-main
.section .rodata.str1.1
.LC5:
.string "_Z9max_flopsIiEvPjS0_PT_S2_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2088:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z9max_flopsIiEvPjS0_PT_S2_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2088:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC2:
.long 964689920
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <stdlib.h>
#include <cuda.h>
#define THREADS_PER_BLOCK 1
#define THREADS_PER_SM 1
#define BLOCKS_NUM 1
#define TOTAL_THREADS (THREADS_PER_BLOCK*BLOCKS_NUM)
#define WARP_SIZE 32
#define REPEAT_TIMES 4096
// GPU error check
#define gpuErrchk(ans) { gpuAssert((ans), __FILE__, __LINE__); }
inline void gpuAssert(cudaError_t code, const char *file, int line, bool abort=true){
if (code != cudaSuccess) {
fprintf(stderr,"GPUassert: %s %s %d\n", cudaGetErrorString(code), file, line);
if (abort) exit(code);
}
}
template <class T>
__global__ void max_flops(uint32_t *startClk, uint32_t *stopClk, T *data1, T *res) {
int gid = blockIdx.x*blockDim.x + threadIdx.x;
//register T s1 = data1[gid];
//register T s2 = data2[gid];
//register T result = 0;
uint32_t index = 0;
int32_t offset = 10;
// synchronize all threads
asm volatile ("bar.sync 0;");
// start timing
uint32_t start = 0;
asm volatile ("mov.u32 %0, %%clock;" : "=r"(start) :: "memory");
//printf("%ld \n", &data1[0]);
for (int j=0 ; j<REPEAT_TIMES ; ++j) {
index = atomicAdd(&data1[index], offset);
//printf("index = %d", index);
}
// synchronize all threads
asm volatile("bar.sync 0;");
// stop timing
uint32_t stop = 0;
asm volatile("mov.u32 %0, %%clock;" : "=r"(stop) :: "memory");
// write time and data back to memory
startClk[gid] = start;
stopClk[gid] = stop;
res[gid] = data1[0];
}
int main(){
uint32_t *startClk = (uint32_t*) malloc(TOTAL_THREADS*sizeof(uint32_t));
uint32_t *stopClk = (uint32_t*) malloc(TOTAL_THREADS*sizeof(uint32_t));
int32_t *data1 = (int32_t*) malloc(REPEAT_TIMES*sizeof(int32_t));
//int32_t *data2 = (int32_t*) malloc(TOTAL_THREADS*sizeof(int32_t));
int32_t *res = (int32_t*) malloc(TOTAL_THREADS*sizeof(int32_t));
uint32_t *startClk_g;
uint32_t *stopClk_g;
int32_t *data1_g;
//int32_t *data2_g;
int32_t *res_g;
int32_t stride = 1;
for (int32_t i=0; i<(REPEAT_TIMES); i++)
data1[i] = (i+stride)%REPEAT_TIMES;
gpuErrchk( cudaMalloc(&startClk_g, TOTAL_THREADS*sizeof(uint32_t)) );
gpuErrchk( cudaMalloc(&stopClk_g, TOTAL_THREADS*sizeof(uint32_t)) );
gpuErrchk( cudaMalloc(&data1_g, REPEAT_TIMES*sizeof(int32_t)) );
//gpuErrchk( cudaMalloc(&data2_g, TOTAL_THREADS*sizeof(int32_t)) );
gpuErrchk( cudaMalloc(&res_g, TOTAL_THREADS*sizeof(int32_t)) );
//printf("address = %ld\n", (long)data1_g);
gpuErrchk( cudaMemcpy(data1_g, data1, REPEAT_TIMES*sizeof(int32_t), cudaMemcpyHostToDevice) );
//gpuErrchk( cudaMemcpy(data2_g, data2, TOTAL_THREADS*sizeof(int32_t), cudaMemcpyHostToDevice) );
max_flops<int32_t><<<BLOCKS_NUM,THREADS_PER_BLOCK>>>(startClk_g, stopClk_g, data1_g, res_g);
gpuErrchk( cudaPeekAtLastError() );
gpuErrchk( cudaMemcpy(startClk, startClk_g, TOTAL_THREADS*sizeof(uint32_t), cudaMemcpyDeviceToHost) );
gpuErrchk( cudaMemcpy(stopClk, stopClk_g, TOTAL_THREADS*sizeof(uint32_t), cudaMemcpyDeviceToHost) );
gpuErrchk( cudaMemcpy(res, res_g, TOTAL_THREADS*sizeof(int32_t), cudaMemcpyDeviceToHost) );
float latency;
latency = ((float)(stopClk[0]-startClk[0]))/((float)(REPEAT_TIMES));
printf("int32 latency = %f (clk)\n", latency);
printf("Total Clk number = %u \n", stopClk[0]-startClk[0]);
return 0;
} | #include <stdio.h>
#include <stdlib.h>
#include <hip/hip_runtime.h>
#define THREADS_PER_BLOCK 1
#define THREADS_PER_SM 1
#define BLOCKS_NUM 1
#define TOTAL_THREADS (THREADS_PER_BLOCK*BLOCKS_NUM)
#define WARP_SIZE 32
#define REPEAT_TIMES 4096
// GPU error check
#define gpuErrchk(ans) { gpuAssert((ans), __FILE__, __LINE__); }
inline void gpuAssert(hipError_t code, const char *file, int line, bool abort=true){
if (code != hipSuccess) {
fprintf(stderr,"GPUassert: %s %s %d\n", hipGetErrorString(code), file, line);
if (abort) exit(code);
}
}
template <class T>
__global__ void max_flops(uint32_t *startClk, uint32_t *stopClk, T *data1, T *res) {
int gid = blockIdx.x*blockDim.x + threadIdx.x;
//register T s1 = data1[gid];
//register T s2 = data2[gid];
//register T result = 0;
uint32_t index = 0;
int32_t offset = 10;
// synchronize all threads
asm volatile ("bar.sync 0;");
// start timing
uint32_t start = 0;
asm volatile ("mov.u32 %0, %%clock;" : "=r"(start) :: "memory");
//printf("%ld \n", &data1[0]);
for (int j=0 ; j<REPEAT_TIMES ; ++j) {
index = atomicAdd(&data1[index], offset);
//printf("index = %d", index);
}
// synchronize all threads
asm volatile("bar.sync 0;");
// stop timing
uint32_t stop = 0;
asm volatile("mov.u32 %0, %%clock;" : "=r"(stop) :: "memory");
// write time and data back to memory
startClk[gid] = start;
stopClk[gid] = stop;
res[gid] = data1[0];
}
int main(){
uint32_t *startClk = (uint32_t*) malloc(TOTAL_THREADS*sizeof(uint32_t));
uint32_t *stopClk = (uint32_t*) malloc(TOTAL_THREADS*sizeof(uint32_t));
int32_t *data1 = (int32_t*) malloc(REPEAT_TIMES*sizeof(int32_t));
//int32_t *data2 = (int32_t*) malloc(TOTAL_THREADS*sizeof(int32_t));
int32_t *res = (int32_t*) malloc(TOTAL_THREADS*sizeof(int32_t));
uint32_t *startClk_g;
uint32_t *stopClk_g;
int32_t *data1_g;
//int32_t *data2_g;
int32_t *res_g;
int32_t stride = 1;
for (int32_t i=0; i<(REPEAT_TIMES); i++)
data1[i] = (i+stride)%REPEAT_TIMES;
gpuErrchk( hipMalloc(&startClk_g, TOTAL_THREADS*sizeof(uint32_t)) );
gpuErrchk( hipMalloc(&stopClk_g, TOTAL_THREADS*sizeof(uint32_t)) );
gpuErrchk( hipMalloc(&data1_g, REPEAT_TIMES*sizeof(int32_t)) );
//gpuErrchk( cudaMalloc(&data2_g, TOTAL_THREADS*sizeof(int32_t)) );
gpuErrchk( hipMalloc(&res_g, TOTAL_THREADS*sizeof(int32_t)) );
//printf("address = %ld\n", (long)data1_g);
gpuErrchk( hipMemcpy(data1_g, data1, REPEAT_TIMES*sizeof(int32_t), hipMemcpyHostToDevice) );
//gpuErrchk( cudaMemcpy(data2_g, data2, TOTAL_THREADS*sizeof(int32_t), cudaMemcpyHostToDevice) );
max_flops<int32_t><<<BLOCKS_NUM,THREADS_PER_BLOCK>>>(startClk_g, stopClk_g, data1_g, res_g);
gpuErrchk( hipPeekAtLastError() );
gpuErrchk( hipMemcpy(startClk, startClk_g, TOTAL_THREADS*sizeof(uint32_t), hipMemcpyDeviceToHost) );
gpuErrchk( hipMemcpy(stopClk, stopClk_g, TOTAL_THREADS*sizeof(uint32_t), hipMemcpyDeviceToHost) );
gpuErrchk( hipMemcpy(res, res_g, TOTAL_THREADS*sizeof(int32_t), hipMemcpyDeviceToHost) );
float latency;
latency = ((float)(stopClk[0]-startClk[0]))/((float)(REPEAT_TIMES));
printf("int32 latency = %f (clk)\n", latency);
printf("Total Clk number = %u \n", stopClk[0]-startClk[0]);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <stdio.h>
#include <stdlib.h>
#include <hip/hip_runtime.h>
#define THREADS_PER_BLOCK 1
#define THREADS_PER_SM 1
#define BLOCKS_NUM 1
#define TOTAL_THREADS (THREADS_PER_BLOCK*BLOCKS_NUM)
#define WARP_SIZE 32
#define REPEAT_TIMES 4096
// GPU error check
#define gpuErrchk(ans) { gpuAssert((ans), __FILE__, __LINE__); }
inline void gpuAssert(hipError_t code, const char *file, int line, bool abort=true){
if (code != hipSuccess) {
fprintf(stderr,"GPUassert: %s %s %d\n", hipGetErrorString(code), file, line);
if (abort) exit(code);
}
}
template <class T>
__global__ void max_flops(uint32_t *startClk, uint32_t *stopClk, T *data1, T *res) {
int gid = blockIdx.x*blockDim.x + threadIdx.x;
//register T s1 = data1[gid];
//register T s2 = data2[gid];
//register T result = 0;
uint32_t index = 0;
int32_t offset = 10;
// synchronize all threads
asm volatile ("bar.sync 0;");
// start timing
uint32_t start = 0;
asm volatile ("mov.u32 %0, %%clock;" : "=r"(start) :: "memory");
//printf("%ld \n", &data1[0]);
for (int j=0 ; j<REPEAT_TIMES ; ++j) {
index = atomicAdd(&data1[index], offset);
//printf("index = %d", index);
}
// synchronize all threads
asm volatile("bar.sync 0;");
// stop timing
uint32_t stop = 0;
asm volatile("mov.u32 %0, %%clock;" : "=r"(stop) :: "memory");
// write time and data back to memory
startClk[gid] = start;
stopClk[gid] = stop;
res[gid] = data1[0];
}
int main(){
uint32_t *startClk = (uint32_t*) malloc(TOTAL_THREADS*sizeof(uint32_t));
uint32_t *stopClk = (uint32_t*) malloc(TOTAL_THREADS*sizeof(uint32_t));
int32_t *data1 = (int32_t*) malloc(REPEAT_TIMES*sizeof(int32_t));
//int32_t *data2 = (int32_t*) malloc(TOTAL_THREADS*sizeof(int32_t));
int32_t *res = (int32_t*) malloc(TOTAL_THREADS*sizeof(int32_t));
uint32_t *startClk_g;
uint32_t *stopClk_g;
int32_t *data1_g;
//int32_t *data2_g;
int32_t *res_g;
int32_t stride = 1;
for (int32_t i=0; i<(REPEAT_TIMES); i++)
data1[i] = (i+stride)%REPEAT_TIMES;
gpuErrchk( hipMalloc(&startClk_g, TOTAL_THREADS*sizeof(uint32_t)) );
gpuErrchk( hipMalloc(&stopClk_g, TOTAL_THREADS*sizeof(uint32_t)) );
gpuErrchk( hipMalloc(&data1_g, REPEAT_TIMES*sizeof(int32_t)) );
//gpuErrchk( cudaMalloc(&data2_g, TOTAL_THREADS*sizeof(int32_t)) );
gpuErrchk( hipMalloc(&res_g, TOTAL_THREADS*sizeof(int32_t)) );
//printf("address = %ld\n", (long)data1_g);
gpuErrchk( hipMemcpy(data1_g, data1, REPEAT_TIMES*sizeof(int32_t), hipMemcpyHostToDevice) );
//gpuErrchk( cudaMemcpy(data2_g, data2, TOTAL_THREADS*sizeof(int32_t), cudaMemcpyHostToDevice) );
max_flops<int32_t><<<BLOCKS_NUM,THREADS_PER_BLOCK>>>(startClk_g, stopClk_g, data1_g, res_g);
gpuErrchk( hipPeekAtLastError() );
gpuErrchk( hipMemcpy(startClk, startClk_g, TOTAL_THREADS*sizeof(uint32_t), hipMemcpyDeviceToHost) );
gpuErrchk( hipMemcpy(stopClk, stopClk_g, TOTAL_THREADS*sizeof(uint32_t), hipMemcpyDeviceToHost) );
gpuErrchk( hipMemcpy(res, res_g, TOTAL_THREADS*sizeof(int32_t), hipMemcpyDeviceToHost) );
float latency;
latency = ((float)(stopClk[0]-startClk[0]))/((float)(REPEAT_TIMES));
printf("int32 latency = %f (clk)\n", latency);
printf("Total Clk number = %u \n", stopClk[0]-startClk[0]);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.section .text._Z9max_flopsIiEvPjS0_PT_S2_,"axG",@progbits,_Z9max_flopsIiEvPjS0_PT_S2_,comdat
.protected _Z9max_flopsIiEvPjS0_PT_S2_
.globl _Z9max_flopsIiEvPjS0_PT_S2_
.p2align 8
.type _Z9max_flopsIiEvPjS0_PT_S2_,@function
_Z9max_flopsIiEvPjS0_PT_S2_:
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x10
s_load_b32 s5, s[0:1], 0x2c
v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v3, 10
bar.sync 0
mov.u32 s4, %clock
s_movk_i32 s6, 0x1000
s_delay_alu instid0(VALU_DEP_1)
v_mov_b32_e32 v1, v2
.LBB0_1:
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_lshlrev_b64 v[4:5], 2, v[1:2]
s_add_i32 s6, s6, -1
s_cmp_eq_u32 s6, 0
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v4, vcc_lo, s2, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v5, vcc_lo
global_atomic_add_u32 v1, v[4:5], v3, off glc
s_cbranch_scc0 .LBB0_1
s_and_b32 s5, 0xffff, s5
s_load_b128 s[8:11], s[0:1], 0x0
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[1:2], null, s15, s5, v[0:1]
bar.sync 0
mov.u32 s5, %clock
v_dual_mov_b32 v6, s4 :: v_dual_mov_b32 v7, s5
v_mov_b32_e32 v8, 0
s_load_b64 s[0:1], s[0:1], 0x18
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s8, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s9, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s10, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s11, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_store_b32 v[2:3], v6, off
global_store_b32 v[4:5], v7, off
global_load_b32 v2, v8, s[2:3]
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9max_flopsIiEvPjS0_PT_S2_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.section .text._Z9max_flopsIiEvPjS0_PT_S2_,"axG",@progbits,_Z9max_flopsIiEvPjS0_PT_S2_,comdat
.Lfunc_end0:
.size _Z9max_flopsIiEvPjS0_PT_S2_, .Lfunc_end0-_Z9max_flopsIiEvPjS0_PT_S2_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9max_flopsIiEvPjS0_PT_S2_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9max_flopsIiEvPjS0_PT_S2_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <stdio.h>
#include <stdlib.h>
#include <hip/hip_runtime.h>
#define THREADS_PER_BLOCK 1
#define THREADS_PER_SM 1
#define BLOCKS_NUM 1
#define TOTAL_THREADS (THREADS_PER_BLOCK*BLOCKS_NUM)
#define WARP_SIZE 32
#define REPEAT_TIMES 4096
// GPU error check
#define gpuErrchk(ans) { gpuAssert((ans), __FILE__, __LINE__); }
inline void gpuAssert(hipError_t code, const char *file, int line, bool abort=true){
if (code != hipSuccess) {
fprintf(stderr,"GPUassert: %s %s %d\n", hipGetErrorString(code), file, line);
if (abort) exit(code);
}
}
template <class T>
__global__ void max_flops(uint32_t *startClk, uint32_t *stopClk, T *data1, T *res) {
int gid = blockIdx.x*blockDim.x + threadIdx.x;
//register T s1 = data1[gid];
//register T s2 = data2[gid];
//register T result = 0;
uint32_t index = 0;
int32_t offset = 10;
// synchronize all threads
asm volatile ("bar.sync 0;");
// start timing
uint32_t start = 0;
asm volatile ("mov.u32 %0, %%clock;" : "=r"(start) :: "memory");
//printf("%ld \n", &data1[0]);
for (int j=0 ; j<REPEAT_TIMES ; ++j) {
index = atomicAdd(&data1[index], offset);
//printf("index = %d", index);
}
// synchronize all threads
asm volatile("bar.sync 0;");
// stop timing
uint32_t stop = 0;
asm volatile("mov.u32 %0, %%clock;" : "=r"(stop) :: "memory");
// write time and data back to memory
startClk[gid] = start;
stopClk[gid] = stop;
res[gid] = data1[0];
}
int main(){
uint32_t *startClk = (uint32_t*) malloc(TOTAL_THREADS*sizeof(uint32_t));
uint32_t *stopClk = (uint32_t*) malloc(TOTAL_THREADS*sizeof(uint32_t));
int32_t *data1 = (int32_t*) malloc(REPEAT_TIMES*sizeof(int32_t));
//int32_t *data2 = (int32_t*) malloc(TOTAL_THREADS*sizeof(int32_t));
int32_t *res = (int32_t*) malloc(TOTAL_THREADS*sizeof(int32_t));
uint32_t *startClk_g;
uint32_t *stopClk_g;
int32_t *data1_g;
//int32_t *data2_g;
int32_t *res_g;
int32_t stride = 1;
for (int32_t i=0; i<(REPEAT_TIMES); i++)
data1[i] = (i+stride)%REPEAT_TIMES;
gpuErrchk( hipMalloc(&startClk_g, TOTAL_THREADS*sizeof(uint32_t)) );
gpuErrchk( hipMalloc(&stopClk_g, TOTAL_THREADS*sizeof(uint32_t)) );
gpuErrchk( hipMalloc(&data1_g, REPEAT_TIMES*sizeof(int32_t)) );
//gpuErrchk( cudaMalloc(&data2_g, TOTAL_THREADS*sizeof(int32_t)) );
gpuErrchk( hipMalloc(&res_g, TOTAL_THREADS*sizeof(int32_t)) );
//printf("address = %ld\n", (long)data1_g);
gpuErrchk( hipMemcpy(data1_g, data1, REPEAT_TIMES*sizeof(int32_t), hipMemcpyHostToDevice) );
//gpuErrchk( cudaMemcpy(data2_g, data2, TOTAL_THREADS*sizeof(int32_t), cudaMemcpyHostToDevice) );
max_flops<int32_t><<<BLOCKS_NUM,THREADS_PER_BLOCK>>>(startClk_g, stopClk_g, data1_g, res_g);
gpuErrchk( hipPeekAtLastError() );
gpuErrchk( hipMemcpy(startClk, startClk_g, TOTAL_THREADS*sizeof(uint32_t), hipMemcpyDeviceToHost) );
gpuErrchk( hipMemcpy(stopClk, stopClk_g, TOTAL_THREADS*sizeof(uint32_t), hipMemcpyDeviceToHost) );
gpuErrchk( hipMemcpy(res, res_g, TOTAL_THREADS*sizeof(int32_t), hipMemcpyDeviceToHost) );
float latency;
latency = ((float)(stopClk[0]-startClk[0]))/((float)(REPEAT_TIMES));
printf("int32 latency = %f (clk)\n", latency);
printf("Total Clk number = %u \n", stopClk[0]-startClk[0]);
return 0;
} | .text
.file "atomic_add_lat.hip"
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI0_0:
.long 0x39800000 # float 2.44140625E-4
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $144, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $4, %edi
callq malloc
movq %rax, %rbx
movl $4, %edi
callq malloc
movq %rax, %r14
movl $16384, %edi # imm = 0x4000
callq malloc
movq %rax, %r12
movl $4, %edi
callq malloc
movq %rax, %r15
xorl %eax, %eax
.p2align 4, 0x90
.LBB0_1: # =>This Inner Loop Header: Depth=1
leaq 1(%rax), %rcx
movl %ecx, %edx
andl $4095, %edx # imm = 0xFFF
movl %edx, (%r12,%rax,4)
movq %rcx, %rax
cmpq $4096, %rcx # imm = 0x1000
jne .LBB0_1
# %bb.2:
leaq 24(%rsp), %rdi
movl $4, %esi
callq hipMalloc
testl %eax, %eax
jne .LBB0_3
# %bb.5: # %_Z9gpuAssert10hipError_tPKcib.exit
leaq 16(%rsp), %rdi
movl $4, %esi
callq hipMalloc
testl %eax, %eax
jne .LBB0_6
# %bb.7: # %_Z9gpuAssert10hipError_tPKcib.exit17
leaq 8(%rsp), %rdi
movl $16384, %esi # imm = 0x4000
callq hipMalloc
testl %eax, %eax
jne .LBB0_8
# %bb.9: # %_Z9gpuAssert10hipError_tPKcib.exit19
movq %rsp, %rdi
movl $4, %esi
callq hipMalloc
testl %eax, %eax
jne .LBB0_10
# %bb.11: # %_Z9gpuAssert10hipError_tPKcib.exit21
movq 8(%rsp), %rdi
movl $16384, %edx # imm = 0x4000
movq %r12, %rsi
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB0_12
# %bb.13: # %_Z9gpuAssert10hipError_tPKcib.exit23
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB0_15
# %bb.14:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq (%rsp), %rsi
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
movq %rsi, 80(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 80(%rsp), %rax
movq %rax, 136(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z9max_flopsIiEvPjS0_PT_S2_, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB0_15:
callq hipPeekAtLastError
testl %eax, %eax
jne .LBB0_16
# %bb.17: # %_Z9gpuAssert10hipError_tPKcib.exit25
movq 24(%rsp), %rsi
movl $4, %edx
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB0_18
# %bb.19: # %_Z9gpuAssert10hipError_tPKcib.exit27
movq 16(%rsp), %rsi
movl $4, %edx
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB0_20
# %bb.21: # %_Z9gpuAssert10hipError_tPKcib.exit29
movq (%rsp), %rsi
movl $4, %edx
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB0_22
# %bb.23: # %_Z9gpuAssert10hipError_tPKcib.exit31
movl (%r14), %eax
subl (%rbx), %eax
cvtsi2ss %rax, %xmm0
mulss .LCPI0_0(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movl $.L.str.1, %edi
movb $1, %al
callq printf
movl (%r14), %esi
subl (%rbx), %esi
movl $.L.str.2, %edi
xorl %eax, %eax
callq printf
xorl %eax, %eax
addq $144, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB0_3:
.cfi_def_cfa_offset 192
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.3, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $73, %r8d
jmp .LBB0_4
.LBB0_6:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.3, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $74, %r8d
jmp .LBB0_4
.LBB0_8:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.3, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $75, %r8d
jmp .LBB0_4
.LBB0_10:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.3, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $77, %r8d
jmp .LBB0_4
.LBB0_12:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.3, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $79, %r8d
jmp .LBB0_4
.LBB0_16:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.3, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $83, %r8d
jmp .LBB0_4
.LBB0_18:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.3, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $85, %r8d
jmp .LBB0_4
.LBB0_20:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.3, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $86, %r8d
jmp .LBB0_4
.LBB0_22:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.3, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $87, %r8d
.LBB0_4:
xorl %eax, %eax
callq fprintf
movl %ebp, %edi
callq exit
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.section .text._Z24__device_stub__max_flopsIiEvPjS0_PT_S2_,"axG",@progbits,_Z24__device_stub__max_flopsIiEvPjS0_PT_S2_,comdat
.weak _Z24__device_stub__max_flopsIiEvPjS0_PT_S2_ # -- Begin function _Z24__device_stub__max_flopsIiEvPjS0_PT_S2_
.p2align 4, 0x90
.type _Z24__device_stub__max_flopsIiEvPjS0_PT_S2_,@function
_Z24__device_stub__max_flopsIiEvPjS0_PT_S2_: # @_Z24__device_stub__max_flopsIiEvPjS0_PT_S2_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movq %rcx, 48(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rax
movq %rax, 104(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9max_flopsIiEvPjS0_PT_S2_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end1:
.size _Z24__device_stub__max_flopsIiEvPjS0_PT_S2_, .Lfunc_end1-_Z24__device_stub__max_flopsIiEvPjS0_PT_S2_
.cfi_endproc
# -- End function
.text
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9max_flopsIiEvPjS0_PT_S2_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/purdue-aalp/gpgpu-sim_simulations/master/benchmarks/src/cuda/GPU_Microbenchmark/Atomic_ubench/Atomic_add/Atomic_add_lat/atomic_add_lat.hip"
.size .L.str, 196
.type _Z9max_flopsIiEvPjS0_PT_S2_,@object # @_Z9max_flopsIiEvPjS0_PT_S2_
.section .rodata._Z9max_flopsIiEvPjS0_PT_S2_,"aG",@progbits,_Z9max_flopsIiEvPjS0_PT_S2_,comdat
.weak _Z9max_flopsIiEvPjS0_PT_S2_
.p2align 3, 0x0
_Z9max_flopsIiEvPjS0_PT_S2_:
.quad _Z24__device_stub__max_flopsIiEvPjS0_PT_S2_
.size _Z9max_flopsIiEvPjS0_PT_S2_, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "int32 latency = %f (clk)\n"
.size .L.str.1, 26
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Total Clk number = %u \n"
.size .L.str.2, 24
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "GPUassert: %s %s %d\n"
.size .L.str.3, 21
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z9max_flopsIiEvPjS0_PT_S2_"
.size .L__unnamed_1, 28
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__max_flopsIiEvPjS0_PT_S2_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9max_flopsIiEvPjS0_PT_S2_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z9max_flopsIiEvPjS0_PT_S2_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0030*/ CS2R.32 R0, SR_CLOCKLO ; /* 0x0000000000007805 */
/* 0x000fc60000005000 */
/*0040*/ HFMA2.MMA R3, -RZ, RZ, 0, 0 ; /* 0x00000000ff037435 */
/* 0x000fe200000001ff */
/*0050*/ MOV R9, RZ ; /* 0x000000ff00097202 */
/* 0x000fc60000000f00 */
/*0060*/ MOV R2, 0x4 ; /* 0x0000000400027802 */
/* 0x000fe40000000f00 */
/*0070*/ MOV R4, 0xa ; /* 0x0000000a00047802 */
/* 0x001fc60000000f00 */
/*0080*/ IMAD.WIDE.U32 R6, R9, R2, c[0x0][0x170] ; /* 0x00005c0009067625 */
/* 0x020fcc00078e0002 */
/*0090*/ ATOMG.E.ADD.STRONG.GPU PT, R7, [R6.64], R4 ; /* 0x00000004060779a8 */
/* 0x000ea400081ee1c4 */
/*00a0*/ IMAD.WIDE.U32 R8, R7, R2, c[0x0][0x170] ; /* 0x00005c0007087625 */
/* 0x004fcc00078e0002 */
/*00b0*/ ATOMG.E.ADD.STRONG.GPU PT, R9, [R8.64], R4 ; /* 0x00000004080979a8 */
/* 0x000ea400081ee1c4 */
/*00c0*/ IMAD.WIDE.U32 R10, R9, R2, c[0x0][0x170] ; /* 0x00005c00090a7625 */
/* 0x004fcc00078e0002 */
/*00d0*/ ATOMG.E.ADD.STRONG.GPU PT, R11, [R10.64], R4 ; /* 0x000000040a0b79a8 */
/* 0x000ea400081ee1c4 */
/*00e0*/ IMAD.WIDE.U32 R12, R11, R2, c[0x0][0x170] ; /* 0x00005c000b0c7625 */
/* 0x004fcc00078e0002 */
/*00f0*/ ATOMG.E.ADD.STRONG.GPU PT, R13, [R12.64], R4 ; /* 0x000000040c0d79a8 */
/* 0x000ea400081ee1c4 */
/*0100*/ IMAD.WIDE.U32 R14, R13, R2, c[0x0][0x170] ; /* 0x00005c000d0e7625 */
/* 0x004fcc00078e0002 */
/*0110*/ ATOMG.E.ADD.STRONG.GPU PT, R15, [R14.64], R4 ; /* 0x000000040e0f79a8 */
/* 0x000ea400081ee1c4 */
/*0120*/ IMAD.WIDE.U32 R16, R15, R2, c[0x0][0x170] ; /* 0x00005c000f107625 */
/* 0x004fcc00078e0002 */
/*0130*/ ATOMG.E.ADD.STRONG.GPU PT, R17, [R16.64], R4 ; /* 0x00000004101179a8 */
/* 0x000ea400081ee1c4 */
/*0140*/ IMAD.WIDE.U32 R6, R17, R2, c[0x0][0x170] ; /* 0x00005c0011067625 */
/* 0x004fcc00078e0002 */
/*0150*/ ATOMG.E.ADD.STRONG.GPU PT, R7, [R6.64], R4 ; /* 0x00000004060779a8 */
/* 0x000ea400081ee1c4 */
/*0160*/ IMAD.WIDE.U32 R8, R7, R2, c[0x0][0x170] ; /* 0x00005c0007087625 */
/* 0x004fcc00078e0002 */
/*0170*/ ATOMG.E.ADD.STRONG.GPU PT, R9, [R8.64], R4 ; /* 0x00000004080979a8 */
/* 0x000ea400081ee1c4 */
/*0180*/ IMAD.WIDE.U32 R10, R9, R2, c[0x0][0x170] ; /* 0x00005c00090a7625 */
/* 0x004fcc00078e0002 */
/*0190*/ ATOMG.E.ADD.STRONG.GPU PT, R11, [R10.64], R4 ; /* 0x000000040a0b79a8 */
/* 0x000ea400081ee1c4 */
/*01a0*/ IMAD.WIDE.U32 R12, R11, R2, c[0x0][0x170] ; /* 0x00005c000b0c7625 */
/* 0x004fcc00078e0002 */
/*01b0*/ ATOMG.E.ADD.STRONG.GPU PT, R13, [R12.64], R4 ; /* 0x000000040c0d79a8 */
/* 0x000ea400081ee1c4 */
/*01c0*/ IMAD.WIDE.U32 R14, R13, R2, c[0x0][0x170] ; /* 0x00005c000d0e7625 */
/* 0x004fcc00078e0002 */
/*01d0*/ ATOMG.E.ADD.STRONG.GPU PT, R15, [R14.64], R4 ; /* 0x000000040e0f79a8 */
/* 0x000ea400081ee1c4 */
/*01e0*/ IMAD.WIDE.U32 R16, R15, R2, c[0x0][0x170] ; /* 0x00005c000f107625 */
/* 0x004fcc00078e0002 */
/*01f0*/ ATOMG.E.ADD.STRONG.GPU PT, R17, [R16.64], R4 ; /* 0x00000004101179a8 */
/* 0x000ea400081ee1c4 */
/*0200*/ IMAD.WIDE.U32 R6, R17, R2, c[0x0][0x170] ; /* 0x00005c0011067625 */
/* 0x004fcc00078e0002 */
/*0210*/ ATOMG.E.ADD.STRONG.GPU PT, R7, [R6.64], R4 ; /* 0x00000004060779a8 */
/* 0x000ea400081ee1c4 */
/*0220*/ IMAD.WIDE.U32 R8, R7, R2, c[0x0][0x170] ; /* 0x00005c0007087625 */
/* 0x004fcc00078e0002 */
/*0230*/ ATOMG.E.ADD.STRONG.GPU PT, R9, [R8.64], R4 ; /* 0x00000004080979a8 */
/* 0x000ea400081ee1c4 */
/*0240*/ IMAD.WIDE.U32 R10, R9, R2, c[0x0][0x170] ; /* 0x00005c00090a7625 */
/* 0x004fcc00078e0002 */
/*0250*/ ATOMG.E.ADD.STRONG.GPU PT, R11, [R10.64], R4 ; /* 0x000000040a0b79a8 */
/* 0x000ea400081ee1c4 */
/*0260*/ IMAD.WIDE.U32 R12, R11, R2, c[0x0][0x170] ; /* 0x00005c000b0c7625 */
/* 0x004fcc00078e0002 */
/*0270*/ ATOMG.E.ADD.STRONG.GPU PT, R13, [R12.64], R4 ; /* 0x000000040c0d79a8 */
/* 0x000ea400081ee1c4 */
/*0280*/ IMAD.WIDE.U32 R14, R13, R2, c[0x0][0x170] ; /* 0x00005c000d0e7625 */
/* 0x004fcc00078e0002 */
/*0290*/ ATOMG.E.ADD.STRONG.GPU PT, R15, [R14.64], R4 ; /* 0x000000040e0f79a8 */
/* 0x000ea400081ee1c4 */
/*02a0*/ IMAD.WIDE.U32 R16, R15, R2, c[0x0][0x170] ; /* 0x00005c000f107625 */
/* 0x004fcc00078e0002 */
/*02b0*/ ATOMG.E.ADD.STRONG.GPU PT, R17, [R16.64], R4 ; /* 0x00000004101179a8 */
/* 0x000ea400081ee1c4 */
/*02c0*/ IMAD.WIDE.U32 R6, R17, R2, c[0x0][0x170] ; /* 0x00005c0011067625 */
/* 0x004fcc00078e0002 */
/*02d0*/ ATOMG.E.ADD.STRONG.GPU PT, R7, [R6.64], R4 ; /* 0x00000004060779a8 */
/* 0x000ea400081ee1c4 */
/*02e0*/ IMAD.WIDE.U32 R8, R7, R2, c[0x0][0x170] ; /* 0x00005c0007087625 */
/* 0x004fcc00078e0002 */
/*02f0*/ ATOMG.E.ADD.STRONG.GPU PT, R9, [R8.64], R4 ; /* 0x00000004080979a8 */
/* 0x000ea400081ee1c4 */
/*0300*/ IMAD.WIDE.U32 R10, R9, R2, c[0x0][0x170] ; /* 0x00005c00090a7625 */
/* 0x004fcc00078e0002 */
/*0310*/ ATOMG.E.ADD.STRONG.GPU PT, R11, [R10.64], R4 ; /* 0x000000040a0b79a8 */
/* 0x000ea400081ee1c4 */
/*0320*/ IMAD.WIDE.U32 R12, R11, R2, c[0x0][0x170] ; /* 0x00005c000b0c7625 */
/* 0x004fcc00078e0002 */
/*0330*/ ATOMG.E.ADD.STRONG.GPU PT, R13, [R12.64], R4 ; /* 0x000000040c0d79a8 */
/* 0x000ea400081ee1c4 */
/*0340*/ IMAD.WIDE.U32 R14, R13, R2, c[0x0][0x170] ; /* 0x00005c000d0e7625 */
/* 0x004fcc00078e0002 */
/*0350*/ ATOMG.E.ADD.STRONG.GPU PT, R15, [R14.64], R4 ; /* 0x000000040e0f79a8 */
/* 0x000ea400081ee1c4 */
/*0360*/ IMAD.WIDE.U32 R16, R15, R2, c[0x0][0x170] ; /* 0x00005c000f107625 */
/* 0x004fcc00078e0002 */
/*0370*/ ATOMG.E.ADD.STRONG.GPU PT, R17, [R16.64], R4 ; /* 0x00000004101179a8 */
/* 0x000ea400081ee1c4 */
/*0380*/ IMAD.WIDE.U32 R6, R17, R2, c[0x0][0x170] ; /* 0x00005c0011067625 */
/* 0x004fcc00078e0002 */
/*0390*/ ATOMG.E.ADD.STRONG.GPU PT, R7, [R6.64], R4 ; /* 0x00000004060779a8 */
/* 0x000ea400081ee1c4 */
/*03a0*/ IMAD.WIDE.U32 R8, R7, R2, c[0x0][0x170] ; /* 0x00005c0007087625 */
/* 0x004fcc00078e0002 */
/*03b0*/ ATOMG.E.ADD.STRONG.GPU PT, R9, [R8.64], R4 ; /* 0x00000004080979a8 */
/* 0x000ea400081ee1c4 */
/*03c0*/ IMAD.WIDE.U32 R10, R9, R2, c[0x0][0x170] ; /* 0x00005c00090a7625 */
/* 0x004fcc00078e0002 */
/*03d0*/ ATOMG.E.ADD.STRONG.GPU PT, R11, [R10.64], R4 ; /* 0x000000040a0b79a8 */
/* 0x000ea400081ee1c4 */
/*03e0*/ IMAD.WIDE.U32 R12, R11, R2, c[0x0][0x170] ; /* 0x00005c000b0c7625 */
/* 0x004fcc00078e0002 */
/*03f0*/ ATOMG.E.ADD.STRONG.GPU PT, R13, [R12.64], R4 ; /* 0x000000040c0d79a8 */
/* 0x000ea400081ee1c4 */
/*0400*/ IMAD.WIDE.U32 R14, R13, R2, c[0x0][0x170] ; /* 0x00005c000d0e7625 */
/* 0x004fcc00078e0002 */
/*0410*/ ATOMG.E.ADD.STRONG.GPU PT, R15, [R14.64], R4 ; /* 0x000000040e0f79a8 */
/* 0x000ea400081ee1c4 */
/*0420*/ IMAD.WIDE.U32 R16, R15, R2, c[0x0][0x170] ; /* 0x00005c000f107625 */
/* 0x004fcc00078e0002 */
/*0430*/ ATOMG.E.ADD.STRONG.GPU PT, R17, [R16.64], R4 ; /* 0x00000004101179a8 */
/* 0x000ea200081ee1c4 */
/*0440*/ IADD3 R3, R3, 0x20, RZ ; /* 0x0000002003037810 */
/* 0x000fe20007ffe0ff */
/*0450*/ IMAD.WIDE.U32 R6, R17, R2, c[0x0][0x170] ; /* 0x00005c0011067625 */
/* 0x004fcc00078e0002 */
/*0460*/ ATOMG.E.ADD.STRONG.GPU PT, R7, [R6.64], R4 ; /* 0x00000004060779a8 */
/* 0x000ea200081ee1c4 */
/*0470*/ ISETP.NE.AND P0, PT, R3, 0x1000, PT ; /* 0x000010000300780c */
/* 0x000fe20003f05270 */
/*0480*/ IMAD.WIDE.U32 R8, R7, R2, c[0x0][0x170] ; /* 0x00005c0007087625 */
/* 0x004fcc00078e0002 */
/*0490*/ ATOMG.E.ADD.STRONG.GPU PT, R9, [R8.64], R4 ; /* 0x00000004080979a8 */
/* 0x00016c00081ee1c4 */
/*04a0*/ @P0 BRA 0x60 ; /* 0xfffffbb000000947 */
/* 0x000fea000383ffff */
/*04b0*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e680000002500 */
/*04c0*/ S2R R4, SR_TID.X ; /* 0x0000000000047919 */
/* 0x001e680000002100 */
/*04d0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*04e0*/ IMAD R3, R3, c[0x0][0x0], R4 ; /* 0x0000000003037a24 */
/* 0x002fca00078e0204 */
/*04f0*/ CS2R.32 R11, SR_CLOCKLO ; /* 0x00000000000b7805 */
/* 0x000fe40000005000 */
/*0500*/ IMAD.WIDE R4, R3, R2, c[0x0][0x160] ; /* 0x0000580003047625 */
/* 0x000fe200078e0202 */
/*0510*/ MOV R9, c[0x0][0x174] ; /* 0x00005d0000097a02 */
/* 0x020fc40000000f00 */
/*0520*/ MOV R8, c[0x0][0x170] ; /* 0x00005c0000087a02 */
/* 0x000fe20000000f00 */
/*0530*/ IMAD.WIDE R6, R3.reuse, R2.reuse, c[0x0][0x168] ; /* 0x00005a0003067625 */
/* 0x0c0fe200078e0202 */
/*0540*/ STG.E [R4.64], R0 ; /* 0x0000000004007986 */
/* 0x000fe8000c101904 */
/*0550*/ STG.E [R6.64], R11 ; /* 0x0000000b06007986 */
/* 0x000fe8000c101904 */
/*0560*/ LDG.E R9, [R8.64] ; /* 0x0000000408097981 */
/* 0x000ea2000c1e1900 */
/*0570*/ IMAD.WIDE R2, R3, R2, c[0x0][0x178] ; /* 0x00005e0003027625 */
/* 0x000fca00078e0202 */
/*0580*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x004fe2000c101904 */
/*0590*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*05a0*/ BRA 0x5a0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*05b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0600*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0610*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0620*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0630*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0640*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0650*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0660*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0670*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.section .text._Z9max_flopsIiEvPjS0_PT_S2_,"axG",@progbits,_Z9max_flopsIiEvPjS0_PT_S2_,comdat
.protected _Z9max_flopsIiEvPjS0_PT_S2_
.globl _Z9max_flopsIiEvPjS0_PT_S2_
.p2align 8
.type _Z9max_flopsIiEvPjS0_PT_S2_,@function
_Z9max_flopsIiEvPjS0_PT_S2_:
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x10
s_load_b32 s5, s[0:1], 0x2c
v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v3, 10
bar.sync 0
mov.u32 s4, %clock
s_movk_i32 s6, 0x1000
s_delay_alu instid0(VALU_DEP_1)
v_mov_b32_e32 v1, v2
.LBB0_1:
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_lshlrev_b64 v[4:5], 2, v[1:2]
s_add_i32 s6, s6, -1
s_cmp_eq_u32 s6, 0
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v4, vcc_lo, s2, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v5, vcc_lo
global_atomic_add_u32 v1, v[4:5], v3, off glc
s_cbranch_scc0 .LBB0_1
s_and_b32 s5, 0xffff, s5
s_load_b128 s[8:11], s[0:1], 0x0
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[1:2], null, s15, s5, v[0:1]
bar.sync 0
mov.u32 s5, %clock
v_dual_mov_b32 v6, s4 :: v_dual_mov_b32 v7, s5
v_mov_b32_e32 v8, 0
s_load_b64 s[0:1], s[0:1], 0x18
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s8, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s9, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s10, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s11, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_store_b32 v[2:3], v6, off
global_store_b32 v[4:5], v7, off
global_load_b32 v2, v8, s[2:3]
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9max_flopsIiEvPjS0_PT_S2_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.section .text._Z9max_flopsIiEvPjS0_PT_S2_,"axG",@progbits,_Z9max_flopsIiEvPjS0_PT_S2_,comdat
.Lfunc_end0:
.size _Z9max_flopsIiEvPjS0_PT_S2_, .Lfunc_end0-_Z9max_flopsIiEvPjS0_PT_S2_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9max_flopsIiEvPjS0_PT_S2_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9max_flopsIiEvPjS0_PT_S2_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0005f1e6_00000000-6_atomic_add_lat.cudafe1.cpp"
.text
#APP
#NO_APP
.section .text._Z9max_flopsIiEvPjS0_PT_S2_,"axG",@progbits,_Z9max_flopsIiEvPjS0_PT_S2_,comdat
.weak _Z9max_flopsIiEvPjS0_PT_S2_
.type _Z9max_flopsIiEvPjS0_PT_S2_, @function
_Z9max_flopsIiEvPjS0_PT_S2_:
.LFB2136:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
movq %rdi, (%rsp)
movq %rsi, 8(%rsp)
movq %rdx, 16(%rsp)
movq %rcx, 24(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 24(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L5
.L1:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L6
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L5:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9max_flopsIiEvPjS0_PT_S2_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L1
.L6:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2136:
.size _Z9max_flopsIiEvPjS0_PT_S2_, .-_Z9max_flopsIiEvPjS0_PT_S2_
.text
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2063:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2063:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata._Z9gpuAssert9cudaErrorPKcib.str1.1,"aMS",@progbits,1
.LC0:
.string "GPUassert: %s %s %d\n"
.section .text._Z9gpuAssert9cudaErrorPKcib,"axG",@progbits,_Z9gpuAssert9cudaErrorPKcib,comdat
.weak _Z9gpuAssert9cudaErrorPKcib
.type _Z9gpuAssert9cudaErrorPKcib, @function
_Z9gpuAssert9cudaErrorPKcib:
.LFB2057:
.cfi_startproc
endbr64
testl %edi, %edi
jne .L15
ret
.L15:
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $8, %rsp
.cfi_def_cfa_offset 48
movl %edi, %ebx
movq %rsi, %r13
movl %edx, %r12d
movl %ecx, %ebp
call cudaGetErrorString@PLT
movq %rax, %rcx
movl %r12d, %r9d
movq %r13, %r8
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
testb %bpl, %bpl
jne .L16
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L16:
.cfi_restore_state
movl %ebx, %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size _Z9gpuAssert9cudaErrorPKcib, .-_Z9gpuAssert9cudaErrorPKcib
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "/home/ubuntu/Datasets/stackv2/train-structured/purdue-aalp/gpgpu-sim_simulations/master/benchmarks/src/cuda/GPU_Microbenchmark/Atomic_ubench/Atomic_add/Atomic_add_lat/atomic_add_lat.cu"
.section .rodata.str1.1,"aMS",@progbits,1
.LC3:
.string "int32 latency = %f (clk)\n"
.LC4:
.string "Total Clk number = %u \n"
.text
.globl main
.type main, @function
main:
.LFB2060:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $64, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $4, %edi
call malloc@PLT
movq %rax, %rbx
movl $4, %edi
call malloc@PLT
movq %rax, %rbp
movl $16384, %edi
call malloc@PLT
movq %rax, %r12
movl $4, %edi
call malloc@PLT
movq %rax, %r13
movq %r12, %rsi
movl $0, %edx
.L18:
addl $1, %edx
movl %edx, %ecx
sarl $31, %ecx
shrl $20, %ecx
leal (%rdx,%rcx), %eax
andl $4095, %eax
subl %ecx, %eax
movl %eax, (%rsi)
addq $4, %rsi
cmpl $4096, %edx
jne .L18
movq %rsp, %rdi
movl $4, %esi
call cudaMalloc@PLT
movl %eax, %edi
movl $1, %ecx
movl $73, %edx
leaq .LC1(%rip), %r14
movq %r14, %rsi
call _Z9gpuAssert9cudaErrorPKcib
leaq 8(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
movl %eax, %edi
movl $1, %ecx
movl $74, %edx
movq %r14, %rsi
call _Z9gpuAssert9cudaErrorPKcib
leaq 16(%rsp), %rdi
movl $16384, %esi
call cudaMalloc@PLT
movl %eax, %edi
movl $1, %ecx
movl $75, %edx
movq %r14, %rsi
call _Z9gpuAssert9cudaErrorPKcib
leaq 24(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
movl %eax, %edi
movl $1, %ecx
movl $77, %edx
movq %r14, %rsi
call _Z9gpuAssert9cudaErrorPKcib
movl $1, %ecx
movl $16384, %edx
movq %r12, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
movl $1, %ecx
movl $79, %edx
movq %r14, %rsi
call _Z9gpuAssert9cudaErrorPKcib
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L25
.L19:
call cudaPeekAtLastError@PLT
movl %eax, %edi
movl $1, %ecx
movl $83, %edx
leaq .LC1(%rip), %r12
movq %r12, %rsi
call _Z9gpuAssert9cudaErrorPKcib
movl $2, %ecx
movl $4, %edx
movq (%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movl %eax, %edi
movl $1, %ecx
movl $85, %edx
movq %r12, %rsi
call _Z9gpuAssert9cudaErrorPKcib
movl $2, %ecx
movl $4, %edx
movq 8(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
movl %eax, %edi
movl $1, %ecx
movl $86, %edx
movq %r12, %rsi
call _Z9gpuAssert9cudaErrorPKcib
movl $2, %ecx
movl $4, %edx
movq 24(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
movl %eax, %edi
movl $1, %ecx
movl $87, %edx
movq %r12, %rsi
call _Z9gpuAssert9cudaErrorPKcib
movl 0(%rbp), %eax
subl (%rbx), %eax
pxor %xmm0, %xmm0
cvtsi2ssq %rax, %xmm0
mulss .LC2(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl 0(%rbp), %edx
subl (%rbx), %edx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L26
movl $0, %eax
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L25:
.cfi_restore_state
movq 24(%rsp), %rcx
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z9max_flopsIiEvPjS0_PT_S2_
jmp .L19
.L26:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2060:
.size main, .-main
.section .rodata.str1.1
.LC5:
.string "_Z9max_flopsIiEvPjS0_PT_S2_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2088:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z9max_flopsIiEvPjS0_PT_S2_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2088:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC2:
.long 964689920
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "atomic_add_lat.hip"
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI0_0:
.long 0x39800000 # float 2.44140625E-4
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $144, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $4, %edi
callq malloc
movq %rax, %rbx
movl $4, %edi
callq malloc
movq %rax, %r14
movl $16384, %edi # imm = 0x4000
callq malloc
movq %rax, %r12
movl $4, %edi
callq malloc
movq %rax, %r15
xorl %eax, %eax
.p2align 4, 0x90
.LBB0_1: # =>This Inner Loop Header: Depth=1
leaq 1(%rax), %rcx
movl %ecx, %edx
andl $4095, %edx # imm = 0xFFF
movl %edx, (%r12,%rax,4)
movq %rcx, %rax
cmpq $4096, %rcx # imm = 0x1000
jne .LBB0_1
# %bb.2:
leaq 24(%rsp), %rdi
movl $4, %esi
callq hipMalloc
testl %eax, %eax
jne .LBB0_3
# %bb.5: # %_Z9gpuAssert10hipError_tPKcib.exit
leaq 16(%rsp), %rdi
movl $4, %esi
callq hipMalloc
testl %eax, %eax
jne .LBB0_6
# %bb.7: # %_Z9gpuAssert10hipError_tPKcib.exit17
leaq 8(%rsp), %rdi
movl $16384, %esi # imm = 0x4000
callq hipMalloc
testl %eax, %eax
jne .LBB0_8
# %bb.9: # %_Z9gpuAssert10hipError_tPKcib.exit19
movq %rsp, %rdi
movl $4, %esi
callq hipMalloc
testl %eax, %eax
jne .LBB0_10
# %bb.11: # %_Z9gpuAssert10hipError_tPKcib.exit21
movq 8(%rsp), %rdi
movl $16384, %edx # imm = 0x4000
movq %r12, %rsi
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB0_12
# %bb.13: # %_Z9gpuAssert10hipError_tPKcib.exit23
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB0_15
# %bb.14:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq (%rsp), %rsi
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
movq %rsi, 80(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 80(%rsp), %rax
movq %rax, 136(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z9max_flopsIiEvPjS0_PT_S2_, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB0_15:
callq hipPeekAtLastError
testl %eax, %eax
jne .LBB0_16
# %bb.17: # %_Z9gpuAssert10hipError_tPKcib.exit25
movq 24(%rsp), %rsi
movl $4, %edx
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB0_18
# %bb.19: # %_Z9gpuAssert10hipError_tPKcib.exit27
movq 16(%rsp), %rsi
movl $4, %edx
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB0_20
# %bb.21: # %_Z9gpuAssert10hipError_tPKcib.exit29
movq (%rsp), %rsi
movl $4, %edx
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB0_22
# %bb.23: # %_Z9gpuAssert10hipError_tPKcib.exit31
movl (%r14), %eax
subl (%rbx), %eax
cvtsi2ss %rax, %xmm0
mulss .LCPI0_0(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movl $.L.str.1, %edi
movb $1, %al
callq printf
movl (%r14), %esi
subl (%rbx), %esi
movl $.L.str.2, %edi
xorl %eax, %eax
callq printf
xorl %eax, %eax
addq $144, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB0_3:
.cfi_def_cfa_offset 192
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.3, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $73, %r8d
jmp .LBB0_4
.LBB0_6:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.3, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $74, %r8d
jmp .LBB0_4
.LBB0_8:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.3, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $75, %r8d
jmp .LBB0_4
.LBB0_10:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.3, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $77, %r8d
jmp .LBB0_4
.LBB0_12:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.3, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $79, %r8d
jmp .LBB0_4
.LBB0_16:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.3, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $83, %r8d
jmp .LBB0_4
.LBB0_18:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.3, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $85, %r8d
jmp .LBB0_4
.LBB0_20:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.3, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $86, %r8d
jmp .LBB0_4
.LBB0_22:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.3, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $87, %r8d
.LBB0_4:
xorl %eax, %eax
callq fprintf
movl %ebp, %edi
callq exit
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.section .text._Z24__device_stub__max_flopsIiEvPjS0_PT_S2_,"axG",@progbits,_Z24__device_stub__max_flopsIiEvPjS0_PT_S2_,comdat
.weak _Z24__device_stub__max_flopsIiEvPjS0_PT_S2_ # -- Begin function _Z24__device_stub__max_flopsIiEvPjS0_PT_S2_
.p2align 4, 0x90
.type _Z24__device_stub__max_flopsIiEvPjS0_PT_S2_,@function
_Z24__device_stub__max_flopsIiEvPjS0_PT_S2_: # @_Z24__device_stub__max_flopsIiEvPjS0_PT_S2_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movq %rcx, 48(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rax
movq %rax, 104(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9max_flopsIiEvPjS0_PT_S2_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end1:
.size _Z24__device_stub__max_flopsIiEvPjS0_PT_S2_, .Lfunc_end1-_Z24__device_stub__max_flopsIiEvPjS0_PT_S2_
.cfi_endproc
# -- End function
.text
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9max_flopsIiEvPjS0_PT_S2_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/purdue-aalp/gpgpu-sim_simulations/master/benchmarks/src/cuda/GPU_Microbenchmark/Atomic_ubench/Atomic_add/Atomic_add_lat/atomic_add_lat.hip"
.size .L.str, 196
.type _Z9max_flopsIiEvPjS0_PT_S2_,@object # @_Z9max_flopsIiEvPjS0_PT_S2_
.section .rodata._Z9max_flopsIiEvPjS0_PT_S2_,"aG",@progbits,_Z9max_flopsIiEvPjS0_PT_S2_,comdat
.weak _Z9max_flopsIiEvPjS0_PT_S2_
.p2align 3, 0x0
_Z9max_flopsIiEvPjS0_PT_S2_:
.quad _Z24__device_stub__max_flopsIiEvPjS0_PT_S2_
.size _Z9max_flopsIiEvPjS0_PT_S2_, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "int32 latency = %f (clk)\n"
.size .L.str.1, 26
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Total Clk number = %u \n"
.size .L.str.2, 24
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "GPUassert: %s %s %d\n"
.size .L.str.3, 21
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z9max_flopsIiEvPjS0_PT_S2_"
.size .L__unnamed_1, 28
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__max_flopsIiEvPjS0_PT_S2_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9max_flopsIiEvPjS0_PT_S2_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void vectorAdd(int* a, int* b, int* c, int n) {
// Calculate global thread ID (tid)
int tid = (blockIdx.x * blockDim.x) + threadIdx.x;
// Vector boundary guard
if (tid < n) {
// Each thread adds a single element
c[tid] = a[tid] + b[tid];
}
} | code for sm_80
Function : _Z9vectorAddPiS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R6, R6, c[0x0][0x0], R3 ; /* 0x0000000006067a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x178], PT ; /* 0x00005e0006007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R4, R6, R7, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x000fc800078e0207 */
/*0090*/ IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x0c0fe400078e0207 */
/*00a0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fe200078e0207 */
/*00d0*/ IADD3 R9, R4, R3, RZ ; /* 0x0000000304097210 */
/* 0x004fca0007ffe0ff */
/*00e0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void vectorAdd(int* a, int* b, int* c, int n) {
// Calculate global thread ID (tid)
int tid = (blockIdx.x * blockDim.x) + threadIdx.x;
// Vector boundary guard
if (tid < n) {
// Each thread adds a single element
c[tid] = a[tid] + b[tid];
}
} | .file "tmpxft_00084049_00000000-6_vectorAdd.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z33__device_stub__Z9vectorAddPiS_S_iPiS_S_i
.type _Z33__device_stub__Z9vectorAddPiS_S_iPiS_S_i, @function
_Z33__device_stub__Z9vectorAddPiS_S_iPiS_S_i:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9vectorAddPiS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z33__device_stub__Z9vectorAddPiS_S_iPiS_S_i, .-_Z33__device_stub__Z9vectorAddPiS_S_iPiS_S_i
.globl _Z9vectorAddPiS_S_i
.type _Z9vectorAddPiS_S_i, @function
_Z9vectorAddPiS_S_i:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z9vectorAddPiS_S_iPiS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z9vectorAddPiS_S_i, .-_Z9vectorAddPiS_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z9vectorAddPiS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z9vectorAddPiS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void vectorAdd(int* a, int* b, int* c, int n) {
// Calculate global thread ID (tid)
int tid = (blockIdx.x * blockDim.x) + threadIdx.x;
// Vector boundary guard
if (tid < n) {
// Each thread adds a single element
c[tid] = a[tid] + b[tid];
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void vectorAdd(int* a, int* b, int* c, int n) {
// Calculate global thread ID (tid)
int tid = (blockIdx.x * blockDim.x) + threadIdx.x;
// Vector boundary guard
if (tid < n) {
// Each thread adds a single element
c[tid] = a[tid] + b[tid];
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void vectorAdd(int* a, int* b, int* c, int n) {
// Calculate global thread ID (tid)
int tid = (blockIdx.x * blockDim.x) + threadIdx.x;
// Vector boundary guard
if (tid < n) {
// Each thread adds a single element
c[tid] = a[tid] + b[tid];
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9vectorAddPiS_S_i
.globl _Z9vectorAddPiS_S_i
.p2align 8
.type _Z9vectorAddPiS_S_i,@function
_Z9vectorAddPiS_S_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v2, v3, v2
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9vectorAddPiS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9vectorAddPiS_S_i, .Lfunc_end0-_Z9vectorAddPiS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9vectorAddPiS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9vectorAddPiS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void vectorAdd(int* a, int* b, int* c, int n) {
// Calculate global thread ID (tid)
int tid = (blockIdx.x * blockDim.x) + threadIdx.x;
// Vector boundary guard
if (tid < n) {
// Each thread adds a single element
c[tid] = a[tid] + b[tid];
}
} | .text
.file "vectorAdd.hip"
.globl _Z24__device_stub__vectorAddPiS_S_i # -- Begin function _Z24__device_stub__vectorAddPiS_S_i
.p2align 4, 0x90
.type _Z24__device_stub__vectorAddPiS_S_i,@function
_Z24__device_stub__vectorAddPiS_S_i: # @_Z24__device_stub__vectorAddPiS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9vectorAddPiS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z24__device_stub__vectorAddPiS_S_i, .Lfunc_end0-_Z24__device_stub__vectorAddPiS_S_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9vectorAddPiS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9vectorAddPiS_S_i,@object # @_Z9vectorAddPiS_S_i
.section .rodata,"a",@progbits
.globl _Z9vectorAddPiS_S_i
.p2align 3, 0x0
_Z9vectorAddPiS_S_i:
.quad _Z24__device_stub__vectorAddPiS_S_i
.size _Z9vectorAddPiS_S_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z9vectorAddPiS_S_i"
.size .L__unnamed_1, 20
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__vectorAddPiS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9vectorAddPiS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z9vectorAddPiS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R6, R6, c[0x0][0x0], R3 ; /* 0x0000000006067a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x178], PT ; /* 0x00005e0006007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R4, R6, R7, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x000fc800078e0207 */
/*0090*/ IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x0c0fe400078e0207 */
/*00a0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fe200078e0207 */
/*00d0*/ IADD3 R9, R4, R3, RZ ; /* 0x0000000304097210 */
/* 0x004fca0007ffe0ff */
/*00e0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9vectorAddPiS_S_i
.globl _Z9vectorAddPiS_S_i
.p2align 8
.type _Z9vectorAddPiS_S_i,@function
_Z9vectorAddPiS_S_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v2, v3, v2
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9vectorAddPiS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9vectorAddPiS_S_i, .Lfunc_end0-_Z9vectorAddPiS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9vectorAddPiS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9vectorAddPiS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00084049_00000000-6_vectorAdd.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z33__device_stub__Z9vectorAddPiS_S_iPiS_S_i
.type _Z33__device_stub__Z9vectorAddPiS_S_iPiS_S_i, @function
_Z33__device_stub__Z9vectorAddPiS_S_iPiS_S_i:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9vectorAddPiS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z33__device_stub__Z9vectorAddPiS_S_iPiS_S_i, .-_Z33__device_stub__Z9vectorAddPiS_S_iPiS_S_i
.globl _Z9vectorAddPiS_S_i
.type _Z9vectorAddPiS_S_i, @function
_Z9vectorAddPiS_S_i:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z9vectorAddPiS_S_iPiS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z9vectorAddPiS_S_i, .-_Z9vectorAddPiS_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z9vectorAddPiS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z9vectorAddPiS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "vectorAdd.hip"
.globl _Z24__device_stub__vectorAddPiS_S_i # -- Begin function _Z24__device_stub__vectorAddPiS_S_i
.p2align 4, 0x90
.type _Z24__device_stub__vectorAddPiS_S_i,@function
_Z24__device_stub__vectorAddPiS_S_i: # @_Z24__device_stub__vectorAddPiS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9vectorAddPiS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z24__device_stub__vectorAddPiS_S_i, .Lfunc_end0-_Z24__device_stub__vectorAddPiS_S_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9vectorAddPiS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9vectorAddPiS_S_i,@object # @_Z9vectorAddPiS_S_i
.section .rodata,"a",@progbits
.globl _Z9vectorAddPiS_S_i
.p2align 3, 0x0
_Z9vectorAddPiS_S_i:
.quad _Z24__device_stub__vectorAddPiS_S_i
.size _Z9vectorAddPiS_S_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z9vectorAddPiS_S_i"
.size .L__unnamed_1, 20
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__vectorAddPiS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9vectorAddPiS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | /*
Name: Paul Talaga
Date: Dec 5, 2017
Desc: Program to add two arrays using the GPU
It uses multiple threads and multiple blocks, so this is
as fast it can go.
To compile this, do: nvcc add-blockthreads.cu
*/
#include <iostream>
using namespace std;
#define numThreads 32 // upper limit of 1024
#define numBlocks 1000
// CUDA kernel function to add to arrays element by element
// This isn't a great demonstration because there isn't much
// work for this function to do, so you'll likely not see
// a big speedup over the CPU.
__global__
void add(int size, int* x, int* y, int* z){
//threadIdx.x
//blockIdx.x
int index = blockIdx.x * blockDim.x + threadIdx.x;
int stride = blockDim.x * gridDim.x; // gridDim is numThreads
for(int i = index; i < size; i+= stride){
z[i] = x[i] + y[i];
}
}
int main(void){
// Size of the arrays we'll be adding
const unsigned N = 10000000;
cout << "Size: " << N*3*sizeof(int) / 1024 / 1024 << " MB" << endl;
// To used unified memory (CUDA takes care of data movement)
// all memory must be allocated via the cudaMallocManaged call below.
int* x;
int* y;
int* z;
cudaMallocManaged(&x, N * sizeof(int));
cudaMallocManaged(&y, N * sizeof(int));
cudaMallocManaged(&z, N * sizeof(int));
// Fill the arrays with numbers
for(int i = 0; i < N; i++){
x[i] = i;
y[i] = 2 * i;
}
// Call the add function, with 1 block, and 1 thread
add<<<numBlocks,numThreads>>>(N, x, y, z);
// Wait until the device is done before proceeding, otherwise we'd be
// accessing x, y, and z in the loop below before the add function completes
// on the device.
cudaDeviceSynchronize();
// Check to see if the math is correct
int errors = 0;
for(int i = 0; i < N; i++){
if(z[i] != x[i] + y[i]){
cout << i << " did not add correctly!" << endl;
errors++;
}
}
if(!errors)cout << "All good!" << endl;
return 0;
} | code for sm_80
Function : _Z3addiPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e280000002500 */
/*0020*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R3, R3, c[0x0][0x0], R0 ; /* 0x0000000003037a24 */
/* 0x001fca00078e0200 */
/*0040*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x160], PT ; /* 0x0000580003007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ MOV R0, c[0x0][0x0] ; /* 0x0000000000007a02 */
/* 0x000fe20000000f00 */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0080*/ BSSY B0, 0x340 ; /* 0x000002b000007945 */
/* 0x000fe60003800000 */
/*0090*/ IMAD R0, R0, c[0x0][0xc], RZ ; /* 0x0000030000007a24 */
/* 0x000fc800078e02ff */
/*00a0*/ I2F.U32.RP R6, R0 ; /* 0x0000000000067306 */
/* 0x000e220000209000 */
/*00b0*/ IMAD.MOV R9, RZ, RZ, -R0 ; /* 0x000000ffff097224 */
/* 0x000fe200078e0a00 */
/*00c0*/ IADD3 R2, R0.reuse, R3, RZ ; /* 0x0000000300027210 */
/* 0x040fe40007ffe0ff */
/*00d0*/ ISETP.NE.U32.AND P2, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe40003f45070 */
/*00e0*/ LOP3.LUT R7, RZ, R2, RZ, 0x33, !PT ; /* 0x00000002ff077212 */
/* 0x000fc800078e33ff */
/*00f0*/ IADD3 R7, R7, c[0x0][0x160], R0 ; /* 0x0000580007077a10 */
/* 0x000fe20007ffe000 */
/*0100*/ MUFU.RCP R6, R6 ; /* 0x0000000600067308 */
/* 0x001e240000001000 */
/*0110*/ IADD3 R4, R6, 0xffffffe, RZ ; /* 0x0ffffffe06047810 */
/* 0x001fcc0007ffe0ff */
/*0120*/ F2I.FTZ.U32.TRUNC.NTZ R5, R4 ; /* 0x0000000400057305 */
/* 0x000064000021f000 */
/*0130*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x001fe400078e00ff */
/*0140*/ IMAD R9, R9, R5, RZ ; /* 0x0000000509097224 */
/* 0x002fc800078e02ff */
/*0150*/ IMAD.HI.U32 R2, R5, R9, R4 ; /* 0x0000000905027227 */
/* 0x000fcc00078e0004 */
/*0160*/ IMAD.HI.U32 R2, R2, R7, RZ ; /* 0x0000000702027227 */
/* 0x000fca00078e00ff */
/*0170*/ IADD3 R4, -R2, RZ, RZ ; /* 0x000000ff02047210 */
/* 0x000fca0007ffe1ff */
/*0180*/ IMAD R7, R0, R4, R7 ; /* 0x0000000400077224 */
/* 0x000fca00078e0207 */
/*0190*/ ISETP.GE.U32.AND P0, PT, R7, R0, PT ; /* 0x000000000700720c */
/* 0x000fda0003f06070 */
/*01a0*/ @P0 IADD3 R7, -R0, R7, RZ ; /* 0x0000000700070210 */
/* 0x000fe40007ffe1ff */
/*01b0*/ @P0 IADD3 R2, R2, 0x1, RZ ; /* 0x0000000102020810 */
/* 0x000fe40007ffe0ff */
/*01c0*/ ISETP.GE.U32.AND P1, PT, R7, R0, PT ; /* 0x000000000700720c */
/* 0x000fda0003f26070 */
/*01d0*/ @P1 IADD3 R2, R2, 0x1, RZ ; /* 0x0000000102021810 */
/* 0x000fe40007ffe0ff */
/*01e0*/ @!P2 LOP3.LUT R2, RZ, R0, RZ, 0x33, !PT ; /* 0x00000000ff02a212 */
/* 0x000fc800078e33ff */
/*01f0*/ IADD3 R4, R2.reuse, 0x1, RZ ; /* 0x0000000102047810 */
/* 0x040fe40007ffe0ff */
/*0200*/ ISETP.GE.U32.AND P1, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fe40003f26070 */
/*0210*/ LOP3.LUT P0, R4, R4, 0x3, RZ, 0xc0, !PT ; /* 0x0000000304047812 */
/* 0x000fda000780c0ff */
/*0220*/ @!P0 BRA 0x330 ; /* 0x0000010000008947 */
/* 0x000fea0003800000 */
/*0230*/ IMAD.MOV.U32 R8, RZ, RZ, 0x4 ; /* 0x00000004ff087424 */
/* 0x000fe200078e00ff */
/*0240*/ MOV R2, R4 ; /* 0x0000000400027202 */
/* 0x000fc60000000f00 */
/*0250*/ IMAD.WIDE R4, R3, R8, c[0x0][0x178] ; /* 0x00005e0003047625 */
/* 0x000fc800078e0208 */
/*0260*/ IMAD.WIDE R6, R3, R8, c[0x0][0x170] ; /* 0x00005c0003067625 */
/* 0x000fc800078e0208 */
/*0270*/ IMAD.WIDE R8, R3, R8, c[0x0][0x168] ; /* 0x00005a0003087625 */
/* 0x000fc800078e0208 */
/*0280*/ LDG.E R10, [R6.64] ; /* 0x00000004060a7981 */
/* 0x0000a8000c1e1900 */
/*0290*/ LDG.E R11, [R8.64] ; /* 0x00000004080b7981 */
/* 0x0002a2000c1e1900 */
/*02a0*/ IADD3 R2, R2, -0x1, RZ ; /* 0xffffffff02027810 */
/* 0x000fe20007ffe0ff */
/*02b0*/ IMAD.IADD R3, R0, 0x1, R3 ; /* 0x0000000100037824 */
/* 0x000fc600078e0203 */
/*02c0*/ ISETP.NE.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fe20003f05270 */
/*02d0*/ IMAD.WIDE R6, R0, 0x4, R6 ; /* 0x0000000400067825 */
/* 0x001fc800078e0206 */
/*02e0*/ IMAD.WIDE R8, R0, 0x4, R8 ; /* 0x0000000400087825 */
/* 0x002fe200078e0208 */
/*02f0*/ IADD3 R11, R10, R11, RZ ; /* 0x0000000b0a0b7210 */
/* 0x004fca0007ffe0ff */
/*0300*/ STG.E [R4.64], R11 ; /* 0x0000000b04007986 */
/* 0x0001e4000c101904 */
/*0310*/ IMAD.WIDE R4, R0, 0x4, R4 ; /* 0x0000000400047825 */
/* 0x001fe200078e0204 */
/*0320*/ @P0 BRA 0x280 ; /* 0xffffff5000000947 */
/* 0x000fea000383ffff */
/*0330*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0340*/ @!P1 EXIT ; /* 0x000000000000994d */
/* 0x000fea0003800000 */
/*0350*/ HFMA2.MMA R8, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff087435 */
/* 0x000fd400000001ff */
/*0360*/ IMAD.WIDE R6, R3, R8, c[0x0][0x170] ; /* 0x00005c0003067625 */
/* 0x000fc800078e0208 */
/*0370*/ IMAD.WIDE R4, R3.reuse, R8.reuse, c[0x0][0x168] ; /* 0x00005a0003047625 */
/* 0x0c0fe200078e0208 */
/*0380*/ LDG.E R2, [R6.64] ; /* 0x0000000406027981 */
/* 0x000ea8000c1e1900 */
/*0390*/ LDG.E R11, [R4.64] ; /* 0x00000004040b7981 */
/* 0x001ea2000c1e1900 */
/*03a0*/ IMAD.WIDE R8, R3, R8, c[0x0][0x178] ; /* 0x00005e0003087625 */
/* 0x000fc800078e0208 */
/*03b0*/ IMAD.WIDE R12, R0, 0x4, R6 ; /* 0x00000004000c7825 */
/* 0x000fe200078e0206 */
/*03c0*/ IADD3 R19, R2, R11, RZ ; /* 0x0000000b02137210 */
/* 0x004fc60007ffe0ff */
/*03d0*/ IMAD.WIDE R10, R0.reuse, 0x4, R4 ; /* 0x00000004000a7825 */
/* 0x040fe400078e0204 */
/*03e0*/ STG.E [R8.64], R19 ; /* 0x0000001308007986 */
/* 0x0001e8000c101904 */
/*03f0*/ LDG.E R2, [R12.64] ; /* 0x000000040c027981 */
/* 0x000ea8000c1e1900 */
/*0400*/ LDG.E R17, [R10.64] ; /* 0x000000040a117981 */
/* 0x000ea2000c1e1900 */
/*0410*/ IMAD.WIDE R14, R0, 0x4, R8 ; /* 0x00000004000e7825 */
/* 0x000fc800078e0208 */
/*0420*/ IMAD.WIDE R6, R0, 0x4, R12 ; /* 0x0000000400067825 */
/* 0x000fc800078e020c */
/*0430*/ IMAD.WIDE R4, R0, 0x4, R10 ; /* 0x0000000400047825 */
/* 0x000fc800078e020a */
/*0440*/ IMAD.IADD R21, R2, 0x1, R17 ; /* 0x0000000102157824 */
/* 0x004fca00078e0211 */
/*0450*/ STG.E [R14.64], R21 ; /* 0x000000150e007986 */
/* 0x0003e8000c101904 */
/*0460*/ LDG.E R2, [R6.64] ; /* 0x0000000406027981 */
/* 0x000ea8000c1e1900 */
/*0470*/ LDG.E R23, [R4.64] ; /* 0x0000000404177981 */
/* 0x000ea2000c1e1900 */
/*0480*/ IMAD.WIDE R16, R0, 0x4, R14 ; /* 0x0000000400107825 */
/* 0x000fc800078e020e */
/*0490*/ IMAD.WIDE R12, R0, 0x4, R6 ; /* 0x00000004000c7825 */
/* 0x000fc800078e0206 */
/*04a0*/ IMAD.WIDE R8, R0, 0x4, R4 ; /* 0x0000000400087825 */
/* 0x001fe200078e0204 */
/*04b0*/ IADD3 R23, R2, R23, RZ ; /* 0x0000001702177210 */
/* 0x004fca0007ffe0ff */
/*04c0*/ STG.E [R16.64], R23 ; /* 0x0000001710007986 */
/* 0x0001e8000c101904 */
/*04d0*/ LDG.E R12, [R12.64] ; /* 0x000000040c0c7981 */
/* 0x000e68000c1e1900 */
/*04e0*/ LDG.E R9, [R8.64] ; /* 0x0000000408097981 */
/* 0x000e62000c1e1900 */
/*04f0*/ IMAD.WIDE R10, R0.reuse, 0x4, R16 ; /* 0x00000004000a7825 */
/* 0x040fe200078e0210 */
/*0500*/ IADD3 R3, R0, R3, R0 ; /* 0x0000000300037210 */
/* 0x000fc80007ffe000 */
/*0510*/ IADD3 R3, R0, R3, R0 ; /* 0x0000000300037210 */
/* 0x000fc80007ffe000 */
/*0520*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x160], PT ; /* 0x0000580003007a0c */
/* 0x000fe40003f06270 */
/*0530*/ IADD3 R15, R12, R9, RZ ; /* 0x000000090c0f7210 */
/* 0x002fca0007ffe0ff */
/*0540*/ STG.E [R10.64], R15 ; /* 0x0000000f0a007986 */
/* 0x0001ec000c101904 */
/*0550*/ @!P0 BRA 0x350 ; /* 0xfffffdf000008947 */
/* 0x000fea000383ffff */
/*0560*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0570*/ BRA 0x570; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0580*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0590*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /*
Name: Paul Talaga
Date: Dec 5, 2017
Desc: Program to add two arrays using the GPU
It uses multiple threads and multiple blocks, so this is
as fast it can go.
To compile this, do: nvcc add-blockthreads.cu
*/
#include <iostream>
using namespace std;
#define numThreads 32 // upper limit of 1024
#define numBlocks 1000
// CUDA kernel function to add to arrays element by element
// This isn't a great demonstration because there isn't much
// work for this function to do, so you'll likely not see
// a big speedup over the CPU.
__global__
void add(int size, int* x, int* y, int* z){
//threadIdx.x
//blockIdx.x
int index = blockIdx.x * blockDim.x + threadIdx.x;
int stride = blockDim.x * gridDim.x; // gridDim is numThreads
for(int i = index; i < size; i+= stride){
z[i] = x[i] + y[i];
}
}
int main(void){
// Size of the arrays we'll be adding
const unsigned N = 10000000;
cout << "Size: " << N*3*sizeof(int) / 1024 / 1024 << " MB" << endl;
// To used unified memory (CUDA takes care of data movement)
// all memory must be allocated via the cudaMallocManaged call below.
int* x;
int* y;
int* z;
cudaMallocManaged(&x, N * sizeof(int));
cudaMallocManaged(&y, N * sizeof(int));
cudaMallocManaged(&z, N * sizeof(int));
// Fill the arrays with numbers
for(int i = 0; i < N; i++){
x[i] = i;
y[i] = 2 * i;
}
// Call the add function, with 1 block, and 1 thread
add<<<numBlocks,numThreads>>>(N, x, y, z);
// Wait until the device is done before proceeding, otherwise we'd be
// accessing x, y, and z in the loop below before the add function completes
// on the device.
cudaDeviceSynchronize();
// Check to see if the math is correct
int errors = 0;
for(int i = 0; i < N; i++){
if(z[i] != x[i] + y[i]){
cout << i << " did not add correctly!" << endl;
errors++;
}
}
if(!errors)cout << "All good!" << endl;
return 0;
} | .file "tmpxft_000d6ad6_00000000-6_add-blockthreads.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z27__device_stub__Z3addiPiS_S_iPiS_S_
.type _Z27__device_stub__Z3addiPiS_S_iPiS_S_, @function
_Z27__device_stub__Z3addiPiS_S_iPiS_S_:
.LFB3694:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3addiPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3694:
.size _Z27__device_stub__Z3addiPiS_S_iPiS_S_, .-_Z27__device_stub__Z3addiPiS_S_iPiS_S_
.globl _Z3addiPiS_S_
.type _Z3addiPiS_S_, @function
_Z3addiPiS_S_:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z27__device_stub__Z3addiPiS_S_iPiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _Z3addiPiS_S_, .-_Z3addiPiS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Size: "
.LC1:
.string " MB"
.LC2:
.string " did not add correctly!"
.LC3:
.string "All good!"
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $72, %rsp
.cfi_def_cfa_offset 128
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
leaq .LC0(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl $114, %esi
call _ZNSo9_M_insertImEERSoT_@PLT
movq %rax, %rdi
leaq .LC1(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq 8(%rsp), %rdi
movl $1, %edx
movl $40000000, %esi
call cudaMallocManaged@PLT
leaq 16(%rsp), %rdi
movl $1, %edx
movl $40000000, %esi
call cudaMallocManaged@PLT
leaq 24(%rsp), %rdi
movl $1, %edx
movl $40000000, %esi
call cudaMallocManaged@PLT
movl $0, %eax
.L12:
movq 8(%rsp), %rdx
movl %eax, (%rdx,%rax,4)
leal (%rax,%rax), %ecx
movq 16(%rsp), %rdx
movl %ecx, (%rdx,%rax,4)
addq $1, %rax
cmpq $10000000, %rax
jne .L12
movl $32, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1000, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L25
.L13:
call cudaDeviceSynchronize@PLT
movl $0, %ebx
movl $0, %ebp
leaq _ZSt4cout(%rip), %r13
leaq .LC2(%rip), %r12
jmp .L19
.L25:
movq 24(%rsp), %rcx
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
movl $10000000, %edi
call _Z27__device_stub__Z3addiPiS_S_iPiS_S_
jmp .L13
.L28:
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L26
call _ZSt16__throw_bad_castv@PLT
.L26:
call __stack_chk_fail@PLT
.L17:
movq %r15, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r15), %rax
movl $10, %esi
movq %r15, %rdi
call *48(%rax)
movl %eax, %esi
.L18:
movsbl %sil, %esi
movq %r14, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
addl $1, %ebp
.L14:
addq $1, %rbx
cmpq $10000000, %rbx
je .L27
.L19:
movq 16(%rsp), %rax
movl (%rax,%rbx,4), %eax
movq 8(%rsp), %rdx
addl (%rdx,%rbx,4), %eax
movq 24(%rsp), %rdx
cmpl %eax, (%rdx,%rbx,4)
je .L14
movl %ebx, %esi
movq %r13, %rdi
call _ZNSolsEi@PLT
movq %rax, %r14
movl $23, %edx
movq %r12, %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq (%r14), %rax
movq -24(%rax), %rax
movq 240(%r14,%rax), %r15
testq %r15, %r15
je .L28
cmpb $0, 56(%r15)
je .L17
movzbl 67(%r15), %esi
jmp .L18
.L27:
testl %ebp, %ebp
je .L29
.L20:
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L30
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L29:
.cfi_restore_state
leaq .LC3(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
jmp .L20
.L30:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size main, .-main
.section .rodata.str1.1
.LC4:
.string "_Z3addiPiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z3addiPiS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /*
Name: Paul Talaga
Date: Dec 5, 2017
Desc: Program to add two arrays using the GPU
It uses multiple threads and multiple blocks, so this is
as fast it can go.
To compile this, do: nvcc add-blockthreads.cu
*/
#include <iostream>
using namespace std;
#define numThreads 32 // upper limit of 1024
#define numBlocks 1000
// CUDA kernel function to add to arrays element by element
// This isn't a great demonstration because there isn't much
// work for this function to do, so you'll likely not see
// a big speedup over the CPU.
__global__
void add(int size, int* x, int* y, int* z){
//threadIdx.x
//blockIdx.x
int index = blockIdx.x * blockDim.x + threadIdx.x;
int stride = blockDim.x * gridDim.x; // gridDim is numThreads
for(int i = index; i < size; i+= stride){
z[i] = x[i] + y[i];
}
}
int main(void){
// Size of the arrays we'll be adding
const unsigned N = 10000000;
cout << "Size: " << N*3*sizeof(int) / 1024 / 1024 << " MB" << endl;
// To used unified memory (CUDA takes care of data movement)
// all memory must be allocated via the cudaMallocManaged call below.
int* x;
int* y;
int* z;
cudaMallocManaged(&x, N * sizeof(int));
cudaMallocManaged(&y, N * sizeof(int));
cudaMallocManaged(&z, N * sizeof(int));
// Fill the arrays with numbers
for(int i = 0; i < N; i++){
x[i] = i;
y[i] = 2 * i;
}
// Call the add function, with 1 block, and 1 thread
add<<<numBlocks,numThreads>>>(N, x, y, z);
// Wait until the device is done before proceeding, otherwise we'd be
// accessing x, y, and z in the loop below before the add function completes
// on the device.
cudaDeviceSynchronize();
// Check to see if the math is correct
int errors = 0;
for(int i = 0; i < N; i++){
if(z[i] != x[i] + y[i]){
cout << i << " did not add correctly!" << endl;
errors++;
}
}
if(!errors)cout << "All good!" << endl;
return 0;
} | /*
Name: Paul Talaga
Date: Dec 5, 2017
Desc: Program to add two arrays using the GPU
It uses multiple threads and multiple blocks, so this is
as fast it can go.
To compile this, do: nvcc add-blockthreads.cu
*/
#include <hip/hip_runtime.h>
#include <iostream>
using namespace std;
#define numThreads 32 // upper limit of 1024
#define numBlocks 1000
// CUDA kernel function to add to arrays element by element
// This isn't a great demonstration because there isn't much
// work for this function to do, so you'll likely not see
// a big speedup over the CPU.
__global__
void add(int size, int* x, int* y, int* z){
//threadIdx.x
//blockIdx.x
int index = blockIdx.x * blockDim.x + threadIdx.x;
int stride = blockDim.x * gridDim.x; // gridDim is numThreads
for(int i = index; i < size; i+= stride){
z[i] = x[i] + y[i];
}
}
int main(void){
// Size of the arrays we'll be adding
const unsigned N = 10000000;
cout << "Size: " << N*3*sizeof(int) / 1024 / 1024 << " MB" << endl;
// To used unified memory (CUDA takes care of data movement)
// all memory must be allocated via the cudaMallocManaged call below.
int* x;
int* y;
int* z;
hipMallocManaged(&x, N * sizeof(int));
hipMallocManaged(&y, N * sizeof(int));
hipMallocManaged(&z, N * sizeof(int));
// Fill the arrays with numbers
for(int i = 0; i < N; i++){
x[i] = i;
y[i] = 2 * i;
}
// Call the add function, with 1 block, and 1 thread
add<<<numBlocks,numThreads>>>(N, x, y, z);
// Wait until the device is done before proceeding, otherwise we'd be
// accessing x, y, and z in the loop below before the add function completes
// on the device.
hipDeviceSynchronize();
// Check to see if the math is correct
int errors = 0;
for(int i = 0; i < N; i++){
if(z[i] != x[i] + y[i]){
cout << i << " did not add correctly!" << endl;
errors++;
}
}
if(!errors)cout << "All good!" << endl;
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | /*
Name: Paul Talaga
Date: Dec 5, 2017
Desc: Program to add two arrays using the GPU
It uses multiple threads and multiple blocks, so this is
as fast it can go.
To compile this, do: nvcc add-blockthreads.cu
*/
#include <hip/hip_runtime.h>
#include <iostream>
using namespace std;
#define numThreads 32 // upper limit of 1024
#define numBlocks 1000
// CUDA kernel function to add to arrays element by element
// This isn't a great demonstration because there isn't much
// work for this function to do, so you'll likely not see
// a big speedup over the CPU.
__global__
void add(int size, int* x, int* y, int* z){
//threadIdx.x
//blockIdx.x
int index = blockIdx.x * blockDim.x + threadIdx.x;
int stride = blockDim.x * gridDim.x; // gridDim is numThreads
for(int i = index; i < size; i+= stride){
z[i] = x[i] + y[i];
}
}
int main(void){
// Size of the arrays we'll be adding
const unsigned N = 10000000;
cout << "Size: " << N*3*sizeof(int) / 1024 / 1024 << " MB" << endl;
// To used unified memory (CUDA takes care of data movement)
// all memory must be allocated via the cudaMallocManaged call below.
int* x;
int* y;
int* z;
hipMallocManaged(&x, N * sizeof(int));
hipMallocManaged(&y, N * sizeof(int));
hipMallocManaged(&z, N * sizeof(int));
// Fill the arrays with numbers
for(int i = 0; i < N; i++){
x[i] = i;
y[i] = 2 * i;
}
// Call the add function, with 1 block, and 1 thread
add<<<numBlocks,numThreads>>>(N, x, y, z);
// Wait until the device is done before proceeding, otherwise we'd be
// accessing x, y, and z in the loop below before the add function completes
// on the device.
hipDeviceSynchronize();
// Check to see if the math is correct
int errors = 0;
for(int i = 0; i < N; i++){
if(z[i] != x[i] + y[i]){
cout << i << " did not add correctly!" << endl;
errors++;
}
}
if(!errors)cout << "All good!" << endl;
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3addiPiS_S_
.globl _Z3addiPiS_S_
.p2align 8
.type _Z3addiPiS_S_,@function
_Z3addiPiS_S_:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x2c
s_load_b32 s12, s[0:1], 0x0
s_add_u32 s2, s0, 32
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s8, s4, 0xffff
s_mov_b32 s4, exec_lo
v_mad_u64_u32 v[1:2], null, s15, s8, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s12, v1
s_cbranch_execz .LBB0_3
s_load_b32 s9, s[2:3], 0x0
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x8
s_load_b64 s[2:3], s[0:1], 0x18
v_ashrrev_i32_e32 v2, 31, v1
s_mov_b32 s1, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_mul_i32 s8, s9, s8
s_ashr_i32 s9, s8, 31
s_delay_alu instid0(SALU_CYCLE_1)
s_lshl_b64 s[10:11], s[8:9], 2
.p2align 6
.LBB0_2:
s_delay_alu instid0(VALU_DEP_1)
v_add_co_u32 v4, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v3, vcc_lo
v_add_co_u32 v6, vcc_lo, s6, v2
v_add_co_ci_u32_e32 v7, vcc_lo, s7, v3, vcc_lo
v_add_nc_u32_e32 v1, s8, v1
global_load_b32 v0, v[4:5], off
global_load_b32 v6, v[6:7], off
v_add_co_u32 v4, vcc_lo, s2, v2
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v3, vcc_lo
v_add_co_u32 v2, vcc_lo, v2, s10
v_cmp_le_i32_e64 s0, s12, v1
v_add_co_ci_u32_e32 v3, vcc_lo, s11, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_2)
s_or_b32 s1, s0, s1
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v0, v6, v0
global_store_b32 v[4:5], v0, off
s_and_not1_b32 exec_lo, exec_lo, s1
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3addiPiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3addiPiS_S_, .Lfunc_end0-_Z3addiPiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3addiPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z3addiPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | /*
Name: Paul Talaga
Date: Dec 5, 2017
Desc: Program to add two arrays using the GPU
It uses multiple threads and multiple blocks, so this is
as fast it can go.
To compile this, do: nvcc add-blockthreads.cu
*/
#include <hip/hip_runtime.h>
#include <iostream>
using namespace std;
#define numThreads 32 // upper limit of 1024
#define numBlocks 1000
// CUDA kernel function to add to arrays element by element
// This isn't a great demonstration because there isn't much
// work for this function to do, so you'll likely not see
// a big speedup over the CPU.
__global__
void add(int size, int* x, int* y, int* z){
//threadIdx.x
//blockIdx.x
int index = blockIdx.x * blockDim.x + threadIdx.x;
int stride = blockDim.x * gridDim.x; // gridDim is numThreads
for(int i = index; i < size; i+= stride){
z[i] = x[i] + y[i];
}
}
int main(void){
// Size of the arrays we'll be adding
const unsigned N = 10000000;
cout << "Size: " << N*3*sizeof(int) / 1024 / 1024 << " MB" << endl;
// To used unified memory (CUDA takes care of data movement)
// all memory must be allocated via the cudaMallocManaged call below.
int* x;
int* y;
int* z;
hipMallocManaged(&x, N * sizeof(int));
hipMallocManaged(&y, N * sizeof(int));
hipMallocManaged(&z, N * sizeof(int));
// Fill the arrays with numbers
for(int i = 0; i < N; i++){
x[i] = i;
y[i] = 2 * i;
}
// Call the add function, with 1 block, and 1 thread
add<<<numBlocks,numThreads>>>(N, x, y, z);
// Wait until the device is done before proceeding, otherwise we'd be
// accessing x, y, and z in the loop below before the add function completes
// on the device.
hipDeviceSynchronize();
// Check to see if the math is correct
int errors = 0;
for(int i = 0; i < N; i++){
if(z[i] != x[i] + y[i]){
cout << i << " did not add correctly!" << endl;
errors++;
}
}
if(!errors)cout << "All good!" << endl;
return 0;
} | .text
.file "add-blockthreads.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z18__device_stub__addiPiS_S_ # -- Begin function _Z18__device_stub__addiPiS_S_
.p2align 4, 0x90
.type _Z18__device_stub__addiPiS_S_,@function
_Z18__device_stub__addiPiS_S_: # @_Z18__device_stub__addiPiS_S_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 4(%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 64(%rsp)
movq %rcx, 56(%rsp)
leaq 4(%rsp), %rax
movq %rax, 80(%rsp)
leaq 72(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 56(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3addiPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z18__device_stub__addiPiS_S_, .Lfunc_end0-_Z18__device_stub__addiPiS_S_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $152, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $6, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl $114, %esi
callq _ZNSo9_M_insertImEERSoT_
movq %rax, %rbx
movl $.L.str.1, %esi
movl $3, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%rbx), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r14
testq %r14, %r14
je .LBB1_23
# %bb.1: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%r14)
je .LBB1_3
# %bb.2:
movzbl 67(%r14), %eax
jmp .LBB1_4
.LBB1_3:
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_4: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movq %rbx, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
leaq 16(%rsp), %rdi
movl $40000000, %esi # imm = 0x2625A00
movl $1, %edx
callq hipMallocManaged
leaq 8(%rsp), %rdi
movl $40000000, %esi # imm = 0x2625A00
movl $1, %edx
callq hipMallocManaged
leaq 32(%rsp), %rdi
movl $40000000, %esi # imm = 0x2625A00
movl $1, %edx
callq hipMallocManaged
movq 16(%rsp), %rax
xorl %ecx, %ecx
movq 8(%rsp), %rdx
xorl %esi, %esi
.p2align 4, 0x90
.LBB1_5: # =>This Inner Loop Header: Depth=1
movl %esi, (%rax,%rsi,4)
movl %ecx, (%rdx,%rsi,4)
incq %rsi
addl $2, %ecx
cmpq $10000000, %rsi # imm = 0x989680
jne .LBB1_5
# %bb.6:
movabsq $4294967328, %rdx # imm = 0x100000020
leaq 968(%rdx), %rdi
xorl %r12d, %r12d
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_8
# %bb.7:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq 32(%rsp), %rdx
movl $10000000, 28(%rsp) # imm = 0x989680
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
leaq 28(%rsp), %rax
movq %rax, 112(%rsp)
leaq 104(%rsp), %rax
movq %rax, 120(%rsp)
leaq 96(%rsp), %rax
movq %rax, 128(%rsp)
leaq 88(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z3addiPiS_S_, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_8:
callq hipDeviceSynchronize
xorl %ebx, %ebx
jmp .LBB1_9
.LBB1_13: # in Loop: Header=BB1_9 Depth=1
movq %r15, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_14: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit24
# in Loop: Header=BB1_9 Depth=1
movsbl %al, %esi
movq %r14, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
incl %r12d
.LBB1_15: # in Loop: Header=BB1_9 Depth=1
incq %rbx
cmpq $10000000, %rbx # imm = 0x989680
je .LBB1_16
.LBB1_9: # =>This Inner Loop Header: Depth=1
movq 32(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movl (%rdx,%rbx,4), %edx
addl (%rcx,%rbx,4), %edx
cmpl %edx, (%rax,%rbx,4)
je .LBB1_15
# %bb.10: # in Loop: Header=BB1_9 Depth=1
movl $_ZSt4cout, %edi
movl %ebx, %esi
callq _ZNSolsEi
movq %rax, %r14
movl $.L.str.2, %esi
movl $23, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%r14), %rax
movq -24(%rax), %rax
movq 240(%r14,%rax), %r15
testq %r15, %r15
je .LBB1_23
# %bb.11: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i21
# in Loop: Header=BB1_9 Depth=1
cmpb $0, 56(%r15)
je .LBB1_13
# %bb.12: # in Loop: Header=BB1_9 Depth=1
movzbl 67(%r15), %eax
jmp .LBB1_14
.LBB1_16:
testl %r12d, %r12d
jne .LBB1_22
# %bb.17:
movl $_ZSt4cout, %edi
movl $.L.str.3, %esi
movl $9, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB1_23
# %bb.18: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i26
cmpb $0, 56(%rbx)
je .LBB1_20
# %bb.19:
movzbl 67(%rbx), %eax
jmp .LBB1_21
.LBB1_20:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_21: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit29
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
.LBB1_22:
xorl %eax, %eax
addq $152, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB1_23:
.cfi_def_cfa_offset 192
callq _ZSt16__throw_bad_castv
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3addiPiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3addiPiS_S_,@object # @_Z3addiPiS_S_
.section .rodata,"a",@progbits
.globl _Z3addiPiS_S_
.p2align 3, 0x0
_Z3addiPiS_S_:
.quad _Z18__device_stub__addiPiS_S_
.size _Z3addiPiS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Size: "
.size .L.str, 7
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz " MB"
.size .L.str.1, 4
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz " did not add correctly!"
.size .L.str.2, 24
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "All good!"
.size .L.str.3, 10
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z3addiPiS_S_"
.size .L__unnamed_1, 14
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__addiPiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3addiPiS_S_
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z3addiPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e280000002500 */
/*0020*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R3, R3, c[0x0][0x0], R0 ; /* 0x0000000003037a24 */
/* 0x001fca00078e0200 */
/*0040*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x160], PT ; /* 0x0000580003007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ MOV R0, c[0x0][0x0] ; /* 0x0000000000007a02 */
/* 0x000fe20000000f00 */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0080*/ BSSY B0, 0x340 ; /* 0x000002b000007945 */
/* 0x000fe60003800000 */
/*0090*/ IMAD R0, R0, c[0x0][0xc], RZ ; /* 0x0000030000007a24 */
/* 0x000fc800078e02ff */
/*00a0*/ I2F.U32.RP R6, R0 ; /* 0x0000000000067306 */
/* 0x000e220000209000 */
/*00b0*/ IMAD.MOV R9, RZ, RZ, -R0 ; /* 0x000000ffff097224 */
/* 0x000fe200078e0a00 */
/*00c0*/ IADD3 R2, R0.reuse, R3, RZ ; /* 0x0000000300027210 */
/* 0x040fe40007ffe0ff */
/*00d0*/ ISETP.NE.U32.AND P2, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe40003f45070 */
/*00e0*/ LOP3.LUT R7, RZ, R2, RZ, 0x33, !PT ; /* 0x00000002ff077212 */
/* 0x000fc800078e33ff */
/*00f0*/ IADD3 R7, R7, c[0x0][0x160], R0 ; /* 0x0000580007077a10 */
/* 0x000fe20007ffe000 */
/*0100*/ MUFU.RCP R6, R6 ; /* 0x0000000600067308 */
/* 0x001e240000001000 */
/*0110*/ IADD3 R4, R6, 0xffffffe, RZ ; /* 0x0ffffffe06047810 */
/* 0x001fcc0007ffe0ff */
/*0120*/ F2I.FTZ.U32.TRUNC.NTZ R5, R4 ; /* 0x0000000400057305 */
/* 0x000064000021f000 */
/*0130*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x001fe400078e00ff */
/*0140*/ IMAD R9, R9, R5, RZ ; /* 0x0000000509097224 */
/* 0x002fc800078e02ff */
/*0150*/ IMAD.HI.U32 R2, R5, R9, R4 ; /* 0x0000000905027227 */
/* 0x000fcc00078e0004 */
/*0160*/ IMAD.HI.U32 R2, R2, R7, RZ ; /* 0x0000000702027227 */
/* 0x000fca00078e00ff */
/*0170*/ IADD3 R4, -R2, RZ, RZ ; /* 0x000000ff02047210 */
/* 0x000fca0007ffe1ff */
/*0180*/ IMAD R7, R0, R4, R7 ; /* 0x0000000400077224 */
/* 0x000fca00078e0207 */
/*0190*/ ISETP.GE.U32.AND P0, PT, R7, R0, PT ; /* 0x000000000700720c */
/* 0x000fda0003f06070 */
/*01a0*/ @P0 IADD3 R7, -R0, R7, RZ ; /* 0x0000000700070210 */
/* 0x000fe40007ffe1ff */
/*01b0*/ @P0 IADD3 R2, R2, 0x1, RZ ; /* 0x0000000102020810 */
/* 0x000fe40007ffe0ff */
/*01c0*/ ISETP.GE.U32.AND P1, PT, R7, R0, PT ; /* 0x000000000700720c */
/* 0x000fda0003f26070 */
/*01d0*/ @P1 IADD3 R2, R2, 0x1, RZ ; /* 0x0000000102021810 */
/* 0x000fe40007ffe0ff */
/*01e0*/ @!P2 LOP3.LUT R2, RZ, R0, RZ, 0x33, !PT ; /* 0x00000000ff02a212 */
/* 0x000fc800078e33ff */
/*01f0*/ IADD3 R4, R2.reuse, 0x1, RZ ; /* 0x0000000102047810 */
/* 0x040fe40007ffe0ff */
/*0200*/ ISETP.GE.U32.AND P1, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fe40003f26070 */
/*0210*/ LOP3.LUT P0, R4, R4, 0x3, RZ, 0xc0, !PT ; /* 0x0000000304047812 */
/* 0x000fda000780c0ff */
/*0220*/ @!P0 BRA 0x330 ; /* 0x0000010000008947 */
/* 0x000fea0003800000 */
/*0230*/ IMAD.MOV.U32 R8, RZ, RZ, 0x4 ; /* 0x00000004ff087424 */
/* 0x000fe200078e00ff */
/*0240*/ MOV R2, R4 ; /* 0x0000000400027202 */
/* 0x000fc60000000f00 */
/*0250*/ IMAD.WIDE R4, R3, R8, c[0x0][0x178] ; /* 0x00005e0003047625 */
/* 0x000fc800078e0208 */
/*0260*/ IMAD.WIDE R6, R3, R8, c[0x0][0x170] ; /* 0x00005c0003067625 */
/* 0x000fc800078e0208 */
/*0270*/ IMAD.WIDE R8, R3, R8, c[0x0][0x168] ; /* 0x00005a0003087625 */
/* 0x000fc800078e0208 */
/*0280*/ LDG.E R10, [R6.64] ; /* 0x00000004060a7981 */
/* 0x0000a8000c1e1900 */
/*0290*/ LDG.E R11, [R8.64] ; /* 0x00000004080b7981 */
/* 0x0002a2000c1e1900 */
/*02a0*/ IADD3 R2, R2, -0x1, RZ ; /* 0xffffffff02027810 */
/* 0x000fe20007ffe0ff */
/*02b0*/ IMAD.IADD R3, R0, 0x1, R3 ; /* 0x0000000100037824 */
/* 0x000fc600078e0203 */
/*02c0*/ ISETP.NE.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fe20003f05270 */
/*02d0*/ IMAD.WIDE R6, R0, 0x4, R6 ; /* 0x0000000400067825 */
/* 0x001fc800078e0206 */
/*02e0*/ IMAD.WIDE R8, R0, 0x4, R8 ; /* 0x0000000400087825 */
/* 0x002fe200078e0208 */
/*02f0*/ IADD3 R11, R10, R11, RZ ; /* 0x0000000b0a0b7210 */
/* 0x004fca0007ffe0ff */
/*0300*/ STG.E [R4.64], R11 ; /* 0x0000000b04007986 */
/* 0x0001e4000c101904 */
/*0310*/ IMAD.WIDE R4, R0, 0x4, R4 ; /* 0x0000000400047825 */
/* 0x001fe200078e0204 */
/*0320*/ @P0 BRA 0x280 ; /* 0xffffff5000000947 */
/* 0x000fea000383ffff */
/*0330*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0340*/ @!P1 EXIT ; /* 0x000000000000994d */
/* 0x000fea0003800000 */
/*0350*/ HFMA2.MMA R8, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff087435 */
/* 0x000fd400000001ff */
/*0360*/ IMAD.WIDE R6, R3, R8, c[0x0][0x170] ; /* 0x00005c0003067625 */
/* 0x000fc800078e0208 */
/*0370*/ IMAD.WIDE R4, R3.reuse, R8.reuse, c[0x0][0x168] ; /* 0x00005a0003047625 */
/* 0x0c0fe200078e0208 */
/*0380*/ LDG.E R2, [R6.64] ; /* 0x0000000406027981 */
/* 0x000ea8000c1e1900 */
/*0390*/ LDG.E R11, [R4.64] ; /* 0x00000004040b7981 */
/* 0x001ea2000c1e1900 */
/*03a0*/ IMAD.WIDE R8, R3, R8, c[0x0][0x178] ; /* 0x00005e0003087625 */
/* 0x000fc800078e0208 */
/*03b0*/ IMAD.WIDE R12, R0, 0x4, R6 ; /* 0x00000004000c7825 */
/* 0x000fe200078e0206 */
/*03c0*/ IADD3 R19, R2, R11, RZ ; /* 0x0000000b02137210 */
/* 0x004fc60007ffe0ff */
/*03d0*/ IMAD.WIDE R10, R0.reuse, 0x4, R4 ; /* 0x00000004000a7825 */
/* 0x040fe400078e0204 */
/*03e0*/ STG.E [R8.64], R19 ; /* 0x0000001308007986 */
/* 0x0001e8000c101904 */
/*03f0*/ LDG.E R2, [R12.64] ; /* 0x000000040c027981 */
/* 0x000ea8000c1e1900 */
/*0400*/ LDG.E R17, [R10.64] ; /* 0x000000040a117981 */
/* 0x000ea2000c1e1900 */
/*0410*/ IMAD.WIDE R14, R0, 0x4, R8 ; /* 0x00000004000e7825 */
/* 0x000fc800078e0208 */
/*0420*/ IMAD.WIDE R6, R0, 0x4, R12 ; /* 0x0000000400067825 */
/* 0x000fc800078e020c */
/*0430*/ IMAD.WIDE R4, R0, 0x4, R10 ; /* 0x0000000400047825 */
/* 0x000fc800078e020a */
/*0440*/ IMAD.IADD R21, R2, 0x1, R17 ; /* 0x0000000102157824 */
/* 0x004fca00078e0211 */
/*0450*/ STG.E [R14.64], R21 ; /* 0x000000150e007986 */
/* 0x0003e8000c101904 */
/*0460*/ LDG.E R2, [R6.64] ; /* 0x0000000406027981 */
/* 0x000ea8000c1e1900 */
/*0470*/ LDG.E R23, [R4.64] ; /* 0x0000000404177981 */
/* 0x000ea2000c1e1900 */
/*0480*/ IMAD.WIDE R16, R0, 0x4, R14 ; /* 0x0000000400107825 */
/* 0x000fc800078e020e */
/*0490*/ IMAD.WIDE R12, R0, 0x4, R6 ; /* 0x00000004000c7825 */
/* 0x000fc800078e0206 */
/*04a0*/ IMAD.WIDE R8, R0, 0x4, R4 ; /* 0x0000000400087825 */
/* 0x001fe200078e0204 */
/*04b0*/ IADD3 R23, R2, R23, RZ ; /* 0x0000001702177210 */
/* 0x004fca0007ffe0ff */
/*04c0*/ STG.E [R16.64], R23 ; /* 0x0000001710007986 */
/* 0x0001e8000c101904 */
/*04d0*/ LDG.E R12, [R12.64] ; /* 0x000000040c0c7981 */
/* 0x000e68000c1e1900 */
/*04e0*/ LDG.E R9, [R8.64] ; /* 0x0000000408097981 */
/* 0x000e62000c1e1900 */
/*04f0*/ IMAD.WIDE R10, R0.reuse, 0x4, R16 ; /* 0x00000004000a7825 */
/* 0x040fe200078e0210 */
/*0500*/ IADD3 R3, R0, R3, R0 ; /* 0x0000000300037210 */
/* 0x000fc80007ffe000 */
/*0510*/ IADD3 R3, R0, R3, R0 ; /* 0x0000000300037210 */
/* 0x000fc80007ffe000 */
/*0520*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x160], PT ; /* 0x0000580003007a0c */
/* 0x000fe40003f06270 */
/*0530*/ IADD3 R15, R12, R9, RZ ; /* 0x000000090c0f7210 */
/* 0x002fca0007ffe0ff */
/*0540*/ STG.E [R10.64], R15 ; /* 0x0000000f0a007986 */
/* 0x0001ec000c101904 */
/*0550*/ @!P0 BRA 0x350 ; /* 0xfffffdf000008947 */
/* 0x000fea000383ffff */
/*0560*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0570*/ BRA 0x570; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0580*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0590*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3addiPiS_S_
.globl _Z3addiPiS_S_
.p2align 8
.type _Z3addiPiS_S_,@function
_Z3addiPiS_S_:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x2c
s_load_b32 s12, s[0:1], 0x0
s_add_u32 s2, s0, 32
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s8, s4, 0xffff
s_mov_b32 s4, exec_lo
v_mad_u64_u32 v[1:2], null, s15, s8, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s12, v1
s_cbranch_execz .LBB0_3
s_load_b32 s9, s[2:3], 0x0
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x8
s_load_b64 s[2:3], s[0:1], 0x18
v_ashrrev_i32_e32 v2, 31, v1
s_mov_b32 s1, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_mul_i32 s8, s9, s8
s_ashr_i32 s9, s8, 31
s_delay_alu instid0(SALU_CYCLE_1)
s_lshl_b64 s[10:11], s[8:9], 2
.p2align 6
.LBB0_2:
s_delay_alu instid0(VALU_DEP_1)
v_add_co_u32 v4, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v3, vcc_lo
v_add_co_u32 v6, vcc_lo, s6, v2
v_add_co_ci_u32_e32 v7, vcc_lo, s7, v3, vcc_lo
v_add_nc_u32_e32 v1, s8, v1
global_load_b32 v0, v[4:5], off
global_load_b32 v6, v[6:7], off
v_add_co_u32 v4, vcc_lo, s2, v2
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v3, vcc_lo
v_add_co_u32 v2, vcc_lo, v2, s10
v_cmp_le_i32_e64 s0, s12, v1
v_add_co_ci_u32_e32 v3, vcc_lo, s11, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_2)
s_or_b32 s1, s0, s1
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v0, v6, v0
global_store_b32 v[4:5], v0, off
s_and_not1_b32 exec_lo, exec_lo, s1
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3addiPiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3addiPiS_S_, .Lfunc_end0-_Z3addiPiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3addiPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z3addiPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000d6ad6_00000000-6_add-blockthreads.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z27__device_stub__Z3addiPiS_S_iPiS_S_
.type _Z27__device_stub__Z3addiPiS_S_iPiS_S_, @function
_Z27__device_stub__Z3addiPiS_S_iPiS_S_:
.LFB3694:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3addiPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3694:
.size _Z27__device_stub__Z3addiPiS_S_iPiS_S_, .-_Z27__device_stub__Z3addiPiS_S_iPiS_S_
.globl _Z3addiPiS_S_
.type _Z3addiPiS_S_, @function
_Z3addiPiS_S_:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z27__device_stub__Z3addiPiS_S_iPiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _Z3addiPiS_S_, .-_Z3addiPiS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Size: "
.LC1:
.string " MB"
.LC2:
.string " did not add correctly!"
.LC3:
.string "All good!"
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $72, %rsp
.cfi_def_cfa_offset 128
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
leaq .LC0(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl $114, %esi
call _ZNSo9_M_insertImEERSoT_@PLT
movq %rax, %rdi
leaq .LC1(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq 8(%rsp), %rdi
movl $1, %edx
movl $40000000, %esi
call cudaMallocManaged@PLT
leaq 16(%rsp), %rdi
movl $1, %edx
movl $40000000, %esi
call cudaMallocManaged@PLT
leaq 24(%rsp), %rdi
movl $1, %edx
movl $40000000, %esi
call cudaMallocManaged@PLT
movl $0, %eax
.L12:
movq 8(%rsp), %rdx
movl %eax, (%rdx,%rax,4)
leal (%rax,%rax), %ecx
movq 16(%rsp), %rdx
movl %ecx, (%rdx,%rax,4)
addq $1, %rax
cmpq $10000000, %rax
jne .L12
movl $32, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1000, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L25
.L13:
call cudaDeviceSynchronize@PLT
movl $0, %ebx
movl $0, %ebp
leaq _ZSt4cout(%rip), %r13
leaq .LC2(%rip), %r12
jmp .L19
.L25:
movq 24(%rsp), %rcx
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
movl $10000000, %edi
call _Z27__device_stub__Z3addiPiS_S_iPiS_S_
jmp .L13
.L28:
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L26
call _ZSt16__throw_bad_castv@PLT
.L26:
call __stack_chk_fail@PLT
.L17:
movq %r15, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r15), %rax
movl $10, %esi
movq %r15, %rdi
call *48(%rax)
movl %eax, %esi
.L18:
movsbl %sil, %esi
movq %r14, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
addl $1, %ebp
.L14:
addq $1, %rbx
cmpq $10000000, %rbx
je .L27
.L19:
movq 16(%rsp), %rax
movl (%rax,%rbx,4), %eax
movq 8(%rsp), %rdx
addl (%rdx,%rbx,4), %eax
movq 24(%rsp), %rdx
cmpl %eax, (%rdx,%rbx,4)
je .L14
movl %ebx, %esi
movq %r13, %rdi
call _ZNSolsEi@PLT
movq %rax, %r14
movl $23, %edx
movq %r12, %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq (%r14), %rax
movq -24(%rax), %rax
movq 240(%r14,%rax), %r15
testq %r15, %r15
je .L28
cmpb $0, 56(%r15)
je .L17
movzbl 67(%r15), %esi
jmp .L18
.L27:
testl %ebp, %ebp
je .L29
.L20:
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L30
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L29:
.cfi_restore_state
leaq .LC3(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
jmp .L20
.L30:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size main, .-main
.section .rodata.str1.1
.LC4:
.string "_Z3addiPiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z3addiPiS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "add-blockthreads.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z18__device_stub__addiPiS_S_ # -- Begin function _Z18__device_stub__addiPiS_S_
.p2align 4, 0x90
.type _Z18__device_stub__addiPiS_S_,@function
_Z18__device_stub__addiPiS_S_: # @_Z18__device_stub__addiPiS_S_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 4(%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 64(%rsp)
movq %rcx, 56(%rsp)
leaq 4(%rsp), %rax
movq %rax, 80(%rsp)
leaq 72(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 56(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3addiPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z18__device_stub__addiPiS_S_, .Lfunc_end0-_Z18__device_stub__addiPiS_S_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $152, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $6, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl $114, %esi
callq _ZNSo9_M_insertImEERSoT_
movq %rax, %rbx
movl $.L.str.1, %esi
movl $3, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%rbx), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r14
testq %r14, %r14
je .LBB1_23
# %bb.1: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%r14)
je .LBB1_3
# %bb.2:
movzbl 67(%r14), %eax
jmp .LBB1_4
.LBB1_3:
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_4: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movq %rbx, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
leaq 16(%rsp), %rdi
movl $40000000, %esi # imm = 0x2625A00
movl $1, %edx
callq hipMallocManaged
leaq 8(%rsp), %rdi
movl $40000000, %esi # imm = 0x2625A00
movl $1, %edx
callq hipMallocManaged
leaq 32(%rsp), %rdi
movl $40000000, %esi # imm = 0x2625A00
movl $1, %edx
callq hipMallocManaged
movq 16(%rsp), %rax
xorl %ecx, %ecx
movq 8(%rsp), %rdx
xorl %esi, %esi
.p2align 4, 0x90
.LBB1_5: # =>This Inner Loop Header: Depth=1
movl %esi, (%rax,%rsi,4)
movl %ecx, (%rdx,%rsi,4)
incq %rsi
addl $2, %ecx
cmpq $10000000, %rsi # imm = 0x989680
jne .LBB1_5
# %bb.6:
movabsq $4294967328, %rdx # imm = 0x100000020
leaq 968(%rdx), %rdi
xorl %r12d, %r12d
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_8
# %bb.7:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq 32(%rsp), %rdx
movl $10000000, 28(%rsp) # imm = 0x989680
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
leaq 28(%rsp), %rax
movq %rax, 112(%rsp)
leaq 104(%rsp), %rax
movq %rax, 120(%rsp)
leaq 96(%rsp), %rax
movq %rax, 128(%rsp)
leaq 88(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z3addiPiS_S_, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_8:
callq hipDeviceSynchronize
xorl %ebx, %ebx
jmp .LBB1_9
.LBB1_13: # in Loop: Header=BB1_9 Depth=1
movq %r15, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_14: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit24
# in Loop: Header=BB1_9 Depth=1
movsbl %al, %esi
movq %r14, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
incl %r12d
.LBB1_15: # in Loop: Header=BB1_9 Depth=1
incq %rbx
cmpq $10000000, %rbx # imm = 0x989680
je .LBB1_16
.LBB1_9: # =>This Inner Loop Header: Depth=1
movq 32(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movl (%rdx,%rbx,4), %edx
addl (%rcx,%rbx,4), %edx
cmpl %edx, (%rax,%rbx,4)
je .LBB1_15
# %bb.10: # in Loop: Header=BB1_9 Depth=1
movl $_ZSt4cout, %edi
movl %ebx, %esi
callq _ZNSolsEi
movq %rax, %r14
movl $.L.str.2, %esi
movl $23, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%r14), %rax
movq -24(%rax), %rax
movq 240(%r14,%rax), %r15
testq %r15, %r15
je .LBB1_23
# %bb.11: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i21
# in Loop: Header=BB1_9 Depth=1
cmpb $0, 56(%r15)
je .LBB1_13
# %bb.12: # in Loop: Header=BB1_9 Depth=1
movzbl 67(%r15), %eax
jmp .LBB1_14
.LBB1_16:
testl %r12d, %r12d
jne .LBB1_22
# %bb.17:
movl $_ZSt4cout, %edi
movl $.L.str.3, %esi
movl $9, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB1_23
# %bb.18: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i26
cmpb $0, 56(%rbx)
je .LBB1_20
# %bb.19:
movzbl 67(%rbx), %eax
jmp .LBB1_21
.LBB1_20:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_21: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit29
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
.LBB1_22:
xorl %eax, %eax
addq $152, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB1_23:
.cfi_def_cfa_offset 192
callq _ZSt16__throw_bad_castv
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3addiPiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3addiPiS_S_,@object # @_Z3addiPiS_S_
.section .rodata,"a",@progbits
.globl _Z3addiPiS_S_
.p2align 3, 0x0
_Z3addiPiS_S_:
.quad _Z18__device_stub__addiPiS_S_
.size _Z3addiPiS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Size: "
.size .L.str, 7
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz " MB"
.size .L.str.1, 4
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz " did not add correctly!"
.size .L.str.2, 24
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "All good!"
.size .L.str.3, 10
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z3addiPiS_S_"
.size .L__unnamed_1, 14
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__addiPiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3addiPiS_S_
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void cleanCopy(int *S, int *D){
D[threadIdx.x] = S[threadIdx.x];
} | code for sm_80
Function : _Z9cleanCopyPiS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_TID.X ; /* 0x0000000000047919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0040*/ IMAD.WIDE.U32 R2, R4, R5, c[0x0][0x160] ; /* 0x0000580004027625 */
/* 0x001fcc00078e0005 */
/*0050*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*0060*/ IMAD.WIDE.U32 R4, R4, R5, c[0x0][0x168] ; /* 0x00005a0004047625 */
/* 0x000fca00078e0005 */
/*0070*/ STG.E [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x004fe2000c101904 */
/*0080*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0090*/ BRA 0x90; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void cleanCopy(int *S, int *D){
D[threadIdx.x] = S[threadIdx.x];
} | .file "tmpxft_001aef96_00000000-6_cleanCopy.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z30__device_stub__Z9cleanCopyPiS_PiS_
.type _Z30__device_stub__Z9cleanCopyPiS_PiS_, @function
_Z30__device_stub__Z9cleanCopyPiS_PiS_:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z9cleanCopyPiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z30__device_stub__Z9cleanCopyPiS_PiS_, .-_Z30__device_stub__Z9cleanCopyPiS_PiS_
.globl _Z9cleanCopyPiS_
.type _Z9cleanCopyPiS_, @function
_Z9cleanCopyPiS_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z9cleanCopyPiS_PiS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z9cleanCopyPiS_, .-_Z9cleanCopyPiS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z9cleanCopyPiS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z9cleanCopyPiS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void cleanCopy(int *S, int *D){
D[threadIdx.x] = S[threadIdx.x];
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void cleanCopy(int *S, int *D){
D[threadIdx.x] = S[threadIdx.x];
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void cleanCopy(int *S, int *D){
D[threadIdx.x] = S[threadIdx.x];
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9cleanCopyPiS_
.globl _Z9cleanCopyPiS_
.p2align 8
.type _Z9cleanCopyPiS_,@function
_Z9cleanCopyPiS_:
s_load_b128 s[0:3], s[0:1], 0x0
v_lshlrev_b32_e32 v0, 2, v0
s_waitcnt lgkmcnt(0)
global_load_b32 v1, v0, s[0:1]
s_waitcnt vmcnt(0)
global_store_b32 v0, v1, s[2:3]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9cleanCopyPiS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 16
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 4
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9cleanCopyPiS_, .Lfunc_end0-_Z9cleanCopyPiS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 16
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9cleanCopyPiS_
.private_segment_fixed_size: 0
.sgpr_count: 4
.sgpr_spill_count: 0
.symbol: _Z9cleanCopyPiS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void cleanCopy(int *S, int *D){
D[threadIdx.x] = S[threadIdx.x];
} | .text
.file "cleanCopy.hip"
.globl _Z24__device_stub__cleanCopyPiS_ # -- Begin function _Z24__device_stub__cleanCopyPiS_
.p2align 4, 0x90
.type _Z24__device_stub__cleanCopyPiS_,@function
_Z24__device_stub__cleanCopyPiS_: # @_Z24__device_stub__cleanCopyPiS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z9cleanCopyPiS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z24__device_stub__cleanCopyPiS_, .Lfunc_end0-_Z24__device_stub__cleanCopyPiS_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9cleanCopyPiS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9cleanCopyPiS_,@object # @_Z9cleanCopyPiS_
.section .rodata,"a",@progbits
.globl _Z9cleanCopyPiS_
.p2align 3, 0x0
_Z9cleanCopyPiS_:
.quad _Z24__device_stub__cleanCopyPiS_
.size _Z9cleanCopyPiS_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z9cleanCopyPiS_"
.size .L__unnamed_1, 17
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__cleanCopyPiS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9cleanCopyPiS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z9cleanCopyPiS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_TID.X ; /* 0x0000000000047919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0040*/ IMAD.WIDE.U32 R2, R4, R5, c[0x0][0x160] ; /* 0x0000580004027625 */
/* 0x001fcc00078e0005 */
/*0050*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*0060*/ IMAD.WIDE.U32 R4, R4, R5, c[0x0][0x168] ; /* 0x00005a0004047625 */
/* 0x000fca00078e0005 */
/*0070*/ STG.E [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x004fe2000c101904 */
/*0080*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0090*/ BRA 0x90; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9cleanCopyPiS_
.globl _Z9cleanCopyPiS_
.p2align 8
.type _Z9cleanCopyPiS_,@function
_Z9cleanCopyPiS_:
s_load_b128 s[0:3], s[0:1], 0x0
v_lshlrev_b32_e32 v0, 2, v0
s_waitcnt lgkmcnt(0)
global_load_b32 v1, v0, s[0:1]
s_waitcnt vmcnt(0)
global_store_b32 v0, v1, s[2:3]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9cleanCopyPiS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 16
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 4
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9cleanCopyPiS_, .Lfunc_end0-_Z9cleanCopyPiS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 16
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9cleanCopyPiS_
.private_segment_fixed_size: 0
.sgpr_count: 4
.sgpr_spill_count: 0
.symbol: _Z9cleanCopyPiS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001aef96_00000000-6_cleanCopy.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z30__device_stub__Z9cleanCopyPiS_PiS_
.type _Z30__device_stub__Z9cleanCopyPiS_PiS_, @function
_Z30__device_stub__Z9cleanCopyPiS_PiS_:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z9cleanCopyPiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z30__device_stub__Z9cleanCopyPiS_PiS_, .-_Z30__device_stub__Z9cleanCopyPiS_PiS_
.globl _Z9cleanCopyPiS_
.type _Z9cleanCopyPiS_, @function
_Z9cleanCopyPiS_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z9cleanCopyPiS_PiS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z9cleanCopyPiS_, .-_Z9cleanCopyPiS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z9cleanCopyPiS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z9cleanCopyPiS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "cleanCopy.hip"
.globl _Z24__device_stub__cleanCopyPiS_ # -- Begin function _Z24__device_stub__cleanCopyPiS_
.p2align 4, 0x90
.type _Z24__device_stub__cleanCopyPiS_,@function
_Z24__device_stub__cleanCopyPiS_: # @_Z24__device_stub__cleanCopyPiS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z9cleanCopyPiS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z24__device_stub__cleanCopyPiS_, .Lfunc_end0-_Z24__device_stub__cleanCopyPiS_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9cleanCopyPiS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9cleanCopyPiS_,@object # @_Z9cleanCopyPiS_
.section .rodata,"a",@progbits
.globl _Z9cleanCopyPiS_
.p2align 3, 0x0
_Z9cleanCopyPiS_:
.quad _Z24__device_stub__cleanCopyPiS_
.size _Z9cleanCopyPiS_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z9cleanCopyPiS_"
.size .L__unnamed_1, 17
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__cleanCopyPiS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9cleanCopyPiS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <stdio.h>
__global__ void add(int *a,int *b,int*c){
int tid = threadIdx.x;
c[tid] = a[tid] + b[tid];
}
int main(void){
int n,a[1000],b[1000],c[1000],i,size,*d_a,*d_b,*d_c;
printf("Enter no. of elements:\n");
scanf("%d",&n);
for(i=0;i<n;i++){
a[i] = i;
b[i] = i*2;
}
size = sizeof(int);
cudaMalloc((void **)&d_a,size*n);
cudaMalloc((void **)&d_b,size*n);
cudaMalloc((void **)&d_c,size*n);
cudaMemcpy(d_a,a,size*n,cudaMemcpyHostToDevice);
cudaMemcpy(d_b,b,size*n,cudaMemcpyHostToDevice);
add <<<1,n>>> (d_a,d_b,d_c);
cudaMemcpy(c,d_c,size*n,cudaMemcpyDeviceToHost);
for(i=0;i<n;i++)
printf("%d\t",c[i]);
cudaFree(d_a);
cudaFree(d_b);
cudaFree(d_c);
return 0;
} | code for sm_80
Function : _Z3addPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0040*/ IMAD.WIDE R2, R6, R7, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x001fc800078e0207 */
/*0050*/ IMAD.WIDE R4, R6.reuse, R7.reuse, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x0c0fe400078e0207 */
/*0060*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*0070*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*0080*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fe200078e0207 */
/*0090*/ IADD3 R9, R2, R5, RZ ; /* 0x0000000502097210 */
/* 0x004fca0007ffe0ff */
/*00a0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00c0*/ BRA 0xc0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <stdio.h>
__global__ void add(int *a,int *b,int*c){
int tid = threadIdx.x;
c[tid] = a[tid] + b[tid];
}
int main(void){
int n,a[1000],b[1000],c[1000],i,size,*d_a,*d_b,*d_c;
printf("Enter no. of elements:\n");
scanf("%d",&n);
for(i=0;i<n;i++){
a[i] = i;
b[i] = i*2;
}
size = sizeof(int);
cudaMalloc((void **)&d_a,size*n);
cudaMalloc((void **)&d_b,size*n);
cudaMalloc((void **)&d_c,size*n);
cudaMemcpy(d_a,a,size*n,cudaMemcpyHostToDevice);
cudaMemcpy(d_b,b,size*n,cudaMemcpyHostToDevice);
add <<<1,n>>> (d_a,d_b,d_c);
cudaMemcpy(c,d_c,size*n,cudaMemcpyDeviceToHost);
for(i=0;i<n;i++)
printf("%d\t",c[i]);
cudaFree(d_a);
cudaFree(d_b);
cudaFree(d_c);
return 0;
} | .file "tmpxft_000ee483_00000000-6_array_add.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z26__device_stub__Z3addPiS_S_PiS_S_
.type _Z26__device_stub__Z3addPiS_S_PiS_S_, @function
_Z26__device_stub__Z3addPiS_S_PiS_S_:
.LFB2082:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3addPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z26__device_stub__Z3addPiS_S_PiS_S_, .-_Z26__device_stub__Z3addPiS_S_PiS_S_
.globl _Z3addPiS_S_
.type _Z3addPiS_S_, @function
_Z3addPiS_S_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z3addPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z3addPiS_S_, .-_Z3addPiS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Enter no. of elements:\n"
.LC1:
.string "%d"
.LC2:
.string "%d\t"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $4096, %rsp
.cfi_def_cfa_offset 4120
orq $0, (%rsp)
subq $4096, %rsp
.cfi_def_cfa_offset 8216
orq $0, (%rsp)
subq $3896, %rsp
.cfi_def_cfa_offset 12112
movq %fs:40, %rax
movq %rax, 12072(%rsp)
xorl %eax, %eax
leaq .LC0(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
leaq 12(%rsp), %rsi
leaq .LC1(%rip), %rdi
movl $0, %eax
call __isoc23_scanf@PLT
movl 12(%rsp), %esi
testl %esi, %esi
jle .L12
movslq %esi, %rcx
movl $0, %eax
.L13:
movl %eax, 64(%rsp,%rax,4)
leal (%rax,%rax), %edx
movl %edx, 4064(%rsp,%rax,4)
addq $1, %rax
cmpq %rcx, %rax
jne .L13
.L12:
sall $2, %esi
movslq %esi, %rsi
leaq 16(%rsp), %rdi
call cudaMalloc@PLT
movl 12(%rsp), %eax
leal 0(,%rax,4), %esi
movslq %esi, %rsi
leaq 24(%rsp), %rdi
call cudaMalloc@PLT
movl 12(%rsp), %eax
leal 0(,%rax,4), %esi
movslq %esi, %rsi
leaq 32(%rsp), %rdi
call cudaMalloc@PLT
movl 12(%rsp), %eax
leal 0(,%rax,4), %edx
movslq %edx, %rdx
leaq 64(%rsp), %rsi
movl $1, %ecx
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl 12(%rsp), %eax
leal 0(,%rax,4), %edx
movslq %edx, %rdx
leaq 4064(%rsp), %rsi
movl $1, %ecx
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl 12(%rsp), %eax
movl %eax, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 52(%rsp), %rdx
movl $1, %ecx
movq 40(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L21
.L14:
movl 12(%rsp), %eax
leal 0(,%rax,4), %edx
movslq %edx, %rdx
leaq 8064(%rsp), %rdi
movl $2, %ecx
movq 32(%rsp), %rsi
call cudaMemcpy@PLT
cmpl $0, 12(%rsp)
jle .L15
movl $0, %ebx
leaq .LC2(%rip), %rbp
.L16:
movl 8064(%rsp,%rbx,4), %edx
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpl %ebx, 12(%rsp)
jg .L16
.L15:
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 12072(%rsp), %rax
subq %fs:40, %rax
jne .L22
movl $0, %eax
addq $12088, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L21:
.cfi_restore_state
movq 32(%rsp), %rdx
movq 24(%rsp), %rsi
movq 16(%rsp), %rdi
call _Z26__device_stub__Z3addPiS_S_PiS_S_
jmp .L14
.L22:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC3:
.string "_Z3addPiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z3addPiS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <stdio.h>
__global__ void add(int *a,int *b,int*c){
int tid = threadIdx.x;
c[tid] = a[tid] + b[tid];
}
int main(void){
int n,a[1000],b[1000],c[1000],i,size,*d_a,*d_b,*d_c;
printf("Enter no. of elements:\n");
scanf("%d",&n);
for(i=0;i<n;i++){
a[i] = i;
b[i] = i*2;
}
size = sizeof(int);
cudaMalloc((void **)&d_a,size*n);
cudaMalloc((void **)&d_b,size*n);
cudaMalloc((void **)&d_c,size*n);
cudaMemcpy(d_a,a,size*n,cudaMemcpyHostToDevice);
cudaMemcpy(d_b,b,size*n,cudaMemcpyHostToDevice);
add <<<1,n>>> (d_a,d_b,d_c);
cudaMemcpy(c,d_c,size*n,cudaMemcpyDeviceToHost);
for(i=0;i<n;i++)
printf("%d\t",c[i]);
cudaFree(d_a);
cudaFree(d_b);
cudaFree(d_c);
return 0;
} | #include "hip/hip_runtime.h"
#include <stdio.h>
__global__ void add(int *a,int *b,int*c){
int tid = threadIdx.x;
c[tid] = a[tid] + b[tid];
}
int main(void){
int n,a[1000],b[1000],c[1000],i,size,*d_a,*d_b,*d_c;
printf("Enter no. of elements:\n");
scanf("%d",&n);
for(i=0;i<n;i++){
a[i] = i;
b[i] = i*2;
}
size = sizeof(int);
hipMalloc((void **)&d_a,size*n);
hipMalloc((void **)&d_b,size*n);
hipMalloc((void **)&d_c,size*n);
hipMemcpy(d_a,a,size*n,hipMemcpyHostToDevice);
hipMemcpy(d_b,b,size*n,hipMemcpyHostToDevice);
add <<<1,n>>> (d_a,d_b,d_c);
hipMemcpy(c,d_c,size*n,hipMemcpyDeviceToHost);
for(i=0;i<n;i++)
printf("%d\t",c[i]);
hipFree(d_a);
hipFree(d_b);
hipFree(d_c);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include "hip/hip_runtime.h"
#include <stdio.h>
__global__ void add(int *a,int *b,int*c){
int tid = threadIdx.x;
c[tid] = a[tid] + b[tid];
}
int main(void){
int n,a[1000],b[1000],c[1000],i,size,*d_a,*d_b,*d_c;
printf("Enter no. of elements:\n");
scanf("%d",&n);
for(i=0;i<n;i++){
a[i] = i;
b[i] = i*2;
}
size = sizeof(int);
hipMalloc((void **)&d_a,size*n);
hipMalloc((void **)&d_b,size*n);
hipMalloc((void **)&d_c,size*n);
hipMemcpy(d_a,a,size*n,hipMemcpyHostToDevice);
hipMemcpy(d_b,b,size*n,hipMemcpyHostToDevice);
add <<<1,n>>> (d_a,d_b,d_c);
hipMemcpy(c,d_c,size*n,hipMemcpyDeviceToHost);
for(i=0;i<n;i++)
printf("%d\t",c[i]);
hipFree(d_a);
hipFree(d_b);
hipFree(d_c);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3addPiS_S_
.globl _Z3addPiS_S_
.p2align 8
.type _Z3addPiS_S_,@function
_Z3addPiS_S_:
s_load_b128 s[4:7], s[0:1], 0x0
v_lshlrev_b32_e32 v0, 2, v0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_load_b32 v1, v0, s[4:5]
global_load_b32 v2, v0, s[6:7]
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v1, v2, v1
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3addPiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 8
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3addPiS_S_, .Lfunc_end0-_Z3addPiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3addPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 8
.sgpr_spill_count: 0
.symbol: _Z3addPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include "hip/hip_runtime.h"
#include <stdio.h>
__global__ void add(int *a,int *b,int*c){
int tid = threadIdx.x;
c[tid] = a[tid] + b[tid];
}
int main(void){
int n,a[1000],b[1000],c[1000],i,size,*d_a,*d_b,*d_c;
printf("Enter no. of elements:\n");
scanf("%d",&n);
for(i=0;i<n;i++){
a[i] = i;
b[i] = i*2;
}
size = sizeof(int);
hipMalloc((void **)&d_a,size*n);
hipMalloc((void **)&d_b,size*n);
hipMalloc((void **)&d_c,size*n);
hipMemcpy(d_a,a,size*n,hipMemcpyHostToDevice);
hipMemcpy(d_b,b,size*n,hipMemcpyHostToDevice);
add <<<1,n>>> (d_a,d_b,d_c);
hipMemcpy(c,d_c,size*n,hipMemcpyDeviceToHost);
for(i=0;i<n;i++)
printf("%d\t",c[i]);
hipFree(d_a);
hipFree(d_b);
hipFree(d_c);
return 0;
} | .text
.file "array_add.hip"
.globl _Z18__device_stub__addPiS_S_ # -- Begin function _Z18__device_stub__addPiS_S_
.p2align 4, 0x90
.type _Z18__device_stub__addPiS_S_,@function
_Z18__device_stub__addPiS_S_: # @_Z18__device_stub__addPiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3addPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z18__device_stub__addPiS_S_, .Lfunc_end0-_Z18__device_stub__addPiS_S_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $12112, %rsp # imm = 0x2F50
.cfi_def_cfa_offset 12128
.cfi_offset %rbx, -16
movl $.Lstr, %edi
callq puts@PLT
xorl %ebx, %ebx
leaq 12(%rsp), %rsi
movl $.L.str.1, %edi
xorl %eax, %eax
callq __isoc23_scanf
movl 12(%rsp), %eax
testl %eax, %eax
jle .LBB1_3
# %bb.1: # %.lr.ph.preheader
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl %ecx, 8112(%rsp,%rcx,4)
movl %ebx, 4112(%rsp,%rcx,4)
incq %rcx
addl $2, %ebx
cmpq %rcx, %rax
jne .LBB1_2
.LBB1_3: # %._crit_edge
shll $2, %eax
movslq %eax, %rsi
leaq 32(%rsp), %rdi
callq hipMalloc
movslq 12(%rsp), %rsi
shlq $2, %rsi
leaq 24(%rsp), %rdi
callq hipMalloc
movslq 12(%rsp), %rsi
shlq $2, %rsi
leaq 16(%rsp), %rdi
callq hipMalloc
movq 32(%rsp), %rdi
movslq 12(%rsp), %rdx
shlq $2, %rdx
leaq 8112(%rsp), %rsi
movl $1, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
movslq 12(%rsp), %rdx
shlq $2, %rdx
leaq 4112(%rsp), %rsi
movl $1, %ecx
callq hipMemcpy
movl 12(%rsp), %edx
movabsq $4294967296, %rdi # imm = 0x100000000
orq %rdi, %rdx
orq $1, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_5
# %bb.4:
movq 32(%rsp), %rax
movq 24(%rsp), %rcx
movq 16(%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z3addPiS_S_, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_5:
movq 16(%rsp), %rsi
movslq 12(%rsp), %rdx
shlq $2, %rdx
leaq 112(%rsp), %rdi
movl $2, %ecx
callq hipMemcpy
cmpl $0, 12(%rsp)
jle .LBB1_8
# %bb.6: # %.lr.ph24.preheader
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_7: # %.lr.ph24
# =>This Inner Loop Header: Depth=1
movl 112(%rsp,%rbx,4), %esi
movl $.L.str.2, %edi
xorl %eax, %eax
callq printf
incq %rbx
movslq 12(%rsp), %rax
cmpq %rax, %rbx
jl .LBB1_7
.LBB1_8: # %._crit_edge25
movq 32(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $12112, %rsp # imm = 0x2F50
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3addPiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3addPiS_S_,@object # @_Z3addPiS_S_
.section .rodata,"a",@progbits
.globl _Z3addPiS_S_
.p2align 3, 0x0
_Z3addPiS_S_:
.quad _Z18__device_stub__addPiS_S_
.size _Z3addPiS_S_, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "%d"
.size .L.str.1, 3
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "%d\t"
.size .L.str.2, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z3addPiS_S_"
.size .L__unnamed_1, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Enter no. of elements:"
.size .Lstr, 23
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__addPiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3addPiS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z3addPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0040*/ IMAD.WIDE R2, R6, R7, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x001fc800078e0207 */
/*0050*/ IMAD.WIDE R4, R6.reuse, R7.reuse, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x0c0fe400078e0207 */
/*0060*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*0070*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*0080*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fe200078e0207 */
/*0090*/ IADD3 R9, R2, R5, RZ ; /* 0x0000000502097210 */
/* 0x004fca0007ffe0ff */
/*00a0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00c0*/ BRA 0xc0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3addPiS_S_
.globl _Z3addPiS_S_
.p2align 8
.type _Z3addPiS_S_,@function
_Z3addPiS_S_:
s_load_b128 s[4:7], s[0:1], 0x0
v_lshlrev_b32_e32 v0, 2, v0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_load_b32 v1, v0, s[4:5]
global_load_b32 v2, v0, s[6:7]
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v1, v2, v1
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3addPiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 8
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3addPiS_S_, .Lfunc_end0-_Z3addPiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3addPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 8
.sgpr_spill_count: 0
.symbol: _Z3addPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000ee483_00000000-6_array_add.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z26__device_stub__Z3addPiS_S_PiS_S_
.type _Z26__device_stub__Z3addPiS_S_PiS_S_, @function
_Z26__device_stub__Z3addPiS_S_PiS_S_:
.LFB2082:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3addPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z26__device_stub__Z3addPiS_S_PiS_S_, .-_Z26__device_stub__Z3addPiS_S_PiS_S_
.globl _Z3addPiS_S_
.type _Z3addPiS_S_, @function
_Z3addPiS_S_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z3addPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z3addPiS_S_, .-_Z3addPiS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Enter no. of elements:\n"
.LC1:
.string "%d"
.LC2:
.string "%d\t"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $4096, %rsp
.cfi_def_cfa_offset 4120
orq $0, (%rsp)
subq $4096, %rsp
.cfi_def_cfa_offset 8216
orq $0, (%rsp)
subq $3896, %rsp
.cfi_def_cfa_offset 12112
movq %fs:40, %rax
movq %rax, 12072(%rsp)
xorl %eax, %eax
leaq .LC0(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
leaq 12(%rsp), %rsi
leaq .LC1(%rip), %rdi
movl $0, %eax
call __isoc23_scanf@PLT
movl 12(%rsp), %esi
testl %esi, %esi
jle .L12
movslq %esi, %rcx
movl $0, %eax
.L13:
movl %eax, 64(%rsp,%rax,4)
leal (%rax,%rax), %edx
movl %edx, 4064(%rsp,%rax,4)
addq $1, %rax
cmpq %rcx, %rax
jne .L13
.L12:
sall $2, %esi
movslq %esi, %rsi
leaq 16(%rsp), %rdi
call cudaMalloc@PLT
movl 12(%rsp), %eax
leal 0(,%rax,4), %esi
movslq %esi, %rsi
leaq 24(%rsp), %rdi
call cudaMalloc@PLT
movl 12(%rsp), %eax
leal 0(,%rax,4), %esi
movslq %esi, %rsi
leaq 32(%rsp), %rdi
call cudaMalloc@PLT
movl 12(%rsp), %eax
leal 0(,%rax,4), %edx
movslq %edx, %rdx
leaq 64(%rsp), %rsi
movl $1, %ecx
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl 12(%rsp), %eax
leal 0(,%rax,4), %edx
movslq %edx, %rdx
leaq 4064(%rsp), %rsi
movl $1, %ecx
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl 12(%rsp), %eax
movl %eax, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 52(%rsp), %rdx
movl $1, %ecx
movq 40(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L21
.L14:
movl 12(%rsp), %eax
leal 0(,%rax,4), %edx
movslq %edx, %rdx
leaq 8064(%rsp), %rdi
movl $2, %ecx
movq 32(%rsp), %rsi
call cudaMemcpy@PLT
cmpl $0, 12(%rsp)
jle .L15
movl $0, %ebx
leaq .LC2(%rip), %rbp
.L16:
movl 8064(%rsp,%rbx,4), %edx
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpl %ebx, 12(%rsp)
jg .L16
.L15:
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 12072(%rsp), %rax
subq %fs:40, %rax
jne .L22
movl $0, %eax
addq $12088, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L21:
.cfi_restore_state
movq 32(%rsp), %rdx
movq 24(%rsp), %rsi
movq 16(%rsp), %rdi
call _Z26__device_stub__Z3addPiS_S_PiS_S_
jmp .L14
.L22:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC3:
.string "_Z3addPiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z3addPiS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "array_add.hip"
.globl _Z18__device_stub__addPiS_S_ # -- Begin function _Z18__device_stub__addPiS_S_
.p2align 4, 0x90
.type _Z18__device_stub__addPiS_S_,@function
_Z18__device_stub__addPiS_S_: # @_Z18__device_stub__addPiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3addPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z18__device_stub__addPiS_S_, .Lfunc_end0-_Z18__device_stub__addPiS_S_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $12112, %rsp # imm = 0x2F50
.cfi_def_cfa_offset 12128
.cfi_offset %rbx, -16
movl $.Lstr, %edi
callq puts@PLT
xorl %ebx, %ebx
leaq 12(%rsp), %rsi
movl $.L.str.1, %edi
xorl %eax, %eax
callq __isoc23_scanf
movl 12(%rsp), %eax
testl %eax, %eax
jle .LBB1_3
# %bb.1: # %.lr.ph.preheader
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl %ecx, 8112(%rsp,%rcx,4)
movl %ebx, 4112(%rsp,%rcx,4)
incq %rcx
addl $2, %ebx
cmpq %rcx, %rax
jne .LBB1_2
.LBB1_3: # %._crit_edge
shll $2, %eax
movslq %eax, %rsi
leaq 32(%rsp), %rdi
callq hipMalloc
movslq 12(%rsp), %rsi
shlq $2, %rsi
leaq 24(%rsp), %rdi
callq hipMalloc
movslq 12(%rsp), %rsi
shlq $2, %rsi
leaq 16(%rsp), %rdi
callq hipMalloc
movq 32(%rsp), %rdi
movslq 12(%rsp), %rdx
shlq $2, %rdx
leaq 8112(%rsp), %rsi
movl $1, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
movslq 12(%rsp), %rdx
shlq $2, %rdx
leaq 4112(%rsp), %rsi
movl $1, %ecx
callq hipMemcpy
movl 12(%rsp), %edx
movabsq $4294967296, %rdi # imm = 0x100000000
orq %rdi, %rdx
orq $1, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_5
# %bb.4:
movq 32(%rsp), %rax
movq 24(%rsp), %rcx
movq 16(%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z3addPiS_S_, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_5:
movq 16(%rsp), %rsi
movslq 12(%rsp), %rdx
shlq $2, %rdx
leaq 112(%rsp), %rdi
movl $2, %ecx
callq hipMemcpy
cmpl $0, 12(%rsp)
jle .LBB1_8
# %bb.6: # %.lr.ph24.preheader
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_7: # %.lr.ph24
# =>This Inner Loop Header: Depth=1
movl 112(%rsp,%rbx,4), %esi
movl $.L.str.2, %edi
xorl %eax, %eax
callq printf
incq %rbx
movslq 12(%rsp), %rax
cmpq %rax, %rbx
jl .LBB1_7
.LBB1_8: # %._crit_edge25
movq 32(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $12112, %rsp # imm = 0x2F50
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3addPiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3addPiS_S_,@object # @_Z3addPiS_S_
.section .rodata,"a",@progbits
.globl _Z3addPiS_S_
.p2align 3, 0x0
_Z3addPiS_S_:
.quad _Z18__device_stub__addPiS_S_
.size _Z3addPiS_S_, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "%d"
.size .L.str.1, 3
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "%d\t"
.size .L.str.2, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z3addPiS_S_"
.size .L__unnamed_1, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Enter no. of elements:"
.size .Lstr, 23
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__addPiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3addPiS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | //pass
//--blockDim=512 --gridDim=512
#include <cuda.h>
//////////////////////////////////////////////////////////////////////////////
//// THIS CODE AND INFORMATION IS PROVIDED "AS IS" WITHOUT WARRANTY OF
//// ANY KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING BUT NOT LIMITED TO
//// THE IMPLIED WARRANTIES OF MERCHANTABILITY AND/OR FITNESS FOR A
//// PARTICULAR PURPOSE.
////
//// Copyright (c) Microsoft Corporation. All rights reserved
//////////////////////////////////////////////////////////////////////////////
// Original kernels are templated. We will check the float case.
#define _type float
//----------------------------------------------------------------------------
// File: BitonicSort.cpp
//
// Implements Bitonic sort in C++ AMP
// Supports only int, unsigned, long and unsigned long
//----------------------------------------------------------------------------
#define BITONIC_TILE_SIZE 512
// Should be a square matrix
#define NUM_ELEMENTS (BITONIC_TILE_SIZE * BITONIC_TILE_SIZE)
#define MATRIX_WIDTH BITONIC_TILE_SIZE
#define MATRIX_HEIGHT BITONIC_TILE_SIZE
// Should be divisible by MATRIX_WIDTH and MATRIX_HEIGHT
// else parallel_for_each will crash
#define TRANSPOSE_TILE_SIZE 16
//----------------------------------------------------------------------------
// Kernel implements partial sorting on accelerator, BITONIC_TILE_SIZE at a time
//----------------------------------------------------------------------------
__global__ void bitonic_sort_kernel(_type* data, unsigned ulevel, unsigned ulevelmask)
{
__shared__ _type sh_data[BITONIC_TILE_SIZE];
int local_idx = threadIdx.x;
int global_idx = blockIdx.x*blockDim.x + threadIdx.x;
// Cooperatively load data - each thread will load data from global memory
// into tile_static
sh_data[local_idx] = data[global_idx];
// Wait till all threads have loaded their portion of data
#ifndef MUTATION
/* BUGINJECT: REMOVE_BARRIER, DOWN */
__syncthreads();
#endif
// Sort data in tile_static memory
for (unsigned int j = ulevel >> 1 ;
j > 0 ; j >>= 1)
{
_type result = ((sh_data[local_idx & ~j] <= sh_data[local_idx | j]) == (bool)(ulevelmask & global_idx)) ? sh_data[local_idx ^ j] : sh_data[local_idx];
__syncthreads();
sh_data[local_idx] = result;
__syncthreads();
}
// Store shared data
data[global_idx] = sh_data[local_idx];
} | code for sm_80
Function : _Z19bitonic_sort_kernelPfjj
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R7, SR_TID.X ; /* 0x0000000000077919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R7 ; /* 0x0000000000007a24 */
/* 0x001fc800078e0207 */
/*0060*/ IMAD.WIDE R2, R0, R3, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fca00078e0203 */
/*0070*/ LDG.E R4, [R2.64] ; /* 0x0000000602047981 */
/* 0x000ea2000c1e1900 */
/*0080*/ ULDC UR4, c[0x0][0x168] ; /* 0x00005a0000047ab9 */
/* 0x000fe40000000800 */
/*0090*/ USHF.R.U32.HI UR4, URZ, 0x1, UR4 ; /* 0x000000013f047899 */
/* 0x000fcc0008011604 */
/*00a0*/ ISETP.NE.AND P0, PT, RZ, UR4, PT ; /* 0x00000004ff007c0c */
/* 0x000fe2000bf05270 */
/*00b0*/ STS [R7.X4], R4 ; /* 0x0000000407007388 */
/* 0x0041e80000004800 */
/*00c0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000ff00000010000 */
/*00d0*/ @!P0 BRA 0x1e0 ; /* 0x0000010000008947 */
/* 0x000fea0003800000 */
/*00e0*/ LOP3.LUT P0, RZ, R0, c[0x0][0x16c], RZ, 0xc0, !PT ; /* 0x00005b0000ff7a12 */
/* 0x001fe2000780c0ff */
/*00f0*/ IMAD.U32 R0, RZ, RZ, UR4 ; /* 0x00000004ff007e24 */
/* 0x000fca000f8e00ff */
/*0100*/ LOP3.LUT R4, R7, R0, RZ, 0x30, !PT ; /* 0x0000000007047212 */
/* 0x000fe400078e30ff */
/*0110*/ LOP3.LUT R5, R0, R7, RZ, 0xfc, !PT ; /* 0x0000000700057212 */
/* 0x000fc800078efcff */
/*0120*/ LDS R4, [R4.X4] ; /* 0x0000000004047984 */
/* 0x000fe80000004800 */
/*0130*/ LDS R5, [R5.X4] ; /* 0x0000000005057984 */
/* 0x000e240000004800 */
/*0140*/ FSETP.LE.XOR P1, PT, R4, R5, P0 ; /* 0x000000050400720b */
/* 0x001fc80000723800 */
/*0150*/ SEL R6, R0, RZ, !P1 ; /* 0x000000ff00067207 */
/* 0x000fe40004800000 */
/*0160*/ SHF.R.U32.HI R0, RZ, 0x1, R0 ; /* 0x00000001ff007819 */
/* 0x000fe40000011600 */
/*0170*/ LOP3.LUT R6, R6, R7, RZ, 0x3c, !PT ; /* 0x0000000706067212 */
/* 0x000fe400078e3cff */
/*0180*/ ISETP.NE.AND P1, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fc80003f25270 */
/*0190*/ LDS R6, [R6.X4] ; /* 0x0000000006067984 */
/* 0x000e280000004800 */
/*01a0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*01b0*/ STS [R7.X4], R6 ; /* 0x0000000607007388 */
/* 0x0011e80000004800 */
/*01c0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*01d0*/ @P1 BRA 0x100 ; /* 0xffffff2000001947 */
/* 0x001fea000383ffff */
/*01e0*/ LDS R5, [R7.X4] ; /* 0x0000000007057984 */
/* 0x001e280000004800 */
/*01f0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x001fe2000c101906 */
/*0200*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0210*/ BRA 0x210; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | //pass
//--blockDim=512 --gridDim=512
#include <cuda.h>
//////////////////////////////////////////////////////////////////////////////
//// THIS CODE AND INFORMATION IS PROVIDED "AS IS" WITHOUT WARRANTY OF
//// ANY KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING BUT NOT LIMITED TO
//// THE IMPLIED WARRANTIES OF MERCHANTABILITY AND/OR FITNESS FOR A
//// PARTICULAR PURPOSE.
////
//// Copyright (c) Microsoft Corporation. All rights reserved
//////////////////////////////////////////////////////////////////////////////
// Original kernels are templated. We will check the float case.
#define _type float
//----------------------------------------------------------------------------
// File: BitonicSort.cpp
//
// Implements Bitonic sort in C++ AMP
// Supports only int, unsigned, long and unsigned long
//----------------------------------------------------------------------------
#define BITONIC_TILE_SIZE 512
// Should be a square matrix
#define NUM_ELEMENTS (BITONIC_TILE_SIZE * BITONIC_TILE_SIZE)
#define MATRIX_WIDTH BITONIC_TILE_SIZE
#define MATRIX_HEIGHT BITONIC_TILE_SIZE
// Should be divisible by MATRIX_WIDTH and MATRIX_HEIGHT
// else parallel_for_each will crash
#define TRANSPOSE_TILE_SIZE 16
//----------------------------------------------------------------------------
// Kernel implements partial sorting on accelerator, BITONIC_TILE_SIZE at a time
//----------------------------------------------------------------------------
__global__ void bitonic_sort_kernel(_type* data, unsigned ulevel, unsigned ulevelmask)
{
__shared__ _type sh_data[BITONIC_TILE_SIZE];
int local_idx = threadIdx.x;
int global_idx = blockIdx.x*blockDim.x + threadIdx.x;
// Cooperatively load data - each thread will load data from global memory
// into tile_static
sh_data[local_idx] = data[global_idx];
// Wait till all threads have loaded their portion of data
#ifndef MUTATION
/* BUGINJECT: REMOVE_BARRIER, DOWN */
__syncthreads();
#endif
// Sort data in tile_static memory
for (unsigned int j = ulevel >> 1 ;
j > 0 ; j >>= 1)
{
_type result = ((sh_data[local_idx & ~j] <= sh_data[local_idx | j]) == (bool)(ulevelmask & global_idx)) ? sh_data[local_idx ^ j] : sh_data[local_idx];
__syncthreads();
sh_data[local_idx] = result;
__syncthreads();
}
// Store shared data
data[global_idx] = sh_data[local_idx];
} | .file "tmpxft_00187ce4_00000000-6_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z41__device_stub__Z19bitonic_sort_kernelPfjjPfjj
.type _Z41__device_stub__Z19bitonic_sort_kernelPfjjPfjj, @function
_Z41__device_stub__Z19bitonic_sort_kernelPfjjPfjj:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z19bitonic_sort_kernelPfjj(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z41__device_stub__Z19bitonic_sort_kernelPfjjPfjj, .-_Z41__device_stub__Z19bitonic_sort_kernelPfjjPfjj
.globl _Z19bitonic_sort_kernelPfjj
.type _Z19bitonic_sort_kernelPfjj, @function
_Z19bitonic_sort_kernelPfjj:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z41__device_stub__Z19bitonic_sort_kernelPfjjPfjj
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z19bitonic_sort_kernelPfjj, .-_Z19bitonic_sort_kernelPfjj
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z19bitonic_sort_kernelPfjj"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z19bitonic_sort_kernelPfjj(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | //pass
//--blockDim=512 --gridDim=512
#include <cuda.h>
//////////////////////////////////////////////////////////////////////////////
//// THIS CODE AND INFORMATION IS PROVIDED "AS IS" WITHOUT WARRANTY OF
//// ANY KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING BUT NOT LIMITED TO
//// THE IMPLIED WARRANTIES OF MERCHANTABILITY AND/OR FITNESS FOR A
//// PARTICULAR PURPOSE.
////
//// Copyright (c) Microsoft Corporation. All rights reserved
//////////////////////////////////////////////////////////////////////////////
// Original kernels are templated. We will check the float case.
#define _type float
//----------------------------------------------------------------------------
// File: BitonicSort.cpp
//
// Implements Bitonic sort in C++ AMP
// Supports only int, unsigned, long and unsigned long
//----------------------------------------------------------------------------
#define BITONIC_TILE_SIZE 512
// Should be a square matrix
#define NUM_ELEMENTS (BITONIC_TILE_SIZE * BITONIC_TILE_SIZE)
#define MATRIX_WIDTH BITONIC_TILE_SIZE
#define MATRIX_HEIGHT BITONIC_TILE_SIZE
// Should be divisible by MATRIX_WIDTH and MATRIX_HEIGHT
// else parallel_for_each will crash
#define TRANSPOSE_TILE_SIZE 16
//----------------------------------------------------------------------------
// Kernel implements partial sorting on accelerator, BITONIC_TILE_SIZE at a time
//----------------------------------------------------------------------------
__global__ void bitonic_sort_kernel(_type* data, unsigned ulevel, unsigned ulevelmask)
{
__shared__ _type sh_data[BITONIC_TILE_SIZE];
int local_idx = threadIdx.x;
int global_idx = blockIdx.x*blockDim.x + threadIdx.x;
// Cooperatively load data - each thread will load data from global memory
// into tile_static
sh_data[local_idx] = data[global_idx];
// Wait till all threads have loaded their portion of data
#ifndef MUTATION
/* BUGINJECT: REMOVE_BARRIER, DOWN */
__syncthreads();
#endif
// Sort data in tile_static memory
for (unsigned int j = ulevel >> 1 ;
j > 0 ; j >>= 1)
{
_type result = ((sh_data[local_idx & ~j] <= sh_data[local_idx | j]) == (bool)(ulevelmask & global_idx)) ? sh_data[local_idx ^ j] : sh_data[local_idx];
__syncthreads();
sh_data[local_idx] = result;
__syncthreads();
}
// Store shared data
data[global_idx] = sh_data[local_idx];
} | //pass
//--blockDim=512 --gridDim=512
#include <hip/hip_runtime.h>
//////////////////////////////////////////////////////////////////////////////
//// THIS CODE AND INFORMATION IS PROVIDED "AS IS" WITHOUT WARRANTY OF
//// ANY KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING BUT NOT LIMITED TO
//// THE IMPLIED WARRANTIES OF MERCHANTABILITY AND/OR FITNESS FOR A
//// PARTICULAR PURPOSE.
////
//// Copyright (c) Microsoft Corporation. All rights reserved
//////////////////////////////////////////////////////////////////////////////
// Original kernels are templated. We will check the float case.
#define _type float
//----------------------------------------------------------------------------
// File: BitonicSort.cpp
//
// Implements Bitonic sort in C++ AMP
// Supports only int, unsigned, long and unsigned long
//----------------------------------------------------------------------------
#define BITONIC_TILE_SIZE 512
// Should be a square matrix
#define NUM_ELEMENTS (BITONIC_TILE_SIZE * BITONIC_TILE_SIZE)
#define MATRIX_WIDTH BITONIC_TILE_SIZE
#define MATRIX_HEIGHT BITONIC_TILE_SIZE
// Should be divisible by MATRIX_WIDTH and MATRIX_HEIGHT
// else parallel_for_each will crash
#define TRANSPOSE_TILE_SIZE 16
//----------------------------------------------------------------------------
// Kernel implements partial sorting on accelerator, BITONIC_TILE_SIZE at a time
//----------------------------------------------------------------------------
__global__ void bitonic_sort_kernel(_type* data, unsigned ulevel, unsigned ulevelmask)
{
__shared__ _type sh_data[BITONIC_TILE_SIZE];
int local_idx = threadIdx.x;
int global_idx = blockIdx.x*blockDim.x + threadIdx.x;
// Cooperatively load data - each thread will load data from global memory
// into tile_static
sh_data[local_idx] = data[global_idx];
// Wait till all threads have loaded their portion of data
#ifndef MUTATION
/* BUGINJECT: REMOVE_BARRIER, DOWN */
__syncthreads();
#endif
// Sort data in tile_static memory
for (unsigned int j = ulevel >> 1 ;
j > 0 ; j >>= 1)
{
_type result = ((sh_data[local_idx & ~j] <= sh_data[local_idx | j]) == (bool)(ulevelmask & global_idx)) ? sh_data[local_idx ^ j] : sh_data[local_idx];
__syncthreads();
sh_data[local_idx] = result;
__syncthreads();
}
// Store shared data
data[global_idx] = sh_data[local_idx];
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | //pass
//--blockDim=512 --gridDim=512
#include <hip/hip_runtime.h>
//////////////////////////////////////////////////////////////////////////////
//// THIS CODE AND INFORMATION IS PROVIDED "AS IS" WITHOUT WARRANTY OF
//// ANY KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING BUT NOT LIMITED TO
//// THE IMPLIED WARRANTIES OF MERCHANTABILITY AND/OR FITNESS FOR A
//// PARTICULAR PURPOSE.
////
//// Copyright (c) Microsoft Corporation. All rights reserved
//////////////////////////////////////////////////////////////////////////////
// Original kernels are templated. We will check the float case.
#define _type float
//----------------------------------------------------------------------------
// File: BitonicSort.cpp
//
// Implements Bitonic sort in C++ AMP
// Supports only int, unsigned, long and unsigned long
//----------------------------------------------------------------------------
#define BITONIC_TILE_SIZE 512
// Should be a square matrix
#define NUM_ELEMENTS (BITONIC_TILE_SIZE * BITONIC_TILE_SIZE)
#define MATRIX_WIDTH BITONIC_TILE_SIZE
#define MATRIX_HEIGHT BITONIC_TILE_SIZE
// Should be divisible by MATRIX_WIDTH and MATRIX_HEIGHT
// else parallel_for_each will crash
#define TRANSPOSE_TILE_SIZE 16
//----------------------------------------------------------------------------
// Kernel implements partial sorting on accelerator, BITONIC_TILE_SIZE at a time
//----------------------------------------------------------------------------
__global__ void bitonic_sort_kernel(_type* data, unsigned ulevel, unsigned ulevelmask)
{
__shared__ _type sh_data[BITONIC_TILE_SIZE];
int local_idx = threadIdx.x;
int global_idx = blockIdx.x*blockDim.x + threadIdx.x;
// Cooperatively load data - each thread will load data from global memory
// into tile_static
sh_data[local_idx] = data[global_idx];
// Wait till all threads have loaded their portion of data
#ifndef MUTATION
/* BUGINJECT: REMOVE_BARRIER, DOWN */
__syncthreads();
#endif
// Sort data in tile_static memory
for (unsigned int j = ulevel >> 1 ;
j > 0 ; j >>= 1)
{
_type result = ((sh_data[local_idx & ~j] <= sh_data[local_idx | j]) == (bool)(ulevelmask & global_idx)) ? sh_data[local_idx ^ j] : sh_data[local_idx];
__syncthreads();
sh_data[local_idx] = result;
__syncthreads();
}
// Store shared data
data[global_idx] = sh_data[local_idx];
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z19bitonic_sort_kernelPfjj
.globl _Z19bitonic_sort_kernelPfjj
.p2align 8
.type _Z19bitonic_sort_kernelPfjj,@function
_Z19bitonic_sort_kernelPfjj:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x1c
s_load_b64 s[4:5], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[3:4], null, s15, s2, v[0:1]
s_load_b32 s2, s[0:1], 0x8
v_ashrrev_i32_e32 v4, 31, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[1:2], 2, v[3:4]
v_lshlrev_b32_e32 v4, 2, v0
v_add_co_u32 v1, vcc_lo, s4, v1
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v2, vcc_lo, s5, v2, vcc_lo
s_waitcnt lgkmcnt(0)
s_cmp_lt_u32 s2, 2
global_load_b32 v5, v[1:2], off
s_waitcnt vmcnt(0)
ds_store_b32 v4, v5
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_3
s_load_b32 s0, s[0:1], 0xc
s_waitcnt lgkmcnt(0)
v_and_b32_e32 v3, s0, v3
s_delay_alu instid0(VALU_DEP_1)
v_cmp_eq_u32_e32 vcc_lo, 0, v3
.p2align 6
.LBB0_2:
s_lshr_b32 s1, s2, 1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
s_not_b32 s0, s1
v_or_b32_e32 v3, s1, v0
v_and_b32_e32 v5, s0, v0
v_xor_b32_e32 v6, s1, v0
v_lshlrev_b32_e32 v3, 2, v3
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_lshlrev_b32_e32 v5, 2, v5
v_lshlrev_b32_e32 v6, 2, v6
ds_load_b32 v5, v5
ds_load_b32 v3, v3
s_waitcnt lgkmcnt(0)
v_cmp_le_f32_e64 s0, v5, v3
s_delay_alu instid0(VALU_DEP_1)
s_xor_b32 s0, vcc_lo, s0
s_cmp_lt_u32 s2, 4
v_cndmask_b32_e64 v3, v4, v6, s0
s_mov_b32 s2, s1
ds_load_b32 v3, v3
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
ds_store_b32 v4, v3
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc0 .LBB0_2
.LBB0_3:
ds_load_b32 v0, v4
s_waitcnt lgkmcnt(0)
global_store_b32 v[1:2], v0, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z19bitonic_sort_kernelPfjj
.amdhsa_group_segment_fixed_size 2048
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z19bitonic_sort_kernelPfjj, .Lfunc_end0-_Z19bitonic_sort_kernelPfjj
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 2048
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z19bitonic_sort_kernelPfjj
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z19bitonic_sort_kernelPfjj.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | //pass
//--blockDim=512 --gridDim=512
#include <hip/hip_runtime.h>
//////////////////////////////////////////////////////////////////////////////
//// THIS CODE AND INFORMATION IS PROVIDED "AS IS" WITHOUT WARRANTY OF
//// ANY KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING BUT NOT LIMITED TO
//// THE IMPLIED WARRANTIES OF MERCHANTABILITY AND/OR FITNESS FOR A
//// PARTICULAR PURPOSE.
////
//// Copyright (c) Microsoft Corporation. All rights reserved
//////////////////////////////////////////////////////////////////////////////
// Original kernels are templated. We will check the float case.
#define _type float
//----------------------------------------------------------------------------
// File: BitonicSort.cpp
//
// Implements Bitonic sort in C++ AMP
// Supports only int, unsigned, long and unsigned long
//----------------------------------------------------------------------------
#define BITONIC_TILE_SIZE 512
// Should be a square matrix
#define NUM_ELEMENTS (BITONIC_TILE_SIZE * BITONIC_TILE_SIZE)
#define MATRIX_WIDTH BITONIC_TILE_SIZE
#define MATRIX_HEIGHT BITONIC_TILE_SIZE
// Should be divisible by MATRIX_WIDTH and MATRIX_HEIGHT
// else parallel_for_each will crash
#define TRANSPOSE_TILE_SIZE 16
//----------------------------------------------------------------------------
// Kernel implements partial sorting on accelerator, BITONIC_TILE_SIZE at a time
//----------------------------------------------------------------------------
__global__ void bitonic_sort_kernel(_type* data, unsigned ulevel, unsigned ulevelmask)
{
__shared__ _type sh_data[BITONIC_TILE_SIZE];
int local_idx = threadIdx.x;
int global_idx = blockIdx.x*blockDim.x + threadIdx.x;
// Cooperatively load data - each thread will load data from global memory
// into tile_static
sh_data[local_idx] = data[global_idx];
// Wait till all threads have loaded their portion of data
#ifndef MUTATION
/* BUGINJECT: REMOVE_BARRIER, DOWN */
__syncthreads();
#endif
// Sort data in tile_static memory
for (unsigned int j = ulevel >> 1 ;
j > 0 ; j >>= 1)
{
_type result = ((sh_data[local_idx & ~j] <= sh_data[local_idx | j]) == (bool)(ulevelmask & global_idx)) ? sh_data[local_idx ^ j] : sh_data[local_idx];
__syncthreads();
sh_data[local_idx] = result;
__syncthreads();
}
// Store shared data
data[global_idx] = sh_data[local_idx];
} | .text
.file "kernel.hip"
.globl _Z34__device_stub__bitonic_sort_kernelPfjj # -- Begin function _Z34__device_stub__bitonic_sort_kernelPfjj
.p2align 4, 0x90
.type _Z34__device_stub__bitonic_sort_kernelPfjj,@function
_Z34__device_stub__bitonic_sort_kernelPfjj: # @_Z34__device_stub__bitonic_sort_kernelPfjj
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z19bitonic_sort_kernelPfjj, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z34__device_stub__bitonic_sort_kernelPfjj, .Lfunc_end0-_Z34__device_stub__bitonic_sort_kernelPfjj
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z19bitonic_sort_kernelPfjj, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z19bitonic_sort_kernelPfjj,@object # @_Z19bitonic_sort_kernelPfjj
.section .rodata,"a",@progbits
.globl _Z19bitonic_sort_kernelPfjj
.p2align 3, 0x0
_Z19bitonic_sort_kernelPfjj:
.quad _Z34__device_stub__bitonic_sort_kernelPfjj
.size _Z19bitonic_sort_kernelPfjj, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z19bitonic_sort_kernelPfjj"
.size .L__unnamed_1, 28
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z34__device_stub__bitonic_sort_kernelPfjj
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z19bitonic_sort_kernelPfjj
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z19bitonic_sort_kernelPfjj
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R7, SR_TID.X ; /* 0x0000000000077919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R7 ; /* 0x0000000000007a24 */
/* 0x001fc800078e0207 */
/*0060*/ IMAD.WIDE R2, R0, R3, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fca00078e0203 */
/*0070*/ LDG.E R4, [R2.64] ; /* 0x0000000602047981 */
/* 0x000ea2000c1e1900 */
/*0080*/ ULDC UR4, c[0x0][0x168] ; /* 0x00005a0000047ab9 */
/* 0x000fe40000000800 */
/*0090*/ USHF.R.U32.HI UR4, URZ, 0x1, UR4 ; /* 0x000000013f047899 */
/* 0x000fcc0008011604 */
/*00a0*/ ISETP.NE.AND P0, PT, RZ, UR4, PT ; /* 0x00000004ff007c0c */
/* 0x000fe2000bf05270 */
/*00b0*/ STS [R7.X4], R4 ; /* 0x0000000407007388 */
/* 0x0041e80000004800 */
/*00c0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000ff00000010000 */
/*00d0*/ @!P0 BRA 0x1e0 ; /* 0x0000010000008947 */
/* 0x000fea0003800000 */
/*00e0*/ LOP3.LUT P0, RZ, R0, c[0x0][0x16c], RZ, 0xc0, !PT ; /* 0x00005b0000ff7a12 */
/* 0x001fe2000780c0ff */
/*00f0*/ IMAD.U32 R0, RZ, RZ, UR4 ; /* 0x00000004ff007e24 */
/* 0x000fca000f8e00ff */
/*0100*/ LOP3.LUT R4, R7, R0, RZ, 0x30, !PT ; /* 0x0000000007047212 */
/* 0x000fe400078e30ff */
/*0110*/ LOP3.LUT R5, R0, R7, RZ, 0xfc, !PT ; /* 0x0000000700057212 */
/* 0x000fc800078efcff */
/*0120*/ LDS R4, [R4.X4] ; /* 0x0000000004047984 */
/* 0x000fe80000004800 */
/*0130*/ LDS R5, [R5.X4] ; /* 0x0000000005057984 */
/* 0x000e240000004800 */
/*0140*/ FSETP.LE.XOR P1, PT, R4, R5, P0 ; /* 0x000000050400720b */
/* 0x001fc80000723800 */
/*0150*/ SEL R6, R0, RZ, !P1 ; /* 0x000000ff00067207 */
/* 0x000fe40004800000 */
/*0160*/ SHF.R.U32.HI R0, RZ, 0x1, R0 ; /* 0x00000001ff007819 */
/* 0x000fe40000011600 */
/*0170*/ LOP3.LUT R6, R6, R7, RZ, 0x3c, !PT ; /* 0x0000000706067212 */
/* 0x000fe400078e3cff */
/*0180*/ ISETP.NE.AND P1, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fc80003f25270 */
/*0190*/ LDS R6, [R6.X4] ; /* 0x0000000006067984 */
/* 0x000e280000004800 */
/*01a0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*01b0*/ STS [R7.X4], R6 ; /* 0x0000000607007388 */
/* 0x0011e80000004800 */
/*01c0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*01d0*/ @P1 BRA 0x100 ; /* 0xffffff2000001947 */
/* 0x001fea000383ffff */
/*01e0*/ LDS R5, [R7.X4] ; /* 0x0000000007057984 */
/* 0x001e280000004800 */
/*01f0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x001fe2000c101906 */
/*0200*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0210*/ BRA 0x210; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z19bitonic_sort_kernelPfjj
.globl _Z19bitonic_sort_kernelPfjj
.p2align 8
.type _Z19bitonic_sort_kernelPfjj,@function
_Z19bitonic_sort_kernelPfjj:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x1c
s_load_b64 s[4:5], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[3:4], null, s15, s2, v[0:1]
s_load_b32 s2, s[0:1], 0x8
v_ashrrev_i32_e32 v4, 31, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[1:2], 2, v[3:4]
v_lshlrev_b32_e32 v4, 2, v0
v_add_co_u32 v1, vcc_lo, s4, v1
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v2, vcc_lo, s5, v2, vcc_lo
s_waitcnt lgkmcnt(0)
s_cmp_lt_u32 s2, 2
global_load_b32 v5, v[1:2], off
s_waitcnt vmcnt(0)
ds_store_b32 v4, v5
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_3
s_load_b32 s0, s[0:1], 0xc
s_waitcnt lgkmcnt(0)
v_and_b32_e32 v3, s0, v3
s_delay_alu instid0(VALU_DEP_1)
v_cmp_eq_u32_e32 vcc_lo, 0, v3
.p2align 6
.LBB0_2:
s_lshr_b32 s1, s2, 1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
s_not_b32 s0, s1
v_or_b32_e32 v3, s1, v0
v_and_b32_e32 v5, s0, v0
v_xor_b32_e32 v6, s1, v0
v_lshlrev_b32_e32 v3, 2, v3
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_lshlrev_b32_e32 v5, 2, v5
v_lshlrev_b32_e32 v6, 2, v6
ds_load_b32 v5, v5
ds_load_b32 v3, v3
s_waitcnt lgkmcnt(0)
v_cmp_le_f32_e64 s0, v5, v3
s_delay_alu instid0(VALU_DEP_1)
s_xor_b32 s0, vcc_lo, s0
s_cmp_lt_u32 s2, 4
v_cndmask_b32_e64 v3, v4, v6, s0
s_mov_b32 s2, s1
ds_load_b32 v3, v3
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
ds_store_b32 v4, v3
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc0 .LBB0_2
.LBB0_3:
ds_load_b32 v0, v4
s_waitcnt lgkmcnt(0)
global_store_b32 v[1:2], v0, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z19bitonic_sort_kernelPfjj
.amdhsa_group_segment_fixed_size 2048
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z19bitonic_sort_kernelPfjj, .Lfunc_end0-_Z19bitonic_sort_kernelPfjj
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 2048
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z19bitonic_sort_kernelPfjj
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z19bitonic_sort_kernelPfjj.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00187ce4_00000000-6_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z41__device_stub__Z19bitonic_sort_kernelPfjjPfjj
.type _Z41__device_stub__Z19bitonic_sort_kernelPfjjPfjj, @function
_Z41__device_stub__Z19bitonic_sort_kernelPfjjPfjj:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z19bitonic_sort_kernelPfjj(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z41__device_stub__Z19bitonic_sort_kernelPfjjPfjj, .-_Z41__device_stub__Z19bitonic_sort_kernelPfjjPfjj
.globl _Z19bitonic_sort_kernelPfjj
.type _Z19bitonic_sort_kernelPfjj, @function
_Z19bitonic_sort_kernelPfjj:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z41__device_stub__Z19bitonic_sort_kernelPfjjPfjj
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z19bitonic_sort_kernelPfjj, .-_Z19bitonic_sort_kernelPfjj
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z19bitonic_sort_kernelPfjj"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z19bitonic_sort_kernelPfjj(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "kernel.hip"
.globl _Z34__device_stub__bitonic_sort_kernelPfjj # -- Begin function _Z34__device_stub__bitonic_sort_kernelPfjj
.p2align 4, 0x90
.type _Z34__device_stub__bitonic_sort_kernelPfjj,@function
_Z34__device_stub__bitonic_sort_kernelPfjj: # @_Z34__device_stub__bitonic_sort_kernelPfjj
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z19bitonic_sort_kernelPfjj, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z34__device_stub__bitonic_sort_kernelPfjj, .Lfunc_end0-_Z34__device_stub__bitonic_sort_kernelPfjj
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z19bitonic_sort_kernelPfjj, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z19bitonic_sort_kernelPfjj,@object # @_Z19bitonic_sort_kernelPfjj
.section .rodata,"a",@progbits
.globl _Z19bitonic_sort_kernelPfjj
.p2align 3, 0x0
_Z19bitonic_sort_kernelPfjj:
.quad _Z34__device_stub__bitonic_sort_kernelPfjj
.size _Z19bitonic_sort_kernelPfjj, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z19bitonic_sort_kernelPfjj"
.size .L__unnamed_1, 28
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z34__device_stub__bitonic_sort_kernelPfjj
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z19bitonic_sort_kernelPfjj
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <time.h>
#include <stdlib.h>
#include <cuda.h>
#include <sys/time.h>
#define array_size 268435456
__global__ void vector_add(float *out, float *a, float *b, int n){
int index = threadIdx.x;
int stride = blockDim.x;
for(int i = index; i < n; i += stride){
out[i] = a[i] + b[i];}
}
extern double mysecond();
int main(){
float *a, *b, *out;
float *d_a, *d_b, *d_out;
double t;
// Allocate host memory
a = (float*)malloc(sizeof(float) * array_size);
b = (float*)malloc(sizeof(float) * array_size);
out = (float*)malloc(sizeof(float) * array_size);
// Initialize array
for(int i = 0; i < array_size; i++){
a[i] = 1.0f;
b[i] = 2.0f;
}
// Allocate device memory
cudaMalloc((void**)&d_a,sizeof(float)*array_size);
cudaMalloc((void**)&d_b,sizeof(float)*array_size);
cudaMalloc((void**)&d_out,sizeof(float)*array_size);
t = mysecond();
// Transfer data from host to device memory
cudaMemcpy(d_a,a, sizeof(float)*array_size, cudaMemcpyHostToDevice);
cudaMemcpy(d_b,b, sizeof(float)*array_size, cudaMemcpyHostToDevice);
t = (mysecond() - t);
printf ("\nElapsed time for copy from host to device = %g\n", t);
int block_size = 256;
t = mysecond();
// Vector addition
vector_add<<<1,block_size>>>(d_out, d_a, d_b, array_size);
cudaDeviceSynchronize();
t = (mysecond() - t);
printf ("\nElapsed time for vector addition in 1 block = %g\n", t);
t = mysecond();
// Transfer data from device to host memory
cudaMemcpy(out, d_out, sizeof(float)*array_size, cudaMemcpyDeviceToHost);
t = (mysecond() - t);
printf ("\nElapsed time for copy from device to host = %g\n", t);
// Deallocate device memory
cudaFree(d_a);
cudaFree(d_b);
cudaFree(d_out);
// Deallocate host memory
free(a);
free(b);
free(out);
printf ("\nBLock size (number of threads): %d \n", block_size);
printf ("\nNumber of blocks : 1 \n");
}
double mysecond()
{
struct timeval tp;
struct timezone tzp;
gettimeofday(&tp,&tzp);
return ( (double) tp.tv_sec + (double) tp.tv_usec * 1.e-6);
} | code for sm_80
Function : _Z10vector_addPfS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e240000002100 */
/*0020*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x178], PT ; /* 0x00005e0000007a0c */
/* 0x001fda0003f06270 */
/*0030*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0040*/ I2F.U32.RP R5, c[0x0][0x0] ; /* 0x0000000000057b06 */
/* 0x000e220000209000 */
/*0050*/ LOP3.LUT R4, RZ, R0, RZ, 0x33, !PT ; /* 0x00000000ff047212 */
/* 0x000fe200078e33ff */
/*0060*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0070*/ ISETP.NE.U32.AND P2, PT, RZ, c[0x0][0x0], PT ; /* 0x00000000ff007a0c */
/* 0x000fe20003f45070 */
/*0080*/ BSSY B0, 0x2f0 ; /* 0x0000026000007945 */
/* 0x000fe20003800000 */
/*0090*/ IADD3 R4, R4, c[0x0][0x178], RZ ; /* 0x00005e0004047a10 */
/* 0x000fc60007ffe0ff */
/*00a0*/ MUFU.RCP R5, R5 ; /* 0x0000000500057308 */
/* 0x001e240000001000 */
/*00b0*/ IADD3 R2, R5, 0xffffffe, RZ ; /* 0x0ffffffe05027810 */
/* 0x001fcc0007ffe0ff */
/*00c0*/ F2I.FTZ.U32.TRUNC.NTZ R3, R2 ; /* 0x0000000200037305 */
/* 0x000064000021f000 */
/*00d0*/ HFMA2.MMA R2, -RZ, RZ, 0, 0 ; /* 0x00000000ff027435 */
/* 0x001fe200000001ff */
/*00e0*/ IADD3 R7, RZ, -R3, RZ ; /* 0x80000003ff077210 */
/* 0x002fca0007ffe0ff */
/*00f0*/ IMAD R7, R7, c[0x0][0x0], RZ ; /* 0x0000000007077a24 */
/* 0x000fc800078e02ff */
/*0100*/ IMAD.HI.U32 R3, R3, R7, R2 ; /* 0x0000000703037227 */
/* 0x000fcc00078e0002 */
/*0110*/ IMAD.HI.U32 R3, R3, R4, RZ ; /* 0x0000000403037227 */
/* 0x000fca00078e00ff */
/*0120*/ IADD3 R5, -R3, RZ, RZ ; /* 0x000000ff03057210 */
/* 0x000fca0007ffe1ff */
/*0130*/ IMAD R4, R5, c[0x0][0x0], R4 ; /* 0x0000000005047a24 */
/* 0x000fca00078e0204 */
/*0140*/ ISETP.GE.U32.AND P0, PT, R4, c[0x0][0x0], PT ; /* 0x0000000004007a0c */
/* 0x000fda0003f06070 */
/*0150*/ @P0 IADD3 R4, R4, -c[0x0][0x0], RZ ; /* 0x8000000004040a10 */
/* 0x000fe40007ffe0ff */
/*0160*/ @P0 IADD3 R3, R3, 0x1, RZ ; /* 0x0000000103030810 */
/* 0x000fe40007ffe0ff */
/*0170*/ ISETP.GE.U32.AND P1, PT, R4, c[0x0][0x0], PT ; /* 0x0000000004007a0c */
/* 0x000fda0003f26070 */
/*0180*/ @P1 IADD3 R3, R3, 0x1, RZ ; /* 0x0000000103031810 */
/* 0x000fe40007ffe0ff */
/*0190*/ @!P2 LOP3.LUT R3, RZ, c[0x0][0x0], RZ, 0x33, !PT ; /* 0x00000000ff03aa12 */
/* 0x000fc800078e33ff */
/*01a0*/ IADD3 R2, R3.reuse, 0x1, RZ ; /* 0x0000000103027810 */
/* 0x040fe40007ffe0ff */
/*01b0*/ ISETP.GE.U32.AND P1, PT, R3, 0x3, PT ; /* 0x000000030300780c */
/* 0x000fe40003f26070 */
/*01c0*/ LOP3.LUT P0, R2, R2, 0x3, RZ, 0xc0, !PT ; /* 0x0000000302027812 */
/* 0x000fda000780c0ff */
/*01d0*/ @!P0 BRA 0x2e0 ; /* 0x0000010000008947 */
/* 0x000fea0003800000 */
/*01e0*/ MOV R11, 0x4 ; /* 0x00000004000b7802 */
/* 0x000fe40000000f00 */
/*01f0*/ MOV R8, R2 ; /* 0x0000000200087202 */
/* 0x000fc60000000f00 */
/*0200*/ IMAD.WIDE R2, R0, R11, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fc800078e020b */
/*0210*/ IMAD.WIDE R4, R0, R11, c[0x0][0x170] ; /* 0x00005c0000047625 */
/* 0x000fc800078e020b */
/*0220*/ IMAD.WIDE R6, R0, R11, c[0x0][0x168] ; /* 0x00005a0000067625 */
/* 0x000fc800078e020b */
/*0230*/ LDG.E R9, [R4.64] ; /* 0x0000000404097981 */
/* 0x0000a8000c1e1900 */
/*0240*/ LDG.E R10, [R6.64] ; /* 0x00000004060a7981 */
/* 0x0002a2000c1e1900 */
/*0250*/ IADD3 R8, R8, -0x1, RZ ; /* 0xffffffff08087810 */
/* 0x000fe40007ffe0ff */
/*0260*/ IADD3 R0, R0, c[0x0][0x0], RZ ; /* 0x0000000000007a10 */
/* 0x000fe40007ffe0ff */
/*0270*/ ISETP.NE.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fe20003f05270 */
/*0280*/ IMAD.WIDE R4, R11, c[0x0][0x0], R4 ; /* 0x000000000b047a25 */
/* 0x001fc800078e0204 */
/*0290*/ IMAD.WIDE R6, R11, c[0x0][0x0], R6 ; /* 0x000000000b067a25 */
/* 0x002fc800078e0206 */
/*02a0*/ FADD R9, R9, R10 ; /* 0x0000000a09097221 */
/* 0x004fca0000000000 */
/*02b0*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x0001e4000c101904 */
/*02c0*/ IMAD.WIDE R2, R11, c[0x0][0x0], R2 ; /* 0x000000000b027a25 */
/* 0x001fe200078e0202 */
/*02d0*/ @P0 BRA 0x230 ; /* 0xffffff5000000947 */
/* 0x000fea000383ffff */
/*02e0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*02f0*/ @!P1 EXIT ; /* 0x000000000000994d */
/* 0x000fea0003800000 */
/*0300*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x002fd400000001ff */
/*0310*/ IMAD.WIDE R6, R0, R3, c[0x0][0x170] ; /* 0x00005c0000067625 */
/* 0x000fc800078e0203 */
/*0320*/ IMAD.WIDE R4, R0.reuse, R3.reuse, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x0c0fe200078e0203 */
/*0330*/ LDG.E R2, [R6.64] ; /* 0x0000000406027981 */
/* 0x000ea8000c1e1900 */
/*0340*/ LDG.E R11, [R4.64] ; /* 0x00000004040b7981 */
/* 0x000ea2000c1e1900 */
/*0350*/ IMAD.WIDE R8, R0, R3, c[0x0][0x160] ; /* 0x0000580000087625 */
/* 0x000fc800078e0203 */
/*0360*/ IMAD.WIDE R12, R3, c[0x0][0x0], R6 ; /* 0x00000000030c7a25 */
/* 0x000fc800078e0206 */
/*0370*/ FADD R19, R2, R11 ; /* 0x0000000b02137221 */
/* 0x004fe40000000000 */
/*0380*/ IMAD.WIDE R10, R3, c[0x0][0x0], R4 ; /* 0x00000000030a7a25 */
/* 0x000fc600078e0204 */
/*0390*/ STG.E [R8.64], R19 ; /* 0x0000001308007986 */
/* 0x0001e8000c101904 */
/*03a0*/ LDG.E R2, [R12.64] ; /* 0x000000040c027981 */
/* 0x000ea8000c1e1900 */
/*03b0*/ LDG.E R17, [R10.64] ; /* 0x000000040a117981 */
/* 0x000ea2000c1e1900 */
/*03c0*/ IMAD.WIDE R14, R3, c[0x0][0x0], R8 ; /* 0x00000000030e7a25 */
/* 0x000fc800078e0208 */
/*03d0*/ IMAD.WIDE R6, R3, c[0x0][0x0], R12 ; /* 0x0000000003067a25 */
/* 0x000fc800078e020c */
/*03e0*/ IMAD.WIDE R4, R3, c[0x0][0x0], R10 ; /* 0x0000000003047a25 */
/* 0x000fc800078e020a */
/*03f0*/ FADD R21, R2, R17 ; /* 0x0000001102157221 */
/* 0x004fca0000000000 */
/*0400*/ STG.E [R14.64], R21 ; /* 0x000000150e007986 */
/* 0x0003e8000c101904 */
/*0410*/ LDG.E R2, [R6.64] ; /* 0x0000000406027981 */
/* 0x000ea8000c1e1900 */
/*0420*/ LDG.E R23, [R4.64] ; /* 0x0000000404177981 */
/* 0x000ea2000c1e1900 */
/*0430*/ IMAD.WIDE R16, R3, c[0x0][0x0], R14 ; /* 0x0000000003107a25 */
/* 0x000fc800078e020e */
/*0440*/ IMAD.WIDE R12, R3, c[0x0][0x0], R6 ; /* 0x00000000030c7a25 */
/* 0x000fc800078e0206 */
/*0450*/ IMAD.WIDE R8, R3, c[0x0][0x0], R4 ; /* 0x0000000003087a25 */
/* 0x001fc800078e0204 */
/*0460*/ FADD R23, R2, R23 ; /* 0x0000001702177221 */
/* 0x004fca0000000000 */
/*0470*/ STG.E [R16.64], R23 ; /* 0x0000001710007986 */
/* 0x0003e8000c101904 */
/*0480*/ LDG.E R12, [R12.64] ; /* 0x000000040c0c7981 */
/* 0x000ea8000c1e1900 */
/*0490*/ LDG.E R9, [R8.64] ; /* 0x0000000408097981 */
/* 0x000ea2000c1e1900 */
/*04a0*/ MOV R7, c[0x0][0x0] ; /* 0x0000000000077a02 */
/* 0x000fe20000000f00 */
/*04b0*/ IMAD.WIDE R2, R3, c[0x0][0x0], R16 ; /* 0x0000000003027a25 */
/* 0x000fe200078e0210 */
/*04c0*/ MOV R5, c[0x0][0x0] ; /* 0x0000000000057a02 */
/* 0x000fc40000000f00 */
/*04d0*/ LEA R0, R7, R0, 0x1 ; /* 0x0000000007007211 */
/* 0x000fc800078e08ff */
/*04e0*/ LEA R0, R5, R0, 0x1 ; /* 0x0000000005007211 */
/* 0x000fc800078e08ff */
/*04f0*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x178], PT ; /* 0x00005e0000007a0c */
/* 0x000fe20003f06270 */
/*0500*/ FADD R11, R12, R9 ; /* 0x000000090c0b7221 */
/* 0x004fca0000000000 */
/*0510*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x0003ee000c101904 */
/*0520*/ @!P0 BRA 0x300 ; /* 0xfffffdd000008947 */
/* 0x000fea000383ffff */
/*0530*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0540*/ BRA 0x540; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0550*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0560*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0570*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0580*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0590*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <time.h>
#include <stdlib.h>
#include <cuda.h>
#include <sys/time.h>
#define array_size 268435456
__global__ void vector_add(float *out, float *a, float *b, int n){
int index = threadIdx.x;
int stride = blockDim.x;
for(int i = index; i < n; i += stride){
out[i] = a[i] + b[i];}
}
extern double mysecond();
int main(){
float *a, *b, *out;
float *d_a, *d_b, *d_out;
double t;
// Allocate host memory
a = (float*)malloc(sizeof(float) * array_size);
b = (float*)malloc(sizeof(float) * array_size);
out = (float*)malloc(sizeof(float) * array_size);
// Initialize array
for(int i = 0; i < array_size; i++){
a[i] = 1.0f;
b[i] = 2.0f;
}
// Allocate device memory
cudaMalloc((void**)&d_a,sizeof(float)*array_size);
cudaMalloc((void**)&d_b,sizeof(float)*array_size);
cudaMalloc((void**)&d_out,sizeof(float)*array_size);
t = mysecond();
// Transfer data from host to device memory
cudaMemcpy(d_a,a, sizeof(float)*array_size, cudaMemcpyHostToDevice);
cudaMemcpy(d_b,b, sizeof(float)*array_size, cudaMemcpyHostToDevice);
t = (mysecond() - t);
printf ("\nElapsed time for copy from host to device = %g\n", t);
int block_size = 256;
t = mysecond();
// Vector addition
vector_add<<<1,block_size>>>(d_out, d_a, d_b, array_size);
cudaDeviceSynchronize();
t = (mysecond() - t);
printf ("\nElapsed time for vector addition in 1 block = %g\n", t);
t = mysecond();
// Transfer data from device to host memory
cudaMemcpy(out, d_out, sizeof(float)*array_size, cudaMemcpyDeviceToHost);
t = (mysecond() - t);
printf ("\nElapsed time for copy from device to host = %g\n", t);
// Deallocate device memory
cudaFree(d_a);
cudaFree(d_b);
cudaFree(d_out);
// Deallocate host memory
free(a);
free(b);
free(out);
printf ("\nBLock size (number of threads): %d \n", block_size);
printf ("\nNumber of blocks : 1 \n");
}
double mysecond()
{
struct timeval tp;
struct timezone tzp;
gettimeofday(&tp,&tzp);
return ( (double) tp.tv_sec + (double) tp.tv_usec * 1.e-6);
} | .file "tmpxft_00017391_00000000-6_vector_add_oneblock.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z8mysecondv
.type _Z8mysecondv, @function
_Z8mysecondv:
.LFB2058:
.cfi_startproc
endbr64
subq $56, %rsp
.cfi_def_cfa_offset 64
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rsi
leaq 16(%rsp), %rdi
call gettimeofday@PLT
pxor %xmm0, %xmm0
cvtsi2sdq 24(%rsp), %xmm0
mulsd .LC0(%rip), %xmm0
pxor %xmm1, %xmm1
cvtsi2sdq 16(%rsp), %xmm1
addsd %xmm1, %xmm0
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L6
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L6:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size _Z8mysecondv, .-_Z8mysecondv
.globl _Z35__device_stub__Z10vector_addPfS_S_iPfS_S_i
.type _Z35__device_stub__Z10vector_addPfS_S_iPfS_S_i, @function
_Z35__device_stub__Z10vector_addPfS_S_iPfS_S_i:
.LFB2083:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L11
.L7:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L12
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z10vector_addPfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L7
.L12:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z35__device_stub__Z10vector_addPfS_S_iPfS_S_i, .-_Z35__device_stub__Z10vector_addPfS_S_iPfS_S_i
.globl _Z10vector_addPfS_S_i
.type _Z10vector_addPfS_S_i, @function
_Z10vector_addPfS_S_i:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z10vector_addPfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z10vector_addPfS_S_i, .-_Z10vector_addPfS_S_i
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC3:
.string "\nElapsed time for copy from host to device = %g\n"
.align 8
.LC4:
.string "\nElapsed time for vector addition in 1 block = %g\n"
.align 8
.LC5:
.string "\nElapsed time for copy from device to host = %g\n"
.align 8
.LC6:
.string "\nBLock size (number of threads): %d \n"
.align 8
.LC7:
.string "\nNumber of blocks : 1 \n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $80, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1073741824, %edi
call malloc@PLT
movq %rax, %rbp
movl $1073741824, %edi
call malloc@PLT
movq %rax, %rbx
movl $1073741824, %edi
call malloc@PLT
movq %rax, %r12
movl $0, %eax
movss .LC1(%rip), %xmm1
movss .LC2(%rip), %xmm0
.L16:
movss %xmm1, 0(%rbp,%rax)
movss %xmm0, (%rbx,%rax)
addq $4, %rax
cmpq $1073741824, %rax
jne .L16
leaq 24(%rsp), %rdi
movl $1073741824, %esi
call cudaMalloc@PLT
leaq 32(%rsp), %rdi
movl $1073741824, %esi
call cudaMalloc@PLT
leaq 40(%rsp), %rdi
movl $1073741824, %esi
call cudaMalloc@PLT
call _Z8mysecondv
movsd %xmm0, 8(%rsp)
movl $1, %ecx
movl $1073741824, %edx
movq %rbp, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $1073741824, %edx
movq %rbx, %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
call _Z8mysecondv
subsd 8(%rsp), %xmm0
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
call _Z8mysecondv
movsd %xmm0, 8(%rsp)
movl $256, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movl $1, %ecx
movq 48(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L21
.L17:
call cudaDeviceSynchronize@PLT
call _Z8mysecondv
subsd 8(%rsp), %xmm0
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
call _Z8mysecondv
movsd %xmm0, 8(%rsp)
movl $2, %ecx
movl $1073741824, %edx
movq 40(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
call _Z8mysecondv
subsd 8(%rsp), %xmm0
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq %rbp, %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
movl $256, %edx
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L22
movl $0, %eax
addq $80, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L21:
.cfi_restore_state
movl $268435456, %ecx
movq 32(%rsp), %rdx
movq 24(%rsp), %rsi
movq 40(%rsp), %rdi
call _Z35__device_stub__Z10vector_addPfS_S_iPfS_S_i
jmp .L17
.L22:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC8:
.string "_Z10vector_addPfS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _Z10vector_addPfS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long -1598689907
.long 1051772663
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC1:
.long 1065353216
.align 4
.LC2:
.long 1073741824
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <time.h>
#include <stdlib.h>
#include <cuda.h>
#include <sys/time.h>
#define array_size 268435456
__global__ void vector_add(float *out, float *a, float *b, int n){
int index = threadIdx.x;
int stride = blockDim.x;
for(int i = index; i < n; i += stride){
out[i] = a[i] + b[i];}
}
extern double mysecond();
int main(){
float *a, *b, *out;
float *d_a, *d_b, *d_out;
double t;
// Allocate host memory
a = (float*)malloc(sizeof(float) * array_size);
b = (float*)malloc(sizeof(float) * array_size);
out = (float*)malloc(sizeof(float) * array_size);
// Initialize array
for(int i = 0; i < array_size; i++){
a[i] = 1.0f;
b[i] = 2.0f;
}
// Allocate device memory
cudaMalloc((void**)&d_a,sizeof(float)*array_size);
cudaMalloc((void**)&d_b,sizeof(float)*array_size);
cudaMalloc((void**)&d_out,sizeof(float)*array_size);
t = mysecond();
// Transfer data from host to device memory
cudaMemcpy(d_a,a, sizeof(float)*array_size, cudaMemcpyHostToDevice);
cudaMemcpy(d_b,b, sizeof(float)*array_size, cudaMemcpyHostToDevice);
t = (mysecond() - t);
printf ("\nElapsed time for copy from host to device = %g\n", t);
int block_size = 256;
t = mysecond();
// Vector addition
vector_add<<<1,block_size>>>(d_out, d_a, d_b, array_size);
cudaDeviceSynchronize();
t = (mysecond() - t);
printf ("\nElapsed time for vector addition in 1 block = %g\n", t);
t = mysecond();
// Transfer data from device to host memory
cudaMemcpy(out, d_out, sizeof(float)*array_size, cudaMemcpyDeviceToHost);
t = (mysecond() - t);
printf ("\nElapsed time for copy from device to host = %g\n", t);
// Deallocate device memory
cudaFree(d_a);
cudaFree(d_b);
cudaFree(d_out);
// Deallocate host memory
free(a);
free(b);
free(out);
printf ("\nBLock size (number of threads): %d \n", block_size);
printf ("\nNumber of blocks : 1 \n");
}
double mysecond()
{
struct timeval tp;
struct timezone tzp;
gettimeofday(&tp,&tzp);
return ( (double) tp.tv_sec + (double) tp.tv_usec * 1.e-6);
} | #include <stdio.h>
#include <time.h>
#include <stdlib.h>
#include <hip/hip_runtime.h>
#include <sys/time.h>
#define array_size 268435456
__global__ void vector_add(float *out, float *a, float *b, int n){
int index = threadIdx.x;
int stride = blockDim.x;
for(int i = index; i < n; i += stride){
out[i] = a[i] + b[i];}
}
extern double mysecond();
int main(){
float *a, *b, *out;
float *d_a, *d_b, *d_out;
double t;
// Allocate host memory
a = (float*)malloc(sizeof(float) * array_size);
b = (float*)malloc(sizeof(float) * array_size);
out = (float*)malloc(sizeof(float) * array_size);
// Initialize array
for(int i = 0; i < array_size; i++){
a[i] = 1.0f;
b[i] = 2.0f;
}
// Allocate device memory
hipMalloc((void**)&d_a,sizeof(float)*array_size);
hipMalloc((void**)&d_b,sizeof(float)*array_size);
hipMalloc((void**)&d_out,sizeof(float)*array_size);
t = mysecond();
// Transfer data from host to device memory
hipMemcpy(d_a,a, sizeof(float)*array_size, hipMemcpyHostToDevice);
hipMemcpy(d_b,b, sizeof(float)*array_size, hipMemcpyHostToDevice);
t = (mysecond() - t);
printf ("\nElapsed time for copy from host to device = %g\n", t);
int block_size = 256;
t = mysecond();
// Vector addition
vector_add<<<1,block_size>>>(d_out, d_a, d_b, array_size);
hipDeviceSynchronize();
t = (mysecond() - t);
printf ("\nElapsed time for vector addition in 1 block = %g\n", t);
t = mysecond();
// Transfer data from device to host memory
hipMemcpy(out, d_out, sizeof(float)*array_size, hipMemcpyDeviceToHost);
t = (mysecond() - t);
printf ("\nElapsed time for copy from device to host = %g\n", t);
// Deallocate device memory
hipFree(d_a);
hipFree(d_b);
hipFree(d_out);
// Deallocate host memory
free(a);
free(b);
free(out);
printf ("\nBLock size (number of threads): %d \n", block_size);
printf ("\nNumber of blocks : 1 \n");
}
double mysecond()
{
struct timeval tp;
struct timezone tzp;
gettimeofday(&tp,&tzp);
return ( (double) tp.tv_sec + (double) tp.tv_usec * 1.e-6);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <stdio.h>
#include <time.h>
#include <stdlib.h>
#include <hip/hip_runtime.h>
#include <sys/time.h>
#define array_size 268435456
__global__ void vector_add(float *out, float *a, float *b, int n){
int index = threadIdx.x;
int stride = blockDim.x;
for(int i = index; i < n; i += stride){
out[i] = a[i] + b[i];}
}
extern double mysecond();
int main(){
float *a, *b, *out;
float *d_a, *d_b, *d_out;
double t;
// Allocate host memory
a = (float*)malloc(sizeof(float) * array_size);
b = (float*)malloc(sizeof(float) * array_size);
out = (float*)malloc(sizeof(float) * array_size);
// Initialize array
for(int i = 0; i < array_size; i++){
a[i] = 1.0f;
b[i] = 2.0f;
}
// Allocate device memory
hipMalloc((void**)&d_a,sizeof(float)*array_size);
hipMalloc((void**)&d_b,sizeof(float)*array_size);
hipMalloc((void**)&d_out,sizeof(float)*array_size);
t = mysecond();
// Transfer data from host to device memory
hipMemcpy(d_a,a, sizeof(float)*array_size, hipMemcpyHostToDevice);
hipMemcpy(d_b,b, sizeof(float)*array_size, hipMemcpyHostToDevice);
t = (mysecond() - t);
printf ("\nElapsed time for copy from host to device = %g\n", t);
int block_size = 256;
t = mysecond();
// Vector addition
vector_add<<<1,block_size>>>(d_out, d_a, d_b, array_size);
hipDeviceSynchronize();
t = (mysecond() - t);
printf ("\nElapsed time for vector addition in 1 block = %g\n", t);
t = mysecond();
// Transfer data from device to host memory
hipMemcpy(out, d_out, sizeof(float)*array_size, hipMemcpyDeviceToHost);
t = (mysecond() - t);
printf ("\nElapsed time for copy from device to host = %g\n", t);
// Deallocate device memory
hipFree(d_a);
hipFree(d_b);
hipFree(d_out);
// Deallocate host memory
free(a);
free(b);
free(out);
printf ("\nBLock size (number of threads): %d \n", block_size);
printf ("\nNumber of blocks : 1 \n");
}
double mysecond()
{
struct timeval tp;
struct timezone tzp;
gettimeofday(&tp,&tzp);
return ( (double) tp.tv_sec + (double) tp.tv_usec * 1.e-6);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10vector_addPfS_S_i
.globl _Z10vector_addPfS_S_i
.p2align 8
.type _Z10vector_addPfS_S_i,@function
_Z10vector_addPfS_S_i:
s_load_b32 s8, s[0:1], 0x18
s_mov_b32 s2, exec_lo
s_waitcnt lgkmcnt(0)
v_cmpx_gt_i32_e64 s8, v0
s_cbranch_execz .LBB0_3
s_clause 0x2
s_load_b32 s9, s[0:1], 0x2c
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[2:3], s[0:1], 0x10
v_dual_mov_b32 v2, 0 :: v_dual_lshlrev_b32 v1, 2, v0
s_waitcnt lgkmcnt(0)
s_and_b32 s1, s9, 0xffff
s_mov_b32 s9, 0
s_lshl_b32 s10, s1, 2
s_mov_b32 s11, s9
.p2align 6
.LBB0_2:
v_add_co_u32 v3, vcc_lo, s6, v1
v_add_co_ci_u32_e32 v4, vcc_lo, s7, v2, vcc_lo
v_add_co_u32 v5, vcc_lo, s2, v1
v_add_co_ci_u32_e32 v6, vcc_lo, s3, v2, vcc_lo
global_load_b32 v7, v[3:4], off
global_load_b32 v5, v[5:6], off
v_add_nc_u32_e32 v0, s1, v0
v_add_co_u32 v3, vcc_lo, s4, v1
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v2, vcc_lo
v_add_co_u32 v1, vcc_lo, v1, s10
v_add_co_ci_u32_e32 v2, vcc_lo, s9, v2, vcc_lo
s_waitcnt vmcnt(0)
v_add_f32_e32 v5, v7, v5
v_cmp_le_i32_e64 s0, s8, v0
global_store_b32 v[3:4], v5, off
s_or_b32 s11, s0, s11
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s11
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10vector_addPfS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 12
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10vector_addPfS_S_i, .Lfunc_end0-_Z10vector_addPfS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10vector_addPfS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 14
.sgpr_spill_count: 0
.symbol: _Z10vector_addPfS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <stdio.h>
#include <time.h>
#include <stdlib.h>
#include <hip/hip_runtime.h>
#include <sys/time.h>
#define array_size 268435456
__global__ void vector_add(float *out, float *a, float *b, int n){
int index = threadIdx.x;
int stride = blockDim.x;
for(int i = index; i < n; i += stride){
out[i] = a[i] + b[i];}
}
extern double mysecond();
int main(){
float *a, *b, *out;
float *d_a, *d_b, *d_out;
double t;
// Allocate host memory
a = (float*)malloc(sizeof(float) * array_size);
b = (float*)malloc(sizeof(float) * array_size);
out = (float*)malloc(sizeof(float) * array_size);
// Initialize array
for(int i = 0; i < array_size; i++){
a[i] = 1.0f;
b[i] = 2.0f;
}
// Allocate device memory
hipMalloc((void**)&d_a,sizeof(float)*array_size);
hipMalloc((void**)&d_b,sizeof(float)*array_size);
hipMalloc((void**)&d_out,sizeof(float)*array_size);
t = mysecond();
// Transfer data from host to device memory
hipMemcpy(d_a,a, sizeof(float)*array_size, hipMemcpyHostToDevice);
hipMemcpy(d_b,b, sizeof(float)*array_size, hipMemcpyHostToDevice);
t = (mysecond() - t);
printf ("\nElapsed time for copy from host to device = %g\n", t);
int block_size = 256;
t = mysecond();
// Vector addition
vector_add<<<1,block_size>>>(d_out, d_a, d_b, array_size);
hipDeviceSynchronize();
t = (mysecond() - t);
printf ("\nElapsed time for vector addition in 1 block = %g\n", t);
t = mysecond();
// Transfer data from device to host memory
hipMemcpy(out, d_out, sizeof(float)*array_size, hipMemcpyDeviceToHost);
t = (mysecond() - t);
printf ("\nElapsed time for copy from device to host = %g\n", t);
// Deallocate device memory
hipFree(d_a);
hipFree(d_b);
hipFree(d_out);
// Deallocate host memory
free(a);
free(b);
free(out);
printf ("\nBLock size (number of threads): %d \n", block_size);
printf ("\nNumber of blocks : 1 \n");
}
double mysecond()
{
struct timeval tp;
struct timezone tzp;
gettimeofday(&tp,&tzp);
return ( (double) tp.tv_sec + (double) tp.tv_usec * 1.e-6);
} | .text
.file "vector_add_oneblock.hip"
.globl _Z25__device_stub__vector_addPfS_S_i # -- Begin function _Z25__device_stub__vector_addPfS_S_i
.p2align 4, 0x90
.type _Z25__device_stub__vector_addPfS_S_i,@function
_Z25__device_stub__vector_addPfS_S_i: # @_Z25__device_stub__vector_addPfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10vector_addPfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z25__device_stub__vector_addPfS_S_i, .Lfunc_end0-_Z25__device_stub__vector_addPfS_S_i
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI1_0:
.quad 0x3eb0c6f7a0b5ed8d # double 9.9999999999999995E-7
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $160, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $1073741824, %edi # imm = 0x40000000
callq malloc
movq %rax, %rbx
movl $1073741824, %edi # imm = 0x40000000
callq malloc
movq %rax, %r14
movl $1073741824, %edi # imm = 0x40000000
callq malloc
movq %rax, %r15
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movl $1065353216, (%rbx,%rax,4) # imm = 0x3F800000
movl $1073741824, (%r14,%rax,4) # imm = 0x40000000
incq %rax
cmpq $268435456, %rax # imm = 0x10000000
jne .LBB1_1
# %bb.2:
leaq 88(%rsp), %rdi
movl $1073741824, %esi # imm = 0x40000000
callq hipMalloc
leaq 80(%rsp), %rdi
movl $1073741824, %esi # imm = 0x40000000
callq hipMalloc
leaq 72(%rsp), %rdi
movl $1073741824, %esi # imm = 0x40000000
callq hipMalloc
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
callq gettimeofday
cvtsi2sdq 32(%rsp), %xmm0
cvtsi2sdq 40(%rsp), %xmm1
mulsd .LCPI1_0(%rip), %xmm1
addsd %xmm0, %xmm1
movsd %xmm1, 8(%rsp) # 8-byte Spill
movq 88(%rsp), %rdi
movl $1073741824, %edx # imm = 0x40000000
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 80(%rsp), %rdi
movl $1073741824, %edx # imm = 0x40000000
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
callq gettimeofday
xorps %xmm1, %xmm1
cvtsi2sdq 32(%rsp), %xmm1
xorps %xmm0, %xmm0
cvtsi2sdq 40(%rsp), %xmm0
mulsd .LCPI1_0(%rip), %xmm0
addsd %xmm1, %xmm0
subsd 8(%rsp), %xmm0 # 8-byte Folded Reload
movl $.L.str, %edi
movb $1, %al
callq printf
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
callq gettimeofday
movq 32(%rsp), %r12
movq 40(%rsp), %r13
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 255(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 72(%rsp), %rax
movq 88(%rsp), %rcx
movq 80(%rsp), %rdx
movq %rax, 152(%rsp)
movq %rcx, 144(%rsp)
movq %rdx, 136(%rsp)
movl $268435456, 100(%rsp) # imm = 0x10000000
leaq 152(%rsp), %rax
movq %rax, 32(%rsp)
leaq 144(%rsp), %rax
movq %rax, 40(%rsp)
leaq 136(%rsp), %rax
movq %rax, 48(%rsp)
leaq 100(%rsp), %rax
movq %rax, 56(%rsp)
leaq 16(%rsp), %rdi
leaq 120(%rsp), %rsi
leaq 112(%rsp), %rdx
leaq 104(%rsp), %rcx
callq __hipPopCallConfiguration
movq 16(%rsp), %rsi
movl 24(%rsp), %edx
movq 120(%rsp), %rcx
movl 128(%rsp), %r8d
leaq 32(%rsp), %r9
movl $_Z10vector_addPfS_S_i, %edi
pushq 104(%rsp)
.cfi_adjust_cfa_offset 8
pushq 120(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
xorps %xmm0, %xmm0
cvtsi2sd %r13, %xmm0
movsd .LCPI1_0(%rip), %xmm1 # xmm1 = mem[0],zero
mulsd %xmm1, %xmm0
xorps %xmm1, %xmm1
cvtsi2sd %r12, %xmm1
addsd %xmm0, %xmm1
movsd %xmm1, 8(%rsp) # 8-byte Spill
callq hipDeviceSynchronize
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
callq gettimeofday
xorps %xmm1, %xmm1
cvtsi2sdq 32(%rsp), %xmm1
xorps %xmm0, %xmm0
cvtsi2sdq 40(%rsp), %xmm0
mulsd .LCPI1_0(%rip), %xmm0
addsd %xmm1, %xmm0
subsd 8(%rsp), %xmm0 # 8-byte Folded Reload
movl $.L.str.1, %edi
movb $1, %al
callq printf
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
callq gettimeofday
xorps %xmm0, %xmm0
cvtsi2sdq 32(%rsp), %xmm0
xorps %xmm1, %xmm1
cvtsi2sdq 40(%rsp), %xmm1
mulsd .LCPI1_0(%rip), %xmm1
addsd %xmm0, %xmm1
movsd %xmm1, 8(%rsp) # 8-byte Spill
movq 72(%rsp), %rsi
movl $1073741824, %edx # imm = 0x40000000
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
callq gettimeofday
xorps %xmm1, %xmm1
cvtsi2sdq 32(%rsp), %xmm1
xorps %xmm0, %xmm0
cvtsi2sdq 40(%rsp), %xmm0
mulsd .LCPI1_0(%rip), %xmm0
addsd %xmm1, %xmm0
subsd 8(%rsp), %xmm0 # 8-byte Folded Reload
movl $.L.str.2, %edi
movb $1, %al
callq printf
movq 88(%rsp), %rdi
callq hipFree
movq 80(%rsp), %rdi
callq hipFree
movq 72(%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
movl $.L.str.3, %edi
movl $256, %esi # imm = 0x100
xorl %eax, %eax
callq printf
movl $.Lstr, %edi
callq puts@PLT
xorl %eax, %eax
addq $160, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z8mysecondv
.LCPI2_0:
.quad 0x3eb0c6f7a0b5ed8d # double 9.9999999999999995E-7
.text
.globl _Z8mysecondv
.p2align 4, 0x90
.type _Z8mysecondv,@function
_Z8mysecondv: # @_Z8mysecondv
.cfi_startproc
# %bb.0:
subq $24, %rsp
.cfi_def_cfa_offset 32
movq %rsp, %rdi
leaq 16(%rsp), %rsi
callq gettimeofday
cvtsi2sdq (%rsp), %xmm1
cvtsi2sdq 8(%rsp), %xmm0
mulsd .LCPI2_0(%rip), %xmm0
addsd %xmm1, %xmm0
addq $24, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z8mysecondv, .Lfunc_end2-_Z8mysecondv
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10vector_addPfS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10vector_addPfS_S_i,@object # @_Z10vector_addPfS_S_i
.section .rodata,"a",@progbits
.globl _Z10vector_addPfS_S_i
.p2align 3, 0x0
_Z10vector_addPfS_S_i:
.quad _Z25__device_stub__vector_addPfS_S_i
.size _Z10vector_addPfS_S_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "\nElapsed time for copy from host to device = %g\n"
.size .L.str, 51
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "\nElapsed time for vector addition in 1 block = %g\n"
.size .L.str.1, 51
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "\nElapsed time for copy from device to host = %g\n"
.size .L.str.2, 51
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "\nBLock size (number of threads): %d \n"
.size .L.str.3, 38
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z10vector_addPfS_S_i"
.size .L__unnamed_1, 22
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "\nNumber of blocks : 1 "
.size .Lstr, 36
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__vector_addPfS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10vector_addPfS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z10vector_addPfS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e240000002100 */
/*0020*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x178], PT ; /* 0x00005e0000007a0c */
/* 0x001fda0003f06270 */
/*0030*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0040*/ I2F.U32.RP R5, c[0x0][0x0] ; /* 0x0000000000057b06 */
/* 0x000e220000209000 */
/*0050*/ LOP3.LUT R4, RZ, R0, RZ, 0x33, !PT ; /* 0x00000000ff047212 */
/* 0x000fe200078e33ff */
/*0060*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0070*/ ISETP.NE.U32.AND P2, PT, RZ, c[0x0][0x0], PT ; /* 0x00000000ff007a0c */
/* 0x000fe20003f45070 */
/*0080*/ BSSY B0, 0x2f0 ; /* 0x0000026000007945 */
/* 0x000fe20003800000 */
/*0090*/ IADD3 R4, R4, c[0x0][0x178], RZ ; /* 0x00005e0004047a10 */
/* 0x000fc60007ffe0ff */
/*00a0*/ MUFU.RCP R5, R5 ; /* 0x0000000500057308 */
/* 0x001e240000001000 */
/*00b0*/ IADD3 R2, R5, 0xffffffe, RZ ; /* 0x0ffffffe05027810 */
/* 0x001fcc0007ffe0ff */
/*00c0*/ F2I.FTZ.U32.TRUNC.NTZ R3, R2 ; /* 0x0000000200037305 */
/* 0x000064000021f000 */
/*00d0*/ HFMA2.MMA R2, -RZ, RZ, 0, 0 ; /* 0x00000000ff027435 */
/* 0x001fe200000001ff */
/*00e0*/ IADD3 R7, RZ, -R3, RZ ; /* 0x80000003ff077210 */
/* 0x002fca0007ffe0ff */
/*00f0*/ IMAD R7, R7, c[0x0][0x0], RZ ; /* 0x0000000007077a24 */
/* 0x000fc800078e02ff */
/*0100*/ IMAD.HI.U32 R3, R3, R7, R2 ; /* 0x0000000703037227 */
/* 0x000fcc00078e0002 */
/*0110*/ IMAD.HI.U32 R3, R3, R4, RZ ; /* 0x0000000403037227 */
/* 0x000fca00078e00ff */
/*0120*/ IADD3 R5, -R3, RZ, RZ ; /* 0x000000ff03057210 */
/* 0x000fca0007ffe1ff */
/*0130*/ IMAD R4, R5, c[0x0][0x0], R4 ; /* 0x0000000005047a24 */
/* 0x000fca00078e0204 */
/*0140*/ ISETP.GE.U32.AND P0, PT, R4, c[0x0][0x0], PT ; /* 0x0000000004007a0c */
/* 0x000fda0003f06070 */
/*0150*/ @P0 IADD3 R4, R4, -c[0x0][0x0], RZ ; /* 0x8000000004040a10 */
/* 0x000fe40007ffe0ff */
/*0160*/ @P0 IADD3 R3, R3, 0x1, RZ ; /* 0x0000000103030810 */
/* 0x000fe40007ffe0ff */
/*0170*/ ISETP.GE.U32.AND P1, PT, R4, c[0x0][0x0], PT ; /* 0x0000000004007a0c */
/* 0x000fda0003f26070 */
/*0180*/ @P1 IADD3 R3, R3, 0x1, RZ ; /* 0x0000000103031810 */
/* 0x000fe40007ffe0ff */
/*0190*/ @!P2 LOP3.LUT R3, RZ, c[0x0][0x0], RZ, 0x33, !PT ; /* 0x00000000ff03aa12 */
/* 0x000fc800078e33ff */
/*01a0*/ IADD3 R2, R3.reuse, 0x1, RZ ; /* 0x0000000103027810 */
/* 0x040fe40007ffe0ff */
/*01b0*/ ISETP.GE.U32.AND P1, PT, R3, 0x3, PT ; /* 0x000000030300780c */
/* 0x000fe40003f26070 */
/*01c0*/ LOP3.LUT P0, R2, R2, 0x3, RZ, 0xc0, !PT ; /* 0x0000000302027812 */
/* 0x000fda000780c0ff */
/*01d0*/ @!P0 BRA 0x2e0 ; /* 0x0000010000008947 */
/* 0x000fea0003800000 */
/*01e0*/ MOV R11, 0x4 ; /* 0x00000004000b7802 */
/* 0x000fe40000000f00 */
/*01f0*/ MOV R8, R2 ; /* 0x0000000200087202 */
/* 0x000fc60000000f00 */
/*0200*/ IMAD.WIDE R2, R0, R11, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fc800078e020b */
/*0210*/ IMAD.WIDE R4, R0, R11, c[0x0][0x170] ; /* 0x00005c0000047625 */
/* 0x000fc800078e020b */
/*0220*/ IMAD.WIDE R6, R0, R11, c[0x0][0x168] ; /* 0x00005a0000067625 */
/* 0x000fc800078e020b */
/*0230*/ LDG.E R9, [R4.64] ; /* 0x0000000404097981 */
/* 0x0000a8000c1e1900 */
/*0240*/ LDG.E R10, [R6.64] ; /* 0x00000004060a7981 */
/* 0x0002a2000c1e1900 */
/*0250*/ IADD3 R8, R8, -0x1, RZ ; /* 0xffffffff08087810 */
/* 0x000fe40007ffe0ff */
/*0260*/ IADD3 R0, R0, c[0x0][0x0], RZ ; /* 0x0000000000007a10 */
/* 0x000fe40007ffe0ff */
/*0270*/ ISETP.NE.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fe20003f05270 */
/*0280*/ IMAD.WIDE R4, R11, c[0x0][0x0], R4 ; /* 0x000000000b047a25 */
/* 0x001fc800078e0204 */
/*0290*/ IMAD.WIDE R6, R11, c[0x0][0x0], R6 ; /* 0x000000000b067a25 */
/* 0x002fc800078e0206 */
/*02a0*/ FADD R9, R9, R10 ; /* 0x0000000a09097221 */
/* 0x004fca0000000000 */
/*02b0*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x0001e4000c101904 */
/*02c0*/ IMAD.WIDE R2, R11, c[0x0][0x0], R2 ; /* 0x000000000b027a25 */
/* 0x001fe200078e0202 */
/*02d0*/ @P0 BRA 0x230 ; /* 0xffffff5000000947 */
/* 0x000fea000383ffff */
/*02e0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*02f0*/ @!P1 EXIT ; /* 0x000000000000994d */
/* 0x000fea0003800000 */
/*0300*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x002fd400000001ff */
/*0310*/ IMAD.WIDE R6, R0, R3, c[0x0][0x170] ; /* 0x00005c0000067625 */
/* 0x000fc800078e0203 */
/*0320*/ IMAD.WIDE R4, R0.reuse, R3.reuse, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x0c0fe200078e0203 */
/*0330*/ LDG.E R2, [R6.64] ; /* 0x0000000406027981 */
/* 0x000ea8000c1e1900 */
/*0340*/ LDG.E R11, [R4.64] ; /* 0x00000004040b7981 */
/* 0x000ea2000c1e1900 */
/*0350*/ IMAD.WIDE R8, R0, R3, c[0x0][0x160] ; /* 0x0000580000087625 */
/* 0x000fc800078e0203 */
/*0360*/ IMAD.WIDE R12, R3, c[0x0][0x0], R6 ; /* 0x00000000030c7a25 */
/* 0x000fc800078e0206 */
/*0370*/ FADD R19, R2, R11 ; /* 0x0000000b02137221 */
/* 0x004fe40000000000 */
/*0380*/ IMAD.WIDE R10, R3, c[0x0][0x0], R4 ; /* 0x00000000030a7a25 */
/* 0x000fc600078e0204 */
/*0390*/ STG.E [R8.64], R19 ; /* 0x0000001308007986 */
/* 0x0001e8000c101904 */
/*03a0*/ LDG.E R2, [R12.64] ; /* 0x000000040c027981 */
/* 0x000ea8000c1e1900 */
/*03b0*/ LDG.E R17, [R10.64] ; /* 0x000000040a117981 */
/* 0x000ea2000c1e1900 */
/*03c0*/ IMAD.WIDE R14, R3, c[0x0][0x0], R8 ; /* 0x00000000030e7a25 */
/* 0x000fc800078e0208 */
/*03d0*/ IMAD.WIDE R6, R3, c[0x0][0x0], R12 ; /* 0x0000000003067a25 */
/* 0x000fc800078e020c */
/*03e0*/ IMAD.WIDE R4, R3, c[0x0][0x0], R10 ; /* 0x0000000003047a25 */
/* 0x000fc800078e020a */
/*03f0*/ FADD R21, R2, R17 ; /* 0x0000001102157221 */
/* 0x004fca0000000000 */
/*0400*/ STG.E [R14.64], R21 ; /* 0x000000150e007986 */
/* 0x0003e8000c101904 */
/*0410*/ LDG.E R2, [R6.64] ; /* 0x0000000406027981 */
/* 0x000ea8000c1e1900 */
/*0420*/ LDG.E R23, [R4.64] ; /* 0x0000000404177981 */
/* 0x000ea2000c1e1900 */
/*0430*/ IMAD.WIDE R16, R3, c[0x0][0x0], R14 ; /* 0x0000000003107a25 */
/* 0x000fc800078e020e */
/*0440*/ IMAD.WIDE R12, R3, c[0x0][0x0], R6 ; /* 0x00000000030c7a25 */
/* 0x000fc800078e0206 */
/*0450*/ IMAD.WIDE R8, R3, c[0x0][0x0], R4 ; /* 0x0000000003087a25 */
/* 0x001fc800078e0204 */
/*0460*/ FADD R23, R2, R23 ; /* 0x0000001702177221 */
/* 0x004fca0000000000 */
/*0470*/ STG.E [R16.64], R23 ; /* 0x0000001710007986 */
/* 0x0003e8000c101904 */
/*0480*/ LDG.E R12, [R12.64] ; /* 0x000000040c0c7981 */
/* 0x000ea8000c1e1900 */
/*0490*/ LDG.E R9, [R8.64] ; /* 0x0000000408097981 */
/* 0x000ea2000c1e1900 */
/*04a0*/ MOV R7, c[0x0][0x0] ; /* 0x0000000000077a02 */
/* 0x000fe20000000f00 */
/*04b0*/ IMAD.WIDE R2, R3, c[0x0][0x0], R16 ; /* 0x0000000003027a25 */
/* 0x000fe200078e0210 */
/*04c0*/ MOV R5, c[0x0][0x0] ; /* 0x0000000000057a02 */
/* 0x000fc40000000f00 */
/*04d0*/ LEA R0, R7, R0, 0x1 ; /* 0x0000000007007211 */
/* 0x000fc800078e08ff */
/*04e0*/ LEA R0, R5, R0, 0x1 ; /* 0x0000000005007211 */
/* 0x000fc800078e08ff */
/*04f0*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x178], PT ; /* 0x00005e0000007a0c */
/* 0x000fe20003f06270 */
/*0500*/ FADD R11, R12, R9 ; /* 0x000000090c0b7221 */
/* 0x004fca0000000000 */
/*0510*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x0003ee000c101904 */
/*0520*/ @!P0 BRA 0x300 ; /* 0xfffffdd000008947 */
/* 0x000fea000383ffff */
/*0530*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0540*/ BRA 0x540; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0550*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0560*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0570*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0580*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0590*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10vector_addPfS_S_i
.globl _Z10vector_addPfS_S_i
.p2align 8
.type _Z10vector_addPfS_S_i,@function
_Z10vector_addPfS_S_i:
s_load_b32 s8, s[0:1], 0x18
s_mov_b32 s2, exec_lo
s_waitcnt lgkmcnt(0)
v_cmpx_gt_i32_e64 s8, v0
s_cbranch_execz .LBB0_3
s_clause 0x2
s_load_b32 s9, s[0:1], 0x2c
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[2:3], s[0:1], 0x10
v_dual_mov_b32 v2, 0 :: v_dual_lshlrev_b32 v1, 2, v0
s_waitcnt lgkmcnt(0)
s_and_b32 s1, s9, 0xffff
s_mov_b32 s9, 0
s_lshl_b32 s10, s1, 2
s_mov_b32 s11, s9
.p2align 6
.LBB0_2:
v_add_co_u32 v3, vcc_lo, s6, v1
v_add_co_ci_u32_e32 v4, vcc_lo, s7, v2, vcc_lo
v_add_co_u32 v5, vcc_lo, s2, v1
v_add_co_ci_u32_e32 v6, vcc_lo, s3, v2, vcc_lo
global_load_b32 v7, v[3:4], off
global_load_b32 v5, v[5:6], off
v_add_nc_u32_e32 v0, s1, v0
v_add_co_u32 v3, vcc_lo, s4, v1
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v2, vcc_lo
v_add_co_u32 v1, vcc_lo, v1, s10
v_add_co_ci_u32_e32 v2, vcc_lo, s9, v2, vcc_lo
s_waitcnt vmcnt(0)
v_add_f32_e32 v5, v7, v5
v_cmp_le_i32_e64 s0, s8, v0
global_store_b32 v[3:4], v5, off
s_or_b32 s11, s0, s11
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s11
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10vector_addPfS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 12
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10vector_addPfS_S_i, .Lfunc_end0-_Z10vector_addPfS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10vector_addPfS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 14
.sgpr_spill_count: 0
.symbol: _Z10vector_addPfS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00017391_00000000-6_vector_add_oneblock.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z8mysecondv
.type _Z8mysecondv, @function
_Z8mysecondv:
.LFB2058:
.cfi_startproc
endbr64
subq $56, %rsp
.cfi_def_cfa_offset 64
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rsi
leaq 16(%rsp), %rdi
call gettimeofday@PLT
pxor %xmm0, %xmm0
cvtsi2sdq 24(%rsp), %xmm0
mulsd .LC0(%rip), %xmm0
pxor %xmm1, %xmm1
cvtsi2sdq 16(%rsp), %xmm1
addsd %xmm1, %xmm0
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L6
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L6:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size _Z8mysecondv, .-_Z8mysecondv
.globl _Z35__device_stub__Z10vector_addPfS_S_iPfS_S_i
.type _Z35__device_stub__Z10vector_addPfS_S_iPfS_S_i, @function
_Z35__device_stub__Z10vector_addPfS_S_iPfS_S_i:
.LFB2083:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L11
.L7:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L12
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z10vector_addPfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L7
.L12:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z35__device_stub__Z10vector_addPfS_S_iPfS_S_i, .-_Z35__device_stub__Z10vector_addPfS_S_iPfS_S_i
.globl _Z10vector_addPfS_S_i
.type _Z10vector_addPfS_S_i, @function
_Z10vector_addPfS_S_i:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z10vector_addPfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z10vector_addPfS_S_i, .-_Z10vector_addPfS_S_i
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC3:
.string "\nElapsed time for copy from host to device = %g\n"
.align 8
.LC4:
.string "\nElapsed time for vector addition in 1 block = %g\n"
.align 8
.LC5:
.string "\nElapsed time for copy from device to host = %g\n"
.align 8
.LC6:
.string "\nBLock size (number of threads): %d \n"
.align 8
.LC7:
.string "\nNumber of blocks : 1 \n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $80, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1073741824, %edi
call malloc@PLT
movq %rax, %rbp
movl $1073741824, %edi
call malloc@PLT
movq %rax, %rbx
movl $1073741824, %edi
call malloc@PLT
movq %rax, %r12
movl $0, %eax
movss .LC1(%rip), %xmm1
movss .LC2(%rip), %xmm0
.L16:
movss %xmm1, 0(%rbp,%rax)
movss %xmm0, (%rbx,%rax)
addq $4, %rax
cmpq $1073741824, %rax
jne .L16
leaq 24(%rsp), %rdi
movl $1073741824, %esi
call cudaMalloc@PLT
leaq 32(%rsp), %rdi
movl $1073741824, %esi
call cudaMalloc@PLT
leaq 40(%rsp), %rdi
movl $1073741824, %esi
call cudaMalloc@PLT
call _Z8mysecondv
movsd %xmm0, 8(%rsp)
movl $1, %ecx
movl $1073741824, %edx
movq %rbp, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $1073741824, %edx
movq %rbx, %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
call _Z8mysecondv
subsd 8(%rsp), %xmm0
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
call _Z8mysecondv
movsd %xmm0, 8(%rsp)
movl $256, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movl $1, %ecx
movq 48(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L21
.L17:
call cudaDeviceSynchronize@PLT
call _Z8mysecondv
subsd 8(%rsp), %xmm0
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
call _Z8mysecondv
movsd %xmm0, 8(%rsp)
movl $2, %ecx
movl $1073741824, %edx
movq 40(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
call _Z8mysecondv
subsd 8(%rsp), %xmm0
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq %rbp, %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
movl $256, %edx
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L22
movl $0, %eax
addq $80, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L21:
.cfi_restore_state
movl $268435456, %ecx
movq 32(%rsp), %rdx
movq 24(%rsp), %rsi
movq 40(%rsp), %rdi
call _Z35__device_stub__Z10vector_addPfS_S_iPfS_S_i
jmp .L17
.L22:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC8:
.string "_Z10vector_addPfS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _Z10vector_addPfS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long -1598689907
.long 1051772663
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC1:
.long 1065353216
.align 4
.LC2:
.long 1073741824
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "vector_add_oneblock.hip"
.globl _Z25__device_stub__vector_addPfS_S_i # -- Begin function _Z25__device_stub__vector_addPfS_S_i
.p2align 4, 0x90
.type _Z25__device_stub__vector_addPfS_S_i,@function
_Z25__device_stub__vector_addPfS_S_i: # @_Z25__device_stub__vector_addPfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10vector_addPfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z25__device_stub__vector_addPfS_S_i, .Lfunc_end0-_Z25__device_stub__vector_addPfS_S_i
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI1_0:
.quad 0x3eb0c6f7a0b5ed8d # double 9.9999999999999995E-7
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $160, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $1073741824, %edi # imm = 0x40000000
callq malloc
movq %rax, %rbx
movl $1073741824, %edi # imm = 0x40000000
callq malloc
movq %rax, %r14
movl $1073741824, %edi # imm = 0x40000000
callq malloc
movq %rax, %r15
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movl $1065353216, (%rbx,%rax,4) # imm = 0x3F800000
movl $1073741824, (%r14,%rax,4) # imm = 0x40000000
incq %rax
cmpq $268435456, %rax # imm = 0x10000000
jne .LBB1_1
# %bb.2:
leaq 88(%rsp), %rdi
movl $1073741824, %esi # imm = 0x40000000
callq hipMalloc
leaq 80(%rsp), %rdi
movl $1073741824, %esi # imm = 0x40000000
callq hipMalloc
leaq 72(%rsp), %rdi
movl $1073741824, %esi # imm = 0x40000000
callq hipMalloc
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
callq gettimeofday
cvtsi2sdq 32(%rsp), %xmm0
cvtsi2sdq 40(%rsp), %xmm1
mulsd .LCPI1_0(%rip), %xmm1
addsd %xmm0, %xmm1
movsd %xmm1, 8(%rsp) # 8-byte Spill
movq 88(%rsp), %rdi
movl $1073741824, %edx # imm = 0x40000000
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 80(%rsp), %rdi
movl $1073741824, %edx # imm = 0x40000000
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
callq gettimeofday
xorps %xmm1, %xmm1
cvtsi2sdq 32(%rsp), %xmm1
xorps %xmm0, %xmm0
cvtsi2sdq 40(%rsp), %xmm0
mulsd .LCPI1_0(%rip), %xmm0
addsd %xmm1, %xmm0
subsd 8(%rsp), %xmm0 # 8-byte Folded Reload
movl $.L.str, %edi
movb $1, %al
callq printf
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
callq gettimeofday
movq 32(%rsp), %r12
movq 40(%rsp), %r13
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 255(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 72(%rsp), %rax
movq 88(%rsp), %rcx
movq 80(%rsp), %rdx
movq %rax, 152(%rsp)
movq %rcx, 144(%rsp)
movq %rdx, 136(%rsp)
movl $268435456, 100(%rsp) # imm = 0x10000000
leaq 152(%rsp), %rax
movq %rax, 32(%rsp)
leaq 144(%rsp), %rax
movq %rax, 40(%rsp)
leaq 136(%rsp), %rax
movq %rax, 48(%rsp)
leaq 100(%rsp), %rax
movq %rax, 56(%rsp)
leaq 16(%rsp), %rdi
leaq 120(%rsp), %rsi
leaq 112(%rsp), %rdx
leaq 104(%rsp), %rcx
callq __hipPopCallConfiguration
movq 16(%rsp), %rsi
movl 24(%rsp), %edx
movq 120(%rsp), %rcx
movl 128(%rsp), %r8d
leaq 32(%rsp), %r9
movl $_Z10vector_addPfS_S_i, %edi
pushq 104(%rsp)
.cfi_adjust_cfa_offset 8
pushq 120(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
xorps %xmm0, %xmm0
cvtsi2sd %r13, %xmm0
movsd .LCPI1_0(%rip), %xmm1 # xmm1 = mem[0],zero
mulsd %xmm1, %xmm0
xorps %xmm1, %xmm1
cvtsi2sd %r12, %xmm1
addsd %xmm0, %xmm1
movsd %xmm1, 8(%rsp) # 8-byte Spill
callq hipDeviceSynchronize
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
callq gettimeofday
xorps %xmm1, %xmm1
cvtsi2sdq 32(%rsp), %xmm1
xorps %xmm0, %xmm0
cvtsi2sdq 40(%rsp), %xmm0
mulsd .LCPI1_0(%rip), %xmm0
addsd %xmm1, %xmm0
subsd 8(%rsp), %xmm0 # 8-byte Folded Reload
movl $.L.str.1, %edi
movb $1, %al
callq printf
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
callq gettimeofday
xorps %xmm0, %xmm0
cvtsi2sdq 32(%rsp), %xmm0
xorps %xmm1, %xmm1
cvtsi2sdq 40(%rsp), %xmm1
mulsd .LCPI1_0(%rip), %xmm1
addsd %xmm0, %xmm1
movsd %xmm1, 8(%rsp) # 8-byte Spill
movq 72(%rsp), %rsi
movl $1073741824, %edx # imm = 0x40000000
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
callq gettimeofday
xorps %xmm1, %xmm1
cvtsi2sdq 32(%rsp), %xmm1
xorps %xmm0, %xmm0
cvtsi2sdq 40(%rsp), %xmm0
mulsd .LCPI1_0(%rip), %xmm0
addsd %xmm1, %xmm0
subsd 8(%rsp), %xmm0 # 8-byte Folded Reload
movl $.L.str.2, %edi
movb $1, %al
callq printf
movq 88(%rsp), %rdi
callq hipFree
movq 80(%rsp), %rdi
callq hipFree
movq 72(%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
movl $.L.str.3, %edi
movl $256, %esi # imm = 0x100
xorl %eax, %eax
callq printf
movl $.Lstr, %edi
callq puts@PLT
xorl %eax, %eax
addq $160, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z8mysecondv
.LCPI2_0:
.quad 0x3eb0c6f7a0b5ed8d # double 9.9999999999999995E-7
.text
.globl _Z8mysecondv
.p2align 4, 0x90
.type _Z8mysecondv,@function
_Z8mysecondv: # @_Z8mysecondv
.cfi_startproc
# %bb.0:
subq $24, %rsp
.cfi_def_cfa_offset 32
movq %rsp, %rdi
leaq 16(%rsp), %rsi
callq gettimeofday
cvtsi2sdq (%rsp), %xmm1
cvtsi2sdq 8(%rsp), %xmm0
mulsd .LCPI2_0(%rip), %xmm0
addsd %xmm1, %xmm0
addq $24, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z8mysecondv, .Lfunc_end2-_Z8mysecondv
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10vector_addPfS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10vector_addPfS_S_i,@object # @_Z10vector_addPfS_S_i
.section .rodata,"a",@progbits
.globl _Z10vector_addPfS_S_i
.p2align 3, 0x0
_Z10vector_addPfS_S_i:
.quad _Z25__device_stub__vector_addPfS_S_i
.size _Z10vector_addPfS_S_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "\nElapsed time for copy from host to device = %g\n"
.size .L.str, 51
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "\nElapsed time for vector addition in 1 block = %g\n"
.size .L.str.1, 51
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "\nElapsed time for copy from device to host = %g\n"
.size .L.str.2, 51
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "\nBLock size (number of threads): %d \n"
.size .L.str.3, 38
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z10vector_addPfS_S_i"
.size .L__unnamed_1, 22
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "\nNumber of blocks : 1 "
.size .Lstr, 36
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__vector_addPfS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10vector_addPfS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
/**
* Quantum Lattice Boltzmann
* (c) 2015 Fabian Thüring, ETH Zurich
*
* This file contains all the CUDA kernels and function that make use of the
* CUDA runtime API
*/
// Local includes
// ==== CONSTANTS ====
__constant__ unsigned int d_L;
__constant__ float d_dx;
__constant__ float d_dt;
__constant__ float d_mass;
__constant__ float d_g;
__constant__ unsigned int d_t;
__constant__ float d_scaling;
__constant__ int d_current_scene;
// ==== INITIALIZATION ====
__global__ void kernel_calculate_vertex_V(float3* vbo_ptr, float* d_ptr)
{
int i = blockIdx.x*blockDim.x + threadIdx.x;
int j = blockIdx.y*blockDim.y + threadIdx.y;
if(i < d_L && j < d_L)
vbo_ptr[d_L*i + j].y = d_scaling * fabsf( d_ptr[i*d_L +j] ) - 0.005f*d_L;
} | code for sm_80
Function : _Z25kernel_calculate_vertex_VP6float3Pf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e280000002600 */
/*0020*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e280000002200 */
/*0030*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e680000002500 */
/*0040*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0050*/ IMAD R3, R3, c[0x0][0x4], R2 ; /* 0x0000010003037a24 */
/* 0x001fca00078e0202 */
/*0060*/ ISETP.GE.U32.AND P0, PT, R3, c[0x3][0x0], PT ; /* 0x00c0000003007a0c */
/* 0x000fe20003f06070 */
/*0070*/ IMAD R0, R0, c[0x0][0x0], R5 ; /* 0x0000000000007a24 */
/* 0x002fca00078e0205 */
/*0080*/ ISETP.GE.U32.OR P0, PT, R0, c[0x3][0x0], P0 ; /* 0x00c0000000007a0c */
/* 0x000fda0000706470 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*00b0*/ IMAD R0, R0, c[0x3][0x0], R3 ; /* 0x00c0000000007a24 */
/* 0x000fe200078e0203 */
/*00c0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd00000000a00 */
/*00d0*/ IMAD.WIDE.U32 R2, R0, R5, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x000fcc00078e0005 */
/*00e0*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*00f0*/ I2F.U32 R4, c[0x3][0x0] ; /* 0x00c0000000047b06 */
/* 0x000e220000201000 */
/*0100*/ HFMA2.MMA R5, -RZ, RZ, 0, 7.152557373046875e-07 ; /* 0x0000000cff057435 */
/* 0x000fe200000001ff */
/*0110*/ FMUL R7, R4, -0.0049999998882412910461 ; /* 0xbba3d70a04077820 */
/* 0x001fd20000400000 */
/*0120*/ IMAD.WIDE.U32 R4, R0, R5, c[0x0][0x160] ; /* 0x0000580000047625 */
/* 0x000fc800078e0005 */
/*0130*/ FFMA R7, |R2|, c[0x3][0x18], R7 ; /* 0x00c0060002077a23 */
/* 0x004fca0000000207 */
/*0140*/ STG.E [R4.64+0x4], R7 ; /* 0x0000040704007986 */
/* 0x000fe2000c101904 */
/*0150*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0160*/ BRA 0x160; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
/**
* Quantum Lattice Boltzmann
* (c) 2015 Fabian Thüring, ETH Zurich
*
* This file contains all the CUDA kernels and function that make use of the
* CUDA runtime API
*/
// Local includes
// ==== CONSTANTS ====
__constant__ unsigned int d_L;
__constant__ float d_dx;
__constant__ float d_dt;
__constant__ float d_mass;
__constant__ float d_g;
__constant__ unsigned int d_t;
__constant__ float d_scaling;
__constant__ int d_current_scene;
// ==== INITIALIZATION ====
__global__ void kernel_calculate_vertex_V(float3* vbo_ptr, float* d_ptr)
{
int i = blockIdx.x*blockDim.x + threadIdx.x;
int j = blockIdx.y*blockDim.y + threadIdx.y;
if(i < d_L && j < d_L)
vbo_ptr[d_L*i + j].y = d_scaling * fabsf( d_ptr[i*d_L +j] ) - 0.005f*d_L;
} | .file "tmpxft_000fd71c_00000000-6_kernel_calculate_vertex_V.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z53__device_stub__Z25kernel_calculate_vertex_VP6float3PfP6float3Pf
.type _Z53__device_stub__Z25kernel_calculate_vertex_VP6float3PfP6float3Pf, @function
_Z53__device_stub__Z25kernel_calculate_vertex_VP6float3PfP6float3Pf:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z25kernel_calculate_vertex_VP6float3Pf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z53__device_stub__Z25kernel_calculate_vertex_VP6float3PfP6float3Pf, .-_Z53__device_stub__Z25kernel_calculate_vertex_VP6float3PfP6float3Pf
.globl _Z25kernel_calculate_vertex_VP6float3Pf
.type _Z25kernel_calculate_vertex_VP6float3Pf, @function
_Z25kernel_calculate_vertex_VP6float3Pf:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z53__device_stub__Z25kernel_calculate_vertex_VP6float3PfP6float3Pf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z25kernel_calculate_vertex_VP6float3Pf, .-_Z25kernel_calculate_vertex_VP6float3Pf
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z25kernel_calculate_vertex_VP6float3Pf"
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "d_L"
.LC2:
.string "d_dx"
.LC3:
.string "d_dt"
.LC4:
.string "d_mass"
.LC5:
.string "d_g"
.LC6:
.string "d_t"
.LC7:
.string "d_scaling"
.LC8:
.string "d_current_scene"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z25kernel_calculate_vertex_VP6float3Pf(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $4, %r9d
movl $0, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _ZL3d_L(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $4, %r9d
movl $0, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _ZL4d_dx(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $4, %r9d
movl $0, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _ZL4d_dt(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $4, %r9d
movl $0, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _ZL6d_mass(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $4, %r9d
movl $0, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _ZL3d_g(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $4, %r9d
movl $0, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _ZL3d_t(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $4, %r9d
movl $0, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _ZL9d_scaling(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $4, %r9d
movl $0, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _ZL15d_current_scene(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL15d_current_scene
.comm _ZL15d_current_scene,4,4
.local _ZL9d_scaling
.comm _ZL9d_scaling,4,4
.local _ZL3d_t
.comm _ZL3d_t,4,4
.local _ZL3d_g
.comm _ZL3d_g,4,4
.local _ZL6d_mass
.comm _ZL6d_mass,4,4
.local _ZL4d_dt
.comm _ZL4d_dt,4,4
.local _ZL4d_dx
.comm _ZL4d_dx,4,4
.local _ZL3d_L
.comm _ZL3d_L,4,4
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
/**
* Quantum Lattice Boltzmann
* (c) 2015 Fabian Thüring, ETH Zurich
*
* This file contains all the CUDA kernels and function that make use of the
* CUDA runtime API
*/
// Local includes
// ==== CONSTANTS ====
__constant__ unsigned int d_L;
__constant__ float d_dx;
__constant__ float d_dt;
__constant__ float d_mass;
__constant__ float d_g;
__constant__ unsigned int d_t;
__constant__ float d_scaling;
__constant__ int d_current_scene;
// ==== INITIALIZATION ====
__global__ void kernel_calculate_vertex_V(float3* vbo_ptr, float* d_ptr)
{
int i = blockIdx.x*blockDim.x + threadIdx.x;
int j = blockIdx.y*blockDim.y + threadIdx.y;
if(i < d_L && j < d_L)
vbo_ptr[d_L*i + j].y = d_scaling * fabsf( d_ptr[i*d_L +j] ) - 0.005f*d_L;
} | #include <hip/hip_runtime.h>
#include "includes.h"
/**
* Quantum Lattice Boltzmann
* (c) 2015 Fabian Thüring, ETH Zurich
*
* This file contains all the CUDA kernels and function that make use of the
* CUDA runtime API
*/
// Local includes
// ==== CONSTANTS ====
__constant__ unsigned int d_L;
__constant__ float d_dx;
__constant__ float d_dt;
__constant__ float d_mass;
__constant__ float d_g;
__constant__ unsigned int d_t;
__constant__ float d_scaling;
__constant__ int d_current_scene;
// ==== INITIALIZATION ====
__global__ void kernel_calculate_vertex_V(float3* vbo_ptr, float* d_ptr)
{
int i = blockIdx.x*blockDim.x + threadIdx.x;
int j = blockIdx.y*blockDim.y + threadIdx.y;
if(i < d_L && j < d_L)
vbo_ptr[d_L*i + j].y = d_scaling * fabsf( d_ptr[i*d_L +j] ) - 0.005f*d_L;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
/**
* Quantum Lattice Boltzmann
* (c) 2015 Fabian Thüring, ETH Zurich
*
* This file contains all the CUDA kernels and function that make use of the
* CUDA runtime API
*/
// Local includes
// ==== CONSTANTS ====
__constant__ unsigned int d_L;
__constant__ float d_dx;
__constant__ float d_dt;
__constant__ float d_mass;
__constant__ float d_g;
__constant__ unsigned int d_t;
__constant__ float d_scaling;
__constant__ int d_current_scene;
// ==== INITIALIZATION ====
__global__ void kernel_calculate_vertex_V(float3* vbo_ptr, float* d_ptr)
{
int i = blockIdx.x*blockDim.x + threadIdx.x;
int j = blockIdx.y*blockDim.y + threadIdx.y;
if(i < d_L && j < d_L)
vbo_ptr[d_L*i + j].y = d_scaling * fabsf( d_ptr[i*d_L +j] ) - 0.005f*d_L;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z25kernel_calculate_vertex_VP15HIP_vector_typeIfLj3EEPf
.globl _Z25kernel_calculate_vertex_VP15HIP_vector_typeIfLj3EEPf
.p2align 8
.type _Z25kernel_calculate_vertex_VP15HIP_vector_typeIfLj3EEPf,@function
_Z25kernel_calculate_vertex_VP15HIP_vector_typeIfLj3EEPf:
s_load_b32 s4, s[0:1], 0x1c
s_getpc_b64 s[2:3]
s_add_u32 s2, s2, d_L@rel32@lo+4
s_addc_u32 s3, s3, d_L@rel32@hi+12
v_and_b32_e32 v2, 0x3ff, v0
s_load_b32 s2, s[2:3], 0x0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s4, 0xffff
s_lshr_b32 s4, s4, 16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[0:1], null, s14, s3, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s4, v[3:4]
s_mov_b32 s3, exec_lo
v_max_u32_e32 v2, v0, v1
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_u32_e64 s2, v2
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_mad_u64_u32 v[2:3], null, v0, s2, v[1:2]
v_mov_b32_e32 v3, 0
s_getpc_b64 s[0:1]
s_add_u32 s0, s0, d_scaling@rel32@lo+4
s_addc_u32 s1, s1, d_scaling@rel32@hi+12
s_load_b32 s0, s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[2:3]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s6, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
global_load_b32 v3, v[0:1], off
v_cvt_f32_u32_e32 v0, s2
v_mul_f32_e32 v4, 0xbba3d70a, v0
v_mad_u64_u32 v[0:1], null, v2, 12, s[4:5]
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_2)
v_fma_f32 v2, s0, |v3|, v4
global_store_b32 v[0:1], v2, off offset:4
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z25kernel_calculate_vertex_VP15HIP_vector_typeIfLj3EEPf
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z25kernel_calculate_vertex_VP15HIP_vector_typeIfLj3EEPf, .Lfunc_end0-_Z25kernel_calculate_vertex_VP15HIP_vector_typeIfLj3EEPf
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.protected d_L
.type d_L,@object
.section .bss,"aw",@nobits
.globl d_L
.p2align 2, 0x0
d_L:
.long 0
.size d_L, 4
.protected d_dx
.type d_dx,@object
.globl d_dx
.p2align 2, 0x0
d_dx:
.long 0x00000000
.size d_dx, 4
.protected d_dt
.type d_dt,@object
.globl d_dt
.p2align 2, 0x0
d_dt:
.long 0x00000000
.size d_dt, 4
.protected d_mass
.type d_mass,@object
.globl d_mass
.p2align 2, 0x0
d_mass:
.long 0x00000000
.size d_mass, 4
.protected d_g
.type d_g,@object
.globl d_g
.p2align 2, 0x0
d_g:
.long 0x00000000
.size d_g, 4
.protected d_t
.type d_t,@object
.globl d_t
.p2align 2, 0x0
d_t:
.long 0
.size d_t, 4
.protected d_scaling
.type d_scaling,@object
.globl d_scaling
.p2align 2, 0x0
d_scaling:
.long 0x00000000
.size d_scaling, 4
.protected d_current_scene
.type d_current_scene,@object
.globl d_current_scene
.p2align 2, 0x0
d_current_scene:
.long 0
.size d_current_scene, 4
.type __hip_cuid_,@object
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym d_L
.addrsig_sym d_scaling
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z25kernel_calculate_vertex_VP15HIP_vector_typeIfLj3EEPf
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z25kernel_calculate_vertex_VP15HIP_vector_typeIfLj3EEPf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
/**
* Quantum Lattice Boltzmann
* (c) 2015 Fabian Thüring, ETH Zurich
*
* This file contains all the CUDA kernels and function that make use of the
* CUDA runtime API
*/
// Local includes
// ==== CONSTANTS ====
__constant__ unsigned int d_L;
__constant__ float d_dx;
__constant__ float d_dt;
__constant__ float d_mass;
__constant__ float d_g;
__constant__ unsigned int d_t;
__constant__ float d_scaling;
__constant__ int d_current_scene;
// ==== INITIALIZATION ====
__global__ void kernel_calculate_vertex_V(float3* vbo_ptr, float* d_ptr)
{
int i = blockIdx.x*blockDim.x + threadIdx.x;
int j = blockIdx.y*blockDim.y + threadIdx.y;
if(i < d_L && j < d_L)
vbo_ptr[d_L*i + j].y = d_scaling * fabsf( d_ptr[i*d_L +j] ) - 0.005f*d_L;
} | .text
.file "kernel_calculate_vertex_V.hip"
.globl _Z40__device_stub__kernel_calculate_vertex_VP15HIP_vector_typeIfLj3EEPf # -- Begin function _Z40__device_stub__kernel_calculate_vertex_VP15HIP_vector_typeIfLj3EEPf
.p2align 4, 0x90
.type _Z40__device_stub__kernel_calculate_vertex_VP15HIP_vector_typeIfLj3EEPf,@function
_Z40__device_stub__kernel_calculate_vertex_VP15HIP_vector_typeIfLj3EEPf: # @_Z40__device_stub__kernel_calculate_vertex_VP15HIP_vector_typeIfLj3EEPf
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z25kernel_calculate_vertex_VP15HIP_vector_typeIfLj3EEPf, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z40__device_stub__kernel_calculate_vertex_VP15HIP_vector_typeIfLj3EEPf, .Lfunc_end0-_Z40__device_stub__kernel_calculate_vertex_VP15HIP_vector_typeIfLj3EEPf
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rbx
subq $32, %rsp
.cfi_adjust_cfa_offset 32
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z25kernel_calculate_vertex_VP15HIP_vector_typeIfLj3EEPf, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
addq $32, %rsp
.cfi_adjust_cfa_offset -32
movl $d_L, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movl $4, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
pushq $0
.cfi_adjust_cfa_offset 8
pushq $1
.cfi_adjust_cfa_offset 8
callq __hipRegisterVar
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movl $d_dx, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movl $4, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
pushq $0
.cfi_adjust_cfa_offset 8
pushq $1
.cfi_adjust_cfa_offset 8
callq __hipRegisterVar
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movl $d_dt, %esi
movl $.L__unnamed_4, %edx
movl $.L__unnamed_4, %ecx
movl $4, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
pushq $0
.cfi_adjust_cfa_offset 8
pushq $1
.cfi_adjust_cfa_offset 8
callq __hipRegisterVar
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movl $d_mass, %esi
movl $.L__unnamed_5, %edx
movl $.L__unnamed_5, %ecx
movl $4, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
pushq $0
.cfi_adjust_cfa_offset 8
pushq $1
.cfi_adjust_cfa_offset 8
callq __hipRegisterVar
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movl $d_g, %esi
movl $.L__unnamed_6, %edx
movl $.L__unnamed_6, %ecx
movl $4, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
pushq $0
.cfi_adjust_cfa_offset 8
pushq $1
.cfi_adjust_cfa_offset 8
callq __hipRegisterVar
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movl $d_t, %esi
movl $.L__unnamed_7, %edx
movl $.L__unnamed_7, %ecx
movl $4, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
pushq $0
.cfi_adjust_cfa_offset 8
pushq $1
.cfi_adjust_cfa_offset 8
callq __hipRegisterVar
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movl $d_scaling, %esi
movl $.L__unnamed_8, %edx
movl $.L__unnamed_8, %ecx
movl $4, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
pushq $0
.cfi_adjust_cfa_offset 8
pushq $1
.cfi_adjust_cfa_offset 8
callq __hipRegisterVar
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movl $d_current_scene, %esi
movl $.L__unnamed_9, %edx
movl $.L__unnamed_9, %ecx
movl $4, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
pushq $0
.cfi_adjust_cfa_offset 8
pushq $1
.cfi_adjust_cfa_offset 8
callq __hipRegisterVar
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movl $__hip_module_dtor, %edi
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type d_L,@object # @d_L
.local d_L
.comm d_L,4,4
.type d_dx,@object # @d_dx
.local d_dx
.comm d_dx,4,4
.type d_dt,@object # @d_dt
.local d_dt
.comm d_dt,4,4
.type d_mass,@object # @d_mass
.local d_mass
.comm d_mass,4,4
.type d_g,@object # @d_g
.local d_g
.comm d_g,4,4
.type d_t,@object # @d_t
.local d_t
.comm d_t,4,4
.type d_scaling,@object # @d_scaling
.local d_scaling
.comm d_scaling,4,4
.type d_current_scene,@object # @d_current_scene
.local d_current_scene
.comm d_current_scene,4,4
.type _Z25kernel_calculate_vertex_VP15HIP_vector_typeIfLj3EEPf,@object # @_Z25kernel_calculate_vertex_VP15HIP_vector_typeIfLj3EEPf
.section .rodata,"a",@progbits
.globl _Z25kernel_calculate_vertex_VP15HIP_vector_typeIfLj3EEPf
.p2align 3, 0x0
_Z25kernel_calculate_vertex_VP15HIP_vector_typeIfLj3EEPf:
.quad _Z40__device_stub__kernel_calculate_vertex_VP15HIP_vector_typeIfLj3EEPf
.size _Z25kernel_calculate_vertex_VP15HIP_vector_typeIfLj3EEPf, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z25kernel_calculate_vertex_VP15HIP_vector_typeIfLj3EEPf"
.size .L__unnamed_1, 57
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "d_L"
.size .L__unnamed_2, 4
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "d_dx"
.size .L__unnamed_3, 5
.type .L__unnamed_4,@object # @3
.L__unnamed_4:
.asciz "d_dt"
.size .L__unnamed_4, 5
.type .L__unnamed_5,@object # @4
.L__unnamed_5:
.asciz "d_mass"
.size .L__unnamed_5, 7
.type .L__unnamed_6,@object # @5
.L__unnamed_6:
.asciz "d_g"
.size .L__unnamed_6, 4
.type .L__unnamed_7,@object # @6
.L__unnamed_7:
.asciz "d_t"
.size .L__unnamed_7, 4
.type .L__unnamed_8,@object # @7
.L__unnamed_8:
.asciz "d_scaling"
.size .L__unnamed_8, 10
.type .L__unnamed_9,@object # @8
.L__unnamed_9:
.asciz "d_current_scene"
.size .L__unnamed_9, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z40__device_stub__kernel_calculate_vertex_VP15HIP_vector_typeIfLj3EEPf
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym d_L
.addrsig_sym d_dx
.addrsig_sym d_dt
.addrsig_sym d_mass
.addrsig_sym d_g
.addrsig_sym d_t
.addrsig_sym d_scaling
.addrsig_sym d_current_scene
.addrsig_sym _Z25kernel_calculate_vertex_VP15HIP_vector_typeIfLj3EEPf
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z25kernel_calculate_vertex_VP6float3Pf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e280000002600 */
/*0020*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e280000002200 */
/*0030*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e680000002500 */
/*0040*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0050*/ IMAD R3, R3, c[0x0][0x4], R2 ; /* 0x0000010003037a24 */
/* 0x001fca00078e0202 */
/*0060*/ ISETP.GE.U32.AND P0, PT, R3, c[0x3][0x0], PT ; /* 0x00c0000003007a0c */
/* 0x000fe20003f06070 */
/*0070*/ IMAD R0, R0, c[0x0][0x0], R5 ; /* 0x0000000000007a24 */
/* 0x002fca00078e0205 */
/*0080*/ ISETP.GE.U32.OR P0, PT, R0, c[0x3][0x0], P0 ; /* 0x00c0000000007a0c */
/* 0x000fda0000706470 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*00b0*/ IMAD R0, R0, c[0x3][0x0], R3 ; /* 0x00c0000000007a24 */
/* 0x000fe200078e0203 */
/*00c0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd00000000a00 */
/*00d0*/ IMAD.WIDE.U32 R2, R0, R5, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x000fcc00078e0005 */
/*00e0*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*00f0*/ I2F.U32 R4, c[0x3][0x0] ; /* 0x00c0000000047b06 */
/* 0x000e220000201000 */
/*0100*/ HFMA2.MMA R5, -RZ, RZ, 0, 7.152557373046875e-07 ; /* 0x0000000cff057435 */
/* 0x000fe200000001ff */
/*0110*/ FMUL R7, R4, -0.0049999998882412910461 ; /* 0xbba3d70a04077820 */
/* 0x001fd20000400000 */
/*0120*/ IMAD.WIDE.U32 R4, R0, R5, c[0x0][0x160] ; /* 0x0000580000047625 */
/* 0x000fc800078e0005 */
/*0130*/ FFMA R7, |R2|, c[0x3][0x18], R7 ; /* 0x00c0060002077a23 */
/* 0x004fca0000000207 */
/*0140*/ STG.E [R4.64+0x4], R7 ; /* 0x0000040704007986 */
/* 0x000fe2000c101904 */
/*0150*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0160*/ BRA 0x160; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z25kernel_calculate_vertex_VP15HIP_vector_typeIfLj3EEPf
.globl _Z25kernel_calculate_vertex_VP15HIP_vector_typeIfLj3EEPf
.p2align 8
.type _Z25kernel_calculate_vertex_VP15HIP_vector_typeIfLj3EEPf,@function
_Z25kernel_calculate_vertex_VP15HIP_vector_typeIfLj3EEPf:
s_load_b32 s4, s[0:1], 0x1c
s_getpc_b64 s[2:3]
s_add_u32 s2, s2, d_L@rel32@lo+4
s_addc_u32 s3, s3, d_L@rel32@hi+12
v_and_b32_e32 v2, 0x3ff, v0
s_load_b32 s2, s[2:3], 0x0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s4, 0xffff
s_lshr_b32 s4, s4, 16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[0:1], null, s14, s3, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s4, v[3:4]
s_mov_b32 s3, exec_lo
v_max_u32_e32 v2, v0, v1
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_u32_e64 s2, v2
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_mad_u64_u32 v[2:3], null, v0, s2, v[1:2]
v_mov_b32_e32 v3, 0
s_getpc_b64 s[0:1]
s_add_u32 s0, s0, d_scaling@rel32@lo+4
s_addc_u32 s1, s1, d_scaling@rel32@hi+12
s_load_b32 s0, s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[2:3]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s6, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
global_load_b32 v3, v[0:1], off
v_cvt_f32_u32_e32 v0, s2
v_mul_f32_e32 v4, 0xbba3d70a, v0
v_mad_u64_u32 v[0:1], null, v2, 12, s[4:5]
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_2)
v_fma_f32 v2, s0, |v3|, v4
global_store_b32 v[0:1], v2, off offset:4
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z25kernel_calculate_vertex_VP15HIP_vector_typeIfLj3EEPf
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z25kernel_calculate_vertex_VP15HIP_vector_typeIfLj3EEPf, .Lfunc_end0-_Z25kernel_calculate_vertex_VP15HIP_vector_typeIfLj3EEPf
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.protected d_L
.type d_L,@object
.section .bss,"aw",@nobits
.globl d_L
.p2align 2, 0x0
d_L:
.long 0
.size d_L, 4
.protected d_dx
.type d_dx,@object
.globl d_dx
.p2align 2, 0x0
d_dx:
.long 0x00000000
.size d_dx, 4
.protected d_dt
.type d_dt,@object
.globl d_dt
.p2align 2, 0x0
d_dt:
.long 0x00000000
.size d_dt, 4
.protected d_mass
.type d_mass,@object
.globl d_mass
.p2align 2, 0x0
d_mass:
.long 0x00000000
.size d_mass, 4
.protected d_g
.type d_g,@object
.globl d_g
.p2align 2, 0x0
d_g:
.long 0x00000000
.size d_g, 4
.protected d_t
.type d_t,@object
.globl d_t
.p2align 2, 0x0
d_t:
.long 0
.size d_t, 4
.protected d_scaling
.type d_scaling,@object
.globl d_scaling
.p2align 2, 0x0
d_scaling:
.long 0x00000000
.size d_scaling, 4
.protected d_current_scene
.type d_current_scene,@object
.globl d_current_scene
.p2align 2, 0x0
d_current_scene:
.long 0
.size d_current_scene, 4
.type __hip_cuid_,@object
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym d_L
.addrsig_sym d_scaling
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z25kernel_calculate_vertex_VP15HIP_vector_typeIfLj3EEPf
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z25kernel_calculate_vertex_VP15HIP_vector_typeIfLj3EEPf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
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