system stringclasses 7 values | input stringlengths 10 94.5k | output stringlengths 14 55.5k |
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You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | //optimization homework #4 cs 677 Theodore Jagodits
#include <time.h>
#include <stdio.h>
#include <stdlib.h>
#include "string.h"
#include <iostream>
#define DEFAULT_ROW 128
#define DEFAULT_COL 128
#define TILE_SIZE 16
#define MAX_CONST 16000
//add constant memory
__constant__ float c_inp[MAX_CONST];
//tiling complete
__global__ void unknown_algo_inp2(float *inp2, float *result, int row, int col, int num_tiles){
//add shared memory
__shared__ float temp_shared_2[TILE_SIZE * TILE_SIZE];
//get row col idx
int tx = blockIdx.x * blockDim.x + threadIdx.x;
int ty = blockIdx.y * blockDim.y + threadIdx.y;
float temp = 0.0f;
unsigned int curr = 0, pos_x;
for(unsigned int count = 0; count < num_tiles; count++){
//find position
pos_x = count * TILE_SIZE + threadIdx.x;
//check bounds and load tile
if(pos_x < col && tx < row){
temp_shared_2[threadIdx.y * TILE_SIZE + threadIdx.x] = c_inp[ty*row + pos_x];
}
__syncthreads();
for(unsigned int tile = 0; tile < TILE_SIZE; tile++){
if(curr <= tx){
temp += temp_shared_2[threadIdx.x * TILE_SIZE + tile];
}
curr ++;
}
}
if(ty < row && tx < col){
result[ty*row + tx] = 30;
}
}
__global__ void unknown_algo_inp1(float *inp1, float *result, int row, int col, int num_tiles){
//add shared memory
__shared__ float temp_shared_1[TILE_SIZE][TILE_SIZE];
//get row col idx
int tx = blockIdx.x * blockDim.x + threadIdx.x;
int ty = blockIdx.y * blockDim.y + threadIdx.y;
float temp, local;
unsigned int curr = 0, pos_y;
//preload local
if(tx < row && ty < row){
temp = 0.0f;
local = inp1[row*tx + ty];
}
for(unsigned int count = 0; count < num_tiles; count++){
pos_y = count * TILE_SIZE + threadIdx.y;
//decrease load by letting one thread do it
if(pos_y < col && tx < row){
temp_shared_1[threadIdx.x][threadIdx.y] = inp1[pos_y];
}
__syncthreads();
for(unsigned int tile = 0; tile < TILE_SIZE; tile++){
if(curr <= ty){
temp += temp_shared_1[threadIdx.x][tile] * local;
}
curr++;
}
}
if(tx < row && ty < col){
result[tx*row + ty] = temp;
}
}
void cpu_v(float *inp1, float *inp2, float *result, int row, int col, float *temp){
for(int i = 0 ; i < row; i++){
temp[i] = 0.0f;
for(int j = 0; j < col; j++){
temp[i] += inp2[i*row + j];
result[i*row + j] = temp[i];
for(int k = 0; k < col; k++){
result[i*row + j] += inp1[j] * inp1[k];
}
}
}
}
int compare_res(float *d_res, float *h_res, int row, int col){
int check = 0;
for(int i = 0; i < row; i++){
for(int j = 0; j < col; j++){
if(d_res[i*row + j] != h_res[i*row +j]){
check += 1;
}
}
}
return check;
}
int main( int argc, char **argv ){
int row = DEFAULT_ROW;
int col = DEFAULT_COL;
if(argc == 3){
row = atoi(argv[1]);
col = atoi(argv[2]);
}
//create vars
int input1_bytes = col * sizeof(float);
int num_bytes = row * col * sizeof(float);
//event timers
cudaEvent_t start,stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
clock_t start_cpu, end_cpu;
//malloc device
float *d_input1 = (float *) malloc(input1_bytes);
float *d_input2 = (float *) malloc(num_bytes);
float *d_result = (float *) malloc(num_bytes);
//malloc host
float *h_input1 = (float *) malloc(input1_bytes);
float *h_input2 = (float *) malloc(num_bytes);
float *h_result = (float *) malloc(num_bytes);
//malloc test
float *temp = (float *) malloc(row* sizeof(float));
float *cpu_res = (float *) malloc(num_bytes);
//cuda malloc
cudaMalloc(&d_input1, input1_bytes);
cudaMalloc(&d_input2, num_bytes);
cudaMalloc(&d_result, num_bytes);
//put in data
for(int o = 0; o < row; o++){
for(int p = 0; p < col; p++){
h_input2[row * o + p] = 1.0f;
}
}
for(int i = 0; i < col; i++){
h_input1[i] = 1.0f;
}
//copy over memory
cudaMemcpy(d_input1, h_input1, input1_bytes, cudaMemcpyHostToDevice);
//cudaMemcpy(d_input2, h_input2, num_bytes, cudaMemcpyHostToDevice);
cudaMemcpyToSymbol(c_inp, h_input2, num_bytes);
//declare block and grid size for kernel
int block_size = TILE_SIZE;
//make grids x y
int grid_x = (int)ceil((float)row/block_size);
int grid_y = (int)ceil((float)col/block_size);
dim3 dim_grid (grid_x, grid_y);
dim3 dim_block (block_size, block_size);
//start timer
cudaEventRecord(start);
//run kernel on inp2
unknown_algo_inp2<<< dim_grid, dim_block >>> (d_input2, d_result, row, col, grid_x);
//inp1
//unknown_algo_inp1<<< dim_grid, dim_block >>> (d_input1, d_result, row, col, grid_x);
//end timer
cudaEventRecord(stop);
// Copy result back to host
cudaMemcpy(h_result, d_result, num_bytes, cudaMemcpyDeviceToHost);
//synchronize https://devblogs.nvidia.com/how-implement-performance-metrics-cuda-cc/
cudaEventSynchronize(stop);
float milliseconds = 0;
cudaEventElapsedTime(&milliseconds, start, stop);
//cpu version
start_cpu = clock();
cpu_v(h_input1, h_input2, cpu_res, row, col, temp);
end_cpu = clock();
int error_count = compare_res(h_result, cpu_res, row, col);
printf("error count: %d\nGPU time for execution: %lf ms\nCPU time for execution: %lf ms\n", error_count, milliseconds, ((float)((end_cpu-start_cpu)*1000))/CLOCKS_PER_SEC);
printf("gridx: %d gridy: %d\n", grid_x, grid_y);
//print error check
for(int i = 0; i < row; i++){
printf("%d. ", i);
for(int j = 0; j < col; j++){
printf("%d ", (int)h_result[i*row + j]);
}
printf("\n");
}
for(int i = 0; i < row; i++){
printf("%d. ", i);
for(int j = 0; j < col; j++){
printf("%d ", (int)cpu_res[i*row + j]);
}
printf("\n");
}
//free all vars
free(h_input1);
free(h_input2);
free(h_result);
free(temp);
cudaFree(d_input1);
cudaFree(d_input2);
cudaFree(d_result);
return 0;
} | //optimization homework #4 cs 677 Theodore Jagodits
#include <hip/hip_runtime.h>
#include <time.h>
#include <stdio.h>
#include <stdlib.h>
#include "string.h"
#include <iostream>
#define DEFAULT_ROW 128
#define DEFAULT_COL 128
#define TILE_SIZE 16
#define MAX_CONST 16000
//add constant memory
__constant__ float c_inp[MAX_CONST];
//tiling complete
__global__ void unknown_algo_inp2(float *inp2, float *result, int row, int col, int num_tiles){
//add shared memory
__shared__ float temp_shared_2[TILE_SIZE * TILE_SIZE];
//get row col idx
int tx = blockIdx.x * blockDim.x + threadIdx.x;
int ty = blockIdx.y * blockDim.y + threadIdx.y;
float temp = 0.0f;
unsigned int curr = 0, pos_x;
for(unsigned int count = 0; count < num_tiles; count++){
//find position
pos_x = count * TILE_SIZE + threadIdx.x;
//check bounds and load tile
if(pos_x < col && tx < row){
temp_shared_2[threadIdx.y * TILE_SIZE + threadIdx.x] = c_inp[ty*row + pos_x];
}
__syncthreads();
for(unsigned int tile = 0; tile < TILE_SIZE; tile++){
if(curr <= tx){
temp += temp_shared_2[threadIdx.x * TILE_SIZE + tile];
}
curr ++;
}
}
if(ty < row && tx < col){
result[ty*row + tx] = 30;
}
}
__global__ void unknown_algo_inp1(float *inp1, float *result, int row, int col, int num_tiles){
//add shared memory
__shared__ float temp_shared_1[TILE_SIZE][TILE_SIZE];
//get row col idx
int tx = blockIdx.x * blockDim.x + threadIdx.x;
int ty = blockIdx.y * blockDim.y + threadIdx.y;
float temp, local;
unsigned int curr = 0, pos_y;
//preload local
if(tx < row && ty < row){
temp = 0.0f;
local = inp1[row*tx + ty];
}
for(unsigned int count = 0; count < num_tiles; count++){
pos_y = count * TILE_SIZE + threadIdx.y;
//decrease load by letting one thread do it
if(pos_y < col && tx < row){
temp_shared_1[threadIdx.x][threadIdx.y] = inp1[pos_y];
}
__syncthreads();
for(unsigned int tile = 0; tile < TILE_SIZE; tile++){
if(curr <= ty){
temp += temp_shared_1[threadIdx.x][tile] * local;
}
curr++;
}
}
if(tx < row && ty < col){
result[tx*row + ty] = temp;
}
}
void cpu_v(float *inp1, float *inp2, float *result, int row, int col, float *temp){
for(int i = 0 ; i < row; i++){
temp[i] = 0.0f;
for(int j = 0; j < col; j++){
temp[i] += inp2[i*row + j];
result[i*row + j] = temp[i];
for(int k = 0; k < col; k++){
result[i*row + j] += inp1[j] * inp1[k];
}
}
}
}
int compare_res(float *d_res, float *h_res, int row, int col){
int check = 0;
for(int i = 0; i < row; i++){
for(int j = 0; j < col; j++){
if(d_res[i*row + j] != h_res[i*row +j]){
check += 1;
}
}
}
return check;
}
int main( int argc, char **argv ){
int row = DEFAULT_ROW;
int col = DEFAULT_COL;
if(argc == 3){
row = atoi(argv[1]);
col = atoi(argv[2]);
}
//create vars
int input1_bytes = col * sizeof(float);
int num_bytes = row * col * sizeof(float);
//event timers
hipEvent_t start,stop;
hipEventCreate(&start);
hipEventCreate(&stop);
clock_t start_cpu, end_cpu;
//malloc device
float *d_input1 = (float *) malloc(input1_bytes);
float *d_input2 = (float *) malloc(num_bytes);
float *d_result = (float *) malloc(num_bytes);
//malloc host
float *h_input1 = (float *) malloc(input1_bytes);
float *h_input2 = (float *) malloc(num_bytes);
float *h_result = (float *) malloc(num_bytes);
//malloc test
float *temp = (float *) malloc(row* sizeof(float));
float *cpu_res = (float *) malloc(num_bytes);
//cuda malloc
hipMalloc(&d_input1, input1_bytes);
hipMalloc(&d_input2, num_bytes);
hipMalloc(&d_result, num_bytes);
//put in data
for(int o = 0; o < row; o++){
for(int p = 0; p < col; p++){
h_input2[row * o + p] = 1.0f;
}
}
for(int i = 0; i < col; i++){
h_input1[i] = 1.0f;
}
//copy over memory
hipMemcpy(d_input1, h_input1, input1_bytes, hipMemcpyHostToDevice);
//cudaMemcpy(d_input2, h_input2, num_bytes, cudaMemcpyHostToDevice);
hipMemcpyToSymbol(HIP_SYMBOL(c_inp), h_input2, num_bytes);
//declare block and grid size for kernel
int block_size = TILE_SIZE;
//make grids x y
int grid_x = (int)ceil((float)row/block_size);
int grid_y = (int)ceil((float)col/block_size);
dim3 dim_grid (grid_x, grid_y);
dim3 dim_block (block_size, block_size);
//start timer
hipEventRecord(start);
//run kernel on inp2
unknown_algo_inp2<<< dim_grid, dim_block >>> (d_input2, d_result, row, col, grid_x);
//inp1
//unknown_algo_inp1<<< dim_grid, dim_block >>> (d_input1, d_result, row, col, grid_x);
//end timer
hipEventRecord(stop);
// Copy result back to host
hipMemcpy(h_result, d_result, num_bytes, hipMemcpyDeviceToHost);
//synchronize https://devblogs.nvidia.com/how-implement-performance-metrics-cuda-cc/
hipEventSynchronize(stop);
float milliseconds = 0;
hipEventElapsedTime(&milliseconds, start, stop);
//cpu version
start_cpu = clock();
cpu_v(h_input1, h_input2, cpu_res, row, col, temp);
end_cpu = clock();
int error_count = compare_res(h_result, cpu_res, row, col);
printf("error count: %d\nGPU time for execution: %lf ms\nCPU time for execution: %lf ms\n", error_count, milliseconds, ((float)((end_cpu-start_cpu)*1000))/CLOCKS_PER_SEC);
printf("gridx: %d gridy: %d\n", grid_x, grid_y);
//print error check
for(int i = 0; i < row; i++){
printf("%d. ", i);
for(int j = 0; j < col; j++){
printf("%d ", (int)h_result[i*row + j]);
}
printf("\n");
}
for(int i = 0; i < row; i++){
printf("%d. ", i);
for(int j = 0; j < col; j++){
printf("%d ", (int)cpu_res[i*row + j]);
}
printf("\n");
}
//free all vars
free(h_input1);
free(h_input2);
free(h_result);
free(temp);
hipFree(d_input1);
hipFree(d_input2);
hipFree(d_result);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | //optimization homework #4 cs 677 Theodore Jagodits
#include <hip/hip_runtime.h>
#include <time.h>
#include <stdio.h>
#include <stdlib.h>
#include "string.h"
#include <iostream>
#define DEFAULT_ROW 128
#define DEFAULT_COL 128
#define TILE_SIZE 16
#define MAX_CONST 16000
//add constant memory
__constant__ float c_inp[MAX_CONST];
//tiling complete
__global__ void unknown_algo_inp2(float *inp2, float *result, int row, int col, int num_tiles){
//add shared memory
__shared__ float temp_shared_2[TILE_SIZE * TILE_SIZE];
//get row col idx
int tx = blockIdx.x * blockDim.x + threadIdx.x;
int ty = blockIdx.y * blockDim.y + threadIdx.y;
float temp = 0.0f;
unsigned int curr = 0, pos_x;
for(unsigned int count = 0; count < num_tiles; count++){
//find position
pos_x = count * TILE_SIZE + threadIdx.x;
//check bounds and load tile
if(pos_x < col && tx < row){
temp_shared_2[threadIdx.y * TILE_SIZE + threadIdx.x] = c_inp[ty*row + pos_x];
}
__syncthreads();
for(unsigned int tile = 0; tile < TILE_SIZE; tile++){
if(curr <= tx){
temp += temp_shared_2[threadIdx.x * TILE_SIZE + tile];
}
curr ++;
}
}
if(ty < row && tx < col){
result[ty*row + tx] = 30;
}
}
__global__ void unknown_algo_inp1(float *inp1, float *result, int row, int col, int num_tiles){
//add shared memory
__shared__ float temp_shared_1[TILE_SIZE][TILE_SIZE];
//get row col idx
int tx = blockIdx.x * blockDim.x + threadIdx.x;
int ty = blockIdx.y * blockDim.y + threadIdx.y;
float temp, local;
unsigned int curr = 0, pos_y;
//preload local
if(tx < row && ty < row){
temp = 0.0f;
local = inp1[row*tx + ty];
}
for(unsigned int count = 0; count < num_tiles; count++){
pos_y = count * TILE_SIZE + threadIdx.y;
//decrease load by letting one thread do it
if(pos_y < col && tx < row){
temp_shared_1[threadIdx.x][threadIdx.y] = inp1[pos_y];
}
__syncthreads();
for(unsigned int tile = 0; tile < TILE_SIZE; tile++){
if(curr <= ty){
temp += temp_shared_1[threadIdx.x][tile] * local;
}
curr++;
}
}
if(tx < row && ty < col){
result[tx*row + ty] = temp;
}
}
void cpu_v(float *inp1, float *inp2, float *result, int row, int col, float *temp){
for(int i = 0 ; i < row; i++){
temp[i] = 0.0f;
for(int j = 0; j < col; j++){
temp[i] += inp2[i*row + j];
result[i*row + j] = temp[i];
for(int k = 0; k < col; k++){
result[i*row + j] += inp1[j] * inp1[k];
}
}
}
}
int compare_res(float *d_res, float *h_res, int row, int col){
int check = 0;
for(int i = 0; i < row; i++){
for(int j = 0; j < col; j++){
if(d_res[i*row + j] != h_res[i*row +j]){
check += 1;
}
}
}
return check;
}
int main( int argc, char **argv ){
int row = DEFAULT_ROW;
int col = DEFAULT_COL;
if(argc == 3){
row = atoi(argv[1]);
col = atoi(argv[2]);
}
//create vars
int input1_bytes = col * sizeof(float);
int num_bytes = row * col * sizeof(float);
//event timers
hipEvent_t start,stop;
hipEventCreate(&start);
hipEventCreate(&stop);
clock_t start_cpu, end_cpu;
//malloc device
float *d_input1 = (float *) malloc(input1_bytes);
float *d_input2 = (float *) malloc(num_bytes);
float *d_result = (float *) malloc(num_bytes);
//malloc host
float *h_input1 = (float *) malloc(input1_bytes);
float *h_input2 = (float *) malloc(num_bytes);
float *h_result = (float *) malloc(num_bytes);
//malloc test
float *temp = (float *) malloc(row* sizeof(float));
float *cpu_res = (float *) malloc(num_bytes);
//cuda malloc
hipMalloc(&d_input1, input1_bytes);
hipMalloc(&d_input2, num_bytes);
hipMalloc(&d_result, num_bytes);
//put in data
for(int o = 0; o < row; o++){
for(int p = 0; p < col; p++){
h_input2[row * o + p] = 1.0f;
}
}
for(int i = 0; i < col; i++){
h_input1[i] = 1.0f;
}
//copy over memory
hipMemcpy(d_input1, h_input1, input1_bytes, hipMemcpyHostToDevice);
//cudaMemcpy(d_input2, h_input2, num_bytes, cudaMemcpyHostToDevice);
hipMemcpyToSymbol(HIP_SYMBOL(c_inp), h_input2, num_bytes);
//declare block and grid size for kernel
int block_size = TILE_SIZE;
//make grids x y
int grid_x = (int)ceil((float)row/block_size);
int grid_y = (int)ceil((float)col/block_size);
dim3 dim_grid (grid_x, grid_y);
dim3 dim_block (block_size, block_size);
//start timer
hipEventRecord(start);
//run kernel on inp2
unknown_algo_inp2<<< dim_grid, dim_block >>> (d_input2, d_result, row, col, grid_x);
//inp1
//unknown_algo_inp1<<< dim_grid, dim_block >>> (d_input1, d_result, row, col, grid_x);
//end timer
hipEventRecord(stop);
// Copy result back to host
hipMemcpy(h_result, d_result, num_bytes, hipMemcpyDeviceToHost);
//synchronize https://devblogs.nvidia.com/how-implement-performance-metrics-cuda-cc/
hipEventSynchronize(stop);
float milliseconds = 0;
hipEventElapsedTime(&milliseconds, start, stop);
//cpu version
start_cpu = clock();
cpu_v(h_input1, h_input2, cpu_res, row, col, temp);
end_cpu = clock();
int error_count = compare_res(h_result, cpu_res, row, col);
printf("error count: %d\nGPU time for execution: %lf ms\nCPU time for execution: %lf ms\n", error_count, milliseconds, ((float)((end_cpu-start_cpu)*1000))/CLOCKS_PER_SEC);
printf("gridx: %d gridy: %d\n", grid_x, grid_y);
//print error check
for(int i = 0; i < row; i++){
printf("%d. ", i);
for(int j = 0; j < col; j++){
printf("%d ", (int)h_result[i*row + j]);
}
printf("\n");
}
for(int i = 0; i < row; i++){
printf("%d. ", i);
for(int j = 0; j < col; j++){
printf("%d ", (int)cpu_res[i*row + j]);
}
printf("\n");
}
//free all vars
free(h_input1);
free(h_input2);
free(h_result);
free(temp);
hipFree(d_input1);
hipFree(d_input2);
hipFree(d_result);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z17unknown_algo_inp2PfS_iii
.globl _Z17unknown_algo_inp2PfS_iii
.p2align 8
.type _Z17unknown_algo_inp2PfS_iii,@function
_Z17unknown_algo_inp2PfS_iii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s4, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_lshr_b32 s3, s2, 16
s_cmp_eq_u32 s4, 0
s_cbranch_scc1 .LBB0_2
.LBB0_1:
s_add_i32 s4, s4, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s4, 0
s_barrier
buffer_gl0_inv
s_cbranch_scc0 .LBB0_1
.LBB0_2:
s_load_b64 s[4:5], s[0:1], 0x10
v_bfe_u32 v2, v0, 10, 10
v_and_b32_e32 v3, 0x3ff, v0
s_and_b32 s3, 0xffff, s3
s_and_b32 s2, 0xffff, s2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[0:1], null, s15, s3, v[2:3]
v_mad_u64_u32 v[1:2], null, s14, s2, v[3:4]
s_waitcnt lgkmcnt(0)
v_cmp_gt_i32_e32 vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i32_e64 s2, s5, v1
s_and_b32 s2, s2, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_4
s_load_b64 s[0:1], s[0:1], 0x8
v_mad_u64_u32 v[2:3], null, v0, s4, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[0:1], 2, v[2:3]
v_mov_b32_e32 v2, 0x41f00000
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v2, off
.LBB0_4:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z17unknown_algo_inp2PfS_iii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z17unknown_algo_inp2PfS_iii, .Lfunc_end0-_Z17unknown_algo_inp2PfS_iii
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z17unknown_algo_inp1PfS_iii
.globl _Z17unknown_algo_inp1PfS_iii
.p2align 8
.type _Z17unknown_algo_inp1PfS_iii,@function
_Z17unknown_algo_inp1PfS_iii:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x10
s_load_b64 s[4:5], s[0:1], 0x0
v_and_b32_e32 v4, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s6, s2, 0xffff
s_lshr_b32 s2, s2, 16
v_mad_u64_u32 v[0:1], null, s14, s6, v[4:5]
v_mad_u64_u32 v[1:2], null, s15, s2, v[3:4]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_gt_i32_e32 vcc_lo, s3, v0
v_cmp_gt_i32_e64 s2, s3, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, vcc_lo, s2
s_and_saveexec_b32 s6, s2
s_cbranch_execz .LBB1_2
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[5:6], null, v0, s3, v[1:2]
v_ashrrev_i32_e32 v6, 31, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[5:6], 2, v[5:6]
v_add_co_u32 v5, s2, s4, v5
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v6, s2, s5, v6, s2
global_load_b32 v6, v[5:6], off
.LBB1_2:
s_or_b32 exec_lo, exec_lo, s6
s_load_b64 s[6:7], s[0:1], 0x14
s_mov_b32 s8, 0
s_waitcnt lgkmcnt(0)
s_cmp_eq_u32 s7, 0
s_cbranch_scc1 .LBB1_11
v_dual_mov_b32 v2, 0 :: v_dual_lshlrev_b32 v7, 6, v4
v_mov_b32_e32 v5, 0
s_mov_b32 s9, 0
s_delay_alu instid0(VALU_DEP_2)
v_lshl_add_u32 v8, v3, 2, v7
s_set_inst_prefetch_distance 0x1
s_branch .LBB1_5
.p2align 6
.LBB1_4:
s_add_i32 s8, s8, 1
s_add_i32 s9, s9, 16
s_cmp_eq_u32 s8, s7
s_cbranch_scc1 .LBB1_12
.LBB1_5:
v_lshl_add_u32 v4, s8, 4, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_u32_e64 s2, s6, v4
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s10, s2
s_cbranch_execz .LBB1_7
v_lshlrev_b64 v[9:10], 2, v[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v9, s2, s4, v9
v_add_co_ci_u32_e64 v10, s2, s5, v10, s2
global_load_b32 v4, v[9:10], off
s_waitcnt vmcnt(0)
ds_store_b32 v8, v4
.LBB1_7:
s_or_b32 exec_lo, exec_lo, s10
v_mov_b32_e32 v4, v7
s_mov_b32 s10, 0
s_waitcnt vmcnt(0) lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_branch .LBB1_9
.LBB1_8:
s_or_b32 exec_lo, exec_lo, s11
v_add_nc_u32_e32 v4, 4, v4
s_add_i32 s10, s10, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s10, 16
s_cbranch_scc1 .LBB1_4
.LBB1_9:
s_add_i32 s2, s9, s10
s_mov_b32 s11, exec_lo
v_cmpx_le_u32_e64 s2, v1
s_cbranch_execz .LBB1_8
ds_load_b32 v9, v4
s_waitcnt lgkmcnt(0)
v_fmac_f32_e32 v2, v6, v9
s_branch .LBB1_8
.LBB1_11:
v_mov_b32_e32 v2, 0
.LBB1_12:
s_set_inst_prefetch_distance 0x2
v_cmp_gt_i32_e64 s2, s6, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, vcc_lo, s2
s_and_saveexec_b32 s4, s2
s_cbranch_execz .LBB1_14
s_load_b64 s[0:1], s[0:1], 0x8
v_mad_u64_u32 v[3:4], null, v0, s3, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v4, 31, v3
v_lshlrev_b64 v[0:1], 2, v[3:4]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v2, off
.LBB1_14:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z17unknown_algo_inp1PfS_iii
.amdhsa_group_segment_fixed_size 1024
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 11
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z17unknown_algo_inp1PfS_iii, .Lfunc_end1-_Z17unknown_algo_inp1PfS_iii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.protected c_inp
.type c_inp,@object
.section .bss,"aw",@nobits
.globl c_inp
.p2align 4, 0x0
c_inp:
.zero 64000
.size c_inp, 64000
.type __hip_cuid_,@object
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym c_inp
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z17unknown_algo_inp2PfS_iii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z17unknown_algo_inp2PfS_iii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 1024
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z17unknown_algo_inp1PfS_iii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z17unknown_algo_inp1PfS_iii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 11
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | //optimization homework #4 cs 677 Theodore Jagodits
#include <hip/hip_runtime.h>
#include <time.h>
#include <stdio.h>
#include <stdlib.h>
#include "string.h"
#include <iostream>
#define DEFAULT_ROW 128
#define DEFAULT_COL 128
#define TILE_SIZE 16
#define MAX_CONST 16000
//add constant memory
__constant__ float c_inp[MAX_CONST];
//tiling complete
__global__ void unknown_algo_inp2(float *inp2, float *result, int row, int col, int num_tiles){
//add shared memory
__shared__ float temp_shared_2[TILE_SIZE * TILE_SIZE];
//get row col idx
int tx = blockIdx.x * blockDim.x + threadIdx.x;
int ty = blockIdx.y * blockDim.y + threadIdx.y;
float temp = 0.0f;
unsigned int curr = 0, pos_x;
for(unsigned int count = 0; count < num_tiles; count++){
//find position
pos_x = count * TILE_SIZE + threadIdx.x;
//check bounds and load tile
if(pos_x < col && tx < row){
temp_shared_2[threadIdx.y * TILE_SIZE + threadIdx.x] = c_inp[ty*row + pos_x];
}
__syncthreads();
for(unsigned int tile = 0; tile < TILE_SIZE; tile++){
if(curr <= tx){
temp += temp_shared_2[threadIdx.x * TILE_SIZE + tile];
}
curr ++;
}
}
if(ty < row && tx < col){
result[ty*row + tx] = 30;
}
}
__global__ void unknown_algo_inp1(float *inp1, float *result, int row, int col, int num_tiles){
//add shared memory
__shared__ float temp_shared_1[TILE_SIZE][TILE_SIZE];
//get row col idx
int tx = blockIdx.x * blockDim.x + threadIdx.x;
int ty = blockIdx.y * blockDim.y + threadIdx.y;
float temp, local;
unsigned int curr = 0, pos_y;
//preload local
if(tx < row && ty < row){
temp = 0.0f;
local = inp1[row*tx + ty];
}
for(unsigned int count = 0; count < num_tiles; count++){
pos_y = count * TILE_SIZE + threadIdx.y;
//decrease load by letting one thread do it
if(pos_y < col && tx < row){
temp_shared_1[threadIdx.x][threadIdx.y] = inp1[pos_y];
}
__syncthreads();
for(unsigned int tile = 0; tile < TILE_SIZE; tile++){
if(curr <= ty){
temp += temp_shared_1[threadIdx.x][tile] * local;
}
curr++;
}
}
if(tx < row && ty < col){
result[tx*row + ty] = temp;
}
}
void cpu_v(float *inp1, float *inp2, float *result, int row, int col, float *temp){
for(int i = 0 ; i < row; i++){
temp[i] = 0.0f;
for(int j = 0; j < col; j++){
temp[i] += inp2[i*row + j];
result[i*row + j] = temp[i];
for(int k = 0; k < col; k++){
result[i*row + j] += inp1[j] * inp1[k];
}
}
}
}
int compare_res(float *d_res, float *h_res, int row, int col){
int check = 0;
for(int i = 0; i < row; i++){
for(int j = 0; j < col; j++){
if(d_res[i*row + j] != h_res[i*row +j]){
check += 1;
}
}
}
return check;
}
int main( int argc, char **argv ){
int row = DEFAULT_ROW;
int col = DEFAULT_COL;
if(argc == 3){
row = atoi(argv[1]);
col = atoi(argv[2]);
}
//create vars
int input1_bytes = col * sizeof(float);
int num_bytes = row * col * sizeof(float);
//event timers
hipEvent_t start,stop;
hipEventCreate(&start);
hipEventCreate(&stop);
clock_t start_cpu, end_cpu;
//malloc device
float *d_input1 = (float *) malloc(input1_bytes);
float *d_input2 = (float *) malloc(num_bytes);
float *d_result = (float *) malloc(num_bytes);
//malloc host
float *h_input1 = (float *) malloc(input1_bytes);
float *h_input2 = (float *) malloc(num_bytes);
float *h_result = (float *) malloc(num_bytes);
//malloc test
float *temp = (float *) malloc(row* sizeof(float));
float *cpu_res = (float *) malloc(num_bytes);
//cuda malloc
hipMalloc(&d_input1, input1_bytes);
hipMalloc(&d_input2, num_bytes);
hipMalloc(&d_result, num_bytes);
//put in data
for(int o = 0; o < row; o++){
for(int p = 0; p < col; p++){
h_input2[row * o + p] = 1.0f;
}
}
for(int i = 0; i < col; i++){
h_input1[i] = 1.0f;
}
//copy over memory
hipMemcpy(d_input1, h_input1, input1_bytes, hipMemcpyHostToDevice);
//cudaMemcpy(d_input2, h_input2, num_bytes, cudaMemcpyHostToDevice);
hipMemcpyToSymbol(HIP_SYMBOL(c_inp), h_input2, num_bytes);
//declare block and grid size for kernel
int block_size = TILE_SIZE;
//make grids x y
int grid_x = (int)ceil((float)row/block_size);
int grid_y = (int)ceil((float)col/block_size);
dim3 dim_grid (grid_x, grid_y);
dim3 dim_block (block_size, block_size);
//start timer
hipEventRecord(start);
//run kernel on inp2
unknown_algo_inp2<<< dim_grid, dim_block >>> (d_input2, d_result, row, col, grid_x);
//inp1
//unknown_algo_inp1<<< dim_grid, dim_block >>> (d_input1, d_result, row, col, grid_x);
//end timer
hipEventRecord(stop);
// Copy result back to host
hipMemcpy(h_result, d_result, num_bytes, hipMemcpyDeviceToHost);
//synchronize https://devblogs.nvidia.com/how-implement-performance-metrics-cuda-cc/
hipEventSynchronize(stop);
float milliseconds = 0;
hipEventElapsedTime(&milliseconds, start, stop);
//cpu version
start_cpu = clock();
cpu_v(h_input1, h_input2, cpu_res, row, col, temp);
end_cpu = clock();
int error_count = compare_res(h_result, cpu_res, row, col);
printf("error count: %d\nGPU time for execution: %lf ms\nCPU time for execution: %lf ms\n", error_count, milliseconds, ((float)((end_cpu-start_cpu)*1000))/CLOCKS_PER_SEC);
printf("gridx: %d gridy: %d\n", grid_x, grid_y);
//print error check
for(int i = 0; i < row; i++){
printf("%d. ", i);
for(int j = 0; j < col; j++){
printf("%d ", (int)h_result[i*row + j]);
}
printf("\n");
}
for(int i = 0; i < row; i++){
printf("%d. ", i);
for(int j = 0; j < col; j++){
printf("%d ", (int)cpu_res[i*row + j]);
}
printf("\n");
}
//free all vars
free(h_input1);
free(h_input2);
free(h_result);
free(temp);
hipFree(d_input1);
hipFree(d_input2);
hipFree(d_result);
return 0;
} | .text
.file "v5_gpu.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z32__device_stub__unknown_algo_inp2PfS_iii # -- Begin function _Z32__device_stub__unknown_algo_inp2PfS_iii
.p2align 4, 0x90
.type _Z32__device_stub__unknown_algo_inp2PfS_iii,@function
_Z32__device_stub__unknown_algo_inp2PfS_iii: # @_Z32__device_stub__unknown_algo_inp2PfS_iii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z17unknown_algo_inp2PfS_iii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z32__device_stub__unknown_algo_inp2PfS_iii, .Lfunc_end0-_Z32__device_stub__unknown_algo_inp2PfS_iii
.cfi_endproc
# -- End function
.globl _Z32__device_stub__unknown_algo_inp1PfS_iii # -- Begin function _Z32__device_stub__unknown_algo_inp1PfS_iii
.p2align 4, 0x90
.type _Z32__device_stub__unknown_algo_inp1PfS_iii,@function
_Z32__device_stub__unknown_algo_inp1PfS_iii: # @_Z32__device_stub__unknown_algo_inp1PfS_iii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z17unknown_algo_inp1PfS_iii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end1:
.size _Z32__device_stub__unknown_algo_inp1PfS_iii, .Lfunc_end1-_Z32__device_stub__unknown_algo_inp1PfS_iii
.cfi_endproc
# -- End function
.globl _Z5cpu_vPfS_S_iiS_ # -- Begin function _Z5cpu_vPfS_S_iiS_
.p2align 4, 0x90
.type _Z5cpu_vPfS_S_iiS_,@function
_Z5cpu_vPfS_S_iiS_: # @_Z5cpu_vPfS_S_iiS_
.cfi_startproc
# %bb.0:
testl %ecx, %ecx
jle .LBB2_9
# %bb.1: # %.lr.ph41
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl %ecx, %eax
movl %r8d, %r10d
xorl %r11d, %r11d
jmp .LBB2_2
.p2align 4, 0x90
.LBB2_7: # %._crit_edge38
# in Loop: Header=BB2_2 Depth=1
incq %r11
cmpq %rax, %r11
je .LBB2_8
.LBB2_2: # =>This Loop Header: Depth=1
# Child Loop BB2_4 Depth 2
# Child Loop BB2_5 Depth 3
movl $0, (%r9,%r11,4)
testl %r8d, %r8d
jle .LBB2_7
# %bb.3: # %.lr.ph37
# in Loop: Header=BB2_2 Depth=1
movl %r11d, %ebx
imull %ecx, %ebx
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB2_4: # %.lr.ph
# Parent Loop BB2_2 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB2_5 Depth 3
leaq (%r14,%rbx), %r15
movss (%rsi,%r15,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
addss (%r9,%r11,4), %xmm0
movss %xmm0, (%r9,%r11,4)
movss %xmm0, (%rdx,%r15,4)
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB2_5: # Parent Loop BB2_2 Depth=1
# Parent Loop BB2_4 Depth=2
# => This Inner Loop Header: Depth=3
movss (%rdi,%r14,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
mulss (%rdi,%r12,4), %xmm0
addss (%rdx,%r15,4), %xmm0
movss %xmm0, (%rdx,%r15,4)
incq %r12
cmpq %r12, %r10
jne .LBB2_5
# %bb.6: # %._crit_edge
# in Loop: Header=BB2_4 Depth=2
incq %r14
cmpq %r10, %r14
jne .LBB2_4
jmp .LBB2_7
.LBB2_8:
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r12
.cfi_restore %r14
.cfi_restore %r15
.LBB2_9: # %._crit_edge42
retq
.Lfunc_end2:
.size _Z5cpu_vPfS_S_iiS_, .Lfunc_end2-_Z5cpu_vPfS_S_iiS_
.cfi_endproc
# -- End function
.globl _Z11compare_resPfS_ii # -- Begin function _Z11compare_resPfS_ii
.p2align 4, 0x90
.type _Z11compare_resPfS_ii,@function
_Z11compare_resPfS_ii: # @_Z11compare_resPfS_ii
.cfi_startproc
# %bb.0:
testl %edx, %edx
jle .LBB3_1
# %bb.3: # %.preheader.lr.ph
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset %rbx, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %edx, %r8d
movl %ecx, %r9d
xorl %r10d, %r10d
xorl %r11d, %r11d
xorl %eax, %eax
jmp .LBB3_4
.p2align 4, 0x90
.LBB3_7: # %._crit_edge
# in Loop: Header=BB3_4 Depth=1
incq %r11
addl %edx, %r10d
cmpq %r8, %r11
je .LBB3_8
.LBB3_4: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB3_6 Depth 2
testl %ecx, %ecx
jle .LBB3_7
# %bb.5: # %.lr.ph
# in Loop: Header=BB3_4 Depth=1
movl %r10d, %r14d
leaq (%rsi,%r14,4), %rbx
leaq (%rdi,%r14,4), %r14
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB3_6: # Parent Loop BB3_4 Depth=1
# => This Inner Loop Header: Depth=2
movss (%rbx,%r15,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cmpneqss (%r14,%r15,4), %xmm0
movd %xmm0, %ebp
subl %ebp, %eax
incq %r15
cmpq %r15, %r9
jne .LBB3_6
jmp .LBB3_7
.LBB3_8:
popq %rbx
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r14
.cfi_restore %r15
.cfi_restore %rbp
retq
.LBB3_1:
xorl %eax, %eax
retq
.Lfunc_end3:
.size _Z11compare_resPfS_ii, .Lfunc_end3-_Z11compare_resPfS_ii
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI4_0:
.long 0x3d800000 # float 0.0625
.LCPI4_1:
.long 0x49742400 # float 1.0E+6
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $232, %rsp
.cfi_def_cfa_offset 288
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $128, %r13d
movl $128, %r12d
cmpl $3, %edi
jne .LBB4_2
# %bb.1:
movq 8(%rsi), %rdi
movq %rsi, %rbx
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r12
movq 16(%rbx), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r13
.LBB4_2:
leal (,%r13,4), %ebx
movl %ebx, %r14d
imull %r12d, %r14d
leaq 112(%rsp), %rdi
callq hipEventCreate
leaq 80(%rsp), %rdi
callq hipEventCreate
movslq %ebx, %rbp
movq %rbp, %rdi
callq malloc
movq %rax, 72(%rsp)
movslq %r14d, %r14
movq %r14, %rdi
callq malloc
movq %rax, 64(%rsp)
movq %r14, %rdi
callq malloc
movq %rax, 40(%rsp)
movq %rbp, %rdi
callq malloc
movq %rax, %r15
movq %r14, %rdi
callq malloc
movq %rax, 56(%rsp) # 8-byte Spill
movq %r14, %rdi
callq malloc
movq %rax, 24(%rsp) # 8-byte Spill
movslq %r12d, %rbx
leaq (,%rbx,4), %rdi
callq malloc
movq %rax, 104(%rsp) # 8-byte Spill
movq %r14, %rdi
callq malloc
movq %rax, 48(%rsp) # 8-byte Spill
leaq 72(%rsp), %rdi
movq %rbp, %rsi
callq hipMalloc
leaq 64(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
leaq 40(%rsp), %rdi
movq %r14, 8(%rsp) # 8-byte Spill
movq %r14, %rsi
callq hipMalloc
movl %r12d, %edi
movl %r13d, %r14d
testl %ebx, %ebx
jle .LBB4_8
# %bb.3: # %.preheader114.lr.ph
xorl %eax, %eax
xorl %ecx, %ecx
jmp .LBB4_4
.p2align 4, 0x90
.LBB4_7: # %._crit_edge
# in Loop: Header=BB4_4 Depth=1
incq %rcx
addl %r12d, %eax
cmpq %rdi, %rcx
je .LBB4_8
.LBB4_4: # %.preheader114
# =>This Loop Header: Depth=1
# Child Loop BB4_6 Depth 2
testl %r13d, %r13d
jle .LBB4_7
# %bb.5: # %.lr.ph
# in Loop: Header=BB4_4 Depth=1
movl %eax, %edx
movq 56(%rsp), %rsi # 8-byte Reload
leaq (%rsi,%rdx,4), %rdx
xorl %esi, %esi
.p2align 4, 0x90
.LBB4_6: # Parent Loop BB4_4 Depth=1
# => This Inner Loop Header: Depth=2
movl $1065353216, (%rdx,%rsi,4) # imm = 0x3F800000
incq %rsi
cmpq %rsi, %r14
jne .LBB4_6
jmp .LBB4_7
.LBB4_8: # %.preheader113
movq %rdi, 32(%rsp) # 8-byte Spill
testl %r13d, %r13d
jle .LBB4_11
# %bb.9: # %.lr.ph118.preheader
xorl %eax, %eax
.p2align 4, 0x90
.LBB4_10: # %.lr.ph118
# =>This Inner Loop Header: Depth=1
movl $1065353216, (%r15,%rax,4) # imm = 0x3F800000
incq %rax
cmpq %rax, %r14
jne .LBB4_10
.LBB4_11: # %._crit_edge119
movq 72(%rsp), %rdi
movq %r15, %rsi
movq %rbp, %rdx
movl $1, %ecx
callq hipMemcpy
movl $c_inp, %edi
movq 56(%rsp), %rbx # 8-byte Reload
movq %rbx, %rsi
movq 8(%rsp), %rdx # 8-byte Reload
xorl %ecx, %ecx
movl $1, %r8d
callq hipMemcpyToSymbol
cvtsi2ss %r12d, %xmm0
mulss .LCPI4_0(%rip), %xmm0
callq ceilf@PLT
cvttss2si %xmm0, %eax
movq %rax, 16(%rsp) # 8-byte Spill
xorps %xmm0, %xmm0
cvtsi2ss %r13d, %xmm0
mulss .LCPI4_0(%rip), %xmm0
callq ceilf@PLT
cvttss2si %xmm0, %ebp
movq %rbp, 120(%rsp) # 8-byte Spill
shlq $32, %rbp
addq 16(%rsp), %rbp # 8-byte Folded Reload
movq 112(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movabsq $68719476752, %rdx # imm = 0x1000000010
movq %rbp, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_13
# %bb.12:
movq 64(%rsp), %rax
movq 40(%rsp), %rcx
movq %rax, 184(%rsp)
movq %rcx, 176(%rsp)
movl %r12d, 100(%rsp)
movl %r13d, 96(%rsp)
movq 16(%rsp), %rax # 8-byte Reload
movl %eax, 92(%rsp)
leaq 184(%rsp), %rax
movq %rax, 192(%rsp)
leaq 176(%rsp), %rax
movq %rax, 200(%rsp)
leaq 100(%rsp), %rax
movq %rax, 208(%rsp)
leaq 96(%rsp), %rax
movq %rax, 216(%rsp)
leaq 92(%rsp), %rax
movq %rax, 224(%rsp)
leaq 160(%rsp), %rdi
leaq 144(%rsp), %rsi
leaq 136(%rsp), %rdx
leaq 128(%rsp), %rcx
callq __hipPopCallConfiguration
movq 160(%rsp), %rsi
movl 168(%rsp), %edx
movq 144(%rsp), %rcx
movl 152(%rsp), %r8d
leaq 192(%rsp), %r9
movl $_Z17unknown_algo_inp2PfS_iii, %edi
pushq 128(%rsp)
.cfi_adjust_cfa_offset 8
pushq 144(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_13:
movq 80(%rsp), %rdi
xorl %ebp, %ebp
xorl %esi, %esi
callq hipEventRecord
movq 40(%rsp), %rsi
movq 24(%rsp), %rdi # 8-byte Reload
movq 8(%rsp), %rdx # 8-byte Reload
movl $2, %ecx
callq hipMemcpy
movq 80(%rsp), %rdi
callq hipEventSynchronize
movl $0, 192(%rsp)
movq 112(%rsp), %rsi
movq 80(%rsp), %rdx
leaq 192(%rsp), %rdi
callq hipEventElapsedTime
callq clock
movq %rax, 8(%rsp) # 8-byte Spill
testl %r12d, %r12d
movq 104(%rsp), %r8 # 8-byte Reload
movq 48(%rsp), %r9 # 8-byte Reload
movq 32(%rsp), %r10 # 8-byte Reload
jle .LBB4_22
# %bb.14: # %.lr.ph41.i
xorl %eax, %eax
jmp .LBB4_15
.p2align 4, 0x90
.LBB4_21: # %._crit_edge38.i
# in Loop: Header=BB4_15 Depth=1
incq %rax
cmpq %r10, %rax
je .LBB4_22
.LBB4_15: # =>This Loop Header: Depth=1
# Child Loop BB4_17 Depth 2
# Child Loop BB4_18 Depth 3
movl $0, (%r8,%rax,4)
testl %r13d, %r13d
jle .LBB4_21
# %bb.16: # %.lr.ph37.i
# in Loop: Header=BB4_15 Depth=1
movl %r12d, %ecx
imull %eax, %ecx
movss (%r8,%rax,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
xorl %edx, %edx
.p2align 4, 0x90
.LBB4_17: # %.lr.ph.i
# Parent Loop BB4_15 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB4_18 Depth 3
leaq (%rdx,%rcx), %rsi
addss (%rbx,%rsi,4), %xmm0
movss %xmm0, (%r9,%rsi,4)
movss (%r15,%rdx,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
movaps %xmm0, %xmm2
xorl %edi, %edi
.p2align 4, 0x90
.LBB4_18: # Parent Loop BB4_15 Depth=1
# Parent Loop BB4_17 Depth=2
# => This Inner Loop Header: Depth=3
movss (%r15,%rdi,4), %xmm3 # xmm3 = mem[0],zero,zero,zero
mulss %xmm1, %xmm3
addss %xmm3, %xmm2
incq %rdi
cmpq %rdi, %r14
jne .LBB4_18
# %bb.19: # %._crit_edge.i
# in Loop: Header=BB4_17 Depth=2
movss %xmm2, (%r9,%rsi,4)
incq %rdx
cmpq %r14, %rdx
jne .LBB4_17
# %bb.20: # %._crit_edge38.i.loopexit
# in Loop: Header=BB4_15 Depth=1
movss %xmm0, (%r8,%rax,4)
jmp .LBB4_21
.LBB4_22: # %_Z5cpu_vPfS_S_iiS_.exit
callq clock
movq 32(%rsp), %r11 # 8-byte Reload
movq 48(%rsp), %r10 # 8-byte Reload
testl %r12d, %r12d
jle .LBB4_28
# %bb.23: # %.preheader.lr.ph.i
xorl %ecx, %ecx
xorl %edx, %edx
xorl %ebp, %ebp
jmp .LBB4_24
.p2align 4, 0x90
.LBB4_27: # %._crit_edge.i105
# in Loop: Header=BB4_24 Depth=1
incq %rdx
addl %r12d, %ecx
cmpq %r11, %rdx
je .LBB4_28
.LBB4_24: # %.preheader.i
# =>This Loop Header: Depth=1
# Child Loop BB4_26 Depth 2
testl %r13d, %r13d
jle .LBB4_27
# %bb.25: # %.lr.ph.i106
# in Loop: Header=BB4_24 Depth=1
movl %ecx, %edi
leaq (%r10,%rdi,4), %rsi
movq 24(%rsp), %r8 # 8-byte Reload
leaq (%r8,%rdi,4), %rdi
xorl %r8d, %r8d
.p2align 4, 0x90
.LBB4_26: # Parent Loop BB4_24 Depth=1
# => This Inner Loop Header: Depth=2
movss (%rsi,%r8,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cmpneqss (%rdi,%r8,4), %xmm0
movd %xmm0, %r9d
subl %r9d, %ebp
incq %r8
cmpq %r8, %r14
jne .LBB4_26
jmp .LBB4_27
.LBB4_28: # %_Z11compare_resPfS_ii.exit
movss 192(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
subq 8(%rsp), %rax # 8-byte Folded Reload
imulq $1000, %rax, %rax # imm = 0x3E8
xorps %xmm1, %xmm1
cvtsi2ss %rax, %xmm1
cvtss2sd %xmm0, %xmm0
divss .LCPI4_1(%rip), %xmm1
cvtss2sd %xmm1, %xmm1
movl $.L.str, %edi
movl %ebp, %esi
movb $2, %al
callq printf
movl $.L.str.1, %edi
movq 16(%rsp), %rsi # 8-byte Reload
# kill: def $esi killed $esi killed $rsi
movq 120(%rsp), %rdx # 8-byte Reload
# kill: def $edx killed $edx killed $rdx
xorl %eax, %eax
callq printf
testl %r12d, %r12d
movq %r12, 16(%rsp) # 8-byte Spill
movq %r13, 8(%rsp) # 8-byte Spill
jle .LBB4_34
# %bb.29: # %.lr.ph127
xorl %ebx, %ebx
xorl %ebp, %ebp
jmp .LBB4_30
.p2align 4, 0x90
.LBB4_33: # %._crit_edge125
# in Loop: Header=BB4_30 Depth=1
movl $10, %edi
callq putchar@PLT
incq %rbp
movq 16(%rsp), %r12 # 8-byte Reload
addl %r12d, %ebx
cmpq 32(%rsp), %rbp # 8-byte Folded Reload
movq 8(%rsp), %r13 # 8-byte Reload
je .LBB4_34
.LBB4_30: # =>This Loop Header: Depth=1
# Child Loop BB4_32 Depth 2
movl $.L.str.2, %edi
movl %ebp, %esi
xorl %eax, %eax
callq printf
testl %r13d, %r13d
jle .LBB4_33
# %bb.31: # %.lr.ph124
# in Loop: Header=BB4_30 Depth=1
movl %ebx, %eax
movq 24(%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax,4), %r12
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB4_32: # Parent Loop BB4_30 Depth=1
# => This Inner Loop Header: Depth=2
cvttss2si (%r12,%r13,4), %esi
movl $.L.str.3, %edi
xorl %eax, %eax
callq printf
incq %r13
cmpq %r13, %r14
jne .LBB4_32
jmp .LBB4_33
.LBB4_34: # %.preheader
testl %r12d, %r12d
jle .LBB4_40
# %bb.35: # %.lr.ph133
xorl %ebx, %ebx
xorl %ebp, %ebp
jmp .LBB4_36
.p2align 4, 0x90
.LBB4_39: # %._crit_edge131
# in Loop: Header=BB4_36 Depth=1
movl $10, %edi
callq putchar@PLT
incq %rbp
addl 16(%rsp), %ebx # 4-byte Folded Reload
cmpq 32(%rsp), %rbp # 8-byte Folded Reload
movq 8(%rsp), %r13 # 8-byte Reload
je .LBB4_40
.LBB4_36: # =>This Loop Header: Depth=1
# Child Loop BB4_38 Depth 2
movl $.L.str.2, %edi
movl %ebp, %esi
xorl %eax, %eax
callq printf
testl %r13d, %r13d
jle .LBB4_39
# %bb.37: # %.lr.ph130
# in Loop: Header=BB4_36 Depth=1
movl %ebx, %eax
movq 48(%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax,4), %r12
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB4_38: # Parent Loop BB4_36 Depth=1
# => This Inner Loop Header: Depth=2
cvttss2si (%r12,%r13,4), %esi
movl $.L.str.3, %edi
xorl %eax, %eax
callq printf
incq %r13
cmpq %r13, %r14
jne .LBB4_38
jmp .LBB4_39
.LBB4_40: # %._crit_edge134
movq %r15, %rdi
callq free
movq 56(%rsp), %rdi # 8-byte Reload
callq free
movq 24(%rsp), %rdi # 8-byte Reload
callq free
movq 104(%rsp), %rdi # 8-byte Reload
callq free
movq 72(%rsp), %rdi
callq hipFree
movq 64(%rsp), %rdi
callq hipFree
movq 40(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $232, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end4:
.size main, .Lfunc_end4-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z17unknown_algo_inp2PfS_iii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z17unknown_algo_inp1PfS_iii, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $0, 8(%rsp)
movl $1, (%rsp)
movl $c_inp, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movl $64000, %r9d # imm = 0xFA00
movq %rbx, %rdi
xorl %r8d, %r8d
callq __hipRegisterVar
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type c_inp,@object # @c_inp
.local c_inp
.comm c_inp,64000,16
.type _Z17unknown_algo_inp2PfS_iii,@object # @_Z17unknown_algo_inp2PfS_iii
.section .rodata,"a",@progbits
.globl _Z17unknown_algo_inp2PfS_iii
.p2align 3, 0x0
_Z17unknown_algo_inp2PfS_iii:
.quad _Z32__device_stub__unknown_algo_inp2PfS_iii
.size _Z17unknown_algo_inp2PfS_iii, 8
.type _Z17unknown_algo_inp1PfS_iii,@object # @_Z17unknown_algo_inp1PfS_iii
.globl _Z17unknown_algo_inp1PfS_iii
.p2align 3, 0x0
_Z17unknown_algo_inp1PfS_iii:
.quad _Z32__device_stub__unknown_algo_inp1PfS_iii
.size _Z17unknown_algo_inp1PfS_iii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "error count: %d\nGPU time for execution: %lf ms\nCPU time for execution: %lf ms\n"
.size .L.str, 79
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "gridx: %d gridy: %d\n"
.size .L.str.1, 21
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "%d. "
.size .L.str.2, 5
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "%d "
.size .L.str.3, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z17unknown_algo_inp2PfS_iii"
.size .L__unnamed_1, 29
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z17unknown_algo_inp1PfS_iii"
.size .L__unnamed_2, 29
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "c_inp"
.size .L__unnamed_3, 6
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z32__device_stub__unknown_algo_inp2PfS_iii
.addrsig_sym _Z32__device_stub__unknown_algo_inp1PfS_iii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym c_inp
.addrsig_sym _Z17unknown_algo_inp2PfS_iii
.addrsig_sym _Z17unknown_algo_inp1PfS_iii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z17unknown_algo_inp1PfS_iii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR8, c[0x0][0x118] ; /* 0x0000460000087ab9 */
/* 0x000fe20000000a00 */
/*0030*/ BSSY B0, 0x140 ; /* 0x0000010000007945 */
/* 0x000fe20003800000 */
/*0040*/ HFMA2.MMA R0, -RZ, RZ, 0, 0 ; /* 0x00000000ff007435 */
/* 0x000fe200000001ff */
/*0050*/ S2R R8, SR_TID.X ; /* 0x0000000000087919 */
/* 0x000e220000002100 */
/*0060*/ ISETP.NE.AND P3, PT, RZ, c[0x0][0x178], PT ; /* 0x00005e00ff007a0c */
/* 0x000fc60003f65270 */
/*0070*/ S2R R5, SR_CTAID.Y ; /* 0x0000000000057919 */
/* 0x000e680000002600 */
/*0080*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e620000002200 */
/*0090*/ IMAD R3, R3, c[0x0][0x0], R8 ; /* 0x0000000003037a24 */
/* 0x001fca00078e0208 */
/*00a0*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x170], PT ; /* 0x00005c0003007a0c */
/* 0x000fe20003f06270 */
/*00b0*/ IMAD R4, R5, c[0x0][0x4], R2 ; /* 0x0000010005047a24 */
/* 0x002fca00078e0202 */
/*00c0*/ ISETP.GE.OR P2, PT, R4.reuse, c[0x0][0x170], P0 ; /* 0x00005c0004007a0c */
/* 0x040fe40000746670 */
/*00d0*/ ISETP.GE.OR P1, PT, R4, c[0x0][0x174], P0 ; /* 0x00005d0004007a0c */
/* 0x000fd60000726670 */
/*00e0*/ @P2 BRA 0x130 ; /* 0x0000004000002947 */
/* 0x000fea0003800000 */
/*00f0*/ IMAD.MOV.U32 R7, RZ, RZ, 0x4 ; /* 0x00000004ff077424 */
/* 0x000fe400078e00ff */
/*0100*/ IMAD R6, R3, c[0x0][0x170], R4 ; /* 0x00005c0003067a24 */
/* 0x000fc800078e0204 */
/*0110*/ IMAD.WIDE R6, R6, R7, c[0x0][0x160] ; /* 0x0000580006067625 */
/* 0x000fca00078e0207 */
/*0120*/ LDG.E R5, [R6.64] ; /* 0x0000000806057981 */
/* 0x000164000c1e1900 */
/*0130*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0140*/ @!P3 BRA 0x640 ; /* 0x000004f00000b947 */
/* 0x000fea0003800000 */
/*0150*/ SHF.L.U32 R9, R8, 0x6, RZ ; /* 0x0000000608097819 */
/* 0x000fe200000006ff */
/*0160*/ HFMA2.MMA R8, -RZ, RZ, 0, 0 ; /* 0x00000000ff087435 */
/* 0x000fe200000001ff */
/*0170*/ IMAD.MOV.U32 R0, RZ, RZ, RZ ; /* 0x000000ffff007224 */
/* 0x000fe200078e00ff */
/*0180*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe40008000000 */
/*0190*/ IMAD R11, R2, 0x4, R9 ; /* 0x00000004020b7824 */
/* 0x000fe400078e0209 */
/*01a0*/ ISETP.GE.U32.OR P2, PT, R2, c[0x0][0x174], P0 ; /* 0x00005d0002007a0c */
/* 0x000fda0000746470 */
/*01b0*/ @!P2 MOV R7, 0x4 ; /* 0x000000040007a802 */
/* 0x001fca0000000f00 */
/*01c0*/ @!P2 IMAD.WIDE.U32 R6, R2, R7, c[0x0][0x160] ; /* 0x000058000206a625 */
/* 0x000fcc00078e0007 */
/*01d0*/ @!P2 LDG.E R6, [R6.64] ; /* 0x000000080606a981 */
/* 0x000ea2000c1e1900 */
/*01e0*/ ISETP.LT.U32.AND P6, PT, R4, UR4, PT ; /* 0x0000000404007c0c */
/* 0x000fe2000bfc1070 */
/*01f0*/ UIADD3 UR5, UR4, 0x1, URZ ; /* 0x0000000104057890 */
/* 0x000fe2000fffe03f */
/*0200*/ IADD3 R8, R8, 0x1, RZ ; /* 0x0000000108087810 */
/* 0x000fe20007ffe0ff */
/*0210*/ UIADD3 UR6, UR4, 0x2, URZ ; /* 0x0000000204067890 */
/* 0x000fe2000fffe03f */
/*0220*/ IADD3 R2, R2, 0x10, RZ ; /* 0x0000001002027810 */
/* 0x000fc60007ffe0ff */
/*0230*/ ISETP.LT.U32.AND P5, PT, R4, UR5, PT ; /* 0x0000000504007c0c */
/* 0x000fe2000bfa1070 */
/*0240*/ UIADD3 UR5, UR4, 0x3, URZ ; /* 0x0000000304057890 */
/* 0x000fcc000fffe03f */
/*0250*/ ISETP.LT.U32.AND P4, PT, R4.reuse, UR5, PT ; /* 0x0000000504007c0c */
/* 0x040fe2000bf81070 */
/*0260*/ UIADD3 UR5, UR4, 0x5, URZ ; /* 0x0000000504057890 */
/* 0x000fe2000fffe03f */
/*0270*/ @!P2 STS [R11], R6 ; /* 0x000000060b00a388 */
/* 0x004fe80000000800 */
/*0280*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0290*/ ISETP.LT.U32.AND P2, PT, R4, UR6, PT ; /* 0x0000000604007c0c */
/* 0x000fe2000bf41070 */
/*02a0*/ UIADD3 UR6, UR4, 0x4, URZ ; /* 0x0000000404067890 */
/* 0x000fcc000fffe03f */
/*02b0*/ ISETP.LT.U32.AND P3, PT, R4.reuse, UR6, PT ; /* 0x0000000604007c0c */
/* 0x040fe2000bf61070 */
/*02c0*/ UIADD3 UR6, UR4, 0x7, URZ ; /* 0x0000000704067890 */
/* 0x000fe2000fffe03f */
/*02d0*/ @!P6 LDS R10, [R9] ; /* 0x00000000090ae984 */
/* 0x000e280000000800 */
/*02e0*/ @!P5 LDS R7, [R9+0x4] ; /* 0x000004000907d984 */
/* 0x000e680000000800 */
/*02f0*/ @!P4 LDS R12, [R9+0xc] ; /* 0x00000c00090cc984 */
/* 0x000fe80000000800 */
/*0300*/ @!P3 LDS R6, [R9+0x10] ; /* 0x000010000906b984 */
/* 0x000fe20000000800 */
/*0310*/ @!P6 FFMA R0, R5, R10, R0 ; /* 0x0000000a0500e223 */
/* 0x021fe20000000000 */
/*0320*/ ISETP.LT.U32.AND P6, PT, R4, UR5, PT ; /* 0x0000000504007c0c */
/* 0x000fc4000bfc1070 */
/*0330*/ @!P2 LDS R10, [R9+0x8] ; /* 0x00000800090aa984 */
/* 0x000e220000000800 */
/*0340*/ UIADD3 UR5, UR4, 0x6, URZ ; /* 0x0000000604057890 */
/* 0x000fe2000fffe03f */
/*0350*/ @!P5 FFMA R0, R5, R7, R0 ; /* 0x000000070500d223 */
/* 0x002fca0000000000 */
/*0360*/ ISETP.LT.U32.AND P5, PT, R4, UR5, PT ; /* 0x0000000504007c0c */
/* 0x000fe2000bfa1070 */
/*0370*/ UIADD3 UR5, UR4, 0x8, URZ ; /* 0x0000000804057890 */
/* 0x000fc6000fffe03f */
/*0380*/ @!P6 LDS R13, [R9+0x14] ; /* 0x00001400090de984 */
/* 0x000e720000000800 */
/*0390*/ @!P5 LDS R7, [R9+0x18] ; /* 0x000018000907d984 */
/* 0x000ea20000000800 */
/*03a0*/ @!P2 FFMA R0, R5, R10, R0 ; /* 0x0000000a0500a223 */
/* 0x001fe20000000000 */
/*03b0*/ ISETP.LT.U32.AND P2, PT, R4, UR6, PT ; /* 0x0000000604007c0c */
/* 0x000fe2000bf41070 */
/*03c0*/ UIADD3 UR6, UR4, 0x9, URZ ; /* 0x0000000904067890 */
/* 0x000fc4000fffe03f */
/*03d0*/ @!P4 FFMA R0, R5.reuse, R12, R0 ; /* 0x0000000c0500c223 */
/* 0x040fe20000000000 */
/*03e0*/ ISETP.LT.U32.AND P4, PT, R4.reuse, UR5, PT ; /* 0x0000000504007c0c */
/* 0x040fe2000bf81070 */
/*03f0*/ UIADD3 UR5, UR4, 0xa, URZ ; /* 0x0000000a04057890 */
/* 0x000fe4000fffe03f */
/*0400*/ @!P3 FFMA R0, R5.reuse, R6, R0 ; /* 0x000000060500b223 */
/* 0x040fe20000000000 */
/*0410*/ ISETP.LT.U32.AND P3, PT, R4.reuse, UR6, PT ; /* 0x0000000604007c0c */
/* 0x040fe2000bf61070 */
/*0420*/ UIADD3 UR6, UR4, 0xc, URZ ; /* 0x0000000c04067890 */
/* 0x000fe4000fffe03f */
/*0430*/ @!P6 FFMA R0, R5, R13, R0 ; /* 0x0000000d0500e223 */
/* 0x002fe20000000000 */
/*0440*/ ISETP.LT.U32.AND P6, PT, R4, UR5, PT ; /* 0x0000000504007c0c */
/* 0x000fe2000bfc1070 */
/*0450*/ @!P2 LDS R10, [R9+0x1c] ; /* 0x00001c00090aa984 */
/* 0x000e220000000800 */
/*0460*/ UIADD3 UR5, UR4, 0xb, URZ ; /* 0x0000000b04057890 */
/* 0x000fc6000fffe03f */
/*0470*/ @!P4 LDS R6, [R9+0x20] ; /* 0x000020000906c984 */
/* 0x000e620000000800 */
/*0480*/ @!P5 FFMA R0, R5, R7, R0 ; /* 0x000000070500d223 */
/* 0x004fe40000000000 */
/*0490*/ ISETP.LT.U32.AND P5, PT, R4, UR5, PT ; /* 0x0000000504007c0c */
/* 0x000fe2000bfa1070 */
/*04a0*/ @!P3 LDS R12, [R9+0x24] ; /* 0x00002400090cb984 */
/* 0x000ea20000000800 */
/*04b0*/ UIADD3 UR5, UR4, 0xd, URZ ; /* 0x0000000d04057890 */
/* 0x000fc6000fffe03f */
/*04c0*/ @!P6 LDS R13, [R9+0x28] ; /* 0x00002800090de984 */
/* 0x000ef00000000800 */
/*04d0*/ @!P5 LDS R7, [R9+0x2c] ; /* 0x00002c000907d984 */
/* 0x000f220000000800 */
/*04e0*/ @!P2 FFMA R0, R5, R10, R0 ; /* 0x0000000a0500a223 */
/* 0x001fe20000000000 */
/*04f0*/ ISETP.LT.U32.AND P2, PT, R4, UR6, PT ; /* 0x0000000604007c0c */
/* 0x000fe2000bf41070 */
/*0500*/ UIADD3 UR6, UR4, 0xe, URZ ; /* 0x0000000e04067890 */
/* 0x000fc4000fffe03f */
/*0510*/ @!P4 FFMA R0, R5.reuse, R6, R0 ; /* 0x000000060500c223 */
/* 0x042fe20000000000 */
/*0520*/ ISETP.LT.U32.AND P4, PT, R4.reuse, UR5, PT ; /* 0x0000000504007c0c */
/* 0x040fe2000bf81070 */
/*0530*/ UIADD3 UR5, UR4, 0xf, URZ ; /* 0x0000000f04057890 */
/* 0x000fe4000fffe03f */
/*0540*/ @!P3 FFMA R0, R5.reuse, R12, R0 ; /* 0x0000000c0500b223 */
/* 0x044fe20000000000 */
/*0550*/ ISETP.LT.U32.AND P3, PT, R4.reuse, UR6, PT ; /* 0x0000000604007c0c */
/* 0x040fe2000bf61070 */
/*0560*/ UIADD3 UR4, UR4, 0x10, URZ ; /* 0x0000001004047890 */
/* 0x000fe4000fffe03f */
/*0570*/ @!P6 FFMA R0, R5.reuse, R13, R0 ; /* 0x0000000d0500e223 */
/* 0x048fe20000000000 */
/*0580*/ ISETP.LT.U32.AND P6, PT, R4, UR5, PT ; /* 0x0000000504007c0c */
/* 0x000fe2000bfc1070 */
/*0590*/ @!P2 LDS R6, [R9+0x30] ; /* 0x000030000906a984 */
/* 0x000e280000000800 */
/*05a0*/ @!P4 LDS R10, [R9+0x34] ; /* 0x00003400090ac984 */
/* 0x000e620000000800 */
/*05b0*/ @!P5 FFMA R0, R5, R7, R0 ; /* 0x000000070500d223 */
/* 0x010fc60000000000 */
/*05c0*/ @!P3 LDS R12, [R9+0x38] ; /* 0x00003800090cb984 */
/* 0x000ea80000000800 */
/*05d0*/ @!P6 LDS R13, [R9+0x3c] ; /* 0x00003c00090de984 */
/* 0x000ee20000000800 */
/*05e0*/ @!P2 FFMA R0, R5, R6, R0 ; /* 0x000000060500a223 */
/* 0x001fe20000000000 */
/*05f0*/ ISETP.GE.U32.AND P2, PT, R8, c[0x0][0x178], PT ; /* 0x00005e0008007a0c */
/* 0x000fc60003f46070 */
/*0600*/ @!P4 FFMA R0, R5, R10, R0 ; /* 0x0000000a0500c223 */
/* 0x002fc80000000000 */
/*0610*/ @!P3 FFMA R0, R5, R12, R0 ; /* 0x0000000c0500b223 */
/* 0x004fc80000000000 */
/*0620*/ @!P6 FFMA R0, R5, R13, R0 ; /* 0x0000000d0500e223 */
/* 0x008fe40000000000 */
/*0630*/ @!P2 BRA 0x1a0 ; /* 0xfffffb600000a947 */
/* 0x000fea000383ffff */
/*0640*/ @P1 EXIT ; /* 0x000000000000194d */
/* 0x000fea0003800000 */
/*0650*/ IMAD.MOV.U32 R2, RZ, RZ, 0x4 ; /* 0x00000004ff027424 */
/* 0x000fe400078e00ff */
/*0660*/ IMAD R3, R3, c[0x0][0x170], R4 ; /* 0x00005c0003037a24 */
/* 0x000fc800078e0204 */
/*0670*/ IMAD.WIDE R2, R3, R2, c[0x0][0x168] ; /* 0x00005a0003027625 */
/* 0x000fca00078e0202 */
/*0680*/ STG.E [R2.64], R0 ; /* 0x0000000002007986 */
/* 0x000fe2000c101908 */
/*0690*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*06a0*/ BRA 0x6a0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*06b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0700*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0710*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0720*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0730*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0740*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0750*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0760*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0770*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z17unknown_algo_inp2PfS_iii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ ISETP.NE.AND P1, PT, RZ, c[0x0][0x178], PT ; /* 0x00005e00ff007a0c */
/* 0x000fc60003f25270 */
/*0030*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e280000002100 */
/*0040*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e680000002600 */
/*0050*/ S2R R4, SR_TID.Y ; /* 0x0000000000047919 */
/* 0x000e620000002200 */
/*0060*/ IMAD R0, R0, c[0x0][0x0], R2 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0202 */
/*0070*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x174], PT ; /* 0x00005d0000007a0c */
/* 0x000fe20003f06270 */
/*0080*/ IMAD R3, R3, c[0x0][0x4], R4 ; /* 0x0000010003037a24 */
/* 0x002fca00078e0204 */
/*0090*/ ISETP.GE.OR P0, PT, R3, c[0x0][0x170], P0 ; /* 0x00005c0003007a0c */
/* 0x000fe20000706670 */
/*00a0*/ @!P1 BRA 0x1a0 ; /* 0x000000f000009947 */
/* 0x000fd80003800000 */
/*00b0*/ IMAD R4, R4, 0x10, R2.reuse ; /* 0x0000001004047824 */
/* 0x100fe200078e0202 */
/*00c0*/ HFMA2.MMA R6, -RZ, RZ, 0, 0 ; /* 0x00000000ff067435 */
/* 0x000fe200000001ff */
/*00d0*/ IMAD R5, R3, c[0x0][0x170], R2 ; /* 0x00005c0003057a24 */
/* 0x000fe400078e0202 */
/*00e0*/ IMAD.SHL.U32 R7, R4, 0x4, RZ ; /* 0x0000000404077824 */
/* 0x000fca00078e00ff */
/*00f0*/ ISETP.GE.U32.AND P1, PT, R2, c[0x0][0x174], PT ; /* 0x00005d0002007a0c */
/* 0x000fe40003f26070 */
/*0100*/ IADD3 R6, R6, 0x1, RZ ; /* 0x0000000106067810 */
/* 0x000fe40007ffe0ff */
/*0110*/ ISETP.GE.OR P1, PT, R0, c[0x0][0x170], P1 ; /* 0x00005c0000007a0c */
/* 0x000fe40000f26670 */
/*0120*/ IADD3 R2, R2, 0x10, RZ ; /* 0x0000001002027810 */
/* 0x000fd60007ffe0ff */
/*0130*/ @!P1 SHF.L.U32 R4, R5.reuse, 0x2, RZ ; /* 0x0000000205049819 */
/* 0x040fe400000006ff */
/*0140*/ IADD3 R5, R5, 0x10, RZ ; /* 0x0000001005057810 */
/* 0x000fc80007ffe0ff */
/*0150*/ @!P1 LDC R4, c[0x3][R4] ; /* 0x00c0000004049b82 */
/* 0x000e240000000800 */
/*0160*/ @!P1 STS [R7], R4 ; /* 0x0000000407009388 */
/* 0x0011e80000000800 */
/*0170*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0180*/ ISETP.GE.U32.AND P1, PT, R6, c[0x0][0x178], PT ; /* 0x00005e0006007a0c */
/* 0x000fda0003f26070 */
/*0190*/ @!P1 BRA 0xf0 ; /* 0xffffff5000009947 */
/* 0x001fea000383ffff */
/*01a0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*01b0*/ IMAD.MOV.U32 R2, RZ, RZ, 0x4 ; /* 0x00000004ff027424 */
/* 0x000fe200078e00ff */
/*01c0*/ MOV R5, 0x41f00000 ; /* 0x41f0000000057802 */
/* 0x000fe20000000f00 */
/*01d0*/ IMAD R3, R3, c[0x0][0x170], R0 ; /* 0x00005c0003037a24 */
/* 0x000fe200078e0200 */
/*01e0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*01f0*/ IMAD.WIDE R2, R3, R2, c[0x0][0x168] ; /* 0x00005a0003027625 */
/* 0x000fca00078e0202 */
/*0200*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*0210*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0220*/ BRA 0x220; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z17unknown_algo_inp2PfS_iii
.globl _Z17unknown_algo_inp2PfS_iii
.p2align 8
.type _Z17unknown_algo_inp2PfS_iii,@function
_Z17unknown_algo_inp2PfS_iii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s4, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_lshr_b32 s3, s2, 16
s_cmp_eq_u32 s4, 0
s_cbranch_scc1 .LBB0_2
.LBB0_1:
s_add_i32 s4, s4, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s4, 0
s_barrier
buffer_gl0_inv
s_cbranch_scc0 .LBB0_1
.LBB0_2:
s_load_b64 s[4:5], s[0:1], 0x10
v_bfe_u32 v2, v0, 10, 10
v_and_b32_e32 v3, 0x3ff, v0
s_and_b32 s3, 0xffff, s3
s_and_b32 s2, 0xffff, s2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[0:1], null, s15, s3, v[2:3]
v_mad_u64_u32 v[1:2], null, s14, s2, v[3:4]
s_waitcnt lgkmcnt(0)
v_cmp_gt_i32_e32 vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i32_e64 s2, s5, v1
s_and_b32 s2, s2, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_4
s_load_b64 s[0:1], s[0:1], 0x8
v_mad_u64_u32 v[2:3], null, v0, s4, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[0:1], 2, v[2:3]
v_mov_b32_e32 v2, 0x41f00000
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v2, off
.LBB0_4:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z17unknown_algo_inp2PfS_iii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z17unknown_algo_inp2PfS_iii, .Lfunc_end0-_Z17unknown_algo_inp2PfS_iii
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z17unknown_algo_inp1PfS_iii
.globl _Z17unknown_algo_inp1PfS_iii
.p2align 8
.type _Z17unknown_algo_inp1PfS_iii,@function
_Z17unknown_algo_inp1PfS_iii:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x10
s_load_b64 s[4:5], s[0:1], 0x0
v_and_b32_e32 v4, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s6, s2, 0xffff
s_lshr_b32 s2, s2, 16
v_mad_u64_u32 v[0:1], null, s14, s6, v[4:5]
v_mad_u64_u32 v[1:2], null, s15, s2, v[3:4]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_gt_i32_e32 vcc_lo, s3, v0
v_cmp_gt_i32_e64 s2, s3, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, vcc_lo, s2
s_and_saveexec_b32 s6, s2
s_cbranch_execz .LBB1_2
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[5:6], null, v0, s3, v[1:2]
v_ashrrev_i32_e32 v6, 31, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[5:6], 2, v[5:6]
v_add_co_u32 v5, s2, s4, v5
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v6, s2, s5, v6, s2
global_load_b32 v6, v[5:6], off
.LBB1_2:
s_or_b32 exec_lo, exec_lo, s6
s_load_b64 s[6:7], s[0:1], 0x14
s_mov_b32 s8, 0
s_waitcnt lgkmcnt(0)
s_cmp_eq_u32 s7, 0
s_cbranch_scc1 .LBB1_11
v_dual_mov_b32 v2, 0 :: v_dual_lshlrev_b32 v7, 6, v4
v_mov_b32_e32 v5, 0
s_mov_b32 s9, 0
s_delay_alu instid0(VALU_DEP_2)
v_lshl_add_u32 v8, v3, 2, v7
s_set_inst_prefetch_distance 0x1
s_branch .LBB1_5
.p2align 6
.LBB1_4:
s_add_i32 s8, s8, 1
s_add_i32 s9, s9, 16
s_cmp_eq_u32 s8, s7
s_cbranch_scc1 .LBB1_12
.LBB1_5:
v_lshl_add_u32 v4, s8, 4, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_u32_e64 s2, s6, v4
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s10, s2
s_cbranch_execz .LBB1_7
v_lshlrev_b64 v[9:10], 2, v[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v9, s2, s4, v9
v_add_co_ci_u32_e64 v10, s2, s5, v10, s2
global_load_b32 v4, v[9:10], off
s_waitcnt vmcnt(0)
ds_store_b32 v8, v4
.LBB1_7:
s_or_b32 exec_lo, exec_lo, s10
v_mov_b32_e32 v4, v7
s_mov_b32 s10, 0
s_waitcnt vmcnt(0) lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_branch .LBB1_9
.LBB1_8:
s_or_b32 exec_lo, exec_lo, s11
v_add_nc_u32_e32 v4, 4, v4
s_add_i32 s10, s10, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s10, 16
s_cbranch_scc1 .LBB1_4
.LBB1_9:
s_add_i32 s2, s9, s10
s_mov_b32 s11, exec_lo
v_cmpx_le_u32_e64 s2, v1
s_cbranch_execz .LBB1_8
ds_load_b32 v9, v4
s_waitcnt lgkmcnt(0)
v_fmac_f32_e32 v2, v6, v9
s_branch .LBB1_8
.LBB1_11:
v_mov_b32_e32 v2, 0
.LBB1_12:
s_set_inst_prefetch_distance 0x2
v_cmp_gt_i32_e64 s2, s6, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, vcc_lo, s2
s_and_saveexec_b32 s4, s2
s_cbranch_execz .LBB1_14
s_load_b64 s[0:1], s[0:1], 0x8
v_mad_u64_u32 v[3:4], null, v0, s3, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v4, 31, v3
v_lshlrev_b64 v[0:1], 2, v[3:4]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v2, off
.LBB1_14:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z17unknown_algo_inp1PfS_iii
.amdhsa_group_segment_fixed_size 1024
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 11
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z17unknown_algo_inp1PfS_iii, .Lfunc_end1-_Z17unknown_algo_inp1PfS_iii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.protected c_inp
.type c_inp,@object
.section .bss,"aw",@nobits
.globl c_inp
.p2align 4, 0x0
c_inp:
.zero 64000
.size c_inp, 64000
.type __hip_cuid_,@object
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym c_inp
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z17unknown_algo_inp2PfS_iii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z17unknown_algo_inp2PfS_iii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 1024
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z17unknown_algo_inp1PfS_iii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z17unknown_algo_inp1PfS_iii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 11
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00091176_00000000-6_v5_gpu.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3674:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3674:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z5cpu_vPfS_S_iiS_
.type _Z5cpu_vPfS_S_iiS_, @function
_Z5cpu_vPfS_S_iiS_:
.LFB3669:
.cfi_startproc
endbr64
testl %ecx, %ecx
jle .L13
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
movq %rdi, %r10
movq %rsi, %rbx
movq %rdx, %rbp
movl %ecx, %r12d
movl %r8d, %r13d
movslq %ecx, %rcx
leaq (%r9,%rcx,4), %r14
movslq %r8d, %rax
leaq (%rdi,%rax,4), %rsi
movl $0, %r11d
movq %r9, %rcx
.L8:
movq %rcx, %rdx
movl $0x00000000, (%rcx)
testl %r13d, %r13d
jle .L5
movslq %r11d, %r8
salq $2, %r8
leaq (%rbx,%r8), %r9
addq %rbp, %r8
movq %r10, %rdi
.L7:
movss (%rdx), %xmm0
addss (%r9), %xmm0
movss %xmm0, (%rdx)
movq %r8, %r15
movss %xmm0, (%r8)
movq %r10, %rax
.L6:
movss (%rdi), %xmm0
mulss (%rax), %xmm0
addss (%r15), %xmm0
movss %xmm0, (%r15)
addq $4, %rax
cmpq %rsi, %rax
jne .L6
addq $4, %r9
addq $4, %r8
addq $4, %rdi
cmpq %rsi, %rdi
jne .L7
.L5:
addq $4, %rcx
addl %r12d, %r11d
cmpq %r14, %rcx
jne .L8
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L13:
.cfi_restore 3
.cfi_restore 6
.cfi_restore 12
.cfi_restore 13
.cfi_restore 14
.cfi_restore 15
ret
.cfi_endproc
.LFE3669:
.size _Z5cpu_vPfS_S_iiS_, .-_Z5cpu_vPfS_S_iiS_
.globl _Z11compare_resPfS_ii
.type _Z11compare_resPfS_ii, @function
_Z11compare_resPfS_ii:
.LFB3670:
.cfi_startproc
endbr64
testl %edx, %edx
jle .L24
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movl $0, %r11d
movl $0, %r10d
movl $0, %r9d
movslq %ecx, %rbx
jmp .L18
.L25:
addl $1, %r9d
.L19:
addq $4, %rax
cmpq %r8, %rax
je .L23
.L21:
movss (%rdi,%rax), %xmm0
ucomiss (%rsi,%rax), %xmm0
jp .L25
je .L19
jmp .L25
.L23:
addl $1, %r10d
addl %edx, %r11d
cmpl %r10d, %edx
je .L16
.L18:
testl %ecx, %ecx
jle .L23
movslq %r11d, %r8
leaq 0(,%r8,4), %rax
addq %rbx, %r8
salq $2, %r8
jmp .L21
.L24:
.cfi_def_cfa_offset 8
.cfi_restore 3
movl $0, %r9d
movl %r9d, %eax
ret
.L16:
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movl %r9d, %eax
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3670:
.size _Z11compare_resPfS_ii, .-_Z11compare_resPfS_ii
.globl _Z42__device_stub__Z17unknown_algo_inp2PfS_iiiPfS_iii
.type _Z42__device_stub__Z17unknown_algo_inp2PfS_iiiPfS_iii, @function
_Z42__device_stub__Z17unknown_algo_inp2PfS_iiiPfS_iii:
.LFB3696:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L35
.L31:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L36
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L35:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z17unknown_algo_inp2PfS_iii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L31
.L36:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3696:
.size _Z42__device_stub__Z17unknown_algo_inp2PfS_iiiPfS_iii, .-_Z42__device_stub__Z17unknown_algo_inp2PfS_iiiPfS_iii
.globl _Z17unknown_algo_inp2PfS_iii
.type _Z17unknown_algo_inp2PfS_iii, @function
_Z17unknown_algo_inp2PfS_iii:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z42__device_stub__Z17unknown_algo_inp2PfS_iiiPfS_iii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _Z17unknown_algo_inp2PfS_iii, .-_Z17unknown_algo_inp2PfS_iii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC6:
.string "error count: %d\nGPU time for execution: %lf ms\nCPU time for execution: %lf ms\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC7:
.string "gridx: %d gridy: %d\n"
.LC8:
.string "%d. "
.LC9:
.string "%d "
.LC10:
.string "\n"
.text
.globl main
.type main, @function
main:
.LFB3671:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $152, %rsp
.cfi_def_cfa_offset 208
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
movl $128, %r13d
movl $128, %r14d
cmpl $3, %edi
je .L68
.L40:
movslq %r13d, %rbp
leaq 72(%rsp), %rdi
call cudaEventCreate@PLT
leaq 80(%rsp), %rdi
call cudaEventCreate@PLT
leal 0(,%r13,4), %eax
movslq %eax, %r12
movq %r12, %rdi
call malloc@PLT
movq %rax, 88(%rsp)
movl %r14d, %ebx
imull %r13d, %ebx
sall $2, %ebx
movslq %ebx, %rbx
movq %rbx, %rdi
call malloc@PLT
movq %rax, 96(%rsp)
movq %rbx, %rdi
call malloc@PLT
movq %rax, 104(%rsp)
movq %r12, %rdi
call malloc@PLT
movq %rax, 24(%rsp)
movq %rbx, %rdi
call malloc@PLT
movq %rax, %r15
movq %rax, 40(%rsp)
movq %rbx, %rdi
call malloc@PLT
movq %rax, 32(%rsp)
movslq %r14d, %rdi
salq $2, %rdi
call malloc@PLT
movq %rax, 56(%rsp)
movq %rbx, %rdi
call malloc@PLT
movq %rax, 48(%rsp)
leaq 88(%rsp), %rdi
movq %r12, %rsi
call cudaMalloc@PLT
leaq 96(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 104(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
testl %r14d, %r14d
jle .L41
movl %r14d, %edi
movl $0, %esi
movl $0, %ecx
movss .LC1(%rip), %xmm0
movq %r15, %r8
jmp .L42
.L68:
movq %rsi, %rbx
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movl %eax, %r14d
movq 16(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movl %eax, %r13d
jmp .L40
.L44:
movslq %esi, %rdx
leaq (%r8,%rdx,4), %rax
addq %rbp, %rdx
leaq (%r8,%rdx,4), %rdx
.L43:
movss %xmm0, (%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L43
.L45:
addl $1, %ecx
addl %edi, %esi
cmpl %ecx, %r14d
je .L41
.L42:
testl %r13d, %r13d
jg .L44
jmp .L45
.L41:
testl %r13d, %r13d
jle .L46
movq 24(%rsp), %rcx
movq %rcx, %rax
leaq (%rcx,%rbp,4), %rdx
movss .LC1(%rip), %xmm0
.L47:
movss %xmm0, (%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L47
.L46:
movl $1, %ecx
movq %r12, %rdx
movq 24(%rsp), %rsi
movq 88(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %r8d
movl $0, %ecx
movq %rbx, %rdx
movq 40(%rsp), %rsi
leaq _ZL5c_inp(%rip), %rdi
call cudaMemcpyToSymbol@PLT
pxor %xmm0, %xmm0
cvtsi2ssl %r14d, %xmm0
mulss .LC2(%rip), %xmm0
movaps %xmm0, %xmm3
movss .LC11(%rip), %xmm2
movaps %xmm0, %xmm1
andps %xmm2, %xmm1
movss .LC3(%rip), %xmm4
ucomiss %xmm1, %xmm4
jbe .L48
cvttss2sil %xmm0, %eax
pxor %xmm1, %xmm1
cvtsi2ssl %eax, %xmm1
cmpnless %xmm1, %xmm3
movss .LC1(%rip), %xmm4
andps %xmm4, %xmm3
addss %xmm1, %xmm3
andnps %xmm0, %xmm2
orps %xmm2, %xmm3
.L48:
cvttss2sil %xmm3, %r15d
pxor %xmm0, %xmm0
cvtsi2ssl %r13d, %xmm0
mulss .LC2(%rip), %xmm0
movaps %xmm0, %xmm3
movss .LC11(%rip), %xmm2
movaps %xmm0, %xmm1
andps %xmm2, %xmm1
movss .LC3(%rip), %xmm4
ucomiss %xmm1, %xmm4
jbe .L49
cvttss2sil %xmm0, %eax
pxor %xmm1, %xmm1
cvtsi2ssl %eax, %xmm1
cmpnless %xmm1, %xmm3
movss .LC1(%rip), %xmm4
andps %xmm4, %xmm3
addss %xmm1, %xmm3
andnps %xmm0, %xmm2
orps %xmm2, %xmm3
.L49:
cvttss2sil %xmm3, %r12d
movl %r15d, 112(%rsp)
movl %r12d, 116(%rsp)
movl $1, 120(%rsp)
movl $16, 124(%rsp)
movl $16, 128(%rsp)
movl $1, 132(%rsp)
movl $0, %esi
movq 72(%rsp), %rdi
call cudaEventRecord@PLT
movl 132(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 124(%rsp), %rdx
movq 112(%rsp), %rdi
movl 120(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L69
.L50:
movl $0, %esi
movq 80(%rsp), %rdi
call cudaEventRecord@PLT
movl $2, %ecx
movq %rbx, %rdx
movq 104(%rsp), %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
movq 80(%rsp), %rdi
call cudaEventSynchronize@PLT
movl $0x00000000, 68(%rsp)
leaq 68(%rsp), %rdi
movq 80(%rsp), %rdx
movq 72(%rsp), %rsi
call cudaEventElapsedTime@PLT
call clock@PLT
movq %rax, (%rsp)
movq 56(%rsp), %r9
movl %r13d, %r8d
movl %r14d, %ecx
movq 48(%rsp), %rdx
movq 40(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z5cpu_vPfS_S_iiS_
call clock@PLT
movq %rax, %rbx
movl %r13d, %ecx
movl %r14d, %edx
movq 48(%rsp), %rsi
movq 32(%rsp), %rdi
call _Z11compare_resPfS_ii
movq (%rsp), %rcx
subq %rcx, %rbx
imulq $1000, %rbx, %rdx
pxor %xmm1, %xmm1
cvtsi2ssq %rdx, %xmm1
divss .LC5(%rip), %xmm1
pxor %xmm0, %xmm0
cvtss2sd 68(%rsp), %xmm0
cvtss2sd %xmm1, %xmm1
movl %eax, %edx
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $2, %eax
call __printf_chk@PLT
movl %r12d, %ecx
movl %r15d, %edx
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
testl %r14d, %r14d
jle .L51
movl %r14d, 8(%rsp)
movl $0, %r15d
movl $0, %eax
leaq .LC9(%rip), %r12
movq %rbp, 16(%rsp)
movl %r14d, 12(%rsp)
movl %r13d, (%rsp)
movq 32(%rsp), %r13
movl %eax, %r14d
jmp .L54
.L69:
movl %r15d, %r8d
movl %r13d, %ecx
movl %r14d, %edx
movq 104(%rsp), %rsi
movq 96(%rsp), %rdi
call _Z42__device_stub__Z17unknown_algo_inp2PfS_iiiPfS_iii
jmp .L50
.L60:
movl %ecx, %r14d
.L54:
movl %r14d, %edx
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
cmpl $0, (%rsp)
jle .L52
movslq %r15d, %rax
leaq 0(%r13,%rax,4), %rbx
movq 16(%rsp), %rcx
addq %rcx, %rax
leaq 0(%r13,%rax,4), %rbp
.L53:
cvttss2sil (%rbx), %edx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %rbp, %rbx
jne .L53
.L52:
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leal 1(%r14), %ecx
movl 8(%rsp), %eax
addl %eax, %r15d
cmpl %ecx, 12(%rsp)
jne .L60
movl (%rsp), %r13d
movl %r14d, (%rsp)
movl $0, %eax
movl $0, %r14d
leaq .LC9(%rip), %r12
movl %r13d, 8(%rsp)
movl %eax, %r13d
movq 48(%rsp), %r15
movl %ecx, 12(%rsp)
jmp .L57
.L61:
movl %eax, %r14d
.L57:
movl %r14d, %edx
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
cmpl $0, 8(%rsp)
jle .L55
movslq %r13d, %rax
leaq (%r15,%rax,4), %rbx
movq 16(%rsp), %rcx
addq %rcx, %rax
leaq (%r15,%rax,4), %rbp
.L56:
cvttss2sil (%rbx), %edx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %rbx, %rbp
jne .L56
.L55:
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leal 1(%r14), %eax
movl 12(%rsp), %ecx
addl %ecx, %r13d
cmpl %r14d, (%rsp)
jne .L61
.L51:
movq 24(%rsp), %rdi
call free@PLT
movq 40(%rsp), %rdi
call free@PLT
movq 32(%rsp), %rdi
call free@PLT
movq 56(%rsp), %rdi
call free@PLT
movq 88(%rsp), %rdi
call cudaFree@PLT
movq 96(%rsp), %rdi
call cudaFree@PLT
movq 104(%rsp), %rdi
call cudaFree@PLT
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L70
movl $0, %eax
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L70:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3671:
.size main, .-main
.globl _Z42__device_stub__Z17unknown_algo_inp1PfS_iiiPfS_iii
.type _Z42__device_stub__Z17unknown_algo_inp1PfS_iiiPfS_iii, @function
_Z42__device_stub__Z17unknown_algo_inp1PfS_iiiPfS_iii:
.LFB3698:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L75
.L71:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L76
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L75:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z17unknown_algo_inp1PfS_iii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L71
.L76:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3698:
.size _Z42__device_stub__Z17unknown_algo_inp1PfS_iiiPfS_iii, .-_Z42__device_stub__Z17unknown_algo_inp1PfS_iiiPfS_iii
.globl _Z17unknown_algo_inp1PfS_iii
.type _Z17unknown_algo_inp1PfS_iii, @function
_Z17unknown_algo_inp1PfS_iii:
.LFB3699:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z42__device_stub__Z17unknown_algo_inp1PfS_iiiPfS_iii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3699:
.size _Z17unknown_algo_inp1PfS_iii, .-_Z17unknown_algo_inp1PfS_iii
.section .rodata.str1.1
.LC12:
.string "_Z17unknown_algo_inp1PfS_iii"
.LC13:
.string "_Z17unknown_algo_inp2PfS_iii"
.LC14:
.string "c_inp"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3701:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC12(%rip), %rdx
movq %rdx, %rcx
leaq _Z17unknown_algo_inp1PfS_iii(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC13(%rip), %rdx
movq %rdx, %rcx
leaq _Z17unknown_algo_inp2PfS_iii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $64000, %r9d
movl $0, %r8d
leaq .LC14(%rip), %rdx
movq %rdx, %rcx
leaq _ZL5c_inp(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3701:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL5c_inp
.comm _ZL5c_inp,64000,32
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC1:
.long 1065353216
.align 4
.LC2:
.long 1031798784
.align 4
.LC3:
.long 1258291200
.align 4
.LC5:
.long 1232348160
.align 4
.LC11:
.long 2147483647
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "v5_gpu.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z32__device_stub__unknown_algo_inp2PfS_iii # -- Begin function _Z32__device_stub__unknown_algo_inp2PfS_iii
.p2align 4, 0x90
.type _Z32__device_stub__unknown_algo_inp2PfS_iii,@function
_Z32__device_stub__unknown_algo_inp2PfS_iii: # @_Z32__device_stub__unknown_algo_inp2PfS_iii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z17unknown_algo_inp2PfS_iii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z32__device_stub__unknown_algo_inp2PfS_iii, .Lfunc_end0-_Z32__device_stub__unknown_algo_inp2PfS_iii
.cfi_endproc
# -- End function
.globl _Z32__device_stub__unknown_algo_inp1PfS_iii # -- Begin function _Z32__device_stub__unknown_algo_inp1PfS_iii
.p2align 4, 0x90
.type _Z32__device_stub__unknown_algo_inp1PfS_iii,@function
_Z32__device_stub__unknown_algo_inp1PfS_iii: # @_Z32__device_stub__unknown_algo_inp1PfS_iii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z17unknown_algo_inp1PfS_iii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end1:
.size _Z32__device_stub__unknown_algo_inp1PfS_iii, .Lfunc_end1-_Z32__device_stub__unknown_algo_inp1PfS_iii
.cfi_endproc
# -- End function
.globl _Z5cpu_vPfS_S_iiS_ # -- Begin function _Z5cpu_vPfS_S_iiS_
.p2align 4, 0x90
.type _Z5cpu_vPfS_S_iiS_,@function
_Z5cpu_vPfS_S_iiS_: # @_Z5cpu_vPfS_S_iiS_
.cfi_startproc
# %bb.0:
testl %ecx, %ecx
jle .LBB2_9
# %bb.1: # %.lr.ph41
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl %ecx, %eax
movl %r8d, %r10d
xorl %r11d, %r11d
jmp .LBB2_2
.p2align 4, 0x90
.LBB2_7: # %._crit_edge38
# in Loop: Header=BB2_2 Depth=1
incq %r11
cmpq %rax, %r11
je .LBB2_8
.LBB2_2: # =>This Loop Header: Depth=1
# Child Loop BB2_4 Depth 2
# Child Loop BB2_5 Depth 3
movl $0, (%r9,%r11,4)
testl %r8d, %r8d
jle .LBB2_7
# %bb.3: # %.lr.ph37
# in Loop: Header=BB2_2 Depth=1
movl %r11d, %ebx
imull %ecx, %ebx
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB2_4: # %.lr.ph
# Parent Loop BB2_2 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB2_5 Depth 3
leaq (%r14,%rbx), %r15
movss (%rsi,%r15,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
addss (%r9,%r11,4), %xmm0
movss %xmm0, (%r9,%r11,4)
movss %xmm0, (%rdx,%r15,4)
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB2_5: # Parent Loop BB2_2 Depth=1
# Parent Loop BB2_4 Depth=2
# => This Inner Loop Header: Depth=3
movss (%rdi,%r14,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
mulss (%rdi,%r12,4), %xmm0
addss (%rdx,%r15,4), %xmm0
movss %xmm0, (%rdx,%r15,4)
incq %r12
cmpq %r12, %r10
jne .LBB2_5
# %bb.6: # %._crit_edge
# in Loop: Header=BB2_4 Depth=2
incq %r14
cmpq %r10, %r14
jne .LBB2_4
jmp .LBB2_7
.LBB2_8:
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r12
.cfi_restore %r14
.cfi_restore %r15
.LBB2_9: # %._crit_edge42
retq
.Lfunc_end2:
.size _Z5cpu_vPfS_S_iiS_, .Lfunc_end2-_Z5cpu_vPfS_S_iiS_
.cfi_endproc
# -- End function
.globl _Z11compare_resPfS_ii # -- Begin function _Z11compare_resPfS_ii
.p2align 4, 0x90
.type _Z11compare_resPfS_ii,@function
_Z11compare_resPfS_ii: # @_Z11compare_resPfS_ii
.cfi_startproc
# %bb.0:
testl %edx, %edx
jle .LBB3_1
# %bb.3: # %.preheader.lr.ph
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset %rbx, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %edx, %r8d
movl %ecx, %r9d
xorl %r10d, %r10d
xorl %r11d, %r11d
xorl %eax, %eax
jmp .LBB3_4
.p2align 4, 0x90
.LBB3_7: # %._crit_edge
# in Loop: Header=BB3_4 Depth=1
incq %r11
addl %edx, %r10d
cmpq %r8, %r11
je .LBB3_8
.LBB3_4: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB3_6 Depth 2
testl %ecx, %ecx
jle .LBB3_7
# %bb.5: # %.lr.ph
# in Loop: Header=BB3_4 Depth=1
movl %r10d, %r14d
leaq (%rsi,%r14,4), %rbx
leaq (%rdi,%r14,4), %r14
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB3_6: # Parent Loop BB3_4 Depth=1
# => This Inner Loop Header: Depth=2
movss (%rbx,%r15,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cmpneqss (%r14,%r15,4), %xmm0
movd %xmm0, %ebp
subl %ebp, %eax
incq %r15
cmpq %r15, %r9
jne .LBB3_6
jmp .LBB3_7
.LBB3_8:
popq %rbx
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r14
.cfi_restore %r15
.cfi_restore %rbp
retq
.LBB3_1:
xorl %eax, %eax
retq
.Lfunc_end3:
.size _Z11compare_resPfS_ii, .Lfunc_end3-_Z11compare_resPfS_ii
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI4_0:
.long 0x3d800000 # float 0.0625
.LCPI4_1:
.long 0x49742400 # float 1.0E+6
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $232, %rsp
.cfi_def_cfa_offset 288
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $128, %r13d
movl $128, %r12d
cmpl $3, %edi
jne .LBB4_2
# %bb.1:
movq 8(%rsi), %rdi
movq %rsi, %rbx
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r12
movq 16(%rbx), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r13
.LBB4_2:
leal (,%r13,4), %ebx
movl %ebx, %r14d
imull %r12d, %r14d
leaq 112(%rsp), %rdi
callq hipEventCreate
leaq 80(%rsp), %rdi
callq hipEventCreate
movslq %ebx, %rbp
movq %rbp, %rdi
callq malloc
movq %rax, 72(%rsp)
movslq %r14d, %r14
movq %r14, %rdi
callq malloc
movq %rax, 64(%rsp)
movq %r14, %rdi
callq malloc
movq %rax, 40(%rsp)
movq %rbp, %rdi
callq malloc
movq %rax, %r15
movq %r14, %rdi
callq malloc
movq %rax, 56(%rsp) # 8-byte Spill
movq %r14, %rdi
callq malloc
movq %rax, 24(%rsp) # 8-byte Spill
movslq %r12d, %rbx
leaq (,%rbx,4), %rdi
callq malloc
movq %rax, 104(%rsp) # 8-byte Spill
movq %r14, %rdi
callq malloc
movq %rax, 48(%rsp) # 8-byte Spill
leaq 72(%rsp), %rdi
movq %rbp, %rsi
callq hipMalloc
leaq 64(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
leaq 40(%rsp), %rdi
movq %r14, 8(%rsp) # 8-byte Spill
movq %r14, %rsi
callq hipMalloc
movl %r12d, %edi
movl %r13d, %r14d
testl %ebx, %ebx
jle .LBB4_8
# %bb.3: # %.preheader114.lr.ph
xorl %eax, %eax
xorl %ecx, %ecx
jmp .LBB4_4
.p2align 4, 0x90
.LBB4_7: # %._crit_edge
# in Loop: Header=BB4_4 Depth=1
incq %rcx
addl %r12d, %eax
cmpq %rdi, %rcx
je .LBB4_8
.LBB4_4: # %.preheader114
# =>This Loop Header: Depth=1
# Child Loop BB4_6 Depth 2
testl %r13d, %r13d
jle .LBB4_7
# %bb.5: # %.lr.ph
# in Loop: Header=BB4_4 Depth=1
movl %eax, %edx
movq 56(%rsp), %rsi # 8-byte Reload
leaq (%rsi,%rdx,4), %rdx
xorl %esi, %esi
.p2align 4, 0x90
.LBB4_6: # Parent Loop BB4_4 Depth=1
# => This Inner Loop Header: Depth=2
movl $1065353216, (%rdx,%rsi,4) # imm = 0x3F800000
incq %rsi
cmpq %rsi, %r14
jne .LBB4_6
jmp .LBB4_7
.LBB4_8: # %.preheader113
movq %rdi, 32(%rsp) # 8-byte Spill
testl %r13d, %r13d
jle .LBB4_11
# %bb.9: # %.lr.ph118.preheader
xorl %eax, %eax
.p2align 4, 0x90
.LBB4_10: # %.lr.ph118
# =>This Inner Loop Header: Depth=1
movl $1065353216, (%r15,%rax,4) # imm = 0x3F800000
incq %rax
cmpq %rax, %r14
jne .LBB4_10
.LBB4_11: # %._crit_edge119
movq 72(%rsp), %rdi
movq %r15, %rsi
movq %rbp, %rdx
movl $1, %ecx
callq hipMemcpy
movl $c_inp, %edi
movq 56(%rsp), %rbx # 8-byte Reload
movq %rbx, %rsi
movq 8(%rsp), %rdx # 8-byte Reload
xorl %ecx, %ecx
movl $1, %r8d
callq hipMemcpyToSymbol
cvtsi2ss %r12d, %xmm0
mulss .LCPI4_0(%rip), %xmm0
callq ceilf@PLT
cvttss2si %xmm0, %eax
movq %rax, 16(%rsp) # 8-byte Spill
xorps %xmm0, %xmm0
cvtsi2ss %r13d, %xmm0
mulss .LCPI4_0(%rip), %xmm0
callq ceilf@PLT
cvttss2si %xmm0, %ebp
movq %rbp, 120(%rsp) # 8-byte Spill
shlq $32, %rbp
addq 16(%rsp), %rbp # 8-byte Folded Reload
movq 112(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movabsq $68719476752, %rdx # imm = 0x1000000010
movq %rbp, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_13
# %bb.12:
movq 64(%rsp), %rax
movq 40(%rsp), %rcx
movq %rax, 184(%rsp)
movq %rcx, 176(%rsp)
movl %r12d, 100(%rsp)
movl %r13d, 96(%rsp)
movq 16(%rsp), %rax # 8-byte Reload
movl %eax, 92(%rsp)
leaq 184(%rsp), %rax
movq %rax, 192(%rsp)
leaq 176(%rsp), %rax
movq %rax, 200(%rsp)
leaq 100(%rsp), %rax
movq %rax, 208(%rsp)
leaq 96(%rsp), %rax
movq %rax, 216(%rsp)
leaq 92(%rsp), %rax
movq %rax, 224(%rsp)
leaq 160(%rsp), %rdi
leaq 144(%rsp), %rsi
leaq 136(%rsp), %rdx
leaq 128(%rsp), %rcx
callq __hipPopCallConfiguration
movq 160(%rsp), %rsi
movl 168(%rsp), %edx
movq 144(%rsp), %rcx
movl 152(%rsp), %r8d
leaq 192(%rsp), %r9
movl $_Z17unknown_algo_inp2PfS_iii, %edi
pushq 128(%rsp)
.cfi_adjust_cfa_offset 8
pushq 144(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_13:
movq 80(%rsp), %rdi
xorl %ebp, %ebp
xorl %esi, %esi
callq hipEventRecord
movq 40(%rsp), %rsi
movq 24(%rsp), %rdi # 8-byte Reload
movq 8(%rsp), %rdx # 8-byte Reload
movl $2, %ecx
callq hipMemcpy
movq 80(%rsp), %rdi
callq hipEventSynchronize
movl $0, 192(%rsp)
movq 112(%rsp), %rsi
movq 80(%rsp), %rdx
leaq 192(%rsp), %rdi
callq hipEventElapsedTime
callq clock
movq %rax, 8(%rsp) # 8-byte Spill
testl %r12d, %r12d
movq 104(%rsp), %r8 # 8-byte Reload
movq 48(%rsp), %r9 # 8-byte Reload
movq 32(%rsp), %r10 # 8-byte Reload
jle .LBB4_22
# %bb.14: # %.lr.ph41.i
xorl %eax, %eax
jmp .LBB4_15
.p2align 4, 0x90
.LBB4_21: # %._crit_edge38.i
# in Loop: Header=BB4_15 Depth=1
incq %rax
cmpq %r10, %rax
je .LBB4_22
.LBB4_15: # =>This Loop Header: Depth=1
# Child Loop BB4_17 Depth 2
# Child Loop BB4_18 Depth 3
movl $0, (%r8,%rax,4)
testl %r13d, %r13d
jle .LBB4_21
# %bb.16: # %.lr.ph37.i
# in Loop: Header=BB4_15 Depth=1
movl %r12d, %ecx
imull %eax, %ecx
movss (%r8,%rax,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
xorl %edx, %edx
.p2align 4, 0x90
.LBB4_17: # %.lr.ph.i
# Parent Loop BB4_15 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB4_18 Depth 3
leaq (%rdx,%rcx), %rsi
addss (%rbx,%rsi,4), %xmm0
movss %xmm0, (%r9,%rsi,4)
movss (%r15,%rdx,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
movaps %xmm0, %xmm2
xorl %edi, %edi
.p2align 4, 0x90
.LBB4_18: # Parent Loop BB4_15 Depth=1
# Parent Loop BB4_17 Depth=2
# => This Inner Loop Header: Depth=3
movss (%r15,%rdi,4), %xmm3 # xmm3 = mem[0],zero,zero,zero
mulss %xmm1, %xmm3
addss %xmm3, %xmm2
incq %rdi
cmpq %rdi, %r14
jne .LBB4_18
# %bb.19: # %._crit_edge.i
# in Loop: Header=BB4_17 Depth=2
movss %xmm2, (%r9,%rsi,4)
incq %rdx
cmpq %r14, %rdx
jne .LBB4_17
# %bb.20: # %._crit_edge38.i.loopexit
# in Loop: Header=BB4_15 Depth=1
movss %xmm0, (%r8,%rax,4)
jmp .LBB4_21
.LBB4_22: # %_Z5cpu_vPfS_S_iiS_.exit
callq clock
movq 32(%rsp), %r11 # 8-byte Reload
movq 48(%rsp), %r10 # 8-byte Reload
testl %r12d, %r12d
jle .LBB4_28
# %bb.23: # %.preheader.lr.ph.i
xorl %ecx, %ecx
xorl %edx, %edx
xorl %ebp, %ebp
jmp .LBB4_24
.p2align 4, 0x90
.LBB4_27: # %._crit_edge.i105
# in Loop: Header=BB4_24 Depth=1
incq %rdx
addl %r12d, %ecx
cmpq %r11, %rdx
je .LBB4_28
.LBB4_24: # %.preheader.i
# =>This Loop Header: Depth=1
# Child Loop BB4_26 Depth 2
testl %r13d, %r13d
jle .LBB4_27
# %bb.25: # %.lr.ph.i106
# in Loop: Header=BB4_24 Depth=1
movl %ecx, %edi
leaq (%r10,%rdi,4), %rsi
movq 24(%rsp), %r8 # 8-byte Reload
leaq (%r8,%rdi,4), %rdi
xorl %r8d, %r8d
.p2align 4, 0x90
.LBB4_26: # Parent Loop BB4_24 Depth=1
# => This Inner Loop Header: Depth=2
movss (%rsi,%r8,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cmpneqss (%rdi,%r8,4), %xmm0
movd %xmm0, %r9d
subl %r9d, %ebp
incq %r8
cmpq %r8, %r14
jne .LBB4_26
jmp .LBB4_27
.LBB4_28: # %_Z11compare_resPfS_ii.exit
movss 192(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
subq 8(%rsp), %rax # 8-byte Folded Reload
imulq $1000, %rax, %rax # imm = 0x3E8
xorps %xmm1, %xmm1
cvtsi2ss %rax, %xmm1
cvtss2sd %xmm0, %xmm0
divss .LCPI4_1(%rip), %xmm1
cvtss2sd %xmm1, %xmm1
movl $.L.str, %edi
movl %ebp, %esi
movb $2, %al
callq printf
movl $.L.str.1, %edi
movq 16(%rsp), %rsi # 8-byte Reload
# kill: def $esi killed $esi killed $rsi
movq 120(%rsp), %rdx # 8-byte Reload
# kill: def $edx killed $edx killed $rdx
xorl %eax, %eax
callq printf
testl %r12d, %r12d
movq %r12, 16(%rsp) # 8-byte Spill
movq %r13, 8(%rsp) # 8-byte Spill
jle .LBB4_34
# %bb.29: # %.lr.ph127
xorl %ebx, %ebx
xorl %ebp, %ebp
jmp .LBB4_30
.p2align 4, 0x90
.LBB4_33: # %._crit_edge125
# in Loop: Header=BB4_30 Depth=1
movl $10, %edi
callq putchar@PLT
incq %rbp
movq 16(%rsp), %r12 # 8-byte Reload
addl %r12d, %ebx
cmpq 32(%rsp), %rbp # 8-byte Folded Reload
movq 8(%rsp), %r13 # 8-byte Reload
je .LBB4_34
.LBB4_30: # =>This Loop Header: Depth=1
# Child Loop BB4_32 Depth 2
movl $.L.str.2, %edi
movl %ebp, %esi
xorl %eax, %eax
callq printf
testl %r13d, %r13d
jle .LBB4_33
# %bb.31: # %.lr.ph124
# in Loop: Header=BB4_30 Depth=1
movl %ebx, %eax
movq 24(%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax,4), %r12
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB4_32: # Parent Loop BB4_30 Depth=1
# => This Inner Loop Header: Depth=2
cvttss2si (%r12,%r13,4), %esi
movl $.L.str.3, %edi
xorl %eax, %eax
callq printf
incq %r13
cmpq %r13, %r14
jne .LBB4_32
jmp .LBB4_33
.LBB4_34: # %.preheader
testl %r12d, %r12d
jle .LBB4_40
# %bb.35: # %.lr.ph133
xorl %ebx, %ebx
xorl %ebp, %ebp
jmp .LBB4_36
.p2align 4, 0x90
.LBB4_39: # %._crit_edge131
# in Loop: Header=BB4_36 Depth=1
movl $10, %edi
callq putchar@PLT
incq %rbp
addl 16(%rsp), %ebx # 4-byte Folded Reload
cmpq 32(%rsp), %rbp # 8-byte Folded Reload
movq 8(%rsp), %r13 # 8-byte Reload
je .LBB4_40
.LBB4_36: # =>This Loop Header: Depth=1
# Child Loop BB4_38 Depth 2
movl $.L.str.2, %edi
movl %ebp, %esi
xorl %eax, %eax
callq printf
testl %r13d, %r13d
jle .LBB4_39
# %bb.37: # %.lr.ph130
# in Loop: Header=BB4_36 Depth=1
movl %ebx, %eax
movq 48(%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax,4), %r12
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB4_38: # Parent Loop BB4_36 Depth=1
# => This Inner Loop Header: Depth=2
cvttss2si (%r12,%r13,4), %esi
movl $.L.str.3, %edi
xorl %eax, %eax
callq printf
incq %r13
cmpq %r13, %r14
jne .LBB4_38
jmp .LBB4_39
.LBB4_40: # %._crit_edge134
movq %r15, %rdi
callq free
movq 56(%rsp), %rdi # 8-byte Reload
callq free
movq 24(%rsp), %rdi # 8-byte Reload
callq free
movq 104(%rsp), %rdi # 8-byte Reload
callq free
movq 72(%rsp), %rdi
callq hipFree
movq 64(%rsp), %rdi
callq hipFree
movq 40(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $232, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end4:
.size main, .Lfunc_end4-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z17unknown_algo_inp2PfS_iii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z17unknown_algo_inp1PfS_iii, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $0, 8(%rsp)
movl $1, (%rsp)
movl $c_inp, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movl $64000, %r9d # imm = 0xFA00
movq %rbx, %rdi
xorl %r8d, %r8d
callq __hipRegisterVar
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type c_inp,@object # @c_inp
.local c_inp
.comm c_inp,64000,16
.type _Z17unknown_algo_inp2PfS_iii,@object # @_Z17unknown_algo_inp2PfS_iii
.section .rodata,"a",@progbits
.globl _Z17unknown_algo_inp2PfS_iii
.p2align 3, 0x0
_Z17unknown_algo_inp2PfS_iii:
.quad _Z32__device_stub__unknown_algo_inp2PfS_iii
.size _Z17unknown_algo_inp2PfS_iii, 8
.type _Z17unknown_algo_inp1PfS_iii,@object # @_Z17unknown_algo_inp1PfS_iii
.globl _Z17unknown_algo_inp1PfS_iii
.p2align 3, 0x0
_Z17unknown_algo_inp1PfS_iii:
.quad _Z32__device_stub__unknown_algo_inp1PfS_iii
.size _Z17unknown_algo_inp1PfS_iii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "error count: %d\nGPU time for execution: %lf ms\nCPU time for execution: %lf ms\n"
.size .L.str, 79
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "gridx: %d gridy: %d\n"
.size .L.str.1, 21
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "%d. "
.size .L.str.2, 5
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "%d "
.size .L.str.3, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z17unknown_algo_inp2PfS_iii"
.size .L__unnamed_1, 29
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z17unknown_algo_inp1PfS_iii"
.size .L__unnamed_2, 29
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "c_inp"
.size .L__unnamed_3, 6
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z32__device_stub__unknown_algo_inp2PfS_iii
.addrsig_sym _Z32__device_stub__unknown_algo_inp1PfS_iii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym c_inp
.addrsig_sym _Z17unknown_algo_inp2PfS_iii
.addrsig_sym _Z17unknown_algo_inp1PfS_iii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void imagePaddingKernel(float3 *ptr, float3 *dst, int width, int height, int top, int bottom, int left, int right)
{
int x = threadIdx.x + blockIdx.x * blockDim.x;
int y = threadIdx.y + blockIdx.y * blockDim.y;
if(x < left || x >= (width - right) || y < top || y > (height - bottom)) {
return;
}
float3 color = ptr[(y - top) * (width - top - right) + (x - left)];
dst[y * width + x] = color;
} | code for sm_80
Function : _Z18imagePaddingKernelP6float3S0_iiiiii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ ULDC UR4, c[0x0][0x184] ; /* 0x0000610000047ab9 */
/* 0x000fe40000000800 */
/*0030*/ ULDC.64 UR6, c[0x0][0x170] ; /* 0x00005c0000067ab9 */
/* 0x000fe20000000a00 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e220000002100 */
/*0050*/ UIADD3 UR4, UR6, -UR4, URZ ; /* 0x8000000406047290 */
/* 0x000fc6000fffe03f */
/*0060*/ S2R R5, SR_CTAID.Y ; /* 0x0000000000057919 */
/* 0x000e680000002600 */
/*0070*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e620000002200 */
/*0080*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0090*/ ISETP.GE.AND P0, PT, R0.reuse, UR4, PT ; /* 0x0000000400007c0c */
/* 0x040fe2000bf06270 */
/*00a0*/ ULDC UR4, c[0x0][0x17c] ; /* 0x00005f0000047ab9 */
/* 0x000fe20000000800 */
/*00b0*/ IMAD R5, R5, c[0x0][0x4], R2 ; /* 0x0000010005057a24 */
/* 0x002fe400078e0202 */
/*00c0*/ ISETP.LT.OR P0, PT, R0, c[0x0][0x180], P0 ; /* 0x0000600000007a0c */
/* 0x000fe20000701670 */
/*00d0*/ UIADD3 UR4, UR7, -UR4, URZ ; /* 0x8000000407047290 */
/* 0x000fc6000fffe03f */
/*00e0*/ ISETP.LT.OR P0, PT, R5, c[0x0][0x178], P0 ; /* 0x00005e0005007a0c */
/* 0x000fc80000701670 */
/*00f0*/ ISETP.GT.OR P0, PT, R5, UR4, P0 ; /* 0x0000000405007c0c */
/* 0x000fda0008704670 */
/*0100*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0110*/ ULDC UR4, c[0x0][0x178] ; /* 0x00005e0000047ab9 */
/* 0x000fe20000000800 */
/*0120*/ HFMA2.MMA R4, -RZ, RZ, 0, 7.152557373046875e-07 ; /* 0x0000000cff047435 */
/* 0x000fe200000001ff */
/*0130*/ UIADD3 UR4, UR6, -UR4, URZ ; /* 0x8000000406047290 */
/* 0x000fe2000fffe03f */
/*0140*/ IADD3 R2, R5, -c[0x0][0x178], RZ ; /* 0x80005e0005027a10 */
/* 0x000fe20007ffe0ff */
/*0150*/ ULDC UR5, c[0x0][0x184] ; /* 0x0000610000057ab9 */
/* 0x000fe20000000800 */
/*0160*/ IADD3 R3, R0, -c[0x0][0x180], RZ ; /* 0x8000600000037a10 */
/* 0x000fe20007ffe0ff */
/*0170*/ UIADD3 UR4, UR4, -UR5, URZ ; /* 0x8000000504047290 */
/* 0x000fcc000fffe03f */
/*0180*/ IMAD R2, R2, UR4, R3 ; /* 0x0000000402027c24 */
/* 0x000fe2000f8e0203 */
/*0190*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*01a0*/ IMAD.WIDE R2, R2, R4, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0204 */
/*01b0*/ LDG.E R7, [R2.64] ; /* 0x0000000402077981 */
/* 0x000ea8000c1e1900 */
/*01c0*/ LDG.E R9, [R2.64+0x4] ; /* 0x0000040402097981 */
/* 0x000ee8000c1e1900 */
/*01d0*/ LDG.E R11, [R2.64+0x8] ; /* 0x00000804020b7981 */
/* 0x000f22000c1e1900 */
/*01e0*/ IMAD R5, R5, c[0x0][0x170], R0 ; /* 0x00005c0005057a24 */
/* 0x000fc800078e0200 */
/*01f0*/ IMAD.WIDE R4, R5, R4, c[0x0][0x168] ; /* 0x00005a0005047625 */
/* 0x000fca00078e0204 */
/*0200*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x004fe8000c101904 */
/*0210*/ STG.E [R4.64+0x4], R9 ; /* 0x0000040904007986 */
/* 0x008fe8000c101904 */
/*0220*/ STG.E [R4.64+0x8], R11 ; /* 0x0000080b04007986 */
/* 0x010fe2000c101904 */
/*0230*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0240*/ BRA 0x240; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void imagePaddingKernel(float3 *ptr, float3 *dst, int width, int height, int top, int bottom, int left, int right)
{
int x = threadIdx.x + blockIdx.x * blockDim.x;
int y = threadIdx.y + blockIdx.y * blockDim.y;
if(x < left || x >= (width - right) || y < top || y > (height - bottom)) {
return;
}
float3 color = ptr[(y - top) * (width - top - right) + (x - left)];
dst[y * width + x] = color;
} | .file "tmpxft_0009ba9b_00000000-6_imagePaddingKernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z53__device_stub__Z18imagePaddingKernelP6float3S0_iiiiiiP6float3S0_iiiiii
.type _Z53__device_stub__Z18imagePaddingKernelP6float3S0_iiiiiiP6float3S0_iiiiii, @function
_Z53__device_stub__Z18imagePaddingKernelP6float3S0_iiiiiiP6float3S0_iiiiii:
.LFB2051:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movl %r9d, (%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
movq %rsp, %rax
movq %rax, 136(%rsp)
leaq 192(%rsp), %rax
movq %rax, 144(%rsp)
leaq 200(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 200
pushq 40(%rsp)
.cfi_def_cfa_offset 208
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z18imagePaddingKernelP6float3S0_iiiiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z53__device_stub__Z18imagePaddingKernelP6float3S0_iiiiiiP6float3S0_iiiiii, .-_Z53__device_stub__Z18imagePaddingKernelP6float3S0_iiiiiiP6float3S0_iiiiii
.globl _Z18imagePaddingKernelP6float3S0_iiiiii
.type _Z18imagePaddingKernelP6float3S0_iiiiii, @function
_Z18imagePaddingKernelP6float3S0_iiiiii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 24
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
call _Z53__device_stub__Z18imagePaddingKernelP6float3S0_iiiiiiP6float3S0_iiiiii
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z18imagePaddingKernelP6float3S0_iiiiii, .-_Z18imagePaddingKernelP6float3S0_iiiiii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z18imagePaddingKernelP6float3S0_iiiiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z18imagePaddingKernelP6float3S0_iiiiii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void imagePaddingKernel(float3 *ptr, float3 *dst, int width, int height, int top, int bottom, int left, int right)
{
int x = threadIdx.x + blockIdx.x * blockDim.x;
int y = threadIdx.y + blockIdx.y * blockDim.y;
if(x < left || x >= (width - right) || y < top || y > (height - bottom)) {
return;
}
float3 color = ptr[(y - top) * (width - top - right) + (x - left)];
dst[y * width + x] = color;
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void imagePaddingKernel(float3 *ptr, float3 *dst, int width, int height, int top, int bottom, int left, int right)
{
int x = threadIdx.x + blockIdx.x * blockDim.x;
int y = threadIdx.y + blockIdx.y * blockDim.y;
if(x < left || x >= (width - right) || y < top || y > (height - bottom)) {
return;
}
float3 color = ptr[(y - top) * (width - top - right) + (x - left)];
dst[y * width + x] = color;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void imagePaddingKernel(float3 *ptr, float3 *dst, int width, int height, int top, int bottom, int left, int right)
{
int x = threadIdx.x + blockIdx.x * blockDim.x;
int y = threadIdx.y + blockIdx.y * blockDim.y;
if(x < left || x >= (width - right) || y < top || y > (height - bottom)) {
return;
}
float3 color = ptr[(y - top) * (width - top - right) + (x - left)];
dst[y * width + x] = color;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z18imagePaddingKernelP15HIP_vector_typeIfLj3EES1_iiiiii
.globl _Z18imagePaddingKernelP15HIP_vector_typeIfLj3EES1_iiiiii
.p2align 8
.type _Z18imagePaddingKernelP15HIP_vector_typeIfLj3EES1_iiiiii,@function
_Z18imagePaddingKernelP15HIP_vector_typeIfLj3EES1_iiiiii:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x34
s_load_b128 s[8:11], s[0:1], 0x10
s_load_b64 s[6:7], s[0:1], 0x20
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_lshr_b32 s2, s2, 16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[0:1], null, s14, s3, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s2, v[3:4]
s_sub_i32 s3, s8, s7
s_sub_i32 s4, s9, s11
v_cmp_le_i32_e32 vcc_lo, s6, v0
v_cmp_gt_i32_e64 s3, s3, v0
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cmp_le_i32_e64 s2, s10, v1
v_cmp_ge_i32_e64 s4, s4, v1
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(VALU_DEP_3) | instid1(SALU_CYCLE_1)
s_and_b32 s2, s2, s3
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
s_and_b32 s2, s2, s4
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_2
s_load_b128 s[0:3], s[0:1], 0x0
v_subrev_nc_u32_e32 v5, s10, v1
v_subrev_nc_u32_e32 v2, s6, v0
s_add_i32 s4, s10, s7
s_delay_alu instid0(SALU_CYCLE_1)
s_sub_i32 s4, s8, s4
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[3:4], null, v5, s4, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_mad_i64_i32 v[4:5], null, v3, 12, s[0:1]
global_load_b96 v[2:4], v[4:5], off
v_mad_u64_u32 v[5:6], null, v1, s8, v[0:1]
v_mad_i64_i32 v[0:1], null, v5, 12, s[2:3]
s_waitcnt vmcnt(0)
global_store_b96 v[0:1], v[2:4], off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z18imagePaddingKernelP15HIP_vector_typeIfLj3EES1_iiiiii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z18imagePaddingKernelP15HIP_vector_typeIfLj3EES1_iiiiii, .Lfunc_end0-_Z18imagePaddingKernelP15HIP_vector_typeIfLj3EES1_iiiiii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 36
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z18imagePaddingKernelP15HIP_vector_typeIfLj3EES1_iiiiii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z18imagePaddingKernelP15HIP_vector_typeIfLj3EES1_iiiiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void imagePaddingKernel(float3 *ptr, float3 *dst, int width, int height, int top, int bottom, int left, int right)
{
int x = threadIdx.x + blockIdx.x * blockDim.x;
int y = threadIdx.y + blockIdx.y * blockDim.y;
if(x < left || x >= (width - right) || y < top || y > (height - bottom)) {
return;
}
float3 color = ptr[(y - top) * (width - top - right) + (x - left)];
dst[y * width + x] = color;
} | .text
.file "imagePaddingKernel.hip"
.globl _Z33__device_stub__imagePaddingKernelP15HIP_vector_typeIfLj3EES1_iiiiii # -- Begin function _Z33__device_stub__imagePaddingKernelP15HIP_vector_typeIfLj3EES1_iiiiii
.p2align 4, 0x90
.type _Z33__device_stub__imagePaddingKernelP15HIP_vector_typeIfLj3EES1_iiiiii,@function
_Z33__device_stub__imagePaddingKernelP15HIP_vector_typeIfLj3EES1_iiiiii: # @_Z33__device_stub__imagePaddingKernelP15HIP_vector_typeIfLj3EES1_iiiiii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movl %r9d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
leaq 160(%rsp), %rax
movq %rax, 128(%rsp)
leaq 168(%rsp), %rax
movq %rax, 136(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z18imagePaddingKernelP15HIP_vector_typeIfLj3EES1_iiiiii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z33__device_stub__imagePaddingKernelP15HIP_vector_typeIfLj3EES1_iiiiii, .Lfunc_end0-_Z33__device_stub__imagePaddingKernelP15HIP_vector_typeIfLj3EES1_iiiiii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z18imagePaddingKernelP15HIP_vector_typeIfLj3EES1_iiiiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z18imagePaddingKernelP15HIP_vector_typeIfLj3EES1_iiiiii,@object # @_Z18imagePaddingKernelP15HIP_vector_typeIfLj3EES1_iiiiii
.section .rodata,"a",@progbits
.globl _Z18imagePaddingKernelP15HIP_vector_typeIfLj3EES1_iiiiii
.p2align 3, 0x0
_Z18imagePaddingKernelP15HIP_vector_typeIfLj3EES1_iiiiii:
.quad _Z33__device_stub__imagePaddingKernelP15HIP_vector_typeIfLj3EES1_iiiiii
.size _Z18imagePaddingKernelP15HIP_vector_typeIfLj3EES1_iiiiii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z18imagePaddingKernelP15HIP_vector_typeIfLj3EES1_iiiiii"
.size .L__unnamed_1, 57
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z33__device_stub__imagePaddingKernelP15HIP_vector_typeIfLj3EES1_iiiiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z18imagePaddingKernelP15HIP_vector_typeIfLj3EES1_iiiiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z18imagePaddingKernelP6float3S0_iiiiii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ ULDC UR4, c[0x0][0x184] ; /* 0x0000610000047ab9 */
/* 0x000fe40000000800 */
/*0030*/ ULDC.64 UR6, c[0x0][0x170] ; /* 0x00005c0000067ab9 */
/* 0x000fe20000000a00 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e220000002100 */
/*0050*/ UIADD3 UR4, UR6, -UR4, URZ ; /* 0x8000000406047290 */
/* 0x000fc6000fffe03f */
/*0060*/ S2R R5, SR_CTAID.Y ; /* 0x0000000000057919 */
/* 0x000e680000002600 */
/*0070*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e620000002200 */
/*0080*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0090*/ ISETP.GE.AND P0, PT, R0.reuse, UR4, PT ; /* 0x0000000400007c0c */
/* 0x040fe2000bf06270 */
/*00a0*/ ULDC UR4, c[0x0][0x17c] ; /* 0x00005f0000047ab9 */
/* 0x000fe20000000800 */
/*00b0*/ IMAD R5, R5, c[0x0][0x4], R2 ; /* 0x0000010005057a24 */
/* 0x002fe400078e0202 */
/*00c0*/ ISETP.LT.OR P0, PT, R0, c[0x0][0x180], P0 ; /* 0x0000600000007a0c */
/* 0x000fe20000701670 */
/*00d0*/ UIADD3 UR4, UR7, -UR4, URZ ; /* 0x8000000407047290 */
/* 0x000fc6000fffe03f */
/*00e0*/ ISETP.LT.OR P0, PT, R5, c[0x0][0x178], P0 ; /* 0x00005e0005007a0c */
/* 0x000fc80000701670 */
/*00f0*/ ISETP.GT.OR P0, PT, R5, UR4, P0 ; /* 0x0000000405007c0c */
/* 0x000fda0008704670 */
/*0100*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0110*/ ULDC UR4, c[0x0][0x178] ; /* 0x00005e0000047ab9 */
/* 0x000fe20000000800 */
/*0120*/ HFMA2.MMA R4, -RZ, RZ, 0, 7.152557373046875e-07 ; /* 0x0000000cff047435 */
/* 0x000fe200000001ff */
/*0130*/ UIADD3 UR4, UR6, -UR4, URZ ; /* 0x8000000406047290 */
/* 0x000fe2000fffe03f */
/*0140*/ IADD3 R2, R5, -c[0x0][0x178], RZ ; /* 0x80005e0005027a10 */
/* 0x000fe20007ffe0ff */
/*0150*/ ULDC UR5, c[0x0][0x184] ; /* 0x0000610000057ab9 */
/* 0x000fe20000000800 */
/*0160*/ IADD3 R3, R0, -c[0x0][0x180], RZ ; /* 0x8000600000037a10 */
/* 0x000fe20007ffe0ff */
/*0170*/ UIADD3 UR4, UR4, -UR5, URZ ; /* 0x8000000504047290 */
/* 0x000fcc000fffe03f */
/*0180*/ IMAD R2, R2, UR4, R3 ; /* 0x0000000402027c24 */
/* 0x000fe2000f8e0203 */
/*0190*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*01a0*/ IMAD.WIDE R2, R2, R4, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0204 */
/*01b0*/ LDG.E R7, [R2.64] ; /* 0x0000000402077981 */
/* 0x000ea8000c1e1900 */
/*01c0*/ LDG.E R9, [R2.64+0x4] ; /* 0x0000040402097981 */
/* 0x000ee8000c1e1900 */
/*01d0*/ LDG.E R11, [R2.64+0x8] ; /* 0x00000804020b7981 */
/* 0x000f22000c1e1900 */
/*01e0*/ IMAD R5, R5, c[0x0][0x170], R0 ; /* 0x00005c0005057a24 */
/* 0x000fc800078e0200 */
/*01f0*/ IMAD.WIDE R4, R5, R4, c[0x0][0x168] ; /* 0x00005a0005047625 */
/* 0x000fca00078e0204 */
/*0200*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x004fe8000c101904 */
/*0210*/ STG.E [R4.64+0x4], R9 ; /* 0x0000040904007986 */
/* 0x008fe8000c101904 */
/*0220*/ STG.E [R4.64+0x8], R11 ; /* 0x0000080b04007986 */
/* 0x010fe2000c101904 */
/*0230*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0240*/ BRA 0x240; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z18imagePaddingKernelP15HIP_vector_typeIfLj3EES1_iiiiii
.globl _Z18imagePaddingKernelP15HIP_vector_typeIfLj3EES1_iiiiii
.p2align 8
.type _Z18imagePaddingKernelP15HIP_vector_typeIfLj3EES1_iiiiii,@function
_Z18imagePaddingKernelP15HIP_vector_typeIfLj3EES1_iiiiii:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x34
s_load_b128 s[8:11], s[0:1], 0x10
s_load_b64 s[6:7], s[0:1], 0x20
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_lshr_b32 s2, s2, 16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[0:1], null, s14, s3, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s2, v[3:4]
s_sub_i32 s3, s8, s7
s_sub_i32 s4, s9, s11
v_cmp_le_i32_e32 vcc_lo, s6, v0
v_cmp_gt_i32_e64 s3, s3, v0
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cmp_le_i32_e64 s2, s10, v1
v_cmp_ge_i32_e64 s4, s4, v1
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(VALU_DEP_3) | instid1(SALU_CYCLE_1)
s_and_b32 s2, s2, s3
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
s_and_b32 s2, s2, s4
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_2
s_load_b128 s[0:3], s[0:1], 0x0
v_subrev_nc_u32_e32 v5, s10, v1
v_subrev_nc_u32_e32 v2, s6, v0
s_add_i32 s4, s10, s7
s_delay_alu instid0(SALU_CYCLE_1)
s_sub_i32 s4, s8, s4
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[3:4], null, v5, s4, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_mad_i64_i32 v[4:5], null, v3, 12, s[0:1]
global_load_b96 v[2:4], v[4:5], off
v_mad_u64_u32 v[5:6], null, v1, s8, v[0:1]
v_mad_i64_i32 v[0:1], null, v5, 12, s[2:3]
s_waitcnt vmcnt(0)
global_store_b96 v[0:1], v[2:4], off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z18imagePaddingKernelP15HIP_vector_typeIfLj3EES1_iiiiii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z18imagePaddingKernelP15HIP_vector_typeIfLj3EES1_iiiiii, .Lfunc_end0-_Z18imagePaddingKernelP15HIP_vector_typeIfLj3EES1_iiiiii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 36
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z18imagePaddingKernelP15HIP_vector_typeIfLj3EES1_iiiiii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z18imagePaddingKernelP15HIP_vector_typeIfLj3EES1_iiiiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0009ba9b_00000000-6_imagePaddingKernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z53__device_stub__Z18imagePaddingKernelP6float3S0_iiiiiiP6float3S0_iiiiii
.type _Z53__device_stub__Z18imagePaddingKernelP6float3S0_iiiiiiP6float3S0_iiiiii, @function
_Z53__device_stub__Z18imagePaddingKernelP6float3S0_iiiiiiP6float3S0_iiiiii:
.LFB2051:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movl %r9d, (%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
movq %rsp, %rax
movq %rax, 136(%rsp)
leaq 192(%rsp), %rax
movq %rax, 144(%rsp)
leaq 200(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 200
pushq 40(%rsp)
.cfi_def_cfa_offset 208
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z18imagePaddingKernelP6float3S0_iiiiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z53__device_stub__Z18imagePaddingKernelP6float3S0_iiiiiiP6float3S0_iiiiii, .-_Z53__device_stub__Z18imagePaddingKernelP6float3S0_iiiiiiP6float3S0_iiiiii
.globl _Z18imagePaddingKernelP6float3S0_iiiiii
.type _Z18imagePaddingKernelP6float3S0_iiiiii, @function
_Z18imagePaddingKernelP6float3S0_iiiiii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 24
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
call _Z53__device_stub__Z18imagePaddingKernelP6float3S0_iiiiiiP6float3S0_iiiiii
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z18imagePaddingKernelP6float3S0_iiiiii, .-_Z18imagePaddingKernelP6float3S0_iiiiii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z18imagePaddingKernelP6float3S0_iiiiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z18imagePaddingKernelP6float3S0_iiiiii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "imagePaddingKernel.hip"
.globl _Z33__device_stub__imagePaddingKernelP15HIP_vector_typeIfLj3EES1_iiiiii # -- Begin function _Z33__device_stub__imagePaddingKernelP15HIP_vector_typeIfLj3EES1_iiiiii
.p2align 4, 0x90
.type _Z33__device_stub__imagePaddingKernelP15HIP_vector_typeIfLj3EES1_iiiiii,@function
_Z33__device_stub__imagePaddingKernelP15HIP_vector_typeIfLj3EES1_iiiiii: # @_Z33__device_stub__imagePaddingKernelP15HIP_vector_typeIfLj3EES1_iiiiii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movl %r9d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
leaq 160(%rsp), %rax
movq %rax, 128(%rsp)
leaq 168(%rsp), %rax
movq %rax, 136(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z18imagePaddingKernelP15HIP_vector_typeIfLj3EES1_iiiiii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z33__device_stub__imagePaddingKernelP15HIP_vector_typeIfLj3EES1_iiiiii, .Lfunc_end0-_Z33__device_stub__imagePaddingKernelP15HIP_vector_typeIfLj3EES1_iiiiii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z18imagePaddingKernelP15HIP_vector_typeIfLj3EES1_iiiiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z18imagePaddingKernelP15HIP_vector_typeIfLj3EES1_iiiiii,@object # @_Z18imagePaddingKernelP15HIP_vector_typeIfLj3EES1_iiiiii
.section .rodata,"a",@progbits
.globl _Z18imagePaddingKernelP15HIP_vector_typeIfLj3EES1_iiiiii
.p2align 3, 0x0
_Z18imagePaddingKernelP15HIP_vector_typeIfLj3EES1_iiiiii:
.quad _Z33__device_stub__imagePaddingKernelP15HIP_vector_typeIfLj3EES1_iiiiii
.size _Z18imagePaddingKernelP15HIP_vector_typeIfLj3EES1_iiiiii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z18imagePaddingKernelP15HIP_vector_typeIfLj3EES1_iiiiii"
.size .L__unnamed_1, 57
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z33__device_stub__imagePaddingKernelP15HIP_vector_typeIfLj3EES1_iiiiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z18imagePaddingKernelP15HIP_vector_typeIfLj3EES1_iiiiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | //#include <cudaDefs.h>
//#include <time.h>
//#include <math.h>
//#include <random>
//
//using namespace std;
//
//
//cudaError_t error = cudaSuccess;
//cudaDeviceProp deviceProp = cudaDeviceProp();
//
//
//__constant__ __device__ int hodnota;
//
//typedef struct { int x; int y;} Point;
//__constant__ __device__ Point dPoint;
//__constant__ __device__ int dPole[5];
//
//
//
//void Cv1()
//{
// initializeCUDA(deviceProp);
//
//
// int hA = 100;
// int hB = 0;
// cudaMemcpyToSymbol(static_cast<const void*>(&hodnota), static_cast<const void*>(&hA), sizeof(hodnota));
// cudaMemcpyFromSymbol(static_cast<void*>(&hB), static_cast<const void*>(&hodnota), sizeof(hodnota));
//
// cout << hB << endl;
//
//
//
// Point hL;
// hL.x = 1;
// hL.y = 2;
//
// Point hL2;
// cudaMemcpyToSymbol(static_cast<const void*>(&dPoint), static_cast<const void*>(&hL), sizeof(hL));
// cudaMemcpyFromSymbol(static_cast<void*>(&hL2), static_cast<const void*>(&dPoint), sizeof(hL));
//
// cout << hL2.x << " " << hL2.y << endl;
//
// int Pole[5] = { 1,2,3,4,5 };
// int hPole2[5];
// cudaMemcpyToSymbol(dPole, Pole, sizeof(Pole));
// cudaMemcpyFromSymbol(hPole2, dPole, sizeof(Pole));
//
// cout << hPole2[0] << " " << hPole2[1];
//}
//
//
//int main(int argc, char *argv[])
//{
// initializeCUDA(deviceProp);
//
// //Cv1();
// Cv2();
// system("pause");
//
//} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | //#include <cudaDefs.h>
//#include <time.h>
//#include <math.h>
//#include <random>
//
//using namespace std;
//
//
//cudaError_t error = cudaSuccess;
//cudaDeviceProp deviceProp = cudaDeviceProp();
//
//
//__constant__ __device__ int hodnota;
//
//typedef struct { int x; int y;} Point;
//__constant__ __device__ Point dPoint;
//__constant__ __device__ int dPole[5];
//
//
//
//void Cv1()
//{
// initializeCUDA(deviceProp);
//
//
// int hA = 100;
// int hB = 0;
// cudaMemcpyToSymbol(static_cast<const void*>(&hodnota), static_cast<const void*>(&hA), sizeof(hodnota));
// cudaMemcpyFromSymbol(static_cast<void*>(&hB), static_cast<const void*>(&hodnota), sizeof(hodnota));
//
// cout << hB << endl;
//
//
//
// Point hL;
// hL.x = 1;
// hL.y = 2;
//
// Point hL2;
// cudaMemcpyToSymbol(static_cast<const void*>(&dPoint), static_cast<const void*>(&hL), sizeof(hL));
// cudaMemcpyFromSymbol(static_cast<void*>(&hL2), static_cast<const void*>(&dPoint), sizeof(hL));
//
// cout << hL2.x << " " << hL2.y << endl;
//
// int Pole[5] = { 1,2,3,4,5 };
// int hPole2[5];
// cudaMemcpyToSymbol(dPole, Pole, sizeof(Pole));
// cudaMemcpyFromSymbol(hPole2, dPole, sizeof(Pole));
//
// cout << hPole2[0] << " " << hPole2[1];
//}
//
//
//int main(int argc, char *argv[])
//{
// initializeCUDA(deviceProp);
//
// //Cv1();
// Cv2();
// system("pause");
//
//} | .file "tmpxft_000573f2_00000000-6_Runner.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | //#include <cudaDefs.h>
//#include <time.h>
//#include <math.h>
//#include <random>
//
//using namespace std;
//
//
//cudaError_t error = cudaSuccess;
//cudaDeviceProp deviceProp = cudaDeviceProp();
//
//
//__constant__ __device__ int hodnota;
//
//typedef struct { int x; int y;} Point;
//__constant__ __device__ Point dPoint;
//__constant__ __device__ int dPole[5];
//
//
//
//void Cv1()
//{
// initializeCUDA(deviceProp);
//
//
// int hA = 100;
// int hB = 0;
// cudaMemcpyToSymbol(static_cast<const void*>(&hodnota), static_cast<const void*>(&hA), sizeof(hodnota));
// cudaMemcpyFromSymbol(static_cast<void*>(&hB), static_cast<const void*>(&hodnota), sizeof(hodnota));
//
// cout << hB << endl;
//
//
//
// Point hL;
// hL.x = 1;
// hL.y = 2;
//
// Point hL2;
// cudaMemcpyToSymbol(static_cast<const void*>(&dPoint), static_cast<const void*>(&hL), sizeof(hL));
// cudaMemcpyFromSymbol(static_cast<void*>(&hL2), static_cast<const void*>(&dPoint), sizeof(hL));
//
// cout << hL2.x << " " << hL2.y << endl;
//
// int Pole[5] = { 1,2,3,4,5 };
// int hPole2[5];
// cudaMemcpyToSymbol(dPole, Pole, sizeof(Pole));
// cudaMemcpyFromSymbol(hPole2, dPole, sizeof(Pole));
//
// cout << hPole2[0] << " " << hPole2[1];
//}
//
//
//int main(int argc, char *argv[])
//{
// initializeCUDA(deviceProp);
//
// //Cv1();
// Cv2();
// system("pause");
//
//} | #include <hip/hip_runtime.h>
//#include <cudaDefs.h>
//#include <time.h>
//#include <math.h>
//#include <random>
//
//using namespace std;
//
//
//cudaError_t error = cudaSuccess;
//cudaDeviceProp deviceProp = cudaDeviceProp();
//
//
//__constant__ __device__ int hodnota;
//
//typedef struct { int x; int y;} Point;
//__constant__ __device__ Point dPoint;
//__constant__ __device__ int dPole[5];
//
//
//
//void Cv1()
//{
// initializeCUDA(deviceProp);
//
//
// int hA = 100;
// int hB = 0;
// cudaMemcpyToSymbol(static_cast<const void*>(&hodnota), static_cast<const void*>(&hA), sizeof(hodnota));
// cudaMemcpyFromSymbol(static_cast<void*>(&hB), static_cast<const void*>(&hodnota), sizeof(hodnota));
//
// cout << hB << endl;
//
//
//
// Point hL;
// hL.x = 1;
// hL.y = 2;
//
// Point hL2;
// cudaMemcpyToSymbol(static_cast<const void*>(&dPoint), static_cast<const void*>(&hL), sizeof(hL));
// cudaMemcpyFromSymbol(static_cast<void*>(&hL2), static_cast<const void*>(&dPoint), sizeof(hL));
//
// cout << hL2.x << " " << hL2.y << endl;
//
// int Pole[5] = { 1,2,3,4,5 };
// int hPole2[5];
// cudaMemcpyToSymbol(dPole, Pole, sizeof(Pole));
// cudaMemcpyFromSymbol(hPole2, dPole, sizeof(Pole));
//
// cout << hPole2[0] << " " << hPole2[1];
//}
//
//
//int main(int argc, char *argv[])
//{
// initializeCUDA(deviceProp);
//
// //Cv1();
// Cv2();
// system("pause");
//
//} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
//#include <cudaDefs.h>
//#include <time.h>
//#include <math.h>
//#include <random>
//
//using namespace std;
//
//
//cudaError_t error = cudaSuccess;
//cudaDeviceProp deviceProp = cudaDeviceProp();
//
//
//__constant__ __device__ int hodnota;
//
//typedef struct { int x; int y;} Point;
//__constant__ __device__ Point dPoint;
//__constant__ __device__ int dPole[5];
//
//
//
//void Cv1()
//{
// initializeCUDA(deviceProp);
//
//
// int hA = 100;
// int hB = 0;
// cudaMemcpyToSymbol(static_cast<const void*>(&hodnota), static_cast<const void*>(&hA), sizeof(hodnota));
// cudaMemcpyFromSymbol(static_cast<void*>(&hB), static_cast<const void*>(&hodnota), sizeof(hodnota));
//
// cout << hB << endl;
//
//
//
// Point hL;
// hL.x = 1;
// hL.y = 2;
//
// Point hL2;
// cudaMemcpyToSymbol(static_cast<const void*>(&dPoint), static_cast<const void*>(&hL), sizeof(hL));
// cudaMemcpyFromSymbol(static_cast<void*>(&hL2), static_cast<const void*>(&dPoint), sizeof(hL));
//
// cout << hL2.x << " " << hL2.y << endl;
//
// int Pole[5] = { 1,2,3,4,5 };
// int hPole2[5];
// cudaMemcpyToSymbol(dPole, Pole, sizeof(Pole));
// cudaMemcpyFromSymbol(hPole2, dPole, sizeof(Pole));
//
// cout << hPole2[0] << " " << hPole2[1];
//}
//
//
//int main(int argc, char *argv[])
//{
// initializeCUDA(deviceProp);
//
// //Cv1();
// Cv2();
// system("pause");
//
//} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
//#include <cudaDefs.h>
//#include <time.h>
//#include <math.h>
//#include <random>
//
//using namespace std;
//
//
//cudaError_t error = cudaSuccess;
//cudaDeviceProp deviceProp = cudaDeviceProp();
//
//
//__constant__ __device__ int hodnota;
//
//typedef struct { int x; int y;} Point;
//__constant__ __device__ Point dPoint;
//__constant__ __device__ int dPole[5];
//
//
//
//void Cv1()
//{
// initializeCUDA(deviceProp);
//
//
// int hA = 100;
// int hB = 0;
// cudaMemcpyToSymbol(static_cast<const void*>(&hodnota), static_cast<const void*>(&hA), sizeof(hodnota));
// cudaMemcpyFromSymbol(static_cast<void*>(&hB), static_cast<const void*>(&hodnota), sizeof(hodnota));
//
// cout << hB << endl;
//
//
//
// Point hL;
// hL.x = 1;
// hL.y = 2;
//
// Point hL2;
// cudaMemcpyToSymbol(static_cast<const void*>(&dPoint), static_cast<const void*>(&hL), sizeof(hL));
// cudaMemcpyFromSymbol(static_cast<void*>(&hL2), static_cast<const void*>(&dPoint), sizeof(hL));
//
// cout << hL2.x << " " << hL2.y << endl;
//
// int Pole[5] = { 1,2,3,4,5 };
// int hPole2[5];
// cudaMemcpyToSymbol(dPole, Pole, sizeof(Pole));
// cudaMemcpyFromSymbol(hPole2, dPole, sizeof(Pole));
//
// cout << hPole2[0] << " " << hPole2[1];
//}
//
//
//int main(int argc, char *argv[])
//{
// initializeCUDA(deviceProp);
//
// //Cv1();
// Cv2();
// system("pause");
//
//} | .text
.file "Runner.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000573f2_00000000-6_Runner.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "Runner.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ static void findRHS(double* cOld, double* cCurr, double* cHalf, double* cNonLinRHS, int nx)
{
// Matrix index
int globalIdx = blockDim.x * blockIdx.x + threadIdx.x;
int globalIdy = blockDim.y * blockIdx.y + threadIdx.y;
// Set index being computed
int index = globalIdy * nx + globalIdx;
// Set the RHS for inversion
cHalf[index] += - (2.0 / 3.0) * (cCurr[index] - cOld[index]) + cNonLinRHS[index];
// Set cOld to cCurr
cOld[index] = cCurr[index];
} | code for sm_80
Function : _Z7findRHSPdS_S_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R13, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff0d7435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e280000002100 */
/*0050*/ S2R R2, SR_CTAID.Y ; /* 0x0000000000027919 */
/* 0x000e680000002600 */
/*0060*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e620000002200 */
/*0070*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fc400078e0203 */
/*0080*/ IMAD R3, R2, c[0x0][0x4], R5 ; /* 0x0000010002037a24 */
/* 0x002fc800078e0205 */
/*0090*/ IMAD R0, R3, c[0x0][0x180], R0 ; /* 0x0000600003007a24 */
/* 0x000fc800078e0200 */
/*00a0*/ IMAD.WIDE R2, R0, R13, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x000fc800078e020d */
/*00b0*/ IMAD.WIDE R6, R0.reuse, R13.reuse, c[0x0][0x160] ; /* 0x0000580000067625 */
/* 0x0c0fe200078e020d */
/*00c0*/ LDG.E.64 R4, [R2.64] ; /* 0x0000000402047981 */
/* 0x000ea6000c1e1b00 */
/*00d0*/ IMAD.WIDE R10, R0.reuse, R13.reuse, c[0x0][0x178] ; /* 0x00005e00000a7625 */
/* 0x0c0fe200078e020d */
/*00e0*/ LDG.E.64 R8, [R6.64] ; /* 0x0000000406087981 */
/* 0x000ea6000c1e1b00 */
/*00f0*/ IMAD.WIDE R12, R0, R13, c[0x0][0x170] ; /* 0x00005c00000c7625 */
/* 0x000fe400078e020d */
/*0100*/ LDG.E.64 R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x000ee8000c1e1b00 */
/*0110*/ LDG.E.64 R14, [R12.64] ; /* 0x000000040c0e7981 */
/* 0x000f22000c1e1b00 */
/*0120*/ DADD R4, R4, -R8 ; /* 0x0000000004047229 */
/* 0x004ecc0000000808 */
/*0130*/ DFMA R4, R4, c[0x2][0x0], R10 ; /* 0x0080000004047a2b */
/* 0x008f0c000000000a */
/*0140*/ DADD R4, R4, R14 ; /* 0x0000000004047229 */
/* 0x010e0e000000000e */
/*0150*/ STG.E.64 [R12.64], R4 ; /* 0x000000040c007986 */
/* 0x001fe8000c101b04 */
/*0160*/ LDG.E.64 R8, [R2.64] ; /* 0x0000000402087981 */
/* 0x000ea8000c1e1b00 */
/*0170*/ STG.E.64 [R6.64], R8 ; /* 0x0000000806007986 */
/* 0x004fe2000c101b04 */
/*0180*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0190*/ BRA 0x190; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ static void findRHS(double* cOld, double* cCurr, double* cHalf, double* cNonLinRHS, int nx)
{
// Matrix index
int globalIdx = blockDim.x * blockIdx.x + threadIdx.x;
int globalIdy = blockDim.y * blockIdx.y + threadIdx.y;
// Set index being computed
int index = globalIdy * nx + globalIdx;
// Set the RHS for inversion
cHalf[index] += - (2.0 / 3.0) * (cCurr[index] - cOld[index]) + cNonLinRHS[index];
// Set cOld to cCurr
cOld[index] = cCurr[index];
} | .file "tmpxft_0019cd0b_00000000-6_findRHS.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.type _ZL7findRHSPdS_S_S_i, @function
_ZL7findRHSPdS_S_S_i:
.LFB2052:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
movq %rdi, 16(%rsp)
movq %rsi, 24(%rsp)
movq %rdx, 32(%rsp)
movq %rcx, 40(%rsp)
movl %r8d, 12(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 24(%rsp), %rax
movq %rax, 120(%rsp)
leaq 32(%rsp), %rax
movq %rax, 128(%rsp)
leaq 40(%rsp), %rax
movq %rax, 136(%rsp)
leaq 12(%rsp), %rax
movq %rax, 144(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 184
pushq 56(%rsp)
.cfi_def_cfa_offset 192
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _ZL7findRHSPdS_S_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2052:
.size _ZL7findRHSPdS_S_S_i, .-_ZL7findRHSPdS_S_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z7findRHSPdS_S_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _ZL7findRHSPdS_S_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ static void findRHS(double* cOld, double* cCurr, double* cHalf, double* cNonLinRHS, int nx)
{
// Matrix index
int globalIdx = blockDim.x * blockIdx.x + threadIdx.x;
int globalIdy = blockDim.y * blockIdx.y + threadIdx.y;
// Set index being computed
int index = globalIdy * nx + globalIdx;
// Set the RHS for inversion
cHalf[index] += - (2.0 / 3.0) * (cCurr[index] - cOld[index]) + cNonLinRHS[index];
// Set cOld to cCurr
cOld[index] = cCurr[index];
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ static void findRHS(double* cOld, double* cCurr, double* cHalf, double* cNonLinRHS, int nx)
{
// Matrix index
int globalIdx = blockDim.x * blockIdx.x + threadIdx.x;
int globalIdy = blockDim.y * blockIdx.y + threadIdx.y;
// Set index being computed
int index = globalIdy * nx + globalIdx;
// Set the RHS for inversion
cHalf[index] += - (2.0 / 3.0) * (cCurr[index] - cOld[index]) + cNonLinRHS[index];
// Set cOld to cCurr
cOld[index] = cCurr[index];
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ static void findRHS(double* cOld, double* cCurr, double* cHalf, double* cNonLinRHS, int nx)
{
// Matrix index
int globalIdx = blockDim.x * blockIdx.x + threadIdx.x;
int globalIdy = blockDim.y * blockIdx.y + threadIdx.y;
// Set index being computed
int index = globalIdy * nx + globalIdx;
// Set the RHS for inversion
cHalf[index] += - (2.0 / 3.0) * (cCurr[index] - cOld[index]) + cNonLinRHS[index];
// Set cOld to cCurr
cOld[index] = cCurr[index];
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.section .text._ZL7findRHSPdS_S_S_i,"axG",@progbits,_ZL7findRHSPdS_S_S_i,comdat
.globl _ZL7findRHSPdS_S_S_i
.p2align 8
.type _ZL7findRHSPdS_S_S_i,@function
_ZL7findRHSPdS_S_S_i:
s_clause 0x1
s_load_b32 s8, s[0:1], 0x34
s_load_b32 s2, s[0:1], 0x20
v_bfe_u32 v1, v0, 10, 10
v_and_b32_e32 v0, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s3, s8, 16
s_and_b32 s8, s8, 0xffff
v_mad_u64_u32 v[2:3], null, s15, s3, v[1:2]
s_mul_i32 s14, s14, s8
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mul_lo_u32 v1, v2, s2
s_load_b256 s[0:7], s[0:1], 0x0
v_add3_u32 v0, s14, v0, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[0:1], 3, v[0:1]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v1, vcc_lo
v_add_co_u32 v10, vcc_lo, s6, v0
global_load_b64 v[6:7], v[2:3], off
global_load_b64 v[8:9], v[4:5], off
v_add_co_ci_u32_e32 v11, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
global_load_b64 v[10:11], v[10:11], off
s_mov_b32 s1, 0xbfe55555
s_mov_b32 s0, 0x55555555
global_load_b64 v[12:13], v[0:1], off
s_waitcnt vmcnt(2)
v_add_f64 v[6:7], v[6:7], -v[8:9]
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fma_f64 v[6:7], v[6:7], s[0:1], v[10:11]
s_waitcnt vmcnt(0)
v_add_f64 v[6:7], v[12:13], v[6:7]
global_store_b64 v[0:1], v[6:7], off
global_load_b64 v[0:1], v[2:3], off
s_waitcnt vmcnt(0)
global_store_b64 v[4:5], v[0:1], off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _ZL7findRHSPdS_S_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 14
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.section .text._ZL7findRHSPdS_S_S_i,"axG",@progbits,_ZL7findRHSPdS_S_S_i,comdat
.Lfunc_end0:
.size _ZL7findRHSPdS_S_S_i, .Lfunc_end0-_ZL7findRHSPdS_S_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _ZL7findRHSPdS_S_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _ZL7findRHSPdS_S_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 14
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ static void findRHS(double* cOld, double* cCurr, double* cHalf, double* cNonLinRHS, int nx)
{
// Matrix index
int globalIdx = blockDim.x * blockIdx.x + threadIdx.x;
int globalIdy = blockDim.y * blockIdx.y + threadIdx.y;
// Set index being computed
int index = globalIdy * nx + globalIdx;
// Set the RHS for inversion
cHalf[index] += - (2.0 / 3.0) * (cCurr[index] - cOld[index]) + cNonLinRHS[index];
// Set cOld to cCurr
cOld[index] = cCurr[index];
} | .text
.file "findRHS.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z7findRHSPdS_S_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R13, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff0d7435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e280000002100 */
/*0050*/ S2R R2, SR_CTAID.Y ; /* 0x0000000000027919 */
/* 0x000e680000002600 */
/*0060*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e620000002200 */
/*0070*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fc400078e0203 */
/*0080*/ IMAD R3, R2, c[0x0][0x4], R5 ; /* 0x0000010002037a24 */
/* 0x002fc800078e0205 */
/*0090*/ IMAD R0, R3, c[0x0][0x180], R0 ; /* 0x0000600003007a24 */
/* 0x000fc800078e0200 */
/*00a0*/ IMAD.WIDE R2, R0, R13, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x000fc800078e020d */
/*00b0*/ IMAD.WIDE R6, R0.reuse, R13.reuse, c[0x0][0x160] ; /* 0x0000580000067625 */
/* 0x0c0fe200078e020d */
/*00c0*/ LDG.E.64 R4, [R2.64] ; /* 0x0000000402047981 */
/* 0x000ea6000c1e1b00 */
/*00d0*/ IMAD.WIDE R10, R0.reuse, R13.reuse, c[0x0][0x178] ; /* 0x00005e00000a7625 */
/* 0x0c0fe200078e020d */
/*00e0*/ LDG.E.64 R8, [R6.64] ; /* 0x0000000406087981 */
/* 0x000ea6000c1e1b00 */
/*00f0*/ IMAD.WIDE R12, R0, R13, c[0x0][0x170] ; /* 0x00005c00000c7625 */
/* 0x000fe400078e020d */
/*0100*/ LDG.E.64 R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x000ee8000c1e1b00 */
/*0110*/ LDG.E.64 R14, [R12.64] ; /* 0x000000040c0e7981 */
/* 0x000f22000c1e1b00 */
/*0120*/ DADD R4, R4, -R8 ; /* 0x0000000004047229 */
/* 0x004ecc0000000808 */
/*0130*/ DFMA R4, R4, c[0x2][0x0], R10 ; /* 0x0080000004047a2b */
/* 0x008f0c000000000a */
/*0140*/ DADD R4, R4, R14 ; /* 0x0000000004047229 */
/* 0x010e0e000000000e */
/*0150*/ STG.E.64 [R12.64], R4 ; /* 0x000000040c007986 */
/* 0x001fe8000c101b04 */
/*0160*/ LDG.E.64 R8, [R2.64] ; /* 0x0000000402087981 */
/* 0x000ea8000c1e1b00 */
/*0170*/ STG.E.64 [R6.64], R8 ; /* 0x0000000806007986 */
/* 0x004fe2000c101b04 */
/*0180*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0190*/ BRA 0x190; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.section .text._ZL7findRHSPdS_S_S_i,"axG",@progbits,_ZL7findRHSPdS_S_S_i,comdat
.globl _ZL7findRHSPdS_S_S_i
.p2align 8
.type _ZL7findRHSPdS_S_S_i,@function
_ZL7findRHSPdS_S_S_i:
s_clause 0x1
s_load_b32 s8, s[0:1], 0x34
s_load_b32 s2, s[0:1], 0x20
v_bfe_u32 v1, v0, 10, 10
v_and_b32_e32 v0, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s3, s8, 16
s_and_b32 s8, s8, 0xffff
v_mad_u64_u32 v[2:3], null, s15, s3, v[1:2]
s_mul_i32 s14, s14, s8
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mul_lo_u32 v1, v2, s2
s_load_b256 s[0:7], s[0:1], 0x0
v_add3_u32 v0, s14, v0, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[0:1], 3, v[0:1]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v1, vcc_lo
v_add_co_u32 v10, vcc_lo, s6, v0
global_load_b64 v[6:7], v[2:3], off
global_load_b64 v[8:9], v[4:5], off
v_add_co_ci_u32_e32 v11, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
global_load_b64 v[10:11], v[10:11], off
s_mov_b32 s1, 0xbfe55555
s_mov_b32 s0, 0x55555555
global_load_b64 v[12:13], v[0:1], off
s_waitcnt vmcnt(2)
v_add_f64 v[6:7], v[6:7], -v[8:9]
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fma_f64 v[6:7], v[6:7], s[0:1], v[10:11]
s_waitcnt vmcnt(0)
v_add_f64 v[6:7], v[12:13], v[6:7]
global_store_b64 v[0:1], v[6:7], off
global_load_b64 v[0:1], v[2:3], off
s_waitcnt vmcnt(0)
global_store_b64 v[4:5], v[0:1], off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _ZL7findRHSPdS_S_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 14
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.section .text._ZL7findRHSPdS_S_S_i,"axG",@progbits,_ZL7findRHSPdS_S_S_i,comdat
.Lfunc_end0:
.size _ZL7findRHSPdS_S_S_i, .Lfunc_end0-_ZL7findRHSPdS_S_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _ZL7findRHSPdS_S_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _ZL7findRHSPdS_S_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 14
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0019cd0b_00000000-6_findRHS.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.type _ZL7findRHSPdS_S_S_i, @function
_ZL7findRHSPdS_S_S_i:
.LFB2052:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
movq %rdi, 16(%rsp)
movq %rsi, 24(%rsp)
movq %rdx, 32(%rsp)
movq %rcx, 40(%rsp)
movl %r8d, 12(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 24(%rsp), %rax
movq %rax, 120(%rsp)
leaq 32(%rsp), %rax
movq %rax, 128(%rsp)
leaq 40(%rsp), %rax
movq %rax, 136(%rsp)
leaq 12(%rsp), %rax
movq %rax, 144(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 184
pushq 56(%rsp)
.cfi_def_cfa_offset 192
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _ZL7findRHSPdS_S_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2052:
.size _ZL7findRHSPdS_S_S_i, .-_ZL7findRHSPdS_S_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z7findRHSPdS_S_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _ZL7findRHSPdS_S_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "findRHS.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void ConstantB(bool * x, bool value, size_t idx, size_t N)
{
for (int i = blockIdx.x * blockDim.x + threadIdx.x; i < N; i += blockDim.x * gridDim.x)
{
x[(idx)*N + i] = value;
}
return;
} | code for sm_80
Function : _Z9ConstantBPbbmm
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x178], PT ; /* 0x00005e0000007a0c */
/* 0x000fe40003f06070 */
/*0050*/ SHF.R.S32.HI R2, RZ, 0x1f, R0 ; /* 0x0000001fff027819 */
/* 0x000fc80000011400 */
/*0060*/ ISETP.GE.U32.AND.EX P0, PT, R2, c[0x0][0x17c], PT, P0 ; /* 0x00005f0002007a0c */
/* 0x000fda0003f06100 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ LDC.S8 R5, c[0x0][0x168] ; /* 0x00005a00ff057b82 */
/* 0x000e220000000200 */
/*0090*/ IMAD.MOV.U32 R11, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff0b7624 */
/* 0x000fe200078e00ff */
/*00a0*/ MOV R4, c[0x0][0x178] ; /* 0x00005e0000047a02 */
/* 0x000fe20000000f00 */
/*00b0*/ IMAD.MOV.U32 R7, RZ, RZ, R2 ; /* 0x000000ffff077224 */
/* 0x000fe200078e0002 */
/*00c0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00d0*/ IMAD R3, R11, c[0x0][0x17c], RZ ; /* 0x00005f000b037a24 */
/* 0x000fe400078e02ff */
/*00e0*/ IMAD.MOV.U32 R13, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff0d7624 */
/* 0x000fe400078e00ff */
/*00f0*/ IMAD R9, R4, c[0x0][0x174], R3 ; /* 0x00005d0004097a24 */
/* 0x000fe200078e0203 */
/*0100*/ MOV R4, R0 ; /* 0x0000000000047202 */
/* 0x000fc40000000f00 */
/*0110*/ PRMT R5, R5, 0x7710, RZ ; /* 0x0000771005057816 */
/* 0x001fe400000000ff */
/*0120*/ MOV R2, R4 ; /* 0x0000000400027202 */
/* 0x000fe20000000f00 */
/*0130*/ IMAD.MOV.U32 R3, RZ, RZ, R7 ; /* 0x000000ffff037224 */
/* 0x000fe400078e0007 */
/*0140*/ IMAD R4, R13, c[0x0][0xc], R0 ; /* 0x000003000d047a24 */
/* 0x000fe400078e0200 */
/*0150*/ IMAD.WIDE.U32 R2, R11, c[0x0][0x178], R2 ; /* 0x00005e000b027a25 */
/* 0x000fc600078e0002 */
/*0160*/ SHF.R.S32.HI R7, RZ, 0x1f, R4 ; /* 0x0000001fff077819 */
/* 0x000fe40000011404 */
/*0170*/ IADD3 R2, P0, R2, c[0x0][0x160], RZ ; /* 0x0000580002027a10 */
/* 0x000fe40007f1e0ff */
/*0180*/ MOV R0, R4 ; /* 0x0000000400007202 */
/* 0x000fe40000000f00 */
/*0190*/ IADD3.X R3, R3, c[0x0][0x164], R9, P0, !PT ; /* 0x0000590003037a10 */
/* 0x000fe400007fe409 */
/*01a0*/ ISETP.GE.U32.AND P0, PT, R4, c[0x0][0x178], PT ; /* 0x00005e0004007a0c */
/* 0x000fc60003f06070 */
/*01b0*/ STG.E.U8 [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x0001e2000c101104 */
/*01c0*/ ISETP.GE.U32.AND.EX P0, PT, R7, c[0x0][0x17c], PT, P0 ; /* 0x00005f0007007a0c */
/* 0x000fda0003f06100 */
/*01d0*/ @!P0 BRA 0x120 ; /* 0xffffff4000008947 */
/* 0x001fea000383ffff */
/*01e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01f0*/ BRA 0x1f0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void ConstantB(bool * x, bool value, size_t idx, size_t N)
{
for (int i = blockIdx.x * blockDim.x + threadIdx.x; i < N; i += blockDim.x * gridDim.x)
{
x[(idx)*N + i] = value;
}
return;
} | .file "tmpxft_000ac6f2_00000000-6_ConstantB.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z31__device_stub__Z9ConstantBPbbmmPbbmm
.type _Z31__device_stub__Z9ConstantBPbbmmPbbmm, @function
_Z31__device_stub__Z9ConstantBPbbmmPbbmm:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rdx, 8(%rsp)
movq %rcx, (%rsp)
movb %sil, 20(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9ConstantBPbbmm(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z31__device_stub__Z9ConstantBPbbmmPbbmm, .-_Z31__device_stub__Z9ConstantBPbbmmPbbmm
.globl _Z9ConstantBPbbmm
.type _Z9ConstantBPbbmm, @function
_Z9ConstantBPbbmm:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movzbl %sil, %esi
call _Z31__device_stub__Z9ConstantBPbbmmPbbmm
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z9ConstantBPbbmm, .-_Z9ConstantBPbbmm
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z9ConstantBPbbmm"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z9ConstantBPbbmm(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void ConstantB(bool * x, bool value, size_t idx, size_t N)
{
for (int i = blockIdx.x * blockDim.x + threadIdx.x; i < N; i += blockDim.x * gridDim.x)
{
x[(idx)*N + i] = value;
}
return;
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void ConstantB(bool * x, bool value, size_t idx, size_t N)
{
for (int i = blockIdx.x * blockDim.x + threadIdx.x; i < N; i += blockDim.x * gridDim.x)
{
x[(idx)*N + i] = value;
}
return;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void ConstantB(bool * x, bool value, size_t idx, size_t N)
{
for (int i = blockIdx.x * blockDim.x + threadIdx.x; i < N; i += blockDim.x * gridDim.x)
{
x[(idx)*N + i] = value;
}
return;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9ConstantBPbbmm
.globl _Z9ConstantBPbbmm
.p2align 8
.type _Z9ConstantBPbbmm,@function
_Z9ConstantBPbbmm:
s_clause 0x1
s_load_b32 s6, s[0:1], 0x2c
s_load_b64 s[2:3], s[0:1], 0x18
s_add_u32 s4, s0, 32
s_addc_u32 s5, s1, 0
s_mov_b32 s7, exec_lo
s_waitcnt lgkmcnt(0)
s_and_b32 s6, s6, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s6, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_u64_e64 s[2:3], v[1:2]
s_cbranch_execz .LBB0_3
s_clause 0x1
s_load_b64 s[8:9], s[0:1], 0x10
s_load_b64 s[10:11], s[0:1], 0x0
s_load_b32 s5, s[4:5], 0x0
s_load_b32 s0, s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_mul_i32 s1, s2, s9
s_mul_hi_u32 s4, s2, s8
s_mul_i32 s7, s3, s8
s_add_i32 s1, s4, s1
s_mul_i32 s4, s2, s8
s_add_i32 s7, s1, s7
s_add_u32 s1, s10, s4
s_addc_u32 s4, s11, s7
s_add_i32 s15, s15, s5
s_mul_i32 s5, s5, s6
v_mad_u64_u32 v[3:4], null, s15, s6, v[0:1]
v_and_b32_e64 v0, s0, 1
s_mov_b32 s6, 0
.LBB0_2:
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_ashrrev_i32_e32 v4, 31, v3
v_add_co_u32 v5, vcc_lo, s1, v1
v_add_co_ci_u32_e32 v6, vcc_lo, s4, v2, vcc_lo
v_cmp_le_u64_e64 s0, s[2:3], v[3:4]
v_dual_mov_b32 v1, v3 :: v_dual_mov_b32 v2, v4
v_add_nc_u32_e32 v3, s5, v3
global_store_b8 v[5:6], v0, off
s_or_b32 s6, s0, s6
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s6
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9ConstantBPbbmm
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9ConstantBPbbmm, .Lfunc_end0-_Z9ConstantBPbbmm
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 1
.value_kind: by_value
- .offset: 16
.size: 8
.value_kind: by_value
- .offset: 24
.size: 8
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9ConstantBPbbmm
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9ConstantBPbbmm.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void ConstantB(bool * x, bool value, size_t idx, size_t N)
{
for (int i = blockIdx.x * blockDim.x + threadIdx.x; i < N; i += blockDim.x * gridDim.x)
{
x[(idx)*N + i] = value;
}
return;
} | .text
.file "ConstantB.hip"
.globl _Z24__device_stub__ConstantBPbbmm # -- Begin function _Z24__device_stub__ConstantBPbbmm
.p2align 4, 0x90
.type _Z24__device_stub__ConstantBPbbmm,@function
_Z24__device_stub__ConstantBPbbmm: # @_Z24__device_stub__ConstantBPbbmm
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movb %sil, 7(%rsp)
movq %rdx, 64(%rsp)
movq %rcx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 7(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 56(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9ConstantBPbbmm, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z24__device_stub__ConstantBPbbmm, .Lfunc_end0-_Z24__device_stub__ConstantBPbbmm
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9ConstantBPbbmm, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9ConstantBPbbmm,@object # @_Z9ConstantBPbbmm
.section .rodata,"a",@progbits
.globl _Z9ConstantBPbbmm
.p2align 3, 0x0
_Z9ConstantBPbbmm:
.quad _Z24__device_stub__ConstantBPbbmm
.size _Z9ConstantBPbbmm, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z9ConstantBPbbmm"
.size .L__unnamed_1, 18
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__ConstantBPbbmm
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9ConstantBPbbmm
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z9ConstantBPbbmm
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x178], PT ; /* 0x00005e0000007a0c */
/* 0x000fe40003f06070 */
/*0050*/ SHF.R.S32.HI R2, RZ, 0x1f, R0 ; /* 0x0000001fff027819 */
/* 0x000fc80000011400 */
/*0060*/ ISETP.GE.U32.AND.EX P0, PT, R2, c[0x0][0x17c], PT, P0 ; /* 0x00005f0002007a0c */
/* 0x000fda0003f06100 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ LDC.S8 R5, c[0x0][0x168] ; /* 0x00005a00ff057b82 */
/* 0x000e220000000200 */
/*0090*/ IMAD.MOV.U32 R11, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff0b7624 */
/* 0x000fe200078e00ff */
/*00a0*/ MOV R4, c[0x0][0x178] ; /* 0x00005e0000047a02 */
/* 0x000fe20000000f00 */
/*00b0*/ IMAD.MOV.U32 R7, RZ, RZ, R2 ; /* 0x000000ffff077224 */
/* 0x000fe200078e0002 */
/*00c0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00d0*/ IMAD R3, R11, c[0x0][0x17c], RZ ; /* 0x00005f000b037a24 */
/* 0x000fe400078e02ff */
/*00e0*/ IMAD.MOV.U32 R13, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff0d7624 */
/* 0x000fe400078e00ff */
/*00f0*/ IMAD R9, R4, c[0x0][0x174], R3 ; /* 0x00005d0004097a24 */
/* 0x000fe200078e0203 */
/*0100*/ MOV R4, R0 ; /* 0x0000000000047202 */
/* 0x000fc40000000f00 */
/*0110*/ PRMT R5, R5, 0x7710, RZ ; /* 0x0000771005057816 */
/* 0x001fe400000000ff */
/*0120*/ MOV R2, R4 ; /* 0x0000000400027202 */
/* 0x000fe20000000f00 */
/*0130*/ IMAD.MOV.U32 R3, RZ, RZ, R7 ; /* 0x000000ffff037224 */
/* 0x000fe400078e0007 */
/*0140*/ IMAD R4, R13, c[0x0][0xc], R0 ; /* 0x000003000d047a24 */
/* 0x000fe400078e0200 */
/*0150*/ IMAD.WIDE.U32 R2, R11, c[0x0][0x178], R2 ; /* 0x00005e000b027a25 */
/* 0x000fc600078e0002 */
/*0160*/ SHF.R.S32.HI R7, RZ, 0x1f, R4 ; /* 0x0000001fff077819 */
/* 0x000fe40000011404 */
/*0170*/ IADD3 R2, P0, R2, c[0x0][0x160], RZ ; /* 0x0000580002027a10 */
/* 0x000fe40007f1e0ff */
/*0180*/ MOV R0, R4 ; /* 0x0000000400007202 */
/* 0x000fe40000000f00 */
/*0190*/ IADD3.X R3, R3, c[0x0][0x164], R9, P0, !PT ; /* 0x0000590003037a10 */
/* 0x000fe400007fe409 */
/*01a0*/ ISETP.GE.U32.AND P0, PT, R4, c[0x0][0x178], PT ; /* 0x00005e0004007a0c */
/* 0x000fc60003f06070 */
/*01b0*/ STG.E.U8 [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x0001e2000c101104 */
/*01c0*/ ISETP.GE.U32.AND.EX P0, PT, R7, c[0x0][0x17c], PT, P0 ; /* 0x00005f0007007a0c */
/* 0x000fda0003f06100 */
/*01d0*/ @!P0 BRA 0x120 ; /* 0xffffff4000008947 */
/* 0x001fea000383ffff */
/*01e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01f0*/ BRA 0x1f0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9ConstantBPbbmm
.globl _Z9ConstantBPbbmm
.p2align 8
.type _Z9ConstantBPbbmm,@function
_Z9ConstantBPbbmm:
s_clause 0x1
s_load_b32 s6, s[0:1], 0x2c
s_load_b64 s[2:3], s[0:1], 0x18
s_add_u32 s4, s0, 32
s_addc_u32 s5, s1, 0
s_mov_b32 s7, exec_lo
s_waitcnt lgkmcnt(0)
s_and_b32 s6, s6, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s6, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_u64_e64 s[2:3], v[1:2]
s_cbranch_execz .LBB0_3
s_clause 0x1
s_load_b64 s[8:9], s[0:1], 0x10
s_load_b64 s[10:11], s[0:1], 0x0
s_load_b32 s5, s[4:5], 0x0
s_load_b32 s0, s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_mul_i32 s1, s2, s9
s_mul_hi_u32 s4, s2, s8
s_mul_i32 s7, s3, s8
s_add_i32 s1, s4, s1
s_mul_i32 s4, s2, s8
s_add_i32 s7, s1, s7
s_add_u32 s1, s10, s4
s_addc_u32 s4, s11, s7
s_add_i32 s15, s15, s5
s_mul_i32 s5, s5, s6
v_mad_u64_u32 v[3:4], null, s15, s6, v[0:1]
v_and_b32_e64 v0, s0, 1
s_mov_b32 s6, 0
.LBB0_2:
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_ashrrev_i32_e32 v4, 31, v3
v_add_co_u32 v5, vcc_lo, s1, v1
v_add_co_ci_u32_e32 v6, vcc_lo, s4, v2, vcc_lo
v_cmp_le_u64_e64 s0, s[2:3], v[3:4]
v_dual_mov_b32 v1, v3 :: v_dual_mov_b32 v2, v4
v_add_nc_u32_e32 v3, s5, v3
global_store_b8 v[5:6], v0, off
s_or_b32 s6, s0, s6
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s6
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9ConstantBPbbmm
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9ConstantBPbbmm, .Lfunc_end0-_Z9ConstantBPbbmm
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 1
.value_kind: by_value
- .offset: 16
.size: 8
.value_kind: by_value
- .offset: 24
.size: 8
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9ConstantBPbbmm
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9ConstantBPbbmm.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000ac6f2_00000000-6_ConstantB.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z31__device_stub__Z9ConstantBPbbmmPbbmm
.type _Z31__device_stub__Z9ConstantBPbbmmPbbmm, @function
_Z31__device_stub__Z9ConstantBPbbmmPbbmm:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rdx, 8(%rsp)
movq %rcx, (%rsp)
movb %sil, 20(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9ConstantBPbbmm(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z31__device_stub__Z9ConstantBPbbmmPbbmm, .-_Z31__device_stub__Z9ConstantBPbbmmPbbmm
.globl _Z9ConstantBPbbmm
.type _Z9ConstantBPbbmm, @function
_Z9ConstantBPbbmm:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movzbl %sil, %esi
call _Z31__device_stub__Z9ConstantBPbbmmPbbmm
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z9ConstantBPbbmm, .-_Z9ConstantBPbbmm
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z9ConstantBPbbmm"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z9ConstantBPbbmm(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "ConstantB.hip"
.globl _Z24__device_stub__ConstantBPbbmm # -- Begin function _Z24__device_stub__ConstantBPbbmm
.p2align 4, 0x90
.type _Z24__device_stub__ConstantBPbbmm,@function
_Z24__device_stub__ConstantBPbbmm: # @_Z24__device_stub__ConstantBPbbmm
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movb %sil, 7(%rsp)
movq %rdx, 64(%rsp)
movq %rcx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 7(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 56(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9ConstantBPbbmm, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z24__device_stub__ConstantBPbbmm, .Lfunc_end0-_Z24__device_stub__ConstantBPbbmm
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9ConstantBPbbmm, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9ConstantBPbbmm,@object # @_Z9ConstantBPbbmm
.section .rodata,"a",@progbits
.globl _Z9ConstantBPbbmm
.p2align 3, 0x0
_Z9ConstantBPbbmm:
.quad _Z24__device_stub__ConstantBPbbmm
.size _Z9ConstantBPbbmm, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z9ConstantBPbbmm"
.size .L__unnamed_1, 18
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__ConstantBPbbmm
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9ConstantBPbbmm
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <stdlib.h>
#include <string>
#include <curand.h>
#include <curand_kernel.h>
#define ull unsigned long long
#define ld long double
#define GTX_1060_BLOCKS 1280
#define WARP_SIZE 32 // количество потоков в блоке
/**
* Запуск по всем блокам. После выполнения функции в per_blocks_sum лежат
* сумма для каждого блока, и тогда эти значения суммируются в одно.
* @param per_blocks_sum массив с локальной суммой по всем потокам каждого блока
* @param iterations количество итераций на поток.
*/
__global__ void kernel(ull *per_blocks_sum, ull iterations) {
__shared__ ull per_block_sum[WARP_SIZE];
ull index = threadIdx.x + blockIdx.x * blockDim.x;
curandState_t rng;
curand_init(clock64(), index, 0, &rng);
per_block_sum[threadIdx.x] = 0;
for (int i = 0; i < iterations; i++) {
double x = curand_uniform(&rng); // x в [0,1]
double y = curand_uniform(&rng); // y в [0,1]
per_block_sum[threadIdx.x] += 1 - int(x * x + y * y);
}
if (threadIdx.x == 0) {
per_blocks_sum[blockIdx.x] = 0;
for (int i = 0; i < WARP_SIZE; i++) {
per_blocks_sum[blockIdx.x] += per_block_sum[i];
}
}
}
__host__ ld monteCarloCPU(ull N) {
double x,y;
ld sum = 0;
for(int i = 0; i < N; i++){
x = (double) rand()/RAND_MAX;
y = (double) rand()/RAND_MAX;
if(x*x + y*y <= 1) sum += 1.0;
}
return sum * 4.0 / (ld)(N);
}
__host__ ld monteCarloGPU(ull N) {
ull iterations;
size_t size = N * sizeof(ull);
ull *sums_per_blocks = nullptr;
cudaMalloc(&sums_per_blocks, size);
iterations = N / (GTX_1060_BLOCKS * WARP_SIZE);
if (iterations == 0) {
iterations = 1;
kernel<<<N, 1>>>(sums_per_blocks, iterations);
}
else {
kernel<<<GTX_1060_BLOCKS, WARP_SIZE>>>(sums_per_blocks, iterations);
}
cudaDeviceSynchronize();
ull *host_sums_per_blocks = (ull *) malloc(size);
cudaMemcpy(host_sums_per_blocks, sums_per_blocks, size, cudaMemcpyDeviceToHost);
double sum = 0;
double sum_iterations = GTX_1060_BLOCKS;
if(iterations == 1) {
sum_iterations = N;
}
for (int i = 0; i < sum_iterations; i++) {
sum += host_sums_per_blocks[i];
}
double divizor = iterations == 1 ? N : GTX_1060_BLOCKS * WARP_SIZE * iterations;
free(host_sums_per_blocks);
cudaFree(sums_per_blocks);
return sum * 4 / divizor;
}
int main() {
unsigned long long n = 1e8;
// scanf("%llu", &n);
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaEventRecord(start, 0);
ld pi = monteCarloGPU(n);
cudaEventRecord(stop, 0);
cudaEventSynchronize(stop);
printf("GPU Pi:: %Lf\n", pi);
float milliseconds = 0;
cudaEventElapsedTime(&milliseconds, start, stop);
printf("Time consumed for monteCarloGPU :: %3.1f ms \n", milliseconds);
cudaEventRecord(start, 0);
pi = monteCarloCPU(n);
cudaEventRecord(stop, 0);
cudaEventSynchronize(stop);
printf("CPU Pi:: %Lf\n", pi);
cudaEventElapsedTime(&milliseconds, start, stop);
printf("Time consumed for monteCarloCPU :: %3.1f ms \n", milliseconds);
return 0;
} | .file "tmpxft_000a536f_00000000-6_monteCarloPi.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3275:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3275:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z13monteCarloCPUy
.type _Z13monteCarloCPUy, @function
_Z13monteCarloCPUy:
.LFB3270:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $40, %rsp
.cfi_def_cfa_offset 64
movq %rdi, %rbp
testq %rdi, %rdi
je .L9
movl $0, %ebx
fldz
fstpt 16(%rsp)
jmp .L7
.L5:
addq $1, %rbx
cmpq %rbx, %rbp
je .L4
.L7:
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
divsd .LC1(%rip), %xmm0
movsd %xmm0, 8(%rsp)
call rand@PLT
pxor %xmm1, %xmm1
cvtsi2sdl %eax, %xmm1
divsd .LC1(%rip), %xmm1
movsd 8(%rsp), %xmm0
mulsd %xmm0, %xmm0
mulsd %xmm1, %xmm1
addsd %xmm1, %xmm0
movsd .LC2(%rip), %xmm2
comisd %xmm0, %xmm2
jb .L5
fld1
fldt 16(%rsp)
faddp %st, %st(1)
fstpt 16(%rsp)
jmp .L5
.L9:
fldz
fstpt 16(%rsp)
.L4:
fldt 16(%rsp)
fmuls .LC4(%rip)
movq %rbp, 8(%rsp)
fildq 8(%rsp)
testq %rbp, %rbp
js .L13
.L8:
fdivrp %st, %st(1)
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L13:
.cfi_restore_state
fadds .LC5(%rip)
jmp .L8
.cfi_endproc
.LFE3270:
.size _Z13monteCarloCPUy, .-_Z13monteCarloCPUy
.globl _Z26__device_stub__Z6kernelPyyPyy
.type _Z26__device_stub__Z6kernelPyyPyy, @function
_Z26__device_stub__Z6kernelPyyPyy:
.LFB3297:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L18
.L14:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L19
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L18:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z6kernelPyy(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L14
.L19:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3297:
.size _Z26__device_stub__Z6kernelPyyPyy, .-_Z26__device_stub__Z6kernelPyyPyy
.globl _Z6kernelPyy
.type _Z6kernelPyy, @function
_Z6kernelPyy:
.LFB3298:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z6kernelPyyPyy
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3298:
.size _Z6kernelPyy, .-_Z6kernelPyy
.globl _Z13monteCarloGPUy
.type _Z13monteCarloGPUy, @function
_Z13monteCarloGPUy:
.LFB3271:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $72, %rsp
.cfi_def_cfa_offset 112
movq %rdi, %rbp
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
leaq 0(,%rdi,8), %r13
movq $0, 24(%rsp)
leaq 24(%rsp), %rdi
movq %r13, %rsi
call cudaMalloc@PLT
cmpq $40959, %rbp
ja .L23
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl %ebp, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L47
.L24:
call cudaDeviceSynchronize@PLT
movq %r13, %rdi
call malloc@PLT
movq %rax, %rbx
movl $2, %ecx
movq %r13, %rdx
movq 24(%rsp), %rsi
movq %rax, %rdi
call cudaMemcpy@PLT
.L25:
testq %rbp, %rbp
js .L28
pxor %xmm1, %xmm1
cvtsi2sdq %rbp, %xmm1
.L29:
movl $1, %r12d
pxor %xmm0, %xmm0
comisd %xmm0, %xmm1
ja .L27
movq $0x000000000, (%rsp)
.L30:
testq %rbp, %rbp
js .L38
pxor %xmm5, %xmm5
cvtsi2sdq %rbp, %xmm5
movsd %xmm5, 8(%rsp)
jmp .L37
.L47:
movl $1, %esi
movq 24(%rsp), %rdi
call _Z26__device_stub__Z6kernelPyyPyy
jmp .L24
.L23:
movabsq $-3689348814741910323, %rdx
movq %rbp, %rax
mulq %rdx
shrq $15, %rdx
movq %rdx, %r12
movl $32, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1280, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L48
.L26:
call cudaDeviceSynchronize@PLT
movq %r13, %rdi
call malloc@PLT
movq %rax, %rbx
movl $2, %ecx
movq %r13, %rdx
movq 24(%rsp), %rsi
movq %rax, %rdi
call cudaMemcpy@PLT
cmpq $1, %r12
je .L25
movsd .LC8(%rip), %xmm1
.L27:
movl $1, %esi
movq $0x000000000, (%rsp)
jmp .L34
.L48:
movq %r12, %rsi
movq 24(%rsp), %rdi
call _Z26__device_stub__Z6kernelPyyPyy
jmp .L26
.L28:
movq %rbp, %rax
shrq %rax
movq %rbp, %rdx
andl $1, %edx
orq %rdx, %rax
pxor %xmm1, %xmm1
cvtsi2sdq %rax, %xmm1
addsd %xmm1, %xmm1
jmp .L29
.L32:
movq %rcx, %rax
shrq %rax
andl $1, %ecx
orq %rcx, %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
addsd %xmm0, %xmm0
.L33:
addsd (%rsp), %xmm0
movsd %xmm0, (%rsp)
pxor %xmm0, %xmm0
cvtsi2sdl %esi, %xmm0
addq $1, %rsi
comisd %xmm0, %xmm1
jbe .L49
.L34:
movq -8(%rbx,%rsi,8), %rcx
testq %rcx, %rcx
js .L32
pxor %xmm0, %xmm0
cvtsi2sdq %rcx, %xmm0
jmp .L33
.L49:
cmpq $1, %r12
je .L30
leaq (%r12,%r12,4), %rax
salq $13, %rax
js .L35
pxor %xmm4, %xmm4
cvtsi2sdq %rax, %xmm4
movsd %xmm4, 8(%rsp)
.L37:
movq %rbx, %rdi
call free@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movsd (%rsp), %xmm0
mulsd .LC10(%rip), %xmm0
divsd 8(%rsp), %xmm0
movsd %xmm0, (%rsp)
fldl (%rsp)
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L50
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L35:
.cfi_restore_state
shrq %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
addsd %xmm0, %xmm0
movsd %xmm0, 8(%rsp)
jmp .L37
.L38:
movq %rbp, %rax
shrq %rax
andl $1, %ebp
orq %rbp, %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
addsd %xmm0, %xmm0
movsd %xmm0, 8(%rsp)
jmp .L37
.L50:
fstp %st(0)
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3271:
.size _Z13monteCarloGPUy, .-_Z13monteCarloGPUy
.section .rodata.str1.1,"aMS",@progbits,1
.LC11:
.string "GPU Pi:: %Lf\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC12:
.string "Time consumed for monteCarloGPU :: %3.1f ms \n"
.section .rodata.str1.1
.LC13:
.string "CPU Pi:: %Lf\n"
.section .rodata.str1.8
.align 8
.LC14:
.string "Time consumed for monteCarloCPU :: %3.1f ms \n"
.text
.globl main
.type main, @function
main:
.LFB3272:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $48, %rsp
.cfi_def_cfa_offset 80
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rdi
call cudaEventCreate@PLT
leaq 32(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 24(%rsp), %rdi
call cudaEventRecord@PLT
movl $100000000, %edi
call _Z13monteCarloGPUy
fstpt (%rsp)
movq (%rsp), %r14
movl 8(%rsp), %r15d
movl $0, %esi
movq 32(%rsp), %rdi
call cudaEventRecord@PLT
movq 32(%rsp), %rdi
call cudaEventSynchronize@PLT
pushq %r15
.cfi_def_cfa_offset 88
pushq %r14
.cfi_def_cfa_offset 96
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0x00000000, 36(%rsp)
addq $16, %rsp
.cfi_def_cfa_offset 80
leaq 20(%rsp), %rbx
movq 32(%rsp), %rdx
movq 24(%rsp), %rsi
movq %rbx, %rdi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtss2sd 20(%rsp), %xmm0
leaq .LC12(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl $0, %esi
movq 24(%rsp), %rdi
call cudaEventRecord@PLT
movl $100000000, %edi
call _Z13monteCarloCPUy
fstpt (%rsp)
movq (%rsp), %r14
movl 8(%rsp), %r15d
movl $0, %esi
movq 32(%rsp), %rdi
call cudaEventRecord@PLT
movq 32(%rsp), %rdi
call cudaEventSynchronize@PLT
pushq %r15
.cfi_def_cfa_offset 88
pushq %r14
.cfi_def_cfa_offset 96
leaq .LC13(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $16, %rsp
.cfi_def_cfa_offset 80
movq 32(%rsp), %rdx
movq 24(%rsp), %rsi
movq %rbx, %rdi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtss2sd 20(%rsp), %xmm0
leaq .LC14(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L54
movl $0, %eax
addq $48, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L54:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3272:
.size main, .-main
.section .rodata.str1.1
.LC15:
.string "_Z6kernelPyy"
.LC16:
.string "precalc_xorwow_matrix"
.LC17:
.string "precalc_xorwow_offset_matrix"
.LC18:
.string "mrg32k3aM1"
.LC19:
.string "mrg32k3aM2"
.LC20:
.string "mrg32k3aM1SubSeq"
.LC21:
.string "mrg32k3aM2SubSeq"
.LC22:
.string "mrg32k3aM1Seq"
.LC23:
.string "mrg32k3aM2Seq"
.LC24:
.string "__cr_lgamma_table"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3300:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC15(%rip), %rdx
movq %rdx, %rcx
leaq _Z6kernelPyy(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $102400, %r9d
movl $0, %r8d
leaq .LC16(%rip), %rdx
movq %rdx, %rcx
leaq _ZL21precalc_xorwow_matrix(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $102400, %r9d
movl $0, %r8d
leaq .LC17(%rip), %rdx
movq %rdx, %rcx
leaq _ZL28precalc_xorwow_offset_matrix(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC18(%rip), %rdx
movq %rdx, %rcx
leaq _ZL10mrg32k3aM1(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC19(%rip), %rdx
movq %rdx, %rcx
leaq _ZL10mrg32k3aM2(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2016, %r9d
movl $0, %r8d
leaq .LC20(%rip), %rdx
movq %rdx, %rcx
leaq _ZL16mrg32k3aM1SubSeq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2016, %r9d
movl $0, %r8d
leaq .LC21(%rip), %rdx
movq %rdx, %rcx
leaq _ZL16mrg32k3aM2SubSeq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC22(%rip), %rdx
movq %rdx, %rcx
leaq _ZL13mrg32k3aM1Seq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC23(%rip), %rdx
movq %rdx, %rcx
leaq _ZL13mrg32k3aM2Seq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $72, %r9d
movl $0, %r8d
leaq .LC24(%rip), %rdx
movq %rdx, %rcx
leaq _ZL17__cr_lgamma_table(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3300:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL17__cr_lgamma_table
.comm _ZL17__cr_lgamma_table,72,32
.local _ZL13mrg32k3aM2Seq
.comm _ZL13mrg32k3aM2Seq,2304,32
.local _ZL13mrg32k3aM1Seq
.comm _ZL13mrg32k3aM1Seq,2304,32
.local _ZL16mrg32k3aM2SubSeq
.comm _ZL16mrg32k3aM2SubSeq,2016,32
.local _ZL16mrg32k3aM1SubSeq
.comm _ZL16mrg32k3aM1SubSeq,2016,32
.local _ZL10mrg32k3aM2
.comm _ZL10mrg32k3aM2,2304,32
.local _ZL10mrg32k3aM1
.comm _ZL10mrg32k3aM1,2304,32
.local _ZL28precalc_xorwow_offset_matrix
.comm _ZL28precalc_xorwow_offset_matrix,102400,32
.local _ZL21precalc_xorwow_matrix
.comm _ZL21precalc_xorwow_matrix,102400,32
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC1:
.long -4194304
.long 1105199103
.align 8
.LC2:
.long 0
.long 1072693248
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC4:
.long 1082130432
.align 4
.LC5:
.long 1602224128
.section .rodata.cst8
.align 8
.LC8:
.long 0
.long 1083441152
.align 8
.LC10:
.long 0
.long 1074790400
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <stdlib.h>
#include <string>
#include <curand.h>
#include <curand_kernel.h>
#define ull unsigned long long
#define ld long double
#define GTX_1060_BLOCKS 1280
#define WARP_SIZE 32 // количество потоков в блоке
/**
* Запуск по всем блокам. После выполнения функции в per_blocks_sum лежат
* сумма для каждого блока, и тогда эти значения суммируются в одно.
* @param per_blocks_sum массив с локальной суммой по всем потокам каждого блока
* @param iterations количество итераций на поток.
*/
__global__ void kernel(ull *per_blocks_sum, ull iterations) {
__shared__ ull per_block_sum[WARP_SIZE];
ull index = threadIdx.x + blockIdx.x * blockDim.x;
curandState_t rng;
curand_init(clock64(), index, 0, &rng);
per_block_sum[threadIdx.x] = 0;
for (int i = 0; i < iterations; i++) {
double x = curand_uniform(&rng); // x в [0,1]
double y = curand_uniform(&rng); // y в [0,1]
per_block_sum[threadIdx.x] += 1 - int(x * x + y * y);
}
if (threadIdx.x == 0) {
per_blocks_sum[blockIdx.x] = 0;
for (int i = 0; i < WARP_SIZE; i++) {
per_blocks_sum[blockIdx.x] += per_block_sum[i];
}
}
}
__host__ ld monteCarloCPU(ull N) {
double x,y;
ld sum = 0;
for(int i = 0; i < N; i++){
x = (double) rand()/RAND_MAX;
y = (double) rand()/RAND_MAX;
if(x*x + y*y <= 1) sum += 1.0;
}
return sum * 4.0 / (ld)(N);
}
__host__ ld monteCarloGPU(ull N) {
ull iterations;
size_t size = N * sizeof(ull);
ull *sums_per_blocks = nullptr;
cudaMalloc(&sums_per_blocks, size);
iterations = N / (GTX_1060_BLOCKS * WARP_SIZE);
if (iterations == 0) {
iterations = 1;
kernel<<<N, 1>>>(sums_per_blocks, iterations);
}
else {
kernel<<<GTX_1060_BLOCKS, WARP_SIZE>>>(sums_per_blocks, iterations);
}
cudaDeviceSynchronize();
ull *host_sums_per_blocks = (ull *) malloc(size);
cudaMemcpy(host_sums_per_blocks, sums_per_blocks, size, cudaMemcpyDeviceToHost);
double sum = 0;
double sum_iterations = GTX_1060_BLOCKS;
if(iterations == 1) {
sum_iterations = N;
}
for (int i = 0; i < sum_iterations; i++) {
sum += host_sums_per_blocks[i];
}
double divizor = iterations == 1 ? N : GTX_1060_BLOCKS * WARP_SIZE * iterations;
free(host_sums_per_blocks);
cudaFree(sums_per_blocks);
return sum * 4 / divizor;
}
int main() {
unsigned long long n = 1e8;
// scanf("%llu", &n);
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaEventRecord(start, 0);
ld pi = monteCarloGPU(n);
cudaEventRecord(stop, 0);
cudaEventSynchronize(stop);
printf("GPU Pi:: %Lf\n", pi);
float milliseconds = 0;
cudaEventElapsedTime(&milliseconds, start, stop);
printf("Time consumed for monteCarloGPU :: %3.1f ms \n", milliseconds);
cudaEventRecord(start, 0);
pi = monteCarloCPU(n);
cudaEventRecord(stop, 0);
cudaEventSynchronize(stop);
printf("CPU Pi:: %Lf\n", pi);
cudaEventElapsedTime(&milliseconds, start, stop);
printf("Time consumed for monteCarloCPU :: %3.1f ms \n", milliseconds);
return 0;
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <string>
#include <hiprand/hiprand.h>
#include <hiprand/hiprand_kernel.h>
#define ull unsigned long long
#define ld long double
#define GTX_1060_BLOCKS 1280
#define WARP_SIZE 32 // количество потоков в блоке
/**
* Запуск по всем блокам. После выполнения функции в per_blocks_sum лежат
* сумма для каждого блока, и тогда эти значения суммируются в одно.
* @param per_blocks_sum массив с локальной суммой по всем потокам каждого блока
* @param iterations количество итераций на поток.
*/
__global__ void kernel(ull *per_blocks_sum, ull iterations) {
__shared__ ull per_block_sum[WARP_SIZE];
ull index = threadIdx.x + blockIdx.x * blockDim.x;
hiprandState_t rng;
hiprand_init(clock64(), index, 0, &rng);
per_block_sum[threadIdx.x] = 0;
for (int i = 0; i < iterations; i++) {
double x = hiprand_uniform(&rng); // x в [0,1]
double y = hiprand_uniform(&rng); // y в [0,1]
per_block_sum[threadIdx.x] += 1 - int(x * x + y * y);
}
if (threadIdx.x == 0) {
per_blocks_sum[blockIdx.x] = 0;
for (int i = 0; i < WARP_SIZE; i++) {
per_blocks_sum[blockIdx.x] += per_block_sum[i];
}
}
}
__host__ ld monteCarloCPU(ull N) {
double x,y;
ld sum = 0;
for(int i = 0; i < N; i++){
x = (double) rand()/RAND_MAX;
y = (double) rand()/RAND_MAX;
if(x*x + y*y <= 1) sum += 1.0;
}
return sum * 4.0 / (ld)(N);
}
__host__ ld monteCarloGPU(ull N) {
ull iterations;
size_t size = N * sizeof(ull);
ull *sums_per_blocks = nullptr;
hipMalloc(&sums_per_blocks, size);
iterations = N / (GTX_1060_BLOCKS * WARP_SIZE);
if (iterations == 0) {
iterations = 1;
kernel<<<N, 1>>>(sums_per_blocks, iterations);
}
else {
kernel<<<GTX_1060_BLOCKS, WARP_SIZE>>>(sums_per_blocks, iterations);
}
hipDeviceSynchronize();
ull *host_sums_per_blocks = (ull *) malloc(size);
hipMemcpy(host_sums_per_blocks, sums_per_blocks, size, hipMemcpyDeviceToHost);
double sum = 0;
double sum_iterations = GTX_1060_BLOCKS;
if(iterations == 1) {
sum_iterations = N;
}
for (int i = 0; i < sum_iterations; i++) {
sum += host_sums_per_blocks[i];
}
double divizor = iterations == 1 ? N : GTX_1060_BLOCKS * WARP_SIZE * iterations;
free(host_sums_per_blocks);
hipFree(sums_per_blocks);
return sum * 4 / divizor;
}
int main() {
unsigned long long n = 1e8;
// scanf("%llu", &n);
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
hipEventRecord(start, 0);
ld pi = monteCarloGPU(n);
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
printf("GPU Pi:: %Lf\n", pi);
float milliseconds = 0;
hipEventElapsedTime(&milliseconds, start, stop);
printf("Time consumed for monteCarloGPU :: %3.1f ms \n", milliseconds);
hipEventRecord(start, 0);
pi = monteCarloCPU(n);
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
printf("CPU Pi:: %Lf\n", pi);
hipEventElapsedTime(&milliseconds, start, stop);
printf("Time consumed for monteCarloCPU :: %3.1f ms \n", milliseconds);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <string>
#include <hiprand/hiprand.h>
#include <hiprand/hiprand_kernel.h>
#define ull unsigned long long
#define ld long double
#define GTX_1060_BLOCKS 1280
#define WARP_SIZE 32 // количество потоков в блоке
/**
* Запуск по всем блокам. После выполнения функции в per_blocks_sum лежат
* сумма для каждого блока, и тогда эти значения суммируются в одно.
* @param per_blocks_sum массив с локальной суммой по всем потокам каждого блока
* @param iterations количество итераций на поток.
*/
__global__ void kernel(ull *per_blocks_sum, ull iterations) {
__shared__ ull per_block_sum[WARP_SIZE];
ull index = threadIdx.x + blockIdx.x * blockDim.x;
hiprandState_t rng;
hiprand_init(clock64(), index, 0, &rng);
per_block_sum[threadIdx.x] = 0;
for (int i = 0; i < iterations; i++) {
double x = hiprand_uniform(&rng); // x в [0,1]
double y = hiprand_uniform(&rng); // y в [0,1]
per_block_sum[threadIdx.x] += 1 - int(x * x + y * y);
}
if (threadIdx.x == 0) {
per_blocks_sum[blockIdx.x] = 0;
for (int i = 0; i < WARP_SIZE; i++) {
per_blocks_sum[blockIdx.x] += per_block_sum[i];
}
}
}
__host__ ld monteCarloCPU(ull N) {
double x,y;
ld sum = 0;
for(int i = 0; i < N; i++){
x = (double) rand()/RAND_MAX;
y = (double) rand()/RAND_MAX;
if(x*x + y*y <= 1) sum += 1.0;
}
return sum * 4.0 / (ld)(N);
}
__host__ ld monteCarloGPU(ull N) {
ull iterations;
size_t size = N * sizeof(ull);
ull *sums_per_blocks = nullptr;
hipMalloc(&sums_per_blocks, size);
iterations = N / (GTX_1060_BLOCKS * WARP_SIZE);
if (iterations == 0) {
iterations = 1;
kernel<<<N, 1>>>(sums_per_blocks, iterations);
}
else {
kernel<<<GTX_1060_BLOCKS, WARP_SIZE>>>(sums_per_blocks, iterations);
}
hipDeviceSynchronize();
ull *host_sums_per_blocks = (ull *) malloc(size);
hipMemcpy(host_sums_per_blocks, sums_per_blocks, size, hipMemcpyDeviceToHost);
double sum = 0;
double sum_iterations = GTX_1060_BLOCKS;
if(iterations == 1) {
sum_iterations = N;
}
for (int i = 0; i < sum_iterations; i++) {
sum += host_sums_per_blocks[i];
}
double divizor = iterations == 1 ? N : GTX_1060_BLOCKS * WARP_SIZE * iterations;
free(host_sums_per_blocks);
hipFree(sums_per_blocks);
return sum * 4 / divizor;
}
int main() {
unsigned long long n = 1e8;
// scanf("%llu", &n);
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
hipEventRecord(start, 0);
ld pi = monteCarloGPU(n);
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
printf("GPU Pi:: %Lf\n", pi);
float milliseconds = 0;
hipEventElapsedTime(&milliseconds, start, stop);
printf("Time consumed for monteCarloGPU :: %3.1f ms \n", milliseconds);
hipEventRecord(start, 0);
pi = monteCarloCPU(n);
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
printf("CPU Pi:: %Lf\n", pi);
hipEventElapsedTime(&milliseconds, start, stop);
printf("Time consumed for monteCarloCPU :: %3.1f ms \n", milliseconds);
return 0;
} | .text
.file "monteCarloPi.hip"
.globl _Z21__device_stub__kernelPyy # -- Begin function _Z21__device_stub__kernelPyy
.p2align 4, 0x90
.type _Z21__device_stub__kernelPyy,@function
_Z21__device_stub__kernelPyy: # @_Z21__device_stub__kernelPyy
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z6kernelPyy, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z21__device_stub__kernelPyy, .Lfunc_end0-_Z21__device_stub__kernelPyy
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z13monteCarloCPUy
.LCPI1_0:
.quad 0x41dfffffffc00000 # double 2147483647
.LCPI1_1:
.quad 0x3ff0000000000000 # double 1
.LCPI1_3:
.quad 6881500230622117888 # 0x5f80000000000000
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0
.LCPI1_2:
.long 0x40800000 # float 4
.text
.globl _Z13monteCarloCPUy
.p2align 4, 0x90
.type _Z13monteCarloCPUy,@function
_Z13monteCarloCPUy: # @_Z13monteCarloCPUy
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $40, %rsp
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movq %rdi, %rbx
fldz
testq %rdi, %rdi
je .LBB1_4
# %bb.1: # %.lr.ph.preheader
fstp %st(0)
fldz
movq %rbx, %r14
.p2align 4, 0x90
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
fstpt 28(%rsp) # 10-byte Folded Spill
callq rand
xorps %xmm1, %xmm1
cvtsi2sd %eax, %xmm1
movsd .LCPI1_0(%rip), %xmm0 # xmm0 = mem[0],zero
divsd %xmm0, %xmm1
movsd %xmm1, 8(%rsp) # 8-byte Spill
callq rand
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
divsd .LCPI1_0(%rip), %xmm0
movsd 8(%rsp), %xmm1 # 8-byte Reload
# xmm1 = mem[0],zero
mulsd %xmm1, %xmm1
mulsd %xmm0, %xmm0
addsd %xmm1, %xmm0
movsd .LCPI1_1(%rip), %xmm1 # xmm1 = mem[0],zero
ucomisd %xmm0, %xmm1
fld1
fldt 28(%rsp) # 10-byte Folded Reload
fadd %st, %st(1)
fxch %st(1)
fcmovb %st(1), %st
fstp %st(1)
decq %r14
jne .LBB1_2
# %bb.3: # %._crit_edge.loopexit
fmuls .LCPI1_2(%rip)
.LBB1_4: # %._crit_edge
movq %rbx, 16(%rsp)
xorl %eax, %eax
testq %rbx, %rbx
sets %al
fildll 16(%rsp)
fadds .LCPI1_3(,%rax,4)
fdivrp %st, %st(1)
addq $40, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z13monteCarloCPUy, .Lfunc_end1-_Z13monteCarloCPUy
.cfi_endproc
# -- End function
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function _Z13monteCarloGPUy
.LCPI2_0:
.long 1127219200 # 0x43300000
.long 1160773632 # 0x45300000
.long 0 # 0x0
.long 0 # 0x0
.LCPI2_1:
.quad 0x4330000000000000 # double 4503599627370496
.quad 0x4530000000000000 # double 1.9342813113834067E+25
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0
.LCPI2_2:
.quad 0x4094000000000000 # double 1280
.LCPI2_3:
.quad 0x4010000000000000 # double 4
.text
.globl _Z13monteCarloGPUy
.p2align 4, 0x90
.type _Z13monteCarloGPUy,@function
_Z13monteCarloGPUy: # @_Z13monteCarloGPUy
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $120, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdi, %rbx
movabsq $4294967296, %r12 # imm = 0x100000000
leaq (,%rdi,8), %r15
movq $0, 8(%rsp)
leaq 8(%rsp), %rdi
movq %r15, %rsi
callq hipMalloc
movabsq $-3689348814741910323, %rcx # imm = 0xCCCCCCCCCCCCCCCD
movq %rbx, %rax
mulq %rcx
cmpq $40959, %rbx # imm = 0x9FFF
ja .LBB2_3
# %bb.1:
movq %rbx, %rdi
orq %r12, %rdi
incq %r12
movl $1, %esi
movq %r12, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
movl $1, %r14d
testl %eax, %eax
jne .LBB2_6
# %bb.2:
movq 8(%rsp), %rax
movq %rax, 72(%rsp)
movq $1, 64(%rsp)
jmp .LBB2_5
.LBB2_3:
movq %rdx, %r14
shrq $15, %r14
leaq 32(%r12), %rdx
addq $1280, %r12 # imm = 0x500
movq %r12, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_6
# %bb.4:
movq 8(%rsp), %rax
movq %rax, 72(%rsp)
movq %r14, 64(%rsp)
.LBB2_5:
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6kernelPyy, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_6:
callq hipDeviceSynchronize
movq %r15, %rdi
callq malloc
movq %rax, %r12
movq 8(%rsp), %rsi
movq %rax, %rdi
movq %r15, %rdx
movl $2, %ecx
callq hipMemcpy
cmpq $1, %r14
je .LBB2_7
# %bb.8:
movsd .LCPI2_2(%rip), %xmm0 # xmm0 = mem[0],zero
jmp .LBB2_9
.LBB2_7:
movq %rbx, %xmm1
punpckldq .LCPI2_0(%rip), %xmm1 # xmm1 = xmm1[0],mem[0],xmm1[1],mem[1]
subpd .LCPI2_1(%rip), %xmm1
movapd %xmm1, %xmm0
unpckhpd %xmm1, %xmm0 # xmm0 = xmm0[1],xmm1[1]
addsd %xmm1, %xmm0
.LBB2_9:
xorpd %xmm5, %xmm5
ucomisd %xmm5, %xmm0
jbe .LBB2_13
# %bb.10: # %.lr.ph.preheader
xorl %eax, %eax
movapd .LCPI2_0(%rip), %xmm1 # xmm1 = [1127219200,1160773632,0,0]
movapd .LCPI2_1(%rip), %xmm2 # xmm2 = [4.503599627370496E+15,1.9342813113834067E+25]
.p2align 4, 0x90
.LBB2_11: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movsd (%r12,%rax,8), %xmm3 # xmm3 = mem[0],zero
unpcklps %xmm1, %xmm3 # xmm3 = xmm3[0],xmm1[0],xmm3[1],xmm1[1]
subpd %xmm2, %xmm3
movapd %xmm3, %xmm4
unpckhpd %xmm3, %xmm4 # xmm4 = xmm4[1],xmm3[1]
addsd %xmm3, %xmm4
addsd %xmm4, %xmm5
incq %rax
xorps %xmm3, %xmm3
cvtsi2sd %eax, %xmm3
ucomisd %xmm3, %xmm0
ja .LBB2_11
# %bb.12: # %._crit_edge.loopexit
mulsd .LCPI2_3(%rip), %xmm5
.LBB2_13: # %._crit_edge
movq %r14, %rax
shlq $13, %rax
cmpq $1, %r14
leaq (%rax,%rax,4), %rax
cmoveq %rbx, %rax
movq %rax, %xmm0
punpckldq .LCPI2_0(%rip), %xmm0 # xmm0 = xmm0[0],mem[0],xmm0[1],mem[1]
subpd .LCPI2_1(%rip), %xmm0
movapd %xmm0, %xmm1
unpckhpd %xmm0, %xmm1 # xmm1 = xmm1[1],xmm0[1]
addsd %xmm0, %xmm1
divsd %xmm1, %xmm5
movsd %xmm5, 104(%rsp) # 8-byte Spill
movq %r12, %rdi
callq free
movq 8(%rsp), %rdi
callq hipFree
movsd 104(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
movsd %xmm0, 112(%rsp)
fldl 112(%rsp)
addq $120, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z13monteCarloGPUy, .Lfunc_end2-_Z13monteCarloGPUy
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI3_0:
.quad 0x41dfffffffc00000 # double 2147483647
.LCPI3_1:
.quad 0x3ff0000000000000 # double 1
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0
.LCPI3_2:
.long 0x40800000 # float 4
.LCPI3_3:
.long 0x4cbebc20 # float 1.0E+8
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $64, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -16
leaq 32(%rsp), %rdi
callq hipEventCreate
leaq 24(%rsp), %rdi
callq hipEventCreate
movq 32(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movl $100000000, %ebx # imm = 0x5F5E100
movl $100000000, %edi # imm = 0x5F5E100
callq _Z13monteCarloGPUy
fstpt 44(%rsp) # 10-byte Folded Spill
movq 24(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 24(%rsp), %rdi
callq hipEventSynchronize
fldt 44(%rsp) # 10-byte Folded Reload
fstpt (%rsp)
movl $.L.str, %edi
xorl %eax, %eax
callq printf
movl $0, 20(%rsp)
movq 32(%rsp), %rsi
movq 24(%rsp), %rdx
leaq 20(%rsp), %rdi
callq hipEventElapsedTime
movss 20(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.1, %edi
movb $1, %al
callq printf
movq 32(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
fldz
.p2align 4, 0x90
.LBB3_1: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
fstpt 44(%rsp) # 10-byte Folded Spill
callq rand
xorps %xmm1, %xmm1
cvtsi2sd %eax, %xmm1
movsd .LCPI3_0(%rip), %xmm0 # xmm0 = mem[0],zero
divsd %xmm0, %xmm1
movsd %xmm1, 56(%rsp) # 8-byte Spill
callq rand
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
divsd .LCPI3_0(%rip), %xmm0
movsd 56(%rsp), %xmm1 # 8-byte Reload
# xmm1 = mem[0],zero
mulsd %xmm1, %xmm1
mulsd %xmm0, %xmm0
addsd %xmm1, %xmm0
movsd .LCPI3_1(%rip), %xmm1 # xmm1 = mem[0],zero
ucomisd %xmm0, %xmm1
fld1
fldt 44(%rsp) # 10-byte Folded Reload
fadd %st, %st(1)
fxch %st(1)
fcmovb %st(1), %st
fstp %st(1)
decq %rbx
jne .LBB3_1
# %bb.2: # %_Z13monteCarloCPUy.exit
fmuls .LCPI3_2(%rip)
fdivs .LCPI3_3(%rip)
fstpt 44(%rsp) # 10-byte Folded Spill
movq 24(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 24(%rsp), %rdi
callq hipEventSynchronize
fldt 44(%rsp) # 10-byte Folded Reload
fstpt (%rsp)
movl $.L.str.2, %edi
xorl %eax, %eax
callq printf
movq 32(%rsp), %rsi
movq 24(%rsp), %rdx
leaq 20(%rsp), %rdi
callq hipEventElapsedTime
movss 20(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.3, %edi
movb $1, %al
callq printf
xorl %eax, %eax
addq $64, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6kernelPyy, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6kernelPyy,@object # @_Z6kernelPyy
.section .rodata,"a",@progbits
.globl _Z6kernelPyy
.p2align 3, 0x0
_Z6kernelPyy:
.quad _Z21__device_stub__kernelPyy
.size _Z6kernelPyy, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "GPU Pi:: %Lf\n"
.size .L.str, 14
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Time consumed for monteCarloGPU :: %3.1f ms \n"
.size .L.str.1, 46
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "CPU Pi:: %Lf\n"
.size .L.str.2, 14
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Time consumed for monteCarloCPU :: %3.1f ms \n"
.size .L.str.3, 46
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z6kernelPyy"
.size .L__unnamed_1, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__kernelPyy
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6kernelPyy
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000a536f_00000000-6_monteCarloPi.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3275:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3275:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z13monteCarloCPUy
.type _Z13monteCarloCPUy, @function
_Z13monteCarloCPUy:
.LFB3270:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $40, %rsp
.cfi_def_cfa_offset 64
movq %rdi, %rbp
testq %rdi, %rdi
je .L9
movl $0, %ebx
fldz
fstpt 16(%rsp)
jmp .L7
.L5:
addq $1, %rbx
cmpq %rbx, %rbp
je .L4
.L7:
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
divsd .LC1(%rip), %xmm0
movsd %xmm0, 8(%rsp)
call rand@PLT
pxor %xmm1, %xmm1
cvtsi2sdl %eax, %xmm1
divsd .LC1(%rip), %xmm1
movsd 8(%rsp), %xmm0
mulsd %xmm0, %xmm0
mulsd %xmm1, %xmm1
addsd %xmm1, %xmm0
movsd .LC2(%rip), %xmm2
comisd %xmm0, %xmm2
jb .L5
fld1
fldt 16(%rsp)
faddp %st, %st(1)
fstpt 16(%rsp)
jmp .L5
.L9:
fldz
fstpt 16(%rsp)
.L4:
fldt 16(%rsp)
fmuls .LC4(%rip)
movq %rbp, 8(%rsp)
fildq 8(%rsp)
testq %rbp, %rbp
js .L13
.L8:
fdivrp %st, %st(1)
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L13:
.cfi_restore_state
fadds .LC5(%rip)
jmp .L8
.cfi_endproc
.LFE3270:
.size _Z13monteCarloCPUy, .-_Z13monteCarloCPUy
.globl _Z26__device_stub__Z6kernelPyyPyy
.type _Z26__device_stub__Z6kernelPyyPyy, @function
_Z26__device_stub__Z6kernelPyyPyy:
.LFB3297:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L18
.L14:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L19
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L18:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z6kernelPyy(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L14
.L19:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3297:
.size _Z26__device_stub__Z6kernelPyyPyy, .-_Z26__device_stub__Z6kernelPyyPyy
.globl _Z6kernelPyy
.type _Z6kernelPyy, @function
_Z6kernelPyy:
.LFB3298:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z6kernelPyyPyy
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3298:
.size _Z6kernelPyy, .-_Z6kernelPyy
.globl _Z13monteCarloGPUy
.type _Z13monteCarloGPUy, @function
_Z13monteCarloGPUy:
.LFB3271:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $72, %rsp
.cfi_def_cfa_offset 112
movq %rdi, %rbp
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
leaq 0(,%rdi,8), %r13
movq $0, 24(%rsp)
leaq 24(%rsp), %rdi
movq %r13, %rsi
call cudaMalloc@PLT
cmpq $40959, %rbp
ja .L23
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl %ebp, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L47
.L24:
call cudaDeviceSynchronize@PLT
movq %r13, %rdi
call malloc@PLT
movq %rax, %rbx
movl $2, %ecx
movq %r13, %rdx
movq 24(%rsp), %rsi
movq %rax, %rdi
call cudaMemcpy@PLT
.L25:
testq %rbp, %rbp
js .L28
pxor %xmm1, %xmm1
cvtsi2sdq %rbp, %xmm1
.L29:
movl $1, %r12d
pxor %xmm0, %xmm0
comisd %xmm0, %xmm1
ja .L27
movq $0x000000000, (%rsp)
.L30:
testq %rbp, %rbp
js .L38
pxor %xmm5, %xmm5
cvtsi2sdq %rbp, %xmm5
movsd %xmm5, 8(%rsp)
jmp .L37
.L47:
movl $1, %esi
movq 24(%rsp), %rdi
call _Z26__device_stub__Z6kernelPyyPyy
jmp .L24
.L23:
movabsq $-3689348814741910323, %rdx
movq %rbp, %rax
mulq %rdx
shrq $15, %rdx
movq %rdx, %r12
movl $32, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1280, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L48
.L26:
call cudaDeviceSynchronize@PLT
movq %r13, %rdi
call malloc@PLT
movq %rax, %rbx
movl $2, %ecx
movq %r13, %rdx
movq 24(%rsp), %rsi
movq %rax, %rdi
call cudaMemcpy@PLT
cmpq $1, %r12
je .L25
movsd .LC8(%rip), %xmm1
.L27:
movl $1, %esi
movq $0x000000000, (%rsp)
jmp .L34
.L48:
movq %r12, %rsi
movq 24(%rsp), %rdi
call _Z26__device_stub__Z6kernelPyyPyy
jmp .L26
.L28:
movq %rbp, %rax
shrq %rax
movq %rbp, %rdx
andl $1, %edx
orq %rdx, %rax
pxor %xmm1, %xmm1
cvtsi2sdq %rax, %xmm1
addsd %xmm1, %xmm1
jmp .L29
.L32:
movq %rcx, %rax
shrq %rax
andl $1, %ecx
orq %rcx, %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
addsd %xmm0, %xmm0
.L33:
addsd (%rsp), %xmm0
movsd %xmm0, (%rsp)
pxor %xmm0, %xmm0
cvtsi2sdl %esi, %xmm0
addq $1, %rsi
comisd %xmm0, %xmm1
jbe .L49
.L34:
movq -8(%rbx,%rsi,8), %rcx
testq %rcx, %rcx
js .L32
pxor %xmm0, %xmm0
cvtsi2sdq %rcx, %xmm0
jmp .L33
.L49:
cmpq $1, %r12
je .L30
leaq (%r12,%r12,4), %rax
salq $13, %rax
js .L35
pxor %xmm4, %xmm4
cvtsi2sdq %rax, %xmm4
movsd %xmm4, 8(%rsp)
.L37:
movq %rbx, %rdi
call free@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movsd (%rsp), %xmm0
mulsd .LC10(%rip), %xmm0
divsd 8(%rsp), %xmm0
movsd %xmm0, (%rsp)
fldl (%rsp)
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L50
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L35:
.cfi_restore_state
shrq %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
addsd %xmm0, %xmm0
movsd %xmm0, 8(%rsp)
jmp .L37
.L38:
movq %rbp, %rax
shrq %rax
andl $1, %ebp
orq %rbp, %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
addsd %xmm0, %xmm0
movsd %xmm0, 8(%rsp)
jmp .L37
.L50:
fstp %st(0)
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3271:
.size _Z13monteCarloGPUy, .-_Z13monteCarloGPUy
.section .rodata.str1.1,"aMS",@progbits,1
.LC11:
.string "GPU Pi:: %Lf\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC12:
.string "Time consumed for monteCarloGPU :: %3.1f ms \n"
.section .rodata.str1.1
.LC13:
.string "CPU Pi:: %Lf\n"
.section .rodata.str1.8
.align 8
.LC14:
.string "Time consumed for monteCarloCPU :: %3.1f ms \n"
.text
.globl main
.type main, @function
main:
.LFB3272:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $48, %rsp
.cfi_def_cfa_offset 80
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rdi
call cudaEventCreate@PLT
leaq 32(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 24(%rsp), %rdi
call cudaEventRecord@PLT
movl $100000000, %edi
call _Z13monteCarloGPUy
fstpt (%rsp)
movq (%rsp), %r14
movl 8(%rsp), %r15d
movl $0, %esi
movq 32(%rsp), %rdi
call cudaEventRecord@PLT
movq 32(%rsp), %rdi
call cudaEventSynchronize@PLT
pushq %r15
.cfi_def_cfa_offset 88
pushq %r14
.cfi_def_cfa_offset 96
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0x00000000, 36(%rsp)
addq $16, %rsp
.cfi_def_cfa_offset 80
leaq 20(%rsp), %rbx
movq 32(%rsp), %rdx
movq 24(%rsp), %rsi
movq %rbx, %rdi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtss2sd 20(%rsp), %xmm0
leaq .LC12(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl $0, %esi
movq 24(%rsp), %rdi
call cudaEventRecord@PLT
movl $100000000, %edi
call _Z13monteCarloCPUy
fstpt (%rsp)
movq (%rsp), %r14
movl 8(%rsp), %r15d
movl $0, %esi
movq 32(%rsp), %rdi
call cudaEventRecord@PLT
movq 32(%rsp), %rdi
call cudaEventSynchronize@PLT
pushq %r15
.cfi_def_cfa_offset 88
pushq %r14
.cfi_def_cfa_offset 96
leaq .LC13(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $16, %rsp
.cfi_def_cfa_offset 80
movq 32(%rsp), %rdx
movq 24(%rsp), %rsi
movq %rbx, %rdi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtss2sd 20(%rsp), %xmm0
leaq .LC14(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L54
movl $0, %eax
addq $48, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L54:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3272:
.size main, .-main
.section .rodata.str1.1
.LC15:
.string "_Z6kernelPyy"
.LC16:
.string "precalc_xorwow_matrix"
.LC17:
.string "precalc_xorwow_offset_matrix"
.LC18:
.string "mrg32k3aM1"
.LC19:
.string "mrg32k3aM2"
.LC20:
.string "mrg32k3aM1SubSeq"
.LC21:
.string "mrg32k3aM2SubSeq"
.LC22:
.string "mrg32k3aM1Seq"
.LC23:
.string "mrg32k3aM2Seq"
.LC24:
.string "__cr_lgamma_table"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3300:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC15(%rip), %rdx
movq %rdx, %rcx
leaq _Z6kernelPyy(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $102400, %r9d
movl $0, %r8d
leaq .LC16(%rip), %rdx
movq %rdx, %rcx
leaq _ZL21precalc_xorwow_matrix(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $102400, %r9d
movl $0, %r8d
leaq .LC17(%rip), %rdx
movq %rdx, %rcx
leaq _ZL28precalc_xorwow_offset_matrix(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC18(%rip), %rdx
movq %rdx, %rcx
leaq _ZL10mrg32k3aM1(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC19(%rip), %rdx
movq %rdx, %rcx
leaq _ZL10mrg32k3aM2(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2016, %r9d
movl $0, %r8d
leaq .LC20(%rip), %rdx
movq %rdx, %rcx
leaq _ZL16mrg32k3aM1SubSeq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2016, %r9d
movl $0, %r8d
leaq .LC21(%rip), %rdx
movq %rdx, %rcx
leaq _ZL16mrg32k3aM2SubSeq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC22(%rip), %rdx
movq %rdx, %rcx
leaq _ZL13mrg32k3aM1Seq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC23(%rip), %rdx
movq %rdx, %rcx
leaq _ZL13mrg32k3aM2Seq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $72, %r9d
movl $0, %r8d
leaq .LC24(%rip), %rdx
movq %rdx, %rcx
leaq _ZL17__cr_lgamma_table(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3300:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL17__cr_lgamma_table
.comm _ZL17__cr_lgamma_table,72,32
.local _ZL13mrg32k3aM2Seq
.comm _ZL13mrg32k3aM2Seq,2304,32
.local _ZL13mrg32k3aM1Seq
.comm _ZL13mrg32k3aM1Seq,2304,32
.local _ZL16mrg32k3aM2SubSeq
.comm _ZL16mrg32k3aM2SubSeq,2016,32
.local _ZL16mrg32k3aM1SubSeq
.comm _ZL16mrg32k3aM1SubSeq,2016,32
.local _ZL10mrg32k3aM2
.comm _ZL10mrg32k3aM2,2304,32
.local _ZL10mrg32k3aM1
.comm _ZL10mrg32k3aM1,2304,32
.local _ZL28precalc_xorwow_offset_matrix
.comm _ZL28precalc_xorwow_offset_matrix,102400,32
.local _ZL21precalc_xorwow_matrix
.comm _ZL21precalc_xorwow_matrix,102400,32
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC1:
.long -4194304
.long 1105199103
.align 8
.LC2:
.long 0
.long 1072693248
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC4:
.long 1082130432
.align 4
.LC5:
.long 1602224128
.section .rodata.cst8
.align 8
.LC8:
.long 0
.long 1083441152
.align 8
.LC10:
.long 0
.long 1074790400
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "monteCarloPi.hip"
.globl _Z21__device_stub__kernelPyy # -- Begin function _Z21__device_stub__kernelPyy
.p2align 4, 0x90
.type _Z21__device_stub__kernelPyy,@function
_Z21__device_stub__kernelPyy: # @_Z21__device_stub__kernelPyy
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z6kernelPyy, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z21__device_stub__kernelPyy, .Lfunc_end0-_Z21__device_stub__kernelPyy
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z13monteCarloCPUy
.LCPI1_0:
.quad 0x41dfffffffc00000 # double 2147483647
.LCPI1_1:
.quad 0x3ff0000000000000 # double 1
.LCPI1_3:
.quad 6881500230622117888 # 0x5f80000000000000
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0
.LCPI1_2:
.long 0x40800000 # float 4
.text
.globl _Z13monteCarloCPUy
.p2align 4, 0x90
.type _Z13monteCarloCPUy,@function
_Z13monteCarloCPUy: # @_Z13monteCarloCPUy
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $40, %rsp
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movq %rdi, %rbx
fldz
testq %rdi, %rdi
je .LBB1_4
# %bb.1: # %.lr.ph.preheader
fstp %st(0)
fldz
movq %rbx, %r14
.p2align 4, 0x90
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
fstpt 28(%rsp) # 10-byte Folded Spill
callq rand
xorps %xmm1, %xmm1
cvtsi2sd %eax, %xmm1
movsd .LCPI1_0(%rip), %xmm0 # xmm0 = mem[0],zero
divsd %xmm0, %xmm1
movsd %xmm1, 8(%rsp) # 8-byte Spill
callq rand
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
divsd .LCPI1_0(%rip), %xmm0
movsd 8(%rsp), %xmm1 # 8-byte Reload
# xmm1 = mem[0],zero
mulsd %xmm1, %xmm1
mulsd %xmm0, %xmm0
addsd %xmm1, %xmm0
movsd .LCPI1_1(%rip), %xmm1 # xmm1 = mem[0],zero
ucomisd %xmm0, %xmm1
fld1
fldt 28(%rsp) # 10-byte Folded Reload
fadd %st, %st(1)
fxch %st(1)
fcmovb %st(1), %st
fstp %st(1)
decq %r14
jne .LBB1_2
# %bb.3: # %._crit_edge.loopexit
fmuls .LCPI1_2(%rip)
.LBB1_4: # %._crit_edge
movq %rbx, 16(%rsp)
xorl %eax, %eax
testq %rbx, %rbx
sets %al
fildll 16(%rsp)
fadds .LCPI1_3(,%rax,4)
fdivrp %st, %st(1)
addq $40, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z13monteCarloCPUy, .Lfunc_end1-_Z13monteCarloCPUy
.cfi_endproc
# -- End function
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function _Z13monteCarloGPUy
.LCPI2_0:
.long 1127219200 # 0x43300000
.long 1160773632 # 0x45300000
.long 0 # 0x0
.long 0 # 0x0
.LCPI2_1:
.quad 0x4330000000000000 # double 4503599627370496
.quad 0x4530000000000000 # double 1.9342813113834067E+25
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0
.LCPI2_2:
.quad 0x4094000000000000 # double 1280
.LCPI2_3:
.quad 0x4010000000000000 # double 4
.text
.globl _Z13monteCarloGPUy
.p2align 4, 0x90
.type _Z13monteCarloGPUy,@function
_Z13monteCarloGPUy: # @_Z13monteCarloGPUy
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $120, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdi, %rbx
movabsq $4294967296, %r12 # imm = 0x100000000
leaq (,%rdi,8), %r15
movq $0, 8(%rsp)
leaq 8(%rsp), %rdi
movq %r15, %rsi
callq hipMalloc
movabsq $-3689348814741910323, %rcx # imm = 0xCCCCCCCCCCCCCCCD
movq %rbx, %rax
mulq %rcx
cmpq $40959, %rbx # imm = 0x9FFF
ja .LBB2_3
# %bb.1:
movq %rbx, %rdi
orq %r12, %rdi
incq %r12
movl $1, %esi
movq %r12, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
movl $1, %r14d
testl %eax, %eax
jne .LBB2_6
# %bb.2:
movq 8(%rsp), %rax
movq %rax, 72(%rsp)
movq $1, 64(%rsp)
jmp .LBB2_5
.LBB2_3:
movq %rdx, %r14
shrq $15, %r14
leaq 32(%r12), %rdx
addq $1280, %r12 # imm = 0x500
movq %r12, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_6
# %bb.4:
movq 8(%rsp), %rax
movq %rax, 72(%rsp)
movq %r14, 64(%rsp)
.LBB2_5:
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6kernelPyy, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_6:
callq hipDeviceSynchronize
movq %r15, %rdi
callq malloc
movq %rax, %r12
movq 8(%rsp), %rsi
movq %rax, %rdi
movq %r15, %rdx
movl $2, %ecx
callq hipMemcpy
cmpq $1, %r14
je .LBB2_7
# %bb.8:
movsd .LCPI2_2(%rip), %xmm0 # xmm0 = mem[0],zero
jmp .LBB2_9
.LBB2_7:
movq %rbx, %xmm1
punpckldq .LCPI2_0(%rip), %xmm1 # xmm1 = xmm1[0],mem[0],xmm1[1],mem[1]
subpd .LCPI2_1(%rip), %xmm1
movapd %xmm1, %xmm0
unpckhpd %xmm1, %xmm0 # xmm0 = xmm0[1],xmm1[1]
addsd %xmm1, %xmm0
.LBB2_9:
xorpd %xmm5, %xmm5
ucomisd %xmm5, %xmm0
jbe .LBB2_13
# %bb.10: # %.lr.ph.preheader
xorl %eax, %eax
movapd .LCPI2_0(%rip), %xmm1 # xmm1 = [1127219200,1160773632,0,0]
movapd .LCPI2_1(%rip), %xmm2 # xmm2 = [4.503599627370496E+15,1.9342813113834067E+25]
.p2align 4, 0x90
.LBB2_11: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movsd (%r12,%rax,8), %xmm3 # xmm3 = mem[0],zero
unpcklps %xmm1, %xmm3 # xmm3 = xmm3[0],xmm1[0],xmm3[1],xmm1[1]
subpd %xmm2, %xmm3
movapd %xmm3, %xmm4
unpckhpd %xmm3, %xmm4 # xmm4 = xmm4[1],xmm3[1]
addsd %xmm3, %xmm4
addsd %xmm4, %xmm5
incq %rax
xorps %xmm3, %xmm3
cvtsi2sd %eax, %xmm3
ucomisd %xmm3, %xmm0
ja .LBB2_11
# %bb.12: # %._crit_edge.loopexit
mulsd .LCPI2_3(%rip), %xmm5
.LBB2_13: # %._crit_edge
movq %r14, %rax
shlq $13, %rax
cmpq $1, %r14
leaq (%rax,%rax,4), %rax
cmoveq %rbx, %rax
movq %rax, %xmm0
punpckldq .LCPI2_0(%rip), %xmm0 # xmm0 = xmm0[0],mem[0],xmm0[1],mem[1]
subpd .LCPI2_1(%rip), %xmm0
movapd %xmm0, %xmm1
unpckhpd %xmm0, %xmm1 # xmm1 = xmm1[1],xmm0[1]
addsd %xmm0, %xmm1
divsd %xmm1, %xmm5
movsd %xmm5, 104(%rsp) # 8-byte Spill
movq %r12, %rdi
callq free
movq 8(%rsp), %rdi
callq hipFree
movsd 104(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
movsd %xmm0, 112(%rsp)
fldl 112(%rsp)
addq $120, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z13monteCarloGPUy, .Lfunc_end2-_Z13monteCarloGPUy
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI3_0:
.quad 0x41dfffffffc00000 # double 2147483647
.LCPI3_1:
.quad 0x3ff0000000000000 # double 1
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0
.LCPI3_2:
.long 0x40800000 # float 4
.LCPI3_3:
.long 0x4cbebc20 # float 1.0E+8
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $64, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -16
leaq 32(%rsp), %rdi
callq hipEventCreate
leaq 24(%rsp), %rdi
callq hipEventCreate
movq 32(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movl $100000000, %ebx # imm = 0x5F5E100
movl $100000000, %edi # imm = 0x5F5E100
callq _Z13monteCarloGPUy
fstpt 44(%rsp) # 10-byte Folded Spill
movq 24(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 24(%rsp), %rdi
callq hipEventSynchronize
fldt 44(%rsp) # 10-byte Folded Reload
fstpt (%rsp)
movl $.L.str, %edi
xorl %eax, %eax
callq printf
movl $0, 20(%rsp)
movq 32(%rsp), %rsi
movq 24(%rsp), %rdx
leaq 20(%rsp), %rdi
callq hipEventElapsedTime
movss 20(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.1, %edi
movb $1, %al
callq printf
movq 32(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
fldz
.p2align 4, 0x90
.LBB3_1: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
fstpt 44(%rsp) # 10-byte Folded Spill
callq rand
xorps %xmm1, %xmm1
cvtsi2sd %eax, %xmm1
movsd .LCPI3_0(%rip), %xmm0 # xmm0 = mem[0],zero
divsd %xmm0, %xmm1
movsd %xmm1, 56(%rsp) # 8-byte Spill
callq rand
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
divsd .LCPI3_0(%rip), %xmm0
movsd 56(%rsp), %xmm1 # 8-byte Reload
# xmm1 = mem[0],zero
mulsd %xmm1, %xmm1
mulsd %xmm0, %xmm0
addsd %xmm1, %xmm0
movsd .LCPI3_1(%rip), %xmm1 # xmm1 = mem[0],zero
ucomisd %xmm0, %xmm1
fld1
fldt 44(%rsp) # 10-byte Folded Reload
fadd %st, %st(1)
fxch %st(1)
fcmovb %st(1), %st
fstp %st(1)
decq %rbx
jne .LBB3_1
# %bb.2: # %_Z13monteCarloCPUy.exit
fmuls .LCPI3_2(%rip)
fdivs .LCPI3_3(%rip)
fstpt 44(%rsp) # 10-byte Folded Spill
movq 24(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 24(%rsp), %rdi
callq hipEventSynchronize
fldt 44(%rsp) # 10-byte Folded Reload
fstpt (%rsp)
movl $.L.str.2, %edi
xorl %eax, %eax
callq printf
movq 32(%rsp), %rsi
movq 24(%rsp), %rdx
leaq 20(%rsp), %rdi
callq hipEventElapsedTime
movss 20(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.3, %edi
movb $1, %al
callq printf
xorl %eax, %eax
addq $64, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6kernelPyy, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6kernelPyy,@object # @_Z6kernelPyy
.section .rodata,"a",@progbits
.globl _Z6kernelPyy
.p2align 3, 0x0
_Z6kernelPyy:
.quad _Z21__device_stub__kernelPyy
.size _Z6kernelPyy, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "GPU Pi:: %Lf\n"
.size .L.str, 14
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Time consumed for monteCarloGPU :: %3.1f ms \n"
.size .L.str.1, 46
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "CPU Pi:: %Lf\n"
.size .L.str.2, 14
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Time consumed for monteCarloCPU :: %3.1f ms \n"
.size .L.str.3, 46
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z6kernelPyy"
.size .L__unnamed_1, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__kernelPyy
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6kernelPyy
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <cuda.h>
#define SIM_THREADS 10 // how many simultaneus threads
#define N 20 // number of variables in a vector
// this function returns a result
__global__ void cudaFunct(float *pArgument, float *pResult)
{
int i;
// this loop will do sequences:
// i = 0, 10, 20, ...
// i = 1, 11, 21, ...
// i = 2, 12, 22, ...
// ...
// i = 9, 19, 29, ...
//
// assuming SIM_THREADS = 10
for ( i = threadIdx.x; // start from i = thread ID
i < N; // stop if all i's are done
i += SIM_THREADS) // skip number of threads
pResult[i] = pArgument[i] -pArgument[i-1];
}
int main(void)
{
float *pHostArgument;
float *pCudaArgument = 0;
float *pHostResult;
float *pCudaResult = 0;
int i;
// reserve memory in host system
pHostArgument = (float *)malloc(N*sizeof(pHostArgument[0]));
pHostResult = (float *) malloc(N*sizeof(pHostResult[0]));
// reserve memory in cuda
cudaMalloc((void **) &pCudaArgument, N*sizeof(pCudaResult[0]));
cudaMalloc((void **) &pCudaResult, N*sizeof(pCudaResult[0]));
// initialize argument
for (i = 0; i < N; i++) pHostArgument[i] = float(i);
// copy argument from host to cuda
cudaMemcpy( pCudaArgument, // destination
pHostArgument, // source
N*sizeof(pCudaResult[0]), // amount to copy
cudaMemcpyHostToDevice); // type: host -> device
// execute in cuda
cudaFunct<<<1,SIM_THREADS>>>(pCudaArgument, pCudaResult);
// copy result from cuda to host
cudaMemcpy( pHostResult, // destination
pCudaResult, // source
N*sizeof(pCudaResult[0]), // amount to copy
cudaMemcpyDeviceToHost); // type: device -> host
for (i = 0; i < N; i++)
printf("%f\n", pHostResult[i]);
} | code for sm_80
Function : _Z9cudaFunctPfS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000e240000002100 */
/*0020*/ ISETP.GT.AND P0, PT, R6, 0x13, PT ; /* 0x000000130600780c */
/* 0x001fda0003f04270 */
/*0030*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0040*/ IMNMX R3, R6.reuse, 0xa, !PT ; /* 0x0000000a06037817 */
/* 0x040fe20007800200 */
/*0050*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0060*/ BSSY B0, 0x250 ; /* 0x000001e000007945 */
/* 0x000fe40003800000 */
/*0070*/ IADD3 R4, -R6, 0x9, R3 ; /* 0x0000000906047810 */
/* 0x000fc80007ffe103 */
/*0080*/ ISETP.GE.U32.AND P0, PT, R4.reuse, 0x1e, PT ; /* 0x0000001e0400780c */
/* 0x040fe20003f06070 */
/*0090*/ IMAD.WIDE.U32 R2, R4, -0x33333333, RZ ; /* 0xcccccccd04027825 */
/* 0x000fca00078e00ff */
/*00a0*/ LEA.HI R2, R3, 0x1, RZ, 0x1d ; /* 0x0000000103027811 */
/* 0x000fc800078fe8ff */
/*00b0*/ LOP3.LUT P1, R0, R2, 0x3, RZ, 0xc0, !PT ; /* 0x0000000302007812 */
/* 0x000fda000782c0ff */
/*00c0*/ @!P1 BRA 0x240 ; /* 0x0000017000009947 */
/* 0x000fea0003800000 */
/*00d0*/ IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; /* 0x00000004ff057424 */
/* 0x000fc800078e00ff */
/*00e0*/ IMAD.WIDE R2, R6, R5, c[0x0][0x168] ; /* 0x00005a0006027625 */
/* 0x000fc800078e0205 */
/*00f0*/ IMAD.WIDE R4, R6, R5, c[0x0][0x160] ; /* 0x0000580006047625 */
/* 0x000fe200078e0205 */
/*0100*/ MOV R10, R2 ; /* 0x00000002000a7202 */
/* 0x000fc60000000f00 */
/*0110*/ IMAD.MOV.U32 R11, RZ, RZ, R3 ; /* 0x000000ffff0b7224 */
/* 0x000fe200078e0003 */
/*0120*/ MOV R8, R4 ; /* 0x0000000400087202 */
/* 0x000fe20000000f00 */
/*0130*/ IMAD.MOV.U32 R9, RZ, RZ, R5 ; /* 0x000000ffff097224 */
/* 0x000fc600078e0005 */
/*0140*/ MOV R2, R8 ; /* 0x0000000800027202 */
/* 0x000fe20000000f00 */
/*0150*/ IMAD.MOV.U32 R3, RZ, RZ, R9 ; /* 0x000000ffff037224 */
/* 0x000fca00078e0009 */
/*0160*/ LDG.E R4, [R2.64+-0x4] ; /* 0xfffffc0402047981 */
/* 0x001ea8000c1e1900 */
/*0170*/ LDG.E R5, [R2.64] ; /* 0x0000000402057981 */
/* 0x000ea2000c1e1900 */
/*0180*/ IADD3 R0, R0, -0x1, RZ ; /* 0xffffffff00007810 */
/* 0x000fe40007ffe0ff */
/*0190*/ IADD3 R8, P3, R2, 0x28, RZ ; /* 0x0000002802087810 */
/* 0x000fe40007f7e0ff */
/*01a0*/ ISETP.NE.AND P1, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe40003f25270 */
/*01b0*/ IADD3.X R9, RZ, R3, RZ, P3, !PT ; /* 0x00000003ff097210 */
/* 0x000fc40001ffe4ff */
/*01c0*/ IADD3 R6, R6, 0xa, RZ ; /* 0x0000000a06067810 */
/* 0x000fe20007ffe0ff */
/*01d0*/ FADD R7, -R4, R5 ; /* 0x0000000504077221 */
/* 0x004fe20000000100 */
/*01e0*/ MOV R4, R10 ; /* 0x0000000a00047202 */
/* 0x000fe20000000f00 */
/*01f0*/ IMAD.MOV.U32 R5, RZ, RZ, R11 ; /* 0x000000ffff057224 */
/* 0x000fe200078e000b */
/*0200*/ IADD3 R10, P2, R10, 0x28, RZ ; /* 0x000000280a0a7810 */
/* 0x000fc80007f5e0ff */
/*0210*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x0001e2000c101904 */
/*0220*/ IMAD.X R11, RZ, RZ, R11, P2 ; /* 0x000000ffff0b7224 */
/* 0x000fe200010e060b */
/*0230*/ @P1 BRA 0x140 ; /* 0xffffff0000001947 */
/* 0x000fea000383ffff */
/*0240*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0250*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0260*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0270*/ IADD3 R0, R6.reuse, -0x28, RZ ; /* 0xffffffd806007810 */
/* 0x040fe20007ffe0ff */
/*0280*/ BSSY B0, 0x800 ; /* 0x0000057000007945 */
/* 0x000ff00003800000 */
/*0290*/ IMAD.WIDE R4, R6, R3, c[0x0][0x160] ; /* 0x0000580006047625 */
/* 0x001fc800078e0203 */
/*02a0*/ IMAD.WIDE R2, R6, R3, c[0x0][0x168] ; /* 0x00005a0006027625 */
/* 0x000fe200078e0203 */
/*02b0*/ IADD3 R6, -R0, -0x14, RZ ; /* 0xffffffec00067810 */
/* 0x000fe40007ffe1ff */
/*02c0*/ IADD3 R4, P0, R4, 0x4c, RZ ; /* 0x0000004c04047810 */
/* 0x000fe40007f1e0ff */
/*02d0*/ ISETP.GT.AND P1, PT, R6, 0x78, PT ; /* 0x000000780600780c */
/* 0x000fe40003f24270 */
/*02e0*/ IADD3 R2, P2, R2, 0x50, RZ ; /* 0x0000005002027810 */
/* 0x000fe20007f5e0ff */
/*02f0*/ IMAD.X R5, RZ, RZ, R5, P0 ; /* 0x000000ffff057224 */
/* 0x000fe200000e0605 */
/*0300*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0f070 */
/*0310*/ IADD3.X R3, RZ, R3, RZ, P2, !PT ; /* 0x00000003ff037210 */
/* 0x000fce00017fe4ff */
/*0320*/ @!P1 BRA 0x7f0 ; /* 0x000004c000009947 */
/* 0x000fea0003800000 */
/*0330*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0340*/ LDG.E R6, [R4.64+-0x50] ; /* 0xffffb00404067981 */
/* 0x000ea8000c1e1900 */
/*0350*/ LDG.E R7, [R4.64+-0x4c] ; /* 0xffffb40404077981 */
/* 0x000ea4000c1e1900 */
/*0360*/ FADD R7, -R6, R7 ; /* 0x0000000706077221 */
/* 0x004fca0000000100 */
/*0370*/ STG.E [R2.64+-0x50], R7 ; /* 0xffffb00702007986 */
/* 0x0001e8000c101904 */
/*0380*/ LDG.E R6, [R4.64+-0x28] ; /* 0xffffd80404067981 */
/* 0x000ea8000c1e1900 */
/*0390*/ LDG.E R9, [R4.64+-0x24] ; /* 0xffffdc0404097981 */
/* 0x000ea4000c1e1900 */
/*03a0*/ FADD R9, -R6, R9 ; /* 0x0000000906097221 */
/* 0x004fca0000000100 */
/*03b0*/ STG.E [R2.64+-0x28], R9 ; /* 0xffffd80902007986 */
/* 0x0003e8000c101904 */
/*03c0*/ LDG.E R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000ea8000c1e1900 */
/*03d0*/ LDG.E R11, [R4.64+0x4] ; /* 0x00000404040b7981 */
/* 0x000ea4000c1e1900 */
/*03e0*/ FADD R11, -R6, R11 ; /* 0x0000000b060b7221 */
/* 0x004fca0000000100 */
/*03f0*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x0005e8000c101904 */
/*0400*/ LDG.E R6, [R4.64+0x28] ; /* 0x0000280404067981 */
/* 0x000ee8000c1e1900 */
/*0410*/ LDG.E R13, [R4.64+0x2c] ; /* 0x00002c04040d7981 */
/* 0x000ee4000c1e1900 */
/*0420*/ FADD R13, -R6, R13 ; /* 0x0000000d060d7221 */
/* 0x008fca0000000100 */
/*0430*/ STG.E [R2.64+0x28], R13 ; /* 0x0000280d02007986 */
/* 0x0007e8000c101904 */
/*0440*/ LDG.E R6, [R4.64+0x50] ; /* 0x0000500404067981 */
/* 0x000f28000c1e1900 */
/*0450*/ LDG.E R7, [R4.64+0x54] ; /* 0x0000540404077981 */
/* 0x001f24000c1e1900 */
/*0460*/ FADD R7, -R6, R7 ; /* 0x0000000706077221 */
/* 0x010fca0000000100 */
/*0470*/ STG.E [R2.64+0x50], R7 ; /* 0x0000500702007986 */
/* 0x0001e8000c101904 */
/*0480*/ LDG.E R6, [R4.64+0x78] ; /* 0x0000780404067981 */
/* 0x000f28000c1e1900 */
/*0490*/ LDG.E R9, [R4.64+0x7c] ; /* 0x00007c0404097981 */
/* 0x002f24000c1e1900 */
/*04a0*/ FADD R9, -R6, R9 ; /* 0x0000000906097221 */
/* 0x010fca0000000100 */
/*04b0*/ STG.E [R2.64+0x78], R9 ; /* 0x0000780902007986 */
/* 0x0003e8000c101904 */
/*04c0*/ LDG.E R6, [R4.64+0xa0] ; /* 0x0000a00404067981 */
/* 0x000f28000c1e1900 */
/*04d0*/ LDG.E R11, [R4.64+0xa4] ; /* 0x0000a404040b7981 */
/* 0x004f24000c1e1900 */
/*04e0*/ FADD R11, -R6, R11 ; /* 0x0000000b060b7221 */
/* 0x010fca0000000100 */
/*04f0*/ STG.E [R2.64+0xa0], R11 ; /* 0x0000a00b02007986 */
/* 0x0005e8000c101904 */
/*0500*/ LDG.E R6, [R4.64+0xc8] ; /* 0x0000c80404067981 */
/* 0x000f28000c1e1900 */
/*0510*/ LDG.E R13, [R4.64+0xcc] ; /* 0x0000cc04040d7981 */
/* 0x008f24000c1e1900 */
/*0520*/ FADD R13, -R6, R13 ; /* 0x0000000d060d7221 */
/* 0x010fca0000000100 */
/*0530*/ STG.E [R2.64+0xc8], R13 ; /* 0x0000c80d02007986 */
/* 0x0007e8000c101904 */
/*0540*/ LDG.E R6, [R4.64+0xf0] ; /* 0x0000f00404067981 */
/* 0x000f28000c1e1900 */
/*0550*/ LDG.E R7, [R4.64+0xf4] ; /* 0x0000f40404077981 */
/* 0x001f24000c1e1900 */
/*0560*/ FADD R7, -R6, R7 ; /* 0x0000000706077221 */
/* 0x010fca0000000100 */
/*0570*/ STG.E [R2.64+0xf0], R7 ; /* 0x0000f00702007986 */
/* 0x0001e8000c101904 */
/*0580*/ LDG.E R6, [R4.64+0x118] ; /* 0x0001180404067981 */
/* 0x000f28000c1e1900 */
/*0590*/ LDG.E R9, [R4.64+0x11c] ; /* 0x00011c0404097981 */
/* 0x002f24000c1e1900 */
/*05a0*/ FADD R9, -R6, R9 ; /* 0x0000000906097221 */
/* 0x010fca0000000100 */
/*05b0*/ STG.E [R2.64+0x118], R9 ; /* 0x0001180902007986 */
/* 0x0003e8000c101904 */
/*05c0*/ LDG.E R6, [R4.64+0x140] ; /* 0x0001400404067981 */
/* 0x000f28000c1e1900 */
/*05d0*/ LDG.E R11, [R4.64+0x144] ; /* 0x00014404040b7981 */
/* 0x004f24000c1e1900 */
/*05e0*/ FADD R11, -R6, R11 ; /* 0x0000000b060b7221 */
/* 0x010fca0000000100 */
/*05f0*/ STG.E [R2.64+0x140], R11 ; /* 0x0001400b02007986 */
/* 0x0005e8000c101904 */
/*0600*/ LDG.E R6, [R4.64+0x168] ; /* 0x0001680404067981 */
/* 0x000f28000c1e1900 */
/*0610*/ LDG.E R13, [R4.64+0x16c] ; /* 0x00016c04040d7981 */
/* 0x008f24000c1e1900 */
/*0620*/ FADD R13, -R6, R13 ; /* 0x0000000d060d7221 */
/* 0x010fca0000000100 */
/*0630*/ STG.E [R2.64+0x168], R13 ; /* 0x0001680d02007986 */
/* 0x0007e8000c101904 */
/*0640*/ LDG.E R6, [R4.64+0x190] ; /* 0x0001900404067981 */
/* 0x000f28000c1e1900 */
/*0650*/ LDG.E R7, [R4.64+0x194] ; /* 0x0001940404077981 */
/* 0x001f24000c1e1900 */
/*0660*/ FADD R7, -R6, R7 ; /* 0x0000000706077221 */
/* 0x010fca0000000100 */
/*0670*/ STG.E [R2.64+0x190], R7 ; /* 0x0001900702007986 */
/* 0x000fe8000c101904 */
/*0680*/ LDG.E R6, [R4.64+0x1b8] ; /* 0x0001b80404067981 */
/* 0x000f28000c1e1900 */
/*0690*/ LDG.E R9, [R4.64+0x1bc] ; /* 0x0001bc0404097981 */
/* 0x002f24000c1e1900 */
/*06a0*/ FADD R9, -R6, R9 ; /* 0x0000000906097221 */
/* 0x010fca0000000100 */
/*06b0*/ STG.E [R2.64+0x1b8], R9 ; /* 0x0001b80902007986 */
/* 0x0001e8000c101904 */
/*06c0*/ LDG.E R6, [R4.64+0x1e0] ; /* 0x0001e00404067981 */
/* 0x000f28000c1e1900 */
/*06d0*/ LDG.E R11, [R4.64+0x1e4] ; /* 0x0001e404040b7981 */
/* 0x004f22000c1e1900 */
/*06e0*/ IADD3 R0, R0, 0xa0, RZ ; /* 0x000000a000007810 */
/* 0x000fe20007ffe0ff */
/*06f0*/ FADD R11, -R6, R11 ; /* 0x0000000b060b7221 */
/* 0x010fca0000000100 */
/*0700*/ STG.E [R2.64+0x1e0], R11 ; /* 0x0001e00b02007986 */
/* 0x000fe8000c101904 */
/*0710*/ LDG.E R6, [R4.64+0x208] ; /* 0x0002080404067981 */
/* 0x0002a8000c1e1900 */
/*0720*/ LDG.E R13, [R4.64+0x20c] ; /* 0x00020c04040d7981 */
/* 0x0082a2000c1e1900 */
/*0730*/ ISETP.GE.AND P1, PT, R0, -0x8c, PT ; /* 0xffffff740000780c */
/* 0x000fe40003f26270 */
/*0740*/ IADD3 R8, P2, R4, 0x280, RZ ; /* 0x0000028004087810 */
/* 0x000fca0007f5e0ff */
/*0750*/ IMAD.X R9, RZ, RZ, R5, P2 ; /* 0x000000ffff097224 */
/* 0x001fe200010e0605 */
/*0760*/ MOV R4, R8 ; /* 0x0000000800047202 */
/* 0x002fc60000000f00 */
/*0770*/ IMAD.MOV.U32 R5, RZ, RZ, R9 ; /* 0x000000ffff057224 */
/* 0x000fe400078e0009 */
/*0780*/ FADD R13, -R6, R13 ; /* 0x0000000d060d7221 */
/* 0x004fe20000000100 */
/*0790*/ IADD3 R6, P3, R2, 0x280, RZ ; /* 0x0000028002067810 */
/* 0x000fc80007f7e0ff */
/*07a0*/ IADD3.X R7, RZ, R3, RZ, P3, !PT ; /* 0x00000003ff077210 */
/* 0x000fe20001ffe4ff */
/*07b0*/ STG.E [R2.64+0x208], R13 ; /* 0x0002080d02007986 */
/* 0x0001e4000c101904 */
/*07c0*/ MOV R2, R6 ; /* 0x0000000600027202 */
/* 0x001fe40000000f00 */
/*07d0*/ MOV R3, R7 ; /* 0x0000000700037202 */
/* 0x000fe20000000f00 */
/*07e0*/ @!P1 BRA 0x340 ; /* 0xfffffb5000009947 */
/* 0x000fea000383ffff */
/*07f0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0800*/ IADD3 R6, -R0, -0x14, RZ ; /* 0xffffffec00067810 */
/* 0x000fe20007ffe1ff */
/*0810*/ BSSY B0, 0xaf0 ; /* 0x000002d000007945 */
/* 0x000fe60003800000 */
/*0820*/ ISETP.GT.AND P1, PT, R6, 0x28, PT ; /* 0x000000280600780c */
/* 0x000fda0003f24270 */
/*0830*/ @!P1 BRA 0xae0 ; /* 0x000002a000009947 */
/* 0x000fea0003800000 */
/*0840*/ LDG.E R6, [R4.64+-0x50] ; /* 0xffffb00404067981 */
/* 0x000ea8000c1e1900 */
/*0850*/ LDG.E R7, [R4.64+-0x4c] ; /* 0xffffb40404077981 */
/* 0x000ea4000c1e1900 */
/*0860*/ FADD R7, -R6, R7 ; /* 0x0000000706077221 */
/* 0x004fca0000000100 */
/*0870*/ STG.E [R2.64+-0x50], R7 ; /* 0xffffb00702007986 */
/* 0x0001e8000c101904 */
/*0880*/ LDG.E R6, [R4.64+-0x28] ; /* 0xffffd80404067981 */
/* 0x000ea8000c1e1900 */
/*0890*/ LDG.E R9, [R4.64+-0x24] ; /* 0xffffdc0404097981 */
/* 0x000ea4000c1e1900 */
/*08a0*/ FADD R9, -R6, R9 ; /* 0x0000000906097221 */
/* 0x004fca0000000100 */
/*08b0*/ STG.E [R2.64+-0x28], R9 ; /* 0xffffd80902007986 */
/* 0x0003e8000c101904 */
/*08c0*/ LDG.E R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000ea8000c1e1900 */
/*08d0*/ LDG.E R11, [R4.64+0x4] ; /* 0x00000404040b7981 */
/* 0x000ea4000c1e1900 */
/*08e0*/ FADD R11, -R6, R11 ; /* 0x0000000b060b7221 */
/* 0x004fca0000000100 */
/*08f0*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x0005e8000c101904 */
/*0900*/ LDG.E R6, [R4.64+0x28] ; /* 0x0000280404067981 */
/* 0x000ee8000c1e1900 */
/*0910*/ LDG.E R13, [R4.64+0x2c] ; /* 0x00002c04040d7981 */
/* 0x000ee4000c1e1900 */
/*0920*/ FADD R13, -R6, R13 ; /* 0x0000000d060d7221 */
/* 0x008fca0000000100 */
/*0930*/ STG.E [R2.64+0x28], R13 ; /* 0x0000280d02007986 */
/* 0x0007e8000c101904 */
/*0940*/ LDG.E R6, [R4.64+0x50] ; /* 0x0000500404067981 */
/* 0x000f28000c1e1900 */
/*0950*/ LDG.E R7, [R4.64+0x54] ; /* 0x0000540404077981 */
/* 0x001f24000c1e1900 */
/*0960*/ FADD R7, -R6, R7 ; /* 0x0000000706077221 */
/* 0x010fca0000000100 */
/*0970*/ STG.E [R2.64+0x50], R7 ; /* 0x0000500702007986 */
/* 0x000fe8000c101904 */
/*0980*/ LDG.E R6, [R4.64+0x78] ; /* 0x0000780404067981 */
/* 0x000f28000c1e1900 */
/*0990*/ LDG.E R9, [R4.64+0x7c] ; /* 0x00007c0404097981 */
/* 0x002f24000c1e1900 */
/*09a0*/ FADD R9, -R6, R9 ; /* 0x0000000906097221 */
/* 0x010fca0000000100 */
/*09b0*/ STG.E [R2.64+0x78], R9 ; /* 0x0000780902007986 */
/* 0x0001e8000c101904 */
/*09c0*/ LDG.E R6, [R4.64+0xa0] ; /* 0x0000a00404067981 */
/* 0x000f28000c1e1900 */
/*09d0*/ LDG.E R11, [R4.64+0xa4] ; /* 0x0000a404040b7981 */
/* 0x004f24000c1e1900 */
/*09e0*/ FADD R11, -R6, R11 ; /* 0x0000000b060b7221 */
/* 0x010fca0000000100 */
/*09f0*/ STG.E [R2.64+0xa0], R11 ; /* 0x0000a00b02007986 */
/* 0x000fe8000c101904 */
/*0a00*/ LDG.E R6, [R4.64+0xc8] ; /* 0x0000c80404067981 */
/* 0x0002a8000c1e1900 */
/*0a10*/ LDG.E R13, [R4.64+0xcc] ; /* 0x0000cc04040d7981 */
/* 0x0082a2000c1e1900 */
/*0a20*/ IADD3 R8, P1, R4, 0x140, RZ ; /* 0x0000014004087810 */
/* 0x000fe40007f3e0ff */
/*0a30*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc40003f0e170 */
/*0a40*/ IADD3 R0, R0, 0x50, RZ ; /* 0x0000005000007810 */
/* 0x000fe20007ffe0ff */
/*0a50*/ IMAD.X R9, RZ, RZ, R5, P1 ; /* 0x000000ffff097224 */
/* 0x001fe200008e0605 */
/*0a60*/ MOV R4, R8 ; /* 0x0000000800047202 */
/* 0x002fc60000000f00 */
/*0a70*/ IMAD.MOV.U32 R5, RZ, RZ, R9 ; /* 0x000000ffff057224 */
/* 0x000fe400078e0009 */
/*0a80*/ FADD R13, -R6, R13 ; /* 0x0000000d060d7221 */
/* 0x004fe20000000100 */
/*0a90*/ IADD3 R6, P2, R2, 0x140, RZ ; /* 0x0000014002067810 */
/* 0x000fc80007f5e0ff */
/*0aa0*/ IADD3.X R7, RZ, R3, RZ, P2, !PT ; /* 0x00000003ff077210 */
/* 0x000fe200017fe4ff */
/*0ab0*/ STG.E [R2.64+0xc8], R13 ; /* 0x0000c80d02007986 */
/* 0x0001e4000c101904 */
/*0ac0*/ MOV R2, R6 ; /* 0x0000000600027202 */
/* 0x001fe40000000f00 */
/*0ad0*/ MOV R3, R7 ; /* 0x0000000700037202 */
/* 0x000fe40000000f00 */
/*0ae0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0af0*/ ISETP.LT.OR P0, PT, R0, -0x14, P0 ; /* 0xffffffec0000780c */
/* 0x000fda0000701670 */
/*0b00*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0b10*/ LDG.E R0, [R4.64+-0x50] ; /* 0xffffb00404007981 */
/* 0x000ea8000c1e1900 */
/*0b20*/ LDG.E R7, [R4.64+-0x4c] ; /* 0xffffb40404077981 */
/* 0x000ea4000c1e1900 */
/*0b30*/ FADD R7, -R0, R7 ; /* 0x0000000700077221 */
/* 0x004fca0000000100 */
/*0b40*/ STG.E [R2.64+-0x50], R7 ; /* 0xffffb00702007986 */
/* 0x000fe8000c101904 */
/*0b50*/ LDG.E R0, [R4.64+-0x28] ; /* 0xffffd80404007981 */
/* 0x000ea8000c1e1900 */
/*0b60*/ LDG.E R9, [R4.64+-0x24] ; /* 0xffffdc0404097981 */
/* 0x000ea4000c1e1900 */
/*0b70*/ FADD R9, -R0, R9 ; /* 0x0000000900097221 */
/* 0x004fca0000000100 */
/*0b80*/ STG.E [R2.64+-0x28], R9 ; /* 0xffffd80902007986 */
/* 0x000fe8000c101904 */
/*0b90*/ LDG.E R0, [R4.64] ; /* 0x0000000404007981 */
/* 0x000ea8000c1e1900 */
/*0ba0*/ LDG.E R11, [R4.64+0x4] ; /* 0x00000404040b7981 */
/* 0x000ea4000c1e1900 */
/*0bb0*/ FADD R11, -R0, R11 ; /* 0x0000000b000b7221 */
/* 0x004fca0000000100 */
/*0bc0*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x000fe8000c101904 */
/*0bd0*/ LDG.E R0, [R4.64+0x28] ; /* 0x0000280404007981 */
/* 0x000ea8000c1e1900 */
/*0be0*/ LDG.E R13, [R4.64+0x2c] ; /* 0x00002c04040d7981 */
/* 0x000ea4000c1e1900 */
/*0bf0*/ FADD R13, -R0, R13 ; /* 0x0000000d000d7221 */
/* 0x004fca0000000100 */
/*0c00*/ STG.E [R2.64+0x28], R13 ; /* 0x0000280d02007986 */
/* 0x000fe2000c101904 */
/*0c10*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0c20*/ BRA 0xc20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0c30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ca0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ce0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <cuda.h>
#define SIM_THREADS 10 // how many simultaneus threads
#define N 20 // number of variables in a vector
// this function returns a result
__global__ void cudaFunct(float *pArgument, float *pResult)
{
int i;
// this loop will do sequences:
// i = 0, 10, 20, ...
// i = 1, 11, 21, ...
// i = 2, 12, 22, ...
// ...
// i = 9, 19, 29, ...
//
// assuming SIM_THREADS = 10
for ( i = threadIdx.x; // start from i = thread ID
i < N; // stop if all i's are done
i += SIM_THREADS) // skip number of threads
pResult[i] = pArgument[i] -pArgument[i-1];
}
int main(void)
{
float *pHostArgument;
float *pCudaArgument = 0;
float *pHostResult;
float *pCudaResult = 0;
int i;
// reserve memory in host system
pHostArgument = (float *)malloc(N*sizeof(pHostArgument[0]));
pHostResult = (float *) malloc(N*sizeof(pHostResult[0]));
// reserve memory in cuda
cudaMalloc((void **) &pCudaArgument, N*sizeof(pCudaResult[0]));
cudaMalloc((void **) &pCudaResult, N*sizeof(pCudaResult[0]));
// initialize argument
for (i = 0; i < N; i++) pHostArgument[i] = float(i);
// copy argument from host to cuda
cudaMemcpy( pCudaArgument, // destination
pHostArgument, // source
N*sizeof(pCudaResult[0]), // amount to copy
cudaMemcpyHostToDevice); // type: host -> device
// execute in cuda
cudaFunct<<<1,SIM_THREADS>>>(pCudaArgument, pCudaResult);
// copy result from cuda to host
cudaMemcpy( pHostResult, // destination
pCudaResult, // source
N*sizeof(pCudaResult[0]), // amount to copy
cudaMemcpyDeviceToHost); // type: device -> host
for (i = 0; i < N; i++)
printf("%f\n", pHostResult[i]);
} | .file "tmpxft_00017ff0_00000000-6_simpleCuda3.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z30__device_stub__Z9cudaFunctPfS_PfS_
.type _Z30__device_stub__Z9cudaFunctPfS_PfS_, @function
_Z30__device_stub__Z9cudaFunctPfS_PfS_:
.LFB2082:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z9cudaFunctPfS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z30__device_stub__Z9cudaFunctPfS_PfS_, .-_Z30__device_stub__Z9cudaFunctPfS_PfS_
.globl _Z9cudaFunctPfS_
.type _Z9cudaFunctPfS_, @function
_Z9cudaFunctPfS_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z9cudaFunctPfS_PfS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z9cudaFunctPfS_, .-_Z9cudaFunctPfS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%f\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $48, %rsp
.cfi_def_cfa_offset 80
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movq $0, (%rsp)
movq $0, 8(%rsp)
movl $80, %edi
call malloc@PLT
movq %rax, %rbx
movl $80, %edi
call malloc@PLT
movq %rax, %rbp
movq %rsp, %rdi
movl $80, %esi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movl $80, %esi
call cudaMalloc@PLT
movl $0, %eax
.L12:
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, (%rbx,%rax,4)
addq $1, %rax
cmpq $20, %rax
jne .L12
movl $1, %ecx
movl $80, %edx
movq %rbx, %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
movl $10, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L19
.L13:
movl $2, %ecx
movl $80, %edx
movq 8(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
movq %rbp, %rbx
addq $80, %rbp
leaq .LC0(%rip), %r12
.L14:
pxor %xmm0, %xmm0
cvtss2sd (%rbx), %xmm0
movq %r12, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %rbp, %rbx
jne .L14
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L20
movl $0, %eax
addq $48, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z30__device_stub__Z9cudaFunctPfS_PfS_
jmp .L13
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z9cudaFunctPfS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z9cudaFunctPfS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <cuda.h>
#define SIM_THREADS 10 // how many simultaneus threads
#define N 20 // number of variables in a vector
// this function returns a result
__global__ void cudaFunct(float *pArgument, float *pResult)
{
int i;
// this loop will do sequences:
// i = 0, 10, 20, ...
// i = 1, 11, 21, ...
// i = 2, 12, 22, ...
// ...
// i = 9, 19, 29, ...
//
// assuming SIM_THREADS = 10
for ( i = threadIdx.x; // start from i = thread ID
i < N; // stop if all i's are done
i += SIM_THREADS) // skip number of threads
pResult[i] = pArgument[i] -pArgument[i-1];
}
int main(void)
{
float *pHostArgument;
float *pCudaArgument = 0;
float *pHostResult;
float *pCudaResult = 0;
int i;
// reserve memory in host system
pHostArgument = (float *)malloc(N*sizeof(pHostArgument[0]));
pHostResult = (float *) malloc(N*sizeof(pHostResult[0]));
// reserve memory in cuda
cudaMalloc((void **) &pCudaArgument, N*sizeof(pCudaResult[0]));
cudaMalloc((void **) &pCudaResult, N*sizeof(pCudaResult[0]));
// initialize argument
for (i = 0; i < N; i++) pHostArgument[i] = float(i);
// copy argument from host to cuda
cudaMemcpy( pCudaArgument, // destination
pHostArgument, // source
N*sizeof(pCudaResult[0]), // amount to copy
cudaMemcpyHostToDevice); // type: host -> device
// execute in cuda
cudaFunct<<<1,SIM_THREADS>>>(pCudaArgument, pCudaResult);
// copy result from cuda to host
cudaMemcpy( pHostResult, // destination
pCudaResult, // source
N*sizeof(pCudaResult[0]), // amount to copy
cudaMemcpyDeviceToHost); // type: device -> host
for (i = 0; i < N; i++)
printf("%f\n", pHostResult[i]);
} | #include <stdio.h>
#include <hip/hip_runtime.h>
#define SIM_THREADS 10 // how many simultaneus threads
#define N 20 // number of variables in a vector
// this function returns a result
__global__ void cudaFunct(float *pArgument, float *pResult)
{
int i;
// this loop will do sequences:
// i = 0, 10, 20, ...
// i = 1, 11, 21, ...
// i = 2, 12, 22, ...
// ...
// i = 9, 19, 29, ...
//
// assuming SIM_THREADS = 10
for ( i = threadIdx.x; // start from i = thread ID
i < N; // stop if all i's are done
i += SIM_THREADS) // skip number of threads
pResult[i] = pArgument[i] -pArgument[i-1];
}
int main(void)
{
float *pHostArgument;
float *pCudaArgument = 0;
float *pHostResult;
float *pCudaResult = 0;
int i;
// reserve memory in host system
pHostArgument = (float *)malloc(N*sizeof(pHostArgument[0]));
pHostResult = (float *) malloc(N*sizeof(pHostResult[0]));
// reserve memory in cuda
hipMalloc((void **) &pCudaArgument, N*sizeof(pCudaResult[0]));
hipMalloc((void **) &pCudaResult, N*sizeof(pCudaResult[0]));
// initialize argument
for (i = 0; i < N; i++) pHostArgument[i] = float(i);
// copy argument from host to cuda
hipMemcpy( pCudaArgument, // destination
pHostArgument, // source
N*sizeof(pCudaResult[0]), // amount to copy
hipMemcpyHostToDevice); // type: host -> device
// execute in cuda
cudaFunct<<<1,SIM_THREADS>>>(pCudaArgument, pCudaResult);
// copy result from cuda to host
hipMemcpy( pHostResult, // destination
pCudaResult, // source
N*sizeof(pCudaResult[0]), // amount to copy
hipMemcpyDeviceToHost); // type: device -> host
for (i = 0; i < N; i++)
printf("%f\n", pHostResult[i]);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <stdio.h>
#include <hip/hip_runtime.h>
#define SIM_THREADS 10 // how many simultaneus threads
#define N 20 // number of variables in a vector
// this function returns a result
__global__ void cudaFunct(float *pArgument, float *pResult)
{
int i;
// this loop will do sequences:
// i = 0, 10, 20, ...
// i = 1, 11, 21, ...
// i = 2, 12, 22, ...
// ...
// i = 9, 19, 29, ...
//
// assuming SIM_THREADS = 10
for ( i = threadIdx.x; // start from i = thread ID
i < N; // stop if all i's are done
i += SIM_THREADS) // skip number of threads
pResult[i] = pArgument[i] -pArgument[i-1];
}
int main(void)
{
float *pHostArgument;
float *pCudaArgument = 0;
float *pHostResult;
float *pCudaResult = 0;
int i;
// reserve memory in host system
pHostArgument = (float *)malloc(N*sizeof(pHostArgument[0]));
pHostResult = (float *) malloc(N*sizeof(pHostResult[0]));
// reserve memory in cuda
hipMalloc((void **) &pCudaArgument, N*sizeof(pCudaResult[0]));
hipMalloc((void **) &pCudaResult, N*sizeof(pCudaResult[0]));
// initialize argument
for (i = 0; i < N; i++) pHostArgument[i] = float(i);
// copy argument from host to cuda
hipMemcpy( pCudaArgument, // destination
pHostArgument, // source
N*sizeof(pCudaResult[0]), // amount to copy
hipMemcpyHostToDevice); // type: host -> device
// execute in cuda
cudaFunct<<<1,SIM_THREADS>>>(pCudaArgument, pCudaResult);
// copy result from cuda to host
hipMemcpy( pHostResult, // destination
pCudaResult, // source
N*sizeof(pCudaResult[0]), // amount to copy
hipMemcpyDeviceToHost); // type: device -> host
for (i = 0; i < N; i++)
printf("%f\n", pHostResult[i]);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9cudaFunctPfS_
.globl _Z9cudaFunctPfS_
.p2align 8
.type _Z9cudaFunctPfS_,@function
_Z9cudaFunctPfS_:
s_mov_b32 s2, exec_lo
v_cmpx_gt_u32_e32 20, v0
s_cbranch_execz .LBB0_3
s_load_b128 s[0:3], s[0:1], 0x0
v_lshlrev_b32_e32 v2, 2, v0
v_add_nc_u32_e32 v4, -10, v0
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v1, s0, v2, s0
v_add_co_ci_u32_e64 v3, null, 0, s1, s0
v_add_co_u32 v2, s0, s2, v2
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v0, vcc_lo, v1, -4
v_add_co_ci_u32_e32 v1, vcc_lo, -1, v3, vcc_lo
v_add_co_ci_u32_e64 v3, null, s3, 0, s0
s_mov_b32 s0, 0
.p2align 6
.LBB0_2:
global_load_b64 v[5:6], v[0:1], off
v_add_co_u32 v0, vcc_lo, v0, 40
v_add_co_u32 v4, s1, v4, 10
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
s_xor_b32 s1, s1, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s1, exec_lo, s1
s_or_b32 s0, s1, s0
s_waitcnt vmcnt(0)
v_sub_f32_e32 v5, v6, v5
global_store_b32 v[2:3], v5, off
v_add_co_u32 v2, vcc_lo, v2, 40
v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9cudaFunctPfS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 16
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 4
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9cudaFunctPfS_, .Lfunc_end0-_Z9cudaFunctPfS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 16
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9cudaFunctPfS_
.private_segment_fixed_size: 0
.sgpr_count: 6
.sgpr_spill_count: 0
.symbol: _Z9cudaFunctPfS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <stdio.h>
#include <hip/hip_runtime.h>
#define SIM_THREADS 10 // how many simultaneus threads
#define N 20 // number of variables in a vector
// this function returns a result
__global__ void cudaFunct(float *pArgument, float *pResult)
{
int i;
// this loop will do sequences:
// i = 0, 10, 20, ...
// i = 1, 11, 21, ...
// i = 2, 12, 22, ...
// ...
// i = 9, 19, 29, ...
//
// assuming SIM_THREADS = 10
for ( i = threadIdx.x; // start from i = thread ID
i < N; // stop if all i's are done
i += SIM_THREADS) // skip number of threads
pResult[i] = pArgument[i] -pArgument[i-1];
}
int main(void)
{
float *pHostArgument;
float *pCudaArgument = 0;
float *pHostResult;
float *pCudaResult = 0;
int i;
// reserve memory in host system
pHostArgument = (float *)malloc(N*sizeof(pHostArgument[0]));
pHostResult = (float *) malloc(N*sizeof(pHostResult[0]));
// reserve memory in cuda
hipMalloc((void **) &pCudaArgument, N*sizeof(pCudaResult[0]));
hipMalloc((void **) &pCudaResult, N*sizeof(pCudaResult[0]));
// initialize argument
for (i = 0; i < N; i++) pHostArgument[i] = float(i);
// copy argument from host to cuda
hipMemcpy( pCudaArgument, // destination
pHostArgument, // source
N*sizeof(pCudaResult[0]), // amount to copy
hipMemcpyHostToDevice); // type: host -> device
// execute in cuda
cudaFunct<<<1,SIM_THREADS>>>(pCudaArgument, pCudaResult);
// copy result from cuda to host
hipMemcpy( pHostResult, // destination
pCudaResult, // source
N*sizeof(pCudaResult[0]), // amount to copy
hipMemcpyDeviceToHost); // type: device -> host
for (i = 0; i < N; i++)
printf("%f\n", pHostResult[i]);
} | .text
.file "simpleCuda3.hip"
.globl _Z24__device_stub__cudaFunctPfS_ # -- Begin function _Z24__device_stub__cudaFunctPfS_
.p2align 4, 0x90
.type _Z24__device_stub__cudaFunctPfS_,@function
_Z24__device_stub__cudaFunctPfS_: # @_Z24__device_stub__cudaFunctPfS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z9cudaFunctPfS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z24__device_stub__cudaFunctPfS_, .Lfunc_end0-_Z24__device_stub__cudaFunctPfS_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $104, %rsp
.cfi_def_cfa_offset 128
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movq $0, 8(%rsp)
movq $0, (%rsp)
movl $80, %edi
callq malloc
movq %rax, %r14
movl $80, %edi
callq malloc
movq %rax, %rbx
leaq 8(%rsp), %rdi
movl $80, %esi
callq hipMalloc
movq %rsp, %rdi
movl $80, %esi
callq hipMalloc
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, (%r14,%rax,4)
incq %rax
cmpq $20, %rax
jne .LBB1_1
# %bb.2:
movq 8(%rsp), %rdi
movl $80, %edx
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 9(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 8(%rsp), %rax
movq (%rsp), %rcx
movq %rax, 72(%rsp)
movq %rcx, 64(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9cudaFunctPfS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
movq (%rsp), %rsi
movl $80, %edx
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB1_5: # =>This Inner Loop Header: Depth=1
movss (%rbx,%r14,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
incq %r14
cmpq $20, %r14
jne .LBB1_5
# %bb.6:
xorl %eax, %eax
addq $104, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9cudaFunctPfS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9cudaFunctPfS_,@object # @_Z9cudaFunctPfS_
.section .rodata,"a",@progbits
.globl _Z9cudaFunctPfS_
.p2align 3, 0x0
_Z9cudaFunctPfS_:
.quad _Z24__device_stub__cudaFunctPfS_
.size _Z9cudaFunctPfS_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%f\n"
.size .L.str, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z9cudaFunctPfS_"
.size .L__unnamed_1, 17
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__cudaFunctPfS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9cudaFunctPfS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z9cudaFunctPfS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000e240000002100 */
/*0020*/ ISETP.GT.AND P0, PT, R6, 0x13, PT ; /* 0x000000130600780c */
/* 0x001fda0003f04270 */
/*0030*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0040*/ IMNMX R3, R6.reuse, 0xa, !PT ; /* 0x0000000a06037817 */
/* 0x040fe20007800200 */
/*0050*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0060*/ BSSY B0, 0x250 ; /* 0x000001e000007945 */
/* 0x000fe40003800000 */
/*0070*/ IADD3 R4, -R6, 0x9, R3 ; /* 0x0000000906047810 */
/* 0x000fc80007ffe103 */
/*0080*/ ISETP.GE.U32.AND P0, PT, R4.reuse, 0x1e, PT ; /* 0x0000001e0400780c */
/* 0x040fe20003f06070 */
/*0090*/ IMAD.WIDE.U32 R2, R4, -0x33333333, RZ ; /* 0xcccccccd04027825 */
/* 0x000fca00078e00ff */
/*00a0*/ LEA.HI R2, R3, 0x1, RZ, 0x1d ; /* 0x0000000103027811 */
/* 0x000fc800078fe8ff */
/*00b0*/ LOP3.LUT P1, R0, R2, 0x3, RZ, 0xc0, !PT ; /* 0x0000000302007812 */
/* 0x000fda000782c0ff */
/*00c0*/ @!P1 BRA 0x240 ; /* 0x0000017000009947 */
/* 0x000fea0003800000 */
/*00d0*/ IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; /* 0x00000004ff057424 */
/* 0x000fc800078e00ff */
/*00e0*/ IMAD.WIDE R2, R6, R5, c[0x0][0x168] ; /* 0x00005a0006027625 */
/* 0x000fc800078e0205 */
/*00f0*/ IMAD.WIDE R4, R6, R5, c[0x0][0x160] ; /* 0x0000580006047625 */
/* 0x000fe200078e0205 */
/*0100*/ MOV R10, R2 ; /* 0x00000002000a7202 */
/* 0x000fc60000000f00 */
/*0110*/ IMAD.MOV.U32 R11, RZ, RZ, R3 ; /* 0x000000ffff0b7224 */
/* 0x000fe200078e0003 */
/*0120*/ MOV R8, R4 ; /* 0x0000000400087202 */
/* 0x000fe20000000f00 */
/*0130*/ IMAD.MOV.U32 R9, RZ, RZ, R5 ; /* 0x000000ffff097224 */
/* 0x000fc600078e0005 */
/*0140*/ MOV R2, R8 ; /* 0x0000000800027202 */
/* 0x000fe20000000f00 */
/*0150*/ IMAD.MOV.U32 R3, RZ, RZ, R9 ; /* 0x000000ffff037224 */
/* 0x000fca00078e0009 */
/*0160*/ LDG.E R4, [R2.64+-0x4] ; /* 0xfffffc0402047981 */
/* 0x001ea8000c1e1900 */
/*0170*/ LDG.E R5, [R2.64] ; /* 0x0000000402057981 */
/* 0x000ea2000c1e1900 */
/*0180*/ IADD3 R0, R0, -0x1, RZ ; /* 0xffffffff00007810 */
/* 0x000fe40007ffe0ff */
/*0190*/ IADD3 R8, P3, R2, 0x28, RZ ; /* 0x0000002802087810 */
/* 0x000fe40007f7e0ff */
/*01a0*/ ISETP.NE.AND P1, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe40003f25270 */
/*01b0*/ IADD3.X R9, RZ, R3, RZ, P3, !PT ; /* 0x00000003ff097210 */
/* 0x000fc40001ffe4ff */
/*01c0*/ IADD3 R6, R6, 0xa, RZ ; /* 0x0000000a06067810 */
/* 0x000fe20007ffe0ff */
/*01d0*/ FADD R7, -R4, R5 ; /* 0x0000000504077221 */
/* 0x004fe20000000100 */
/*01e0*/ MOV R4, R10 ; /* 0x0000000a00047202 */
/* 0x000fe20000000f00 */
/*01f0*/ IMAD.MOV.U32 R5, RZ, RZ, R11 ; /* 0x000000ffff057224 */
/* 0x000fe200078e000b */
/*0200*/ IADD3 R10, P2, R10, 0x28, RZ ; /* 0x000000280a0a7810 */
/* 0x000fc80007f5e0ff */
/*0210*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x0001e2000c101904 */
/*0220*/ IMAD.X R11, RZ, RZ, R11, P2 ; /* 0x000000ffff0b7224 */
/* 0x000fe200010e060b */
/*0230*/ @P1 BRA 0x140 ; /* 0xffffff0000001947 */
/* 0x000fea000383ffff */
/*0240*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0250*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0260*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0270*/ IADD3 R0, R6.reuse, -0x28, RZ ; /* 0xffffffd806007810 */
/* 0x040fe20007ffe0ff */
/*0280*/ BSSY B0, 0x800 ; /* 0x0000057000007945 */
/* 0x000ff00003800000 */
/*0290*/ IMAD.WIDE R4, R6, R3, c[0x0][0x160] ; /* 0x0000580006047625 */
/* 0x001fc800078e0203 */
/*02a0*/ IMAD.WIDE R2, R6, R3, c[0x0][0x168] ; /* 0x00005a0006027625 */
/* 0x000fe200078e0203 */
/*02b0*/ IADD3 R6, -R0, -0x14, RZ ; /* 0xffffffec00067810 */
/* 0x000fe40007ffe1ff */
/*02c0*/ IADD3 R4, P0, R4, 0x4c, RZ ; /* 0x0000004c04047810 */
/* 0x000fe40007f1e0ff */
/*02d0*/ ISETP.GT.AND P1, PT, R6, 0x78, PT ; /* 0x000000780600780c */
/* 0x000fe40003f24270 */
/*02e0*/ IADD3 R2, P2, R2, 0x50, RZ ; /* 0x0000005002027810 */
/* 0x000fe20007f5e0ff */
/*02f0*/ IMAD.X R5, RZ, RZ, R5, P0 ; /* 0x000000ffff057224 */
/* 0x000fe200000e0605 */
/*0300*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0f070 */
/*0310*/ IADD3.X R3, RZ, R3, RZ, P2, !PT ; /* 0x00000003ff037210 */
/* 0x000fce00017fe4ff */
/*0320*/ @!P1 BRA 0x7f0 ; /* 0x000004c000009947 */
/* 0x000fea0003800000 */
/*0330*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0340*/ LDG.E R6, [R4.64+-0x50] ; /* 0xffffb00404067981 */
/* 0x000ea8000c1e1900 */
/*0350*/ LDG.E R7, [R4.64+-0x4c] ; /* 0xffffb40404077981 */
/* 0x000ea4000c1e1900 */
/*0360*/ FADD R7, -R6, R7 ; /* 0x0000000706077221 */
/* 0x004fca0000000100 */
/*0370*/ STG.E [R2.64+-0x50], R7 ; /* 0xffffb00702007986 */
/* 0x0001e8000c101904 */
/*0380*/ LDG.E R6, [R4.64+-0x28] ; /* 0xffffd80404067981 */
/* 0x000ea8000c1e1900 */
/*0390*/ LDG.E R9, [R4.64+-0x24] ; /* 0xffffdc0404097981 */
/* 0x000ea4000c1e1900 */
/*03a0*/ FADD R9, -R6, R9 ; /* 0x0000000906097221 */
/* 0x004fca0000000100 */
/*03b0*/ STG.E [R2.64+-0x28], R9 ; /* 0xffffd80902007986 */
/* 0x0003e8000c101904 */
/*03c0*/ LDG.E R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000ea8000c1e1900 */
/*03d0*/ LDG.E R11, [R4.64+0x4] ; /* 0x00000404040b7981 */
/* 0x000ea4000c1e1900 */
/*03e0*/ FADD R11, -R6, R11 ; /* 0x0000000b060b7221 */
/* 0x004fca0000000100 */
/*03f0*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x0005e8000c101904 */
/*0400*/ LDG.E R6, [R4.64+0x28] ; /* 0x0000280404067981 */
/* 0x000ee8000c1e1900 */
/*0410*/ LDG.E R13, [R4.64+0x2c] ; /* 0x00002c04040d7981 */
/* 0x000ee4000c1e1900 */
/*0420*/ FADD R13, -R6, R13 ; /* 0x0000000d060d7221 */
/* 0x008fca0000000100 */
/*0430*/ STG.E [R2.64+0x28], R13 ; /* 0x0000280d02007986 */
/* 0x0007e8000c101904 */
/*0440*/ LDG.E R6, [R4.64+0x50] ; /* 0x0000500404067981 */
/* 0x000f28000c1e1900 */
/*0450*/ LDG.E R7, [R4.64+0x54] ; /* 0x0000540404077981 */
/* 0x001f24000c1e1900 */
/*0460*/ FADD R7, -R6, R7 ; /* 0x0000000706077221 */
/* 0x010fca0000000100 */
/*0470*/ STG.E [R2.64+0x50], R7 ; /* 0x0000500702007986 */
/* 0x0001e8000c101904 */
/*0480*/ LDG.E R6, [R4.64+0x78] ; /* 0x0000780404067981 */
/* 0x000f28000c1e1900 */
/*0490*/ LDG.E R9, [R4.64+0x7c] ; /* 0x00007c0404097981 */
/* 0x002f24000c1e1900 */
/*04a0*/ FADD R9, -R6, R9 ; /* 0x0000000906097221 */
/* 0x010fca0000000100 */
/*04b0*/ STG.E [R2.64+0x78], R9 ; /* 0x0000780902007986 */
/* 0x0003e8000c101904 */
/*04c0*/ LDG.E R6, [R4.64+0xa0] ; /* 0x0000a00404067981 */
/* 0x000f28000c1e1900 */
/*04d0*/ LDG.E R11, [R4.64+0xa4] ; /* 0x0000a404040b7981 */
/* 0x004f24000c1e1900 */
/*04e0*/ FADD R11, -R6, R11 ; /* 0x0000000b060b7221 */
/* 0x010fca0000000100 */
/*04f0*/ STG.E [R2.64+0xa0], R11 ; /* 0x0000a00b02007986 */
/* 0x0005e8000c101904 */
/*0500*/ LDG.E R6, [R4.64+0xc8] ; /* 0x0000c80404067981 */
/* 0x000f28000c1e1900 */
/*0510*/ LDG.E R13, [R4.64+0xcc] ; /* 0x0000cc04040d7981 */
/* 0x008f24000c1e1900 */
/*0520*/ FADD R13, -R6, R13 ; /* 0x0000000d060d7221 */
/* 0x010fca0000000100 */
/*0530*/ STG.E [R2.64+0xc8], R13 ; /* 0x0000c80d02007986 */
/* 0x0007e8000c101904 */
/*0540*/ LDG.E R6, [R4.64+0xf0] ; /* 0x0000f00404067981 */
/* 0x000f28000c1e1900 */
/*0550*/ LDG.E R7, [R4.64+0xf4] ; /* 0x0000f40404077981 */
/* 0x001f24000c1e1900 */
/*0560*/ FADD R7, -R6, R7 ; /* 0x0000000706077221 */
/* 0x010fca0000000100 */
/*0570*/ STG.E [R2.64+0xf0], R7 ; /* 0x0000f00702007986 */
/* 0x0001e8000c101904 */
/*0580*/ LDG.E R6, [R4.64+0x118] ; /* 0x0001180404067981 */
/* 0x000f28000c1e1900 */
/*0590*/ LDG.E R9, [R4.64+0x11c] ; /* 0x00011c0404097981 */
/* 0x002f24000c1e1900 */
/*05a0*/ FADD R9, -R6, R9 ; /* 0x0000000906097221 */
/* 0x010fca0000000100 */
/*05b0*/ STG.E [R2.64+0x118], R9 ; /* 0x0001180902007986 */
/* 0x0003e8000c101904 */
/*05c0*/ LDG.E R6, [R4.64+0x140] ; /* 0x0001400404067981 */
/* 0x000f28000c1e1900 */
/*05d0*/ LDG.E R11, [R4.64+0x144] ; /* 0x00014404040b7981 */
/* 0x004f24000c1e1900 */
/*05e0*/ FADD R11, -R6, R11 ; /* 0x0000000b060b7221 */
/* 0x010fca0000000100 */
/*05f0*/ STG.E [R2.64+0x140], R11 ; /* 0x0001400b02007986 */
/* 0x0005e8000c101904 */
/*0600*/ LDG.E R6, [R4.64+0x168] ; /* 0x0001680404067981 */
/* 0x000f28000c1e1900 */
/*0610*/ LDG.E R13, [R4.64+0x16c] ; /* 0x00016c04040d7981 */
/* 0x008f24000c1e1900 */
/*0620*/ FADD R13, -R6, R13 ; /* 0x0000000d060d7221 */
/* 0x010fca0000000100 */
/*0630*/ STG.E [R2.64+0x168], R13 ; /* 0x0001680d02007986 */
/* 0x0007e8000c101904 */
/*0640*/ LDG.E R6, [R4.64+0x190] ; /* 0x0001900404067981 */
/* 0x000f28000c1e1900 */
/*0650*/ LDG.E R7, [R4.64+0x194] ; /* 0x0001940404077981 */
/* 0x001f24000c1e1900 */
/*0660*/ FADD R7, -R6, R7 ; /* 0x0000000706077221 */
/* 0x010fca0000000100 */
/*0670*/ STG.E [R2.64+0x190], R7 ; /* 0x0001900702007986 */
/* 0x000fe8000c101904 */
/*0680*/ LDG.E R6, [R4.64+0x1b8] ; /* 0x0001b80404067981 */
/* 0x000f28000c1e1900 */
/*0690*/ LDG.E R9, [R4.64+0x1bc] ; /* 0x0001bc0404097981 */
/* 0x002f24000c1e1900 */
/*06a0*/ FADD R9, -R6, R9 ; /* 0x0000000906097221 */
/* 0x010fca0000000100 */
/*06b0*/ STG.E [R2.64+0x1b8], R9 ; /* 0x0001b80902007986 */
/* 0x0001e8000c101904 */
/*06c0*/ LDG.E R6, [R4.64+0x1e0] ; /* 0x0001e00404067981 */
/* 0x000f28000c1e1900 */
/*06d0*/ LDG.E R11, [R4.64+0x1e4] ; /* 0x0001e404040b7981 */
/* 0x004f22000c1e1900 */
/*06e0*/ IADD3 R0, R0, 0xa0, RZ ; /* 0x000000a000007810 */
/* 0x000fe20007ffe0ff */
/*06f0*/ FADD R11, -R6, R11 ; /* 0x0000000b060b7221 */
/* 0x010fca0000000100 */
/*0700*/ STG.E [R2.64+0x1e0], R11 ; /* 0x0001e00b02007986 */
/* 0x000fe8000c101904 */
/*0710*/ LDG.E R6, [R4.64+0x208] ; /* 0x0002080404067981 */
/* 0x0002a8000c1e1900 */
/*0720*/ LDG.E R13, [R4.64+0x20c] ; /* 0x00020c04040d7981 */
/* 0x0082a2000c1e1900 */
/*0730*/ ISETP.GE.AND P1, PT, R0, -0x8c, PT ; /* 0xffffff740000780c */
/* 0x000fe40003f26270 */
/*0740*/ IADD3 R8, P2, R4, 0x280, RZ ; /* 0x0000028004087810 */
/* 0x000fca0007f5e0ff */
/*0750*/ IMAD.X R9, RZ, RZ, R5, P2 ; /* 0x000000ffff097224 */
/* 0x001fe200010e0605 */
/*0760*/ MOV R4, R8 ; /* 0x0000000800047202 */
/* 0x002fc60000000f00 */
/*0770*/ IMAD.MOV.U32 R5, RZ, RZ, R9 ; /* 0x000000ffff057224 */
/* 0x000fe400078e0009 */
/*0780*/ FADD R13, -R6, R13 ; /* 0x0000000d060d7221 */
/* 0x004fe20000000100 */
/*0790*/ IADD3 R6, P3, R2, 0x280, RZ ; /* 0x0000028002067810 */
/* 0x000fc80007f7e0ff */
/*07a0*/ IADD3.X R7, RZ, R3, RZ, P3, !PT ; /* 0x00000003ff077210 */
/* 0x000fe20001ffe4ff */
/*07b0*/ STG.E [R2.64+0x208], R13 ; /* 0x0002080d02007986 */
/* 0x0001e4000c101904 */
/*07c0*/ MOV R2, R6 ; /* 0x0000000600027202 */
/* 0x001fe40000000f00 */
/*07d0*/ MOV R3, R7 ; /* 0x0000000700037202 */
/* 0x000fe20000000f00 */
/*07e0*/ @!P1 BRA 0x340 ; /* 0xfffffb5000009947 */
/* 0x000fea000383ffff */
/*07f0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0800*/ IADD3 R6, -R0, -0x14, RZ ; /* 0xffffffec00067810 */
/* 0x000fe20007ffe1ff */
/*0810*/ BSSY B0, 0xaf0 ; /* 0x000002d000007945 */
/* 0x000fe60003800000 */
/*0820*/ ISETP.GT.AND P1, PT, R6, 0x28, PT ; /* 0x000000280600780c */
/* 0x000fda0003f24270 */
/*0830*/ @!P1 BRA 0xae0 ; /* 0x000002a000009947 */
/* 0x000fea0003800000 */
/*0840*/ LDG.E R6, [R4.64+-0x50] ; /* 0xffffb00404067981 */
/* 0x000ea8000c1e1900 */
/*0850*/ LDG.E R7, [R4.64+-0x4c] ; /* 0xffffb40404077981 */
/* 0x000ea4000c1e1900 */
/*0860*/ FADD R7, -R6, R7 ; /* 0x0000000706077221 */
/* 0x004fca0000000100 */
/*0870*/ STG.E [R2.64+-0x50], R7 ; /* 0xffffb00702007986 */
/* 0x0001e8000c101904 */
/*0880*/ LDG.E R6, [R4.64+-0x28] ; /* 0xffffd80404067981 */
/* 0x000ea8000c1e1900 */
/*0890*/ LDG.E R9, [R4.64+-0x24] ; /* 0xffffdc0404097981 */
/* 0x000ea4000c1e1900 */
/*08a0*/ FADD R9, -R6, R9 ; /* 0x0000000906097221 */
/* 0x004fca0000000100 */
/*08b0*/ STG.E [R2.64+-0x28], R9 ; /* 0xffffd80902007986 */
/* 0x0003e8000c101904 */
/*08c0*/ LDG.E R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000ea8000c1e1900 */
/*08d0*/ LDG.E R11, [R4.64+0x4] ; /* 0x00000404040b7981 */
/* 0x000ea4000c1e1900 */
/*08e0*/ FADD R11, -R6, R11 ; /* 0x0000000b060b7221 */
/* 0x004fca0000000100 */
/*08f0*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x0005e8000c101904 */
/*0900*/ LDG.E R6, [R4.64+0x28] ; /* 0x0000280404067981 */
/* 0x000ee8000c1e1900 */
/*0910*/ LDG.E R13, [R4.64+0x2c] ; /* 0x00002c04040d7981 */
/* 0x000ee4000c1e1900 */
/*0920*/ FADD R13, -R6, R13 ; /* 0x0000000d060d7221 */
/* 0x008fca0000000100 */
/*0930*/ STG.E [R2.64+0x28], R13 ; /* 0x0000280d02007986 */
/* 0x0007e8000c101904 */
/*0940*/ LDG.E R6, [R4.64+0x50] ; /* 0x0000500404067981 */
/* 0x000f28000c1e1900 */
/*0950*/ LDG.E R7, [R4.64+0x54] ; /* 0x0000540404077981 */
/* 0x001f24000c1e1900 */
/*0960*/ FADD R7, -R6, R7 ; /* 0x0000000706077221 */
/* 0x010fca0000000100 */
/*0970*/ STG.E [R2.64+0x50], R7 ; /* 0x0000500702007986 */
/* 0x000fe8000c101904 */
/*0980*/ LDG.E R6, [R4.64+0x78] ; /* 0x0000780404067981 */
/* 0x000f28000c1e1900 */
/*0990*/ LDG.E R9, [R4.64+0x7c] ; /* 0x00007c0404097981 */
/* 0x002f24000c1e1900 */
/*09a0*/ FADD R9, -R6, R9 ; /* 0x0000000906097221 */
/* 0x010fca0000000100 */
/*09b0*/ STG.E [R2.64+0x78], R9 ; /* 0x0000780902007986 */
/* 0x0001e8000c101904 */
/*09c0*/ LDG.E R6, [R4.64+0xa0] ; /* 0x0000a00404067981 */
/* 0x000f28000c1e1900 */
/*09d0*/ LDG.E R11, [R4.64+0xa4] ; /* 0x0000a404040b7981 */
/* 0x004f24000c1e1900 */
/*09e0*/ FADD R11, -R6, R11 ; /* 0x0000000b060b7221 */
/* 0x010fca0000000100 */
/*09f0*/ STG.E [R2.64+0xa0], R11 ; /* 0x0000a00b02007986 */
/* 0x000fe8000c101904 */
/*0a00*/ LDG.E R6, [R4.64+0xc8] ; /* 0x0000c80404067981 */
/* 0x0002a8000c1e1900 */
/*0a10*/ LDG.E R13, [R4.64+0xcc] ; /* 0x0000cc04040d7981 */
/* 0x0082a2000c1e1900 */
/*0a20*/ IADD3 R8, P1, R4, 0x140, RZ ; /* 0x0000014004087810 */
/* 0x000fe40007f3e0ff */
/*0a30*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc40003f0e170 */
/*0a40*/ IADD3 R0, R0, 0x50, RZ ; /* 0x0000005000007810 */
/* 0x000fe20007ffe0ff */
/*0a50*/ IMAD.X R9, RZ, RZ, R5, P1 ; /* 0x000000ffff097224 */
/* 0x001fe200008e0605 */
/*0a60*/ MOV R4, R8 ; /* 0x0000000800047202 */
/* 0x002fc60000000f00 */
/*0a70*/ IMAD.MOV.U32 R5, RZ, RZ, R9 ; /* 0x000000ffff057224 */
/* 0x000fe400078e0009 */
/*0a80*/ FADD R13, -R6, R13 ; /* 0x0000000d060d7221 */
/* 0x004fe20000000100 */
/*0a90*/ IADD3 R6, P2, R2, 0x140, RZ ; /* 0x0000014002067810 */
/* 0x000fc80007f5e0ff */
/*0aa0*/ IADD3.X R7, RZ, R3, RZ, P2, !PT ; /* 0x00000003ff077210 */
/* 0x000fe200017fe4ff */
/*0ab0*/ STG.E [R2.64+0xc8], R13 ; /* 0x0000c80d02007986 */
/* 0x0001e4000c101904 */
/*0ac0*/ MOV R2, R6 ; /* 0x0000000600027202 */
/* 0x001fe40000000f00 */
/*0ad0*/ MOV R3, R7 ; /* 0x0000000700037202 */
/* 0x000fe40000000f00 */
/*0ae0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0af0*/ ISETP.LT.OR P0, PT, R0, -0x14, P0 ; /* 0xffffffec0000780c */
/* 0x000fda0000701670 */
/*0b00*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0b10*/ LDG.E R0, [R4.64+-0x50] ; /* 0xffffb00404007981 */
/* 0x000ea8000c1e1900 */
/*0b20*/ LDG.E R7, [R4.64+-0x4c] ; /* 0xffffb40404077981 */
/* 0x000ea4000c1e1900 */
/*0b30*/ FADD R7, -R0, R7 ; /* 0x0000000700077221 */
/* 0x004fca0000000100 */
/*0b40*/ STG.E [R2.64+-0x50], R7 ; /* 0xffffb00702007986 */
/* 0x000fe8000c101904 */
/*0b50*/ LDG.E R0, [R4.64+-0x28] ; /* 0xffffd80404007981 */
/* 0x000ea8000c1e1900 */
/*0b60*/ LDG.E R9, [R4.64+-0x24] ; /* 0xffffdc0404097981 */
/* 0x000ea4000c1e1900 */
/*0b70*/ FADD R9, -R0, R9 ; /* 0x0000000900097221 */
/* 0x004fca0000000100 */
/*0b80*/ STG.E [R2.64+-0x28], R9 ; /* 0xffffd80902007986 */
/* 0x000fe8000c101904 */
/*0b90*/ LDG.E R0, [R4.64] ; /* 0x0000000404007981 */
/* 0x000ea8000c1e1900 */
/*0ba0*/ LDG.E R11, [R4.64+0x4] ; /* 0x00000404040b7981 */
/* 0x000ea4000c1e1900 */
/*0bb0*/ FADD R11, -R0, R11 ; /* 0x0000000b000b7221 */
/* 0x004fca0000000100 */
/*0bc0*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x000fe8000c101904 */
/*0bd0*/ LDG.E R0, [R4.64+0x28] ; /* 0x0000280404007981 */
/* 0x000ea8000c1e1900 */
/*0be0*/ LDG.E R13, [R4.64+0x2c] ; /* 0x00002c04040d7981 */
/* 0x000ea4000c1e1900 */
/*0bf0*/ FADD R13, -R0, R13 ; /* 0x0000000d000d7221 */
/* 0x004fca0000000100 */
/*0c00*/ STG.E [R2.64+0x28], R13 ; /* 0x0000280d02007986 */
/* 0x000fe2000c101904 */
/*0c10*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0c20*/ BRA 0xc20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0c30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ca0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ce0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9cudaFunctPfS_
.globl _Z9cudaFunctPfS_
.p2align 8
.type _Z9cudaFunctPfS_,@function
_Z9cudaFunctPfS_:
s_mov_b32 s2, exec_lo
v_cmpx_gt_u32_e32 20, v0
s_cbranch_execz .LBB0_3
s_load_b128 s[0:3], s[0:1], 0x0
v_lshlrev_b32_e32 v2, 2, v0
v_add_nc_u32_e32 v4, -10, v0
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v1, s0, v2, s0
v_add_co_ci_u32_e64 v3, null, 0, s1, s0
v_add_co_u32 v2, s0, s2, v2
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v0, vcc_lo, v1, -4
v_add_co_ci_u32_e32 v1, vcc_lo, -1, v3, vcc_lo
v_add_co_ci_u32_e64 v3, null, s3, 0, s0
s_mov_b32 s0, 0
.p2align 6
.LBB0_2:
global_load_b64 v[5:6], v[0:1], off
v_add_co_u32 v0, vcc_lo, v0, 40
v_add_co_u32 v4, s1, v4, 10
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
s_xor_b32 s1, s1, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s1, exec_lo, s1
s_or_b32 s0, s1, s0
s_waitcnt vmcnt(0)
v_sub_f32_e32 v5, v6, v5
global_store_b32 v[2:3], v5, off
v_add_co_u32 v2, vcc_lo, v2, 40
v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9cudaFunctPfS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 16
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 4
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9cudaFunctPfS_, .Lfunc_end0-_Z9cudaFunctPfS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 16
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9cudaFunctPfS_
.private_segment_fixed_size: 0
.sgpr_count: 6
.sgpr_spill_count: 0
.symbol: _Z9cudaFunctPfS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00017ff0_00000000-6_simpleCuda3.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z30__device_stub__Z9cudaFunctPfS_PfS_
.type _Z30__device_stub__Z9cudaFunctPfS_PfS_, @function
_Z30__device_stub__Z9cudaFunctPfS_PfS_:
.LFB2082:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z9cudaFunctPfS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z30__device_stub__Z9cudaFunctPfS_PfS_, .-_Z30__device_stub__Z9cudaFunctPfS_PfS_
.globl _Z9cudaFunctPfS_
.type _Z9cudaFunctPfS_, @function
_Z9cudaFunctPfS_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z9cudaFunctPfS_PfS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z9cudaFunctPfS_, .-_Z9cudaFunctPfS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%f\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $48, %rsp
.cfi_def_cfa_offset 80
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movq $0, (%rsp)
movq $0, 8(%rsp)
movl $80, %edi
call malloc@PLT
movq %rax, %rbx
movl $80, %edi
call malloc@PLT
movq %rax, %rbp
movq %rsp, %rdi
movl $80, %esi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movl $80, %esi
call cudaMalloc@PLT
movl $0, %eax
.L12:
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, (%rbx,%rax,4)
addq $1, %rax
cmpq $20, %rax
jne .L12
movl $1, %ecx
movl $80, %edx
movq %rbx, %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
movl $10, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L19
.L13:
movl $2, %ecx
movl $80, %edx
movq 8(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
movq %rbp, %rbx
addq $80, %rbp
leaq .LC0(%rip), %r12
.L14:
pxor %xmm0, %xmm0
cvtss2sd (%rbx), %xmm0
movq %r12, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %rbp, %rbx
jne .L14
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L20
movl $0, %eax
addq $48, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z30__device_stub__Z9cudaFunctPfS_PfS_
jmp .L13
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z9cudaFunctPfS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z9cudaFunctPfS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "simpleCuda3.hip"
.globl _Z24__device_stub__cudaFunctPfS_ # -- Begin function _Z24__device_stub__cudaFunctPfS_
.p2align 4, 0x90
.type _Z24__device_stub__cudaFunctPfS_,@function
_Z24__device_stub__cudaFunctPfS_: # @_Z24__device_stub__cudaFunctPfS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z9cudaFunctPfS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z24__device_stub__cudaFunctPfS_, .Lfunc_end0-_Z24__device_stub__cudaFunctPfS_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $104, %rsp
.cfi_def_cfa_offset 128
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movq $0, 8(%rsp)
movq $0, (%rsp)
movl $80, %edi
callq malloc
movq %rax, %r14
movl $80, %edi
callq malloc
movq %rax, %rbx
leaq 8(%rsp), %rdi
movl $80, %esi
callq hipMalloc
movq %rsp, %rdi
movl $80, %esi
callq hipMalloc
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, (%r14,%rax,4)
incq %rax
cmpq $20, %rax
jne .LBB1_1
# %bb.2:
movq 8(%rsp), %rdi
movl $80, %edx
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 9(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 8(%rsp), %rax
movq (%rsp), %rcx
movq %rax, 72(%rsp)
movq %rcx, 64(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9cudaFunctPfS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
movq (%rsp), %rsi
movl $80, %edx
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB1_5: # =>This Inner Loop Header: Depth=1
movss (%rbx,%r14,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
incq %r14
cmpq $20, %r14
jne .LBB1_5
# %bb.6:
xorl %eax, %eax
addq $104, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9cudaFunctPfS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9cudaFunctPfS_,@object # @_Z9cudaFunctPfS_
.section .rodata,"a",@progbits
.globl _Z9cudaFunctPfS_
.p2align 3, 0x0
_Z9cudaFunctPfS_:
.quad _Z24__device_stub__cudaFunctPfS_
.size _Z9cudaFunctPfS_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%f\n"
.size .L.str, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z9cudaFunctPfS_"
.size .L__unnamed_1, 17
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__cudaFunctPfS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9cudaFunctPfS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <stdlib.h>
typedef unsigned char uchar;
__global__ void calcGis(uchar* data, int n, int* height) {
int idx = threadIdx.x + blockIdx.x * blockDim.x;
int offsetx = gridDim.x * blockDim.x;
__shared__ int tmp[256];
for(int i = threadIdx.x; i<256; i+=blockDim.x){
tmp[i]=0;
}
__syncthreads();
for(int i = idx; i < n; i += offsetx){
atomicAdd(tmp+(int)data[i], 1);
}
__syncthreads();
for(int i = threadIdx.x; i<256; i+=blockDim.x){
atomicAdd(height + i, tmp[i]);
}
}
__global__ void scan(int* height){
int idx = threadIdx.x + blockIdx.x * blockDim.x;
int forSwap,k;
__shared__ int data[264];
if(idx<256){
data[idx+(idx>>5)]=height[idx];
__syncthreads();
for(k=1;k<256;k*=2){
int j=idx*k*2+k-1;
if(j+k<256){
data[((j+k)>>5)+(j+k)]+=data[j+(j>>5)];
}
__syncthreads();
}
data[((255)>>5)+(255)]=0;
__syncthreads();
for( k=256;k>1;k/=2){
int j=k*(idx+1)-1;
if(j<256){
forSwap=data[((j-k/2)>>5)+(j-k/2)];
data[((j-k/2)>>5)+(j-k/2)]=data[(j>>5)+j];
data[(j>>5)+j]=forSwap+data[(j>>5)+j];
}
__syncthreads();
}
__syncthreads();
height[idx]+=data[idx+(idx>>5)];
}
}
__global__ void outGis(uchar* data, int n, int* height) {
int idx = threadIdx.x + blockIdx.x * blockDim.x;
int offsetx = gridDim.x * blockDim.x;
uchar j = 0;
for(int i = idx; i < n; i += offsetx){
while(height[j] <= i){
j++;
}
data[i] = j;
}
}
int main() {
int size = 256;
int n;
fread(&n, sizeof(int), 1, stdin);
uchar* data = (uchar*) malloc(sizeof(uchar) * n);
fread(data, sizeof(uchar), n, stdin);
int *height1;
uchar *data1;
cudaMalloc(&data1, n * sizeof(uchar));
cudaMemcpy(data1, data, n*sizeof(uchar), cudaMemcpyHostToDevice);
cudaMalloc(&height1, size * sizeof(int));
cudaMemset(height1, 0, size * sizeof(int));
dim3 threads = 256;
dim3 blocks = 256;
calcGis<<<blocks, threads>>>(data1, n, height1);
scan<<<blocks, threads>>>(height1);
outGis<<<blocks, threads>>>(data1, n, height1);
cudaMemcpy(data, data1, n * sizeof(uchar), cudaMemcpyDeviceToHost);
cudaFree(height1);
cudaFree(data1);
fwrite(data, sizeof(uchar), n, stdout);
free(data);
return 0;
} | code for sm_80
Function : _Z6outGisPhiPi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x168], PT ; /* 0x00005a0000007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ PRMT R4, RZ, 0x7610, R4 ; /* 0x00007610ff047816 */
/* 0x000fe20000000004 */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc80000000a00 */
/*0080*/ BSSY B0, 0x130 ; /* 0x000000a000007945 */
/* 0x000fe40003800000 */
/*0090*/ LOP3.LUT R2, R4, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff04027812 */
/* 0x000fe200078ec0ff */
/*00a0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fc800078e00ff */
/*00b0*/ IMAD.WIDE.U32 R2, R2, R3, c[0x0][0x170] ; /* 0x00005c0002027625 */
/* 0x000fcc00078e0003 */
/*00c0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00d0*/ IADD3 R5, R4.reuse, 0x1, RZ ; /* 0x0000000104057810 */
/* 0x040fe40007ffe0ff */
/*00e0*/ PRMT R6, R4, 0x7610, R6 ; /* 0x0000761004067816 */
/* 0x000fe40000000006 */
/*00f0*/ PRMT R4, R5, 0x7610, R4 ; /* 0x0000761005047816 */
/* 0x000fe40000000004 */
/*0100*/ ISETP.GT.AND P0, PT, R3, R0, PT ; /* 0x000000000300720c */
/* 0x004fda0003f04270 */
/*0110*/ @!P0 BRA 0x90 ; /* 0xffffff7000008947 */
/* 0x000fea000383ffff */
/*0120*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0130*/ IADD3 R2, P0, R0, c[0x0][0x160], RZ ; /* 0x0000580000027a10 */
/* 0x000fe20007f1e0ff */
/*0140*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0xc] ; /* 0x00000300ff057624 */
/* 0x000fe200078e00ff */
/*0150*/ PRMT R4, R6, 0x7610, R4 ; /* 0x0000761006047816 */
/* 0x000fe40000000004 */
/*0160*/ LEA.HI.X.SX32 R3, R0, c[0x0][0x164], 0x1, P0 ; /* 0x0000590000037a11 */
/* 0x000fe200000f0eff */
/*0170*/ IMAD R0, R5, c[0x0][0x0], R0 ; /* 0x0000000005007a24 */
/* 0x000fc800078e0200 */
/*0180*/ STG.E.U8 [R2.64], R6 ; /* 0x0000000602007986 */
/* 0x0001e2000c101104 */
/*0190*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x168], PT ; /* 0x00005a0000007a0c */
/* 0x000fda0003f06270 */
/*01a0*/ @!P0 BRA 0x80 ; /* 0xfffffed000008947 */
/* 0x001fea000383ffff */
/*01b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01c0*/ BRA 0x1c0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z4scanPi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e280000002100 */
/*0020*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e240000002500 */
/*0030*/ IMAD R5, R0, c[0x0][0x0], R5 ; /* 0x0000000000057a24 */
/* 0x001fca00078e0205 */
/*0040*/ ISETP.GT.AND P0, PT, R5, 0xff, PT ; /* 0x000000ff0500780c */
/* 0x000fda0003f04270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ IMAD.MOV.U32 R2, RZ, RZ, 0x4 ; /* 0x00000004ff027424 */
/* 0x000fe200078e00ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0080*/ IMAD.WIDE R2, R5, R2, c[0x0][0x160] ; /* 0x0000580005027625 */
/* 0x000fca00078e0202 */
/*0090*/ LDG.E R7, [R2.64] ; /* 0x0000000402077981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ LEA.HI.SX32 R0, R5.reuse, R5, 0x1b ; /* 0x0000000505007211 */
/* 0x040fe200078fdaff */
/*00b0*/ IMAD.SHL.U32 R4, R5.reuse, 0x2, RZ ; /* 0x0000000205047824 */
/* 0x040fe400078e00ff */
/*00c0*/ IMAD.SHL.U32 R12, R5.reuse, 0x4, RZ ; /* 0x00000004050c7824 */
/* 0x040fe400078e00ff */
/*00d0*/ IMAD.SHL.U32 R15, R5, 0x8, RZ ; /* 0x00000008050f7824 */
/* 0x000fe200078e00ff */
/*00e0*/ ISETP.GT.AND P1, PT, R4.reuse, 0xfe, PT ; /* 0x000000fe0400780c */
/* 0x040fe40003f24270 */
/*00f0*/ IADD3 R9, R4, 0x1, RZ ; /* 0x0000000104097810 */
/* 0x000fe40007ffe0ff */
/*0100*/ ISETP.GT.AND P0, PT, R12, 0xfc, PT ; /* 0x000000fc0c00780c */
/* 0x000fc60003f04270 */
/*0110*/ IMAD.IADD R6, R4, 0x1, R9 ; /* 0x0000000104067824 */
/* 0x000fcc00078e0209 */
/*0120*/ @!P1 LEA.HI.SX32 R8, R4, R4, 0x1b ; /* 0x0000000404089211 */
/* 0x000fe400078fdaff */
/*0130*/ @!P1 LEA.HI.SX32 R10, R9, R9, 0x1b ; /* 0x00000009090a9211 */
/* 0x000fe400078fdaff */
/*0140*/ IADD3 R9, R6.reuse, 0x2, RZ ; /* 0x0000000206097810 */
/* 0x040fe40007ffe0ff */
/*0150*/ @!P0 LEA.HI.SX32 R13, R6, R6, 0x1b ; /* 0x00000006060d8211 */
/* 0x000fe400078fdaff */
/*0160*/ @!P0 LEA.HI.SX32 R14, R9, R9, 0x1b ; /* 0x00000009090e8211 */
/* 0x000fe200078fdaff */
/*0170*/ STS [R0.X4], R7 ; /* 0x0000000700007388 */
/* 0x0041e80000004800 */
/*0180*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0190*/ IMAD.IADD R7, R12, 0x1, R9 ; /* 0x000000010c077824 */
/* 0x001fca00078e0209 */
/*01a0*/ IADD3 R12, R7, 0x4, RZ ; /* 0x00000004070c7810 */
/* 0x000fe20007ffe0ff */
/*01b0*/ @!P1 LDS R8, [R8.X4] ; /* 0x0000000008089984 */
/* 0x000fe80000004800 */
/*01c0*/ @!P1 LDS R11, [R10.X4] ; /* 0x000000000a0b9984 */
/* 0x000e240000004800 */
/*01d0*/ @!P1 IMAD.IADD R11, R11, 0x1, R8 ; /* 0x000000010b0b9824 */
/* 0x001fca00078e0208 */
/*01e0*/ @!P1 STS [R10.X4], R11 ; /* 0x0000000b0a009388 */
/* 0x000fe80000004800 */
/*01f0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0200*/ ISETP.GT.AND P1, PT, R15, 0xf8, PT ; /* 0x000000f80f00780c */
/* 0x000fda0003f24270 */
/*0210*/ @!P1 LEA.HI.SX32 R16, R7, R7, 0x1b ; /* 0x0000000707109211 */
/* 0x000fe400078fdaff */
/*0220*/ @!P1 LEA.HI.SX32 R17, R12, R12, 0x1b ; /* 0x0000000c0c119211 */
/* 0x000fe200078fdaff */
/*0230*/ @!P0 LDS R13, [R13.X4] ; /* 0x000000000d0d8984 */
/* 0x000fe80000004800 */
/*0240*/ @!P0 LDS R8, [R14.X4] ; /* 0x000000000e088984 */
/* 0x000e240000004800 */
/*0250*/ @!P0 IMAD.IADD R9, R8, 0x1, R13 ; /* 0x0000000108098824 */
/* 0x001fe400078e020d */
/*0260*/ IMAD.SHL.U32 R13, R5, 0x10, RZ ; /* 0x00000010050d7824 */
/* 0x000fc400078e00ff */
/*0270*/ IMAD.IADD R8, R15, 0x1, R12 ; /* 0x000000010f087824 */
/* 0x000fe200078e020c */
/*0280*/ @!P0 STS [R14.X4], R9 ; /* 0x000000090e008388 */
/* 0x0001e80000004800 */
/*0290*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*02a0*/ ISETP.GT.AND P0, PT, R13, 0xf0, PT ; /* 0x000000f00d00780c */
/* 0x000fe40003f04270 */
/*02b0*/ IADD3 R12, R8, 0x8, RZ ; /* 0x00000008080c7810 */
/* 0x000fca0007ffe0ff */
/*02c0*/ IMAD.IADD R9, R13, 0x1, R12 ; /* 0x000000010d097824 */
/* 0x001fca00078e020c */
/*02d0*/ IADD3 R13, R9, 0x10, RZ ; /* 0x00000010090d7810 */
/* 0x000fe40007ffe0ff */
/*02e0*/ @!P0 LEA.HI.SX32 R15, R12, R12, 0x1b ; /* 0x0000000c0c0f8211 */
/* 0x000fe200078fdaff */
/*02f0*/ @!P1 LDS R11, [R16.X4] ; /* 0x00000000100b9984 */
/* 0x0001e80000004800 */
/*0300*/ @!P1 LDS R10, [R17.X4] ; /* 0x00000000110a9984 */
/* 0x000e620000004800 */
/*0310*/ IMAD.SHL.U32 R16, R5, 0x20, RZ ; /* 0x0000002005107824 */
/* 0x001fe400078e00ff */
/*0320*/ @!P1 IMAD.IADD R10, R10, 0x1, R11 ; /* 0x000000010a0a9824 */
/* 0x002fe200078e020b */
/*0330*/ @!P0 LEA.HI.SX32 R11, R8, R8, 0x1b ; /* 0x00000008080b8211 */
/* 0x000fc800078fdaff */
/*0340*/ @!P1 STS [R17.X4], R10 ; /* 0x0000000a11009388 */
/* 0x0001e80000004800 */
/*0350*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0360*/ ISETP.GT.AND P1, PT, R16.reuse, 0xe0, PT ; /* 0x000000e01000780c */
/* 0x040fe20003f24270 */
/*0370*/ IMAD.IADD R10, R16, 0x1, R13 ; /* 0x00000001100a7824 */
/* 0x001fe400078e020d */
/*0380*/ IMAD.SHL.U32 R17, R5, 0x40, RZ ; /* 0x0000004005117824 */
/* 0x000fc600078e00ff */
/*0390*/ IADD3 R16, R10, 0x20, RZ ; /* 0x000000200a107810 */
/* 0x000fce0007ffe0ff */
/*03a0*/ @!P1 LEA.HI.SX32 R12, R9, R9, 0x1b ; /* 0x00000009090c9211 */
/* 0x000fe400078fdaff */
/*03b0*/ @!P1 LEA.HI.SX32 R18, R13, R13, 0x1b ; /* 0x0000000d0d129211 */
/* 0x000fe200078fdaff */
/*03c0*/ @!P0 LDS R11, [R11.X4] ; /* 0x000000000b0b8984 */
/* 0x000fe80000004800 */
/*03d0*/ @!P0 LDS R14, [R15.X4] ; /* 0x000000000f0e8984 */
/* 0x000e240000004800 */
/*03e0*/ @!P0 IMAD.IADD R14, R14, 0x1, R11 ; /* 0x000000010e0e8824 */
/* 0x001fca00078e020b */
/*03f0*/ @!P0 STS [R15.X4], R14 ; /* 0x0000000e0f008388 */
/* 0x0001e80000004800 */
/*0400*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0410*/ ISETP.GT.AND P0, PT, R17, 0xc0, PT ; /* 0x000000c01100780c */
/* 0x000fe20003f04270 */
/*0420*/ IMAD.SHL.U32 R14, R5, 0x80, RZ ; /* 0x00000080050e7824 */
/* 0x001fd800078e00ff */
/*0430*/ @!P0 LEA.HI.SX32 R19, R10, R10, 0x1b ; /* 0x0000000a0a138211 */
/* 0x000fe400078fdaff */
/*0440*/ @!P0 LEA.HI.SX32 R20, R16, R16, 0x1b ; /* 0x0000001010148211 */
/* 0x000fe200078fdaff */
/*0450*/ @!P1 LDS R12, [R12.X4] ; /* 0x000000000c0c9984 */
/* 0x000fe80000004800 */
/*0460*/ @!P1 LDS R11, [R18.X4] ; /* 0x00000000120b9984 */
/* 0x000e240000004800 */
/*0470*/ @!P1 IMAD.IADD R13, R11, 0x1, R12 ; /* 0x000000010b0d9824 */
/* 0x001fe400078e020c */
/*0480*/ IMAD.IADD R11, R17, 0x1, R16 ; /* 0x00000001110b7824 */
/* 0x000fc600078e0210 */
/*0490*/ @!P1 STS [R18.X4], R13 ; /* 0x0000000d12009388 */
/* 0x000fe80000004800 */
/*04a0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*04b0*/ ISETP.GT.AND P1, PT, R14, 0x80, PT ; /* 0x000000800e00780c */
/* 0x000fe40003f24270 */
/*04c0*/ IADD3 R17, R11, 0x40, RZ ; /* 0x000000400b117810 */
/* 0x000fd60007ffe0ff */
/*04d0*/ @!P1 LEA.HI.SX32 R16, R11, R11, 0x1b ; /* 0x0000000b0b109211 */
/* 0x000fe400078fdaff */
/*04e0*/ @!P1 LEA.HI.SX32 R21, R17, R17, 0x1b ; /* 0x0000001111159211 */
/* 0x000fe200078fdaff */
/*04f0*/ IMAD.IADD R17, R14, 0x1, R17 ; /* 0x000000010e117824 */
/* 0x000fe200078e0211 */
/*0500*/ @!P0 LDS R19, [R19.X4] ; /* 0x0000000013138984 */
/* 0x000fe80000004800 */
/*0510*/ @!P0 LDS R12, [R20.X4] ; /* 0x00000000140c8984 */
/* 0x000e240000004800 */
/*0520*/ @!P0 IMAD.IADD R15, R12, 0x1, R19 ; /* 0x000000010c0f8824 */
/* 0x001fe200078e0213 */
/*0530*/ IADD3 R12, R17, 0x80, RZ ; /* 0x00000080110c7810 */
/* 0x000fe20007ffe0ff */
/*0540*/ IMAD.SHL.U32 R19, R5, 0x100, RZ ; /* 0x0000010005137824 */
/* 0x000fc600078e00ff */
/*0550*/ @!P0 STS [R20.X4], R15 ; /* 0x0000000f14008388 */
/* 0x000fe80000004800 */
/*0560*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0570*/ ISETP.GT.AND P0, PT, R19, RZ, PT ; /* 0x000000ff1300720c */
/* 0x000fda0003f04270 */
/*0580*/ @!P0 LEA.HI.SX32 R18, R17, R17, 0x1b ; /* 0x0000001111128211 */
/* 0x000fe400078fdaff */
/*0590*/ @!P0 LEA.HI.SX32 R19, R12, R19, 0x1b ; /* 0x000000130c138211 */
/* 0x000fe200078fdaff */
/*05a0*/ @!P1 LDS R16, [R16.X4] ; /* 0x0000000010109984 */
/* 0x000fe80000004800 */
/*05b0*/ @!P1 LDS R13, [R21.X4] ; /* 0x00000000150d9984 */
/* 0x000e240000004800 */
/*05c0*/ @!P1 IMAD.IADD R14, R13, 0x1, R16 ; /* 0x000000010d0e9824 */
/* 0x001fe200078e0210 */
/*05d0*/ IADD3 R13, R5, 0x1, RZ ; /* 0x00000001050d7810 */
/* 0x000fc80007ffe0ff */
/*05e0*/ @!P1 STS [R21.X4], R14 ; /* 0x0000000e15009388 */
/* 0x000fe80000004800 */
/*05f0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0600*/ ISETP.GT.AND P1, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe20003f24270 */
/*0610*/ IMAD.SHL.U32 R20, R13.reuse, 0x100, RZ ; /* 0x000001000d147824 */
/* 0x040fe400078e00ff */
/*0620*/ IMAD.SHL.U32 R23, R13, 0x40, RZ ; /* 0x000000400d177824 */
/* 0x000fd400078e00ff */
/*0630*/ @!P1 LEA.HI.SX32 R20, R17, R20, 0x1b ; /* 0x0000001411149211 */
/* 0x000fe200078fdaff */
/*0640*/ @!P0 LDS R18, [R18.X4] ; /* 0x0000000012128984 */
/* 0x000fe80000004800 */
/*0650*/ @!P0 LDS R15, [R19.X4+0x3fc] ; /* 0x0003fc00130f8984 */
/* 0x000e240000004800 */
/*0660*/ @!P0 IMAD.IADD R16, R15, 0x1, R18 ; /* 0x000000010f108824 */
/* 0x001fe200078e0212 */
/*0670*/ @!P1 LEA.HI.SX32 R15, R12, R12, 0x1b ; /* 0x0000000c0c0f9211 */
/* 0x000fe200078fdaff */
/*0680*/ IMAD.SHL.U32 R18, R13, 0x80, RZ ; /* 0x000000800d127824 */
/* 0x000fc600078e00ff */
/*0690*/ @!P0 STS [R19.X4+0x3fc], R16 ; /* 0x0003fc1013008388 */
/* 0x000fe80000004800 */
/*06a0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*06b0*/ ISETP.GT.AND P0, PT, R5, 0x1, PT ; /* 0x000000010500780c */
/* 0x000fe20003f04270 */
/*06c0*/ IMAD.IADD R12, R12, 0x1, -R18 ; /* 0x000000010c0c7824 */
/* 0x000fd800078e0a12 */
/*06d0*/ @!P0 LEA.HI.SX32 R11, R11, R18, 0x1b ; /* 0x000000120b0b8211 */
/* 0x000fe400078fdaff */
/*06e0*/ @!P0 LEA.HI.SX32 R18, R12.reuse, R12, 0x1b ; /* 0x0000000c0c128211 */
/* 0x040fe200078fdaff */
/*06f0*/ IMAD.IADD R12, R12, 0x1, -R23 ; /* 0x000000010c0c7824 */
/* 0x000fe200078e0a17 */
/*0700*/ STS [0x418], RZ ; /* 0x000418ffff007388 */
/* 0x000fe80000000800 */
/*0710*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0720*/ @!P1 LDS R14, [R20.X4+-0x204] ; /* 0xfffdfc00140e9984 */
/* 0x000fe80000004800 */
/*0730*/ @!P1 LDS R17, [R15.X4] ; /* 0x000000000f119984 */
/* 0x000e240000004800 */
/*0740*/ @!P1 IMAD.IADD R14, R14, 0x1, R17 ; /* 0x000000010e0e9824 */
/* 0x001fc400078e0211 */
/*0750*/ @!P1 STS [R20.X4+-0x204], R17 ; /* 0xfffdfc1114009388 */
/* 0x0001e80000004800 */
/*0760*/ @!P1 STS [R15.X4], R14 ; /* 0x0000000e0f009388 */
/* 0x000fe80000004800 */
/*0770*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0780*/ ISETP.GT.AND P1, PT, R5, 0x3, PT ; /* 0x000000030500780c */
/* 0x000fe20003f24270 */
/*0790*/ IMAD.SHL.U32 R20, R13, 0x20, RZ ; /* 0x000000200d147824 */
/* 0x001fd800078e00ff */
/*07a0*/ @!P1 LEA.HI.SX32 R10, R10, R23, 0x1b ; /* 0x000000170a0a9211 */
/* 0x000fe200078fdaff */
/*07b0*/ @!P0 LDS R16, [R11.X4+-0x104] ; /* 0xfffefc000b108984 */
/* 0x000fe80000004800 */
/*07c0*/ @!P0 LDS R19, [R18.X4] ; /* 0x0000000012138984 */
/* 0x000e240000004800 */
/*07d0*/ @!P0 IMAD.IADD R21, R16, 0x1, R19 ; /* 0x0000000110158824 */
/* 0x001fe400078e0213 */
/*07e0*/ @!P0 STS [R11.X4+-0x104], R19 ; /* 0xfffefc130b008388 */
/* 0x0001e20000004800 */
/*07f0*/ @!P1 LEA.HI.SX32 R16, R12.reuse, R12, 0x1b ; /* 0x0000000c0c109211 */
/* 0x040fe200078fdaff */
/*0800*/ IMAD.IADD R12, R12, 0x1, -R20 ; /* 0x000000010c0c7824 */
/* 0x000fc400078e0a14 */
/*0810*/ @!P0 STS [R18.X4], R21 ; /* 0x0000001512008388 */
/* 0x000fe80000004800 */
/*0820*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0830*/ ISETP.GT.AND P0, PT, R5, 0x7, PT ; /* 0x000000070500780c */
/* 0x000fe20003f04270 */
/*0840*/ IMAD.SHL.U32 R19, R13, 0x10, RZ ; /* 0x000000100d137824 */
/* 0x001fd800078e00ff */
/*0850*/ @!P0 LEA.HI.SX32 R9, R9, R20, 0x1b ; /* 0x0000001409098211 */
/* 0x000fe200078fdaff */
/*0860*/ @!P1 LDS R14, [R10.X4+-0x84] ; /* 0xffff7c000a0e9984 */
/* 0x000fe80000004800 */
/*0870*/ @!P1 LDS R15, [R16.X4] ; /* 0x00000000100f9984 */
/* 0x000e240000004800 */
/*0880*/ @!P1 IMAD.IADD R17, R14, 0x1, R15 ; /* 0x000000010e119824 */
/* 0x001fe400078e020f */
/*0890*/ @!P1 STS [R10.X4+-0x84], R15 ; /* 0xffff7c0f0a009388 */
/* 0x000fe20000004800 */
/*08a0*/ @!P0 LEA.HI.SX32 R14, R12.reuse, R12, 0x1b ; /* 0x0000000c0c0e8211 */
/* 0x040fe200078fdaff */
/*08b0*/ IMAD.IADD R12, R12, 0x1, -R19 ; /* 0x000000010c0c7824 */
/* 0x000fc400078e0a13 */
/*08c0*/ @!P1 STS [R16.X4], R17 ; /* 0x0000001110009388 */
/* 0x0001e80000004800 */
/*08d0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*08e0*/ ISETP.GT.AND P1, PT, R5, 0xf, PT ; /* 0x0000000f0500780c */
/* 0x000fe20003f24270 */
/*08f0*/ IMAD.SHL.U32 R17, R13, 0x8, RZ ; /* 0x000000080d117824 */
/* 0x001fd800078e00ff */
/*0900*/ @!P1 LEA.HI.SX32 R10, R12.reuse, R12, 0x1b ; /* 0x0000000c0c0a9211 */
/* 0x040fe200078fdaff */
/*0910*/ IMAD.IADD R12, R12, 0x1, -R17 ; /* 0x000000010c0c7824 */
/* 0x000fe200078e0a11 */
/*0920*/ @!P1 LEA.HI.SX32 R8, R8, R19, 0x1b ; /* 0x0000001308089211 */
/* 0x000fe200078fdaff */
/*0930*/ @!P0 LDS R18, [R14.X4] ; /* 0x000000000e128984 */
/* 0x000e280000004800 */
/*0940*/ @!P0 LDS R11, [R9.X4+-0x44] ; /* 0xffffbc00090b8984 */
/* 0x000fe80000004800 */
/*0950*/ @!P0 STS [R9.X4+-0x44], R18 ; /* 0xffffbc1209008388 */
/* 0x001fe80000004800 */
/*0960*/ @!P0 LDS R20, [R14.X4] ; /* 0x000000000e148984 */
/* 0x000e240000004800 */
/*0970*/ @!P0 IMAD.IADD R11, R11, 0x1, R20 ; /* 0x000000010b0b8824 */
/* 0x001fca00078e0214 */
/*0980*/ @!P0 STS [R14.X4], R11 ; /* 0x0000000b0e008388 */
/* 0x0001e80000004800 */
/*0990*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*09a0*/ ISETP.GT.AND P0, PT, R5, 0x1f, PT ; /* 0x0000001f0500780c */
/* 0x000fda0003f04270 */
/*09b0*/ @!P0 LEA.HI.SX32 R11, R12, R12, 0x1b ; /* 0x0000000c0c0b8211 */
/* 0x001fe400078fdaff */
/*09c0*/ @!P0 LEA.HI.SX32 R7, R7, R17, 0x1b ; /* 0x0000001107078211 */
/* 0x000fe200078fdaff */
/*09d0*/ IMAD.SHL.U32 R17, R13, 0x4, RZ ; /* 0x000000040d117824 */
/* 0x000fc800078e00ff */
/*09e0*/ IMAD.IADD R12, R12, 0x1, -R17 ; /* 0x000000010c0c7824 */
/* 0x000fe200078e0a11 */
/*09f0*/ @!P1 LDS R15, [R10.X4] ; /* 0x000000000a0f9984 */
/* 0x000e280000004800 */
/*0a00*/ @!P1 LDS R9, [R8.X4+-0x24] ; /* 0xffffdc0008099984 */
/* 0x000fe80000004800 */
/*0a10*/ @!P1 STS [R8.X4+-0x24], R15 ; /* 0xffffdc0f08009388 */
/* 0x001fe80000004800 */
/*0a20*/ @!P1 LDS R16, [R10.X4] ; /* 0x000000000a109984 */
/* 0x000e240000004800 */
/*0a30*/ @!P1 IMAD.IADD R9, R9, 0x1, R16 ; /* 0x0000000109099824 */
/* 0x001fca00078e0210 */
/*0a40*/ @!P1 STS [R10.X4], R9 ; /* 0x000000090a009388 */
/* 0x0001e80000004800 */
/*0a50*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0a60*/ ISETP.GT.AND P1, PT, R5, 0x3f, PT ; /* 0x0000003f0500780c */
/* 0x000fda0003f24270 */
/*0a70*/ @!P1 LEA.HI.SX32 R9, R12, R12, 0x1b ; /* 0x0000000c0c099211 */
/* 0x001fe400078fdaff */
/*0a80*/ @!P1 LEA.HI.SX32 R6, R6, R17, 0x1b ; /* 0x0000001106069211 */
/* 0x000fe200078fdaff */
/*0a90*/ @!P0 LDS R14, [R11.X4] ; /* 0x000000000b0e8984 */
/* 0x000e280000004800 */
/*0aa0*/ @!P0 LDS R8, [R7.X4+-0x14] ; /* 0xffffec0007088984 */
/* 0x000fe80000004800 */
/*0ab0*/ @!P0 STS [R7.X4+-0x14], R14 ; /* 0xffffec0e07008388 */
/* 0x001fe80000004800 */
/*0ac0*/ @!P0 LDS R15, [R11.X4] ; /* 0x000000000b0f8984 */
/* 0x000e240000004800 */
/*0ad0*/ @!P0 IMAD.IADD R8, R8, 0x1, R15 ; /* 0x0000000108088824 */
/* 0x001fca00078e020f */
/*0ae0*/ @!P0 STS [R11.X4], R8 ; /* 0x000000080b008388 */
/* 0x000fe80000004800 */
/*0af0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0b00*/ ISETP.GT.AND P0, PT, R5, 0x7f, PT ; /* 0x0000007f0500780c */
/* 0x000fda0003f04270 */
/*0b10*/ @!P0 IMAD.SHL.U32 R13, R13, 0x2, RZ ; /* 0x000000020d0d8824 */
/* 0x000fc800078e00ff */
/*0b20*/ @!P0 IMAD.IADD R12, R12, 0x1, -R13 ; /* 0x000000010c0c8824 */
/* 0x000fe200078e0a0d */
/*0b30*/ @!P0 LEA.HI.SX32 R4, R4, R13, 0x1b ; /* 0x0000000d04048211 */
/* 0x000fc800078fdaff */
/*0b40*/ @!P0 LEA.HI.SX32 R12, R12, R12, 0x1b ; /* 0x0000000c0c0c8211 */
/* 0x000fe200078fdaff */
/*0b50*/ @!P1 LDS R15, [R9.X4] ; /* 0x00000000090f9984 */
/* 0x000e280000004800 */
/*0b60*/ @!P1 LDS R7, [R6.X4+-0xc] ; /* 0xfffff40006079984 */
/* 0x000fe80000004800 */
/*0b70*/ @!P1 STS [R6.X4+-0xc], R15 ; /* 0xfffff40f06009388 */
/* 0x001fe80000004800 */
/*0b80*/ @!P1 LDS R10, [R9.X4] ; /* 0x00000000090a9984 */
/* 0x000e240000004800 */
/*0b90*/ @!P1 IMAD.IADD R10, R7, 0x1, R10 ; /* 0x00000001070a9824 */
/* 0x001fca00078e020a */
/*0ba0*/ @!P1 STS [R9.X4], R10 ; /* 0x0000000a09009388 */
/* 0x000fe80000004800 */
/*0bb0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0bc0*/ @!P0 LDS R7, [R12.X4] ; /* 0x000000000c078984 */
/* 0x000e280000004800 */
/*0bd0*/ @!P0 LDS R5, [R4.X4+-0x8] ; /* 0xfffff80004058984 */
/* 0x000fe80000004800 */
/*0be0*/ @!P0 STS [R4.X4+-0x8], R7 ; /* 0xfffff80704008388 */
/* 0x001fe80000004800 */
/*0bf0*/ @!P0 LDS R6, [R12.X4] ; /* 0x000000000c068984 */
/* 0x000e240000004800 */
/*0c00*/ @!P0 IMAD.IADD R5, R5, 0x1, R6 ; /* 0x0000000105058824 */
/* 0x001fca00078e0206 */
/*0c10*/ @!P0 STS [R12.X4], R5 ; /* 0x000000050c008388 */
/* 0x000fe80000004800 */
/*0c20*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0c30*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0c40*/ LDG.E R6, [R2.64] ; /* 0x0000000402067981 */
/* 0x000ea8000c1e1900 */
/*0c50*/ LDS R9, [R0.X4] ; /* 0x0000000000097984 */
/* 0x000ea40000004800 */
/*0c60*/ IMAD.IADD R9, R6, 0x1, R9 ; /* 0x0000000106097824 */
/* 0x004fca00078e0209 */
/*0c70*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x000fe2000c101904 */
/*0c80*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0c90*/ BRA 0xc90; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0ca0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ce0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z7calcGisPhiPi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e220000002100 */
/*0020*/ BSSY B0, 0xe0 ; /* 0x000000b000007945 */
/* 0x000fe60003800000 */
/*0030*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e620000002500 */
/*0040*/ ISETP.GT.AND P0, PT, R0, 0xff, PT ; /* 0x000000ff0000780c */
/* 0x001fe20003f04270 */
/*0050*/ IMAD R4, R3, c[0x0][0x0], R0 ; /* 0x0000000003047a24 */
/* 0x002fca00078e0200 */
/*0060*/ ISETP.GE.AND P2, PT, R4, c[0x0][0x168], PT ; /* 0x00005a0004007a0c */
/* 0x000fce0003f46270 */
/*0070*/ @P0 BRA 0xd0 ; /* 0x0000005000000947 */
/* 0x000fea0003800000 */
/*0080*/ IMAD.MOV.U32 R2, RZ, RZ, R0 ; /* 0x000000ffff027224 */
/* 0x000fca00078e0000 */
/*0090*/ STS [R2.X4], RZ ; /* 0x000000ff02007388 */
/* 0x0001e40000004800 */
/*00a0*/ IADD3 R2, R2, c[0x0][0x0], RZ ; /* 0x0000000002027a10 */
/* 0x001fc80007ffe0ff */
/*00b0*/ ISETP.GE.AND P1, PT, R2, 0x100, PT ; /* 0x000001000200780c */
/* 0x000fda0003f26270 */
/*00c0*/ @!P1 BRA 0x90 ; /* 0xffffffc000009947 */
/* 0x000fea000383ffff */
/*00d0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*00e0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*00f0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0100*/ @P2 BRA 0x1a0 ; /* 0x0000009000002947 */
/* 0x000fea0003800000 */
/*0110*/ IADD3 R2, P1, R4, c[0x0][0x160], RZ ; /* 0x0000580004027a10 */
/* 0x001fc80007f3e0ff */
/*0120*/ LEA.HI.X.SX32 R3, R4, c[0x0][0x164], 0x1, P1 ; /* 0x0000590004037a11 */
/* 0x000fca00008f0eff */
/*0130*/ LDG.E.U8 R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1100 */
/*0140*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0xc] ; /* 0x00000300ff057624 */
/* 0x000fe200078e00ff */
/*0150*/ YIELD ; /* 0x0000000000007946 */
/* 0x000fe60003800000 */
/*0160*/ IMAD R4, R5, c[0x0][0x0], R4 ; /* 0x0000000005047a24 */
/* 0x000fca00078e0204 */
/*0170*/ ISETP.GE.AND P1, PT, R4, c[0x0][0x168], PT ; /* 0x00005a0004007a0c */
/* 0x000fe20003f26270 */
/*0180*/ ATOMS.POPC.INC.32 RZ, [R2.X4+URZ] ; /* 0x0000000002ff7f8c */
/* 0x0041d8000d00403f */
/*0190*/ @!P1 BRA 0x110 ; /* 0xffffff7000009947 */
/* 0x000fea000383ffff */
/*01a0*/ WARPSYNC 0xffffffff ; /* 0xffffffff00007948 */
/* 0x000fe20003800000 */
/*01b0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*01c0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*01d0*/ IMAD.MOV.U32 R7, RZ, RZ, 0x4 ; /* 0x00000004ff077424 */
/* 0x000fc600078e00ff */
/*01e0*/ LDS R5, [R0.X4] ; /* 0x0000000000057984 */
/* 0x0012a20000004800 */
/*01f0*/ IMAD.WIDE R2, R0.reuse, R7, c[0x0][0x170] ; /* 0x00005c0000027625 */
/* 0x041fe200078e0207 */
/*0200*/ YIELD ; /* 0x0000000000007946 */
/* 0x000fe20003800000 */
/*0210*/ IADD3 R0, R0, c[0x0][0x0], RZ ; /* 0x0000000000007a10 */
/* 0x002fc80007ffe0ff */
/*0220*/ ISETP.GE.AND P0, PT, R0, 0x100, PT ; /* 0x000001000000780c */
/* 0x000fe20003f06270 */
/*0230*/ RED.E.ADD.STRONG.GPU [R2.64], R5 ; /* 0x000000050200798e */
/* 0x0041d8000c10e184 */
/*0240*/ @!P0 BRA 0x1e0 ; /* 0xffffff9000008947 */
/* 0x000fea000383ffff */
/*0250*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0260*/ BRA 0x260; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <stdlib.h>
typedef unsigned char uchar;
__global__ void calcGis(uchar* data, int n, int* height) {
int idx = threadIdx.x + blockIdx.x * blockDim.x;
int offsetx = gridDim.x * blockDim.x;
__shared__ int tmp[256];
for(int i = threadIdx.x; i<256; i+=blockDim.x){
tmp[i]=0;
}
__syncthreads();
for(int i = idx; i < n; i += offsetx){
atomicAdd(tmp+(int)data[i], 1);
}
__syncthreads();
for(int i = threadIdx.x; i<256; i+=blockDim.x){
atomicAdd(height + i, tmp[i]);
}
}
__global__ void scan(int* height){
int idx = threadIdx.x + blockIdx.x * blockDim.x;
int forSwap,k;
__shared__ int data[264];
if(idx<256){
data[idx+(idx>>5)]=height[idx];
__syncthreads();
for(k=1;k<256;k*=2){
int j=idx*k*2+k-1;
if(j+k<256){
data[((j+k)>>5)+(j+k)]+=data[j+(j>>5)];
}
__syncthreads();
}
data[((255)>>5)+(255)]=0;
__syncthreads();
for( k=256;k>1;k/=2){
int j=k*(idx+1)-1;
if(j<256){
forSwap=data[((j-k/2)>>5)+(j-k/2)];
data[((j-k/2)>>5)+(j-k/2)]=data[(j>>5)+j];
data[(j>>5)+j]=forSwap+data[(j>>5)+j];
}
__syncthreads();
}
__syncthreads();
height[idx]+=data[idx+(idx>>5)];
}
}
__global__ void outGis(uchar* data, int n, int* height) {
int idx = threadIdx.x + blockIdx.x * blockDim.x;
int offsetx = gridDim.x * blockDim.x;
uchar j = 0;
for(int i = idx; i < n; i += offsetx){
while(height[j] <= i){
j++;
}
data[i] = j;
}
}
int main() {
int size = 256;
int n;
fread(&n, sizeof(int), 1, stdin);
uchar* data = (uchar*) malloc(sizeof(uchar) * n);
fread(data, sizeof(uchar), n, stdin);
int *height1;
uchar *data1;
cudaMalloc(&data1, n * sizeof(uchar));
cudaMemcpy(data1, data, n*sizeof(uchar), cudaMemcpyHostToDevice);
cudaMalloc(&height1, size * sizeof(int));
cudaMemset(height1, 0, size * sizeof(int));
dim3 threads = 256;
dim3 blocks = 256;
calcGis<<<blocks, threads>>>(data1, n, height1);
scan<<<blocks, threads>>>(height1);
outGis<<<blocks, threads>>>(data1, n, height1);
cudaMemcpy(data, data1, n * sizeof(uchar), cudaMemcpyDeviceToHost);
cudaFree(height1);
cudaFree(data1);
fwrite(data, sizeof(uchar), n, stdout);
free(data);
return 0;
} | .file "tmpxft_0011e653_00000000-6_lab5.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z29__device_stub__Z7calcGisPhiPiPhiPi
.type _Z29__device_stub__Z7calcGisPhiPiPhiPi, @function
_Z29__device_stub__Z7calcGisPhiPiPhiPi:
.LFB2082:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z7calcGisPhiPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z29__device_stub__Z7calcGisPhiPiPhiPi, .-_Z29__device_stub__Z7calcGisPhiPiPhiPi
.globl _Z7calcGisPhiPi
.type _Z7calcGisPhiPi, @function
_Z7calcGisPhiPi:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z7calcGisPhiPiPhiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z7calcGisPhiPi, .-_Z7calcGisPhiPi
.globl _Z23__device_stub__Z4scanPiPi
.type _Z23__device_stub__Z4scanPiPi, @function
_Z23__device_stub__Z4scanPiPi:
.LFB2084:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z4scanPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z23__device_stub__Z4scanPiPi, .-_Z23__device_stub__Z4scanPiPi
.globl _Z4scanPi
.type _Z4scanPi, @function
_Z4scanPi:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z23__device_stub__Z4scanPiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z4scanPi, .-_Z4scanPi
.globl _Z28__device_stub__Z6outGisPhiPiPhiPi
.type _Z28__device_stub__Z6outGisPhiPiPhiPi, @function
_Z28__device_stub__Z6outGisPhiPiPhiPi:
.LFB2086:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L23
.L19:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L24
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6outGisPhiPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L19
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2086:
.size _Z28__device_stub__Z6outGisPhiPiPhiPi, .-_Z28__device_stub__Z6outGisPhiPiPhiPi
.globl _Z6outGisPhiPi
.type _Z6outGisPhiPi, @function
_Z6outGisPhiPi:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z28__device_stub__Z6outGisPhiPiPhiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _Z6outGisPhiPi, .-_Z6outGisPhiPi
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $72, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rdi
movq stdin(%rip), %r8
movl $1, %ecx
movl $4, %edx
movl $4, %esi
call __fread_chk@PLT
movslq 12(%rsp), %rbp
movq %rbp, %rdi
call malloc@PLT
movq %rax, %rbx
movq stdin(%rip), %r8
movq %rbp, %rcx
movl $1, %edx
movq %rbp, %rsi
movq %rax, %rdi
call __fread_chk@PLT
movslq 12(%rsp), %rsi
leaq 24(%rsp), %rdi
call cudaMalloc@PLT
movslq 12(%rsp), %rdx
movl $1, %ecx
movq %rbx, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
leaq 16(%rsp), %rdi
movl $1024, %esi
call cudaMalloc@PLT
movl $1024, %edx
movl $0, %esi
movq 16(%rsp), %rdi
call cudaMemset@PLT
movl $256, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $256, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 32(%rsp), %rdx
movl $1, %ecx
movq 44(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L33
.L28:
movl 40(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 32(%rsp), %rdx
movq 44(%rsp), %rdi
movl 52(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L34
.L29:
movl 40(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 32(%rsp), %rdx
movq 44(%rsp), %rdi
movl 52(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L35
.L30:
movslq 12(%rsp), %rdx
movl $2, %ecx
movq 24(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movslq 12(%rsp), %rdx
movq stdout(%rip), %rcx
movl $1, %esi
movq %rbx, %rdi
call fwrite@PLT
movq %rbx, %rdi
call free@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L36
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L33:
.cfi_restore_state
movq 16(%rsp), %rdx
movl 12(%rsp), %esi
movq 24(%rsp), %rdi
call _Z29__device_stub__Z7calcGisPhiPiPhiPi
jmp .L28
.L34:
movq 16(%rsp), %rdi
call _Z23__device_stub__Z4scanPiPi
jmp .L29
.L35:
movq 16(%rsp), %rdx
movl 12(%rsp), %esi
movq 24(%rsp), %rdi
call _Z28__device_stub__Z6outGisPhiPiPhiPi
jmp .L30
.L36:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z6outGisPhiPi"
.LC1:
.string "_Z4scanPi"
.LC2:
.string "_Z7calcGisPhiPi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2089:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z6outGisPhiPi(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z4scanPi(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z7calcGisPhiPi(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2089:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <stdlib.h>
typedef unsigned char uchar;
__global__ void calcGis(uchar* data, int n, int* height) {
int idx = threadIdx.x + blockIdx.x * blockDim.x;
int offsetx = gridDim.x * blockDim.x;
__shared__ int tmp[256];
for(int i = threadIdx.x; i<256; i+=blockDim.x){
tmp[i]=0;
}
__syncthreads();
for(int i = idx; i < n; i += offsetx){
atomicAdd(tmp+(int)data[i], 1);
}
__syncthreads();
for(int i = threadIdx.x; i<256; i+=blockDim.x){
atomicAdd(height + i, tmp[i]);
}
}
__global__ void scan(int* height){
int idx = threadIdx.x + blockIdx.x * blockDim.x;
int forSwap,k;
__shared__ int data[264];
if(idx<256){
data[idx+(idx>>5)]=height[idx];
__syncthreads();
for(k=1;k<256;k*=2){
int j=idx*k*2+k-1;
if(j+k<256){
data[((j+k)>>5)+(j+k)]+=data[j+(j>>5)];
}
__syncthreads();
}
data[((255)>>5)+(255)]=0;
__syncthreads();
for( k=256;k>1;k/=2){
int j=k*(idx+1)-1;
if(j<256){
forSwap=data[((j-k/2)>>5)+(j-k/2)];
data[((j-k/2)>>5)+(j-k/2)]=data[(j>>5)+j];
data[(j>>5)+j]=forSwap+data[(j>>5)+j];
}
__syncthreads();
}
__syncthreads();
height[idx]+=data[idx+(idx>>5)];
}
}
__global__ void outGis(uchar* data, int n, int* height) {
int idx = threadIdx.x + blockIdx.x * blockDim.x;
int offsetx = gridDim.x * blockDim.x;
uchar j = 0;
for(int i = idx; i < n; i += offsetx){
while(height[j] <= i){
j++;
}
data[i] = j;
}
}
int main() {
int size = 256;
int n;
fread(&n, sizeof(int), 1, stdin);
uchar* data = (uchar*) malloc(sizeof(uchar) * n);
fread(data, sizeof(uchar), n, stdin);
int *height1;
uchar *data1;
cudaMalloc(&data1, n * sizeof(uchar));
cudaMemcpy(data1, data, n*sizeof(uchar), cudaMemcpyHostToDevice);
cudaMalloc(&height1, size * sizeof(int));
cudaMemset(height1, 0, size * sizeof(int));
dim3 threads = 256;
dim3 blocks = 256;
calcGis<<<blocks, threads>>>(data1, n, height1);
scan<<<blocks, threads>>>(height1);
outGis<<<blocks, threads>>>(data1, n, height1);
cudaMemcpy(data, data1, n * sizeof(uchar), cudaMemcpyDeviceToHost);
cudaFree(height1);
cudaFree(data1);
fwrite(data, sizeof(uchar), n, stdout);
free(data);
return 0;
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
typedef unsigned char uchar;
__global__ void calcGis(uchar* data, int n, int* height) {
int idx = threadIdx.x + blockIdx.x * blockDim.x;
int offsetx = gridDim.x * blockDim.x;
__shared__ int tmp[256];
for(int i = threadIdx.x; i<256; i+=blockDim.x){
tmp[i]=0;
}
__syncthreads();
for(int i = idx; i < n; i += offsetx){
atomicAdd(tmp+(int)data[i], 1);
}
__syncthreads();
for(int i = threadIdx.x; i<256; i+=blockDim.x){
atomicAdd(height + i, tmp[i]);
}
}
__global__ void scan(int* height){
int idx = threadIdx.x + blockIdx.x * blockDim.x;
int forSwap,k;
__shared__ int data[264];
if(idx<256){
data[idx+(idx>>5)]=height[idx];
__syncthreads();
for(k=1;k<256;k*=2){
int j=idx*k*2+k-1;
if(j+k<256){
data[((j+k)>>5)+(j+k)]+=data[j+(j>>5)];
}
__syncthreads();
}
data[((255)>>5)+(255)]=0;
__syncthreads();
for( k=256;k>1;k/=2){
int j=k*(idx+1)-1;
if(j<256){
forSwap=data[((j-k/2)>>5)+(j-k/2)];
data[((j-k/2)>>5)+(j-k/2)]=data[(j>>5)+j];
data[(j>>5)+j]=forSwap+data[(j>>5)+j];
}
__syncthreads();
}
__syncthreads();
height[idx]+=data[idx+(idx>>5)];
}
}
__global__ void outGis(uchar* data, int n, int* height) {
int idx = threadIdx.x + blockIdx.x * blockDim.x;
int offsetx = gridDim.x * blockDim.x;
uchar j = 0;
for(int i = idx; i < n; i += offsetx){
while(height[j] <= i){
j++;
}
data[i] = j;
}
}
int main() {
int size = 256;
int n;
fread(&n, sizeof(int), 1, stdin);
uchar* data = (uchar*) malloc(sizeof(uchar) * n);
fread(data, sizeof(uchar), n, stdin);
int *height1;
uchar *data1;
hipMalloc(&data1, n * sizeof(uchar));
hipMemcpy(data1, data, n*sizeof(uchar), hipMemcpyHostToDevice);
hipMalloc(&height1, size * sizeof(int));
hipMemset(height1, 0, size * sizeof(int));
dim3 threads = 256;
dim3 blocks = 256;
calcGis<<<blocks, threads>>>(data1, n, height1);
scan<<<blocks, threads>>>(height1);
outGis<<<blocks, threads>>>(data1, n, height1);
hipMemcpy(data, data1, n * sizeof(uchar), hipMemcpyDeviceToHost);
hipFree(height1);
hipFree(data1);
fwrite(data, sizeof(uchar), n, stdout);
free(data);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
typedef unsigned char uchar;
__global__ void calcGis(uchar* data, int n, int* height) {
int idx = threadIdx.x + blockIdx.x * blockDim.x;
int offsetx = gridDim.x * blockDim.x;
__shared__ int tmp[256];
for(int i = threadIdx.x; i<256; i+=blockDim.x){
tmp[i]=0;
}
__syncthreads();
for(int i = idx; i < n; i += offsetx){
atomicAdd(tmp+(int)data[i], 1);
}
__syncthreads();
for(int i = threadIdx.x; i<256; i+=blockDim.x){
atomicAdd(height + i, tmp[i]);
}
}
__global__ void scan(int* height){
int idx = threadIdx.x + blockIdx.x * blockDim.x;
int forSwap,k;
__shared__ int data[264];
if(idx<256){
data[idx+(idx>>5)]=height[idx];
__syncthreads();
for(k=1;k<256;k*=2){
int j=idx*k*2+k-1;
if(j+k<256){
data[((j+k)>>5)+(j+k)]+=data[j+(j>>5)];
}
__syncthreads();
}
data[((255)>>5)+(255)]=0;
__syncthreads();
for( k=256;k>1;k/=2){
int j=k*(idx+1)-1;
if(j<256){
forSwap=data[((j-k/2)>>5)+(j-k/2)];
data[((j-k/2)>>5)+(j-k/2)]=data[(j>>5)+j];
data[(j>>5)+j]=forSwap+data[(j>>5)+j];
}
__syncthreads();
}
__syncthreads();
height[idx]+=data[idx+(idx>>5)];
}
}
__global__ void outGis(uchar* data, int n, int* height) {
int idx = threadIdx.x + blockIdx.x * blockDim.x;
int offsetx = gridDim.x * blockDim.x;
uchar j = 0;
for(int i = idx; i < n; i += offsetx){
while(height[j] <= i){
j++;
}
data[i] = j;
}
}
int main() {
int size = 256;
int n;
fread(&n, sizeof(int), 1, stdin);
uchar* data = (uchar*) malloc(sizeof(uchar) * n);
fread(data, sizeof(uchar), n, stdin);
int *height1;
uchar *data1;
hipMalloc(&data1, n * sizeof(uchar));
hipMemcpy(data1, data, n*sizeof(uchar), hipMemcpyHostToDevice);
hipMalloc(&height1, size * sizeof(int));
hipMemset(height1, 0, size * sizeof(int));
dim3 threads = 256;
dim3 blocks = 256;
calcGis<<<blocks, threads>>>(data1, n, height1);
scan<<<blocks, threads>>>(height1);
outGis<<<blocks, threads>>>(data1, n, height1);
hipMemcpy(data, data1, n * sizeof(uchar), hipMemcpyDeviceToHost);
hipFree(height1);
hipFree(data1);
fwrite(data, sizeof(uchar), n, stdout);
free(data);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z7calcGisPhiPi
.globl _Z7calcGisPhiPi
.p2align 8
.type _Z7calcGisPhiPi,@function
_Z7calcGisPhiPi:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x24
s_load_b32 s2, s[0:1], 0x18
s_mov_b32 s4, exec_lo
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
v_cmpx_gt_u32_e32 0x100, v0
s_cbranch_execz .LBB0_3
v_dual_mov_b32 v2, 0 :: v_dual_lshlrev_b32 v1, 2, v0
v_mov_b32_e32 v3, v0
s_lshl_b32 s5, s3, 2
s_mov_b32 s6, 0
.LBB0_2:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
v_add_nc_u32_e32 v3, s3, v3
ds_store_b32 v1, v2
v_add_nc_u32_e32 v1, s5, v1
v_cmp_lt_u32_e32 vcc_lo, 0xff, v3
s_or_b32 s6, vcc_lo, s6
s_and_not1_b32 exec_lo, exec_lo, s6
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s4
s_load_b32 s4, s[0:1], 0x8
v_mad_u64_u32 v[1:2], null, s15, s3, v[0:1]
s_mov_b32 s5, exec_lo
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_gt_i32_e64 s4, v1
s_cbranch_execz .LBB0_6
s_load_b64 s[8:9], s[0:1], 0x0
v_ashrrev_i32_e32 v3, 31, v1
v_mov_b32_e32 v4, 1
s_mul_i32 s6, s2, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_ashr_i32 s7, s6, 31
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s8, v1
v_add_co_ci_u32_e32 v3, vcc_lo, s9, v3, vcc_lo
s_mov_b32 s8, 0
.LBB0_5:
global_load_u8 v5, v[2:3], off
v_add_nc_u32_e32 v1, s6, v1
v_add_co_u32 v2, s2, v2, s6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e64 v3, s2, s7, v3, s2
v_cmp_le_i32_e32 vcc_lo, s4, v1
s_or_b32 s8, vcc_lo, s8
s_waitcnt vmcnt(0)
v_lshlrev_b32_e32 v5, 2, v5
ds_add_u32 v5, v4
s_and_not1_b32 exec_lo, exec_lo, s8
s_cbranch_execnz .LBB0_5
.LBB0_6:
s_or_b32 exec_lo, exec_lo, s5
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_mov_b32 s2, exec_lo
v_cmpx_gt_u32_e32 0x100, v0
s_cbranch_execz .LBB0_9
s_load_b64 s[0:1], s[0:1], 0x10
v_lshlrev_b32_e32 v3, 2, v0
s_lshl_b32 s2, s3, 2
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v1, s0, s0, v3
v_add_co_ci_u32_e64 v2, null, s1, 0, s0
s_mov_b32 s1, 0
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 s4, s1
.LBB0_8:
ds_load_b32 v4, v3
v_add_nc_u32_e32 v0, s3, v0
v_add_nc_u32_e32 v3, s2, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_1)
v_cmp_lt_u32_e32 vcc_lo, 0xff, v0
s_or_b32 s4, vcc_lo, s4
s_waitcnt lgkmcnt(0)
global_atomic_add_u32 v[1:2], v4, off
v_add_co_u32 v1, s0, v1, s2
v_add_co_ci_u32_e64 v2, s0, s1, v2, s0
s_and_not1_b32 exec_lo, exec_lo, s4
s_cbranch_execnz .LBB0_8
.LBB0_9:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7calcGisPhiPi
.amdhsa_group_segment_fixed_size 1024
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z7calcGisPhiPi, .Lfunc_end0-_Z7calcGisPhiPi
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z4scanPi
.globl _Z4scanPi
.p2align 8
.type _Z4scanPi,@function
_Z4scanPi:
s_load_b32 s2, s[0:1], 0x14
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e32 0x100, v2
s_cbranch_execz .LBB1_10
s_load_b64 s[0:1], s[0:1], 0x0
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b32_e32 v4, 1, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[2:3]
v_ashrrev_i32_e32 v3, 5, v2
v_add_lshl_u32 v3, v3, v2, 2
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_mov_b32 s0, 1
global_load_b32 v5, v[0:1], off
s_waitcnt vmcnt(0)
ds_store_b32 v3, v5
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_set_inst_prefetch_distance 0x1
s_branch .LBB1_3
.p2align 6
.LBB1_2:
s_or_b32 exec_lo, exec_lo, s1
s_lshl_b32 s1, s0, 1
s_cmpk_lt_u32 s0, 0x80
s_mov_b32 s0, s1
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc0 .LBB1_5
.LBB1_3:
v_mul_lo_u32 v5, v4, s0
s_mov_b32 s1, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add3_u32 v5, s0, -1, v5
v_add_nc_u32_e32 v6, s0, v5
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e32 0x100, v6
s_cbranch_execz .LBB1_2
v_ashrrev_i32_e32 v7, 5, v5
v_ashrrev_i32_e32 v8, 5, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_lshl_u32 v5, v7, v5, 2
v_add_lshl_u32 v6, v8, v6, 2
ds_load_b32 v5, v5
ds_load_b32 v7, v6
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v5, v7, v5
ds_store_b32 v6, v5
s_branch .LBB1_2
.LBB1_5:
s_set_inst_prefetch_distance 0x2
v_mov_b32_e32 v4, 0
v_add_nc_u32_e32 v2, 1, v2
s_movk_i32 s0, 0x100
ds_store_b32 v4, v4 offset:1048
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_set_inst_prefetch_distance 0x1
s_branch .LBB1_7
.p2align 6
.LBB1_6:
s_or_b32 exec_lo, exec_lo, s1
s_lshr_b32 s1, s0, 1
s_cmp_gt_u32 s0, 3
s_mov_b32 s0, s1
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc0 .LBB1_9
.LBB1_7:
v_mul_lo_u32 v4, s0, v2
s_mov_b32 s1, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e32 0x101, v4
s_cbranch_execz .LBB1_6
v_add_nc_u32_e32 v4, -1, v4
s_lshr_b32 s2, s0, 1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v5, 5, v4
v_add_lshl_u32 v5, v5, v4, 2
v_subrev_nc_u32_e32 v4, s2, v4
ds_load_b32 v6, v5
v_ashrrev_i32_e32 v7, 5, v4
s_delay_alu instid0(VALU_DEP_1)
v_add_lshl_u32 v4, v7, v4, 2
ds_load_b32 v7, v4
s_waitcnt lgkmcnt(1)
ds_store_b32 v4, v6
ds_load_b32 v4, v5
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v4, v4, v7
ds_store_b32 v5, v4
s_branch .LBB1_6
.LBB1_9:
s_set_inst_prefetch_distance 0x2
s_barrier
buffer_gl0_inv
global_load_b32 v2, v[0:1], off
ds_load_b32 v3, v3
s_waitcnt vmcnt(0) lgkmcnt(0)
v_add_nc_u32_e32 v2, v2, v3
global_store_b32 v[0:1], v2, off
.LBB1_10:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z4scanPi
.amdhsa_group_segment_fixed_size 1056
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 264
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z4scanPi, .Lfunc_end1-_Z4scanPi
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z6outGisPhiPi
.globl _Z6outGisPhiPi
.p2align 8
.type _Z6outGisPhiPi,@function
_Z6outGisPhiPi:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x24
s_load_b32 s6, s[0:1], 0x8
s_add_u32 s2, s0, 24
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s7, s4, 0xffff
s_mov_b32 s4, exec_lo
v_mad_u64_u32 v[1:2], null, s15, s7, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s6, v1
s_cbranch_execz .LBB2_5
s_load_b32 s8, s[2:3], 0x0
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x0
s_load_b64 s[4:5], s[0:1], 0x10
v_mov_b32_e32 v0, 0
s_waitcnt lgkmcnt(0)
s_mul_i32 s1, s8, s7
s_mov_b32 s7, 0
.p2align 6
.LBB2_2:
s_delay_alu instid0(VALU_DEP_1)
v_mov_b32_e32 v2, v0
s_mov_b32 s0, 0
.LBB2_3:
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mov_b32_e32 v0, v2
v_and_b32_e32 v2, 0xff, v0
s_delay_alu instid0(VALU_DEP_1)
v_lshlrev_b32_e32 v2, 2, v2
global_load_b32 v2, v2, s[4:5]
s_waitcnt vmcnt(0)
v_cmp_gt_i32_e32 vcc_lo, v2, v1
v_add_nc_u16 v2, v0, 1
s_or_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB2_3
s_or_b32 exec_lo, exec_lo, s0
v_ashrrev_i32_e32 v3, 31, v1
v_add_co_u32 v2, vcc_lo, s2, v1
v_add_nc_u32_e32 v1, s1, v1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
v_cmp_le_i32_e64 s0, s6, v1
global_store_b8 v[2:3], v0, off
s_or_b32 s7, s0, s7
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s7
s_cbranch_execnz .LBB2_2
.LBB2_5:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6outGisPhiPi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end2:
.size _Z6outGisPhiPi, .Lfunc_end2-_Z6outGisPhiPi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 1024
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7calcGisPhiPi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z7calcGisPhiPi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: hidden_block_count_x
- .offset: 12
.size: 4
.value_kind: hidden_block_count_y
- .offset: 16
.size: 4
.value_kind: hidden_block_count_z
- .offset: 20
.size: 2
.value_kind: hidden_group_size_x
- .offset: 22
.size: 2
.value_kind: hidden_group_size_y
- .offset: 24
.size: 2
.value_kind: hidden_group_size_z
- .offset: 26
.size: 2
.value_kind: hidden_remainder_x
- .offset: 28
.size: 2
.value_kind: hidden_remainder_y
- .offset: 30
.size: 2
.value_kind: hidden_remainder_z
- .offset: 48
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 72
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 1056
.kernarg_segment_align: 8
.kernarg_segment_size: 264
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z4scanPi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z4scanPi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6outGisPhiPi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6outGisPhiPi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
typedef unsigned char uchar;
__global__ void calcGis(uchar* data, int n, int* height) {
int idx = threadIdx.x + blockIdx.x * blockDim.x;
int offsetx = gridDim.x * blockDim.x;
__shared__ int tmp[256];
for(int i = threadIdx.x; i<256; i+=blockDim.x){
tmp[i]=0;
}
__syncthreads();
for(int i = idx; i < n; i += offsetx){
atomicAdd(tmp+(int)data[i], 1);
}
__syncthreads();
for(int i = threadIdx.x; i<256; i+=blockDim.x){
atomicAdd(height + i, tmp[i]);
}
}
__global__ void scan(int* height){
int idx = threadIdx.x + blockIdx.x * blockDim.x;
int forSwap,k;
__shared__ int data[264];
if(idx<256){
data[idx+(idx>>5)]=height[idx];
__syncthreads();
for(k=1;k<256;k*=2){
int j=idx*k*2+k-1;
if(j+k<256){
data[((j+k)>>5)+(j+k)]+=data[j+(j>>5)];
}
__syncthreads();
}
data[((255)>>5)+(255)]=0;
__syncthreads();
for( k=256;k>1;k/=2){
int j=k*(idx+1)-1;
if(j<256){
forSwap=data[((j-k/2)>>5)+(j-k/2)];
data[((j-k/2)>>5)+(j-k/2)]=data[(j>>5)+j];
data[(j>>5)+j]=forSwap+data[(j>>5)+j];
}
__syncthreads();
}
__syncthreads();
height[idx]+=data[idx+(idx>>5)];
}
}
__global__ void outGis(uchar* data, int n, int* height) {
int idx = threadIdx.x + blockIdx.x * blockDim.x;
int offsetx = gridDim.x * blockDim.x;
uchar j = 0;
for(int i = idx; i < n; i += offsetx){
while(height[j] <= i){
j++;
}
data[i] = j;
}
}
int main() {
int size = 256;
int n;
fread(&n, sizeof(int), 1, stdin);
uchar* data = (uchar*) malloc(sizeof(uchar) * n);
fread(data, sizeof(uchar), n, stdin);
int *height1;
uchar *data1;
hipMalloc(&data1, n * sizeof(uchar));
hipMemcpy(data1, data, n*sizeof(uchar), hipMemcpyHostToDevice);
hipMalloc(&height1, size * sizeof(int));
hipMemset(height1, 0, size * sizeof(int));
dim3 threads = 256;
dim3 blocks = 256;
calcGis<<<blocks, threads>>>(data1, n, height1);
scan<<<blocks, threads>>>(height1);
outGis<<<blocks, threads>>>(data1, n, height1);
hipMemcpy(data, data1, n * sizeof(uchar), hipMemcpyDeviceToHost);
hipFree(height1);
hipFree(data1);
fwrite(data, sizeof(uchar), n, stdout);
free(data);
return 0;
} | .text
.file "lab5.hip"
.globl _Z22__device_stub__calcGisPhiPi # -- Begin function _Z22__device_stub__calcGisPhiPi
.p2align 4, 0x90
.type _Z22__device_stub__calcGisPhiPi,@function
_Z22__device_stub__calcGisPhiPi: # @_Z22__device_stub__calcGisPhiPi
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movl %esi, 12(%rsp)
movq %rdx, 64(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z7calcGisPhiPi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z22__device_stub__calcGisPhiPi, .Lfunc_end0-_Z22__device_stub__calcGisPhiPi
.cfi_endproc
# -- End function
.globl _Z19__device_stub__scanPi # -- Begin function _Z19__device_stub__scanPi
.p2align 4, 0x90
.type _Z19__device_stub__scanPi,@function
_Z19__device_stub__scanPi: # @_Z19__device_stub__scanPi
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z4scanPi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end1:
.size _Z19__device_stub__scanPi, .Lfunc_end1-_Z19__device_stub__scanPi
.cfi_endproc
# -- End function
.globl _Z21__device_stub__outGisPhiPi # -- Begin function _Z21__device_stub__outGisPhiPi
.p2align 4, 0x90
.type _Z21__device_stub__outGisPhiPi,@function
_Z21__device_stub__outGisPhiPi: # @_Z21__device_stub__outGisPhiPi
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movl %esi, 12(%rsp)
movq %rdx, 64(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6outGisPhiPi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end2:
.size _Z21__device_stub__outGisPhiPi, .Lfunc_end2-_Z21__device_stub__outGisPhiPi
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $136, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movabsq $4294967552, %r15 # imm = 0x100000100
movq stdin(%rip), %rcx
leaq 108(%rsp), %rdi
movl $4, %esi
movl $1, %edx
callq fread
movl 108(%rsp), %ebp
movslq %ebp, %rbx
movq %rbx, %rdi
callq malloc
movq %rax, %r14
movq stdin(%rip), %rcx
movl $1, %esi
movq %rax, %rdi
movq %rbx, %rdx
callq fread
leaq 32(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
movq 32(%rsp), %rdi
movq %r14, %rsi
movq %rbx, %rdx
movl $1, %ecx
callq hipMemcpy
leaq 40(%rsp), %rdi
movl $1024, %esi # imm = 0x400
callq hipMalloc
movq 40(%rsp), %rdi
movl $1024, %edx # imm = 0x400
xorl %esi, %esi
callq hipMemset
movq %r15, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_2
# %bb.1:
movq 32(%rsp), %rax
movq 40(%rsp), %rcx
movq %rax, 72(%rsp)
movl %ebp, 12(%rsp)
movq %rcx, 64(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
leaq 64(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rdi
leaq 80(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 96(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 80(%rsp), %rcx
movl 88(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z7calcGisPhiPi, %edi
pushq 96(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_2:
movq %r15, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_4
# %bb.3:
movq 40(%rsp), %rax
movq %rax, 80(%rsp)
leaq 80(%rsp), %rax
movq %rax, 16(%rsp)
leaq 112(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 72(%rsp), %rdx
leaq 64(%rsp), %rcx
callq __hipPopCallConfiguration
movq 112(%rsp), %rsi
movl 120(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z4scanPi, %edi
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
pushq 80(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_4:
movq %r15, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_6
# %bb.5:
movq 32(%rsp), %rax
movq 40(%rsp), %rcx
movq %rax, 72(%rsp)
movl %ebp, 12(%rsp)
movq %rcx, 64(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
leaq 64(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rdi
leaq 80(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 96(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 80(%rsp), %rcx
movl 88(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z6outGisPhiPi, %edi
pushq 96(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_6:
movq 32(%rsp), %rsi
movq %r14, %rdi
movq %rbx, %rdx
movl $2, %ecx
callq hipMemcpy
movq 40(%rsp), %rdi
callq hipFree
movq 32(%rsp), %rdi
callq hipFree
movq stdout(%rip), %rcx
movl $1, %esi
movq %r14, %rdi
movq %rbx, %rdx
callq fwrite
movq %r14, %rdi
callq free
xorl %eax, %eax
addq $136, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7calcGisPhiPi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z4scanPi, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6outGisPhiPi, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z7calcGisPhiPi,@object # @_Z7calcGisPhiPi
.section .rodata,"a",@progbits
.globl _Z7calcGisPhiPi
.p2align 3, 0x0
_Z7calcGisPhiPi:
.quad _Z22__device_stub__calcGisPhiPi
.size _Z7calcGisPhiPi, 8
.type _Z4scanPi,@object # @_Z4scanPi
.globl _Z4scanPi
.p2align 3, 0x0
_Z4scanPi:
.quad _Z19__device_stub__scanPi
.size _Z4scanPi, 8
.type _Z6outGisPhiPi,@object # @_Z6outGisPhiPi
.globl _Z6outGisPhiPi
.p2align 3, 0x0
_Z6outGisPhiPi:
.quad _Z21__device_stub__outGisPhiPi
.size _Z6outGisPhiPi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z7calcGisPhiPi"
.size .L__unnamed_1, 16
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z4scanPi"
.size .L__unnamed_2, 10
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z6outGisPhiPi"
.size .L__unnamed_3, 15
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__calcGisPhiPi
.addrsig_sym _Z19__device_stub__scanPi
.addrsig_sym _Z21__device_stub__outGisPhiPi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7calcGisPhiPi
.addrsig_sym _Z4scanPi
.addrsig_sym _Z6outGisPhiPi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0011e653_00000000-6_lab5.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z29__device_stub__Z7calcGisPhiPiPhiPi
.type _Z29__device_stub__Z7calcGisPhiPiPhiPi, @function
_Z29__device_stub__Z7calcGisPhiPiPhiPi:
.LFB2082:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z7calcGisPhiPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z29__device_stub__Z7calcGisPhiPiPhiPi, .-_Z29__device_stub__Z7calcGisPhiPiPhiPi
.globl _Z7calcGisPhiPi
.type _Z7calcGisPhiPi, @function
_Z7calcGisPhiPi:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z7calcGisPhiPiPhiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z7calcGisPhiPi, .-_Z7calcGisPhiPi
.globl _Z23__device_stub__Z4scanPiPi
.type _Z23__device_stub__Z4scanPiPi, @function
_Z23__device_stub__Z4scanPiPi:
.LFB2084:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z4scanPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z23__device_stub__Z4scanPiPi, .-_Z23__device_stub__Z4scanPiPi
.globl _Z4scanPi
.type _Z4scanPi, @function
_Z4scanPi:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z23__device_stub__Z4scanPiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z4scanPi, .-_Z4scanPi
.globl _Z28__device_stub__Z6outGisPhiPiPhiPi
.type _Z28__device_stub__Z6outGisPhiPiPhiPi, @function
_Z28__device_stub__Z6outGisPhiPiPhiPi:
.LFB2086:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L23
.L19:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L24
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6outGisPhiPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L19
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2086:
.size _Z28__device_stub__Z6outGisPhiPiPhiPi, .-_Z28__device_stub__Z6outGisPhiPiPhiPi
.globl _Z6outGisPhiPi
.type _Z6outGisPhiPi, @function
_Z6outGisPhiPi:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z28__device_stub__Z6outGisPhiPiPhiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _Z6outGisPhiPi, .-_Z6outGisPhiPi
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $72, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rdi
movq stdin(%rip), %r8
movl $1, %ecx
movl $4, %edx
movl $4, %esi
call __fread_chk@PLT
movslq 12(%rsp), %rbp
movq %rbp, %rdi
call malloc@PLT
movq %rax, %rbx
movq stdin(%rip), %r8
movq %rbp, %rcx
movl $1, %edx
movq %rbp, %rsi
movq %rax, %rdi
call __fread_chk@PLT
movslq 12(%rsp), %rsi
leaq 24(%rsp), %rdi
call cudaMalloc@PLT
movslq 12(%rsp), %rdx
movl $1, %ecx
movq %rbx, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
leaq 16(%rsp), %rdi
movl $1024, %esi
call cudaMalloc@PLT
movl $1024, %edx
movl $0, %esi
movq 16(%rsp), %rdi
call cudaMemset@PLT
movl $256, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $256, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 32(%rsp), %rdx
movl $1, %ecx
movq 44(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L33
.L28:
movl 40(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 32(%rsp), %rdx
movq 44(%rsp), %rdi
movl 52(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L34
.L29:
movl 40(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 32(%rsp), %rdx
movq 44(%rsp), %rdi
movl 52(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L35
.L30:
movslq 12(%rsp), %rdx
movl $2, %ecx
movq 24(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movslq 12(%rsp), %rdx
movq stdout(%rip), %rcx
movl $1, %esi
movq %rbx, %rdi
call fwrite@PLT
movq %rbx, %rdi
call free@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L36
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L33:
.cfi_restore_state
movq 16(%rsp), %rdx
movl 12(%rsp), %esi
movq 24(%rsp), %rdi
call _Z29__device_stub__Z7calcGisPhiPiPhiPi
jmp .L28
.L34:
movq 16(%rsp), %rdi
call _Z23__device_stub__Z4scanPiPi
jmp .L29
.L35:
movq 16(%rsp), %rdx
movl 12(%rsp), %esi
movq 24(%rsp), %rdi
call _Z28__device_stub__Z6outGisPhiPiPhiPi
jmp .L30
.L36:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z6outGisPhiPi"
.LC1:
.string "_Z4scanPi"
.LC2:
.string "_Z7calcGisPhiPi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2089:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z6outGisPhiPi(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z4scanPi(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z7calcGisPhiPi(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2089:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "lab5.hip"
.globl _Z22__device_stub__calcGisPhiPi # -- Begin function _Z22__device_stub__calcGisPhiPi
.p2align 4, 0x90
.type _Z22__device_stub__calcGisPhiPi,@function
_Z22__device_stub__calcGisPhiPi: # @_Z22__device_stub__calcGisPhiPi
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movl %esi, 12(%rsp)
movq %rdx, 64(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z7calcGisPhiPi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z22__device_stub__calcGisPhiPi, .Lfunc_end0-_Z22__device_stub__calcGisPhiPi
.cfi_endproc
# -- End function
.globl _Z19__device_stub__scanPi # -- Begin function _Z19__device_stub__scanPi
.p2align 4, 0x90
.type _Z19__device_stub__scanPi,@function
_Z19__device_stub__scanPi: # @_Z19__device_stub__scanPi
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z4scanPi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end1:
.size _Z19__device_stub__scanPi, .Lfunc_end1-_Z19__device_stub__scanPi
.cfi_endproc
# -- End function
.globl _Z21__device_stub__outGisPhiPi # -- Begin function _Z21__device_stub__outGisPhiPi
.p2align 4, 0x90
.type _Z21__device_stub__outGisPhiPi,@function
_Z21__device_stub__outGisPhiPi: # @_Z21__device_stub__outGisPhiPi
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movl %esi, 12(%rsp)
movq %rdx, 64(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6outGisPhiPi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end2:
.size _Z21__device_stub__outGisPhiPi, .Lfunc_end2-_Z21__device_stub__outGisPhiPi
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $136, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movabsq $4294967552, %r15 # imm = 0x100000100
movq stdin(%rip), %rcx
leaq 108(%rsp), %rdi
movl $4, %esi
movl $1, %edx
callq fread
movl 108(%rsp), %ebp
movslq %ebp, %rbx
movq %rbx, %rdi
callq malloc
movq %rax, %r14
movq stdin(%rip), %rcx
movl $1, %esi
movq %rax, %rdi
movq %rbx, %rdx
callq fread
leaq 32(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
movq 32(%rsp), %rdi
movq %r14, %rsi
movq %rbx, %rdx
movl $1, %ecx
callq hipMemcpy
leaq 40(%rsp), %rdi
movl $1024, %esi # imm = 0x400
callq hipMalloc
movq 40(%rsp), %rdi
movl $1024, %edx # imm = 0x400
xorl %esi, %esi
callq hipMemset
movq %r15, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_2
# %bb.1:
movq 32(%rsp), %rax
movq 40(%rsp), %rcx
movq %rax, 72(%rsp)
movl %ebp, 12(%rsp)
movq %rcx, 64(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
leaq 64(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rdi
leaq 80(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 96(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 80(%rsp), %rcx
movl 88(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z7calcGisPhiPi, %edi
pushq 96(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_2:
movq %r15, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_4
# %bb.3:
movq 40(%rsp), %rax
movq %rax, 80(%rsp)
leaq 80(%rsp), %rax
movq %rax, 16(%rsp)
leaq 112(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 72(%rsp), %rdx
leaq 64(%rsp), %rcx
callq __hipPopCallConfiguration
movq 112(%rsp), %rsi
movl 120(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z4scanPi, %edi
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
pushq 80(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_4:
movq %r15, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_6
# %bb.5:
movq 32(%rsp), %rax
movq 40(%rsp), %rcx
movq %rax, 72(%rsp)
movl %ebp, 12(%rsp)
movq %rcx, 64(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
leaq 64(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rdi
leaq 80(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 96(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 80(%rsp), %rcx
movl 88(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z6outGisPhiPi, %edi
pushq 96(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_6:
movq 32(%rsp), %rsi
movq %r14, %rdi
movq %rbx, %rdx
movl $2, %ecx
callq hipMemcpy
movq 40(%rsp), %rdi
callq hipFree
movq 32(%rsp), %rdi
callq hipFree
movq stdout(%rip), %rcx
movl $1, %esi
movq %r14, %rdi
movq %rbx, %rdx
callq fwrite
movq %r14, %rdi
callq free
xorl %eax, %eax
addq $136, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7calcGisPhiPi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z4scanPi, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6outGisPhiPi, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z7calcGisPhiPi,@object # @_Z7calcGisPhiPi
.section .rodata,"a",@progbits
.globl _Z7calcGisPhiPi
.p2align 3, 0x0
_Z7calcGisPhiPi:
.quad _Z22__device_stub__calcGisPhiPi
.size _Z7calcGisPhiPi, 8
.type _Z4scanPi,@object # @_Z4scanPi
.globl _Z4scanPi
.p2align 3, 0x0
_Z4scanPi:
.quad _Z19__device_stub__scanPi
.size _Z4scanPi, 8
.type _Z6outGisPhiPi,@object # @_Z6outGisPhiPi
.globl _Z6outGisPhiPi
.p2align 3, 0x0
_Z6outGisPhiPi:
.quad _Z21__device_stub__outGisPhiPi
.size _Z6outGisPhiPi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z7calcGisPhiPi"
.size .L__unnamed_1, 16
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z4scanPi"
.size .L__unnamed_2, 10
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z6outGisPhiPi"
.size .L__unnamed_3, 15
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__calcGisPhiPi
.addrsig_sym _Z19__device_stub__scanPi
.addrsig_sym _Z21__device_stub__outGisPhiPi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7calcGisPhiPi
.addrsig_sym _Z4scanPi
.addrsig_sym _Z6outGisPhiPi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | /*
* Check grid and block dimensions
*/
#include<stdio.h>
__global__ void checkIndex(void)
{
printf("threadIdx : (%d,%d,%d) blockIdx : (%d,%d,%d)) blockDim : (%d,%d,%d) gridDim : (%d,%d,%d)\n ",threadIdx.x,threadIdx.y,threadIdx.z,blockIdx.x,blockIdx.y,blockIdx.z,blockDim.x,blockDim.y,blockDim.z,gridDim.x,gridDim.y,gridDim.z);
}
int main(void)
{ int n=6;
dim3 block(3);
dim3 grid((n+block.x-1)/block.x);
checkIndex<<<grid,block>>>();
cudaDeviceReset();
} | code for sm_80
Function : _Z10checkIndexv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fc800078e00ff */
/*0010*/ S2R R11, SR_CTAID.X ; /* 0x00000000000b7919 */
/* 0x000e220000002500 */
/*0020*/ IADD3 R1, R1, -0x30, RZ ; /* 0xffffffd001017810 */
/* 0x000fe20007ffe0ff */
/*0030*/ IMAD.MOV.U32 R14, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff0e7624 */
/* 0x000fe200078e00ff */
/*0040*/ MOV R18, c[0x0][0x10] ; /* 0x0000040000127a02 */
/* 0x000fe20000000f00 */
/*0050*/ S2R R10, SR_TID.Z ; /* 0x00000000000a7919 */
/* 0x000e220000002300 */
/*0060*/ IMAD.MOV.U32 R15, RZ, RZ, c[0x0][0x4] ; /* 0x00000100ff0f7624 */
/* 0x000fe200078e00ff */
/*0070*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe20000000f00 */
/*0080*/ IMAD.MOV.U32 R16, RZ, RZ, c[0x0][0x8] ; /* 0x00000200ff107624 */
/* 0x000fe200078e00ff */
/*0090*/ S2R R9, SR_TID.Y ; /* 0x0000000000097919 */
/* 0x000e220000002200 */
/*00a0*/ IMAD.MOV.U32 R17, RZ, RZ, c[0x0][0xc] ; /* 0x00000300ff117624 */
/* 0x000fe200078e00ff */
/*00b0*/ LDC.64 R2, c[0x4][R0] ; /* 0x0100000000027b82 */
/* 0x0002a20000000a00 */
/*00c0*/ IMAD.MOV.U32 R19, RZ, RZ, c[0x0][0x14] ; /* 0x00000500ff137624 */
/* 0x000fe200078e00ff */
/*00d0*/ S2R R8, SR_TID.X ; /* 0x0000000000087919 */
/* 0x000e220000002100 */
/*00e0*/ IADD3 R6, P0, R1, c[0x0][0x20], RZ ; /* 0x0000080001067a10 */
/* 0x000fe20007f1e0ff */
/*00f0*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x8] ; /* 0x01000200ff047624 */
/* 0x000fe200078e00ff */
/*0100*/ MOV R5, c[0x4][0xc] ; /* 0x0100030000057a02 */
/* 0x000fe20000000f00 */
/*0110*/ S2R R13, SR_CTAID.Z ; /* 0x00000000000d7919 */
/* 0x000ee40000002700 */
/*0120*/ IMAD.X R7, RZ, RZ, c[0x0][0x24], P0 ; /* 0x00000900ff077624 */
/* 0x000fc400000e06ff */
/*0130*/ S2R R12, SR_CTAID.Y ; /* 0x00000000000c7919 */
/* 0x000ee80000002600 */
/*0140*/ STL.128 [R1+0x20], R16 ; /* 0x0000201001007387 */
/* 0x0003e80000100c00 */
/*0150*/ STL.128 [R1], R8 ; /* 0x0000000801007387 */
/* 0x0013e80000100c00 */
/*0160*/ STL.128 [R1+0x10], R12 ; /* 0x0000100c01007387 */
/* 0x0083e40000100c00 */
/*0170*/ LEPC R8 ; /* 0x000000000008734e */
/* 0x006fe40000000000 */
/*0180*/ MOV R11, 0x1f0 ; /* 0x000001f0000b7802 */
/* 0x000fe40000000f00 */
/*0190*/ MOV R20, 0x170 ; /* 0x0000017000147802 */
/* 0x000fc40000000f00 */
/*01a0*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*01b0*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe40000000f00 */
/*01c0*/ IADD3 R20, P0, P1, -R20, R11, R8 ; /* 0x0000000b14147210 */
/* 0x000fc8000791e108 */
/*01d0*/ IADD3.X R21, ~R0, R21, R9, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2509 */
/*01e0*/ CALL.ABS.NOINC R2 ; /* 0x0000000002007343 */
/* 0x000fea0003c00000 */
/*01f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0200*/ BRA 0x200; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /*
* Check grid and block dimensions
*/
#include<stdio.h>
__global__ void checkIndex(void)
{
printf("threadIdx : (%d,%d,%d) blockIdx : (%d,%d,%d)) blockDim : (%d,%d,%d) gridDim : (%d,%d,%d)\n ",threadIdx.x,threadIdx.y,threadIdx.z,blockIdx.x,blockIdx.y,blockIdx.z,blockDim.x,blockDim.y,blockDim.z,gridDim.x,gridDim.y,gridDim.z);
}
int main(void)
{ int n=6;
dim3 block(3);
dim3 grid((n+block.x-1)/block.x);
checkIndex<<<grid,block>>>();
cudaDeviceReset();
} | .file "tmpxft_0003882d_00000000-6_grids_and_blocks.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z29__device_stub__Z10checkIndexvv
.type _Z29__device_stub__Z10checkIndexvv, @function
_Z29__device_stub__Z10checkIndexvv:
.LFB2082:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z10checkIndexv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z29__device_stub__Z10checkIndexvv, .-_Z29__device_stub__Z10checkIndexvv
.globl _Z10checkIndexv
.type _Z10checkIndexv, @function
_Z10checkIndexv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z10checkIndexvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z10checkIndexv, .-_Z10checkIndexv
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movl $1, 12(%rsp)
movl $2, 20(%rsp)
movl $1, 24(%rsp)
movl $3, 8(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 8(%rsp), %rdx
movl $1, %ecx
movq 20(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L12:
call cudaDeviceReset@PLT
movl $0, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
call _Z29__device_stub__Z10checkIndexvv
jmp .L12
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z10checkIndexv"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z10checkIndexv(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /*
* Check grid and block dimensions
*/
#include<stdio.h>
__global__ void checkIndex(void)
{
printf("threadIdx : (%d,%d,%d) blockIdx : (%d,%d,%d)) blockDim : (%d,%d,%d) gridDim : (%d,%d,%d)\n ",threadIdx.x,threadIdx.y,threadIdx.z,blockIdx.x,blockIdx.y,blockIdx.z,blockDim.x,blockDim.y,blockDim.z,gridDim.x,gridDim.y,gridDim.z);
}
int main(void)
{ int n=6;
dim3 block(3);
dim3 grid((n+block.x-1)/block.x);
checkIndex<<<grid,block>>>();
cudaDeviceReset();
} | /*
* Check grid and block dimensions
*/
#include <hip/hip_runtime.h>
#include<stdio.h>
__global__ void checkIndex(void)
{
printf("threadIdx : (%d,%d,%d) blockIdx : (%d,%d,%d)) blockDim : (%d,%d,%d) gridDim : (%d,%d,%d)\n ",threadIdx.x,threadIdx.y,threadIdx.z,blockIdx.x,blockIdx.y,blockIdx.z,blockDim.x,blockDim.y,blockDim.z,gridDim.x,gridDim.y,gridDim.z);
}
int main(void)
{ int n=6;
dim3 block(3);
dim3 grid((n+block.x-1)/block.x);
checkIndex<<<grid,block>>>();
hipDeviceReset();
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | /*
* Check grid and block dimensions
*/
#include <hip/hip_runtime.h>
#include<stdio.h>
__global__ void checkIndex(void)
{
printf("threadIdx : (%d,%d,%d) blockIdx : (%d,%d,%d)) blockDim : (%d,%d,%d) gridDim : (%d,%d,%d)\n ",threadIdx.x,threadIdx.y,threadIdx.z,blockIdx.x,blockIdx.y,blockIdx.z,blockDim.x,blockDim.y,blockDim.z,gridDim.x,gridDim.y,gridDim.z);
}
int main(void)
{ int n=6;
dim3 block(3);
dim3 grid((n+block.x-1)/block.x);
checkIndex<<<grid,block>>>();
hipDeviceReset();
} | .text
.file "grids_and_blocks.hip"
.globl _Z25__device_stub__checkIndexv # -- Begin function _Z25__device_stub__checkIndexv
.p2align 4, 0x90
.type _Z25__device_stub__checkIndexv,@function
_Z25__device_stub__checkIndexv: # @_Z25__device_stub__checkIndexv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z10checkIndexv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z25__device_stub__checkIndexv, .Lfunc_end0-_Z25__device_stub__checkIndexv
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
movabsq $4294967298, %rdi # imm = 0x100000002
leaq 1(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z10checkIndexv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
callq hipDeviceReset
xorl %eax, %eax
addq $56, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10checkIndexv, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10checkIndexv,@object # @_Z10checkIndexv
.section .rodata,"a",@progbits
.globl _Z10checkIndexv
.p2align 3, 0x0
_Z10checkIndexv:
.quad _Z25__device_stub__checkIndexv
.size _Z10checkIndexv, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z10checkIndexv"
.size .L__unnamed_1, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__checkIndexv
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10checkIndexv
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0003882d_00000000-6_grids_and_blocks.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z29__device_stub__Z10checkIndexvv
.type _Z29__device_stub__Z10checkIndexvv, @function
_Z29__device_stub__Z10checkIndexvv:
.LFB2082:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z10checkIndexv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z29__device_stub__Z10checkIndexvv, .-_Z29__device_stub__Z10checkIndexvv
.globl _Z10checkIndexv
.type _Z10checkIndexv, @function
_Z10checkIndexv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z10checkIndexvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z10checkIndexv, .-_Z10checkIndexv
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movl $1, 12(%rsp)
movl $2, 20(%rsp)
movl $1, 24(%rsp)
movl $3, 8(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 8(%rsp), %rdx
movl $1, %ecx
movq 20(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L12:
call cudaDeviceReset@PLT
movl $0, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
call _Z29__device_stub__Z10checkIndexvv
jmp .L12
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z10checkIndexv"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z10checkIndexv(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "grids_and_blocks.hip"
.globl _Z25__device_stub__checkIndexv # -- Begin function _Z25__device_stub__checkIndexv
.p2align 4, 0x90
.type _Z25__device_stub__checkIndexv,@function
_Z25__device_stub__checkIndexv: # @_Z25__device_stub__checkIndexv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z10checkIndexv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z25__device_stub__checkIndexv, .Lfunc_end0-_Z25__device_stub__checkIndexv
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
movabsq $4294967298, %rdi # imm = 0x100000002
leaq 1(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z10checkIndexv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
callq hipDeviceReset
xorl %eax, %eax
addq $56, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10checkIndexv, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10checkIndexv,@object # @_Z10checkIndexv
.section .rodata,"a",@progbits
.globl _Z10checkIndexv
.p2align 3, 0x0
_Z10checkIndexv:
.quad _Z25__device_stub__checkIndexv
.size _Z10checkIndexv, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z10checkIndexv"
.size .L__unnamed_1, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__checkIndexv
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10checkIndexv
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdint.h>
#include <stdio.h>
#include <stdlib.h>
#include <thrust/device_vector.h>
#include <thrust/execution_policy.h>
#include <thrust/host_vector.h>
#include <thrust/scan.h>
#define MAX_VALUE ((1UL << 24) + 1U)
#define BLOCK_DIM (16U)
#define GRID_DIM (16U)
typedef unsigned uint;
#define CSC(call) \
do { \
cudaError_t res = call; \
if (res != cudaSuccess) { \
fprintf(stderr, "ERROR in %s:%d. Message: %s\n", \
__FILE__, __LINE__, cudaGetErrorString(res)); \
exit(0); \
} \
} while(0)
__global__ static void hist(
const int * __restrict__ const input,
int * __restrict__ const counts,
const uint count
) {
const uint offset = blockDim.x * gridDim.x;
uint idx = threadIdx.x + blockIdx.x * blockDim.x;
for (; idx < count; idx += offset)
atomicAdd(counts + input[idx], 1);
}
__global__ static void sort(
const int * __restrict__ const input,
int * __restrict__ const counts,
int * __restrict__ const output,
const uint count
) {
const uint offset = blockDim.x * gridDim.x;
uint idx = threadIdx.x + blockIdx.x * blockDim.x;
for (; idx < count; idx += offset) {
const int i = atomicAdd(counts + input[idx], -1) - 1;
output[i] = input[idx];
}
}
int main(void) {
uint count;
fread(&count, sizeof(uint), 1U, stdin);
const uint size = sizeof(int) * count;
int *buffer = (int *) malloc(size);
fread(buffer, sizeof(int), count, stdin);
int *deviceInput;
CSC(cudaMalloc(&deviceInput, size));
CSC(cudaMemcpy(deviceInput, buffer, size, cudaMemcpyHostToDevice));
int *deviceCounts;
CSC(cudaMalloc(&deviceCounts, sizeof(int) * MAX_VALUE));
CSC(cudaMemset(deviceCounts, 0, sizeof(int) * MAX_VALUE));
int *deviceOutput;
CSC(cudaMalloc(&deviceOutput, size));
cudaEvent_t startTime, endTime;
CSC(cudaEventCreate(&startTime));
CSC(cudaEventCreate(&endTime));
CSC(cudaEventRecord(startTime));
hist<<<GRID_DIM, BLOCK_DIM>>>(deviceInput, deviceCounts, count);
thrust::inclusive_scan(thrust::device,
deviceCounts, deviceCounts + MAX_VALUE, deviceCounts
);
sort<<<GRID_DIM, BLOCK_DIM>>>(deviceInput, deviceCounts, deviceOutput, count);
CSC(cudaGetLastError());
CSC(cudaEventRecord(endTime));
CSC(cudaEventSynchronize(endTime));
float t;
CSC(cudaEventElapsedTime(&t, startTime, endTime));
CSC(cudaEventDestroy(startTime));
CSC(cudaEventDestroy(endTime));
CSC(cudaMemcpy(buffer, deviceOutput, sizeof(int) * count,
cudaMemcpyDeviceToHost
));
CSC(cudaFree(deviceInput));
CSC(cudaFree(deviceOutput));
fwrite(buffer, sizeof(int), count, stdout);
free(buffer);
return 0;
} | #include <hip/hip_runtime.h>
#include <stdint.h>
#include <stdio.h>
#include <stdlib.h>
#include <thrust/device_vector.h>
#include <thrust/execution_policy.h>
#include <thrust/host_vector.h>
#include <thrust/scan.h>
#define MAX_VALUE ((1UL << 24) + 1U)
#define BLOCK_DIM (16U)
#define GRID_DIM (16U)
typedef unsigned uint;
#define CSC(call) \
do { \
hipError_t res = call; \
if (res != hipSuccess) { \
fprintf(stderr, "ERROR in %s:%d. Message: %s\n", \
__FILE__, __LINE__, hipGetErrorString(res)); \
exit(0); \
} \
} while(0)
__global__ static void hist(
const int * __restrict__ const input,
int * __restrict__ const counts,
const uint count
) {
const uint offset = blockDim.x * gridDim.x;
uint idx = threadIdx.x + blockIdx.x * blockDim.x;
for (; idx < count; idx += offset)
atomicAdd(counts + input[idx], 1);
}
__global__ static void sort(
const int * __restrict__ const input,
int * __restrict__ const counts,
int * __restrict__ const output,
const uint count
) {
const uint offset = blockDim.x * gridDim.x;
uint idx = threadIdx.x + blockIdx.x * blockDim.x;
for (; idx < count; idx += offset) {
const int i = atomicAdd(counts + input[idx], -1) - 1;
output[i] = input[idx];
}
}
int main(void) {
uint count;
fread(&count, sizeof(uint), 1U, stdin);
const uint size = sizeof(int) * count;
int *buffer = (int *) malloc(size);
fread(buffer, sizeof(int), count, stdin);
int *deviceInput;
CSC(hipMalloc(&deviceInput, size));
CSC(hipMemcpy(deviceInput, buffer, size, hipMemcpyHostToDevice));
int *deviceCounts;
CSC(hipMalloc(&deviceCounts, sizeof(int) * MAX_VALUE));
CSC(hipMemset(deviceCounts, 0, sizeof(int) * MAX_VALUE));
int *deviceOutput;
CSC(hipMalloc(&deviceOutput, size));
hipEvent_t startTime, endTime;
CSC(hipEventCreate(&startTime));
CSC(hipEventCreate(&endTime));
CSC(hipEventRecord(startTime));
hist<<<GRID_DIM, BLOCK_DIM>>>(deviceInput, deviceCounts, count);
thrust::inclusive_scan(thrust::device,
deviceCounts, deviceCounts + MAX_VALUE, deviceCounts
);
sort<<<GRID_DIM, BLOCK_DIM>>>(deviceInput, deviceCounts, deviceOutput, count);
CSC(hipGetLastError());
CSC(hipEventRecord(endTime));
CSC(hipEventSynchronize(endTime));
float t;
CSC(hipEventElapsedTime(&t, startTime, endTime));
CSC(hipEventDestroy(startTime));
CSC(hipEventDestroy(endTime));
CSC(hipMemcpy(buffer, deviceOutput, sizeof(int) * count,
hipMemcpyDeviceToHost
));
CSC(hipFree(deviceInput));
CSC(hipFree(deviceOutput));
fwrite(buffer, sizeof(int), count, stdout);
free(buffer);
return 0;
} |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
# include <bits/stdc++.h>
# include <cuda.h>
#define SIZE 60// Global Size
#define BLOCK_SIZE 1024
using namespace std;
//::::::::::::::::::::::::::::::::::::::::::GPU::::::::::::::::::::::::::::::::
// :::: Kernel
// :::: Calls
__global__ void kernel_prefix_sum_inefficient(double *g_idata,double *g_odata,int l){ // Sequential Addressing technique
__shared__ double sdata[BLOCK_SIZE];
// each thread loads one element from global to shared mem
unsigned int tid = threadIdx.x;
unsigned int i = blockIdx.x*blockDim.x + threadIdx.x;
if(i<l && tid !=0){
sdata[tid] = g_idata[i-1];
}else{
sdata[tid] = 0;
}
// do reduction in shared mem
for(unsigned int s=1;s<=tid;s *=2){
__syncthreads();
sdata[tid]+=sdata[tid-s];
}
// write result for this block to global mem
g_odata[i] = sdata[tid];
} | code for sm_80
Function : _Z29kernel_prefix_sum_inefficientPdS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0030*/ BSSY B0, 0x120 ; /* 0x000000e000007945 */
/* 0x000fe40003800000 */
/*0040*/ S2R R7, SR_TID.X ; /* 0x0000000000077919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R7 ; /* 0x0000000000007a24 */
/* 0x001fe200078e0207 */
/*0060*/ ISETP.NE.AND P1, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fc80003f25270 */
/*0070*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x000fc80003f06070 */
/*0080*/ ISETP.NE.AND P0, PT, R7, RZ, !P0 ; /* 0x000000ff0700720c */
/* 0x000fda0004705270 */
/*0090*/ @!P0 STS.64 [R7.X8], RZ ; /* 0x000000ff07008388 */
/* 0x0001e20000008a00 */
/*00a0*/ @!P0 CS2R R2, SRZ ; /* 0x0000000000028805 */
/* 0x000fe2000001ff00 */
/*00b0*/ @!P0 BRA 0x110 ; /* 0x0000005000008947 */
/* 0x000fea0003800000 */
/*00c0*/ IADD3 R2, R0, -0x1, RZ ; /* 0xffffffff00027810 */
/* 0x000fe20007ffe0ff */
/*00d0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x8 ; /* 0x00000008ff037424 */
/* 0x000fc800078e00ff */
/*00e0*/ IMAD.WIDE.U32 R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fcc00078e0003 */
/*00f0*/ LDG.E.64 R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1b00 */
/*0100*/ STS.64 [R7.X8], R2 ; /* 0x0000000207007388 */
/* 0x0043e40000008a00 */
/*0110*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0120*/ @!P1 BRA 0x1e0 ; /* 0x000000b000009947 */
/* 0x000fea0003800000 */
/*0130*/ HFMA2.MMA R6, -RZ, RZ, 0, 5.9604644775390625e-08 ; /* 0x00000001ff067435 */
/* 0x000fd000000001ff */
/*0140*/ WARPSYNC 0xffffffff ; /* 0xffffffff00007948 */
/* 0x000fe20003800000 */
/*0150*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0160*/ IMAD.IADD R4, R7, 0x1, -R6 ; /* 0x0000000107047824 */
/* 0x000fe200078e0a06 */
/*0170*/ SHF.L.U32 R6, R6, 0x1, RZ ; /* 0x0000000106067819 */
/* 0x000fc800000006ff */
/*0180*/ ISETP.GE.U32.AND P0, PT, R7, R6, PT ; /* 0x000000060700720c */
/* 0x000fe20003f06070 */
/*0190*/ LDS.64 R4, [R4.X8] ; /* 0x0000000004047984 */
/* 0x000fe80000008a00 */
/*01a0*/ LDS.64 R2, [R7.X8] ; /* 0x0000000007027984 */
/* 0x002e640000008a00 */
/*01b0*/ DADD R2, R2, R4 ; /* 0x0000000002027229 */
/* 0x002e4e0000000004 */
/*01c0*/ STS.64 [R7.X8], R2 ; /* 0x0000000207007388 */
/* 0x0023e20000008a00 */
/*01d0*/ @P0 BRA 0x140 ; /* 0xffffff6000000947 */
/* 0x000fea000383ffff */
/*01e0*/ IMAD.MOV.U32 R5, RZ, RZ, 0x8 ; /* 0x00000008ff057424 */
/* 0x000fc800078e00ff */
/*01f0*/ IMAD.WIDE.U32 R4, R0, R5, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x000fca00078e0005 */
/*0200*/ STG.E.64 [R4.64], R2 ; /* 0x0000000204007986 */
/* 0x000fe2000c101b04 */
/*0210*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0220*/ BRA 0x220; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
# include <bits/stdc++.h>
# include <cuda.h>
#define SIZE 60// Global Size
#define BLOCK_SIZE 1024
using namespace std;
//::::::::::::::::::::::::::::::::::::::::::GPU::::::::::::::::::::::::::::::::
// :::: Kernel
// :::: Calls
__global__ void kernel_prefix_sum_inefficient(double *g_idata,double *g_odata,int l){ // Sequential Addressing technique
__shared__ double sdata[BLOCK_SIZE];
// each thread loads one element from global to shared mem
unsigned int tid = threadIdx.x;
unsigned int i = blockIdx.x*blockDim.x + threadIdx.x;
if(i<l && tid !=0){
sdata[tid] = g_idata[i-1];
}else{
sdata[tid] = 0;
}
// do reduction in shared mem
for(unsigned int s=1;s<=tid;s *=2){
__syncthreads();
sdata[tid]+=sdata[tid-s];
}
// write result for this block to global mem
g_odata[i] = sdata[tid];
} | .file "tmpxft_000a084f_00000000-6_kernel_prefix_sum_inefficient.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB10861:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE10861:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z52__device_stub__Z29kernel_prefix_sum_inefficientPdS_iPdS_i
.type _Z52__device_stub__Z29kernel_prefix_sum_inefficientPdS_iPdS_i, @function
_Z52__device_stub__Z29kernel_prefix_sum_inefficientPdS_iPdS_i:
.LFB10883:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z29kernel_prefix_sum_inefficientPdS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE10883:
.size _Z52__device_stub__Z29kernel_prefix_sum_inefficientPdS_iPdS_i, .-_Z52__device_stub__Z29kernel_prefix_sum_inefficientPdS_iPdS_i
.globl _Z29kernel_prefix_sum_inefficientPdS_i
.type _Z29kernel_prefix_sum_inefficientPdS_i, @function
_Z29kernel_prefix_sum_inefficientPdS_i:
.LFB10884:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z52__device_stub__Z29kernel_prefix_sum_inefficientPdS_iPdS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE10884:
.size _Z29kernel_prefix_sum_inefficientPdS_i, .-_Z29kernel_prefix_sum_inefficientPdS_i
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z29kernel_prefix_sum_inefficientPdS_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB10886:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z29kernel_prefix_sum_inefficientPdS_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE10886:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
# include <bits/stdc++.h>
# include <cuda.h>
#define SIZE 60// Global Size
#define BLOCK_SIZE 1024
using namespace std;
//::::::::::::::::::::::::::::::::::::::::::GPU::::::::::::::::::::::::::::::::
// :::: Kernel
// :::: Calls
__global__ void kernel_prefix_sum_inefficient(double *g_idata,double *g_odata,int l){ // Sequential Addressing technique
__shared__ double sdata[BLOCK_SIZE];
// each thread loads one element from global to shared mem
unsigned int tid = threadIdx.x;
unsigned int i = blockIdx.x*blockDim.x + threadIdx.x;
if(i<l && tid !=0){
sdata[tid] = g_idata[i-1];
}else{
sdata[tid] = 0;
}
// do reduction in shared mem
for(unsigned int s=1;s<=tid;s *=2){
__syncthreads();
sdata[tid]+=sdata[tid-s];
}
// write result for this block to global mem
g_odata[i] = sdata[tid];
} | #include "includes.h"
# include <bits/stdc++.h>
# include <hip/hip_runtime.h>
#define SIZE 60// Global Size
#define BLOCK_SIZE 1024
using namespace std;
//::::::::::::::::::::::::::::::::::::::::::GPU::::::::::::::::::::::::::::::::
// :::: Kernel
// :::: Calls
__global__ void kernel_prefix_sum_inefficient(double *g_idata,double *g_odata,int l){ // Sequential Addressing technique
__shared__ double sdata[BLOCK_SIZE];
// each thread loads one element from global to shared mem
unsigned int tid = threadIdx.x;
unsigned int i = blockIdx.x*blockDim.x + threadIdx.x;
if(i<l && tid !=0){
sdata[tid] = g_idata[i-1];
}else{
sdata[tid] = 0;
}
// do reduction in shared mem
for(unsigned int s=1;s<=tid;s *=2){
__syncthreads();
sdata[tid]+=sdata[tid-s];
}
// write result for this block to global mem
g_odata[i] = sdata[tid];
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include "includes.h"
# include <bits/stdc++.h>
# include <hip/hip_runtime.h>
#define SIZE 60// Global Size
#define BLOCK_SIZE 1024
using namespace std;
//::::::::::::::::::::::::::::::::::::::::::GPU::::::::::::::::::::::::::::::::
// :::: Kernel
// :::: Calls
__global__ void kernel_prefix_sum_inefficient(double *g_idata,double *g_odata,int l){ // Sequential Addressing technique
__shared__ double sdata[BLOCK_SIZE];
// each thread loads one element from global to shared mem
unsigned int tid = threadIdx.x;
unsigned int i = blockIdx.x*blockDim.x + threadIdx.x;
if(i<l && tid !=0){
sdata[tid] = g_idata[i-1];
}else{
sdata[tid] = 0;
}
// do reduction in shared mem
for(unsigned int s=1;s<=tid;s *=2){
__syncthreads();
sdata[tid]+=sdata[tid-s];
}
// write result for this block to global mem
g_odata[i] = sdata[tid];
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z29kernel_prefix_sum_inefficientPdS_i
.globl _Z29kernel_prefix_sum_inefficientPdS_i
.p2align 8
.type _Z29kernel_prefix_sum_inefficientPdS_i,@function
_Z29kernel_prefix_sum_inefficientPdS_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_cmp_ne_u32_e64 s2, 0, v0
v_mov_b32_e32 v2, 0
v_mov_b32_e32 v3, 0
v_cmp_gt_u32_e32 vcc_lo, s3, v1
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s3, s2, vcc_lo
s_and_saveexec_b32 s2, s3
s_cbranch_execz .LBB0_2
s_load_b64 s[4:5], s[0:1], 0x0
v_dual_mov_b32 v3, 0 :: v_dual_add_nc_u32 v2, -1, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 3, v[2:3]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
global_load_b64 v[2:3], v[2:3], off
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s2
v_lshlrev_b32_e32 v4, 3, v0
s_mov_b32 s2, exec_lo
s_waitcnt vmcnt(0)
ds_store_b64 v4, v[2:3]
v_cmpx_ne_u32_e32 0, v0
s_cbranch_execz .LBB0_5
s_mov_b32 s3, 1
s_mov_b32 s4, 0
.LBB0_4:
v_subrev_nc_u32_e32 v2, s3, v0
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_lshl_b32 s3, s3, 1
v_lshlrev_b32_e32 v2, 3, v2
v_cmp_gt_u32_e32 vcc_lo, s3, v0
ds_load_b64 v[2:3], v2
ds_load_b64 v[5:6], v4
s_or_b32 s4, vcc_lo, s4
s_waitcnt lgkmcnt(0)
v_add_f64 v[2:3], v[2:3], v[5:6]
ds_store_b64 v4, v[2:3]
s_and_not1_b32 exec_lo, exec_lo, s4
s_cbranch_execnz .LBB0_4
.LBB0_5:
s_or_b32 exec_lo, exec_lo, s2
s_load_b64 s[0:1], s[0:1], 0x8
v_lshlrev_b32_e32 v0, 3, v0
v_mov_b32_e32 v2, 0
ds_load_b64 v[3:4], v0
v_lshlrev_b64 v[0:1], 3, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b64 v[0:1], v[3:4], off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z29kernel_prefix_sum_inefficientPdS_i
.amdhsa_group_segment_fixed_size 8192
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z29kernel_prefix_sum_inefficientPdS_i, .Lfunc_end0-_Z29kernel_prefix_sum_inefficientPdS_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 8192
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z29kernel_prefix_sum_inefficientPdS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z29kernel_prefix_sum_inefficientPdS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include "includes.h"
# include <bits/stdc++.h>
# include <hip/hip_runtime.h>
#define SIZE 60// Global Size
#define BLOCK_SIZE 1024
using namespace std;
//::::::::::::::::::::::::::::::::::::::::::GPU::::::::::::::::::::::::::::::::
// :::: Kernel
// :::: Calls
__global__ void kernel_prefix_sum_inefficient(double *g_idata,double *g_odata,int l){ // Sequential Addressing technique
__shared__ double sdata[BLOCK_SIZE];
// each thread loads one element from global to shared mem
unsigned int tid = threadIdx.x;
unsigned int i = blockIdx.x*blockDim.x + threadIdx.x;
if(i<l && tid !=0){
sdata[tid] = g_idata[i-1];
}else{
sdata[tid] = 0;
}
// do reduction in shared mem
for(unsigned int s=1;s<=tid;s *=2){
__syncthreads();
sdata[tid]+=sdata[tid-s];
}
// write result for this block to global mem
g_odata[i] = sdata[tid];
} | .text
.file "kernel_prefix_sum_inefficient.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z44__device_stub__kernel_prefix_sum_inefficientPdS_i # -- Begin function _Z44__device_stub__kernel_prefix_sum_inefficientPdS_i
.p2align 4, 0x90
.type _Z44__device_stub__kernel_prefix_sum_inefficientPdS_i,@function
_Z44__device_stub__kernel_prefix_sum_inefficientPdS_i: # @_Z44__device_stub__kernel_prefix_sum_inefficientPdS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z29kernel_prefix_sum_inefficientPdS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z44__device_stub__kernel_prefix_sum_inefficientPdS_i, .Lfunc_end0-_Z44__device_stub__kernel_prefix_sum_inefficientPdS_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z29kernel_prefix_sum_inefficientPdS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z29kernel_prefix_sum_inefficientPdS_i,@object # @_Z29kernel_prefix_sum_inefficientPdS_i
.section .rodata,"a",@progbits
.globl _Z29kernel_prefix_sum_inefficientPdS_i
.p2align 3, 0x0
_Z29kernel_prefix_sum_inefficientPdS_i:
.quad _Z44__device_stub__kernel_prefix_sum_inefficientPdS_i
.size _Z29kernel_prefix_sum_inefficientPdS_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z29kernel_prefix_sum_inefficientPdS_i"
.size .L__unnamed_1, 39
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z44__device_stub__kernel_prefix_sum_inefficientPdS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z29kernel_prefix_sum_inefficientPdS_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z29kernel_prefix_sum_inefficientPdS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0030*/ BSSY B0, 0x120 ; /* 0x000000e000007945 */
/* 0x000fe40003800000 */
/*0040*/ S2R R7, SR_TID.X ; /* 0x0000000000077919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R7 ; /* 0x0000000000007a24 */
/* 0x001fe200078e0207 */
/*0060*/ ISETP.NE.AND P1, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fc80003f25270 */
/*0070*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x000fc80003f06070 */
/*0080*/ ISETP.NE.AND P0, PT, R7, RZ, !P0 ; /* 0x000000ff0700720c */
/* 0x000fda0004705270 */
/*0090*/ @!P0 STS.64 [R7.X8], RZ ; /* 0x000000ff07008388 */
/* 0x0001e20000008a00 */
/*00a0*/ @!P0 CS2R R2, SRZ ; /* 0x0000000000028805 */
/* 0x000fe2000001ff00 */
/*00b0*/ @!P0 BRA 0x110 ; /* 0x0000005000008947 */
/* 0x000fea0003800000 */
/*00c0*/ IADD3 R2, R0, -0x1, RZ ; /* 0xffffffff00027810 */
/* 0x000fe20007ffe0ff */
/*00d0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x8 ; /* 0x00000008ff037424 */
/* 0x000fc800078e00ff */
/*00e0*/ IMAD.WIDE.U32 R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fcc00078e0003 */
/*00f0*/ LDG.E.64 R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1b00 */
/*0100*/ STS.64 [R7.X8], R2 ; /* 0x0000000207007388 */
/* 0x0043e40000008a00 */
/*0110*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0120*/ @!P1 BRA 0x1e0 ; /* 0x000000b000009947 */
/* 0x000fea0003800000 */
/*0130*/ HFMA2.MMA R6, -RZ, RZ, 0, 5.9604644775390625e-08 ; /* 0x00000001ff067435 */
/* 0x000fd000000001ff */
/*0140*/ WARPSYNC 0xffffffff ; /* 0xffffffff00007948 */
/* 0x000fe20003800000 */
/*0150*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0160*/ IMAD.IADD R4, R7, 0x1, -R6 ; /* 0x0000000107047824 */
/* 0x000fe200078e0a06 */
/*0170*/ SHF.L.U32 R6, R6, 0x1, RZ ; /* 0x0000000106067819 */
/* 0x000fc800000006ff */
/*0180*/ ISETP.GE.U32.AND P0, PT, R7, R6, PT ; /* 0x000000060700720c */
/* 0x000fe20003f06070 */
/*0190*/ LDS.64 R4, [R4.X8] ; /* 0x0000000004047984 */
/* 0x000fe80000008a00 */
/*01a0*/ LDS.64 R2, [R7.X8] ; /* 0x0000000007027984 */
/* 0x002e640000008a00 */
/*01b0*/ DADD R2, R2, R4 ; /* 0x0000000002027229 */
/* 0x002e4e0000000004 */
/*01c0*/ STS.64 [R7.X8], R2 ; /* 0x0000000207007388 */
/* 0x0023e20000008a00 */
/*01d0*/ @P0 BRA 0x140 ; /* 0xffffff6000000947 */
/* 0x000fea000383ffff */
/*01e0*/ IMAD.MOV.U32 R5, RZ, RZ, 0x8 ; /* 0x00000008ff057424 */
/* 0x000fc800078e00ff */
/*01f0*/ IMAD.WIDE.U32 R4, R0, R5, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x000fca00078e0005 */
/*0200*/ STG.E.64 [R4.64], R2 ; /* 0x0000000204007986 */
/* 0x000fe2000c101b04 */
/*0210*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0220*/ BRA 0x220; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z29kernel_prefix_sum_inefficientPdS_i
.globl _Z29kernel_prefix_sum_inefficientPdS_i
.p2align 8
.type _Z29kernel_prefix_sum_inefficientPdS_i,@function
_Z29kernel_prefix_sum_inefficientPdS_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_cmp_ne_u32_e64 s2, 0, v0
v_mov_b32_e32 v2, 0
v_mov_b32_e32 v3, 0
v_cmp_gt_u32_e32 vcc_lo, s3, v1
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s3, s2, vcc_lo
s_and_saveexec_b32 s2, s3
s_cbranch_execz .LBB0_2
s_load_b64 s[4:5], s[0:1], 0x0
v_dual_mov_b32 v3, 0 :: v_dual_add_nc_u32 v2, -1, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 3, v[2:3]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
global_load_b64 v[2:3], v[2:3], off
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s2
v_lshlrev_b32_e32 v4, 3, v0
s_mov_b32 s2, exec_lo
s_waitcnt vmcnt(0)
ds_store_b64 v4, v[2:3]
v_cmpx_ne_u32_e32 0, v0
s_cbranch_execz .LBB0_5
s_mov_b32 s3, 1
s_mov_b32 s4, 0
.LBB0_4:
v_subrev_nc_u32_e32 v2, s3, v0
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_lshl_b32 s3, s3, 1
v_lshlrev_b32_e32 v2, 3, v2
v_cmp_gt_u32_e32 vcc_lo, s3, v0
ds_load_b64 v[2:3], v2
ds_load_b64 v[5:6], v4
s_or_b32 s4, vcc_lo, s4
s_waitcnt lgkmcnt(0)
v_add_f64 v[2:3], v[2:3], v[5:6]
ds_store_b64 v4, v[2:3]
s_and_not1_b32 exec_lo, exec_lo, s4
s_cbranch_execnz .LBB0_4
.LBB0_5:
s_or_b32 exec_lo, exec_lo, s2
s_load_b64 s[0:1], s[0:1], 0x8
v_lshlrev_b32_e32 v0, 3, v0
v_mov_b32_e32 v2, 0
ds_load_b64 v[3:4], v0
v_lshlrev_b64 v[0:1], 3, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b64 v[0:1], v[3:4], off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z29kernel_prefix_sum_inefficientPdS_i
.amdhsa_group_segment_fixed_size 8192
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z29kernel_prefix_sum_inefficientPdS_i, .Lfunc_end0-_Z29kernel_prefix_sum_inefficientPdS_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 8192
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z29kernel_prefix_sum_inefficientPdS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z29kernel_prefix_sum_inefficientPdS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000a084f_00000000-6_kernel_prefix_sum_inefficient.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB10861:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE10861:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z52__device_stub__Z29kernel_prefix_sum_inefficientPdS_iPdS_i
.type _Z52__device_stub__Z29kernel_prefix_sum_inefficientPdS_iPdS_i, @function
_Z52__device_stub__Z29kernel_prefix_sum_inefficientPdS_iPdS_i:
.LFB10883:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z29kernel_prefix_sum_inefficientPdS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE10883:
.size _Z52__device_stub__Z29kernel_prefix_sum_inefficientPdS_iPdS_i, .-_Z52__device_stub__Z29kernel_prefix_sum_inefficientPdS_iPdS_i
.globl _Z29kernel_prefix_sum_inefficientPdS_i
.type _Z29kernel_prefix_sum_inefficientPdS_i, @function
_Z29kernel_prefix_sum_inefficientPdS_i:
.LFB10884:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z52__device_stub__Z29kernel_prefix_sum_inefficientPdS_iPdS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE10884:
.size _Z29kernel_prefix_sum_inefficientPdS_i, .-_Z29kernel_prefix_sum_inefficientPdS_i
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z29kernel_prefix_sum_inefficientPdS_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB10886:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z29kernel_prefix_sum_inefficientPdS_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE10886:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "kernel_prefix_sum_inefficient.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z44__device_stub__kernel_prefix_sum_inefficientPdS_i # -- Begin function _Z44__device_stub__kernel_prefix_sum_inefficientPdS_i
.p2align 4, 0x90
.type _Z44__device_stub__kernel_prefix_sum_inefficientPdS_i,@function
_Z44__device_stub__kernel_prefix_sum_inefficientPdS_i: # @_Z44__device_stub__kernel_prefix_sum_inefficientPdS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z29kernel_prefix_sum_inefficientPdS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z44__device_stub__kernel_prefix_sum_inefficientPdS_i, .Lfunc_end0-_Z44__device_stub__kernel_prefix_sum_inefficientPdS_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z29kernel_prefix_sum_inefficientPdS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z29kernel_prefix_sum_inefficientPdS_i,@object # @_Z29kernel_prefix_sum_inefficientPdS_i
.section .rodata,"a",@progbits
.globl _Z29kernel_prefix_sum_inefficientPdS_i
.p2align 3, 0x0
_Z29kernel_prefix_sum_inefficientPdS_i:
.quad _Z44__device_stub__kernel_prefix_sum_inefficientPdS_i
.size _Z29kernel_prefix_sum_inefficientPdS_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z29kernel_prefix_sum_inefficientPdS_i"
.size .L__unnamed_1, 39
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z44__device_stub__kernel_prefix_sum_inefficientPdS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z29kernel_prefix_sum_inefficientPdS_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /*!
* \brief Record the basic usage of Transformations in Thrust.
* https://docs.nvidia.com/cuda/thrust/
* \Functor plus: +;
* minus: -;
* multiplies: *;
* equal_to: ==;
* less: <;
*/
#include <iostream>
#include "time.h"
// Thrust related
#include <thrust/device_vector.h>
#include <thrust/transform.h>
#include <thrust/transform_reduce.h>
#include <thrust/functional.h>
#include <thrust/copy.h>
#include <thrust/fill.h>
#include <thrust/sequence.h>
////////// Test Saxpy ////////////
struct saxpy_functor {
const float alpha_;
saxpy_functor(float a) : alpha_(a) {}
__host__ __device__
float operator()(const float& x, const float& y) const {
return alpha_ * x + y;
}
};
void saxpy_fast(float A, thrust::device_vector<float>& X, thrust::device_vector<float>& Y) {
// Y <- A * X + Y
thrust::transform(X.begin(), X.end(), Y.begin(), Y.begin(), saxpy_functor(A));
}
void saxpy_slow(float A, thrust::device_vector<float>& X, thrust::device_vector<float>& Y) {
thrust::device_vector<float> temp(X.size());
// temp <- A
thrust::fill(temp.begin(), temp.end(), A);
// temp <- A * X
thrust::transform(X.begin(), X.end(), temp.begin(), temp.begin(), thrust::multiplies<float>());
// Y <- A * X + Y
thrust::transform(temp.begin(), temp.end(), Y.begin(), Y.begin(), thrust::plus<float>());
}
void TestSaxpy() {
// allocate three device_vectors with 10 elements
thrust::device_vector<float> d_x(10);
thrust::device_vector<float> d_y(10);
// initialize X to 0,1,2,3, ....
thrust::sequence(d_x.begin(), d_x.end(), 0);
thrust::fill(d_y.begin(), d_y.end(), 1);
float alpha = 2.0;
time_t t = clock();
saxpy_slow(alpha, d_x, d_y);
printf("saxpy_slow, msec_total = %lld\n", clock() - t);
for (int i = 0; i < d_y.size(); i++)
std::cout << "y[" << i << "] = " << d_y[i] << std::endl;
thrust::fill(d_y.begin(), d_y.end(), 1);
t = clock();
saxpy_fast(alpha, d_x, d_y);
printf("saxpy_fast, msec_total = %lld\n", clock() - t);
for (int i = 0; i < d_y.size(); i++)
std::cout << "y2[" << i << "] = " << d_y[i] << std::endl;
}
////////// Test Reduce ////////////
// square<T> computes the square of a number f(x) -> x*x
template <typename T>
struct square {
__host__ __device__
T operator()(const T& x) const {
return x * x;
}
};
void TestReduce() {
float x[4] = { 1.0, 2.0, 3.0, 4.0 };
// transfer to device
thrust::device_vector<float> d_x(x, x + 4);
// setup arguments
float init = 0;
float sum = thrust::transform_reduce(d_x.begin(), d_x.end(), square<float>(), init, thrust::plus<float>());
std::cout << "sum: " << sum << std::endl;
}
////////// Test Scan ////////////
void TestScan() {
const int LEN = 12;
int data[LEN] = { 1, 0, 2, 2, 1, 3, 7, 8, 12, 36, 15, 6 };
thrust::inclusive_scan(data, data + LEN, data);
std::cout << "Scan Result: " << std::endl;
for (int i = 0; i < LEN; i++) {
std::cout << data[i] << ", ";
}
std::cout << std::endl;
}
int main() {
std::cout << "Start TestSaxpy()." << std::endl;
TestSaxpy();
std::cout << "Start TestReduce()." << std::endl;
TestReduce();
std::cout << "Start TestScan()." << std::endl;
TestScan();
system("pause");
return 0;
} | /*!
* \brief Record the basic usage of Transformations in Thrust.
* https://docs.nvidia.com/cuda/thrust/
* \Functor plus: +;
* minus: -;
* multiplies: *;
* equal_to: ==;
* less: <;
*/
#include <hip/hip_runtime.h>
#include <iostream>
#include "time.h"
// Thrust related
#include <thrust/device_vector.h>
#include <thrust/transform.h>
#include <thrust/transform_reduce.h>
#include <thrust/functional.h>
#include <thrust/copy.h>
#include <thrust/fill.h>
#include <thrust/sequence.h>
////////// Test Saxpy ////////////
struct saxpy_functor {
const float alpha_;
saxpy_functor(float a) : alpha_(a) {}
__host__ __device__
float operator()(const float& x, const float& y) const {
return alpha_ * x + y;
}
};
void saxpy_fast(float A, thrust::device_vector<float>& X, thrust::device_vector<float>& Y) {
// Y <- A * X + Y
thrust::transform(X.begin(), X.end(), Y.begin(), Y.begin(), saxpy_functor(A));
}
void saxpy_slow(float A, thrust::device_vector<float>& X, thrust::device_vector<float>& Y) {
thrust::device_vector<float> temp(X.size());
// temp <- A
thrust::fill(temp.begin(), temp.end(), A);
// temp <- A * X
thrust::transform(X.begin(), X.end(), temp.begin(), temp.begin(), thrust::multiplies<float>());
// Y <- A * X + Y
thrust::transform(temp.begin(), temp.end(), Y.begin(), Y.begin(), thrust::plus<float>());
}
void TestSaxpy() {
// allocate three device_vectors with 10 elements
thrust::device_vector<float> d_x(10);
thrust::device_vector<float> d_y(10);
// initialize X to 0,1,2,3, ....
thrust::sequence(d_x.begin(), d_x.end(), 0);
thrust::fill(d_y.begin(), d_y.end(), 1);
float alpha = 2.0;
time_t t = clock();
saxpy_slow(alpha, d_x, d_y);
printf("saxpy_slow, msec_total = %lld\n", clock() - t);
for (int i = 0; i < d_y.size(); i++)
std::cout << "y[" << i << "] = " << d_y[i] << std::endl;
thrust::fill(d_y.begin(), d_y.end(), 1);
t = clock();
saxpy_fast(alpha, d_x, d_y);
printf("saxpy_fast, msec_total = %lld\n", clock() - t);
for (int i = 0; i < d_y.size(); i++)
std::cout << "y2[" << i << "] = " << d_y[i] << std::endl;
}
////////// Test Reduce ////////////
// square<T> computes the square of a number f(x) -> x*x
template <typename T>
struct square {
__host__ __device__
T operator()(const T& x) const {
return x * x;
}
};
void TestReduce() {
float x[4] = { 1.0, 2.0, 3.0, 4.0 };
// transfer to device
thrust::device_vector<float> d_x(x, x + 4);
// setup arguments
float init = 0;
float sum = thrust::transform_reduce(d_x.begin(), d_x.end(), square<float>(), init, thrust::plus<float>());
std::cout << "sum: " << sum << std::endl;
}
////////// Test Scan ////////////
void TestScan() {
const int LEN = 12;
int data[LEN] = { 1, 0, 2, 2, 1, 3, 7, 8, 12, 36, 15, 6 };
thrust::inclusive_scan(data, data + LEN, data);
std::cout << "Scan Result: " << std::endl;
for (int i = 0; i < LEN; i++) {
std::cout << data[i] << ", ";
}
std::cout << std::endl;
}
int main() {
std::cout << "Start TestSaxpy()." << std::endl;
TestSaxpy();
std::cout << "Start TestReduce()." << std::endl;
TestReduce();
std::cout << "Start TestScan()." << std::endl;
TestScan();
system("pause");
return 0;
} |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | // centroid: [ 92.6200991 -157.6624484 -666.61104378]
// scale: [1.38349843 0.99729681 2.00067234
inline __host__ __device__ float3 operator-(float3 a, float3 b)
{
return make_float3(a.x - b.x, a.y - b.y, a.z - b.z);
}
inline __host__ __device__ float3 cross(float3 a, float3 b)
{
return make_float3(a.y*b.z - a.z*b.y, a.z*b.x - a.x*b.z, a.x*b.y - a.y*b.x);
}
inline __host__ __device__ float dot(float3 a, float3 b)
{
return a.x * b.x + a.y * b.y + a.z * b.z;
}
inline __host__ __device__ float dot2(float3 a)
{
return dot(a,a);
}
inline __device__ __host__ float clamp(float f, float a, float b)
{
return fmaxf(a, fminf(f, b));
}
inline __host__ __device__ float3 operator*(float3 a, float b)
{
return make_float3(a.x * b, a.y * b, a.z * b);
}
inline __host__ __device__ float sign(float x)
{
float t = x > 0.0;
return t - (x < 0.0);
}
// inigo quilez: https://www.iquilezles.org/www/articles/triangledistance/triangledistance.htm
__device__
float distance( float3 v1, float3 v2, float3 v3, float3 p )
{
// prepare data
float3 v21 = v2 - v1; float3 p1 = p - v1;
float3 v32 = v3 - v2; float3 p2 = p - v2;
float3 v13 = v1 - v3; float3 p3 = p - v3;
float3 nor = cross( v21, v13 );
float dist = sqrt( // inside/outside test
( sign(dot(cross(v21,nor),p1))
+ sign(dot(cross(v32,nor),p2))
+ sign(dot(cross(v13,nor),p3))<2.0)
?
// 3 edges
min( min(
dot2(v21*clamp(dot(v21,p1)/dot2(v21),0.0,1.0)-p1),
dot2(v32*clamp(dot(v32,p2)/dot2(v32),0.0,1.0)-p2) ),
dot2(v13*clamp(dot(v13,p3)/dot2(v13),0.0,1.0)-p3) )
:
// 1 face
dot(nor,p1)*dot(nor,p1)/dot2(nor) );
// which side of the triangle?
return sign(dot(nor, p1)) * dist;
}
__global__ void mesh2sdf(float *sdf, int w, int h, int d, float *V, int *F, int nFaces)
{
const uint y = (blockIdx.y * blockDim.y) + threadIdx.y;
const uint z = (blockIdx.z * blockDim.z) + threadIdx.z;
// TODO is this right? (most definitely not)
if(y >= h || z >= d) {
return;
}
// todo pass in scale dont hardcode
const float pt_y = (y - h / 2.0) * 0.99729681 * 64.0 / (float) h;
const float pt_z = (z - d / 2.0) * 2.00067234 * 64.0 / (float) d;
for(uint x=0; x<w; x++) {
const int idx = x + w * (y + d * z);
float currDist = sdf[idx];
const float pt_x = (x - w / 2.0) * 1.38349843 * 64.0 / (float) w;
float3 pt = make_float3(pt_x, pt_y, pt_z);
for(int f=0; f<nFaces; f++) {
float3 v1 = make_float3(V[3*F[3*f+0]+0], V[3*F[3*f+0]+1], V[3*F[3*f+0]+2]);
float3 v2 = make_float3(V[3*F[3*f+1]+0], V[3*F[3*f+1]+1], V[3*F[3*f+1]+2]);
float3 v3 = make_float3(V[3*F[3*f+2]+0], V[3*F[3*f+2]+1], V[3*F[3*f+2]+2]);
const float dist = distance(v1, v2, v3, pt);
if(abs(dist) < abs(currDist)) {
currDist = dist;
}
}
sdf[idx] = currDist;
}
} | .file "tmpxft_0009031b_00000000-6_mesh2sdf.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2037:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2037:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z8distance6float3S_S_S_
.type _Z8distance6float3S_S_S_, @function
_Z8distance6float3S_S_S_:
.LFB2034:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %xmm0, 48(%rsp)
movss %xmm1, 56(%rsp)
movq %xmm2, 32(%rsp)
movss %xmm3, 40(%rsp)
movq %xmm4, 16(%rsp)
movss %xmm5, 24(%rsp)
movq %xmm6, (%rsp)
movss %xmm7, 8(%rsp)
movl $1, 76(%rsp)
movl 76(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2034:
.size _Z8distance6float3S_S_S_, .-_Z8distance6float3S_S_S_
.globl _Z35__device_stub__Z8mesh2sdfPfiiiS_PiiPfiiiS_Pii
.type _Z35__device_stub__Z8mesh2sdfPfiiiS_PiiPfiiiS_Pii, @function
_Z35__device_stub__Z8mesh2sdfPfiiiS_PiiPfiiiS_Pii:
.LFB2059:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movl %esi, 36(%rsp)
movl %edx, 32(%rsp)
movl %ecx, 28(%rsp)
movq %r8, 16(%rsp)
movq %r9, 8(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 36(%rsp), %rax
movq %rax, 120(%rsp)
leaq 32(%rsp), %rax
movq %rax, 128(%rsp)
leaq 28(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
leaq 192(%rsp), %rax
movq %rax, 160(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L9
.L5:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L10
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z8mesh2sdfPfiiiS_Pii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L5
.L10:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size _Z35__device_stub__Z8mesh2sdfPfiiiS_PiiPfiiiS_Pii, .-_Z35__device_stub__Z8mesh2sdfPfiiiS_PiiPfiiiS_Pii
.globl _Z8mesh2sdfPfiiiS_Pii
.type _Z8mesh2sdfPfiiiS_Pii, @function
_Z8mesh2sdfPfiiiS_Pii:
.LFB2060:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
call _Z35__device_stub__Z8mesh2sdfPfiiiS_PiiPfiiiS_Pii
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _Z8mesh2sdfPfiiiS_Pii, .-_Z8mesh2sdfPfiiiS_Pii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z8mesh2sdfPfiiiS_Pii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z8mesh2sdfPfiiiS_Pii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | // centroid: [ 92.6200991 -157.6624484 -666.61104378]
// scale: [1.38349843 0.99729681 2.00067234
inline __host__ __device__ float3 operator-(float3 a, float3 b)
{
return make_float3(a.x - b.x, a.y - b.y, a.z - b.z);
}
inline __host__ __device__ float3 cross(float3 a, float3 b)
{
return make_float3(a.y*b.z - a.z*b.y, a.z*b.x - a.x*b.z, a.x*b.y - a.y*b.x);
}
inline __host__ __device__ float dot(float3 a, float3 b)
{
return a.x * b.x + a.y * b.y + a.z * b.z;
}
inline __host__ __device__ float dot2(float3 a)
{
return dot(a,a);
}
inline __device__ __host__ float clamp(float f, float a, float b)
{
return fmaxf(a, fminf(f, b));
}
inline __host__ __device__ float3 operator*(float3 a, float b)
{
return make_float3(a.x * b, a.y * b, a.z * b);
}
inline __host__ __device__ float sign(float x)
{
float t = x > 0.0;
return t - (x < 0.0);
}
// inigo quilez: https://www.iquilezles.org/www/articles/triangledistance/triangledistance.htm
__device__
float distance( float3 v1, float3 v2, float3 v3, float3 p )
{
// prepare data
float3 v21 = v2 - v1; float3 p1 = p - v1;
float3 v32 = v3 - v2; float3 p2 = p - v2;
float3 v13 = v1 - v3; float3 p3 = p - v3;
float3 nor = cross( v21, v13 );
float dist = sqrt( // inside/outside test
( sign(dot(cross(v21,nor),p1))
+ sign(dot(cross(v32,nor),p2))
+ sign(dot(cross(v13,nor),p3))<2.0)
?
// 3 edges
min( min(
dot2(v21*clamp(dot(v21,p1)/dot2(v21),0.0,1.0)-p1),
dot2(v32*clamp(dot(v32,p2)/dot2(v32),0.0,1.0)-p2) ),
dot2(v13*clamp(dot(v13,p3)/dot2(v13),0.0,1.0)-p3) )
:
// 1 face
dot(nor,p1)*dot(nor,p1)/dot2(nor) );
// which side of the triangle?
return sign(dot(nor, p1)) * dist;
}
__global__ void mesh2sdf(float *sdf, int w, int h, int d, float *V, int *F, int nFaces)
{
const uint y = (blockIdx.y * blockDim.y) + threadIdx.y;
const uint z = (blockIdx.z * blockDim.z) + threadIdx.z;
// TODO is this right? (most definitely not)
if(y >= h || z >= d) {
return;
}
// todo pass in scale dont hardcode
const float pt_y = (y - h / 2.0) * 0.99729681 * 64.0 / (float) h;
const float pt_z = (z - d / 2.0) * 2.00067234 * 64.0 / (float) d;
for(uint x=0; x<w; x++) {
const int idx = x + w * (y + d * z);
float currDist = sdf[idx];
const float pt_x = (x - w / 2.0) * 1.38349843 * 64.0 / (float) w;
float3 pt = make_float3(pt_x, pt_y, pt_z);
for(int f=0; f<nFaces; f++) {
float3 v1 = make_float3(V[3*F[3*f+0]+0], V[3*F[3*f+0]+1], V[3*F[3*f+0]+2]);
float3 v2 = make_float3(V[3*F[3*f+1]+0], V[3*F[3*f+1]+1], V[3*F[3*f+1]+2]);
float3 v3 = make_float3(V[3*F[3*f+2]+0], V[3*F[3*f+2]+1], V[3*F[3*f+2]+2]);
const float dist = distance(v1, v2, v3, pt);
if(abs(dist) < abs(currDist)) {
currDist = dist;
}
}
sdf[idx] = currDist;
}
} | #include <hip/hip_runtime.h>
// centroid: [ 92.6200991 -157.6624484 -666.61104378]
// scale: [1.38349843 0.99729681 2.00067234
inline __host__ __device__ float3 operator-(float3 a, float3 b)
{
return make_float3(a.x - b.x, a.y - b.y, a.z - b.z);
}
inline __host__ __device__ float3 cross(float3 a, float3 b)
{
return make_float3(a.y*b.z - a.z*b.y, a.z*b.x - a.x*b.z, a.x*b.y - a.y*b.x);
}
inline __host__ __device__ float dot(float3 a, float3 b)
{
return a.x * b.x + a.y * b.y + a.z * b.z;
}
inline __host__ __device__ float dot2(float3 a)
{
return dot(a,a);
}
inline __device__ __host__ float clamp(float f, float a, float b)
{
return fmaxf(a, fminf(f, b));
}
inline __host__ __device__ float3 operator*(float3 a, float b)
{
return make_float3(a.x * b, a.y * b, a.z * b);
}
inline __host__ __device__ float sign(float x)
{
float t = x > 0.0;
return t - (x < 0.0);
}
// inigo quilez: https://www.iquilezles.org/www/articles/triangledistance/triangledistance.htm
__device__
float distance( float3 v1, float3 v2, float3 v3, float3 p )
{
// prepare data
float3 v21 = v2 - v1; float3 p1 = p - v1;
float3 v32 = v3 - v2; float3 p2 = p - v2;
float3 v13 = v1 - v3; float3 p3 = p - v3;
float3 nor = cross( v21, v13 );
float dist = sqrt( // inside/outside test
( sign(dot(cross(v21,nor),p1))
+ sign(dot(cross(v32,nor),p2))
+ sign(dot(cross(v13,nor),p3))<2.0)
?
// 3 edges
min( min(
dot2(v21*clamp(dot(v21,p1)/dot2(v21),0.0,1.0)-p1),
dot2(v32*clamp(dot(v32,p2)/dot2(v32),0.0,1.0)-p2) ),
dot2(v13*clamp(dot(v13,p3)/dot2(v13),0.0,1.0)-p3) )
:
// 1 face
dot(nor,p1)*dot(nor,p1)/dot2(nor) );
// which side of the triangle?
return sign(dot(nor, p1)) * dist;
}
__global__ void mesh2sdf(float *sdf, int w, int h, int d, float *V, int *F, int nFaces)
{
const uint y = (blockIdx.y * blockDim.y) + threadIdx.y;
const uint z = (blockIdx.z * blockDim.z) + threadIdx.z;
// TODO is this right? (most definitely not)
if(y >= h || z >= d) {
return;
}
// todo pass in scale dont hardcode
const float pt_y = (y - h / 2.0) * 0.99729681 * 64.0 / (float) h;
const float pt_z = (z - d / 2.0) * 2.00067234 * 64.0 / (float) d;
for(uint x=0; x<w; x++) {
const int idx = x + w * (y + d * z);
float currDist = sdf[idx];
const float pt_x = (x - w / 2.0) * 1.38349843 * 64.0 / (float) w;
float3 pt = make_float3(pt_x, pt_y, pt_z);
for(int f=0; f<nFaces; f++) {
float3 v1 = make_float3(V[3*F[3*f+0]+0], V[3*F[3*f+0]+1], V[3*F[3*f+0]+2]);
float3 v2 = make_float3(V[3*F[3*f+1]+0], V[3*F[3*f+1]+1], V[3*F[3*f+1]+2]);
float3 v3 = make_float3(V[3*F[3*f+2]+0], V[3*F[3*f+2]+1], V[3*F[3*f+2]+2]);
const float dist = distance(v1, v2, v3, pt);
if(abs(dist) < abs(currDist)) {
currDist = dist;
}
}
sdf[idx] = currDist;
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
// centroid: [ 92.6200991 -157.6624484 -666.61104378]
// scale: [1.38349843 0.99729681 2.00067234
inline __host__ __device__ float3 operator-(float3 a, float3 b)
{
return make_float3(a.x - b.x, a.y - b.y, a.z - b.z);
}
inline __host__ __device__ float3 cross(float3 a, float3 b)
{
return make_float3(a.y*b.z - a.z*b.y, a.z*b.x - a.x*b.z, a.x*b.y - a.y*b.x);
}
inline __host__ __device__ float dot(float3 a, float3 b)
{
return a.x * b.x + a.y * b.y + a.z * b.z;
}
inline __host__ __device__ float dot2(float3 a)
{
return dot(a,a);
}
inline __device__ __host__ float clamp(float f, float a, float b)
{
return fmaxf(a, fminf(f, b));
}
inline __host__ __device__ float3 operator*(float3 a, float b)
{
return make_float3(a.x * b, a.y * b, a.z * b);
}
inline __host__ __device__ float sign(float x)
{
float t = x > 0.0;
return t - (x < 0.0);
}
// inigo quilez: https://www.iquilezles.org/www/articles/triangledistance/triangledistance.htm
__device__
float distance( float3 v1, float3 v2, float3 v3, float3 p )
{
// prepare data
float3 v21 = v2 - v1; float3 p1 = p - v1;
float3 v32 = v3 - v2; float3 p2 = p - v2;
float3 v13 = v1 - v3; float3 p3 = p - v3;
float3 nor = cross( v21, v13 );
float dist = sqrt( // inside/outside test
( sign(dot(cross(v21,nor),p1))
+ sign(dot(cross(v32,nor),p2))
+ sign(dot(cross(v13,nor),p3))<2.0)
?
// 3 edges
min( min(
dot2(v21*clamp(dot(v21,p1)/dot2(v21),0.0,1.0)-p1),
dot2(v32*clamp(dot(v32,p2)/dot2(v32),0.0,1.0)-p2) ),
dot2(v13*clamp(dot(v13,p3)/dot2(v13),0.0,1.0)-p3) )
:
// 1 face
dot(nor,p1)*dot(nor,p1)/dot2(nor) );
// which side of the triangle?
return sign(dot(nor, p1)) * dist;
}
__global__ void mesh2sdf(float *sdf, int w, int h, int d, float *V, int *F, int nFaces)
{
const uint y = (blockIdx.y * blockDim.y) + threadIdx.y;
const uint z = (blockIdx.z * blockDim.z) + threadIdx.z;
// TODO is this right? (most definitely not)
if(y >= h || z >= d) {
return;
}
// todo pass in scale dont hardcode
const float pt_y = (y - h / 2.0) * 0.99729681 * 64.0 / (float) h;
const float pt_z = (z - d / 2.0) * 2.00067234 * 64.0 / (float) d;
for(uint x=0; x<w; x++) {
const int idx = x + w * (y + d * z);
float currDist = sdf[idx];
const float pt_x = (x - w / 2.0) * 1.38349843 * 64.0 / (float) w;
float3 pt = make_float3(pt_x, pt_y, pt_z);
for(int f=0; f<nFaces; f++) {
float3 v1 = make_float3(V[3*F[3*f+0]+0], V[3*F[3*f+0]+1], V[3*F[3*f+0]+2]);
float3 v2 = make_float3(V[3*F[3*f+1]+0], V[3*F[3*f+1]+1], V[3*F[3*f+1]+2]);
float3 v3 = make_float3(V[3*F[3*f+2]+0], V[3*F[3*f+2]+1], V[3*F[3*f+2]+2]);
const float dist = distance(v1, v2, v3, pt);
if(abs(dist) < abs(currDist)) {
currDist = dist;
}
}
sdf[idx] = currDist;
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z8mesh2sdfPfiiiS_Pii
.globl _Z8mesh2sdfPfiiiS_Pii
.p2align 8
.type _Z8mesh2sdfPfiiiS_Pii,@function
_Z8mesh2sdfPfiiiS_Pii:
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x3c
s_load_b64 s[8:9], s[0:1], 0xc
v_bfe_u32 v1, v0, 10, 10
v_bfe_u32 v0, v0, 20, 10
s_waitcnt lgkmcnt(0)
s_lshr_b32 s2, s2, 16
s_and_b32 s3, s3, 0xffff
v_mad_u64_u32 v[4:5], null, s14, s2, v[1:2]
v_mad_u64_u32 v[5:6], null, s15, s3, v[0:1]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_gt_u32_e32 vcc_lo, s8, v4
v_cmp_gt_u32_e64 s2, s9, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, vcc_lo, s2
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_11
s_load_b32 s12, s[0:1], 0x8
s_mov_b32 s13, 0
s_waitcnt lgkmcnt(0)
s_cmp_eq_u32 s12, 0
s_cbranch_scc1 .LBB0_11
v_cvt_f64_u32_e32 v[0:1], v4
v_cvt_f64_i32_e32 v[2:3], s8
v_cvt_f64_u32_e32 v[6:7], v5
v_cvt_f64_i32_e32 v[8:9], s9
s_mov_b32 s3, 0x3fefe9da
s_mov_b32 s2, 0xffeb5d31
s_mov_b32 s5, 0x40000160
s_mov_b32 s4, 0x7ff27e8d
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f64 v[0:1], v[2:3], -0.5, v[0:1]
v_fma_f64 v[2:3], v[8:9], -0.5, v[6:7]
v_cvt_f32_i32_e32 v6, s8
v_cvt_f32_i32_e32 v8, s9
s_mov_b32 s8, 0x3feead72
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cvt_f64_f32_e32 v[6:7], v6
v_cvt_f64_f32_e32 v[8:9], v8
v_mul_f64 v[0:1], v[0:1], s[2:3]
v_mul_f64 v[2:3], v[2:3], s[4:5]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ldexp_f64 v[0:1], v[0:1], 6
v_ldexp_f64 v[2:3], v[2:3], 6
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_div_scale_f64 v[10:11], null, v[6:7], v[6:7], v[0:1]
v_div_scale_f64 v[12:13], null, v[8:9], v[8:9], v[2:3]
v_div_scale_f64 v[22:23], vcc_lo, v[0:1], v[6:7], v[0:1]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_rcp_f64_e32 v[14:15], v[10:11]
v_rcp_f64_e32 v[16:17], v[12:13]
s_waitcnt_depctr 0xfff
v_fma_f64 v[18:19], -v[10:11], v[14:15], 1.0
v_fma_f64 v[20:21], -v[12:13], v[16:17], 1.0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f64 v[14:15], v[14:15], v[18:19], v[14:15]
v_fma_f64 v[16:17], v[16:17], v[20:21], v[16:17]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f64 v[18:19], -v[10:11], v[14:15], 1.0
v_fma_f64 v[20:21], -v[12:13], v[16:17], 1.0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_fma_f64 v[14:15], v[14:15], v[18:19], v[14:15]
v_div_scale_f64 v[18:19], s2, v[2:3], v[8:9], v[2:3]
v_fma_f64 v[16:17], v[16:17], v[20:21], v[16:17]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_f64 v[20:21], v[22:23], v[14:15]
v_mul_f64 v[24:25], v[18:19], v[16:17]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f64 v[10:11], -v[10:11], v[20:21], v[22:23]
v_fma_f64 v[12:13], -v[12:13], v[24:25], v[18:19]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_div_fmas_f64 v[10:11], v[10:11], v[14:15], v[20:21]
s_mov_b32 vcc_lo, s2
v_cvt_f64_i32_e32 v[14:15], s12
v_div_fmas_f64 v[12:13], v[12:13], v[16:17], v[24:25]
s_clause 0x2
s_load_b32 s14, s[0:1], 0x28
s_load_b128 s[4:7], s[0:1], 0x18
s_load_b64 s[2:3], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_cmp_gt_i32 s14, 0
s_cselect_b32 s15, -1, 0
s_add_u32 s6, s6, 4
s_addc_u32 s7, s7, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_div_fixup_f64 v[6:7], v[10:11], v[6:7], v[0:1]
v_cvt_f32_i32_e32 v10, s12
v_mul_f64 v[0:1], v[14:15], 0.5
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
v_div_fixup_f64 v[2:3], v[12:13], v[8:9], v[2:3]
v_mov_b32_e32 v11, 0
v_cvt_f32_f64_e32 v8, v[6:7]
v_mad_u64_u32 v[6:7], null, v5, s9, v[4:5]
v_cvt_f32_f64_e32 v9, v[2:3]
v_cvt_f64_f32_e32 v[2:3], v10
v_mov_b32_e32 v4, 0
v_mov_b32_e32 v5, 0
s_mov_b32 s9, 0x3ff622cf
v_mul_lo_u32 v10, v6, s12
s_branch .LBB0_4
.LBB0_3:
v_add_f64 v[4:5], v[4:5], 1.0
s_add_i32 s13, s13, 1
s_waitcnt vmcnt(0)
global_store_b32 v[6:7], v12, off
s_cmp_eq_u32 s13, s12
s_cbranch_scc1 .LBB0_11
.LBB0_4:
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v6, s13, v10
v_ashrrev_i32_e32 v7, 31, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[6:7], 2, v[6:7]
v_add_co_u32 v6, vcc_lo, s2, v6
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v7, vcc_lo, s3, v7, vcc_lo
s_and_not1_b32 vcc_lo, exec_lo, s15
global_load_b32 v12, v[6:7], off
s_cbranch_vccnz .LBB0_3
v_add_f64 v[13:14], v[4:5], -v[0:1]
s_mov_b64 s[10:11], s[6:7]
s_mov_b32 s16, s14
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[13:14], v[13:14], s[8:9]
v_ldexp_f64 v[13:14], v[13:14], 6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_scale_f64 v[15:16], null, v[2:3], v[2:3], v[13:14]
v_rcp_f64_e32 v[17:18], v[15:16]
s_waitcnt_depctr 0xfff
v_fma_f64 v[19:20], -v[15:16], v[17:18], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[17:18], v[17:18], v[19:20], v[17:18]
v_fma_f64 v[19:20], -v[15:16], v[17:18], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fma_f64 v[17:18], v[17:18], v[19:20], v[17:18]
v_div_scale_f64 v[19:20], vcc_lo, v[13:14], v[2:3], v[13:14]
v_mul_f64 v[21:22], v[19:20], v[17:18]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[15:16], -v[15:16], v[21:22], v[19:20]
v_div_fmas_f64 v[15:16], v[15:16], v[17:18], v[21:22]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fixup_f64 v[13:14], v[15:16], v[2:3], v[13:14]
v_cvt_f32_f64_e32 v13, v[13:14]
s_branch .LBB0_7
.LBB0_6:
s_or_b32 exec_lo, exec_lo, s17
s_delay_alu instid0(VALU_DEP_1)
v_mul_f32_e32 v18, 0x4f800000, v36
v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v36
v_fmac_f32_e32 v28, v15, v17
s_add_i32 s16, s16, -1
s_add_u32 s10, s10, 12
s_addc_u32 s11, s11, 0
v_cndmask_b32_e32 v18, v36, v18, vcc_lo
v_fmac_f32_e32 v28, v14, v16
s_cmp_eq_u32 s16, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_sqrt_f32_e32 v19, v18
s_waitcnt_depctr 0xfff
v_add_nc_u32_e32 v21, 1, v19
v_add_nc_u32_e32 v20, -1, v19
v_fma_f32 v23, -v21, v19, v18
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v22, -v20, v19, v18
v_cmp_ge_f32_e64 s0, 0, v22
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
v_cndmask_b32_e64 v19, v19, v20, s0
v_cmp_lt_f32_e64 s0, 0, v23
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cndmask_b32_e64 v15, v19, v21, s0
v_cmp_lt_f32_e64 s0, 0, v28
v_mul_f32_e32 v14, 0x37800000, v15
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_cndmask_b32_e64 v16, 0, 1.0, s0
v_cmp_gt_f32_e64 s0, 0, v28
v_cndmask_b32_e32 v14, v15, v14, vcc_lo
v_cmp_class_f32_e64 vcc_lo, v18, 0x260
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e64 v17, 0, 1.0, s0
v_dual_cndmask_b32 v14, v14, v18 :: v_dual_sub_f32 v15, v16, v17
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v14, v15, v14
v_cmp_lt_f32_e64 vcc_lo, |v14|, |v12|
v_cndmask_b32_e32 v12, v12, v14, vcc_lo
s_cbranch_scc1 .LBB0_3
.LBB0_7:
s_add_u32 s0, s10, -4
s_addc_u32 s1, s11, -1
s_clause 0x1
s_load_b32 s17, s[0:1], 0x0
s_load_b64 s[0:1], s[10:11], 0x0
s_waitcnt lgkmcnt(0)
s_mul_i32 s18, s17, 3
s_mul_i32 s20, s0, 3
s_ashr_i32 s19, s18, 31
s_mul_i32 s0, s1, 3
s_lshl_b64 s[18:19], s[18:19], 2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
s_add_u32 s18, s4, s18
s_addc_u32 s19, s5, s19
s_ashr_i32 s21, s20, 31
global_load_b96 v[27:29], v11, s[18:19]
s_lshl_b64 s[20:21], s[20:21], 2
s_add_u32 s20, s4, s20
s_addc_u32 s21, s5, s21
s_ashr_i32 s1, s0, 31
global_load_b96 v[31:33], v11, s[20:21]
s_lshl_b64 s[0:1], s[0:1], 2
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s0, s4, s0
s_addc_u32 s1, s5, s1
global_load_b96 v[35:37], v11, s[0:1]
s_waitcnt vmcnt(2)
v_sub_f32_e32 v15, v13, v27
v_dual_sub_f32 v19, v8, v28 :: v_dual_sub_f32 v14, v9, v29
s_waitcnt vmcnt(1)
v_dual_sub_f32 v20, v31, v27 :: v_dual_sub_f32 v23, v32, v28
v_sub_f32_e32 v18, v9, v33
v_dual_sub_f32 v22, v33, v29 :: v_dual_sub_f32 v21, v8, v32
v_sub_f32_e32 v24, v13, v31
s_waitcnt vmcnt(0)
v_dual_sub_f32 v25, v29, v37 :: v_dual_sub_f32 v26, v35, v31
v_dual_sub_f32 v27, v27, v35 :: v_dual_sub_f32 v30, v28, v36
v_sub_f32_e32 v34, v13, v35
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_mul_f32_e32 v16, v20, v25
v_sub_f32_e32 v31, v36, v32
v_dual_mul_f32 v17, v23, v27 :: v_dual_mul_f32 v28, v22, v30
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_fma_f32 v35, v22, v27, -v16
v_sub_f32_e32 v29, v9, v37
v_fma_f32 v16, v20, v30, -v17
v_dual_sub_f32 v32, v37, v33 :: v_dual_sub_f32 v33, v8, v36
v_fma_f32 v17, v23, v25, -v28
v_mul_f32_e32 v28, v22, v35
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_mul_f32_e32 v39, v26, v16
v_dual_mul_f32 v36, v20, v16 :: v_dual_mul_f32 v41, v25, v35
v_dual_mul_f32 v38, v32, v35 :: v_dual_mul_f32 v43, v30, v17
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fma_f32 v39, v32, v17, -v39
v_fma_f32 v36, v22, v17, -v36
v_mul_f32_e32 v37, v23, v17
v_mul_f32_e32 v40, v31, v17
v_fma_f32 v28, v23, v16, -v28
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_4)
v_dual_mul_f32 v39, v21, v39 :: v_dual_mul_f32 v36, v19, v36
v_fma_f32 v38, v31, v16, -v38
v_mul_f32_e32 v42, v27, v16
v_fma_f32 v37, v20, v35, -v37
v_fma_f32 v41, v30, v16, -v41
v_dual_fmac_f32 v36, v15, v28 :: v_dual_fmac_f32 v39, v24, v38
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
v_fma_f32 v42, v25, v17, -v42
v_fma_f32 v28, v26, v35, -v40
v_fma_f32 v38, v27, v35, -v43
v_fmac_f32_e32 v36, v14, v37
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_dual_mul_f32 v42, v33, v42 :: v_dual_fmac_f32 v39, v18, v28
v_cmp_lt_f32_e32 vcc_lo, 0, v36
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_fmac_f32_e32 v42, v34, v41
v_cndmask_b32_e64 v28, 0, 1, vcc_lo
v_cmp_lt_f32_e32 vcc_lo, 0, v39
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_fmac_f32_e32 v42, v29, v38
v_cndmask_b32_e64 v37, 0, 1, vcc_lo
v_cmp_lt_f32_e32 vcc_lo, 0, v42
v_cndmask_b32_e64 v38, 0, 1, vcc_lo
v_cmp_gt_f32_e32 vcc_lo, 0, v36
v_subrev_co_ci_u32_e32 v28, vcc_lo, 0, v28, vcc_lo
v_cmp_gt_f32_e32 vcc_lo, 0, v39
v_subrev_co_ci_u32_e32 v36, vcc_lo, 0, v37, vcc_lo
v_cmp_gt_f32_e32 vcc_lo, 0, v42
v_subrev_co_ci_u32_e32 v37, vcc_lo, 0, v38, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add3_u32 v28, v28, v36, v37
v_cmp_lt_i32_e32 vcc_lo, 1, v28
v_mul_f32_e32 v28, v19, v35
s_and_saveexec_b32 s0, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s0, exec_lo, s0
s_cbranch_execz .LBB0_9
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fma_f32 v18, v15, v17, v28
v_mul_f32_e32 v19, v35, v35
v_dual_fmac_f32 v18, v14, v16 :: v_dual_fmac_f32 v19, v17, v17
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mul_f32 v18, v18, v18 :: v_dual_fmac_f32 v19, v16, v16
v_div_scale_f32 v20, null, v19, v19, v18
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v21, v20
s_waitcnt_depctr 0xfff
v_fma_f32 v22, -v20, v21, 1.0
v_fmac_f32_e32 v21, v22, v21
v_div_scale_f32 v22, vcc_lo, v18, v19, v18
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v23, v22, v21
v_fma_f32 v24, -v20, v23, v22
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v23, v24, v21
v_fma_f32 v20, -v20, v23, v22
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fmas_f32 v20, v20, v21, v23
v_div_fixup_f32 v36, v20, v19, v18
.LBB0_9:
s_and_not1_saveexec_b32 s17, s0
s_cbranch_execz .LBB0_6
v_dual_mul_f32 v36, v23, v23 :: v_dual_mul_f32 v39, v30, v33
v_mul_f32_e32 v35, v19, v23
v_dual_mul_f32 v37, v21, v31 :: v_dual_mul_f32 v40, v30, v30
v_mul_f32_e32 v38, v31, v31
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fmac_f32_e32 v36, v20, v20
v_fmac_f32_e32 v37, v24, v26
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_dual_fmac_f32 v35, v15, v20 :: v_dual_fmac_f32 v38, v26, v26
v_fmac_f32_e32 v39, v27, v34
v_dual_fmac_f32 v40, v27, v27 :: v_dual_fmac_f32 v37, v18, v32
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_dual_fmac_f32 v35, v14, v22 :: v_dual_fmac_f32 v38, v32, v32
v_dual_fmac_f32 v36, v22, v22 :: v_dual_fmac_f32 v39, v25, v29
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fmac_f32_e32 v40, v25, v25
v_div_scale_f32 v42, null, v38, v38, v37
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_div_scale_f32 v41, null, v36, v36, v35
v_div_scale_f32 v43, null, v40, v40, v39
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_rcp_f32_e32 v45, v42
v_rcp_f32_e32 v44, v41
v_div_scale_f32 v47, vcc_lo, v35, v36, v35
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(TRANS32_DEP_3)
v_rcp_f32_e32 v46, v43
v_div_scale_f32 v50, s0, v37, v38, v37
v_fma_f32 v49, -v42, v45, 1.0
s_waitcnt_depctr 0xfff
v_fma_f32 v48, -v41, v44, 1.0
v_fma_f32 v51, -v43, v46, 1.0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_dual_fmac_f32 v45, v49, v45 :: v_dual_fmac_f32 v44, v48, v44
v_div_scale_f32 v48, s1, v39, v40, v39
v_dual_fmac_f32 v46, v51, v46 :: v_dual_mul_f32 v51, v50, v45
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_dual_mul_f32 v49, v47, v44 :: v_dual_mul_f32 v52, v48, v46
v_fma_f32 v54, -v42, v51, v50
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fma_f32 v53, -v41, v49, v47
v_fma_f32 v55, -v43, v52, v48
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fmac_f32_e32 v51, v54, v45
v_dual_fmac_f32 v49, v53, v44 :: v_dual_fmac_f32 v52, v55, v46
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v42, -v42, v51, v50
v_fma_f32 v41, -v41, v49, v47
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v43, -v43, v52, v48
v_div_fmas_f32 v41, v41, v44, v49
s_mov_b32 vcc_lo, s0
v_div_fmas_f32 v42, v42, v45, v51
s_mov_b32 vcc_lo, s1
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_div_fixup_f32 v35, v41, v36, v35
v_div_fmas_f32 v43, v43, v46, v52
v_div_fixup_f32 v36, v42, v38, v37
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_minmax_f32 v35, v35, 1.0, 0
v_div_fixup_f32 v37, v43, v40, v39
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_minmax_f32 v36, v36, 1.0, 0
v_fma_f32 v19, v23, v35, -v19
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_minmax_f32 v37, v37, 1.0, 0
v_fma_f32 v20, v20, v35, -v15
v_fma_f32 v21, v31, v36, -v21
v_fma_f32 v24, v26, v36, -v24
v_mul_f32_e32 v19, v19, v19
v_fma_f32 v23, v30, v37, -v33
v_fma_f32 v26, v27, v37, -v34
v_mul_f32_e32 v21, v21, v21
v_fma_f32 v22, v22, v35, -v14
v_fmac_f32_e32 v19, v20, v20
v_mul_f32_e32 v23, v23, v23
v_fma_f32 v18, v32, v36, -v18
v_fmac_f32_e32 v21, v24, v24
v_fma_f32 v20, v25, v37, -v29
v_fmac_f32_e32 v19, v22, v22
v_fmac_f32_e32 v23, v26, v26
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fmac_f32_e32 v21, v18, v18
v_fmac_f32_e32 v23, v20, v20
s_delay_alu instid0(VALU_DEP_1)
v_min3_f32 v36, v19, v21, v23
s_branch .LBB0_6
.LBB0_11:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8mesh2sdfPfiiiS_Pii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 304
.amdhsa_user_sgpr_count 13
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 1
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 2
.amdhsa_next_free_vgpr 56
.amdhsa_next_free_sgpr 22
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z8mesh2sdfPfiiiS_Pii, .Lfunc_end0-_Z8mesh2sdfPfiiiS_Pii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .offset: 40
.size: 4
.value_kind: by_value
- .offset: 48
.size: 4
.value_kind: hidden_block_count_x
- .offset: 52
.size: 4
.value_kind: hidden_block_count_y
- .offset: 56
.size: 4
.value_kind: hidden_block_count_z
- .offset: 60
.size: 2
.value_kind: hidden_group_size_x
- .offset: 62
.size: 2
.value_kind: hidden_group_size_y
- .offset: 64
.size: 2
.value_kind: hidden_group_size_z
- .offset: 66
.size: 2
.value_kind: hidden_remainder_x
- .offset: 68
.size: 2
.value_kind: hidden_remainder_y
- .offset: 70
.size: 2
.value_kind: hidden_remainder_z
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 112
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 304
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8mesh2sdfPfiiiS_Pii
.private_segment_fixed_size: 0
.sgpr_count: 24
.sgpr_spill_count: 0
.symbol: _Z8mesh2sdfPfiiiS_Pii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 56
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
// centroid: [ 92.6200991 -157.6624484 -666.61104378]
// scale: [1.38349843 0.99729681 2.00067234
inline __host__ __device__ float3 operator-(float3 a, float3 b)
{
return make_float3(a.x - b.x, a.y - b.y, a.z - b.z);
}
inline __host__ __device__ float3 cross(float3 a, float3 b)
{
return make_float3(a.y*b.z - a.z*b.y, a.z*b.x - a.x*b.z, a.x*b.y - a.y*b.x);
}
inline __host__ __device__ float dot(float3 a, float3 b)
{
return a.x * b.x + a.y * b.y + a.z * b.z;
}
inline __host__ __device__ float dot2(float3 a)
{
return dot(a,a);
}
inline __device__ __host__ float clamp(float f, float a, float b)
{
return fmaxf(a, fminf(f, b));
}
inline __host__ __device__ float3 operator*(float3 a, float b)
{
return make_float3(a.x * b, a.y * b, a.z * b);
}
inline __host__ __device__ float sign(float x)
{
float t = x > 0.0;
return t - (x < 0.0);
}
// inigo quilez: https://www.iquilezles.org/www/articles/triangledistance/triangledistance.htm
__device__
float distance( float3 v1, float3 v2, float3 v3, float3 p )
{
// prepare data
float3 v21 = v2 - v1; float3 p1 = p - v1;
float3 v32 = v3 - v2; float3 p2 = p - v2;
float3 v13 = v1 - v3; float3 p3 = p - v3;
float3 nor = cross( v21, v13 );
float dist = sqrt( // inside/outside test
( sign(dot(cross(v21,nor),p1))
+ sign(dot(cross(v32,nor),p2))
+ sign(dot(cross(v13,nor),p3))<2.0)
?
// 3 edges
min( min(
dot2(v21*clamp(dot(v21,p1)/dot2(v21),0.0,1.0)-p1),
dot2(v32*clamp(dot(v32,p2)/dot2(v32),0.0,1.0)-p2) ),
dot2(v13*clamp(dot(v13,p3)/dot2(v13),0.0,1.0)-p3) )
:
// 1 face
dot(nor,p1)*dot(nor,p1)/dot2(nor) );
// which side of the triangle?
return sign(dot(nor, p1)) * dist;
}
__global__ void mesh2sdf(float *sdf, int w, int h, int d, float *V, int *F, int nFaces)
{
const uint y = (blockIdx.y * blockDim.y) + threadIdx.y;
const uint z = (blockIdx.z * blockDim.z) + threadIdx.z;
// TODO is this right? (most definitely not)
if(y >= h || z >= d) {
return;
}
// todo pass in scale dont hardcode
const float pt_y = (y - h / 2.0) * 0.99729681 * 64.0 / (float) h;
const float pt_z = (z - d / 2.0) * 2.00067234 * 64.0 / (float) d;
for(uint x=0; x<w; x++) {
const int idx = x + w * (y + d * z);
float currDist = sdf[idx];
const float pt_x = (x - w / 2.0) * 1.38349843 * 64.0 / (float) w;
float3 pt = make_float3(pt_x, pt_y, pt_z);
for(int f=0; f<nFaces; f++) {
float3 v1 = make_float3(V[3*F[3*f+0]+0], V[3*F[3*f+0]+1], V[3*F[3*f+0]+2]);
float3 v2 = make_float3(V[3*F[3*f+1]+0], V[3*F[3*f+1]+1], V[3*F[3*f+1]+2]);
float3 v3 = make_float3(V[3*F[3*f+2]+0], V[3*F[3*f+2]+1], V[3*F[3*f+2]+2]);
const float dist = distance(v1, v2, v3, pt);
if(abs(dist) < abs(currDist)) {
currDist = dist;
}
}
sdf[idx] = currDist;
}
} | .text
.file "mesh2sdf.hip"
.globl _Z23__device_stub__mesh2sdfPfiiiS_Pii # -- Begin function _Z23__device_stub__mesh2sdfPfiiiS_Pii
.p2align 4, 0x90
.type _Z23__device_stub__mesh2sdfPfiiiS_Pii,@function
_Z23__device_stub__mesh2sdfPfiiiS_Pii: # @_Z23__device_stub__mesh2sdfPfiiiS_Pii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movl %ecx, 12(%rsp)
movq %r8, 80(%rsp)
movq %r9, 72(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
leaq 80(%rsp), %rax
movq %rax, 128(%rsp)
leaq 72(%rsp), %rax
movq %rax, 136(%rsp)
leaq 160(%rsp), %rax
movq %rax, 144(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z8mesh2sdfPfiiiS_Pii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z23__device_stub__mesh2sdfPfiiiS_Pii, .Lfunc_end0-_Z23__device_stub__mesh2sdfPfiiiS_Pii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8mesh2sdfPfiiiS_Pii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z8mesh2sdfPfiiiS_Pii,@object # @_Z8mesh2sdfPfiiiS_Pii
.section .rodata,"a",@progbits
.globl _Z8mesh2sdfPfiiiS_Pii
.p2align 3, 0x0
_Z8mesh2sdfPfiiiS_Pii:
.quad _Z23__device_stub__mesh2sdfPfiiiS_Pii
.size _Z8mesh2sdfPfiiiS_Pii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z8mesh2sdfPfiiiS_Pii"
.size .L__unnamed_1, 22
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__mesh2sdfPfiiiS_Pii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8mesh2sdfPfiiiS_Pii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0009031b_00000000-6_mesh2sdf.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2037:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2037:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z8distance6float3S_S_S_
.type _Z8distance6float3S_S_S_, @function
_Z8distance6float3S_S_S_:
.LFB2034:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %xmm0, 48(%rsp)
movss %xmm1, 56(%rsp)
movq %xmm2, 32(%rsp)
movss %xmm3, 40(%rsp)
movq %xmm4, 16(%rsp)
movss %xmm5, 24(%rsp)
movq %xmm6, (%rsp)
movss %xmm7, 8(%rsp)
movl $1, 76(%rsp)
movl 76(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2034:
.size _Z8distance6float3S_S_S_, .-_Z8distance6float3S_S_S_
.globl _Z35__device_stub__Z8mesh2sdfPfiiiS_PiiPfiiiS_Pii
.type _Z35__device_stub__Z8mesh2sdfPfiiiS_PiiPfiiiS_Pii, @function
_Z35__device_stub__Z8mesh2sdfPfiiiS_PiiPfiiiS_Pii:
.LFB2059:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movl %esi, 36(%rsp)
movl %edx, 32(%rsp)
movl %ecx, 28(%rsp)
movq %r8, 16(%rsp)
movq %r9, 8(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 36(%rsp), %rax
movq %rax, 120(%rsp)
leaq 32(%rsp), %rax
movq %rax, 128(%rsp)
leaq 28(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
leaq 192(%rsp), %rax
movq %rax, 160(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L9
.L5:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L10
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z8mesh2sdfPfiiiS_Pii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L5
.L10:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size _Z35__device_stub__Z8mesh2sdfPfiiiS_PiiPfiiiS_Pii, .-_Z35__device_stub__Z8mesh2sdfPfiiiS_PiiPfiiiS_Pii
.globl _Z8mesh2sdfPfiiiS_Pii
.type _Z8mesh2sdfPfiiiS_Pii, @function
_Z8mesh2sdfPfiiiS_Pii:
.LFB2060:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
call _Z35__device_stub__Z8mesh2sdfPfiiiS_PiiPfiiiS_Pii
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _Z8mesh2sdfPfiiiS_Pii, .-_Z8mesh2sdfPfiiiS_Pii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z8mesh2sdfPfiiiS_Pii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z8mesh2sdfPfiiiS_Pii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "mesh2sdf.hip"
.globl _Z23__device_stub__mesh2sdfPfiiiS_Pii # -- Begin function _Z23__device_stub__mesh2sdfPfiiiS_Pii
.p2align 4, 0x90
.type _Z23__device_stub__mesh2sdfPfiiiS_Pii,@function
_Z23__device_stub__mesh2sdfPfiiiS_Pii: # @_Z23__device_stub__mesh2sdfPfiiiS_Pii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movl %ecx, 12(%rsp)
movq %r8, 80(%rsp)
movq %r9, 72(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
leaq 80(%rsp), %rax
movq %rax, 128(%rsp)
leaq 72(%rsp), %rax
movq %rax, 136(%rsp)
leaq 160(%rsp), %rax
movq %rax, 144(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z8mesh2sdfPfiiiS_Pii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z23__device_stub__mesh2sdfPfiiiS_Pii, .Lfunc_end0-_Z23__device_stub__mesh2sdfPfiiiS_Pii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8mesh2sdfPfiiiS_Pii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z8mesh2sdfPfiiiS_Pii,@object # @_Z8mesh2sdfPfiiiS_Pii
.section .rodata,"a",@progbits
.globl _Z8mesh2sdfPfiiiS_Pii
.p2align 3, 0x0
_Z8mesh2sdfPfiiiS_Pii:
.quad _Z23__device_stub__mesh2sdfPfiiiS_Pii
.size _Z8mesh2sdfPfiiiS_Pii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z8mesh2sdfPfiiiS_Pii"
.size .L__unnamed_1, 22
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__mesh2sdfPfiiiS_Pii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8mesh2sdfPfiiiS_Pii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <iostream>
using namespace std;
__global__ void kernel( int* b, int* t)
{
if( !threadIdx.x)
{
*b = blockDim.x; // num threads per block
}
t[threadIdx.x] = threadIdx.x;
}
int main()
{
int numthreads = 4;
int b;
int* t;
t = new int[numthreads];
int* d_b; // pointer to device memory
int* d_t; // pointer to device memory
cudaMalloc( (void**)&d_b, sizeof(int));
cudaMalloc( (void**)&d_t, numthreads*sizeof(int));
kernel<<<1,numthreads>>>( d_b, d_t);
cudaMemcpy( &b, d_b, sizeof(int)
, cudaMemcpyDeviceToHost);
cudaMemcpy( t, d_t, numthreads*sizeof(int)
, cudaMemcpyDeviceToHost);
cout << "blockDim.x = " << b << endl;
int thread;
for( thread=0; thread<numthreads; thread++)
{
cout << "thread " << thread
<< ": " << t[thread]
<< endl;
}
cudaFree(d_t);
cudaFree(d_b);
return 0;
} | code for sm_80
Function : _Z6kernelPiS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R7, SR_TID.X ; /* 0x0000000000077919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R4, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff047435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ ISETP.NE.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x001fd00003f05270 */
/*0050*/ IMAD.WIDE.U32 R4, R7, R4, c[0x0][0x168] ; /* 0x00005a0007047625 */
/* 0x000fca00078e0004 */
/*0060*/ @!P0 IMAD.MOV.U32 R9, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff098624 */
/* 0x000fe200078e00ff */
/*0070*/ @!P0 MOV R2, c[0x0][0x160] ; /* 0x0000580000028a02 */
/* 0x000fe20000000f00 */
/*0080*/ @!P0 IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff038624 */
/* 0x000fca00078e00ff */
/*0090*/ @!P0 STG.E [R2.64], R9 ; /* 0x0000000902008986 */
/* 0x000fe8000c101904 */
/*00a0*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x000fe2000c101904 */
/*00b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00c0*/ BRA 0xc0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <iostream>
using namespace std;
__global__ void kernel( int* b, int* t)
{
if( !threadIdx.x)
{
*b = blockDim.x; // num threads per block
}
t[threadIdx.x] = threadIdx.x;
}
int main()
{
int numthreads = 4;
int b;
int* t;
t = new int[numthreads];
int* d_b; // pointer to device memory
int* d_t; // pointer to device memory
cudaMalloc( (void**)&d_b, sizeof(int));
cudaMalloc( (void**)&d_t, numthreads*sizeof(int));
kernel<<<1,numthreads>>>( d_b, d_t);
cudaMemcpy( &b, d_b, sizeof(int)
, cudaMemcpyDeviceToHost);
cudaMemcpy( t, d_t, numthreads*sizeof(int)
, cudaMemcpyDeviceToHost);
cout << "blockDim.x = " << b << endl;
int thread;
for( thread=0; thread<numthreads; thread++)
{
cout << "thread " << thread
<< ": " << t[thread]
<< endl;
}
cudaFree(d_t);
cudaFree(d_b);
return 0;
} | .file "tmpxft_000dc4fd_00000000-6_05_cuda.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z27__device_stub__Z6kernelPiS_PiS_
.type _Z27__device_stub__Z6kernelPiS_PiS_, @function
_Z27__device_stub__Z6kernelPiS_PiS_:
.LFB3694:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z6kernelPiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3694:
.size _Z27__device_stub__Z6kernelPiS_PiS_, .-_Z27__device_stub__Z6kernelPiS_PiS_
.globl _Z6kernelPiS_
.type _Z6kernelPiS_, @function
_Z6kernelPiS_:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z27__device_stub__Z6kernelPiS_PiS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _Z6kernelPiS_, .-_Z6kernelPiS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "blockDim.x = "
.LC1:
.string "thread "
.LC2:
.string ": "
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $56, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movl $16, %edi
call _Znam@PLT
movq %rax, %r14
movq %rsp, %rdi
movl $4, %esi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movl $16, %esi
call cudaMalloc@PLT
movl $4, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L21
.L12:
leaq 28(%rsp), %rdi
movl $2, %ecx
movl $4, %edx
movq (%rsp), %rsi
call cudaMemcpy@PLT
movl $2, %ecx
movl $16, %edx
movq 8(%rsp), %rsi
movq %r14, %rdi
call cudaMemcpy@PLT
leaq .LC0(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl 28(%rsp), %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $0, %ebp
leaq .LC1(%rip), %r15
leaq _ZSt4cout(%rip), %r13
jmp .L17
.L21:
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z27__device_stub__Z6kernelPiS_PiS_
jmp .L12
.L24:
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L22
call _ZSt16__throw_bad_castv@PLT
.L22:
call __stack_chk_fail@PLT
.L15:
movq %r12, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r12), %rax
movl $10, %esi
movq %r12, %rdi
call *48(%rax)
movl %eax, %esi
.L16:
movsbl %sil, %esi
movq %rbx, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
addq $1, %rbp
cmpq $4, %rbp
je .L23
.L17:
movl $7, %edx
movq %r15, %rsi
movq %r13, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl %ebp, %esi
movq %r13, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbx
movl $2, %edx
leaq .LC2(%rip), %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl (%r14,%rbp,4), %esi
movq %rbx, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbx
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r12
testq %r12, %r12
je .L24
cmpb $0, 56(%r12)
je .L15
movzbl 67(%r12), %esi
jmp .L16
.L23:
movq 8(%rsp), %rdi
call cudaFree@PLT
movq (%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L25
movl $0, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L25:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size main, .-main
.section .rodata.str1.1
.LC3:
.string "_Z6kernelPiS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z6kernelPiS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <iostream>
using namespace std;
__global__ void kernel( int* b, int* t)
{
if( !threadIdx.x)
{
*b = blockDim.x; // num threads per block
}
t[threadIdx.x] = threadIdx.x;
}
int main()
{
int numthreads = 4;
int b;
int* t;
t = new int[numthreads];
int* d_b; // pointer to device memory
int* d_t; // pointer to device memory
cudaMalloc( (void**)&d_b, sizeof(int));
cudaMalloc( (void**)&d_t, numthreads*sizeof(int));
kernel<<<1,numthreads>>>( d_b, d_t);
cudaMemcpy( &b, d_b, sizeof(int)
, cudaMemcpyDeviceToHost);
cudaMemcpy( t, d_t, numthreads*sizeof(int)
, cudaMemcpyDeviceToHost);
cout << "blockDim.x = " << b << endl;
int thread;
for( thread=0; thread<numthreads; thread++)
{
cout << "thread " << thread
<< ": " << t[thread]
<< endl;
}
cudaFree(d_t);
cudaFree(d_b);
return 0;
} | #include <hip/hip_runtime.h>
#include <iostream>
using namespace std;
__global__ void kernel( int* b, int* t)
{
if( !threadIdx.x)
{
*b = blockDim.x; // num threads per block
}
t[threadIdx.x] = threadIdx.x;
}
int main()
{
int numthreads = 4;
int b;
int* t;
t = new int[numthreads];
int* d_b; // pointer to device memory
int* d_t; // pointer to device memory
hipMalloc( (void**)&d_b, sizeof(int));
hipMalloc( (void**)&d_t, numthreads*sizeof(int));
kernel<<<1,numthreads>>>( d_b, d_t);
hipMemcpy( &b, d_b, sizeof(int)
, hipMemcpyDeviceToHost);
hipMemcpy( t, d_t, numthreads*sizeof(int)
, hipMemcpyDeviceToHost);
cout << "blockDim.x = " << b << endl;
int thread;
for( thread=0; thread<numthreads; thread++)
{
cout << "thread " << thread
<< ": " << t[thread]
<< endl;
}
hipFree(d_t);
hipFree(d_b);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <iostream>
using namespace std;
__global__ void kernel( int* b, int* t)
{
if( !threadIdx.x)
{
*b = blockDim.x; // num threads per block
}
t[threadIdx.x] = threadIdx.x;
}
int main()
{
int numthreads = 4;
int b;
int* t;
t = new int[numthreads];
int* d_b; // pointer to device memory
int* d_t; // pointer to device memory
hipMalloc( (void**)&d_b, sizeof(int));
hipMalloc( (void**)&d_t, numthreads*sizeof(int));
kernel<<<1,numthreads>>>( d_b, d_t);
hipMemcpy( &b, d_b, sizeof(int)
, hipMemcpyDeviceToHost);
hipMemcpy( t, d_t, numthreads*sizeof(int)
, hipMemcpyDeviceToHost);
cout << "blockDim.x = " << b << endl;
int thread;
for( thread=0; thread<numthreads; thread++)
{
cout << "thread " << thread
<< ": " << t[thread]
<< endl;
}
hipFree(d_t);
hipFree(d_b);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6kernelPiS_
.globl _Z6kernelPiS_
.p2align 8
.type _Z6kernelPiS_,@function
_Z6kernelPiS_:
s_mov_b32 s2, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_2
s_clause 0x1
s_load_b32 s3, s[0:1], 0x1c
s_load_b64 s[4:5], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v2, s3
global_store_b32 v1, v2, s[4:5]
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s2
s_load_b64 s[0:1], s[0:1], 0x8
v_lshlrev_b32_e32 v1, 2, v0
s_waitcnt lgkmcnt(0)
global_store_b32 v1, v0, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6kernelPiS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 6
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6kernelPiS_, .Lfunc_end0-_Z6kernelPiS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6kernelPiS_
.private_segment_fixed_size: 0
.sgpr_count: 6
.sgpr_spill_count: 0
.symbol: _Z6kernelPiS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <iostream>
using namespace std;
__global__ void kernel( int* b, int* t)
{
if( !threadIdx.x)
{
*b = blockDim.x; // num threads per block
}
t[threadIdx.x] = threadIdx.x;
}
int main()
{
int numthreads = 4;
int b;
int* t;
t = new int[numthreads];
int* d_b; // pointer to device memory
int* d_t; // pointer to device memory
hipMalloc( (void**)&d_b, sizeof(int));
hipMalloc( (void**)&d_t, numthreads*sizeof(int));
kernel<<<1,numthreads>>>( d_b, d_t);
hipMemcpy( &b, d_b, sizeof(int)
, hipMemcpyDeviceToHost);
hipMemcpy( t, d_t, numthreads*sizeof(int)
, hipMemcpyDeviceToHost);
cout << "blockDim.x = " << b << endl;
int thread;
for( thread=0; thread<numthreads; thread++)
{
cout << "thread " << thread
<< ": " << t[thread]
<< endl;
}
hipFree(d_t);
hipFree(d_b);
return 0;
} | .text
.file "05_cuda.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z21__device_stub__kernelPiS_ # -- Begin function _Z21__device_stub__kernelPiS_
.p2align 4, 0x90
.type _Z21__device_stub__kernelPiS_,@function
_Z21__device_stub__kernelPiS_: # @_Z21__device_stub__kernelPiS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z6kernelPiS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z21__device_stub__kernelPiS_, .Lfunc_end0-_Z21__device_stub__kernelPiS_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $104, %rsp
.cfi_def_cfa_offset 144
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $16, %edi
callq _Znam
movq %rax, %rbx
leaq 8(%rsp), %rdi
movl $4, %esi
callq hipMalloc
movq %rsp, %rdi
movl $16, %esi
callq hipMalloc
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 3(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq 8(%rsp), %rax
movq (%rsp), %rcx
movq %rax, 96(%rsp)
movq %rcx, 88(%rsp)
leaq 96(%rsp), %rax
movq %rax, 16(%rsp)
leaq 88(%rsp), %rax
movq %rax, 24(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z6kernelPiS_, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
movq 8(%rsp), %rsi
leaq 16(%rsp), %rdi
movl $4, %edx
movl $2, %ecx
callq hipMemcpy
movq (%rsp), %rsi
movl $16, %edx
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $13, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl 16(%rsp), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r14
testq %r14, %r14
je .LBB1_13
# %bb.3: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%r14)
je .LBB1_5
# %bb.4:
movzbl 67(%r14), %ecx
jmp .LBB1_6
.LBB1_5:
movq %r14, %rdi
movq %rax, %r15
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r15, %rax
.LBB1_6: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
xorl %r14d, %r14d
jmp .LBB1_7
.p2align 4, 0x90
.LBB1_10: # in Loop: Header=BB1_7 Depth=1
movq %r15, %rdi
movq %rax, %r12
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r12, %rax
.LBB1_11: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit16
# in Loop: Header=BB1_7 Depth=1
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
incq %r14
cmpq $4, %r14
je .LBB1_12
.LBB1_7: # =>This Inner Loop Header: Depth=1
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $7, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl %r14d, %esi
callq _ZNSolsEi
movq %rax, %r15
movl $.L.str.2, %esi
movl $2, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl (%rbx,%r14,4), %esi
movq %r15, %rdi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r15
testq %r15, %r15
je .LBB1_13
# %bb.8: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i13
# in Loop: Header=BB1_7 Depth=1
cmpb $0, 56(%r15)
je .LBB1_10
# %bb.9: # in Loop: Header=BB1_7 Depth=1
movzbl 67(%r15), %ecx
jmp .LBB1_11
.LBB1_12:
movq (%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $104, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB1_13:
.cfi_def_cfa_offset 144
callq _ZSt16__throw_bad_castv
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6kernelPiS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6kernelPiS_,@object # @_Z6kernelPiS_
.section .rodata,"a",@progbits
.globl _Z6kernelPiS_
.p2align 3, 0x0
_Z6kernelPiS_:
.quad _Z21__device_stub__kernelPiS_
.size _Z6kernelPiS_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "blockDim.x = "
.size .L.str, 14
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "thread "
.size .L.str.1, 8
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz ": "
.size .L.str.2, 3
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z6kernelPiS_"
.size .L__unnamed_1, 14
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__kernelPiS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6kernelPiS_
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z6kernelPiS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R7, SR_TID.X ; /* 0x0000000000077919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R4, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff047435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ ISETP.NE.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x001fd00003f05270 */
/*0050*/ IMAD.WIDE.U32 R4, R7, R4, c[0x0][0x168] ; /* 0x00005a0007047625 */
/* 0x000fca00078e0004 */
/*0060*/ @!P0 IMAD.MOV.U32 R9, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff098624 */
/* 0x000fe200078e00ff */
/*0070*/ @!P0 MOV R2, c[0x0][0x160] ; /* 0x0000580000028a02 */
/* 0x000fe20000000f00 */
/*0080*/ @!P0 IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff038624 */
/* 0x000fca00078e00ff */
/*0090*/ @!P0 STG.E [R2.64], R9 ; /* 0x0000000902008986 */
/* 0x000fe8000c101904 */
/*00a0*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x000fe2000c101904 */
/*00b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00c0*/ BRA 0xc0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6kernelPiS_
.globl _Z6kernelPiS_
.p2align 8
.type _Z6kernelPiS_,@function
_Z6kernelPiS_:
s_mov_b32 s2, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_2
s_clause 0x1
s_load_b32 s3, s[0:1], 0x1c
s_load_b64 s[4:5], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v2, s3
global_store_b32 v1, v2, s[4:5]
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s2
s_load_b64 s[0:1], s[0:1], 0x8
v_lshlrev_b32_e32 v1, 2, v0
s_waitcnt lgkmcnt(0)
global_store_b32 v1, v0, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6kernelPiS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 6
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6kernelPiS_, .Lfunc_end0-_Z6kernelPiS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6kernelPiS_
.private_segment_fixed_size: 0
.sgpr_count: 6
.sgpr_spill_count: 0
.symbol: _Z6kernelPiS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000dc4fd_00000000-6_05_cuda.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z27__device_stub__Z6kernelPiS_PiS_
.type _Z27__device_stub__Z6kernelPiS_PiS_, @function
_Z27__device_stub__Z6kernelPiS_PiS_:
.LFB3694:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z6kernelPiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3694:
.size _Z27__device_stub__Z6kernelPiS_PiS_, .-_Z27__device_stub__Z6kernelPiS_PiS_
.globl _Z6kernelPiS_
.type _Z6kernelPiS_, @function
_Z6kernelPiS_:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z27__device_stub__Z6kernelPiS_PiS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _Z6kernelPiS_, .-_Z6kernelPiS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "blockDim.x = "
.LC1:
.string "thread "
.LC2:
.string ": "
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $56, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movl $16, %edi
call _Znam@PLT
movq %rax, %r14
movq %rsp, %rdi
movl $4, %esi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movl $16, %esi
call cudaMalloc@PLT
movl $4, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L21
.L12:
leaq 28(%rsp), %rdi
movl $2, %ecx
movl $4, %edx
movq (%rsp), %rsi
call cudaMemcpy@PLT
movl $2, %ecx
movl $16, %edx
movq 8(%rsp), %rsi
movq %r14, %rdi
call cudaMemcpy@PLT
leaq .LC0(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl 28(%rsp), %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $0, %ebp
leaq .LC1(%rip), %r15
leaq _ZSt4cout(%rip), %r13
jmp .L17
.L21:
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z27__device_stub__Z6kernelPiS_PiS_
jmp .L12
.L24:
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L22
call _ZSt16__throw_bad_castv@PLT
.L22:
call __stack_chk_fail@PLT
.L15:
movq %r12, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r12), %rax
movl $10, %esi
movq %r12, %rdi
call *48(%rax)
movl %eax, %esi
.L16:
movsbl %sil, %esi
movq %rbx, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
addq $1, %rbp
cmpq $4, %rbp
je .L23
.L17:
movl $7, %edx
movq %r15, %rsi
movq %r13, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl %ebp, %esi
movq %r13, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbx
movl $2, %edx
leaq .LC2(%rip), %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl (%r14,%rbp,4), %esi
movq %rbx, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbx
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r12
testq %r12, %r12
je .L24
cmpb $0, 56(%r12)
je .L15
movzbl 67(%r12), %esi
jmp .L16
.L23:
movq 8(%rsp), %rdi
call cudaFree@PLT
movq (%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L25
movl $0, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L25:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size main, .-main
.section .rodata.str1.1
.LC3:
.string "_Z6kernelPiS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z6kernelPiS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "05_cuda.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z21__device_stub__kernelPiS_ # -- Begin function _Z21__device_stub__kernelPiS_
.p2align 4, 0x90
.type _Z21__device_stub__kernelPiS_,@function
_Z21__device_stub__kernelPiS_: # @_Z21__device_stub__kernelPiS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z6kernelPiS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z21__device_stub__kernelPiS_, .Lfunc_end0-_Z21__device_stub__kernelPiS_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $104, %rsp
.cfi_def_cfa_offset 144
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $16, %edi
callq _Znam
movq %rax, %rbx
leaq 8(%rsp), %rdi
movl $4, %esi
callq hipMalloc
movq %rsp, %rdi
movl $16, %esi
callq hipMalloc
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 3(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq 8(%rsp), %rax
movq (%rsp), %rcx
movq %rax, 96(%rsp)
movq %rcx, 88(%rsp)
leaq 96(%rsp), %rax
movq %rax, 16(%rsp)
leaq 88(%rsp), %rax
movq %rax, 24(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z6kernelPiS_, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
movq 8(%rsp), %rsi
leaq 16(%rsp), %rdi
movl $4, %edx
movl $2, %ecx
callq hipMemcpy
movq (%rsp), %rsi
movl $16, %edx
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $13, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl 16(%rsp), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r14
testq %r14, %r14
je .LBB1_13
# %bb.3: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%r14)
je .LBB1_5
# %bb.4:
movzbl 67(%r14), %ecx
jmp .LBB1_6
.LBB1_5:
movq %r14, %rdi
movq %rax, %r15
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r15, %rax
.LBB1_6: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
xorl %r14d, %r14d
jmp .LBB1_7
.p2align 4, 0x90
.LBB1_10: # in Loop: Header=BB1_7 Depth=1
movq %r15, %rdi
movq %rax, %r12
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r12, %rax
.LBB1_11: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit16
# in Loop: Header=BB1_7 Depth=1
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
incq %r14
cmpq $4, %r14
je .LBB1_12
.LBB1_7: # =>This Inner Loop Header: Depth=1
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $7, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl %r14d, %esi
callq _ZNSolsEi
movq %rax, %r15
movl $.L.str.2, %esi
movl $2, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl (%rbx,%r14,4), %esi
movq %r15, %rdi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r15
testq %r15, %r15
je .LBB1_13
# %bb.8: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i13
# in Loop: Header=BB1_7 Depth=1
cmpb $0, 56(%r15)
je .LBB1_10
# %bb.9: # in Loop: Header=BB1_7 Depth=1
movzbl 67(%r15), %ecx
jmp .LBB1_11
.LBB1_12:
movq (%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $104, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB1_13:
.cfi_def_cfa_offset 144
callq _ZSt16__throw_bad_castv
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6kernelPiS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6kernelPiS_,@object # @_Z6kernelPiS_
.section .rodata,"a",@progbits
.globl _Z6kernelPiS_
.p2align 3, 0x0
_Z6kernelPiS_:
.quad _Z21__device_stub__kernelPiS_
.size _Z6kernelPiS_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "blockDim.x = "
.size .L.str, 14
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "thread "
.size .L.str.1, 8
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz ": "
.size .L.str.2, 3
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z6kernelPiS_"
.size .L__unnamed_1, 14
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__kernelPiS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6kernelPiS_
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
#define N 10
//Sum Arrays
__global__ void add(int *x, int *y, int *z){
int tID = blockIdx.x;
if (tID < N){
z[tID] = x[tID] + y[tID];
}
} | code for sm_80
Function : _Z3addPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e240000002500 */
/*0020*/ ISETP.GT.AND P0, PT, R6, 0x9, PT ; /* 0x000000090600780c */
/* 0x001fda0003f04270 */
/*0030*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0040*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0050*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0060*/ IMAD.WIDE R4, R6, R7, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x000fc800078e0207 */
/*0070*/ IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x0c0fe400078e0207 */
/*0080*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*0090*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fe200078e0207 */
/*00b0*/ IADD3 R9, R4, R3, RZ ; /* 0x0000000304097210 */
/* 0x004fca0007ffe0ff */
/*00c0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00e0*/ BRA 0xe0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
#define N 10
//Sum Arrays
__global__ void add(int *x, int *y, int *z){
int tID = blockIdx.x;
if (tID < N){
z[tID] = x[tID] + y[tID];
}
} | .file "tmpxft_000a10fe_00000000-6_add.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z26__device_stub__Z3addPiS_S_PiS_S_
.type _Z26__device_stub__Z3addPiS_S_PiS_S_, @function
_Z26__device_stub__Z3addPiS_S_PiS_S_:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3addPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z26__device_stub__Z3addPiS_S_PiS_S_, .-_Z26__device_stub__Z3addPiS_S_PiS_S_
.globl _Z3addPiS_S_
.type _Z3addPiS_S_, @function
_Z3addPiS_S_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z3addPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z3addPiS_S_, .-_Z3addPiS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z3addPiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z3addPiS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
#define N 10
//Sum Arrays
__global__ void add(int *x, int *y, int *z){
int tID = blockIdx.x;
if (tID < N){
z[tID] = x[tID] + y[tID];
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
#define N 10
//Sum Arrays
__global__ void add(int *x, int *y, int *z){
int tID = blockIdx.x;
if (tID < N){
z[tID] = x[tID] + y[tID];
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
#define N 10
//Sum Arrays
__global__ void add(int *x, int *y, int *z){
int tID = blockIdx.x;
if (tID < N){
z[tID] = x[tID] + y[tID];
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3addPiS_S_
.globl _Z3addPiS_S_
.p2align 8
.type _Z3addPiS_S_,@function
_Z3addPiS_S_:
s_cmp_gt_i32 s15, 9
s_cbranch_scc1 .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
s_mov_b32 s2, s15
s_ashr_i32 s3, s15, 31
s_load_b64 s[0:1], s[0:1], 0x10
s_lshl_b64 s[2:3], s[2:3], 2
s_waitcnt lgkmcnt(0)
s_add_u32 s4, s4, s2
s_addc_u32 s5, s5, s3
s_add_u32 s6, s6, s2
s_addc_u32 s7, s7, s3
s_load_b32 s4, s[4:5], 0x0
s_load_b32 s5, s[6:7], 0x0
s_waitcnt lgkmcnt(0)
s_add_i32 s4, s5, s4
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s4
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
global_store_b32 v0, v1, s[0:1]
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3addPiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 16
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3addPiS_S_, .Lfunc_end0-_Z3addPiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3addPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 16
.sgpr_spill_count: 0
.symbol: _Z3addPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
#define N 10
//Sum Arrays
__global__ void add(int *x, int *y, int *z){
int tID = blockIdx.x;
if (tID < N){
z[tID] = x[tID] + y[tID];
}
} | .text
.file "add.hip"
.globl _Z18__device_stub__addPiS_S_ # -- Begin function _Z18__device_stub__addPiS_S_
.p2align 4, 0x90
.type _Z18__device_stub__addPiS_S_,@function
_Z18__device_stub__addPiS_S_: # @_Z18__device_stub__addPiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3addPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z18__device_stub__addPiS_S_, .Lfunc_end0-_Z18__device_stub__addPiS_S_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3addPiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3addPiS_S_,@object # @_Z3addPiS_S_
.section .rodata,"a",@progbits
.globl _Z3addPiS_S_
.p2align 3, 0x0
_Z3addPiS_S_:
.quad _Z18__device_stub__addPiS_S_
.size _Z3addPiS_S_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z3addPiS_S_"
.size .L__unnamed_1, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__addPiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3addPiS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z3addPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e240000002500 */
/*0020*/ ISETP.GT.AND P0, PT, R6, 0x9, PT ; /* 0x000000090600780c */
/* 0x001fda0003f04270 */
/*0030*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0040*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0050*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0060*/ IMAD.WIDE R4, R6, R7, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x000fc800078e0207 */
/*0070*/ IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x0c0fe400078e0207 */
/*0080*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*0090*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fe200078e0207 */
/*00b0*/ IADD3 R9, R4, R3, RZ ; /* 0x0000000304097210 */
/* 0x004fca0007ffe0ff */
/*00c0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00e0*/ BRA 0xe0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3addPiS_S_
.globl _Z3addPiS_S_
.p2align 8
.type _Z3addPiS_S_,@function
_Z3addPiS_S_:
s_cmp_gt_i32 s15, 9
s_cbranch_scc1 .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
s_mov_b32 s2, s15
s_ashr_i32 s3, s15, 31
s_load_b64 s[0:1], s[0:1], 0x10
s_lshl_b64 s[2:3], s[2:3], 2
s_waitcnt lgkmcnt(0)
s_add_u32 s4, s4, s2
s_addc_u32 s5, s5, s3
s_add_u32 s6, s6, s2
s_addc_u32 s7, s7, s3
s_load_b32 s4, s[4:5], 0x0
s_load_b32 s5, s[6:7], 0x0
s_waitcnt lgkmcnt(0)
s_add_i32 s4, s5, s4
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s4
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
global_store_b32 v0, v1, s[0:1]
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3addPiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 16
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3addPiS_S_, .Lfunc_end0-_Z3addPiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3addPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 16
.sgpr_spill_count: 0
.symbol: _Z3addPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000a10fe_00000000-6_add.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z26__device_stub__Z3addPiS_S_PiS_S_
.type _Z26__device_stub__Z3addPiS_S_PiS_S_, @function
_Z26__device_stub__Z3addPiS_S_PiS_S_:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3addPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z26__device_stub__Z3addPiS_S_PiS_S_, .-_Z26__device_stub__Z3addPiS_S_PiS_S_
.globl _Z3addPiS_S_
.type _Z3addPiS_S_, @function
_Z3addPiS_S_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z3addPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z3addPiS_S_, .-_Z3addPiS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z3addPiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z3addPiS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "add.hip"
.globl _Z18__device_stub__addPiS_S_ # -- Begin function _Z18__device_stub__addPiS_S_
.p2align 4, 0x90
.type _Z18__device_stub__addPiS_S_,@function
_Z18__device_stub__addPiS_S_: # @_Z18__device_stub__addPiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3addPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z18__device_stub__addPiS_S_, .Lfunc_end0-_Z18__device_stub__addPiS_S_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3addPiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3addPiS_S_,@object # @_Z3addPiS_S_
.section .rodata,"a",@progbits
.globl _Z3addPiS_S_
.p2align 3, 0x0
_Z3addPiS_S_:
.quad _Z18__device_stub__addPiS_S_
.size _Z3addPiS_S_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z3addPiS_S_"
.size .L__unnamed_1, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__addPiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3addPiS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
// filename: eeTanh.cu
// a simple CUDA kernel to square the elements of a matrix
extern "C" // ensure function name to be exactly "eeTanh"
{
}
__global__ void cauchyLogErrDeriv(int N, int M, float *A, float *Y, float *out)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
int j = blockIdx.y * blockDim.y + threadIdx.y;
int index = j*N + i;
int L = N*M;
if (i < N && j < M)
{
float a = __expf(A[index+L]);
if (A[index] > Y[index])
{
out[index] = a;
}
else if (A[index] < Y[index])
{
out[index] = -a;
}
else
{
out[index] = 0.0;
}
out[index+L] = __fmaf_rn(a, fabsf(__fsub_rn(A[index], Y[index])), -1.0);
// A2 in this case is stored in the doubled rows of A, the length of A is
// doublt that of Y, out is the same length as A and will store both parts of the derivative
}
} | code for sm_80
Function : _Z17cauchyLogErrDeriviiPfS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e280000002600 */
/*0020*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e280000002200 */
/*0030*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e680000002500 */
/*0040*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0050*/ IMAD R3, R3, c[0x0][0x4], R2 ; /* 0x0000010003037a24 */
/* 0x001fca00078e0202 */
/*0060*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x164], PT ; /* 0x0000590003007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R0, R0, c[0x0][0x0], R5 ; /* 0x0000000000007a24 */
/* 0x002fca00078e0205 */
/*0080*/ ISETP.GE.OR P0, PT, R0, c[0x0][0x160], P0 ; /* 0x0000580000007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ MOV R11, c[0x0][0x164] ; /* 0x00005900000b7a02 */
/* 0x000fe20000000f00 */
/*00b0*/ IMAD R0, R3, c[0x0][0x160], R0 ; /* 0x0000580003007a24 */
/* 0x000fe200078e0200 */
/*00c0*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*00d0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*00e0*/ IMAD R11, R11, c[0x0][0x160], RZ ; /* 0x000058000b0b7a24 */
/* 0x000fca00078e02ff */
/*00f0*/ IADD3 R2, R11, R0, RZ ; /* 0x000000000b027210 */
/* 0x000fca0007ffe0ff */
/*0100*/ IMAD.WIDE R2, R2, R5, c[0x0][0x168] ; /* 0x00005a0002027625 */
/* 0x000fcc00078e0205 */
/*0110*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*0120*/ IMAD.WIDE R6, R0, R5, c[0x0][0x170] ; /* 0x00005c0000067625 */
/* 0x000fc800078e0205 */
/*0130*/ IMAD.WIDE R4, R0.reuse, R5, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x040fe200078e0205 */
/*0140*/ LDG.E R13, [R6.64] ; /* 0x00000004060d7981 */
/* 0x000ee8000c1e1900 */
/*0150*/ LDG.E R14, [R4.64] ; /* 0x00000004040e7981 */
/* 0x000ee2000c1e1900 */
/*0160*/ SHF.R.S32.HI R9, RZ, 0x1f, R0 ; /* 0x0000001fff097819 */
/* 0x000fe20000011400 */
/*0170*/ BSSY B0, 0x260 ; /* 0x000000e000007945 */
/* 0x000fe20003800000 */
/*0180*/ LEA R8, P2, R0, c[0x0][0x178], 0x2 ; /* 0x00005e0000087a11 */
/* 0x000fc800078410ff */
/*0190*/ LEA.HI.X R9, R0, c[0x0][0x17c], R9, 0x2, P2 ; /* 0x00005f0000097a11 */
/* 0x000fe200010f1409 */
/*01a0*/ FMUL R10, R2, 1.4426950216293334961 ; /* 0x3fb8aa3b020a7820 */
/* 0x004fca0000400000 */
/*01b0*/ FSETP.GEU.AND P0, PT, R10, -126, PT ; /* 0xc2fc00000a00780b */
/* 0x000fe40003f0e000 */
/*01c0*/ FSETP.GT.AND P1, PT, R14, R13, PT ; /* 0x0000000d0e00720b */
/* 0x008fd60003f24000 */
/*01d0*/ @!P0 FMUL R10, R10, 0.5 ; /* 0x3f0000000a0a8820 */
/* 0x000fc80000400000 */
/*01e0*/ MUFU.EX2 R12, R10 ; /* 0x0000000a000c7308 */
/* 0x000e240000000800 */
/*01f0*/ @!P0 FMUL R12, R12, R12 ; /* 0x0000000c0c0c8220 */
/* 0x001fca0000400000 */
/*0200*/ MOV R15, R12 ; /* 0x0000000c000f7202 */
/* 0x000fe20000000f00 */
/*0210*/ @P1 BRA 0x250 ; /* 0x0000003000001947 */
/* 0x000fea0003800000 */
/*0220*/ FSETP.GEU.AND P0, PT, R14, R13, PT ; /* 0x0000000d0e00720b */
/* 0x000fe40003f0e000 */
/*0230*/ MOV R15, RZ ; /* 0x000000ff000f7202 */
/* 0x000fd60000000f00 */
/*0240*/ @!P0 FADD R15, -R12, -RZ ; /* 0x800000ff0c0f8221 */
/* 0x000fe40000000100 */
/*0250*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0260*/ STG.E [R8.64], R15 ; /* 0x0000000f08007986 */
/* 0x000fe8000c101904 */
/*0270*/ LDG.E R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000ea8000c1e1900 */
/*0280*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*0290*/ IMAD.WIDE R2, R11, 0x4, R8 ; /* 0x000000040b027825 */
/* 0x000fc800078e0208 */
/*02a0*/ FADD R13, -R6, R5 ; /* 0x00000005060d7221 */
/* 0x004fc80000000100 */
/*02b0*/ FFMA R13, R12, |R13|, -1 ; /* 0xbf8000000c0d7423 */
/* 0x000fca000000040d */
/*02c0*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x000fe2000c101904 */
/*02d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*02e0*/ BRA 0x2e0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0300*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0310*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0320*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
// filename: eeTanh.cu
// a simple CUDA kernel to square the elements of a matrix
extern "C" // ensure function name to be exactly "eeTanh"
{
}
__global__ void cauchyLogErrDeriv(int N, int M, float *A, float *Y, float *out)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
int j = blockIdx.y * blockDim.y + threadIdx.y;
int index = j*N + i;
int L = N*M;
if (i < N && j < M)
{
float a = __expf(A[index+L]);
if (A[index] > Y[index])
{
out[index] = a;
}
else if (A[index] < Y[index])
{
out[index] = -a;
}
else
{
out[index] = 0.0;
}
out[index+L] = __fmaf_rn(a, fabsf(__fsub_rn(A[index], Y[index])), -1.0);
// A2 in this case is stored in the doubled rows of A, the length of A is
// doublt that of Y, out is the same length as A and will store both parts of the derivative
}
} | .file "tmpxft_00090437_00000000-6_cauchyLogErrDeriv.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z43__device_stub__Z17cauchyLogErrDeriviiPfS_S_iiPfS_S_
.type _Z43__device_stub__Z17cauchyLogErrDeriviiPfS_S_iiPfS_S_, @function
_Z43__device_stub__Z17cauchyLogErrDeriviiPfS_S_iiPfS_S_:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movl %esi, 24(%rsp)
movq %rdx, 16(%rsp)
movq %rcx, 8(%rsp)
movq %r8, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z17cauchyLogErrDeriviiPfS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z43__device_stub__Z17cauchyLogErrDeriviiPfS_S_iiPfS_S_, .-_Z43__device_stub__Z17cauchyLogErrDeriviiPfS_S_iiPfS_S_
.globl _Z17cauchyLogErrDeriviiPfS_S_
.type _Z17cauchyLogErrDeriviiPfS_S_, @function
_Z17cauchyLogErrDeriviiPfS_S_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z43__device_stub__Z17cauchyLogErrDeriviiPfS_S_iiPfS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z17cauchyLogErrDeriviiPfS_S_, .-_Z17cauchyLogErrDeriviiPfS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z17cauchyLogErrDeriviiPfS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z17cauchyLogErrDeriviiPfS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
// filename: eeTanh.cu
// a simple CUDA kernel to square the elements of a matrix
extern "C" // ensure function name to be exactly "eeTanh"
{
}
__global__ void cauchyLogErrDeriv(int N, int M, float *A, float *Y, float *out)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
int j = blockIdx.y * blockDim.y + threadIdx.y;
int index = j*N + i;
int L = N*M;
if (i < N && j < M)
{
float a = __expf(A[index+L]);
if (A[index] > Y[index])
{
out[index] = a;
}
else if (A[index] < Y[index])
{
out[index] = -a;
}
else
{
out[index] = 0.0;
}
out[index+L] = __fmaf_rn(a, fabsf(__fsub_rn(A[index], Y[index])), -1.0);
// A2 in this case is stored in the doubled rows of A, the length of A is
// doublt that of Y, out is the same length as A and will store both parts of the derivative
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
// filename: eeTanh.cu
// a simple CUDA kernel to square the elements of a matrix
extern "C" // ensure function name to be exactly "eeTanh"
{
}
__global__ void cauchyLogErrDeriv(int N, int M, float *A, float *Y, float *out)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
int j = blockIdx.y * blockDim.y + threadIdx.y;
int index = j*N + i;
int L = N*M;
if (i < N && j < M)
{
float a = __expf(A[index+L]);
if (A[index] > Y[index])
{
out[index] = a;
}
else if (A[index] < Y[index])
{
out[index] = -a;
}
else
{
out[index] = 0.0;
}
out[index+L] = __fmaf_rn(a, fabsf(__fsub_rn(A[index], Y[index])), -1.0);
// A2 in this case is stored in the doubled rows of A, the length of A is
// doublt that of Y, out is the same length as A and will store both parts of the derivative
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
// filename: eeTanh.cu
// a simple CUDA kernel to square the elements of a matrix
extern "C" // ensure function name to be exactly "eeTanh"
{
}
__global__ void cauchyLogErrDeriv(int N, int M, float *A, float *Y, float *out)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
int j = blockIdx.y * blockDim.y + threadIdx.y;
int index = j*N + i;
int L = N*M;
if (i < N && j < M)
{
float a = __expf(A[index+L]);
if (A[index] > Y[index])
{
out[index] = a;
}
else if (A[index] < Y[index])
{
out[index] = -a;
}
else
{
out[index] = 0.0;
}
out[index+L] = __fmaf_rn(a, fabsf(__fsub_rn(A[index], Y[index])), -1.0);
// A2 in this case is stored in the doubled rows of A, the length of A is
// doublt that of Y, out is the same length as A and will store both parts of the derivative
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z17cauchyLogErrDeriviiPfS_S_
.globl _Z17cauchyLogErrDeriviiPfS_S_
.p2align 8
.type _Z17cauchyLogErrDeriviiPfS_S_,@function
_Z17cauchyLogErrDeriviiPfS_S_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b64 s[4:5], s[0:1], 0x0
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_lshr_b32 s2, s2, 16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[0:1], null, s14, s3, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s2, v[3:4]
v_cmp_gt_i32_e32 vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i32_e64 s2, s5, v1
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_6
v_mad_u64_u32 v[2:3], null, v1, s4, v[0:1]
s_load_b128 s[8:11], s[0:1], 0x8
s_mov_b32 s2, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[0:1], null, s5, s4, v[2:3]
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[4:5], 2, v[2:3]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v6, vcc_lo, s8, v0
v_add_co_ci_u32_e32 v7, vcc_lo, s9, v1, vcc_lo
v_add_co_u32 v2, vcc_lo, s8, v4
v_add_co_ci_u32_e32 v3, vcc_lo, s9, v5, vcc_lo
global_load_b32 v8, v[6:7], off
v_add_co_u32 v6, vcc_lo, s10, v4
v_add_co_ci_u32_e32 v7, vcc_lo, s11, v5, vcc_lo
global_load_b32 v10, v[2:3], off
global_load_b32 v11, v[6:7], off
s_waitcnt vmcnt(2)
v_mul_f32_e32 v8, 0x3fb8aa3b, v8
s_delay_alu instid0(VALU_DEP_1)
v_exp_f32_e32 v8, v8
s_waitcnt_depctr 0xfff
v_mov_b32_e32 v9, v8
s_waitcnt vmcnt(0)
v_cmpx_ngt_f32_e32 v10, v11
s_cbranch_execz .LBB0_5
v_mov_b32_e32 v9, 0
s_mov_b32 s3, exec_lo
v_cmpx_lt_f32_e32 v10, v11
v_xor_b32_e32 v9, 0x80000000, v8
s_or_b32 exec_lo, exec_lo, s3
.LBB0_5:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s2
s_load_b64 s[0:1], s[0:1], 0x18
s_waitcnt lgkmcnt(0)
v_add_co_u32 v4, vcc_lo, s0, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v5, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[4:5], v9, off
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[6:7], off
s_waitcnt vmcnt(0)
v_sub_f32_e32 v2, v2, v3
s_delay_alu instid0(VALU_DEP_1)
v_fma_f32 v2, v8, |v2|, -1.0
global_store_b32 v[0:1], v2, off
.LBB0_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z17cauchyLogErrDeriviiPfS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 12
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z17cauchyLogErrDeriviiPfS_S_, .Lfunc_end0-_Z17cauchyLogErrDeriviiPfS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z17cauchyLogErrDeriviiPfS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z17cauchyLogErrDeriviiPfS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 12
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
// filename: eeTanh.cu
// a simple CUDA kernel to square the elements of a matrix
extern "C" // ensure function name to be exactly "eeTanh"
{
}
__global__ void cauchyLogErrDeriv(int N, int M, float *A, float *Y, float *out)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
int j = blockIdx.y * blockDim.y + threadIdx.y;
int index = j*N + i;
int L = N*M;
if (i < N && j < M)
{
float a = __expf(A[index+L]);
if (A[index] > Y[index])
{
out[index] = a;
}
else if (A[index] < Y[index])
{
out[index] = -a;
}
else
{
out[index] = 0.0;
}
out[index+L] = __fmaf_rn(a, fabsf(__fsub_rn(A[index], Y[index])), -1.0);
// A2 in this case is stored in the doubled rows of A, the length of A is
// doublt that of Y, out is the same length as A and will store both parts of the derivative
}
} | .text
.file "cauchyLogErrDeriv.hip"
.globl _Z32__device_stub__cauchyLogErrDeriviiPfS_S_ # -- Begin function _Z32__device_stub__cauchyLogErrDeriviiPfS_S_
.p2align 4, 0x90
.type _Z32__device_stub__cauchyLogErrDeriviiPfS_S_,@function
_Z32__device_stub__cauchyLogErrDeriviiPfS_S_: # @_Z32__device_stub__cauchyLogErrDeriviiPfS_S_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 4(%rsp)
movl %esi, (%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
leaq 4(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
leaq 72(%rsp), %rax
movq %rax, 96(%rsp)
leaq 64(%rsp), %rax
movq %rax, 104(%rsp)
leaq 56(%rsp), %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z17cauchyLogErrDeriviiPfS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z32__device_stub__cauchyLogErrDeriviiPfS_S_, .Lfunc_end0-_Z32__device_stub__cauchyLogErrDeriviiPfS_S_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z17cauchyLogErrDeriviiPfS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z17cauchyLogErrDeriviiPfS_S_,@object # @_Z17cauchyLogErrDeriviiPfS_S_
.section .rodata,"a",@progbits
.globl _Z17cauchyLogErrDeriviiPfS_S_
.p2align 3, 0x0
_Z17cauchyLogErrDeriviiPfS_S_:
.quad _Z32__device_stub__cauchyLogErrDeriviiPfS_S_
.size _Z17cauchyLogErrDeriviiPfS_S_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z17cauchyLogErrDeriviiPfS_S_"
.size .L__unnamed_1, 30
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z32__device_stub__cauchyLogErrDeriviiPfS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z17cauchyLogErrDeriviiPfS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z17cauchyLogErrDeriviiPfS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e280000002600 */
/*0020*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e280000002200 */
/*0030*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e680000002500 */
/*0040*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0050*/ IMAD R3, R3, c[0x0][0x4], R2 ; /* 0x0000010003037a24 */
/* 0x001fca00078e0202 */
/*0060*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x164], PT ; /* 0x0000590003007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R0, R0, c[0x0][0x0], R5 ; /* 0x0000000000007a24 */
/* 0x002fca00078e0205 */
/*0080*/ ISETP.GE.OR P0, PT, R0, c[0x0][0x160], P0 ; /* 0x0000580000007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ MOV R11, c[0x0][0x164] ; /* 0x00005900000b7a02 */
/* 0x000fe20000000f00 */
/*00b0*/ IMAD R0, R3, c[0x0][0x160], R0 ; /* 0x0000580003007a24 */
/* 0x000fe200078e0200 */
/*00c0*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*00d0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*00e0*/ IMAD R11, R11, c[0x0][0x160], RZ ; /* 0x000058000b0b7a24 */
/* 0x000fca00078e02ff */
/*00f0*/ IADD3 R2, R11, R0, RZ ; /* 0x000000000b027210 */
/* 0x000fca0007ffe0ff */
/*0100*/ IMAD.WIDE R2, R2, R5, c[0x0][0x168] ; /* 0x00005a0002027625 */
/* 0x000fcc00078e0205 */
/*0110*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*0120*/ IMAD.WIDE R6, R0, R5, c[0x0][0x170] ; /* 0x00005c0000067625 */
/* 0x000fc800078e0205 */
/*0130*/ IMAD.WIDE R4, R0.reuse, R5, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x040fe200078e0205 */
/*0140*/ LDG.E R13, [R6.64] ; /* 0x00000004060d7981 */
/* 0x000ee8000c1e1900 */
/*0150*/ LDG.E R14, [R4.64] ; /* 0x00000004040e7981 */
/* 0x000ee2000c1e1900 */
/*0160*/ SHF.R.S32.HI R9, RZ, 0x1f, R0 ; /* 0x0000001fff097819 */
/* 0x000fe20000011400 */
/*0170*/ BSSY B0, 0x260 ; /* 0x000000e000007945 */
/* 0x000fe20003800000 */
/*0180*/ LEA R8, P2, R0, c[0x0][0x178], 0x2 ; /* 0x00005e0000087a11 */
/* 0x000fc800078410ff */
/*0190*/ LEA.HI.X R9, R0, c[0x0][0x17c], R9, 0x2, P2 ; /* 0x00005f0000097a11 */
/* 0x000fe200010f1409 */
/*01a0*/ FMUL R10, R2, 1.4426950216293334961 ; /* 0x3fb8aa3b020a7820 */
/* 0x004fca0000400000 */
/*01b0*/ FSETP.GEU.AND P0, PT, R10, -126, PT ; /* 0xc2fc00000a00780b */
/* 0x000fe40003f0e000 */
/*01c0*/ FSETP.GT.AND P1, PT, R14, R13, PT ; /* 0x0000000d0e00720b */
/* 0x008fd60003f24000 */
/*01d0*/ @!P0 FMUL R10, R10, 0.5 ; /* 0x3f0000000a0a8820 */
/* 0x000fc80000400000 */
/*01e0*/ MUFU.EX2 R12, R10 ; /* 0x0000000a000c7308 */
/* 0x000e240000000800 */
/*01f0*/ @!P0 FMUL R12, R12, R12 ; /* 0x0000000c0c0c8220 */
/* 0x001fca0000400000 */
/*0200*/ MOV R15, R12 ; /* 0x0000000c000f7202 */
/* 0x000fe20000000f00 */
/*0210*/ @P1 BRA 0x250 ; /* 0x0000003000001947 */
/* 0x000fea0003800000 */
/*0220*/ FSETP.GEU.AND P0, PT, R14, R13, PT ; /* 0x0000000d0e00720b */
/* 0x000fe40003f0e000 */
/*0230*/ MOV R15, RZ ; /* 0x000000ff000f7202 */
/* 0x000fd60000000f00 */
/*0240*/ @!P0 FADD R15, -R12, -RZ ; /* 0x800000ff0c0f8221 */
/* 0x000fe40000000100 */
/*0250*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0260*/ STG.E [R8.64], R15 ; /* 0x0000000f08007986 */
/* 0x000fe8000c101904 */
/*0270*/ LDG.E R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000ea8000c1e1900 */
/*0280*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*0290*/ IMAD.WIDE R2, R11, 0x4, R8 ; /* 0x000000040b027825 */
/* 0x000fc800078e0208 */
/*02a0*/ FADD R13, -R6, R5 ; /* 0x00000005060d7221 */
/* 0x004fc80000000100 */
/*02b0*/ FFMA R13, R12, |R13|, -1 ; /* 0xbf8000000c0d7423 */
/* 0x000fca000000040d */
/*02c0*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x000fe2000c101904 */
/*02d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*02e0*/ BRA 0x2e0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0300*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0310*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0320*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z17cauchyLogErrDeriviiPfS_S_
.globl _Z17cauchyLogErrDeriviiPfS_S_
.p2align 8
.type _Z17cauchyLogErrDeriviiPfS_S_,@function
_Z17cauchyLogErrDeriviiPfS_S_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b64 s[4:5], s[0:1], 0x0
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_lshr_b32 s2, s2, 16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[0:1], null, s14, s3, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s2, v[3:4]
v_cmp_gt_i32_e32 vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i32_e64 s2, s5, v1
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_6
v_mad_u64_u32 v[2:3], null, v1, s4, v[0:1]
s_load_b128 s[8:11], s[0:1], 0x8
s_mov_b32 s2, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[0:1], null, s5, s4, v[2:3]
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[4:5], 2, v[2:3]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v6, vcc_lo, s8, v0
v_add_co_ci_u32_e32 v7, vcc_lo, s9, v1, vcc_lo
v_add_co_u32 v2, vcc_lo, s8, v4
v_add_co_ci_u32_e32 v3, vcc_lo, s9, v5, vcc_lo
global_load_b32 v8, v[6:7], off
v_add_co_u32 v6, vcc_lo, s10, v4
v_add_co_ci_u32_e32 v7, vcc_lo, s11, v5, vcc_lo
global_load_b32 v10, v[2:3], off
global_load_b32 v11, v[6:7], off
s_waitcnt vmcnt(2)
v_mul_f32_e32 v8, 0x3fb8aa3b, v8
s_delay_alu instid0(VALU_DEP_1)
v_exp_f32_e32 v8, v8
s_waitcnt_depctr 0xfff
v_mov_b32_e32 v9, v8
s_waitcnt vmcnt(0)
v_cmpx_ngt_f32_e32 v10, v11
s_cbranch_execz .LBB0_5
v_mov_b32_e32 v9, 0
s_mov_b32 s3, exec_lo
v_cmpx_lt_f32_e32 v10, v11
v_xor_b32_e32 v9, 0x80000000, v8
s_or_b32 exec_lo, exec_lo, s3
.LBB0_5:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s2
s_load_b64 s[0:1], s[0:1], 0x18
s_waitcnt lgkmcnt(0)
v_add_co_u32 v4, vcc_lo, s0, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v5, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[4:5], v9, off
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[6:7], off
s_waitcnt vmcnt(0)
v_sub_f32_e32 v2, v2, v3
s_delay_alu instid0(VALU_DEP_1)
v_fma_f32 v2, v8, |v2|, -1.0
global_store_b32 v[0:1], v2, off
.LBB0_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z17cauchyLogErrDeriviiPfS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 12
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z17cauchyLogErrDeriviiPfS_S_, .Lfunc_end0-_Z17cauchyLogErrDeriviiPfS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z17cauchyLogErrDeriviiPfS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z17cauchyLogErrDeriviiPfS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 12
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00090437_00000000-6_cauchyLogErrDeriv.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z43__device_stub__Z17cauchyLogErrDeriviiPfS_S_iiPfS_S_
.type _Z43__device_stub__Z17cauchyLogErrDeriviiPfS_S_iiPfS_S_, @function
_Z43__device_stub__Z17cauchyLogErrDeriviiPfS_S_iiPfS_S_:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movl %esi, 24(%rsp)
movq %rdx, 16(%rsp)
movq %rcx, 8(%rsp)
movq %r8, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z17cauchyLogErrDeriviiPfS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z43__device_stub__Z17cauchyLogErrDeriviiPfS_S_iiPfS_S_, .-_Z43__device_stub__Z17cauchyLogErrDeriviiPfS_S_iiPfS_S_
.globl _Z17cauchyLogErrDeriviiPfS_S_
.type _Z17cauchyLogErrDeriviiPfS_S_, @function
_Z17cauchyLogErrDeriviiPfS_S_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z43__device_stub__Z17cauchyLogErrDeriviiPfS_S_iiPfS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z17cauchyLogErrDeriviiPfS_S_, .-_Z17cauchyLogErrDeriviiPfS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z17cauchyLogErrDeriviiPfS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z17cauchyLogErrDeriviiPfS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "cauchyLogErrDeriv.hip"
.globl _Z32__device_stub__cauchyLogErrDeriviiPfS_S_ # -- Begin function _Z32__device_stub__cauchyLogErrDeriviiPfS_S_
.p2align 4, 0x90
.type _Z32__device_stub__cauchyLogErrDeriviiPfS_S_,@function
_Z32__device_stub__cauchyLogErrDeriviiPfS_S_: # @_Z32__device_stub__cauchyLogErrDeriviiPfS_S_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 4(%rsp)
movl %esi, (%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
leaq 4(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
leaq 72(%rsp), %rax
movq %rax, 96(%rsp)
leaq 64(%rsp), %rax
movq %rax, 104(%rsp)
leaq 56(%rsp), %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z17cauchyLogErrDeriviiPfS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z32__device_stub__cauchyLogErrDeriviiPfS_S_, .Lfunc_end0-_Z32__device_stub__cauchyLogErrDeriviiPfS_S_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z17cauchyLogErrDeriviiPfS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z17cauchyLogErrDeriviiPfS_S_,@object # @_Z17cauchyLogErrDeriviiPfS_S_
.section .rodata,"a",@progbits
.globl _Z17cauchyLogErrDeriviiPfS_S_
.p2align 3, 0x0
_Z17cauchyLogErrDeriviiPfS_S_:
.quad _Z32__device_stub__cauchyLogErrDeriviiPfS_S_
.size _Z17cauchyLogErrDeriviiPfS_S_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z17cauchyLogErrDeriviiPfS_S_"
.size .L__unnamed_1, 30
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z32__device_stub__cauchyLogErrDeriviiPfS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z17cauchyLogErrDeriviiPfS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
/**
* Programma che simula il comportamento del gpdt per
* la risoluzione di un kernel di una serie di
* valori di dimensione variabile utilizzando la
* tecnologia cuda.
* compilare con:
* nvcc -o simil_gpdt_si_cuda simil_gpdt_si_cuda.cu
* lanciare con:
* ./simil_gpdt_si_cuda [numero vettori] [numero componenti] [numero di righe da calcolare] [tipo di kernel] [grado(int)/sigma(float)]
**/
using namespace std;
/**
* Funzione che riempie i vettori con numeri
* casuali compresi tra 0 e 99.
**/
__global__ void Kernel_norme(float *Vd, float *Nd, int *Vp, int *Vnp, int N, int C, int nr_max_val)
{
long int x = threadIdx.x + blockIdx.x * blockDim.x;
int pos;
if(x < N)
{
float norma = 0;
int Nr_val = Vnp[x];
for(int i = 0; i < Nr_val; i++)
{
pos = Vp[x * nr_max_val + i];
norma = norma + (Vd[x * C + pos] * Vd[x * C + pos]);
}
Nd[x] = norma;
}
} | code for sm_80
Function : _Z12Kernel_normePfS_PiS0_iii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ ULDC UR4, c[0x0][0x180] ; /* 0x0000600000047ab9 */
/* 0x000fe40000000800 */
/*0030*/ USHF.R.S32.HI UR4, URZ, 0x1f, UR4 ; /* 0x0000001f3f047899 */
/* 0x000fe20008011404 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0060*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x180], PT ; /* 0x0000600000007a0c */
/* 0x000fc80003f06070 */
/*0070*/ ISETP.GE.AND.EX P0, PT, RZ, UR4, PT, P0 ; /* 0x00000004ff007c0c */
/* 0x000fda000bf06300 */
/*0080*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0090*/ IMAD.SHL.U32 R2, R0, 0x4, RZ ; /* 0x0000000400027824 */
/* 0x000fe200078e00ff */
/*00a0*/ SHF.R.U32.HI R3, RZ, 0x1e, R0 ; /* 0x0000001eff037819 */
/* 0x000fe20000011600 */
/*00b0*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fc60000000a00 */
/*00c0*/ IADD3 R4, P0, R2, c[0x0][0x178], RZ ; /* 0x00005e0002047a10 */
/* 0x000fc80007f1e0ff */
/*00d0*/ IADD3.X R5, R3, c[0x0][0x17c], RZ, P0, !PT ; /* 0x00005f0003057a10 */
/* 0x000fca00007fe4ff */
/*00e0*/ LDG.E R8, [R4.64] ; /* 0x0000000604087981 */
/* 0x000ea2000c1e1900 */
/*00f0*/ BSSY B2, 0x1290 ; /* 0x0000119000027945 */
/* 0x000fe20003800000 */
/*0100*/ IMAD.MOV.U32 R9, RZ, RZ, RZ ; /* 0x000000ffff097224 */
/* 0x000fe200078e00ff */
/*0110*/ ISETP.GE.AND P0, PT, R8, 0x1, PT ; /* 0x000000010800780c */
/* 0x004fda0003f06270 */
/*0120*/ @!P0 BRA 0x1280 ; /* 0x0000115000008947 */
/* 0x000fea0003800000 */
/*0130*/ IADD3 R4, R8, -0x1, RZ ; /* 0xffffffff08047810 */
/* 0x000fe20007ffe0ff */
/*0140*/ ULDC UR4, c[0x0][0x184] ; /* 0x0000610000047ab9 */
/* 0x000fe20000000800 */
/*0150*/ IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x188] ; /* 0x00006200ff077624 */
/* 0x000fe200078e00ff */
/*0160*/ USHF.R.S32.HI UR4, URZ, 0x1f, UR4 ; /* 0x0000001f3f047899 */
/* 0x000fe20008011404 */
/*0170*/ ISETP.GE.U32.AND P0, PT, R4, 0x3, PT ; /* 0x000000030400780c */
/* 0x000fe20003f06070 */
/*0180*/ IMAD.WIDE.U32 R12, R0, c[0x0][0x184], RZ ; /* 0x00006100000c7a25 */
/* 0x000fe200078e00ff */
/*0190*/ BSSY B1, 0x1120 ; /* 0x00000f8000017945 */
/* 0x000fe20003800000 */
/*01a0*/ LOP3.LUT R5, R8, 0x3, RZ, 0xc0, !PT ; /* 0x0000000308057812 */
/* 0x000fe400078ec0ff */
/*01b0*/ IMAD R11, R0, UR4, RZ ; /* 0x00000004000b7c24 */
/* 0x000fe2000f8e02ff */
/*01c0*/ SHF.R.S32.HI R7, RZ, 0x1f, R7 ; /* 0x0000001fff077819 */
/* 0x000fe20000011407 */
/*01d0*/ IMAD.MOV.U32 R9, RZ, RZ, RZ ; /* 0x000000ffff097224 */
/* 0x000fc400078e00ff */
/*01e0*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x000fe400078e00ff */
/*01f0*/ IMAD.IADD R6, R13, 0x1, R11 ; /* 0x000000010d067824 */
/* 0x000fe400078e020b */
/*0200*/ @!P0 BRA 0x1110 ; /* 0x00000f0000008947 */
/* 0x000fea0003800000 */
/*0210*/ IMAD R9, R7, R0, RZ ; /* 0x0000000007097224 */
/* 0x000fe200078e02ff */
/*0220*/ BSSY B0, 0xef0 ; /* 0x00000cc000007945 */
/* 0x000fe20003800000 */
/*0230*/ IMAD.WIDE.U32 R10, R0, c[0x0][0x188], RZ ; /* 0x00006200000a7a25 */
/* 0x000fc800078e00ff */
/*0240*/ IMAD.IADD R9, R11, 0x1, R9 ; /* 0x000000010b097824 */
/* 0x000fe200078e0209 */
/*0250*/ LEA R14, P0, R10, c[0x0][0x170], 0x2 ; /* 0x00005c000a0e7a11 */
/* 0x000fe200078010ff */
/*0260*/ IMAD.IADD R8, R8, 0x1, -R5 ; /* 0x0000000108087824 */
/* 0x000fe400078e0a05 */
/*0270*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x000fe200078e00ff */
/*0280*/ LEA.HI.X R10, R10, c[0x0][0x174], R9, 0x2, P0 ; /* 0x00005d000a0a7a11 */
/* 0x000fe200000f1409 */
/*0290*/ IMAD.MOV.U32 R9, RZ, RZ, RZ ; /* 0x000000ffff097224 */
/* 0x000fe200078e00ff */
/*02a0*/ ISETP.GT.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fe40003f04270 */
/*02b0*/ IADD3 R14, P1, R14, 0x8, RZ ; /* 0x000000080e0e7810 */
/* 0x000fca0007f3e0ff */
/*02c0*/ IMAD.X R15, RZ, RZ, R10, P1 ; /* 0x000000ffff0f7224 */
/* 0x000fcc00008e060a */
/*02d0*/ @!P0 BRA 0xee0 ; /* 0x00000c0000008947 */
/* 0x000fea0003800000 */
/*02e0*/ ISETP.GT.AND P1, PT, R8, 0xc, PT ; /* 0x0000000c0800780c */
/* 0x000fe20003f24270 */
/*02f0*/ BSSY B3, 0xaa0 ; /* 0x000007a000037945 */
/* 0x000fe20003800000 */
/*0300*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*0310*/ @!P1 BRA 0xa90 ; /* 0x0000077000009947 */
/* 0x000fea0003800000 */
/*0320*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0330*/ LDG.E R17, [R14.64+-0x8] ; /* 0xfffff8060e117981 */
/* 0x000ea8000c1e1900 */
/*0340*/ LDG.E R23, [R14.64+-0x4] ; /* 0xfffffc060e177981 */
/* 0x000ee8000c1e1900 */
/*0350*/ LDG.E R21, [R14.64] ; /* 0x000000060e157981 */
/* 0x000f28000c1e1900 */
/*0360*/ LDG.E R11, [R14.64+0x4] ; /* 0x000004060e0b7981 */
/* 0x000f68000c1e1900 */
/*0370*/ LDG.E R19, [R14.64+0x8] ; /* 0x000008060e137981 */
/* 0x000f28000c1e1900 */
/*0380*/ LDG.E R28, [R14.64+0x1c] ; /* 0x00001c060e1c7981 */
/* 0x000f28000c1e1900 */
/*0390*/ LDG.E R29, [R14.64+0x2c] ; /* 0x00002c060e1d7981 */
/* 0x000f22000c1e1900 */
/*03a0*/ IADD3 R16, P1, R17, R12, RZ ; /* 0x0000000c11107210 */
/* 0x004fc80007f3e0ff */
/*03b0*/ LEA.HI.X.SX32 R17, R17, R6, 0x1, P1 ; /* 0x0000000611117211 */
/* 0x000fe400008f0eff */
/*03c0*/ LEA R26, P1, R16.reuse, c[0x0][0x160], 0x2 ; /* 0x00005800101a7a11 */
/* 0x040fe400078210ff */
/*03d0*/ IADD3 R10, P2, R23.reuse, R12, RZ ; /* 0x0000000c170a7210 */
/* 0x048fe40007f5e0ff */
/*03e0*/ LEA.HI.X R27, R16, c[0x0][0x164], R17, 0x2, P1 ; /* 0x00005900101b7a11 */
/* 0x000fe400008f1411 */
/*03f0*/ LEA.HI.X.SX32 R23, R23, R6, 0x1, P2 ; /* 0x0000000617177211 */
/* 0x000fe400010f0eff */
/*0400*/ LEA R16, P1, R10.reuse, c[0x0][0x160], 0x2 ; /* 0x000058000a107a11 */
/* 0x040fe200078210ff */
/*0410*/ LDG.E R26, [R26.64] ; /* 0x000000061a1a7981 */
/* 0x0000a6000c1e1900 */
/*0420*/ LEA.HI.X R17, R10, c[0x0][0x164], R23, 0x2, P1 ; /* 0x000059000a117a11 */
/* 0x000fca00008f1417 */
/*0430*/ LDG.E R23, [R16.64] ; /* 0x0000000610177981 */
/* 0x0002e2000c1e1900 */
/*0440*/ IADD3 R24, P1, R21, R12.reuse, RZ ; /* 0x0000000c15187210 */
/* 0x090fe40007f3e0ff */
/*0450*/ IADD3 R22, P2, R11, R12, RZ ; /* 0x0000000c0b167210 */
/* 0x020fe20007f5e0ff */
/*0460*/ LDG.E R27, [R14.64+0xc] ; /* 0x00000c060e1b7981 */
/* 0x001f22000c1e1900 */
/*0470*/ LEA.HI.X.SX32 R25, R21, R6.reuse, 0x1, P1 ; /* 0x0000000615197211 */
/* 0x080fe400008f0eff */
/*0480*/ LEA R10, P1, R24, c[0x0][0x160], 0x2 ; /* 0x00005800180a7a11 */
/* 0x000fe400078210ff */
/*0490*/ LEA.HI.X.SX32 R21, R11, R6, 0x1, P2 ; /* 0x000000060b157211 */
/* 0x000fe200010f0eff */
/*04a0*/ LDG.E R16, [R14.64+0x14] ; /* 0x000014060e107981 */
/* 0x002f62000c1e1900 */
/*04b0*/ LEA R20, P2, R22, c[0x0][0x160], 0x2 ; /* 0x0000580016147a11 */
/* 0x000fc400078410ff */
/*04c0*/ IADD3 R18, P3, R19.reuse, R12, RZ ; /* 0x0000000c13127210 */
/* 0x040fe20007f7e0ff */
/*04d0*/ LDG.E R17, [R14.64+0x18] ; /* 0x000018060e117981 */
/* 0x000f62000c1e1900 */
/*04e0*/ LEA.HI.X R11, R24, c[0x0][0x164], R25, 0x2, P1 ; /* 0x00005900180b7a11 */
/* 0x000fe400008f1419 */
/*04f0*/ LEA.HI.X R21, R22, c[0x0][0x164], R21, 0x2, P2 ; /* 0x0000590016157a11 */
/* 0x000fe400010f1415 */
/*0500*/ LEA.HI.X.SX32 R19, R19, R6, 0x1, P3 ; /* 0x0000000613137211 */
/* 0x000fe200018f0eff */
/*0510*/ LDG.E R10, [R10.64] ; /* 0x000000060a0a7981 */
/* 0x000962000c1e1900 */
/*0520*/ LEA R24, P1, R18, c[0x0][0x160], 0x2 ; /* 0x0000580012187a11 */
/* 0x000fc600078210ff */
/*0530*/ LDG.E R20, [R20.64] ; /* 0x0000000614147981 */
/* 0x000162000c1e1900 */
/*0540*/ LEA.HI.X R25, R18, c[0x0][0x164], R19, 0x2, P1 ; /* 0x0000590012197a11 */
/* 0x000fc600008f1413 */
/*0550*/ LDG.E R22, [R14.64+0x20] ; /* 0x000020060e167981 */
/* 0x000f68000c1e1900 */
/*0560*/ LDG.E R24, [R24.64] ; /* 0x0000000618187981 */
/* 0x000f68000c1e1900 */
/*0570*/ LDG.E R21, [R14.64+0x10] ; /* 0x000010060e157981 */
/* 0x001f68000c1e1900 */
/*0580*/ LDG.E R18, [R14.64+0x24] ; /* 0x000024060e127981 */
/* 0x000f68000c1e1900 */
/*0590*/ LDG.E R19, [R14.64+0x28] ; /* 0x000028060e137981 */
/* 0x000f62000c1e1900 */
/*05a0*/ FFMA R26, R26, R26, R9 ; /* 0x0000001a1a1a7223 */
/* 0x004fc80000000009 */
/*05b0*/ FFMA R9, R23, R23, R26 ; /* 0x0000001717097223 */
/* 0x008fe4000000001a */
/*05c0*/ LDG.E R23, [R14.64+0x30] ; /* 0x000030060e177981 */
/* 0x000ea2000c1e1900 */
/*05d0*/ IADD3 R11, P1, R27, R12, RZ ; /* 0x0000000c1b0b7210 */
/* 0x010fe20007f3e0ff */
/*05e0*/ FFMA R9, R10, R10, R9 ; /* 0x0000000a0a097223 */
/* 0x020fc80000000009 */
/*05f0*/ FFMA R9, R20, R20, R9 ; /* 0x0000001414097223 */
/* 0x000fc80000000009 */
/*0600*/ FFMA R9, R24, R24, R9 ; /* 0x0000001818097223 */
/* 0x000fe20000000009 */
/*0610*/ LEA.HI.X.SX32 R24, R27, R6, 0x1, P1 ; /* 0x000000061b187211 */
/* 0x000fe400008f0eff */
/*0620*/ LEA R10, P1, R11, c[0x0][0x160], 0x2 ; /* 0x000058000b0a7a11 */
/* 0x000fe400078210ff */
/*0630*/ IADD3 R20, P2, R21, R12, RZ ; /* 0x0000000c15147210 */
/* 0x000fe40007f5e0ff */
/*0640*/ LEA.HI.X R11, R11, c[0x0][0x164], R24, 0x2, P1 ; /* 0x000059000b0b7a11 */
/* 0x000fe400008f1418 */
/*0650*/ LEA.HI.X.SX32 R21, R21, R6, 0x1, P2 ; /* 0x0000000615157211 */
/* 0x000fe400010f0eff */
/*0660*/ LEA R26, P1, R20.reuse, c[0x0][0x160], 0x2 ; /* 0x00005800141a7a11 */
/* 0x040fe200078210ff */
/*0670*/ LDG.E R10, [R10.64] ; /* 0x000000060a0a7981 */
/* 0x0000e6000c1e1900 */
/*0680*/ LEA.HI.X R27, R20, c[0x0][0x164], R21, 0x2, P1 ; /* 0x00005900141b7a11 */
/* 0x000fc400008f1415 */
/*0690*/ IADD3 R21, P1, R16.reuse, R12.reuse, RZ ; /* 0x0000000c10157210 */
/* 0x0c0fe40007f3e0ff */
/*06a0*/ IADD3 R24, P2, R17, R12, RZ ; /* 0x0000000c11187210 */
/* 0x000fe20007f5e0ff */
/*06b0*/ LDG.E R25, [R26.64] ; /* 0x000000061a197981 */
/* 0x000322000c1e1900 */
/*06c0*/ LEA.HI.X.SX32 R16, R16, R6.reuse, 0x1, P1 ; /* 0x0000000610107211 */
/* 0x080fe400008f0eff */
/*06d0*/ LEA R20, P1, R21, c[0x0][0x160], 0x2 ; /* 0x0000580015147a11 */
/* 0x000fe400078210ff */
/*06e0*/ LEA.HI.X.SX32 R17, R17, R6, 0x1, P2 ; /* 0x0000000611117211 */
/* 0x000fe400010f0eff */
/*06f0*/ LEA.HI.X R21, R21, c[0x0][0x164], R16, 0x2, P1 ; /* 0x0000590015157a11 */
/* 0x000fc400008f1410 */
/*0700*/ LEA R16, P1, R24, c[0x0][0x160], 0x2 ; /* 0x0000580018107a11 */
/* 0x000fc800078210ff */
/*0710*/ LEA.HI.X R17, R24, c[0x0][0x164], R17, 0x2, P1 ; /* 0x0000590018117a11 */
/* 0x000fe400008f1411 */
/*0720*/ LDG.E R24, [R20.64] ; /* 0x0000000614187981 */
/* 0x000ae8000c1e1900 */
/*0730*/ LDG.E R11, [R16.64] ; /* 0x00000006100b7981 */
/* 0x0010e2000c1e1900 */
/*0740*/ IADD3 R20, P1, R28, R12, RZ ; /* 0x0000000c1c147210 */
/* 0x020fc80007f3e0ff */
/*0750*/ LEA.HI.X.SX32 R27, R28, R6, 0x1, P1 ; /* 0x000000061c1b7211 */
/* 0x002fe400008f0eff */
/*0760*/ LEA R26, P1, R20, c[0x0][0x160], 0x2 ; /* 0x00005800141a7a11 */
/* 0x000fe400078210ff */
/*0770*/ IADD3 R28, P2, R22, R12, RZ ; /* 0x0000000c161c7210 */
/* 0x000fe40007f5e0ff */
/*0780*/ LEA.HI.X R27, R20, c[0x0][0x164], R27, 0x2, P1 ; /* 0x00005900141b7a11 */
/* 0x000fe400008f141b */
/*0790*/ LEA.HI.X.SX32 R22, R22, R6, 0x1, P2 ; /* 0x0000000616167211 */
/* 0x000fe400010f0eff */
/*07a0*/ LEA R20, P1, R28.reuse, c[0x0][0x160], 0x2 ; /* 0x000058001c147a11 */
/* 0x040fe200078210ff */
/*07b0*/ LDG.E R26, [R26.64] ; /* 0x000000061a1a7981 */
/* 0x000366000c1e1900 */
/*07c0*/ LEA.HI.X R21, R28, c[0x0][0x164], R22, 0x2, P1 ; /* 0x000059001c157a11 */
/* 0x000fc400008f1416 */
/*07d0*/ IADD3 R22, P1, R18.reuse, R12.reuse, RZ ; /* 0x0000000c12167210 */
/* 0x0c0fe40007f3e0ff */
/*07e0*/ IADD3 R28, P2, R19.reuse, R12, RZ ; /* 0x0000000c131c7210 */
/* 0x040fe40007f5e0ff */
/*07f0*/ LEA.HI.X.SX32 R17, R18, R6.reuse, 0x1, P1 ; /* 0x0000000612117211 */
/* 0x081fe200008f0eff */
/*0800*/ LDG.E R27, [R20.64] ; /* 0x00000006141b7981 */
/* 0x0020e2000c1e1900 */
/*0810*/ LEA R16, P1, R22.reuse, c[0x0][0x160], 0x2 ; /* 0x0000580016107a11 */
/* 0x040fe400078210ff */
/*0820*/ LEA.HI.X.SX32 R19, R19, R6, 0x1, P2 ; /* 0x0000000613137211 */
/* 0x000fe400010f0eff */
/*0830*/ LEA.HI.X R17, R22, c[0x0][0x164], R17, 0x2, P1 ; /* 0x0000590016117a11 */
/* 0x000fc400008f1411 */
/*0840*/ LEA R18, P1, R28, c[0x0][0x160], 0x2 ; /* 0x000058001c127a11 */
/* 0x000fc800078210ff */
/*0850*/ LEA.HI.X R19, R28, c[0x0][0x164], R19, 0x2, P1 ; /* 0x000059001c137a11 */
/* 0x000fe400008f1413 */
/*0860*/ IADD3 R22, P1, R29.reuse, R12, RZ ; /* 0x0000000c1d167210 */
/* 0x040fe20007f3e0ff */
/*0870*/ LDG.E R28, [R16.64] ; /* 0x00000006101c7981 */
/* 0x0002e6000c1e1900 */
/*0880*/ LEA.HI.X.SX32 R21, R29, R6, 0x1, P1 ; /* 0x000000061d157211 */
/* 0x001fe200008f0eff */
/*0890*/ LDG.E R18, [R18.64] ; /* 0x0000000612127981 */
/* 0x000ee2000c1e1900 */
/*08a0*/ LEA R20, P1, R22, c[0x0][0x160], 0x2 ; /* 0x0000580016147a11 */
/* 0x000fc800078210ff */
/*08b0*/ LEA.HI.X R21, R22, c[0x0][0x164], R21, 0x2, P1 ; /* 0x0000590016157a11 */
/* 0x000fca00008f1415 */
/*08c0*/ LDG.E R20, [R20.64] ; /* 0x0000000614147981 */
/* 0x000ee2000c1e1900 */
/*08d0*/ IADD3 R29, P2, R23, R12, RZ ; /* 0x0000000c171d7210 */
/* 0x004fc80007f5e0ff */
/*08e0*/ LEA.HI.X.SX32 R23, R23, R6, 0x1, P2 ; /* 0x0000000617177211 */
/* 0x000fe400010f0eff */
/*08f0*/ LEA R22, P1, R29, c[0x0][0x160], 0x2 ; /* 0x000058001d167a11 */
/* 0x000fc800078210ff */
/*0900*/ LEA.HI.X R23, R29, c[0x0][0x164], R23, 0x2, P1 ; /* 0x000059001d177a11 */
/* 0x000fe400008f1417 */
/*0910*/ LDG.E R29, [R14.64+0x34] ; /* 0x000034060e1d7981 */
/* 0x000e68000c1e1900 */
/*0920*/ LDG.E R22, [R22.64] ; /* 0x0000000616167981 */
/* 0x000ee2000c1e1900 */
/*0930*/ IADD3 R8, R8, -0x10, RZ ; /* 0xfffffff008087810 */
/* 0x000fe40007ffe0ff */
/*0940*/ IADD3 R17, P1, R29, R12, RZ ; /* 0x0000000c1d117210 */
/* 0x002fc80007f3e0ff */
/*0950*/ LEA.HI.X.SX32 R29, R29, R6, 0x1, P1 ; /* 0x000000061d1d7211 */
/* 0x000fe400008f0eff */
/*0960*/ LEA R16, P1, R17, c[0x0][0x160], 0x2 ; /* 0x0000580011107a11 */
/* 0x000fc800078210ff */
/*0970*/ LEA.HI.X R17, R17, c[0x0][0x164], R29, 0x2, P1 ; /* 0x0000590011117a11 */
/* 0x000fca00008f141d */
/*0980*/ LDG.E R16, [R16.64] ; /* 0x0000000610107981 */
/* 0x000ea2000c1e1900 */
/*0990*/ FFMA R10, R10, R10, R9 ; /* 0x0000000a0a0a7223 */
/* 0x008fc80000000009 */
/*09a0*/ FFMA R25, R25, R25, R10 ; /* 0x0000001919197223 */
/* 0x010fc8000000000a */
/*09b0*/ FFMA R24, R24, R24, R25 ; /* 0x0000001818187223 */
/* 0x000fc80000000019 */
/*09c0*/ FFMA R11, R11, R11, R24 ; /* 0x0000000b0b0b7223 */
/* 0x000fc80000000018 */
/*09d0*/ FFMA R26, R26, R26, R11 ; /* 0x0000001a1a1a7223 */
/* 0x020fc8000000000b */
/*09e0*/ FFMA R27, R27, R27, R26 ; /* 0x0000001b1b1b7223 */
/* 0x000fe2000000001a */
/*09f0*/ ISETP.GT.AND P1, PT, R8, 0xc, PT ; /* 0x0000000c0800780c */
/* 0x000fc60003f24270 */
/*0a00*/ FFMA R27, R28, R28, R27 ; /* 0x0000001c1c1b7223 */
/* 0x000fc8000000001b */
/*0a10*/ FFMA R27, R18, R18, R27 ; /* 0x00000012121b7223 */
/* 0x000fe2000000001b */
/*0a20*/ IADD3 R14, P2, R14, 0x40, RZ ; /* 0x000000400e0e7810 */
/* 0x000fc60007f5e0ff */
/*0a30*/ FFMA R27, R20, R20, R27 ; /* 0x00000014141b7223 */
/* 0x000fc8000000001b */
/*0a40*/ FFMA R27, R22, R22, R27 ; /* 0x00000016161b7223 */
/* 0x000fe2000000001b */
/*0a50*/ IADD3 R4, R4, 0x10, RZ ; /* 0x0000001004047810 */
/* 0x000fe20007ffe0ff */
/*0a60*/ IMAD.X R15, RZ, RZ, R15, P2 ; /* 0x000000ffff0f7224 */
/* 0x000fe400010e060f */
/*0a70*/ FFMA R9, R16, R16, R27 ; /* 0x0000001010097223 */
/* 0x004fe2000000001b */
/*0a80*/ @P1 BRA 0x330 ; /* 0xfffff8a000001947 */
/* 0x000fea000383ffff */
/*0a90*/ BSYNC B3 ; /* 0x0000000000037941 */
/* 0x000fea0003800000 */
/*0aa0*/ ISETP.GT.AND P1, PT, R8, 0x4, PT ; /* 0x000000040800780c */
/* 0x000fe20003f24270 */
/*0ab0*/ BSSY B3, 0xeb0 ; /* 0x000003f000037945 */
/* 0x000fd80003800000 */
/*0ac0*/ @!P1 BRA 0xea0 ; /* 0x000003d000009947 */
/* 0x000fea0003800000 */
/*0ad0*/ LDG.E R11, [R14.64+-0x8] ; /* 0xfffff8060e0b7981 */
/* 0x000ea8000c1e1900 */
/*0ae0*/ LDG.E R17, [R14.64+-0x4] ; /* 0xfffffc060e117981 */
/* 0x000ee8000c1e1900 */
/*0af0*/ LDG.E R16, [R14.64] ; /* 0x000000060e107981 */
/* 0x000f28000c1e1900 */
/*0b00*/ LDG.E R21, [R14.64+0x4] ; /* 0x000004060e157981 */
/* 0x000f68000c1e1900 */
/*0b10*/ LDG.E R27, [R14.64+0x8] ; /* 0x000008060e1b7981 */
/* 0x000f28000c1e1900 */
/*0b20*/ LDG.E R29, [R14.64+0xc] ; /* 0x00000c060e1d7981 */
/* 0x000f68000c1e1900 */
/*0b30*/ LDG.E R23, [R14.64+0x10] ; /* 0x000010060e177981 */
/* 0x000f68000c1e1900 */
/*0b40*/ LDG.E R25, [R14.64+0x14] ; /* 0x000014060e197981 */
/* 0x000f62000c1e1900 */
/*0b50*/ IADD3 R18, P0, R11, R12, RZ ; /* 0x0000000c0b127210 */
/* 0x004fc80007f1e0ff */
/*0b60*/ LEA.HI.X.SX32 R11, R11, R6, 0x1, P0 ; /* 0x000000060b0b7211 */
/* 0x000fe400000f0eff */
/*0b70*/ LEA R10, P0, R18.reuse, c[0x0][0x160], 0x2 ; /* 0x00005800120a7a11 */
/* 0x040fe400078010ff */
/*0b80*/ IADD3 R19, P1, R17.reuse, R12, RZ ; /* 0x0000000c11137210 */
/* 0x048fe40007f3e0ff */
/*0b90*/ LEA.HI.X R11, R18, c[0x0][0x164], R11, 0x2, P0 ; /* 0x00005900120b7a11 */
/* 0x000fe400000f140b */
/*0ba0*/ LEA.HI.X.SX32 R20, R17, R6, 0x1, P1 ; /* 0x0000000611147211 */
/* 0x000fe400008f0eff */
/*0bb0*/ LEA R18, P0, R19, c[0x0][0x160], 0x2 ; /* 0x0000580013127a11 */
/* 0x000fe200078010ff */
/*0bc0*/ LDG.E R24, [R10.64] ; /* 0x000000060a187981 */
/* 0x0000a2000c1e1900 */
/*0bd0*/ IADD3 R17, P1, R16, R12, RZ ; /* 0x0000000c10117210 */
/* 0x010fc40007f3e0ff */
/*0be0*/ LEA.HI.X R19, R19, c[0x0][0x164], R20, 0x2, P0 ; /* 0x0000590013137a11 */
/* 0x000fe400000f1414 */
/*0bf0*/ LEA.HI.X.SX32 R20, R16, R6, 0x1, P1 ; /* 0x0000000610147211 */
/* 0x000fe400008f0eff */
/*0c00*/ LEA R16, P0, R17, c[0x0][0x160], 0x2 ; /* 0x0000580011107a11 */
/* 0x000fe200078010ff */
/*0c10*/ LDG.E R26, [R18.64] ; /* 0x00000006121a7981 */
/* 0x0002e2000c1e1900 */
/*0c20*/ IADD3 R22, P1, R21, R12, RZ ; /* 0x0000000c15167210 */
/* 0x020fe40007f3e0ff */
/*0c30*/ LEA.HI.X R17, R17, c[0x0][0x164], R20, 0x2, P0 ; /* 0x0000590011117a11 */
/* 0x000fe400000f1414 */
/*0c40*/ LEA.HI.X.SX32 R21, R21, R6, 0x1, P1 ; /* 0x0000000615157211 */
/* 0x000fc400008f0eff */
/*0c50*/ LEA R20, P0, R22.reuse, c[0x0][0x160], 0x2 ; /* 0x0000580016147a11 */
/* 0x040fe400078010ff */
/*0c60*/ IADD3 R28, P1, R27.reuse, R12, RZ ; /* 0x0000000c1b1c7210 */
/* 0x040fe40007f3e0ff */
/*0c70*/ LEA.HI.X R21, R22, c[0x0][0x164], R21, 0x2, P0 ; /* 0x0000590016157a11 */
/* 0x000fe400000f1415 */
/*0c80*/ LEA.HI.X.SX32 R11, R27, R6, 0x1, P1 ; /* 0x000000061b0b7211 */
/* 0x001fe400008f0eff */
/*0c90*/ LEA R10, P0, R28, c[0x0][0x160], 0x2 ; /* 0x000058001c0a7a11 */
/* 0x000fe200078010ff */
/*0ca0*/ LDG.E R27, [R16.64] ; /* 0x00000006101b7981 */
/* 0x000122000c1e1900 */
/*0cb0*/ IADD3 R22, P1, R29, R12, RZ ; /* 0x0000000c1d167210 */
/* 0x000fc40007f3e0ff */
/*0cc0*/ LEA.HI.X R11, R28, c[0x0][0x164], R11, 0x2, P0 ; /* 0x000059001c0b7a11 */
/* 0x000fe200000f140b */
/*0cd0*/ LDG.E R20, [R20.64] ; /* 0x0000000614147981 */
/* 0x000f62000c1e1900 */
/*0ce0*/ LEA.HI.X.SX32 R29, R29, R6, 0x1, P1 ; /* 0x000000061d1d7211 */
/* 0x000fe400008f0eff */
/*0cf0*/ LEA R18, P0, R22.reuse, c[0x0][0x160], 0x2 ; /* 0x0000580016127a11 */
/* 0x042fe200078010ff */
/*0d00*/ LDG.E R10, [R10.64] ; /* 0x000000060a0a7981 */
/* 0x000f62000c1e1900 */
/*0d10*/ IADD3 R28, P1, R23.reuse, R12, RZ ; /* 0x0000000c171c7210 */
/* 0x040fe40007f3e0ff */
/*0d20*/ LEA.HI.X R19, R22, c[0x0][0x164], R29, 0x2, P0 ; /* 0x0000590016137a11 */
/* 0x000fe400000f141d */
/*0d30*/ LEA.HI.X.SX32 R23, R23, R6, 0x1, P1 ; /* 0x0000000617177211 */
/* 0x000fc400008f0eff */
/*0d40*/ LEA R22, P0, R28.reuse, c[0x0][0x160], 0x2 ; /* 0x000058001c167a11 */
/* 0x040fe200078010ff */
/*0d50*/ LDG.E R18, [R18.64] ; /* 0x0000000612127981 */
/* 0x000f62000c1e1900 */
/*0d60*/ IADD3 R17, P1, R25.reuse, R12, RZ ; /* 0x0000000c19117210 */
/* 0x041fe40007f3e0ff */
/*0d70*/ LEA.HI.X R23, R28, c[0x0][0x164], R23, 0x2, P0 ; /* 0x000059001c177a11 */
/* 0x000fe400000f1417 */
/*0d80*/ LEA.HI.X.SX32 R28, R25, R6, 0x1, P1 ; /* 0x00000006191c7211 */
/* 0x000fe400008f0eff */
/*0d90*/ LEA R16, P0, R17.reuse, c[0x0][0x160], 0x2 ; /* 0x0000580011107a11 */
/* 0x040fe200078010ff */
/*0da0*/ LDG.E R22, [R22.64] ; /* 0x0000000616167981 */
/* 0x000f66000c1e1900 */
/*0db0*/ LEA.HI.X R17, R17, c[0x0][0x164], R28, 0x2, P0 ; /* 0x0000590011117a11 */
/* 0x000fca00000f141c */
/*0dc0*/ LDG.E R16, [R16.64] ; /* 0x0000000610107981 */
/* 0x000f62000c1e1900 */
/*0dd0*/ IADD3 R14, P1, R14, 0x20, RZ ; /* 0x000000200e0e7810 */
/* 0x000fe40007f3e0ff */
/*0de0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0df0*/ IADD3 R4, R4, 0x8, RZ ; /* 0x0000000804047810 */
/* 0x000fe20007ffe0ff */
/*0e00*/ IMAD.X R15, RZ, RZ, R15, P1 ; /* 0x000000ffff0f7224 */
/* 0x000fe200008e060f */
/*0e10*/ IADD3 R8, R8, -0x8, RZ ; /* 0xfffffff808087810 */
/* 0x000fe20007ffe0ff */
/*0e20*/ FFMA R9, R24, R24, R9 ; /* 0x0000001818097223 */
/* 0x004fc80000000009 */
/*0e30*/ FFMA R26, R26, R26, R9 ; /* 0x0000001a1a1a7223 */
/* 0x008fc80000000009 */
/*0e40*/ FFMA R27, R27, R27, R26 ; /* 0x0000001b1b1b7223 */
/* 0x010fc8000000001a */
/*0e50*/ FFMA R27, R20, R20, R27 ; /* 0x00000014141b7223 */
/* 0x020fc8000000001b */
/*0e60*/ FFMA R27, R10, R10, R27 ; /* 0x0000000a0a1b7223 */
/* 0x000fc8000000001b */
/*0e70*/ FFMA R27, R18, R18, R27 ; /* 0x00000012121b7223 */
/* 0x000fc8000000001b */
/*0e80*/ FFMA R27, R22, R22, R27 ; /* 0x00000016161b7223 */
/* 0x000fc8000000001b */
/*0e90*/ FFMA R9, R16, R16, R27 ; /* 0x0000001010097223 */
/* 0x000fe4000000001b */
/*0ea0*/ BSYNC B3 ; /* 0x0000000000037941 */
/* 0x000fea0003800000 */
/*0eb0*/ ISETP.NE.OR P0, PT, R8, RZ, P0 ; /* 0x000000ff0800720c */
/* 0x000fda0000705670 */
/*0ec0*/ @!P0 BREAK B0 ; /* 0x0000000000008942 */
/* 0x000fe20003800000 */
/*0ed0*/ @!P0 BRA 0x1110 ; /* 0x0000023000008947 */
/* 0x000fea0003800000 */
/*0ee0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0ef0*/ LDG.E R11, [R14.64+-0x8] ; /* 0xfffff8060e0b7981 */
/* 0x000ea8000c1e1900 */
/*0f00*/ LDG.E R17, [R14.64+-0x4] ; /* 0xfffffc060e117981 */
/* 0x000ee8000c1e1900 */
/*0f10*/ LDG.E R23, [R14.64] ; /* 0x000000060e177981 */
/* 0x000f28000c1e1900 */
/*0f20*/ LDG.E R21, [R14.64+0x4] ; /* 0x000004060e157981 */
/* 0x000f62000c1e1900 */
/*0f30*/ IADD3 R19, P0, R11, R12, RZ ; /* 0x0000000c0b137210 */
/* 0x004fc40007f1e0ff */
/*0f40*/ IADD3 R10, P1, R17, R12, RZ ; /* 0x0000000c110a7210 */
/* 0x008fe40007f3e0ff */
/*0f50*/ LEA.HI.X.SX32 R20, R11, R6.reuse, 0x1, P0 ; /* 0x000000060b147211 */
/* 0x080fe400000f0eff */
/*0f60*/ LEA R18, P0, R19, c[0x0][0x160], 0x2 ; /* 0x0000580013127a11 */
/* 0x000fe400078010ff */
/*0f70*/ LEA.HI.X.SX32 R17, R17, R6, 0x1, P1 ; /* 0x0000000611117211 */
/* 0x000fe400008f0eff */
/*0f80*/ LEA R16, P1, R10, c[0x0][0x160], 0x2 ; /* 0x000058000a107a11 */
/* 0x000fe400078210ff */
/*0f90*/ IADD3 R11, P2, R23, R12, RZ ; /* 0x0000000c170b7210 */
/* 0x010fc40007f5e0ff */
/*0fa0*/ LEA.HI.X R19, R19, c[0x0][0x164], R20, 0x2, P0 ; /* 0x0000590013137a11 */
/* 0x000fe400000f1414 */
/*0fb0*/ LEA.HI.X R17, R10, c[0x0][0x164], R17, 0x2, P1 ; /* 0x000059000a117a11 */
/* 0x000fe400008f1411 */
/*0fc0*/ LEA.HI.X.SX32 R20, R23, R6, 0x1, P2 ; /* 0x0000000617147211 */
/* 0x000fe200010f0eff */
/*0fd0*/ LDG.E R18, [R18.64] ; /* 0x0000000612127981 */
/* 0x000ea2000c1e1900 */
/*0fe0*/ LEA R10, P0, R11, c[0x0][0x160], 0x2 ; /* 0x000058000b0a7a11 */
/* 0x000fe400078010ff */
/*0ff0*/ IADD3 R22, P1, R21, R12, RZ ; /* 0x0000000c15167210 */
/* 0x020fe20007f3e0ff */
/*1000*/ LDG.E R16, [R16.64] ; /* 0x0000000610107981 */
/* 0x000ee2000c1e1900 */
/*1010*/ LEA.HI.X R11, R11, c[0x0][0x164], R20, 0x2, P0 ; /* 0x000059000b0b7a11 */
/* 0x000fc400000f1414 */
/*1020*/ LEA.HI.X.SX32 R21, R21, R6, 0x1, P1 ; /* 0x0000000615157211 */
/* 0x000fe400008f0eff */
/*1030*/ LEA R20, P0, R22.reuse, c[0x0][0x160], 0x2 ; /* 0x0000580016147a11 */
/* 0x040fe200078010ff */
/*1040*/ LDG.E R10, [R10.64] ; /* 0x000000060a0a7981 */
/* 0x000f26000c1e1900 */
/*1050*/ LEA.HI.X R21, R22, c[0x0][0x164], R21, 0x2, P0 ; /* 0x0000590016157a11 */
/* 0x000fca00000f1415 */
/*1060*/ LDG.E R20, [R20.64] ; /* 0x0000000614147981 */
/* 0x000f62000c1e1900 */
/*1070*/ IADD3 R8, R8, -0x4, RZ ; /* 0xfffffffc08087810 */
/* 0x000fc80007ffe0ff */
/*1080*/ ISETP.NE.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fe40003f05270 */
/*1090*/ IADD3 R14, P1, R14, 0x10, RZ ; /* 0x000000100e0e7810 */
/* 0x000fe40007f3e0ff */
/*10a0*/ IADD3 R4, R4, 0x4, RZ ; /* 0x0000000404047810 */
/* 0x000fc60007ffe0ff */
/*10b0*/ IMAD.X R15, RZ, RZ, R15, P1 ; /* 0x000000ffff0f7224 */
/* 0x000fe400008e060f */
/*10c0*/ FFMA R9, R18, R18, R9 ; /* 0x0000001212097223 */
/* 0x004fc80000000009 */
/*10d0*/ FFMA R9, R16, R16, R9 ; /* 0x0000001010097223 */
/* 0x008fc80000000009 */
/*10e0*/ FFMA R9, R10, R10, R9 ; /* 0x0000000a0a097223 */
/* 0x010fc80000000009 */
/*10f0*/ FFMA R9, R20, R20, R9 ; /* 0x0000001414097223 */
/* 0x020fe20000000009 */
/*1100*/ @P0 BRA 0xef0 ; /* 0xfffffde000000947 */
/* 0x000fea000383ffff */
/*1110*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*1120*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fda0003f05270 */
/*1130*/ @!P0 BRA 0x1280 ; /* 0x0000014000008947 */
/* 0x000fea0003800000 */
/*1140*/ SHF.R.S32.HI R11, RZ, 0x1f, R4.reuse ; /* 0x0000001fff0b7819 */
/* 0x100fe20000011404 */
/*1150*/ IMAD.MOV.U32 R10, RZ, RZ, R4 ; /* 0x000000ffff0a7224 */
/* 0x000fe400078e0004 */
/*1160*/ IMAD R7, R7, R0, RZ ; /* 0x0000000007077224 */
/* 0x000fe400078e02ff */
/*1170*/ IMAD.WIDE.U32 R10, R0, c[0x0][0x188], R10 ; /* 0x00006200000a7a25 */
/* 0x000fc800078e000a */
/*1180*/ IMAD.IADD R11, R7, 0x1, R11 ; /* 0x00000001070b7824 */
/* 0x000fe200078e020b */
/*1190*/ LEA R4, P0, R10, c[0x0][0x170], 0x2 ; /* 0x00005c000a047a11 */
/* 0x000fc800078010ff */
/*11a0*/ LEA.HI.X R11, R10, c[0x0][0x174], R11, 0x2, P0 ; /* 0x00005d000a0b7a11 */
/* 0x000fe400000f140b */
/*11b0*/ IMAD.MOV.U32 R10, RZ, RZ, R4 ; /* 0x000000ffff0a7224 */
/* 0x000fca00078e0004 */
/*11c0*/ LDG.E R7, [R10.64] ; /* 0x000000060a077981 */
/* 0x000ea2000c1e1900 */
/*11d0*/ IADD3 R5, R5, -0x1, RZ ; /* 0xffffffff05057810 */
/* 0x000fe40007ffe0ff */
/*11e0*/ IADD3 R0, P0, R7, R12, RZ ; /* 0x0000000c07007210 */
/* 0x004fc80007f1e0ff */
/*11f0*/ LEA.HI.X.SX32 R7, R7, R6, 0x1, P0 ; /* 0x0000000607077211 */
/* 0x000fe400000f0eff */
/*1200*/ LEA R14, P0, R0, c[0x0][0x160], 0x2 ; /* 0x00005800000e7a11 */
/* 0x000fc800078010ff */
/*1210*/ LEA.HI.X R15, R0, c[0x0][0x164], R7, 0x2, P0 ; /* 0x00005900000f7a11 */
/* 0x000fca00000f1407 */
/*1220*/ LDG.E R14, [R14.64] ; /* 0x000000060e0e7981 */
/* 0x000ea2000c1e1900 */
/*1230*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe40003f05270 */
/*1240*/ IADD3 R4, P1, R4, 0x4, RZ ; /* 0x0000000404047810 */
/* 0x000fca0007f3e0ff */
/*1250*/ IMAD.X R11, RZ, RZ, R11, P1 ; /* 0x000000ffff0b7224 */
/* 0x000fe400008e060b */
/*1260*/ FFMA R9, R14, R14, R9 ; /* 0x0000000e0e097223 */
/* 0x004fc80000000009 */
/*1270*/ @P0 BRA 0x11b0 ; /* 0xffffff3000000947 */
/* 0x000fea000383ffff */
/*1280*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*1290*/ WARPSYNC 0xffffffff ; /* 0xffffffff00007948 */
/* 0x000fe20003800000 */
/*12a0*/ IADD3 R2, P0, R2, c[0x0][0x168], RZ ; /* 0x00005a0002027a10 */
/* 0x000fc80007f1e0ff */
/*12b0*/ IADD3.X R3, R3, c[0x0][0x16c], RZ, P0, !PT ; /* 0x00005b0003037a10 */
/* 0x000fca00007fe4ff */
/*12c0*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x000fe2000c101906 */
/*12d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*12e0*/ BRA 0x12e0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*12f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1300*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1310*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1320*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
/**
* Programma che simula il comportamento del gpdt per
* la risoluzione di un kernel di una serie di
* valori di dimensione variabile utilizzando la
* tecnologia cuda.
* compilare con:
* nvcc -o simil_gpdt_si_cuda simil_gpdt_si_cuda.cu
* lanciare con:
* ./simil_gpdt_si_cuda [numero vettori] [numero componenti] [numero di righe da calcolare] [tipo di kernel] [grado(int)/sigma(float)]
**/
using namespace std;
/**
* Funzione che riempie i vettori con numeri
* casuali compresi tra 0 e 99.
**/
__global__ void Kernel_norme(float *Vd, float *Nd, int *Vp, int *Vnp, int N, int C, int nr_max_val)
{
long int x = threadIdx.x + blockIdx.x * blockDim.x;
int pos;
if(x < N)
{
float norma = 0;
int Nr_val = Vnp[x];
for(int i = 0; i < Nr_val; i++)
{
pos = Vp[x * nr_max_val + i];
norma = norma + (Vd[x * C + pos] * Vd[x * C + pos]);
}
Nd[x] = norma;
}
} | .file "tmpxft_00054330_00000000-6_Kernel_norme.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z42__device_stub__Z12Kernel_normePfS_PiS0_iiiPfS_PiS0_iii
.type _Z42__device_stub__Z12Kernel_normePfS_PiS0_iiiPfS_PiS0_iii, @function
_Z42__device_stub__Z12Kernel_normePfS_PiS0_iiiPfS_PiS0_iii:
.LFB2051:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movl %r8d, 12(%rsp)
movl %r9d, 8(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 12(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
leaq 192(%rsp), %rax
movq %rax, 160(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z12Kernel_normePfS_PiS0_iii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z42__device_stub__Z12Kernel_normePfS_PiS0_iiiPfS_PiS0_iii, .-_Z42__device_stub__Z12Kernel_normePfS_PiS0_iiiPfS_PiS0_iii
.globl _Z12Kernel_normePfS_PiS0_iii
.type _Z12Kernel_normePfS_PiS0_iii, @function
_Z12Kernel_normePfS_PiS0_iii:
.LFB2052:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
call _Z42__device_stub__Z12Kernel_normePfS_PiS0_iiiPfS_PiS0_iii
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z12Kernel_normePfS_PiS0_iii, .-_Z12Kernel_normePfS_PiS0_iii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z12Kernel_normePfS_PiS0_iii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z12Kernel_normePfS_PiS0_iii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
/**
* Programma che simula il comportamento del gpdt per
* la risoluzione di un kernel di una serie di
* valori di dimensione variabile utilizzando la
* tecnologia cuda.
* compilare con:
* nvcc -o simil_gpdt_si_cuda simil_gpdt_si_cuda.cu
* lanciare con:
* ./simil_gpdt_si_cuda [numero vettori] [numero componenti] [numero di righe da calcolare] [tipo di kernel] [grado(int)/sigma(float)]
**/
using namespace std;
/**
* Funzione che riempie i vettori con numeri
* casuali compresi tra 0 e 99.
**/
__global__ void Kernel_norme(float *Vd, float *Nd, int *Vp, int *Vnp, int N, int C, int nr_max_val)
{
long int x = threadIdx.x + blockIdx.x * blockDim.x;
int pos;
if(x < N)
{
float norma = 0;
int Nr_val = Vnp[x];
for(int i = 0; i < Nr_val; i++)
{
pos = Vp[x * nr_max_val + i];
norma = norma + (Vd[x * C + pos] * Vd[x * C + pos]);
}
Nd[x] = norma;
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
/**
* Programma che simula il comportamento del gpdt per
* la risoluzione di un kernel di una serie di
* valori di dimensione variabile utilizzando la
* tecnologia cuda.
* compilare con:
* nvcc -o simil_gpdt_si_cuda simil_gpdt_si_cuda.cu
* lanciare con:
* ./simil_gpdt_si_cuda [numero vettori] [numero componenti] [numero di righe da calcolare] [tipo di kernel] [grado(int)/sigma(float)]
**/
using namespace std;
/**
* Funzione che riempie i vettori con numeri
* casuali compresi tra 0 e 99.
**/
__global__ void Kernel_norme(float *Vd, float *Nd, int *Vp, int *Vnp, int N, int C, int nr_max_val)
{
long int x = threadIdx.x + blockIdx.x * blockDim.x;
int pos;
if(x < N)
{
float norma = 0;
int Nr_val = Vnp[x];
for(int i = 0; i < Nr_val; i++)
{
pos = Vp[x * nr_max_val + i];
norma = norma + (Vd[x * C + pos] * Vd[x * C + pos]);
}
Nd[x] = norma;
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
/**
* Programma che simula il comportamento del gpdt per
* la risoluzione di un kernel di una serie di
* valori di dimensione variabile utilizzando la
* tecnologia cuda.
* compilare con:
* nvcc -o simil_gpdt_si_cuda simil_gpdt_si_cuda.cu
* lanciare con:
* ./simil_gpdt_si_cuda [numero vettori] [numero componenti] [numero di righe da calcolare] [tipo di kernel] [grado(int)/sigma(float)]
**/
using namespace std;
/**
* Funzione che riempie i vettori con numeri
* casuali compresi tra 0 e 99.
**/
__global__ void Kernel_norme(float *Vd, float *Nd, int *Vp, int *Vnp, int N, int C, int nr_max_val)
{
long int x = threadIdx.x + blockIdx.x * blockDim.x;
int pos;
if(x < N)
{
float norma = 0;
int Nr_val = Vnp[x];
for(int i = 0; i < Nr_val; i++)
{
pos = Vp[x * nr_max_val + i];
norma = norma + (Vd[x * C + pos] * Vd[x * C + pos]);
}
Nd[x] = norma;
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z12Kernel_normePfS_PiS0_iii
.globl _Z12Kernel_normePfS_PiS0_iii
.p2align 8
.type _Z12Kernel_normePfS_PiS0_iii,@function
_Z12Kernel_normePfS_PiS0_iii:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x3c
s_load_b32 s2, s[0:1], 0x20
v_mov_b32_e32 v5, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[1:2], null, s15, s3, v[0:1]
v_mov_b32_e32 v2, v5
s_ashr_i32 s3, s2, 31
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_cmp_gt_i64_e32 vcc_lo, s[2:3], v[1:2]
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_6
s_load_b64 s[2:3], s[0:1], 0x18
v_lshlrev_b64 v[3:4], 2, v[1:2]
s_mov_b32 s4, 0
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v3, vcc_lo, s2, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v4, vcc_lo
s_mov_b32 s3, exec_lo
global_load_b32 v0, v[3:4], off
s_waitcnt vmcnt(0)
v_cmpx_lt_i32_e32 0, v0
s_cbranch_execz .LBB0_5
s_clause 0x2
s_load_b64 s[6:7], s[0:1], 0x24
s_load_b64 s[8:9], s[0:1], 0x10
s_load_b64 s[10:11], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[3:4], null, v1, s7, 0
v_mad_u64_u32 v[5:6], null, v1, s6, 0
s_ashr_i32 s2, s7, 31
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[7:8], null, v1, s2, v[4:5]
s_ashr_i32 s2, s6, 31
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[8:9], null, v1, s2, v[6:7]
v_mov_b32_e32 v4, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mov_b32_e32 v6, v8
v_lshlrev_b64 v[6:7], 2, v[5:6]
v_mov_b32_e32 v5, 0
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[3:4]
v_add_co_u32 v3, vcc_lo, s8, v3
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, s9, v4, vcc_lo
v_add_co_u32 v6, vcc_lo, s10, v6
v_add_co_ci_u32_e32 v7, vcc_lo, s11, v7, vcc_lo
.p2align 6
.LBB0_3:
global_load_b32 v8, v[3:4], off
v_add_nc_u32_e32 v0, -1, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_eq_u32_e64 s2, 0, v0
s_or_b32 s4, s2, s4
s_waitcnt vmcnt(0)
v_ashrrev_i32_e32 v9, 31, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[8:9], 2, v[8:9]
v_add_co_u32 v8, vcc_lo, v6, v8
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v9, vcc_lo, v7, v9, vcc_lo
v_add_co_u32 v3, vcc_lo, v3, 4
v_add_co_ci_u32_e32 v4, vcc_lo, 0, v4, vcc_lo
global_load_b32 v8, v[8:9], off
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v5, v8, v8
s_and_not1_b32 exec_lo, exec_lo, s4
s_cbranch_execnz .LBB0_3
s_or_b32 exec_lo, exec_lo, s4
.LBB0_5:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
s_or_b32 exec_lo, exec_lo, s3
s_load_b64 s[0:1], s[0:1], 0x8
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v5, off
.LBB0_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12Kernel_normePfS_PiS0_iii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 304
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 10
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z12Kernel_normePfS_PiS0_iii, .Lfunc_end0-_Z12Kernel_normePfS_PiS0_iii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 36
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: by_value
- .offset: 48
.size: 4
.value_kind: hidden_block_count_x
- .offset: 52
.size: 4
.value_kind: hidden_block_count_y
- .offset: 56
.size: 4
.value_kind: hidden_block_count_z
- .offset: 60
.size: 2
.value_kind: hidden_group_size_x
- .offset: 62
.size: 2
.value_kind: hidden_group_size_y
- .offset: 64
.size: 2
.value_kind: hidden_group_size_z
- .offset: 66
.size: 2
.value_kind: hidden_remainder_x
- .offset: 68
.size: 2
.value_kind: hidden_remainder_y
- .offset: 70
.size: 2
.value_kind: hidden_remainder_z
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 112
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 304
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12Kernel_normePfS_PiS0_iii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z12Kernel_normePfS_PiS0_iii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 10
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
/**
* Programma che simula il comportamento del gpdt per
* la risoluzione di un kernel di una serie di
* valori di dimensione variabile utilizzando la
* tecnologia cuda.
* compilare con:
* nvcc -o simil_gpdt_si_cuda simil_gpdt_si_cuda.cu
* lanciare con:
* ./simil_gpdt_si_cuda [numero vettori] [numero componenti] [numero di righe da calcolare] [tipo di kernel] [grado(int)/sigma(float)]
**/
using namespace std;
/**
* Funzione che riempie i vettori con numeri
* casuali compresi tra 0 e 99.
**/
__global__ void Kernel_norme(float *Vd, float *Nd, int *Vp, int *Vnp, int N, int C, int nr_max_val)
{
long int x = threadIdx.x + blockIdx.x * blockDim.x;
int pos;
if(x < N)
{
float norma = 0;
int Nr_val = Vnp[x];
for(int i = 0; i < Nr_val; i++)
{
pos = Vp[x * nr_max_val + i];
norma = norma + (Vd[x * C + pos] * Vd[x * C + pos]);
}
Nd[x] = norma;
}
} | .text
.file "Kernel_norme.hip"
.globl _Z27__device_stub__Kernel_normePfS_PiS0_iii # -- Begin function _Z27__device_stub__Kernel_normePfS_PiS0_iii
.p2align 4, 0x90
.type _Z27__device_stub__Kernel_normePfS_PiS0_iii,@function
_Z27__device_stub__Kernel_normePfS_PiS0_iii: # @_Z27__device_stub__Kernel_normePfS_PiS0_iii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movl %r8d, 12(%rsp)
movl %r9d, 8(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 12(%rsp), %rax
movq %rax, 128(%rsp)
leaq 8(%rsp), %rax
movq %rax, 136(%rsp)
leaq 160(%rsp), %rax
movq %rax, 144(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z12Kernel_normePfS_PiS0_iii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z27__device_stub__Kernel_normePfS_PiS0_iii, .Lfunc_end0-_Z27__device_stub__Kernel_normePfS_PiS0_iii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12Kernel_normePfS_PiS0_iii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z12Kernel_normePfS_PiS0_iii,@object # @_Z12Kernel_normePfS_PiS0_iii
.section .rodata,"a",@progbits
.globl _Z12Kernel_normePfS_PiS0_iii
.p2align 3, 0x0
_Z12Kernel_normePfS_PiS0_iii:
.quad _Z27__device_stub__Kernel_normePfS_PiS0_iii
.size _Z12Kernel_normePfS_PiS0_iii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z12Kernel_normePfS_PiS0_iii"
.size .L__unnamed_1, 29
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__Kernel_normePfS_PiS0_iii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12Kernel_normePfS_PiS0_iii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00054330_00000000-6_Kernel_norme.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z42__device_stub__Z12Kernel_normePfS_PiS0_iiiPfS_PiS0_iii
.type _Z42__device_stub__Z12Kernel_normePfS_PiS0_iiiPfS_PiS0_iii, @function
_Z42__device_stub__Z12Kernel_normePfS_PiS0_iiiPfS_PiS0_iii:
.LFB2051:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movl %r8d, 12(%rsp)
movl %r9d, 8(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 12(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
leaq 192(%rsp), %rax
movq %rax, 160(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z12Kernel_normePfS_PiS0_iii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z42__device_stub__Z12Kernel_normePfS_PiS0_iiiPfS_PiS0_iii, .-_Z42__device_stub__Z12Kernel_normePfS_PiS0_iiiPfS_PiS0_iii
.globl _Z12Kernel_normePfS_PiS0_iii
.type _Z12Kernel_normePfS_PiS0_iii, @function
_Z12Kernel_normePfS_PiS0_iii:
.LFB2052:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
call _Z42__device_stub__Z12Kernel_normePfS_PiS0_iiiPfS_PiS0_iii
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z12Kernel_normePfS_PiS0_iii, .-_Z12Kernel_normePfS_PiS0_iii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z12Kernel_normePfS_PiS0_iii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z12Kernel_normePfS_PiS0_iii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "Kernel_norme.hip"
.globl _Z27__device_stub__Kernel_normePfS_PiS0_iii # -- Begin function _Z27__device_stub__Kernel_normePfS_PiS0_iii
.p2align 4, 0x90
.type _Z27__device_stub__Kernel_normePfS_PiS0_iii,@function
_Z27__device_stub__Kernel_normePfS_PiS0_iii: # @_Z27__device_stub__Kernel_normePfS_PiS0_iii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movl %r8d, 12(%rsp)
movl %r9d, 8(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 12(%rsp), %rax
movq %rax, 128(%rsp)
leaq 8(%rsp), %rax
movq %rax, 136(%rsp)
leaq 160(%rsp), %rax
movq %rax, 144(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z12Kernel_normePfS_PiS0_iii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z27__device_stub__Kernel_normePfS_PiS0_iii, .Lfunc_end0-_Z27__device_stub__Kernel_normePfS_PiS0_iii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12Kernel_normePfS_PiS0_iii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z12Kernel_normePfS_PiS0_iii,@object # @_Z12Kernel_normePfS_PiS0_iii
.section .rodata,"a",@progbits
.globl _Z12Kernel_normePfS_PiS0_iii
.p2align 3, 0x0
_Z12Kernel_normePfS_PiS0_iii:
.quad _Z27__device_stub__Kernel_normePfS_PiS0_iii
.size _Z12Kernel_normePfS_PiS0_iii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z12Kernel_normePfS_PiS0_iii"
.size .L__unnamed_1, 29
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__Kernel_normePfS_PiS0_iii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12Kernel_normePfS_PiS0_iii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void expon(float* env, int nhalf) {
int i = threadIdx.x + blockDim.x*blockIdx.x;
if (i < nhalf) {
env[i] = exp(env[i]/nhalf); // exponentiate
}
} | code for sm_80
Function : _Z5exponPfi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e280000002100 */
/*0020*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0030*/ IMAD R2, R3, c[0x0][0x0], R2 ; /* 0x0000000003027a24 */
/* 0x001fca00078e0202 */
/*0040*/ ISETP.GE.AND P0, PT, R2, c[0x0][0x168], PT ; /* 0x00005a0002007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fe200078e00ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0080*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0203 */
/*0090*/ LDG.E R5, [R2.64] ; /* 0x0000000402057981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ I2F R4, c[0x0][0x168] ; /* 0x00005a0000047b06 */
/* 0x000e220000201400 */
/*00b0*/ BSSY B0, 0x180 ; /* 0x000000c000007945 */
/* 0x000fee0003800000 */
/*00c0*/ MUFU.RCP R7, R4 ; /* 0x0000000400077308 */
/* 0x001e240000001000 */
/*00d0*/ FFMA R0, -R4, R7, 1 ; /* 0x3f80000004007423 */
/* 0x001fc80000000107 */
/*00e0*/ FFMA R0, R7, R0, R7 ; /* 0x0000000007007223 */
/* 0x000fe40000000007 */
/*00f0*/ FCHK P0, R5, R4 ; /* 0x0000000405007302 */
/* 0x004e240000000000 */
/*0100*/ FFMA R7, R5, R0, RZ ; /* 0x0000000005077223 */
/* 0x000fc800000000ff */
/*0110*/ FFMA R6, -R4, R7, R5 ; /* 0x0000000704067223 */
/* 0x000fc80000000105 */
/*0120*/ FFMA R0, R0, R6, R7 ; /* 0x0000000600007223 */
/* 0x000fe20000000007 */
/*0130*/ @!P0 BRA 0x170 ; /* 0x0000003000008947 */
/* 0x001fea0003800000 */
/*0140*/ MOV R0, 0x160 ; /* 0x0000016000007802 */
/* 0x000fe40000000f00 */
/*0150*/ CALL.REL.NOINC 0x240 ; /* 0x000000e000007944 */
/* 0x000fea0003c00000 */
/*0160*/ IMAD.MOV.U32 R0, RZ, RZ, R6 ; /* 0x000000ffff007224 */
/* 0x000fe400078e0006 */
/*0170*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0180*/ IMAD.MOV.U32 R5, RZ, RZ, 0x3bbb989d ; /* 0x3bbb989dff057424 */
/* 0x000fe400078e00ff */
/*0190*/ IMAD.MOV.U32 R7, RZ, RZ, 0x437c0000 ; /* 0x437c0000ff077424 */
/* 0x000fe400078e00ff */
/*01a0*/ FFMA.SAT R4, R0, R5, 0.5 ; /* 0x3f00000000047423 */
/* 0x000fc80000002005 */
/*01b0*/ FFMA.RM R4, R4, R7, 12582913 ; /* 0x4b40000104047423 */
/* 0x000fc80000004007 */
/*01c0*/ FADD R5, R4.reuse, -12583039 ; /* 0xcb40007f04057421 */
/* 0x040fe40000000000 */
/*01d0*/ IMAD.SHL.U32 R4, R4, 0x800000, RZ ; /* 0x0080000004047824 */
/* 0x000fe400078e00ff */
/*01e0*/ FFMA R5, R0, 1.4426950216293334961, -R5 ; /* 0x3fb8aa3b00057823 */
/* 0x000fc80000000805 */
/*01f0*/ FFMA R5, R0, 1.925963033500011079e-08, R5 ; /* 0x32a5706000057823 */
/* 0x000fcc0000000005 */
/*0200*/ MUFU.EX2 R5, R5 ; /* 0x0000000500057308 */
/* 0x000e240000000800 */
/*0210*/ FMUL R7, R4, R5 ; /* 0x0000000504077220 */
/* 0x001fca0000400000 */
/*0220*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x000fe2000c101904 */
/*0230*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0240*/ SHF.R.U32.HI R7, RZ, 0x17, R4.reuse ; /* 0x00000017ff077819 */
/* 0x100fe20000011604 */
/*0250*/ BSSY B1, 0x8a0 ; /* 0x0000064000017945 */
/* 0x000fe20003800000 */
/*0260*/ SHF.R.U32.HI R6, RZ, 0x17, R5.reuse ; /* 0x00000017ff067819 */
/* 0x100fe20000011605 */
/*0270*/ IMAD.MOV.U32 R8, RZ, RZ, R5 ; /* 0x000000ffff087224 */
/* 0x000fe200078e0005 */
/*0280*/ LOP3.LUT R7, R7, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff07077812 */
/* 0x000fe200078ec0ff */
/*0290*/ IMAD.MOV.U32 R9, RZ, RZ, R4 ; /* 0x000000ffff097224 */
/* 0x000fe200078e0004 */
/*02a0*/ LOP3.LUT R6, R6, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff06067812 */
/* 0x000fe400078ec0ff */
/*02b0*/ IADD3 R12, R7, -0x1, RZ ; /* 0xffffffff070c7810 */
/* 0x000fe40007ffe0ff */
/*02c0*/ IADD3 R11, R6, -0x1, RZ ; /* 0xffffffff060b7810 */
/* 0x000fc40007ffe0ff */
/*02d0*/ ISETP.GT.U32.AND P0, PT, R12, 0xfd, PT ; /* 0x000000fd0c00780c */
/* 0x000fc80003f04070 */
/*02e0*/ ISETP.GT.U32.OR P0, PT, R11, 0xfd, P0 ; /* 0x000000fd0b00780c */
/* 0x000fda0000704470 */
/*02f0*/ @!P0 IMAD.MOV.U32 R10, RZ, RZ, RZ ; /* 0x000000ffff0a8224 */
/* 0x000fe200078e00ff */
/*0300*/ @!P0 BRA 0x480 ; /* 0x0000017000008947 */
/* 0x000fea0003800000 */
/*0310*/ FSETP.GTU.FTZ.AND P0, PT, |R5|, +INF , PT ; /* 0x7f8000000500780b */
/* 0x000fe40003f1c200 */
/*0320*/ FSETP.GTU.FTZ.AND P1, PT, |R4|, +INF , PT ; /* 0x7f8000000400780b */
/* 0x000fc80003f3c200 */
/*0330*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000703570 */
/*0340*/ @P0 BRA 0x880 ; /* 0x0000053000000947 */
/* 0x000fea0003800000 */
/*0350*/ LOP3.LUT P0, RZ, R9, 0x7fffffff, R8, 0xc8, !PT ; /* 0x7fffffff09ff7812 */
/* 0x000fda000780c808 */
/*0360*/ @!P0 BRA 0x860 ; /* 0x000004f000008947 */
/* 0x000fea0003800000 */
/*0370*/ FSETP.NEU.FTZ.AND P2, PT, |R5|.reuse, +INF , PT ; /* 0x7f8000000500780b */
/* 0x040fe40003f5d200 */
/*0380*/ FSETP.NEU.FTZ.AND P1, PT, |R4|, +INF , PT ; /* 0x7f8000000400780b */
/* 0x000fe40003f3d200 */
/*0390*/ FSETP.NEU.FTZ.AND P0, PT, |R5|, +INF , PT ; /* 0x7f8000000500780b */
/* 0x000fd60003f1d200 */
/*03a0*/ @!P1 BRA !P2, 0x860 ; /* 0x000004b000009947 */
/* 0x000fea0005000000 */
/*03b0*/ LOP3.LUT P2, RZ, R8, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff08ff7812 */
/* 0x000fc8000784c0ff */
/*03c0*/ PLOP3.LUT P1, PT, P1, P2, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000f24572 */
/*03d0*/ @P1 BRA 0x840 ; /* 0x0000046000001947 */
/* 0x000fea0003800000 */
/*03e0*/ LOP3.LUT P1, RZ, R9, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff09ff7812 */
/* 0x000fc8000782c0ff */
/*03f0*/ PLOP3.LUT P0, PT, P0, P1, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000702572 */
/*0400*/ @P0 BRA 0x810 ; /* 0x0000040000000947 */
/* 0x000fea0003800000 */
/*0410*/ ISETP.GE.AND P0, PT, R11, RZ, PT ; /* 0x000000ff0b00720c */
/* 0x000fe40003f06270 */
/*0420*/ ISETP.GE.AND P1, PT, R12, RZ, PT ; /* 0x000000ff0c00720c */
/* 0x000fd60003f26270 */
/*0430*/ @P0 IMAD.MOV.U32 R10, RZ, RZ, RZ ; /* 0x000000ffff0a0224 */
/* 0x000fe400078e00ff */
/*0440*/ @!P0 IMAD.MOV.U32 R10, RZ, RZ, -0x40 ; /* 0xffffffc0ff0a8424 */
/* 0x000fe400078e00ff */
/*0450*/ @!P0 FFMA R8, R5, 1.84467440737095516160e+19, RZ ; /* 0x5f80000005088823 */
/* 0x000fe400000000ff */
/*0460*/ @!P1 FFMA R9, R4, 1.84467440737095516160e+19, RZ ; /* 0x5f80000004099823 */
/* 0x000fe200000000ff */
/*0470*/ @!P1 IADD3 R10, R10, 0x40, RZ ; /* 0x000000400a0a9810 */
/* 0x000fe40007ffe0ff */
/*0480*/ LEA R4, R7, 0xc0800000, 0x17 ; /* 0xc080000007047811 */
/* 0x000fe200078eb8ff */
/*0490*/ BSSY B2, 0x800 ; /* 0x0000036000027945 */
/* 0x000fe20003800000 */
/*04a0*/ IADD3 R6, R6, -0x7f, RZ ; /* 0xffffff8106067810 */
/* 0x000fc60007ffe0ff */
/*04b0*/ IMAD.IADD R9, R9, 0x1, -R4 ; /* 0x0000000109097824 */
/* 0x000fe200078e0a04 */
/*04c0*/ IADD3 R7, R6.reuse, 0x7f, -R7 ; /* 0x0000007f06077810 */
/* 0x040fe20007ffe807 */
/*04d0*/ IMAD R8, R6, -0x800000, R8 ; /* 0xff80000006087824 */
/* 0x000fe400078e0208 */
/*04e0*/ MUFU.RCP R4, R9 ; /* 0x0000000900047308 */
/* 0x000e220000001000 */
/*04f0*/ FADD.FTZ R5, -R9, -RZ ; /* 0x800000ff09057221 */
/* 0x000fe40000010100 */
/*0500*/ IMAD.IADD R7, R7, 0x1, R10 ; /* 0x0000000107077824 */
/* 0x000fe400078e020a */
/*0510*/ FFMA R11, R4, R5, 1 ; /* 0x3f800000040b7423 */
/* 0x001fc80000000005 */
/*0520*/ FFMA R13, R4, R11, R4 ; /* 0x0000000b040d7223 */
/* 0x000fc80000000004 */
/*0530*/ FFMA R4, R8, R13, RZ ; /* 0x0000000d08047223 */
/* 0x000fc800000000ff */
/*0540*/ FFMA R11, R5, R4, R8 ; /* 0x00000004050b7223 */
/* 0x000fc80000000008 */
/*0550*/ FFMA R12, R13, R11, R4 ; /* 0x0000000b0d0c7223 */
/* 0x000fc80000000004 */
/*0560*/ FFMA R8, R5, R12, R8 ; /* 0x0000000c05087223 */
/* 0x000fc80000000008 */
/*0570*/ FFMA R4, R13, R8, R12 ; /* 0x000000080d047223 */
/* 0x000fca000000000c */
/*0580*/ SHF.R.U32.HI R5, RZ, 0x17, R4 ; /* 0x00000017ff057819 */
/* 0x000fc80000011604 */
/*0590*/ LOP3.LUT R5, R5, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff05057812 */
/* 0x000fca00078ec0ff */
/*05a0*/ IMAD.IADD R9, R5, 0x1, R7 ; /* 0x0000000105097824 */
/* 0x000fca00078e0207 */
/*05b0*/ IADD3 R5, R9, -0x1, RZ ; /* 0xffffffff09057810 */
/* 0x000fc80007ffe0ff */
/*05c0*/ ISETP.GE.U32.AND P0, PT, R5, 0xfe, PT ; /* 0x000000fe0500780c */
/* 0x000fda0003f06070 */
/*05d0*/ @!P0 BRA 0x7e0 ; /* 0x0000020000008947 */
/* 0x000fea0003800000 */
/*05e0*/ ISETP.GT.AND P0, PT, R9, 0xfe, PT ; /* 0x000000fe0900780c */
/* 0x000fda0003f04270 */
/*05f0*/ @P0 BRA 0x7b0 ; /* 0x000001b000000947 */
/* 0x000fea0003800000 */
/*0600*/ ISETP.GE.AND P0, PT, R9, 0x1, PT ; /* 0x000000010900780c */
/* 0x000fda0003f06270 */
/*0610*/ @P0 BRA 0x7f0 ; /* 0x000001d000000947 */
/* 0x000fea0003800000 */
/*0620*/ ISETP.GE.AND P0, PT, R9, -0x18, PT ; /* 0xffffffe80900780c */
/* 0x000fe40003f06270 */
/*0630*/ LOP3.LUT R4, R4, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000004047812 */
/* 0x000fd600078ec0ff */
/*0640*/ @!P0 BRA 0x7f0 ; /* 0x000001a000008947 */
/* 0x000fea0003800000 */
/*0650*/ FFMA.RZ R5, R13, R8.reuse, R12.reuse ; /* 0x000000080d057223 */
/* 0x180fe2000000c00c */
/*0660*/ ISETP.NE.AND P2, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x000fe20003f45270 */
/*0670*/ FFMA.RM R6, R13, R8.reuse, R12.reuse ; /* 0x000000080d067223 */
/* 0x180fe2000000400c */
/*0680*/ ISETP.NE.AND P1, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x000fe40003f25270 */
/*0690*/ LOP3.LUT R7, R5, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff05077812 */
/* 0x000fe200078ec0ff */
/*06a0*/ FFMA.RP R5, R13, R8, R12 ; /* 0x000000080d057223 */
/* 0x000fe2000000800c */
/*06b0*/ IADD3 R8, R9, 0x20, RZ ; /* 0x0000002009087810 */
/* 0x000fe20007ffe0ff */
/*06c0*/ IMAD.MOV R9, RZ, RZ, -R9 ; /* 0x000000ffff097224 */
/* 0x000fe200078e0a09 */
/*06d0*/ LOP3.LUT R7, R7, 0x800000, RZ, 0xfc, !PT ; /* 0x0080000007077812 */
/* 0x000fe400078efcff */
/*06e0*/ FSETP.NEU.FTZ.AND P0, PT, R5, R6, PT ; /* 0x000000060500720b */
/* 0x000fc40003f1d000 */
/*06f0*/ SHF.L.U32 R8, R7, R8, RZ ; /* 0x0000000807087219 */
/* 0x000fe400000006ff */
/*0700*/ SEL R6, R9, RZ, P2 ; /* 0x000000ff09067207 */
/* 0x000fe40001000000 */
/*0710*/ ISETP.NE.AND P1, PT, R8, RZ, P1 ; /* 0x000000ff0800720c */
/* 0x000fe40000f25270 */
/*0720*/ SHF.R.U32.HI R6, RZ, R6, R7 ; /* 0x00000006ff067219 */
/* 0x000fe40000011607 */
/*0730*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40000703570 */
/*0740*/ SHF.R.U32.HI R8, RZ, 0x1, R6 ; /* 0x00000001ff087819 */
/* 0x000fc40000011606 */
/*0750*/ SEL R5, RZ, 0x1, !P0 ; /* 0x00000001ff057807 */
/* 0x000fc80004000000 */
/*0760*/ LOP3.LUT R5, R5, 0x1, R8, 0xf8, !PT ; /* 0x0000000105057812 */
/* 0x000fc800078ef808 */
/*0770*/ LOP3.LUT R5, R5, R6, RZ, 0xc0, !PT ; /* 0x0000000605057212 */
/* 0x000fca00078ec0ff */
/*0780*/ IMAD.IADD R5, R8, 0x1, R5 ; /* 0x0000000108057824 */
/* 0x000fca00078e0205 */
/*0790*/ LOP3.LUT R4, R5, R4, RZ, 0xfc, !PT ; /* 0x0000000405047212 */
/* 0x000fe200078efcff */
/*07a0*/ BRA 0x7f0 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*07b0*/ LOP3.LUT R4, R4, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000004047812 */
/* 0x000fc800078ec0ff */
/*07c0*/ LOP3.LUT R4, R4, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000004047812 */
/* 0x000fe200078efcff */
/*07d0*/ BRA 0x7f0 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*07e0*/ IMAD R4, R7, 0x800000, R4 ; /* 0x0080000007047824 */
/* 0x000fe400078e0204 */
/*07f0*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*0800*/ BRA 0x890 ; /* 0x0000008000007947 */
/* 0x000fea0003800000 */
/*0810*/ LOP3.LUT R4, R9, 0x80000000, R8, 0x48, !PT ; /* 0x8000000009047812 */
/* 0x000fc800078e4808 */
/*0820*/ LOP3.LUT R4, R4, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000004047812 */
/* 0x000fe200078efcff */
/*0830*/ BRA 0x890 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*0840*/ LOP3.LUT R4, R9, 0x80000000, R8, 0x48, !PT ; /* 0x8000000009047812 */
/* 0x000fe200078e4808 */
/*0850*/ BRA 0x890 ; /* 0x0000003000007947 */
/* 0x000fea0003800000 */
/*0860*/ MUFU.RSQ R4, -QNAN ; /* 0xffc0000000047908 */
/* 0x000e220000001400 */
/*0870*/ BRA 0x890 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0880*/ FADD.FTZ R4, R5, R4 ; /* 0x0000000405047221 */
/* 0x000fe40000010000 */
/*0890*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*08a0*/ IMAD.MOV.U32 R6, RZ, RZ, R4 ; /* 0x000000ffff067224 */
/* 0x001fe400078e0004 */
/*08b0*/ IMAD.MOV.U32 R4, RZ, RZ, R0 ; /* 0x000000ffff047224 */
/* 0x000fe400078e0000 */
/*08c0*/ IMAD.MOV.U32 R5, RZ, RZ, 0x0 ; /* 0x00000000ff057424 */
/* 0x000fc800078e00ff */
/*08d0*/ RET.REL.NODEC R4 0x0 ; /* 0xfffff72004007950 */
/* 0x000fea0003c3ffff */
/*08e0*/ BRA 0x8e0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*08f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0900*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0910*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0920*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0930*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0940*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0950*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0960*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0970*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void expon(float* env, int nhalf) {
int i = threadIdx.x + blockDim.x*blockIdx.x;
if (i < nhalf) {
env[i] = exp(env[i]/nhalf); // exponentiate
}
} | .file "tmpxft_000cd269_00000000-6_expon.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z25__device_stub__Z5exponPfiPfi
.type _Z25__device_stub__Z5exponPfiPfi, @function
_Z25__device_stub__Z5exponPfiPfi:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z5exponPfi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z25__device_stub__Z5exponPfiPfi, .-_Z25__device_stub__Z5exponPfiPfi
.globl _Z5exponPfi
.type _Z5exponPfi, @function
_Z5exponPfi:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z25__device_stub__Z5exponPfiPfi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z5exponPfi, .-_Z5exponPfi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z5exponPfi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z5exponPfi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void expon(float* env, int nhalf) {
int i = threadIdx.x + blockDim.x*blockIdx.x;
if (i < nhalf) {
env[i] = exp(env[i]/nhalf); // exponentiate
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void expon(float* env, int nhalf) {
int i = threadIdx.x + blockDim.x*blockIdx.x;
if (i < nhalf) {
env[i] = exp(env[i]/nhalf); // exponentiate
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void expon(float* env, int nhalf) {
int i = threadIdx.x + blockDim.x*blockIdx.x;
if (i < nhalf) {
env[i] = exp(env[i]/nhalf); // exponentiate
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z5exponPfi
.globl _Z5exponPfi
.p2align 8
.type _Z5exponPfi,@function
_Z5exponPfi:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x1c
s_load_b32 s2, s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s3, v[0:1]
s_mov_b32 s3, exec_lo
v_cmpx_gt_i32_e64 s2, v1
s_cbranch_execz .LBB0_2
s_load_b64 s[0:1], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
v_cvt_f32_i32_e32 v3, s2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b32 v2, v[0:1], off
s_waitcnt vmcnt(0)
v_div_scale_f32 v4, null, v3, v3, v2
v_div_scale_f32 v7, vcc_lo, v2, v3, v2
v_rcp_f32_e32 v5, v4
s_waitcnt_depctr 0xfff
v_fma_f32 v6, -v4, v5, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v5, v6, v5
v_mul_f32_e32 v6, v7, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v8, -v4, v6, v7
v_fmac_f32_e32 v6, v8, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v4, -v4, v6, v7
v_div_fmas_f32 v4, v4, v5, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fixup_f32 v2, v4, v3, v2
v_mul_f32_e32 v3, 0x3fb8aa3b, v2
v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fma_f32 v4, v2, 0x3fb8aa3b, -v3
v_rndne_f32_e32 v5, v3
v_dual_fmamk_f32 v4, v2, 0x32a5705f, v4 :: v_dual_sub_f32 v3, v3, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_f32_e32 v3, v3, v4
v_cvt_i32_f32_e32 v4, v5
v_exp_f32_e32 v3, v3
s_waitcnt_depctr 0xfff
v_ldexp_f32 v3, v3, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v3, 0, v3, vcc_lo
v_cmp_nlt_f32_e32 vcc_lo, 0x42b17218, v2
v_cndmask_b32_e32 v2, 0x7f800000, v3, vcc_lo
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z5exponPfi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z5exponPfi, .Lfunc_end0-_Z5exponPfi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z5exponPfi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z5exponPfi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
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