system stringclasses 7 values | input stringlengths 10 94.5k | output stringlengths 14 55.5k |
|---|---|---|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /*
CPU code, still some bugs.
*/
//#include <cuda_runtime.h>
//#include <vector>
//#include <string>
//#include <set>
//
//#include "load_obj.h"
//#include "collision.cuh"
//#include "check.cuh"
//#include "./common/book.h"
//#include "cpu.cuh"
//
//#define COL_MAX_LEN 1000000
//
//void printElapsedTime(cudaEvent_t* start, cudaEvent_t* stop, const char* opname) {
// printf("\nTime of %s: ", opname);
// float elapsedTime;
// HANDLE_ERROR(cudaEventElapsedTime(&elapsedTime, *start, *stop));
// printf("%3.1f ms\n", elapsedTime);
//}
//
//void makeAndPrintSet(unsigned int* data, unsigned int num, const char* title)
//{
// set<unsigned int> dset;
// for (int i = 0; i < num; i++) {
// dset.insert(data[i]);
// }
//
// printf("\n\n%s£¨%u points in total£©:\n", title, dset.size());
// set<unsigned int>::iterator it;
// for (it = dset.begin(); it != dset.end(); it++) {
// printf("%u\n", *it);
// }
//}
//
//int main()
//{
// cudaEvent_t start, stop, m_start, m_stop;
// HANDLE_ERROR(cudaEventCreate(&start));
// HANDLE_ERROR(cudaEventCreate(&stop));
// HANDLE_ERROR(cudaEventCreate(&m_start));
// HANDLE_ERROR(cudaEventCreate(&m_stop));
//
// HANDLE_ERROR(cudaEventRecord(m_start, 0));
//
// const std::string file_path = "F:/¼á¹ûÔÆÎļþ/Îҵļá¹ûÔÆ/ÑÐÒ»ÉÏ/cuda/projects/CollisionDetection/flag-2000-changed.obj";
//
// std::vector<vec3f> vertexes;
// std::vector<Triangle> triangles;
// std::vector<unsigned long long int> mortons;
//
// loadObj(file_path, vertexes, triangles, mortons);
// const unsigned int m_size = mortons.size();
// const unsigned int v_size = vertexes.size();
//
// vec3f* v_ptr = &vertexes[0]; // new vec3f[v_size];
// Triangle* t_ptr = &triangles[0]; // new Triangle[m_size];
// unsigned long long int* m_ptr = &mortons[0]; // new unsigned long long int[m_size];
// Node* leaf_nodes = new Node[m_size];
// Node* internal_nodes = new Node[m_size-1];
// unsigned int* collision_list = new unsigned int[10000];
// unsigned int test_val;
//
// memset(collision_list, 0, 10000 * sizeof(unsigned int));
//
// /* Ìî³äÒ¶½Úµã */
// fillLeafNodesCpu(t_ptr, m_size, leaf_nodes);
//
// /* Éú³ÉBVH */
// printf("\n- before generateHierarchyParallel, wrongParentNum = %u\n", collision_list[0]);
// generateHierarchyParallelCpu(m_ptr, m_size, leaf_nodes, internal_nodes, collision_list);
// printf("\n- generateHierarchyParallel check result: wrongParentNum = %u, with total nodes=%u\n\n", collision_list[0], m_size-1);
//
// /* ¼ÆËã°üΧºÐ */
// calBoundingBoxCpu(leaf_nodes, v_ptr, m_size);
//
// /* ÄÚ²¿½ÚµãºÍÒ¶½Úµã×Ô¼ì */
// memset(collision_list, 0, sizeof(unsigned int) * 5);
// checkInternalNodesCpu(internal_nodes, m_size - 1, &collision_list[0], &collision_list[1], &collision_list[2], &collision_list[3], &collision_list[4]);
// printf("\n- Internal node check result: nullParentnum = %u, wrongBoundCount=%u, nullChildCount=%u, notInternalCount=%u, uninitBoxCount=%u, with total nodes=%u\n\n", collision_list[0], collision_list[1], collision_list[2], collision_list[3], collision_list[4], m_size-1);
//
// memset(collision_list, 0, sizeof(unsigned int) * 5);
// checkLeafNodesCpu(leaf_nodes, m_size, &collision_list[0], &collision_list[1], &collision_list[2], &collision_list[3]);
// printf("\n- Leaf node check result: nullParentnum = %u, nullTriangle=%u, notLeafCount=%u, illegalBoxCount=%u, with total nodes=%u\n\n", collision_list[0], collision_list[1], collision_list[2], collision_list[3], m_size);
//
// memset(collision_list, 0, sizeof(unsigned int) * 5);
// checkTriangleIdxCpu(leaf_nodes, v_ptr, m_size, 632674, &collision_list[0]);
// printf("\n- Triangle check result: illegal triangle vidx num = %u, with total triangles=%u\n\n", collision_list[0], mortons.size());
// printf("\n$ triangle num = %u, mortons num = %u, vertex num = %u\n\n", triangles.size(), mortons.size(), vertexes.size());
//
// /* Ñ°ÕÒÅöײµã¶Ô */
// //findCollisionsCpu(internal_nodes, leaf_nodes, v_ptr, m_size, &test_val, collision_list);
// ////HANDLE_ERROR(cudaMemcpy(temp_nums, test_val, sizeof(unsigned int), cudaMemcpyDeviceToHost));
// ////HANDLE_ERROR(cudaMemcpy(h_collision_list, collision_list, 1000 * sizeof(unsigned int), cudaMemcpyDeviceToHost));
// //printf("\n\n- contact val = %u\n", test_val);
//
// //printf("\nCollision pair (%u triangle pairs in total):\n", test_val);
// //for (int i = 0; i < test_val; i++) {
// // printf("%07u - %07u\n", collision_list[2 * i], collision_list[2 * i + 1]);
// //}
//
// //makeAndPrintSet(collision_list, 2 * test_val, "Collision Triangles:");
//
// std::cout << "- Successfully Return" << std::endl;
//
// HANDLE_ERROR(cudaEventRecord(m_stop, 0)); HANDLE_ERROR(cudaEventSynchronize(m_stop));
// printElapsedTime(&m_start, &m_stop, "Total Time");
//
// printf("\n test for clzll: %u\n", clzll(4567, 1));
//
// //printf("\n test for __builtin_clz: %u\n", __builtin_clz(1278));
//
// return 0;
//} | .file "tmpxft_000ea9df_00000000-6_cpu_main.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /*
CPU code, still some bugs.
*/
//#include <cuda_runtime.h>
//#include <vector>
//#include <string>
//#include <set>
//
//#include "load_obj.h"
//#include "collision.cuh"
//#include "check.cuh"
//#include "./common/book.h"
//#include "cpu.cuh"
//
//#define COL_MAX_LEN 1000000
//
//void printElapsedTime(cudaEvent_t* start, cudaEvent_t* stop, const char* opname) {
// printf("\nTime of %s: ", opname);
// float elapsedTime;
// HANDLE_ERROR(cudaEventElapsedTime(&elapsedTime, *start, *stop));
// printf("%3.1f ms\n", elapsedTime);
//}
//
//void makeAndPrintSet(unsigned int* data, unsigned int num, const char* title)
//{
// set<unsigned int> dset;
// for (int i = 0; i < num; i++) {
// dset.insert(data[i]);
// }
//
// printf("\n\n%s£¨%u points in total£©:\n", title, dset.size());
// set<unsigned int>::iterator it;
// for (it = dset.begin(); it != dset.end(); it++) {
// printf("%u\n", *it);
// }
//}
//
//int main()
//{
// cudaEvent_t start, stop, m_start, m_stop;
// HANDLE_ERROR(cudaEventCreate(&start));
// HANDLE_ERROR(cudaEventCreate(&stop));
// HANDLE_ERROR(cudaEventCreate(&m_start));
// HANDLE_ERROR(cudaEventCreate(&m_stop));
//
// HANDLE_ERROR(cudaEventRecord(m_start, 0));
//
// const std::string file_path = "F:/¼á¹ûÔÆÎļþ/Îҵļá¹ûÔÆ/ÑÐÒ»ÉÏ/cuda/projects/CollisionDetection/flag-2000-changed.obj";
//
// std::vector<vec3f> vertexes;
// std::vector<Triangle> triangles;
// std::vector<unsigned long long int> mortons;
//
// loadObj(file_path, vertexes, triangles, mortons);
// const unsigned int m_size = mortons.size();
// const unsigned int v_size = vertexes.size();
//
// vec3f* v_ptr = &vertexes[0]; // new vec3f[v_size];
// Triangle* t_ptr = &triangles[0]; // new Triangle[m_size];
// unsigned long long int* m_ptr = &mortons[0]; // new unsigned long long int[m_size];
// Node* leaf_nodes = new Node[m_size];
// Node* internal_nodes = new Node[m_size-1];
// unsigned int* collision_list = new unsigned int[10000];
// unsigned int test_val;
//
// memset(collision_list, 0, 10000 * sizeof(unsigned int));
//
// /* Ìî³äÒ¶½Úµã */
// fillLeafNodesCpu(t_ptr, m_size, leaf_nodes);
//
// /* Éú³ÉBVH */
// printf("\n- before generateHierarchyParallel, wrongParentNum = %u\n", collision_list[0]);
// generateHierarchyParallelCpu(m_ptr, m_size, leaf_nodes, internal_nodes, collision_list);
// printf("\n- generateHierarchyParallel check result: wrongParentNum = %u, with total nodes=%u\n\n", collision_list[0], m_size-1);
//
// /* ¼ÆËã°üΧºÐ */
// calBoundingBoxCpu(leaf_nodes, v_ptr, m_size);
//
// /* ÄÚ²¿½ÚµãºÍÒ¶½Úµã×Ô¼ì */
// memset(collision_list, 0, sizeof(unsigned int) * 5);
// checkInternalNodesCpu(internal_nodes, m_size - 1, &collision_list[0], &collision_list[1], &collision_list[2], &collision_list[3], &collision_list[4]);
// printf("\n- Internal node check result: nullParentnum = %u, wrongBoundCount=%u, nullChildCount=%u, notInternalCount=%u, uninitBoxCount=%u, with total nodes=%u\n\n", collision_list[0], collision_list[1], collision_list[2], collision_list[3], collision_list[4], m_size-1);
//
// memset(collision_list, 0, sizeof(unsigned int) * 5);
// checkLeafNodesCpu(leaf_nodes, m_size, &collision_list[0], &collision_list[1], &collision_list[2], &collision_list[3]);
// printf("\n- Leaf node check result: nullParentnum = %u, nullTriangle=%u, notLeafCount=%u, illegalBoxCount=%u, with total nodes=%u\n\n", collision_list[0], collision_list[1], collision_list[2], collision_list[3], m_size);
//
// memset(collision_list, 0, sizeof(unsigned int) * 5);
// checkTriangleIdxCpu(leaf_nodes, v_ptr, m_size, 632674, &collision_list[0]);
// printf("\n- Triangle check result: illegal triangle vidx num = %u, with total triangles=%u\n\n", collision_list[0], mortons.size());
// printf("\n$ triangle num = %u, mortons num = %u, vertex num = %u\n\n", triangles.size(), mortons.size(), vertexes.size());
//
// /* Ñ°ÕÒÅöײµã¶Ô */
// //findCollisionsCpu(internal_nodes, leaf_nodes, v_ptr, m_size, &test_val, collision_list);
// ////HANDLE_ERROR(cudaMemcpy(temp_nums, test_val, sizeof(unsigned int), cudaMemcpyDeviceToHost));
// ////HANDLE_ERROR(cudaMemcpy(h_collision_list, collision_list, 1000 * sizeof(unsigned int), cudaMemcpyDeviceToHost));
// //printf("\n\n- contact val = %u\n", test_val);
//
// //printf("\nCollision pair (%u triangle pairs in total):\n", test_val);
// //for (int i = 0; i < test_val; i++) {
// // printf("%07u - %07u\n", collision_list[2 * i], collision_list[2 * i + 1]);
// //}
//
// //makeAndPrintSet(collision_list, 2 * test_val, "Collision Triangles:");
//
// std::cout << "- Successfully Return" << std::endl;
//
// HANDLE_ERROR(cudaEventRecord(m_stop, 0)); HANDLE_ERROR(cudaEventSynchronize(m_stop));
// printElapsedTime(&m_start, &m_stop, "Total Time");
//
// printf("\n test for clzll: %u\n", clzll(4567, 1));
//
// //printf("\n test for __builtin_clz: %u\n", __builtin_clz(1278));
//
// return 0;
//} | #include <hip/hip_runtime.h>
/*
CPU code, still some bugs.
*/
//#include <cuda_runtime.h>
//#include <vector>
//#include <string>
//#include <set>
//
//#include "load_obj.h"
//#include "collision.cuh"
//#include "check.cuh"
//#include "./common/book.h"
//#include "cpu.cuh"
//
//#define COL_MAX_LEN 1000000
//
//void printElapsedTime(cudaEvent_t* start, cudaEvent_t* stop, const char* opname) {
// printf("\nTime of %s: ", opname);
// float elapsedTime;
// HANDLE_ERROR(cudaEventElapsedTime(&elapsedTime, *start, *stop));
// printf("%3.1f ms\n", elapsedTime);
//}
//
//void makeAndPrintSet(unsigned int* data, unsigned int num, const char* title)
//{
// set<unsigned int> dset;
// for (int i = 0; i < num; i++) {
// dset.insert(data[i]);
// }
//
// printf("\n\n%s£¨%u points in total£©:\n", title, dset.size());
// set<unsigned int>::iterator it;
// for (it = dset.begin(); it != dset.end(); it++) {
// printf("%u\n", *it);
// }
//}
//
//int main()
//{
// cudaEvent_t start, stop, m_start, m_stop;
// HANDLE_ERROR(cudaEventCreate(&start));
// HANDLE_ERROR(cudaEventCreate(&stop));
// HANDLE_ERROR(cudaEventCreate(&m_start));
// HANDLE_ERROR(cudaEventCreate(&m_stop));
//
// HANDLE_ERROR(cudaEventRecord(m_start, 0));
//
// const std::string file_path = "F:/¼á¹ûÔÆÎļþ/Îҵļá¹ûÔÆ/ÑÐÒ»ÉÏ/cuda/projects/CollisionDetection/flag-2000-changed.obj";
//
// std::vector<vec3f> vertexes;
// std::vector<Triangle> triangles;
// std::vector<unsigned long long int> mortons;
//
// loadObj(file_path, vertexes, triangles, mortons);
// const unsigned int m_size = mortons.size();
// const unsigned int v_size = vertexes.size();
//
// vec3f* v_ptr = &vertexes[0]; // new vec3f[v_size];
// Triangle* t_ptr = &triangles[0]; // new Triangle[m_size];
// unsigned long long int* m_ptr = &mortons[0]; // new unsigned long long int[m_size];
// Node* leaf_nodes = new Node[m_size];
// Node* internal_nodes = new Node[m_size-1];
// unsigned int* collision_list = new unsigned int[10000];
// unsigned int test_val;
//
// memset(collision_list, 0, 10000 * sizeof(unsigned int));
//
// /* Ìî³äÒ¶½Úµã */
// fillLeafNodesCpu(t_ptr, m_size, leaf_nodes);
//
// /* Éú³ÉBVH */
// printf("\n- before generateHierarchyParallel, wrongParentNum = %u\n", collision_list[0]);
// generateHierarchyParallelCpu(m_ptr, m_size, leaf_nodes, internal_nodes, collision_list);
// printf("\n- generateHierarchyParallel check result: wrongParentNum = %u, with total nodes=%u\n\n", collision_list[0], m_size-1);
//
// /* ¼ÆËã°üΧºÐ */
// calBoundingBoxCpu(leaf_nodes, v_ptr, m_size);
//
// /* ÄÚ²¿½ÚµãºÍÒ¶½Úµã×Ô¼ì */
// memset(collision_list, 0, sizeof(unsigned int) * 5);
// checkInternalNodesCpu(internal_nodes, m_size - 1, &collision_list[0], &collision_list[1], &collision_list[2], &collision_list[3], &collision_list[4]);
// printf("\n- Internal node check result: nullParentnum = %u, wrongBoundCount=%u, nullChildCount=%u, notInternalCount=%u, uninitBoxCount=%u, with total nodes=%u\n\n", collision_list[0], collision_list[1], collision_list[2], collision_list[3], collision_list[4], m_size-1);
//
// memset(collision_list, 0, sizeof(unsigned int) * 5);
// checkLeafNodesCpu(leaf_nodes, m_size, &collision_list[0], &collision_list[1], &collision_list[2], &collision_list[3]);
// printf("\n- Leaf node check result: nullParentnum = %u, nullTriangle=%u, notLeafCount=%u, illegalBoxCount=%u, with total nodes=%u\n\n", collision_list[0], collision_list[1], collision_list[2], collision_list[3], m_size);
//
// memset(collision_list, 0, sizeof(unsigned int) * 5);
// checkTriangleIdxCpu(leaf_nodes, v_ptr, m_size, 632674, &collision_list[0]);
// printf("\n- Triangle check result: illegal triangle vidx num = %u, with total triangles=%u\n\n", collision_list[0], mortons.size());
// printf("\n$ triangle num = %u, mortons num = %u, vertex num = %u\n\n", triangles.size(), mortons.size(), vertexes.size());
//
// /* Ñ°ÕÒÅöײµã¶Ô */
// //findCollisionsCpu(internal_nodes, leaf_nodes, v_ptr, m_size, &test_val, collision_list);
// ////HANDLE_ERROR(cudaMemcpy(temp_nums, test_val, sizeof(unsigned int), cudaMemcpyDeviceToHost));
// ////HANDLE_ERROR(cudaMemcpy(h_collision_list, collision_list, 1000 * sizeof(unsigned int), cudaMemcpyDeviceToHost));
// //printf("\n\n- contact val = %u\n", test_val);
//
// //printf("\nCollision pair (%u triangle pairs in total):\n", test_val);
// //for (int i = 0; i < test_val; i++) {
// // printf("%07u - %07u\n", collision_list[2 * i], collision_list[2 * i + 1]);
// //}
//
// //makeAndPrintSet(collision_list, 2 * test_val, "Collision Triangles:");
//
// std::cout << "- Successfully Return" << std::endl;
//
// HANDLE_ERROR(cudaEventRecord(m_stop, 0)); HANDLE_ERROR(cudaEventSynchronize(m_stop));
// printElapsedTime(&m_start, &m_stop, "Total Time");
//
// printf("\n test for clzll: %u\n", clzll(4567, 1));
//
// //printf("\n test for __builtin_clz: %u\n", __builtin_clz(1278));
//
// return 0;
//} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
/*
CPU code, still some bugs.
*/
//#include <cuda_runtime.h>
//#include <vector>
//#include <string>
//#include <set>
//
//#include "load_obj.h"
//#include "collision.cuh"
//#include "check.cuh"
//#include "./common/book.h"
//#include "cpu.cuh"
//
//#define COL_MAX_LEN 1000000
//
//void printElapsedTime(cudaEvent_t* start, cudaEvent_t* stop, const char* opname) {
// printf("\nTime of %s: ", opname);
// float elapsedTime;
// HANDLE_ERROR(cudaEventElapsedTime(&elapsedTime, *start, *stop));
// printf("%3.1f ms\n", elapsedTime);
//}
//
//void makeAndPrintSet(unsigned int* data, unsigned int num, const char* title)
//{
// set<unsigned int> dset;
// for (int i = 0; i < num; i++) {
// dset.insert(data[i]);
// }
//
// printf("\n\n%s£¨%u points in total£©:\n", title, dset.size());
// set<unsigned int>::iterator it;
// for (it = dset.begin(); it != dset.end(); it++) {
// printf("%u\n", *it);
// }
//}
//
//int main()
//{
// cudaEvent_t start, stop, m_start, m_stop;
// HANDLE_ERROR(cudaEventCreate(&start));
// HANDLE_ERROR(cudaEventCreate(&stop));
// HANDLE_ERROR(cudaEventCreate(&m_start));
// HANDLE_ERROR(cudaEventCreate(&m_stop));
//
// HANDLE_ERROR(cudaEventRecord(m_start, 0));
//
// const std::string file_path = "F:/¼á¹ûÔÆÎļþ/Îҵļá¹ûÔÆ/ÑÐÒ»ÉÏ/cuda/projects/CollisionDetection/flag-2000-changed.obj";
//
// std::vector<vec3f> vertexes;
// std::vector<Triangle> triangles;
// std::vector<unsigned long long int> mortons;
//
// loadObj(file_path, vertexes, triangles, mortons);
// const unsigned int m_size = mortons.size();
// const unsigned int v_size = vertexes.size();
//
// vec3f* v_ptr = &vertexes[0]; // new vec3f[v_size];
// Triangle* t_ptr = &triangles[0]; // new Triangle[m_size];
// unsigned long long int* m_ptr = &mortons[0]; // new unsigned long long int[m_size];
// Node* leaf_nodes = new Node[m_size];
// Node* internal_nodes = new Node[m_size-1];
// unsigned int* collision_list = new unsigned int[10000];
// unsigned int test_val;
//
// memset(collision_list, 0, 10000 * sizeof(unsigned int));
//
// /* Ìî³äÒ¶½Úµã */
// fillLeafNodesCpu(t_ptr, m_size, leaf_nodes);
//
// /* Éú³ÉBVH */
// printf("\n- before generateHierarchyParallel, wrongParentNum = %u\n", collision_list[0]);
// generateHierarchyParallelCpu(m_ptr, m_size, leaf_nodes, internal_nodes, collision_list);
// printf("\n- generateHierarchyParallel check result: wrongParentNum = %u, with total nodes=%u\n\n", collision_list[0], m_size-1);
//
// /* ¼ÆËã°üΧºÐ */
// calBoundingBoxCpu(leaf_nodes, v_ptr, m_size);
//
// /* ÄÚ²¿½ÚµãºÍÒ¶½Úµã×Ô¼ì */
// memset(collision_list, 0, sizeof(unsigned int) * 5);
// checkInternalNodesCpu(internal_nodes, m_size - 1, &collision_list[0], &collision_list[1], &collision_list[2], &collision_list[3], &collision_list[4]);
// printf("\n- Internal node check result: nullParentnum = %u, wrongBoundCount=%u, nullChildCount=%u, notInternalCount=%u, uninitBoxCount=%u, with total nodes=%u\n\n", collision_list[0], collision_list[1], collision_list[2], collision_list[3], collision_list[4], m_size-1);
//
// memset(collision_list, 0, sizeof(unsigned int) * 5);
// checkLeafNodesCpu(leaf_nodes, m_size, &collision_list[0], &collision_list[1], &collision_list[2], &collision_list[3]);
// printf("\n- Leaf node check result: nullParentnum = %u, nullTriangle=%u, notLeafCount=%u, illegalBoxCount=%u, with total nodes=%u\n\n", collision_list[0], collision_list[1], collision_list[2], collision_list[3], m_size);
//
// memset(collision_list, 0, sizeof(unsigned int) * 5);
// checkTriangleIdxCpu(leaf_nodes, v_ptr, m_size, 632674, &collision_list[0]);
// printf("\n- Triangle check result: illegal triangle vidx num = %u, with total triangles=%u\n\n", collision_list[0], mortons.size());
// printf("\n$ triangle num = %u, mortons num = %u, vertex num = %u\n\n", triangles.size(), mortons.size(), vertexes.size());
//
// /* Ñ°ÕÒÅöײµã¶Ô */
// //findCollisionsCpu(internal_nodes, leaf_nodes, v_ptr, m_size, &test_val, collision_list);
// ////HANDLE_ERROR(cudaMemcpy(temp_nums, test_val, sizeof(unsigned int), cudaMemcpyDeviceToHost));
// ////HANDLE_ERROR(cudaMemcpy(h_collision_list, collision_list, 1000 * sizeof(unsigned int), cudaMemcpyDeviceToHost));
// //printf("\n\n- contact val = %u\n", test_val);
//
// //printf("\nCollision pair (%u triangle pairs in total):\n", test_val);
// //for (int i = 0; i < test_val; i++) {
// // printf("%07u - %07u\n", collision_list[2 * i], collision_list[2 * i + 1]);
// //}
//
// //makeAndPrintSet(collision_list, 2 * test_val, "Collision Triangles:");
//
// std::cout << "- Successfully Return" << std::endl;
//
// HANDLE_ERROR(cudaEventRecord(m_stop, 0)); HANDLE_ERROR(cudaEventSynchronize(m_stop));
// printElapsedTime(&m_start, &m_stop, "Total Time");
//
// printf("\n test for clzll: %u\n", clzll(4567, 1));
//
// //printf("\n test for __builtin_clz: %u\n", __builtin_clz(1278));
//
// return 0;
//} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
/*
CPU code, still some bugs.
*/
//#include <cuda_runtime.h>
//#include <vector>
//#include <string>
//#include <set>
//
//#include "load_obj.h"
//#include "collision.cuh"
//#include "check.cuh"
//#include "./common/book.h"
//#include "cpu.cuh"
//
//#define COL_MAX_LEN 1000000
//
//void printElapsedTime(cudaEvent_t* start, cudaEvent_t* stop, const char* opname) {
// printf("\nTime of %s: ", opname);
// float elapsedTime;
// HANDLE_ERROR(cudaEventElapsedTime(&elapsedTime, *start, *stop));
// printf("%3.1f ms\n", elapsedTime);
//}
//
//void makeAndPrintSet(unsigned int* data, unsigned int num, const char* title)
//{
// set<unsigned int> dset;
// for (int i = 0; i < num; i++) {
// dset.insert(data[i]);
// }
//
// printf("\n\n%s£¨%u points in total£©:\n", title, dset.size());
// set<unsigned int>::iterator it;
// for (it = dset.begin(); it != dset.end(); it++) {
// printf("%u\n", *it);
// }
//}
//
//int main()
//{
// cudaEvent_t start, stop, m_start, m_stop;
// HANDLE_ERROR(cudaEventCreate(&start));
// HANDLE_ERROR(cudaEventCreate(&stop));
// HANDLE_ERROR(cudaEventCreate(&m_start));
// HANDLE_ERROR(cudaEventCreate(&m_stop));
//
// HANDLE_ERROR(cudaEventRecord(m_start, 0));
//
// const std::string file_path = "F:/¼á¹ûÔÆÎļþ/Îҵļá¹ûÔÆ/ÑÐÒ»ÉÏ/cuda/projects/CollisionDetection/flag-2000-changed.obj";
//
// std::vector<vec3f> vertexes;
// std::vector<Triangle> triangles;
// std::vector<unsigned long long int> mortons;
//
// loadObj(file_path, vertexes, triangles, mortons);
// const unsigned int m_size = mortons.size();
// const unsigned int v_size = vertexes.size();
//
// vec3f* v_ptr = &vertexes[0]; // new vec3f[v_size];
// Triangle* t_ptr = &triangles[0]; // new Triangle[m_size];
// unsigned long long int* m_ptr = &mortons[0]; // new unsigned long long int[m_size];
// Node* leaf_nodes = new Node[m_size];
// Node* internal_nodes = new Node[m_size-1];
// unsigned int* collision_list = new unsigned int[10000];
// unsigned int test_val;
//
// memset(collision_list, 0, 10000 * sizeof(unsigned int));
//
// /* Ìî³äÒ¶½Úµã */
// fillLeafNodesCpu(t_ptr, m_size, leaf_nodes);
//
// /* Éú³ÉBVH */
// printf("\n- before generateHierarchyParallel, wrongParentNum = %u\n", collision_list[0]);
// generateHierarchyParallelCpu(m_ptr, m_size, leaf_nodes, internal_nodes, collision_list);
// printf("\n- generateHierarchyParallel check result: wrongParentNum = %u, with total nodes=%u\n\n", collision_list[0], m_size-1);
//
// /* ¼ÆËã°üΧºÐ */
// calBoundingBoxCpu(leaf_nodes, v_ptr, m_size);
//
// /* ÄÚ²¿½ÚµãºÍÒ¶½Úµã×Ô¼ì */
// memset(collision_list, 0, sizeof(unsigned int) * 5);
// checkInternalNodesCpu(internal_nodes, m_size - 1, &collision_list[0], &collision_list[1], &collision_list[2], &collision_list[3], &collision_list[4]);
// printf("\n- Internal node check result: nullParentnum = %u, wrongBoundCount=%u, nullChildCount=%u, notInternalCount=%u, uninitBoxCount=%u, with total nodes=%u\n\n", collision_list[0], collision_list[1], collision_list[2], collision_list[3], collision_list[4], m_size-1);
//
// memset(collision_list, 0, sizeof(unsigned int) * 5);
// checkLeafNodesCpu(leaf_nodes, m_size, &collision_list[0], &collision_list[1], &collision_list[2], &collision_list[3]);
// printf("\n- Leaf node check result: nullParentnum = %u, nullTriangle=%u, notLeafCount=%u, illegalBoxCount=%u, with total nodes=%u\n\n", collision_list[0], collision_list[1], collision_list[2], collision_list[3], m_size);
//
// memset(collision_list, 0, sizeof(unsigned int) * 5);
// checkTriangleIdxCpu(leaf_nodes, v_ptr, m_size, 632674, &collision_list[0]);
// printf("\n- Triangle check result: illegal triangle vidx num = %u, with total triangles=%u\n\n", collision_list[0], mortons.size());
// printf("\n$ triangle num = %u, mortons num = %u, vertex num = %u\n\n", triangles.size(), mortons.size(), vertexes.size());
//
// /* Ñ°ÕÒÅöײµã¶Ô */
// //findCollisionsCpu(internal_nodes, leaf_nodes, v_ptr, m_size, &test_val, collision_list);
// ////HANDLE_ERROR(cudaMemcpy(temp_nums, test_val, sizeof(unsigned int), cudaMemcpyDeviceToHost));
// ////HANDLE_ERROR(cudaMemcpy(h_collision_list, collision_list, 1000 * sizeof(unsigned int), cudaMemcpyDeviceToHost));
// //printf("\n\n- contact val = %u\n", test_val);
//
// //printf("\nCollision pair (%u triangle pairs in total):\n", test_val);
// //for (int i = 0; i < test_val; i++) {
// // printf("%07u - %07u\n", collision_list[2 * i], collision_list[2 * i + 1]);
// //}
//
// //makeAndPrintSet(collision_list, 2 * test_val, "Collision Triangles:");
//
// std::cout << "- Successfully Return" << std::endl;
//
// HANDLE_ERROR(cudaEventRecord(m_stop, 0)); HANDLE_ERROR(cudaEventSynchronize(m_stop));
// printElapsedTime(&m_start, &m_stop, "Total Time");
//
// printf("\n test for clzll: %u\n", clzll(4567, 1));
//
// //printf("\n test for __builtin_clz: %u\n", __builtin_clz(1278));
//
// return 0;
//} | .text
.file "cpu_main.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000ea9df_00000000-6_cpu_main.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "cpu_main.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void kGreaterThanEqScalar(float* mat, float val, float* target, unsigned int len) {
const unsigned int idx = blockIdx.x * blockDim.x + threadIdx.x;
const unsigned int numThreads = blockDim.x * gridDim.x;
for (unsigned int i = idx; i < len; i += numThreads) target[i] = mat[i] >= val;
} | code for sm_80
Function : _Z20kGreaterThanEqScalarPffS_j
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x178], PT ; /* 0x00005e0000007a0c */
/* 0x000fda0003f06070 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0070*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x001fd400000001ff */
/*0080*/ IMAD.WIDE.U32 R2, R0, R5, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fcc00078e0005 */
/*0090*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ IMAD.WIDE.U32 R4, R0, R5, c[0x0][0x170] ; /* 0x00005c0000047625 */
/* 0x000fe200078e0005 */
/*00b0*/ MOV R9, c[0x0][0x0] ; /* 0x0000000000097a02 */
/* 0x000fca0000000f00 */
/*00c0*/ IMAD R0, R9, c[0x0][0xc], R0 ; /* 0x0000030009007a24 */
/* 0x000fca00078e0200 */
/*00d0*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x178], PT ; /* 0x00005e0000007a0c */
/* 0x000fe40003f06070 */
/*00e0*/ FSET.BF.GE.AND R7, R2, c[0x0][0x168], PT ; /* 0x00005a0002077a0a */
/* 0x004fca0003806000 */
/*00f0*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x0001ec000c101904 */
/*0100*/ @!P0 BRA 0x70 ; /* 0xffffff6000008947 */
/* 0x000fea000383ffff */
/*0110*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0120*/ BRA 0x120; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void kGreaterThanEqScalar(float* mat, float val, float* target, unsigned int len) {
const unsigned int idx = blockIdx.x * blockDim.x + threadIdx.x;
const unsigned int numThreads = blockDim.x * gridDim.x;
for (unsigned int i = idx; i < len; i += numThreads) target[i] = mat[i] >= val;
} | .file "tmpxft_001b23a4_00000000-6_kGreaterThanEqScalar.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z44__device_stub__Z20kGreaterThanEqScalarPffS_jPffS_j
.type _Z44__device_stub__Z20kGreaterThanEqScalarPffS_jPffS_j, @function
_Z44__device_stub__Z20kGreaterThanEqScalarPffS_jPffS_j:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movss %xmm0, 20(%rsp)
movq %rsi, 8(%rsp)
movl %edx, 16(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 16(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z20kGreaterThanEqScalarPffS_j(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z44__device_stub__Z20kGreaterThanEqScalarPffS_jPffS_j, .-_Z44__device_stub__Z20kGreaterThanEqScalarPffS_jPffS_j
.globl _Z20kGreaterThanEqScalarPffS_j
.type _Z20kGreaterThanEqScalarPffS_j, @function
_Z20kGreaterThanEqScalarPffS_j:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z44__device_stub__Z20kGreaterThanEqScalarPffS_jPffS_j
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z20kGreaterThanEqScalarPffS_j, .-_Z20kGreaterThanEqScalarPffS_j
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z20kGreaterThanEqScalarPffS_j"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z20kGreaterThanEqScalarPffS_j(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void kGreaterThanEqScalar(float* mat, float val, float* target, unsigned int len) {
const unsigned int idx = blockIdx.x * blockDim.x + threadIdx.x;
const unsigned int numThreads = blockDim.x * gridDim.x;
for (unsigned int i = idx; i < len; i += numThreads) target[i] = mat[i] >= val;
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void kGreaterThanEqScalar(float* mat, float val, float* target, unsigned int len) {
const unsigned int idx = blockIdx.x * blockDim.x + threadIdx.x;
const unsigned int numThreads = blockDim.x * gridDim.x;
for (unsigned int i = idx; i < len; i += numThreads) target[i] = mat[i] >= val;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void kGreaterThanEqScalar(float* mat, float val, float* target, unsigned int len) {
const unsigned int idx = blockIdx.x * blockDim.x + threadIdx.x;
const unsigned int numThreads = blockDim.x * gridDim.x;
for (unsigned int i = idx; i < len; i += numThreads) target[i] = mat[i] >= val;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z20kGreaterThanEqScalarPffS_j
.globl _Z20kGreaterThanEqScalarPffS_j
.p2align 8
.type _Z20kGreaterThanEqScalarPffS_j,@function
_Z20kGreaterThanEqScalarPffS_j:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x2c
s_load_b32 s6, s[0:1], 0x18
s_add_u32 s2, s0, 32
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s8, s4, 0xffff
s_mov_b32 s4, exec_lo
v_mad_u64_u32 v[1:2], null, s15, s8, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_u32_e64 s6, v1
s_cbranch_execz .LBB0_3
s_load_b32 s9, s[2:3], 0x0
s_clause 0x2
s_load_b64 s[2:3], s[0:1], 0x0
s_load_b32 s7, s[0:1], 0x8
s_load_b64 s[4:5], s[0:1], 0x10
v_mov_b32_e32 v2, 0
s_waitcnt lgkmcnt(0)
s_mul_i32 s1, s9, s8
s_mov_b32 s8, 0
.p2align 6
.LBB0_2:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[3:4], 2, v[1:2]
v_add_nc_u32_e32 v1, s1, v1
v_add_co_u32 v5, vcc_lo, s2, v3
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v6, vcc_lo, s3, v4, vcc_lo
v_add_co_u32 v3, s0, s4, v3
v_add_co_ci_u32_e64 v4, s0, s5, v4, s0
global_load_b32 v0, v[5:6], off
v_cmp_le_u32_e32 vcc_lo, s6, v1
s_or_b32 s8, vcc_lo, s8
s_waitcnt vmcnt(0)
v_cmp_le_f32_e64 s0, s7, v0
s_delay_alu instid0(VALU_DEP_1)
v_cndmask_b32_e64 v0, 0, 1.0, s0
global_store_b32 v[3:4], v0, off
s_and_not1_b32 exec_lo, exec_lo, s8
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z20kGreaterThanEqScalarPffS_j
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z20kGreaterThanEqScalarPffS_j, .Lfunc_end0-_Z20kGreaterThanEqScalarPffS_j
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z20kGreaterThanEqScalarPffS_j
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z20kGreaterThanEqScalarPffS_j.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void kGreaterThanEqScalar(float* mat, float val, float* target, unsigned int len) {
const unsigned int idx = blockIdx.x * blockDim.x + threadIdx.x;
const unsigned int numThreads = blockDim.x * gridDim.x;
for (unsigned int i = idx; i < len; i += numThreads) target[i] = mat[i] >= val;
} | .text
.file "kGreaterThanEqScalar.hip"
.globl _Z35__device_stub__kGreaterThanEqScalarPffS_j # -- Begin function _Z35__device_stub__kGreaterThanEqScalarPffS_j
.p2align 4, 0x90
.type _Z35__device_stub__kGreaterThanEqScalarPffS_j,@function
_Z35__device_stub__kGreaterThanEqScalarPffS_j: # @_Z35__device_stub__kGreaterThanEqScalarPffS_j
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movss %xmm0, 12(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z20kGreaterThanEqScalarPffS_j, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z35__device_stub__kGreaterThanEqScalarPffS_j, .Lfunc_end0-_Z35__device_stub__kGreaterThanEqScalarPffS_j
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z20kGreaterThanEqScalarPffS_j, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z20kGreaterThanEqScalarPffS_j,@object # @_Z20kGreaterThanEqScalarPffS_j
.section .rodata,"a",@progbits
.globl _Z20kGreaterThanEqScalarPffS_j
.p2align 3, 0x0
_Z20kGreaterThanEqScalarPffS_j:
.quad _Z35__device_stub__kGreaterThanEqScalarPffS_j
.size _Z20kGreaterThanEqScalarPffS_j, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z20kGreaterThanEqScalarPffS_j"
.size .L__unnamed_1, 31
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z35__device_stub__kGreaterThanEqScalarPffS_j
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z20kGreaterThanEqScalarPffS_j
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z20kGreaterThanEqScalarPffS_j
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x178], PT ; /* 0x00005e0000007a0c */
/* 0x000fda0003f06070 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0070*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x001fd400000001ff */
/*0080*/ IMAD.WIDE.U32 R2, R0, R5, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fcc00078e0005 */
/*0090*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ IMAD.WIDE.U32 R4, R0, R5, c[0x0][0x170] ; /* 0x00005c0000047625 */
/* 0x000fe200078e0005 */
/*00b0*/ MOV R9, c[0x0][0x0] ; /* 0x0000000000097a02 */
/* 0x000fca0000000f00 */
/*00c0*/ IMAD R0, R9, c[0x0][0xc], R0 ; /* 0x0000030009007a24 */
/* 0x000fca00078e0200 */
/*00d0*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x178], PT ; /* 0x00005e0000007a0c */
/* 0x000fe40003f06070 */
/*00e0*/ FSET.BF.GE.AND R7, R2, c[0x0][0x168], PT ; /* 0x00005a0002077a0a */
/* 0x004fca0003806000 */
/*00f0*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x0001ec000c101904 */
/*0100*/ @!P0 BRA 0x70 ; /* 0xffffff6000008947 */
/* 0x000fea000383ffff */
/*0110*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0120*/ BRA 0x120; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z20kGreaterThanEqScalarPffS_j
.globl _Z20kGreaterThanEqScalarPffS_j
.p2align 8
.type _Z20kGreaterThanEqScalarPffS_j,@function
_Z20kGreaterThanEqScalarPffS_j:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x2c
s_load_b32 s6, s[0:1], 0x18
s_add_u32 s2, s0, 32
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s8, s4, 0xffff
s_mov_b32 s4, exec_lo
v_mad_u64_u32 v[1:2], null, s15, s8, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_u32_e64 s6, v1
s_cbranch_execz .LBB0_3
s_load_b32 s9, s[2:3], 0x0
s_clause 0x2
s_load_b64 s[2:3], s[0:1], 0x0
s_load_b32 s7, s[0:1], 0x8
s_load_b64 s[4:5], s[0:1], 0x10
v_mov_b32_e32 v2, 0
s_waitcnt lgkmcnt(0)
s_mul_i32 s1, s9, s8
s_mov_b32 s8, 0
.p2align 6
.LBB0_2:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[3:4], 2, v[1:2]
v_add_nc_u32_e32 v1, s1, v1
v_add_co_u32 v5, vcc_lo, s2, v3
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v6, vcc_lo, s3, v4, vcc_lo
v_add_co_u32 v3, s0, s4, v3
v_add_co_ci_u32_e64 v4, s0, s5, v4, s0
global_load_b32 v0, v[5:6], off
v_cmp_le_u32_e32 vcc_lo, s6, v1
s_or_b32 s8, vcc_lo, s8
s_waitcnt vmcnt(0)
v_cmp_le_f32_e64 s0, s7, v0
s_delay_alu instid0(VALU_DEP_1)
v_cndmask_b32_e64 v0, 0, 1.0, s0
global_store_b32 v[3:4], v0, off
s_and_not1_b32 exec_lo, exec_lo, s8
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z20kGreaterThanEqScalarPffS_j
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z20kGreaterThanEqScalarPffS_j, .Lfunc_end0-_Z20kGreaterThanEqScalarPffS_j
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z20kGreaterThanEqScalarPffS_j
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z20kGreaterThanEqScalarPffS_j.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001b23a4_00000000-6_kGreaterThanEqScalar.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z44__device_stub__Z20kGreaterThanEqScalarPffS_jPffS_j
.type _Z44__device_stub__Z20kGreaterThanEqScalarPffS_jPffS_j, @function
_Z44__device_stub__Z20kGreaterThanEqScalarPffS_jPffS_j:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movss %xmm0, 20(%rsp)
movq %rsi, 8(%rsp)
movl %edx, 16(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 16(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z20kGreaterThanEqScalarPffS_j(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z44__device_stub__Z20kGreaterThanEqScalarPffS_jPffS_j, .-_Z44__device_stub__Z20kGreaterThanEqScalarPffS_jPffS_j
.globl _Z20kGreaterThanEqScalarPffS_j
.type _Z20kGreaterThanEqScalarPffS_j, @function
_Z20kGreaterThanEqScalarPffS_j:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z44__device_stub__Z20kGreaterThanEqScalarPffS_jPffS_j
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z20kGreaterThanEqScalarPffS_j, .-_Z20kGreaterThanEqScalarPffS_j
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z20kGreaterThanEqScalarPffS_j"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z20kGreaterThanEqScalarPffS_j(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "kGreaterThanEqScalar.hip"
.globl _Z35__device_stub__kGreaterThanEqScalarPffS_j # -- Begin function _Z35__device_stub__kGreaterThanEqScalarPffS_j
.p2align 4, 0x90
.type _Z35__device_stub__kGreaterThanEqScalarPffS_j,@function
_Z35__device_stub__kGreaterThanEqScalarPffS_j: # @_Z35__device_stub__kGreaterThanEqScalarPffS_j
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movss %xmm0, 12(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z20kGreaterThanEqScalarPffS_j, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z35__device_stub__kGreaterThanEqScalarPffS_j, .Lfunc_end0-_Z35__device_stub__kGreaterThanEqScalarPffS_j
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z20kGreaterThanEqScalarPffS_j, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z20kGreaterThanEqScalarPffS_j,@object # @_Z20kGreaterThanEqScalarPffS_j
.section .rodata,"a",@progbits
.globl _Z20kGreaterThanEqScalarPffS_j
.p2align 3, 0x0
_Z20kGreaterThanEqScalarPffS_j:
.quad _Z35__device_stub__kGreaterThanEqScalarPffS_j
.size _Z20kGreaterThanEqScalarPffS_j, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z20kGreaterThanEqScalarPffS_j"
.size .L__unnamed_1, 31
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z35__device_stub__kGreaterThanEqScalarPffS_j
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z20kGreaterThanEqScalarPffS_j
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdlib.h>
#include <stdio.h>
#include <time.h>
/* Every thread gets exactly one value in the unsorted array. */
#define THREADS 128 // 2^7
#define BLOCKS 1024 // 2^10
#define NUM_VALS THREADS*BLOCKS
void print_elapsed(clock_t start, clock_t stop)
{
double elapsed = ((double) (stop - start)) / CLOCKS_PER_SEC;
printf("Elapsed time: %.3fs\n", elapsed);
}
__global__ void bitonic_sort_step(int *dev_values, int j, int k)
{
unsigned int i, ixj; /* Sorting partners: i and ixj */
i = threadIdx.x + blockDim.x * blockIdx.x;
ixj = i^j;
/* The threads with the lowest ids sort the array. */
if ((ixj)>i) {
if ((i&k)==0) {
/* Sort ascending */
if (dev_values[i]>dev_values[ixj]) {
// swap
int temp = dev_values[i];
dev_values[i] = dev_values[ixj];
dev_values[ixj] = temp;
}
}
if ((i&k)!=0) {
/* Sort descending */
if (dev_values[i]<dev_values[ixj]) {
// swap
int temp = dev_values[i];
dev_values[i] = dev_values[ixj];
dev_values[ixj] = temp;
}
}
}
}
void bitonic_sort(int *values)
{
int *dev_values;
size_t size = NUM_VALS * sizeof(int);
cudaMalloc((void**) &dev_values, size);
cudaMemcpy(dev_values, values, size, cudaMemcpyHostToDevice);
dim3 blocks(BLOCKS,1);
dim3 threads(THREADS,1);
int j, k;
/* Major step */
for (k = 2; k <= NUM_VALS; k <<= 1) {
/* Minor step */
for (j=k>>1; j>0; j=j>>1) {
bitonic_sort_step<<<blocks, threads>>>(dev_values, j, k);
}
}
cudaMemcpy(values, dev_values, size, cudaMemcpyDeviceToHost);
cudaFree(dev_values);
}
int main(int argc, char const *argv[])
{
clock_t start, stop;
int *values = (int*)malloc(NUM_VALS * sizeof(int));
FILE *f = fopen("reverse_dataset.txt", "r");
for(int i=0;i< NUM_VALS; i++) {
fscanf(f, "%d\n", &values[i]);
}
start = clock();
bitonic_sort(values);
stop = clock();
print_elapsed(start, stop);
return 0;
} | code for sm_80
Function : _Z17bitonic_sort_stepPiii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ LOP3.LUT R5, R0, c[0x0][0x168], RZ, 0x3c, !PT ; /* 0x00005a0000057a12 */
/* 0x000fc800078e3cff */
/*0050*/ ISETP.GT.U32.AND P0, PT, R5, R0, PT ; /* 0x000000000500720c */
/* 0x000fda0003f04070 */
/*0060*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0070*/ IMAD.MOV.U32 R4, RZ, RZ, 0x4 ; /* 0x00000004ff047424 */
/* 0x000fe200078e00ff */
/*0080*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0090*/ IMAD.WIDE.U32 R2, R0, R4, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fc800078e0004 */
/*00a0*/ IMAD.WIDE.U32 R4, R5, R4, c[0x0][0x160] ; /* 0x0000580005047625 */
/* 0x000fe200078e0004 */
/*00b0*/ LDG.E R7, [R2.64] ; /* 0x0000000402077981 */
/* 0x000168000c1e1900 */
/*00c0*/ LDG.E R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000162000c1e1900 */
/*00d0*/ LOP3.LUT P0, RZ, R0, c[0x0][0x16c], RZ, 0xc0, !PT ; /* 0x00005b0000ff7a12 */
/* 0x000fda000780c0ff */
/*00e0*/ @!P0 BRA 0x140 ; /* 0x0000005000008947 */
/* 0x000fea0003800000 */
/*00f0*/ ISETP.GE.AND P0, PT, R7, R6, PT ; /* 0x000000060700720c */
/* 0x021fda0003f06270 */
/*0100*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0110*/ STG.E [R2.64], R6 ; /* 0x0000000602007986 */
/* 0x000fe8000c101904 */
/*0120*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x000fe2000c101904 */
/*0130*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0140*/ ISETP.GT.AND P0, PT, R7, R6, PT ; /* 0x000000060700720c */
/* 0x021fda0003f04270 */
/*0150*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0160*/ STG.E [R2.64], R6 ; /* 0x0000000602007986 */
/* 0x000fe8000c101904 */
/*0170*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x000fe2000c101904 */
/*0180*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0190*/ BRA 0x190; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdlib.h>
#include <stdio.h>
#include <time.h>
/* Every thread gets exactly one value in the unsorted array. */
#define THREADS 128 // 2^7
#define BLOCKS 1024 // 2^10
#define NUM_VALS THREADS*BLOCKS
void print_elapsed(clock_t start, clock_t stop)
{
double elapsed = ((double) (stop - start)) / CLOCKS_PER_SEC;
printf("Elapsed time: %.3fs\n", elapsed);
}
__global__ void bitonic_sort_step(int *dev_values, int j, int k)
{
unsigned int i, ixj; /* Sorting partners: i and ixj */
i = threadIdx.x + blockDim.x * blockIdx.x;
ixj = i^j;
/* The threads with the lowest ids sort the array. */
if ((ixj)>i) {
if ((i&k)==0) {
/* Sort ascending */
if (dev_values[i]>dev_values[ixj]) {
// swap
int temp = dev_values[i];
dev_values[i] = dev_values[ixj];
dev_values[ixj] = temp;
}
}
if ((i&k)!=0) {
/* Sort descending */
if (dev_values[i]<dev_values[ixj]) {
// swap
int temp = dev_values[i];
dev_values[i] = dev_values[ixj];
dev_values[ixj] = temp;
}
}
}
}
void bitonic_sort(int *values)
{
int *dev_values;
size_t size = NUM_VALS * sizeof(int);
cudaMalloc((void**) &dev_values, size);
cudaMemcpy(dev_values, values, size, cudaMemcpyHostToDevice);
dim3 blocks(BLOCKS,1);
dim3 threads(THREADS,1);
int j, k;
/* Major step */
for (k = 2; k <= NUM_VALS; k <<= 1) {
/* Minor step */
for (j=k>>1; j>0; j=j>>1) {
bitonic_sort_step<<<blocks, threads>>>(dev_values, j, k);
}
}
cudaMemcpy(values, dev_values, size, cudaMemcpyDeviceToHost);
cudaFree(dev_values);
}
int main(int argc, char const *argv[])
{
clock_t start, stop;
int *values = (int*)malloc(NUM_VALS * sizeof(int));
FILE *f = fopen("reverse_dataset.txt", "r");
for(int i=0;i< NUM_VALS; i++) {
fscanf(f, "%d\n", &values[i]);
}
start = clock();
bitonic_sort(values);
stop = clock();
print_elapsed(start, stop);
return 0;
} | .file "tmpxft_00117c73_00000000-6_bitonic_sort.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "Elapsed time: %.3fs\n"
.text
.globl _Z13print_elapsedll
.type _Z13print_elapsedll, @function
_Z13print_elapsedll:
.LFB2057:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
subq %rdi, %rsi
pxor %xmm0, %xmm0
cvtsi2sdq %rsi, %xmm0
divsd .LC0(%rip), %xmm0
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _Z13print_elapsedll, .-_Z13print_elapsedll
.globl _Z39__device_stub__Z17bitonic_sort_stepPiiiPiii
.type _Z39__device_stub__Z17bitonic_sort_stepPiiiPiii, @function
_Z39__device_stub__Z17bitonic_sort_stepPiiiPiii:
.LFB2084:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L9
.L5:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L10
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z17bitonic_sort_stepPiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L5
.L10:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z39__device_stub__Z17bitonic_sort_stepPiiiPiii, .-_Z39__device_stub__Z17bitonic_sort_stepPiiiPiii
.globl _Z17bitonic_sort_stepPiii
.type _Z17bitonic_sort_stepPiii, @function
_Z17bitonic_sort_stepPiii:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z39__device_stub__Z17bitonic_sort_stepPiiiPiii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z17bitonic_sort_stepPiii, .-_Z17bitonic_sort_stepPiii
.globl _Z12bitonic_sortPi
.type _Z12bitonic_sortPi, @function
_Z12bitonic_sortPi:
.LFB2058:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $56, %rsp
.cfi_def_cfa_offset 96
movq %rdi, %r13
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rdi
movl $524288, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $524288, %edx
movq %r13, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1024, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $128, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $17, %r12d
movl $2, %ebp
jmp .L17
.L15:
sarl %ebx
testl %ebx, %ebx
jle .L14
.L16:
movl 36(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movq 16(%rsp), %rdi
movl 24(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L15
movl %ebp, %edx
movl %ebx, %esi
movq 8(%rsp), %rdi
call _Z39__device_stub__Z17bitonic_sort_stepPiiiPiii
jmp .L15
.L14:
addl %ebp, %ebp
subl $1, %r12d
je .L22
.L17:
movl %ebp, %ebx
sarl %ebx
testl %ebx, %ebx
jg .L16
jmp .L14
.L22:
movl $2, %ecx
movl $524288, %edx
movq 8(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L23
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size _Z12bitonic_sortPi, .-_Z12bitonic_sortPi
.section .rodata.str1.1
.LC2:
.string "r"
.LC3:
.string "reverse_dataset.txt"
.LC4:
.string "%d\n"
.text
.globl main
.type main, @function
main:
.LFB2059:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
movl $524288, %edi
call malloc@PLT
movq %rax, %r14
leaq .LC2(%rip), %rsi
leaq .LC3(%rip), %rdi
call fopen@PLT
movq %rax, %rbp
movq %r14, %rbx
leaq 524288(%r14), %r13
leaq .LC4(%rip), %r12
.L25:
movq %rbx, %rdx
movq %r12, %rsi
movq %rbp, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
addq $4, %rbx
cmpq %r13, %rbx
jne .L25
call clock@PLT
movq %rax, %rbx
movq %r14, %rdi
call _Z12bitonic_sortPi
call clock@PLT
movq %rax, %rsi
movq %rbx, %rdi
call _Z13print_elapsedll
movl $0, %eax
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size main, .-main
.section .rodata.str1.1
.LC5:
.string "_Z17bitonic_sort_stepPiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z17bitonic_sort_stepPiii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long 0
.long 1093567616
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdlib.h>
#include <stdio.h>
#include <time.h>
/* Every thread gets exactly one value in the unsorted array. */
#define THREADS 128 // 2^7
#define BLOCKS 1024 // 2^10
#define NUM_VALS THREADS*BLOCKS
void print_elapsed(clock_t start, clock_t stop)
{
double elapsed = ((double) (stop - start)) / CLOCKS_PER_SEC;
printf("Elapsed time: %.3fs\n", elapsed);
}
__global__ void bitonic_sort_step(int *dev_values, int j, int k)
{
unsigned int i, ixj; /* Sorting partners: i and ixj */
i = threadIdx.x + blockDim.x * blockIdx.x;
ixj = i^j;
/* The threads with the lowest ids sort the array. */
if ((ixj)>i) {
if ((i&k)==0) {
/* Sort ascending */
if (dev_values[i]>dev_values[ixj]) {
// swap
int temp = dev_values[i];
dev_values[i] = dev_values[ixj];
dev_values[ixj] = temp;
}
}
if ((i&k)!=0) {
/* Sort descending */
if (dev_values[i]<dev_values[ixj]) {
// swap
int temp = dev_values[i];
dev_values[i] = dev_values[ixj];
dev_values[ixj] = temp;
}
}
}
}
void bitonic_sort(int *values)
{
int *dev_values;
size_t size = NUM_VALS * sizeof(int);
cudaMalloc((void**) &dev_values, size);
cudaMemcpy(dev_values, values, size, cudaMemcpyHostToDevice);
dim3 blocks(BLOCKS,1);
dim3 threads(THREADS,1);
int j, k;
/* Major step */
for (k = 2; k <= NUM_VALS; k <<= 1) {
/* Minor step */
for (j=k>>1; j>0; j=j>>1) {
bitonic_sort_step<<<blocks, threads>>>(dev_values, j, k);
}
}
cudaMemcpy(values, dev_values, size, cudaMemcpyDeviceToHost);
cudaFree(dev_values);
}
int main(int argc, char const *argv[])
{
clock_t start, stop;
int *values = (int*)malloc(NUM_VALS * sizeof(int));
FILE *f = fopen("reverse_dataset.txt", "r");
for(int i=0;i< NUM_VALS; i++) {
fscanf(f, "%d\n", &values[i]);
}
start = clock();
bitonic_sort(values);
stop = clock();
print_elapsed(start, stop);
return 0;
} | #include <hip/hip_runtime.h>
#include <stdlib.h>
#include <stdio.h>
#include <time.h>
/* Every thread gets exactly one value in the unsorted array. */
#define THREADS 128 // 2^7
#define BLOCKS 1024 // 2^10
#define NUM_VALS THREADS*BLOCKS
void print_elapsed(clock_t start, clock_t stop)
{
double elapsed = ((double) (stop - start)) / CLOCKS_PER_SEC;
printf("Elapsed time: %.3fs\n", elapsed);
}
__global__ void bitonic_sort_step(int *dev_values, int j, int k)
{
unsigned int i, ixj; /* Sorting partners: i and ixj */
i = threadIdx.x + blockDim.x * blockIdx.x;
ixj = i^j;
/* The threads with the lowest ids sort the array. */
if ((ixj)>i) {
if ((i&k)==0) {
/* Sort ascending */
if (dev_values[i]>dev_values[ixj]) {
// swap
int temp = dev_values[i];
dev_values[i] = dev_values[ixj];
dev_values[ixj] = temp;
}
}
if ((i&k)!=0) {
/* Sort descending */
if (dev_values[i]<dev_values[ixj]) {
// swap
int temp = dev_values[i];
dev_values[i] = dev_values[ixj];
dev_values[ixj] = temp;
}
}
}
}
void bitonic_sort(int *values)
{
int *dev_values;
size_t size = NUM_VALS * sizeof(int);
hipMalloc((void**) &dev_values, size);
hipMemcpy(dev_values, values, size, hipMemcpyHostToDevice);
dim3 blocks(BLOCKS,1);
dim3 threads(THREADS,1);
int j, k;
/* Major step */
for (k = 2; k <= NUM_VALS; k <<= 1) {
/* Minor step */
for (j=k>>1; j>0; j=j>>1) {
bitonic_sort_step<<<blocks, threads>>>(dev_values, j, k);
}
}
hipMemcpy(values, dev_values, size, hipMemcpyDeviceToHost);
hipFree(dev_values);
}
int main(int argc, char const *argv[])
{
clock_t start, stop;
int *values = (int*)malloc(NUM_VALS * sizeof(int));
FILE *f = fopen("reverse_dataset.txt", "r");
for(int i=0;i< NUM_VALS; i++) {
fscanf(f, "%d\n", &values[i]);
}
start = clock();
bitonic_sort(values);
stop = clock();
print_elapsed(start, stop);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdlib.h>
#include <stdio.h>
#include <time.h>
/* Every thread gets exactly one value in the unsorted array. */
#define THREADS 128 // 2^7
#define BLOCKS 1024 // 2^10
#define NUM_VALS THREADS*BLOCKS
void print_elapsed(clock_t start, clock_t stop)
{
double elapsed = ((double) (stop - start)) / CLOCKS_PER_SEC;
printf("Elapsed time: %.3fs\n", elapsed);
}
__global__ void bitonic_sort_step(int *dev_values, int j, int k)
{
unsigned int i, ixj; /* Sorting partners: i and ixj */
i = threadIdx.x + blockDim.x * blockIdx.x;
ixj = i^j;
/* The threads with the lowest ids sort the array. */
if ((ixj)>i) {
if ((i&k)==0) {
/* Sort ascending */
if (dev_values[i]>dev_values[ixj]) {
// swap
int temp = dev_values[i];
dev_values[i] = dev_values[ixj];
dev_values[ixj] = temp;
}
}
if ((i&k)!=0) {
/* Sort descending */
if (dev_values[i]<dev_values[ixj]) {
// swap
int temp = dev_values[i];
dev_values[i] = dev_values[ixj];
dev_values[ixj] = temp;
}
}
}
}
void bitonic_sort(int *values)
{
int *dev_values;
size_t size = NUM_VALS * sizeof(int);
hipMalloc((void**) &dev_values, size);
hipMemcpy(dev_values, values, size, hipMemcpyHostToDevice);
dim3 blocks(BLOCKS,1);
dim3 threads(THREADS,1);
int j, k;
/* Major step */
for (k = 2; k <= NUM_VALS; k <<= 1) {
/* Minor step */
for (j=k>>1; j>0; j=j>>1) {
bitonic_sort_step<<<blocks, threads>>>(dev_values, j, k);
}
}
hipMemcpy(values, dev_values, size, hipMemcpyDeviceToHost);
hipFree(dev_values);
}
int main(int argc, char const *argv[])
{
clock_t start, stop;
int *values = (int*)malloc(NUM_VALS * sizeof(int));
FILE *f = fopen("reverse_dataset.txt", "r");
for(int i=0;i< NUM_VALS; i++) {
fscanf(f, "%d\n", &values[i]);
}
start = clock();
bitonic_sort(values);
stop = clock();
print_elapsed(start, stop);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z17bitonic_sort_stepPiii
.globl _Z17bitonic_sort_stepPiii
.p2align 8
.type _Z17bitonic_sort_stepPiii,@function
_Z17bitonic_sort_stepPiii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x1c
s_load_b32 s3, s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[4:5], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_xor_b32_e32 v0, s3, v4
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_u32_e64 v0, v4
s_cbranch_execz .LBB0_7
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x0
s_load_b32 s0, s[0:1], 0xc
v_mov_b32_e32 v5, 0
s_mov_b32 s1, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[4:5]
s_waitcnt lgkmcnt(0)
v_dual_mov_b32 v1, v5 :: v_dual_and_b32 v4, s0, v4
s_mov_b32 s0, 0
v_lshlrev_b64 v[5:6], 2, v[0:1]
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_u32 v0, vcc_lo, s2, v2
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v3, vcc_lo
v_add_co_u32 v2, vcc_lo, s2, v5
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v6, vcc_lo
s_clause 0x1
global_load_b32 v5, v[0:1], off
global_load_b32 v6, v[2:3], off
v_cmpx_ne_u32_e32 0, v4
s_xor_b32 s1, exec_lo, s1
s_cbranch_execz .LBB0_3
s_waitcnt vmcnt(0)
v_cmp_lt_i32_e32 vcc_lo, v5, v6
s_and_b32 s0, vcc_lo, exec_lo
.LBB0_3:
s_and_not1_saveexec_b32 s1, s1
s_cbranch_execz .LBB0_5
s_waitcnt vmcnt(0)
v_cmp_gt_i32_e32 vcc_lo, v5, v6
s_and_not1_b32 s0, s0, exec_lo
s_and_b32 s2, vcc_lo, exec_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 s0, s0, s2
.LBB0_5:
s_or_b32 exec_lo, exec_lo, s1
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 exec_lo, exec_lo, s0
s_cbranch_execz .LBB0_7
s_waitcnt vmcnt(0)
s_clause 0x1
global_store_b32 v[0:1], v6, off
global_store_b32 v[2:3], v5, off
.LBB0_7:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z17bitonic_sort_stepPiii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z17bitonic_sort_stepPiii, .Lfunc_end0-_Z17bitonic_sort_stepPiii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z17bitonic_sort_stepPiii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z17bitonic_sort_stepPiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdlib.h>
#include <stdio.h>
#include <time.h>
/* Every thread gets exactly one value in the unsorted array. */
#define THREADS 128 // 2^7
#define BLOCKS 1024 // 2^10
#define NUM_VALS THREADS*BLOCKS
void print_elapsed(clock_t start, clock_t stop)
{
double elapsed = ((double) (stop - start)) / CLOCKS_PER_SEC;
printf("Elapsed time: %.3fs\n", elapsed);
}
__global__ void bitonic_sort_step(int *dev_values, int j, int k)
{
unsigned int i, ixj; /* Sorting partners: i and ixj */
i = threadIdx.x + blockDim.x * blockIdx.x;
ixj = i^j;
/* The threads with the lowest ids sort the array. */
if ((ixj)>i) {
if ((i&k)==0) {
/* Sort ascending */
if (dev_values[i]>dev_values[ixj]) {
// swap
int temp = dev_values[i];
dev_values[i] = dev_values[ixj];
dev_values[ixj] = temp;
}
}
if ((i&k)!=0) {
/* Sort descending */
if (dev_values[i]<dev_values[ixj]) {
// swap
int temp = dev_values[i];
dev_values[i] = dev_values[ixj];
dev_values[ixj] = temp;
}
}
}
}
void bitonic_sort(int *values)
{
int *dev_values;
size_t size = NUM_VALS * sizeof(int);
hipMalloc((void**) &dev_values, size);
hipMemcpy(dev_values, values, size, hipMemcpyHostToDevice);
dim3 blocks(BLOCKS,1);
dim3 threads(THREADS,1);
int j, k;
/* Major step */
for (k = 2; k <= NUM_VALS; k <<= 1) {
/* Minor step */
for (j=k>>1; j>0; j=j>>1) {
bitonic_sort_step<<<blocks, threads>>>(dev_values, j, k);
}
}
hipMemcpy(values, dev_values, size, hipMemcpyDeviceToHost);
hipFree(dev_values);
}
int main(int argc, char const *argv[])
{
clock_t start, stop;
int *values = (int*)malloc(NUM_VALS * sizeof(int));
FILE *f = fopen("reverse_dataset.txt", "r");
for(int i=0;i< NUM_VALS; i++) {
fscanf(f, "%d\n", &values[i]);
}
start = clock();
bitonic_sort(values);
stop = clock();
print_elapsed(start, stop);
return 0;
} | .text
.file "bitonic_sort.hip"
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z13print_elapsedll
.LCPI0_0:
.quad 0x412e848000000000 # double 1.0E+6
.text
.globl _Z13print_elapsedll
.p2align 4, 0x90
.type _Z13print_elapsedll,@function
_Z13print_elapsedll: # @_Z13print_elapsedll
.cfi_startproc
# %bb.0:
subq %rdi, %rsi
cvtsi2sd %rsi, %xmm0
divsd .LCPI0_0(%rip), %xmm0
movl $.L.str, %edi
movb $1, %al
jmp printf # TAILCALL
.Lfunc_end0:
.size _Z13print_elapsedll, .Lfunc_end0-_Z13print_elapsedll
.cfi_endproc
# -- End function
.globl _Z32__device_stub__bitonic_sort_stepPiii # -- Begin function _Z32__device_stub__bitonic_sort_stepPiii
.p2align 4, 0x90
.type _Z32__device_stub__bitonic_sort_stepPiii,@function
_Z32__device_stub__bitonic_sort_stepPiii: # @_Z32__device_stub__bitonic_sort_stepPiii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z17bitonic_sort_stepPiii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end1:
.size _Z32__device_stub__bitonic_sort_stepPiii, .Lfunc_end1-_Z32__device_stub__bitonic_sort_stepPiii
.cfi_endproc
# -- End function
.globl _Z12bitonic_sortPi # -- Begin function _Z12bitonic_sortPi
.p2align 4, 0x90
.type _Z12bitonic_sortPi,@function
_Z12bitonic_sortPi: # @_Z12bitonic_sortPi
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $104, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rdi, %rbx
movabsq $4294967424, %r14 # imm = 0x100000080
movq %rsp, %rdi
movl $524288, %esi # imm = 0x80000
callq hipMalloc
movq (%rsp), %rdi
movl $524288, %edx # imm = 0x80000
movq %rbx, 16(%rsp) # 8-byte Spill
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movl $2, %ebp
leaq 896(%r14), %r15
leaq 24(%rsp), %rbx
leaq 80(%rsp), %r12
jmp .LBB2_1
.p2align 4, 0x90
.LBB2_5: # %._crit_edge
# in Loop: Header=BB2_1 Depth=1
addl %ebp, %ebp
cmpl $131073, %ebp # imm = 0x20001
jge .LBB2_6
.LBB2_1: # =>This Loop Header: Depth=1
# Child Loop BB2_2 Depth 2
movl %ebp, %r13d
sarl %r13d
testl %r13d, %r13d
jg .LBB2_2
jmp .LBB2_5
.p2align 4, 0x90
.LBB2_4: # in Loop: Header=BB2_2 Depth=2
movl %r13d, %eax
shrl %eax
cmpl $1, %r13d
movl %eax, %r13d
jbe .LBB2_5
.LBB2_2: # %.lr.ph
# Parent Loop BB2_1 Depth=1
# => This Inner Loop Header: Depth=2
movq %r15, %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_4
# %bb.3: # in Loop: Header=BB2_2 Depth=2
movq (%rsp), %rax
movq %rax, 72(%rsp)
movl %r13d, 12(%rsp)
movl %ebp, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 8(%rsp), %rax
movq %rax, 96(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
movq %rbx, %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
movl $_Z17bitonic_sort_stepPiii, %edi
movq %r12, %r9
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB2_4
.LBB2_6:
movq (%rsp), %rsi
movl $524288, %edx # imm = 0x80000
movq 16(%rsp), %rdi # 8-byte Reload
movl $2, %ecx
callq hipMemcpy
movq (%rsp), %rdi
callq hipFree
addq $104, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z12bitonic_sortPi, .Lfunc_end2-_Z12bitonic_sortPi
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI3_0:
.quad 0x412e848000000000 # double 1.0E+6
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $524288, %edi # imm = 0x80000
callq malloc
movq %rax, %rbx
movl $.L.str.1, %edi
movl $.L.str.2, %esi
callq fopen
movq %rax, %r14
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB3_1: # =>This Inner Loop Header: Depth=1
leaq (%rbx,%r15), %rdx
movl $.L.str.3, %esi
movq %r14, %rdi
xorl %eax, %eax
callq __isoc23_fscanf
addq $4, %r15
cmpq $524288, %r15 # imm = 0x80000
jne .LBB3_1
# %bb.2:
callq clock
movq %rax, %r14
movq %rbx, %rdi
callq _Z12bitonic_sortPi
callq clock
subq %r14, %rax
cvtsi2sd %rax, %xmm0
divsd .LCPI3_0(%rip), %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
xorl %eax, %eax
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z17bitonic_sort_stepPiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Elapsed time: %.3fs\n"
.size .L.str, 21
.type _Z17bitonic_sort_stepPiii,@object # @_Z17bitonic_sort_stepPiii
.section .rodata,"a",@progbits
.globl _Z17bitonic_sort_stepPiii
.p2align 3, 0x0
_Z17bitonic_sort_stepPiii:
.quad _Z32__device_stub__bitonic_sort_stepPiii
.size _Z17bitonic_sort_stepPiii, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "reverse_dataset.txt"
.size .L.str.1, 20
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "r"
.size .L.str.2, 2
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "%d\n"
.size .L.str.3, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z17bitonic_sort_stepPiii"
.size .L__unnamed_1, 26
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z32__device_stub__bitonic_sort_stepPiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z17bitonic_sort_stepPiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z17bitonic_sort_stepPiii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ LOP3.LUT R5, R0, c[0x0][0x168], RZ, 0x3c, !PT ; /* 0x00005a0000057a12 */
/* 0x000fc800078e3cff */
/*0050*/ ISETP.GT.U32.AND P0, PT, R5, R0, PT ; /* 0x000000000500720c */
/* 0x000fda0003f04070 */
/*0060*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0070*/ IMAD.MOV.U32 R4, RZ, RZ, 0x4 ; /* 0x00000004ff047424 */
/* 0x000fe200078e00ff */
/*0080*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0090*/ IMAD.WIDE.U32 R2, R0, R4, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fc800078e0004 */
/*00a0*/ IMAD.WIDE.U32 R4, R5, R4, c[0x0][0x160] ; /* 0x0000580005047625 */
/* 0x000fe200078e0004 */
/*00b0*/ LDG.E R7, [R2.64] ; /* 0x0000000402077981 */
/* 0x000168000c1e1900 */
/*00c0*/ LDG.E R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000162000c1e1900 */
/*00d0*/ LOP3.LUT P0, RZ, R0, c[0x0][0x16c], RZ, 0xc0, !PT ; /* 0x00005b0000ff7a12 */
/* 0x000fda000780c0ff */
/*00e0*/ @!P0 BRA 0x140 ; /* 0x0000005000008947 */
/* 0x000fea0003800000 */
/*00f0*/ ISETP.GE.AND P0, PT, R7, R6, PT ; /* 0x000000060700720c */
/* 0x021fda0003f06270 */
/*0100*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0110*/ STG.E [R2.64], R6 ; /* 0x0000000602007986 */
/* 0x000fe8000c101904 */
/*0120*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x000fe2000c101904 */
/*0130*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0140*/ ISETP.GT.AND P0, PT, R7, R6, PT ; /* 0x000000060700720c */
/* 0x021fda0003f04270 */
/*0150*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0160*/ STG.E [R2.64], R6 ; /* 0x0000000602007986 */
/* 0x000fe8000c101904 */
/*0170*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x000fe2000c101904 */
/*0180*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0190*/ BRA 0x190; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z17bitonic_sort_stepPiii
.globl _Z17bitonic_sort_stepPiii
.p2align 8
.type _Z17bitonic_sort_stepPiii,@function
_Z17bitonic_sort_stepPiii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x1c
s_load_b32 s3, s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[4:5], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_xor_b32_e32 v0, s3, v4
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_u32_e64 v0, v4
s_cbranch_execz .LBB0_7
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x0
s_load_b32 s0, s[0:1], 0xc
v_mov_b32_e32 v5, 0
s_mov_b32 s1, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[4:5]
s_waitcnt lgkmcnt(0)
v_dual_mov_b32 v1, v5 :: v_dual_and_b32 v4, s0, v4
s_mov_b32 s0, 0
v_lshlrev_b64 v[5:6], 2, v[0:1]
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_u32 v0, vcc_lo, s2, v2
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v3, vcc_lo
v_add_co_u32 v2, vcc_lo, s2, v5
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v6, vcc_lo
s_clause 0x1
global_load_b32 v5, v[0:1], off
global_load_b32 v6, v[2:3], off
v_cmpx_ne_u32_e32 0, v4
s_xor_b32 s1, exec_lo, s1
s_cbranch_execz .LBB0_3
s_waitcnt vmcnt(0)
v_cmp_lt_i32_e32 vcc_lo, v5, v6
s_and_b32 s0, vcc_lo, exec_lo
.LBB0_3:
s_and_not1_saveexec_b32 s1, s1
s_cbranch_execz .LBB0_5
s_waitcnt vmcnt(0)
v_cmp_gt_i32_e32 vcc_lo, v5, v6
s_and_not1_b32 s0, s0, exec_lo
s_and_b32 s2, vcc_lo, exec_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 s0, s0, s2
.LBB0_5:
s_or_b32 exec_lo, exec_lo, s1
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 exec_lo, exec_lo, s0
s_cbranch_execz .LBB0_7
s_waitcnt vmcnt(0)
s_clause 0x1
global_store_b32 v[0:1], v6, off
global_store_b32 v[2:3], v5, off
.LBB0_7:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z17bitonic_sort_stepPiii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z17bitonic_sort_stepPiii, .Lfunc_end0-_Z17bitonic_sort_stepPiii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z17bitonic_sort_stepPiii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z17bitonic_sort_stepPiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00117c73_00000000-6_bitonic_sort.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "Elapsed time: %.3fs\n"
.text
.globl _Z13print_elapsedll
.type _Z13print_elapsedll, @function
_Z13print_elapsedll:
.LFB2057:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
subq %rdi, %rsi
pxor %xmm0, %xmm0
cvtsi2sdq %rsi, %xmm0
divsd .LC0(%rip), %xmm0
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _Z13print_elapsedll, .-_Z13print_elapsedll
.globl _Z39__device_stub__Z17bitonic_sort_stepPiiiPiii
.type _Z39__device_stub__Z17bitonic_sort_stepPiiiPiii, @function
_Z39__device_stub__Z17bitonic_sort_stepPiiiPiii:
.LFB2084:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L9
.L5:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L10
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z17bitonic_sort_stepPiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L5
.L10:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z39__device_stub__Z17bitonic_sort_stepPiiiPiii, .-_Z39__device_stub__Z17bitonic_sort_stepPiiiPiii
.globl _Z17bitonic_sort_stepPiii
.type _Z17bitonic_sort_stepPiii, @function
_Z17bitonic_sort_stepPiii:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z39__device_stub__Z17bitonic_sort_stepPiiiPiii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z17bitonic_sort_stepPiii, .-_Z17bitonic_sort_stepPiii
.globl _Z12bitonic_sortPi
.type _Z12bitonic_sortPi, @function
_Z12bitonic_sortPi:
.LFB2058:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $56, %rsp
.cfi_def_cfa_offset 96
movq %rdi, %r13
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rdi
movl $524288, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $524288, %edx
movq %r13, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1024, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $128, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $17, %r12d
movl $2, %ebp
jmp .L17
.L15:
sarl %ebx
testl %ebx, %ebx
jle .L14
.L16:
movl 36(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movq 16(%rsp), %rdi
movl 24(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L15
movl %ebp, %edx
movl %ebx, %esi
movq 8(%rsp), %rdi
call _Z39__device_stub__Z17bitonic_sort_stepPiiiPiii
jmp .L15
.L14:
addl %ebp, %ebp
subl $1, %r12d
je .L22
.L17:
movl %ebp, %ebx
sarl %ebx
testl %ebx, %ebx
jg .L16
jmp .L14
.L22:
movl $2, %ecx
movl $524288, %edx
movq 8(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L23
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size _Z12bitonic_sortPi, .-_Z12bitonic_sortPi
.section .rodata.str1.1
.LC2:
.string "r"
.LC3:
.string "reverse_dataset.txt"
.LC4:
.string "%d\n"
.text
.globl main
.type main, @function
main:
.LFB2059:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
movl $524288, %edi
call malloc@PLT
movq %rax, %r14
leaq .LC2(%rip), %rsi
leaq .LC3(%rip), %rdi
call fopen@PLT
movq %rax, %rbp
movq %r14, %rbx
leaq 524288(%r14), %r13
leaq .LC4(%rip), %r12
.L25:
movq %rbx, %rdx
movq %r12, %rsi
movq %rbp, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
addq $4, %rbx
cmpq %r13, %rbx
jne .L25
call clock@PLT
movq %rax, %rbx
movq %r14, %rdi
call _Z12bitonic_sortPi
call clock@PLT
movq %rax, %rsi
movq %rbx, %rdi
call _Z13print_elapsedll
movl $0, %eax
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size main, .-main
.section .rodata.str1.1
.LC5:
.string "_Z17bitonic_sort_stepPiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z17bitonic_sort_stepPiii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long 0
.long 1093567616
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "bitonic_sort.hip"
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z13print_elapsedll
.LCPI0_0:
.quad 0x412e848000000000 # double 1.0E+6
.text
.globl _Z13print_elapsedll
.p2align 4, 0x90
.type _Z13print_elapsedll,@function
_Z13print_elapsedll: # @_Z13print_elapsedll
.cfi_startproc
# %bb.0:
subq %rdi, %rsi
cvtsi2sd %rsi, %xmm0
divsd .LCPI0_0(%rip), %xmm0
movl $.L.str, %edi
movb $1, %al
jmp printf # TAILCALL
.Lfunc_end0:
.size _Z13print_elapsedll, .Lfunc_end0-_Z13print_elapsedll
.cfi_endproc
# -- End function
.globl _Z32__device_stub__bitonic_sort_stepPiii # -- Begin function _Z32__device_stub__bitonic_sort_stepPiii
.p2align 4, 0x90
.type _Z32__device_stub__bitonic_sort_stepPiii,@function
_Z32__device_stub__bitonic_sort_stepPiii: # @_Z32__device_stub__bitonic_sort_stepPiii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z17bitonic_sort_stepPiii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end1:
.size _Z32__device_stub__bitonic_sort_stepPiii, .Lfunc_end1-_Z32__device_stub__bitonic_sort_stepPiii
.cfi_endproc
# -- End function
.globl _Z12bitonic_sortPi # -- Begin function _Z12bitonic_sortPi
.p2align 4, 0x90
.type _Z12bitonic_sortPi,@function
_Z12bitonic_sortPi: # @_Z12bitonic_sortPi
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $104, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rdi, %rbx
movabsq $4294967424, %r14 # imm = 0x100000080
movq %rsp, %rdi
movl $524288, %esi # imm = 0x80000
callq hipMalloc
movq (%rsp), %rdi
movl $524288, %edx # imm = 0x80000
movq %rbx, 16(%rsp) # 8-byte Spill
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movl $2, %ebp
leaq 896(%r14), %r15
leaq 24(%rsp), %rbx
leaq 80(%rsp), %r12
jmp .LBB2_1
.p2align 4, 0x90
.LBB2_5: # %._crit_edge
# in Loop: Header=BB2_1 Depth=1
addl %ebp, %ebp
cmpl $131073, %ebp # imm = 0x20001
jge .LBB2_6
.LBB2_1: # =>This Loop Header: Depth=1
# Child Loop BB2_2 Depth 2
movl %ebp, %r13d
sarl %r13d
testl %r13d, %r13d
jg .LBB2_2
jmp .LBB2_5
.p2align 4, 0x90
.LBB2_4: # in Loop: Header=BB2_2 Depth=2
movl %r13d, %eax
shrl %eax
cmpl $1, %r13d
movl %eax, %r13d
jbe .LBB2_5
.LBB2_2: # %.lr.ph
# Parent Loop BB2_1 Depth=1
# => This Inner Loop Header: Depth=2
movq %r15, %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_4
# %bb.3: # in Loop: Header=BB2_2 Depth=2
movq (%rsp), %rax
movq %rax, 72(%rsp)
movl %r13d, 12(%rsp)
movl %ebp, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 8(%rsp), %rax
movq %rax, 96(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
movq %rbx, %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
movl $_Z17bitonic_sort_stepPiii, %edi
movq %r12, %r9
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB2_4
.LBB2_6:
movq (%rsp), %rsi
movl $524288, %edx # imm = 0x80000
movq 16(%rsp), %rdi # 8-byte Reload
movl $2, %ecx
callq hipMemcpy
movq (%rsp), %rdi
callq hipFree
addq $104, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z12bitonic_sortPi, .Lfunc_end2-_Z12bitonic_sortPi
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI3_0:
.quad 0x412e848000000000 # double 1.0E+6
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $524288, %edi # imm = 0x80000
callq malloc
movq %rax, %rbx
movl $.L.str.1, %edi
movl $.L.str.2, %esi
callq fopen
movq %rax, %r14
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB3_1: # =>This Inner Loop Header: Depth=1
leaq (%rbx,%r15), %rdx
movl $.L.str.3, %esi
movq %r14, %rdi
xorl %eax, %eax
callq __isoc23_fscanf
addq $4, %r15
cmpq $524288, %r15 # imm = 0x80000
jne .LBB3_1
# %bb.2:
callq clock
movq %rax, %r14
movq %rbx, %rdi
callq _Z12bitonic_sortPi
callq clock
subq %r14, %rax
cvtsi2sd %rax, %xmm0
divsd .LCPI3_0(%rip), %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
xorl %eax, %eax
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z17bitonic_sort_stepPiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Elapsed time: %.3fs\n"
.size .L.str, 21
.type _Z17bitonic_sort_stepPiii,@object # @_Z17bitonic_sort_stepPiii
.section .rodata,"a",@progbits
.globl _Z17bitonic_sort_stepPiii
.p2align 3, 0x0
_Z17bitonic_sort_stepPiii:
.quad _Z32__device_stub__bitonic_sort_stepPiii
.size _Z17bitonic_sort_stepPiii, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "reverse_dataset.txt"
.size .L.str.1, 20
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "r"
.size .L.str.2, 2
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "%d\n"
.size .L.str.3, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z17bitonic_sort_stepPiii"
.size .L__unnamed_1, 26
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z32__device_stub__bitonic_sort_stepPiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z17bitonic_sort_stepPiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <cuda.h>
#define HIST_LENGTH 256
#define THREADS_P_BLOCK 512
__global__ void histogram_kernel(int *data_d, int data_length, int *hist_d)
{
int index, offset;
/** Arreglo en memoria compartida **/
__shared__ int temp_hist[HIST_LENGTH];
/**Inicializacion en 0 **/
temp_hist[threadIdx.x] = 0;
__syncthreads();
index = threadIdx.x + blockIdx.x * blockDim.x;
/** Cada thread debe recorrer los datos segun el offset declarado **/
offset = blockDim.x * gridDim.x;
/** Llenado del histograma **/
while(index < data_length) {
atomicAdd( &temp_hist[data_d[index]], 1);
index += offset;
}
__syncthreads();
/** Traspaso a memoria global **/
atomicAdd(&(hist_d[threadIdx.x]), temp_hist[threadIdx.x]);
}
int main(int argc, char *argv[])
{
float elapsed_Time;
int i, blocks;
int data_length;
int hist_h[HIST_LENGTH], *data_h, *data_d, *hist_d;
cudaEvent_t start, stop;
/** Timers **/
cudaEventCreate(&start);
cudaEventCreate(&stop);
/** Input de datos **/
FILE *in_f = fopen(argv[1], "r");
fscanf(in_f, "%d", &data_length);
data_length *= data_length;
/** Declaracion dinamica del tamano del arreglo dependiendo de la matriz **/
data_h = (int *)malloc(data_length * sizeof(int));
for (i = 0; i < data_length && fscanf(in_f, "%d", &data_h[i]) == 1; ++i);
fclose(in_f);
cudaEventRecord(start, 0);
/** Alloc para la memoria en GPU **/
cudaMalloc((void **) &data_d, data_length * sizeof(int));
/** Se copian los datos del histograma a la memoria del dispositivo **/
cudaMemcpy(data_d, data_h, data_length * sizeof(int), cudaMemcpyHostToDevice);
/** Se reserva la memoria para el histograma en el dispositivo y se inicializa en 0 **/
cudaMalloc((void **) &hist_d, HIST_LENGTH * sizeof(int));
cudaMemset(hist_d, 0, HIST_LENGTH * sizeof(int));
/** Se analizo que los tiempos de ejecucion eran menores al enviar dos veces el numero de
** multiprocesadores presentes **/
cudaDeviceProp prop;
cudaGetDeviceProperties(&prop, 0);
blocks = prop.multiProcessorCount * 2;
/** 256 threads es el numero optimo para la ejecucion **/
histogram_kernel<<<blocks, 256>>>(data_d, data_length, hist_d);
/** Se traspasan los datos del histograma desde el dispositivo **/
cudaMemcpy(hist_h, hist_d, 256 * sizeof(int), cudaMemcpyDeviceToHost);
/** Se detiene el timer **/
cudaEventRecord(stop, 0);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&elapsed_Time, start, stop);
cudaFree(data_d);
cudaFree(hist_d);
cudaEventDestroy(start);
cudaEventDestroy(stop);
/** Datos escritos en el archivo de salida **/
FILE *out = fopen("salida", "w");
for (i = 0; i < 256; i++)
{
if (i == 255)
fprintf(out, "%d", hist_h[i]);
else
fprintf(out, "%d\n", hist_h[i]);
}
fclose(out);
printf("Tiempo de ejecucion: %f ms\n", elapsed_Time);
return 0;
} | code for sm_80
Function : _Z16histogram_kernelPiiS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_TID.X ; /* 0x0000000000047919 */
/* 0x000e220000002100 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0030*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e680000002500 */
/*0040*/ STS [R4.X4], RZ ; /* 0x000000ff04007388 */
/* 0x0011e20000004800 */
/*0050*/ IMAD R0, R3, c[0x0][0x0], R4 ; /* 0x0000000003007a24 */
/* 0x002fc600078e0204 */
/*0060*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe40000010000 */
/*0070*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x168], PT ; /* 0x00005a0000007a0c */
/* 0x000fda0003f06270 */
/*0080*/ @P0 BRA 0x120 ; /* 0x0000009000000947 */
/* 0x001fea0003800000 */
/*0090*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fd400000001ff */
/*00a0*/ IMAD.WIDE R2, R0, R3, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x001fcc00078e0203 */
/*00b0*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ MOV R5, c[0x0][0x0] ; /* 0x0000000000057a02 */
/* 0x000fe20000000f00 */
/*00d0*/ YIELD ; /* 0x0000000000007946 */
/* 0x000fe80003800000 */
/*00e0*/ IMAD R0, R5, c[0x0][0xc], R0 ; /* 0x0000030005007a24 */
/* 0x000fca00078e0200 */
/*00f0*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x168], PT ; /* 0x00005a0000007a0c */
/* 0x000fe20003f06270 */
/*0100*/ ATOMS.POPC.INC.32 RZ, [R2.X4+URZ] ; /* 0x0000000002ff7f8c */
/* 0x0041d8000d00403f */
/*0110*/ @!P0 BRA 0x90 ; /* 0xffffff7000008947 */
/* 0x000fea000383ffff */
/*0120*/ WARPSYNC 0xffffffff ; /* 0xffffffff00007948 */
/* 0x000fe20003800000 */
/*0130*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0140*/ MOV R3, 0x4 ; /* 0x0000000400037802 */
/* 0x000fca0000000f00 */
/*0150*/ IMAD.WIDE.U32 R2, R4, R3, c[0x0][0x170] ; /* 0x00005c0004027625 */
/* 0x001fe200078e0003 */
/*0160*/ LDS R5, [R4.X4] ; /* 0x0000000004057984 */
/* 0x000e280000004800 */
/*0170*/ RED.E.ADD.STRONG.GPU [R2.64], R5 ; /* 0x000000050200798e */
/* 0x001fe2000c10e184 */
/*0180*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0190*/ BRA 0x190; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <cuda.h>
#define HIST_LENGTH 256
#define THREADS_P_BLOCK 512
__global__ void histogram_kernel(int *data_d, int data_length, int *hist_d)
{
int index, offset;
/** Arreglo en memoria compartida **/
__shared__ int temp_hist[HIST_LENGTH];
/**Inicializacion en 0 **/
temp_hist[threadIdx.x] = 0;
__syncthreads();
index = threadIdx.x + blockIdx.x * blockDim.x;
/** Cada thread debe recorrer los datos segun el offset declarado **/
offset = blockDim.x * gridDim.x;
/** Llenado del histograma **/
while(index < data_length) {
atomicAdd( &temp_hist[data_d[index]], 1);
index += offset;
}
__syncthreads();
/** Traspaso a memoria global **/
atomicAdd(&(hist_d[threadIdx.x]), temp_hist[threadIdx.x]);
}
int main(int argc, char *argv[])
{
float elapsed_Time;
int i, blocks;
int data_length;
int hist_h[HIST_LENGTH], *data_h, *data_d, *hist_d;
cudaEvent_t start, stop;
/** Timers **/
cudaEventCreate(&start);
cudaEventCreate(&stop);
/** Input de datos **/
FILE *in_f = fopen(argv[1], "r");
fscanf(in_f, "%d", &data_length);
data_length *= data_length;
/** Declaracion dinamica del tamano del arreglo dependiendo de la matriz **/
data_h = (int *)malloc(data_length * sizeof(int));
for (i = 0; i < data_length && fscanf(in_f, "%d", &data_h[i]) == 1; ++i);
fclose(in_f);
cudaEventRecord(start, 0);
/** Alloc para la memoria en GPU **/
cudaMalloc((void **) &data_d, data_length * sizeof(int));
/** Se copian los datos del histograma a la memoria del dispositivo **/
cudaMemcpy(data_d, data_h, data_length * sizeof(int), cudaMemcpyHostToDevice);
/** Se reserva la memoria para el histograma en el dispositivo y se inicializa en 0 **/
cudaMalloc((void **) &hist_d, HIST_LENGTH * sizeof(int));
cudaMemset(hist_d, 0, HIST_LENGTH * sizeof(int));
/** Se analizo que los tiempos de ejecucion eran menores al enviar dos veces el numero de
** multiprocesadores presentes **/
cudaDeviceProp prop;
cudaGetDeviceProperties(&prop, 0);
blocks = prop.multiProcessorCount * 2;
/** 256 threads es el numero optimo para la ejecucion **/
histogram_kernel<<<blocks, 256>>>(data_d, data_length, hist_d);
/** Se traspasan los datos del histograma desde el dispositivo **/
cudaMemcpy(hist_h, hist_d, 256 * sizeof(int), cudaMemcpyDeviceToHost);
/** Se detiene el timer **/
cudaEventRecord(stop, 0);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&elapsed_Time, start, stop);
cudaFree(data_d);
cudaFree(hist_d);
cudaEventDestroy(start);
cudaEventDestroy(stop);
/** Datos escritos en el archivo de salida **/
FILE *out = fopen("salida", "w");
for (i = 0; i < 256; i++)
{
if (i == 255)
fprintf(out, "%d", hist_h[i]);
else
fprintf(out, "%d\n", hist_h[i]);
}
fclose(out);
printf("Tiempo de ejecucion: %f ms\n", elapsed_Time);
return 0;
} | .file "tmpxft_00008352_00000000-6_Histograma.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z39__device_stub__Z16histogram_kernelPiiS_PiiS_
.type _Z39__device_stub__Z16histogram_kernelPiiS_PiiS_, @function
_Z39__device_stub__Z16histogram_kernelPiiS_PiiS_:
.LFB2082:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z16histogram_kernelPiiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z39__device_stub__Z16histogram_kernelPiiS_PiiS_, .-_Z39__device_stub__Z16histogram_kernelPiiS_PiiS_
.globl _Z16histogram_kernelPiiS_
.type _Z16histogram_kernelPiiS_, @function
_Z16histogram_kernelPiiS_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z39__device_stub__Z16histogram_kernelPiiS_PiiS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z16histogram_kernelPiiS_, .-_Z16histogram_kernelPiiS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "r"
.LC1:
.string "%d"
.LC2:
.string "w"
.LC3:
.string "salida"
.LC4:
.string "%d\n"
.LC5:
.string "Tiempo de ejecucion: %f ms\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $2128, %rsp
.cfi_def_cfa_offset 2176
movq %rsi, %rbx
movq %fs:40, %rax
movq %rax, 2120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rdi
call cudaEventCreate@PLT
leaq 32(%rsp), %rdi
call cudaEventCreate@PLT
movq 8(%rbx), %rdi
leaq .LC0(%rip), %rsi
call fopen@PLT
movq %rax, %r12
leaq 4(%rsp), %rdx
leaq .LC1(%rip), %rsi
movq %rax, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
movl 4(%rsp), %ebx
imull %ebx, %ebx
movl %ebx, 4(%rsp)
movslq %ebx, %rdi
salq $2, %rdi
call malloc@PLT
movq %rax, %r14
testl %ebx, %ebx
jle .L12
movq %rax, %rbx
movl $0, %ebp
leaq .LC1(%rip), %r13
.L13:
movq %rbx, %rdx
movq %r13, %rsi
movq %r12, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
cmpl $1, %eax
jne .L12
addl $1, %ebp
addq $4, %rbx
cmpl %ebp, 4(%rsp)
jg .L13
.L12:
movq %r12, %rdi
call fclose@PLT
movl $0, %esi
movq 24(%rsp), %rdi
call cudaEventRecord@PLT
movslq 4(%rsp), %rsi
salq $2, %rsi
leaq 8(%rsp), %rdi
call cudaMalloc@PLT
movslq 4(%rsp), %rdx
salq $2, %rdx
movl $1, %ecx
movq %r14, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
leaq 16(%rsp), %rdi
movl $1024, %esi
call cudaMalloc@PLT
movl $1024, %edx
movl $0, %esi
movq 16(%rsp), %rdi
call cudaMemset@PLT
leaq 1088(%rsp), %rdi
movl $0, %esi
call cudaGetDeviceProperties_v2@PLT
movl 1476(%rsp), %eax
addl %eax, %eax
movl $256, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl %eax, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 52(%rsp), %rdx
movl $1, %ecx
movq 40(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L22
.L14:
leaq 64(%rsp), %rbx
movl $2, %ecx
movl $1024, %edx
movq 16(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movl $0, %esi
movq 32(%rsp), %rdi
call cudaEventRecord@PLT
movq 32(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 52(%rsp), %rdi
movq 32(%rsp), %rdx
movq 24(%rsp), %rsi
call cudaEventElapsedTime@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaEventDestroy@PLT
movq 32(%rsp), %rdi
call cudaEventDestroy@PLT
leaq .LC2(%rip), %rsi
leaq .LC3(%rip), %rdi
call fopen@PLT
movq %rax, %rbp
leaq 1084(%rsp), %r14
leaq 1088(%rsp), %r13
leaq .LC4(%rip), %r12
.L15:
movl (%rbx), %ecx
movq %r12, %rdx
movl $2, %esi
movq %rbp, %rdi
movl $0, %eax
call __fprintf_chk@PLT
addq $4, %rbx
cmpq %r13, %rbx
je .L16
cmpq %r14, %rbx
jne .L15
movl 1084(%rsp), %ecx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq %rbp, %rdi
movl $0, %eax
call __fprintf_chk@PLT
.L16:
movq %rbp, %rdi
call fclose@PLT
pxor %xmm0, %xmm0
cvtss2sd 52(%rsp), %xmm0
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 2120(%rsp), %rax
subq %fs:40, %rax
jne .L23
movl $0, %eax
addq $2128, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L22:
.cfi_restore_state
movq 16(%rsp), %rdx
movl 4(%rsp), %esi
movq 8(%rsp), %rdi
call _Z39__device_stub__Z16histogram_kernelPiiS_PiiS_
jmp .L14
.L23:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC6:
.string "_Z16histogram_kernelPiiS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _Z16histogram_kernelPiiS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <cuda.h>
#define HIST_LENGTH 256
#define THREADS_P_BLOCK 512
__global__ void histogram_kernel(int *data_d, int data_length, int *hist_d)
{
int index, offset;
/** Arreglo en memoria compartida **/
__shared__ int temp_hist[HIST_LENGTH];
/**Inicializacion en 0 **/
temp_hist[threadIdx.x] = 0;
__syncthreads();
index = threadIdx.x + blockIdx.x * blockDim.x;
/** Cada thread debe recorrer los datos segun el offset declarado **/
offset = blockDim.x * gridDim.x;
/** Llenado del histograma **/
while(index < data_length) {
atomicAdd( &temp_hist[data_d[index]], 1);
index += offset;
}
__syncthreads();
/** Traspaso a memoria global **/
atomicAdd(&(hist_d[threadIdx.x]), temp_hist[threadIdx.x]);
}
int main(int argc, char *argv[])
{
float elapsed_Time;
int i, blocks;
int data_length;
int hist_h[HIST_LENGTH], *data_h, *data_d, *hist_d;
cudaEvent_t start, stop;
/** Timers **/
cudaEventCreate(&start);
cudaEventCreate(&stop);
/** Input de datos **/
FILE *in_f = fopen(argv[1], "r");
fscanf(in_f, "%d", &data_length);
data_length *= data_length;
/** Declaracion dinamica del tamano del arreglo dependiendo de la matriz **/
data_h = (int *)malloc(data_length * sizeof(int));
for (i = 0; i < data_length && fscanf(in_f, "%d", &data_h[i]) == 1; ++i);
fclose(in_f);
cudaEventRecord(start, 0);
/** Alloc para la memoria en GPU **/
cudaMalloc((void **) &data_d, data_length * sizeof(int));
/** Se copian los datos del histograma a la memoria del dispositivo **/
cudaMemcpy(data_d, data_h, data_length * sizeof(int), cudaMemcpyHostToDevice);
/** Se reserva la memoria para el histograma en el dispositivo y se inicializa en 0 **/
cudaMalloc((void **) &hist_d, HIST_LENGTH * sizeof(int));
cudaMemset(hist_d, 0, HIST_LENGTH * sizeof(int));
/** Se analizo que los tiempos de ejecucion eran menores al enviar dos veces el numero de
** multiprocesadores presentes **/
cudaDeviceProp prop;
cudaGetDeviceProperties(&prop, 0);
blocks = prop.multiProcessorCount * 2;
/** 256 threads es el numero optimo para la ejecucion **/
histogram_kernel<<<blocks, 256>>>(data_d, data_length, hist_d);
/** Se traspasan los datos del histograma desde el dispositivo **/
cudaMemcpy(hist_h, hist_d, 256 * sizeof(int), cudaMemcpyDeviceToHost);
/** Se detiene el timer **/
cudaEventRecord(stop, 0);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&elapsed_Time, start, stop);
cudaFree(data_d);
cudaFree(hist_d);
cudaEventDestroy(start);
cudaEventDestroy(stop);
/** Datos escritos en el archivo de salida **/
FILE *out = fopen("salida", "w");
for (i = 0; i < 256; i++)
{
if (i == 255)
fprintf(out, "%d", hist_h[i]);
else
fprintf(out, "%d\n", hist_h[i]);
}
fclose(out);
printf("Tiempo de ejecucion: %f ms\n", elapsed_Time);
return 0;
} | #include <stdio.h>
#include <hip/hip_runtime.h>
#define HIST_LENGTH 256
#define THREADS_P_BLOCK 512
__global__ void histogram_kernel(int *data_d, int data_length, int *hist_d)
{
int index, offset;
/** Arreglo en memoria compartida **/
__shared__ int temp_hist[HIST_LENGTH];
/**Inicializacion en 0 **/
temp_hist[threadIdx.x] = 0;
__syncthreads();
index = threadIdx.x + blockIdx.x * blockDim.x;
/** Cada thread debe recorrer los datos segun el offset declarado **/
offset = blockDim.x * gridDim.x;
/** Llenado del histograma **/
while(index < data_length) {
atomicAdd( &temp_hist[data_d[index]], 1);
index += offset;
}
__syncthreads();
/** Traspaso a memoria global **/
atomicAdd(&(hist_d[threadIdx.x]), temp_hist[threadIdx.x]);
}
int main(int argc, char *argv[])
{
float elapsed_Time;
int i, blocks;
int data_length;
int hist_h[HIST_LENGTH], *data_h, *data_d, *hist_d;
hipEvent_t start, stop;
/** Timers **/
hipEventCreate(&start);
hipEventCreate(&stop);
/** Input de datos **/
FILE *in_f = fopen(argv[1], "r");
fscanf(in_f, "%d", &data_length);
data_length *= data_length;
/** Declaracion dinamica del tamano del arreglo dependiendo de la matriz **/
data_h = (int *)malloc(data_length * sizeof(int));
for (i = 0; i < data_length && fscanf(in_f, "%d", &data_h[i]) == 1; ++i);
fclose(in_f);
hipEventRecord(start, 0);
/** Alloc para la memoria en GPU **/
hipMalloc((void **) &data_d, data_length * sizeof(int));
/** Se copian los datos del histograma a la memoria del dispositivo **/
hipMemcpy(data_d, data_h, data_length * sizeof(int), hipMemcpyHostToDevice);
/** Se reserva la memoria para el histograma en el dispositivo y se inicializa en 0 **/
hipMalloc((void **) &hist_d, HIST_LENGTH * sizeof(int));
hipMemset(hist_d, 0, HIST_LENGTH * sizeof(int));
/** Se analizo que los tiempos de ejecucion eran menores al enviar dos veces el numero de
** multiprocesadores presentes **/
hipDeviceProp_t prop;
hipGetDeviceProperties(&prop, 0);
blocks = prop.multiProcessorCount * 2;
/** 256 threads es el numero optimo para la ejecucion **/
histogram_kernel<<<blocks, 256>>>(data_d, data_length, hist_d);
/** Se traspasan los datos del histograma desde el dispositivo **/
hipMemcpy(hist_h, hist_d, 256 * sizeof(int), hipMemcpyDeviceToHost);
/** Se detiene el timer **/
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
hipEventElapsedTime(&elapsed_Time, start, stop);
hipFree(data_d);
hipFree(hist_d);
hipEventDestroy(start);
hipEventDestroy(stop);
/** Datos escritos en el archivo de salida **/
FILE *out = fopen("salida", "w");
for (i = 0; i < 256; i++)
{
if (i == 255)
fprintf(out, "%d", hist_h[i]);
else
fprintf(out, "%d\n", hist_h[i]);
}
fclose(out);
printf("Tiempo de ejecucion: %f ms\n", elapsed_Time);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <stdio.h>
#include <hip/hip_runtime.h>
#define HIST_LENGTH 256
#define THREADS_P_BLOCK 512
__global__ void histogram_kernel(int *data_d, int data_length, int *hist_d)
{
int index, offset;
/** Arreglo en memoria compartida **/
__shared__ int temp_hist[HIST_LENGTH];
/**Inicializacion en 0 **/
temp_hist[threadIdx.x] = 0;
__syncthreads();
index = threadIdx.x + blockIdx.x * blockDim.x;
/** Cada thread debe recorrer los datos segun el offset declarado **/
offset = blockDim.x * gridDim.x;
/** Llenado del histograma **/
while(index < data_length) {
atomicAdd( &temp_hist[data_d[index]], 1);
index += offset;
}
__syncthreads();
/** Traspaso a memoria global **/
atomicAdd(&(hist_d[threadIdx.x]), temp_hist[threadIdx.x]);
}
int main(int argc, char *argv[])
{
float elapsed_Time;
int i, blocks;
int data_length;
int hist_h[HIST_LENGTH], *data_h, *data_d, *hist_d;
hipEvent_t start, stop;
/** Timers **/
hipEventCreate(&start);
hipEventCreate(&stop);
/** Input de datos **/
FILE *in_f = fopen(argv[1], "r");
fscanf(in_f, "%d", &data_length);
data_length *= data_length;
/** Declaracion dinamica del tamano del arreglo dependiendo de la matriz **/
data_h = (int *)malloc(data_length * sizeof(int));
for (i = 0; i < data_length && fscanf(in_f, "%d", &data_h[i]) == 1; ++i);
fclose(in_f);
hipEventRecord(start, 0);
/** Alloc para la memoria en GPU **/
hipMalloc((void **) &data_d, data_length * sizeof(int));
/** Se copian los datos del histograma a la memoria del dispositivo **/
hipMemcpy(data_d, data_h, data_length * sizeof(int), hipMemcpyHostToDevice);
/** Se reserva la memoria para el histograma en el dispositivo y se inicializa en 0 **/
hipMalloc((void **) &hist_d, HIST_LENGTH * sizeof(int));
hipMemset(hist_d, 0, HIST_LENGTH * sizeof(int));
/** Se analizo que los tiempos de ejecucion eran menores al enviar dos veces el numero de
** multiprocesadores presentes **/
hipDeviceProp_t prop;
hipGetDeviceProperties(&prop, 0);
blocks = prop.multiProcessorCount * 2;
/** 256 threads es el numero optimo para la ejecucion **/
histogram_kernel<<<blocks, 256>>>(data_d, data_length, hist_d);
/** Se traspasan los datos del histograma desde el dispositivo **/
hipMemcpy(hist_h, hist_d, 256 * sizeof(int), hipMemcpyDeviceToHost);
/** Se detiene el timer **/
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
hipEventElapsedTime(&elapsed_Time, start, stop);
hipFree(data_d);
hipFree(hist_d);
hipEventDestroy(start);
hipEventDestroy(stop);
/** Datos escritos en el archivo de salida **/
FILE *out = fopen("salida", "w");
for (i = 0; i < 256; i++)
{
if (i == 255)
fprintf(out, "%d", hist_h[i]);
else
fprintf(out, "%d\n", hist_h[i]);
}
fclose(out);
printf("Tiempo de ejecucion: %f ms\n", elapsed_Time);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z16histogram_kernelPiiS_
.globl _Z16histogram_kernelPiiS_
.p2align 8
.type _Z16histogram_kernelPiiS_,@function
_Z16histogram_kernelPiiS_:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x24
s_load_b32 s8, s[0:1], 0x8
s_add_u32 s2, s0, 24
s_addc_u32 s3, s1, 0
v_lshlrev_b32_e32 v4, 2, v0
s_mov_b32 s9, exec_lo
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1)
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
v_mov_b32_e32 v2, 0
ds_store_b32 v4, v2
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_gt_i32_e64 s8, v1
s_cbranch_execz .LBB0_3
s_load_b32 s5, s[2:3], 0x0
s_load_b64 s[2:3], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
v_mov_b32_e32 v5, 1
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_mul_i32 s4, s5, s4
v_add_co_u32 v2, vcc_lo, s2, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
s_ashr_i32 s5, s4, 31
s_mov_b32 s3, 0
s_lshl_b64 s[6:7], s[4:5], 2
.LBB0_2:
global_load_b32 v6, v[2:3], off
v_add_nc_u32_e32 v1, s4, v1
v_add_co_u32 v2, s2, v2, s6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e64 v3, s2, s7, v3, s2
v_cmp_le_i32_e32 vcc_lo, s8, v1
s_or_b32 s3, vcc_lo, s3
s_waitcnt vmcnt(0)
v_lshlrev_b32_e32 v6, 2, v6
ds_add_u32 v6, v5
s_and_not1_b32 exec_lo, exec_lo, s3
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s9
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
ds_load_b32 v1, v4
v_lshlrev_b32_e32 v0, 2, v0
s_waitcnt lgkmcnt(0)
global_atomic_add_u32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z16histogram_kernelPiiS_
.amdhsa_group_segment_fixed_size 1024
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z16histogram_kernelPiiS_, .Lfunc_end0-_Z16histogram_kernelPiiS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 1024
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z16histogram_kernelPiiS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z16histogram_kernelPiiS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <stdio.h>
#include <hip/hip_runtime.h>
#define HIST_LENGTH 256
#define THREADS_P_BLOCK 512
__global__ void histogram_kernel(int *data_d, int data_length, int *hist_d)
{
int index, offset;
/** Arreglo en memoria compartida **/
__shared__ int temp_hist[HIST_LENGTH];
/**Inicializacion en 0 **/
temp_hist[threadIdx.x] = 0;
__syncthreads();
index = threadIdx.x + blockIdx.x * blockDim.x;
/** Cada thread debe recorrer los datos segun el offset declarado **/
offset = blockDim.x * gridDim.x;
/** Llenado del histograma **/
while(index < data_length) {
atomicAdd( &temp_hist[data_d[index]], 1);
index += offset;
}
__syncthreads();
/** Traspaso a memoria global **/
atomicAdd(&(hist_d[threadIdx.x]), temp_hist[threadIdx.x]);
}
int main(int argc, char *argv[])
{
float elapsed_Time;
int i, blocks;
int data_length;
int hist_h[HIST_LENGTH], *data_h, *data_d, *hist_d;
hipEvent_t start, stop;
/** Timers **/
hipEventCreate(&start);
hipEventCreate(&stop);
/** Input de datos **/
FILE *in_f = fopen(argv[1], "r");
fscanf(in_f, "%d", &data_length);
data_length *= data_length;
/** Declaracion dinamica del tamano del arreglo dependiendo de la matriz **/
data_h = (int *)malloc(data_length * sizeof(int));
for (i = 0; i < data_length && fscanf(in_f, "%d", &data_h[i]) == 1; ++i);
fclose(in_f);
hipEventRecord(start, 0);
/** Alloc para la memoria en GPU **/
hipMalloc((void **) &data_d, data_length * sizeof(int));
/** Se copian los datos del histograma a la memoria del dispositivo **/
hipMemcpy(data_d, data_h, data_length * sizeof(int), hipMemcpyHostToDevice);
/** Se reserva la memoria para el histograma en el dispositivo y se inicializa en 0 **/
hipMalloc((void **) &hist_d, HIST_LENGTH * sizeof(int));
hipMemset(hist_d, 0, HIST_LENGTH * sizeof(int));
/** Se analizo que los tiempos de ejecucion eran menores al enviar dos veces el numero de
** multiprocesadores presentes **/
hipDeviceProp_t prop;
hipGetDeviceProperties(&prop, 0);
blocks = prop.multiProcessorCount * 2;
/** 256 threads es el numero optimo para la ejecucion **/
histogram_kernel<<<blocks, 256>>>(data_d, data_length, hist_d);
/** Se traspasan los datos del histograma desde el dispositivo **/
hipMemcpy(hist_h, hist_d, 256 * sizeof(int), hipMemcpyDeviceToHost);
/** Se detiene el timer **/
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
hipEventElapsedTime(&elapsed_Time, start, stop);
hipFree(data_d);
hipFree(hist_d);
hipEventDestroy(start);
hipEventDestroy(stop);
/** Datos escritos en el archivo de salida **/
FILE *out = fopen("salida", "w");
for (i = 0; i < 256; i++)
{
if (i == 255)
fprintf(out, "%d", hist_h[i]);
else
fprintf(out, "%d\n", hist_h[i]);
}
fclose(out);
printf("Tiempo de ejecucion: %f ms\n", elapsed_Time);
return 0;
} | .text
.file "Histograma.hip"
.globl _Z31__device_stub__histogram_kernelPiiS_ # -- Begin function _Z31__device_stub__histogram_kernelPiiS_
.p2align 4, 0x90
.type _Z31__device_stub__histogram_kernelPiiS_,@function
_Z31__device_stub__histogram_kernelPiiS_: # @_Z31__device_stub__histogram_kernelPiiS_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movl %esi, 12(%rsp)
movq %rdx, 64(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z16histogram_kernelPiiS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z31__device_stub__histogram_kernelPiiS_, .Lfunc_end0-_Z31__device_stub__histogram_kernelPiiS_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $2608, %rsp # imm = 0xA30
.cfi_def_cfa_offset 2656
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %rbx
leaq 24(%rsp), %rdi
callq hipEventCreate
leaq 8(%rsp), %rdi
callq hipEventCreate
movq 8(%rbx), %rdi
movl $.L.str, %esi
callq fopen
movq %rax, %r14
leaq 4(%rsp), %rdx
movl $.L.str.1, %esi
movq %rax, %rdi
xorl %eax, %eax
callq __isoc23_fscanf
movl 4(%rsp), %ebp
movl %ebp, %edi
imull %edi, %edi
movl %edi, 4(%rsp)
shlq $2, %rdi
callq malloc
movq %rax, %rbx
testl %ebp, %ebp
je .LBB1_4
# %bb.1: # %.lr.ph.preheader
movq %rbx, %r15
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB1_3: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl $.L.str.1, %esi
movq %r14, %rdi
movq %r15, %rdx
xorl %eax, %eax
callq __isoc23_fscanf
cmpl $1, %eax
jne .LBB1_4
# %bb.2: # in Loop: Header=BB1_3 Depth=1
incq %r12
movslq 4(%rsp), %rax
addq $4, %r15
cmpq %rax, %r12
jl .LBB1_3
.LBB1_4: # %.critedge
movq %r14, %rdi
callq fclose
movq 24(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movslq 4(%rsp), %rsi
shlq $2, %rsi
leaq 32(%rsp), %rdi
callq hipMalloc
movq 32(%rsp), %rdi
movslq 4(%rsp), %rdx
shlq $2, %rdx
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
leaq 16(%rsp), %rdi
movl $1024, %esi # imm = 0x400
callq hipMalloc
movq 16(%rsp), %rdi
movl $1024, %edx # imm = 0x400
xorl %esi, %esi
callq hipMemset
leaq 1136(%rsp), %rdi
xorl %esi, %esi
callq hipGetDevicePropertiesR0600
movl 1524(%rsp), %edi
addl %edi, %edi
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %rdi
orq $256, %rdx # imm = 0x100
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_6
# %bb.5:
movq 32(%rsp), %rax
movl 4(%rsp), %ecx
movq 16(%rsp), %rdx
movq %rax, 104(%rsp)
movl %ecx, 44(%rsp)
movq %rdx, 96(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 44(%rsp), %rax
movq %rax, 120(%rsp)
leaq 96(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rdi
leaq 80(%rsp), %rsi
leaq 72(%rsp), %rdx
leaq 64(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 80(%rsp), %rcx
movl 88(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z16histogram_kernelPiiS_, %edi
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
pushq 80(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_6:
movq 16(%rsp), %rsi
leaq 112(%rsp), %rdi
movl $1024, %edx # imm = 0x400
movl $2, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 8(%rsp), %rdi
callq hipEventSynchronize
movq 24(%rsp), %rsi
movq 8(%rsp), %rdx
leaq 48(%rsp), %rdi
callq hipEventElapsedTime
movq 32(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipEventDestroy
movq 8(%rsp), %rdi
callq hipEventDestroy
movl $.L.str.2, %edi
movl $.L.str.3, %esi
callq fopen
movq %rax, %rbx
leaq 1132(%rsp), %r14
movl $.L.str.1, %r15d
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB1_7: # =>This Inner Loop Header: Depth=1
cmpq $1020, %r12 # imm = 0x3FC
leaq 112(%rsp,%r12), %rax
cmoveq %r14, %rax
movl $.L.str.4, %esi
cmoveq %r15, %rsi
movl (%rax), %edx
movq %rbx, %rdi
xorl %eax, %eax
callq fprintf
addq $4, %r12
cmpq $1024, %r12 # imm = 0x400
jne .LBB1_7
# %bb.8:
movq %rbx, %rdi
callq fclose
movss 48(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.5, %edi
movb $1, %al
callq printf
xorl %eax, %eax
addq $2608, %rsp # imm = 0xA30
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z16histogram_kernelPiiS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z16histogram_kernelPiiS_,@object # @_Z16histogram_kernelPiiS_
.section .rodata,"a",@progbits
.globl _Z16histogram_kernelPiiS_
.p2align 3, 0x0
_Z16histogram_kernelPiiS_:
.quad _Z31__device_stub__histogram_kernelPiiS_
.size _Z16histogram_kernelPiiS_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "r"
.size .L.str, 2
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "%d"
.size .L.str.1, 3
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "salida"
.size .L.str.2, 7
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "w"
.size .L.str.3, 2
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "%d\n"
.size .L.str.4, 4
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Tiempo de ejecucion: %f ms\n"
.size .L.str.5, 28
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z16histogram_kernelPiiS_"
.size .L__unnamed_1, 26
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z31__device_stub__histogram_kernelPiiS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z16histogram_kernelPiiS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z16histogram_kernelPiiS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_TID.X ; /* 0x0000000000047919 */
/* 0x000e220000002100 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0030*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e680000002500 */
/*0040*/ STS [R4.X4], RZ ; /* 0x000000ff04007388 */
/* 0x0011e20000004800 */
/*0050*/ IMAD R0, R3, c[0x0][0x0], R4 ; /* 0x0000000003007a24 */
/* 0x002fc600078e0204 */
/*0060*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe40000010000 */
/*0070*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x168], PT ; /* 0x00005a0000007a0c */
/* 0x000fda0003f06270 */
/*0080*/ @P0 BRA 0x120 ; /* 0x0000009000000947 */
/* 0x001fea0003800000 */
/*0090*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fd400000001ff */
/*00a0*/ IMAD.WIDE R2, R0, R3, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x001fcc00078e0203 */
/*00b0*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ MOV R5, c[0x0][0x0] ; /* 0x0000000000057a02 */
/* 0x000fe20000000f00 */
/*00d0*/ YIELD ; /* 0x0000000000007946 */
/* 0x000fe80003800000 */
/*00e0*/ IMAD R0, R5, c[0x0][0xc], R0 ; /* 0x0000030005007a24 */
/* 0x000fca00078e0200 */
/*00f0*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x168], PT ; /* 0x00005a0000007a0c */
/* 0x000fe20003f06270 */
/*0100*/ ATOMS.POPC.INC.32 RZ, [R2.X4+URZ] ; /* 0x0000000002ff7f8c */
/* 0x0041d8000d00403f */
/*0110*/ @!P0 BRA 0x90 ; /* 0xffffff7000008947 */
/* 0x000fea000383ffff */
/*0120*/ WARPSYNC 0xffffffff ; /* 0xffffffff00007948 */
/* 0x000fe20003800000 */
/*0130*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0140*/ MOV R3, 0x4 ; /* 0x0000000400037802 */
/* 0x000fca0000000f00 */
/*0150*/ IMAD.WIDE.U32 R2, R4, R3, c[0x0][0x170] ; /* 0x00005c0004027625 */
/* 0x001fe200078e0003 */
/*0160*/ LDS R5, [R4.X4] ; /* 0x0000000004057984 */
/* 0x000e280000004800 */
/*0170*/ RED.E.ADD.STRONG.GPU [R2.64], R5 ; /* 0x000000050200798e */
/* 0x001fe2000c10e184 */
/*0180*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0190*/ BRA 0x190; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z16histogram_kernelPiiS_
.globl _Z16histogram_kernelPiiS_
.p2align 8
.type _Z16histogram_kernelPiiS_,@function
_Z16histogram_kernelPiiS_:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x24
s_load_b32 s8, s[0:1], 0x8
s_add_u32 s2, s0, 24
s_addc_u32 s3, s1, 0
v_lshlrev_b32_e32 v4, 2, v0
s_mov_b32 s9, exec_lo
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1)
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
v_mov_b32_e32 v2, 0
ds_store_b32 v4, v2
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_gt_i32_e64 s8, v1
s_cbranch_execz .LBB0_3
s_load_b32 s5, s[2:3], 0x0
s_load_b64 s[2:3], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
v_mov_b32_e32 v5, 1
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_mul_i32 s4, s5, s4
v_add_co_u32 v2, vcc_lo, s2, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
s_ashr_i32 s5, s4, 31
s_mov_b32 s3, 0
s_lshl_b64 s[6:7], s[4:5], 2
.LBB0_2:
global_load_b32 v6, v[2:3], off
v_add_nc_u32_e32 v1, s4, v1
v_add_co_u32 v2, s2, v2, s6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e64 v3, s2, s7, v3, s2
v_cmp_le_i32_e32 vcc_lo, s8, v1
s_or_b32 s3, vcc_lo, s3
s_waitcnt vmcnt(0)
v_lshlrev_b32_e32 v6, 2, v6
ds_add_u32 v6, v5
s_and_not1_b32 exec_lo, exec_lo, s3
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s9
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
ds_load_b32 v1, v4
v_lshlrev_b32_e32 v0, 2, v0
s_waitcnt lgkmcnt(0)
global_atomic_add_u32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z16histogram_kernelPiiS_
.amdhsa_group_segment_fixed_size 1024
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z16histogram_kernelPiiS_, .Lfunc_end0-_Z16histogram_kernelPiiS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 1024
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z16histogram_kernelPiiS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z16histogram_kernelPiiS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00008352_00000000-6_Histograma.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z39__device_stub__Z16histogram_kernelPiiS_PiiS_
.type _Z39__device_stub__Z16histogram_kernelPiiS_PiiS_, @function
_Z39__device_stub__Z16histogram_kernelPiiS_PiiS_:
.LFB2082:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z16histogram_kernelPiiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z39__device_stub__Z16histogram_kernelPiiS_PiiS_, .-_Z39__device_stub__Z16histogram_kernelPiiS_PiiS_
.globl _Z16histogram_kernelPiiS_
.type _Z16histogram_kernelPiiS_, @function
_Z16histogram_kernelPiiS_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z39__device_stub__Z16histogram_kernelPiiS_PiiS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z16histogram_kernelPiiS_, .-_Z16histogram_kernelPiiS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "r"
.LC1:
.string "%d"
.LC2:
.string "w"
.LC3:
.string "salida"
.LC4:
.string "%d\n"
.LC5:
.string "Tiempo de ejecucion: %f ms\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $2128, %rsp
.cfi_def_cfa_offset 2176
movq %rsi, %rbx
movq %fs:40, %rax
movq %rax, 2120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rdi
call cudaEventCreate@PLT
leaq 32(%rsp), %rdi
call cudaEventCreate@PLT
movq 8(%rbx), %rdi
leaq .LC0(%rip), %rsi
call fopen@PLT
movq %rax, %r12
leaq 4(%rsp), %rdx
leaq .LC1(%rip), %rsi
movq %rax, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
movl 4(%rsp), %ebx
imull %ebx, %ebx
movl %ebx, 4(%rsp)
movslq %ebx, %rdi
salq $2, %rdi
call malloc@PLT
movq %rax, %r14
testl %ebx, %ebx
jle .L12
movq %rax, %rbx
movl $0, %ebp
leaq .LC1(%rip), %r13
.L13:
movq %rbx, %rdx
movq %r13, %rsi
movq %r12, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
cmpl $1, %eax
jne .L12
addl $1, %ebp
addq $4, %rbx
cmpl %ebp, 4(%rsp)
jg .L13
.L12:
movq %r12, %rdi
call fclose@PLT
movl $0, %esi
movq 24(%rsp), %rdi
call cudaEventRecord@PLT
movslq 4(%rsp), %rsi
salq $2, %rsi
leaq 8(%rsp), %rdi
call cudaMalloc@PLT
movslq 4(%rsp), %rdx
salq $2, %rdx
movl $1, %ecx
movq %r14, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
leaq 16(%rsp), %rdi
movl $1024, %esi
call cudaMalloc@PLT
movl $1024, %edx
movl $0, %esi
movq 16(%rsp), %rdi
call cudaMemset@PLT
leaq 1088(%rsp), %rdi
movl $0, %esi
call cudaGetDeviceProperties_v2@PLT
movl 1476(%rsp), %eax
addl %eax, %eax
movl $256, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl %eax, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 52(%rsp), %rdx
movl $1, %ecx
movq 40(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L22
.L14:
leaq 64(%rsp), %rbx
movl $2, %ecx
movl $1024, %edx
movq 16(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movl $0, %esi
movq 32(%rsp), %rdi
call cudaEventRecord@PLT
movq 32(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 52(%rsp), %rdi
movq 32(%rsp), %rdx
movq 24(%rsp), %rsi
call cudaEventElapsedTime@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaEventDestroy@PLT
movq 32(%rsp), %rdi
call cudaEventDestroy@PLT
leaq .LC2(%rip), %rsi
leaq .LC3(%rip), %rdi
call fopen@PLT
movq %rax, %rbp
leaq 1084(%rsp), %r14
leaq 1088(%rsp), %r13
leaq .LC4(%rip), %r12
.L15:
movl (%rbx), %ecx
movq %r12, %rdx
movl $2, %esi
movq %rbp, %rdi
movl $0, %eax
call __fprintf_chk@PLT
addq $4, %rbx
cmpq %r13, %rbx
je .L16
cmpq %r14, %rbx
jne .L15
movl 1084(%rsp), %ecx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq %rbp, %rdi
movl $0, %eax
call __fprintf_chk@PLT
.L16:
movq %rbp, %rdi
call fclose@PLT
pxor %xmm0, %xmm0
cvtss2sd 52(%rsp), %xmm0
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 2120(%rsp), %rax
subq %fs:40, %rax
jne .L23
movl $0, %eax
addq $2128, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L22:
.cfi_restore_state
movq 16(%rsp), %rdx
movl 4(%rsp), %esi
movq 8(%rsp), %rdi
call _Z39__device_stub__Z16histogram_kernelPiiS_PiiS_
jmp .L14
.L23:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC6:
.string "_Z16histogram_kernelPiiS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _Z16histogram_kernelPiiS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "Histograma.hip"
.globl _Z31__device_stub__histogram_kernelPiiS_ # -- Begin function _Z31__device_stub__histogram_kernelPiiS_
.p2align 4, 0x90
.type _Z31__device_stub__histogram_kernelPiiS_,@function
_Z31__device_stub__histogram_kernelPiiS_: # @_Z31__device_stub__histogram_kernelPiiS_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movl %esi, 12(%rsp)
movq %rdx, 64(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z16histogram_kernelPiiS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z31__device_stub__histogram_kernelPiiS_, .Lfunc_end0-_Z31__device_stub__histogram_kernelPiiS_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $2608, %rsp # imm = 0xA30
.cfi_def_cfa_offset 2656
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %rbx
leaq 24(%rsp), %rdi
callq hipEventCreate
leaq 8(%rsp), %rdi
callq hipEventCreate
movq 8(%rbx), %rdi
movl $.L.str, %esi
callq fopen
movq %rax, %r14
leaq 4(%rsp), %rdx
movl $.L.str.1, %esi
movq %rax, %rdi
xorl %eax, %eax
callq __isoc23_fscanf
movl 4(%rsp), %ebp
movl %ebp, %edi
imull %edi, %edi
movl %edi, 4(%rsp)
shlq $2, %rdi
callq malloc
movq %rax, %rbx
testl %ebp, %ebp
je .LBB1_4
# %bb.1: # %.lr.ph.preheader
movq %rbx, %r15
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB1_3: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl $.L.str.1, %esi
movq %r14, %rdi
movq %r15, %rdx
xorl %eax, %eax
callq __isoc23_fscanf
cmpl $1, %eax
jne .LBB1_4
# %bb.2: # in Loop: Header=BB1_3 Depth=1
incq %r12
movslq 4(%rsp), %rax
addq $4, %r15
cmpq %rax, %r12
jl .LBB1_3
.LBB1_4: # %.critedge
movq %r14, %rdi
callq fclose
movq 24(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movslq 4(%rsp), %rsi
shlq $2, %rsi
leaq 32(%rsp), %rdi
callq hipMalloc
movq 32(%rsp), %rdi
movslq 4(%rsp), %rdx
shlq $2, %rdx
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
leaq 16(%rsp), %rdi
movl $1024, %esi # imm = 0x400
callq hipMalloc
movq 16(%rsp), %rdi
movl $1024, %edx # imm = 0x400
xorl %esi, %esi
callq hipMemset
leaq 1136(%rsp), %rdi
xorl %esi, %esi
callq hipGetDevicePropertiesR0600
movl 1524(%rsp), %edi
addl %edi, %edi
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %rdi
orq $256, %rdx # imm = 0x100
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_6
# %bb.5:
movq 32(%rsp), %rax
movl 4(%rsp), %ecx
movq 16(%rsp), %rdx
movq %rax, 104(%rsp)
movl %ecx, 44(%rsp)
movq %rdx, 96(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 44(%rsp), %rax
movq %rax, 120(%rsp)
leaq 96(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rdi
leaq 80(%rsp), %rsi
leaq 72(%rsp), %rdx
leaq 64(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 80(%rsp), %rcx
movl 88(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z16histogram_kernelPiiS_, %edi
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
pushq 80(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_6:
movq 16(%rsp), %rsi
leaq 112(%rsp), %rdi
movl $1024, %edx # imm = 0x400
movl $2, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 8(%rsp), %rdi
callq hipEventSynchronize
movq 24(%rsp), %rsi
movq 8(%rsp), %rdx
leaq 48(%rsp), %rdi
callq hipEventElapsedTime
movq 32(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipEventDestroy
movq 8(%rsp), %rdi
callq hipEventDestroy
movl $.L.str.2, %edi
movl $.L.str.3, %esi
callq fopen
movq %rax, %rbx
leaq 1132(%rsp), %r14
movl $.L.str.1, %r15d
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB1_7: # =>This Inner Loop Header: Depth=1
cmpq $1020, %r12 # imm = 0x3FC
leaq 112(%rsp,%r12), %rax
cmoveq %r14, %rax
movl $.L.str.4, %esi
cmoveq %r15, %rsi
movl (%rax), %edx
movq %rbx, %rdi
xorl %eax, %eax
callq fprintf
addq $4, %r12
cmpq $1024, %r12 # imm = 0x400
jne .LBB1_7
# %bb.8:
movq %rbx, %rdi
callq fclose
movss 48(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.5, %edi
movb $1, %al
callq printf
xorl %eax, %eax
addq $2608, %rsp # imm = 0xA30
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z16histogram_kernelPiiS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z16histogram_kernelPiiS_,@object # @_Z16histogram_kernelPiiS_
.section .rodata,"a",@progbits
.globl _Z16histogram_kernelPiiS_
.p2align 3, 0x0
_Z16histogram_kernelPiiS_:
.quad _Z31__device_stub__histogram_kernelPiiS_
.size _Z16histogram_kernelPiiS_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "r"
.size .L.str, 2
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "%d"
.size .L.str.1, 3
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "salida"
.size .L.str.2, 7
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "w"
.size .L.str.3, 2
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "%d\n"
.size .L.str.4, 4
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Tiempo de ejecucion: %f ms\n"
.size .L.str.5, 28
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z16histogram_kernelPiiS_"
.size .L__unnamed_1, 26
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z31__device_stub__histogram_kernelPiiS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z16histogram_kernelPiiS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <iostream>
#include <cstdlib>
#include <cfloat>
#include <math.h>
#include <sys/time.h>
#define THREADS_PER_BLOCK 32
__global__ void voronoi_d (int *imageArray, int *points, int imageSize, int numPoints) {
// use x to access each cell and compare it to each point and assign the cell's value to match the closest point
int x = blockIdx.x * blockDim.x + threadIdx.x;
double minDistance = DBL_MAX;
int minPoint = -1;
for (int k=0; k<numPoints; k++) {
double distance = sqrt(pow((double) (x % imageSize - points[k + numPoints]), 2.0) + pow((double) (x / imageSize - points[k]), 2.0));
if (distance < minDistance) {
minDistance = distance;
minPoint = k;
}
}
imageArray[x] = minPoint;
}
extern void gpuVoronoi(int *imageArray_h, int *points_h, int imageSize, int numPoints)
{
// allocate space for the image and point coordinates on the device and copy the coordinates over
int *imageArray;
int *points;
cudaMalloc ((void**) &imageArray, sizeof(int) * imageSize * imageSize);
cudaMalloc ((void**) &points, sizeof(int) * numPoints * 2);
cudaMemcpy (points, points_h, sizeof(int) * numPoints * 2, cudaMemcpyHostToDevice);
// start calculation timing
struct timeval start, end;
gettimeofday(&start, NULL);
// calculate and then synchronize to ensure accurate timing
voronoi_d <<< ceil((float) imageSize*imageSize/THREADS_PER_BLOCK), THREADS_PER_BLOCK >>> (imageArray, points, imageSize, numPoints);
cudaDeviceSynchronize();
// end timing and print processing time
gettimeofday(&end, NULL);
long seconds = (end.tv_sec - start.tv_sec);
long micros = ((seconds * 1000000) + end.tv_usec) - (start.tv_usec);
printf("Processing time elpased is %zu seconds or %zu micros\n", seconds, micros);
// print CUDA errors
cudaError_t err = cudaGetLastError();
printf("CUDA error: %s\n", cudaGetErrorString(err));
// copy results to host and free device memory
cudaMemcpy (imageArray_h, imageArray, sizeof(int) * imageSize * imageSize, cudaMemcpyDeviceToHost);
cudaFree (imageArray);
cudaFree (points);
} | code for sm_80
Function : _Z9voronoi_dPiS_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e220000002500 */
/*0020*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x174] ; /* 0x00005d00ff007624 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ IMAD.MOV.U32 R5, RZ, RZ, -0x1 ; /* 0xffffffffff057424 */
/* 0x000fe200078e00ff */
/*0050*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0060*/ ISETP.GE.AND P0, PT, R0, 0x1, PT ; /* 0x000000010000780c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R4, R4, c[0x0][0x0], R3 ; /* 0x0000000004047a24 */
/* 0x001fd800078e0203 */
/*0080*/ @!P0 BRA 0x8b0 ; /* 0x0000082000008947 */
/* 0x000fea0003800000 */
/*0090*/ IABS R5, c[0x0][0x170] ; /* 0x00005c0000057a13 */
/* 0x000fe20000000000 */
/*00a0*/ IMAD.MOV.U32 R8, RZ, RZ, -0x1 ; /* 0xffffffffff087424 */
/* 0x000fe400078e00ff */
/*00b0*/ IMAD.MOV.U32 R9, RZ, RZ, 0x7fefffff ; /* 0x7fefffffff097424 */
/* 0x000fe200078e00ff */
/*00c0*/ I2F.RP R0, R5 ; /* 0x0000000500007306 */
/* 0x000e300000209400 */
/*00d0*/ MUFU.RCP R0, R0 ; /* 0x0000000000007308 */
/* 0x001e240000001000 */
/*00e0*/ IADD3 R2, R0, 0xffffffe, RZ ; /* 0x0ffffffe00027810 */
/* 0x001fcc0007ffe0ff */
/*00f0*/ F2I.FTZ.U32.TRUNC.NTZ R3, R2 ; /* 0x0000000200037305 */
/* 0x000064000021f000 */
/*0100*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x001fe400078e00ff */
/*0110*/ IMAD.MOV R6, RZ, RZ, -R3 ; /* 0x000000ffff067224 */
/* 0x002fc800078e0a03 */
/*0120*/ IMAD R7, R6, R5, RZ ; /* 0x0000000506077224 */
/* 0x000fe200078e02ff */
/*0130*/ IABS R6, R4 ; /* 0x0000000400067213 */
/* 0x000fc60000000000 */
/*0140*/ IMAD.HI.U32 R3, R3, R7, R2 ; /* 0x0000000703037227 */
/* 0x000fc800078e0002 */
/*0150*/ IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff077624 */
/* 0x000fe400078e00ff */
/*0160*/ IMAD.HI.U32 R3, R3, R6, RZ ; /* 0x0000000603037227 */
/* 0x000fc800078e00ff */
/*0170*/ IMAD.MOV R0, RZ, RZ, -R3 ; /* 0x000000ffff007224 */
/* 0x000fc800078e0a03 */
/*0180*/ IMAD R0, R5, R0, R6 ; /* 0x0000000005007224 */
/* 0x000fe400078e0206 */
/*0190*/ IMAD.MOV.U32 R6, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff067624 */
/* 0x000fc600078e00ff */
/*01a0*/ ISETP.GT.U32.AND P2, PT, R5, R0, PT ; /* 0x000000000500720c */
/* 0x000fda0003f44070 */
/*01b0*/ @!P2 IMAD.IADD R0, R0, 0x1, -R5 ; /* 0x000000010000a824 */
/* 0x000fe200078e0a05 */
/*01c0*/ @!P2 IADD3 R3, R3, 0x1, RZ ; /* 0x000000010303a810 */
/* 0x000fe40007ffe0ff */
/*01d0*/ ISETP.NE.AND P2, PT, RZ, c[0x0][0x170], PT ; /* 0x00005c00ff007a0c */
/* 0x000fe40003f45270 */
/*01e0*/ ISETP.GE.U32.AND P0, PT, R0, R5, PT ; /* 0x000000050000720c */
/* 0x000fe20003f06070 */
/*01f0*/ IMAD.MOV.U32 R5, RZ, RZ, -0x1 ; /* 0xffffffffff057424 */
/* 0x000fe200078e00ff */
/*0200*/ LOP3.LUT R0, R4, c[0x0][0x170], RZ, 0x3c, !PT ; /* 0x00005c0004007a12 */
/* 0x000fc800078e3cff */
/*0210*/ ISETP.GE.AND P1, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fce0003f26270 */
/*0220*/ @P0 IADD3 R3, R3, 0x1, RZ ; /* 0x0000000103030810 */
/* 0x000fcc0007ffe0ff */
/*0230*/ @!P1 IMAD.MOV R3, RZ, RZ, -R3 ; /* 0x000000ffff039224 */
/* 0x000fe200078e0a03 */
/*0240*/ @!P2 LOP3.LUT R3, RZ, c[0x0][0x170], RZ, 0x33, !PT ; /* 0x00005c00ff03aa12 */
/* 0x000fca00078e33ff */
/*0250*/ IMAD.MOV R11, RZ, RZ, -R3 ; /* 0x000000ffff0b7224 */
/* 0x000fc800078e0a03 */
/*0260*/ IMAD R0, R11, c[0x0][0x170], R4 ; /* 0x00005c000b007a24 */
/* 0x000fe400078e0204 */
/*0270*/ IMAD.MOV.U32 R11, RZ, RZ, c[0x0][0x174] ; /* 0x00005d00ff0b7624 */
/* 0x000fc800078e00ff */
/*0280*/ IMAD.WIDE R10, R11, 0x4, R6 ; /* 0x000000040b0a7825 */
/* 0x000fcc00078e0206 */
/*0290*/ LDG.E R11, [R10.64] ; /* 0x000000040a0b7981 */
/* 0x000ea2000c1e1900 */
/*02a0*/ BSSY B0, 0x370 ; /* 0x000000c000007945 */
/* 0x000fe20003800000 */
/*02b0*/ IMAD.IADD R30, R0, 0x1, -R11 ; /* 0x00000001001e7824 */
/* 0x004fc800078e0a0b */
/*02c0*/ I2F.F64 R28, R30 ; /* 0x0000001e001c7312 */
/* 0x0030620000201c00 */
/*02d0*/ ISETP.NE.AND P0, PT, R30, RZ, PT ; /* 0x000000ff1e00720c */
/* 0x000fda0003f05270 */
/*02e0*/ @!P0 BRA 0x350 ; /* 0x0000006000008947 */
/* 0x000fea0003800000 */
/*02f0*/ DADD R10, -RZ, |R28| ; /* 0x00000000ff0a7229 */
/* 0x003e22000000051c */
/*0300*/ MOV R32, 0x340 ; /* 0x0000034000207802 */
/* 0x000fd20000000f00 */
/*0310*/ IMAD.MOV.U32 R14, RZ, RZ, R10 ; /* 0x000000ffff0e7224 */
/* 0x001fe400078e000a */
/*0320*/ IMAD.MOV.U32 R12, RZ, RZ, R11 ; /* 0x000000ffff0c7224 */
/* 0x000fe400078e000b */
/*0330*/ CALL.REL.NOINC 0xbc0 ; /* 0x0000088000007944 */
/* 0x000fea0003c00000 */
/*0340*/ BRA 0x360 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0350*/ CS2R R10, SRZ ; /* 0x00000000000a7805 */
/* 0x001fe4000001ff00 */
/*0360*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0370*/ DADD R12, R28, 2 ; /* 0x400000001c0c7429 */
/* 0x002e220000000000 */
/*0380*/ BSSY B0, 0x470 ; /* 0x000000e000007945 */
/* 0x000ff20003800000 */
/*0390*/ LOP3.LUT R12, R13, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff000000d0c7812 */
/* 0x001fc800078ec0ff */
/*03a0*/ ISETP.NE.AND P0, PT, R12, 0x7ff00000, PT ; /* 0x7ff000000c00780c */
/* 0x000fda0003f05270 */
/*03b0*/ @P0 BRA 0x460 ; /* 0x000000a000000947 */
/* 0x000fea0003800000 */
/*03c0*/ DSETP.GTU.AND P0, PT, |R28|, +INF , PT ; /* 0x7ff000001c00742a */
/* 0x000e1c0003f0c200 */
/*03d0*/ @P0 BRA 0x450 ; /* 0x0000007000000947 */
/* 0x001fea0003800000 */
/*03e0*/ ISETP.NE.AND P0, PT, R28, RZ, PT ; /* 0x000000ff1c00720c */
/* 0x000fe40003f05270 */
/*03f0*/ LOP3.LUT R28, R29, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff1d1c7812 */
/* 0x000fc800078ec0ff */
/*0400*/ ISETP.NE.OR P0, PT, R28, 0x7ff00000, P0 ; /* 0x7ff000001c00780c */
/* 0x000fda0000705670 */
/*0410*/ @P0 BRA 0x460 ; /* 0x0000004000000947 */
/* 0x000fea0003800000 */
/*0420*/ IMAD.MOV.U32 R10, RZ, RZ, 0x0 ; /* 0x00000000ff0a7424 */
/* 0x000fe400078e00ff */
/*0430*/ IMAD.MOV.U32 R11, RZ, RZ, 0x7ff00000 ; /* 0x7ff00000ff0b7424 */
/* 0x000fe200078e00ff */
/*0440*/ BRA 0x460 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0450*/ DADD R10, R28, 2 ; /* 0x400000001c0a7429 */
/* 0x00004c0000000000 */
/*0460*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0470*/ LDG.E R34, [R6.64] ; /* 0x0000000406227981 */
/* 0x000ea2000c1e1900 */
/*0480*/ ISETP.NE.AND P0, PT, R30, 0x1, PT ; /* 0x000000011e00780c */
/* 0x000fe20003f05270 */
/*0490*/ BSSY B0, 0x580 ; /* 0x000000e000007945 */
/* 0x000fe60003800000 */
/*04a0*/ FSEL R30, R10, RZ, P0 ; /* 0x000000ff0a1e7208 */
/* 0x002fe40000000000 */
/*04b0*/ FSEL R31, R11, 1.875, P0 ; /* 0x3ff000000b1f7808 */
/* 0x000fe20000000000 */
/*04c0*/ IMAD.IADD R34, R3, 0x1, -R34 ; /* 0x0000000103227824 */
/* 0x004fc800078e0a22 */
/*04d0*/ I2F.F64 R28, R34 ; /* 0x00000022001c7312 */
/* 0x0010620000201c00 */
/*04e0*/ ISETP.NE.AND P1, PT, R34, RZ, PT ; /* 0x000000ff2200720c */
/* 0x000fda0003f25270 */
/*04f0*/ @!P1 BRA 0x560 ; /* 0x0000006000009947 */
/* 0x000fea0003800000 */
/*0500*/ DADD R10, -RZ, |R28| ; /* 0x00000000ff0a7229 */
/* 0x003e22000000051c */
/*0510*/ MOV R32, 0x550 ; /* 0x0000055000207802 */
/* 0x000fd20000000f00 */
/*0520*/ IMAD.MOV.U32 R14, RZ, RZ, R10 ; /* 0x000000ffff0e7224 */
/* 0x001fe200078e000a */
/*0530*/ MOV R12, R11 ; /* 0x0000000b000c7202 */
/* 0x000fe40000000f00 */
/*0540*/ CALL.REL.NOINC 0xbc0 ; /* 0x0000067000007944 */
/* 0x000fea0003c00000 */
/*0550*/ BRA 0x570 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0560*/ CS2R R10, SRZ ; /* 0x00000000000a7805 */
/* 0x001fe4000001ff00 */
/*0570*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0580*/ DADD R12, R28, 2 ; /* 0x400000001c0c7429 */
/* 0x002e220000000000 */
/*0590*/ BSSY B0, 0x680 ; /* 0x000000e000007945 */
/* 0x000ff20003800000 */
/*05a0*/ LOP3.LUT R12, R13, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff000000d0c7812 */
/* 0x001fc800078ec0ff */
/*05b0*/ ISETP.NE.AND P0, PT, R12, 0x7ff00000, PT ; /* 0x7ff000000c00780c */
/* 0x000fda0003f05270 */
/*05c0*/ @P0 BRA 0x670 ; /* 0x000000a000000947 */
/* 0x000fea0003800000 */
/*05d0*/ DSETP.GTU.AND P0, PT, |R28|, +INF , PT ; /* 0x7ff000001c00742a */
/* 0x000e1c0003f0c200 */
/*05e0*/ @P0 BRA 0x660 ; /* 0x0000007000000947 */
/* 0x001fea0003800000 */
/*05f0*/ ISETP.NE.AND P0, PT, R28, RZ, PT ; /* 0x000000ff1c00720c */
/* 0x000fe40003f05270 */
/*0600*/ LOP3.LUT R28, R29, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff1d1c7812 */
/* 0x000fc800078ec0ff */
/*0610*/ ISETP.NE.OR P0, PT, R28, 0x7ff00000, P0 ; /* 0x7ff000001c00780c */
/* 0x000fda0000705670 */
/*0620*/ @P0 BRA 0x670 ; /* 0x0000004000000947 */
/* 0x000fea0003800000 */
/*0630*/ IMAD.MOV.U32 R10, RZ, RZ, 0x0 ; /* 0x00000000ff0a7424 */
/* 0x000fe400078e00ff */
/*0640*/ IMAD.MOV.U32 R11, RZ, RZ, 0x7ff00000 ; /* 0x7ff00000ff0b7424 */
/* 0x000fe200078e00ff */
/*0650*/ BRA 0x670 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0660*/ DADD R10, R28, 2 ; /* 0x400000001c0a7429 */
/* 0x00004c0000000000 */
/*0670*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0680*/ ISETP.NE.AND P0, PT, R34, 0x1, PT ; /* 0x000000012200780c */
/* 0x000fe20003f05270 */
/*0690*/ IMAD.MOV.U32 R14, RZ, RZ, 0x0 ; /* 0x00000000ff0e7424 */
/* 0x000fe200078e00ff */
/*06a0*/ BSSY B0, 0x820 ; /* 0x0000017000007945 */
/* 0x000fe20003800000 */
/*06b0*/ IMAD.MOV.U32 R15, RZ, RZ, 0x3fd80000 ; /* 0x3fd80000ff0f7424 */
/* 0x000fe200078e00ff */
/*06c0*/ FSEL R10, R10, RZ, P0 ; /* 0x000000ff0a0a7208 */
/* 0x002fe40000000000 */
/*06d0*/ FSEL R11, R11, 1.875, P0 ; /* 0x3ff000000b0b7808 */
/* 0x000fcc0000000000 */
/*06e0*/ DADD R30, R30, R10 ; /* 0x000000001e1e7229 */
/* 0x000e4c000000000a */
/*06f0*/ MUFU.RSQ64H R13, R31 ; /* 0x0000001f000d7308 */
/* 0x002e680000001c00 */
/*0700*/ IADD3 R12, R31, -0x3500000, RZ ; /* 0xfcb000001f0c7810 */
/* 0x000fc80007ffe0ff */
/*0710*/ ISETP.GE.U32.AND P0, PT, R12, 0x7ca00000, PT ; /* 0x7ca000000c00780c */
/* 0x000fe40003f06070 */
/*0720*/ DMUL R10, R12, R12 ; /* 0x0000000c0c0a7228 */
/* 0x002e4c0000000000 */
/*0730*/ DFMA R10, R30, -R10, 1 ; /* 0x3ff000001e0a742b */
/* 0x002e4c000000080a */
/*0740*/ DFMA R14, R10, R14, 0.5 ; /* 0x3fe000000a0e742b */
/* 0x002fc8000000000e */
/*0750*/ DMUL R10, R12, R10 ; /* 0x0000000a0c0a7228 */
/* 0x000e4c0000000000 */
/*0760*/ DFMA R16, R14, R10, R12 ; /* 0x0000000a0e10722b */
/* 0x002e4c000000000c */
/*0770*/ DMUL R18, R30, R16 ; /* 0x000000101e127228 */
/* 0x002e480000000000 */
/*0780*/ IADD3 R15, R17, -0x100000, RZ ; /* 0xfff00000110f7810 */
/* 0x000fe20007ffe0ff */
/*0790*/ IMAD.MOV.U32 R14, RZ, RZ, R16 ; /* 0x000000ffff0e7224 */
/* 0x000fe200078e0010 */
/*07a0*/ DFMA R20, R18, -R18, R30 ; /* 0x800000121214722b */
/* 0x002e4c000000001e */
/*07b0*/ DFMA R10, R20, R14, R18 ; /* 0x0000000e140a722b */
/* 0x0022a20000000012 */
/*07c0*/ @!P0 BRA 0x810 ; /* 0x0000004000008947 */
/* 0x000fea0003800000 */
/*07d0*/ MOV R10, 0x7f0 ; /* 0x000007f0000a7802 */
/* 0x004fca0000000f00 */
/*07e0*/ CALL.REL.NOINC 0x8f0 ; /* 0x0000010000007944 */
/* 0x003fea0003c00000 */
/*07f0*/ IMAD.MOV.U32 R10, RZ, RZ, R12 ; /* 0x000000ffff0a7224 */
/* 0x002fe400078e000c */
/*0800*/ IMAD.MOV.U32 R11, RZ, RZ, R13 ; /* 0x000000ffff0b7224 */
/* 0x000fe400078e000d */
/*0810*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0820*/ DSETP.GEU.AND P0, PT, R10, R8, PT ; /* 0x000000080a00722a */
/* 0x004ea20003f0e000 */
/*0830*/ IADD3 R6, P2, R6, 0x4, RZ ; /* 0x0000000406067810 */
/* 0x000fca0007f5e0ff */
/*0840*/ SEL R5, R2.reuse, R5, !P0 ; /* 0x0000000502057207 */
/* 0x044fe20004000000 */
/*0850*/ IMAD.X R7, RZ, RZ, R7, P2 ; /* 0x000000ffff077224 */
/* 0x000fe200010e0607 */
/*0860*/ IADD3 R2, R2, 0x1, RZ ; /* 0x0000000102027810 */
/* 0x000fe40007ffe0ff */
/*0870*/ FSEL R8, R10, R8, !P0 ; /* 0x000000080a087208 */
/* 0x000fe40004000000 */
/*0880*/ ISETP.GE.AND P1, PT, R2, c[0x0][0x174], PT ; /* 0x00005d0002007a0c */
/* 0x000fe40003f26270 */
/*0890*/ FSEL R9, R11, R9, !P0 ; /* 0x000000090b097208 */
/* 0x000fd60004000000 */
/*08a0*/ @!P1 BRA 0x270 ; /* 0xfffff9c000009947 */
/* 0x000fea000383ffff */
/*08b0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fc800078e00ff */
/*08c0*/ IMAD.WIDE R2, R4, R3, c[0x0][0x160] ; /* 0x0000580004027625 */
/* 0x000fca00078e0203 */
/*08d0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*08e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*08f0*/ ISETP.GE.U32.AND P0, PT, R12, -0x3400000, PT ; /* 0xfcc000000c00780c */
/* 0x000fe20003f06070 */
/*0900*/ BSSY B1, 0xba0 ; /* 0x0000029000017945 */
/* 0x000fe20003800000 */
/*0910*/ IMAD.MOV.U32 R17, RZ, RZ, R15 ; /* 0x000000ffff117224 */
/* 0x000fe400078e000f */
/*0920*/ IMAD.MOV.U32 R14, RZ, RZ, R30 ; /* 0x000000ffff0e7224 */
/* 0x000fe400078e001e */
/*0930*/ IMAD.MOV.U32 R15, RZ, RZ, R31 ; /* 0x000000ffff0f7224 */
/* 0x000fe400078e001f */
/*0940*/ IMAD.MOV.U32 R12, RZ, RZ, R20 ; /* 0x000000ffff0c7224 */
/* 0x000fe400078e0014 */
/*0950*/ IMAD.MOV.U32 R13, RZ, RZ, R21 ; /* 0x000000ffff0d7224 */
/* 0x000fc600078e0015 */
/*0960*/ @!P0 BRA 0x9f0 ; /* 0x0000008000008947 */
/* 0x000fea0003800000 */
/*0970*/ DFMA.RM R12, R12, R16, R18 ; /* 0x000000100c0c722b */
/* 0x000e140000004012 */
/*0980*/ IADD3 R16, P0, R12, 0x1, RZ ; /* 0x000000010c107810 */
/* 0x001fc80007f1e0ff */
/*0990*/ IADD3.X R17, RZ, R13, RZ, P0, !PT ; /* 0x0000000dff117210 */
/* 0x000fcc00007fe4ff */
/*09a0*/ DFMA.RP R14, -R12, R16, R14 ; /* 0x000000100c0e722b */
/* 0x000e0c000000810e */
/*09b0*/ DSETP.GT.AND P0, PT, R14, RZ, PT ; /* 0x000000ff0e00722a */
/* 0x001e0c0003f04000 */
/*09c0*/ FSEL R12, R16, R12, P0 ; /* 0x0000000c100c7208 */
/* 0x001fe40000000000 */
/*09d0*/ FSEL R13, R17, R13, P0 ; /* 0x0000000d110d7208 */
/* 0x000fe20000000000 */
/*09e0*/ BRA 0xb90 ; /* 0x000001a000007947 */
/* 0x000fea0003800000 */
/*09f0*/ DSETP.NE.AND P0, PT, R14, RZ, PT ; /* 0x000000ff0e00722a */
/* 0x000e1c0003f05000 */
/*0a00*/ @!P0 BRA 0xb50 ; /* 0x0000014000008947 */
/* 0x001fea0003800000 */
/*0a10*/ ISETP.GE.AND P0, PT, R15, RZ, PT ; /* 0x000000ff0f00720c */
/* 0x000fda0003f06270 */
/*0a20*/ @!P0 BRA 0xb70 ; /* 0x0000014000008947 */
/* 0x000fea0003800000 */
/*0a30*/ ISETP.GT.AND P0, PT, R15, 0x7fefffff, PT ; /* 0x7fefffff0f00780c */
/* 0x000fda0003f04270 */
/*0a40*/ @P0 BRA 0xb50 ; /* 0x0000010000000947 */
/* 0x000fea0003800000 */
/*0a50*/ DMUL R12, R14, 8.11296384146066816958e+31 ; /* 0x469000000e0c7828 */
/* 0x0000620000000000 */
/*0a60*/ IMAD.MOV.U32 R18, RZ, RZ, 0x0 ; /* 0x00000000ff127424 */
/* 0x000fe400078e00ff */
/*0a70*/ IMAD.MOV.U32 R14, RZ, RZ, RZ ; /* 0x000000ffff0e7224 */
/* 0x001fe400078e00ff */
/*0a80*/ IMAD.MOV.U32 R19, RZ, RZ, 0x3fd80000 ; /* 0x3fd80000ff137424 */
/* 0x000fe200078e00ff */
/*0a90*/ MUFU.RSQ64H R15, R13 ; /* 0x0000000d000f7308 */
/* 0x002e260000001c00 */
/*0aa0*/ DMUL R16, R14, R14 ; /* 0x0000000e0e107228 */
/* 0x001e0c0000000000 */
/*0ab0*/ DFMA R16, R12, -R16, 1 ; /* 0x3ff000000c10742b */
/* 0x001e0c0000000810 */
/*0ac0*/ DFMA R18, R16, R18, 0.5 ; /* 0x3fe000001012742b */
/* 0x001fc80000000012 */
/*0ad0*/ DMUL R16, R14, R16 ; /* 0x000000100e107228 */
/* 0x000e0c0000000000 */
/*0ae0*/ DFMA R16, R18, R16, R14 ; /* 0x000000101210722b */
/* 0x001e0c000000000e */
/*0af0*/ DMUL R14, R12, R16 ; /* 0x000000100c0e7228 */
/* 0x0010480000000000 */
/*0b00*/ IADD3 R17, R17, -0x100000, RZ ; /* 0xfff0000011117810 */
/* 0x001fe40007ffe0ff */
/*0b10*/ DFMA R18, R14, -R14, R12 ; /* 0x8000000e0e12722b */
/* 0x002e0c000000000c */
/*0b20*/ DFMA R12, R16, R18, R14 ; /* 0x00000012100c722b */
/* 0x001e14000000000e */
/*0b30*/ IADD3 R13, R13, -0x3500000, RZ ; /* 0xfcb000000d0d7810 */
/* 0x001fe20007ffe0ff */
/*0b40*/ BRA 0xb90 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*0b50*/ DADD R12, R14, R14 ; /* 0x000000000e0c7229 */
/* 0x000062000000000e */
/*0b60*/ BRA 0xb90 ; /* 0x0000002000007947 */
/* 0x000fea0003800000 */
/*0b70*/ IMAD.MOV.U32 R12, RZ, RZ, 0x0 ; /* 0x00000000ff0c7424 */
/* 0x000fe400078e00ff */
/*0b80*/ IMAD.MOV.U32 R13, RZ, RZ, -0x80000 ; /* 0xfff80000ff0d7424 */
/* 0x000fe400078e00ff */
/*0b90*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0ba0*/ IMAD.MOV.U32 R11, RZ, RZ, 0x0 ; /* 0x00000000ff0b7424 */
/* 0x000fc800078e00ff */
/*0bb0*/ RET.REL.NODEC R10 0x0 ; /* 0xfffff4400a007950 */
/* 0x000fea0003c3ffff */
/*0bc0*/ SHF.R.U32.HI R33, RZ, 0x14, R12 ; /* 0x00000014ff217819 */
/* 0x000fe2000001160c */
/*0bd0*/ IMAD.MOV.U32 R10, RZ, RZ, R14 ; /* 0x000000ffff0a7224 */
/* 0x000fe400078e000e */
/*0be0*/ IMAD.MOV.U32 R11, RZ, RZ, R12 ; /* 0x000000ffff0b7224 */
/* 0x000fe200078e000c */
/*0bf0*/ ISETP.NE.AND P0, PT, R33, RZ, PT ; /* 0x000000ff2100720c */
/* 0x000fe20003f05270 */
/*0c00*/ IMAD.MOV.U32 R18, RZ, RZ, RZ ; /* 0x000000ffff127224 */
/* 0x000fe400078e00ff */
/*0c10*/ IMAD.MOV.U32 R16, RZ, RZ, 0x7d2cafe2 ; /* 0x7d2cafe2ff107424 */
/* 0x000fe400078e00ff */
/*0c20*/ IMAD.MOV.U32 R17, RZ, RZ, 0x3eb0f5ff ; /* 0x3eb0f5ffff117424 */
/* 0x000fd000078e00ff */
/*0c30*/ @!P0 DMUL R10, R10, 1.80143985094819840000e+16 ; /* 0x435000000a0a8828 */
/* 0x000e140000000000 */
/*0c40*/ @!P0 IMAD.MOV.U32 R12, RZ, RZ, R11 ; /* 0x000000ffff0c8224 */
/* 0x001fe200078e000b */
/*0c50*/ @!P0 LEA.HI R33, R11, 0xffffffca, RZ, 0xc ; /* 0xffffffca0b218811 */
/* 0x000fe200078f60ff */
/*0c60*/ @!P0 IMAD.MOV.U32 R14, RZ, RZ, R10 ; /* 0x000000ffff0e8224 */
/* 0x000fc600078e000a */
/*0c70*/ LOP3.LUT R12, R12, 0x800fffff, RZ, 0xc0, !PT ; /* 0x800fffff0c0c7812 */
/* 0x000fe400078ec0ff */
/*0c80*/ IADD3 R10, R33, -0x3ff, RZ ; /* 0xfffffc01210a7810 */
/* 0x000fe40007ffe0ff */
/*0c90*/ LOP3.LUT R15, R12, 0x3ff00000, RZ, 0xfc, !PT ; /* 0x3ff000000c0f7812 */
/* 0x000fc800078efcff */
/*0ca0*/ ISETP.GE.U32.AND P1, PT, R15, 0x3ff6a09f, PT ; /* 0x3ff6a09f0f00780c */
/* 0x000fda0003f26070 */
/*0cb0*/ @P1 IADD3 R13, R15, -0x100000, RZ ; /* 0xfff000000f0d1810 */
/* 0x000fe40007ffe0ff */
/*0cc0*/ @P1 IADD3 R10, R33, -0x3fe, RZ ; /* 0xfffffc02210a1810 */
/* 0x000fc60007ffe0ff */
/*0cd0*/ @P1 IMAD.MOV.U32 R15, RZ, RZ, R13 ; /* 0x000000ffff0f1224 */
/* 0x000fcc00078e000d */
/*0ce0*/ DADD R20, R14, 1 ; /* 0x3ff000000e147429 */
/* 0x000e080000000000 */
/*0cf0*/ DADD R14, R14, -1 ; /* 0xbff000000e0e7429 */
/* 0x000fe40000000000 */
/*0d00*/ MUFU.RCP64H R19, R21 ; /* 0x0000001500137308 */
/* 0x001e240000001800 */
/*0d10*/ DFMA R12, -R20, R18, 1 ; /* 0x3ff00000140c742b */
/* 0x001e0c0000000112 */
/*0d20*/ DFMA R12, R12, R12, R12 ; /* 0x0000000c0c0c722b */
/* 0x001e0c000000000c */
/*0d30*/ DFMA R18, R18, R12, R18 ; /* 0x0000000c1212722b */
/* 0x001e0c0000000012 */
/*0d40*/ DMUL R12, R18, R14 ; /* 0x0000000e120c7228 */
/* 0x001e0c0000000000 */
/*0d50*/ DFMA R12, R18, R14, R12 ; /* 0x0000000e120c722b */
/* 0x001e0c000000000c */
/*0d60*/ DMUL R24, R12, R12 ; /* 0x0000000c0c187228 */
/* 0x001e0c0000000000 */
/*0d70*/ DFMA R16, R24, R16, c[0x2][0x0] ; /* 0x008000001810762b */
/* 0x001e0c0000000010 */
/*0d80*/ DFMA R22, R24, R16, c[0x2][0x8] ; /* 0x008002001816762b */
/* 0x001e080000000010 */
/*0d90*/ DADD R16, R14, -R12 ; /* 0x000000000e107229 */
/* 0x000e48000000080c */
/*0da0*/ DFMA R22, R24, R22, c[0x2][0x10] ; /* 0x008004001816762b */
/* 0x001e080000000016 */
/*0db0*/ DADD R16, R16, R16 ; /* 0x0000000010107229 */
/* 0x002e480000000010 */
/*0dc0*/ DFMA R22, R24, R22, c[0x2][0x18] ; /* 0x008006001816762b */
/* 0x001e080000000016 */
/*0dd0*/ DFMA R16, R14, -R12, R16 ; /* 0x8000000c0e10722b */
/* 0x002e480000000010 */
/*0de0*/ DFMA R22, R24, R22, c[0x2][0x20] ; /* 0x008008001816762b */
/* 0x001e080000000016 */
/*0df0*/ DMUL R16, R18, R16 ; /* 0x0000001012107228 */
/* 0x002fc80000000000 */
/*0e00*/ DFMA R22, R24, R22, c[0x2][0x28] ; /* 0x00800a001816762b */
/* 0x001e080000000016 */
/*0e10*/ DMUL R18, R12, R12 ; /* 0x0000000c0c127228 */
/* 0x000fc80000000000 */
/*0e20*/ DFMA R14, R24, R22, c[0x2][0x30] ; /* 0x00800c00180e762b */
/* 0x001e0c0000000016 */
/*0e30*/ DADD R20, -R14, c[0x2][0x30] ; /* 0x00800c000e147629 */
/* 0x001e0c0000000100 */
/*0e40*/ DFMA R20, R24, R22, R20 ; /* 0x000000161814722b */
/* 0x0011e40000000014 */
/*0e50*/ IADD3 R23, R17, 0x100000, RZ ; /* 0x0010000011177810 */
/* 0x001fe40007ffe0ff */
/*0e60*/ DFMA R24, R12, R12, -R18 ; /* 0x0000000c0c18722b */
/* 0x000e220000000812 */
/*0e70*/ MOV R22, R16 ; /* 0x0000001000167202 */
/* 0x000fcc0000000f00 */
/*0e80*/ DFMA R22, R12, R22, R24 ; /* 0x000000160c16722b */
/* 0x001fc80000000018 */
/*0e90*/ DMUL R24, R12, R18 ; /* 0x000000120c187228 */
/* 0x000e0c0000000000 */
/*0ea0*/ DFMA R26, R12, R18, -R24 ; /* 0x000000120c1a722b */
/* 0x001e0c0000000818 */
/*0eb0*/ DFMA R26, R16, R18, R26 ; /* 0x00000012101a722b */
/* 0x001e08000000001a */
/*0ec0*/ DADD R18, RZ, R20 ; /* 0x00000000ff127229 */
/* 0x000e480000000014 */
/*0ed0*/ DFMA R22, R12, R22, R26 ; /* 0x000000160c16722b */
/* 0x001fc8000000001a */
/*0ee0*/ DADD R18, R18, c[0x2][0x38] ; /* 0x00800e0012127629 */
/* 0x002e0c0000000000 */
/*0ef0*/ DADD R20, R14, R18 ; /* 0x000000000e147229 */
/* 0x001e0c0000000012 */
/*0f00*/ DADD R26, R14, -R20 ; /* 0x000000000e1a7229 */
/* 0x001e0c0000000814 */
/*0f10*/ DADD R26, R18, R26 ; /* 0x00000000121a7229 */
/* 0x001fc8000000001a */
/*0f20*/ DMUL R18, R20, R24 ; /* 0x0000001814127228 */
/* 0x000e0c0000000000 */
/*0f30*/ DFMA R14, R20, R24, -R18 ; /* 0x00000018140e722b */
/* 0x001e0c0000000812 */
/*0f40*/ DFMA R14, R20, R22, R14 ; /* 0x00000016140e722b */
/* 0x001e0c000000000e */
/*0f50*/ DFMA R26, R26, R24, R14 ; /* 0x000000181a1a722b */
/* 0x001e0c000000000e */
/*0f60*/ DADD R20, R18, R26 ; /* 0x0000000012147229 */
/* 0x001e0c000000001a */
/*0f70*/ DADD R14, R12, R20 ; /* 0x000000000c0e7229 */
/* 0x001e080000000014 */
/*0f80*/ DADD R18, R18, -R20 ; /* 0x0000000012127229 */
/* 0x000e480000000814 */
/*0f90*/ DADD R12, R12, -R14 ; /* 0x000000000c0c7229 */
/* 0x001e08000000080e */
/*0fa0*/ DADD R18, R26, R18 ; /* 0x000000001a127229 */
/* 0x002fc80000000012 */
/*0fb0*/ DADD R12, R20, R12 ; /* 0x00000000140c7229 */
/* 0x001e0c000000000c */
/*0fc0*/ DADD R18, R18, R12 ; /* 0x0000000012127229 */
/* 0x001064000000000c */
/*0fd0*/ LOP3.LUT R12, R10, 0x80000000, RZ, 0x3c, !PT ; /* 0x800000000a0c7812 */
/* 0x001fe200078e3cff */
/*0fe0*/ IMAD.MOV.U32 R13, RZ, RZ, 0x43300000 ; /* 0x43300000ff0d7424 */
/* 0x000fc600078e00ff */
/*0ff0*/ DADD R18, R16, R18 ; /* 0x0000000010127229 */
/* 0x002e080000000012 */
/*1000*/ DADD R12, R12, c[0x2][0x40] ; /* 0x008010000c0c7629 */
/* 0x000fc80000000000 */
/*1010*/ DADD R16, R14, R18 ; /* 0x000000000e107229 */
/* 0x001e0c0000000012 */
/*1020*/ DFMA R10, R12, c[0x2][0x48], R16 ; /* 0x008012000c0a7a2b */
/* 0x001e080000000010 */
/*1030*/ DADD R20, R14, -R16 ; /* 0x000000000e147229 */
/* 0x000e480000000810 */
/*1040*/ DFMA R14, -R12, c[0x2][0x48], R10 ; /* 0x008012000c0e7a2b */
/* 0x001e08000000010a */
/*1050*/ DADD R20, R18, R20 ; /* 0x0000000012147229 */
/* 0x0023e40000000014 */
/*1060*/ IMAD.MOV.U32 R18, RZ, RZ, 0x69ce2bdf ; /* 0x69ce2bdfff127424 */
/* 0x002fe400078e00ff */
/*1070*/ DADD R14, -R16, R14 ; /* 0x00000000100e7229 */
/* 0x001e22000000010e */
/*1080*/ IMAD.MOV.U32 R19, RZ, RZ, 0x3e5ade15 ; /* 0x3e5ade15ff137424 */
/* 0x000fca00078e00ff */
/*1090*/ DADD R14, R20, -R14 ; /* 0x00000000140e7229 */
/* 0x001e0c000000080e */
/*10a0*/ DFMA R14, R12, c[0x2][0x50], R14 ; /* 0x008014000c0e7a2b */
/* 0x001e0c000000000e */
/*10b0*/ DADD R12, R10, R14 ; /* 0x000000000a0c7229 */
/* 0x001e0c000000000e */
/*10c0*/ DADD R10, R10, -R12 ; /* 0x000000000a0a7229 */
/* 0x001e08000000080c */
/*10d0*/ DMUL R22, R12, 2 ; /* 0x400000000c167828 */
/* 0x000e480000000000 */
/*10e0*/ DADD R10, R14, R10 ; /* 0x000000000e0a7229 */
/* 0x001fc8000000000a */
/*10f0*/ DFMA R20, R12, 2, -R22 ; /* 0x400000000c14782b */
/* 0x0020640000000816 */
/*1100*/ IMAD.MOV.U32 R12, RZ, RZ, 0x652b82fe ; /* 0x652b82feff0c7424 */
/* 0x001fe400078e00ff */
/*1110*/ IMAD.MOV.U32 R13, RZ, RZ, 0x3ff71547 ; /* 0x3ff71547ff0d7424 */
/* 0x000fe400078e00ff */
/*1120*/ DFMA R20, R10, 2, R20 ; /* 0x400000000a14782b */
/* 0x002e0c0000000014 */
/*1130*/ DADD R10, R22, R20 ; /* 0x00000000160a7229 */
/* 0x001e0c0000000014 */
/*1140*/ DFMA R12, R10, R12, 6.75539944105574400000e+15 ; /* 0x433800000a0c742b */
/* 0x001e08000000000c */
/*1150*/ FSETP.GEU.AND P0, PT, |R11|, 4.1917929649353027344, PT ; /* 0x4086232b0b00780b */
/* 0x000fe40003f0e200 */
/*1160*/ DADD R14, R12, -6.75539944105574400000e+15 ; /* 0xc33800000c0e7429 */
/* 0x001e0c0000000000 */
/*1170*/ DFMA R16, R14, c[0x2][0x58], R10 ; /* 0x008016000e107a2b */
/* 0x001e0c000000000a */
/*1180*/ DFMA R14, R14, c[0x2][0x60], R16 ; /* 0x008018000e0e7a2b */
/* 0x001e0c0000000010 */
/*1190*/ DFMA R16, R14, R18, c[0x2][0x68] ; /* 0x00801a000e10762b */
/* 0x001e0c0000000012 */
/*11a0*/ DFMA R16, R14, R16, c[0x2][0x70] ; /* 0x00801c000e10762b */
/* 0x001e0c0000000010 */
/*11b0*/ DFMA R16, R14, R16, c[0x2][0x78] ; /* 0x00801e000e10762b */
/* 0x001e0c0000000010 */
/*11c0*/ DFMA R16, R14, R16, c[0x2][0x80] ; /* 0x008020000e10762b */
/* 0x001e0c0000000010 */
/*11d0*/ DFMA R16, R14, R16, c[0x2][0x88] ; /* 0x008022000e10762b */
/* 0x001e0c0000000010 */
/*11e0*/ DFMA R16, R14, R16, c[0x2][0x90] ; /* 0x008024000e10762b */
/* 0x001e0c0000000010 */
/*11f0*/ DFMA R16, R14, R16, c[0x2][0x98] ; /* 0x008026000e10762b */
/* 0x001e0c0000000010 */
/*1200*/ DFMA R16, R14, R16, c[0x2][0xa0] ; /* 0x008028000e10762b */
/* 0x001e0c0000000010 */
/*1210*/ DFMA R16, R14, R16, c[0x2][0xa8] ; /* 0x00802a000e10762b */
/* 0x001e0c0000000010 */
/*1220*/ DFMA R16, R14, R16, 1 ; /* 0x3ff000000e10742b */
/* 0x001e0c0000000010 */
/*1230*/ DFMA R14, R14, R16, 1 ; /* 0x3ff000000e0e742b */
/* 0x001e140000000010 */
/*1240*/ IMAD R17, R12, 0x100000, R15 ; /* 0x001000000c117824 */
/* 0x001fe400078e020f */
/*1250*/ IMAD.MOV.U32 R16, RZ, RZ, R14 ; /* 0x000000ffff107224 */
/* 0x000fe200078e000e */
/*1260*/ @!P0 BRA 0x1330 ; /* 0x000000c000008947 */
/* 0x000fea0003800000 */
/*1270*/ FSETP.GEU.AND P1, PT, |R11|, 4.2275390625, PT ; /* 0x408748000b00780b */
/* 0x000fe20003f2e200 */
/*1280*/ DADD R16, R10, +INF ; /* 0x7ff000000a107429 */
/* 0x000fc80000000000 */
/*1290*/ DSETP.GEU.AND P0, PT, R10, RZ, PT ; /* 0x000000ff0a00722a */
/* 0x000e0c0003f0e000 */
/*12a0*/ FSEL R16, R16, RZ, P0 ; /* 0x000000ff10107208 */
/* 0x001fe40000000000 */
/*12b0*/ @!P1 LEA.HI R13, R12, R12, RZ, 0x1 ; /* 0x0000000c0c0d9211 */
/* 0x000fe400078f08ff */
/*12c0*/ FSEL R17, R17, RZ, P0 ; /* 0x000000ff11117208 */
/* 0x000fe40000000000 */
/*12d0*/ @!P1 SHF.R.S32.HI R13, RZ, 0x1, R13 ; /* 0x00000001ff0d9819 */
/* 0x000fca000001140d */
/*12e0*/ @!P1 IMAD.IADD R12, R12, 0x1, -R13 ; /* 0x000000010c0c9824 */
/* 0x000fe400078e0a0d */
/*12f0*/ @!P1 IMAD R15, R13, 0x100000, R15 ; /* 0x001000000d0f9824 */
/* 0x000fc600078e020f */
/*1300*/ @!P1 LEA R13, R12, 0x3ff00000, 0x14 ; /* 0x3ff000000c0d9811 */
/* 0x000fe200078ea0ff */
/*1310*/ @!P1 IMAD.MOV.U32 R12, RZ, RZ, RZ ; /* 0x000000ffff0c9224 */
/* 0x000fcc00078e00ff */
/*1320*/ @!P1 DMUL R16, R14, R12 ; /* 0x0000000c0e109228 */
/* 0x0000540000000000 */
/*1330*/ LOP3.LUT R12, R17, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff110c7812 */
/* 0x003fe200078ec0ff */
/*1340*/ DADD R10, R22, -R10 ; /* 0x00000000160a7229 */
/* 0x000e22000000080a */
/*1350*/ IMAD.MOV.U32 R33, RZ, RZ, 0x0 ; /* 0x00000000ff217424 */
/* 0x000fe400078e00ff */
/*1360*/ ISETP.NE.AND P0, PT, R12, 0x7ff00000, PT ; /* 0x7ff000000c00780c */
/* 0x000fc60003f05270 */
/*1370*/ DADD R10, R20, R10 ; /* 0x00000000140a7229 */
/* 0x001e22000000000a */
/*1380*/ ISETP.EQ.AND P0, PT, R16, RZ, !P0 ; /* 0x000000ff1000720c */
/* 0x000fda0004702270 */
/*1390*/ @!P0 DFMA R16, R10, R16, R16 ; /* 0x000000100a10822b */
/* 0x001e140000000010 */
/*13a0*/ IMAD.MOV.U32 R10, RZ, RZ, R16 ; /* 0x000000ffff0a7224 */
/* 0x001fe400078e0010 */
/*13b0*/ IMAD.MOV.U32 R11, RZ, RZ, R17 ; /* 0x000000ffff0b7224 */
/* 0x000fe200078e0011 */
/*13c0*/ RET.REL.NODEC R32 0x0 ; /* 0xffffec3020007950 */
/* 0x000fec0003c3ffff */
/*13d0*/ BRA 0x13d0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*13e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*13f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1400*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1410*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1420*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1430*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1440*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1450*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1460*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1470*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <iostream>
#include <cstdlib>
#include <cfloat>
#include <math.h>
#include <sys/time.h>
#define THREADS_PER_BLOCK 32
__global__ void voronoi_d (int *imageArray, int *points, int imageSize, int numPoints) {
// use x to access each cell and compare it to each point and assign the cell's value to match the closest point
int x = blockIdx.x * blockDim.x + threadIdx.x;
double minDistance = DBL_MAX;
int minPoint = -1;
for (int k=0; k<numPoints; k++) {
double distance = sqrt(pow((double) (x % imageSize - points[k + numPoints]), 2.0) + pow((double) (x / imageSize - points[k]), 2.0));
if (distance < minDistance) {
minDistance = distance;
minPoint = k;
}
}
imageArray[x] = minPoint;
}
extern void gpuVoronoi(int *imageArray_h, int *points_h, int imageSize, int numPoints)
{
// allocate space for the image and point coordinates on the device and copy the coordinates over
int *imageArray;
int *points;
cudaMalloc ((void**) &imageArray, sizeof(int) * imageSize * imageSize);
cudaMalloc ((void**) &points, sizeof(int) * numPoints * 2);
cudaMemcpy (points, points_h, sizeof(int) * numPoints * 2, cudaMemcpyHostToDevice);
// start calculation timing
struct timeval start, end;
gettimeofday(&start, NULL);
// calculate and then synchronize to ensure accurate timing
voronoi_d <<< ceil((float) imageSize*imageSize/THREADS_PER_BLOCK), THREADS_PER_BLOCK >>> (imageArray, points, imageSize, numPoints);
cudaDeviceSynchronize();
// end timing and print processing time
gettimeofday(&end, NULL);
long seconds = (end.tv_sec - start.tv_sec);
long micros = ((seconds * 1000000) + end.tv_usec) - (start.tv_usec);
printf("Processing time elpased is %zu seconds or %zu micros\n", seconds, micros);
// print CUDA errors
cudaError_t err = cudaGetLastError();
printf("CUDA error: %s\n", cudaGetErrorString(err));
// copy results to host and free device memory
cudaMemcpy (imageArray_h, imageArray, sizeof(int) * imageSize * imageSize, cudaMemcpyDeviceToHost);
cudaFree (imageArray);
cudaFree (points);
} | .file "tmpxft_000b38cb_00000000-6_vgpu.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z32__device_stub__Z9voronoi_dPiS_iiPiS_ii
.type _Z32__device_stub__Z9voronoi_dPiS_iiPiS_ii, @function
_Z32__device_stub__Z9voronoi_dPiS_iiPiS_ii:
.LFB3694:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9voronoi_dPiS_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3694:
.size _Z32__device_stub__Z9voronoi_dPiS_iiPiS_ii, .-_Z32__device_stub__Z9voronoi_dPiS_iiPiS_ii
.globl _Z9voronoi_dPiS_ii
.type _Z9voronoi_dPiS_ii, @function
_Z9voronoi_dPiS_ii:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z9voronoi_dPiS_iiPiS_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _Z9voronoi_dPiS_ii, .-_Z9voronoi_dPiS_ii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC4:
.string "Processing time elpased is %zu seconds or %zu micros\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC5:
.string "CUDA error: %s\n"
.text
.globl _Z10gpuVoronoiPiS_ii
.type _Z10gpuVoronoiPiS_ii, @function
_Z10gpuVoronoiPiS_ii:
.LFB3669:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $88, %rsp
.cfi_def_cfa_offset 144
movq %rdi, %rbp
movq %rsi, %r15
movl %edx, %r12d
movl %ecx, %r14d
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movslq %edx, %rbx
imulq %rbx, %rbx
salq $2, %rbx
movq %rsp, %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movslq %r14d, %r13
salq $3, %r13
leaq 8(%rsp), %rdi
movq %r13, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %r13, %rdx
movq %r15, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
leaq 32(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
movl $32, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
pxor %xmm0, %xmm0
cvtsi2ssl %r12d, %xmm0
mulss %xmm0, %xmm0
mulss .LC0(%rip), %xmm0
movaps %xmm0, %xmm3
movss .LC6(%rip), %xmm2
movaps %xmm0, %xmm1
andps %xmm2, %xmm1
movss .LC1(%rip), %xmm4
ucomiss %xmm1, %xmm4
jbe .L12
cvttss2sil %xmm0, %eax
pxor %xmm1, %xmm1
cvtsi2ssl %eax, %xmm1
cmpnless %xmm1, %xmm3
movss .LC3(%rip), %xmm4
andps %xmm4, %xmm3
addss %xmm1, %xmm3
andnps %xmm0, %xmm2
orps %xmm2, %xmm3
.L12:
cvttss2siq %xmm3, %rax
movl %eax, 20(%rsp)
movl $1, 24(%rsp)
movl 56(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 48(%rsp), %rdx
movq 20(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L16
.L13:
call cudaDeviceSynchronize@PLT
leaq 48(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
movq 48(%rsp), %rdx
subq 32(%rsp), %rdx
imulq $1000000, %rdx, %rcx
addq 56(%rsp), %rcx
subq 40(%rsp), %rcx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
call cudaGetLastError@PLT
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $2, %ecx
movq %rbx, %rdx
movq (%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L17
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L16:
.cfi_restore_state
movl %r14d, %ecx
movl %r12d, %edx
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z32__device_stub__Z9voronoi_dPiS_iiPiS_ii
jmp .L13
.L17:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size _Z10gpuVoronoiPiS_ii, .-_Z10gpuVoronoiPiS_ii
.section .rodata.str1.1
.LC7:
.string "_Z9voronoi_dPiS_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _Z9voronoi_dPiS_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC0:
.long 1023410176
.align 4
.LC1:
.long 1258291200
.align 4
.LC3:
.long 1065353216
.align 4
.LC6:
.long 2147483647
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <iostream>
#include <cstdlib>
#include <cfloat>
#include <math.h>
#include <sys/time.h>
#define THREADS_PER_BLOCK 32
__global__ void voronoi_d (int *imageArray, int *points, int imageSize, int numPoints) {
// use x to access each cell and compare it to each point and assign the cell's value to match the closest point
int x = blockIdx.x * blockDim.x + threadIdx.x;
double minDistance = DBL_MAX;
int minPoint = -1;
for (int k=0; k<numPoints; k++) {
double distance = sqrt(pow((double) (x % imageSize - points[k + numPoints]), 2.0) + pow((double) (x / imageSize - points[k]), 2.0));
if (distance < minDistance) {
minDistance = distance;
minPoint = k;
}
}
imageArray[x] = minPoint;
}
extern void gpuVoronoi(int *imageArray_h, int *points_h, int imageSize, int numPoints)
{
// allocate space for the image and point coordinates on the device and copy the coordinates over
int *imageArray;
int *points;
cudaMalloc ((void**) &imageArray, sizeof(int) * imageSize * imageSize);
cudaMalloc ((void**) &points, sizeof(int) * numPoints * 2);
cudaMemcpy (points, points_h, sizeof(int) * numPoints * 2, cudaMemcpyHostToDevice);
// start calculation timing
struct timeval start, end;
gettimeofday(&start, NULL);
// calculate and then synchronize to ensure accurate timing
voronoi_d <<< ceil((float) imageSize*imageSize/THREADS_PER_BLOCK), THREADS_PER_BLOCK >>> (imageArray, points, imageSize, numPoints);
cudaDeviceSynchronize();
// end timing and print processing time
gettimeofday(&end, NULL);
long seconds = (end.tv_sec - start.tv_sec);
long micros = ((seconds * 1000000) + end.tv_usec) - (start.tv_usec);
printf("Processing time elpased is %zu seconds or %zu micros\n", seconds, micros);
// print CUDA errors
cudaError_t err = cudaGetLastError();
printf("CUDA error: %s\n", cudaGetErrorString(err));
// copy results to host and free device memory
cudaMemcpy (imageArray_h, imageArray, sizeof(int) * imageSize * imageSize, cudaMemcpyDeviceToHost);
cudaFree (imageArray);
cudaFree (points);
} | #include <hip/hip_runtime.h>
#include <iostream>
#include <cstdlib>
#include <cfloat>
#include <math.h>
#include <sys/time.h>
#define THREADS_PER_BLOCK 32
__global__ void voronoi_d (int *imageArray, int *points, int imageSize, int numPoints) {
// use x to access each cell and compare it to each point and assign the cell's value to match the closest point
int x = blockIdx.x * blockDim.x + threadIdx.x;
double minDistance = DBL_MAX;
int minPoint = -1;
for (int k=0; k<numPoints; k++) {
double distance = sqrt(pow((double) (x % imageSize - points[k + numPoints]), 2.0) + pow((double) (x / imageSize - points[k]), 2.0));
if (distance < minDistance) {
minDistance = distance;
minPoint = k;
}
}
imageArray[x] = minPoint;
}
extern void gpuVoronoi(int *imageArray_h, int *points_h, int imageSize, int numPoints)
{
// allocate space for the image and point coordinates on the device and copy the coordinates over
int *imageArray;
int *points;
hipMalloc ((void**) &imageArray, sizeof(int) * imageSize * imageSize);
hipMalloc ((void**) &points, sizeof(int) * numPoints * 2);
hipMemcpy (points, points_h, sizeof(int) * numPoints * 2, hipMemcpyHostToDevice);
// start calculation timing
struct timeval start, end;
gettimeofday(&start, NULL);
// calculate and then synchronize to ensure accurate timing
voronoi_d <<< ceil((float) imageSize*imageSize/THREADS_PER_BLOCK), THREADS_PER_BLOCK >>> (imageArray, points, imageSize, numPoints);
hipDeviceSynchronize();
// end timing and print processing time
gettimeofday(&end, NULL);
long seconds = (end.tv_sec - start.tv_sec);
long micros = ((seconds * 1000000) + end.tv_usec) - (start.tv_usec);
printf("Processing time elpased is %zu seconds or %zu micros\n", seconds, micros);
// print CUDA errors
hipError_t err = hipGetLastError();
printf("CUDA error: %s\n", hipGetErrorString(err));
// copy results to host and free device memory
hipMemcpy (imageArray_h, imageArray, sizeof(int) * imageSize * imageSize, hipMemcpyDeviceToHost);
hipFree (imageArray);
hipFree (points);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <iostream>
#include <cstdlib>
#include <cfloat>
#include <math.h>
#include <sys/time.h>
#define THREADS_PER_BLOCK 32
__global__ void voronoi_d (int *imageArray, int *points, int imageSize, int numPoints) {
// use x to access each cell and compare it to each point and assign the cell's value to match the closest point
int x = blockIdx.x * blockDim.x + threadIdx.x;
double minDistance = DBL_MAX;
int minPoint = -1;
for (int k=0; k<numPoints; k++) {
double distance = sqrt(pow((double) (x % imageSize - points[k + numPoints]), 2.0) + pow((double) (x / imageSize - points[k]), 2.0));
if (distance < minDistance) {
minDistance = distance;
minPoint = k;
}
}
imageArray[x] = minPoint;
}
extern void gpuVoronoi(int *imageArray_h, int *points_h, int imageSize, int numPoints)
{
// allocate space for the image and point coordinates on the device and copy the coordinates over
int *imageArray;
int *points;
hipMalloc ((void**) &imageArray, sizeof(int) * imageSize * imageSize);
hipMalloc ((void**) &points, sizeof(int) * numPoints * 2);
hipMemcpy (points, points_h, sizeof(int) * numPoints * 2, hipMemcpyHostToDevice);
// start calculation timing
struct timeval start, end;
gettimeofday(&start, NULL);
// calculate and then synchronize to ensure accurate timing
voronoi_d <<< ceil((float) imageSize*imageSize/THREADS_PER_BLOCK), THREADS_PER_BLOCK >>> (imageArray, points, imageSize, numPoints);
hipDeviceSynchronize();
// end timing and print processing time
gettimeofday(&end, NULL);
long seconds = (end.tv_sec - start.tv_sec);
long micros = ((seconds * 1000000) + end.tv_usec) - (start.tv_usec);
printf("Processing time elpased is %zu seconds or %zu micros\n", seconds, micros);
// print CUDA errors
hipError_t err = hipGetLastError();
printf("CUDA error: %s\n", hipGetErrorString(err));
// copy results to host and free device memory
hipMemcpy (imageArray_h, imageArray, sizeof(int) * imageSize * imageSize, hipMemcpyDeviceToHost);
hipFree (imageArray);
hipFree (points);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9voronoi_dPiS_ii
.globl _Z9voronoi_dPiS_ii
.p2align 8
.type _Z9voronoi_dPiS_ii,@function
_Z9voronoi_dPiS_ii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s10, s[0:1], 0x14
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_cmp_lt_i32 s10, 1
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_cbranch_scc1 .LBB0_3
s_clause 0x1
s_load_b32 s4, s[0:1], 0x10
s_load_b64 s[12:13], s[0:1], 0x8
s_delay_alu instid0(VALU_DEP_1)
v_ashrrev_i32_e32 v4, 31, v1
s_mov_b32 s3, 0x7fefffff
s_mov_b32 s11, 0
s_mov_b32 s15, 0x3fe55555
s_mov_b32 s14, 0x55555555
s_mov_b32 s17, 0x3fba6564
s_mov_b32 s16, 0x968915a9
s_mov_b32 s19, 0x3fbdee67
s_mov_b32 s18, 0x4222de17
s_mov_b32 s21, 0x3fbe25e4
s_mov_b32 s20, 0x3abe935a
s_mov_b32 s23, 0x3fc110ef
s_mov_b32 s22, 0x47e6c9c2
s_mov_b32 s25, 0x3fc3b13b
s_mov_b32 s24, 0xcfa74449
s_mov_b32 s27, 0x3fc745d1
s_mov_b32 s26, 0x71bf3c30
s_mov_b32 s29, 0x3fcc71c7
s_waitcnt lgkmcnt(0)
s_ashr_i32 s5, s4, 31
s_mov_b32 s28, 0x1c7792ce
s_add_i32 s2, s4, s5
s_mov_b32 s31, 0x3fd24924
s_xor_b32 s6, s2, s5
s_mov_b32 s30, 0x924920da
v_cvt_f32_u32_e32 v0, s6
s_sub_i32 s2, 0, s6
s_mov_b32 s35, 0x3fd99999
s_mov_b32 s34, 0x9999999c
s_mov_b32 s37, 0x3fe62e42
v_rcp_iflag_f32_e32 v0, v0
s_mov_b32 s36, 0xfefa39ef
s_mov_b32 s39, 0x3c7abc9e
s_mov_b32 s38, 0x3b39803f
s_mov_b32 s9, 0xbfe55555
s_mov_b32 s41, 0x3c8543b0
s_mov_b32 s40, 0xd5df274d
s_mov_b32 s43, 0x3ff71547
s_mov_b32 s42, 0x652b82fe
s_mov_b32 s45, 0xbfe62e42
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v0, 0x4f7ffffe, v0
s_mov_b32 s47, 0xbc7abc9e
s_mov_b32 s49, 0x3e928af3
s_mov_b32 s48, 0xfca7ab0c
s_mov_b32 s51, 0x3e5ade15
v_cvt_u32_f32_e32 v3, v0
s_mov_b32 s50, 0x6a5dcb37
s_mov_b32 s53, 0x3ec71dee
s_mov_b32 s52, 0x623fde64
s_mov_b32 s55, 0x3efa0199
v_mul_lo_u32 v2, s2, v3
s_mov_b32 s2, -1
v_add_nc_u32_e32 v6, v1, v4
s_mov_b32 s54, 0x7c89e6b0
s_mov_b32 s57, 0x3f2a01a0
s_mov_b32 s56, 0x14761f6e
s_mov_b32 s59, 0x3f56c16c
v_xor_b32_e32 v6, v6, v4
v_mul_hi_u32 v5, v3, v2
v_xor_b32_e32 v4, s5, v4
s_mov_b32 s58, 0x1852b7b0
s_mov_b32 s61, 0x3f811111
s_mov_b32 s60, 0x11122322
s_mov_b32 s63, 0x3fa55555
s_mov_b32 s62, 0x555502a1
s_lshl_b64 s[64:65], s[10:11], 2
v_add_nc_u32_e32 v3, v3, v5
s_mov_b32 s67, 0x3fc55555
s_mov_b32 s66, 0x55555511
s_mov_b32 s69, 0x3fe00000
s_mov_b32 s68, 11
v_mul_hi_u32 v3, v6, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v5, v3, s6
v_sub_nc_u32_e32 v5, v6, v5
v_add_nc_u32_e32 v6, 1, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_subrev_nc_u32_e32 v7, s6, v5
v_cmp_le_u32_e32 vcc_lo, s6, v5
v_mov_b32_e32 v0, -1
v_dual_mov_b32 v2, 0 :: v_dual_cndmask_b32 v5, v5, v7
v_cndmask_b32_e32 v3, v3, v6, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_le_u32_e32 vcc_lo, s6, v5
v_add_nc_u32_e32 v6, 1, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v3, v3, v6, vcc_lo
v_xor_b32_e32 v3, v3, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v10, v3, v4
v_dual_mov_b32 v5, s3 :: v_dual_mov_b32 v4, s2
v_mul_lo_u32 v3, v10, s4
s_delay_alu instid0(VALU_DEP_1)
v_sub_nc_u32_e32 v11, v1, v3
.LBB0_2:
s_add_u32 s2, s12, s64
s_addc_u32 s3, s13, s65
s_mov_b32 s8, s14
s_clause 0x1
s_load_b32 s6, s[2:3], 0x0
s_load_b32 s33, s[12:13], 0x0
s_mov_b32 s44, s36
s_mov_b32 s46, s38
s_waitcnt lgkmcnt(0)
v_subrev_nc_u32_e32 v13, s6, v11
v_subrev_nc_u32_e32 v12, s33, v10
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cvt_f64_i32_e32 v[8:9], v13
v_cvt_f64_i32_e32 v[6:7], v12
v_cmp_eq_u32_e32 vcc_lo, 1, v13
v_cndmask_b32_e64 v3, 2.0, 0x3ff00000, vcc_lo
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_frexp_mant_f64_e64 v[14:15], |v[8:9]|
v_frexp_mant_f64_e64 v[16:17], |v[6:7]|
v_frexp_exp_i32_f64_e32 v8, v[8:9]
v_frexp_exp_i32_f64_e32 v6, v[6:7]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_cmp_gt_f64_e32 vcc_lo, s[14:15], v[14:15]
v_cmp_gt_f64_e64 s2, s[14:15], v[16:17]
v_cndmask_b32_e64 v18, 0, 1, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
v_cndmask_b32_e64 v19, 0, 1, s2
v_subrev_co_ci_u32_e32 v8, vcc_lo, 0, v8, vcc_lo
v_subrev_co_ci_u32_e64 v6, vcc_lo, 0, v6, s2
v_ldexp_f64 v[14:15], v[14:15], v18
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_ldexp_f64 v[16:17], v[16:17], v19
v_cvt_f64_i32_e32 v[20:21], v8
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_cvt_f64_i32_e32 v[24:25], v6
v_add_f64 v[18:19], v[14:15], 1.0
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_f64 v[22:23], v[16:17], 1.0
v_mul_f64 v[34:35], v[20:21], s[36:37]
v_add_f64 v[26:27], v[14:15], -1.0
v_mul_f64 v[38:39], v[24:25], s[36:37]
v_add_f64 v[28:29], v[16:17], -1.0
v_rcp_f64_e32 v[32:33], v[18:19]
v_add_f64 v[30:31], v[18:19], -1.0
v_add_f64 v[36:37], v[22:23], -1.0
v_rcp_f64_e32 v[40:41], v[22:23]
s_delay_alu instid0(VALU_DEP_2)
v_add_f64 v[14:15], v[14:15], -v[30:31]
v_fma_f64 v[30:31], v[20:21], s[36:37], -v[34:35]
s_waitcnt_depctr 0xfff
v_fma_f64 v[42:43], -v[18:19], v[32:33], 1.0
v_add_f64 v[16:17], v[16:17], -v[36:37]
v_fma_f64 v[36:37], v[24:25], s[36:37], -v[38:39]
v_fma_f64 v[44:45], -v[22:23], v[40:41], 1.0
v_fma_f64 v[20:21], v[20:21], s[38:39], v[30:31]
v_fma_f64 v[30:31], v[42:43], v[32:33], v[32:33]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_fma_f64 v[24:25], v[24:25], s[38:39], v[36:37]
v_fma_f64 v[32:33], v[44:45], v[40:41], v[40:41]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_f64 v[36:37], v[34:35], v[20:21]
v_fma_f64 v[42:43], -v[18:19], v[30:31], 1.0
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_f64 v[40:41], v[38:39], v[24:25]
v_fma_f64 v[44:45], -v[22:23], v[32:33], 1.0
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_f64 v[34:35], v[36:37], -v[34:35]
v_fma_f64 v[30:31], v[42:43], v[30:31], v[30:31]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_f64 v[38:39], v[40:41], -v[38:39]
v_fma_f64 v[32:33], v[44:45], v[32:33], v[32:33]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_f64 v[20:21], v[20:21], -v[34:35]
v_mul_f64 v[34:35], v[26:27], v[30:31]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_f64 v[24:25], v[24:25], -v[38:39]
v_mul_f64 v[42:43], v[28:29], v[32:33]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_f64 v[44:45], v[18:19], v[34:35]
v_mul_f64 v[46:47], v[22:23], v[42:43]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f64 v[18:19], v[34:35], v[18:19], -v[44:45]
v_fma_f64 v[22:23], v[42:43], v[22:23], -v[46:47]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f64 v[14:15], v[34:35], v[14:15], v[18:19]
v_fma_f64 v[16:17], v[42:43], v[16:17], v[22:23]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[18:19], v[44:45], v[14:15]
v_add_f64 v[22:23], v[46:47], v[16:17]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_f64 v[48:49], v[26:27], -v[18:19]
v_add_f64 v[44:45], v[18:19], -v[44:45]
v_add_f64 v[50:51], v[28:29], -v[22:23]
v_add_f64 v[46:47], v[22:23], -v[46:47]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_f64 v[26:27], v[26:27], -v[48:49]
v_add_f64 v[14:15], v[44:45], -v[14:15]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_f64 v[28:29], v[28:29], -v[50:51]
v_add_f64 v[16:17], v[46:47], -v[16:17]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f64 v[18:19], v[26:27], -v[18:19]
v_add_f64 v[22:23], v[28:29], -v[22:23]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[14:15], v[14:15], v[18:19]
v_add_f64 v[16:17], v[16:17], v[22:23]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[14:15], v[48:49], v[14:15]
v_add_f64 v[16:17], v[50:51], v[16:17]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_f64 v[14:15], v[30:31], v[14:15]
v_mul_f64 v[16:17], v[32:33], v[16:17]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[18:19], v[34:35], v[14:15]
v_add_f64 v[22:23], v[42:43], v[16:17]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
v_add_f64 v[26:27], v[18:19], -v[34:35]
v_mul_f64 v[28:29], v[18:19], v[18:19]
v_ldexp_f64 v[30:31], v[18:19], 1
v_add_f64 v[32:33], v[22:23], -v[42:43]
v_mul_f64 v[34:35], v[22:23], v[22:23]
v_ldexp_f64 v[42:43], v[22:23], 1
v_add_f64 v[14:15], v[14:15], -v[26:27]
v_fma_f64 v[26:27], v[18:19], v[18:19], -v[28:29]
v_add_f64 v[16:17], v[16:17], -v[32:33]
v_fma_f64 v[32:33], v[22:23], v[22:23], -v[34:35]
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_add_f64 v[44:45], v[14:15], v[14:15]
v_ldexp_f64 v[46:47], v[14:15], 1
v_add_f64 v[48:49], v[16:17], v[16:17]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f64 v[26:27], v[18:19], v[44:45], v[26:27]
v_fma_f64 v[32:33], v[22:23], v[48:49], v[32:33]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[44:45], v[28:29], v[26:27]
v_fma_f64 v[50:51], v[44:45], s[18:19], s[16:17]
v_add_f64 v[28:29], v[44:45], -v[28:29]
v_mul_f64 v[52:53], v[18:19], v[44:45]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fma_f64 v[50:51], v[44:45], v[50:51], s[20:21]
v_add_f64 v[26:27], v[26:27], -v[28:29]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fma_f64 v[28:29], v[44:45], v[18:19], -v[52:53]
v_fma_f64 v[50:51], v[44:45], v[50:51], s[22:23]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f64 v[14:15], v[44:45], v[14:15], v[28:29]
v_fma_f64 v[28:29], v[44:45], v[50:51], s[24:25]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f64 v[14:15], v[26:27], v[18:19], v[14:15]
v_fma_f64 v[28:29], v[44:45], v[28:29], s[26:27]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[28:29], v[44:45], v[28:29], s[28:29]
v_fma_f64 v[28:29], v[44:45], v[28:29], s[30:31]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[28:29], v[44:45], v[28:29], s[34:35]
v_mul_f64 v[50:51], v[44:45], v[28:29]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[44:45], v[44:45], v[28:29], -v[50:51]
v_fma_f64 v[28:29], v[26:27], v[28:29], v[44:45]
v_add_f64 v[26:27], v[52:53], v[14:15]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[44:45], v[50:51], v[28:29]
v_add_f64 v[52:53], v[26:27], -v[52:53]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_f64 v[54:55], v[44:45], s[14:15]
v_add_f64 v[50:51], v[44:45], -v[50:51]
v_add_f64 v[14:15], v[14:15], -v[52:53]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f64 v[56:57], v[54:55], s[8:9]
v_add_f64 v[28:29], v[28:29], -v[50:51]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[44:45], v[44:45], -v[56:57]
v_add_f64 v[28:29], v[28:29], s[40:41]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_f64 v[18:19], v[28:29], v[44:45]
v_ldexp_f64 v[44:45], v[16:17], 1
v_add_f64 v[28:29], v[54:55], v[18:19]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_f64 v[50:51], v[54:55], -v[28:29]
v_mul_f64 v[54:55], v[26:27], v[28:29]
v_add_f64 v[18:19], v[18:19], v[50:51]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[50:51], v[26:27], v[28:29], -v[54:55]
v_fma_f64 v[18:19], v[26:27], v[18:19], v[50:51]
v_add_f64 v[26:27], v[34:35], v[32:33]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f64 v[14:15], v[14:15], v[28:29], v[18:19]
v_add_f64 v[18:19], v[26:27], -v[34:35]
v_fma_f64 v[28:29], v[26:27], s[18:19], s[16:17]
v_mul_f64 v[48:49], v[22:23], v[26:27]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_f64 v[34:35], v[54:55], v[14:15]
v_add_f64 v[18:19], v[32:33], -v[18:19]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_fma_f64 v[28:29], v[26:27], v[28:29], s[20:21]
v_fma_f64 v[52:53], v[26:27], v[22:23], -v[48:49]
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_add_f64 v[32:33], v[30:31], v[34:35]
v_add_f64 v[50:51], v[34:35], -v[54:55]
v_fma_f64 v[28:29], v[26:27], v[28:29], s[22:23]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_fma_f64 v[16:17], v[26:27], v[16:17], v[52:53]
v_add_f64 v[30:31], v[32:33], -v[30:31]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_f64 v[14:15], v[14:15], -v[50:51]
v_fma_f64 v[28:29], v[26:27], v[28:29], s[24:25]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_fma_f64 v[16:17], v[18:19], v[22:23], v[16:17]
v_add_f64 v[30:31], v[34:35], -v[30:31]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_f64 v[14:15], v[46:47], v[14:15]
v_fma_f64 v[22:23], v[26:27], v[28:29], s[26:27]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f64 v[28:29], v[48:49], v[16:17]
v_add_f64 v[14:15], v[14:15], v[30:31]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fma_f64 v[22:23], v[26:27], v[22:23], s[28:29]
v_add_f64 v[34:35], v[28:29], -v[48:49]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f64 v[30:31], v[32:33], v[14:15]
v_fma_f64 v[22:23], v[26:27], v[22:23], s[30:31]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f64 v[16:17], v[16:17], -v[34:35]
v_add_f64 v[46:47], v[36:37], v[30:31]
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_fma_f64 v[22:23], v[26:27], v[22:23], s[34:35]
v_add_f64 v[32:33], v[30:31], -v[32:33]
v_add_f64 v[34:35], v[46:47], -v[36:37]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_mul_f64 v[50:51], v[26:27], v[22:23]
v_add_f64 v[14:15], v[14:15], -v[32:33]
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_add_f64 v[48:49], v[46:47], -v[34:35]
v_add_f64 v[30:31], v[30:31], -v[34:35]
v_fma_f64 v[26:27], v[26:27], v[22:23], -v[50:51]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_f64 v[34:35], v[20:21], v[14:15]
v_add_f64 v[32:33], v[36:37], -v[48:49]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fma_f64 v[18:19], v[18:19], v[22:23], v[26:27]
v_add_f64 v[22:23], v[34:35], -v[20:21]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[30:31], v[30:31], v[32:33]
v_add_f64 v[32:33], v[34:35], -v[22:23]
v_add_f64 v[14:15], v[14:15], -v[22:23]
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_add_f64 v[26:27], v[34:35], v[30:31]
v_add_f64 v[30:31], v[50:51], v[18:19]
v_add_f64 v[20:21], v[20:21], -v[32:33]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f64 v[34:35], v[46:47], v[26:27]
v_add_f64 v[36:37], v[30:31], s[14:15]
v_add_f64 v[32:33], v[30:31], -v[50:51]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_f64 v[14:15], v[14:15], v[20:21]
v_add_f64 v[22:23], v[34:35], -v[46:47]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_f64 v[46:47], v[36:37], s[8:9]
v_add_f64 v[18:19], v[18:19], -v[32:33]
v_cmp_eq_u32_e64 s8, s33, v10
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_f64 v[20:21], v[26:27], -v[22:23]
v_add_f64 v[22:23], v[30:31], -v[46:47]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f64 v[18:19], v[18:19], s[40:41]
v_add_f64 v[14:15], v[14:15], v[20:21]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[18:19], v[18:19], v[22:23]
v_add_f64 v[20:21], v[34:35], v[14:15]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[30:31], v[36:37], v[18:19]
v_add_f64 v[22:23], v[20:21], -v[34:35]
v_mul_f64 v[26:27], v[2:3], v[20:21]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f64 v[32:33], v[36:37], -v[30:31]
v_add_f64 v[14:15], v[14:15], -v[22:23]
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_fma_f64 v[20:21], v[2:3], v[20:21], -v[26:27]
v_mul_f64 v[22:23], v[28:29], v[30:31]
v_add_f64 v[18:19], v[18:19], v[32:33]
v_cmp_class_f64_e64 vcc_lo, v[26:27], 0x204
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_fma_f64 v[14:15], v[2:3], v[14:15], v[20:21]
v_fma_f64 v[20:21], v[28:29], v[30:31], -v[22:23]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[32:33], v[26:27], v[14:15]
v_fma_f64 v[18:19], v[28:29], v[18:19], v[20:21]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_dual_cndmask_b32 v21, v33, v27 :: v_dual_cndmask_b32 v20, v32, v26
v_fma_f64 v[16:17], v[16:17], v[30:31], v[18:19]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_4)
v_mul_f64 v[28:29], v[20:21], s[42:43]
v_cmp_nlt_f64_e64 s2, 0x40900000, v[20:21]
v_cmp_neq_f64_e64 vcc_lo, 0x7ff00000, |v[20:21]|
v_cmp_ngt_f64_e64 s3, 0xc090cc00, v[20:21]
v_rndne_f64_e32 v[18:19], v[28:29]
v_add_f64 v[28:29], v[22:23], v[16:17]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f64 v[34:35], v[18:19], s[44:45], v[20:21]
v_add_f64 v[30:31], v[42:43], v[28:29]
v_add_f64 v[22:23], v[28:29], -v[22:23]
v_cvt_i32_f64_e32 v6, v[18:19]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_fma_f64 v[34:35], v[18:19], s[46:47], v[34:35]
v_add_f64 v[36:37], v[30:31], -v[42:43]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[16:17], v[16:17], -v[22:23]
v_add_f64 v[22:23], v[28:29], -v[36:37]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fma_f64 v[28:29], v[34:35], s[50:51], s[48:49]
v_add_f64 v[16:17], v[44:45], v[16:17]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f64 v[28:29], v[34:35], v[28:29], s[52:53]
v_add_f64 v[16:17], v[16:17], v[22:23]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f64 v[22:23], v[34:35], v[28:29], s[54:55]
v_add_f64 v[28:29], v[30:31], v[16:17]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f64 v[22:23], v[34:35], v[22:23], s[56:57]
v_add_f64 v[36:37], v[40:41], v[28:29]
v_add_f64 v[30:31], v[28:29], -v[30:31]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fma_f64 v[22:23], v[34:35], v[22:23], s[58:59]
v_add_f64 v[38:39], v[36:37], -v[40:41]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f64 v[16:17], v[16:17], -v[30:31]
v_fma_f64 v[22:23], v[34:35], v[22:23], s[60:61]
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_add_f64 v[42:43], v[36:37], -v[38:39]
v_add_f64 v[28:29], v[28:29], -v[38:39]
v_add_f64 v[38:39], v[24:25], v[16:17]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_fma_f64 v[22:23], v[34:35], v[22:23], s[62:63]
v_add_f64 v[30:31], v[40:41], -v[42:43]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f64 v[22:23], v[34:35], v[22:23], s[66:67]
v_add_f64 v[28:29], v[28:29], v[30:31]
v_add_f64 v[30:31], v[38:39], -v[24:25]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fma_f64 v[22:23], v[34:35], v[22:23], s[68:69]
v_add_f64 v[28:29], v[38:39], v[28:29]
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_add_f64 v[38:39], v[38:39], -v[30:31]
v_add_f64 v[16:17], v[16:17], -v[30:31]
v_fma_f64 v[22:23], v[34:35], v[22:23], 1.0
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_f64 v[30:31], v[36:37], v[28:29]
v_add_f64 v[24:25], v[24:25], -v[38:39]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fma_f64 v[18:19], v[34:35], v[22:23], 1.0
v_add_f64 v[22:23], v[30:31], -v[36:37]
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_add_f64 v[16:17], v[16:17], v[24:25]
v_add_f64 v[24:25], v[32:33], -v[26:27]
v_ldexp_f64 v[18:19], v[18:19], v6
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f64 v[22:23], v[28:29], -v[22:23]
v_add_f64 v[14:15], v[14:15], -v[24:25]
v_mul_f64 v[25:26], v[2:3], 0.5
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_cndmask_b32_e64 v6, 0x7ff00000, v19, s2
v_add_f64 v[16:17], v[16:17], v[22:23]
v_trunc_f64_e32 v[19:20], v[2:3]
v_dual_cndmask_b32 v15, 0, v15 :: v_dual_cndmask_b32 v14, 0, v14
s_and_b32 vcc_lo, s3, s2
v_cndmask_b32_e64 v22, 0, v6, s3
v_cndmask_b32_e32 v21, 0, v18, vcc_lo
v_cmp_eq_u32_e32 vcc_lo, 1, v12
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_4)
v_fma_f64 v[14:15], v[21:22], v[14:15], v[21:22]
v_cmp_class_f64_e64 s2, v[21:22], 0x204
v_add_f64 v[23:24], v[30:31], v[16:17]
v_cmp_eq_f64_e64 s3, v[19:20], v[2:3]
v_cndmask_b32_e64 v3, 2.0, 0x3ff00000, vcc_lo
v_cndmask_b32_e64 v6, v14, v21, s2
v_cndmask_b32_e64 v15, v15, v22, s2
v_add_f64 v[27:28], v[23:24], -v[30:31]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_f64 v[18:19], v[2:3], v[23:24]
v_add_f64 v[16:17], v[16:17], -v[27:28]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_fma_f64 v[20:21], v[2:3], v[23:24], -v[18:19]
v_cmp_class_f64_e64 vcc_lo, v[18:19], 0x204
v_fma_f64 v[16:17], v[2:3], v[16:17], v[20:21]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[20:21], v[18:19], v[16:17]
v_dual_cndmask_b32 v24, v21, v19 :: v_dual_cndmask_b32 v23, v20, v18
v_add_f64 v[18:19], v[20:21], -v[18:19]
s_delay_alu instid0(VALU_DEP_2)
v_mul_f64 v[27:28], v[23:24], s[42:43]
v_cmp_neq_f64_e64 vcc_lo, 0x7ff00000, |v[23:24]|
v_cmp_nlt_f64_e64 s4, 0x40900000, v[23:24]
v_cmp_ngt_f64_e64 s5, 0xc090cc00, v[23:24]
v_add_f64 v[16:17], v[16:17], -v[18:19]
v_mul_f64 v[18:19], v[2:3], 0.5
v_rndne_f64_e32 v[27:28], v[27:28]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v16, 0, v16, vcc_lo
v_fma_f64 v[29:30], v[27:28], s[44:45], v[23:24]
v_cvt_i32_f64_e32 v8, v[27:28]
v_trunc_f64_e32 v[23:24], v[25:26]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[29:30], v[27:28], s[46:47], v[29:30]
v_fma_f64 v[31:32], v[29:30], s[50:51], s[48:49]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[31:32], v[29:30], v[31:32], s[52:53]
v_fma_f64 v[31:32], v[29:30], v[31:32], s[54:55]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[31:32], v[29:30], v[31:32], s[56:57]
v_fma_f64 v[31:32], v[29:30], v[31:32], s[58:59]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[31:32], v[29:30], v[31:32], s[60:61]
v_fma_f64 v[31:32], v[29:30], v[31:32], s[62:63]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[31:32], v[29:30], v[31:32], s[66:67]
v_fma_f64 v[31:32], v[29:30], v[31:32], s[68:69]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[31:32], v[29:30], v[31:32], 1.0
v_fma_f64 v[27:28], v[29:30], v[31:32], 1.0
v_trunc_f64_e32 v[29:30], v[18:19]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
v_ldexp_f64 v[20:21], v[27:28], v8
v_trunc_f64_e32 v[27:28], v[2:3]
v_cndmask_b32_e32 v17, 0, v17, vcc_lo
s_and_b32 vcc_lo, s5, s4
v_cndmask_b32_e32 v20, 0, v20, vcc_lo
s_delay_alu instid0(VALU_DEP_4)
v_cndmask_b32_e64 v8, 0x7ff00000, v21, s4
v_cmp_neq_f64_e64 s4, v[23:24], v[25:26]
v_cmp_eq_u32_e32 vcc_lo, s6, v11
v_cmp_eq_f64_e64 s7, v[27:28], v[2:3]
v_cndmask_b32_e64 v3, 0x7ff00000, 0, s8
v_cndmask_b32_e64 v21, 0, v8, s5
v_cmp_neq_f64_e64 s5, v[29:30], v[18:19]
v_cndmask_b32_e64 v8, 0x7ff00000, 0, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_fma_f64 v[16:17], v[20:21], v[16:17], v[20:21]
v_cmp_class_f64_e64 s6, v[20:21], 0x204
s_and_b32 s2, s3, s4
v_cndmask_b32_e64 v18, 0x3ff00000, v9, s2
v_cndmask_b32_e64 v9, 0, v9, s2
v_cmp_gt_i32_e64 s2, 0, v13
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_bfi_b32 v15, 0x7fffffff, v15, v18
v_bfi_b32 v9, 0x7fffffff, v8, v9
v_cndmask_b32_e64 v14, v16, v20, s6
v_cndmask_b32_e64 v16, 0, v6, s3
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cndmask_b32_e64 v8, 0x7ff80000, v15, s3
v_cndmask_b32_e64 v6, v6, v16, s2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cndmask_b32_e64 v13, v15, v8, s2
v_cndmask_b32_e64 v8, v6, 0, vcc_lo
s_delay_alu instid0(VALU_DEP_2)
v_cndmask_b32_e32 v9, v13, v9, vcc_lo
s_and_b32 vcc_lo, s7, s5
v_cndmask_b32_e64 v6, v17, v21, s6
v_cndmask_b32_e32 v15, 0x3ff00000, v7, vcc_lo
v_cndmask_b32_e64 v13, 0, v14, s7
v_cndmask_b32_e32 v7, 0, v7, vcc_lo
v_cmp_gt_i32_e32 vcc_lo, 0, v12
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_bfi_b32 v6, 0x7fffffff, v6, v15
v_bfi_b32 v3, 0x7fffffff, v3, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e64 v7, 0x7ff80000, v6, s7
v_cndmask_b32_e32 v7, v6, v7, vcc_lo
v_cndmask_b32_e32 v6, v14, v13, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cndmask_b32_e64 v7, v7, v3, s8
v_cndmask_b32_e64 v6, v6, 0, s8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[6:7], v[8:9], v[6:7]
v_cmp_gt_f64_e32 vcc_lo, 0x10000000, v[6:7]
v_cndmask_b32_e64 v3, 0, 1, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b32_e32 v3, 8, v3
v_ldexp_f64 v[6:7], v[6:7], v3
v_cndmask_b32_e64 v3, 0, 0xffffff80, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_1)
v_rsq_f64_e32 v[8:9], v[6:7]
v_cmp_class_f64_e64 vcc_lo, v[6:7], 0x260
s_waitcnt_depctr 0xfff
v_mul_f64 v[12:13], v[6:7], v[8:9]
v_mul_f64 v[8:9], v[8:9], 0.5
v_fma_f64 v[14:15], -v[8:9], v[12:13], 0.5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_fma_f64 v[12:13], v[12:13], v[14:15], v[12:13]
v_fma_f64 v[8:9], v[8:9], v[14:15], v[8:9]
v_fma_f64 v[14:15], -v[12:13], v[12:13], v[6:7]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[12:13], v[14:15], v[8:9], v[12:13]
v_fma_f64 v[14:15], -v[12:13], v[12:13], v[6:7]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[8:9], v[14:15], v[8:9], v[12:13]
v_ldexp_f64 v[8:9], v[8:9], v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_cndmask_b32 v7, v9, v7 :: v_dual_cndmask_b32 v6, v8, v6
v_cmp_lt_f64_e32 vcc_lo, v[6:7], v[4:5]
v_cndmask_b32_e32 v4, v4, v6, vcc_lo
v_cndmask_b32_e64 v0, v0, s11, vcc_lo
s_add_i32 s11, s11, 1
v_cndmask_b32_e32 v5, v5, v7, vcc_lo
s_add_u32 s12, s12, 4
s_addc_u32 s13, s13, 0
s_cmp_eq_u32 s10, s11
s_cbranch_scc0 .LBB0_2
s_branch .LBB0_4
.LBB0_3:
v_mov_b32_e32 v0, -1
.LBB0_4:
s_load_b64 s[0:1], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v1, vcc_lo, s0, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
global_store_b32 v[1:2], v0, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9voronoi_dPiS_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 58
.amdhsa_next_free_sgpr 70
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9voronoi_dPiS_ii, .Lfunc_end0-_Z9voronoi_dPiS_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9voronoi_dPiS_ii
.private_segment_fixed_size: 0
.sgpr_count: 72
.sgpr_spill_count: 0
.symbol: _Z9voronoi_dPiS_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 58
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <iostream>
#include <cstdlib>
#include <cfloat>
#include <math.h>
#include <sys/time.h>
#define THREADS_PER_BLOCK 32
__global__ void voronoi_d (int *imageArray, int *points, int imageSize, int numPoints) {
// use x to access each cell and compare it to each point and assign the cell's value to match the closest point
int x = blockIdx.x * blockDim.x + threadIdx.x;
double minDistance = DBL_MAX;
int minPoint = -1;
for (int k=0; k<numPoints; k++) {
double distance = sqrt(pow((double) (x % imageSize - points[k + numPoints]), 2.0) + pow((double) (x / imageSize - points[k]), 2.0));
if (distance < minDistance) {
minDistance = distance;
minPoint = k;
}
}
imageArray[x] = minPoint;
}
extern void gpuVoronoi(int *imageArray_h, int *points_h, int imageSize, int numPoints)
{
// allocate space for the image and point coordinates on the device and copy the coordinates over
int *imageArray;
int *points;
hipMalloc ((void**) &imageArray, sizeof(int) * imageSize * imageSize);
hipMalloc ((void**) &points, sizeof(int) * numPoints * 2);
hipMemcpy (points, points_h, sizeof(int) * numPoints * 2, hipMemcpyHostToDevice);
// start calculation timing
struct timeval start, end;
gettimeofday(&start, NULL);
// calculate and then synchronize to ensure accurate timing
voronoi_d <<< ceil((float) imageSize*imageSize/THREADS_PER_BLOCK), THREADS_PER_BLOCK >>> (imageArray, points, imageSize, numPoints);
hipDeviceSynchronize();
// end timing and print processing time
gettimeofday(&end, NULL);
long seconds = (end.tv_sec - start.tv_sec);
long micros = ((seconds * 1000000) + end.tv_usec) - (start.tv_usec);
printf("Processing time elpased is %zu seconds or %zu micros\n", seconds, micros);
// print CUDA errors
hipError_t err = hipGetLastError();
printf("CUDA error: %s\n", hipGetErrorString(err));
// copy results to host and free device memory
hipMemcpy (imageArray_h, imageArray, sizeof(int) * imageSize * imageSize, hipMemcpyDeviceToHost);
hipFree (imageArray);
hipFree (points);
} | .text
.file "vgpu.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z24__device_stub__voronoi_dPiS_ii # -- Begin function _Z24__device_stub__voronoi_dPiS_ii
.p2align 4, 0x90
.type _Z24__device_stub__voronoi_dPiS_ii,@function
_Z24__device_stub__voronoi_dPiS_ii: # @_Z24__device_stub__voronoi_dPiS_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9voronoi_dPiS_ii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z24__device_stub__voronoi_dPiS_ii, .Lfunc_end0-_Z24__device_stub__voronoi_dPiS_ii
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z10gpuVoronoiPiS_ii
.LCPI1_0:
.long 0x3d000000 # float 0.03125
.text
.globl _Z10gpuVoronoiPiS_ii
.p2align 4, 0x90
.type _Z10gpuVoronoiPiS_ii,@function
_Z10gpuVoronoiPiS_ii: # @_Z10gpuVoronoiPiS_ii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $152, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %ecx, %ebp
movl %edx, %r15d
movq %rsi, %r12
movq %rdi, 64(%rsp) # 8-byte Spill
movslq %edx, %rbx
movq %rbx, %r14
imulq %rbx, %r14
shlq $2, %r14
leaq 16(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
movslq %ebp, %r13
shlq $3, %r13
leaq 8(%rsp), %rdi
movq %r13, %rsi
callq hipMalloc
movq 8(%rsp), %rdi
movq %r12, %rsi
movq %r13, %rdx
movl $1, %ecx
callq hipMemcpy
leaq 136(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
cvtsi2ss %ebx, %xmm0
mulss %xmm0, %xmm0
mulss .LCPI1_0(%rip), %xmm0
callq ceilf@PLT
cvttss2si %xmm0, %rax
movl %eax, %edi
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %rdi
orq $32, %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq %rax, 128(%rsp)
movq %rcx, 120(%rsp)
movl %r15d, 28(%rsp)
movl %ebp, 24(%rsp)
leaq 128(%rsp), %rax
movq %rax, 32(%rsp)
leaq 120(%rsp), %rax
movq %rax, 40(%rsp)
leaq 28(%rsp), %rax
movq %rax, 48(%rsp)
leaq 24(%rsp), %rax
movq %rax, 56(%rsp)
leaq 104(%rsp), %rdi
leaq 88(%rsp), %rsi
leaq 80(%rsp), %rdx
leaq 72(%rsp), %rcx
callq __hipPopCallConfiguration
movq 104(%rsp), %rsi
movl 112(%rsp), %edx
movq 88(%rsp), %rcx
movl 96(%rsp), %r8d
leaq 32(%rsp), %r9
movl $_Z9voronoi_dPiS_ii, %edi
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
pushq 88(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
callq hipDeviceSynchronize
leaq 32(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movq 32(%rsp), %rsi
subq 136(%rsp), %rsi
imulq $1000000, %rsi, %rdx # imm = 0xF4240
addq 40(%rsp), %rdx
subq 144(%rsp), %rdx
movl $.L.str, %edi
xorl %eax, %eax
callq printf
callq hipGetLastError
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.1, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
movq 16(%rsp), %rsi
movq 64(%rsp), %rdi # 8-byte Reload
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
addq $152, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z10gpuVoronoiPiS_ii, .Lfunc_end1-_Z10gpuVoronoiPiS_ii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9voronoi_dPiS_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9voronoi_dPiS_ii,@object # @_Z9voronoi_dPiS_ii
.section .rodata,"a",@progbits
.globl _Z9voronoi_dPiS_ii
.p2align 3, 0x0
_Z9voronoi_dPiS_ii:
.quad _Z24__device_stub__voronoi_dPiS_ii
.size _Z9voronoi_dPiS_ii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Processing time elpased is %zu seconds or %zu micros\n"
.size .L.str, 54
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "CUDA error: %s\n"
.size .L.str.1, 16
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z9voronoi_dPiS_ii"
.size .L__unnamed_1, 19
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__voronoi_dPiS_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9voronoi_dPiS_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000b38cb_00000000-6_vgpu.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z32__device_stub__Z9voronoi_dPiS_iiPiS_ii
.type _Z32__device_stub__Z9voronoi_dPiS_iiPiS_ii, @function
_Z32__device_stub__Z9voronoi_dPiS_iiPiS_ii:
.LFB3694:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9voronoi_dPiS_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3694:
.size _Z32__device_stub__Z9voronoi_dPiS_iiPiS_ii, .-_Z32__device_stub__Z9voronoi_dPiS_iiPiS_ii
.globl _Z9voronoi_dPiS_ii
.type _Z9voronoi_dPiS_ii, @function
_Z9voronoi_dPiS_ii:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z9voronoi_dPiS_iiPiS_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _Z9voronoi_dPiS_ii, .-_Z9voronoi_dPiS_ii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC4:
.string "Processing time elpased is %zu seconds or %zu micros\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC5:
.string "CUDA error: %s\n"
.text
.globl _Z10gpuVoronoiPiS_ii
.type _Z10gpuVoronoiPiS_ii, @function
_Z10gpuVoronoiPiS_ii:
.LFB3669:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $88, %rsp
.cfi_def_cfa_offset 144
movq %rdi, %rbp
movq %rsi, %r15
movl %edx, %r12d
movl %ecx, %r14d
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movslq %edx, %rbx
imulq %rbx, %rbx
salq $2, %rbx
movq %rsp, %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movslq %r14d, %r13
salq $3, %r13
leaq 8(%rsp), %rdi
movq %r13, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %r13, %rdx
movq %r15, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
leaq 32(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
movl $32, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
pxor %xmm0, %xmm0
cvtsi2ssl %r12d, %xmm0
mulss %xmm0, %xmm0
mulss .LC0(%rip), %xmm0
movaps %xmm0, %xmm3
movss .LC6(%rip), %xmm2
movaps %xmm0, %xmm1
andps %xmm2, %xmm1
movss .LC1(%rip), %xmm4
ucomiss %xmm1, %xmm4
jbe .L12
cvttss2sil %xmm0, %eax
pxor %xmm1, %xmm1
cvtsi2ssl %eax, %xmm1
cmpnless %xmm1, %xmm3
movss .LC3(%rip), %xmm4
andps %xmm4, %xmm3
addss %xmm1, %xmm3
andnps %xmm0, %xmm2
orps %xmm2, %xmm3
.L12:
cvttss2siq %xmm3, %rax
movl %eax, 20(%rsp)
movl $1, 24(%rsp)
movl 56(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 48(%rsp), %rdx
movq 20(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L16
.L13:
call cudaDeviceSynchronize@PLT
leaq 48(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
movq 48(%rsp), %rdx
subq 32(%rsp), %rdx
imulq $1000000, %rdx, %rcx
addq 56(%rsp), %rcx
subq 40(%rsp), %rcx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
call cudaGetLastError@PLT
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $2, %ecx
movq %rbx, %rdx
movq (%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L17
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L16:
.cfi_restore_state
movl %r14d, %ecx
movl %r12d, %edx
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z32__device_stub__Z9voronoi_dPiS_iiPiS_ii
jmp .L13
.L17:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size _Z10gpuVoronoiPiS_ii, .-_Z10gpuVoronoiPiS_ii
.section .rodata.str1.1
.LC7:
.string "_Z9voronoi_dPiS_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _Z9voronoi_dPiS_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC0:
.long 1023410176
.align 4
.LC1:
.long 1258291200
.align 4
.LC3:
.long 1065353216
.align 4
.LC6:
.long 2147483647
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "vgpu.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z24__device_stub__voronoi_dPiS_ii # -- Begin function _Z24__device_stub__voronoi_dPiS_ii
.p2align 4, 0x90
.type _Z24__device_stub__voronoi_dPiS_ii,@function
_Z24__device_stub__voronoi_dPiS_ii: # @_Z24__device_stub__voronoi_dPiS_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9voronoi_dPiS_ii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z24__device_stub__voronoi_dPiS_ii, .Lfunc_end0-_Z24__device_stub__voronoi_dPiS_ii
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z10gpuVoronoiPiS_ii
.LCPI1_0:
.long 0x3d000000 # float 0.03125
.text
.globl _Z10gpuVoronoiPiS_ii
.p2align 4, 0x90
.type _Z10gpuVoronoiPiS_ii,@function
_Z10gpuVoronoiPiS_ii: # @_Z10gpuVoronoiPiS_ii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $152, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %ecx, %ebp
movl %edx, %r15d
movq %rsi, %r12
movq %rdi, 64(%rsp) # 8-byte Spill
movslq %edx, %rbx
movq %rbx, %r14
imulq %rbx, %r14
shlq $2, %r14
leaq 16(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
movslq %ebp, %r13
shlq $3, %r13
leaq 8(%rsp), %rdi
movq %r13, %rsi
callq hipMalloc
movq 8(%rsp), %rdi
movq %r12, %rsi
movq %r13, %rdx
movl $1, %ecx
callq hipMemcpy
leaq 136(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
cvtsi2ss %ebx, %xmm0
mulss %xmm0, %xmm0
mulss .LCPI1_0(%rip), %xmm0
callq ceilf@PLT
cvttss2si %xmm0, %rax
movl %eax, %edi
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %rdi
orq $32, %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq %rax, 128(%rsp)
movq %rcx, 120(%rsp)
movl %r15d, 28(%rsp)
movl %ebp, 24(%rsp)
leaq 128(%rsp), %rax
movq %rax, 32(%rsp)
leaq 120(%rsp), %rax
movq %rax, 40(%rsp)
leaq 28(%rsp), %rax
movq %rax, 48(%rsp)
leaq 24(%rsp), %rax
movq %rax, 56(%rsp)
leaq 104(%rsp), %rdi
leaq 88(%rsp), %rsi
leaq 80(%rsp), %rdx
leaq 72(%rsp), %rcx
callq __hipPopCallConfiguration
movq 104(%rsp), %rsi
movl 112(%rsp), %edx
movq 88(%rsp), %rcx
movl 96(%rsp), %r8d
leaq 32(%rsp), %r9
movl $_Z9voronoi_dPiS_ii, %edi
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
pushq 88(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
callq hipDeviceSynchronize
leaq 32(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movq 32(%rsp), %rsi
subq 136(%rsp), %rsi
imulq $1000000, %rsi, %rdx # imm = 0xF4240
addq 40(%rsp), %rdx
subq 144(%rsp), %rdx
movl $.L.str, %edi
xorl %eax, %eax
callq printf
callq hipGetLastError
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.1, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
movq 16(%rsp), %rsi
movq 64(%rsp), %rdi # 8-byte Reload
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
addq $152, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z10gpuVoronoiPiS_ii, .Lfunc_end1-_Z10gpuVoronoiPiS_ii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9voronoi_dPiS_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9voronoi_dPiS_ii,@object # @_Z9voronoi_dPiS_ii
.section .rodata,"a",@progbits
.globl _Z9voronoi_dPiS_ii
.p2align 3, 0x0
_Z9voronoi_dPiS_ii:
.quad _Z24__device_stub__voronoi_dPiS_ii
.size _Z9voronoi_dPiS_ii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Processing time elpased is %zu seconds or %zu micros\n"
.size .L.str, 54
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "CUDA error: %s\n"
.size .L.str.1, 16
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z9voronoi_dPiS_ii"
.size .L__unnamed_1, 19
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__voronoi_dPiS_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9voronoi_dPiS_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /* This is a automatically generated test. Do not modify */
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
__global__
void compute(float comp, int var_1,float var_2,float var_3,float var_4,float var_5,float var_6,float var_7,float var_8,float var_9,float var_10,float var_11,float var_12,float var_13) {
if (comp == (+1.9791E7f * coshf((var_2 + +0.0f)))) {
comp += atan2f(floorf(+1.4721E-44f), -1.3111E-36f * ldexpf((+1.8350E-35f * var_3 - var_4), 2));
float tmp_1 = +1.0002E28f;
float tmp_2 = -1.2076E-35f;
comp += tmp_2 * tmp_1 / sinf(-0.0f);
if (comp == var_5 + -0.0f * asinf(+1.6377E-41f)) {
float tmp_3 = -1.2597E10f;
comp = tmp_3 / powf(-1.2530E7f, -1.8301E-44f);
}
if (comp >= atan2f(atanf((var_6 / (var_7 - (var_8 - +1.9054E35f * +1.0821E-44f - var_9)))), +0.0f)) {
comp = (var_10 - (-0.0f / cosf(+0.0f)));
}
for (int i=0; i < var_1; ++i) {
float tmp_4 = -1.7750E-18f / -1.2021E-43f;
comp = tmp_4 * (+1.3609E-19f + +0.0f);
comp += var_11 - (+0.0f * +1.1393E4f);
comp = (var_12 - var_13);
}
}
printf("%.17g\n", comp);
}
float* initPointer(float v) {
float *ret = (float*) malloc(sizeof(float)*10);
for(int i=0; i < 10; ++i)
ret[i] = v;
return ret;
}
int main(int argc, char** argv) {
/* Program variables */
float tmp_1 = atof(argv[1]);
int tmp_2 = atoi(argv[2]);
float tmp_3 = atof(argv[3]);
float tmp_4 = atof(argv[4]);
float tmp_5 = atof(argv[5]);
float tmp_6 = atof(argv[6]);
float tmp_7 = atof(argv[7]);
float tmp_8 = atof(argv[8]);
float tmp_9 = atof(argv[9]);
float tmp_10 = atof(argv[10]);
float tmp_11 = atof(argv[11]);
float tmp_12 = atof(argv[12]);
float tmp_13 = atof(argv[13]);
float tmp_14 = atof(argv[14]);
compute<<<1,1>>>(tmp_1,tmp_2,tmp_3,tmp_4,tmp_5,tmp_6,tmp_7,tmp_8,tmp_9,tmp_10,tmp_11,tmp_12,tmp_13,tmp_14);
cudaDeviceSynchronize();
return 0;
} | .file "tmpxft_0017ab53_00000000-6_test.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z11initPointerf
.type _Z11initPointerf, @function
_Z11initPointerf:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movd %xmm0, %ebx
movl $40, %edi
call malloc@PLT
movq %rax, %rdx
leaq 40(%rax), %rcx
.L4:
movl %ebx, (%rdx)
addq $4, %rdx
cmpq %rcx, %rdx
jne .L4
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _Z11initPointerf, .-_Z11initPointerf
.globl _Z38__device_stub__Z7computefifffffffffffffiffffffffffff
.type _Z38__device_stub__Z7computefifffffffffffffiffffffffffff, @function
_Z38__device_stub__Z7computefifffffffffffffiffffffffffff:
.LFB2083:
.cfi_startproc
endbr64
subq $248, %rsp
.cfi_def_cfa_offset 256
movss %xmm0, 44(%rsp)
movl %edi, 40(%rsp)
movss %xmm1, 36(%rsp)
movss %xmm2, 32(%rsp)
movss %xmm3, 28(%rsp)
movss %xmm4, 24(%rsp)
movss %xmm5, 20(%rsp)
movss %xmm6, 16(%rsp)
movss %xmm7, 12(%rsp)
movq %fs:40, %rax
movq %rax, 232(%rsp)
xorl %eax, %eax
leaq 44(%rsp), %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rax
movq %rax, 120(%rsp)
leaq 36(%rsp), %rax
movq %rax, 128(%rsp)
leaq 32(%rsp), %rax
movq %rax, 136(%rsp)
leaq 28(%rsp), %rax
movq %rax, 144(%rsp)
leaq 24(%rsp), %rax
movq %rax, 152(%rsp)
leaq 20(%rsp), %rax
movq %rax, 160(%rsp)
leaq 16(%rsp), %rax
movq %rax, 168(%rsp)
leaq 12(%rsp), %rax
movq %rax, 176(%rsp)
leaq 256(%rsp), %rax
movq %rax, 184(%rsp)
leaq 264(%rsp), %rax
movq %rax, 192(%rsp)
leaq 272(%rsp), %rax
movq %rax, 200(%rsp)
leaq 280(%rsp), %rax
movq %rax, 208(%rsp)
leaq 288(%rsp), %rax
movq %rax, 216(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L11
.L7:
movq 232(%rsp), %rax
subq %fs:40, %rax
jne .L12
addq $248, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 264
pushq 56(%rsp)
.cfi_def_cfa_offset 272
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z7computefiffffffffffff(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 256
jmp .L7
.L12:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z38__device_stub__Z7computefifffffffffffffiffffffffffff, .-_Z38__device_stub__Z7computefifffffffffffffiffffffffffff
.globl _Z7computefiffffffffffff
.type _Z7computefiffffffffffff, @function
_Z7computefiffffffffffff:
.LFB2084:
.cfi_startproc
endbr64
subq $56, %rsp
.cfi_def_cfa_offset 64
movss 96(%rsp), %xmm8
movss %xmm8, 32(%rsp)
movss 88(%rsp), %xmm8
movss %xmm8, 24(%rsp)
movss 80(%rsp), %xmm8
movss %xmm8, 16(%rsp)
movss 72(%rsp), %xmm8
movss %xmm8, 8(%rsp)
movss 64(%rsp), %xmm8
movss %xmm8, (%rsp)
call _Z38__device_stub__Z7computefifffffffffffffiffffffffffff
addq $56, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z7computefiffffffffffff, .-_Z7computefiffffffffffff
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $152, %rsp
.cfi_def_cfa_offset 176
movq %rsi, %rbx
movq 8(%rsi), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 104(%rsp)
movq 16(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %rbp
movq 24(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 96(%rsp)
movq 32(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 88(%rsp)
movq 40(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 80(%rsp)
movq 48(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 72(%rsp)
movq 56(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 64(%rsp)
movq 64(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 56(%rsp)
movq 72(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 48(%rsp)
movq 80(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 40(%rsp)
movq 88(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 32(%rsp)
movq 96(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 24(%rsp)
movq 104(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 16(%rsp)
movq 112(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 8(%rsp)
movl $1, 132(%rsp)
movl $1, 136(%rsp)
movl $1, 120(%rsp)
movl $1, 124(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 132(%rsp), %rdx
movl $1, %ecx
movq 120(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L18
.L16:
call cudaDeviceSynchronize@PLT
movl $0, %eax
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L18:
.cfi_restore_state
pxor %xmm0, %xmm0
cvtsd2ss 104(%rsp), %xmm0
subq $48, %rsp
.cfi_def_cfa_offset 224
pxor %xmm1, %xmm1
cvtsd2ss 56(%rsp), %xmm1
movss %xmm1, 32(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 64(%rsp), %xmm1
movss %xmm1, 24(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 72(%rsp), %xmm1
movss %xmm1, 16(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 80(%rsp), %xmm1
movss %xmm1, 8(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 88(%rsp), %xmm1
movss %xmm1, (%rsp)
pxor %xmm7, %xmm7
cvtsd2ss 96(%rsp), %xmm7
pxor %xmm6, %xmm6
cvtsd2ss 104(%rsp), %xmm6
pxor %xmm5, %xmm5
cvtsd2ss 112(%rsp), %xmm5
pxor %xmm4, %xmm4
cvtsd2ss 120(%rsp), %xmm4
pxor %xmm3, %xmm3
cvtsd2ss 128(%rsp), %xmm3
pxor %xmm2, %xmm2
cvtsd2ss 136(%rsp), %xmm2
pxor %xmm1, %xmm1
cvtsd2ss 144(%rsp), %xmm1
movl %ebp, %edi
call _Z38__device_stub__Z7computefifffffffffffffiffffffffffff
addq $48, %rsp
.cfi_def_cfa_offset 176
jmp .L16
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z7computefiffffffffffff"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z7computefiffffffffffff(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /* This is a automatically generated test. Do not modify */
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
__global__
void compute(float comp, int var_1,float var_2,float var_3,float var_4,float var_5,float var_6,float var_7,float var_8,float var_9,float var_10,float var_11,float var_12,float var_13) {
if (comp == (+1.9791E7f * coshf((var_2 + +0.0f)))) {
comp += atan2f(floorf(+1.4721E-44f), -1.3111E-36f * ldexpf((+1.8350E-35f * var_3 - var_4), 2));
float tmp_1 = +1.0002E28f;
float tmp_2 = -1.2076E-35f;
comp += tmp_2 * tmp_1 / sinf(-0.0f);
if (comp == var_5 + -0.0f * asinf(+1.6377E-41f)) {
float tmp_3 = -1.2597E10f;
comp = tmp_3 / powf(-1.2530E7f, -1.8301E-44f);
}
if (comp >= atan2f(atanf((var_6 / (var_7 - (var_8 - +1.9054E35f * +1.0821E-44f - var_9)))), +0.0f)) {
comp = (var_10 - (-0.0f / cosf(+0.0f)));
}
for (int i=0; i < var_1; ++i) {
float tmp_4 = -1.7750E-18f / -1.2021E-43f;
comp = tmp_4 * (+1.3609E-19f + +0.0f);
comp += var_11 - (+0.0f * +1.1393E4f);
comp = (var_12 - var_13);
}
}
printf("%.17g\n", comp);
}
float* initPointer(float v) {
float *ret = (float*) malloc(sizeof(float)*10);
for(int i=0; i < 10; ++i)
ret[i] = v;
return ret;
}
int main(int argc, char** argv) {
/* Program variables */
float tmp_1 = atof(argv[1]);
int tmp_2 = atoi(argv[2]);
float tmp_3 = atof(argv[3]);
float tmp_4 = atof(argv[4]);
float tmp_5 = atof(argv[5]);
float tmp_6 = atof(argv[6]);
float tmp_7 = atof(argv[7]);
float tmp_8 = atof(argv[8]);
float tmp_9 = atof(argv[9]);
float tmp_10 = atof(argv[10]);
float tmp_11 = atof(argv[11]);
float tmp_12 = atof(argv[12]);
float tmp_13 = atof(argv[13]);
float tmp_14 = atof(argv[14]);
compute<<<1,1>>>(tmp_1,tmp_2,tmp_3,tmp_4,tmp_5,tmp_6,tmp_7,tmp_8,tmp_9,tmp_10,tmp_11,tmp_12,tmp_13,tmp_14);
cudaDeviceSynchronize();
return 0;
} | /* This is a automatically generated test. Do not modify */
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
__global__
void compute(float comp, int var_1,float var_2,float var_3,float var_4,float var_5,float var_6,float var_7,float var_8,float var_9,float var_10,float var_11,float var_12,float var_13) {
if (comp == (+1.9791E7f * coshf((var_2 + +0.0f)))) {
comp += atan2f(floorf(+1.4721E-44f), -1.3111E-36f * ldexpf((+1.8350E-35f * var_3 - var_4), 2));
float tmp_1 = +1.0002E28f;
float tmp_2 = -1.2076E-35f;
comp += tmp_2 * tmp_1 / sinf(-0.0f);
if (comp == var_5 + -0.0f * asinf(+1.6377E-41f)) {
float tmp_3 = -1.2597E10f;
comp = tmp_3 / powf(-1.2530E7f, -1.8301E-44f);
}
if (comp >= atan2f(atanf((var_6 / (var_7 - (var_8 - +1.9054E35f * +1.0821E-44f - var_9)))), +0.0f)) {
comp = (var_10 - (-0.0f / cosf(+0.0f)));
}
for (int i=0; i < var_1; ++i) {
float tmp_4 = -1.7750E-18f / -1.2021E-43f;
comp = tmp_4 * (+1.3609E-19f + +0.0f);
comp += var_11 - (+0.0f * +1.1393E4f);
comp = (var_12 - var_13);
}
}
printf("%.17g\n", comp);
}
float* initPointer(float v) {
float *ret = (float*) malloc(sizeof(float)*10);
for(int i=0; i < 10; ++i)
ret[i] = v;
return ret;
}
int main(int argc, char** argv) {
/* Program variables */
float tmp_1 = atof(argv[1]);
int tmp_2 = atoi(argv[2]);
float tmp_3 = atof(argv[3]);
float tmp_4 = atof(argv[4]);
float tmp_5 = atof(argv[5]);
float tmp_6 = atof(argv[6]);
float tmp_7 = atof(argv[7]);
float tmp_8 = atof(argv[8]);
float tmp_9 = atof(argv[9]);
float tmp_10 = atof(argv[10]);
float tmp_11 = atof(argv[11]);
float tmp_12 = atof(argv[12]);
float tmp_13 = atof(argv[13]);
float tmp_14 = atof(argv[14]);
compute<<<1,1>>>(tmp_1,tmp_2,tmp_3,tmp_4,tmp_5,tmp_6,tmp_7,tmp_8,tmp_9,tmp_10,tmp_11,tmp_12,tmp_13,tmp_14);
hipDeviceSynchronize();
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | /* This is a automatically generated test. Do not modify */
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
__global__
void compute(float comp, int var_1,float var_2,float var_3,float var_4,float var_5,float var_6,float var_7,float var_8,float var_9,float var_10,float var_11,float var_12,float var_13) {
if (comp == (+1.9791E7f * coshf((var_2 + +0.0f)))) {
comp += atan2f(floorf(+1.4721E-44f), -1.3111E-36f * ldexpf((+1.8350E-35f * var_3 - var_4), 2));
float tmp_1 = +1.0002E28f;
float tmp_2 = -1.2076E-35f;
comp += tmp_2 * tmp_1 / sinf(-0.0f);
if (comp == var_5 + -0.0f * asinf(+1.6377E-41f)) {
float tmp_3 = -1.2597E10f;
comp = tmp_3 / powf(-1.2530E7f, -1.8301E-44f);
}
if (comp >= atan2f(atanf((var_6 / (var_7 - (var_8 - +1.9054E35f * +1.0821E-44f - var_9)))), +0.0f)) {
comp = (var_10 - (-0.0f / cosf(+0.0f)));
}
for (int i=0; i < var_1; ++i) {
float tmp_4 = -1.7750E-18f / -1.2021E-43f;
comp = tmp_4 * (+1.3609E-19f + +0.0f);
comp += var_11 - (+0.0f * +1.1393E4f);
comp = (var_12 - var_13);
}
}
printf("%.17g\n", comp);
}
float* initPointer(float v) {
float *ret = (float*) malloc(sizeof(float)*10);
for(int i=0; i < 10; ++i)
ret[i] = v;
return ret;
}
int main(int argc, char** argv) {
/* Program variables */
float tmp_1 = atof(argv[1]);
int tmp_2 = atoi(argv[2]);
float tmp_3 = atof(argv[3]);
float tmp_4 = atof(argv[4]);
float tmp_5 = atof(argv[5]);
float tmp_6 = atof(argv[6]);
float tmp_7 = atof(argv[7]);
float tmp_8 = atof(argv[8]);
float tmp_9 = atof(argv[9]);
float tmp_10 = atof(argv[10]);
float tmp_11 = atof(argv[11]);
float tmp_12 = atof(argv[12]);
float tmp_13 = atof(argv[13]);
float tmp_14 = atof(argv[14]);
compute<<<1,1>>>(tmp_1,tmp_2,tmp_3,tmp_4,tmp_5,tmp_6,tmp_7,tmp_8,tmp_9,tmp_10,tmp_11,tmp_12,tmp_13,tmp_14);
hipDeviceSynchronize();
return 0;
} | .text
.file "test.hip"
.globl _Z22__device_stub__computefiffffffffffff # -- Begin function _Z22__device_stub__computefiffffffffffff
.p2align 4, 0x90
.type _Z22__device_stub__computefiffffffffffff,@function
_Z22__device_stub__computefiffffffffffff: # @_Z22__device_stub__computefiffffffffffff
.cfi_startproc
# %bb.0:
subq $216, %rsp
.cfi_def_cfa_offset 224
movss %xmm0, 44(%rsp)
movl %edi, 40(%rsp)
movss %xmm1, 36(%rsp)
movss %xmm2, 32(%rsp)
movss %xmm3, 28(%rsp)
movss %xmm4, 24(%rsp)
movss %xmm5, 20(%rsp)
movss %xmm6, 16(%rsp)
movss %xmm7, 12(%rsp)
leaq 44(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rax
movq %rax, 104(%rsp)
leaq 36(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 28(%rsp), %rax
movq %rax, 128(%rsp)
leaq 24(%rsp), %rax
movq %rax, 136(%rsp)
leaq 20(%rsp), %rax
movq %rax, 144(%rsp)
leaq 16(%rsp), %rax
movq %rax, 152(%rsp)
leaq 12(%rsp), %rax
movq %rax, 160(%rsp)
leaq 224(%rsp), %rax
movq %rax, 168(%rsp)
leaq 232(%rsp), %rax
movq %rax, 176(%rsp)
leaq 240(%rsp), %rax
movq %rax, 184(%rsp)
leaq 248(%rsp), %rax
movq %rax, 192(%rsp)
leaq 256(%rsp), %rax
movq %rax, 200(%rsp)
leaq 80(%rsp), %rdi
leaq 64(%rsp), %rsi
leaq 56(%rsp), %rdx
leaq 48(%rsp), %rcx
callq __hipPopCallConfiguration
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
movq 64(%rsp), %rcx
movl 72(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z7computefiffffffffffff, %edi
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $232, %rsp
.cfi_adjust_cfa_offset -232
retq
.Lfunc_end0:
.size _Z22__device_stub__computefiffffffffffff, .Lfunc_end0-_Z22__device_stub__computefiffffffffffff
.cfi_endproc
# -- End function
.globl _Z11initPointerf # -- Begin function _Z11initPointerf
.p2align 4, 0x90
.type _Z11initPointerf,@function
_Z11initPointerf: # @_Z11initPointerf
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
movss %xmm0, 4(%rsp) # 4-byte Spill
movl $40, %edi
callq malloc
movss 4(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movss %xmm0, (%rax,%rcx,4)
incq %rcx
cmpq $10, %rcx
jne .LBB1_1
# %bb.2:
popq %rcx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z11initPointerf, .Lfunc_end1-_Z11initPointerf
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $328, %rsp # imm = 0x148
.cfi_def_cfa_offset 352
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movq %rsi, %r14
movq 8(%rsi), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 152(%rsp) # 8-byte Spill
movq 16(%r14), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %rbx
movq 24(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 144(%rsp) # 8-byte Spill
movq 32(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 136(%rsp) # 8-byte Spill
movq 40(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 128(%rsp) # 8-byte Spill
movq 48(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 120(%rsp) # 8-byte Spill
movq 56(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 112(%rsp) # 8-byte Spill
movq 64(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 104(%rsp) # 8-byte Spill
movq 72(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 96(%rsp) # 8-byte Spill
movq 80(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 88(%rsp) # 8-byte Spill
movq 88(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 80(%rsp) # 8-byte Spill
movq 96(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 72(%rsp) # 8-byte Spill
movq 104(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 64(%rsp) # 8-byte Spill
movq 112(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 56(%rsp) # 8-byte Spill
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_2
# %bb.1:
movsd 56(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movsd 64(%rsp), %xmm1 # 8-byte Reload
# xmm1 = mem[0],zero
cvtsd2ss %xmm1, %xmm1
movsd 72(%rsp), %xmm2 # 8-byte Reload
# xmm2 = mem[0],zero
cvtsd2ss %xmm2, %xmm2
movsd 80(%rsp), %xmm3 # 8-byte Reload
# xmm3 = mem[0],zero
cvtsd2ss %xmm3, %xmm3
movsd 88(%rsp), %xmm4 # 8-byte Reload
# xmm4 = mem[0],zero
cvtsd2ss %xmm4, %xmm4
movsd 96(%rsp), %xmm5 # 8-byte Reload
# xmm5 = mem[0],zero
cvtsd2ss %xmm5, %xmm5
movsd 104(%rsp), %xmm6 # 8-byte Reload
# xmm6 = mem[0],zero
cvtsd2ss %xmm6, %xmm6
movsd 112(%rsp), %xmm7 # 8-byte Reload
# xmm7 = mem[0],zero
cvtsd2ss %xmm7, %xmm7
movsd 120(%rsp), %xmm8 # 8-byte Reload
# xmm8 = mem[0],zero
cvtsd2ss %xmm8, %xmm8
movsd 128(%rsp), %xmm9 # 8-byte Reload
# xmm9 = mem[0],zero
cvtsd2ss %xmm9, %xmm9
movsd 136(%rsp), %xmm10 # 8-byte Reload
# xmm10 = mem[0],zero
cvtsd2ss %xmm10, %xmm10
movsd 144(%rsp), %xmm11 # 8-byte Reload
# xmm11 = mem[0],zero
cvtsd2ss %xmm11, %xmm11
movsd 152(%rsp), %xmm12 # 8-byte Reload
# xmm12 = mem[0],zero
cvtsd2ss %xmm12, %xmm12
movss %xmm12, 52(%rsp)
movl %ebx, 48(%rsp)
movss %xmm11, 44(%rsp)
movss %xmm10, 40(%rsp)
movss %xmm9, 36(%rsp)
movss %xmm8, 32(%rsp)
movss %xmm7, 28(%rsp)
movss %xmm6, 24(%rsp)
movss %xmm5, 20(%rsp)
movss %xmm4, 16(%rsp)
movss %xmm3, 12(%rsp)
movss %xmm2, 8(%rsp)
movss %xmm1, 4(%rsp)
movss %xmm0, (%rsp)
leaq 52(%rsp), %rax
movq %rax, 208(%rsp)
leaq 48(%rsp), %rax
movq %rax, 216(%rsp)
leaq 44(%rsp), %rax
movq %rax, 224(%rsp)
leaq 40(%rsp), %rax
movq %rax, 232(%rsp)
leaq 36(%rsp), %rax
movq %rax, 240(%rsp)
leaq 32(%rsp), %rax
movq %rax, 248(%rsp)
leaq 28(%rsp), %rax
movq %rax, 256(%rsp)
leaq 24(%rsp), %rax
movq %rax, 264(%rsp)
leaq 20(%rsp), %rax
movq %rax, 272(%rsp)
leaq 16(%rsp), %rax
movq %rax, 280(%rsp)
leaq 12(%rsp), %rax
movq %rax, 288(%rsp)
leaq 8(%rsp), %rax
movq %rax, 296(%rsp)
leaq 4(%rsp), %rax
movq %rax, 304(%rsp)
movq %rsp, %rax
movq %rax, 312(%rsp)
leaq 192(%rsp), %rdi
leaq 176(%rsp), %rsi
leaq 168(%rsp), %rdx
leaq 160(%rsp), %rcx
callq __hipPopCallConfiguration
movq 192(%rsp), %rsi
movl 200(%rsp), %edx
movq 176(%rsp), %rcx
movl 184(%rsp), %r8d
leaq 208(%rsp), %r9
movl $_Z7computefiffffffffffff, %edi
pushq 160(%rsp)
.cfi_adjust_cfa_offset 8
pushq 176(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_2:
callq hipDeviceSynchronize
xorl %eax, %eax
addq $328, %rsp # imm = 0x148
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7computefiffffffffffff, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z7computefiffffffffffff,@object # @_Z7computefiffffffffffff
.section .rodata,"a",@progbits
.globl _Z7computefiffffffffffff
.p2align 3, 0x0
_Z7computefiffffffffffff:
.quad _Z22__device_stub__computefiffffffffffff
.size _Z7computefiffffffffffff, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z7computefiffffffffffff"
.size .L__unnamed_1, 25
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__computefiffffffffffff
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7computefiffffffffffff
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0017ab53_00000000-6_test.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z11initPointerf
.type _Z11initPointerf, @function
_Z11initPointerf:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movd %xmm0, %ebx
movl $40, %edi
call malloc@PLT
movq %rax, %rdx
leaq 40(%rax), %rcx
.L4:
movl %ebx, (%rdx)
addq $4, %rdx
cmpq %rcx, %rdx
jne .L4
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _Z11initPointerf, .-_Z11initPointerf
.globl _Z38__device_stub__Z7computefifffffffffffffiffffffffffff
.type _Z38__device_stub__Z7computefifffffffffffffiffffffffffff, @function
_Z38__device_stub__Z7computefifffffffffffffiffffffffffff:
.LFB2083:
.cfi_startproc
endbr64
subq $248, %rsp
.cfi_def_cfa_offset 256
movss %xmm0, 44(%rsp)
movl %edi, 40(%rsp)
movss %xmm1, 36(%rsp)
movss %xmm2, 32(%rsp)
movss %xmm3, 28(%rsp)
movss %xmm4, 24(%rsp)
movss %xmm5, 20(%rsp)
movss %xmm6, 16(%rsp)
movss %xmm7, 12(%rsp)
movq %fs:40, %rax
movq %rax, 232(%rsp)
xorl %eax, %eax
leaq 44(%rsp), %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rax
movq %rax, 120(%rsp)
leaq 36(%rsp), %rax
movq %rax, 128(%rsp)
leaq 32(%rsp), %rax
movq %rax, 136(%rsp)
leaq 28(%rsp), %rax
movq %rax, 144(%rsp)
leaq 24(%rsp), %rax
movq %rax, 152(%rsp)
leaq 20(%rsp), %rax
movq %rax, 160(%rsp)
leaq 16(%rsp), %rax
movq %rax, 168(%rsp)
leaq 12(%rsp), %rax
movq %rax, 176(%rsp)
leaq 256(%rsp), %rax
movq %rax, 184(%rsp)
leaq 264(%rsp), %rax
movq %rax, 192(%rsp)
leaq 272(%rsp), %rax
movq %rax, 200(%rsp)
leaq 280(%rsp), %rax
movq %rax, 208(%rsp)
leaq 288(%rsp), %rax
movq %rax, 216(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L11
.L7:
movq 232(%rsp), %rax
subq %fs:40, %rax
jne .L12
addq $248, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 264
pushq 56(%rsp)
.cfi_def_cfa_offset 272
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z7computefiffffffffffff(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 256
jmp .L7
.L12:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z38__device_stub__Z7computefifffffffffffffiffffffffffff, .-_Z38__device_stub__Z7computefifffffffffffffiffffffffffff
.globl _Z7computefiffffffffffff
.type _Z7computefiffffffffffff, @function
_Z7computefiffffffffffff:
.LFB2084:
.cfi_startproc
endbr64
subq $56, %rsp
.cfi_def_cfa_offset 64
movss 96(%rsp), %xmm8
movss %xmm8, 32(%rsp)
movss 88(%rsp), %xmm8
movss %xmm8, 24(%rsp)
movss 80(%rsp), %xmm8
movss %xmm8, 16(%rsp)
movss 72(%rsp), %xmm8
movss %xmm8, 8(%rsp)
movss 64(%rsp), %xmm8
movss %xmm8, (%rsp)
call _Z38__device_stub__Z7computefifffffffffffffiffffffffffff
addq $56, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z7computefiffffffffffff, .-_Z7computefiffffffffffff
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $152, %rsp
.cfi_def_cfa_offset 176
movq %rsi, %rbx
movq 8(%rsi), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 104(%rsp)
movq 16(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %rbp
movq 24(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 96(%rsp)
movq 32(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 88(%rsp)
movq 40(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 80(%rsp)
movq 48(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 72(%rsp)
movq 56(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 64(%rsp)
movq 64(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 56(%rsp)
movq 72(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 48(%rsp)
movq 80(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 40(%rsp)
movq 88(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 32(%rsp)
movq 96(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 24(%rsp)
movq 104(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 16(%rsp)
movq 112(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 8(%rsp)
movl $1, 132(%rsp)
movl $1, 136(%rsp)
movl $1, 120(%rsp)
movl $1, 124(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 132(%rsp), %rdx
movl $1, %ecx
movq 120(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L18
.L16:
call cudaDeviceSynchronize@PLT
movl $0, %eax
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L18:
.cfi_restore_state
pxor %xmm0, %xmm0
cvtsd2ss 104(%rsp), %xmm0
subq $48, %rsp
.cfi_def_cfa_offset 224
pxor %xmm1, %xmm1
cvtsd2ss 56(%rsp), %xmm1
movss %xmm1, 32(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 64(%rsp), %xmm1
movss %xmm1, 24(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 72(%rsp), %xmm1
movss %xmm1, 16(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 80(%rsp), %xmm1
movss %xmm1, 8(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 88(%rsp), %xmm1
movss %xmm1, (%rsp)
pxor %xmm7, %xmm7
cvtsd2ss 96(%rsp), %xmm7
pxor %xmm6, %xmm6
cvtsd2ss 104(%rsp), %xmm6
pxor %xmm5, %xmm5
cvtsd2ss 112(%rsp), %xmm5
pxor %xmm4, %xmm4
cvtsd2ss 120(%rsp), %xmm4
pxor %xmm3, %xmm3
cvtsd2ss 128(%rsp), %xmm3
pxor %xmm2, %xmm2
cvtsd2ss 136(%rsp), %xmm2
pxor %xmm1, %xmm1
cvtsd2ss 144(%rsp), %xmm1
movl %ebp, %edi
call _Z38__device_stub__Z7computefifffffffffffffiffffffffffff
addq $48, %rsp
.cfi_def_cfa_offset 176
jmp .L16
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z7computefiffffffffffff"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z7computefiffffffffffff(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "test.hip"
.globl _Z22__device_stub__computefiffffffffffff # -- Begin function _Z22__device_stub__computefiffffffffffff
.p2align 4, 0x90
.type _Z22__device_stub__computefiffffffffffff,@function
_Z22__device_stub__computefiffffffffffff: # @_Z22__device_stub__computefiffffffffffff
.cfi_startproc
# %bb.0:
subq $216, %rsp
.cfi_def_cfa_offset 224
movss %xmm0, 44(%rsp)
movl %edi, 40(%rsp)
movss %xmm1, 36(%rsp)
movss %xmm2, 32(%rsp)
movss %xmm3, 28(%rsp)
movss %xmm4, 24(%rsp)
movss %xmm5, 20(%rsp)
movss %xmm6, 16(%rsp)
movss %xmm7, 12(%rsp)
leaq 44(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rax
movq %rax, 104(%rsp)
leaq 36(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 28(%rsp), %rax
movq %rax, 128(%rsp)
leaq 24(%rsp), %rax
movq %rax, 136(%rsp)
leaq 20(%rsp), %rax
movq %rax, 144(%rsp)
leaq 16(%rsp), %rax
movq %rax, 152(%rsp)
leaq 12(%rsp), %rax
movq %rax, 160(%rsp)
leaq 224(%rsp), %rax
movq %rax, 168(%rsp)
leaq 232(%rsp), %rax
movq %rax, 176(%rsp)
leaq 240(%rsp), %rax
movq %rax, 184(%rsp)
leaq 248(%rsp), %rax
movq %rax, 192(%rsp)
leaq 256(%rsp), %rax
movq %rax, 200(%rsp)
leaq 80(%rsp), %rdi
leaq 64(%rsp), %rsi
leaq 56(%rsp), %rdx
leaq 48(%rsp), %rcx
callq __hipPopCallConfiguration
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
movq 64(%rsp), %rcx
movl 72(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z7computefiffffffffffff, %edi
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $232, %rsp
.cfi_adjust_cfa_offset -232
retq
.Lfunc_end0:
.size _Z22__device_stub__computefiffffffffffff, .Lfunc_end0-_Z22__device_stub__computefiffffffffffff
.cfi_endproc
# -- End function
.globl _Z11initPointerf # -- Begin function _Z11initPointerf
.p2align 4, 0x90
.type _Z11initPointerf,@function
_Z11initPointerf: # @_Z11initPointerf
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
movss %xmm0, 4(%rsp) # 4-byte Spill
movl $40, %edi
callq malloc
movss 4(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movss %xmm0, (%rax,%rcx,4)
incq %rcx
cmpq $10, %rcx
jne .LBB1_1
# %bb.2:
popq %rcx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z11initPointerf, .Lfunc_end1-_Z11initPointerf
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $328, %rsp # imm = 0x148
.cfi_def_cfa_offset 352
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movq %rsi, %r14
movq 8(%rsi), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 152(%rsp) # 8-byte Spill
movq 16(%r14), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %rbx
movq 24(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 144(%rsp) # 8-byte Spill
movq 32(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 136(%rsp) # 8-byte Spill
movq 40(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 128(%rsp) # 8-byte Spill
movq 48(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 120(%rsp) # 8-byte Spill
movq 56(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 112(%rsp) # 8-byte Spill
movq 64(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 104(%rsp) # 8-byte Spill
movq 72(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 96(%rsp) # 8-byte Spill
movq 80(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 88(%rsp) # 8-byte Spill
movq 88(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 80(%rsp) # 8-byte Spill
movq 96(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 72(%rsp) # 8-byte Spill
movq 104(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 64(%rsp) # 8-byte Spill
movq 112(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 56(%rsp) # 8-byte Spill
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_2
# %bb.1:
movsd 56(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movsd 64(%rsp), %xmm1 # 8-byte Reload
# xmm1 = mem[0],zero
cvtsd2ss %xmm1, %xmm1
movsd 72(%rsp), %xmm2 # 8-byte Reload
# xmm2 = mem[0],zero
cvtsd2ss %xmm2, %xmm2
movsd 80(%rsp), %xmm3 # 8-byte Reload
# xmm3 = mem[0],zero
cvtsd2ss %xmm3, %xmm3
movsd 88(%rsp), %xmm4 # 8-byte Reload
# xmm4 = mem[0],zero
cvtsd2ss %xmm4, %xmm4
movsd 96(%rsp), %xmm5 # 8-byte Reload
# xmm5 = mem[0],zero
cvtsd2ss %xmm5, %xmm5
movsd 104(%rsp), %xmm6 # 8-byte Reload
# xmm6 = mem[0],zero
cvtsd2ss %xmm6, %xmm6
movsd 112(%rsp), %xmm7 # 8-byte Reload
# xmm7 = mem[0],zero
cvtsd2ss %xmm7, %xmm7
movsd 120(%rsp), %xmm8 # 8-byte Reload
# xmm8 = mem[0],zero
cvtsd2ss %xmm8, %xmm8
movsd 128(%rsp), %xmm9 # 8-byte Reload
# xmm9 = mem[0],zero
cvtsd2ss %xmm9, %xmm9
movsd 136(%rsp), %xmm10 # 8-byte Reload
# xmm10 = mem[0],zero
cvtsd2ss %xmm10, %xmm10
movsd 144(%rsp), %xmm11 # 8-byte Reload
# xmm11 = mem[0],zero
cvtsd2ss %xmm11, %xmm11
movsd 152(%rsp), %xmm12 # 8-byte Reload
# xmm12 = mem[0],zero
cvtsd2ss %xmm12, %xmm12
movss %xmm12, 52(%rsp)
movl %ebx, 48(%rsp)
movss %xmm11, 44(%rsp)
movss %xmm10, 40(%rsp)
movss %xmm9, 36(%rsp)
movss %xmm8, 32(%rsp)
movss %xmm7, 28(%rsp)
movss %xmm6, 24(%rsp)
movss %xmm5, 20(%rsp)
movss %xmm4, 16(%rsp)
movss %xmm3, 12(%rsp)
movss %xmm2, 8(%rsp)
movss %xmm1, 4(%rsp)
movss %xmm0, (%rsp)
leaq 52(%rsp), %rax
movq %rax, 208(%rsp)
leaq 48(%rsp), %rax
movq %rax, 216(%rsp)
leaq 44(%rsp), %rax
movq %rax, 224(%rsp)
leaq 40(%rsp), %rax
movq %rax, 232(%rsp)
leaq 36(%rsp), %rax
movq %rax, 240(%rsp)
leaq 32(%rsp), %rax
movq %rax, 248(%rsp)
leaq 28(%rsp), %rax
movq %rax, 256(%rsp)
leaq 24(%rsp), %rax
movq %rax, 264(%rsp)
leaq 20(%rsp), %rax
movq %rax, 272(%rsp)
leaq 16(%rsp), %rax
movq %rax, 280(%rsp)
leaq 12(%rsp), %rax
movq %rax, 288(%rsp)
leaq 8(%rsp), %rax
movq %rax, 296(%rsp)
leaq 4(%rsp), %rax
movq %rax, 304(%rsp)
movq %rsp, %rax
movq %rax, 312(%rsp)
leaq 192(%rsp), %rdi
leaq 176(%rsp), %rsi
leaq 168(%rsp), %rdx
leaq 160(%rsp), %rcx
callq __hipPopCallConfiguration
movq 192(%rsp), %rsi
movl 200(%rsp), %edx
movq 176(%rsp), %rcx
movl 184(%rsp), %r8d
leaq 208(%rsp), %r9
movl $_Z7computefiffffffffffff, %edi
pushq 160(%rsp)
.cfi_adjust_cfa_offset 8
pushq 176(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_2:
callq hipDeviceSynchronize
xorl %eax, %eax
addq $328, %rsp # imm = 0x148
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7computefiffffffffffff, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z7computefiffffffffffff,@object # @_Z7computefiffffffffffff
.section .rodata,"a",@progbits
.globl _Z7computefiffffffffffff
.p2align 3, 0x0
_Z7computefiffffffffffff:
.quad _Z22__device_stub__computefiffffffffffff
.size _Z7computefiffffffffffff, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z7computefiffffffffffff"
.size .L__unnamed_1, 25
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__computefiffffffffffff
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7computefiffffffffffff
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <iostream>
#include <time.h>
//#include <cutil_inline.h>
using namespace std;
//*****************************************//
//ÒÔÏÂÁ½²¿·Ö½«ÔÚÉ豸ÉϱàÒë ÓÉ__global__±êʶ£»
template<typename T> __global__ void reducePI1(T* __restrict__ d_sum, int num){
//__restrict__ ÊÇ˵´ÓÖ»¶Á»º´æÖжÁÈ¡¸ÃÊý¾Ý£¬»áÓÐʲôÓÅÊÆÄØ£¿
//printf("blockIdx.x is %d\n",blockIdx.x);//Ï߳̿éË÷Òý£¬0~grid-1
//printf("blockDim.x is %d\n",blockDim.x);//Ï߳̿é°üº¬µÄÏß³ÌÊý£¬ÕâÀï¾ÍÊÇ<<<grid,block,size>>>ÖеÄblock
//printf("threadIdx.x is %d\n",threadIdx.x);//ÿ¸öÏ߳̿éÖÐÏ̵߳ıêºÅ£¬0~block-1
int id = blockIdx.x*blockDim.x + threadIdx.x;//Ϊÿ¸öÏ̹߳¹½¨Î¨Ò»±êºÅ£¬0~grid*block-1
T temp;
T pSum = 0;
extern T __shared__ s_pi[];//Êý¾Ý´æ·ÅÔÚ¹²Ïí´æ´¢ÉÏ£¬Ö»Óб¾Ï߳̿éÄÚµÄÏ߳̿ÉÒÔ·ÃÎÊ
T rnum = 1.0/num;
for(int i=id;i<num;i +=blockDim.x*gridDim.x){
//ÿ¸öÏ̼߳ÆËãµÄ´ÎÊýÊÇ×ܵĴÎÊý£¨num£©³ýÒÔ×ܵÄÏß³ÌÊý£¨grid*block£©
temp = (i+0.5f)*rnum;
pSum += 4.0f/(1+temp*temp);
}
s_pi[threadIdx.x] = pSum*rnum;//ÿ¸öÏ߳̿éÖеÄÏ̻߳á°Ñ×Ô¼º¼ÆËãµÃµ½µÄs_pi¶ÀÁ¢´æ´¢ÔÚ±¾¿éµÄ¹²Ïí´æ´¢ÉÏ
__syncthreads();//µÈ´ý±¾¿éËùÓÐÏ̼߳ÆËãÍê±Ï
for(int i = (blockDim.x>>1);i >0;i >>= 1){
//½«±¾¿éÄÚµÄ ¼ÆËã½á¹û ½øÐÐÀÛ¼Ó
if (threadIdx.x<i){
s_pi[threadIdx.x] += s_pi[threadIdx.x+i];
}
__syncthreads();
}
//½«¼ÓºÍµÄ½á¹ûдµ½±¾¿é¶ÔÓ¦µÄÏÔ´æÖУ¬ÒÔ±¸reducePI2ʹÓÃ
if (threadIdx.x==0)
{
d_sum[blockIdx.x]=s_pi[0];
}
//ÏÂÃæÕâ¶Î´úÂëÓ¦¸ÃÊÇÔÚÖ´ÐÐÀàËƵÄËã·¨µ«Êǽá¹û»áÓкܴóÆ«²î£¬²¢Î´ÕÒµ½ÔÒò^_^
//if (warpSize>63){
// if (threadIdx.x<32){
// s_pi[threadIdx.x] += s_pi[threadIdx.x +32];
// }
//}
//if (threadIdx.x<16){
// s_pi[threadIdx.x] += s_pi[threadIdx.x +16];
//printf("threadIdx.x 16 is %d\n",threadIdx.x);
//}
//if (threadIdx.x<8){
// s_pi[threadIdx.x] += s_pi[threadIdx.x +8];
//printf("threadIdx.x 8 is %d\n",threadIdx.x);
//}
//if (threadIdx.x<4){
// s_pi[threadIdx.x] += s_pi[threadIdx.x +4];
//printf("threadIdx.x 4 is %d\n",threadIdx.x);
//}
//if (threadIdx.x<2){
// s_pi[threadIdx.x] += s_pi[threadIdx.x +2];
//printf("threadIdx.x 2 is %d\n",threadIdx.x);
//}
//if (threadIdx.x<1){
// d_sum[blockIdx.x] = s_pi[0]+s_pi[1];
//printf("threadIdx.x 1 is %d\n",threadIdx.x);
//}
}
template<typename T> __global__ void reducePI2(T* __restrict__ d_sum, int num, T* __restrict__ d_pi){
int id = threadIdx.x;//Õâ¸öº¯ÊýµÄÏ߳̿éÖ»ÓÐÒ»¸ö£¬Ïß³ÌÊýÊÇgrid£¬ÕâÀïÒÀÈ»ÓÃid×÷ΪË÷ÒýÃû
extern T __shared__ s_sum[];//Õâ¸öÊǹ²ÏíÄÚ´æÖеģ¬Ö»ÓпéÄڿɼû
s_sum[id]=d_sum[id];//°ÑÏÔ´æÖеÄÊý¾Ý×°ÔؽøÀ´
__syncthreads();//µÈ´ý×°ÔØÍê³É
for(int i = (blockDim.x>>1);i>0;i >>=1)
//ÈÔÈ»²ÉÓðë¶Ô°ëÕۺ͵ķ½·¨¶Ô±¾¿éÄÚËùÓÐÏß³ÌÖеÄs_sum½øÐÐÇóºÍ
{
if (id<i){
s_sum[id] += s_sum[id+i];
}
__syncthreads();//µÈ´ýÇóºÍÍê³É
}
//½«ÇóºÍ½á¹ûдÈëÏԴ棬ʹµÃcpuÖ÷»ú¶Ë¿É¼û
if(threadIdx.x==0)
{
*d_pi =s_sum[0];
}
//if (warpSize>63){
// if (threadIdx.x<32){
// s_sum[threadIdx.x] += s_sum[threadIdx.x +32];
// }
//}
//if (threadIdx.x<16){
// s_sum[threadIdx.x] += s_sum[threadIdx.x +16];
//}//
//if (threadIdx.x<8){
// s_sum[threadIdx.x] += s_sum[threadIdx.x +8];
//}
//if (threadIdx.x<4){
// s_sum[threadIdx.x] += s_sum[threadIdx.x +4];
//}
//if (threadIdx.x<2){
// s_sum[threadIdx.x] += s_sum[threadIdx.x +2];
//}
//if (threadIdx.x<1){
// *d_pi = s_sum[0]+s_sum[1];
//}
}
//**********************************************//
//ÒÔÏ´úÂëÔÚÖ÷»úÉϱàÒë
template <typename T> T reducePI(int num){
int grid = 1024;//ÓÃÀ´µ÷ÕûÏ߳̿éµÄÊýÁ¿
T *tmp;
cudaMalloc((void**)&tmp,grid*sizeof(T));//ÔÚÉ豸´æ´¢Æ÷£¨ÏԴ棩ÉÏ¿ª±Ùgrid*sizeof(T)´óСµÄ¿Õ¼ä£¬Ö÷»úÉϵÄÖ¸ÕëtmpÖ¸Ïò¸Ã¿Õ¼ä
reducePI1<<<grid,256,256*sizeof(T)>>>(tmp,num);//µ÷ÓÃreducePI1
//²ÎÊý±íʾÓÐgrid¸öÏ߳̿飬ÿ¸öÏ߳̿éÓÐ256¸öỊ̈߳¬Ã¿¸öÏ߳̿éʹÓÃ256*size´óСµÄ¹²Ïí´æ´¢Æ÷£¨Ö»ÓпéÄÚ¿ÉÒÔ·ÃÎÊ£©
//Ö´ÐÐÖ®ºó£¬»áÔÚtmpΪÊ×µÄÏÔ´æÖд洢grid ¸öÖмä½á¹û
//printf("%d\n",__LINE__);//ÏÔʾ´úÂëËùÔÚÐкţ¬²»Öª»áÓÐʲôÓÃ
T *d_PI;
cudaMalloc((void**)&d_PI,sizeof(T));//ÏÔ´æÖÐΪ¦ÐµÄ¼ÆËã½á¹û¿ª±Ù¿Õ¼ä
reducePI2<<<1,grid,grid*sizeof(T)>>>(tmp,grid,d_PI);//Ö»ÓÐÒ»¸öÏ߳̿飬ÓÐgrid¸öÏß³Ì
//Ö´ÐкóÔÚÏÔ´æÖÐd_PIµÄλÖôæ·Å×îºó½á¹û
T pi;//ÕâÊÇÔÚÖ÷»úÄÚ´æÉϵĿռä
cudaMemcpy(&pi,d_PI,sizeof(T),cudaMemcpyDeviceToHost);//´ÓÏÔ´æÖн«Êý¾Ý¿½±´³öÀ´
cudaFree(tmp);//ÊÍ·ÅÏàÓ¦µÄÏÔ´æ¿Õ¼ä
cudaFree(d_PI);
return pi;
}
template <typename T> T cpuPI(int num){
T sum = 0.0f;
T temp;
for (int i=0;i<num;i++)
{
temp =(i+0.5f)/num;
sum += 4/(1+temp*temp);
}
return sum/num;
}
int main(){
printf("test for compell \n");
clock_t start, finish;//ÓÃÀ´¼Æʱ
float costtime;
start = clock();
//************
printf("cpu pi is %f\n",cpuPI<float>(1000000));//µ÷ÓÃÆÕͨµÄ´®ÐÐÑ»·¼ÆËã ¦Ð
//*************
finish = clock();
costtime = (float)(finish - start) / CLOCKS_PER_SEC; //µ¥Î»ÊÇÃë
printf("costtime of CPU is %f\n",costtime);
start = clock();
//************
printf("gpu pi is %f\n",reducePI<float>(1000000));//µ÷ÓÃÖ÷»úÉϵIJ¢ÐмÆË㺯Êý
//************
finish = clock();
costtime = (float)(finish - start) / CLOCKS_PER_SEC;
printf("costtime of GPU is %f\n",costtime);
return 0;
} | code for sm_80
Function : _Z9reducePI2IfEvPT_iS1_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R7, SR_TID.X ; /* 0x0000000000077919 */
/* 0x000e220000002100 */
/*0020*/ IMAD.MOV.U32 R2, RZ, RZ, 0x4 ; /* 0x00000004ff027424 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fc60000000a00 */
/*0040*/ IMAD.WIDE R2, R7, R2, c[0x0][0x160] ; /* 0x0000580007027625 */
/* 0x001fcc00078e0202 */
/*0050*/ LDG.E.CONSTANT R2, [R2.64] ; /* 0x0000000602027981 */
/* 0x000ea2000c1e9900 */
/*0060*/ ULDC UR4, c[0x0][0x0] ; /* 0x0000000000047ab9 */
/* 0x000fe20000000800 */
/*0070*/ ISETP.NE.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fe20003f05270 */
/*0080*/ USHF.R.U32.HI UR4, URZ, 0x1, UR4 ; /* 0x000000013f047899 */
/* 0x000fcc0008011604 */
/*0090*/ ISETP.NE.AND P1, PT, RZ, UR4, PT ; /* 0x00000004ff007c0c */
/* 0x000fe2000bf25270 */
/*00a0*/ STS [R7.X4], R2 ; /* 0x0000000207007388 */
/* 0x0041e80000004800 */
/*00b0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000ff00000010000 */
/*00c0*/ @!P1 BRA 0x190 ; /* 0x000000c000009947 */
/* 0x000fea0003800000 */
/*00d0*/ SHF.L.U32 R0, R7, 0x2, RZ ; /* 0x0000000207007819 */
/* 0x001fe200000006ff */
/*00e0*/ IMAD.U32 R3, RZ, RZ, UR4 ; /* 0x00000004ff037e24 */
/* 0x000fca000f8e00ff */
/*00f0*/ ISETP.GE.AND P1, PT, R7, R3, PT ; /* 0x000000030700720c */
/* 0x000fda0003f26270 */
/*0100*/ @!P1 LEA R2, R3, R0, 0x2 ; /* 0x0000000003029211 */
/* 0x000fe200078e10ff */
/*0110*/ @!P1 LDS R4, [R7.X4] ; /* 0x0000000007049984 */
/* 0x000fe20000004800 */
/*0120*/ SHF.R.U32.HI R3, RZ, 0x1, R3 ; /* 0x00000001ff037819 */
/* 0x000fc60000011603 */
/*0130*/ @!P1 LDS R5, [R2] ; /* 0x0000000002059984 */
/* 0x000e240000000800 */
/*0140*/ @!P1 FADD R4, R4, R5 ; /* 0x0000000504049221 */
/* 0x001fca0000000000 */
/*0150*/ @!P1 STS [R7.X4], R4 ; /* 0x0000000407009388 */
/* 0x0001e80000004800 */
/*0160*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0170*/ ISETP.NE.AND P1, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fda0003f25270 */
/*0180*/ @P1 BRA 0xf0 ; /* 0xffffff6000001947 */
/* 0x001fea000383ffff */
/*0190*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x001fea0003800000 */
/*01a0*/ LDS R5, [RZ] ; /* 0x00000000ff057984 */
/* 0x000e220000000800 */
/*01b0*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff027624 */
/* 0x000fe200078e00ff */
/*01c0*/ MOV R3, c[0x0][0x174] ; /* 0x00005d0000037a02 */
/* 0x000fca0000000f00 */
/*01d0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x001fe2000c101906 */
/*01e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01f0*/ BRA 0x1f0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z9reducePI1IfEvPT_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ I2F.F64 R6, c[0x0][0x168] ; /* 0x00005a0000067b12 */
/* 0x000e220000201c00 */
/*0020*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e680000002500 */
/*0030*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e660000002100 */
/*0040*/ MUFU.RCP64H R5, R7 ; /* 0x0000000700057308 */
/* 0x001e220000001800 */
/*0050*/ IADD3 R4, R7, 0x300402, RZ ; /* 0x0030040207047810 */
/* 0x000fc80007ffe0ff */
/*0060*/ FSETP.GEU.AND P0, PT, |R4|, 5.8789094863358348022e-39, PT ; /* 0x004004020400780b */
/* 0x000fe20003f0e200 */
/*0070*/ IMAD R2, R0, c[0x0][0x0], R3 ; /* 0x0000000000027a24 */
/* 0x002fe200078e0203 */
/*0080*/ DFMA R8, -R6, R4, 1 ; /* 0x3ff000000608742b */
/* 0x001e0c0000000104 */
/*0090*/ DFMA R8, R8, R8, R8 ; /* 0x000000080808722b */
/* 0x001e0c0000000008 */
/*00a0*/ DFMA R8, R4, R8, R4 ; /* 0x000000080408722b */
/* 0x001e0c0000000004 */
/*00b0*/ DFMA R10, -R6, R8, 1 ; /* 0x3ff00000060a742b */
/* 0x001e0c0000000108 */
/*00c0*/ DFMA R8, R8, R10, R8 ; /* 0x0000000a0808722b */
/* 0x0010620000000008 */
/*00d0*/ @P0 BRA 0x120 ; /* 0x0000004000000947 */
/* 0x000fea0003800000 */
/*00e0*/ LOP3.LUT R4, R7, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff07047812 */
/* 0x000fc800078ec0ff */
/*00f0*/ IADD3 R10, R4, -0x100000, RZ ; /* 0xfff00000040a7810 */
/* 0x001fe40007ffe0ff */
/*0100*/ MOV R4, 0x120 ; /* 0x0000012000047802 */
/* 0x000fe40000000f00 */
/*0110*/ CALL.REL.NOINC 0x4c0 ; /* 0x000003a000007944 */
/* 0x002fea0003c00000 */
/*0120*/ ISETP.GE.AND P0, PT, R2, c[0x0][0x168], PT ; /* 0x00005a0002007a0c */
/* 0x000fe20003f06270 */
/*0130*/ F2F.F32.F64 R4, R8 ; /* 0x0000000800047310 */
/* 0x0030620000301000 */
/*0140*/ BSSY B2, 0x310 ; /* 0x000001c000027945 */
/* 0x000fe20003800000 */
/*0150*/ IMAD.MOV.U32 R5, RZ, RZ, RZ ; /* 0x000000ffff057224 */
/* 0x000fd400078e00ff */
/*0160*/ @P0 BRA 0x300 ; /* 0x0000019000000947 */
/* 0x000fea0003800000 */
/*0170*/ IMAD.MOV.U32 R5, RZ, RZ, RZ ; /* 0x000000ffff057224 */
/* 0x001fe400078e00ff */
/*0180*/ I2F R6, R2 ; /* 0x0000000200067306 */
/* 0x0000a20000201400 */
/*0190*/ UMOV UR4, 0x40800000 ; /* 0x4080000000047882 */
/* 0x000fe20000000000 */
/*01a0*/ IMAD.MOV.U32 R9, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff097624 */
/* 0x000fe200078e00ff */
/*01b0*/ BSSY B1, 0x2e0 ; /* 0x0000012000017945 */
/* 0x000fe20003800000 */
/*01c0*/ IMAD.U32 R10, RZ, RZ, UR4 ; /* 0x00000004ff0a7e24 */
/* 0x000fe4000f8e00ff */
/*01d0*/ IMAD R2, R9, c[0x0][0xc], R2 ; /* 0x0000030009027a24 */
/* 0x001fca00078e0202 */
/*01e0*/ ISETP.GE.AND P2, PT, R2, c[0x0][0x168], PT ; /* 0x00005a0002007a0c */
/* 0x000fe20003f46270 */
/*01f0*/ FADD R7, R6, 0.5 ; /* 0x3f00000006077421 */
/* 0x004fc80000000000 */
/*0200*/ FMUL R7, R4, R7 ; /* 0x0000000704077220 */
/* 0x002fc80000400000 */
/*0210*/ FFMA R11, R7, R7, 1 ; /* 0x3f800000070b7423 */
/* 0x000fc80000000007 */
/*0220*/ MUFU.RCP R6, R11 ; /* 0x0000000b00067308 */
/* 0x000e300000001000 */
/*0230*/ FCHK P0, R10, R11 ; /* 0x0000000b0a007302 */
/* 0x000e620000000000 */
/*0240*/ FFMA R7, -R11, R6, 1 ; /* 0x3f8000000b077423 */
/* 0x001fc80000000106 */
/*0250*/ FFMA R7, R6, R7, R6 ; /* 0x0000000706077223 */
/* 0x000fc80000000006 */
/*0260*/ FFMA R6, R7, 4, RZ ; /* 0x4080000007067823 */
/* 0x000fc800000000ff */
/*0270*/ FFMA R8, -R11, R6, 4 ; /* 0x408000000b087423 */
/* 0x000fc80000000106 */
/*0280*/ FFMA R6, R7, R8, R6 ; /* 0x0000000807067223 */
/* 0x000fe20000000006 */
/*0290*/ @!P0 BRA 0x2d0 ; /* 0x0000003000008947 */
/* 0x002fea0003800000 */
/*02a0*/ MOV R6, 0x2c0 ; /* 0x000002c000067802 */
/* 0x000fe40000000f00 */
/*02b0*/ CALL.REL.NOINC 0x710 ; /* 0x0000045000007944 */
/* 0x000fea0003c00000 */
/*02c0*/ IMAD.MOV.U32 R6, RZ, RZ, R8 ; /* 0x000000ffff067224 */
/* 0x000fe400078e0008 */
/*02d0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*02e0*/ FADD R5, R6, R5 ; /* 0x0000000506057221 */
/* 0x000fe20000000000 */
/*02f0*/ @!P2 BRA 0x180 ; /* 0xfffffe800000a947 */
/* 0x000fea000383ffff */
/*0300*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x001fea0003800000 */
/*0310*/ ULDC UR4, c[0x0][0x0] ; /* 0x0000000000047ab9 */
/* 0x000fe20000000800 */
/*0320*/ FMUL R4, R4, R5 ; /* 0x0000000504047220 */
/* 0x002fe20000400000 */
/*0330*/ USHF.R.U32.HI UR4, URZ, 0x1, UR4 ; /* 0x000000013f047899 */
/* 0x000fe20008011604 */
/*0340*/ ISETP.NE.AND P1, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fc60003f25270 */
/*0350*/ STS [R3.X4], R4 ; /* 0x0000000403007388 */
/* 0x0001e80000004800 */
/*0360*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0370*/ ISETP.NE.AND P0, PT, RZ, UR4, PT ; /* 0x00000004ff007c0c */
/* 0x000fda000bf05270 */
/*0380*/ @!P0 BRA 0x450 ; /* 0x000000c000008947 */
/* 0x000fea0003800000 */
/*0390*/ IMAD.SHL.U32 R2, R3, 0x4, RZ ; /* 0x0000000403027824 */
/* 0x001fe400078e00ff */
/*03a0*/ IMAD.U32 R4, RZ, RZ, UR4 ; /* 0x00000004ff047e24 */
/* 0x000fca000f8e00ff */
/*03b0*/ ISETP.GE.U32.AND P0, PT, R3, R4, PT ; /* 0x000000040300720c */
/* 0x000fda0003f06070 */
/*03c0*/ @!P0 IMAD R5, R4, 0x4, R2 ; /* 0x0000000404058824 */
/* 0x000fe200078e0202 */
/*03d0*/ @!P0 LDS R6, [R3.X4] ; /* 0x0000000003068984 */
/* 0x000fe20000004800 */
/*03e0*/ SHF.R.U32.HI R4, RZ, 0x1, R4 ; /* 0x00000001ff047819 */
/* 0x000fc80000011604 */
/*03f0*/ @!P0 LDS R5, [R5] ; /* 0x0000000005058984 */
/* 0x000e240000000800 */
/*0400*/ @!P0 FADD R6, R6, R5 ; /* 0x0000000506068221 */
/* 0x001fca0000000000 */
/*0410*/ @!P0 STS [R3.X4], R6 ; /* 0x0000000603008388 */
/* 0x0001e80000004800 */
/*0420*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0430*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fda0003f05270 */
/*0440*/ @P0 BRA 0x3b0 ; /* 0xffffff6000000947 */
/* 0x001fea000383ffff */
/*0450*/ @P1 EXIT ; /* 0x000000000000194d */
/* 0x001fea0003800000 */
/*0460*/ LDS R5, [RZ] ; /* 0x00000000ff057984 */
/* 0x000e220000000800 */
/*0470*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fe200078e00ff */
/*0480*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0490*/ IMAD.WIDE.U32 R2, R0, R3, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fca00078e0003 */
/*04a0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x001fe2000c101904 */
/*04b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*04c0*/ DSETP.GTU.AND P0, PT, |R6|, +INF , PT ; /* 0x7ff000000600742a */
/* 0x000e1c0003f0c200 */
/*04d0*/ @P0 BRA 0x6d0 ; /* 0x000001f000000947 */
/* 0x001fea0003800000 */
/*04e0*/ LOP3.LUT R5, R7, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff07057812 */
/* 0x000fc800078ec0ff */
/*04f0*/ IADD3 R8, R5, -0x1, RZ ; /* 0xffffffff05087810 */
/* 0x000fc80007ffe0ff */
/*0500*/ ISETP.GE.U32.AND P0, PT, R8, 0x7fefffff, PT ; /* 0x7fefffff0800780c */
/* 0x000fda0003f06070 */
/*0510*/ @P0 LOP3.LUT R9, R7, 0x7ff00000, RZ, 0x3c, !PT ; /* 0x7ff0000007090812 */
/* 0x000fe200078e3cff */
/*0520*/ @P0 IMAD.MOV.U32 R8, RZ, RZ, RZ ; /* 0x000000ffff080224 */
/* 0x000fe200078e00ff */
/*0530*/ @P0 BRA 0x6f0 ; /* 0x000001b000000947 */
/* 0x000fea0003800000 */
/*0540*/ ISETP.GE.U32.AND P0, PT, R5, 0x1000001, PT ; /* 0x010000010500780c */
/* 0x000fda0003f06070 */
/*0550*/ @!P0 BRA 0x630 ; /* 0x000000d000008947 */
/* 0x000fea0003800000 */
/*0560*/ IADD3 R9, R7, -0x3fe00000, RZ ; /* 0xc020000007097810 */
/* 0x000fe20007ffe0ff */
/*0570*/ IMAD.MOV.U32 R8, RZ, RZ, R6 ; /* 0x000000ffff087224 */
/* 0x000fc600078e0006 */
/*0580*/ MUFU.RCP64H R11, R9 ; /* 0x00000009000b7308 */
/* 0x000e260000001800 */
/*0590*/ DFMA R12, -R8, R10, 1 ; /* 0x3ff00000080c742b */
/* 0x001e0c000000010a */
/*05a0*/ DFMA R12, R12, R12, R12 ; /* 0x0000000c0c0c722b */
/* 0x001e0c000000000c */
/*05b0*/ DFMA R12, R10, R12, R10 ; /* 0x0000000c0a0c722b */
/* 0x001e0c000000000a */
/*05c0*/ DFMA R10, -R8, R12, 1 ; /* 0x3ff00000080a742b */
/* 0x001e0c000000010c */
/*05d0*/ DFMA R10, R12, R10, R12 ; /* 0x0000000a0c0a722b */
/* 0x001e0c000000000c */
/*05e0*/ DMUL R10, R10, 2.2250738585072013831e-308 ; /* 0x001000000a0a7828 */
/* 0x001e0c0000000000 */
/*05f0*/ DFMA R6, -R6, R10, 1 ; /* 0x3ff000000606742b */
/* 0x001e0c000000010a */
/*0600*/ DFMA R6, R6, R6, R6 ; /* 0x000000060606722b */
/* 0x001e0c0000000006 */
/*0610*/ DFMA R8, R10, R6, R10 ; /* 0x000000060a08722b */
/* 0x001062000000000a */
/*0620*/ BRA 0x6f0 ; /* 0x000000c000007947 */
/* 0x000fea0003800000 */
/*0630*/ DMUL R6, R6, 8.11296384146066816958e+31 ; /* 0x4690000006067828 */
/* 0x000e220000000000 */
/*0640*/ IMAD.MOV.U32 R8, RZ, RZ, R10 ; /* 0x000000ffff087224 */
/* 0x000fca00078e000a */
/*0650*/ MUFU.RCP64H R9, R7 ; /* 0x0000000700097308 */
/* 0x001e240000001800 */
/*0660*/ DFMA R10, -R6, R8, 1 ; /* 0x3ff00000060a742b */
/* 0x001e0c0000000108 */
/*0670*/ DFMA R10, R10, R10, R10 ; /* 0x0000000a0a0a722b */
/* 0x001e0c000000000a */
/*0680*/ DFMA R10, R8, R10, R8 ; /* 0x0000000a080a722b */
/* 0x001e0c0000000008 */
/*0690*/ DFMA R8, -R6, R10, 1 ; /* 0x3ff000000608742b */
/* 0x001e0c000000010a */
/*06a0*/ DFMA R8, R10, R8, R10 ; /* 0x000000080a08722b */
/* 0x001e0c000000000a */
/*06b0*/ DMUL R8, R8, 8.11296384146066816958e+31 ; /* 0x4690000008087828 */
/* 0x001e220000000000 */
/*06c0*/ BRA 0x6f0 ; /* 0x0000002000007947 */
/* 0x000fea0003800000 */
/*06d0*/ LOP3.LUT R9, R7, 0x80000, RZ, 0xfc, !PT ; /* 0x0008000007097812 */
/* 0x000fe200078efcff */
/*06e0*/ IMAD.MOV.U32 R8, RZ, RZ, R6 ; /* 0x000000ffff087224 */
/* 0x000fe400078e0006 */
/*06f0*/ IMAD.MOV.U32 R5, RZ, RZ, 0x0 ; /* 0x00000000ff057424 */
/* 0x000fc800078e00ff */
/*0700*/ RET.REL.NODEC R4 0x0 ; /* 0xfffff8f004007950 */
/* 0x000fea0003c3ffff */
/*0710*/ SHF.R.U32.HI R7, RZ, 0x17, R11.reuse ; /* 0x00000017ff077819 */
/* 0x100fe2000001160b */
/*0720*/ BSSY B0, 0xd00 ; /* 0x000005d000007945 */
/* 0x000fe20003800000 */
/*0730*/ BSSY B3, 0x8f0 ; /* 0x000001b000037945 */
/* 0x000fe20003800000 */
/*0740*/ IMAD.MOV.U32 R9, RZ, RZ, R11 ; /* 0x000000ffff097224 */
/* 0x000fe200078e000b */
/*0750*/ LOP3.LUT R13, R7, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff070d7812 */
/* 0x000fc800078ec0ff */
/*0760*/ IADD3 R10, R13, -0x1, RZ ; /* 0xffffffff0d0a7810 */
/* 0x000fc80007ffe0ff */
/*0770*/ ISETP.GT.U32.AND P0, PT, R10, 0xfd, PT ; /* 0x000000fd0a00780c */
/* 0x000fda0003f04070 */
/*0780*/ @!P0 IMAD.MOV.U32 R8, RZ, RZ, RZ ; /* 0x000000ffff088224 */
/* 0x000fe200078e00ff */
/*0790*/ @!P0 BRA 0x8e0 ; /* 0x0000014000008947 */
/* 0x000fea0003800000 */
/*07a0*/ FSETP.GTU.FTZ.AND P0, PT, |R11|, +INF , PT ; /* 0x7f8000000b00780b */
/* 0x000fe20003f1c200 */
/*07b0*/ IMAD.MOV.U32 R7, RZ, RZ, R11 ; /* 0x000000ffff077224 */
/* 0x000fd800078e000b */
/*07c0*/ @P0 BREAK B3 ; /* 0x0000000000030942 */
/* 0x000fe20003800000 */
/*07d0*/ @P0 BRA 0xce0 ; /* 0x0000050000000947 */
/* 0x000fea0003800000 */
/*07e0*/ IMAD.MOV.U32 R8, RZ, RZ, 0x40800000 ; /* 0x40800000ff087424 */
/* 0x000fca00078e00ff */
/*07f0*/ LOP3.LUT P0, RZ, R9, 0x7fffffff, R8, 0xc8, !PT ; /* 0x7fffffff09ff7812 */
/* 0x000fda000780c808 */
/*0800*/ @!P0 BREAK B3 ; /* 0x0000000000038942 */
/* 0x000fe20003800000 */
/*0810*/ @!P0 BRA 0xcc0 ; /* 0x000004a000008947 */
/* 0x000fea0003800000 */
/*0820*/ FSETP.NEU.FTZ.AND P0, PT, |R7|, +INF , PT ; /* 0x7f8000000700780b */
/* 0x000fe40003f1d200 */
/*0830*/ LOP3.LUT P1, RZ, R8, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff08ff7812 */
/* 0x000fc8000782c0ff */
/*0840*/ PLOP3.LUT P0, PT, P0, P1, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000702572 */
/*0850*/ @P0 BREAK B3 ; /* 0x0000000000030942 */
/* 0x000fe20003800000 */
/*0860*/ @P0 BRA 0xca0 ; /* 0x0000043000000947 */
/* 0x000fea0003800000 */
/*0870*/ LOP3.LUT P0, RZ, R9, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff09ff7812 */
/* 0x000fda000780c0ff */
/*0880*/ @!P0 BREAK B3 ; /* 0x0000000000038942 */
/* 0x000fe20003800000 */
/*0890*/ @!P0 BRA 0xc70 ; /* 0x000003d000008947 */
/* 0x000fea0003800000 */
/*08a0*/ ISETP.GE.AND P0, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fe20003f06270 */
/*08b0*/ IMAD.MOV.U32 R8, RZ, RZ, RZ ; /* 0x000000ffff087224 */
/* 0x000fd800078e00ff */
/*08c0*/ @!P0 FFMA R9, R7, 1.84467440737095516160e+19, RZ ; /* 0x5f80000007098823 */
/* 0x000fe200000000ff */
/*08d0*/ @!P0 IADD3 R8, R8, 0x40, RZ ; /* 0x0000004008088810 */
/* 0x000fe40007ffe0ff */
/*08e0*/ BSYNC B3 ; /* 0x0000000000037941 */
/* 0x000fea0003800000 */
/*08f0*/ LEA R10, R13, 0xc0800000, 0x17 ; /* 0xc08000000d0a7811 */
/* 0x000fe200078eb8ff */
/*0900*/ UMOV UR4, 0x40800000 ; /* 0x4080000000047882 */
/* 0x000fe20000000000 */
/*0910*/ IADD3 R8, R8, 0x81, -R13 ; /* 0x0000008108087810 */
/* 0x000fe20007ffe80d */
/*0920*/ UIADD3 UR4, UR4, -0x1000000, URZ ; /* 0xff00000004047890 */
/* 0x000fe2000fffe03f */
/*0930*/ BSSY B3, 0xc60 ; /* 0x0000032000037945 */
/* 0x000fe20003800000 */
/*0940*/ IMAD.IADD R10, R9, 0x1, -R10 ; /* 0x00000001090a7824 */
/* 0x000fc800078e0a0a */
/*0950*/ MUFU.RCP R7, R10 ; /* 0x0000000a00077308 */
/* 0x000e220000001000 */
/*0960*/ FADD.FTZ R12, -R10, -RZ ; /* 0x800000ff0a0c7221 */
/* 0x000fc80000010100 */
/*0970*/ FFMA R14, R7, R12, 1 ; /* 0x3f800000070e7423 */
/* 0x001fc8000000000c */
/*0980*/ FFMA R11, R7, R14, R7 ; /* 0x0000000e070b7223 */
/* 0x000fc80000000007 */
/*0990*/ FFMA R7, R11, UR4, RZ ; /* 0x000000040b077c23 */
/* 0x000fc800080000ff */
/*09a0*/ FFMA R14, R12, R7, UR4 ; /* 0x000000040c0e7e23 */
/* 0x000fc80008000007 */
/*09b0*/ FFMA R14, R11, R14, R7 ; /* 0x0000000e0b0e7223 */
/* 0x000fc80000000007 */
/*09c0*/ FFMA R12, R12, R14, UR4 ; /* 0x000000040c0c7e23 */
/* 0x000fc8000800000e */
/*09d0*/ FFMA R7, R11, R12, R14 ; /* 0x0000000c0b077223 */
/* 0x000fca000000000e */
/*09e0*/ SHF.R.U32.HI R9, RZ, 0x17, R7 ; /* 0x00000017ff097819 */
/* 0x000fc80000011607 */
/*09f0*/ LOP3.LUT R9, R9, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff09097812 */
/* 0x000fca00078ec0ff */
/*0a00*/ IMAD.IADD R13, R9, 0x1, R8 ; /* 0x00000001090d7824 */
/* 0x000fca00078e0208 */
/*0a10*/ IADD3 R9, R13, -0x1, RZ ; /* 0xffffffff0d097810 */
/* 0x000fc80007ffe0ff */
/*0a20*/ ISETP.GE.U32.AND P0, PT, R9, 0xfe, PT ; /* 0x000000fe0900780c */
/* 0x000fda0003f06070 */
/*0a30*/ @!P0 BRA 0xc40 ; /* 0x0000020000008947 */
/* 0x000fea0003800000 */
/*0a40*/ ISETP.GT.AND P0, PT, R13, 0xfe, PT ; /* 0x000000fe0d00780c */
/* 0x000fda0003f04270 */
/*0a50*/ @P0 BRA 0xc10 ; /* 0x000001b000000947 */
/* 0x000fea0003800000 */
/*0a60*/ ISETP.GE.AND P0, PT, R13, 0x1, PT ; /* 0x000000010d00780c */
/* 0x000fda0003f06270 */
/*0a70*/ @P0 BRA 0xc50 ; /* 0x000001d000000947 */
/* 0x000fea0003800000 */
/*0a80*/ ISETP.GE.AND P0, PT, R13, -0x18, PT ; /* 0xffffffe80d00780c */
/* 0x000fe40003f06270 */
/*0a90*/ LOP3.LUT R7, R7, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000007077812 */
/* 0x000fd600078ec0ff */
/*0aa0*/ @!P0 BRA 0xc50 ; /* 0x000001a000008947 */
/* 0x000fea0003800000 */
/*0ab0*/ FFMA.RZ R8, R11, R12.reuse, R14.reuse ; /* 0x0000000c0b087223 */
/* 0x180fe2000000c00e */
/*0ac0*/ ISETP.NE.AND P3, PT, R13, RZ, PT ; /* 0x000000ff0d00720c */
/* 0x000fe20003f65270 */
/*0ad0*/ FFMA.RM R9, R11, R12.reuse, R14.reuse ; /* 0x0000000c0b097223 */
/* 0x180fe2000000400e */
/*0ae0*/ ISETP.NE.AND P1, PT, R13, RZ, PT ; /* 0x000000ff0d00720c */
/* 0x000fe40003f25270 */
/*0af0*/ LOP3.LUT R10, R8, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff080a7812 */
/* 0x000fe200078ec0ff */
/*0b00*/ FFMA.RP R8, R11, R12, R14 ; /* 0x0000000c0b087223 */
/* 0x000fe2000000800e */
/*0b10*/ IADD3 R11, R13, 0x20, RZ ; /* 0x000000200d0b7810 */
/* 0x000fe20007ffe0ff */
/*0b20*/ IMAD.MOV R12, RZ, RZ, -R13 ; /* 0x000000ffff0c7224 */
/* 0x000fe200078e0a0d */
/*0b30*/ LOP3.LUT R10, R10, 0x800000, RZ, 0xfc, !PT ; /* 0x008000000a0a7812 */
/* 0x000fe400078efcff */
/*0b40*/ FSETP.NEU.FTZ.AND P0, PT, R8, R9, PT ; /* 0x000000090800720b */
/* 0x000fc40003f1d000 */
/*0b50*/ SHF.L.U32 R11, R10, R11, RZ ; /* 0x0000000b0a0b7219 */
/* 0x000fe400000006ff */
/*0b60*/ SEL R9, R12, RZ, P3 ; /* 0x000000ff0c097207 */
/* 0x000fe40001800000 */
/*0b70*/ ISETP.NE.AND P1, PT, R11, RZ, P1 ; /* 0x000000ff0b00720c */
/* 0x000fe40000f25270 */
/*0b80*/ SHF.R.U32.HI R9, RZ, R9, R10 ; /* 0x00000009ff097219 */
/* 0x000fe4000001160a */
/*0b90*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40000703570 */
/*0ba0*/ SHF.R.U32.HI R11, RZ, 0x1, R9 ; /* 0x00000001ff0b7819 */
/* 0x000fc40000011609 */
/*0bb0*/ SEL R8, RZ, 0x1, !P0 ; /* 0x00000001ff087807 */
/* 0x000fc80004000000 */
/*0bc0*/ LOP3.LUT R8, R8, 0x1, R11, 0xf8, !PT ; /* 0x0000000108087812 */
/* 0x000fc800078ef80b */
/*0bd0*/ LOP3.LUT R8, R8, R9, RZ, 0xc0, !PT ; /* 0x0000000908087212 */
/* 0x000fca00078ec0ff */
/*0be0*/ IMAD.IADD R8, R11, 0x1, R8 ; /* 0x000000010b087824 */
/* 0x000fca00078e0208 */
/*0bf0*/ LOP3.LUT R7, R8, R7, RZ, 0xfc, !PT ; /* 0x0000000708077212 */
/* 0x000fe200078efcff */
/*0c00*/ BRA 0xc50 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*0c10*/ LOP3.LUT R7, R7, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000007077812 */
/* 0x000fc800078ec0ff */
/*0c20*/ LOP3.LUT R7, R7, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000007077812 */
/* 0x000fe200078efcff */
/*0c30*/ BRA 0xc50 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0c40*/ IMAD R7, R8, 0x800000, R7 ; /* 0x0080000008077824 */
/* 0x000fe400078e0207 */
/*0c50*/ BSYNC B3 ; /* 0x0000000000037941 */
/* 0x000fea0003800000 */
/*0c60*/ BRA 0xcf0 ; /* 0x0000008000007947 */
/* 0x000fea0003800000 */
/*0c70*/ LOP3.LUT R7, R9, 0x80000000, R8, 0x48, !PT ; /* 0x8000000009077812 */
/* 0x000fc800078e4808 */
/*0c80*/ LOP3.LUT R7, R7, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000007077812 */
/* 0x000fe200078efcff */
/*0c90*/ BRA 0xcf0 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*0ca0*/ LOP3.LUT R7, R9, 0x80000000, R8, 0x48, !PT ; /* 0x8000000009077812 */
/* 0x000fe200078e4808 */
/*0cb0*/ BRA 0xcf0 ; /* 0x0000003000007947 */
/* 0x000fea0003800000 */
/*0cc0*/ MUFU.RSQ R7, -QNAN ; /* 0xffc0000000077908 */
/* 0x000e220000001400 */
/*0cd0*/ BRA 0xcf0 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0ce0*/ FADD.FTZ R7, R7, 4 ; /* 0x4080000007077421 */
/* 0x000fe40000010000 */
/*0cf0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0d00*/ IMAD.MOV.U32 R8, RZ, RZ, R7 ; /* 0x000000ffff087224 */
/* 0x001fe400078e0007 */
/*0d10*/ IMAD.MOV.U32 R7, RZ, RZ, 0x0 ; /* 0x00000000ff077424 */
/* 0x000fc800078e00ff */
/*0d20*/ RET.REL.NODEC R6 0x0 ; /* 0xfffff2d006007950 */
/* 0x000fea0003c3ffff */
/*0d30*/ BRA 0xd30; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0d40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0da0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0db0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0dc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0dd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0de0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0df0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <iostream>
#include <time.h>
//#include <cutil_inline.h>
using namespace std;
//*****************************************//
//ÒÔÏÂÁ½²¿·Ö½«ÔÚÉ豸ÉϱàÒë ÓÉ__global__±êʶ£»
template<typename T> __global__ void reducePI1(T* __restrict__ d_sum, int num){
//__restrict__ ÊÇ˵´ÓÖ»¶Á»º´æÖжÁÈ¡¸ÃÊý¾Ý£¬»áÓÐʲôÓÅÊÆÄØ£¿
//printf("blockIdx.x is %d\n",blockIdx.x);//Ï߳̿éË÷Òý£¬0~grid-1
//printf("blockDim.x is %d\n",blockDim.x);//Ï߳̿é°üº¬µÄÏß³ÌÊý£¬ÕâÀï¾ÍÊÇ<<<grid,block,size>>>ÖеÄblock
//printf("threadIdx.x is %d\n",threadIdx.x);//ÿ¸öÏ߳̿éÖÐÏ̵߳ıêºÅ£¬0~block-1
int id = blockIdx.x*blockDim.x + threadIdx.x;//Ϊÿ¸öÏ̹߳¹½¨Î¨Ò»±êºÅ£¬0~grid*block-1
T temp;
T pSum = 0;
extern T __shared__ s_pi[];//Êý¾Ý´æ·ÅÔÚ¹²Ïí´æ´¢ÉÏ£¬Ö»Óб¾Ï߳̿éÄÚµÄÏ߳̿ÉÒÔ·ÃÎÊ
T rnum = 1.0/num;
for(int i=id;i<num;i +=blockDim.x*gridDim.x){
//ÿ¸öÏ̼߳ÆËãµÄ´ÎÊýÊÇ×ܵĴÎÊý£¨num£©³ýÒÔ×ܵÄÏß³ÌÊý£¨grid*block£©
temp = (i+0.5f)*rnum;
pSum += 4.0f/(1+temp*temp);
}
s_pi[threadIdx.x] = pSum*rnum;//ÿ¸öÏ߳̿éÖеÄÏ̻߳á°Ñ×Ô¼º¼ÆËãµÃµ½µÄs_pi¶ÀÁ¢´æ´¢ÔÚ±¾¿éµÄ¹²Ïí´æ´¢ÉÏ
__syncthreads();//µÈ´ý±¾¿éËùÓÐÏ̼߳ÆËãÍê±Ï
for(int i = (blockDim.x>>1);i >0;i >>= 1){
//½«±¾¿éÄÚµÄ ¼ÆËã½á¹û ½øÐÐÀÛ¼Ó
if (threadIdx.x<i){
s_pi[threadIdx.x] += s_pi[threadIdx.x+i];
}
__syncthreads();
}
//½«¼ÓºÍµÄ½á¹ûдµ½±¾¿é¶ÔÓ¦µÄÏÔ´æÖУ¬ÒÔ±¸reducePI2ʹÓÃ
if (threadIdx.x==0)
{
d_sum[blockIdx.x]=s_pi[0];
}
//ÏÂÃæÕâ¶Î´úÂëÓ¦¸ÃÊÇÔÚÖ´ÐÐÀàËƵÄËã·¨µ«Êǽá¹û»áÓкܴóÆ«²î£¬²¢Î´ÕÒµ½ÔÒò^_^
//if (warpSize>63){
// if (threadIdx.x<32){
// s_pi[threadIdx.x] += s_pi[threadIdx.x +32];
// }
//}
//if (threadIdx.x<16){
// s_pi[threadIdx.x] += s_pi[threadIdx.x +16];
//printf("threadIdx.x 16 is %d\n",threadIdx.x);
//}
//if (threadIdx.x<8){
// s_pi[threadIdx.x] += s_pi[threadIdx.x +8];
//printf("threadIdx.x 8 is %d\n",threadIdx.x);
//}
//if (threadIdx.x<4){
// s_pi[threadIdx.x] += s_pi[threadIdx.x +4];
//printf("threadIdx.x 4 is %d\n",threadIdx.x);
//}
//if (threadIdx.x<2){
// s_pi[threadIdx.x] += s_pi[threadIdx.x +2];
//printf("threadIdx.x 2 is %d\n",threadIdx.x);
//}
//if (threadIdx.x<1){
// d_sum[blockIdx.x] = s_pi[0]+s_pi[1];
//printf("threadIdx.x 1 is %d\n",threadIdx.x);
//}
}
template<typename T> __global__ void reducePI2(T* __restrict__ d_sum, int num, T* __restrict__ d_pi){
int id = threadIdx.x;//Õâ¸öº¯ÊýµÄÏ߳̿éÖ»ÓÐÒ»¸ö£¬Ïß³ÌÊýÊÇgrid£¬ÕâÀïÒÀÈ»ÓÃid×÷ΪË÷ÒýÃû
extern T __shared__ s_sum[];//Õâ¸öÊǹ²ÏíÄÚ´æÖеģ¬Ö»ÓпéÄڿɼû
s_sum[id]=d_sum[id];//°ÑÏÔ´æÖеÄÊý¾Ý×°ÔؽøÀ´
__syncthreads();//µÈ´ý×°ÔØÍê³É
for(int i = (blockDim.x>>1);i>0;i >>=1)
//ÈÔÈ»²ÉÓðë¶Ô°ëÕۺ͵ķ½·¨¶Ô±¾¿éÄÚËùÓÐÏß³ÌÖеÄs_sum½øÐÐÇóºÍ
{
if (id<i){
s_sum[id] += s_sum[id+i];
}
__syncthreads();//µÈ´ýÇóºÍÍê³É
}
//½«ÇóºÍ½á¹ûдÈëÏԴ棬ʹµÃcpuÖ÷»ú¶Ë¿É¼û
if(threadIdx.x==0)
{
*d_pi =s_sum[0];
}
//if (warpSize>63){
// if (threadIdx.x<32){
// s_sum[threadIdx.x] += s_sum[threadIdx.x +32];
// }
//}
//if (threadIdx.x<16){
// s_sum[threadIdx.x] += s_sum[threadIdx.x +16];
//}//
//if (threadIdx.x<8){
// s_sum[threadIdx.x] += s_sum[threadIdx.x +8];
//}
//if (threadIdx.x<4){
// s_sum[threadIdx.x] += s_sum[threadIdx.x +4];
//}
//if (threadIdx.x<2){
// s_sum[threadIdx.x] += s_sum[threadIdx.x +2];
//}
//if (threadIdx.x<1){
// *d_pi = s_sum[0]+s_sum[1];
//}
}
//**********************************************//
//ÒÔÏ´úÂëÔÚÖ÷»úÉϱàÒë
template <typename T> T reducePI(int num){
int grid = 1024;//ÓÃÀ´µ÷ÕûÏ߳̿éµÄÊýÁ¿
T *tmp;
cudaMalloc((void**)&tmp,grid*sizeof(T));//ÔÚÉ豸´æ´¢Æ÷£¨ÏԴ棩ÉÏ¿ª±Ùgrid*sizeof(T)´óСµÄ¿Õ¼ä£¬Ö÷»úÉϵÄÖ¸ÕëtmpÖ¸Ïò¸Ã¿Õ¼ä
reducePI1<<<grid,256,256*sizeof(T)>>>(tmp,num);//µ÷ÓÃreducePI1
//²ÎÊý±íʾÓÐgrid¸öÏ߳̿飬ÿ¸öÏ߳̿éÓÐ256¸öỊ̈߳¬Ã¿¸öÏ߳̿éʹÓÃ256*size´óСµÄ¹²Ïí´æ´¢Æ÷£¨Ö»ÓпéÄÚ¿ÉÒÔ·ÃÎÊ£©
//Ö´ÐÐÖ®ºó£¬»áÔÚtmpΪÊ×µÄÏÔ´æÖд洢grid ¸öÖмä½á¹û
//printf("%d\n",__LINE__);//ÏÔʾ´úÂëËùÔÚÐкţ¬²»Öª»áÓÐʲôÓÃ
T *d_PI;
cudaMalloc((void**)&d_PI,sizeof(T));//ÏÔ´æÖÐΪ¦ÐµÄ¼ÆËã½á¹û¿ª±Ù¿Õ¼ä
reducePI2<<<1,grid,grid*sizeof(T)>>>(tmp,grid,d_PI);//Ö»ÓÐÒ»¸öÏ߳̿飬ÓÐgrid¸öÏß³Ì
//Ö´ÐкóÔÚÏÔ´æÖÐd_PIµÄλÖôæ·Å×îºó½á¹û
T pi;//ÕâÊÇÔÚÖ÷»úÄÚ´æÉϵĿռä
cudaMemcpy(&pi,d_PI,sizeof(T),cudaMemcpyDeviceToHost);//´ÓÏÔ´æÖн«Êý¾Ý¿½±´³öÀ´
cudaFree(tmp);//ÊÍ·ÅÏàÓ¦µÄÏÔ´æ¿Õ¼ä
cudaFree(d_PI);
return pi;
}
template <typename T> T cpuPI(int num){
T sum = 0.0f;
T temp;
for (int i=0;i<num;i++)
{
temp =(i+0.5f)/num;
sum += 4/(1+temp*temp);
}
return sum/num;
}
int main(){
printf("test for compell \n");
clock_t start, finish;//ÓÃÀ´¼Æʱ
float costtime;
start = clock();
//************
printf("cpu pi is %f\n",cpuPI<float>(1000000));//µ÷ÓÃÆÕͨµÄ´®ÐÐÑ»·¼ÆËã ¦Ð
//*************
finish = clock();
costtime = (float)(finish - start) / CLOCKS_PER_SEC; //µ¥Î»ÊÇÃë
printf("costtime of CPU is %f\n",costtime);
start = clock();
//************
printf("gpu pi is %f\n",reducePI<float>(1000000));//µ÷ÓÃÖ÷»úÉϵIJ¢ÐмÆË㺯Êý
//************
finish = clock();
costtime = (float)(finish - start) / CLOCKS_PER_SEC;
printf("costtime of GPU is %f\n",costtime);
return 0;
} | .file "tmpxft_0017a509_00000000-6_computePIsave.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL34__device_stub__Z9reducePI1IfEvPT_iPfi, @function
_ZL34__device_stub__Z9reducePI1IfEvPT_iPfi:
.LFB3700:
.cfi_startproc
subq $136, %rsp
.cfi_def_cfa_offset 144
movl %esi, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
movq %rdi, 24(%rsp)
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 12(%rsp), %rax
movq %rax, 104(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L5
.L1:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L6
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L5:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9reducePI1IfEvPT_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L1
.L6:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3700:
.size _ZL34__device_stub__Z9reducePI1IfEvPT_iPfi, .-_ZL34__device_stub__Z9reducePI1IfEvPT_iPfi
.section .text._Z9reducePI1IfEvPT_i,"axG",@progbits,_Z9reducePI1IfEvPT_i,comdat
.weak _Z9reducePI1IfEvPT_i
.type _Z9reducePI1IfEvPT_i, @function
_Z9reducePI1IfEvPT_i:
.LFB4007:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _ZL34__device_stub__Z9reducePI1IfEvPT_iPfi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4007:
.size _Z9reducePI1IfEvPT_i, .-_Z9reducePI1IfEvPT_i
.text
.type _ZL37__device_stub__Z9reducePI2IfEvPT_iS1_PfiS_, @function
_ZL37__device_stub__Z9reducePI2IfEvPT_iS1_PfiS_:
.LFB3702:
.cfi_startproc
subq $136, %rsp
.cfi_def_cfa_offset 144
movl %esi, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
movq %rdi, 16(%rsp)
leaq 16(%rsp), %rax
movq %rax, 96(%rsp)
leaq 12(%rsp), %rax
movq %rax, 104(%rsp)
movq %rdx, 24(%rsp)
leaq 24(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L13
.L9:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L14
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L13:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9reducePI2IfEvPT_iS1_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L9
.L14:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3702:
.size _ZL37__device_stub__Z9reducePI2IfEvPT_iS1_PfiS_, .-_ZL37__device_stub__Z9reducePI2IfEvPT_iS1_PfiS_
.section .text._Z9reducePI2IfEvPT_iS1_,"axG",@progbits,_Z9reducePI2IfEvPT_iS1_,comdat
.weak _Z9reducePI2IfEvPT_iS1_
.type _Z9reducePI2IfEvPT_iS1_, @function
_Z9reducePI2IfEvPT_iS1_:
.LFB4009:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _ZL37__device_stub__Z9reducePI2IfEvPT_iS1_PfiS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4009:
.size _Z9reducePI2IfEvPT_iS1_, .-_Z9reducePI2IfEvPT_iS1_
.text
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3678:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3678:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z9reducePI2IfEvPT_iS1_"
.LC1:
.string "_Z9reducePI1IfEvPT_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3705:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z9reducePI2IfEvPT_iS1_(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z9reducePI1IfEvPT_i(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3705:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .text._Z8reducePIIfET_i,"axG",@progbits,_Z8reducePIIfET_i,comdat
.weak _Z8reducePIIfET_i
.type _Z8reducePIIfET_i, @function
_Z8reducePIIfET_i:
.LFB4006:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $48, %rsp
.cfi_def_cfa_offset 64
movl %edi, %ebx
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movq %rsp, %rdi
movl $4096, %esi
call cudaMalloc@PLT
movl $256, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1024, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movl $1024, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L26
.L22:
leaq 8(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
movl $1024, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movl $4096, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L27
.L23:
leaq 28(%rsp), %rdi
movl $2, %ecx
movl $4, %edx
movq 8(%rsp), %rsi
call cudaMemcpy@PLT
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movss 28(%rsp), %xmm0
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L28
addq $48, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L26:
.cfi_restore_state
movl %ebx, %esi
movq (%rsp), %rdi
call _ZL34__device_stub__Z9reducePI1IfEvPT_iPfi
jmp .L22
.L27:
movq 8(%rsp), %rdx
movl $1024, %esi
movq (%rsp), %rdi
call _ZL37__device_stub__Z9reducePI2IfEvPT_iS1_PfiS_
jmp .L23
.L28:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4006:
.size _Z8reducePIIfET_i, .-_Z8reducePIIfET_i
.section .rodata.str1.1
.LC3:
.string "test for compell \n"
.LC8:
.string "cpu pi is %f\n"
.LC9:
.string "costtime of CPU is %f\n"
.LC10:
.string "gpu pi is %f\n"
.LC11:
.string "costtime of GPU is %f\n"
.text
.globl main
.type main, @function
main:
.LFB3675:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
call clock@PLT
movq %rax, %rbx
pxor %xmm0, %xmm0
movl $0, %eax
movss .LC4(%rip), %xmm6
movss .LC5(%rip), %xmm5
movss .LC6(%rip), %xmm4
movss .LC7(%rip), %xmm3
.L30:
pxor %xmm1, %xmm1
cvtsi2ssl %eax, %xmm1
addss %xmm6, %xmm1
divss %xmm5, %xmm1
mulss %xmm1, %xmm1
addss %xmm4, %xmm1
movaps %xmm3, %xmm2
divss %xmm1, %xmm2
addss %xmm2, %xmm0
addl $1, %eax
cmpl $1000000, %eax
jne .L30
divss .LC5(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
call clock@PLT
subq %rbx, %rax
pxor %xmm0, %xmm0
cvtsi2ssq %rax, %xmm0
divss .LC5(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
call clock@PLT
movq %rax, %rbx
movl $1000000, %edi
call _Z8reducePIIfET_i
cvtss2sd %xmm0, %xmm0
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
call clock@PLT
subq %rbx, %rax
pxor %xmm0, %xmm0
cvtsi2ssq %rax, %xmm0
divss .LC5(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl $0, %eax
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3675:
.size main, .-main
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC4:
.long 1056964608
.align 4
.LC5:
.long 1232348160
.align 4
.LC6:
.long 1065353216
.align 4
.LC7:
.long 1082130432
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <iostream>
#include <time.h>
//#include <cutil_inline.h>
using namespace std;
//*****************************************//
//ÒÔÏÂÁ½²¿·Ö½«ÔÚÉ豸ÉϱàÒë ÓÉ__global__±êʶ£»
template<typename T> __global__ void reducePI1(T* __restrict__ d_sum, int num){
//__restrict__ ÊÇ˵´ÓÖ»¶Á»º´æÖжÁÈ¡¸ÃÊý¾Ý£¬»áÓÐʲôÓÅÊÆÄØ£¿
//printf("blockIdx.x is %d\n",blockIdx.x);//Ï߳̿éË÷Òý£¬0~grid-1
//printf("blockDim.x is %d\n",blockDim.x);//Ï߳̿é°üº¬µÄÏß³ÌÊý£¬ÕâÀï¾ÍÊÇ<<<grid,block,size>>>ÖеÄblock
//printf("threadIdx.x is %d\n",threadIdx.x);//ÿ¸öÏ߳̿éÖÐÏ̵߳ıêºÅ£¬0~block-1
int id = blockIdx.x*blockDim.x + threadIdx.x;//Ϊÿ¸öÏ̹߳¹½¨Î¨Ò»±êºÅ£¬0~grid*block-1
T temp;
T pSum = 0;
extern T __shared__ s_pi[];//Êý¾Ý´æ·ÅÔÚ¹²Ïí´æ´¢ÉÏ£¬Ö»Óб¾Ï߳̿éÄÚµÄÏ߳̿ÉÒÔ·ÃÎÊ
T rnum = 1.0/num;
for(int i=id;i<num;i +=blockDim.x*gridDim.x){
//ÿ¸öÏ̼߳ÆËãµÄ´ÎÊýÊÇ×ܵĴÎÊý£¨num£©³ýÒÔ×ܵÄÏß³ÌÊý£¨grid*block£©
temp = (i+0.5f)*rnum;
pSum += 4.0f/(1+temp*temp);
}
s_pi[threadIdx.x] = pSum*rnum;//ÿ¸öÏ߳̿éÖеÄÏ̻߳á°Ñ×Ô¼º¼ÆËãµÃµ½µÄs_pi¶ÀÁ¢´æ´¢ÔÚ±¾¿éµÄ¹²Ïí´æ´¢ÉÏ
__syncthreads();//µÈ´ý±¾¿éËùÓÐÏ̼߳ÆËãÍê±Ï
for(int i = (blockDim.x>>1);i >0;i >>= 1){
//½«±¾¿éÄÚµÄ ¼ÆËã½á¹û ½øÐÐÀÛ¼Ó
if (threadIdx.x<i){
s_pi[threadIdx.x] += s_pi[threadIdx.x+i];
}
__syncthreads();
}
//½«¼ÓºÍµÄ½á¹ûдµ½±¾¿é¶ÔÓ¦µÄÏÔ´æÖУ¬ÒÔ±¸reducePI2ʹÓÃ
if (threadIdx.x==0)
{
d_sum[blockIdx.x]=s_pi[0];
}
//ÏÂÃæÕâ¶Î´úÂëÓ¦¸ÃÊÇÔÚÖ´ÐÐÀàËƵÄËã·¨µ«Êǽá¹û»áÓкܴóÆ«²î£¬²¢Î´ÕÒµ½ÔÒò^_^
//if (warpSize>63){
// if (threadIdx.x<32){
// s_pi[threadIdx.x] += s_pi[threadIdx.x +32];
// }
//}
//if (threadIdx.x<16){
// s_pi[threadIdx.x] += s_pi[threadIdx.x +16];
//printf("threadIdx.x 16 is %d\n",threadIdx.x);
//}
//if (threadIdx.x<8){
// s_pi[threadIdx.x] += s_pi[threadIdx.x +8];
//printf("threadIdx.x 8 is %d\n",threadIdx.x);
//}
//if (threadIdx.x<4){
// s_pi[threadIdx.x] += s_pi[threadIdx.x +4];
//printf("threadIdx.x 4 is %d\n",threadIdx.x);
//}
//if (threadIdx.x<2){
// s_pi[threadIdx.x] += s_pi[threadIdx.x +2];
//printf("threadIdx.x 2 is %d\n",threadIdx.x);
//}
//if (threadIdx.x<1){
// d_sum[blockIdx.x] = s_pi[0]+s_pi[1];
//printf("threadIdx.x 1 is %d\n",threadIdx.x);
//}
}
template<typename T> __global__ void reducePI2(T* __restrict__ d_sum, int num, T* __restrict__ d_pi){
int id = threadIdx.x;//Õâ¸öº¯ÊýµÄÏ߳̿éÖ»ÓÐÒ»¸ö£¬Ïß³ÌÊýÊÇgrid£¬ÕâÀïÒÀÈ»ÓÃid×÷ΪË÷ÒýÃû
extern T __shared__ s_sum[];//Õâ¸öÊǹ²ÏíÄÚ´æÖеģ¬Ö»ÓпéÄڿɼû
s_sum[id]=d_sum[id];//°ÑÏÔ´æÖеÄÊý¾Ý×°ÔؽøÀ´
__syncthreads();//µÈ´ý×°ÔØÍê³É
for(int i = (blockDim.x>>1);i>0;i >>=1)
//ÈÔÈ»²ÉÓðë¶Ô°ëÕۺ͵ķ½·¨¶Ô±¾¿éÄÚËùÓÐÏß³ÌÖеÄs_sum½øÐÐÇóºÍ
{
if (id<i){
s_sum[id] += s_sum[id+i];
}
__syncthreads();//µÈ´ýÇóºÍÍê³É
}
//½«ÇóºÍ½á¹ûдÈëÏԴ棬ʹµÃcpuÖ÷»ú¶Ë¿É¼û
if(threadIdx.x==0)
{
*d_pi =s_sum[0];
}
//if (warpSize>63){
// if (threadIdx.x<32){
// s_sum[threadIdx.x] += s_sum[threadIdx.x +32];
// }
//}
//if (threadIdx.x<16){
// s_sum[threadIdx.x] += s_sum[threadIdx.x +16];
//}//
//if (threadIdx.x<8){
// s_sum[threadIdx.x] += s_sum[threadIdx.x +8];
//}
//if (threadIdx.x<4){
// s_sum[threadIdx.x] += s_sum[threadIdx.x +4];
//}
//if (threadIdx.x<2){
// s_sum[threadIdx.x] += s_sum[threadIdx.x +2];
//}
//if (threadIdx.x<1){
// *d_pi = s_sum[0]+s_sum[1];
//}
}
//**********************************************//
//ÒÔÏ´úÂëÔÚÖ÷»úÉϱàÒë
template <typename T> T reducePI(int num){
int grid = 1024;//ÓÃÀ´µ÷ÕûÏ߳̿éµÄÊýÁ¿
T *tmp;
cudaMalloc((void**)&tmp,grid*sizeof(T));//ÔÚÉ豸´æ´¢Æ÷£¨ÏԴ棩ÉÏ¿ª±Ùgrid*sizeof(T)´óСµÄ¿Õ¼ä£¬Ö÷»úÉϵÄÖ¸ÕëtmpÖ¸Ïò¸Ã¿Õ¼ä
reducePI1<<<grid,256,256*sizeof(T)>>>(tmp,num);//µ÷ÓÃreducePI1
//²ÎÊý±íʾÓÐgrid¸öÏ߳̿飬ÿ¸öÏ߳̿éÓÐ256¸öỊ̈߳¬Ã¿¸öÏ߳̿éʹÓÃ256*size´óСµÄ¹²Ïí´æ´¢Æ÷£¨Ö»ÓпéÄÚ¿ÉÒÔ·ÃÎÊ£©
//Ö´ÐÐÖ®ºó£¬»áÔÚtmpΪÊ×µÄÏÔ´æÖд洢grid ¸öÖмä½á¹û
//printf("%d\n",__LINE__);//ÏÔʾ´úÂëËùÔÚÐкţ¬²»Öª»áÓÐʲôÓÃ
T *d_PI;
cudaMalloc((void**)&d_PI,sizeof(T));//ÏÔ´æÖÐΪ¦ÐµÄ¼ÆËã½á¹û¿ª±Ù¿Õ¼ä
reducePI2<<<1,grid,grid*sizeof(T)>>>(tmp,grid,d_PI);//Ö»ÓÐÒ»¸öÏ߳̿飬ÓÐgrid¸öÏß³Ì
//Ö´ÐкóÔÚÏÔ´æÖÐd_PIµÄλÖôæ·Å×îºó½á¹û
T pi;//ÕâÊÇÔÚÖ÷»úÄÚ´æÉϵĿռä
cudaMemcpy(&pi,d_PI,sizeof(T),cudaMemcpyDeviceToHost);//´ÓÏÔ´æÖн«Êý¾Ý¿½±´³öÀ´
cudaFree(tmp);//ÊÍ·ÅÏàÓ¦µÄÏÔ´æ¿Õ¼ä
cudaFree(d_PI);
return pi;
}
template <typename T> T cpuPI(int num){
T sum = 0.0f;
T temp;
for (int i=0;i<num;i++)
{
temp =(i+0.5f)/num;
sum += 4/(1+temp*temp);
}
return sum/num;
}
int main(){
printf("test for compell \n");
clock_t start, finish;//ÓÃÀ´¼Æʱ
float costtime;
start = clock();
//************
printf("cpu pi is %f\n",cpuPI<float>(1000000));//µ÷ÓÃÆÕͨµÄ´®ÐÐÑ»·¼ÆËã ¦Ð
//*************
finish = clock();
costtime = (float)(finish - start) / CLOCKS_PER_SEC; //µ¥Î»ÊÇÃë
printf("costtime of CPU is %f\n",costtime);
start = clock();
//************
printf("gpu pi is %f\n",reducePI<float>(1000000));//µ÷ÓÃÖ÷»úÉϵIJ¢ÐмÆË㺯Êý
//************
finish = clock();
costtime = (float)(finish - start) / CLOCKS_PER_SEC;
printf("costtime of GPU is %f\n",costtime);
return 0;
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <iostream>
#include <time.h>
//#include <cutil_inline.h>
using namespace std;
//*****************************************//
//ÒÔÏÂÁ½²¿·Ö½«ÔÚÉ豸ÉϱàÒë ÓÉ__global__±êʶ£»
template<typename T> __global__ void reducePI1(T* __restrict__ d_sum, int num){
//__restrict__ ÊÇ˵´ÓÖ»¶Á»º´æÖжÁÈ¡¸ÃÊý¾Ý£¬»áÓÐʲôÓÅÊÆÄØ£¿
//printf("blockIdx.x is %d\n",blockIdx.x);//Ï߳̿éË÷Òý£¬0~grid-1
//printf("blockDim.x is %d\n",blockDim.x);//Ï߳̿é°üº¬µÄÏß³ÌÊý£¬ÕâÀï¾ÍÊÇ<<<grid,block,size>>>ÖеÄblock
//printf("threadIdx.x is %d\n",threadIdx.x);//ÿ¸öÏ߳̿éÖÐÏ̵߳ıêºÅ£¬0~block-1
int id = blockIdx.x*blockDim.x + threadIdx.x;//Ϊÿ¸öÏ̹߳¹½¨Î¨Ò»±êºÅ£¬0~grid*block-1
T temp;
T pSum = 0;
extern T __shared__ s_pi[];//Êý¾Ý´æ·ÅÔÚ¹²Ïí´æ´¢ÉÏ£¬Ö»Óб¾Ï߳̿éÄÚµÄÏ߳̿ÉÒÔ·ÃÎÊ
T rnum = 1.0/num;
for(int i=id;i<num;i +=blockDim.x*gridDim.x){
//ÿ¸öÏ̼߳ÆËãµÄ´ÎÊýÊÇ×ܵĴÎÊý£¨num£©³ýÒÔ×ܵÄÏß³ÌÊý£¨grid*block£©
temp = (i+0.5f)*rnum;
pSum += 4.0f/(1+temp*temp);
}
s_pi[threadIdx.x] = pSum*rnum;//ÿ¸öÏ߳̿éÖеÄÏ̻߳á°Ñ×Ô¼º¼ÆËãµÃµ½µÄs_pi¶ÀÁ¢´æ´¢ÔÚ±¾¿éµÄ¹²Ïí´æ´¢ÉÏ
__syncthreads();//µÈ´ý±¾¿éËùÓÐÏ̼߳ÆËãÍê±Ï
for(int i = (blockDim.x>>1);i >0;i >>= 1){
//½«±¾¿éÄÚµÄ ¼ÆËã½á¹û ½øÐÐÀÛ¼Ó
if (threadIdx.x<i){
s_pi[threadIdx.x] += s_pi[threadIdx.x+i];
}
__syncthreads();
}
//½«¼ÓºÍµÄ½á¹ûдµ½±¾¿é¶ÔÓ¦µÄÏÔ´æÖУ¬ÒÔ±¸reducePI2ʹÓÃ
if (threadIdx.x==0)
{
d_sum[blockIdx.x]=s_pi[0];
}
//ÏÂÃæÕâ¶Î´úÂëÓ¦¸ÃÊÇÔÚÖ´ÐÐÀàËƵÄËã·¨µ«Êǽá¹û»áÓкܴóÆ«²î£¬²¢Î´ÕÒµ½ÔÒò^_^
//if (warpSize>63){
// if (threadIdx.x<32){
// s_pi[threadIdx.x] += s_pi[threadIdx.x +32];
// }
//}
//if (threadIdx.x<16){
// s_pi[threadIdx.x] += s_pi[threadIdx.x +16];
//printf("threadIdx.x 16 is %d\n",threadIdx.x);
//}
//if (threadIdx.x<8){
// s_pi[threadIdx.x] += s_pi[threadIdx.x +8];
//printf("threadIdx.x 8 is %d\n",threadIdx.x);
//}
//if (threadIdx.x<4){
// s_pi[threadIdx.x] += s_pi[threadIdx.x +4];
//printf("threadIdx.x 4 is %d\n",threadIdx.x);
//}
//if (threadIdx.x<2){
// s_pi[threadIdx.x] += s_pi[threadIdx.x +2];
//printf("threadIdx.x 2 is %d\n",threadIdx.x);
//}
//if (threadIdx.x<1){
// d_sum[blockIdx.x] = s_pi[0]+s_pi[1];
//printf("threadIdx.x 1 is %d\n",threadIdx.x);
//}
}
template<typename T> __global__ void reducePI2(T* __restrict__ d_sum, int num, T* __restrict__ d_pi){
int id = threadIdx.x;//Õâ¸öº¯ÊýµÄÏ߳̿éÖ»ÓÐÒ»¸ö£¬Ïß³ÌÊýÊÇgrid£¬ÕâÀïÒÀÈ»ÓÃid×÷ΪË÷ÒýÃû
extern T __shared__ s_sum[];//Õâ¸öÊǹ²ÏíÄÚ´æÖеģ¬Ö»ÓпéÄڿɼû
s_sum[id]=d_sum[id];//°ÑÏÔ´æÖеÄÊý¾Ý×°ÔؽøÀ´
__syncthreads();//µÈ´ý×°ÔØÍê³É
for(int i = (blockDim.x>>1);i>0;i >>=1)
//ÈÔÈ»²ÉÓðë¶Ô°ëÕۺ͵ķ½·¨¶Ô±¾¿éÄÚËùÓÐÏß³ÌÖеÄs_sum½øÐÐÇóºÍ
{
if (id<i){
s_sum[id] += s_sum[id+i];
}
__syncthreads();//µÈ´ýÇóºÍÍê³É
}
//½«ÇóºÍ½á¹ûдÈëÏԴ棬ʹµÃcpuÖ÷»ú¶Ë¿É¼û
if(threadIdx.x==0)
{
*d_pi =s_sum[0];
}
//if (warpSize>63){
// if (threadIdx.x<32){
// s_sum[threadIdx.x] += s_sum[threadIdx.x +32];
// }
//}
//if (threadIdx.x<16){
// s_sum[threadIdx.x] += s_sum[threadIdx.x +16];
//}//
//if (threadIdx.x<8){
// s_sum[threadIdx.x] += s_sum[threadIdx.x +8];
//}
//if (threadIdx.x<4){
// s_sum[threadIdx.x] += s_sum[threadIdx.x +4];
//}
//if (threadIdx.x<2){
// s_sum[threadIdx.x] += s_sum[threadIdx.x +2];
//}
//if (threadIdx.x<1){
// *d_pi = s_sum[0]+s_sum[1];
//}
}
//**********************************************//
//ÒÔÏ´úÂëÔÚÖ÷»úÉϱàÒë
template <typename T> T reducePI(int num){
int grid = 1024;//ÓÃÀ´µ÷ÕûÏ߳̿éµÄÊýÁ¿
T *tmp;
hipMalloc((void**)&tmp,grid*sizeof(T));//ÔÚÉ豸´æ´¢Æ÷£¨ÏԴ棩ÉÏ¿ª±Ùgrid*sizeof(T)´óСµÄ¿Õ¼ä£¬Ö÷»úÉϵÄÖ¸ÕëtmpÖ¸Ïò¸Ã¿Õ¼ä
reducePI1<<<grid,256,256*sizeof(T)>>>(tmp,num);//µ÷ÓÃreducePI1
//²ÎÊý±íʾÓÐgrid¸öÏ߳̿飬ÿ¸öÏ߳̿éÓÐ256¸öỊ̈߳¬Ã¿¸öÏ߳̿éʹÓÃ256*size´óСµÄ¹²Ïí´æ´¢Æ÷£¨Ö»ÓпéÄÚ¿ÉÒÔ·ÃÎÊ£©
//Ö´ÐÐÖ®ºó£¬»áÔÚtmpΪÊ×µÄÏÔ´æÖд洢grid ¸öÖмä½á¹û
//printf("%d\n",__LINE__);//ÏÔʾ´úÂëËùÔÚÐкţ¬²»Öª»áÓÐʲôÓÃ
T *d_PI;
hipMalloc((void**)&d_PI,sizeof(T));//ÏÔ´æÖÐΪ¦ÐµÄ¼ÆËã½á¹û¿ª±Ù¿Õ¼ä
reducePI2<<<1,grid,grid*sizeof(T)>>>(tmp,grid,d_PI);//Ö»ÓÐÒ»¸öÏ߳̿飬ÓÐgrid¸öÏß³Ì
//Ö´ÐкóÔÚÏÔ´æÖÐd_PIµÄλÖôæ·Å×îºó½á¹û
T pi;//ÕâÊÇÔÚÖ÷»úÄÚ´æÉϵĿռä
hipMemcpy(&pi,d_PI,sizeof(T),hipMemcpyDeviceToHost);//´ÓÏÔ´æÖн«Êý¾Ý¿½±´³öÀ´
hipFree(tmp);//ÊÍ·ÅÏàÓ¦µÄÏÔ´æ¿Õ¼ä
hipFree(d_PI);
return pi;
}
template <typename T> T cpuPI(int num){
T sum = 0.0f;
T temp;
for (int i=0;i<num;i++)
{
temp =(i+0.5f)/num;
sum += 4/(1+temp*temp);
}
return sum/num;
}
int main(){
printf("test for compell \n");
clock_t start, finish;//ÓÃÀ´¼Æʱ
float costtime;
start = clock();
//************
printf("cpu pi is %f\n",cpuPI<float>(1000000));//µ÷ÓÃÆÕͨµÄ´®ÐÐÑ»·¼ÆËã ¦Ð
//*************
finish = clock();
costtime = (float)(finish - start) / CLOCKS_PER_SEC; //µ¥Î»ÊÇÃë
printf("costtime of CPU is %f\n",costtime);
start = clock();
//************
printf("gpu pi is %f\n",reducePI<float>(1000000));//µ÷ÓÃÖ÷»úÉϵIJ¢ÐмÆË㺯Êý
//************
finish = clock();
costtime = (float)(finish - start) / CLOCKS_PER_SEC;
printf("costtime of GPU is %f\n",costtime);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <iostream>
#include <time.h>
//#include <cutil_inline.h>
using namespace std;
//*****************************************//
//ÒÔÏÂÁ½²¿·Ö½«ÔÚÉ豸ÉϱàÒë ÓÉ__global__±êʶ£»
template<typename T> __global__ void reducePI1(T* __restrict__ d_sum, int num){
//__restrict__ ÊÇ˵´ÓÖ»¶Á»º´æÖжÁÈ¡¸ÃÊý¾Ý£¬»áÓÐʲôÓÅÊÆÄØ£¿
//printf("blockIdx.x is %d\n",blockIdx.x);//Ï߳̿éË÷Òý£¬0~grid-1
//printf("blockDim.x is %d\n",blockDim.x);//Ï߳̿é°üº¬µÄÏß³ÌÊý£¬ÕâÀï¾ÍÊÇ<<<grid,block,size>>>ÖеÄblock
//printf("threadIdx.x is %d\n",threadIdx.x);//ÿ¸öÏ߳̿éÖÐÏ̵߳ıêºÅ£¬0~block-1
int id = blockIdx.x*blockDim.x + threadIdx.x;//Ϊÿ¸öÏ̹߳¹½¨Î¨Ò»±êºÅ£¬0~grid*block-1
T temp;
T pSum = 0;
extern T __shared__ s_pi[];//Êý¾Ý´æ·ÅÔÚ¹²Ïí´æ´¢ÉÏ£¬Ö»Óб¾Ï߳̿éÄÚµÄÏ߳̿ÉÒÔ·ÃÎÊ
T rnum = 1.0/num;
for(int i=id;i<num;i +=blockDim.x*gridDim.x){
//ÿ¸öÏ̼߳ÆËãµÄ´ÎÊýÊÇ×ܵĴÎÊý£¨num£©³ýÒÔ×ܵÄÏß³ÌÊý£¨grid*block£©
temp = (i+0.5f)*rnum;
pSum += 4.0f/(1+temp*temp);
}
s_pi[threadIdx.x] = pSum*rnum;//ÿ¸öÏ߳̿éÖеÄÏ̻߳á°Ñ×Ô¼º¼ÆËãµÃµ½µÄs_pi¶ÀÁ¢´æ´¢ÔÚ±¾¿éµÄ¹²Ïí´æ´¢ÉÏ
__syncthreads();//µÈ´ý±¾¿éËùÓÐÏ̼߳ÆËãÍê±Ï
for(int i = (blockDim.x>>1);i >0;i >>= 1){
//½«±¾¿éÄÚµÄ ¼ÆËã½á¹û ½øÐÐÀÛ¼Ó
if (threadIdx.x<i){
s_pi[threadIdx.x] += s_pi[threadIdx.x+i];
}
__syncthreads();
}
//½«¼ÓºÍµÄ½á¹ûдµ½±¾¿é¶ÔÓ¦µÄÏÔ´æÖУ¬ÒÔ±¸reducePI2ʹÓÃ
if (threadIdx.x==0)
{
d_sum[blockIdx.x]=s_pi[0];
}
//ÏÂÃæÕâ¶Î´úÂëÓ¦¸ÃÊÇÔÚÖ´ÐÐÀàËƵÄËã·¨µ«Êǽá¹û»áÓкܴóÆ«²î£¬²¢Î´ÕÒµ½ÔÒò^_^
//if (warpSize>63){
// if (threadIdx.x<32){
// s_pi[threadIdx.x] += s_pi[threadIdx.x +32];
// }
//}
//if (threadIdx.x<16){
// s_pi[threadIdx.x] += s_pi[threadIdx.x +16];
//printf("threadIdx.x 16 is %d\n",threadIdx.x);
//}
//if (threadIdx.x<8){
// s_pi[threadIdx.x] += s_pi[threadIdx.x +8];
//printf("threadIdx.x 8 is %d\n",threadIdx.x);
//}
//if (threadIdx.x<4){
// s_pi[threadIdx.x] += s_pi[threadIdx.x +4];
//printf("threadIdx.x 4 is %d\n",threadIdx.x);
//}
//if (threadIdx.x<2){
// s_pi[threadIdx.x] += s_pi[threadIdx.x +2];
//printf("threadIdx.x 2 is %d\n",threadIdx.x);
//}
//if (threadIdx.x<1){
// d_sum[blockIdx.x] = s_pi[0]+s_pi[1];
//printf("threadIdx.x 1 is %d\n",threadIdx.x);
//}
}
template<typename T> __global__ void reducePI2(T* __restrict__ d_sum, int num, T* __restrict__ d_pi){
int id = threadIdx.x;//Õâ¸öº¯ÊýµÄÏ߳̿éÖ»ÓÐÒ»¸ö£¬Ïß³ÌÊýÊÇgrid£¬ÕâÀïÒÀÈ»ÓÃid×÷ΪË÷ÒýÃû
extern T __shared__ s_sum[];//Õâ¸öÊǹ²ÏíÄÚ´æÖеģ¬Ö»ÓпéÄڿɼû
s_sum[id]=d_sum[id];//°ÑÏÔ´æÖеÄÊý¾Ý×°ÔؽøÀ´
__syncthreads();//µÈ´ý×°ÔØÍê³É
for(int i = (blockDim.x>>1);i>0;i >>=1)
//ÈÔÈ»²ÉÓðë¶Ô°ëÕۺ͵ķ½·¨¶Ô±¾¿éÄÚËùÓÐÏß³ÌÖеÄs_sum½øÐÐÇóºÍ
{
if (id<i){
s_sum[id] += s_sum[id+i];
}
__syncthreads();//µÈ´ýÇóºÍÍê³É
}
//½«ÇóºÍ½á¹ûдÈëÏԴ棬ʹµÃcpuÖ÷»ú¶Ë¿É¼û
if(threadIdx.x==0)
{
*d_pi =s_sum[0];
}
//if (warpSize>63){
// if (threadIdx.x<32){
// s_sum[threadIdx.x] += s_sum[threadIdx.x +32];
// }
//}
//if (threadIdx.x<16){
// s_sum[threadIdx.x] += s_sum[threadIdx.x +16];
//}//
//if (threadIdx.x<8){
// s_sum[threadIdx.x] += s_sum[threadIdx.x +8];
//}
//if (threadIdx.x<4){
// s_sum[threadIdx.x] += s_sum[threadIdx.x +4];
//}
//if (threadIdx.x<2){
// s_sum[threadIdx.x] += s_sum[threadIdx.x +2];
//}
//if (threadIdx.x<1){
// *d_pi = s_sum[0]+s_sum[1];
//}
}
//**********************************************//
//ÒÔÏ´úÂëÔÚÖ÷»úÉϱàÒë
template <typename T> T reducePI(int num){
int grid = 1024;//ÓÃÀ´µ÷ÕûÏ߳̿éµÄÊýÁ¿
T *tmp;
hipMalloc((void**)&tmp,grid*sizeof(T));//ÔÚÉ豸´æ´¢Æ÷£¨ÏԴ棩ÉÏ¿ª±Ùgrid*sizeof(T)´óСµÄ¿Õ¼ä£¬Ö÷»úÉϵÄÖ¸ÕëtmpÖ¸Ïò¸Ã¿Õ¼ä
reducePI1<<<grid,256,256*sizeof(T)>>>(tmp,num);//µ÷ÓÃreducePI1
//²ÎÊý±íʾÓÐgrid¸öÏ߳̿飬ÿ¸öÏ߳̿éÓÐ256¸öỊ̈߳¬Ã¿¸öÏ߳̿éʹÓÃ256*size´óСµÄ¹²Ïí´æ´¢Æ÷£¨Ö»ÓпéÄÚ¿ÉÒÔ·ÃÎÊ£©
//Ö´ÐÐÖ®ºó£¬»áÔÚtmpΪÊ×µÄÏÔ´æÖд洢grid ¸öÖмä½á¹û
//printf("%d\n",__LINE__);//ÏÔʾ´úÂëËùÔÚÐкţ¬²»Öª»áÓÐʲôÓÃ
T *d_PI;
hipMalloc((void**)&d_PI,sizeof(T));//ÏÔ´æÖÐΪ¦ÐµÄ¼ÆËã½á¹û¿ª±Ù¿Õ¼ä
reducePI2<<<1,grid,grid*sizeof(T)>>>(tmp,grid,d_PI);//Ö»ÓÐÒ»¸öÏ߳̿飬ÓÐgrid¸öÏß³Ì
//Ö´ÐкóÔÚÏÔ´æÖÐd_PIµÄλÖôæ·Å×îºó½á¹û
T pi;//ÕâÊÇÔÚÖ÷»úÄÚ´æÉϵĿռä
hipMemcpy(&pi,d_PI,sizeof(T),hipMemcpyDeviceToHost);//´ÓÏÔ´æÖн«Êý¾Ý¿½±´³öÀ´
hipFree(tmp);//ÊÍ·ÅÏàÓ¦µÄÏÔ´æ¿Õ¼ä
hipFree(d_PI);
return pi;
}
template <typename T> T cpuPI(int num){
T sum = 0.0f;
T temp;
for (int i=0;i<num;i++)
{
temp =(i+0.5f)/num;
sum += 4/(1+temp*temp);
}
return sum/num;
}
int main(){
printf("test for compell \n");
clock_t start, finish;//ÓÃÀ´¼Æʱ
float costtime;
start = clock();
//************
printf("cpu pi is %f\n",cpuPI<float>(1000000));//µ÷ÓÃÆÕͨµÄ´®ÐÐÑ»·¼ÆËã ¦Ð
//*************
finish = clock();
costtime = (float)(finish - start) / CLOCKS_PER_SEC; //µ¥Î»ÊÇÃë
printf("costtime of CPU is %f\n",costtime);
start = clock();
//************
printf("gpu pi is %f\n",reducePI<float>(1000000));//µ÷ÓÃÖ÷»úÉϵIJ¢ÐмÆË㺯Êý
//************
finish = clock();
costtime = (float)(finish - start) / CLOCKS_PER_SEC;
printf("costtime of GPU is %f\n",costtime);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.section .text._Z9reducePI1IfEvPT_i,"axG",@progbits,_Z9reducePI1IfEvPT_i,comdat
.protected _Z9reducePI1IfEvPT_i
.globl _Z9reducePI1IfEvPT_i
.p2align 8
.type _Z9reducePI1IfEvPT_i,@function
_Z9reducePI1IfEvPT_i:
s_clause 0x2
s_load_b32 s6, s[0:1], 0x8
s_load_b32 s3, s[0:1], 0x1c
s_load_b64 s[4:5], s[0:1], 0x0
s_add_u32 s0, s0, 16
s_mov_b32 s2, s15
s_addc_u32 s1, s1, 0
s_mov_b32 s7, exec_lo
s_waitcnt lgkmcnt(0)
v_cvt_f64_i32_e32 v[1:2], s6
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_scale_f64 v[3:4], null, v[1:2], v[1:2], 1.0
v_rcp_f64_e32 v[5:6], v[3:4]
s_waitcnt_depctr 0xfff
v_fma_f64 v[7:8], -v[3:4], v[5:6], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[5:6], v[5:6], v[7:8], v[5:6]
v_fma_f64 v[7:8], -v[3:4], v[5:6], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fma_f64 v[5:6], v[5:6], v[7:8], v[5:6]
v_div_scale_f64 v[7:8], vcc_lo, 1.0, v[1:2], 1.0
v_mul_f64 v[9:10], v[7:8], v[5:6]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[3:4], -v[3:4], v[9:10], v[7:8]
v_div_fmas_f64 v[3:4], v[3:4], v[5:6], v[9:10]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fixup_f64 v[1:2], v[3:4], v[1:2], 1.0
v_cvt_f32_f64_e32 v3, v[1:2]
v_mad_u64_u32 v[1:2], null, s2, s3, v[0:1]
v_mov_b32_e32 v2, 0
s_delay_alu instid0(VALU_DEP_2)
v_cmpx_gt_i32_e64 s6, v1
s_cbranch_execz .LBB0_4
s_load_b32 s1, s[0:1], 0x0
v_mov_b32_e32 v2, 0
s_mov_b32 s0, 0
s_waitcnt lgkmcnt(0)
s_mul_i32 s1, s1, s3
.p2align 6
.LBB0_2:
v_cvt_f32_i32_e32 v4, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_add_f32 v4, 0.5, v4 :: v_dual_add_nc_u32 v1, s1, v1
v_mul_f32_e32 v4, v4, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v4, v4, v4, 1.0
v_div_scale_f32 v5, null, v4, v4, 4.0
v_div_scale_f32 v8, vcc_lo, 4.0, v4, 4.0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v6, v5
s_waitcnt_depctr 0xfff
v_fma_f32 v7, -v5, v6, 1.0
v_fmac_f32_e32 v6, v7, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v7, v8, v6
v_fma_f32 v9, -v5, v7, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v7, v9, v6
v_fma_f32 v5, -v5, v7, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_div_fmas_f32 v5, v5, v6, v7
v_cmp_le_i32_e32 vcc_lo, s6, v1
v_div_fixup_f32 v4, v5, v4, 4.0
s_or_b32 s0, vcc_lo, s0
s_delay_alu instid0(VALU_DEP_1)
v_add_f32_e32 v2, v2, v4
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB0_2
s_or_b32 exec_lo, exec_lo, s0
.LBB0_4:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_or_b32 exec_lo, exec_lo, s7
v_mul_f32_e32 v2, v2, v3
v_lshl_add_u32 v1, v0, 2, 0
s_cmp_lt_u32 s3, 2
ds_store_b32 v1, v2
s_waitcnt lgkmcnt(0)
s_barrier
s_branch .LBB0_6
.p2align 6
.LBB0_5:
s_or_b32 exec_lo, exec_lo, s1
s_waitcnt lgkmcnt(0)
s_barrier
s_cmp_lt_u32 s3, 4
s_mov_b32 s3, s0
.LBB0_6:
buffer_gl0_inv
s_cbranch_scc1 .LBB0_9
s_lshr_b32 s0, s3, 1
s_mov_b32 s1, exec_lo
v_cmpx_gt_u32_e64 s0, v0
s_cbranch_execz .LBB0_5
v_add_nc_u32_e32 v2, s0, v0
s_delay_alu instid0(VALU_DEP_1)
v_lshl_add_u32 v2, v2, 2, 0
ds_load_b32 v2, v2
ds_load_b32 v3, v1
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v2, v2, v3
ds_store_b32 v1, v2
s_branch .LBB0_5
.LBB0_9:
s_mov_b32 s0, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_11
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 0
s_mov_b32 s3, 0
s_delay_alu instid0(SALU_CYCLE_1)
s_lshl_b64 s[0:1], s[2:3], 2
ds_load_b32 v0, v0
s_add_u32 s0, s4, s0
s_addc_u32 s1, s5, s1
s_waitcnt lgkmcnt(0)
global_store_b32 v1, v0, s[0:1]
.LBB0_11:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9reducePI1IfEvPT_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 11
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.section .text._Z9reducePI1IfEvPT_i,"axG",@progbits,_Z9reducePI1IfEvPT_i,comdat
.Lfunc_end0:
.size _Z9reducePI1IfEvPT_i, .Lfunc_end0-_Z9reducePI1IfEvPT_i
.section .AMDGPU.csdata,"",@progbits
.section .text._Z9reducePI2IfEvPT_iS1_,"axG",@progbits,_Z9reducePI2IfEvPT_iS1_,comdat
.protected _Z9reducePI2IfEvPT_iS1_
.globl _Z9reducePI2IfEvPT_iS1_
.p2align 8
.type _Z9reducePI2IfEvPT_iS1_,@function
_Z9reducePI2IfEvPT_iS1_:
s_clause 0x1
s_load_b64 s[4:5], s[0:1], 0x0
s_load_b32 s2, s[0:1], 0x24
v_lshlrev_b32_e32 v1, 2, v0
s_waitcnt lgkmcnt(0)
global_load_b32 v2, v1, s[4:5]
v_cmp_lt_u16_e64 s3, s2, 2
v_add_nc_u32_e32 v1, 0, v1
s_delay_alu instid0(VALU_DEP_2)
s_and_b32 vcc_lo, exec_lo, s3
s_waitcnt vmcnt(0)
ds_store_b32 v1, v2
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_vccnz .LBB1_5
s_and_b32 s2, 0xffff, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_lshr_b32 s2, s2, 1
s_branch .LBB1_3
.p2align 6
.LBB1_2:
s_or_b32 exec_lo, exec_lo, s3
s_lshr_b32 s3, s2, 1
s_cmp_lt_u32 s2, 2
s_mov_b32 s2, s3
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB1_5
.LBB1_3:
s_mov_b32 s3, exec_lo
v_cmpx_gt_u32_e64 s2, v0
s_cbranch_execz .LBB1_2
v_add_nc_u32_e32 v2, s2, v0
s_delay_alu instid0(VALU_DEP_1)
v_lshl_add_u32 v2, v2, 2, 0
ds_load_b32 v2, v2
ds_load_b32 v3, v1
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v2, v2, v3
ds_store_b32 v1, v2
s_branch .LBB1_2
.LBB1_5:
s_mov_b32 s2, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB1_7
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 0
s_load_b64 s[0:1], s[0:1], 0x10
ds_load_b32 v0, v0
s_waitcnt lgkmcnt(0)
global_store_b32 v1, v0, s[0:1]
.LBB1_7:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9reducePI2IfEvPT_iS1_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 6
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.section .text._Z9reducePI2IfEvPT_iS1_,"axG",@progbits,_Z9reducePI2IfEvPT_iS1_,comdat
.Lfunc_end1:
.size _Z9reducePI2IfEvPT_iS1_, .Lfunc_end1-_Z9reducePI2IfEvPT_iS1_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .actual_access: write_only
.address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
- .offset: 136
.size: 4
.value_kind: hidden_dynamic_lds_size
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9reducePI1IfEvPT_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9reducePI1IfEvPT_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 11
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .actual_access: read_only
.address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .actual_access: write_only
.address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
- .offset: 144
.size: 4
.value_kind: hidden_dynamic_lds_size
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9reducePI2IfEvPT_iS1_
.private_segment_fixed_size: 0
.sgpr_count: 8
.sgpr_spill_count: 0
.symbol: _Z9reducePI2IfEvPT_iS1_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <iostream>
#include <time.h>
//#include <cutil_inline.h>
using namespace std;
//*****************************************//
//ÒÔÏÂÁ½²¿·Ö½«ÔÚÉ豸ÉϱàÒë ÓÉ__global__±êʶ£»
template<typename T> __global__ void reducePI1(T* __restrict__ d_sum, int num){
//__restrict__ ÊÇ˵´ÓÖ»¶Á»º´æÖжÁÈ¡¸ÃÊý¾Ý£¬»áÓÐʲôÓÅÊÆÄØ£¿
//printf("blockIdx.x is %d\n",blockIdx.x);//Ï߳̿éË÷Òý£¬0~grid-1
//printf("blockDim.x is %d\n",blockDim.x);//Ï߳̿é°üº¬µÄÏß³ÌÊý£¬ÕâÀï¾ÍÊÇ<<<grid,block,size>>>ÖеÄblock
//printf("threadIdx.x is %d\n",threadIdx.x);//ÿ¸öÏ߳̿éÖÐÏ̵߳ıêºÅ£¬0~block-1
int id = blockIdx.x*blockDim.x + threadIdx.x;//Ϊÿ¸öÏ̹߳¹½¨Î¨Ò»±êºÅ£¬0~grid*block-1
T temp;
T pSum = 0;
extern T __shared__ s_pi[];//Êý¾Ý´æ·ÅÔÚ¹²Ïí´æ´¢ÉÏ£¬Ö»Óб¾Ï߳̿éÄÚµÄÏ߳̿ÉÒÔ·ÃÎÊ
T rnum = 1.0/num;
for(int i=id;i<num;i +=blockDim.x*gridDim.x){
//ÿ¸öÏ̼߳ÆËãµÄ´ÎÊýÊÇ×ܵĴÎÊý£¨num£©³ýÒÔ×ܵÄÏß³ÌÊý£¨grid*block£©
temp = (i+0.5f)*rnum;
pSum += 4.0f/(1+temp*temp);
}
s_pi[threadIdx.x] = pSum*rnum;//ÿ¸öÏ߳̿éÖеÄÏ̻߳á°Ñ×Ô¼º¼ÆËãµÃµ½µÄs_pi¶ÀÁ¢´æ´¢ÔÚ±¾¿éµÄ¹²Ïí´æ´¢ÉÏ
__syncthreads();//µÈ´ý±¾¿éËùÓÐÏ̼߳ÆËãÍê±Ï
for(int i = (blockDim.x>>1);i >0;i >>= 1){
//½«±¾¿éÄÚµÄ ¼ÆËã½á¹û ½øÐÐÀÛ¼Ó
if (threadIdx.x<i){
s_pi[threadIdx.x] += s_pi[threadIdx.x+i];
}
__syncthreads();
}
//½«¼ÓºÍµÄ½á¹ûдµ½±¾¿é¶ÔÓ¦µÄÏÔ´æÖУ¬ÒÔ±¸reducePI2ʹÓÃ
if (threadIdx.x==0)
{
d_sum[blockIdx.x]=s_pi[0];
}
//ÏÂÃæÕâ¶Î´úÂëÓ¦¸ÃÊÇÔÚÖ´ÐÐÀàËƵÄËã·¨µ«Êǽá¹û»áÓкܴóÆ«²î£¬²¢Î´ÕÒµ½ÔÒò^_^
//if (warpSize>63){
// if (threadIdx.x<32){
// s_pi[threadIdx.x] += s_pi[threadIdx.x +32];
// }
//}
//if (threadIdx.x<16){
// s_pi[threadIdx.x] += s_pi[threadIdx.x +16];
//printf("threadIdx.x 16 is %d\n",threadIdx.x);
//}
//if (threadIdx.x<8){
// s_pi[threadIdx.x] += s_pi[threadIdx.x +8];
//printf("threadIdx.x 8 is %d\n",threadIdx.x);
//}
//if (threadIdx.x<4){
// s_pi[threadIdx.x] += s_pi[threadIdx.x +4];
//printf("threadIdx.x 4 is %d\n",threadIdx.x);
//}
//if (threadIdx.x<2){
// s_pi[threadIdx.x] += s_pi[threadIdx.x +2];
//printf("threadIdx.x 2 is %d\n",threadIdx.x);
//}
//if (threadIdx.x<1){
// d_sum[blockIdx.x] = s_pi[0]+s_pi[1];
//printf("threadIdx.x 1 is %d\n",threadIdx.x);
//}
}
template<typename T> __global__ void reducePI2(T* __restrict__ d_sum, int num, T* __restrict__ d_pi){
int id = threadIdx.x;//Õâ¸öº¯ÊýµÄÏ߳̿éÖ»ÓÐÒ»¸ö£¬Ïß³ÌÊýÊÇgrid£¬ÕâÀïÒÀÈ»ÓÃid×÷ΪË÷ÒýÃû
extern T __shared__ s_sum[];//Õâ¸öÊǹ²ÏíÄÚ´æÖеģ¬Ö»ÓпéÄڿɼû
s_sum[id]=d_sum[id];//°ÑÏÔ´æÖеÄÊý¾Ý×°ÔؽøÀ´
__syncthreads();//µÈ´ý×°ÔØÍê³É
for(int i = (blockDim.x>>1);i>0;i >>=1)
//ÈÔÈ»²ÉÓðë¶Ô°ëÕۺ͵ķ½·¨¶Ô±¾¿éÄÚËùÓÐÏß³ÌÖеÄs_sum½øÐÐÇóºÍ
{
if (id<i){
s_sum[id] += s_sum[id+i];
}
__syncthreads();//µÈ´ýÇóºÍÍê³É
}
//½«ÇóºÍ½á¹ûдÈëÏԴ棬ʹµÃcpuÖ÷»ú¶Ë¿É¼û
if(threadIdx.x==0)
{
*d_pi =s_sum[0];
}
//if (warpSize>63){
// if (threadIdx.x<32){
// s_sum[threadIdx.x] += s_sum[threadIdx.x +32];
// }
//}
//if (threadIdx.x<16){
// s_sum[threadIdx.x] += s_sum[threadIdx.x +16];
//}//
//if (threadIdx.x<8){
// s_sum[threadIdx.x] += s_sum[threadIdx.x +8];
//}
//if (threadIdx.x<4){
// s_sum[threadIdx.x] += s_sum[threadIdx.x +4];
//}
//if (threadIdx.x<2){
// s_sum[threadIdx.x] += s_sum[threadIdx.x +2];
//}
//if (threadIdx.x<1){
// *d_pi = s_sum[0]+s_sum[1];
//}
}
//**********************************************//
//ÒÔÏ´úÂëÔÚÖ÷»úÉϱàÒë
template <typename T> T reducePI(int num){
int grid = 1024;//ÓÃÀ´µ÷ÕûÏ߳̿éµÄÊýÁ¿
T *tmp;
hipMalloc((void**)&tmp,grid*sizeof(T));//ÔÚÉ豸´æ´¢Æ÷£¨ÏԴ棩ÉÏ¿ª±Ùgrid*sizeof(T)´óСµÄ¿Õ¼ä£¬Ö÷»úÉϵÄÖ¸ÕëtmpÖ¸Ïò¸Ã¿Õ¼ä
reducePI1<<<grid,256,256*sizeof(T)>>>(tmp,num);//µ÷ÓÃreducePI1
//²ÎÊý±íʾÓÐgrid¸öÏ߳̿飬ÿ¸öÏ߳̿éÓÐ256¸öỊ̈߳¬Ã¿¸öÏ߳̿éʹÓÃ256*size´óСµÄ¹²Ïí´æ´¢Æ÷£¨Ö»ÓпéÄÚ¿ÉÒÔ·ÃÎÊ£©
//Ö´ÐÐÖ®ºó£¬»áÔÚtmpΪÊ×µÄÏÔ´æÖд洢grid ¸öÖмä½á¹û
//printf("%d\n",__LINE__);//ÏÔʾ´úÂëËùÔÚÐкţ¬²»Öª»áÓÐʲôÓÃ
T *d_PI;
hipMalloc((void**)&d_PI,sizeof(T));//ÏÔ´æÖÐΪ¦ÐµÄ¼ÆËã½á¹û¿ª±Ù¿Õ¼ä
reducePI2<<<1,grid,grid*sizeof(T)>>>(tmp,grid,d_PI);//Ö»ÓÐÒ»¸öÏ߳̿飬ÓÐgrid¸öÏß³Ì
//Ö´ÐкóÔÚÏÔ´æÖÐd_PIµÄλÖôæ·Å×îºó½á¹û
T pi;//ÕâÊÇÔÚÖ÷»úÄÚ´æÉϵĿռä
hipMemcpy(&pi,d_PI,sizeof(T),hipMemcpyDeviceToHost);//´ÓÏÔ´æÖн«Êý¾Ý¿½±´³öÀ´
hipFree(tmp);//ÊÍ·ÅÏàÓ¦µÄÏÔ´æ¿Õ¼ä
hipFree(d_PI);
return pi;
}
template <typename T> T cpuPI(int num){
T sum = 0.0f;
T temp;
for (int i=0;i<num;i++)
{
temp =(i+0.5f)/num;
sum += 4/(1+temp*temp);
}
return sum/num;
}
int main(){
printf("test for compell \n");
clock_t start, finish;//ÓÃÀ´¼Æʱ
float costtime;
start = clock();
//************
printf("cpu pi is %f\n",cpuPI<float>(1000000));//µ÷ÓÃÆÕͨµÄ´®ÐÐÑ»·¼ÆËã ¦Ð
//*************
finish = clock();
costtime = (float)(finish - start) / CLOCKS_PER_SEC; //µ¥Î»ÊÇÃë
printf("costtime of CPU is %f\n",costtime);
start = clock();
//************
printf("gpu pi is %f\n",reducePI<float>(1000000));//µ÷ÓÃÖ÷»úÉϵIJ¢ÐмÆË㺯Êý
//************
finish = clock();
costtime = (float)(finish - start) / CLOCKS_PER_SEC;
printf("costtime of GPU is %f\n",costtime);
return 0;
} | .text
.file "computePIsave.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI0_0:
.long 0x3f000000 # float 0.5
.LCPI0_1:
.long 0x49742400 # float 1.0E+6
.LCPI0_2:
.long 0x3f800000 # float 1
.LCPI0_3:
.long 0x40800000 # float 4
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %rbp, -16
movl $.Lstr, %edi
callq puts@PLT
xorl %ebp, %ebp
callq clock
xorps %xmm6, %xmm6
movq %rax, %rbx
movss .LCPI0_0(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
movss .LCPI0_1(%rip), %xmm5 # xmm5 = mem[0],zero,zero,zero
movss .LCPI0_2(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
movss .LCPI0_3(%rip), %xmm2 # xmm2 = mem[0],zero,zero,zero
.p2align 4, 0x90
.LBB0_1: # =>This Inner Loop Header: Depth=1
xorps %xmm3, %xmm3
cvtsi2ss %ebp, %xmm3
addss %xmm0, %xmm3
divss %xmm5, %xmm3
mulss %xmm3, %xmm3
addss %xmm1, %xmm3
movaps %xmm2, %xmm4
divss %xmm3, %xmm4
addss %xmm4, %xmm6
incl %ebp
cmpl $1000000, %ebp # imm = 0xF4240
jne .LBB0_1
# %bb.2: # %_Z5cpuPIIfET_i.exit
divss %xmm5, %xmm6
xorps %xmm0, %xmm0
cvtss2sd %xmm6, %xmm0
movl $.L.str.1, %edi
movb $1, %al
callq printf
callq clock
subq %rbx, %rax
xorps %xmm0, %xmm0
cvtsi2ss %rax, %xmm0
divss .LCPI0_1(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movl $.L.str.2, %edi
movb $1, %al
callq printf
callq clock
movq %rax, %rbx
movl $1000000, %edi # imm = 0xF4240
callq _Z8reducePIIfET_i
cvtss2sd %xmm0, %xmm0
movl $.L.str.3, %edi
movb $1, %al
callq printf
callq clock
subq %rbx, %rax
xorps %xmm0, %xmm0
cvtsi2ss %rax, %xmm0
divss .LCPI0_1(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movl $.L.str.4, %edi
movb $1, %al
callq printf
xorl %eax, %eax
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.section .text._Z8reducePIIfET_i,"axG",@progbits,_Z8reducePIIfET_i,comdat
.weak _Z8reducePIIfET_i # -- Begin function _Z8reducePIIfET_i
.p2align 4, 0x90
.type _Z8reducePIIfET_i,@function
_Z8reducePIIfET_i: # @_Z8reducePIIfET_i
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $120, %rsp
.cfi_def_cfa_offset 144
.cfi_offset %rbx, -24
.cfi_offset %rbp, -16
movl %edi, %ebp
movabsq $4294968320, %rbx # imm = 0x100000400
leaq 16(%rsp), %rdi
movl $4096, %esi # imm = 0x1000
callq hipMalloc
leaq -768(%rbx), %rdx
movl $1024, %r8d # imm = 0x400
movq %rbx, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq 16(%rsp), %rax
movq %rax, 80(%rsp)
movl %ebp, 24(%rsp)
leaq 80(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 72(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z9reducePI1IfEvPT_i, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 80(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
leaq 8(%rsp), %rdi
movl $4, %esi
callq hipMalloc
leaq -1023(%rbx), %rdi
movl $4096, %r8d # imm = 0x1000
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq %rax, 80(%rsp)
movl $1024, 92(%rsp) # imm = 0x400
movq %rcx, 72(%rsp)
leaq 80(%rsp), %rax
movq %rax, 96(%rsp)
leaq 92(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z9reducePI2IfEvPT_iS1_, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
movq 8(%rsp), %rsi
leaq 96(%rsp), %rdi
movl $4, %edx
movl $2, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movss 96(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
addq $120, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z8reducePIIfET_i, .Lfunc_end1-_Z8reducePIIfET_i
.cfi_endproc
# -- End function
.section .text._Z24__device_stub__reducePI1IfEvPT_i,"axG",@progbits,_Z24__device_stub__reducePI1IfEvPT_i,comdat
.weak _Z24__device_stub__reducePI1IfEvPT_i # -- Begin function _Z24__device_stub__reducePI1IfEvPT_i
.p2align 4, 0x90
.type _Z24__device_stub__reducePI1IfEvPT_i,@function
_Z24__device_stub__reducePI1IfEvPT_i: # @_Z24__device_stub__reducePI1IfEvPT_i
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z9reducePI1IfEvPT_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end2:
.size _Z24__device_stub__reducePI1IfEvPT_i, .Lfunc_end2-_Z24__device_stub__reducePI1IfEvPT_i
.cfi_endproc
# -- End function
.section .text._Z24__device_stub__reducePI2IfEvPT_iS1_,"axG",@progbits,_Z24__device_stub__reducePI2IfEvPT_iS1_,comdat
.weak _Z24__device_stub__reducePI2IfEvPT_iS1_ # -- Begin function _Z24__device_stub__reducePI2IfEvPT_iS1_
.p2align 4, 0x90
.type _Z24__device_stub__reducePI2IfEvPT_iS1_,@function
_Z24__device_stub__reducePI2IfEvPT_iS1_: # @_Z24__device_stub__reducePI2IfEvPT_iS1_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movl %esi, 12(%rsp)
movq %rdx, 64(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9reducePI2IfEvPT_iS1_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end3:
.size _Z24__device_stub__reducePI2IfEvPT_iS1_, .Lfunc_end3-_Z24__device_stub__reducePI2IfEvPT_iS1_
.cfi_endproc
# -- End function
.text
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9reducePI1IfEvPT_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9reducePI2IfEvPT_iS1_, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "cpu pi is %f\n"
.size .L.str.1, 15
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "costtime of CPU is %f\n"
.size .L.str.2, 23
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "gpu pi is %f\n"
.size .L.str.3, 14
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "costtime of GPU is %f\n"
.size .L.str.4, 23
.type _Z9reducePI1IfEvPT_i,@object # @_Z9reducePI1IfEvPT_i
.section .rodata._Z9reducePI1IfEvPT_i,"aG",@progbits,_Z9reducePI1IfEvPT_i,comdat
.weak _Z9reducePI1IfEvPT_i
.p2align 3, 0x0
_Z9reducePI1IfEvPT_i:
.quad _Z24__device_stub__reducePI1IfEvPT_i
.size _Z9reducePI1IfEvPT_i, 8
.type _Z9reducePI2IfEvPT_iS1_,@object # @_Z9reducePI2IfEvPT_iS1_
.section .rodata._Z9reducePI2IfEvPT_iS1_,"aG",@progbits,_Z9reducePI2IfEvPT_iS1_,comdat
.weak _Z9reducePI2IfEvPT_iS1_
.p2align 3, 0x0
_Z9reducePI2IfEvPT_iS1_:
.quad _Z24__device_stub__reducePI2IfEvPT_iS1_
.size _Z9reducePI2IfEvPT_iS1_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z9reducePI1IfEvPT_i"
.size .L__unnamed_1, 21
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z9reducePI2IfEvPT_iS1_"
.size .L__unnamed_2, 24
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "test for compell "
.size .Lstr, 18
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__reducePI1IfEvPT_i
.addrsig_sym _Z24__device_stub__reducePI2IfEvPT_iS1_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9reducePI1IfEvPT_i
.addrsig_sym _Z9reducePI2IfEvPT_iS1_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0017a509_00000000-6_computePIsave.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL34__device_stub__Z9reducePI1IfEvPT_iPfi, @function
_ZL34__device_stub__Z9reducePI1IfEvPT_iPfi:
.LFB3700:
.cfi_startproc
subq $136, %rsp
.cfi_def_cfa_offset 144
movl %esi, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
movq %rdi, 24(%rsp)
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 12(%rsp), %rax
movq %rax, 104(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L5
.L1:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L6
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L5:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9reducePI1IfEvPT_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L1
.L6:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3700:
.size _ZL34__device_stub__Z9reducePI1IfEvPT_iPfi, .-_ZL34__device_stub__Z9reducePI1IfEvPT_iPfi
.section .text._Z9reducePI1IfEvPT_i,"axG",@progbits,_Z9reducePI1IfEvPT_i,comdat
.weak _Z9reducePI1IfEvPT_i
.type _Z9reducePI1IfEvPT_i, @function
_Z9reducePI1IfEvPT_i:
.LFB4007:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _ZL34__device_stub__Z9reducePI1IfEvPT_iPfi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4007:
.size _Z9reducePI1IfEvPT_i, .-_Z9reducePI1IfEvPT_i
.text
.type _ZL37__device_stub__Z9reducePI2IfEvPT_iS1_PfiS_, @function
_ZL37__device_stub__Z9reducePI2IfEvPT_iS1_PfiS_:
.LFB3702:
.cfi_startproc
subq $136, %rsp
.cfi_def_cfa_offset 144
movl %esi, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
movq %rdi, 16(%rsp)
leaq 16(%rsp), %rax
movq %rax, 96(%rsp)
leaq 12(%rsp), %rax
movq %rax, 104(%rsp)
movq %rdx, 24(%rsp)
leaq 24(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L13
.L9:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L14
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L13:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9reducePI2IfEvPT_iS1_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L9
.L14:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3702:
.size _ZL37__device_stub__Z9reducePI2IfEvPT_iS1_PfiS_, .-_ZL37__device_stub__Z9reducePI2IfEvPT_iS1_PfiS_
.section .text._Z9reducePI2IfEvPT_iS1_,"axG",@progbits,_Z9reducePI2IfEvPT_iS1_,comdat
.weak _Z9reducePI2IfEvPT_iS1_
.type _Z9reducePI2IfEvPT_iS1_, @function
_Z9reducePI2IfEvPT_iS1_:
.LFB4009:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _ZL37__device_stub__Z9reducePI2IfEvPT_iS1_PfiS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4009:
.size _Z9reducePI2IfEvPT_iS1_, .-_Z9reducePI2IfEvPT_iS1_
.text
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3678:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3678:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z9reducePI2IfEvPT_iS1_"
.LC1:
.string "_Z9reducePI1IfEvPT_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3705:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z9reducePI2IfEvPT_iS1_(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z9reducePI1IfEvPT_i(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3705:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .text._Z8reducePIIfET_i,"axG",@progbits,_Z8reducePIIfET_i,comdat
.weak _Z8reducePIIfET_i
.type _Z8reducePIIfET_i, @function
_Z8reducePIIfET_i:
.LFB4006:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $48, %rsp
.cfi_def_cfa_offset 64
movl %edi, %ebx
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movq %rsp, %rdi
movl $4096, %esi
call cudaMalloc@PLT
movl $256, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1024, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movl $1024, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L26
.L22:
leaq 8(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
movl $1024, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movl $4096, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L27
.L23:
leaq 28(%rsp), %rdi
movl $2, %ecx
movl $4, %edx
movq 8(%rsp), %rsi
call cudaMemcpy@PLT
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movss 28(%rsp), %xmm0
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L28
addq $48, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L26:
.cfi_restore_state
movl %ebx, %esi
movq (%rsp), %rdi
call _ZL34__device_stub__Z9reducePI1IfEvPT_iPfi
jmp .L22
.L27:
movq 8(%rsp), %rdx
movl $1024, %esi
movq (%rsp), %rdi
call _ZL37__device_stub__Z9reducePI2IfEvPT_iS1_PfiS_
jmp .L23
.L28:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4006:
.size _Z8reducePIIfET_i, .-_Z8reducePIIfET_i
.section .rodata.str1.1
.LC3:
.string "test for compell \n"
.LC8:
.string "cpu pi is %f\n"
.LC9:
.string "costtime of CPU is %f\n"
.LC10:
.string "gpu pi is %f\n"
.LC11:
.string "costtime of GPU is %f\n"
.text
.globl main
.type main, @function
main:
.LFB3675:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
call clock@PLT
movq %rax, %rbx
pxor %xmm0, %xmm0
movl $0, %eax
movss .LC4(%rip), %xmm6
movss .LC5(%rip), %xmm5
movss .LC6(%rip), %xmm4
movss .LC7(%rip), %xmm3
.L30:
pxor %xmm1, %xmm1
cvtsi2ssl %eax, %xmm1
addss %xmm6, %xmm1
divss %xmm5, %xmm1
mulss %xmm1, %xmm1
addss %xmm4, %xmm1
movaps %xmm3, %xmm2
divss %xmm1, %xmm2
addss %xmm2, %xmm0
addl $1, %eax
cmpl $1000000, %eax
jne .L30
divss .LC5(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
call clock@PLT
subq %rbx, %rax
pxor %xmm0, %xmm0
cvtsi2ssq %rax, %xmm0
divss .LC5(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
call clock@PLT
movq %rax, %rbx
movl $1000000, %edi
call _Z8reducePIIfET_i
cvtss2sd %xmm0, %xmm0
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
call clock@PLT
subq %rbx, %rax
pxor %xmm0, %xmm0
cvtsi2ssq %rax, %xmm0
divss .LC5(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl $0, %eax
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3675:
.size main, .-main
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC4:
.long 1056964608
.align 4
.LC5:
.long 1232348160
.align 4
.LC6:
.long 1065353216
.align 4
.LC7:
.long 1082130432
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "computePIsave.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI0_0:
.long 0x3f000000 # float 0.5
.LCPI0_1:
.long 0x49742400 # float 1.0E+6
.LCPI0_2:
.long 0x3f800000 # float 1
.LCPI0_3:
.long 0x40800000 # float 4
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %rbp, -16
movl $.Lstr, %edi
callq puts@PLT
xorl %ebp, %ebp
callq clock
xorps %xmm6, %xmm6
movq %rax, %rbx
movss .LCPI0_0(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
movss .LCPI0_1(%rip), %xmm5 # xmm5 = mem[0],zero,zero,zero
movss .LCPI0_2(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
movss .LCPI0_3(%rip), %xmm2 # xmm2 = mem[0],zero,zero,zero
.p2align 4, 0x90
.LBB0_1: # =>This Inner Loop Header: Depth=1
xorps %xmm3, %xmm3
cvtsi2ss %ebp, %xmm3
addss %xmm0, %xmm3
divss %xmm5, %xmm3
mulss %xmm3, %xmm3
addss %xmm1, %xmm3
movaps %xmm2, %xmm4
divss %xmm3, %xmm4
addss %xmm4, %xmm6
incl %ebp
cmpl $1000000, %ebp # imm = 0xF4240
jne .LBB0_1
# %bb.2: # %_Z5cpuPIIfET_i.exit
divss %xmm5, %xmm6
xorps %xmm0, %xmm0
cvtss2sd %xmm6, %xmm0
movl $.L.str.1, %edi
movb $1, %al
callq printf
callq clock
subq %rbx, %rax
xorps %xmm0, %xmm0
cvtsi2ss %rax, %xmm0
divss .LCPI0_1(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movl $.L.str.2, %edi
movb $1, %al
callq printf
callq clock
movq %rax, %rbx
movl $1000000, %edi # imm = 0xF4240
callq _Z8reducePIIfET_i
cvtss2sd %xmm0, %xmm0
movl $.L.str.3, %edi
movb $1, %al
callq printf
callq clock
subq %rbx, %rax
xorps %xmm0, %xmm0
cvtsi2ss %rax, %xmm0
divss .LCPI0_1(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movl $.L.str.4, %edi
movb $1, %al
callq printf
xorl %eax, %eax
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.section .text._Z8reducePIIfET_i,"axG",@progbits,_Z8reducePIIfET_i,comdat
.weak _Z8reducePIIfET_i # -- Begin function _Z8reducePIIfET_i
.p2align 4, 0x90
.type _Z8reducePIIfET_i,@function
_Z8reducePIIfET_i: # @_Z8reducePIIfET_i
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $120, %rsp
.cfi_def_cfa_offset 144
.cfi_offset %rbx, -24
.cfi_offset %rbp, -16
movl %edi, %ebp
movabsq $4294968320, %rbx # imm = 0x100000400
leaq 16(%rsp), %rdi
movl $4096, %esi # imm = 0x1000
callq hipMalloc
leaq -768(%rbx), %rdx
movl $1024, %r8d # imm = 0x400
movq %rbx, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq 16(%rsp), %rax
movq %rax, 80(%rsp)
movl %ebp, 24(%rsp)
leaq 80(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 72(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z9reducePI1IfEvPT_i, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 80(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
leaq 8(%rsp), %rdi
movl $4, %esi
callq hipMalloc
leaq -1023(%rbx), %rdi
movl $4096, %r8d # imm = 0x1000
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq %rax, 80(%rsp)
movl $1024, 92(%rsp) # imm = 0x400
movq %rcx, 72(%rsp)
leaq 80(%rsp), %rax
movq %rax, 96(%rsp)
leaq 92(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z9reducePI2IfEvPT_iS1_, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
movq 8(%rsp), %rsi
leaq 96(%rsp), %rdi
movl $4, %edx
movl $2, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movss 96(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
addq $120, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z8reducePIIfET_i, .Lfunc_end1-_Z8reducePIIfET_i
.cfi_endproc
# -- End function
.section .text._Z24__device_stub__reducePI1IfEvPT_i,"axG",@progbits,_Z24__device_stub__reducePI1IfEvPT_i,comdat
.weak _Z24__device_stub__reducePI1IfEvPT_i # -- Begin function _Z24__device_stub__reducePI1IfEvPT_i
.p2align 4, 0x90
.type _Z24__device_stub__reducePI1IfEvPT_i,@function
_Z24__device_stub__reducePI1IfEvPT_i: # @_Z24__device_stub__reducePI1IfEvPT_i
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z9reducePI1IfEvPT_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end2:
.size _Z24__device_stub__reducePI1IfEvPT_i, .Lfunc_end2-_Z24__device_stub__reducePI1IfEvPT_i
.cfi_endproc
# -- End function
.section .text._Z24__device_stub__reducePI2IfEvPT_iS1_,"axG",@progbits,_Z24__device_stub__reducePI2IfEvPT_iS1_,comdat
.weak _Z24__device_stub__reducePI2IfEvPT_iS1_ # -- Begin function _Z24__device_stub__reducePI2IfEvPT_iS1_
.p2align 4, 0x90
.type _Z24__device_stub__reducePI2IfEvPT_iS1_,@function
_Z24__device_stub__reducePI2IfEvPT_iS1_: # @_Z24__device_stub__reducePI2IfEvPT_iS1_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movl %esi, 12(%rsp)
movq %rdx, 64(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9reducePI2IfEvPT_iS1_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end3:
.size _Z24__device_stub__reducePI2IfEvPT_iS1_, .Lfunc_end3-_Z24__device_stub__reducePI2IfEvPT_iS1_
.cfi_endproc
# -- End function
.text
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9reducePI1IfEvPT_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9reducePI2IfEvPT_iS1_, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "cpu pi is %f\n"
.size .L.str.1, 15
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "costtime of CPU is %f\n"
.size .L.str.2, 23
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "gpu pi is %f\n"
.size .L.str.3, 14
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "costtime of GPU is %f\n"
.size .L.str.4, 23
.type _Z9reducePI1IfEvPT_i,@object # @_Z9reducePI1IfEvPT_i
.section .rodata._Z9reducePI1IfEvPT_i,"aG",@progbits,_Z9reducePI1IfEvPT_i,comdat
.weak _Z9reducePI1IfEvPT_i
.p2align 3, 0x0
_Z9reducePI1IfEvPT_i:
.quad _Z24__device_stub__reducePI1IfEvPT_i
.size _Z9reducePI1IfEvPT_i, 8
.type _Z9reducePI2IfEvPT_iS1_,@object # @_Z9reducePI2IfEvPT_iS1_
.section .rodata._Z9reducePI2IfEvPT_iS1_,"aG",@progbits,_Z9reducePI2IfEvPT_iS1_,comdat
.weak _Z9reducePI2IfEvPT_iS1_
.p2align 3, 0x0
_Z9reducePI2IfEvPT_iS1_:
.quad _Z24__device_stub__reducePI2IfEvPT_iS1_
.size _Z9reducePI2IfEvPT_iS1_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z9reducePI1IfEvPT_i"
.size .L__unnamed_1, 21
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z9reducePI2IfEvPT_iS1_"
.size .L__unnamed_2, 24
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "test for compell "
.size .Lstr, 18
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__reducePI1IfEvPT_i
.addrsig_sym _Z24__device_stub__reducePI2IfEvPT_iS1_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9reducePI1IfEvPT_i
.addrsig_sym _Z9reducePI2IfEvPT_iS1_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
//#define DEBUGPRINT 0
__global__ void InviscidBC_gpu_kernel1(int *lglel, double *fatface,char *cbc, double *xm1,double *ym1,double *zm1,double *vx,double *vy,double *vz,double *t,double *pr,double *sii,double *siii,double *vdiff,double *vtrans,char *cb,double *u,double *phig,double *csound,double *unx,double *uny,double *unz,double molarmass,int iwm,int iwp,int irho,int iux,int iuy,int iuz,int iph,int ipr,int isnd,int ithm,int icpf,int icvf,int iu1,int iu2,int iu3,int iu4,int iu5,int lx1,int lz1,int lxz,int ldim,int lxz2ldim,int nxyz,int lxy,int lxz2ldimlelt,int ntot,int toteq,int e_offset,int p0th,int ifield,int ltot,int icv,int icp,int imu,int ilam,double molmass,int nlel,int npscal,int if3d,int ly1,int outflsub,double pinfty, int lelt){
int id = blockIdx.x*blockDim.x+threadIdx.x;
if(id<ntot){
int i1 = id % lx1;
int i2 = (id/lx1)%lz1;
int iface= ((id/lxz)%(2*ldim));
int e = id/lxz2ldim;
char cb1 = cbc[(ifield)*lelt*18+e*18+iface*3]; //corrected by Kk 02/07/2019 by adding ifield*lelt*18 and iface*3, ifield=1 no need to -1 since in cpu, cbc starting from 0 in the ifield entry
char cb2 = cbc[(ifield)*lelt*18+e*18+iface*3+1];
char cb3 = cbc[(ifield)*lelt*18+e*18+iface*3+2];
if(cb1 =='v'|| cb1=='V'){
int ieg=lglel[e];
int iy,iz,ix,l;
if(iface==0){
iy=0;
iz=i2;
ix=i1;
l=lx1*iz+ix;
}
else if(iface==3){
ix=0;
iz=i2;
iy=i1;
l=ly1*iz+iy;
}
else if(iface==4){
iz=0;
iy=i2;
ix=i1;
l=lx1*iy+ix;
}
else if(iface==1){
ix=lx1-1;
iz=i2;
iy=i1;
l=ly1*iz+iy;
}
else if(iface==2){
iy=ly1-1;
iz=i2;
ix=i1;
l=lx1*iz+ix;
}
else if(iface==5){
iz=lz1-1;
iy=i2;
ix=i1;
l=lx1*iy+ix;
}
//nekasgn
double x = xm1[e*nxyz+iz*lxy+iy*lx1+ix];
double y = ym1[e*nxyz+iz*lxy+iy*lx1+ix];
double z = zm1[e*nxyz+iz*lxy+iy*lx1+ix];
double r = x*x+y*y;
double theta=0.0;
if (r>0.0){ r = sqrtf(r);}
if ( x != 0.0 || y!= 0.0){theta = atan2(y,x); }
double ux= vx[e*nxyz+iz*lxy+iy*lx1+ix];
double uy= vy[e*nxyz+iz*lxy+iy*lx1+ix];
double uz= vz[e*nxyz+iz*lxy+iy*lx1+ix];
double temp = t [ e*nxyz+iz*lxy+iy*lx1+ix];
int ips;
double pa = pr [e*nxyz+iz*lxy+iy*lx1+ix];
double p0= p0th;
double si2 = sii[e*nxyz+iz*lxy+iy*lx1+ix];
double si3 = siii[e*nxyz+iz*lxy+iy*lx1+ix];
double udiff = vdiff[(ifield-1)*nlel+e*nxyz+iz*lxy+iy*lx1+ix];
double utrans = vtrans[(ifield-1)*nlel+e*nxyz+iz*lxy+iy*lx1+ix];
char cbu1 = cb[0];
char cbu2 = cb[1];
char cbu3 = cb[2];
//cmtasgn
double phi = phig[e*nxyz+iz*lxy+iy*lx1+ix];
double rho = vtrans[(irho-1)*nlel +e*nxyz+iz*lxy+iy*lx1+ix];
double pres = pr[e*nxyz+iz*lxy+iy*lx1+ix];
double cv=0.0,cp=0.0;
if(rho!=0){
cv=vtrans[(icv-1)*nlel +e*nxyz+iz*lxy+iy*lx1+ix]/rho;
cp=vtrans[(icp-1)*nlel +e*nxyz+iz*lxy+iy*lx1+ix]/rho;
}
double asnd = csound [e*nxyz+iz*lxy+iy*lx1+ix];
double mu = vdiff[(imu-1)*nlel+e*nxyz+iz*lxy+iy*lx1+ix];
udiff = vdiff[(imu-1)*nlel+e*nxyz+iz*lxy+iy*lx1+ix];// this overrides the udiff in nekasgn (line 63 in this function). Need to check withDr.Tania
double lambda = vdiff[(ilam-1)*nlel+e*nxyz+iz*lxy+iy*lx1+ix];
// userbc
double molarmass = molmass;
fatface[(iwp-1)+(irho-1)*lxz2ldimlelt+e*lxz2ldim+(iface)*lxz+l ] = rho;
fatface[(iwp-1)+(iux-1)*lxz2ldimlelt+e*lxz2ldim+(iface)*lxz+l ] = ux;
fatface[(iwp-1)+(iuy-1)*lxz2ldimlelt+e*lxz2ldim+(iface)*lxz+l ] = uy;
fatface[(iwp-1)+(iuz-1)*lxz2ldimlelt+e*lxz2ldim+(iface)*lxz+l ] = uz;
fatface[(iwp-1)+(iph-1)*lxz2ldimlelt+e*lxz2ldim+(iface)*lxz+l ] = phi;
double rhob = rho*phi;
double rhoub = rhob*ux;
double rhovb = rhob*uy;
double rhowb = rhob*uz;
fatface[(iwp-1)+(iu1-1)*lxz2ldimlelt+e*lxz2ldim+(iface)*lxz+l ] = rhob;
fatface[(iwp-1)+(iu2-1)*lxz2ldimlelt+e*lxz2ldim+(iface)*lxz+l ] = rhoub;
fatface[(iwp-1)+(iu3-1)*lxz2ldimlelt+e*lxz2ldim+(iface)*lxz+l ] = rhovb;
fatface[(iwp-1)+(iu4-1)*lxz2ldimlelt+e*lxz2ldim+(iface)*lxz+l ] = rhowb;
double mach=0;
double snz=0;
if(if3d){
mach = sqrtf(ux*ux+uy*uy+uz*uz)/asnd;
snz = unz[e*6*lx1*lz1+(iface)*lxz+l];
}
else{
mach = sqrt(ux*ux+uy*uy+uz*uz)/asnd;
snz=0;
}
double snx = unx[e*6*lx1*lz1+(iface)*lxz+l];
double sny = uny[e*6*lx1*lz1+(iface)*lxz+l];
if (mach<1.0){
pres = fatface[(iwm-1)+(ipr-1)*lxz2ldimlelt+e*lxz2ldim+(iface)*lxz+l ];
temp = pres/rho/(cp-cv);// ! definitely too perfect!
fatface[(iwp-1)+(ipr-1)*lxz2ldimlelt+e*lxz2ldim+(iface)*lxz+l ] = pres;
fatface[(iwp-1)+(isnd-1)*lxz2ldimlelt+e*lxz2ldim+(iface)*lxz+l ] = sqrt(cp/cv*pres/rho);//check the operator precedence is same as fortran . check with Dr.Tania. adeesha
fatface[(iwp-1)+(ithm-1)*lxz2ldimlelt+e*lxz2ldim+(iface)*lxz+l ] = temp ;// ! definitely too perfect!
fatface[(iwp-1)+(icpf-1)*lxz2ldimlelt+e*lxz2ldim+(iface)*lxz+l ] = rho*cp ;//! NEED EOS WITH TEMP Dirichlet, userbc
fatface[(iwp-1)+(icvf-1)*lxz2ldimlelt+e*lxz2ldim+(iface)*lxz+l ] = rho*cv ;//! NEED EOS WITH TEMP Dirichlet, userbc
}
else{ //supersonic inflow
fatface[(iwp-1)+(ipr-1)*lxz2ldimlelt+e*lxz2ldim+(iface)*lxz+l ] = pres;
fatface[(iwp-1)+(isnd-1)*lxz2ldimlelt+e*lxz2ldim+(iface)*lxz+l ] =asnd;
fatface[(iwp-1)+(ithm-1)*lxz2ldimlelt+e*lxz2ldim+(iface)*lxz+l ] = temp ;// ! definitely too perfect!
fatface[(iwp-1)+(icpf-1)*lxz2ldimlelt+e*lxz2ldim+(iface)*lxz+l ] = rho*cp ;//! NEED EOS WITH TEMP Dirichlet, userbc
fatface[(iwp-1)+(icvf-1)*lxz2ldimlelt+e*lxz2ldim+(iface)*lxz+l ] = rho*cv ;//! NEED EOS WITH TEMP Dirichlet, userbc
}
fatface[(iwp-1)+(iu5-1)*lxz2ldimlelt+e*lxz2ldim+(iface)*lxz+l ] = phi*rho*cv*temp+0.5/rhob*(rhoub*rhoub+rhovb*rhovb+rhowb*rhowb);
}
}
}
__global__ void InviscidBC_gpu_kernel2(int *lglel, double *fatface,char *cbc, double *xm1,double *ym1,double *zm1,double *vx,double *vy,double *vz,double *t,double *pr,double *sii,double *siii,double *vdiff,double *vtrans,char *cb,double *u,double *phig,double *csound,double *unx,double *uny,double *unz,double molarmass,int iwm,int iwp,int irho,int iux,int iuy,int iuz,int iph,int ipr,int isnd,int ithm,int icpf,int icvf,int iu1,int iu2,int iu3,int iu4,int iu5,int lx1,int lz1,int lxz,int ldim,int lxz2ldim,int nxyz,int lxy,int lxz2ldimlelt,int ntot,int toteq,int e_offset,int p0th,int ifield,int ltot,int icv,int icp,int imu,int ilam,double molmass,int nlel,int npscal,int if3d,int ly1,int outflsub,double pinfty,double *fatfaceiwp, int lelt){
int id = blockIdx.x*blockDim.x+threadIdx.x;
if(id<ntot){
int i1 = id % lx1;
int i2 = (id/lx1)%lz1;
int iface= ((id/lxz)%(2*ldim));
int e = id/lxz2ldim;
char cb1 = cbc[(ifield)*lelt*18+e*18+iface*3];//corrected by Kk 02/07/2019 by adding ifield*lelt*18 and iface*3
char cb2 = cbc[(ifield)*lelt*18+e*18+iface*3+1];
char cb3 = cbc[(ifield)*lelt*18+e*18+iface*3+2];
/*if(id==10){
for(int i=0;i<576;i++){
printf("cbc values cbc[%d]=%c \n",i,cbc[i+ifield*lelt*18]);
}
printf("debugggggg iface id %d %d\n", iface, id);
}*/
//if(id ==0) printf("debug ifield %d \n", ifield);
//printf("cb1 =%c \n",cb1);
if(cb1 =='O'){
int ieg=lglel[e];
int iy,iz,ix,l;
if(iface==0){
iy=0;
iz=i2;
ix=i1;
l=lx1*iz+ix;
}
else if(iface==3){
ix=0;
iz=i2;
iy=i1;
l=ly1*iz+iy;
}
else if(iface==4){
iz=0;
iy=i2;
ix=i1;
l=lx1*iy+ix;
}
else if(iface==1){
ix=lx1-1;
iz=i2;
iy=i1;
l=ly1*iz+iy;
}
else if(iface==2){
iy=ly1-1;
iz=i2;
ix=i1;
l=lx1*iz+ix;
}
else if(iface==5){
iz=lz1-1;
iy=i2;
ix=i1;
l=lx1*iy+ix;
}
//nekasgn
double x = xm1[e*nxyz+iz*lxy+iy*lx1+ix];
double y = ym1[e*nxyz+iz*lxy+iy*lx1+ix];
double z = zm1[e*nxyz+iz*lxy+iy*lx1+ix];
// double r = x*x+y*y;
// double theta=0.0;
// if (r>0.0){ r = sqrtf(r);}
// if ( x != 0.0 || y!= 0.0){theta = atan2(y,x); }
// double ux= vx[e*nxyz+iz*lxy+iy*lx1+ix];
// double uy= vy[e*nxyz+iz*lxy+iy*lx1+ix];
// double uz= vz[e*nxyz+iz*lxy+iy*lx1+ix];
// double temp = t [ e*nxyz+iz*lxy+iy*lx1+ix];
// double p0= p0th;
//cmtasgn
double phi = phig[e*nxyz+iz*lxy+iy*lx1+ix];
double rho = vtrans[(irho-1)*nlel +e*nxyz+iz*lxy+iy*lx1+ix];
double pres = pr[e*nxyz+iz*lxy+iy*lx1+ix];
double cv=0.0,cp=0.0;
// userbc
double molarmass = molmass;
double sxn = unx[e*6*lxz+(iface)*lxz+l];
double syn = uny[e*6*lxz+(iface)*lxz+l];
double szn = unz[e*6*lxz+(iface)*lxz+l];
double rhou = fatface[(iwm-1)+(iu2-1)*lxz2ldimlelt+e*lxz2ldim+(iface)*lxz+l ]/phi;
double rhov = fatface[(iwm-1)+(iu3-1)*lxz2ldimlelt+e*lxz2ldim+(iface)*lxz+l ]/phi;
double rhow = fatface[(iwm-1)+(iu4-1)*lxz2ldimlelt+e*lxz2ldim+(iface)*lxz+l ]/phi;
double rhoe = fatface[(iwm-1)+(iu5-1)*lxz2ldimlelt+e*lxz2ldim+(iface)*lxz+l ]/phi;
double pl = fatface[(iwm-1)+(ipr-1)*lxz2ldimlelt+e*lxz2ldim+(iface)*lxz+l ]/phi;
fatfaceiwp[(icpf-1)*lxz2ldimlelt+e*lxz2ldim+(iface)*lxz+l ]= fatface[(iwm-1)+(icpf-1)*lxz2ldimlelt+e*lxz2ldim+(iface)*lxz+l];
fatfaceiwp[(icvf-1)*lxz2ldimlelt+e*lxz2ldim+(iface)*lxz+l ]= fatface[(iwm-1)+(icvf-1)*lxz2ldimlelt+e*lxz2ldim+(iface)*lxz+l];
cp=fatface[(iwm-1)+(icpf-1)*lxz2ldimlelt+e*lxz2ldim+(iface)*lxz+l]/rho;
cv = fatface[(iwm-1)+(icvf-1)*lxz2ldimlelt+e*lxz2ldim+(iface)*lxz+l]/rho;
int idbc=0;
if(outflsub){
pres=pinfty;
idbc=1;
}
else{
pres=fatface[(iwm-1)+(ipr-1)*lxz2ldimlelt+e*lxz2ldim+(iface)*lxz+l];
idbc=0;
}
//BcondOutflowPerf function
double rgas = 8314.3/molarmass;
double gamma = cp/(cp - rgas);
double gam1 = gamma-1;
double u = rhou/rho;
double v = rhov/rho;
double w = rhow/rho;
double csound= sqrtf(gamma*pl/rho);
double mach = sqrtf(u*u+v*v+w*w)/csound;
double rhob,rhoub,rhovb,rhowb,rhoeb;
//subsonic flow
if(mach<1 && idbc==1 || idbc==0){ // check the precendence of and and or in fortran check with Dr.Tania adeesha
double rrhoc = 1.0 / (rho*csound);
double deltp = pl - pres;
rhob = rho - deltp/(csound*csound);
double ub = u+sxn*deltp*rrhoc;
double vb = v+syn*deltp*rrhoc;
double wb = w+szn*deltp*rrhoc;
double vnd = ub*sxn + vb*syn + wb*szn;
if(vnd<0.0){
ub = copysignf(1.0,u)*fmax(fabs(ub),fabs(u));
vb = copysignf(1.0,v)*fmax(fabs(vb),fabs(v));
wb = copysignf(1.0,w)*fmax(fabs(wb),fabs(w));
}
rhoub = rhob*ub;
rhovb = rhob*vb;
rhowb = rhob*wb;
rhoeb = rhob*( pres/(rhob*(gamma - 1.0)) + 0.5*(ub*ub +vb*vb + wb*wb));
}
else{
rhob= rho;
rhoub = rhou;
rhovb = rhov;
rhowb =rhow;
rhoeb = rhoe;
}
// printf("inviscid iu1 %d iu2 %d iu3 %d iu4 %d iu5 %d iph %d ipr %d e %d lxz2ldimlelt %d iface %d lxz2ldim %d rhob %lf phi %lf rhoub %lf rhovb %lf rhowb %lf rhoeb %lf pres %lf l= %d \n",iu1,iu2,iu3,iu4,iu5,iph,ipr,e,lxz2ldimlelt,iface,lxz2ldim,rhob,phi,rhoub,rhovb,rhowb,rhoeb,pres,l);
fatfaceiwp[(irho-1)*lxz2ldimlelt+e*lxz2ldim+(iface)*lxz+l ] = rhob;
fatfaceiwp[(iux-1)*lxz2ldimlelt+e*lxz2ldim+(iface)*lxz+l ] = rhoub/rhob;
fatfaceiwp[(iuy-1)*lxz2ldimlelt+e*lxz2ldim+(iface)*lxz+l ] = rhovb/rhob;
fatfaceiwp[(iuz-1)*lxz2ldimlelt+e*lxz2ldim+(iface)*lxz+l ] = rhowb/rhob;
fatfaceiwp[(ithm-1)*lxz2ldimlelt+e*lxz2ldim+(iface)*lxz+l ] = (rhoeb-0.5*(rhoub*rhoub+rhovb*rhovb+rhowb*rhowb)/rhob)/cv;
fatfaceiwp[(iu1-1)*lxz2ldimlelt+e*lxz2ldim+(iface)*lxz+l ] = rhob*phi;
fatfaceiwp[(iu2-1)*lxz2ldimlelt+e*lxz2ldim+(iface)*lxz+l ] = rhoub*phi;
fatfaceiwp[(iu3-1)*lxz2ldimlelt+e*lxz2ldim+(iface)*lxz+l ] = rhovb*phi;
fatfaceiwp[(iu4-1)*lxz2ldimlelt+e*lxz2ldim+(iface)*lxz+l ] = rhowb*phi;
fatfaceiwp[(iu5-1)*lxz2ldimlelt+e*lxz2ldim+(iface)*lxz+l ] = rhoeb*phi;
fatfaceiwp[(iph-1)*lxz2ldimlelt+e*lxz2ldim+(iface)*lxz+l ] = phi;
fatfaceiwp[(ipr-1)*lxz2ldimlelt+e*lxz2ldim+(iface)*lxz+l ] = pres;
fatfaceiwp[(isnd-1)*lxz2ldimlelt+e*lxz2ldim+(iface)*lxz+l ] = sqrtf(cp/cv*pres/rho);
}
}
}
__global__ void InviscidBC_gpu_kernel3(int *lglel, double *fatface,char *cbc, double *xm1,double *ym1,double *zm1,double *vx,double *vy,double *vz,double *t,double *pr,double *sii,double *siii,double *vdiff,double *vtrans,char *cb,double *u,double *phig,double *csound,double *unx,double *uny,double *unz,double molarmass,int iwm,int iwp,int irho,int iux,int iuy,int iuz,int iph,int ipr,int isnd,int ithm,int icpf,int icvf,int iu1,int iu2,int iu3,int iu4,int iu5,int lx1,int lz1,int lxz,int ldim,int lxz2ldim,int nxyz,int lxy,int lxz2ldimlelt,int ntot,int toteq,int e_offset,int p0th,int ifield,int ltot,int icv,int icp,int imu,int ilam,double molmass,int nlel,int npscal,int if3d,int ly1,int outflsub,double pinfty, int lelt){
int id = blockIdx.x*blockDim.x+threadIdx.x;
if(id<ntot){
int i1 = id % lx1;
int l = id % lxz; //added by Kk 02/07/19
int i2 = (id/lx1)%lz1;
int iface= ((id/lxz)%(2*ldim));
int e = id/lxz2ldim;
char cb1 = cbc[(ifield)*lelt*18+e*18+iface*3];//corrected by Kk 02/07/2019 by adding ifield*lelt*18 and iface*3
char cb2 = cbc[(ifield)*lelt*18+e*18+iface*3+1];
char cb3 = cbc[(ifield)*lelt*18+e*18+iface*3+2];
if(cb1 =='W'|| cb1=='I' || (cb1=='S' && cb2=='Y' && cb3=='M')){
int ieg=lglel[e];
/* following 4 line is commented out by Kk 02/07/2019 since subroutine facind is not used in CPU part
int iy=0;
int iz=i2;
int ix=i1;
int l=lx1*iz+ix;*/ // this is the parallelized version of l = l+1 in every thread. Check with Dr.Tania . adeesha
// ************************ e*lxz2ldim+(f-1)*lx1*lz1+l is same as id. change this later. ******
//printf("debug inviscidBc: lxz2ldimlelt %d, lxz2ldim %d, iface %d, l %d, fatface %.30lf , id %d, e %d, index1 %d, index2 %d\n", lxz2ldimlelt, lxz2ldim, iface, l, fatface[(iwm-1)+(irho-1)*lxz2ldimlelt+e*lxz2ldim+(iface)*lxz+l], id, e, (iwm-1)+(irho-1)*lxz2ldimlelt+e*lxz2ldim+(iface)*lxz+l, (irho-1)*lxz2ldimlelt+e*lxz2ldim+(iface)*lxz+l);
double nx = unx[e*lxz2ldim+(iface)*lxz+l];
double ny = uny[e*lxz2ldim+(iface)*lxz+l];
double nz = unz[e*lxz2ldim+(iface)*lxz+l];
double rl = fatface[(iwm-1)+(irho-1)*lxz2ldimlelt+e*lxz2ldim+(iface)*lxz+l];
double rr=rl;
double ul = fatface[(iwm-1)+(iux-1)*lxz2ldimlelt+e*lxz2ldim+(iface)*lxz+l];
double vl = fatface[(iwm-1)+(iuy-1)*lxz2ldimlelt+e*lxz2ldim+(iface)*lxz+l];
double wl = fatface[(iwm-1)+(iuz-1)*lxz2ldimlelt+e*lxz2ldim+(iface)*lxz+l];
double fs=0.0;
double udotn = ul*nx+vl*ny+wl*nz;
double ur = ul-2.0*udotn*nx;
double vr = vl-2.0*udotn*ny;
double wr = wl-2.0*udotn*nz;
fatface[(iwp-1)+(irho-1)*lxz2ldimlelt+e*lxz2ldim+(iface)*lxz+l]= rr;
fatface[(iwp-1)+(iux-1)*lxz2ldimlelt+e*lxz2ldim+(iface)*lxz+l]= ur;
fatface[(iwp-1)+(iuy-1)*lxz2ldimlelt+e*lxz2ldim+(iface)*lxz+l]= vr;
fatface[(iwp-1)+(iuz-1)*lxz2ldimlelt+e*lxz2ldim+(iface)*lxz+l]= wr;
fatface[(iwp-1)+(ipr-1)*lxz2ldimlelt+e*lxz2ldim+(iface)*lxz+l]= fatface[(iwm-1)+(ipr-1)*lxz2ldimlelt+e*lxz2ldim+(iface)*lxz+l];
fatface[(iwp-1)+(ithm-1)*lxz2ldimlelt+e*lxz2ldim+(iface)*lxz+l]= fatface[(iwm-1)+(ithm-1)*lxz2ldimlelt+e*lxz2ldim+(iface)*lxz+l];
fatface[(iwp-1)+(isnd-1)*lxz2ldimlelt+e*lxz2ldim+(iface)*lxz+l]= fatface[(iwm-1)+(isnd-1)*lxz2ldimlelt+e*lxz2ldim+(iface)*lxz+l];
fatface[(iwp-1)+(iph-1)*lxz2ldimlelt+e*lxz2ldim+(iface)*lxz+l]= fatface[(iwm-1)+(iph-1)*lxz2ldimlelt+e*lxz2ldim+(iface)*lxz+l];
fatface[(iwp-1)+(icvf-1)*lxz2ldimlelt+e*lxz2ldim+(iface)*lxz+l]= fatface[(iwm-1)+(icvf-1)*lxz2ldimlelt+e*lxz2ldim+(iface)*lxz+l];
fatface[(iwp-1)+(icpf-1)*lxz2ldimlelt+e*lxz2ldim+(iface)*lxz+l]= fatface[(iwm-1)+(icpf-1)*lxz2ldimlelt+e*lxz2ldim+(iface)*lxz+l];
fatface[(iwp-1)+(iu1-1)*lxz2ldimlelt+e*lxz2ldim+(iface)*lxz+l]= fatface[(iwm-1)+(iu1-1)*lxz2ldimlelt+e*lxz2ldim+(iface)*lxz+l];
fatface[(iwp-1)+(iu2-1)*lxz2ldimlelt+e*lxz2ldim+(iface)*lxz+l]= rr*ur;
fatface[(iwp-1)+(iu3-1)*lxz2ldimlelt+e*lxz2ldim+(iface)*lxz+l]= rr*vr;
fatface[(iwp-1)+(iu4-1)*lxz2ldimlelt+e*lxz2ldim+(iface)*lxz+l]= rr*wr;
fatface[(iwp-1)+(iu5-1)*lxz2ldimlelt+e*lxz2ldim+(iface)*lxz+l]= fatface[(iwm-1)+(iu5-1)*lxz2ldimlelt+e*lxz2ldim+(iface)*lxz+l];
}
}
}
extern "C" void inviscidbc_gpu_wrapper_(int *glbblockSize2,int *d_lglel,double *d_fatface,char *d_cbc,double *d_xm1,double *d_ym1,double *d_zm1,double *d_vx,double *d_vy,double *d_vz,double *d_t,double *d_pr,double *d_sii,double *d_siii,double *d_vdiff,double *d_vtrans,char *d_cb,double *d_u,double *d_phig,double *d_csound,double *d_unx,double *d_uny,double *d_unz,double *molarmass,int *iwm,int *iwp,int *irho,int *iux,int *iuy,int *iuz,int *iph,int *ipr,int *isnd,int *ithm,int *icpf,int *icvf,int *iu1,int *iu2,int *iu3,int *iu4,int *iu5,int *lx1,int *lz1,int *toteq,int *ldim,int *nelt, int *lelt,double *p0th,int *ifield,int *icv, int *icp,int *imu,int *ilam,double *molmass,int *npscal,int *if3d,int *outflsub,double *pinfty,int *ly1){
#ifdef DEBUGPRINT
cudaDeviceSynchronize();
cudaError_t code1 = cudaPeekAtLastError();
printf("CUDA: Start inviscidbc_gpu_wrapper cuda status: %s\n",cudaGetErrorString(code1));
printf("CUDA: Start inviscidbc_gpu_wrapper values molarmass =%lf ,iwm=%d,iwp=%d,irho=%d,iux=%d,iuy=%d,iuz=%d,iph=%d,ipr=%d,isnd=%d,ithm=%d,icpf=%d,icvf=%d,iu1=%d,iu2=%d,iu3=%d,iu4=%d,iu5=%d,lx1=%d,lz1=%d,itoteq=%d,ldim=%d,nelt=%d,lelt=%d,p0th=%lf,ifield=%d,icv=%d,icp=%d,imu=%d,ilam=%d,molmass=%lf,npscal=%d,if3d=%d,outflsub=%d,pinfty=%lf,ly1=%d \n", molarmass[0],iwm[0],iwp[0],irho[0],iux[0],iuy[0],iuz[0],iph[0],ipr[0],isnd[0],ithm[0],icpf[0],icvf[0],iu1[0],iu2[0],iu3[0],iu4[0],iu5[0],lx1[0],lz1[0],toteq[0],ldim[0],nelt[0],lelt[0],p0th[0],ifield[0],icv[0],icp[0],imu[0],ilam[0],molmass[0],npscal[0],if3d[0],outflsub[0],pinfty[0],ly1[0]);
#endif
int lxz = lx1[0]*lz1[0];
int nxyz =lxz*ly1[0];
int lxz2ldim=lxz*2*ldim[0];
int lxy = lx1[0]*ly1[0];
int lxz2ldimlelt=lxz2ldim*nelt[0];
int e_offset=nxyz*toteq[0];
int nlel=nxyz*lelt[0];
int ntot = nelt[0]*lxz2ldim;
int ltot = lelt[0]*lxz2ldim;
int blockSize = 256, gridSize;
gridSize = (int)ceil((float)ntot/blockSize);
//inflow
InviscidBC_gpu_kernel1<<<gridSize, blockSize>>>(d_lglel,d_fatface,d_cbc,d_xm1,d_ym1,d_zm1,d_vx,d_vy,d_vz,d_t,d_pr,d_sii,d_siii,d_vdiff,d_vtrans,d_cb,d_u,d_phig,d_csound,d_unx,d_uny,d_unz,molarmass[0],iwm[0],iwp[0],irho[0],iux[0],iuy[0],iuz[0],iph[0],ipr[0],isnd[0],ithm[0],icpf[0],icvf[0],iu1[0],iu2[0],iu3[0],iu4[0],iu5[0],lx1[0],lz1[0],lxz,ldim[0],lxz2ldim,nxyz,lxy,lxz2ldimlelt,ntot,toteq[0],e_offset,p0th[0],ifield[0],ltot, icv[0],icp[0],imu[0],ilam[0],molmass[0],nlel,npscal[0],if3d[0], ly1[0],outflsub[0], pinfty[0], lelt[0]);
#ifdef DEBUGPRINT
cudaDeviceSynchronize();
code1 = cudaPeekAtLastError();
printf("CUDA:inviscidbc_gpu_wrapper after 1 cuda status: %s\n",cudaGetErrorString(code1));
#endif
//outflow
InviscidBC_gpu_kernel2<<<gridSize, blockSize>>>(d_lglel,d_fatface,d_cbc,d_xm1,d_ym1,d_zm1,d_vx,d_vy,d_vz,d_t,d_pr,d_sii,d_siii,d_vdiff,d_vtrans,d_cb,d_u,d_phig,d_csound,d_unx,d_uny,d_unz,molarmass[0],iwm[0],iwp[0],irho[0],iux[0],iuy[0],iuz[0],iph[0],ipr[0],isnd[0],ithm[0],icpf[0],icvf[0],iu1[0],iu2[0],iu3[0],iu4[0],iu5[0],lx1[0],lz1[0],lxz,ldim[0],lxz2ldim,nxyz,lxy,lxz2ldimlelt,ntot,toteq[0],e_offset,p0th[0],ifield[0],ltot, icv[0],icp[0],imu[0],ilam[0],molmass[0],nlel,npscal[0],if3d[0], ly1[0],outflsub[0], pinfty[0],d_fatface+iwp[0]-1, lelt[0]);
#ifdef DEBUGPRINT
cudaDeviceSynchronize();
code1 = cudaPeekAtLastError();
printf("CUDA:inviscidbc_gpu_wrapper after 2 cuda status: %s\n",cudaGetErrorString(code1));
#endif
//wallbc_inviscid
InviscidBC_gpu_kernel3<<<gridSize, blockSize>>>(d_lglel,d_fatface,d_cbc,d_xm1,d_ym1,d_zm1,d_vx,d_vy,d_vz,d_t,d_pr,d_sii,d_siii,d_vdiff,d_vtrans,d_cb,d_u,d_phig,d_csound,d_unx,d_uny,d_unz,molarmass[0],iwm[0],iwp[0],irho[0],iux[0],iuy[0],iuz[0],iph[0],ipr[0],isnd[0],ithm[0],icpf[0],icvf[0],iu1[0],iu2[0],iu3[0],iu4[0],iu5[0],lx1[0],lz1[0],lxz,ldim[0],lxz2ldim,nxyz,lxy,lxz2ldimlelt,ntot,toteq[0],e_offset,p0th[0],ifield[0],ltot, icv[0],icp[0],imu[0],ilam[0],molmass[0],nlel,npscal[0],if3d[0], ly1[0],outflsub[0], pinfty[0], lelt[0]);
#ifdef DEBUGPRINT
cudaDeviceSynchronize();
cudaError_t code2 = cudaPeekAtLastError();
printf("CUDA: End nviscidbc_gpu_wrapper cuda status: %s\n",cudaGetErrorString(code2));
#endif
} | #include <hip/hip_runtime.h>
#include <stdio.h>
//#define DEBUGPRINT 0
__global__ void InviscidBC_gpu_kernel1(int *lglel, double *fatface,char *cbc, double *xm1,double *ym1,double *zm1,double *vx,double *vy,double *vz,double *t,double *pr,double *sii,double *siii,double *vdiff,double *vtrans,char *cb,double *u,double *phig,double *csound,double *unx,double *uny,double *unz,double molarmass,int iwm,int iwp,int irho,int iux,int iuy,int iuz,int iph,int ipr,int isnd,int ithm,int icpf,int icvf,int iu1,int iu2,int iu3,int iu4,int iu5,int lx1,int lz1,int lxz,int ldim,int lxz2ldim,int nxyz,int lxy,int lxz2ldimlelt,int ntot,int toteq,int e_offset,int p0th,int ifield,int ltot,int icv,int icp,int imu,int ilam,double molmass,int nlel,int npscal,int if3d,int ly1,int outflsub,double pinfty, int lelt){
int id = blockIdx.x*blockDim.x+threadIdx.x;
if(id<ntot){
int i1 = id % lx1;
int i2 = (id/lx1)%lz1;
int iface= ((id/lxz)%(2*ldim));
int e = id/lxz2ldim;
char cb1 = cbc[(ifield)*lelt*18+e*18+iface*3]; //corrected by Kk 02/07/2019 by adding ifield*lelt*18 and iface*3, ifield=1 no need to -1 since in cpu, cbc starting from 0 in the ifield entry
char cb2 = cbc[(ifield)*lelt*18+e*18+iface*3+1];
char cb3 = cbc[(ifield)*lelt*18+e*18+iface*3+2];
if(cb1 =='v'|| cb1=='V'){
int ieg=lglel[e];
int iy,iz,ix,l;
if(iface==0){
iy=0;
iz=i2;
ix=i1;
l=lx1*iz+ix;
}
else if(iface==3){
ix=0;
iz=i2;
iy=i1;
l=ly1*iz+iy;
}
else if(iface==4){
iz=0;
iy=i2;
ix=i1;
l=lx1*iy+ix;
}
else if(iface==1){
ix=lx1-1;
iz=i2;
iy=i1;
l=ly1*iz+iy;
}
else if(iface==2){
iy=ly1-1;
iz=i2;
ix=i1;
l=lx1*iz+ix;
}
else if(iface==5){
iz=lz1-1;
iy=i2;
ix=i1;
l=lx1*iy+ix;
}
//nekasgn
double x = xm1[e*nxyz+iz*lxy+iy*lx1+ix];
double y = ym1[e*nxyz+iz*lxy+iy*lx1+ix];
double z = zm1[e*nxyz+iz*lxy+iy*lx1+ix];
double r = x*x+y*y;
double theta=0.0;
if (r>0.0){ r = sqrtf(r);}
if ( x != 0.0 || y!= 0.0){theta = atan2(y,x); }
double ux= vx[e*nxyz+iz*lxy+iy*lx1+ix];
double uy= vy[e*nxyz+iz*lxy+iy*lx1+ix];
double uz= vz[e*nxyz+iz*lxy+iy*lx1+ix];
double temp = t [ e*nxyz+iz*lxy+iy*lx1+ix];
int ips;
double pa = pr [e*nxyz+iz*lxy+iy*lx1+ix];
double p0= p0th;
double si2 = sii[e*nxyz+iz*lxy+iy*lx1+ix];
double si3 = siii[e*nxyz+iz*lxy+iy*lx1+ix];
double udiff = vdiff[(ifield-1)*nlel+e*nxyz+iz*lxy+iy*lx1+ix];
double utrans = vtrans[(ifield-1)*nlel+e*nxyz+iz*lxy+iy*lx1+ix];
char cbu1 = cb[0];
char cbu2 = cb[1];
char cbu3 = cb[2];
//cmtasgn
double phi = phig[e*nxyz+iz*lxy+iy*lx1+ix];
double rho = vtrans[(irho-1)*nlel +e*nxyz+iz*lxy+iy*lx1+ix];
double pres = pr[e*nxyz+iz*lxy+iy*lx1+ix];
double cv=0.0,cp=0.0;
if(rho!=0){
cv=vtrans[(icv-1)*nlel +e*nxyz+iz*lxy+iy*lx1+ix]/rho;
cp=vtrans[(icp-1)*nlel +e*nxyz+iz*lxy+iy*lx1+ix]/rho;
}
double asnd = csound [e*nxyz+iz*lxy+iy*lx1+ix];
double mu = vdiff[(imu-1)*nlel+e*nxyz+iz*lxy+iy*lx1+ix];
udiff = vdiff[(imu-1)*nlel+e*nxyz+iz*lxy+iy*lx1+ix];// this overrides the udiff in nekasgn (line 63 in this function). Need to check withDr.Tania
double lambda = vdiff[(ilam-1)*nlel+e*nxyz+iz*lxy+iy*lx1+ix];
// userbc
double molarmass = molmass;
fatface[(iwp-1)+(irho-1)*lxz2ldimlelt+e*lxz2ldim+(iface)*lxz+l ] = rho;
fatface[(iwp-1)+(iux-1)*lxz2ldimlelt+e*lxz2ldim+(iface)*lxz+l ] = ux;
fatface[(iwp-1)+(iuy-1)*lxz2ldimlelt+e*lxz2ldim+(iface)*lxz+l ] = uy;
fatface[(iwp-1)+(iuz-1)*lxz2ldimlelt+e*lxz2ldim+(iface)*lxz+l ] = uz;
fatface[(iwp-1)+(iph-1)*lxz2ldimlelt+e*lxz2ldim+(iface)*lxz+l ] = phi;
double rhob = rho*phi;
double rhoub = rhob*ux;
double rhovb = rhob*uy;
double rhowb = rhob*uz;
fatface[(iwp-1)+(iu1-1)*lxz2ldimlelt+e*lxz2ldim+(iface)*lxz+l ] = rhob;
fatface[(iwp-1)+(iu2-1)*lxz2ldimlelt+e*lxz2ldim+(iface)*lxz+l ] = rhoub;
fatface[(iwp-1)+(iu3-1)*lxz2ldimlelt+e*lxz2ldim+(iface)*lxz+l ] = rhovb;
fatface[(iwp-1)+(iu4-1)*lxz2ldimlelt+e*lxz2ldim+(iface)*lxz+l ] = rhowb;
double mach=0;
double snz=0;
if(if3d){
mach = sqrtf(ux*ux+uy*uy+uz*uz)/asnd;
snz = unz[e*6*lx1*lz1+(iface)*lxz+l];
}
else{
mach = sqrt(ux*ux+uy*uy+uz*uz)/asnd;
snz=0;
}
double snx = unx[e*6*lx1*lz1+(iface)*lxz+l];
double sny = uny[e*6*lx1*lz1+(iface)*lxz+l];
if (mach<1.0){
pres = fatface[(iwm-1)+(ipr-1)*lxz2ldimlelt+e*lxz2ldim+(iface)*lxz+l ];
temp = pres/rho/(cp-cv);// ! definitely too perfect!
fatface[(iwp-1)+(ipr-1)*lxz2ldimlelt+e*lxz2ldim+(iface)*lxz+l ] = pres;
fatface[(iwp-1)+(isnd-1)*lxz2ldimlelt+e*lxz2ldim+(iface)*lxz+l ] = sqrt(cp/cv*pres/rho);//check the operator precedence is same as fortran . check with Dr.Tania. adeesha
fatface[(iwp-1)+(ithm-1)*lxz2ldimlelt+e*lxz2ldim+(iface)*lxz+l ] = temp ;// ! definitely too perfect!
fatface[(iwp-1)+(icpf-1)*lxz2ldimlelt+e*lxz2ldim+(iface)*lxz+l ] = rho*cp ;//! NEED EOS WITH TEMP Dirichlet, userbc
fatface[(iwp-1)+(icvf-1)*lxz2ldimlelt+e*lxz2ldim+(iface)*lxz+l ] = rho*cv ;//! NEED EOS WITH TEMP Dirichlet, userbc
}
else{ //supersonic inflow
fatface[(iwp-1)+(ipr-1)*lxz2ldimlelt+e*lxz2ldim+(iface)*lxz+l ] = pres;
fatface[(iwp-1)+(isnd-1)*lxz2ldimlelt+e*lxz2ldim+(iface)*lxz+l ] =asnd;
fatface[(iwp-1)+(ithm-1)*lxz2ldimlelt+e*lxz2ldim+(iface)*lxz+l ] = temp ;// ! definitely too perfect!
fatface[(iwp-1)+(icpf-1)*lxz2ldimlelt+e*lxz2ldim+(iface)*lxz+l ] = rho*cp ;//! NEED EOS WITH TEMP Dirichlet, userbc
fatface[(iwp-1)+(icvf-1)*lxz2ldimlelt+e*lxz2ldim+(iface)*lxz+l ] = rho*cv ;//! NEED EOS WITH TEMP Dirichlet, userbc
}
fatface[(iwp-1)+(iu5-1)*lxz2ldimlelt+e*lxz2ldim+(iface)*lxz+l ] = phi*rho*cv*temp+0.5/rhob*(rhoub*rhoub+rhovb*rhovb+rhowb*rhowb);
}
}
}
__global__ void InviscidBC_gpu_kernel2(int *lglel, double *fatface,char *cbc, double *xm1,double *ym1,double *zm1,double *vx,double *vy,double *vz,double *t,double *pr,double *sii,double *siii,double *vdiff,double *vtrans,char *cb,double *u,double *phig,double *csound,double *unx,double *uny,double *unz,double molarmass,int iwm,int iwp,int irho,int iux,int iuy,int iuz,int iph,int ipr,int isnd,int ithm,int icpf,int icvf,int iu1,int iu2,int iu3,int iu4,int iu5,int lx1,int lz1,int lxz,int ldim,int lxz2ldim,int nxyz,int lxy,int lxz2ldimlelt,int ntot,int toteq,int e_offset,int p0th,int ifield,int ltot,int icv,int icp,int imu,int ilam,double molmass,int nlel,int npscal,int if3d,int ly1,int outflsub,double pinfty,double *fatfaceiwp, int lelt){
int id = blockIdx.x*blockDim.x+threadIdx.x;
if(id<ntot){
int i1 = id % lx1;
int i2 = (id/lx1)%lz1;
int iface= ((id/lxz)%(2*ldim));
int e = id/lxz2ldim;
char cb1 = cbc[(ifield)*lelt*18+e*18+iface*3];//corrected by Kk 02/07/2019 by adding ifield*lelt*18 and iface*3
char cb2 = cbc[(ifield)*lelt*18+e*18+iface*3+1];
char cb3 = cbc[(ifield)*lelt*18+e*18+iface*3+2];
/*if(id==10){
for(int i=0;i<576;i++){
printf("cbc values cbc[%d]=%c \n",i,cbc[i+ifield*lelt*18]);
}
printf("debugggggg iface id %d %d\n", iface, id);
}*/
//if(id ==0) printf("debug ifield %d \n", ifield);
//printf("cb1 =%c \n",cb1);
if(cb1 =='O'){
int ieg=lglel[e];
int iy,iz,ix,l;
if(iface==0){
iy=0;
iz=i2;
ix=i1;
l=lx1*iz+ix;
}
else if(iface==3){
ix=0;
iz=i2;
iy=i1;
l=ly1*iz+iy;
}
else if(iface==4){
iz=0;
iy=i2;
ix=i1;
l=lx1*iy+ix;
}
else if(iface==1){
ix=lx1-1;
iz=i2;
iy=i1;
l=ly1*iz+iy;
}
else if(iface==2){
iy=ly1-1;
iz=i2;
ix=i1;
l=lx1*iz+ix;
}
else if(iface==5){
iz=lz1-1;
iy=i2;
ix=i1;
l=lx1*iy+ix;
}
//nekasgn
double x = xm1[e*nxyz+iz*lxy+iy*lx1+ix];
double y = ym1[e*nxyz+iz*lxy+iy*lx1+ix];
double z = zm1[e*nxyz+iz*lxy+iy*lx1+ix];
// double r = x*x+y*y;
// double theta=0.0;
// if (r>0.0){ r = sqrtf(r);}
// if ( x != 0.0 || y!= 0.0){theta = atan2(y,x); }
// double ux= vx[e*nxyz+iz*lxy+iy*lx1+ix];
// double uy= vy[e*nxyz+iz*lxy+iy*lx1+ix];
// double uz= vz[e*nxyz+iz*lxy+iy*lx1+ix];
// double temp = t [ e*nxyz+iz*lxy+iy*lx1+ix];
// double p0= p0th;
//cmtasgn
double phi = phig[e*nxyz+iz*lxy+iy*lx1+ix];
double rho = vtrans[(irho-1)*nlel +e*nxyz+iz*lxy+iy*lx1+ix];
double pres = pr[e*nxyz+iz*lxy+iy*lx1+ix];
double cv=0.0,cp=0.0;
// userbc
double molarmass = molmass;
double sxn = unx[e*6*lxz+(iface)*lxz+l];
double syn = uny[e*6*lxz+(iface)*lxz+l];
double szn = unz[e*6*lxz+(iface)*lxz+l];
double rhou = fatface[(iwm-1)+(iu2-1)*lxz2ldimlelt+e*lxz2ldim+(iface)*lxz+l ]/phi;
double rhov = fatface[(iwm-1)+(iu3-1)*lxz2ldimlelt+e*lxz2ldim+(iface)*lxz+l ]/phi;
double rhow = fatface[(iwm-1)+(iu4-1)*lxz2ldimlelt+e*lxz2ldim+(iface)*lxz+l ]/phi;
double rhoe = fatface[(iwm-1)+(iu5-1)*lxz2ldimlelt+e*lxz2ldim+(iface)*lxz+l ]/phi;
double pl = fatface[(iwm-1)+(ipr-1)*lxz2ldimlelt+e*lxz2ldim+(iface)*lxz+l ]/phi;
fatfaceiwp[(icpf-1)*lxz2ldimlelt+e*lxz2ldim+(iface)*lxz+l ]= fatface[(iwm-1)+(icpf-1)*lxz2ldimlelt+e*lxz2ldim+(iface)*lxz+l];
fatfaceiwp[(icvf-1)*lxz2ldimlelt+e*lxz2ldim+(iface)*lxz+l ]= fatface[(iwm-1)+(icvf-1)*lxz2ldimlelt+e*lxz2ldim+(iface)*lxz+l];
cp=fatface[(iwm-1)+(icpf-1)*lxz2ldimlelt+e*lxz2ldim+(iface)*lxz+l]/rho;
cv = fatface[(iwm-1)+(icvf-1)*lxz2ldimlelt+e*lxz2ldim+(iface)*lxz+l]/rho;
int idbc=0;
if(outflsub){
pres=pinfty;
idbc=1;
}
else{
pres=fatface[(iwm-1)+(ipr-1)*lxz2ldimlelt+e*lxz2ldim+(iface)*lxz+l];
idbc=0;
}
//BcondOutflowPerf function
double rgas = 8314.3/molarmass;
double gamma = cp/(cp - rgas);
double gam1 = gamma-1;
double u = rhou/rho;
double v = rhov/rho;
double w = rhow/rho;
double csound= sqrtf(gamma*pl/rho);
double mach = sqrtf(u*u+v*v+w*w)/csound;
double rhob,rhoub,rhovb,rhowb,rhoeb;
//subsonic flow
if(mach<1 && idbc==1 || idbc==0){ // check the precendence of and and or in fortran check with Dr.Tania adeesha
double rrhoc = 1.0 / (rho*csound);
double deltp = pl - pres;
rhob = rho - deltp/(csound*csound);
double ub = u+sxn*deltp*rrhoc;
double vb = v+syn*deltp*rrhoc;
double wb = w+szn*deltp*rrhoc;
double vnd = ub*sxn + vb*syn + wb*szn;
if(vnd<0.0){
ub = copysignf(1.0,u)*fmax(fabs(ub),fabs(u));
vb = copysignf(1.0,v)*fmax(fabs(vb),fabs(v));
wb = copysignf(1.0,w)*fmax(fabs(wb),fabs(w));
}
rhoub = rhob*ub;
rhovb = rhob*vb;
rhowb = rhob*wb;
rhoeb = rhob*( pres/(rhob*(gamma - 1.0)) + 0.5*(ub*ub +vb*vb + wb*wb));
}
else{
rhob= rho;
rhoub = rhou;
rhovb = rhov;
rhowb =rhow;
rhoeb = rhoe;
}
// printf("inviscid iu1 %d iu2 %d iu3 %d iu4 %d iu5 %d iph %d ipr %d e %d lxz2ldimlelt %d iface %d lxz2ldim %d rhob %lf phi %lf rhoub %lf rhovb %lf rhowb %lf rhoeb %lf pres %lf l= %d \n",iu1,iu2,iu3,iu4,iu5,iph,ipr,e,lxz2ldimlelt,iface,lxz2ldim,rhob,phi,rhoub,rhovb,rhowb,rhoeb,pres,l);
fatfaceiwp[(irho-1)*lxz2ldimlelt+e*lxz2ldim+(iface)*lxz+l ] = rhob;
fatfaceiwp[(iux-1)*lxz2ldimlelt+e*lxz2ldim+(iface)*lxz+l ] = rhoub/rhob;
fatfaceiwp[(iuy-1)*lxz2ldimlelt+e*lxz2ldim+(iface)*lxz+l ] = rhovb/rhob;
fatfaceiwp[(iuz-1)*lxz2ldimlelt+e*lxz2ldim+(iface)*lxz+l ] = rhowb/rhob;
fatfaceiwp[(ithm-1)*lxz2ldimlelt+e*lxz2ldim+(iface)*lxz+l ] = (rhoeb-0.5*(rhoub*rhoub+rhovb*rhovb+rhowb*rhowb)/rhob)/cv;
fatfaceiwp[(iu1-1)*lxz2ldimlelt+e*lxz2ldim+(iface)*lxz+l ] = rhob*phi;
fatfaceiwp[(iu2-1)*lxz2ldimlelt+e*lxz2ldim+(iface)*lxz+l ] = rhoub*phi;
fatfaceiwp[(iu3-1)*lxz2ldimlelt+e*lxz2ldim+(iface)*lxz+l ] = rhovb*phi;
fatfaceiwp[(iu4-1)*lxz2ldimlelt+e*lxz2ldim+(iface)*lxz+l ] = rhowb*phi;
fatfaceiwp[(iu5-1)*lxz2ldimlelt+e*lxz2ldim+(iface)*lxz+l ] = rhoeb*phi;
fatfaceiwp[(iph-1)*lxz2ldimlelt+e*lxz2ldim+(iface)*lxz+l ] = phi;
fatfaceiwp[(ipr-1)*lxz2ldimlelt+e*lxz2ldim+(iface)*lxz+l ] = pres;
fatfaceiwp[(isnd-1)*lxz2ldimlelt+e*lxz2ldim+(iface)*lxz+l ] = sqrtf(cp/cv*pres/rho);
}
}
}
__global__ void InviscidBC_gpu_kernel3(int *lglel, double *fatface,char *cbc, double *xm1,double *ym1,double *zm1,double *vx,double *vy,double *vz,double *t,double *pr,double *sii,double *siii,double *vdiff,double *vtrans,char *cb,double *u,double *phig,double *csound,double *unx,double *uny,double *unz,double molarmass,int iwm,int iwp,int irho,int iux,int iuy,int iuz,int iph,int ipr,int isnd,int ithm,int icpf,int icvf,int iu1,int iu2,int iu3,int iu4,int iu5,int lx1,int lz1,int lxz,int ldim,int lxz2ldim,int nxyz,int lxy,int lxz2ldimlelt,int ntot,int toteq,int e_offset,int p0th,int ifield,int ltot,int icv,int icp,int imu,int ilam,double molmass,int nlel,int npscal,int if3d,int ly1,int outflsub,double pinfty, int lelt){
int id = blockIdx.x*blockDim.x+threadIdx.x;
if(id<ntot){
int i1 = id % lx1;
int l = id % lxz; //added by Kk 02/07/19
int i2 = (id/lx1)%lz1;
int iface= ((id/lxz)%(2*ldim));
int e = id/lxz2ldim;
char cb1 = cbc[(ifield)*lelt*18+e*18+iface*3];//corrected by Kk 02/07/2019 by adding ifield*lelt*18 and iface*3
char cb2 = cbc[(ifield)*lelt*18+e*18+iface*3+1];
char cb3 = cbc[(ifield)*lelt*18+e*18+iface*3+2];
if(cb1 =='W'|| cb1=='I' || (cb1=='S' && cb2=='Y' && cb3=='M')){
int ieg=lglel[e];
/* following 4 line is commented out by Kk 02/07/2019 since subroutine facind is not used in CPU part
int iy=0;
int iz=i2;
int ix=i1;
int l=lx1*iz+ix;*/ // this is the parallelized version of l = l+1 in every thread. Check with Dr.Tania . adeesha
// ************************ e*lxz2ldim+(f-1)*lx1*lz1+l is same as id. change this later. ******
//printf("debug inviscidBc: lxz2ldimlelt %d, lxz2ldim %d, iface %d, l %d, fatface %.30lf , id %d, e %d, index1 %d, index2 %d\n", lxz2ldimlelt, lxz2ldim, iface, l, fatface[(iwm-1)+(irho-1)*lxz2ldimlelt+e*lxz2ldim+(iface)*lxz+l], id, e, (iwm-1)+(irho-1)*lxz2ldimlelt+e*lxz2ldim+(iface)*lxz+l, (irho-1)*lxz2ldimlelt+e*lxz2ldim+(iface)*lxz+l);
double nx = unx[e*lxz2ldim+(iface)*lxz+l];
double ny = uny[e*lxz2ldim+(iface)*lxz+l];
double nz = unz[e*lxz2ldim+(iface)*lxz+l];
double rl = fatface[(iwm-1)+(irho-1)*lxz2ldimlelt+e*lxz2ldim+(iface)*lxz+l];
double rr=rl;
double ul = fatface[(iwm-1)+(iux-1)*lxz2ldimlelt+e*lxz2ldim+(iface)*lxz+l];
double vl = fatface[(iwm-1)+(iuy-1)*lxz2ldimlelt+e*lxz2ldim+(iface)*lxz+l];
double wl = fatface[(iwm-1)+(iuz-1)*lxz2ldimlelt+e*lxz2ldim+(iface)*lxz+l];
double fs=0.0;
double udotn = ul*nx+vl*ny+wl*nz;
double ur = ul-2.0*udotn*nx;
double vr = vl-2.0*udotn*ny;
double wr = wl-2.0*udotn*nz;
fatface[(iwp-1)+(irho-1)*lxz2ldimlelt+e*lxz2ldim+(iface)*lxz+l]= rr;
fatface[(iwp-1)+(iux-1)*lxz2ldimlelt+e*lxz2ldim+(iface)*lxz+l]= ur;
fatface[(iwp-1)+(iuy-1)*lxz2ldimlelt+e*lxz2ldim+(iface)*lxz+l]= vr;
fatface[(iwp-1)+(iuz-1)*lxz2ldimlelt+e*lxz2ldim+(iface)*lxz+l]= wr;
fatface[(iwp-1)+(ipr-1)*lxz2ldimlelt+e*lxz2ldim+(iface)*lxz+l]= fatface[(iwm-1)+(ipr-1)*lxz2ldimlelt+e*lxz2ldim+(iface)*lxz+l];
fatface[(iwp-1)+(ithm-1)*lxz2ldimlelt+e*lxz2ldim+(iface)*lxz+l]= fatface[(iwm-1)+(ithm-1)*lxz2ldimlelt+e*lxz2ldim+(iface)*lxz+l];
fatface[(iwp-1)+(isnd-1)*lxz2ldimlelt+e*lxz2ldim+(iface)*lxz+l]= fatface[(iwm-1)+(isnd-1)*lxz2ldimlelt+e*lxz2ldim+(iface)*lxz+l];
fatface[(iwp-1)+(iph-1)*lxz2ldimlelt+e*lxz2ldim+(iface)*lxz+l]= fatface[(iwm-1)+(iph-1)*lxz2ldimlelt+e*lxz2ldim+(iface)*lxz+l];
fatface[(iwp-1)+(icvf-1)*lxz2ldimlelt+e*lxz2ldim+(iface)*lxz+l]= fatface[(iwm-1)+(icvf-1)*lxz2ldimlelt+e*lxz2ldim+(iface)*lxz+l];
fatface[(iwp-1)+(icpf-1)*lxz2ldimlelt+e*lxz2ldim+(iface)*lxz+l]= fatface[(iwm-1)+(icpf-1)*lxz2ldimlelt+e*lxz2ldim+(iface)*lxz+l];
fatface[(iwp-1)+(iu1-1)*lxz2ldimlelt+e*lxz2ldim+(iface)*lxz+l]= fatface[(iwm-1)+(iu1-1)*lxz2ldimlelt+e*lxz2ldim+(iface)*lxz+l];
fatface[(iwp-1)+(iu2-1)*lxz2ldimlelt+e*lxz2ldim+(iface)*lxz+l]= rr*ur;
fatface[(iwp-1)+(iu3-1)*lxz2ldimlelt+e*lxz2ldim+(iface)*lxz+l]= rr*vr;
fatface[(iwp-1)+(iu4-1)*lxz2ldimlelt+e*lxz2ldim+(iface)*lxz+l]= rr*wr;
fatface[(iwp-1)+(iu5-1)*lxz2ldimlelt+e*lxz2ldim+(iface)*lxz+l]= fatface[(iwm-1)+(iu5-1)*lxz2ldimlelt+e*lxz2ldim+(iface)*lxz+l];
}
}
}
extern "C" void inviscidbc_gpu_wrapper_(int *glbblockSize2,int *d_lglel,double *d_fatface,char *d_cbc,double *d_xm1,double *d_ym1,double *d_zm1,double *d_vx,double *d_vy,double *d_vz,double *d_t,double *d_pr,double *d_sii,double *d_siii,double *d_vdiff,double *d_vtrans,char *d_cb,double *d_u,double *d_phig,double *d_csound,double *d_unx,double *d_uny,double *d_unz,double *molarmass,int *iwm,int *iwp,int *irho,int *iux,int *iuy,int *iuz,int *iph,int *ipr,int *isnd,int *ithm,int *icpf,int *icvf,int *iu1,int *iu2,int *iu3,int *iu4,int *iu5,int *lx1,int *lz1,int *toteq,int *ldim,int *nelt, int *lelt,double *p0th,int *ifield,int *icv, int *icp,int *imu,int *ilam,double *molmass,int *npscal,int *if3d,int *outflsub,double *pinfty,int *ly1){
#ifdef DEBUGPRINT
hipDeviceSynchronize();
hipError_t code1 = hipPeekAtLastError();
printf("CUDA: Start inviscidbc_gpu_wrapper cuda status: %s\n",hipGetErrorString(code1));
printf("CUDA: Start inviscidbc_gpu_wrapper values molarmass =%lf ,iwm=%d,iwp=%d,irho=%d,iux=%d,iuy=%d,iuz=%d,iph=%d,ipr=%d,isnd=%d,ithm=%d,icpf=%d,icvf=%d,iu1=%d,iu2=%d,iu3=%d,iu4=%d,iu5=%d,lx1=%d,lz1=%d,itoteq=%d,ldim=%d,nelt=%d,lelt=%d,p0th=%lf,ifield=%d,icv=%d,icp=%d,imu=%d,ilam=%d,molmass=%lf,npscal=%d,if3d=%d,outflsub=%d,pinfty=%lf,ly1=%d \n", molarmass[0],iwm[0],iwp[0],irho[0],iux[0],iuy[0],iuz[0],iph[0],ipr[0],isnd[0],ithm[0],icpf[0],icvf[0],iu1[0],iu2[0],iu3[0],iu4[0],iu5[0],lx1[0],lz1[0],toteq[0],ldim[0],nelt[0],lelt[0],p0th[0],ifield[0],icv[0],icp[0],imu[0],ilam[0],molmass[0],npscal[0],if3d[0],outflsub[0],pinfty[0],ly1[0]);
#endif
int lxz = lx1[0]*lz1[0];
int nxyz =lxz*ly1[0];
int lxz2ldim=lxz*2*ldim[0];
int lxy = lx1[0]*ly1[0];
int lxz2ldimlelt=lxz2ldim*nelt[0];
int e_offset=nxyz*toteq[0];
int nlel=nxyz*lelt[0];
int ntot = nelt[0]*lxz2ldim;
int ltot = lelt[0]*lxz2ldim;
int blockSize = 256, gridSize;
gridSize = (int)ceil((float)ntot/blockSize);
//inflow
InviscidBC_gpu_kernel1<<<gridSize, blockSize>>>(d_lglel,d_fatface,d_cbc,d_xm1,d_ym1,d_zm1,d_vx,d_vy,d_vz,d_t,d_pr,d_sii,d_siii,d_vdiff,d_vtrans,d_cb,d_u,d_phig,d_csound,d_unx,d_uny,d_unz,molarmass[0],iwm[0],iwp[0],irho[0],iux[0],iuy[0],iuz[0],iph[0],ipr[0],isnd[0],ithm[0],icpf[0],icvf[0],iu1[0],iu2[0],iu3[0],iu4[0],iu5[0],lx1[0],lz1[0],lxz,ldim[0],lxz2ldim,nxyz,lxy,lxz2ldimlelt,ntot,toteq[0],e_offset,p0th[0],ifield[0],ltot, icv[0],icp[0],imu[0],ilam[0],molmass[0],nlel,npscal[0],if3d[0], ly1[0],outflsub[0], pinfty[0], lelt[0]);
#ifdef DEBUGPRINT
hipDeviceSynchronize();
code1 = hipPeekAtLastError();
printf("CUDA:inviscidbc_gpu_wrapper after 1 cuda status: %s\n",hipGetErrorString(code1));
#endif
//outflow
InviscidBC_gpu_kernel2<<<gridSize, blockSize>>>(d_lglel,d_fatface,d_cbc,d_xm1,d_ym1,d_zm1,d_vx,d_vy,d_vz,d_t,d_pr,d_sii,d_siii,d_vdiff,d_vtrans,d_cb,d_u,d_phig,d_csound,d_unx,d_uny,d_unz,molarmass[0],iwm[0],iwp[0],irho[0],iux[0],iuy[0],iuz[0],iph[0],ipr[0],isnd[0],ithm[0],icpf[0],icvf[0],iu1[0],iu2[0],iu3[0],iu4[0],iu5[0],lx1[0],lz1[0],lxz,ldim[0],lxz2ldim,nxyz,lxy,lxz2ldimlelt,ntot,toteq[0],e_offset,p0th[0],ifield[0],ltot, icv[0],icp[0],imu[0],ilam[0],molmass[0],nlel,npscal[0],if3d[0], ly1[0],outflsub[0], pinfty[0],d_fatface+iwp[0]-1, lelt[0]);
#ifdef DEBUGPRINT
hipDeviceSynchronize();
code1 = hipPeekAtLastError();
printf("CUDA:inviscidbc_gpu_wrapper after 2 cuda status: %s\n",hipGetErrorString(code1));
#endif
//wallbc_inviscid
InviscidBC_gpu_kernel3<<<gridSize, blockSize>>>(d_lglel,d_fatface,d_cbc,d_xm1,d_ym1,d_zm1,d_vx,d_vy,d_vz,d_t,d_pr,d_sii,d_siii,d_vdiff,d_vtrans,d_cb,d_u,d_phig,d_csound,d_unx,d_uny,d_unz,molarmass[0],iwm[0],iwp[0],irho[0],iux[0],iuy[0],iuz[0],iph[0],ipr[0],isnd[0],ithm[0],icpf[0],icvf[0],iu1[0],iu2[0],iu3[0],iu4[0],iu5[0],lx1[0],lz1[0],lxz,ldim[0],lxz2ldim,nxyz,lxy,lxz2ldimlelt,ntot,toteq[0],e_offset,p0th[0],ifield[0],ltot, icv[0],icp[0],imu[0],ilam[0],molmass[0],nlel,npscal[0],if3d[0], ly1[0],outflsub[0], pinfty[0], lelt[0]);
#ifdef DEBUGPRINT
hipDeviceSynchronize();
hipError_t code2 = hipPeekAtLastError();
printf("CUDA: End nviscidbc_gpu_wrapper cuda status: %s\n",hipGetErrorString(code2));
#endif
} |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__constant__ float *c_Kernel;
__global__ void convolutionRowsKernel_down_smp( float *d_Dst, float *d_Src, int imageW, int n_imageW, int imageH, int filter_Rad, int Halo_steps )
{
extern __shared__ float s_Data[];
//Offset to the left halo edge
const int baseX = (blockIdx.x * 2 * ROWS_RESULT_STEPS - Halo_steps) * ROWS_BLOCKDIM_X + threadIdx.x;
const int baseX1 = (blockIdx.x * ROWS_RESULT_STEPS) * ROWS_BLOCKDIM_X + threadIdx.x;
const int baseY = blockIdx.y * ROWS_BLOCKDIM_Y + threadIdx.y;
if (baseY < imageH)
{
d_Src += baseY * imageW + baseX;
d_Dst += baseY * n_imageW + baseX1;
//Load left halo
#pragma unroll
for (int i = 0; i < Halo_steps; ++i)
{
s_Data[(threadIdx.y*(2 * ROWS_RESULT_STEPS + 2 * Halo_steps)*ROWS_BLOCKDIM_X) + threadIdx.x + i * ROWS_BLOCKDIM_X] = (baseX + i * ROWS_BLOCKDIM_X >= 0) ? d_Src[i * ROWS_BLOCKDIM_X] : 0;
}
//Load right halo and main data
#pragma unroll
for (int i = Halo_steps; i < Halo_steps + 2 * ROWS_RESULT_STEPS + Halo_steps; ++i)
{
s_Data[(threadIdx.y*(2 * ROWS_RESULT_STEPS + 2 * Halo_steps)*ROWS_BLOCKDIM_X) + threadIdx.x + i * ROWS_BLOCKDIM_X] = (baseX + i * ROWS_BLOCKDIM_X < imageW) ? d_Src[i * ROWS_BLOCKDIM_X] : 0;
}
//Compute and store results
__syncthreads();
#pragma unroll
for (int i = 0; i < ROWS_RESULT_STEPS; ++i)
{
float sum = 0;
if (baseX1 + i * ROWS_BLOCKDIM_X < n_imageW)
{
#pragma unroll
for (int j = -filter_Rad; j <= filter_Rad; ++j)
{
sum += c_Kernel[filter_Rad - j] * s_Data[(threadIdx.y*(2 * ROWS_RESULT_STEPS + 2 * Halo_steps)*ROWS_BLOCKDIM_X) + (Halo_steps + 2 * i) * ROWS_BLOCKDIM_X + threadIdx.x * 2 + j];
}
d_Dst[i * ROWS_BLOCKDIM_X] = sum;
}
}
}
} | .file "tmpxft_00164604_00000000-6_convolutionRowsKernel_down_smp.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z57__device_stub__Z30convolutionRowsKernel_down_smpPfS_iiiiiPfS_iiiii
.type _Z57__device_stub__Z30convolutionRowsKernel_down_smpPfS_iiiiiPfS_iiiii, @function
_Z57__device_stub__Z30convolutionRowsKernel_down_smpPfS_iiiiiPfS_iiiii:
.LFB2051:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movl %r9d, (%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
movq %rsp, %rax
movq %rax, 136(%rsp)
leaq 176(%rsp), %rax
movq %rax, 144(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 184
pushq 40(%rsp)
.cfi_def_cfa_offset 192
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z30convolutionRowsKernel_down_smpPfS_iiiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z57__device_stub__Z30convolutionRowsKernel_down_smpPfS_iiiiiPfS_iiiii, .-_Z57__device_stub__Z30convolutionRowsKernel_down_smpPfS_iiiiiPfS_iiiii
.globl _Z30convolutionRowsKernel_down_smpPfS_iiiii
.type _Z30convolutionRowsKernel_down_smpPfS_iiiii, @function
_Z30convolutionRowsKernel_down_smpPfS_iiiii:
.LFB2052:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
call _Z57__device_stub__Z30convolutionRowsKernel_down_smpPfS_iiiiiPfS_iiiii
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z30convolutionRowsKernel_down_smpPfS_iiiii, .-_Z30convolutionRowsKernel_down_smpPfS_iiiii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z30convolutionRowsKernel_down_smpPfS_iiiii"
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "c_Kernel"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z30convolutionRowsKernel_down_smpPfS_iiiii(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $8, %r9d
movl $0, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _ZL8c_Kernel(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL8c_Kernel
.comm _ZL8c_Kernel,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__constant__ float *c_Kernel;
__global__ void convolutionRowsKernel_down_smp( float *d_Dst, float *d_Src, int imageW, int n_imageW, int imageH, int filter_Rad, int Halo_steps )
{
extern __shared__ float s_Data[];
//Offset to the left halo edge
const int baseX = (blockIdx.x * 2 * ROWS_RESULT_STEPS - Halo_steps) * ROWS_BLOCKDIM_X + threadIdx.x;
const int baseX1 = (blockIdx.x * ROWS_RESULT_STEPS) * ROWS_BLOCKDIM_X + threadIdx.x;
const int baseY = blockIdx.y * ROWS_BLOCKDIM_Y + threadIdx.y;
if (baseY < imageH)
{
d_Src += baseY * imageW + baseX;
d_Dst += baseY * n_imageW + baseX1;
//Load left halo
#pragma unroll
for (int i = 0; i < Halo_steps; ++i)
{
s_Data[(threadIdx.y*(2 * ROWS_RESULT_STEPS + 2 * Halo_steps)*ROWS_BLOCKDIM_X) + threadIdx.x + i * ROWS_BLOCKDIM_X] = (baseX + i * ROWS_BLOCKDIM_X >= 0) ? d_Src[i * ROWS_BLOCKDIM_X] : 0;
}
//Load right halo and main data
#pragma unroll
for (int i = Halo_steps; i < Halo_steps + 2 * ROWS_RESULT_STEPS + Halo_steps; ++i)
{
s_Data[(threadIdx.y*(2 * ROWS_RESULT_STEPS + 2 * Halo_steps)*ROWS_BLOCKDIM_X) + threadIdx.x + i * ROWS_BLOCKDIM_X] = (baseX + i * ROWS_BLOCKDIM_X < imageW) ? d_Src[i * ROWS_BLOCKDIM_X] : 0;
}
//Compute and store results
__syncthreads();
#pragma unroll
for (int i = 0; i < ROWS_RESULT_STEPS; ++i)
{
float sum = 0;
if (baseX1 + i * ROWS_BLOCKDIM_X < n_imageW)
{
#pragma unroll
for (int j = -filter_Rad; j <= filter_Rad; ++j)
{
sum += c_Kernel[filter_Rad - j] * s_Data[(threadIdx.y*(2 * ROWS_RESULT_STEPS + 2 * Halo_steps)*ROWS_BLOCKDIM_X) + (Halo_steps + 2 * i) * ROWS_BLOCKDIM_X + threadIdx.x * 2 + j];
}
d_Dst[i * ROWS_BLOCKDIM_X] = sum;
}
}
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__constant__ float *c_Kernel;
__global__ void convolutionRowsKernel_down_smp( float *d_Dst, float *d_Src, int imageW, int n_imageW, int imageH, int filter_Rad, int Halo_steps )
{
extern __shared__ float s_Data[];
//Offset to the left halo edge
const int baseX = (blockIdx.x * 2 * ROWS_RESULT_STEPS - Halo_steps) * ROWS_BLOCKDIM_X + threadIdx.x;
const int baseX1 = (blockIdx.x * ROWS_RESULT_STEPS) * ROWS_BLOCKDIM_X + threadIdx.x;
const int baseY = blockIdx.y * ROWS_BLOCKDIM_Y + threadIdx.y;
if (baseY < imageH)
{
d_Src += baseY * imageW + baseX;
d_Dst += baseY * n_imageW + baseX1;
//Load left halo
#pragma unroll
for (int i = 0; i < Halo_steps; ++i)
{
s_Data[(threadIdx.y*(2 * ROWS_RESULT_STEPS + 2 * Halo_steps)*ROWS_BLOCKDIM_X) + threadIdx.x + i * ROWS_BLOCKDIM_X] = (baseX + i * ROWS_BLOCKDIM_X >= 0) ? d_Src[i * ROWS_BLOCKDIM_X] : 0;
}
//Load right halo and main data
#pragma unroll
for (int i = Halo_steps; i < Halo_steps + 2 * ROWS_RESULT_STEPS + Halo_steps; ++i)
{
s_Data[(threadIdx.y*(2 * ROWS_RESULT_STEPS + 2 * Halo_steps)*ROWS_BLOCKDIM_X) + threadIdx.x + i * ROWS_BLOCKDIM_X] = (baseX + i * ROWS_BLOCKDIM_X < imageW) ? d_Src[i * ROWS_BLOCKDIM_X] : 0;
}
//Compute and store results
__syncthreads();
#pragma unroll
for (int i = 0; i < ROWS_RESULT_STEPS; ++i)
{
float sum = 0;
if (baseX1 + i * ROWS_BLOCKDIM_X < n_imageW)
{
#pragma unroll
for (int j = -filter_Rad; j <= filter_Rad; ++j)
{
sum += c_Kernel[filter_Rad - j] * s_Data[(threadIdx.y*(2 * ROWS_RESULT_STEPS + 2 * Halo_steps)*ROWS_BLOCKDIM_X) + (Halo_steps + 2 * i) * ROWS_BLOCKDIM_X + threadIdx.x * 2 + j];
}
d_Dst[i * ROWS_BLOCKDIM_X] = sum;
}
}
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__constant__ float *c_Kernel;
__global__ void convolutionRowsKernel_down_smp( float *d_Dst, float *d_Src, int imageW, int n_imageW, int imageH, int filter_Rad, int Halo_steps )
{
extern __shared__ float s_Data[];
//Offset to the left halo edge
const int baseX = (blockIdx.x * 2 * ROWS_RESULT_STEPS - Halo_steps) * ROWS_BLOCKDIM_X + threadIdx.x;
const int baseX1 = (blockIdx.x * ROWS_RESULT_STEPS) * ROWS_BLOCKDIM_X + threadIdx.x;
const int baseY = blockIdx.y * ROWS_BLOCKDIM_Y + threadIdx.y;
if (baseY < imageH)
{
d_Src += baseY * imageW + baseX;
d_Dst += baseY * n_imageW + baseX1;
//Load left halo
#pragma unroll
for (int i = 0; i < Halo_steps; ++i)
{
s_Data[(threadIdx.y*(2 * ROWS_RESULT_STEPS + 2 * Halo_steps)*ROWS_BLOCKDIM_X) + threadIdx.x + i * ROWS_BLOCKDIM_X] = (baseX + i * ROWS_BLOCKDIM_X >= 0) ? d_Src[i * ROWS_BLOCKDIM_X] : 0;
}
//Load right halo and main data
#pragma unroll
for (int i = Halo_steps; i < Halo_steps + 2 * ROWS_RESULT_STEPS + Halo_steps; ++i)
{
s_Data[(threadIdx.y*(2 * ROWS_RESULT_STEPS + 2 * Halo_steps)*ROWS_BLOCKDIM_X) + threadIdx.x + i * ROWS_BLOCKDIM_X] = (baseX + i * ROWS_BLOCKDIM_X < imageW) ? d_Src[i * ROWS_BLOCKDIM_X] : 0;
}
//Compute and store results
__syncthreads();
#pragma unroll
for (int i = 0; i < ROWS_RESULT_STEPS; ++i)
{
float sum = 0;
if (baseX1 + i * ROWS_BLOCKDIM_X < n_imageW)
{
#pragma unroll
for (int j = -filter_Rad; j <= filter_Rad; ++j)
{
sum += c_Kernel[filter_Rad - j] * s_Data[(threadIdx.y*(2 * ROWS_RESULT_STEPS + 2 * Halo_steps)*ROWS_BLOCKDIM_X) + (Halo_steps + 2 * i) * ROWS_BLOCKDIM_X + threadIdx.x * 2 + j];
}
d_Dst[i * ROWS_BLOCKDIM_X] = sum;
}
}
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z30convolutionRowsKernel_down_smpPfS_iiiii
.globl _Z30convolutionRowsKernel_down_smpPfS_iiiii
.p2align 8
.type _Z30convolutionRowsKernel_down_smpPfS_iiiii,@function
_Z30convolutionRowsKernel_down_smpPfS_iiiii:
s_load_b32 s2, s[0:1], 0x18
v_bfe_u32 v3, v0, 10, 10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshl_add_u32 v5, s15, 2, v3
s_waitcnt lgkmcnt(0)
v_cmp_gt_i32_e32 vcc_lo, s2, v5
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_72
s_clause 0x1
s_load_b32 s8, s[0:1], 0x20
s_load_b32 s10, s[0:1], 0x10
v_and_b32_e32 v4, 0x3ff, v0
s_lshl_b32 s11, s14, 7
s_waitcnt lgkmcnt(0)
s_lshl_b32 s9, s8, 4
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
s_sub_i32 s2, s11, s9
s_cmp_lt_i32 s8, 1
v_add_nc_u32_e32 v0, s2, v4
s_load_b64 s[2:3], s[0:1], 0x8
v_mad_u64_u32 v[1:2], null, v5, s10, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[6:7], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v6, vcc_lo, s2, v6
v_add_co_ci_u32_e32 v7, vcc_lo, s3, v7, vcc_lo
s_cbranch_scc1 .LBB0_26
s_lshl_b32 s4, s8, 1
v_not_b32_e32 v8, v0
s_add_i32 s4, s4, 8
s_cmp_lt_u32 s8, 8
v_mul_lo_u32 v9, v3, s4
s_mov_b32 s12, 0
s_cbranch_scc1 .LBB0_21
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
v_lshlrev_b32_e32 v10, 6, v9
v_lshlrev_b32_e32 v11, 2, v4
s_and_b32 s13, s8, 0x7ffffff8
s_mov_b32 s5, 0
s_movk_i32 s6, 0x70
v_add3_u32 v10, v10, v11, 0
s_branch .LBB0_5
.LBB0_4:
s_or_b32 exec_lo, exec_lo, s4
s_waitcnt vmcnt(0)
ds_store_b32 v10, v11 offset:448
v_add_nc_u32_e32 v10, 0x200, v10
s_add_i32 s12, s12, 8
s_addk_i32 s6, 0x80
s_cmp_eq_u32 s13, s12
s_cbranch_scc1 .LBB0_21
.LBB0_5:
v_dual_mov_b32 v12, 0 :: v_dual_mov_b32 v11, 0
s_add_i32 s4, s6, 0xffffff90
s_mov_b32 s7, exec_lo
v_cmpx_gt_i32_e64 s4, v8
s_cbranch_execz .LBB0_7
s_lshl_b64 s[16:17], s[4:5], 2
s_delay_alu instid0(SALU_CYCLE_1)
v_add_co_u32 v13, vcc_lo, v6, s16
v_add_co_ci_u32_e32 v14, vcc_lo, s17, v7, vcc_lo
global_load_b32 v11, v[13:14], off
.LBB0_7:
s_or_b32 exec_lo, exec_lo, s7
s_add_i32 s4, s6, 0xffffffa0
s_mov_b32 s7, exec_lo
s_waitcnt vmcnt(0)
ds_store_b32 v10, v11
v_cmpx_gt_i32_e64 s4, v8
s_cbranch_execz .LBB0_9
s_lshl_b64 s[16:17], s[4:5], 2
s_delay_alu instid0(SALU_CYCLE_1)
v_add_co_u32 v11, vcc_lo, v6, s16
v_add_co_ci_u32_e32 v12, vcc_lo, s17, v7, vcc_lo
global_load_b32 v12, v[11:12], off
.LBB0_9:
s_or_b32 exec_lo, exec_lo, s7
v_mov_b32_e32 v11, 0
v_mov_b32_e32 v13, 0
s_add_i32 s4, s6, 0xffffffb0
s_mov_b32 s7, exec_lo
s_waitcnt vmcnt(0)
ds_store_b32 v10, v12 offset:64
v_cmpx_gt_i32_e64 s4, v8
s_cbranch_execz .LBB0_11
s_lshl_b64 s[16:17], s[4:5], 2
s_delay_alu instid0(SALU_CYCLE_1)
v_add_co_u32 v12, vcc_lo, v6, s16
v_add_co_ci_u32_e32 v13, vcc_lo, s17, v7, vcc_lo
global_load_b32 v13, v[12:13], off
.LBB0_11:
s_or_b32 exec_lo, exec_lo, s7
s_sub_i32 s4, s6, 64
s_mov_b32 s7, exec_lo
s_waitcnt vmcnt(0)
ds_store_b32 v10, v13 offset:128
v_cmpx_gt_i32_e64 s4, v8
s_cbranch_execz .LBB0_13
s_lshl_b64 s[16:17], s[4:5], 2
s_delay_alu instid0(SALU_CYCLE_1)
v_add_co_u32 v11, vcc_lo, v6, s16
v_add_co_ci_u32_e32 v12, vcc_lo, s17, v7, vcc_lo
global_load_b32 v11, v[11:12], off
.LBB0_13:
s_or_b32 exec_lo, exec_lo, s7
v_dual_mov_b32 v12, 0 :: v_dual_mov_b32 v13, 0
s_sub_i32 s4, s6, 48
s_mov_b32 s7, exec_lo
s_waitcnt vmcnt(0)
ds_store_b32 v10, v11 offset:192
v_cmpx_gt_i32_e64 s4, v8
s_cbranch_execz .LBB0_15
s_lshl_b64 s[16:17], s[4:5], 2
s_delay_alu instid0(SALU_CYCLE_1)
v_add_co_u32 v13, vcc_lo, v6, s16
v_add_co_ci_u32_e32 v14, vcc_lo, s17, v7, vcc_lo
global_load_b32 v13, v[13:14], off
.LBB0_15:
s_or_b32 exec_lo, exec_lo, s7
s_sub_i32 s4, s6, 32
s_mov_b32 s7, exec_lo
s_waitcnt vmcnt(0)
ds_store_b32 v10, v13 offset:256
v_cmpx_gt_i32_e64 s4, v8
s_cbranch_execz .LBB0_17
s_lshl_b64 s[16:17], s[4:5], 2
s_delay_alu instid0(SALU_CYCLE_1)
v_add_co_u32 v11, vcc_lo, v6, s16
v_add_co_ci_u32_e32 v12, vcc_lo, s17, v7, vcc_lo
global_load_b32 v12, v[11:12], off
.LBB0_17:
s_or_b32 exec_lo, exec_lo, s7
v_mov_b32_e32 v11, 0
v_mov_b32_e32 v13, 0
s_add_i32 s4, s6, -16
s_mov_b32 s7, exec_lo
s_waitcnt vmcnt(0)
ds_store_b32 v10, v12 offset:320
v_cmpx_gt_i32_e64 s4, v8
s_cbranch_execz .LBB0_19
s_lshl_b64 s[16:17], s[4:5], 2
s_delay_alu instid0(SALU_CYCLE_1)
v_add_co_u32 v12, vcc_lo, v6, s16
v_add_co_ci_u32_e32 v13, vcc_lo, s17, v7, vcc_lo
global_load_b32 v13, v[12:13], off
.LBB0_19:
s_or_b32 exec_lo, exec_lo, s7
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 s4, exec_lo
s_waitcnt vmcnt(0)
ds_store_b32 v10, v13 offset:384
v_cmpx_gt_i32_e64 s6, v8
s_cbranch_execz .LBB0_4
s_mov_b32 s7, s5
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_lshl_b64 s[16:17], s[6:7], 2
v_add_co_u32 v11, vcc_lo, v6, s16
v_add_co_ci_u32_e32 v12, vcc_lo, s17, v7, vcc_lo
global_load_b32 v11, v[11:12], off
s_branch .LBB0_4
.LBB0_21:
s_and_b32 s6, s8, 7
s_mov_b32 s5, 0
s_cmp_eq_u32 s6, 0
s_cbranch_scc1 .LBB0_26
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
v_lshlrev_b32_e32 v9, 4, v9
s_lshl_b32 s4, s12, 4
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_lshl_b64 s[12:13], s[4:5], 2
s_add_u32 s2, s2, s12
v_add3_u32 v9, v4, v9, s4
s_addc_u32 s3, s3, s13
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_u32 v1, vcc_lo, s2, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s3, v2, vcc_lo
v_lshl_add_u32 v9, v9, 2, 0
s_branch .LBB0_24
.p2align 6
.LBB0_23:
s_or_b32 exec_lo, exec_lo, s2
v_add_co_u32 v1, vcc_lo, v1, 64
s_waitcnt vmcnt(0)
ds_store_b32 v9, v10
v_add_nc_u32_e32 v9, 64, v9
v_add_co_ci_u32_e32 v2, vcc_lo, 0, v2, vcc_lo
s_add_i32 s6, s6, -1
s_add_i32 s4, s4, 16
s_cmp_lg_u32 s6, 0
s_cbranch_scc0 .LBB0_26
.LBB0_24:
v_mov_b32_e32 v10, 0
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s4, v8
s_cbranch_execz .LBB0_23
global_load_b32 v10, v[1:2], off
s_branch .LBB0_23
.LBB0_26:
s_lshl_b32 s5, s8, 1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s4, s5, 8
s_cmp_le_i32 s4, s8
s_cbranch_scc1 .LBB0_52
s_and_b32 s7, s8, 7
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s7, 0
s_cbranch_scc1 .LBB0_32
v_mul_lo_u32 v1, v3, s4
v_add_nc_u32_e32 v2, s11, v4
s_add_i32 s6, s8, s7
s_mov_b32 s2, s9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b32_e32 v1, 4, v1
v_add3_u32 v1, v4, v1, s9
s_delay_alu instid0(VALU_DEP_1)
v_lshl_add_u32 v1, v1, 2, 0
s_branch .LBB0_30
.p2align 6
.LBB0_29:
s_or_b32 exec_lo, exec_lo, s11
s_waitcnt vmcnt(0)
ds_store_b32 v1, v8
v_add_nc_u32_e32 v1, 64, v1
v_add_nc_u32_e32 v2, 16, v2
s_add_i32 s7, s7, -1
s_add_i32 s2, s2, 16
s_cmp_lg_u32 s7, 0
s_cbranch_scc0 .LBB0_33
.LBB0_30:
v_mov_b32_e32 v8, 0
s_mov_b32 s11, exec_lo
v_cmpx_gt_i32_e64 s10, v2
s_cbranch_execz .LBB0_29
s_ashr_i32 s3, s2, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_lshl_b64 s[12:13], s[2:3], 2
v_add_co_u32 v8, vcc_lo, v6, s12
v_add_co_ci_u32_e32 v9, vcc_lo, s13, v7, vcc_lo
global_load_b32 v8, v[8:9], off
s_branch .LBB0_29
.LBB0_32:
s_mov_b32 s6, s8
.LBB0_33:
s_cmp_gt_u32 s8, -8
s_cbranch_scc1 .LBB0_52
v_mul_lo_u32 v1, v3, s4
v_lshlrev_b32_e32 v2, 2, v4
s_lshl_b32 s3, s6, 6
s_sub_i32 s2, s6, s5
s_mov_b32 s5, 0
s_add_i32 s2, s2, -8
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b32_e32 v1, 6, v1
v_add3_u32 v1, v1, s3, v2
s_lshl_b32 s3, s6, 4
s_mov_b32 s6, 0
s_branch .LBB0_36
.LBB0_35:
s_or_b32 exec_lo, exec_lo, s7
v_add_nc_u32_e32 v0, 0x80, v0
s_add_i32 s2, s2, 8
s_addk_i32 s5, 0x80
s_addk_i32 s6, 0x200
s_cmp_eq_u32 s2, 0
s_waitcnt vmcnt(0)
ds_store_b32 v2, v9 offset:448
s_cbranch_scc1 .LBB0_52
.LBB0_36:
v_dual_mov_b32 v9, 0 :: v_dual_add_nc_u32 v2, s3, v0
v_mov_b32_e32 v8, 0
s_mov_b32 s7, exec_lo
s_delay_alu instid0(VALU_DEP_2)
v_cmpx_gt_i32_e64 s10, v2
s_cbranch_execz .LBB0_38
s_add_i32 s12, s3, s5
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_ashr_i32 s13, s12, 31
s_lshl_b64 s[12:13], s[12:13], 2
s_delay_alu instid0(SALU_CYCLE_1)
v_add_co_u32 v9, vcc_lo, v6, s12
v_add_co_ci_u32_e32 v10, vcc_lo, s13, v7, vcc_lo
global_load_b32 v9, v[9:10], off
.LBB0_38:
s_or_b32 exec_lo, exec_lo, s7
v_add3_u32 v10, s3, v0, 16
v_add_nc_u32_e32 v2, s6, v1
s_mov_b32 s7, exec_lo
s_waitcnt vmcnt(0)
ds_store_b32 v2, v9
v_cmpx_gt_i32_e64 s10, v10
s_cbranch_execz .LBB0_40
s_add_i32 s11, s3, s5
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s12, s11, 16
s_ashr_i32 s13, s12, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_lshl_b64 s[12:13], s[12:13], 2
v_add_co_u32 v8, vcc_lo, v6, s12
v_add_co_ci_u32_e32 v9, vcc_lo, s13, v7, vcc_lo
global_load_b32 v8, v[8:9], off
.LBB0_40:
s_or_b32 exec_lo, exec_lo, s7
v_add3_u32 v10, s3, v0, 32
v_mov_b32_e32 v9, 0
s_waitcnt vmcnt(0)
ds_store_b32 v2, v8 offset:64
v_cmp_gt_i32_e32 vcc_lo, s10, v10
v_mov_b32_e32 v10, 0
s_and_saveexec_b32 s7, vcc_lo
s_cbranch_execz .LBB0_42
s_add_i32 s11, s3, s5
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s12, s11, 32
s_ashr_i32 s13, s12, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_lshl_b64 s[12:13], s[12:13], 2
v_add_co_u32 v10, vcc_lo, v6, s12
v_add_co_ci_u32_e32 v11, vcc_lo, s13, v7, vcc_lo
global_load_b32 v10, v[10:11], off
.LBB0_42:
s_or_b32 exec_lo, exec_lo, s7
v_add3_u32 v8, s3, v0, 48
s_mov_b32 s7, exec_lo
s_waitcnt vmcnt(0)
ds_store_b32 v2, v10 offset:128
v_cmpx_gt_i32_e64 s10, v8
s_cbranch_execz .LBB0_44
s_add_i32 s11, s3, s5
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s12, s11, 48
s_ashr_i32 s13, s12, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_lshl_b64 s[12:13], s[12:13], 2
v_add_co_u32 v8, vcc_lo, v6, s12
v_add_co_ci_u32_e32 v9, vcc_lo, s13, v7, vcc_lo
global_load_b32 v9, v[8:9], off
.LBB0_44:
s_or_b32 exec_lo, exec_lo, s7
v_add3_u32 v10, s3, v0, 64
v_mov_b32_e32 v8, 0
s_waitcnt vmcnt(0)
ds_store_b32 v2, v9 offset:192
v_cmp_gt_i32_e32 vcc_lo, s10, v10
v_mov_b32_e32 v10, 0
s_and_saveexec_b32 s7, vcc_lo
s_cbranch_execz .LBB0_46
s_add_i32 s11, s3, s5
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s12, s11, 64
s_ashr_i32 s13, s12, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_lshl_b64 s[12:13], s[12:13], 2
v_add_co_u32 v9, vcc_lo, v6, s12
v_add_co_ci_u32_e32 v10, vcc_lo, s13, v7, vcc_lo
global_load_b32 v10, v[9:10], off
.LBB0_46:
s_or_b32 exec_lo, exec_lo, s7
v_add3_u32 v9, s3, v0, 0x50
s_mov_b32 s7, exec_lo
s_waitcnt vmcnt(0)
ds_store_b32 v2, v10 offset:256
v_cmpx_gt_i32_e64 s10, v9
s_cbranch_execz .LBB0_48
s_add_i32 s11, s3, s5
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s12, s11, 0x50
s_ashr_i32 s13, s12, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_lshl_b64 s[12:13], s[12:13], 2
v_add_co_u32 v8, vcc_lo, v6, s12
v_add_co_ci_u32_e32 v9, vcc_lo, s13, v7, vcc_lo
global_load_b32 v8, v[8:9], off
.LBB0_48:
s_or_b32 exec_lo, exec_lo, s7
v_add3_u32 v10, s3, v0, 0x60
v_mov_b32_e32 v9, 0
s_waitcnt vmcnt(0)
ds_store_b32 v2, v8 offset:320
v_cmp_gt_i32_e32 vcc_lo, s10, v10
v_mov_b32_e32 v10, 0
s_and_saveexec_b32 s7, vcc_lo
s_cbranch_execz .LBB0_50
s_add_i32 s11, s3, s5
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s12, s11, 0x60
s_ashr_i32 s13, s12, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_lshl_b64 s[12:13], s[12:13], 2
v_add_co_u32 v10, vcc_lo, v6, s12
v_add_co_ci_u32_e32 v11, vcc_lo, s13, v7, vcc_lo
global_load_b32 v10, v[10:11], off
.LBB0_50:
s_or_b32 exec_lo, exec_lo, s7
v_add3_u32 v8, s3, v0, 0x70
s_mov_b32 s7, exec_lo
s_waitcnt vmcnt(0)
ds_store_b32 v2, v10 offset:384
v_cmpx_gt_i32_e64 s10, v8
s_cbranch_execz .LBB0_35
s_add_i32 s11, s3, s5
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s12, s11, 0x70
s_ashr_i32 s13, s12, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_lshl_b64 s[12:13], s[12:13], 2
v_add_co_u32 v8, vcc_lo, v6, s12
v_add_co_ci_u32_e32 v9, vcc_lo, s13, v7, vcc_lo
global_load_b32 v9, v[8:9], off
s_branch .LBB0_35
.LBB0_52:
s_clause 0x1
s_load_b32 s5, s[0:1], 0x1c
s_load_b32 s6, s[0:1], 0x14
v_lshl_add_u32 v2, s14, 6, v4
s_load_b64 s[10:11], s[0:1], 0x0
s_mov_b32 s7, exec_lo
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cmp_gt_i32 s5, -1
v_mad_u64_u32 v[0:1], null, v5, s6, v[2:3]
s_cselect_b32 s2, -1, 0
s_getpc_b64 s[0:1]
s_add_u32 s0, s0, c_Kernel@rel32@lo+4
s_addc_u32 s1, s1, c_Kernel@rel32@hi+12
v_cndmask_b32_e64 v5, 0, 1, s2
s_load_b64 s[0:1], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s10, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s11, v1, vcc_lo
v_cmpx_gt_i32_e64 s6, v2
s_cbranch_execz .LBB0_57
v_mov_b32_e32 v6, 0
s_and_not1_b32 vcc_lo, exec_lo, s2
s_cbranch_vccnz .LBB0_56
v_mul_lo_u32 v6, v3, s4
v_lshlrev_b32_e32 v7, 1, v4
s_lshl_b32 s2, s5, 1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b32_e32 v6, 4, v6
v_add3_u32 v6, v6, s9, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_subrev_nc_u32_e32 v6, s5, v6
v_lshl_add_u32 v7, v6, 2, 0
v_mov_b32_e32 v6, 0
.LBB0_55:
s_ashr_i32 s3, s2, 31
ds_load_b32 v8, v7
s_lshl_b64 s[10:11], s[2:3], 2
s_waitcnt lgkmcnt(0)
s_add_u32 s10, s0, s10
s_addc_u32 s11, s1, s11
s_add_i32 s2, s2, -1
s_load_b32 s3, s[10:11], 0x0
v_add_nc_u32_e32 v7, 4, v7
s_cmp_eq_u32 s2, -1
s_waitcnt lgkmcnt(0)
v_fmac_f32_e32 v6, s3, v8
s_cbranch_scc0 .LBB0_55
.LBB0_56:
global_store_b32 v[0:1], v6, off
.LBB0_57:
s_or_b32 exec_lo, exec_lo, s7
v_add_nc_u32_e32 v6, 16, v2
s_mov_b32 s7, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s6, v6
s_cbranch_execz .LBB0_62
v_cmp_ne_u32_e32 vcc_lo, 1, v5
v_mov_b32_e32 v6, 0
s_cbranch_vccnz .LBB0_61
v_mul_lo_u32 v6, v3, s4
v_lshlrev_b32_e32 v7, 3, v4
s_lshl_b32 s2, s8, 6
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b32_e32 v6, 6, v6
v_add3_u32 v6, v6, s2, v7
v_mov_b32_e32 v7, 0
s_lshl_b32 s2, s5, 2
s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
v_subrev_nc_u32_e32 v6, s2, v6
s_lshl_b32 s2, s5, 1
s_delay_alu instid0(VALU_DEP_1)
v_add3_u32 v8, v6, 0, 0x80
v_mov_b32_e32 v6, 0
.LBB0_60:
s_ashr_i32 s3, s2, 31
ds_load_b32 v10, v8
s_lshl_b64 s[10:11], s[2:3], 2
v_add_nc_u32_e32 v8, 4, v8
s_waitcnt lgkmcnt(0)
s_add_u32 s10, s0, s10
s_addc_u32 s11, s1, s11
s_add_i32 s2, s2, -1
global_load_b32 v9, v7, s[10:11]
s_cmp_lg_u32 s2, -1
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v6, v9, v10
s_cbranch_scc1 .LBB0_60
.LBB0_61:
global_store_b32 v[0:1], v6, off offset:64
.LBB0_62:
s_or_b32 exec_lo, exec_lo, s7
v_add_nc_u32_e32 v6, 32, v2
s_mov_b32 s7, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s6, v6
s_cbranch_execz .LBB0_67
v_cmp_ne_u32_e32 vcc_lo, 1, v5
v_mov_b32_e32 v6, 0
s_cbranch_vccnz .LBB0_66
v_mul_lo_u32 v6, v3, s4
v_lshlrev_b32_e32 v7, 3, v4
s_lshl_b32 s2, s8, 6
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b32_e32 v6, 6, v6
v_add3_u32 v6, v6, s2, v7
v_mov_b32_e32 v7, 0
s_lshl_b32 s2, s5, 2
s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
v_subrev_nc_u32_e32 v6, s2, v6
s_lshl_b32 s2, s5, 1
s_delay_alu instid0(VALU_DEP_1)
v_add3_u32 v8, v6, 0, 0x100
v_mov_b32_e32 v6, 0
.LBB0_65:
s_ashr_i32 s3, s2, 31
ds_load_b32 v10, v8
s_lshl_b64 s[10:11], s[2:3], 2
v_add_nc_u32_e32 v8, 4, v8
s_waitcnt lgkmcnt(0)
s_add_u32 s10, s0, s10
s_addc_u32 s11, s1, s11
s_add_i32 s2, s2, -1
global_load_b32 v9, v7, s[10:11]
s_cmp_lg_u32 s2, -1
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v6, v9, v10
s_cbranch_scc1 .LBB0_65
.LBB0_66:
global_store_b32 v[0:1], v6, off offset:128
.LBB0_67:
s_or_b32 exec_lo, exec_lo, s7
v_add_nc_u32_e32 v2, 48, v2
s_delay_alu instid0(VALU_DEP_1)
v_cmp_gt_i32_e32 vcc_lo, s6, v2
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_72
v_cmp_ne_u32_e32 vcc_lo, 1, v5
v_mov_b32_e32 v2, 0
s_cbranch_vccnz .LBB0_71
v_mul_lo_u32 v2, v3, s4
v_lshlrev_b32_e32 v3, 3, v4
s_lshl_b32 s2, s8, 6
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b32_e32 v2, 6, v2
v_add3_u32 v2, v2, s2, v3
v_mov_b32_e32 v3, 0
s_lshl_b32 s2, s5, 2
s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
v_subrev_nc_u32_e32 v2, s2, v2
s_lshl_b32 s2, s5, 1
s_delay_alu instid0(VALU_DEP_1)
v_add3_u32 v4, v2, 0, 0x180
v_mov_b32_e32 v2, 0
.LBB0_70:
s_ashr_i32 s3, s2, 31
ds_load_b32 v6, v4
s_lshl_b64 s[4:5], s[2:3], 2
v_add_nc_u32_e32 v4, 4, v4
s_waitcnt lgkmcnt(0)
s_add_u32 s4, s0, s4
s_addc_u32 s5, s1, s5
s_add_i32 s2, s2, -1
global_load_b32 v5, v3, s[4:5]
s_cmp_lg_u32 s2, -1
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v2, v5, v6
s_cbranch_scc1 .LBB0_70
.LBB0_71:
global_store_b32 v[0:1], v2, off offset:192
.LBB0_72:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z30convolutionRowsKernel_down_smpPfS_iiiii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 36
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 15
.amdhsa_next_free_sgpr 18
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z30convolutionRowsKernel_down_smpPfS_iiiii, .Lfunc_end0-_Z30convolutionRowsKernel_down_smpPfS_iiiii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.protected c_Kernel
.type c_Kernel,@object
.section .bss,"aw",@nobits
.globl c_Kernel
.p2align 3, 0x0
c_Kernel:
.quad 0
.size c_Kernel, 8
.type __hip_cuid_,@object
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym c_Kernel
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 36
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z30convolutionRowsKernel_down_smpPfS_iiiii
.private_segment_fixed_size: 0
.sgpr_count: 20
.sgpr_spill_count: 0
.symbol: _Z30convolutionRowsKernel_down_smpPfS_iiiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 15
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__constant__ float *c_Kernel;
__global__ void convolutionRowsKernel_down_smp( float *d_Dst, float *d_Src, int imageW, int n_imageW, int imageH, int filter_Rad, int Halo_steps )
{
extern __shared__ float s_Data[];
//Offset to the left halo edge
const int baseX = (blockIdx.x * 2 * ROWS_RESULT_STEPS - Halo_steps) * ROWS_BLOCKDIM_X + threadIdx.x;
const int baseX1 = (blockIdx.x * ROWS_RESULT_STEPS) * ROWS_BLOCKDIM_X + threadIdx.x;
const int baseY = blockIdx.y * ROWS_BLOCKDIM_Y + threadIdx.y;
if (baseY < imageH)
{
d_Src += baseY * imageW + baseX;
d_Dst += baseY * n_imageW + baseX1;
//Load left halo
#pragma unroll
for (int i = 0; i < Halo_steps; ++i)
{
s_Data[(threadIdx.y*(2 * ROWS_RESULT_STEPS + 2 * Halo_steps)*ROWS_BLOCKDIM_X) + threadIdx.x + i * ROWS_BLOCKDIM_X] = (baseX + i * ROWS_BLOCKDIM_X >= 0) ? d_Src[i * ROWS_BLOCKDIM_X] : 0;
}
//Load right halo and main data
#pragma unroll
for (int i = Halo_steps; i < Halo_steps + 2 * ROWS_RESULT_STEPS + Halo_steps; ++i)
{
s_Data[(threadIdx.y*(2 * ROWS_RESULT_STEPS + 2 * Halo_steps)*ROWS_BLOCKDIM_X) + threadIdx.x + i * ROWS_BLOCKDIM_X] = (baseX + i * ROWS_BLOCKDIM_X < imageW) ? d_Src[i * ROWS_BLOCKDIM_X] : 0;
}
//Compute and store results
__syncthreads();
#pragma unroll
for (int i = 0; i < ROWS_RESULT_STEPS; ++i)
{
float sum = 0;
if (baseX1 + i * ROWS_BLOCKDIM_X < n_imageW)
{
#pragma unroll
for (int j = -filter_Rad; j <= filter_Rad; ++j)
{
sum += c_Kernel[filter_Rad - j] * s_Data[(threadIdx.y*(2 * ROWS_RESULT_STEPS + 2 * Halo_steps)*ROWS_BLOCKDIM_X) + (Halo_steps + 2 * i) * ROWS_BLOCKDIM_X + threadIdx.x * 2 + j];
}
d_Dst[i * ROWS_BLOCKDIM_X] = sum;
}
}
}
} | .text
.file "convolutionRowsKernel_down_smp.hip"
.globl _Z45__device_stub__convolutionRowsKernel_down_smpPfS_iiiii # -- Begin function _Z45__device_stub__convolutionRowsKernel_down_smpPfS_iiiii
.p2align 4, 0x90
.type _Z45__device_stub__convolutionRowsKernel_down_smpPfS_iiiii,@function
_Z45__device_stub__convolutionRowsKernel_down_smpPfS_iiiii: # @_Z45__device_stub__convolutionRowsKernel_down_smpPfS_iiiii
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movl %r9d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
leaq 144(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z30convolutionRowsKernel_down_smpPfS_iiiii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end0:
.size _Z45__device_stub__convolutionRowsKernel_down_smpPfS_iiiii, .Lfunc_end0-_Z45__device_stub__convolutionRowsKernel_down_smpPfS_iiiii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z30convolutionRowsKernel_down_smpPfS_iiiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $0, 8(%rsp)
movl $1, (%rsp)
movl $c_Kernel, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movl $8, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
callq __hipRegisterVar
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type c_Kernel,@object # @c_Kernel
.local c_Kernel
.comm c_Kernel,8,8
.type _Z30convolutionRowsKernel_down_smpPfS_iiiii,@object # @_Z30convolutionRowsKernel_down_smpPfS_iiiii
.section .rodata,"a",@progbits
.globl _Z30convolutionRowsKernel_down_smpPfS_iiiii
.p2align 3, 0x0
_Z30convolutionRowsKernel_down_smpPfS_iiiii:
.quad _Z45__device_stub__convolutionRowsKernel_down_smpPfS_iiiii
.size _Z30convolutionRowsKernel_down_smpPfS_iiiii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z30convolutionRowsKernel_down_smpPfS_iiiii"
.size .L__unnamed_1, 44
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "c_Kernel"
.size .L__unnamed_2, 9
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z45__device_stub__convolutionRowsKernel_down_smpPfS_iiiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym c_Kernel
.addrsig_sym _Z30convolutionRowsKernel_down_smpPfS_iiiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00164604_00000000-6_convolutionRowsKernel_down_smp.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z57__device_stub__Z30convolutionRowsKernel_down_smpPfS_iiiiiPfS_iiiii
.type _Z57__device_stub__Z30convolutionRowsKernel_down_smpPfS_iiiiiPfS_iiiii, @function
_Z57__device_stub__Z30convolutionRowsKernel_down_smpPfS_iiiiiPfS_iiiii:
.LFB2051:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movl %r9d, (%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
movq %rsp, %rax
movq %rax, 136(%rsp)
leaq 176(%rsp), %rax
movq %rax, 144(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 184
pushq 40(%rsp)
.cfi_def_cfa_offset 192
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z30convolutionRowsKernel_down_smpPfS_iiiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z57__device_stub__Z30convolutionRowsKernel_down_smpPfS_iiiiiPfS_iiiii, .-_Z57__device_stub__Z30convolutionRowsKernel_down_smpPfS_iiiiiPfS_iiiii
.globl _Z30convolutionRowsKernel_down_smpPfS_iiiii
.type _Z30convolutionRowsKernel_down_smpPfS_iiiii, @function
_Z30convolutionRowsKernel_down_smpPfS_iiiii:
.LFB2052:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
call _Z57__device_stub__Z30convolutionRowsKernel_down_smpPfS_iiiiiPfS_iiiii
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z30convolutionRowsKernel_down_smpPfS_iiiii, .-_Z30convolutionRowsKernel_down_smpPfS_iiiii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z30convolutionRowsKernel_down_smpPfS_iiiii"
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "c_Kernel"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z30convolutionRowsKernel_down_smpPfS_iiiii(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $8, %r9d
movl $0, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _ZL8c_Kernel(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL8c_Kernel
.comm _ZL8c_Kernel,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "convolutionRowsKernel_down_smp.hip"
.globl _Z45__device_stub__convolutionRowsKernel_down_smpPfS_iiiii # -- Begin function _Z45__device_stub__convolutionRowsKernel_down_smpPfS_iiiii
.p2align 4, 0x90
.type _Z45__device_stub__convolutionRowsKernel_down_smpPfS_iiiii,@function
_Z45__device_stub__convolutionRowsKernel_down_smpPfS_iiiii: # @_Z45__device_stub__convolutionRowsKernel_down_smpPfS_iiiii
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movl %r9d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
leaq 144(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z30convolutionRowsKernel_down_smpPfS_iiiii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end0:
.size _Z45__device_stub__convolutionRowsKernel_down_smpPfS_iiiii, .Lfunc_end0-_Z45__device_stub__convolutionRowsKernel_down_smpPfS_iiiii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z30convolutionRowsKernel_down_smpPfS_iiiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $0, 8(%rsp)
movl $1, (%rsp)
movl $c_Kernel, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movl $8, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
callq __hipRegisterVar
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type c_Kernel,@object # @c_Kernel
.local c_Kernel
.comm c_Kernel,8,8
.type _Z30convolutionRowsKernel_down_smpPfS_iiiii,@object # @_Z30convolutionRowsKernel_down_smpPfS_iiiii
.section .rodata,"a",@progbits
.globl _Z30convolutionRowsKernel_down_smpPfS_iiiii
.p2align 3, 0x0
_Z30convolutionRowsKernel_down_smpPfS_iiiii:
.quad _Z45__device_stub__convolutionRowsKernel_down_smpPfS_iiiii
.size _Z30convolutionRowsKernel_down_smpPfS_iiiii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z30convolutionRowsKernel_down_smpPfS_iiiii"
.size .L__unnamed_1, 44
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "c_Kernel"
.size .L__unnamed_2, 9
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z45__device_stub__convolutionRowsKernel_down_smpPfS_iiiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym c_Kernel
.addrsig_sym _Z30convolutionRowsKernel_down_smpPfS_iiiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <iostream>
#include <algorithm>
using namespace std;
__global__ void VectorsPairMaximums(size_t size, double *first, double *second, double *res) {
size_t begin = (size_t) (blockDim.x * blockIdx.x + threadIdx.x);
size_t offset = gridDim.x * blockDim.x;
for (size_t i = begin; i < size; i += offset) {
res[i] = max(first[i], second[i]);
}
}
__host__ int main(void) {
size_t size;
cin >> size;
double *first = new double[size];
double *second = new double[size];
double *res = new double[size];
for (size_t i = 0; i < size; i++) {
cin >> first[i];
//first[i] = i;
}
for (size_t i = 0; i < size; i++) {
cin >> second[i];
//second[i] = i;
}
double *cudaFirst;
double *cudaSecond;
double *cudaRes;
cudaMalloc((void**) &cudaFirst, sizeof(double) * size);
cudaMalloc((void**) &cudaSecond, sizeof(double) * size);
cudaMalloc((void**) &cudaRes, sizeof(double) * size);
cudaMemcpy(cudaFirst, first, sizeof(double) * size, cudaMemcpyHostToDevice);
cudaMemcpy(cudaSecond, second, sizeof(double) * size, cudaMemcpyHostToDevice);
VectorsPairMaximums<<<256, 256>>>(size, cudaFirst, cudaSecond, cudaRes);
cudaEvent_t syncEvent;
cudaEventCreate(&syncEvent);
cudaEventRecord(syncEvent, 0);
cudaEventSynchronize(syncEvent);
cudaMemcpy(res, cudaRes, sizeof(double) * size, cudaMemcpyDeviceToHost);
//double *testArr = new double[size];
//cudaMemcpy(testArr, cudaFirst, sizeof(double) * size, cudaMemcpyDeviceToHost);
cudaEventDestroy(syncEvent);
cudaFree(cudaFirst);
cudaFree(cudaSecond);
cudaFree(cudaRes);
for (size_t i = 0; i < size; i++) {
if (i > 0) {
cout << " ";
}
cout << scientific << res[i];
}
cout << endl;
delete [] first;
delete [] second;
delete [] res;
return 0;
} | code for sm_80
Function : _Z19VectorsPairMaximumsmPdS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x160], PT ; /* 0x0000580000007a0c */
/* 0x000fc80003f06070 */
/*0050*/ ISETP.GE.U32.AND.EX P0, PT, RZ, c[0x0][0x164], PT, P0 ; /* 0x00005900ff007a0c */
/* 0x000fda0003f06100 */
/*0060*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0070*/ IMAD.MOV.U32 R11, RZ, RZ, RZ ; /* 0x000000ffff0b7224 */
/* 0x000fe200078e00ff */
/*0080*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0090*/ IMAD.MOV.U32 R14, RZ, RZ, c[0x0][0xc] ; /* 0x00000300ff0e7624 */
/* 0x000fe400078e00ff */
/*00a0*/ IMAD.SHL.U32 R8, R0.reuse, 0x8, RZ ; /* 0x0000000800087824 */
/* 0x040fe200078e00ff */
/*00b0*/ SHF.L.U64.HI R9, R0, 0x3, R11 ; /* 0x0000000300097819 */
/* 0x000fc8000001020b */
/*00c0*/ IADD3 R4, P1, R8.reuse, c[0x0][0x168], RZ ; /* 0x00005a0008047a10 */
/* 0x040fe40007f3e0ff */
/*00d0*/ IADD3 R6, P0, R8, c[0x0][0x170], RZ ; /* 0x00005c0008067a10 */
/* 0x000fe40007f1e0ff */
/*00e0*/ IADD3.X R5, R9.reuse, c[0x0][0x16c], RZ, P1, !PT ; /* 0x00005b0009057a10 */
/* 0x040fe40000ffe4ff */
/*00f0*/ IADD3.X R7, R9, c[0x0][0x174], RZ, P0, !PT ; /* 0x00005d0009077a10 */
/* 0x000fc800007fe4ff */
/*0100*/ LDG.E.64 R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1b00 */
/*0110*/ LDG.E.64 R2, [R6.64] ; /* 0x0000000406027981 */
/* 0x000ea2000c1e1b00 */
/*0120*/ IADD3 R8, P0, R8, c[0x0][0x178], RZ ; /* 0x00005e0008087a10 */
/* 0x000fc80007f1e0ff */
/*0130*/ IADD3.X R9, R9, c[0x0][0x17c], RZ, P0, !PT ; /* 0x00005f0009097a10 */
/* 0x000fe200007fe4ff */
/*0140*/ DSETP.MAX.AND P1, P2, R2, R4, PT ; /* 0x000000040200722a */
/* 0x004e220003a2f000 */
/*0150*/ IMAD.MOV.U32 R12, RZ, RZ, R5 ; /* 0x000000ffff0c7224 */
/* 0x000fe400078e0005 */
/*0160*/ IMAD.MOV.U32 R10, RZ, RZ, R2 ; /* 0x000000ffff0a7224 */
/* 0x000fc600078e0002 */
/*0170*/ FSEL R13, R3, R12, P1 ; /* 0x0000000c030d7208 */
/* 0x001fe20000800000 */
/*0180*/ IMAD.MOV.U32 R3, RZ, RZ, R4 ; /* 0x000000ffff037224 */
/* 0x000fe400078e0004 */
/*0190*/ IMAD R5, R14, c[0x0][0x0], RZ ; /* 0x000000000e057a24 */
/* 0x000fca00078e02ff */
/*01a0*/ @P2 LOP3.LUT R13, R12, 0x80000, RZ, 0xfc, !PT ; /* 0x000800000c0d2812 */
/* 0x000fe400078efcff */
/*01b0*/ SEL R2, R10, R3, P1 ; /* 0x000000030a027207 */
/* 0x000fe40000800000 */
/*01c0*/ IADD3 R0, P0, R5, R0, RZ ; /* 0x0000000005007210 */
/* 0x000fe20007f1e0ff */
/*01d0*/ IMAD.MOV.U32 R3, RZ, RZ, R13 ; /* 0x000000ffff037224 */
/* 0x000fc800078e000d */
/*01e0*/ IMAD.X R11, RZ, RZ, R11, P0 ; /* 0x000000ffff0b7224 */
/* 0x000fe200000e060b */
/*01f0*/ STG.E.64 [R8.64], R2 ; /* 0x0000000208007986 */
/* 0x0001e2000c101b04 */
/*0200*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x160], PT ; /* 0x0000580000007a0c */
/* 0x000fc80003f06070 */
/*0210*/ ISETP.GE.U32.AND.EX P0, PT, R11, c[0x0][0x164], PT, P0 ; /* 0x000059000b007a0c */
/* 0x000fda0003f06100 */
/*0220*/ @!P0 BRA 0xa0 ; /* 0xfffffe7000008947 */
/* 0x001fea000383ffff */
/*0230*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0240*/ BRA 0x240; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <iostream>
#include <algorithm>
using namespace std;
__global__ void VectorsPairMaximums(size_t size, double *first, double *second, double *res) {
size_t begin = (size_t) (blockDim.x * blockIdx.x + threadIdx.x);
size_t offset = gridDim.x * blockDim.x;
for (size_t i = begin; i < size; i += offset) {
res[i] = max(first[i], second[i]);
}
}
__host__ int main(void) {
size_t size;
cin >> size;
double *first = new double[size];
double *second = new double[size];
double *res = new double[size];
for (size_t i = 0; i < size; i++) {
cin >> first[i];
//first[i] = i;
}
for (size_t i = 0; i < size; i++) {
cin >> second[i];
//second[i] = i;
}
double *cudaFirst;
double *cudaSecond;
double *cudaRes;
cudaMalloc((void**) &cudaFirst, sizeof(double) * size);
cudaMalloc((void**) &cudaSecond, sizeof(double) * size);
cudaMalloc((void**) &cudaRes, sizeof(double) * size);
cudaMemcpy(cudaFirst, first, sizeof(double) * size, cudaMemcpyHostToDevice);
cudaMemcpy(cudaSecond, second, sizeof(double) * size, cudaMemcpyHostToDevice);
VectorsPairMaximums<<<256, 256>>>(size, cudaFirst, cudaSecond, cudaRes);
cudaEvent_t syncEvent;
cudaEventCreate(&syncEvent);
cudaEventRecord(syncEvent, 0);
cudaEventSynchronize(syncEvent);
cudaMemcpy(res, cudaRes, sizeof(double) * size, cudaMemcpyDeviceToHost);
//double *testArr = new double[size];
//cudaMemcpy(testArr, cudaFirst, sizeof(double) * size, cudaMemcpyDeviceToHost);
cudaEventDestroy(syncEvent);
cudaFree(cudaFirst);
cudaFree(cudaSecond);
cudaFree(cudaRes);
for (size_t i = 0; i < size; i++) {
if (i > 0) {
cout << " ";
}
cout << scientific << res[i];
}
cout << endl;
delete [] first;
delete [] second;
delete [] res;
return 0;
} | .file "tmpxft_000f7626_00000000-6_gp-lab1.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3926:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3926:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z44__device_stub__Z19VectorsPairMaximumsmPdS_S_mPdS_S_
.type _Z44__device_stub__Z19VectorsPairMaximumsmPdS_S_mPdS_S_, @function
_Z44__device_stub__Z19VectorsPairMaximumsmPdS_S_mPdS_S_:
.LFB3948:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z19VectorsPairMaximumsmPdS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3948:
.size _Z44__device_stub__Z19VectorsPairMaximumsmPdS_S_mPdS_S_, .-_Z44__device_stub__Z19VectorsPairMaximumsmPdS_S_mPdS_S_
.globl _Z19VectorsPairMaximumsmPdS_S_
.type _Z19VectorsPairMaximumsmPdS_S_, @function
_Z19VectorsPairMaximumsmPdS_S_:
.LFB3949:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z44__device_stub__Z19VectorsPairMaximumsmPdS_S_mPdS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3949:
.size _Z19VectorsPairMaximumsmPdS_S_, .-_Z19VectorsPairMaximumsmPdS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string " "
.text
.globl main
.type main, @function
main:
.LFB3923:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $88, %rsp
.cfi_def_cfa_offset 144
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rsi
leaq _ZSt3cin(%rip), %rdi
call _ZNSi10_M_extractImEERSiRT_@PLT
movq 8(%rsp), %rdi
movq %rdi, %rax
shrq $60, %rax
jne .L12
salq $3, %rdi
call _Znam@PLT
movq %rax, %r13
movq 8(%rsp), %rdi
movq %rdi, %rax
shrq $60, %rax
jne .L38
salq $3, %rdi
call _Znam@PLT
movq %rax, %r14
movq 8(%rsp), %rdi
movq %rdi, %rax
shrq $60, %rax
jne .L39
salq $3, %rdi
call _Znam@PLT
movq %rax, %r12
movq 8(%rsp), %rsi
movq %r13, %rbp
movl $0, %ebx
leaq _ZSt3cin(%rip), %r15
testq %rsi, %rsi
je .L20
.L22:
movq %rbp, %rsi
movq %r15, %rdi
call _ZNSi10_M_extractIdEERSiRT_@PLT
addq $1, %rbx
movq 8(%rsp), %rsi
addq $8, %rbp
cmpq %rsi, %rbx
jb .L22
testq %rsi, %rsi
je .L20
movq %r14, %rbp
movl $0, %ebx
leaq _ZSt3cin(%rip), %r15
.L23:
movq %rbp, %rsi
movq %r15, %rdi
call _ZNSi10_M_extractIdEERSiRT_@PLT
addq $1, %rbx
movq 8(%rsp), %rsi
addq $8, %rbp
cmpq %rsi, %rbx
jb .L23
.L20:
salq $3, %rsi
leaq 16(%rsp), %rdi
call cudaMalloc@PLT
movq 8(%rsp), %rax
leaq 0(,%rax,8), %rsi
leaq 24(%rsp), %rdi
call cudaMalloc@PLT
movq 8(%rsp), %rax
leaq 0(,%rax,8), %rsi
leaq 32(%rsp), %rdi
call cudaMalloc@PLT
movq 8(%rsp), %rax
leaq 0(,%rax,8), %rdx
movl $1, %ecx
movq %r13, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movq 8(%rsp), %rax
leaq 0(,%rax,8), %rdx
movl $1, %ecx
movq %r14, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl $256, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $256, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 56(%rsp), %rdx
movl $1, %ecx
movq 44(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L40
.L24:
leaq 56(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 56(%rsp), %rdi
call cudaEventRecord@PLT
movq 56(%rsp), %rdi
call cudaEventSynchronize@PLT
movq 8(%rsp), %rax
leaq 0(,%rax,8), %rdx
movl $2, %ecx
movq 32(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movq 56(%rsp), %rdi
call cudaEventDestroy@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movl $0, %ebx
leaq _ZSt4cout(%rip), %rbp
leaq .LC0(%rip), %r15
cmpq $0, 8(%rsp)
je .L26
.L25:
movq 0(%rbp), %rax
movq %rbp, %rdx
addq -24(%rax), %rdx
movl 24(%rdx), %eax
andl $-261, %eax
orb $1, %ah
movl %eax, 24(%rdx)
movsd (%r12,%rbx,8), %xmm0
movq %rbp, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
addq $1, %rbx
cmpq 8(%rsp), %rbx
jnb .L26
testq %rbx, %rbx
je .L25
movl $1, %edx
movq %r15, %rsi
movq %rbp, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
jmp .L25
.L12:
movq 72(%rsp), %rax
subq %fs:40, %rax
je .L15
call __stack_chk_fail@PLT
.L15:
call __cxa_throw_bad_array_new_length@PLT
.L38:
movq 72(%rsp), %rax
subq %fs:40, %rax
je .L18
call __stack_chk_fail@PLT
.L18:
call __cxa_throw_bad_array_new_length@PLT
.L39:
movq 72(%rsp), %rax
subq %fs:40, %rax
je .L21
call __stack_chk_fail@PLT
.L21:
call __cxa_throw_bad_array_new_length@PLT
.L40:
movq 32(%rsp), %rcx
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z44__device_stub__Z19VectorsPairMaximumsmPdS_S_mPdS_S_
jmp .L24
.L26:
leaq _ZSt4cout(%rip), %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq %r13, %rdi
call _ZdaPv@PLT
movq %r14, %rdi
call _ZdaPv@PLT
movq %r12, %rdi
call _ZdaPv@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L41
movl $0, %eax
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L41:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3923:
.size main, .-main
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "_Z19VectorsPairMaximumsmPdS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3951:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z19VectorsPairMaximumsmPdS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3951:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <iostream>
#include <algorithm>
using namespace std;
__global__ void VectorsPairMaximums(size_t size, double *first, double *second, double *res) {
size_t begin = (size_t) (blockDim.x * blockIdx.x + threadIdx.x);
size_t offset = gridDim.x * blockDim.x;
for (size_t i = begin; i < size; i += offset) {
res[i] = max(first[i], second[i]);
}
}
__host__ int main(void) {
size_t size;
cin >> size;
double *first = new double[size];
double *second = new double[size];
double *res = new double[size];
for (size_t i = 0; i < size; i++) {
cin >> first[i];
//first[i] = i;
}
for (size_t i = 0; i < size; i++) {
cin >> second[i];
//second[i] = i;
}
double *cudaFirst;
double *cudaSecond;
double *cudaRes;
cudaMalloc((void**) &cudaFirst, sizeof(double) * size);
cudaMalloc((void**) &cudaSecond, sizeof(double) * size);
cudaMalloc((void**) &cudaRes, sizeof(double) * size);
cudaMemcpy(cudaFirst, first, sizeof(double) * size, cudaMemcpyHostToDevice);
cudaMemcpy(cudaSecond, second, sizeof(double) * size, cudaMemcpyHostToDevice);
VectorsPairMaximums<<<256, 256>>>(size, cudaFirst, cudaSecond, cudaRes);
cudaEvent_t syncEvent;
cudaEventCreate(&syncEvent);
cudaEventRecord(syncEvent, 0);
cudaEventSynchronize(syncEvent);
cudaMemcpy(res, cudaRes, sizeof(double) * size, cudaMemcpyDeviceToHost);
//double *testArr = new double[size];
//cudaMemcpy(testArr, cudaFirst, sizeof(double) * size, cudaMemcpyDeviceToHost);
cudaEventDestroy(syncEvent);
cudaFree(cudaFirst);
cudaFree(cudaSecond);
cudaFree(cudaRes);
for (size_t i = 0; i < size; i++) {
if (i > 0) {
cout << " ";
}
cout << scientific << res[i];
}
cout << endl;
delete [] first;
delete [] second;
delete [] res;
return 0;
} | #include <hip/hip_runtime.h>
#include <iostream>
#include <algorithm>
using namespace std;
__global__ void VectorsPairMaximums(size_t size, double *first, double *second, double *res) {
size_t begin = (size_t) (blockDim.x * blockIdx.x + threadIdx.x);
size_t offset = gridDim.x * blockDim.x;
for (size_t i = begin; i < size; i += offset) {
res[i] = max(first[i], second[i]);
}
}
__host__ int main(void) {
size_t size;
cin >> size;
double *first = new double[size];
double *second = new double[size];
double *res = new double[size];
for (size_t i = 0; i < size; i++) {
cin >> first[i];
//first[i] = i;
}
for (size_t i = 0; i < size; i++) {
cin >> second[i];
//second[i] = i;
}
double *cudaFirst;
double *cudaSecond;
double *cudaRes;
hipMalloc((void**) &cudaFirst, sizeof(double) * size);
hipMalloc((void**) &cudaSecond, sizeof(double) * size);
hipMalloc((void**) &cudaRes, sizeof(double) * size);
hipMemcpy(cudaFirst, first, sizeof(double) * size, hipMemcpyHostToDevice);
hipMemcpy(cudaSecond, second, sizeof(double) * size, hipMemcpyHostToDevice);
VectorsPairMaximums<<<256, 256>>>(size, cudaFirst, cudaSecond, cudaRes);
hipEvent_t syncEvent;
hipEventCreate(&syncEvent);
hipEventRecord(syncEvent, 0);
hipEventSynchronize(syncEvent);
hipMemcpy(res, cudaRes, sizeof(double) * size, hipMemcpyDeviceToHost);
//double *testArr = new double[size];
//cudaMemcpy(testArr, cudaFirst, sizeof(double) * size, cudaMemcpyDeviceToHost);
hipEventDestroy(syncEvent);
hipFree(cudaFirst);
hipFree(cudaSecond);
hipFree(cudaRes);
for (size_t i = 0; i < size; i++) {
if (i > 0) {
cout << " ";
}
cout << scientific << res[i];
}
cout << endl;
delete [] first;
delete [] second;
delete [] res;
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <iostream>
#include <algorithm>
using namespace std;
__global__ void VectorsPairMaximums(size_t size, double *first, double *second, double *res) {
size_t begin = (size_t) (blockDim.x * blockIdx.x + threadIdx.x);
size_t offset = gridDim.x * blockDim.x;
for (size_t i = begin; i < size; i += offset) {
res[i] = max(first[i], second[i]);
}
}
__host__ int main(void) {
size_t size;
cin >> size;
double *first = new double[size];
double *second = new double[size];
double *res = new double[size];
for (size_t i = 0; i < size; i++) {
cin >> first[i];
//first[i] = i;
}
for (size_t i = 0; i < size; i++) {
cin >> second[i];
//second[i] = i;
}
double *cudaFirst;
double *cudaSecond;
double *cudaRes;
hipMalloc((void**) &cudaFirst, sizeof(double) * size);
hipMalloc((void**) &cudaSecond, sizeof(double) * size);
hipMalloc((void**) &cudaRes, sizeof(double) * size);
hipMemcpy(cudaFirst, first, sizeof(double) * size, hipMemcpyHostToDevice);
hipMemcpy(cudaSecond, second, sizeof(double) * size, hipMemcpyHostToDevice);
VectorsPairMaximums<<<256, 256>>>(size, cudaFirst, cudaSecond, cudaRes);
hipEvent_t syncEvent;
hipEventCreate(&syncEvent);
hipEventRecord(syncEvent, 0);
hipEventSynchronize(syncEvent);
hipMemcpy(res, cudaRes, sizeof(double) * size, hipMemcpyDeviceToHost);
//double *testArr = new double[size];
//cudaMemcpy(testArr, cudaFirst, sizeof(double) * size, cudaMemcpyDeviceToHost);
hipEventDestroy(syncEvent);
hipFree(cudaFirst);
hipFree(cudaSecond);
hipFree(cudaRes);
for (size_t i = 0; i < size; i++) {
if (i > 0) {
cout << " ";
}
cout << scientific << res[i];
}
cout << endl;
delete [] first;
delete [] second;
delete [] res;
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z19VectorsPairMaximumsmPdS_S_
.globl _Z19VectorsPairMaximumsmPdS_S_
.p2align 8
.type _Z19VectorsPairMaximumsmPdS_S_,@function
_Z19VectorsPairMaximumsmPdS_S_:
s_clause 0x1
s_load_b32 s6, s[0:1], 0x2c
s_load_b64 s[2:3], s[0:1], 0x0
s_add_u32 s4, s0, 32
s_addc_u32 s5, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s10, s6, 0xffff
s_mov_b32 s6, exec_lo
v_mad_u64_u32 v[1:2], null, s15, s10, v[0:1]
v_mov_b32_e32 v2, 0
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_u64_e64 s[2:3], v[1:2]
s_cbranch_execz .LBB0_3
s_load_b32 s12, s[4:5], 0x0
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x8
s_load_b64 s[8:9], s[0:1], 0x18
v_lshlrev_b64 v[3:4], 3, v[1:2]
s_mov_b32 s11, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
s_mov_b32 s1, s11
s_waitcnt lgkmcnt(0)
s_mul_i32 s10, s12, s10
s_lshl_b64 s[12:13], s[10:11], 3
.p2align 6
.LBB0_2:
v_add_co_u32 v5, vcc_lo, s6, v3
v_add_co_ci_u32_e32 v6, vcc_lo, s7, v4, vcc_lo
v_add_co_u32 v7, vcc_lo, s4, v3
v_add_co_ci_u32_e32 v8, vcc_lo, s5, v4, vcc_lo
v_add_co_u32 v1, vcc_lo, v1, s10
global_load_b64 v[5:6], v[5:6], off
global_load_b64 v[7:8], v[7:8], off
v_add_co_ci_u32_e32 v2, vcc_lo, s11, v2, vcc_lo
s_waitcnt vmcnt(1)
v_max_f64 v[5:6], v[5:6], v[5:6]
s_waitcnt vmcnt(0)
v_max_f64 v[7:8], v[7:8], v[7:8]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
v_max_f64 v[5:6], v[7:8], v[5:6]
v_add_co_u32 v7, vcc_lo, s8, v3
v_add_co_ci_u32_e32 v8, vcc_lo, s9, v4, vcc_lo
v_cmp_le_u64_e32 vcc_lo, s[2:3], v[1:2]
v_add_co_u32 v3, s0, v3, s12
v_add_co_ci_u32_e64 v4, s0, s13, v4, s0
s_or_b32 s1, vcc_lo, s1
global_store_b64 v[7:8], v[5:6], off
s_and_not1_b32 exec_lo, exec_lo, s1
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z19VectorsPairMaximumsmPdS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z19VectorsPairMaximumsmPdS_S_, .Lfunc_end0-_Z19VectorsPairMaximumsmPdS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 8
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z19VectorsPairMaximumsmPdS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z19VectorsPairMaximumsmPdS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <iostream>
#include <algorithm>
using namespace std;
__global__ void VectorsPairMaximums(size_t size, double *first, double *second, double *res) {
size_t begin = (size_t) (blockDim.x * blockIdx.x + threadIdx.x);
size_t offset = gridDim.x * blockDim.x;
for (size_t i = begin; i < size; i += offset) {
res[i] = max(first[i], second[i]);
}
}
__host__ int main(void) {
size_t size;
cin >> size;
double *first = new double[size];
double *second = new double[size];
double *res = new double[size];
for (size_t i = 0; i < size; i++) {
cin >> first[i];
//first[i] = i;
}
for (size_t i = 0; i < size; i++) {
cin >> second[i];
//second[i] = i;
}
double *cudaFirst;
double *cudaSecond;
double *cudaRes;
hipMalloc((void**) &cudaFirst, sizeof(double) * size);
hipMalloc((void**) &cudaSecond, sizeof(double) * size);
hipMalloc((void**) &cudaRes, sizeof(double) * size);
hipMemcpy(cudaFirst, first, sizeof(double) * size, hipMemcpyHostToDevice);
hipMemcpy(cudaSecond, second, sizeof(double) * size, hipMemcpyHostToDevice);
VectorsPairMaximums<<<256, 256>>>(size, cudaFirst, cudaSecond, cudaRes);
hipEvent_t syncEvent;
hipEventCreate(&syncEvent);
hipEventRecord(syncEvent, 0);
hipEventSynchronize(syncEvent);
hipMemcpy(res, cudaRes, sizeof(double) * size, hipMemcpyDeviceToHost);
//double *testArr = new double[size];
//cudaMemcpy(testArr, cudaFirst, sizeof(double) * size, cudaMemcpyDeviceToHost);
hipEventDestroy(syncEvent);
hipFree(cudaFirst);
hipFree(cudaSecond);
hipFree(cudaRes);
for (size_t i = 0; i < size; i++) {
if (i > 0) {
cout << " ";
}
cout << scientific << res[i];
}
cout << endl;
delete [] first;
delete [] second;
delete [] res;
return 0;
} | .text
.file "gp-lab1.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z34__device_stub__VectorsPairMaximumsmPdS_S_ # -- Begin function _Z34__device_stub__VectorsPairMaximumsmPdS_S_
.p2align 4, 0x90
.type _Z34__device_stub__VectorsPairMaximumsmPdS_S_,@function
_Z34__device_stub__VectorsPairMaximumsmPdS_S_: # @_Z34__device_stub__VectorsPairMaximumsmPdS_S_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movq %rcx, 48(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rax
movq %rax, 104(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z19VectorsPairMaximumsmPdS_S_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z34__device_stub__VectorsPairMaximumsmPdS_S_, .Lfunc_end0-_Z34__device_stub__VectorsPairMaximumsmPdS_S_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $152, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsp, %rsi
movl $_ZSt3cin, %edi
callq _ZNSi10_M_extractImEERSiRT_
movq (%rsp), %rax
movq %rax, %rcx
shrq $61, %rcx
shlq $3, %rax
xorl %r15d, %r15d
negq %rcx
sbbq %r15, %r15
orq %rax, %r15
movq %r15, %rdi
callq _Znam
movq %rax, %rbx
movq %r15, %rdi
callq _Znam
movq %rax, %r14
movq %r15, %rdi
callq _Znam
movq %rax, %r15
cmpq $0, (%rsp)
je .LBB1_3
# %bb.1: # %.lr.ph.preheader
xorl %r13d, %r13d
movq %rbx, %r12
.p2align 4, 0x90
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl $_ZSt3cin, %edi
movq %r12, %rsi
callq _ZNSi10_M_extractIdEERSiRT_
incq %r13
addq $8, %r12
cmpq (%rsp), %r13
jb .LBB1_2
.LBB1_3: # %.preheader
movq (%rsp), %rsi
testq %rsi, %rsi
je .LBB1_6
# %bb.4: # %.lr.ph28.preheader
xorl %r13d, %r13d
movq %r14, %r12
.p2align 4, 0x90
.LBB1_5: # %.lr.ph28
# =>This Inner Loop Header: Depth=1
movl $_ZSt3cin, %edi
movq %r12, %rsi
callq _ZNSi10_M_extractIdEERSiRT_
incq %r13
movq (%rsp), %rsi
addq $8, %r12
cmpq %rsi, %r13
jb .LBB1_5
.LBB1_6: # %._crit_edge
shlq $3, %rsi
leaq 24(%rsp), %rdi
callq hipMalloc
movq (%rsp), %rsi
shlq $3, %rsi
leaq 16(%rsp), %rdi
callq hipMalloc
movq (%rsp), %rsi
shlq $3, %rsi
leaq 8(%rsp), %rdi
callq hipMalloc
movq 24(%rsp), %rdi
movq (%rsp), %rdx
shlq $3, %rdx
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
movq (%rsp), %rdx
shlq $3, %rdx
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967552, %rdi # imm = 0x100000100
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_8
# %bb.7:
movq (%rsp), %rax
movq 24(%rsp), %rcx
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
movq %rax, 144(%rsp)
movq %rcx, 136(%rsp)
movq %rdx, 128(%rsp)
movq %rsi, 120(%rsp)
leaq 144(%rsp), %rax
movq %rax, 32(%rsp)
leaq 136(%rsp), %rax
movq %rax, 40(%rsp)
leaq 128(%rsp), %rax
movq %rax, 48(%rsp)
leaq 120(%rsp), %rax
movq %rax, 56(%rsp)
leaq 104(%rsp), %rdi
leaq 88(%rsp), %rsi
leaq 80(%rsp), %rdx
leaq 72(%rsp), %rcx
callq __hipPopCallConfiguration
movq 104(%rsp), %rsi
movl 112(%rsp), %edx
movq 88(%rsp), %rcx
movl 96(%rsp), %r8d
leaq 32(%rsp), %r9
movl $_Z19VectorsPairMaximumsmPdS_S_, %edi
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
pushq 88(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_8:
leaq 32(%rsp), %rdi
callq hipEventCreate
movq 32(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 32(%rsp), %rdi
callq hipEventSynchronize
movq 8(%rsp), %rsi
movq (%rsp), %rdx
shlq $3, %rdx
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
movq 32(%rsp), %rdi
callq hipEventDestroy
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
cmpq $0, (%rsp)
je .LBB1_13
# %bb.9: # %.lr.ph31.preheader
xorl %r12d, %r12d
movl $-261, %ebp # imm = 0xFEFB
jmp .LBB1_10
.p2align 4, 0x90
.LBB1_12: # in Loop: Header=BB1_10 Depth=1
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movl _ZSt4cout+24(%rax), %ecx
andl %ebp, %ecx
orl $256, %ecx # imm = 0x100
movl %ecx, _ZSt4cout+24(%rax)
movsd (%r15,%r12,8), %xmm0 # xmm0 = mem[0],zero
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
incq %r12
cmpq (%rsp), %r12
jae .LBB1_13
.LBB1_10: # %.lr.ph31
# =>This Inner Loop Header: Depth=1
testq %r12, %r12
je .LBB1_12
# %bb.11: # in Loop: Header=BB1_10 Depth=1
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $1, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
jmp .LBB1_12
.LBB1_13: # %._crit_edge32
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r12
testq %r12, %r12
je .LBB1_18
# %bb.14: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%r12)
je .LBB1_16
# %bb.15:
movzbl 67(%r12), %eax
jmp .LBB1_17
.LBB1_16:
movq %r12, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r12), %rax
movq %r12, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_17: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq %rbx, %rdi
callq _ZdaPv
movq %r14, %rdi
callq _ZdaPv
movq %r15, %rdi
callq _ZdaPv
xorl %eax, %eax
addq $152, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_18:
.cfi_def_cfa_offset 208
callq _ZSt16__throw_bad_castv
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z19VectorsPairMaximumsmPdS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z19VectorsPairMaximumsmPdS_S_,@object # @_Z19VectorsPairMaximumsmPdS_S_
.section .rodata,"a",@progbits
.globl _Z19VectorsPairMaximumsmPdS_S_
.p2align 3, 0x0
_Z19VectorsPairMaximumsmPdS_S_:
.quad _Z34__device_stub__VectorsPairMaximumsmPdS_S_
.size _Z19VectorsPairMaximumsmPdS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz " "
.size .L.str, 2
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z19VectorsPairMaximumsmPdS_S_"
.size .L__unnamed_1, 31
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z34__device_stub__VectorsPairMaximumsmPdS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z19VectorsPairMaximumsmPdS_S_
.addrsig_sym _ZSt3cin
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z19VectorsPairMaximumsmPdS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x160], PT ; /* 0x0000580000007a0c */
/* 0x000fc80003f06070 */
/*0050*/ ISETP.GE.U32.AND.EX P0, PT, RZ, c[0x0][0x164], PT, P0 ; /* 0x00005900ff007a0c */
/* 0x000fda0003f06100 */
/*0060*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0070*/ IMAD.MOV.U32 R11, RZ, RZ, RZ ; /* 0x000000ffff0b7224 */
/* 0x000fe200078e00ff */
/*0080*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0090*/ IMAD.MOV.U32 R14, RZ, RZ, c[0x0][0xc] ; /* 0x00000300ff0e7624 */
/* 0x000fe400078e00ff */
/*00a0*/ IMAD.SHL.U32 R8, R0.reuse, 0x8, RZ ; /* 0x0000000800087824 */
/* 0x040fe200078e00ff */
/*00b0*/ SHF.L.U64.HI R9, R0, 0x3, R11 ; /* 0x0000000300097819 */
/* 0x000fc8000001020b */
/*00c0*/ IADD3 R4, P1, R8.reuse, c[0x0][0x168], RZ ; /* 0x00005a0008047a10 */
/* 0x040fe40007f3e0ff */
/*00d0*/ IADD3 R6, P0, R8, c[0x0][0x170], RZ ; /* 0x00005c0008067a10 */
/* 0x000fe40007f1e0ff */
/*00e0*/ IADD3.X R5, R9.reuse, c[0x0][0x16c], RZ, P1, !PT ; /* 0x00005b0009057a10 */
/* 0x040fe40000ffe4ff */
/*00f0*/ IADD3.X R7, R9, c[0x0][0x174], RZ, P0, !PT ; /* 0x00005d0009077a10 */
/* 0x000fc800007fe4ff */
/*0100*/ LDG.E.64 R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1b00 */
/*0110*/ LDG.E.64 R2, [R6.64] ; /* 0x0000000406027981 */
/* 0x000ea2000c1e1b00 */
/*0120*/ IADD3 R8, P0, R8, c[0x0][0x178], RZ ; /* 0x00005e0008087a10 */
/* 0x000fc80007f1e0ff */
/*0130*/ IADD3.X R9, R9, c[0x0][0x17c], RZ, P0, !PT ; /* 0x00005f0009097a10 */
/* 0x000fe200007fe4ff */
/*0140*/ DSETP.MAX.AND P1, P2, R2, R4, PT ; /* 0x000000040200722a */
/* 0x004e220003a2f000 */
/*0150*/ IMAD.MOV.U32 R12, RZ, RZ, R5 ; /* 0x000000ffff0c7224 */
/* 0x000fe400078e0005 */
/*0160*/ IMAD.MOV.U32 R10, RZ, RZ, R2 ; /* 0x000000ffff0a7224 */
/* 0x000fc600078e0002 */
/*0170*/ FSEL R13, R3, R12, P1 ; /* 0x0000000c030d7208 */
/* 0x001fe20000800000 */
/*0180*/ IMAD.MOV.U32 R3, RZ, RZ, R4 ; /* 0x000000ffff037224 */
/* 0x000fe400078e0004 */
/*0190*/ IMAD R5, R14, c[0x0][0x0], RZ ; /* 0x000000000e057a24 */
/* 0x000fca00078e02ff */
/*01a0*/ @P2 LOP3.LUT R13, R12, 0x80000, RZ, 0xfc, !PT ; /* 0x000800000c0d2812 */
/* 0x000fe400078efcff */
/*01b0*/ SEL R2, R10, R3, P1 ; /* 0x000000030a027207 */
/* 0x000fe40000800000 */
/*01c0*/ IADD3 R0, P0, R5, R0, RZ ; /* 0x0000000005007210 */
/* 0x000fe20007f1e0ff */
/*01d0*/ IMAD.MOV.U32 R3, RZ, RZ, R13 ; /* 0x000000ffff037224 */
/* 0x000fc800078e000d */
/*01e0*/ IMAD.X R11, RZ, RZ, R11, P0 ; /* 0x000000ffff0b7224 */
/* 0x000fe200000e060b */
/*01f0*/ STG.E.64 [R8.64], R2 ; /* 0x0000000208007986 */
/* 0x0001e2000c101b04 */
/*0200*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x160], PT ; /* 0x0000580000007a0c */
/* 0x000fc80003f06070 */
/*0210*/ ISETP.GE.U32.AND.EX P0, PT, R11, c[0x0][0x164], PT, P0 ; /* 0x000059000b007a0c */
/* 0x000fda0003f06100 */
/*0220*/ @!P0 BRA 0xa0 ; /* 0xfffffe7000008947 */
/* 0x001fea000383ffff */
/*0230*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0240*/ BRA 0x240; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z19VectorsPairMaximumsmPdS_S_
.globl _Z19VectorsPairMaximumsmPdS_S_
.p2align 8
.type _Z19VectorsPairMaximumsmPdS_S_,@function
_Z19VectorsPairMaximumsmPdS_S_:
s_clause 0x1
s_load_b32 s6, s[0:1], 0x2c
s_load_b64 s[2:3], s[0:1], 0x0
s_add_u32 s4, s0, 32
s_addc_u32 s5, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s10, s6, 0xffff
s_mov_b32 s6, exec_lo
v_mad_u64_u32 v[1:2], null, s15, s10, v[0:1]
v_mov_b32_e32 v2, 0
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_u64_e64 s[2:3], v[1:2]
s_cbranch_execz .LBB0_3
s_load_b32 s12, s[4:5], 0x0
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x8
s_load_b64 s[8:9], s[0:1], 0x18
v_lshlrev_b64 v[3:4], 3, v[1:2]
s_mov_b32 s11, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
s_mov_b32 s1, s11
s_waitcnt lgkmcnt(0)
s_mul_i32 s10, s12, s10
s_lshl_b64 s[12:13], s[10:11], 3
.p2align 6
.LBB0_2:
v_add_co_u32 v5, vcc_lo, s6, v3
v_add_co_ci_u32_e32 v6, vcc_lo, s7, v4, vcc_lo
v_add_co_u32 v7, vcc_lo, s4, v3
v_add_co_ci_u32_e32 v8, vcc_lo, s5, v4, vcc_lo
v_add_co_u32 v1, vcc_lo, v1, s10
global_load_b64 v[5:6], v[5:6], off
global_load_b64 v[7:8], v[7:8], off
v_add_co_ci_u32_e32 v2, vcc_lo, s11, v2, vcc_lo
s_waitcnt vmcnt(1)
v_max_f64 v[5:6], v[5:6], v[5:6]
s_waitcnt vmcnt(0)
v_max_f64 v[7:8], v[7:8], v[7:8]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
v_max_f64 v[5:6], v[7:8], v[5:6]
v_add_co_u32 v7, vcc_lo, s8, v3
v_add_co_ci_u32_e32 v8, vcc_lo, s9, v4, vcc_lo
v_cmp_le_u64_e32 vcc_lo, s[2:3], v[1:2]
v_add_co_u32 v3, s0, v3, s12
v_add_co_ci_u32_e64 v4, s0, s13, v4, s0
s_or_b32 s1, vcc_lo, s1
global_store_b64 v[7:8], v[5:6], off
s_and_not1_b32 exec_lo, exec_lo, s1
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z19VectorsPairMaximumsmPdS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z19VectorsPairMaximumsmPdS_S_, .Lfunc_end0-_Z19VectorsPairMaximumsmPdS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 8
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z19VectorsPairMaximumsmPdS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z19VectorsPairMaximumsmPdS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000f7626_00000000-6_gp-lab1.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3926:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3926:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z44__device_stub__Z19VectorsPairMaximumsmPdS_S_mPdS_S_
.type _Z44__device_stub__Z19VectorsPairMaximumsmPdS_S_mPdS_S_, @function
_Z44__device_stub__Z19VectorsPairMaximumsmPdS_S_mPdS_S_:
.LFB3948:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z19VectorsPairMaximumsmPdS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3948:
.size _Z44__device_stub__Z19VectorsPairMaximumsmPdS_S_mPdS_S_, .-_Z44__device_stub__Z19VectorsPairMaximumsmPdS_S_mPdS_S_
.globl _Z19VectorsPairMaximumsmPdS_S_
.type _Z19VectorsPairMaximumsmPdS_S_, @function
_Z19VectorsPairMaximumsmPdS_S_:
.LFB3949:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z44__device_stub__Z19VectorsPairMaximumsmPdS_S_mPdS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3949:
.size _Z19VectorsPairMaximumsmPdS_S_, .-_Z19VectorsPairMaximumsmPdS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string " "
.text
.globl main
.type main, @function
main:
.LFB3923:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $88, %rsp
.cfi_def_cfa_offset 144
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rsi
leaq _ZSt3cin(%rip), %rdi
call _ZNSi10_M_extractImEERSiRT_@PLT
movq 8(%rsp), %rdi
movq %rdi, %rax
shrq $60, %rax
jne .L12
salq $3, %rdi
call _Znam@PLT
movq %rax, %r13
movq 8(%rsp), %rdi
movq %rdi, %rax
shrq $60, %rax
jne .L38
salq $3, %rdi
call _Znam@PLT
movq %rax, %r14
movq 8(%rsp), %rdi
movq %rdi, %rax
shrq $60, %rax
jne .L39
salq $3, %rdi
call _Znam@PLT
movq %rax, %r12
movq 8(%rsp), %rsi
movq %r13, %rbp
movl $0, %ebx
leaq _ZSt3cin(%rip), %r15
testq %rsi, %rsi
je .L20
.L22:
movq %rbp, %rsi
movq %r15, %rdi
call _ZNSi10_M_extractIdEERSiRT_@PLT
addq $1, %rbx
movq 8(%rsp), %rsi
addq $8, %rbp
cmpq %rsi, %rbx
jb .L22
testq %rsi, %rsi
je .L20
movq %r14, %rbp
movl $0, %ebx
leaq _ZSt3cin(%rip), %r15
.L23:
movq %rbp, %rsi
movq %r15, %rdi
call _ZNSi10_M_extractIdEERSiRT_@PLT
addq $1, %rbx
movq 8(%rsp), %rsi
addq $8, %rbp
cmpq %rsi, %rbx
jb .L23
.L20:
salq $3, %rsi
leaq 16(%rsp), %rdi
call cudaMalloc@PLT
movq 8(%rsp), %rax
leaq 0(,%rax,8), %rsi
leaq 24(%rsp), %rdi
call cudaMalloc@PLT
movq 8(%rsp), %rax
leaq 0(,%rax,8), %rsi
leaq 32(%rsp), %rdi
call cudaMalloc@PLT
movq 8(%rsp), %rax
leaq 0(,%rax,8), %rdx
movl $1, %ecx
movq %r13, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movq 8(%rsp), %rax
leaq 0(,%rax,8), %rdx
movl $1, %ecx
movq %r14, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl $256, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $256, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 56(%rsp), %rdx
movl $1, %ecx
movq 44(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L40
.L24:
leaq 56(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 56(%rsp), %rdi
call cudaEventRecord@PLT
movq 56(%rsp), %rdi
call cudaEventSynchronize@PLT
movq 8(%rsp), %rax
leaq 0(,%rax,8), %rdx
movl $2, %ecx
movq 32(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movq 56(%rsp), %rdi
call cudaEventDestroy@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movl $0, %ebx
leaq _ZSt4cout(%rip), %rbp
leaq .LC0(%rip), %r15
cmpq $0, 8(%rsp)
je .L26
.L25:
movq 0(%rbp), %rax
movq %rbp, %rdx
addq -24(%rax), %rdx
movl 24(%rdx), %eax
andl $-261, %eax
orb $1, %ah
movl %eax, 24(%rdx)
movsd (%r12,%rbx,8), %xmm0
movq %rbp, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
addq $1, %rbx
cmpq 8(%rsp), %rbx
jnb .L26
testq %rbx, %rbx
je .L25
movl $1, %edx
movq %r15, %rsi
movq %rbp, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
jmp .L25
.L12:
movq 72(%rsp), %rax
subq %fs:40, %rax
je .L15
call __stack_chk_fail@PLT
.L15:
call __cxa_throw_bad_array_new_length@PLT
.L38:
movq 72(%rsp), %rax
subq %fs:40, %rax
je .L18
call __stack_chk_fail@PLT
.L18:
call __cxa_throw_bad_array_new_length@PLT
.L39:
movq 72(%rsp), %rax
subq %fs:40, %rax
je .L21
call __stack_chk_fail@PLT
.L21:
call __cxa_throw_bad_array_new_length@PLT
.L40:
movq 32(%rsp), %rcx
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z44__device_stub__Z19VectorsPairMaximumsmPdS_S_mPdS_S_
jmp .L24
.L26:
leaq _ZSt4cout(%rip), %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq %r13, %rdi
call _ZdaPv@PLT
movq %r14, %rdi
call _ZdaPv@PLT
movq %r12, %rdi
call _ZdaPv@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L41
movl $0, %eax
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L41:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3923:
.size main, .-main
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "_Z19VectorsPairMaximumsmPdS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3951:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z19VectorsPairMaximumsmPdS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3951:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "gp-lab1.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z34__device_stub__VectorsPairMaximumsmPdS_S_ # -- Begin function _Z34__device_stub__VectorsPairMaximumsmPdS_S_
.p2align 4, 0x90
.type _Z34__device_stub__VectorsPairMaximumsmPdS_S_,@function
_Z34__device_stub__VectorsPairMaximumsmPdS_S_: # @_Z34__device_stub__VectorsPairMaximumsmPdS_S_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movq %rcx, 48(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rax
movq %rax, 104(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z19VectorsPairMaximumsmPdS_S_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z34__device_stub__VectorsPairMaximumsmPdS_S_, .Lfunc_end0-_Z34__device_stub__VectorsPairMaximumsmPdS_S_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $152, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsp, %rsi
movl $_ZSt3cin, %edi
callq _ZNSi10_M_extractImEERSiRT_
movq (%rsp), %rax
movq %rax, %rcx
shrq $61, %rcx
shlq $3, %rax
xorl %r15d, %r15d
negq %rcx
sbbq %r15, %r15
orq %rax, %r15
movq %r15, %rdi
callq _Znam
movq %rax, %rbx
movq %r15, %rdi
callq _Znam
movq %rax, %r14
movq %r15, %rdi
callq _Znam
movq %rax, %r15
cmpq $0, (%rsp)
je .LBB1_3
# %bb.1: # %.lr.ph.preheader
xorl %r13d, %r13d
movq %rbx, %r12
.p2align 4, 0x90
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl $_ZSt3cin, %edi
movq %r12, %rsi
callq _ZNSi10_M_extractIdEERSiRT_
incq %r13
addq $8, %r12
cmpq (%rsp), %r13
jb .LBB1_2
.LBB1_3: # %.preheader
movq (%rsp), %rsi
testq %rsi, %rsi
je .LBB1_6
# %bb.4: # %.lr.ph28.preheader
xorl %r13d, %r13d
movq %r14, %r12
.p2align 4, 0x90
.LBB1_5: # %.lr.ph28
# =>This Inner Loop Header: Depth=1
movl $_ZSt3cin, %edi
movq %r12, %rsi
callq _ZNSi10_M_extractIdEERSiRT_
incq %r13
movq (%rsp), %rsi
addq $8, %r12
cmpq %rsi, %r13
jb .LBB1_5
.LBB1_6: # %._crit_edge
shlq $3, %rsi
leaq 24(%rsp), %rdi
callq hipMalloc
movq (%rsp), %rsi
shlq $3, %rsi
leaq 16(%rsp), %rdi
callq hipMalloc
movq (%rsp), %rsi
shlq $3, %rsi
leaq 8(%rsp), %rdi
callq hipMalloc
movq 24(%rsp), %rdi
movq (%rsp), %rdx
shlq $3, %rdx
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
movq (%rsp), %rdx
shlq $3, %rdx
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967552, %rdi # imm = 0x100000100
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_8
# %bb.7:
movq (%rsp), %rax
movq 24(%rsp), %rcx
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
movq %rax, 144(%rsp)
movq %rcx, 136(%rsp)
movq %rdx, 128(%rsp)
movq %rsi, 120(%rsp)
leaq 144(%rsp), %rax
movq %rax, 32(%rsp)
leaq 136(%rsp), %rax
movq %rax, 40(%rsp)
leaq 128(%rsp), %rax
movq %rax, 48(%rsp)
leaq 120(%rsp), %rax
movq %rax, 56(%rsp)
leaq 104(%rsp), %rdi
leaq 88(%rsp), %rsi
leaq 80(%rsp), %rdx
leaq 72(%rsp), %rcx
callq __hipPopCallConfiguration
movq 104(%rsp), %rsi
movl 112(%rsp), %edx
movq 88(%rsp), %rcx
movl 96(%rsp), %r8d
leaq 32(%rsp), %r9
movl $_Z19VectorsPairMaximumsmPdS_S_, %edi
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
pushq 88(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_8:
leaq 32(%rsp), %rdi
callq hipEventCreate
movq 32(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 32(%rsp), %rdi
callq hipEventSynchronize
movq 8(%rsp), %rsi
movq (%rsp), %rdx
shlq $3, %rdx
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
movq 32(%rsp), %rdi
callq hipEventDestroy
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
cmpq $0, (%rsp)
je .LBB1_13
# %bb.9: # %.lr.ph31.preheader
xorl %r12d, %r12d
movl $-261, %ebp # imm = 0xFEFB
jmp .LBB1_10
.p2align 4, 0x90
.LBB1_12: # in Loop: Header=BB1_10 Depth=1
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movl _ZSt4cout+24(%rax), %ecx
andl %ebp, %ecx
orl $256, %ecx # imm = 0x100
movl %ecx, _ZSt4cout+24(%rax)
movsd (%r15,%r12,8), %xmm0 # xmm0 = mem[0],zero
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
incq %r12
cmpq (%rsp), %r12
jae .LBB1_13
.LBB1_10: # %.lr.ph31
# =>This Inner Loop Header: Depth=1
testq %r12, %r12
je .LBB1_12
# %bb.11: # in Loop: Header=BB1_10 Depth=1
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $1, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
jmp .LBB1_12
.LBB1_13: # %._crit_edge32
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r12
testq %r12, %r12
je .LBB1_18
# %bb.14: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%r12)
je .LBB1_16
# %bb.15:
movzbl 67(%r12), %eax
jmp .LBB1_17
.LBB1_16:
movq %r12, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r12), %rax
movq %r12, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_17: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq %rbx, %rdi
callq _ZdaPv
movq %r14, %rdi
callq _ZdaPv
movq %r15, %rdi
callq _ZdaPv
xorl %eax, %eax
addq $152, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_18:
.cfi_def_cfa_offset 208
callq _ZSt16__throw_bad_castv
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z19VectorsPairMaximumsmPdS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z19VectorsPairMaximumsmPdS_S_,@object # @_Z19VectorsPairMaximumsmPdS_S_
.section .rodata,"a",@progbits
.globl _Z19VectorsPairMaximumsmPdS_S_
.p2align 3, 0x0
_Z19VectorsPairMaximumsmPdS_S_:
.quad _Z34__device_stub__VectorsPairMaximumsmPdS_S_
.size _Z19VectorsPairMaximumsmPdS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz " "
.size .L.str, 2
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z19VectorsPairMaximumsmPdS_S_"
.size .L__unnamed_1, 31
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z34__device_stub__VectorsPairMaximumsmPdS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z19VectorsPairMaximumsmPdS_S_
.addrsig_sym _ZSt3cin
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | /* jacobi.c - Poisson problem in 3d
*
*/
#include <math.h>
#include <stdio.h>
__device__ void print_matrix2(double*** A, int N){
int i,j,k;
for (i=0; i<N; i++){
printf("\n %d -th Layer \n", i);
for(j=0; j<N; j++){
for(k=0; k<N; k++){
printf("%lf \t", A[i][j][k]);
}
printf("\n");
}
}
}
__global__ void jacobi_gpu1(double*** u, double***prev_u, double*** f, int N, double step_width, double denominator) {
//iteration: checking norm and Nr of iterations at the same time
double temp;
int i,j,k= 0;
for (i=1; i<N-1; i++){
for (j=1; j<N-1; j++){
for (k=1; k<N-1; k++){
temp=prev_u[i-1][j][k] + prev_u[i+1][j][k]+ prev_u[i][j-1][k] + prev_u[i][j+1][k] + prev_u[i][j][k-1]
+ prev_u[i][j][k+1] + step_width*step_width*f[i][j][k];
u[i][j][k]=temp*denominator;
//printf("For %d %d %d \n", i,j,k,temp*denominator);
//printf("We have in the matrix: %lf \n", u[i][j][k]);
}
}
}
//printf("On the GPU we now have matrix:\n");
//print_matrix2(u,N);
} | code for sm_80
Function : _Z11jacobi_gpu1PPPdS1_S1_idd
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x178] ; /* 0x00005e00ff027624 */
/* 0x000fca00078e00ff */
/*0020*/ ISETP.GE.AND P0, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fda0003f06270 */
/*0030*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0040*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x180] ; /* 0x00006000ff047624 */
/* 0x000fe200078e00ff */
/*0050*/ IADD3 R0, R2.reuse, -0x2, RZ ; /* 0xfffffffe02007810 */
/* 0x040fe20007ffe0ff */
/*0060*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x184] ; /* 0x00006100ff057624 */
/* 0x000fe200078e00ff */
/*0070*/ IADD3 R2, R2, -0x1, RZ ; /* 0xffffffff02027810 */
/* 0x000fe20007ffe0ff */
/*0080*/ IMAD.MOV.U32 R3, RZ, RZ, 0x1 ; /* 0x00000001ff037424 */
/* 0x000fe200078e00ff */
/*0090*/ LOP3.LUT R0, R0, 0x1, RZ, 0xc0, !PT ; /* 0x0000000100007812 */
/* 0x000fe200078ec0ff */
/*00a0*/ ULDC.64 UR10, c[0x0][0x118] ; /* 0x00004600000a7ab9 */
/* 0x000fe40000000a00 */
/*00b0*/ DMUL R4, R4, c[0x0][0x180] ; /* 0x0000600004047a28 */
/* 0x000e220000000000 */
/*00c0*/ IADD3 R24, -R0, c[0x0][0x178], RZ ; /* 0x00005e0000187a10 */
/* 0x000fc60007ffe1ff */
/*00d0*/ IADD3 R6, R3.reuse, -0x1, RZ ; /* 0xffffffff03067810 */
/* 0x040fe20007ffe0ff */
/*00e0*/ IMAD.MOV.U32 R10, RZ, RZ, 0x8 ; /* 0x00000008ff0a7424 */
/* 0x000fe200078e00ff */
/*00f0*/ IADD3 R13, R3, 0x1, RZ ; /* 0x00000001030d7810 */
/* 0x001fe20007ffe0ff */
/*0100*/ UMOV UR6, 0x1 ; /* 0x0000000100067882 */
/* 0x000fc40000000000 */
/*0110*/ IMAD.WIDE R6, R6, R10, c[0x0][0x168] ; /* 0x00005a0006067625 */
/* 0x000fe200078e020a */
/*0120*/ ISETP.GE.AND P0, PT, R13, R2, PT ; /* 0x000000020d00720c */
/* 0x000fc60003f06270 */
/*0130*/ IMAD.WIDE R8, R3, R10, c[0x0][0x170] ; /* 0x00005c0003087625 */
/* 0x000fc800078e020a */
/*0140*/ IMAD.WIDE R10, R3, R10, c[0x0][0x160] ; /* 0x00005800030a7625 */
/* 0x000fc800078e020a */
/*0150*/ IMAD.MOV.U32 R3, RZ, RZ, R13 ; /* 0x000000ffff037224 */
/* 0x000fe400078e000d */
/*0160*/ IMAD.MOV.U32 R12, RZ, RZ, c[0x0][0x178] ; /* 0x00005e00ff0c7624 */
/* 0x001fe200078e00ff */
/*0170*/ UMOV UR5, UR6 ; /* 0x0000000600057c82 */
/* 0x000fe20008000000 */
/*0180*/ ISETP.NE.AND P1, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe20003f25270 */
/*0190*/ USHF.R.S32.HI UR7, URZ, 0x1f, UR6 ; /* 0x0000001f3f077899 */
/* 0x000fe20008011406 */
/*01a0*/ IMAD.MOV.U32 R25, RZ, RZ, 0x1 ; /* 0x00000001ff197424 */
/* 0x000fe200078e00ff */
/*01b0*/ ISETP.NE.AND P3, PT, R12, 0x3, PT ; /* 0x000000030c00780c */
/* 0x000fe20003f65270 */
/*01c0*/ UIADD3 UR8, UR6, -0x1, URZ ; /* 0xffffffff06087890 */
/* 0x000fe4000fffe03f */
/*01d0*/ UIADD3 UR6, UR6, 0x1, URZ ; /* 0x0000000106067890 */
/* 0x000fe4000fffe03f */
/*01e0*/ USHF.R.S32.HI UR9, URZ, 0x1f, UR8 ; /* 0x0000001f3f097899 */
/* 0x000fc80008011408 */
/*01f0*/ ISETP.LE.AND P2, PT, R2, UR6, PT ; /* 0x0000000602007c0c */
/* 0x000fc8000bf43270 */
/*0200*/ @!P3 BRA 0x950 ; /* 0x000007400000b947 */
/* 0x000fea0003800000 */
/*0210*/ IMAD.MOV.U32 R25, RZ, RZ, 0x1 ; /* 0x00000001ff197424 */
/* 0x000fe200078e00ff */
/*0220*/ USHF.L.U64.HI UR13, UR5, 0x3, UR7 ; /* 0x00000003050d7899 */
/* 0x000fe20008010207 */
/*0230*/ IMAD.MOV.U32 R26, RZ, RZ, R24 ; /* 0x000000ffff1a7224 */
/* 0x000fe200078e0018 */
/*0240*/ USHF.L.U32 UR14, UR5, 0x3, URZ ; /* 0x00000003050e7899 */
/* 0x000fe4000800063f */
/*0250*/ USHF.L.U64.HI UR15, UR8, 0x3, UR9 ; /* 0x00000003080f7899 */
/* 0x000fe40008010209 */
/*0260*/ USHF.L.U32 UR16, UR8, 0x3, URZ ; /* 0x0000000308107899 */
/* 0x000fe4000800063f */
/*0270*/ UMOV UR12, 0x10 ; /* 0x00000010000c7882 */
/* 0x000fe40000000000 */
/*0280*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fc40008000000 */
/*0290*/ LDG.E.64 R14, [R6.64] ; /* 0x0000000a060e7981 */
/* 0x000ea8000c1e1b00 */
/*02a0*/ LDG.E.64 R12, [R6.64+0x10] ; /* 0x0000100a060c7981 */
/* 0x001ee2000c1e1b00 */
/*02b0*/ IADD3 R18, P3, R14, UR14, RZ ; /* 0x0000000e0e127c10 */
/* 0x004fc4000ff7e0ff */
/*02c0*/ IADD3 R28, P4, R12, UR14, RZ ; /* 0x0000000e0c1c7c10 */
/* 0x008fe4000ff9e0ff */
/*02d0*/ IADD3.X R19, R15, UR13, RZ, P3, !PT ; /* 0x0000000d0f137c10 */
/* 0x000fe40009ffe4ff */
/*02e0*/ IADD3.X R29, R13, UR13, RZ, P4, !PT ; /* 0x0000000d0d1d7c10 */
/* 0x000fe4000a7fe4ff */
/*02f0*/ LDG.E.64 R12, [R6.64+0x8] ; /* 0x0000080a060c7981 */
/* 0x000ea8000c1e1b00 */
/*0300*/ LDG.E.64 R14, [R18.64] ; /* 0x0000000a120e7981 */
/* 0x000ee8000c1e1b00 */
/*0310*/ LDG.E.64 R16, [R28.64] ; /* 0x0000000a1c107981 */
/* 0x000328000c1e1b00 */
/*0320*/ LDG.E.64 R28, [R10.64] ; /* 0x0000000a0a1c7981 */
/* 0x002f62000c1e1b00 */
/*0330*/ IADD3 R12, P5, R12, UR16, RZ ; /* 0x000000100c0c7c10 */
/* 0x004fc4000ffbe0ff */
/*0340*/ IADD3 R20, P3, R14, UR12, RZ ; /* 0x0000000c0e147c10 */
/* 0x008fe4000ff7e0ff */
/*0350*/ IADD3.X R13, R13, UR15, RZ, P5, !PT ; /* 0x0000000f0d0d7c10 */
/* 0x000fe4000affe4ff */
/*0360*/ IADD3.X R21, R15, UR4, RZ, P3, !PT ; /* 0x000000040f157c10 */
/* 0x000fe40009ffe4ff */
/*0370*/ IADD3 R22, P4, R16, UR12, RZ ; /* 0x0000000c10167c10 */
/* 0x010fe2000ff9e0ff */
/*0380*/ LDG.E.64 R14, [R12.64] ; /* 0x0000000a0c0e7981 */
/* 0x000ea6000c1e1b00 */
/*0390*/ IADD3.X R23, R17, UR4, RZ, P4, !PT ; /* 0x0000000411177c10 */
/* 0x000fe2000a7fe4ff */
/*03a0*/ LDG.E.64 R18, [R12.64+0x10] ; /* 0x0000100a0c127981 */
/* 0x000ee8000c1e1b00 */
/*03b0*/ LDG.E.64 R16, [R8.64] ; /* 0x0000000a08107981 */
/* 0x000f28000c1e1b00 */
/*03c0*/ LDG.E.64 R20, [R20.64+-0x8] ; /* 0xfffff80a14147981 */
/* 0x000ee8000c1e1b00 */
/*03d0*/ LDG.E.64 R22, [R22.64+-0x8] ; /* 0xfffff80a16167981 */
/* 0x000f62000c1e1b00 */
/*03e0*/ IADD3 R14, P3, R14, UR12, RZ ; /* 0x0000000c0e0e7c10 */
/* 0x004fc8000ff7e0ff */
/*03f0*/ IADD3.X R15, R15, UR4, RZ, P3, !PT ; /* 0x000000040f0f7c10 */
/* 0x000fe40009ffe4ff */
/*0400*/ IADD3 R16, P3, R16, UR14, RZ ; /* 0x0000000e10107c10 */
/* 0x010fc8000ff7e0ff */
/*0410*/ LDG.E.64 R14, [R14.64+-0x8] ; /* 0xfffff80a0e0e7981 */
/* 0x000ea2000c1e1b00 */
/*0420*/ IADD3.X R17, R17, UR13, RZ, P3, !PT ; /* 0x0000000d11117c10 */
/* 0x000fe40009ffe4ff */
/*0430*/ IADD3 R18, P3, R18, UR12, RZ ; /* 0x0000000c12127c10 */
/* 0x008fe2000ff7e0ff */
/*0440*/ DADD R20, R22, R20 ; /* 0x0000000016147229 */
/* 0x0202a40000000014 */
/*0450*/ LDG.E.64 R22, [R12.64+0x8] ; /* 0x0000080a0c167981 */
/* 0x002ee2000c1e1b00 */
/*0460*/ IADD3.X R19, R19, UR4, RZ, P3, !PT ; /* 0x0000000413137c10 */
/* 0x000fc60009ffe4ff */
/*0470*/ LDG.E.64 R16, [R16.64] ; /* 0x0000000a10107981 */
/* 0x000f28000c1e1b00 */
/*0480*/ LDG.E.64 R18, [R18.64+-0x8] ; /* 0xfffff80a12127981 */
/* 0x000f62000c1e1b00 */
/*0490*/ DADD R14, R20, R14 ; /* 0x00000000140e7229 */
/* 0x004764000000000e */
/*04a0*/ IADD3 R20, P3, R22, UR12, RZ ; /* 0x0000000c16147c10 */
/* 0x008fc8000ff7e0ff */
/*04b0*/ IADD3.X R21, R23, UR4, RZ, P3, !PT ; /* 0x0000000417157c10 */
/* 0x000fe40009ffe4ff */
/*04c0*/ IADD3 R12, P3, R16, UR12, RZ ; /* 0x0000000c100c7c10 */
/* 0x010fe2000ff7e0ff */
/*04d0*/ DADD R22, R14, R18 ; /* 0x000000000e167229 */
/* 0x0202a40000000012 */
/*04e0*/ LDG.E.64 R14, [R20.64+-0x10] ; /* 0xfffff00a140e7981 */
/* 0x002ea2000c1e1b00 */
/*04f0*/ IADD3.X R13, R17, UR4, RZ, P3, !PT ; /* 0x00000004110d7c10 */
/* 0x000fe40009ffe4ff */
/*0500*/ IADD3 R28, P3, R28, UR14, RZ ; /* 0x0000000e1c1c7c10 */
/* 0x000fe2000ff7e0ff */
/*0510*/ LDG.E.64 R18, [R20.64] ; /* 0x0000000a14127981 */
/* 0x000ee6000c1e1b00 */
/*0520*/ IADD3.X R29, R29, UR13, RZ, P3, !PT ; /* 0x0000000d1d1d7c10 */
/* 0x000fe20009ffe4ff */
/*0530*/ LDG.E.64 R12, [R12.64+-0x8] ; /* 0xfffff80a0c0c7981 */
/* 0x000f2a000c1e1b00 */
/*0540*/ LDG.E.64 R28, [R28.64] ; /* 0x0000000a1c1c7981 */
/* 0x000f62000c1e1b00 */
/*0550*/ DADD R14, R22, R14 ; /* 0x00000000160e7229 */
/* 0x004ecc000000000e */
/*0560*/ DADD R14, R14, R18 ; /* 0x000000000e0e7229 */
/* 0x008f0c0000000012 */
/*0570*/ DFMA R14, R4, R12, R14 ; /* 0x0000000c040e722b */
/* 0x011e22000000000e */
/*0580*/ IADD3 R16, P3, R28, UR12, RZ ; /* 0x0000000c1c107c10 */
/* 0x020fca000ff7e0ff */
/*0590*/ DMUL R22, R14, c[0x0][0x188] ; /* 0x000062000e167a28 */
/* 0x001e220000000000 */
/*05a0*/ IADD3.X R17, R29, UR4, RZ, P3, !PT ; /* 0x000000041d117c10 */
/* 0x000fcc0009ffe4ff */
/*05b0*/ STG.E.64 [R16.64+-0x8], R22 ; /* 0xfffff81610007986 */
/* 0x0011e8000c101b0a */
/*05c0*/ LDG.E.64 R14, [R6.64] ; /* 0x0000000a060e7981 */
/* 0x000ea8000c1e1b00 */
/*05d0*/ LDG.E.64 R18, [R6.64+0x10] ; /* 0x0000100a06127981 */
/* 0x000ee8000c1e1b00 */
/*05e0*/ LDG.E.64 R16, [R6.64+0x8] ; /* 0x0000080a06107981 */
/* 0x001f22000c1e1b00 */
/*05f0*/ IADD3 R14, P3, R14, UR14, RZ ; /* 0x0000000e0e0e7c10 */
/* 0x004fc4000ff7e0ff */
/*0600*/ IADD3 R28, P4, R18, UR14, RZ ; /* 0x0000000e121c7c10 */
/* 0x008fe4000ff9e0ff */
/*0610*/ IADD3.X R15, R15, UR13, RZ, P3, !PT ; /* 0x0000000d0f0f7c10 */
/* 0x000fe40009ffe4ff */
/*0620*/ IADD3.X R29, R19, UR13, RZ, P4, !PT ; /* 0x0000000d131d7c10 */
/* 0x000fc8000a7fe4ff */
/*0630*/ LDG.E.64 R14, [R14.64] ; /* 0x0000000a0e0e7981 */
/* 0x000ea8000c1e1b00 */
/*0640*/ LDG.E.64 R12, [R28.64] ; /* 0x0000000a1c0c7981 */
/* 0x000ee2000c1e1b00 */
/*0650*/ IADD3 R18, P3, R16, UR16, RZ ; /* 0x0000001010127c10 */
/* 0x010fc8000ff7e0ff */
/*0660*/ IADD3.X R19, R17, UR15, RZ, P3, !PT ; /* 0x0000000f11137c10 */
/* 0x000fca0009ffe4ff */
/*0670*/ LDG.E.64 R16, [R18.64] ; /* 0x0000000a12107981 */
/* 0x000f22000c1e1b00 */
/*0680*/ IADD3 R20, P3, R14, UR12, RZ ; /* 0x0000000c0e147c10 */
/* 0x004fe4000ff7e0ff */
/*0690*/ IADD3 R12, P4, R12, UR12, RZ ; /* 0x0000000c0c0c7c10 */
/* 0x008fe4000ff9e0ff */
/*06a0*/ IADD3.X R21, R15, UR4, RZ, P3, !PT ; /* 0x000000040f157c10 */
/* 0x000fe40009ffe4ff */
/*06b0*/ IADD3.X R13, R13, UR4, RZ, P4, !PT ; /* 0x000000040d0d7c10 */
/* 0x000fe2000a7fe4ff */
/*06c0*/ LDG.E.64 R14, [R8.64] ; /* 0x0000000a080e7981 */
/* 0x000ea8000c1e1b00 */
/*06d0*/ LDG.E.64 R20, [R20.64] ; /* 0x0000000a14147981 */
/* 0x000ee8000c1e1b00 */
/*06e0*/ LDG.E.64 R12, [R12.64] ; /* 0x0000000a0c0c7981 */
/* 0x000ee2000c1e1b00 */
/*06f0*/ IADD3 R28, P3, R16, UR12, RZ ; /* 0x0000000c101c7c10 */
/* 0x010fc8000ff7e0ff */
/*0700*/ IADD3.X R29, R17, UR4, RZ, P3, !PT ; /* 0x00000004111d7c10 */
/* 0x000fe40009ffe4ff */
/*0710*/ LDG.E.64 R16, [R10.64] ; /* 0x0000000a0a107981 */
/* 0x000f28000c1e1b00 */
/*0720*/ LDG.E.64 R22, [R28.64] ; /* 0x0000000a1c167981 */
/* 0x000f62000c1e1b00 */
/*0730*/ DADD R20, R12, R20 ; /* 0x000000000c147229 */
/* 0x0081460000000014 */
/*0740*/ LDG.E.64 R12, [R18.64+0x10] ; /* 0x0000100a120c7981 */
/* 0x0010e2000c1e1b00 */
/*0750*/ IADD3 R14, P3, R14, UR14, RZ ; /* 0x0000000e0e0e7c10 */
/* 0x004fc8000ff7e0ff */
/*0760*/ IADD3.X R15, R15, UR13, RZ, P3, !PT ; /* 0x0000000d0f0f7c10 */
/* 0x000fe20009ffe4ff */
/*0770*/ LDG.E.64 R18, [R18.64+0x8] ; /* 0x0000080a12127981 */
/* 0x001eaa000c1e1b00 */
/*0780*/ LDG.E.64 R14, [R14.64] ; /* 0x0000000a0e0e7981 */
/* 0x000ea2000c1e1b00 */
/*0790*/ IADD3 R16, P4, R16, UR14, RZ ; /* 0x0000000e10107c10 */
/* 0x010fe2000ff9e0ff */
/*07a0*/ DADD R22, R20, R22 ; /* 0x0000000014167229 */
/* 0x0200460000000016 */
/*07b0*/ IADD3.X R17, R17, UR13, RZ, P4, !PT ; /* 0x0000000d11117c10 */
/* 0x000fcc000a7fe4ff */
/*07c0*/ LDG.E.64 R16, [R16.64] ; /* 0x0000000a10107981 */
/* 0x000f22000c1e1b00 */
/*07d0*/ IADD3 R12, P3, R12, UR12, RZ ; /* 0x0000000c0c0c7c10 */
/* 0x008fc8000ff7e0ff */
/*07e0*/ IADD3.X R13, R13, UR4, RZ, P3, !PT ; /* 0x000000040d0d7c10 */
/* 0x000fe40009ffe4ff */
/*07f0*/ IADD3 R28, P3, R18, UR12, RZ ; /* 0x0000000c121c7c10 */
/* 0x004fc8000ff7e0ff */
/*0800*/ LDG.E.64 R12, [R12.64] ; /* 0x0000000a0c0c7981 */
/* 0x000e62000c1e1b00 */
/*0810*/ IADD3.X R29, R19, UR4, RZ, P3, !PT ; /* 0x00000004131d7c10 */
/* 0x000fe40009ffe4ff */
/*0820*/ IADD3 R14, P3, R14, UR12, RZ ; /* 0x0000000c0e0e7c10 */
/* 0x000fc6000ff7e0ff */
/*0830*/ LDG.E.64 R18, [R28.64+-0x8] ; /* 0xfffff80a1c127981 */
/* 0x000ea2000c1e1b00 */
/*0840*/ IADD3.X R15, R15, UR4, RZ, P3, !PT ; /* 0x000000040f0f7c10 */
/* 0x000fc60009ffe4ff */
/*0850*/ LDG.E.64 R20, [R28.64+0x8] ; /* 0x0000080a1c147981 */
/* 0x001ee8000c1e1b00 */
/*0860*/ LDG.E.64 R14, [R14.64] ; /* 0x0000000a0e0e7981 */
/* 0x000f62000c1e1b00 */
/*0870*/ IADD3 R26, R26, -0x2, RZ ; /* 0xfffffffe1a1a7810 */
/* 0x000fe40007ffe0ff */
/*0880*/ IADD3 R25, R25, 0x2, RZ ; /* 0x0000000219197810 */
/* 0x000fe20007ffe0ff */
/*0890*/ DADD R22, R22, R12 ; /* 0x0000000016167229 */
/* 0x002e8c000000000c */
/*08a0*/ DADD R18, R22, R18 ; /* 0x0000000016127229 */
/* 0x004ee20000000012 */
/*08b0*/ IADD3 R12, P3, R16, UR12, RZ ; /* 0x0000000c100c7c10 */
/* 0x010fca000ff7e0ff */
/*08c0*/ DADD R18, R18, R20 ; /* 0x0000000012127229 */
/* 0x008f620000000014 */
/*08d0*/ IADD3.X R13, R17, UR4, RZ, P3, !PT ; /* 0x00000004110d7c10 */
/* 0x000fe40009ffe4ff */
/*08e0*/ ISETP.NE.AND P3, PT, R26, 0x2, PT ; /* 0x000000021a00780c */
/* 0x000fc60003f65270 */
/*08f0*/ DFMA R18, R4, R14, R18 ; /* 0x0000000e0412722b */
/* 0x020e220000000012 */
/*0900*/ UIADD3 UR12, UP0, UR12, 0x10, URZ ; /* 0x000000100c0c7890 */
/* 0x000fca000ff1e03f */
/*0910*/ DMUL R18, R18, c[0x0][0x188] ; /* 0x0000620012127a28 */
/* 0x001e220000000000 */
/*0920*/ UIADD3.X UR4, URZ, UR4, URZ, UP0, !UPT ; /* 0x000000043f047290 */
/* 0x000fcc00087fe43f */
/*0930*/ STG.E.64 [R12.64], R18 ; /* 0x000000120c007986 */
/* 0x0011e2000c101b0a */
/*0940*/ @P3 BRA 0x290 ; /* 0xfffff94000003947 */
/* 0x000fea000383ffff */
/*0950*/ @!P1 BRA 0xc90 ; /* 0x0000033000009947 */
/* 0x000fea0003800000 */
/*0960*/ LDG.E.64 R12, [R6.64+0x8] ; /* 0x0000080a060c7981 */
/* 0x001ea8000c1e1b00 */
/*0970*/ LDG.E.64 R16, [R6.64] ; /* 0x0000000a06107981 */
/* 0x000ee8000c1e1b00 */
/*0980*/ LDG.E.64 R14, [R6.64+0x10] ; /* 0x0000100a060e7981 */
/* 0x000f22000c1e1b00 */
/*0990*/ USHF.L.U32 UR13, UR5, 0x3, URZ ; /* 0x00000003050d7899 */
/* 0x000fc4000800063f */
/*09a0*/ USHF.L.U64.HI UR7, UR5, 0x3, UR7 ; /* 0x0000000305077899 */
/* 0x000fe20008010207 */
/*09b0*/ LDG.E.64 R20, [R8.64] ; /* 0x0000000a08147981 */
/* 0x000f62000c1e1b00 */
/*09c0*/ R2UR UR4, R12 ; /* 0x000000000c0473c2 */
/* 0x004e3000000e0000 */
/*09d0*/ R2UR UR5, R13 ; /* 0x000000000d0573c2 */
/* 0x000e6200000e0000 */
/*09e0*/ IADD3 R26, P1, R16, UR13, RZ ; /* 0x0000000d101a7c10 */
/* 0x008fc4000ff3e0ff */
/*09f0*/ IADD3 R28, P3, R14, UR13, RZ ; /* 0x0000000d0e1c7c10 */
/* 0x010fe4000ff7e0ff */
/*0a00*/ IADD3.X R27, R17, UR7, RZ, P1, !PT ; /* 0x00000007111b7c10 */
/* 0x000fe40008ffe4ff */
/*0a10*/ IADD3.X R29, R15, UR7, RZ, P3, !PT ; /* 0x000000070f1d7c10 */
/* 0x000fc60009ffe4ff */
/*0a20*/ LDG.E.64 R14, [R26.64] ; /* 0x0000000a1a0e7981 */
/* 0x0004e8000c1e1b00 */
/*0a30*/ LDG.E.64 R16, [R28.64] ; /* 0x0000000a1c107981 */
/* 0x000b22000c1e1b00 */
/*0a40*/ ULEA UR12, UP0, UR8, UR4, 0x3 ; /* 0x00000004080c7291 */
/* 0x001fc8000f80183f */
/*0a50*/ ULEA.HI.X UR4, UR8, UR5, UR9, 0x3, UP0 ; /* 0x0000000508047291 */
/* 0x002fe400080f1c09 */
/*0a60*/ IMAD.U32 R22, RZ, RZ, UR12 ; /* 0x0000000cff167e24 */
/* 0x000fc8000f8e00ff */
/*0a70*/ IMAD.U32 R23, RZ, RZ, UR4 ; /* 0x00000004ff177e24 */
/* 0x000fca000f8e00ff */
/*0a80*/ LDG.E.64 R18, [R22.64] ; /* 0x0000000a16127981 */
/* 0x000128000c1e1b00 */
/*0a90*/ LDG.E.64 R12, [R22.64+0x10] ; /* 0x0000100a160c7981 */
/* 0x000122000c1e1b00 */
/*0aa0*/ IADD3 R28, P1, R20, UR13, RZ ; /* 0x0000000d141c7c10 */
/* 0x020fc6000ff3e0ff */
/*0ab0*/ LDG.E.64 R26, [R22.64+0x8] ; /* 0x0000080a161a7981 */
/* 0x0040a2000c1e1b00 */
/*0ac0*/ IADD3.X R29, R21, UR7, RZ, P1, !PT ; /* 0x00000007151d7c10 */
/* 0x000fc60008ffe4ff */
/*0ad0*/ LDG.E.64 R20, [R10.64] ; /* 0x0000000a0a147981 */
/* 0x000f68000c1e1b00 */
/*0ae0*/ LDG.E.64 R22, [R28.64] ; /* 0x0000000a1c167981 */
/* 0x001ea2000c1e1b00 */
/*0af0*/ IMAD.WIDE R14, R25, 0x8, R14 ; /* 0x00000008190e7825 */
/* 0x008fc800078e020e */
/*0b00*/ IMAD.WIDE R16, R25.reuse, 0x8, R16 ; /* 0x0000000819107825 */
/* 0x050fe400078e0210 */
/*0b10*/ LDG.E.64 R14, [R14.64] ; /* 0x0000000a0e0e7981 */
/* 0x000ee8000c1e1b00 */
/*0b20*/ LDG.E.64 R16, [R16.64] ; /* 0x0000000a10107981 */
/* 0x000ee2000c1e1b00 */
/*0b30*/ IMAD.WIDE R18, R25, 0x8, R18 ; /* 0x0000000819127825 */
/* 0x000fcc00078e0212 */
/*0b40*/ LDG.E.64 R18, [R18.64] ; /* 0x0000000a12127981 */
/* 0x000f22000c1e1b00 */
/*0b50*/ IMAD.WIDE R12, R25, 0x8, R12 ; /* 0x00000008190c7825 */
/* 0x000fcc00078e020c */
/*0b60*/ LDG.E.64 R12, [R12.64] ; /* 0x0000000a0c0c7981 */
/* 0x000f22000c1e1b00 */
/*0b70*/ IADD3 R20, P1, R20, UR13, RZ ; /* 0x0000000d14147c10 */
/* 0x020fe2000ff3e0ff */
/*0b80*/ IMAD.WIDE R22, R25, 0x8, R22 ; /* 0x0000000819167825 */
/* 0x004fc600078e0216 */
/*0b90*/ IADD3.X R21, R21, UR7, RZ, P1, !PT ; /* 0x0000000715157c10 */
/* 0x000fc60008ffe4ff */
/*0ba0*/ LDG.E.64 R22, [R22.64] ; /* 0x0000000a16167981 */
/* 0x000ea8000c1e1b00 */
/*0bb0*/ LDG.E.64 R20, [R20.64] ; /* 0x0000000a14147981 */
/* 0x000f62000c1e1b00 */
/*0bc0*/ DADD R14, R16, R14 ; /* 0x00000000100e7229 */
/* 0x008124000000000e */
/*0bd0*/ IADD3 R17, R25, -0x1, RZ ; /* 0xffffffff19117810 */
/* 0x001fca0007ffe0ff */
/*0be0*/ IMAD.WIDE R26, R17, 0x8, R26 ; /* 0x00000008111a7825 */
/* 0x000fca00078e021a */
/*0bf0*/ LDG.E.64 R16, [R26.64] ; /* 0x0000000a1a107981 */
/* 0x000ee2000c1e1b00 */
/*0c00*/ DADD R18, R14, R18 ; /* 0x000000000e127229 */
/* 0x0100460000000012 */
/*0c10*/ LDG.E.64 R14, [R26.64+0x10] ; /* 0x0000100a1a0e7981 */
/* 0x001f26000c1e1b00 */
/*0c20*/ DADD R18, R18, R12 ; /* 0x0000000012127229 */
/* 0x002ae4000000000c */
/*0c30*/ IMAD.WIDE R12, R25, 0x8, R20 ; /* 0x00000008190c7825 */
/* 0x020fc800078e0214 */
/*0c40*/ DADD R16, R18, R16 ; /* 0x0000000012107229 */
/* 0x008f0c0000000010 */
/*0c50*/ DADD R14, R16, R14 ; /* 0x00000000100e7229 */
/* 0x010e8c000000000e */
/*0c60*/ DFMA R14, R4, R22, R14 ; /* 0x00000016040e722b */
/* 0x004e0c000000000e */
/*0c70*/ DMUL R14, R14, c[0x0][0x188] ; /* 0x000062000e0e7a28 */
/* 0x001e0e0000000000 */
/*0c80*/ STG.E.64 [R12.64], R14 ; /* 0x0000000e0c007986 */
/* 0x0011e8000c101b0a */
/*0c90*/ @!P2 BRA 0x160 ; /* 0xfffff4c00000a947 */
/* 0x000fea000383ffff */
/*0ca0*/ @!P0 BRA 0xd0 ; /* 0xfffff42000008947 */
/* 0x000fea000383ffff */
/*0cb0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0cc0*/ BRA 0xcc0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0cd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ce0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /* jacobi.c - Poisson problem in 3d
*
*/
#include <math.h>
#include <stdio.h>
__device__ void print_matrix2(double*** A, int N){
int i,j,k;
for (i=0; i<N; i++){
printf("\n %d -th Layer \n", i);
for(j=0; j<N; j++){
for(k=0; k<N; k++){
printf("%lf \t", A[i][j][k]);
}
printf("\n");
}
}
}
__global__ void jacobi_gpu1(double*** u, double***prev_u, double*** f, int N, double step_width, double denominator) {
//iteration: checking norm and Nr of iterations at the same time
double temp;
int i,j,k= 0;
for (i=1; i<N-1; i++){
for (j=1; j<N-1; j++){
for (k=1; k<N-1; k++){
temp=prev_u[i-1][j][k] + prev_u[i+1][j][k]+ prev_u[i][j-1][k] + prev_u[i][j+1][k] + prev_u[i][j][k-1]
+ prev_u[i][j][k+1] + step_width*step_width*f[i][j][k];
u[i][j][k]=temp*denominator;
//printf("For %d %d %d \n", i,j,k,temp*denominator);
//printf("We have in the matrix: %lf \n", u[i][j][k]);
}
}
}
//printf("On the GPU we now have matrix:\n");
//print_matrix2(u,N);
} | .file "tmpxft_00188127_00000000-6_jacobi.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z13print_matrix2PPPdi
.type _Z13print_matrix2PPPdi, @function
_Z13print_matrix2PPPdi:
.LFB2057:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size _Z13print_matrix2PPPdi, .-_Z13print_matrix2PPPdi
.globl _Z42__device_stub__Z11jacobi_gpu1PPPdS1_S1_iddPPPdS1_S1_idd
.type _Z42__device_stub__Z11jacobi_gpu1PPPdS1_S1_iddPPPdS1_S1_idd, @function
_Z42__device_stub__Z11jacobi_gpu1PPPdS1_S1_iddPPPdS1_S1_idd:
.LFB2082:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movsd %xmm0, 8(%rsp)
movsd %xmm1, (%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
movq %rsp, %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L9
.L5:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L10
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z11jacobi_gpu1PPPdS1_S1_idd(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L5
.L10:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z42__device_stub__Z11jacobi_gpu1PPPdS1_S1_iddPPPdS1_S1_idd, .-_Z42__device_stub__Z11jacobi_gpu1PPPdS1_S1_iddPPPdS1_S1_idd
.globl _Z11jacobi_gpu1PPPdS1_S1_idd
.type _Z11jacobi_gpu1PPPdS1_S1_idd, @function
_Z11jacobi_gpu1PPPdS1_S1_idd:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z42__device_stub__Z11jacobi_gpu1PPPdS1_S1_iddPPPdS1_S1_idd
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z11jacobi_gpu1PPPdS1_S1_idd, .-_Z11jacobi_gpu1PPPdS1_S1_idd
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z11jacobi_gpu1PPPdS1_S1_idd"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z11jacobi_gpu1PPPdS1_S1_idd(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /* jacobi.c - Poisson problem in 3d
*
*/
#include <math.h>
#include <stdio.h>
__device__ void print_matrix2(double*** A, int N){
int i,j,k;
for (i=0; i<N; i++){
printf("\n %d -th Layer \n", i);
for(j=0; j<N; j++){
for(k=0; k<N; k++){
printf("%lf \t", A[i][j][k]);
}
printf("\n");
}
}
}
__global__ void jacobi_gpu1(double*** u, double***prev_u, double*** f, int N, double step_width, double denominator) {
//iteration: checking norm and Nr of iterations at the same time
double temp;
int i,j,k= 0;
for (i=1; i<N-1; i++){
for (j=1; j<N-1; j++){
for (k=1; k<N-1; k++){
temp=prev_u[i-1][j][k] + prev_u[i+1][j][k]+ prev_u[i][j-1][k] + prev_u[i][j+1][k] + prev_u[i][j][k-1]
+ prev_u[i][j][k+1] + step_width*step_width*f[i][j][k];
u[i][j][k]=temp*denominator;
//printf("For %d %d %d \n", i,j,k,temp*denominator);
//printf("We have in the matrix: %lf \n", u[i][j][k]);
}
}
}
//printf("On the GPU we now have matrix:\n");
//print_matrix2(u,N);
} | /* jacobi.c - Poisson problem in 3d
*
*/
#include <hip/hip_runtime.h>
#include <math.h>
#include <stdio.h>
__device__ void print_matrix2(double*** A, int N){
int i,j,k;
for (i=0; i<N; i++){
printf("\n %d -th Layer \n", i);
for(j=0; j<N; j++){
for(k=0; k<N; k++){
printf("%lf \t", A[i][j][k]);
}
printf("\n");
}
}
}
__global__ void jacobi_gpu1(double*** u, double***prev_u, double*** f, int N, double step_width, double denominator) {
//iteration: checking norm and Nr of iterations at the same time
double temp;
int i,j,k= 0;
for (i=1; i<N-1; i++){
for (j=1; j<N-1; j++){
for (k=1; k<N-1; k++){
temp=prev_u[i-1][j][k] + prev_u[i+1][j][k]+ prev_u[i][j-1][k] + prev_u[i][j+1][k] + prev_u[i][j][k-1]
+ prev_u[i][j][k+1] + step_width*step_width*f[i][j][k];
u[i][j][k]=temp*denominator;
//printf("For %d %d %d \n", i,j,k,temp*denominator);
//printf("We have in the matrix: %lf \n", u[i][j][k]);
}
}
}
//printf("On the GPU we now have matrix:\n");
//print_matrix2(u,N);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | /* jacobi.c - Poisson problem in 3d
*
*/
#include <hip/hip_runtime.h>
#include <math.h>
#include <stdio.h>
__device__ void print_matrix2(double*** A, int N){
int i,j,k;
for (i=0; i<N; i++){
printf("\n %d -th Layer \n", i);
for(j=0; j<N; j++){
for(k=0; k<N; k++){
printf("%lf \t", A[i][j][k]);
}
printf("\n");
}
}
}
__global__ void jacobi_gpu1(double*** u, double***prev_u, double*** f, int N, double step_width, double denominator) {
//iteration: checking norm and Nr of iterations at the same time
double temp;
int i,j,k= 0;
for (i=1; i<N-1; i++){
for (j=1; j<N-1; j++){
for (k=1; k<N-1; k++){
temp=prev_u[i-1][j][k] + prev_u[i+1][j][k]+ prev_u[i][j-1][k] + prev_u[i][j+1][k] + prev_u[i][j][k-1]
+ prev_u[i][j][k+1] + step_width*step_width*f[i][j][k];
u[i][j][k]=temp*denominator;
//printf("For %d %d %d \n", i,j,k,temp*denominator);
//printf("We have in the matrix: %lf \n", u[i][j][k]);
}
}
}
//printf("On the GPU we now have matrix:\n");
//print_matrix2(u,N);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11jacobi_gpu1PPPdS1_S1_idd
.globl _Z11jacobi_gpu1PPPdS1_S1_idd
.p2align 8
.type _Z11jacobi_gpu1PPPdS1_S1_idd,@function
_Z11jacobi_gpu1PPPdS1_S1_idd:
s_load_b32 s25, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s25, 3
s_cbranch_scc1 .LBB0_7
s_load_b128 s[4:7], s[0:1], 0x20
s_add_i32 s24, s25, -1
s_add_i32 s25, s25, -2
s_mov_b32 s26, 1
s_mov_b32 s13, 0
s_mov_b32 s14, 1
s_waitcnt lgkmcnt(0)
v_mul_f64 v[4:5], s[4:5], s[4:5]
s_clause 0x1
s_load_b128 s[8:11], s[0:1], 0x0
s_load_b64 s[4:5], s[0:1], 0x10
.LBB0_2:
s_mov_b32 s15, s13
s_mov_b32 s12, s26
s_lshl_b64 s[0:1], s[14:15], 3
s_waitcnt lgkmcnt(0)
s_add_u32 s2, s10, s0
s_addc_u32 s3, s11, s1
s_add_u32 s16, s2, -8
s_addc_u32 s17, s3, -1
s_add_u32 s18, s4, s0
s_addc_u32 s19, s5, s1
s_add_u32 s20, s8, s0
s_addc_u32 s21, s9, s1
s_clause 0x1
s_load_b64 s[16:17], s[16:17], 0x0
s_load_b128 s[0:3], s[2:3], 0x0
s_load_b64 s[18:19], s[18:19], 0x0
s_load_b64 s[20:21], s[20:21], 0x0
.LBB0_3:
s_lshl_b64 s[22:23], s[12:13], 3
s_waitcnt lgkmcnt(0)
s_add_u32 s28, s16, s22
s_addc_u32 s29, s17, s23
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v0, s28 :: v_dual_mov_b32 v1, s29
s_add_u32 s30, s2, s22
s_addc_u32 s31, s3, s23
s_add_u32 s28, s0, s22
v_dual_mov_b32 v2, s30 :: v_dual_mov_b32 v3, s31
s_addc_u32 s29, s1, s23
flat_load_b64 v[6:7], v[0:1]
v_add_co_u32 v0, s15, -8, s28
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v1, null, -1, s29, s15
flat_load_b64 v[8:9], v[2:3]
s_add_u32 s30, s18, s22
v_dual_mov_b32 v2, s28 :: v_dual_mov_b32 v3, s29
s_addc_u32 s31, s19, s23
flat_load_b64 v[10:11], v[0:1]
s_add_u32 s22, s20, s22
s_addc_u32 s23, s21, s23
v_dual_mov_b32 v12, s30 :: v_dual_mov_b32 v13, s31
flat_load_b128 v[0:3], v[2:3]
v_dual_mov_b32 v14, s22 :: v_dual_mov_b32 v15, s23
flat_load_b64 v[12:13], v[12:13]
flat_load_b64 v[14:15], v[14:15]
s_mov_b64 s[22:23], 0
s_mov_b32 s15, s25
s_waitcnt vmcnt(5) lgkmcnt(5)
v_add_co_u32 v6, vcc_lo, v6, 8
v_add_co_ci_u32_e32 v7, vcc_lo, 0, v7, vcc_lo
s_waitcnt vmcnt(4) lgkmcnt(4)
v_add_co_u32 v8, vcc_lo, v8, 8
v_add_co_ci_u32_e32 v9, vcc_lo, 0, v9, vcc_lo
s_waitcnt vmcnt(3) lgkmcnt(3)
v_add_co_u32 v10, vcc_lo, v10, 8
v_add_co_ci_u32_e32 v11, vcc_lo, 0, v11, vcc_lo
s_waitcnt vmcnt(2) lgkmcnt(2)
v_add_co_u32 v2, vcc_lo, v2, 8
v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
s_waitcnt vmcnt(1) lgkmcnt(1)
v_add_co_u32 v12, vcc_lo, v12, 8
v_add_co_ci_u32_e32 v13, vcc_lo, 0, v13, vcc_lo
s_waitcnt vmcnt(0) lgkmcnt(0)
v_add_co_u32 v14, vcc_lo, v14, 8
v_add_co_ci_u32_e32 v15, vcc_lo, 0, v15, vcc_lo
.LBB0_4:
v_add_co_u32 v16, vcc_lo, v6, s22
v_add_co_ci_u32_e32 v17, vcc_lo, s23, v7, vcc_lo
v_add_co_u32 v18, vcc_lo, v8, s22
v_add_co_ci_u32_e32 v19, vcc_lo, s23, v9, vcc_lo
v_add_co_u32 v20, vcc_lo, v10, s22
flat_load_b64 v[16:17], v[16:17]
flat_load_b64 v[18:19], v[18:19]
v_add_co_ci_u32_e32 v21, vcc_lo, s23, v11, vcc_lo
v_add_co_u32 v22, vcc_lo, v2, s22
v_add_co_ci_u32_e32 v23, vcc_lo, s23, v3, vcc_lo
flat_load_b64 v[20:21], v[20:21]
v_add_co_u32 v24, vcc_lo, v0, s22
flat_load_b64 v[22:23], v[22:23]
v_add_co_ci_u32_e32 v25, vcc_lo, s23, v1, vcc_lo
s_clause 0x1
flat_load_b64 v[26:27], v[24:25]
flat_load_b64 v[24:25], v[24:25] offset:16
v_add_co_u32 v28, vcc_lo, v12, s22
v_add_co_ci_u32_e32 v29, vcc_lo, s23, v13, vcc_lo
s_add_i32 s15, s15, -1
flat_load_b64 v[28:29], v[28:29]
s_waitcnt vmcnt(5) lgkmcnt(5)
v_add_f64 v[16:17], v[16:17], v[18:19]
v_add_co_u32 v18, vcc_lo, v14, s22
v_add_co_ci_u32_e32 v19, vcc_lo, s23, v15, vcc_lo
s_add_u32 s22, s22, 8
s_addc_u32 s23, s23, 0
s_cmp_lg_u32 s15, 0
s_waitcnt vmcnt(4) lgkmcnt(4)
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_f64 v[16:17], v[16:17], v[20:21]
s_waitcnt vmcnt(3) lgkmcnt(3)
v_add_f64 v[16:17], v[16:17], v[22:23]
s_waitcnt vmcnt(2) lgkmcnt(2)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_f64 v[16:17], v[16:17], v[26:27]
s_waitcnt vmcnt(1) lgkmcnt(1)
v_add_f64 v[16:17], v[16:17], v[24:25]
s_waitcnt vmcnt(0) lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[16:17], v[4:5], v[28:29], v[16:17]
v_mul_f64 v[16:17], v[16:17], s[6:7]
flat_store_b64 v[18:19], v[16:17]
s_cbranch_scc1 .LBB0_4
s_add_i32 s12, s12, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lg_u32 s12, s24
s_cbranch_scc1 .LBB0_3
s_add_i32 s14, s14, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lg_u32 s14, s24
s_cbranch_scc1 .LBB0_2
.LBB0_7:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11jacobi_gpu1PPPdS1_S1_idd
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 48
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 30
.amdhsa_next_free_sgpr 32
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z11jacobi_gpu1PPPdS1_S1_idd, .Lfunc_end0-_Z11jacobi_gpu1PPPdS1_S1_idd
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 8
.value_kind: by_value
- .offset: 40
.size: 8
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 48
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11jacobi_gpu1PPPdS1_S1_idd
.private_segment_fixed_size: 0
.sgpr_count: 34
.sgpr_spill_count: 0
.symbol: _Z11jacobi_gpu1PPPdS1_S1_idd.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 30
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | /* jacobi.c - Poisson problem in 3d
*
*/
#include <hip/hip_runtime.h>
#include <math.h>
#include <stdio.h>
__device__ void print_matrix2(double*** A, int N){
int i,j,k;
for (i=0; i<N; i++){
printf("\n %d -th Layer \n", i);
for(j=0; j<N; j++){
for(k=0; k<N; k++){
printf("%lf \t", A[i][j][k]);
}
printf("\n");
}
}
}
__global__ void jacobi_gpu1(double*** u, double***prev_u, double*** f, int N, double step_width, double denominator) {
//iteration: checking norm and Nr of iterations at the same time
double temp;
int i,j,k= 0;
for (i=1; i<N-1; i++){
for (j=1; j<N-1; j++){
for (k=1; k<N-1; k++){
temp=prev_u[i-1][j][k] + prev_u[i+1][j][k]+ prev_u[i][j-1][k] + prev_u[i][j+1][k] + prev_u[i][j][k-1]
+ prev_u[i][j][k+1] + step_width*step_width*f[i][j][k];
u[i][j][k]=temp*denominator;
//printf("For %d %d %d \n", i,j,k,temp*denominator);
//printf("We have in the matrix: %lf \n", u[i][j][k]);
}
}
}
//printf("On the GPU we now have matrix:\n");
//print_matrix2(u,N);
} | .text
.file "jacobi.hip"
.globl _Z26__device_stub__jacobi_gpu1PPPdS1_S1_idd # -- Begin function _Z26__device_stub__jacobi_gpu1PPPdS1_S1_idd
.p2align 4, 0x90
.type _Z26__device_stub__jacobi_gpu1PPPdS1_S1_idd,@function
_Z26__device_stub__jacobi_gpu1PPPdS1_S1_idd: # @_Z26__device_stub__jacobi_gpu1PPPdS1_S1_idd
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 4(%rsp)
movsd %xmm0, 64(%rsp)
movsd %xmm1, 56(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
leaq 64(%rsp), %rax
movq %rax, 128(%rsp)
leaq 56(%rsp), %rax
movq %rax, 136(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z11jacobi_gpu1PPPdS1_S1_idd, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z26__device_stub__jacobi_gpu1PPPdS1_S1_idd, .Lfunc_end0-_Z26__device_stub__jacobi_gpu1PPPdS1_S1_idd
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11jacobi_gpu1PPPdS1_S1_idd, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z11jacobi_gpu1PPPdS1_S1_idd,@object # @_Z11jacobi_gpu1PPPdS1_S1_idd
.section .rodata,"a",@progbits
.globl _Z11jacobi_gpu1PPPdS1_S1_idd
.p2align 3, 0x0
_Z11jacobi_gpu1PPPdS1_S1_idd:
.quad _Z26__device_stub__jacobi_gpu1PPPdS1_S1_idd
.size _Z11jacobi_gpu1PPPdS1_S1_idd, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z11jacobi_gpu1PPPdS1_S1_idd"
.size .L__unnamed_1, 29
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__jacobi_gpu1PPPdS1_S1_idd
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11jacobi_gpu1PPPdS1_S1_idd
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z11jacobi_gpu1PPPdS1_S1_idd
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x178] ; /* 0x00005e00ff027624 */
/* 0x000fca00078e00ff */
/*0020*/ ISETP.GE.AND P0, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fda0003f06270 */
/*0030*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0040*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x180] ; /* 0x00006000ff047624 */
/* 0x000fe200078e00ff */
/*0050*/ IADD3 R0, R2.reuse, -0x2, RZ ; /* 0xfffffffe02007810 */
/* 0x040fe20007ffe0ff */
/*0060*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x184] ; /* 0x00006100ff057624 */
/* 0x000fe200078e00ff */
/*0070*/ IADD3 R2, R2, -0x1, RZ ; /* 0xffffffff02027810 */
/* 0x000fe20007ffe0ff */
/*0080*/ IMAD.MOV.U32 R3, RZ, RZ, 0x1 ; /* 0x00000001ff037424 */
/* 0x000fe200078e00ff */
/*0090*/ LOP3.LUT R0, R0, 0x1, RZ, 0xc0, !PT ; /* 0x0000000100007812 */
/* 0x000fe200078ec0ff */
/*00a0*/ ULDC.64 UR10, c[0x0][0x118] ; /* 0x00004600000a7ab9 */
/* 0x000fe40000000a00 */
/*00b0*/ DMUL R4, R4, c[0x0][0x180] ; /* 0x0000600004047a28 */
/* 0x000e220000000000 */
/*00c0*/ IADD3 R24, -R0, c[0x0][0x178], RZ ; /* 0x00005e0000187a10 */
/* 0x000fc60007ffe1ff */
/*00d0*/ IADD3 R6, R3.reuse, -0x1, RZ ; /* 0xffffffff03067810 */
/* 0x040fe20007ffe0ff */
/*00e0*/ IMAD.MOV.U32 R10, RZ, RZ, 0x8 ; /* 0x00000008ff0a7424 */
/* 0x000fe200078e00ff */
/*00f0*/ IADD3 R13, R3, 0x1, RZ ; /* 0x00000001030d7810 */
/* 0x001fe20007ffe0ff */
/*0100*/ UMOV UR6, 0x1 ; /* 0x0000000100067882 */
/* 0x000fc40000000000 */
/*0110*/ IMAD.WIDE R6, R6, R10, c[0x0][0x168] ; /* 0x00005a0006067625 */
/* 0x000fe200078e020a */
/*0120*/ ISETP.GE.AND P0, PT, R13, R2, PT ; /* 0x000000020d00720c */
/* 0x000fc60003f06270 */
/*0130*/ IMAD.WIDE R8, R3, R10, c[0x0][0x170] ; /* 0x00005c0003087625 */
/* 0x000fc800078e020a */
/*0140*/ IMAD.WIDE R10, R3, R10, c[0x0][0x160] ; /* 0x00005800030a7625 */
/* 0x000fc800078e020a */
/*0150*/ IMAD.MOV.U32 R3, RZ, RZ, R13 ; /* 0x000000ffff037224 */
/* 0x000fe400078e000d */
/*0160*/ IMAD.MOV.U32 R12, RZ, RZ, c[0x0][0x178] ; /* 0x00005e00ff0c7624 */
/* 0x001fe200078e00ff */
/*0170*/ UMOV UR5, UR6 ; /* 0x0000000600057c82 */
/* 0x000fe20008000000 */
/*0180*/ ISETP.NE.AND P1, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe20003f25270 */
/*0190*/ USHF.R.S32.HI UR7, URZ, 0x1f, UR6 ; /* 0x0000001f3f077899 */
/* 0x000fe20008011406 */
/*01a0*/ IMAD.MOV.U32 R25, RZ, RZ, 0x1 ; /* 0x00000001ff197424 */
/* 0x000fe200078e00ff */
/*01b0*/ ISETP.NE.AND P3, PT, R12, 0x3, PT ; /* 0x000000030c00780c */
/* 0x000fe20003f65270 */
/*01c0*/ UIADD3 UR8, UR6, -0x1, URZ ; /* 0xffffffff06087890 */
/* 0x000fe4000fffe03f */
/*01d0*/ UIADD3 UR6, UR6, 0x1, URZ ; /* 0x0000000106067890 */
/* 0x000fe4000fffe03f */
/*01e0*/ USHF.R.S32.HI UR9, URZ, 0x1f, UR8 ; /* 0x0000001f3f097899 */
/* 0x000fc80008011408 */
/*01f0*/ ISETP.LE.AND P2, PT, R2, UR6, PT ; /* 0x0000000602007c0c */
/* 0x000fc8000bf43270 */
/*0200*/ @!P3 BRA 0x950 ; /* 0x000007400000b947 */
/* 0x000fea0003800000 */
/*0210*/ IMAD.MOV.U32 R25, RZ, RZ, 0x1 ; /* 0x00000001ff197424 */
/* 0x000fe200078e00ff */
/*0220*/ USHF.L.U64.HI UR13, UR5, 0x3, UR7 ; /* 0x00000003050d7899 */
/* 0x000fe20008010207 */
/*0230*/ IMAD.MOV.U32 R26, RZ, RZ, R24 ; /* 0x000000ffff1a7224 */
/* 0x000fe200078e0018 */
/*0240*/ USHF.L.U32 UR14, UR5, 0x3, URZ ; /* 0x00000003050e7899 */
/* 0x000fe4000800063f */
/*0250*/ USHF.L.U64.HI UR15, UR8, 0x3, UR9 ; /* 0x00000003080f7899 */
/* 0x000fe40008010209 */
/*0260*/ USHF.L.U32 UR16, UR8, 0x3, URZ ; /* 0x0000000308107899 */
/* 0x000fe4000800063f */
/*0270*/ UMOV UR12, 0x10 ; /* 0x00000010000c7882 */
/* 0x000fe40000000000 */
/*0280*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fc40008000000 */
/*0290*/ LDG.E.64 R14, [R6.64] ; /* 0x0000000a060e7981 */
/* 0x000ea8000c1e1b00 */
/*02a0*/ LDG.E.64 R12, [R6.64+0x10] ; /* 0x0000100a060c7981 */
/* 0x001ee2000c1e1b00 */
/*02b0*/ IADD3 R18, P3, R14, UR14, RZ ; /* 0x0000000e0e127c10 */
/* 0x004fc4000ff7e0ff */
/*02c0*/ IADD3 R28, P4, R12, UR14, RZ ; /* 0x0000000e0c1c7c10 */
/* 0x008fe4000ff9e0ff */
/*02d0*/ IADD3.X R19, R15, UR13, RZ, P3, !PT ; /* 0x0000000d0f137c10 */
/* 0x000fe40009ffe4ff */
/*02e0*/ IADD3.X R29, R13, UR13, RZ, P4, !PT ; /* 0x0000000d0d1d7c10 */
/* 0x000fe4000a7fe4ff */
/*02f0*/ LDG.E.64 R12, [R6.64+0x8] ; /* 0x0000080a060c7981 */
/* 0x000ea8000c1e1b00 */
/*0300*/ LDG.E.64 R14, [R18.64] ; /* 0x0000000a120e7981 */
/* 0x000ee8000c1e1b00 */
/*0310*/ LDG.E.64 R16, [R28.64] ; /* 0x0000000a1c107981 */
/* 0x000328000c1e1b00 */
/*0320*/ LDG.E.64 R28, [R10.64] ; /* 0x0000000a0a1c7981 */
/* 0x002f62000c1e1b00 */
/*0330*/ IADD3 R12, P5, R12, UR16, RZ ; /* 0x000000100c0c7c10 */
/* 0x004fc4000ffbe0ff */
/*0340*/ IADD3 R20, P3, R14, UR12, RZ ; /* 0x0000000c0e147c10 */
/* 0x008fe4000ff7e0ff */
/*0350*/ IADD3.X R13, R13, UR15, RZ, P5, !PT ; /* 0x0000000f0d0d7c10 */
/* 0x000fe4000affe4ff */
/*0360*/ IADD3.X R21, R15, UR4, RZ, P3, !PT ; /* 0x000000040f157c10 */
/* 0x000fe40009ffe4ff */
/*0370*/ IADD3 R22, P4, R16, UR12, RZ ; /* 0x0000000c10167c10 */
/* 0x010fe2000ff9e0ff */
/*0380*/ LDG.E.64 R14, [R12.64] ; /* 0x0000000a0c0e7981 */
/* 0x000ea6000c1e1b00 */
/*0390*/ IADD3.X R23, R17, UR4, RZ, P4, !PT ; /* 0x0000000411177c10 */
/* 0x000fe2000a7fe4ff */
/*03a0*/ LDG.E.64 R18, [R12.64+0x10] ; /* 0x0000100a0c127981 */
/* 0x000ee8000c1e1b00 */
/*03b0*/ LDG.E.64 R16, [R8.64] ; /* 0x0000000a08107981 */
/* 0x000f28000c1e1b00 */
/*03c0*/ LDG.E.64 R20, [R20.64+-0x8] ; /* 0xfffff80a14147981 */
/* 0x000ee8000c1e1b00 */
/*03d0*/ LDG.E.64 R22, [R22.64+-0x8] ; /* 0xfffff80a16167981 */
/* 0x000f62000c1e1b00 */
/*03e0*/ IADD3 R14, P3, R14, UR12, RZ ; /* 0x0000000c0e0e7c10 */
/* 0x004fc8000ff7e0ff */
/*03f0*/ IADD3.X R15, R15, UR4, RZ, P3, !PT ; /* 0x000000040f0f7c10 */
/* 0x000fe40009ffe4ff */
/*0400*/ IADD3 R16, P3, R16, UR14, RZ ; /* 0x0000000e10107c10 */
/* 0x010fc8000ff7e0ff */
/*0410*/ LDG.E.64 R14, [R14.64+-0x8] ; /* 0xfffff80a0e0e7981 */
/* 0x000ea2000c1e1b00 */
/*0420*/ IADD3.X R17, R17, UR13, RZ, P3, !PT ; /* 0x0000000d11117c10 */
/* 0x000fe40009ffe4ff */
/*0430*/ IADD3 R18, P3, R18, UR12, RZ ; /* 0x0000000c12127c10 */
/* 0x008fe2000ff7e0ff */
/*0440*/ DADD R20, R22, R20 ; /* 0x0000000016147229 */
/* 0x0202a40000000014 */
/*0450*/ LDG.E.64 R22, [R12.64+0x8] ; /* 0x0000080a0c167981 */
/* 0x002ee2000c1e1b00 */
/*0460*/ IADD3.X R19, R19, UR4, RZ, P3, !PT ; /* 0x0000000413137c10 */
/* 0x000fc60009ffe4ff */
/*0470*/ LDG.E.64 R16, [R16.64] ; /* 0x0000000a10107981 */
/* 0x000f28000c1e1b00 */
/*0480*/ LDG.E.64 R18, [R18.64+-0x8] ; /* 0xfffff80a12127981 */
/* 0x000f62000c1e1b00 */
/*0490*/ DADD R14, R20, R14 ; /* 0x00000000140e7229 */
/* 0x004764000000000e */
/*04a0*/ IADD3 R20, P3, R22, UR12, RZ ; /* 0x0000000c16147c10 */
/* 0x008fc8000ff7e0ff */
/*04b0*/ IADD3.X R21, R23, UR4, RZ, P3, !PT ; /* 0x0000000417157c10 */
/* 0x000fe40009ffe4ff */
/*04c0*/ IADD3 R12, P3, R16, UR12, RZ ; /* 0x0000000c100c7c10 */
/* 0x010fe2000ff7e0ff */
/*04d0*/ DADD R22, R14, R18 ; /* 0x000000000e167229 */
/* 0x0202a40000000012 */
/*04e0*/ LDG.E.64 R14, [R20.64+-0x10] ; /* 0xfffff00a140e7981 */
/* 0x002ea2000c1e1b00 */
/*04f0*/ IADD3.X R13, R17, UR4, RZ, P3, !PT ; /* 0x00000004110d7c10 */
/* 0x000fe40009ffe4ff */
/*0500*/ IADD3 R28, P3, R28, UR14, RZ ; /* 0x0000000e1c1c7c10 */
/* 0x000fe2000ff7e0ff */
/*0510*/ LDG.E.64 R18, [R20.64] ; /* 0x0000000a14127981 */
/* 0x000ee6000c1e1b00 */
/*0520*/ IADD3.X R29, R29, UR13, RZ, P3, !PT ; /* 0x0000000d1d1d7c10 */
/* 0x000fe20009ffe4ff */
/*0530*/ LDG.E.64 R12, [R12.64+-0x8] ; /* 0xfffff80a0c0c7981 */
/* 0x000f2a000c1e1b00 */
/*0540*/ LDG.E.64 R28, [R28.64] ; /* 0x0000000a1c1c7981 */
/* 0x000f62000c1e1b00 */
/*0550*/ DADD R14, R22, R14 ; /* 0x00000000160e7229 */
/* 0x004ecc000000000e */
/*0560*/ DADD R14, R14, R18 ; /* 0x000000000e0e7229 */
/* 0x008f0c0000000012 */
/*0570*/ DFMA R14, R4, R12, R14 ; /* 0x0000000c040e722b */
/* 0x011e22000000000e */
/*0580*/ IADD3 R16, P3, R28, UR12, RZ ; /* 0x0000000c1c107c10 */
/* 0x020fca000ff7e0ff */
/*0590*/ DMUL R22, R14, c[0x0][0x188] ; /* 0x000062000e167a28 */
/* 0x001e220000000000 */
/*05a0*/ IADD3.X R17, R29, UR4, RZ, P3, !PT ; /* 0x000000041d117c10 */
/* 0x000fcc0009ffe4ff */
/*05b0*/ STG.E.64 [R16.64+-0x8], R22 ; /* 0xfffff81610007986 */
/* 0x0011e8000c101b0a */
/*05c0*/ LDG.E.64 R14, [R6.64] ; /* 0x0000000a060e7981 */
/* 0x000ea8000c1e1b00 */
/*05d0*/ LDG.E.64 R18, [R6.64+0x10] ; /* 0x0000100a06127981 */
/* 0x000ee8000c1e1b00 */
/*05e0*/ LDG.E.64 R16, [R6.64+0x8] ; /* 0x0000080a06107981 */
/* 0x001f22000c1e1b00 */
/*05f0*/ IADD3 R14, P3, R14, UR14, RZ ; /* 0x0000000e0e0e7c10 */
/* 0x004fc4000ff7e0ff */
/*0600*/ IADD3 R28, P4, R18, UR14, RZ ; /* 0x0000000e121c7c10 */
/* 0x008fe4000ff9e0ff */
/*0610*/ IADD3.X R15, R15, UR13, RZ, P3, !PT ; /* 0x0000000d0f0f7c10 */
/* 0x000fe40009ffe4ff */
/*0620*/ IADD3.X R29, R19, UR13, RZ, P4, !PT ; /* 0x0000000d131d7c10 */
/* 0x000fc8000a7fe4ff */
/*0630*/ LDG.E.64 R14, [R14.64] ; /* 0x0000000a0e0e7981 */
/* 0x000ea8000c1e1b00 */
/*0640*/ LDG.E.64 R12, [R28.64] ; /* 0x0000000a1c0c7981 */
/* 0x000ee2000c1e1b00 */
/*0650*/ IADD3 R18, P3, R16, UR16, RZ ; /* 0x0000001010127c10 */
/* 0x010fc8000ff7e0ff */
/*0660*/ IADD3.X R19, R17, UR15, RZ, P3, !PT ; /* 0x0000000f11137c10 */
/* 0x000fca0009ffe4ff */
/*0670*/ LDG.E.64 R16, [R18.64] ; /* 0x0000000a12107981 */
/* 0x000f22000c1e1b00 */
/*0680*/ IADD3 R20, P3, R14, UR12, RZ ; /* 0x0000000c0e147c10 */
/* 0x004fe4000ff7e0ff */
/*0690*/ IADD3 R12, P4, R12, UR12, RZ ; /* 0x0000000c0c0c7c10 */
/* 0x008fe4000ff9e0ff */
/*06a0*/ IADD3.X R21, R15, UR4, RZ, P3, !PT ; /* 0x000000040f157c10 */
/* 0x000fe40009ffe4ff */
/*06b0*/ IADD3.X R13, R13, UR4, RZ, P4, !PT ; /* 0x000000040d0d7c10 */
/* 0x000fe2000a7fe4ff */
/*06c0*/ LDG.E.64 R14, [R8.64] ; /* 0x0000000a080e7981 */
/* 0x000ea8000c1e1b00 */
/*06d0*/ LDG.E.64 R20, [R20.64] ; /* 0x0000000a14147981 */
/* 0x000ee8000c1e1b00 */
/*06e0*/ LDG.E.64 R12, [R12.64] ; /* 0x0000000a0c0c7981 */
/* 0x000ee2000c1e1b00 */
/*06f0*/ IADD3 R28, P3, R16, UR12, RZ ; /* 0x0000000c101c7c10 */
/* 0x010fc8000ff7e0ff */
/*0700*/ IADD3.X R29, R17, UR4, RZ, P3, !PT ; /* 0x00000004111d7c10 */
/* 0x000fe40009ffe4ff */
/*0710*/ LDG.E.64 R16, [R10.64] ; /* 0x0000000a0a107981 */
/* 0x000f28000c1e1b00 */
/*0720*/ LDG.E.64 R22, [R28.64] ; /* 0x0000000a1c167981 */
/* 0x000f62000c1e1b00 */
/*0730*/ DADD R20, R12, R20 ; /* 0x000000000c147229 */
/* 0x0081460000000014 */
/*0740*/ LDG.E.64 R12, [R18.64+0x10] ; /* 0x0000100a120c7981 */
/* 0x0010e2000c1e1b00 */
/*0750*/ IADD3 R14, P3, R14, UR14, RZ ; /* 0x0000000e0e0e7c10 */
/* 0x004fc8000ff7e0ff */
/*0760*/ IADD3.X R15, R15, UR13, RZ, P3, !PT ; /* 0x0000000d0f0f7c10 */
/* 0x000fe20009ffe4ff */
/*0770*/ LDG.E.64 R18, [R18.64+0x8] ; /* 0x0000080a12127981 */
/* 0x001eaa000c1e1b00 */
/*0780*/ LDG.E.64 R14, [R14.64] ; /* 0x0000000a0e0e7981 */
/* 0x000ea2000c1e1b00 */
/*0790*/ IADD3 R16, P4, R16, UR14, RZ ; /* 0x0000000e10107c10 */
/* 0x010fe2000ff9e0ff */
/*07a0*/ DADD R22, R20, R22 ; /* 0x0000000014167229 */
/* 0x0200460000000016 */
/*07b0*/ IADD3.X R17, R17, UR13, RZ, P4, !PT ; /* 0x0000000d11117c10 */
/* 0x000fcc000a7fe4ff */
/*07c0*/ LDG.E.64 R16, [R16.64] ; /* 0x0000000a10107981 */
/* 0x000f22000c1e1b00 */
/*07d0*/ IADD3 R12, P3, R12, UR12, RZ ; /* 0x0000000c0c0c7c10 */
/* 0x008fc8000ff7e0ff */
/*07e0*/ IADD3.X R13, R13, UR4, RZ, P3, !PT ; /* 0x000000040d0d7c10 */
/* 0x000fe40009ffe4ff */
/*07f0*/ IADD3 R28, P3, R18, UR12, RZ ; /* 0x0000000c121c7c10 */
/* 0x004fc8000ff7e0ff */
/*0800*/ LDG.E.64 R12, [R12.64] ; /* 0x0000000a0c0c7981 */
/* 0x000e62000c1e1b00 */
/*0810*/ IADD3.X R29, R19, UR4, RZ, P3, !PT ; /* 0x00000004131d7c10 */
/* 0x000fe40009ffe4ff */
/*0820*/ IADD3 R14, P3, R14, UR12, RZ ; /* 0x0000000c0e0e7c10 */
/* 0x000fc6000ff7e0ff */
/*0830*/ LDG.E.64 R18, [R28.64+-0x8] ; /* 0xfffff80a1c127981 */
/* 0x000ea2000c1e1b00 */
/*0840*/ IADD3.X R15, R15, UR4, RZ, P3, !PT ; /* 0x000000040f0f7c10 */
/* 0x000fc60009ffe4ff */
/*0850*/ LDG.E.64 R20, [R28.64+0x8] ; /* 0x0000080a1c147981 */
/* 0x001ee8000c1e1b00 */
/*0860*/ LDG.E.64 R14, [R14.64] ; /* 0x0000000a0e0e7981 */
/* 0x000f62000c1e1b00 */
/*0870*/ IADD3 R26, R26, -0x2, RZ ; /* 0xfffffffe1a1a7810 */
/* 0x000fe40007ffe0ff */
/*0880*/ IADD3 R25, R25, 0x2, RZ ; /* 0x0000000219197810 */
/* 0x000fe20007ffe0ff */
/*0890*/ DADD R22, R22, R12 ; /* 0x0000000016167229 */
/* 0x002e8c000000000c */
/*08a0*/ DADD R18, R22, R18 ; /* 0x0000000016127229 */
/* 0x004ee20000000012 */
/*08b0*/ IADD3 R12, P3, R16, UR12, RZ ; /* 0x0000000c100c7c10 */
/* 0x010fca000ff7e0ff */
/*08c0*/ DADD R18, R18, R20 ; /* 0x0000000012127229 */
/* 0x008f620000000014 */
/*08d0*/ IADD3.X R13, R17, UR4, RZ, P3, !PT ; /* 0x00000004110d7c10 */
/* 0x000fe40009ffe4ff */
/*08e0*/ ISETP.NE.AND P3, PT, R26, 0x2, PT ; /* 0x000000021a00780c */
/* 0x000fc60003f65270 */
/*08f0*/ DFMA R18, R4, R14, R18 ; /* 0x0000000e0412722b */
/* 0x020e220000000012 */
/*0900*/ UIADD3 UR12, UP0, UR12, 0x10, URZ ; /* 0x000000100c0c7890 */
/* 0x000fca000ff1e03f */
/*0910*/ DMUL R18, R18, c[0x0][0x188] ; /* 0x0000620012127a28 */
/* 0x001e220000000000 */
/*0920*/ UIADD3.X UR4, URZ, UR4, URZ, UP0, !UPT ; /* 0x000000043f047290 */
/* 0x000fcc00087fe43f */
/*0930*/ STG.E.64 [R12.64], R18 ; /* 0x000000120c007986 */
/* 0x0011e2000c101b0a */
/*0940*/ @P3 BRA 0x290 ; /* 0xfffff94000003947 */
/* 0x000fea000383ffff */
/*0950*/ @!P1 BRA 0xc90 ; /* 0x0000033000009947 */
/* 0x000fea0003800000 */
/*0960*/ LDG.E.64 R12, [R6.64+0x8] ; /* 0x0000080a060c7981 */
/* 0x001ea8000c1e1b00 */
/*0970*/ LDG.E.64 R16, [R6.64] ; /* 0x0000000a06107981 */
/* 0x000ee8000c1e1b00 */
/*0980*/ LDG.E.64 R14, [R6.64+0x10] ; /* 0x0000100a060e7981 */
/* 0x000f22000c1e1b00 */
/*0990*/ USHF.L.U32 UR13, UR5, 0x3, URZ ; /* 0x00000003050d7899 */
/* 0x000fc4000800063f */
/*09a0*/ USHF.L.U64.HI UR7, UR5, 0x3, UR7 ; /* 0x0000000305077899 */
/* 0x000fe20008010207 */
/*09b0*/ LDG.E.64 R20, [R8.64] ; /* 0x0000000a08147981 */
/* 0x000f62000c1e1b00 */
/*09c0*/ R2UR UR4, R12 ; /* 0x000000000c0473c2 */
/* 0x004e3000000e0000 */
/*09d0*/ R2UR UR5, R13 ; /* 0x000000000d0573c2 */
/* 0x000e6200000e0000 */
/*09e0*/ IADD3 R26, P1, R16, UR13, RZ ; /* 0x0000000d101a7c10 */
/* 0x008fc4000ff3e0ff */
/*09f0*/ IADD3 R28, P3, R14, UR13, RZ ; /* 0x0000000d0e1c7c10 */
/* 0x010fe4000ff7e0ff */
/*0a00*/ IADD3.X R27, R17, UR7, RZ, P1, !PT ; /* 0x00000007111b7c10 */
/* 0x000fe40008ffe4ff */
/*0a10*/ IADD3.X R29, R15, UR7, RZ, P3, !PT ; /* 0x000000070f1d7c10 */
/* 0x000fc60009ffe4ff */
/*0a20*/ LDG.E.64 R14, [R26.64] ; /* 0x0000000a1a0e7981 */
/* 0x0004e8000c1e1b00 */
/*0a30*/ LDG.E.64 R16, [R28.64] ; /* 0x0000000a1c107981 */
/* 0x000b22000c1e1b00 */
/*0a40*/ ULEA UR12, UP0, UR8, UR4, 0x3 ; /* 0x00000004080c7291 */
/* 0x001fc8000f80183f */
/*0a50*/ ULEA.HI.X UR4, UR8, UR5, UR9, 0x3, UP0 ; /* 0x0000000508047291 */
/* 0x002fe400080f1c09 */
/*0a60*/ IMAD.U32 R22, RZ, RZ, UR12 ; /* 0x0000000cff167e24 */
/* 0x000fc8000f8e00ff */
/*0a70*/ IMAD.U32 R23, RZ, RZ, UR4 ; /* 0x00000004ff177e24 */
/* 0x000fca000f8e00ff */
/*0a80*/ LDG.E.64 R18, [R22.64] ; /* 0x0000000a16127981 */
/* 0x000128000c1e1b00 */
/*0a90*/ LDG.E.64 R12, [R22.64+0x10] ; /* 0x0000100a160c7981 */
/* 0x000122000c1e1b00 */
/*0aa0*/ IADD3 R28, P1, R20, UR13, RZ ; /* 0x0000000d141c7c10 */
/* 0x020fc6000ff3e0ff */
/*0ab0*/ LDG.E.64 R26, [R22.64+0x8] ; /* 0x0000080a161a7981 */
/* 0x0040a2000c1e1b00 */
/*0ac0*/ IADD3.X R29, R21, UR7, RZ, P1, !PT ; /* 0x00000007151d7c10 */
/* 0x000fc60008ffe4ff */
/*0ad0*/ LDG.E.64 R20, [R10.64] ; /* 0x0000000a0a147981 */
/* 0x000f68000c1e1b00 */
/*0ae0*/ LDG.E.64 R22, [R28.64] ; /* 0x0000000a1c167981 */
/* 0x001ea2000c1e1b00 */
/*0af0*/ IMAD.WIDE R14, R25, 0x8, R14 ; /* 0x00000008190e7825 */
/* 0x008fc800078e020e */
/*0b00*/ IMAD.WIDE R16, R25.reuse, 0x8, R16 ; /* 0x0000000819107825 */
/* 0x050fe400078e0210 */
/*0b10*/ LDG.E.64 R14, [R14.64] ; /* 0x0000000a0e0e7981 */
/* 0x000ee8000c1e1b00 */
/*0b20*/ LDG.E.64 R16, [R16.64] ; /* 0x0000000a10107981 */
/* 0x000ee2000c1e1b00 */
/*0b30*/ IMAD.WIDE R18, R25, 0x8, R18 ; /* 0x0000000819127825 */
/* 0x000fcc00078e0212 */
/*0b40*/ LDG.E.64 R18, [R18.64] ; /* 0x0000000a12127981 */
/* 0x000f22000c1e1b00 */
/*0b50*/ IMAD.WIDE R12, R25, 0x8, R12 ; /* 0x00000008190c7825 */
/* 0x000fcc00078e020c */
/*0b60*/ LDG.E.64 R12, [R12.64] ; /* 0x0000000a0c0c7981 */
/* 0x000f22000c1e1b00 */
/*0b70*/ IADD3 R20, P1, R20, UR13, RZ ; /* 0x0000000d14147c10 */
/* 0x020fe2000ff3e0ff */
/*0b80*/ IMAD.WIDE R22, R25, 0x8, R22 ; /* 0x0000000819167825 */
/* 0x004fc600078e0216 */
/*0b90*/ IADD3.X R21, R21, UR7, RZ, P1, !PT ; /* 0x0000000715157c10 */
/* 0x000fc60008ffe4ff */
/*0ba0*/ LDG.E.64 R22, [R22.64] ; /* 0x0000000a16167981 */
/* 0x000ea8000c1e1b00 */
/*0bb0*/ LDG.E.64 R20, [R20.64] ; /* 0x0000000a14147981 */
/* 0x000f62000c1e1b00 */
/*0bc0*/ DADD R14, R16, R14 ; /* 0x00000000100e7229 */
/* 0x008124000000000e */
/*0bd0*/ IADD3 R17, R25, -0x1, RZ ; /* 0xffffffff19117810 */
/* 0x001fca0007ffe0ff */
/*0be0*/ IMAD.WIDE R26, R17, 0x8, R26 ; /* 0x00000008111a7825 */
/* 0x000fca00078e021a */
/*0bf0*/ LDG.E.64 R16, [R26.64] ; /* 0x0000000a1a107981 */
/* 0x000ee2000c1e1b00 */
/*0c00*/ DADD R18, R14, R18 ; /* 0x000000000e127229 */
/* 0x0100460000000012 */
/*0c10*/ LDG.E.64 R14, [R26.64+0x10] ; /* 0x0000100a1a0e7981 */
/* 0x001f26000c1e1b00 */
/*0c20*/ DADD R18, R18, R12 ; /* 0x0000000012127229 */
/* 0x002ae4000000000c */
/*0c30*/ IMAD.WIDE R12, R25, 0x8, R20 ; /* 0x00000008190c7825 */
/* 0x020fc800078e0214 */
/*0c40*/ DADD R16, R18, R16 ; /* 0x0000000012107229 */
/* 0x008f0c0000000010 */
/*0c50*/ DADD R14, R16, R14 ; /* 0x00000000100e7229 */
/* 0x010e8c000000000e */
/*0c60*/ DFMA R14, R4, R22, R14 ; /* 0x00000016040e722b */
/* 0x004e0c000000000e */
/*0c70*/ DMUL R14, R14, c[0x0][0x188] ; /* 0x000062000e0e7a28 */
/* 0x001e0e0000000000 */
/*0c80*/ STG.E.64 [R12.64], R14 ; /* 0x0000000e0c007986 */
/* 0x0011e8000c101b0a */
/*0c90*/ @!P2 BRA 0x160 ; /* 0xfffff4c00000a947 */
/* 0x000fea000383ffff */
/*0ca0*/ @!P0 BRA 0xd0 ; /* 0xfffff42000008947 */
/* 0x000fea000383ffff */
/*0cb0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0cc0*/ BRA 0xcc0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0cd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ce0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11jacobi_gpu1PPPdS1_S1_idd
.globl _Z11jacobi_gpu1PPPdS1_S1_idd
.p2align 8
.type _Z11jacobi_gpu1PPPdS1_S1_idd,@function
_Z11jacobi_gpu1PPPdS1_S1_idd:
s_load_b32 s25, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s25, 3
s_cbranch_scc1 .LBB0_7
s_load_b128 s[4:7], s[0:1], 0x20
s_add_i32 s24, s25, -1
s_add_i32 s25, s25, -2
s_mov_b32 s26, 1
s_mov_b32 s13, 0
s_mov_b32 s14, 1
s_waitcnt lgkmcnt(0)
v_mul_f64 v[4:5], s[4:5], s[4:5]
s_clause 0x1
s_load_b128 s[8:11], s[0:1], 0x0
s_load_b64 s[4:5], s[0:1], 0x10
.LBB0_2:
s_mov_b32 s15, s13
s_mov_b32 s12, s26
s_lshl_b64 s[0:1], s[14:15], 3
s_waitcnt lgkmcnt(0)
s_add_u32 s2, s10, s0
s_addc_u32 s3, s11, s1
s_add_u32 s16, s2, -8
s_addc_u32 s17, s3, -1
s_add_u32 s18, s4, s0
s_addc_u32 s19, s5, s1
s_add_u32 s20, s8, s0
s_addc_u32 s21, s9, s1
s_clause 0x1
s_load_b64 s[16:17], s[16:17], 0x0
s_load_b128 s[0:3], s[2:3], 0x0
s_load_b64 s[18:19], s[18:19], 0x0
s_load_b64 s[20:21], s[20:21], 0x0
.LBB0_3:
s_lshl_b64 s[22:23], s[12:13], 3
s_waitcnt lgkmcnt(0)
s_add_u32 s28, s16, s22
s_addc_u32 s29, s17, s23
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v0, s28 :: v_dual_mov_b32 v1, s29
s_add_u32 s30, s2, s22
s_addc_u32 s31, s3, s23
s_add_u32 s28, s0, s22
v_dual_mov_b32 v2, s30 :: v_dual_mov_b32 v3, s31
s_addc_u32 s29, s1, s23
flat_load_b64 v[6:7], v[0:1]
v_add_co_u32 v0, s15, -8, s28
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v1, null, -1, s29, s15
flat_load_b64 v[8:9], v[2:3]
s_add_u32 s30, s18, s22
v_dual_mov_b32 v2, s28 :: v_dual_mov_b32 v3, s29
s_addc_u32 s31, s19, s23
flat_load_b64 v[10:11], v[0:1]
s_add_u32 s22, s20, s22
s_addc_u32 s23, s21, s23
v_dual_mov_b32 v12, s30 :: v_dual_mov_b32 v13, s31
flat_load_b128 v[0:3], v[2:3]
v_dual_mov_b32 v14, s22 :: v_dual_mov_b32 v15, s23
flat_load_b64 v[12:13], v[12:13]
flat_load_b64 v[14:15], v[14:15]
s_mov_b64 s[22:23], 0
s_mov_b32 s15, s25
s_waitcnt vmcnt(5) lgkmcnt(5)
v_add_co_u32 v6, vcc_lo, v6, 8
v_add_co_ci_u32_e32 v7, vcc_lo, 0, v7, vcc_lo
s_waitcnt vmcnt(4) lgkmcnt(4)
v_add_co_u32 v8, vcc_lo, v8, 8
v_add_co_ci_u32_e32 v9, vcc_lo, 0, v9, vcc_lo
s_waitcnt vmcnt(3) lgkmcnt(3)
v_add_co_u32 v10, vcc_lo, v10, 8
v_add_co_ci_u32_e32 v11, vcc_lo, 0, v11, vcc_lo
s_waitcnt vmcnt(2) lgkmcnt(2)
v_add_co_u32 v2, vcc_lo, v2, 8
v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
s_waitcnt vmcnt(1) lgkmcnt(1)
v_add_co_u32 v12, vcc_lo, v12, 8
v_add_co_ci_u32_e32 v13, vcc_lo, 0, v13, vcc_lo
s_waitcnt vmcnt(0) lgkmcnt(0)
v_add_co_u32 v14, vcc_lo, v14, 8
v_add_co_ci_u32_e32 v15, vcc_lo, 0, v15, vcc_lo
.LBB0_4:
v_add_co_u32 v16, vcc_lo, v6, s22
v_add_co_ci_u32_e32 v17, vcc_lo, s23, v7, vcc_lo
v_add_co_u32 v18, vcc_lo, v8, s22
v_add_co_ci_u32_e32 v19, vcc_lo, s23, v9, vcc_lo
v_add_co_u32 v20, vcc_lo, v10, s22
flat_load_b64 v[16:17], v[16:17]
flat_load_b64 v[18:19], v[18:19]
v_add_co_ci_u32_e32 v21, vcc_lo, s23, v11, vcc_lo
v_add_co_u32 v22, vcc_lo, v2, s22
v_add_co_ci_u32_e32 v23, vcc_lo, s23, v3, vcc_lo
flat_load_b64 v[20:21], v[20:21]
v_add_co_u32 v24, vcc_lo, v0, s22
flat_load_b64 v[22:23], v[22:23]
v_add_co_ci_u32_e32 v25, vcc_lo, s23, v1, vcc_lo
s_clause 0x1
flat_load_b64 v[26:27], v[24:25]
flat_load_b64 v[24:25], v[24:25] offset:16
v_add_co_u32 v28, vcc_lo, v12, s22
v_add_co_ci_u32_e32 v29, vcc_lo, s23, v13, vcc_lo
s_add_i32 s15, s15, -1
flat_load_b64 v[28:29], v[28:29]
s_waitcnt vmcnt(5) lgkmcnt(5)
v_add_f64 v[16:17], v[16:17], v[18:19]
v_add_co_u32 v18, vcc_lo, v14, s22
v_add_co_ci_u32_e32 v19, vcc_lo, s23, v15, vcc_lo
s_add_u32 s22, s22, 8
s_addc_u32 s23, s23, 0
s_cmp_lg_u32 s15, 0
s_waitcnt vmcnt(4) lgkmcnt(4)
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_f64 v[16:17], v[16:17], v[20:21]
s_waitcnt vmcnt(3) lgkmcnt(3)
v_add_f64 v[16:17], v[16:17], v[22:23]
s_waitcnt vmcnt(2) lgkmcnt(2)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_f64 v[16:17], v[16:17], v[26:27]
s_waitcnt vmcnt(1) lgkmcnt(1)
v_add_f64 v[16:17], v[16:17], v[24:25]
s_waitcnt vmcnt(0) lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[16:17], v[4:5], v[28:29], v[16:17]
v_mul_f64 v[16:17], v[16:17], s[6:7]
flat_store_b64 v[18:19], v[16:17]
s_cbranch_scc1 .LBB0_4
s_add_i32 s12, s12, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lg_u32 s12, s24
s_cbranch_scc1 .LBB0_3
s_add_i32 s14, s14, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lg_u32 s14, s24
s_cbranch_scc1 .LBB0_2
.LBB0_7:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11jacobi_gpu1PPPdS1_S1_idd
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 48
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 30
.amdhsa_next_free_sgpr 32
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z11jacobi_gpu1PPPdS1_S1_idd, .Lfunc_end0-_Z11jacobi_gpu1PPPdS1_S1_idd
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 8
.value_kind: by_value
- .offset: 40
.size: 8
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 48
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11jacobi_gpu1PPPdS1_S1_idd
.private_segment_fixed_size: 0
.sgpr_count: 34
.sgpr_spill_count: 0
.symbol: _Z11jacobi_gpu1PPPdS1_S1_idd.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 30
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00188127_00000000-6_jacobi.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z13print_matrix2PPPdi
.type _Z13print_matrix2PPPdi, @function
_Z13print_matrix2PPPdi:
.LFB2057:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size _Z13print_matrix2PPPdi, .-_Z13print_matrix2PPPdi
.globl _Z42__device_stub__Z11jacobi_gpu1PPPdS1_S1_iddPPPdS1_S1_idd
.type _Z42__device_stub__Z11jacobi_gpu1PPPdS1_S1_iddPPPdS1_S1_idd, @function
_Z42__device_stub__Z11jacobi_gpu1PPPdS1_S1_iddPPPdS1_S1_idd:
.LFB2082:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movsd %xmm0, 8(%rsp)
movsd %xmm1, (%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
movq %rsp, %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L9
.L5:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L10
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z11jacobi_gpu1PPPdS1_S1_idd(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L5
.L10:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z42__device_stub__Z11jacobi_gpu1PPPdS1_S1_iddPPPdS1_S1_idd, .-_Z42__device_stub__Z11jacobi_gpu1PPPdS1_S1_iddPPPdS1_S1_idd
.globl _Z11jacobi_gpu1PPPdS1_S1_idd
.type _Z11jacobi_gpu1PPPdS1_S1_idd, @function
_Z11jacobi_gpu1PPPdS1_S1_idd:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z42__device_stub__Z11jacobi_gpu1PPPdS1_S1_iddPPPdS1_S1_idd
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z11jacobi_gpu1PPPdS1_S1_idd, .-_Z11jacobi_gpu1PPPdS1_S1_idd
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z11jacobi_gpu1PPPdS1_S1_idd"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z11jacobi_gpu1PPPdS1_S1_idd(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "jacobi.hip"
.globl _Z26__device_stub__jacobi_gpu1PPPdS1_S1_idd # -- Begin function _Z26__device_stub__jacobi_gpu1PPPdS1_S1_idd
.p2align 4, 0x90
.type _Z26__device_stub__jacobi_gpu1PPPdS1_S1_idd,@function
_Z26__device_stub__jacobi_gpu1PPPdS1_S1_idd: # @_Z26__device_stub__jacobi_gpu1PPPdS1_S1_idd
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 4(%rsp)
movsd %xmm0, 64(%rsp)
movsd %xmm1, 56(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
leaq 64(%rsp), %rax
movq %rax, 128(%rsp)
leaq 56(%rsp), %rax
movq %rax, 136(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z11jacobi_gpu1PPPdS1_S1_idd, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z26__device_stub__jacobi_gpu1PPPdS1_S1_idd, .Lfunc_end0-_Z26__device_stub__jacobi_gpu1PPPdS1_S1_idd
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11jacobi_gpu1PPPdS1_S1_idd, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z11jacobi_gpu1PPPdS1_S1_idd,@object # @_Z11jacobi_gpu1PPPdS1_S1_idd
.section .rodata,"a",@progbits
.globl _Z11jacobi_gpu1PPPdS1_S1_idd
.p2align 3, 0x0
_Z11jacobi_gpu1PPPdS1_S1_idd:
.quad _Z26__device_stub__jacobi_gpu1PPPdS1_S1_idd
.size _Z11jacobi_gpu1PPPdS1_S1_idd, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z11jacobi_gpu1PPPdS1_S1_idd"
.size .L__unnamed_1, 29
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__jacobi_gpu1PPPdS1_S1_idd
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11jacobi_gpu1PPPdS1_S1_idd
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | /***********************************************************************************
This work is COMS 4824 Architecture Final Project, advised by Professor Martha Kim.
"A Walk on the Hyperthreaded Side:
an Implementation and Analysis of Translating Virtual Addresses on a GPU"
Copyright (c) 2017 Columbia University.
All rights reserved.
Created by Serena Liu and Raphael Norwitz.
AWS EC2 instance configuration:
--Instance type: g2.2xlarge
--AMI Id: NVIDIA CUDA 7.5 Toolkit on Amazon Linux-0ce7aca3-5b96-4ff4-8396-05245687380a-ami-52420645.3 (ami-52f7b345)
CUDA examples used:
https://raw.githubusercontent.com/berkeley-scf/gpu-workshop-2016/master/kernelExample.cu
Software Usage:
--compile: nvcc page_walk.cu -o page_walk.out
--output: ./page_walk.out -n <total addresses> <intermediate table parameters>
(eg, ./page_walk.out -n 400 2 3 2 4)
************************************************************************************/
#include <stdio.h>
#include <stdlib.h>
#include <unistd.h>
#include <string.h>
#include <errno.h>
#include <assert.h>
#include <sys/time.h>
#include <time.h>
#include <cuda.h>
#include <cuda_runtime.h>
#include <stdint.h>
#define BLOCK_D1 512
#define BLOCK_D2 1
#define BLOCK_D3 1
#define MAX_LEVELS 20
#define cudaCheckErrors(msg) \
do { \
cudaError_t __err = cudaGetLastError(); \
if (__err != cudaSuccess) { \
fprintf(stderr, "Fatal error: %s (%s at %s:%d)\n", \
msg, cudaGetErrorString(__err), \
__FILE__, __LINE__); \
fprintf(stderr, "*** FAILED - ABORTING\n"); \
exit(1); \
} \
} while (0)
static int max_table;
struct trans_thread {
void **curr_table;
unsigned long cuda_result;
int offset[MAX_LEVELS];
int curr;
int max;
};
//function called by CUDA kernel
__host__ __device__ int translate_cpu(struct trans_thread *trans) {
unsigned long *gpu_ptr = (unsigned long *) trans->curr_table;
while(trans->curr < trans->max-1) {
gpu_ptr = (unsigned long *) gpu_ptr[trans->offset[trans->curr]];
trans->curr++;
}
return (int) *((int *) gpu_ptr + trans->offset[trans->curr]);
// ((void *) trans->curr_table + trans->offset[trans->max-1]);
}
//CPU counterpart
int translate_cpu2(struct trans_thread *trans) {
while(trans->curr < trans->max-1) {
trans->curr_table = (void **) trans->curr_table[trans->offset[trans->curr]];
trans->curr++;
}
return (int) *((int *) trans->curr_table + trans->offset[trans->curr]);
// ((void *) trans->curr_table + trans->offset[trans->max-1]);
}
// CUDA kernel: gpu_run_time<<<gridSize, blockSize>>>(d_new_threads, total_addresses);
__global__ void gpu_run_time(struct trans_thread *trans, int addresses) {
// id of the block
int myblock = blockIdx.x + blockIdx.y * gridDim.x;
// size of each block (within grid of blocks)
int blocksize = blockDim.x * blockDim.y * blockDim.z;
// id of thread in a given block
int subthread = threadIdx.z*(blockDim.x * blockDim.y) + threadIdx.y*blockDim.x + threadIdx.x;
// assign overall id/index of the thread
int idx = myblock * blocksize + subthread;
if(idx < addresses) {
translate_cpu(&trans[idx]);
}
}
// CPU analog for speed comparison
float cpu_run_time(struct trans_thread *trans, int addresses) {
for(int i = 0; i < addresses; i++) {
translate_cpu2(&trans[i]);
}
return 0;
}
/* --------------------------- host code ------------------------------*/
double read_timer() {
struct timeval end;
gettimeofday( &end, NULL );
return end.tv_sec+1.e-6*end.tv_usec;
}
//sequential phase 1: construct the table
int construct_table(void *table, int *levels, int num_levels) {
int i, j, level_size = 1;
void **table_ptr = (void **) table;
unsigned long **level_ptr;
// set intermediate addresses of table
for(i = 0; i < num_levels-1; i++)
{
level_size *= levels[i];
level_ptr = (unsigned long **) table + level_size + (((unsigned long *)table_ptr - (unsigned long *) table)/(sizeof(unsigned long *)));
fprintf(stderr, "level_size: %d, level_ptr: %d, table_ptr: %d\n", level_size, (level_ptr- (unsigned long **) table) / sizeof(void *), (unsigned long **) table_ptr - (unsigned long **) table);
for(j = 0; j < level_size; j++) {
table_ptr[j] = level_ptr + ((j)*levels[i+1]);
}
table_ptr += level_size;
}
assert((intptr_t )table_ptr - (intptr_t )table < max_table);
// set last level of page table to garbage;
for(i = 0; i < level_size * levels[num_levels-1]; i++) {
*table_ptr = (unsigned long *) i;
table_ptr++;
}
assert((intptr_t )table_ptr - (intptr_t )table == max_table);
// return number of entries at the lowest level of the page table
return levels[num_levels-1] * level_size;
}
//sequential phase 2: generate struct trans_thread for each address
struct trans_thread *gen_addresses(int num_addr, int levels, int *level_sizes, void **pgd)
{
int i,j;
struct trans_thread *new_threads = (struct trans_thread *)malloc(sizeof(struct trans_thread) * num_addr);
if (!new_threads){
fprintf(stderr, "malloc failed: %d\n", strerror(errno));
exit(1);
}
for(i = 0; i < num_addr; i++)
{
new_threads[i].curr_table = pgd;
new_threads[i].max = levels;
new_threads[i].curr = 0;
for(j = 0; j < levels; j++) {
new_threads[i].offset[j] =
rand() % level_sizes[j];
}
}
return new_threads;
}
////////////////////////////////////////////////////////////////////////////////
//
// Main Program
//
////////////////////////////////////////////////////////////////////////////////
int main(int argc, char** argv) {
void **d_pg_table; //device page table
int i, j, table_size = 0, level_size = 1,
total_addresses, table_lowest_addresses,
levels = argc-3;
int level_sizes[levels];
//struct trans_thread *sample;
struct trans_thread *h_new_threads; //host
struct trans_thread *d_new_threads; //device
cudaError_t cudaStat;
//start of the program
printf("===============================================================================\n");
srand(time(NULL));
// get number of pointers in contiguous page table
for(i = 1, j =0; i < argc; i++) {
if ( !strcmp(argv[i], "-n")) {
total_addresses = atoi(argv[++i]);
continue;
}
level_size *= atoi(argv[i]);
level_sizes[j++] = atoi(argv[i]);
table_size += level_size;
}
//tuning the parameters of the device
// fixed block size (512 x1x1 threads)
const dim3 blockSize(BLOCK_D1, BLOCK_D2, BLOCK_D3);
// determine number of blocks we need for a given problem size
int tmp = ceil(pow(total_addresses/BLOCK_D1, 0.5));
printf("Grid dimension is %i x %i\n", tmp, tmp);
//grid size
dim3 gridSize(tmp, tmp, 1);
//total number of threads
int nthreads = BLOCK_D1*BLOCK_D2*BLOCK_D3*tmp*tmp;
//threads number legitimacy check
if (nthreads < total_addresses){
printf("\n============ NOT ENOUGH THREADS TO COVER total addresses=%d ===============\n\n",total_addresses);
} else {
printf("Launching %d threads (total_addresses=%d)\n", nthreads, total_addresses);
}
// allocate host memory
max_table = table_size * sizeof(void *); //total size of page table
void **pg_table = (void **) malloc(sizeof(void *) * table_size);
if (!pg_table) {
fprintf(stderr, "host memory allocation failed: %d\n", strerror(errno));
exit(1);
}
else {
printf ("host memory allocation succeeded.\n");
}
// allocate device memory
cudaStat = cudaMalloc(&d_pg_table, sizeof(void *) * table_size);
if(cudaStat != cudaSuccess) {
printf ("device memory allocation failed.\n");
return EXIT_FAILURE;
}
else {
printf ("device memory allocation succeeded.\n");
}
/* --------------------------- sequential code on CPU; phase 1 --------------------------------------*/
//number of entries at the lowest level of the page table
//number of translatable addresses
printf ("now construct the page table on the host.\n");
table_lowest_addresses = construct_table(pg_table, level_sizes, levels);
fprintf(stderr, "number of translatable addresses: %d\n", table_lowest_addresses);
fprintf(stderr, "total size of page table: %d\n", max_table);
cudaDeviceSynchronize();
double tInit = read_timer();
/* --------------------------- copy the page table from CPU to the GPU ------------------------------*/
cudaStat = cudaMemcpy(d_pg_table, pg_table, sizeof(void *) * table_size, cudaMemcpyHostToDevice);
printf("Memory Copy for page table from Host to Device");
if (cudaStat != cudaSuccess){
printf("failed.\n");
return EXIT_FAILURE;
} else {
printf("successful.\n");
}
cudaDeviceSynchronize();
double tTransferToGPU_pgtable = read_timer();
/* --------------------------- sequential code on CPU; phase 2 ---------------------------------------*/
h_new_threads = gen_addresses(total_addresses, levels, level_sizes, pg_table);
cudaDeviceSynchronize();
double tInit2 = read_timer();
/* ------------------------- copy the trans_threads from CPU to the GPU ------------------------------*/
cudaStat = cudaMalloc( (void**) &d_new_threads, sizeof(struct trans_thread) * total_addresses) ;
if (cudaStat != cudaSuccess){
printf("device memory allocation for d_new_threads failed.\n");
return EXIT_FAILURE;
} else {
printf("device memory allocation for d_new_threads succeeded.\n");
}
cudaStat = cudaMemcpy( d_new_threads, h_new_threads, sizeof(struct trans_thread) * total_addresses, cudaMemcpyHostToDevice);
printf("Memory Copy h_new_threads from Host to Device");
if (cudaStat != cudaSuccess){
printf("failed.\n");
return EXIT_FAILURE;
} else {
printf(" successful.\n");
}
cudaCheckErrors("cudaMemcpy h_new_threads fail");
cudaDeviceSynchronize();
double tTransferToGPU_threads = read_timer();
/* ----------------------------------- parallel code on GPU: kernel -----------------------------------*/
gpu_run_time<<<gridSize, blockSize>>>(d_new_threads, total_addresses);
cudaError_t cudaerr = cudaDeviceSynchronize();
if (cudaerr){
printf("kernel launch failed with error \"%s\".\n",
cudaGetErrorString(cudaerr));
} else {
printf("kernel launch success!\n");
}
cudaDeviceSynchronize();
double gpu_time = read_timer();
printf("GPU done!\n");
/* --------------------------------- sequential code on CPU; phase 3 ----------------------------------*/
printf("now do calculation on CPU for comparison!\n");
cpu_run_time(h_new_threads, total_addresses);
double cpu_time = read_timer();
fprintf(stderr, "The CPU took %lu microseconds to compute %d addresses. ""For a table of depth %d.\n", cpu_time - gpu_time , total_addresses, levels);
/* --------------------------------- sequential code on CPU; phase 4 ----------------------------------*/
printf("Timing results for n = %d\n", total_addresses);
//printf("page table Transfer to GPU time: %f\n", tTransferToGPU_pgtable - tInit);
//printf("threads Transfer to GPU time: %f\n", tTransferToGPU_threads - tInit2);
printf("Calculation time (GPU): %f\n", gpu_time - tTransferToGPU_threads);
//printf("Transfer from GPU time: %f\n", tTransferFromGPU - gpu_time);
printf("Calculation time (CPU): %f\n", cpu_time - gpu_time);
printf("Freeing memory...\n");
printf("====================================================\n");
free(pg_table);
free(h_new_threads);
cudaFree(d_pg_table);
cudaFree(d_new_threads);
return 0;
} | code for sm_80
Function : _Z12gpu_run_timeP12trans_threadi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e280000002600 */
/*0030*/ S2R R5, SR_TID.Z ; /* 0x0000000000057919 */
/* 0x000e680000002300 */
/*0040*/ S2R R7, SR_TID.Y ; /* 0x0000000000077919 */
/* 0x000ea80000002200 */
/*0050*/ S2R R9, SR_TID.X ; /* 0x0000000000097919 */
/* 0x000ee20000002100 */
/*0060*/ IMAD R0, R3, c[0x0][0xc], R0 ; /* 0x0000030003007a24 */
/* 0x001fc800078e0200 */
/*0070*/ IMAD R0, R0, c[0x0][0x8], R5 ; /* 0x0000020000007a24 */
/* 0x002fc800078e0205 */
/*0080*/ IMAD R0, R0, c[0x0][0x4], R7 ; /* 0x0000010000007a24 */
/* 0x004fc800078e0207 */
/*0090*/ IMAD R0, R0, c[0x0][0x0], R9 ; /* 0x0000000000007a24 */
/* 0x008fca00078e0209 */
/*00a0*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x168], PT ; /* 0x00005a0000007a0c */
/* 0x000fda0003f06270 */
/*00b0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00c0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x68 ; /* 0x00000068ff037424 */
/* 0x000fe200078e00ff */
/*00d0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*00e0*/ IMAD.WIDE R2, R0, R3, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fca00078e0203 */
/*00f0*/ LDG.E.64 R4, [R2.64+0x60] ; /* 0x0000600402047981 */
/* 0x000ea4000c1e1b00 */
/*0100*/ IADD3 R7, R5, -0x1, RZ ; /* 0xffffffff05077810 */
/* 0x004fc80007ffe0ff */
/*0110*/ ISETP.GE.AND P0, PT, R4, R7, PT ; /* 0x000000070400720c */
/* 0x000fda0003f06270 */
/*0120*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0130*/ IMAD.IADD R0, R7, 0x1, -R4 ; /* 0x0000000107007824 */
/* 0x000fe200078e0a04 */
/*0140*/ BSSY B0, 0x200 ; /* 0x000000b000007945 */
/* 0x000fe20003800000 */
/*0150*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fc60003f0f070 */
/*0160*/ ISETP.GT.AND P1, PT, R0, 0x3, PT ; /* 0x000000030000780c */
/* 0x000fda0003f24270 */
/*0170*/ @!P1 BRA 0x1f0 ; /* 0x0000007000009947 */
/* 0x000fea0003800000 */
/*0180*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0190*/ IADD3 R0, R5, -0x4, RZ ; /* 0xfffffffc05007810 */
/* 0x000fe40007ffe0ff */
/*01a0*/ IADD3 R5, R4, 0x4, RZ ; /* 0x0000000404057810 */
/* 0x000fc80007ffe0ff */
/*01b0*/ ISETP.GE.AND P1, PT, R5, R0, PT ; /* 0x000000000500720c */
/* 0x000fe20003f26270 */
/*01c0*/ STG.E [R2.64+0x60], R5 ; /* 0x0000600502007986 */
/* 0x0001e2000c101904 */
/*01d0*/ IMAD.MOV.U32 R4, RZ, RZ, R5 ; /* 0x000000ffff047224 */
/* 0x000fd600078e0005 */
/*01e0*/ @!P1 BRA 0x1a0 ; /* 0xffffffb000009947 */
/* 0x001fea000383ffff */
/*01f0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0200*/ IMAD.IADD R0, R7, 0x1, -R4 ; /* 0x0000000107007824 */
/* 0x000fca00078e0a04 */
/*0210*/ ISETP.GT.AND P1, PT, R0, 0x1, PT ; /* 0x000000010000780c */
/* 0x000fda0003f24270 */
/*0220*/ @P1 PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000181c */
/* 0x000fe40003f0e170 */
/*0230*/ @P1 IADD3 R4, R4, 0x2, RZ ; /* 0x0000000204041810 */
/* 0x000fca0007ffe0ff */
/*0240*/ @P1 STG.E [R2.64+0x60], R4 ; /* 0x0000600402001986 */
/* 0x0001ec000c101904 */
/*0250*/ ISETP.LT.OR P0, PT, R4, R7, P0 ; /* 0x000000070400720c */
/* 0x000fda0000701670 */
/*0260*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0270*/ IADD3 R5, R4, 0x1, RZ ; /* 0x0000000104057810 */
/* 0x001fca0007ffe0ff */
/*0280*/ STG.E [R2.64+0x60], R5 ; /* 0x0000600502007986 */
/* 0x000fe2000c101904 */
/*0290*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*02a0*/ BRA 0x2a0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0300*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0310*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0320*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /***********************************************************************************
This work is COMS 4824 Architecture Final Project, advised by Professor Martha Kim.
"A Walk on the Hyperthreaded Side:
an Implementation and Analysis of Translating Virtual Addresses on a GPU"
Copyright (c) 2017 Columbia University.
All rights reserved.
Created by Serena Liu and Raphael Norwitz.
AWS EC2 instance configuration:
--Instance type: g2.2xlarge
--AMI Id: NVIDIA CUDA 7.5 Toolkit on Amazon Linux-0ce7aca3-5b96-4ff4-8396-05245687380a-ami-52420645.3 (ami-52f7b345)
CUDA examples used:
https://raw.githubusercontent.com/berkeley-scf/gpu-workshop-2016/master/kernelExample.cu
Software Usage:
--compile: nvcc page_walk.cu -o page_walk.out
--output: ./page_walk.out -n <total addresses> <intermediate table parameters>
(eg, ./page_walk.out -n 400 2 3 2 4)
************************************************************************************/
#include <stdio.h>
#include <stdlib.h>
#include <unistd.h>
#include <string.h>
#include <errno.h>
#include <assert.h>
#include <sys/time.h>
#include <time.h>
#include <cuda.h>
#include <cuda_runtime.h>
#include <stdint.h>
#define BLOCK_D1 512
#define BLOCK_D2 1
#define BLOCK_D3 1
#define MAX_LEVELS 20
#define cudaCheckErrors(msg) \
do { \
cudaError_t __err = cudaGetLastError(); \
if (__err != cudaSuccess) { \
fprintf(stderr, "Fatal error: %s (%s at %s:%d)\n", \
msg, cudaGetErrorString(__err), \
__FILE__, __LINE__); \
fprintf(stderr, "*** FAILED - ABORTING\n"); \
exit(1); \
} \
} while (0)
static int max_table;
struct trans_thread {
void **curr_table;
unsigned long cuda_result;
int offset[MAX_LEVELS];
int curr;
int max;
};
//function called by CUDA kernel
__host__ __device__ int translate_cpu(struct trans_thread *trans) {
unsigned long *gpu_ptr = (unsigned long *) trans->curr_table;
while(trans->curr < trans->max-1) {
gpu_ptr = (unsigned long *) gpu_ptr[trans->offset[trans->curr]];
trans->curr++;
}
return (int) *((int *) gpu_ptr + trans->offset[trans->curr]);
// ((void *) trans->curr_table + trans->offset[trans->max-1]);
}
//CPU counterpart
int translate_cpu2(struct trans_thread *trans) {
while(trans->curr < trans->max-1) {
trans->curr_table = (void **) trans->curr_table[trans->offset[trans->curr]];
trans->curr++;
}
return (int) *((int *) trans->curr_table + trans->offset[trans->curr]);
// ((void *) trans->curr_table + trans->offset[trans->max-1]);
}
// CUDA kernel: gpu_run_time<<<gridSize, blockSize>>>(d_new_threads, total_addresses);
__global__ void gpu_run_time(struct trans_thread *trans, int addresses) {
// id of the block
int myblock = blockIdx.x + blockIdx.y * gridDim.x;
// size of each block (within grid of blocks)
int blocksize = blockDim.x * blockDim.y * blockDim.z;
// id of thread in a given block
int subthread = threadIdx.z*(blockDim.x * blockDim.y) + threadIdx.y*blockDim.x + threadIdx.x;
// assign overall id/index of the thread
int idx = myblock * blocksize + subthread;
if(idx < addresses) {
translate_cpu(&trans[idx]);
}
}
// CPU analog for speed comparison
float cpu_run_time(struct trans_thread *trans, int addresses) {
for(int i = 0; i < addresses; i++) {
translate_cpu2(&trans[i]);
}
return 0;
}
/* --------------------------- host code ------------------------------*/
double read_timer() {
struct timeval end;
gettimeofday( &end, NULL );
return end.tv_sec+1.e-6*end.tv_usec;
}
//sequential phase 1: construct the table
int construct_table(void *table, int *levels, int num_levels) {
int i, j, level_size = 1;
void **table_ptr = (void **) table;
unsigned long **level_ptr;
// set intermediate addresses of table
for(i = 0; i < num_levels-1; i++)
{
level_size *= levels[i];
level_ptr = (unsigned long **) table + level_size + (((unsigned long *)table_ptr - (unsigned long *) table)/(sizeof(unsigned long *)));
fprintf(stderr, "level_size: %d, level_ptr: %d, table_ptr: %d\n", level_size, (level_ptr- (unsigned long **) table) / sizeof(void *), (unsigned long **) table_ptr - (unsigned long **) table);
for(j = 0; j < level_size; j++) {
table_ptr[j] = level_ptr + ((j)*levels[i+1]);
}
table_ptr += level_size;
}
assert((intptr_t )table_ptr - (intptr_t )table < max_table);
// set last level of page table to garbage;
for(i = 0; i < level_size * levels[num_levels-1]; i++) {
*table_ptr = (unsigned long *) i;
table_ptr++;
}
assert((intptr_t )table_ptr - (intptr_t )table == max_table);
// return number of entries at the lowest level of the page table
return levels[num_levels-1] * level_size;
}
//sequential phase 2: generate struct trans_thread for each address
struct trans_thread *gen_addresses(int num_addr, int levels, int *level_sizes, void **pgd)
{
int i,j;
struct trans_thread *new_threads = (struct trans_thread *)malloc(sizeof(struct trans_thread) * num_addr);
if (!new_threads){
fprintf(stderr, "malloc failed: %d\n", strerror(errno));
exit(1);
}
for(i = 0; i < num_addr; i++)
{
new_threads[i].curr_table = pgd;
new_threads[i].max = levels;
new_threads[i].curr = 0;
for(j = 0; j < levels; j++) {
new_threads[i].offset[j] =
rand() % level_sizes[j];
}
}
return new_threads;
}
////////////////////////////////////////////////////////////////////////////////
//
// Main Program
//
////////////////////////////////////////////////////////////////////////////////
int main(int argc, char** argv) {
void **d_pg_table; //device page table
int i, j, table_size = 0, level_size = 1,
total_addresses, table_lowest_addresses,
levels = argc-3;
int level_sizes[levels];
//struct trans_thread *sample;
struct trans_thread *h_new_threads; //host
struct trans_thread *d_new_threads; //device
cudaError_t cudaStat;
//start of the program
printf("===============================================================================\n");
srand(time(NULL));
// get number of pointers in contiguous page table
for(i = 1, j =0; i < argc; i++) {
if ( !strcmp(argv[i], "-n")) {
total_addresses = atoi(argv[++i]);
continue;
}
level_size *= atoi(argv[i]);
level_sizes[j++] = atoi(argv[i]);
table_size += level_size;
}
//tuning the parameters of the device
// fixed block size (512 x1x1 threads)
const dim3 blockSize(BLOCK_D1, BLOCK_D2, BLOCK_D3);
// determine number of blocks we need for a given problem size
int tmp = ceil(pow(total_addresses/BLOCK_D1, 0.5));
printf("Grid dimension is %i x %i\n", tmp, tmp);
//grid size
dim3 gridSize(tmp, tmp, 1);
//total number of threads
int nthreads = BLOCK_D1*BLOCK_D2*BLOCK_D3*tmp*tmp;
//threads number legitimacy check
if (nthreads < total_addresses){
printf("\n============ NOT ENOUGH THREADS TO COVER total addresses=%d ===============\n\n",total_addresses);
} else {
printf("Launching %d threads (total_addresses=%d)\n", nthreads, total_addresses);
}
// allocate host memory
max_table = table_size * sizeof(void *); //total size of page table
void **pg_table = (void **) malloc(sizeof(void *) * table_size);
if (!pg_table) {
fprintf(stderr, "host memory allocation failed: %d\n", strerror(errno));
exit(1);
}
else {
printf ("host memory allocation succeeded.\n");
}
// allocate device memory
cudaStat = cudaMalloc(&d_pg_table, sizeof(void *) * table_size);
if(cudaStat != cudaSuccess) {
printf ("device memory allocation failed.\n");
return EXIT_FAILURE;
}
else {
printf ("device memory allocation succeeded.\n");
}
/* --------------------------- sequential code on CPU; phase 1 --------------------------------------*/
//number of entries at the lowest level of the page table
//number of translatable addresses
printf ("now construct the page table on the host.\n");
table_lowest_addresses = construct_table(pg_table, level_sizes, levels);
fprintf(stderr, "number of translatable addresses: %d\n", table_lowest_addresses);
fprintf(stderr, "total size of page table: %d\n", max_table);
cudaDeviceSynchronize();
double tInit = read_timer();
/* --------------------------- copy the page table from CPU to the GPU ------------------------------*/
cudaStat = cudaMemcpy(d_pg_table, pg_table, sizeof(void *) * table_size, cudaMemcpyHostToDevice);
printf("Memory Copy for page table from Host to Device");
if (cudaStat != cudaSuccess){
printf("failed.\n");
return EXIT_FAILURE;
} else {
printf("successful.\n");
}
cudaDeviceSynchronize();
double tTransferToGPU_pgtable = read_timer();
/* --------------------------- sequential code on CPU; phase 2 ---------------------------------------*/
h_new_threads = gen_addresses(total_addresses, levels, level_sizes, pg_table);
cudaDeviceSynchronize();
double tInit2 = read_timer();
/* ------------------------- copy the trans_threads from CPU to the GPU ------------------------------*/
cudaStat = cudaMalloc( (void**) &d_new_threads, sizeof(struct trans_thread) * total_addresses) ;
if (cudaStat != cudaSuccess){
printf("device memory allocation for d_new_threads failed.\n");
return EXIT_FAILURE;
} else {
printf("device memory allocation for d_new_threads succeeded.\n");
}
cudaStat = cudaMemcpy( d_new_threads, h_new_threads, sizeof(struct trans_thread) * total_addresses, cudaMemcpyHostToDevice);
printf("Memory Copy h_new_threads from Host to Device");
if (cudaStat != cudaSuccess){
printf("failed.\n");
return EXIT_FAILURE;
} else {
printf(" successful.\n");
}
cudaCheckErrors("cudaMemcpy h_new_threads fail");
cudaDeviceSynchronize();
double tTransferToGPU_threads = read_timer();
/* ----------------------------------- parallel code on GPU: kernel -----------------------------------*/
gpu_run_time<<<gridSize, blockSize>>>(d_new_threads, total_addresses);
cudaError_t cudaerr = cudaDeviceSynchronize();
if (cudaerr){
printf("kernel launch failed with error \"%s\".\n",
cudaGetErrorString(cudaerr));
} else {
printf("kernel launch success!\n");
}
cudaDeviceSynchronize();
double gpu_time = read_timer();
printf("GPU done!\n");
/* --------------------------------- sequential code on CPU; phase 3 ----------------------------------*/
printf("now do calculation on CPU for comparison!\n");
cpu_run_time(h_new_threads, total_addresses);
double cpu_time = read_timer();
fprintf(stderr, "The CPU took %lu microseconds to compute %d addresses. ""For a table of depth %d.\n", cpu_time - gpu_time , total_addresses, levels);
/* --------------------------------- sequential code on CPU; phase 4 ----------------------------------*/
printf("Timing results for n = %d\n", total_addresses);
//printf("page table Transfer to GPU time: %f\n", tTransferToGPU_pgtable - tInit);
//printf("threads Transfer to GPU time: %f\n", tTransferToGPU_threads - tInit2);
printf("Calculation time (GPU): %f\n", gpu_time - tTransferToGPU_threads);
//printf("Transfer from GPU time: %f\n", tTransferFromGPU - gpu_time);
printf("Calculation time (CPU): %f\n", cpu_time - gpu_time);
printf("Freeing memory...\n");
printf("====================================================\n");
free(pg_table);
free(h_new_threads);
cudaFree(d_pg_table);
cudaFree(d_new_threads);
return 0;
} | .file "tmpxft_0012add1_00000000-6_page_walk.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2079:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2079:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z13translate_cpuP12trans_thread
.type _Z13translate_cpuP12trans_thread, @function
_Z13translate_cpuP12trans_thread:
.LFB2070:
.cfi_startproc
endbr64
movq (%rdi), %rdx
movl 96(%rdi), %ecx
movl 100(%rdi), %r8d
leal -1(%r8), %eax
cmpl %eax, %ecx
jge .L4
leal 1(%rcx), %eax
cltq
leal -2(%r8), %esi
subl %ecx, %esi
movslq %ecx, %rcx
leaq 2(%rsi,%rcx), %rsi
.L5:
movslq 12(%rdi,%rax,4), %rcx
movq (%rdx,%rcx,8), %rdx
movl %eax, 96(%rdi)
addq $1, %rax
cmpq %rsi, %rax
jne .L5
leal -1(%r8), %ecx
.L4:
movslq %ecx, %rcx
movslq 16(%rdi,%rcx,4), %rax
movl (%rdx,%rax,4), %eax
ret
.cfi_endproc
.LFE2070:
.size _Z13translate_cpuP12trans_thread, .-_Z13translate_cpuP12trans_thread
.globl _Z14translate_cpu2P12trans_thread
.type _Z14translate_cpu2P12trans_thread, @function
_Z14translate_cpu2P12trans_thread:
.LFB2071:
.cfi_startproc
endbr64
movl 96(%rdi), %edx
movl 100(%rdi), %r8d
leal -1(%r8), %eax
cmpl %eax, %edx
jge .L8
leal 1(%rdx), %eax
cltq
leal -2(%r8), %ecx
subl %edx, %ecx
movslq %edx, %rdx
leaq 2(%rcx,%rdx), %rsi
.L9:
movslq 12(%rdi,%rax,4), %rcx
movq (%rdi), %rdx
movq (%rdx,%rcx,8), %rdx
movq %rdx, (%rdi)
movl %eax, 96(%rdi)
addq $1, %rax
cmpq %rsi, %rax
jne .L9
leal -1(%r8), %edx
.L8:
movslq %edx, %rdx
movslq 16(%rdi,%rdx,4), %rdx
movq (%rdi), %rax
movl (%rax,%rdx,4), %eax
ret
.cfi_endproc
.LFE2071:
.size _Z14translate_cpu2P12trans_thread, .-_Z14translate_cpu2P12trans_thread
.globl _Z12cpu_run_timeP12trans_threadi
.type _Z12cpu_run_timeP12trans_threadi, @function
_Z12cpu_run_timeP12trans_threadi:
.LFB2072:
.cfi_startproc
endbr64
testl %esi, %esi
jle .L16
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
movq %rdi, %rbx
movslq %esi, %rsi
leaq (%rsi,%rsi,2), %rax
leaq (%rsi,%rax,4), %rax
leaq (%rdi,%rax,8), %rbp
.L13:
movq %rbx, %rdi
call _Z14translate_cpu2P12trans_thread
addq $104, %rbx
cmpq %rbp, %rbx
jne .L13
pxor %xmm0, %xmm0
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L16:
.cfi_restore 3
.cfi_restore 6
pxor %xmm0, %xmm0
ret
.cfi_endproc
.LFE2072:
.size _Z12cpu_run_timeP12trans_threadi, .-_Z12cpu_run_timeP12trans_threadi
.globl _Z10read_timerv
.type _Z10read_timerv, @function
_Z10read_timerv:
.LFB2073:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movq %fs:40, %rax
movq %rax, 24(%rsp)
xorl %eax, %eax
movq %rsp, %rdi
movl $0, %esi
call gettimeofday@PLT
pxor %xmm0, %xmm0
cvtsi2sdq 8(%rsp), %xmm0
mulsd .LC1(%rip), %xmm0
pxor %xmm1, %xmm1
cvtsi2sdq (%rsp), %xmm1
addsd %xmm1, %xmm0
movq 24(%rsp), %rax
subq %fs:40, %rax
jne .L22
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L22:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2073:
.size _Z10read_timerv, .-_Z10read_timerv
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC2:
.string "level_size: %d, level_ptr: %d, table_ptr: %d\n"
.text
.globl _Z15construct_tablePvPii
.type _Z15construct_tablePvPii, @function
_Z15construct_tablePvPii:
.LFB2074:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $40, %rsp
.cfi_def_cfa_offset 96
movq %rdi, %r13
movq %rsi, %r14
movl %edx, %ebx
cmpl $1, %edx
jle .L30
movq %rsi, (%rsp)
leal -2(%rdx), %eax
leaq 4(%rsi,%rax,4), %rax
movq %rax, 8(%rsp)
movq %rdi, %rbp
movl $1, %r15d
movq %rsi, 16(%rsp)
movl %edx, 28(%rsp)
.L27:
movq (%rsp), %rax
movq %rax, %r14
imull (%rax), %r15d
movslq %r15d, %r12
movq %rbp, %r9
subq %r13, %r9
sarq $3, %r9
movq %r9, %rbx
shrq $3, %rbx
addq %r12, %rbx
salq $3, %rbx
movq %rbx, %r8
sarq $3, %r8
shrq $3, %r8
movl %r15d, %ecx
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
testl %r15d, %r15d
jle .L25
movl $0, %eax
.L26:
movl %eax, %edx
imull 4(%r14), %edx
movslq %edx, %rdx
leaq (%rbx,%rdx,8), %rdx
addq %r13, %rdx
movq %rdx, 0(%rbp,%rax,8)
addq $1, %rax
cmpq %rax, %r12
jne .L26
.L25:
leaq 0(%rbp,%r12,8), %rbp
addq $4, (%rsp)
movq (%rsp), %rax
movq 8(%rsp), %rsi
cmpq %rsi, %rax
jne .L27
movq 16(%rsp), %r14
movl 28(%rsp), %ebx
.L24:
movslq %ebx, %rbx
leaq -4(%r14,%rbx,4), %rcx
movl %r15d, %edx
imull (%rcx), %edx
testl %edx, %edx
jle .L23
movl $0, %eax
.L29:
movq %rax, 0(%rbp,%rax,8)
movl %r15d, %edx
imull (%rcx), %edx
addq $1, %rax
cmpl %eax, %edx
jg .L29
.L23:
movl %edx, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L30:
.cfi_restore_state
movq %rdi, %rbp
movl $1, %r15d
jmp .L24
.cfi_endproc
.LFE2074:
.size _Z15construct_tablePvPii, .-_Z15construct_tablePvPii
.section .rodata.str1.1,"aMS",@progbits,1
.LC3:
.string "malloc failed: %d\n"
.text
.globl _Z13gen_addressesiiPiPPv
.type _Z13gen_addressesiiPiPPv, @function
_Z13gen_addressesiiPiPPv:
.LFB2075:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $40, %rsp
.cfi_def_cfa_offset 96
movl %edi, %ebp
movl %esi, %r14d
movq %rdx, 16(%rsp)
movq %rcx, 8(%rsp)
movslq %edi, %rax
leaq (%rax,%rax,2), %rdx
leaq (%rax,%rdx,4), %rbx
salq $3, %rbx
movq %rbx, %rdi
call malloc@PLT
movq %rax, 24(%rsp)
testq %rax, %rax
je .L36
testl %ebp, %ebp
jle .L35
movq 24(%rsp), %rax
leaq 16(%rax), %r13
leaq 16(%rax,%rbx), %r15
movslq %r14d, %rax
movq 16(%rsp), %rsi
leaq (%rsi,%rax,4), %r12
jmp .L41
.L36:
call __errno_location@PLT
movl (%rax), %edi
call strerror@PLT
movq %rax, %rcx
leaq .LC3(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L39:
addq $104, %r13
cmpq %r15, %r13
je .L35
.L41:
movq 8(%rsp), %rax
movq %rax, -16(%r13)
movl %r14d, 84(%r13)
movl $0, 80(%r13)
testl %r14d, %r14d
jle .L39
movq %r13, %rbp
movq 16(%rsp), %rbx
.L40:
call rand@PLT
cltd
idivl (%rbx)
movl %edx, 0(%rbp)
addq $4, %rbx
addq $4, %rbp
cmpq %r12, %rbx
jne .L40
jmp .L39
.L35:
movq 24(%rsp), %rax
addq $40, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2075:
.size _Z13gen_addressesiiPiPPv, .-_Z13gen_addressesiiPiPPv
.globl _Z46__device_stub__Z12gpu_run_timeP12trans_threadiP12trans_threadi
.type _Z46__device_stub__Z12gpu_run_timeP12trans_threadiP12trans_threadi, @function
_Z46__device_stub__Z12gpu_run_timeP12trans_threadiP12trans_threadi:
.LFB2101:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L49
.L45:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L50
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L49:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z12gpu_run_timeP12trans_threadi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L45
.L50:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2101:
.size _Z46__device_stub__Z12gpu_run_timeP12trans_threadiP12trans_threadi, .-_Z46__device_stub__Z12gpu_run_timeP12trans_threadiP12trans_threadi
.globl _Z12gpu_run_timeP12trans_threadi
.type _Z12gpu_run_timeP12trans_threadi, @function
_Z12gpu_run_timeP12trans_threadi:
.LFB2102:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z46__device_stub__Z12gpu_run_timeP12trans_threadiP12trans_threadi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2102:
.size _Z12gpu_run_timeP12trans_threadi, .-_Z12gpu_run_timeP12trans_threadi
.section .rodata.str1.8
.align 8
.LC4:
.string "===============================================================================\n"
.section .rodata.str1.1
.LC5:
.string "-n"
.LC10:
.string "Grid dimension is %i x %i\n"
.section .rodata.str1.8
.align 8
.LC11:
.string "\n============ NOT ENOUGH THREADS TO COVER total addresses=%d ===============\n\n"
.align 8
.LC12:
.string "Launching %d threads (total_addresses=%d)\n"
.align 8
.LC13:
.string "host memory allocation failed: %d\n"
.align 8
.LC14:
.string "host memory allocation succeeded.\n"
.align 8
.LC15:
.string "device memory allocation failed.\n"
.align 8
.LC16:
.string "device memory allocation succeeded.\n"
.align 8
.LC17:
.string "now construct the page table on the host.\n"
.align 8
.LC18:
.string "number of translatable addresses: %d\n"
.section .rodata.str1.1
.LC19:
.string "total size of page table: %d\n"
.section .rodata.str1.8
.align 8
.LC20:
.string "Memory Copy for page table from Host to Device"
.section .rodata.str1.1
.LC21:
.string "failed.\n"
.LC22:
.string "successful.\n"
.section .rodata.str1.8
.align 8
.LC23:
.string "device memory allocation for d_new_threads failed.\n"
.align 8
.LC24:
.string "device memory allocation for d_new_threads succeeded.\n"
.align 8
.LC25:
.string "Memory Copy h_new_threads from Host to Device"
.section .rodata.str1.1
.LC26:
.string " successful.\n"
.section .rodata.str1.8
.align 8
.LC27:
.string "/home/ubuntu/Datasets/stackv2/train-structured/raphael-s-norwitz/arch_final_project/master/page_walk.cu"
.section .rodata.str1.1
.LC28:
.string "cudaMemcpy h_new_threads fail"
.section .rodata.str1.8
.align 8
.LC29:
.string "Fatal error: %s (%s at %s:%d)\n"
.section .rodata.str1.1
.LC30:
.string "*** FAILED - ABORTING\n"
.section .rodata.str1.8
.align 8
.LC31:
.string "kernel launch failed with error \"%s\".\n"
.section .rodata.str1.1
.LC32:
.string "kernel launch success!\n"
.LC33:
.string "GPU done!\n"
.section .rodata.str1.8
.align 8
.LC34:
.string "now do calculation on CPU for comparison!\n"
.align 8
.LC35:
.string "The CPU took %lu microseconds to compute %d addresses. For a table of depth %d.\n"
.section .rodata.str1.1
.LC36:
.string "Timing results for n = %d\n"
.LC37:
.string "Calculation time (GPU): %f\n"
.LC38:
.string "Calculation time (CPU): %f\n"
.LC39:
.string "Freeing memory...\n"
.section .rodata.str1.8
.align 8
.LC40:
.string "====================================================\n"
.text
.globl main
.type main, @function
main:
.LFB2076:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
movq %rsp, %rbp
.cfi_def_cfa_register 6
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $104, %rsp
.cfi_offset 15, -24
.cfi_offset 14, -32
.cfi_offset 13, -40
.cfi_offset 12, -48
.cfi_offset 3, -56
movl %edi, -116(%rbp)
movq %rsi, -104(%rbp)
movq %fs:40, %rax
movq %rax, -56(%rbp)
xorl %eax, %eax
leal -3(%rdi), %eax
movl %eax, -136(%rbp)
cltq
leaq 15(,%rax,4), %rax
movq %rax, %rcx
andq $-16, %rcx
andq $-4096, %rax
movq %rsp, %rdx
subq %rax, %rdx
.L54:
cmpq %rdx, %rsp
je .L55
subq $4096, %rsp
orq $0, 4088(%rsp)
jmp .L54
.L55:
movq %rcx, %rax
andl $4095, %eax
subq %rax, %rsp
testq %rax, %rax
je .L56
orq $0, -8(%rsp,%rax)
.L56:
movq %rsp, -128(%rbp)
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %edi
call time@PLT
movl %eax, %edi
call srand@PLT
cmpl $1, -116(%rbp)
jle .L75
movl $1, %r15d
movl $0, -120(%rbp)
movl $0, -112(%rbp)
movl $1, %ebx
jmp .L60
.L58:
movl $10, %edx
movl $0, %esi
movq %r14, %rdi
call __isoc23_strtol@PLT
imull %eax, %r15d
movq 0(%r13), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %rdx
movl -112(%rbp), %ecx
movslq %ecx, %rax
movq -128(%rbp), %rsi
movl %edx, (%rsi,%rax,4)
addl %r15d, -120(%rbp)
leal 1(%rcx), %eax
movl %eax, -112(%rbp)
.L59:
addl $1, %ebx
cmpl %ebx, -116(%rbp)
jle .L57
.L60:
movslq %ebx, %r12
salq $3, %r12
movq -104(%rbp), %rax
leaq (%rax,%r12), %r13
movq 0(%r13), %r14
leaq .LC5(%rip), %rsi
movq %r14, %rdi
call strcmp@PLT
testl %eax, %eax
jne .L58
addl $1, %ebx
movq -104(%rbp), %rax
movq 8(%rax,%r12), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movl %eax, -132(%rbp)
jmp .L59
.L75:
movl $0, -120(%rbp)
.L57:
movl $512, -80(%rbp)
movl $1, -76(%rbp)
movl $1, -72(%rbp)
movl -132(%rbp), %edx
leal 511(%rdx), %eax
testl %edx, %edx
cmovns %edx, %eax
sarl $9, %eax
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
movsd .LC6(%rip), %xmm1
call pow@PLT
movapd %xmm0, %xmm3
movsd .LC41(%rip), %xmm2
movapd %xmm0, %xmm1
andpd %xmm2, %xmm1
movsd .LC7(%rip), %xmm4
ucomisd %xmm1, %xmm4
jbe .L61
cvttsd2siq %xmm0, %rax
pxor %xmm1, %xmm1
cvtsi2sdq %rax, %xmm1
cmpnlesd %xmm1, %xmm3
movsd .LC9(%rip), %xmm4
andpd %xmm4, %xmm3
addsd %xmm1, %xmm3
andnpd %xmm0, %xmm2
orpd %xmm2, %xmm3
.L61:
cvttsd2sil %xmm3, %ebx
movl %ebx, %ecx
movl %ebx, %edx
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %ebx, -68(%rbp)
movl %ebx, -64(%rbp)
movl $1, -60(%rbp)
imull %ebx, %ebx
sall $9, %ebx
movl -132(%rbp), %edx
cmpl %edx, %ebx
jge .L62
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L63:
movl -120(%rbp), %eax
movslq %eax, %r12
sall $3, %eax
movl %eax, _ZL9max_table(%rip)
salq $3, %r12
movq %r12, %rdi
call malloc@PLT
movq %rax, %rbx
testq %rax, %rax
je .L78
leaq .LC14(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq -96(%rbp), %rdi
movq %r12, %rsi
call cudaMalloc@PLT
testl %eax, %eax
jne .L79
leaq .LC16(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC17(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl -136(%rbp), %edx
movq -128(%rbp), %rsi
movq %rbx, %rdi
call _Z15construct_tablePvPii
movl %eax, %ecx
leaq .LC18(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl _ZL9max_table(%rip), %ecx
leaq .LC19(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
call cudaDeviceSynchronize@PLT
call _Z10read_timerv
movl $1, %ecx
movq %r12, %rdx
movq %rbx, %rsi
movq -96(%rbp), %rdi
call cudaMemcpy@PLT
movl %eax, %r12d
leaq .LC20(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
testl %r12d, %r12d
jne .L80
leaq .LC22(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
call cudaDeviceSynchronize@PLT
call _Z10read_timerv
movq %rbx, %rcx
movq -128(%rbp), %rdx
movl -136(%rbp), %esi
movl -132(%rbp), %r15d
movl %r15d, %edi
call _Z13gen_addressesiiPiPPv
movq %rax, %r13
call cudaDeviceSynchronize@PLT
call _Z10read_timerv
movslq %r15d, %r12
imulq $104, %r12, %r12
leaq -88(%rbp), %rdi
movq %r12, %rsi
call cudaMalloc@PLT
testl %eax, %eax
jne .L81
leaq .LC24(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %ecx
movq %r12, %rdx
movq %r13, %rsi
movq -88(%rbp), %rdi
call cudaMemcpy@PLT
movl %eax, %r12d
leaq .LC25(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
testl %r12d, %r12d
jne .L82
leaq .LC26(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
call cudaGetLastError@PLT
testl %eax, %eax
jne .L83
call cudaDeviceSynchronize@PLT
call _Z10read_timerv
movsd %xmm0, -112(%rbp)
movl -72(%rbp), %ecx
movl $0, %r9d
movl $0, %r8d
movq -80(%rbp), %rdx
movq -68(%rbp), %rdi
movl -60(%rbp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L84
.L71:
call cudaDeviceSynchronize@PLT
testl %eax, %eax
je .L72
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC31(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L73:
call cudaDeviceSynchronize@PLT
call _Z10read_timerv
movsd %xmm0, -104(%rbp)
leaq .LC33(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC34(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl -132(%rbp), %r15d
movl %r15d, %esi
movq %r13, %rdi
call _Z12cpu_run_timeP12trans_threadi
call _Z10read_timerv
movapd %xmm0, %xmm6
subsd -104(%rbp), %xmm6
movq %xmm6, %r12
movl -136(%rbp), %r8d
movl %r15d, %ecx
movapd %xmm6, %xmm0
leaq .LC35(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $1, %eax
call __fprintf_chk@PLT
movl %r15d, %edx
leaq .LC36(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movsd -104(%rbp), %xmm0
subsd -112(%rbp), %xmm0
leaq .LC37(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq %r12, %xmm0
leaq .LC38(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
leaq .LC39(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC40(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rbx, %rdi
call free@PLT
movq %r13, %rdi
call free@PLT
movq -96(%rbp), %rdi
call cudaFree@PLT
movq -88(%rbp), %rdi
call cudaFree@PLT
movl $0, %eax
jmp .L53
.L62:
movl -132(%rbp), %ecx
movl %ebx, %edx
leaq .LC12(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L63
.L78:
call __errno_location@PLT
movl (%rax), %edi
call strerror@PLT
movq %rax, %rcx
leaq .LC13(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L79:
leaq .LC15(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %eax
.L53:
movq -56(%rbp), %rdx
subq %fs:40, %rdx
jne .L85
leaq -40(%rbp), %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
.cfi_remember_state
.cfi_def_cfa 7, 8
ret
.L80:
.cfi_restore_state
leaq .LC21(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %eax
jmp .L53
.L81:
leaq .LC23(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %eax
jmp .L53
.L82:
leaq .LC21(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %eax
jmp .L53
.L83:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
subq $8, %rsp
pushq $305
leaq .LC27(%rip), %r9
leaq .LC28(%rip), %rcx
leaq .LC29(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
addq $16, %rsp
leaq .LC30(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L84:
movl -132(%rbp), %esi
movq -88(%rbp), %rdi
call _Z46__device_stub__Z12gpu_run_timeP12trans_threadiP12trans_threadi
jmp .L71
.L72:
leaq .LC32(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L73
.L85:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2076:
.size main, .-main
.section .rodata.str1.8
.align 8
.LC42:
.string "_Z12gpu_run_timeP12trans_threadi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2104:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC42(%rip), %rdx
movq %rdx, %rcx
leaq _Z12gpu_run_timeP12trans_threadi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2104:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL9max_table
.comm _ZL9max_table,4,4
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC1:
.long -1598689907
.long 1051772663
.align 8
.LC6:
.long 0
.long 1071644672
.align 8
.LC7:
.long 0
.long 1127219200
.align 8
.LC9:
.long 0
.long 1072693248
.align 8
.LC41:
.long -1
.long 2147483647
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /***********************************************************************************
This work is COMS 4824 Architecture Final Project, advised by Professor Martha Kim.
"A Walk on the Hyperthreaded Side:
an Implementation and Analysis of Translating Virtual Addresses on a GPU"
Copyright (c) 2017 Columbia University.
All rights reserved.
Created by Serena Liu and Raphael Norwitz.
AWS EC2 instance configuration:
--Instance type: g2.2xlarge
--AMI Id: NVIDIA CUDA 7.5 Toolkit on Amazon Linux-0ce7aca3-5b96-4ff4-8396-05245687380a-ami-52420645.3 (ami-52f7b345)
CUDA examples used:
https://raw.githubusercontent.com/berkeley-scf/gpu-workshop-2016/master/kernelExample.cu
Software Usage:
--compile: nvcc page_walk.cu -o page_walk.out
--output: ./page_walk.out -n <total addresses> <intermediate table parameters>
(eg, ./page_walk.out -n 400 2 3 2 4)
************************************************************************************/
#include <stdio.h>
#include <stdlib.h>
#include <unistd.h>
#include <string.h>
#include <errno.h>
#include <assert.h>
#include <sys/time.h>
#include <time.h>
#include <cuda.h>
#include <cuda_runtime.h>
#include <stdint.h>
#define BLOCK_D1 512
#define BLOCK_D2 1
#define BLOCK_D3 1
#define MAX_LEVELS 20
#define cudaCheckErrors(msg) \
do { \
cudaError_t __err = cudaGetLastError(); \
if (__err != cudaSuccess) { \
fprintf(stderr, "Fatal error: %s (%s at %s:%d)\n", \
msg, cudaGetErrorString(__err), \
__FILE__, __LINE__); \
fprintf(stderr, "*** FAILED - ABORTING\n"); \
exit(1); \
} \
} while (0)
static int max_table;
struct trans_thread {
void **curr_table;
unsigned long cuda_result;
int offset[MAX_LEVELS];
int curr;
int max;
};
//function called by CUDA kernel
__host__ __device__ int translate_cpu(struct trans_thread *trans) {
unsigned long *gpu_ptr = (unsigned long *) trans->curr_table;
while(trans->curr < trans->max-1) {
gpu_ptr = (unsigned long *) gpu_ptr[trans->offset[trans->curr]];
trans->curr++;
}
return (int) *((int *) gpu_ptr + trans->offset[trans->curr]);
// ((void *) trans->curr_table + trans->offset[trans->max-1]);
}
//CPU counterpart
int translate_cpu2(struct trans_thread *trans) {
while(trans->curr < trans->max-1) {
trans->curr_table = (void **) trans->curr_table[trans->offset[trans->curr]];
trans->curr++;
}
return (int) *((int *) trans->curr_table + trans->offset[trans->curr]);
// ((void *) trans->curr_table + trans->offset[trans->max-1]);
}
// CUDA kernel: gpu_run_time<<<gridSize, blockSize>>>(d_new_threads, total_addresses);
__global__ void gpu_run_time(struct trans_thread *trans, int addresses) {
// id of the block
int myblock = blockIdx.x + blockIdx.y * gridDim.x;
// size of each block (within grid of blocks)
int blocksize = blockDim.x * blockDim.y * blockDim.z;
// id of thread in a given block
int subthread = threadIdx.z*(blockDim.x * blockDim.y) + threadIdx.y*blockDim.x + threadIdx.x;
// assign overall id/index of the thread
int idx = myblock * blocksize + subthread;
if(idx < addresses) {
translate_cpu(&trans[idx]);
}
}
// CPU analog for speed comparison
float cpu_run_time(struct trans_thread *trans, int addresses) {
for(int i = 0; i < addresses; i++) {
translate_cpu2(&trans[i]);
}
return 0;
}
/* --------------------------- host code ------------------------------*/
double read_timer() {
struct timeval end;
gettimeofday( &end, NULL );
return end.tv_sec+1.e-6*end.tv_usec;
}
//sequential phase 1: construct the table
int construct_table(void *table, int *levels, int num_levels) {
int i, j, level_size = 1;
void **table_ptr = (void **) table;
unsigned long **level_ptr;
// set intermediate addresses of table
for(i = 0; i < num_levels-1; i++)
{
level_size *= levels[i];
level_ptr = (unsigned long **) table + level_size + (((unsigned long *)table_ptr - (unsigned long *) table)/(sizeof(unsigned long *)));
fprintf(stderr, "level_size: %d, level_ptr: %d, table_ptr: %d\n", level_size, (level_ptr- (unsigned long **) table) / sizeof(void *), (unsigned long **) table_ptr - (unsigned long **) table);
for(j = 0; j < level_size; j++) {
table_ptr[j] = level_ptr + ((j)*levels[i+1]);
}
table_ptr += level_size;
}
assert((intptr_t )table_ptr - (intptr_t )table < max_table);
// set last level of page table to garbage;
for(i = 0; i < level_size * levels[num_levels-1]; i++) {
*table_ptr = (unsigned long *) i;
table_ptr++;
}
assert((intptr_t )table_ptr - (intptr_t )table == max_table);
// return number of entries at the lowest level of the page table
return levels[num_levels-1] * level_size;
}
//sequential phase 2: generate struct trans_thread for each address
struct trans_thread *gen_addresses(int num_addr, int levels, int *level_sizes, void **pgd)
{
int i,j;
struct trans_thread *new_threads = (struct trans_thread *)malloc(sizeof(struct trans_thread) * num_addr);
if (!new_threads){
fprintf(stderr, "malloc failed: %d\n", strerror(errno));
exit(1);
}
for(i = 0; i < num_addr; i++)
{
new_threads[i].curr_table = pgd;
new_threads[i].max = levels;
new_threads[i].curr = 0;
for(j = 0; j < levels; j++) {
new_threads[i].offset[j] =
rand() % level_sizes[j];
}
}
return new_threads;
}
////////////////////////////////////////////////////////////////////////////////
//
// Main Program
//
////////////////////////////////////////////////////////////////////////////////
int main(int argc, char** argv) {
void **d_pg_table; //device page table
int i, j, table_size = 0, level_size = 1,
total_addresses, table_lowest_addresses,
levels = argc-3;
int level_sizes[levels];
//struct trans_thread *sample;
struct trans_thread *h_new_threads; //host
struct trans_thread *d_new_threads; //device
cudaError_t cudaStat;
//start of the program
printf("===============================================================================\n");
srand(time(NULL));
// get number of pointers in contiguous page table
for(i = 1, j =0; i < argc; i++) {
if ( !strcmp(argv[i], "-n")) {
total_addresses = atoi(argv[++i]);
continue;
}
level_size *= atoi(argv[i]);
level_sizes[j++] = atoi(argv[i]);
table_size += level_size;
}
//tuning the parameters of the device
// fixed block size (512 x1x1 threads)
const dim3 blockSize(BLOCK_D1, BLOCK_D2, BLOCK_D3);
// determine number of blocks we need for a given problem size
int tmp = ceil(pow(total_addresses/BLOCK_D1, 0.5));
printf("Grid dimension is %i x %i\n", tmp, tmp);
//grid size
dim3 gridSize(tmp, tmp, 1);
//total number of threads
int nthreads = BLOCK_D1*BLOCK_D2*BLOCK_D3*tmp*tmp;
//threads number legitimacy check
if (nthreads < total_addresses){
printf("\n============ NOT ENOUGH THREADS TO COVER total addresses=%d ===============\n\n",total_addresses);
} else {
printf("Launching %d threads (total_addresses=%d)\n", nthreads, total_addresses);
}
// allocate host memory
max_table = table_size * sizeof(void *); //total size of page table
void **pg_table = (void **) malloc(sizeof(void *) * table_size);
if (!pg_table) {
fprintf(stderr, "host memory allocation failed: %d\n", strerror(errno));
exit(1);
}
else {
printf ("host memory allocation succeeded.\n");
}
// allocate device memory
cudaStat = cudaMalloc(&d_pg_table, sizeof(void *) * table_size);
if(cudaStat != cudaSuccess) {
printf ("device memory allocation failed.\n");
return EXIT_FAILURE;
}
else {
printf ("device memory allocation succeeded.\n");
}
/* --------------------------- sequential code on CPU; phase 1 --------------------------------------*/
//number of entries at the lowest level of the page table
//number of translatable addresses
printf ("now construct the page table on the host.\n");
table_lowest_addresses = construct_table(pg_table, level_sizes, levels);
fprintf(stderr, "number of translatable addresses: %d\n", table_lowest_addresses);
fprintf(stderr, "total size of page table: %d\n", max_table);
cudaDeviceSynchronize();
double tInit = read_timer();
/* --------------------------- copy the page table from CPU to the GPU ------------------------------*/
cudaStat = cudaMemcpy(d_pg_table, pg_table, sizeof(void *) * table_size, cudaMemcpyHostToDevice);
printf("Memory Copy for page table from Host to Device");
if (cudaStat != cudaSuccess){
printf("failed.\n");
return EXIT_FAILURE;
} else {
printf("successful.\n");
}
cudaDeviceSynchronize();
double tTransferToGPU_pgtable = read_timer();
/* --------------------------- sequential code on CPU; phase 2 ---------------------------------------*/
h_new_threads = gen_addresses(total_addresses, levels, level_sizes, pg_table);
cudaDeviceSynchronize();
double tInit2 = read_timer();
/* ------------------------- copy the trans_threads from CPU to the GPU ------------------------------*/
cudaStat = cudaMalloc( (void**) &d_new_threads, sizeof(struct trans_thread) * total_addresses) ;
if (cudaStat != cudaSuccess){
printf("device memory allocation for d_new_threads failed.\n");
return EXIT_FAILURE;
} else {
printf("device memory allocation for d_new_threads succeeded.\n");
}
cudaStat = cudaMemcpy( d_new_threads, h_new_threads, sizeof(struct trans_thread) * total_addresses, cudaMemcpyHostToDevice);
printf("Memory Copy h_new_threads from Host to Device");
if (cudaStat != cudaSuccess){
printf("failed.\n");
return EXIT_FAILURE;
} else {
printf(" successful.\n");
}
cudaCheckErrors("cudaMemcpy h_new_threads fail");
cudaDeviceSynchronize();
double tTransferToGPU_threads = read_timer();
/* ----------------------------------- parallel code on GPU: kernel -----------------------------------*/
gpu_run_time<<<gridSize, blockSize>>>(d_new_threads, total_addresses);
cudaError_t cudaerr = cudaDeviceSynchronize();
if (cudaerr){
printf("kernel launch failed with error \"%s\".\n",
cudaGetErrorString(cudaerr));
} else {
printf("kernel launch success!\n");
}
cudaDeviceSynchronize();
double gpu_time = read_timer();
printf("GPU done!\n");
/* --------------------------------- sequential code on CPU; phase 3 ----------------------------------*/
printf("now do calculation on CPU for comparison!\n");
cpu_run_time(h_new_threads, total_addresses);
double cpu_time = read_timer();
fprintf(stderr, "The CPU took %lu microseconds to compute %d addresses. ""For a table of depth %d.\n", cpu_time - gpu_time , total_addresses, levels);
/* --------------------------------- sequential code on CPU; phase 4 ----------------------------------*/
printf("Timing results for n = %d\n", total_addresses);
//printf("page table Transfer to GPU time: %f\n", tTransferToGPU_pgtable - tInit);
//printf("threads Transfer to GPU time: %f\n", tTransferToGPU_threads - tInit2);
printf("Calculation time (GPU): %f\n", gpu_time - tTransferToGPU_threads);
//printf("Transfer from GPU time: %f\n", tTransferFromGPU - gpu_time);
printf("Calculation time (CPU): %f\n", cpu_time - gpu_time);
printf("Freeing memory...\n");
printf("====================================================\n");
free(pg_table);
free(h_new_threads);
cudaFree(d_pg_table);
cudaFree(d_new_threads);
return 0;
} | /***********************************************************************************
This work is COMS 4824 Architecture Final Project, advised by Professor Martha Kim.
"A Walk on the Hyperthreaded Side:
an Implementation and Analysis of Translating Virtual Addresses on a GPU"
Copyright (c) 2017 Columbia University.
All rights reserved.
Created by Serena Liu and Raphael Norwitz.
AWS EC2 instance configuration:
--Instance type: g2.2xlarge
--AMI Id: NVIDIA CUDA 7.5 Toolkit on Amazon Linux-0ce7aca3-5b96-4ff4-8396-05245687380a-ami-52420645.3 (ami-52f7b345)
CUDA examples used:
https://raw.githubusercontent.com/berkeley-scf/gpu-workshop-2016/master/kernelExample.cu
Software Usage:
--compile: nvcc page_walk.cu -o page_walk.out
--output: ./page_walk.out -n <total addresses> <intermediate table parameters>
(eg, ./page_walk.out -n 400 2 3 2 4)
************************************************************************************/
#include <stdio.h>
#include <stdlib.h>
#include <unistd.h>
#include <string.h>
#include <errno.h>
#include <assert.h>
#include <sys/time.h>
#include <time.h>
#include <hip/hip_runtime.h>
#include <stdint.h>
#define BLOCK_D1 512
#define BLOCK_D2 1
#define BLOCK_D3 1
#define MAX_LEVELS 20
#define cudaCheckErrors(msg) \
do { \
hipError_t __err = hipGetLastError(); \
if (__err != hipSuccess) { \
fprintf(stderr, "Fatal error: %s (%s at %s:%d)\n", \
msg, hipGetErrorString(__err), \
__FILE__, __LINE__); \
fprintf(stderr, "*** FAILED - ABORTING\n"); \
exit(1); \
} \
} while (0)
static int max_table;
struct trans_thread {
void **curr_table;
unsigned long cuda_result;
int offset[MAX_LEVELS];
int curr;
int max;
};
//function called by CUDA kernel
__host__ __device__ int translate_cpu(struct trans_thread *trans) {
unsigned long *gpu_ptr = (unsigned long *) trans->curr_table;
while(trans->curr < trans->max-1) {
gpu_ptr = (unsigned long *) gpu_ptr[trans->offset[trans->curr]];
trans->curr++;
}
return (int) *((int *) gpu_ptr + trans->offset[trans->curr]);
// ((void *) trans->curr_table + trans->offset[trans->max-1]);
}
//CPU counterpart
int translate_cpu2(struct trans_thread *trans) {
while(trans->curr < trans->max-1) {
trans->curr_table = (void **) trans->curr_table[trans->offset[trans->curr]];
trans->curr++;
}
return (int) *((int *) trans->curr_table + trans->offset[trans->curr]);
// ((void *) trans->curr_table + trans->offset[trans->max-1]);
}
// CUDA kernel: gpu_run_time<<<gridSize, blockSize>>>(d_new_threads, total_addresses);
__global__ void gpu_run_time(struct trans_thread *trans, int addresses) {
// id of the block
int myblock = blockIdx.x + blockIdx.y * gridDim.x;
// size of each block (within grid of blocks)
int blocksize = blockDim.x * blockDim.y * blockDim.z;
// id of thread in a given block
int subthread = threadIdx.z*(blockDim.x * blockDim.y) + threadIdx.y*blockDim.x + threadIdx.x;
// assign overall id/index of the thread
int idx = myblock * blocksize + subthread;
if(idx < addresses) {
translate_cpu(&trans[idx]);
}
}
// CPU analog for speed comparison
float cpu_run_time(struct trans_thread *trans, int addresses) {
for(int i = 0; i < addresses; i++) {
translate_cpu2(&trans[i]);
}
return 0;
}
/* --------------------------- host code ------------------------------*/
double read_timer() {
struct timeval end;
gettimeofday( &end, NULL );
return end.tv_sec+1.e-6*end.tv_usec;
}
//sequential phase 1: construct the table
int construct_table(void *table, int *levels, int num_levels) {
int i, j, level_size = 1;
void **table_ptr = (void **) table;
unsigned long **level_ptr;
// set intermediate addresses of table
for(i = 0; i < num_levels-1; i++)
{
level_size *= levels[i];
level_ptr = (unsigned long **) table + level_size + (((unsigned long *)table_ptr - (unsigned long *) table)/(sizeof(unsigned long *)));
fprintf(stderr, "level_size: %d, level_ptr: %d, table_ptr: %d\n", level_size, (level_ptr- (unsigned long **) table) / sizeof(void *), (unsigned long **) table_ptr - (unsigned long **) table);
for(j = 0; j < level_size; j++) {
table_ptr[j] = level_ptr + ((j)*levels[i+1]);
}
table_ptr += level_size;
}
assert((intptr_t )table_ptr - (intptr_t )table < max_table);
// set last level of page table to garbage;
for(i = 0; i < level_size * levels[num_levels-1]; i++) {
*table_ptr = (unsigned long *) i;
table_ptr++;
}
assert((intptr_t )table_ptr - (intptr_t )table == max_table);
// return number of entries at the lowest level of the page table
return levels[num_levels-1] * level_size;
}
//sequential phase 2: generate struct trans_thread for each address
struct trans_thread *gen_addresses(int num_addr, int levels, int *level_sizes, void **pgd)
{
int i,j;
struct trans_thread *new_threads = (struct trans_thread *)malloc(sizeof(struct trans_thread) * num_addr);
if (!new_threads){
fprintf(stderr, "malloc failed: %d\n", strerror(errno));
exit(1);
}
for(i = 0; i < num_addr; i++)
{
new_threads[i].curr_table = pgd;
new_threads[i].max = levels;
new_threads[i].curr = 0;
for(j = 0; j < levels; j++) {
new_threads[i].offset[j] =
rand() % level_sizes[j];
}
}
return new_threads;
}
////////////////////////////////////////////////////////////////////////////////
//
// Main Program
//
////////////////////////////////////////////////////////////////////////////////
int main(int argc, char** argv) {
void **d_pg_table; //device page table
int i, j, table_size = 0, level_size = 1,
total_addresses, table_lowest_addresses,
levels = argc-3;
int level_sizes[levels];
//struct trans_thread *sample;
struct trans_thread *h_new_threads; //host
struct trans_thread *d_new_threads; //device
hipError_t cudaStat;
//start of the program
printf("===============================================================================\n");
srand(time(NULL));
// get number of pointers in contiguous page table
for(i = 1, j =0; i < argc; i++) {
if ( !strcmp(argv[i], "-n")) {
total_addresses = atoi(argv[++i]);
continue;
}
level_size *= atoi(argv[i]);
level_sizes[j++] = atoi(argv[i]);
table_size += level_size;
}
//tuning the parameters of the device
// fixed block size (512 x1x1 threads)
const dim3 blockSize(BLOCK_D1, BLOCK_D2, BLOCK_D3);
// determine number of blocks we need for a given problem size
int tmp = ceil(pow(total_addresses/BLOCK_D1, 0.5));
printf("Grid dimension is %i x %i\n", tmp, tmp);
//grid size
dim3 gridSize(tmp, tmp, 1);
//total number of threads
int nthreads = BLOCK_D1*BLOCK_D2*BLOCK_D3*tmp*tmp;
//threads number legitimacy check
if (nthreads < total_addresses){
printf("\n============ NOT ENOUGH THREADS TO COVER total addresses=%d ===============\n\n",total_addresses);
} else {
printf("Launching %d threads (total_addresses=%d)\n", nthreads, total_addresses);
}
// allocate host memory
max_table = table_size * sizeof(void *); //total size of page table
void **pg_table = (void **) malloc(sizeof(void *) * table_size);
if (!pg_table) {
fprintf(stderr, "host memory allocation failed: %d\n", strerror(errno));
exit(1);
}
else {
printf ("host memory allocation succeeded.\n");
}
// allocate device memory
cudaStat = hipMalloc(&d_pg_table, sizeof(void *) * table_size);
if(cudaStat != hipSuccess) {
printf ("device memory allocation failed.\n");
return EXIT_FAILURE;
}
else {
printf ("device memory allocation succeeded.\n");
}
/* --------------------------- sequential code on CPU; phase 1 --------------------------------------*/
//number of entries at the lowest level of the page table
//number of translatable addresses
printf ("now construct the page table on the host.\n");
table_lowest_addresses = construct_table(pg_table, level_sizes, levels);
fprintf(stderr, "number of translatable addresses: %d\n", table_lowest_addresses);
fprintf(stderr, "total size of page table: %d\n", max_table);
hipDeviceSynchronize();
double tInit = read_timer();
/* --------------------------- copy the page table from CPU to the GPU ------------------------------*/
cudaStat = hipMemcpy(d_pg_table, pg_table, sizeof(void *) * table_size, hipMemcpyHostToDevice);
printf("Memory Copy for page table from Host to Device");
if (cudaStat != hipSuccess){
printf("failed.\n");
return EXIT_FAILURE;
} else {
printf("successful.\n");
}
hipDeviceSynchronize();
double tTransferToGPU_pgtable = read_timer();
/* --------------------------- sequential code on CPU; phase 2 ---------------------------------------*/
h_new_threads = gen_addresses(total_addresses, levels, level_sizes, pg_table);
hipDeviceSynchronize();
double tInit2 = read_timer();
/* ------------------------- copy the trans_threads from CPU to the GPU ------------------------------*/
cudaStat = hipMalloc( (void**) &d_new_threads, sizeof(struct trans_thread) * total_addresses) ;
if (cudaStat != hipSuccess){
printf("device memory allocation for d_new_threads failed.\n");
return EXIT_FAILURE;
} else {
printf("device memory allocation for d_new_threads succeeded.\n");
}
cudaStat = hipMemcpy( d_new_threads, h_new_threads, sizeof(struct trans_thread) * total_addresses, hipMemcpyHostToDevice);
printf("Memory Copy h_new_threads from Host to Device");
if (cudaStat != hipSuccess){
printf("failed.\n");
return EXIT_FAILURE;
} else {
printf(" successful.\n");
}
cudaCheckErrors("hipMemcpy h_new_threads fail");
hipDeviceSynchronize();
double tTransferToGPU_threads = read_timer();
/* ----------------------------------- parallel code on GPU: kernel -----------------------------------*/
gpu_run_time<<<gridSize, blockSize>>>(d_new_threads, total_addresses);
hipError_t cudaerr = hipDeviceSynchronize();
if (cudaerr){
printf("kernel launch failed with error \"%s\".\n",
hipGetErrorString(cudaerr));
} else {
printf("kernel launch success!\n");
}
hipDeviceSynchronize();
double gpu_time = read_timer();
printf("GPU done!\n");
/* --------------------------------- sequential code on CPU; phase 3 ----------------------------------*/
printf("now do calculation on CPU for comparison!\n");
cpu_run_time(h_new_threads, total_addresses);
double cpu_time = read_timer();
fprintf(stderr, "The CPU took %lu microseconds to compute %d addresses. ""For a table of depth %d.\n", cpu_time - gpu_time , total_addresses, levels);
/* --------------------------------- sequential code on CPU; phase 4 ----------------------------------*/
printf("Timing results for n = %d\n", total_addresses);
//printf("page table Transfer to GPU time: %f\n", tTransferToGPU_pgtable - tInit);
//printf("threads Transfer to GPU time: %f\n", tTransferToGPU_threads - tInit2);
printf("Calculation time (GPU): %f\n", gpu_time - tTransferToGPU_threads);
//printf("Transfer from GPU time: %f\n", tTransferFromGPU - gpu_time);
printf("Calculation time (CPU): %f\n", cpu_time - gpu_time);
printf("Freeing memory...\n");
printf("====================================================\n");
free(pg_table);
free(h_new_threads);
hipFree(d_pg_table);
hipFree(d_new_threads);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | /***********************************************************************************
This work is COMS 4824 Architecture Final Project, advised by Professor Martha Kim.
"A Walk on the Hyperthreaded Side:
an Implementation and Analysis of Translating Virtual Addresses on a GPU"
Copyright (c) 2017 Columbia University.
All rights reserved.
Created by Serena Liu and Raphael Norwitz.
AWS EC2 instance configuration:
--Instance type: g2.2xlarge
--AMI Id: NVIDIA CUDA 7.5 Toolkit on Amazon Linux-0ce7aca3-5b96-4ff4-8396-05245687380a-ami-52420645.3 (ami-52f7b345)
CUDA examples used:
https://raw.githubusercontent.com/berkeley-scf/gpu-workshop-2016/master/kernelExample.cu
Software Usage:
--compile: nvcc page_walk.cu -o page_walk.out
--output: ./page_walk.out -n <total addresses> <intermediate table parameters>
(eg, ./page_walk.out -n 400 2 3 2 4)
************************************************************************************/
#include <stdio.h>
#include <stdlib.h>
#include <unistd.h>
#include <string.h>
#include <errno.h>
#include <assert.h>
#include <sys/time.h>
#include <time.h>
#include <hip/hip_runtime.h>
#include <stdint.h>
#define BLOCK_D1 512
#define BLOCK_D2 1
#define BLOCK_D3 1
#define MAX_LEVELS 20
#define cudaCheckErrors(msg) \
do { \
hipError_t __err = hipGetLastError(); \
if (__err != hipSuccess) { \
fprintf(stderr, "Fatal error: %s (%s at %s:%d)\n", \
msg, hipGetErrorString(__err), \
__FILE__, __LINE__); \
fprintf(stderr, "*** FAILED - ABORTING\n"); \
exit(1); \
} \
} while (0)
static int max_table;
struct trans_thread {
void **curr_table;
unsigned long cuda_result;
int offset[MAX_LEVELS];
int curr;
int max;
};
//function called by CUDA kernel
__host__ __device__ int translate_cpu(struct trans_thread *trans) {
unsigned long *gpu_ptr = (unsigned long *) trans->curr_table;
while(trans->curr < trans->max-1) {
gpu_ptr = (unsigned long *) gpu_ptr[trans->offset[trans->curr]];
trans->curr++;
}
return (int) *((int *) gpu_ptr + trans->offset[trans->curr]);
// ((void *) trans->curr_table + trans->offset[trans->max-1]);
}
//CPU counterpart
int translate_cpu2(struct trans_thread *trans) {
while(trans->curr < trans->max-1) {
trans->curr_table = (void **) trans->curr_table[trans->offset[trans->curr]];
trans->curr++;
}
return (int) *((int *) trans->curr_table + trans->offset[trans->curr]);
// ((void *) trans->curr_table + trans->offset[trans->max-1]);
}
// CUDA kernel: gpu_run_time<<<gridSize, blockSize>>>(d_new_threads, total_addresses);
__global__ void gpu_run_time(struct trans_thread *trans, int addresses) {
// id of the block
int myblock = blockIdx.x + blockIdx.y * gridDim.x;
// size of each block (within grid of blocks)
int blocksize = blockDim.x * blockDim.y * blockDim.z;
// id of thread in a given block
int subthread = threadIdx.z*(blockDim.x * blockDim.y) + threadIdx.y*blockDim.x + threadIdx.x;
// assign overall id/index of the thread
int idx = myblock * blocksize + subthread;
if(idx < addresses) {
translate_cpu(&trans[idx]);
}
}
// CPU analog for speed comparison
float cpu_run_time(struct trans_thread *trans, int addresses) {
for(int i = 0; i < addresses; i++) {
translate_cpu2(&trans[i]);
}
return 0;
}
/* --------------------------- host code ------------------------------*/
double read_timer() {
struct timeval end;
gettimeofday( &end, NULL );
return end.tv_sec+1.e-6*end.tv_usec;
}
//sequential phase 1: construct the table
int construct_table(void *table, int *levels, int num_levels) {
int i, j, level_size = 1;
void **table_ptr = (void **) table;
unsigned long **level_ptr;
// set intermediate addresses of table
for(i = 0; i < num_levels-1; i++)
{
level_size *= levels[i];
level_ptr = (unsigned long **) table + level_size + (((unsigned long *)table_ptr - (unsigned long *) table)/(sizeof(unsigned long *)));
fprintf(stderr, "level_size: %d, level_ptr: %d, table_ptr: %d\n", level_size, (level_ptr- (unsigned long **) table) / sizeof(void *), (unsigned long **) table_ptr - (unsigned long **) table);
for(j = 0; j < level_size; j++) {
table_ptr[j] = level_ptr + ((j)*levels[i+1]);
}
table_ptr += level_size;
}
assert((intptr_t )table_ptr - (intptr_t )table < max_table);
// set last level of page table to garbage;
for(i = 0; i < level_size * levels[num_levels-1]; i++) {
*table_ptr = (unsigned long *) i;
table_ptr++;
}
assert((intptr_t )table_ptr - (intptr_t )table == max_table);
// return number of entries at the lowest level of the page table
return levels[num_levels-1] * level_size;
}
//sequential phase 2: generate struct trans_thread for each address
struct trans_thread *gen_addresses(int num_addr, int levels, int *level_sizes, void **pgd)
{
int i,j;
struct trans_thread *new_threads = (struct trans_thread *)malloc(sizeof(struct trans_thread) * num_addr);
if (!new_threads){
fprintf(stderr, "malloc failed: %d\n", strerror(errno));
exit(1);
}
for(i = 0; i < num_addr; i++)
{
new_threads[i].curr_table = pgd;
new_threads[i].max = levels;
new_threads[i].curr = 0;
for(j = 0; j < levels; j++) {
new_threads[i].offset[j] =
rand() % level_sizes[j];
}
}
return new_threads;
}
////////////////////////////////////////////////////////////////////////////////
//
// Main Program
//
////////////////////////////////////////////////////////////////////////////////
int main(int argc, char** argv) {
void **d_pg_table; //device page table
int i, j, table_size = 0, level_size = 1,
total_addresses, table_lowest_addresses,
levels = argc-3;
int level_sizes[levels];
//struct trans_thread *sample;
struct trans_thread *h_new_threads; //host
struct trans_thread *d_new_threads; //device
hipError_t cudaStat;
//start of the program
printf("===============================================================================\n");
srand(time(NULL));
// get number of pointers in contiguous page table
for(i = 1, j =0; i < argc; i++) {
if ( !strcmp(argv[i], "-n")) {
total_addresses = atoi(argv[++i]);
continue;
}
level_size *= atoi(argv[i]);
level_sizes[j++] = atoi(argv[i]);
table_size += level_size;
}
//tuning the parameters of the device
// fixed block size (512 x1x1 threads)
const dim3 blockSize(BLOCK_D1, BLOCK_D2, BLOCK_D3);
// determine number of blocks we need for a given problem size
int tmp = ceil(pow(total_addresses/BLOCK_D1, 0.5));
printf("Grid dimension is %i x %i\n", tmp, tmp);
//grid size
dim3 gridSize(tmp, tmp, 1);
//total number of threads
int nthreads = BLOCK_D1*BLOCK_D2*BLOCK_D3*tmp*tmp;
//threads number legitimacy check
if (nthreads < total_addresses){
printf("\n============ NOT ENOUGH THREADS TO COVER total addresses=%d ===============\n\n",total_addresses);
} else {
printf("Launching %d threads (total_addresses=%d)\n", nthreads, total_addresses);
}
// allocate host memory
max_table = table_size * sizeof(void *); //total size of page table
void **pg_table = (void **) malloc(sizeof(void *) * table_size);
if (!pg_table) {
fprintf(stderr, "host memory allocation failed: %d\n", strerror(errno));
exit(1);
}
else {
printf ("host memory allocation succeeded.\n");
}
// allocate device memory
cudaStat = hipMalloc(&d_pg_table, sizeof(void *) * table_size);
if(cudaStat != hipSuccess) {
printf ("device memory allocation failed.\n");
return EXIT_FAILURE;
}
else {
printf ("device memory allocation succeeded.\n");
}
/* --------------------------- sequential code on CPU; phase 1 --------------------------------------*/
//number of entries at the lowest level of the page table
//number of translatable addresses
printf ("now construct the page table on the host.\n");
table_lowest_addresses = construct_table(pg_table, level_sizes, levels);
fprintf(stderr, "number of translatable addresses: %d\n", table_lowest_addresses);
fprintf(stderr, "total size of page table: %d\n", max_table);
hipDeviceSynchronize();
double tInit = read_timer();
/* --------------------------- copy the page table from CPU to the GPU ------------------------------*/
cudaStat = hipMemcpy(d_pg_table, pg_table, sizeof(void *) * table_size, hipMemcpyHostToDevice);
printf("Memory Copy for page table from Host to Device");
if (cudaStat != hipSuccess){
printf("failed.\n");
return EXIT_FAILURE;
} else {
printf("successful.\n");
}
hipDeviceSynchronize();
double tTransferToGPU_pgtable = read_timer();
/* --------------------------- sequential code on CPU; phase 2 ---------------------------------------*/
h_new_threads = gen_addresses(total_addresses, levels, level_sizes, pg_table);
hipDeviceSynchronize();
double tInit2 = read_timer();
/* ------------------------- copy the trans_threads from CPU to the GPU ------------------------------*/
cudaStat = hipMalloc( (void**) &d_new_threads, sizeof(struct trans_thread) * total_addresses) ;
if (cudaStat != hipSuccess){
printf("device memory allocation for d_new_threads failed.\n");
return EXIT_FAILURE;
} else {
printf("device memory allocation for d_new_threads succeeded.\n");
}
cudaStat = hipMemcpy( d_new_threads, h_new_threads, sizeof(struct trans_thread) * total_addresses, hipMemcpyHostToDevice);
printf("Memory Copy h_new_threads from Host to Device");
if (cudaStat != hipSuccess){
printf("failed.\n");
return EXIT_FAILURE;
} else {
printf(" successful.\n");
}
cudaCheckErrors("hipMemcpy h_new_threads fail");
hipDeviceSynchronize();
double tTransferToGPU_threads = read_timer();
/* ----------------------------------- parallel code on GPU: kernel -----------------------------------*/
gpu_run_time<<<gridSize, blockSize>>>(d_new_threads, total_addresses);
hipError_t cudaerr = hipDeviceSynchronize();
if (cudaerr){
printf("kernel launch failed with error \"%s\".\n",
hipGetErrorString(cudaerr));
} else {
printf("kernel launch success!\n");
}
hipDeviceSynchronize();
double gpu_time = read_timer();
printf("GPU done!\n");
/* --------------------------------- sequential code on CPU; phase 3 ----------------------------------*/
printf("now do calculation on CPU for comparison!\n");
cpu_run_time(h_new_threads, total_addresses);
double cpu_time = read_timer();
fprintf(stderr, "The CPU took %lu microseconds to compute %d addresses. ""For a table of depth %d.\n", cpu_time - gpu_time , total_addresses, levels);
/* --------------------------------- sequential code on CPU; phase 4 ----------------------------------*/
printf("Timing results for n = %d\n", total_addresses);
//printf("page table Transfer to GPU time: %f\n", tTransferToGPU_pgtable - tInit);
//printf("threads Transfer to GPU time: %f\n", tTransferToGPU_threads - tInit2);
printf("Calculation time (GPU): %f\n", gpu_time - tTransferToGPU_threads);
//printf("Transfer from GPU time: %f\n", tTransferFromGPU - gpu_time);
printf("Calculation time (CPU): %f\n", cpu_time - gpu_time);
printf("Freeing memory...\n");
printf("====================================================\n");
free(pg_table);
free(h_new_threads);
hipFree(d_pg_table);
hipFree(d_new_threads);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z12gpu_run_timeP12trans_threadi
.globl _Z12gpu_run_timeP12trans_threadi
.p2align 8
.type _Z12gpu_run_timeP12trans_threadi,@function
_Z12gpu_run_timeP12trans_threadi:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x10
s_load_b64 s[2:3], s[0:1], 0x1c
v_bfe_u32 v1, v0, 20, 10
s_waitcnt lgkmcnt(0)
s_mul_i32 s4, s4, s15
s_and_b32 s3, s3, 0xffff
s_add_i32 s4, s4, s14
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, s4, s3, v[1:2]
v_bfe_u32 v1, v0, 10, 10
s_load_b32 s3, s[0:1], 0x8
s_lshr_b32 s4, s2, 16
s_and_b32 s2, s2, 0xffff
v_mad_u64_u32 v[3:4], null, v2, s4, v[1:2]
v_and_b32_e32 v2, 0x3ff, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[0:1], null, v3, s2, v[2:3]
s_mov_b32 s2, exec_lo
s_waitcnt lgkmcnt(0)
v_cmpx_gt_i32_e64 s3, v0
s_cbranch_execz .LBB0_5
s_load_b64 s[0:1], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
v_mad_i64_i32 v[2:3], null, v0, 0x68, s[0:1]
global_load_b64 v[0:1], v[2:3], off offset:96
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v4, -1, v1
s_delay_alu instid0(VALU_DEP_1)
v_cmp_lt_i32_e32 vcc_lo, v0, v4
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_5
v_add_co_u32 v1, vcc_lo, v2, 0x60
v_add_co_ci_u32_e32 v2, vcc_lo, 0, v3, vcc_lo
s_mov_b32 s0, 0
.LBB0_3:
v_add_nc_u32_e32 v0, 1, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_ge_i32_e32 vcc_lo, v0, v4
s_or_b32 s0, vcc_lo, s0
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB0_3
s_or_b32 exec_lo, exec_lo, s0
global_store_b32 v[1:2], v0, off
.LBB0_5:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12gpu_run_timeP12trans_threadi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 2
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z12gpu_run_timeP12trans_threadi, .Lfunc_end0-_Z12gpu_run_timeP12trans_threadi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12gpu_run_timeP12trans_threadi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z12gpu_run_timeP12trans_threadi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | /***********************************************************************************
This work is COMS 4824 Architecture Final Project, advised by Professor Martha Kim.
"A Walk on the Hyperthreaded Side:
an Implementation and Analysis of Translating Virtual Addresses on a GPU"
Copyright (c) 2017 Columbia University.
All rights reserved.
Created by Serena Liu and Raphael Norwitz.
AWS EC2 instance configuration:
--Instance type: g2.2xlarge
--AMI Id: NVIDIA CUDA 7.5 Toolkit on Amazon Linux-0ce7aca3-5b96-4ff4-8396-05245687380a-ami-52420645.3 (ami-52f7b345)
CUDA examples used:
https://raw.githubusercontent.com/berkeley-scf/gpu-workshop-2016/master/kernelExample.cu
Software Usage:
--compile: nvcc page_walk.cu -o page_walk.out
--output: ./page_walk.out -n <total addresses> <intermediate table parameters>
(eg, ./page_walk.out -n 400 2 3 2 4)
************************************************************************************/
#include <stdio.h>
#include <stdlib.h>
#include <unistd.h>
#include <string.h>
#include <errno.h>
#include <assert.h>
#include <sys/time.h>
#include <time.h>
#include <hip/hip_runtime.h>
#include <stdint.h>
#define BLOCK_D1 512
#define BLOCK_D2 1
#define BLOCK_D3 1
#define MAX_LEVELS 20
#define cudaCheckErrors(msg) \
do { \
hipError_t __err = hipGetLastError(); \
if (__err != hipSuccess) { \
fprintf(stderr, "Fatal error: %s (%s at %s:%d)\n", \
msg, hipGetErrorString(__err), \
__FILE__, __LINE__); \
fprintf(stderr, "*** FAILED - ABORTING\n"); \
exit(1); \
} \
} while (0)
static int max_table;
struct trans_thread {
void **curr_table;
unsigned long cuda_result;
int offset[MAX_LEVELS];
int curr;
int max;
};
//function called by CUDA kernel
__host__ __device__ int translate_cpu(struct trans_thread *trans) {
unsigned long *gpu_ptr = (unsigned long *) trans->curr_table;
while(trans->curr < trans->max-1) {
gpu_ptr = (unsigned long *) gpu_ptr[trans->offset[trans->curr]];
trans->curr++;
}
return (int) *((int *) gpu_ptr + trans->offset[trans->curr]);
// ((void *) trans->curr_table + trans->offset[trans->max-1]);
}
//CPU counterpart
int translate_cpu2(struct trans_thread *trans) {
while(trans->curr < trans->max-1) {
trans->curr_table = (void **) trans->curr_table[trans->offset[trans->curr]];
trans->curr++;
}
return (int) *((int *) trans->curr_table + trans->offset[trans->curr]);
// ((void *) trans->curr_table + trans->offset[trans->max-1]);
}
// CUDA kernel: gpu_run_time<<<gridSize, blockSize>>>(d_new_threads, total_addresses);
__global__ void gpu_run_time(struct trans_thread *trans, int addresses) {
// id of the block
int myblock = blockIdx.x + blockIdx.y * gridDim.x;
// size of each block (within grid of blocks)
int blocksize = blockDim.x * blockDim.y * blockDim.z;
// id of thread in a given block
int subthread = threadIdx.z*(blockDim.x * blockDim.y) + threadIdx.y*blockDim.x + threadIdx.x;
// assign overall id/index of the thread
int idx = myblock * blocksize + subthread;
if(idx < addresses) {
translate_cpu(&trans[idx]);
}
}
// CPU analog for speed comparison
float cpu_run_time(struct trans_thread *trans, int addresses) {
for(int i = 0; i < addresses; i++) {
translate_cpu2(&trans[i]);
}
return 0;
}
/* --------------------------- host code ------------------------------*/
double read_timer() {
struct timeval end;
gettimeofday( &end, NULL );
return end.tv_sec+1.e-6*end.tv_usec;
}
//sequential phase 1: construct the table
int construct_table(void *table, int *levels, int num_levels) {
int i, j, level_size = 1;
void **table_ptr = (void **) table;
unsigned long **level_ptr;
// set intermediate addresses of table
for(i = 0; i < num_levels-1; i++)
{
level_size *= levels[i];
level_ptr = (unsigned long **) table + level_size + (((unsigned long *)table_ptr - (unsigned long *) table)/(sizeof(unsigned long *)));
fprintf(stderr, "level_size: %d, level_ptr: %d, table_ptr: %d\n", level_size, (level_ptr- (unsigned long **) table) / sizeof(void *), (unsigned long **) table_ptr - (unsigned long **) table);
for(j = 0; j < level_size; j++) {
table_ptr[j] = level_ptr + ((j)*levels[i+1]);
}
table_ptr += level_size;
}
assert((intptr_t )table_ptr - (intptr_t )table < max_table);
// set last level of page table to garbage;
for(i = 0; i < level_size * levels[num_levels-1]; i++) {
*table_ptr = (unsigned long *) i;
table_ptr++;
}
assert((intptr_t )table_ptr - (intptr_t )table == max_table);
// return number of entries at the lowest level of the page table
return levels[num_levels-1] * level_size;
}
//sequential phase 2: generate struct trans_thread for each address
struct trans_thread *gen_addresses(int num_addr, int levels, int *level_sizes, void **pgd)
{
int i,j;
struct trans_thread *new_threads = (struct trans_thread *)malloc(sizeof(struct trans_thread) * num_addr);
if (!new_threads){
fprintf(stderr, "malloc failed: %d\n", strerror(errno));
exit(1);
}
for(i = 0; i < num_addr; i++)
{
new_threads[i].curr_table = pgd;
new_threads[i].max = levels;
new_threads[i].curr = 0;
for(j = 0; j < levels; j++) {
new_threads[i].offset[j] =
rand() % level_sizes[j];
}
}
return new_threads;
}
////////////////////////////////////////////////////////////////////////////////
//
// Main Program
//
////////////////////////////////////////////////////////////////////////////////
int main(int argc, char** argv) {
void **d_pg_table; //device page table
int i, j, table_size = 0, level_size = 1,
total_addresses, table_lowest_addresses,
levels = argc-3;
int level_sizes[levels];
//struct trans_thread *sample;
struct trans_thread *h_new_threads; //host
struct trans_thread *d_new_threads; //device
hipError_t cudaStat;
//start of the program
printf("===============================================================================\n");
srand(time(NULL));
// get number of pointers in contiguous page table
for(i = 1, j =0; i < argc; i++) {
if ( !strcmp(argv[i], "-n")) {
total_addresses = atoi(argv[++i]);
continue;
}
level_size *= atoi(argv[i]);
level_sizes[j++] = atoi(argv[i]);
table_size += level_size;
}
//tuning the parameters of the device
// fixed block size (512 x1x1 threads)
const dim3 blockSize(BLOCK_D1, BLOCK_D2, BLOCK_D3);
// determine number of blocks we need for a given problem size
int tmp = ceil(pow(total_addresses/BLOCK_D1, 0.5));
printf("Grid dimension is %i x %i\n", tmp, tmp);
//grid size
dim3 gridSize(tmp, tmp, 1);
//total number of threads
int nthreads = BLOCK_D1*BLOCK_D2*BLOCK_D3*tmp*tmp;
//threads number legitimacy check
if (nthreads < total_addresses){
printf("\n============ NOT ENOUGH THREADS TO COVER total addresses=%d ===============\n\n",total_addresses);
} else {
printf("Launching %d threads (total_addresses=%d)\n", nthreads, total_addresses);
}
// allocate host memory
max_table = table_size * sizeof(void *); //total size of page table
void **pg_table = (void **) malloc(sizeof(void *) * table_size);
if (!pg_table) {
fprintf(stderr, "host memory allocation failed: %d\n", strerror(errno));
exit(1);
}
else {
printf ("host memory allocation succeeded.\n");
}
// allocate device memory
cudaStat = hipMalloc(&d_pg_table, sizeof(void *) * table_size);
if(cudaStat != hipSuccess) {
printf ("device memory allocation failed.\n");
return EXIT_FAILURE;
}
else {
printf ("device memory allocation succeeded.\n");
}
/* --------------------------- sequential code on CPU; phase 1 --------------------------------------*/
//number of entries at the lowest level of the page table
//number of translatable addresses
printf ("now construct the page table on the host.\n");
table_lowest_addresses = construct_table(pg_table, level_sizes, levels);
fprintf(stderr, "number of translatable addresses: %d\n", table_lowest_addresses);
fprintf(stderr, "total size of page table: %d\n", max_table);
hipDeviceSynchronize();
double tInit = read_timer();
/* --------------------------- copy the page table from CPU to the GPU ------------------------------*/
cudaStat = hipMemcpy(d_pg_table, pg_table, sizeof(void *) * table_size, hipMemcpyHostToDevice);
printf("Memory Copy for page table from Host to Device");
if (cudaStat != hipSuccess){
printf("failed.\n");
return EXIT_FAILURE;
} else {
printf("successful.\n");
}
hipDeviceSynchronize();
double tTransferToGPU_pgtable = read_timer();
/* --------------------------- sequential code on CPU; phase 2 ---------------------------------------*/
h_new_threads = gen_addresses(total_addresses, levels, level_sizes, pg_table);
hipDeviceSynchronize();
double tInit2 = read_timer();
/* ------------------------- copy the trans_threads from CPU to the GPU ------------------------------*/
cudaStat = hipMalloc( (void**) &d_new_threads, sizeof(struct trans_thread) * total_addresses) ;
if (cudaStat != hipSuccess){
printf("device memory allocation for d_new_threads failed.\n");
return EXIT_FAILURE;
} else {
printf("device memory allocation for d_new_threads succeeded.\n");
}
cudaStat = hipMemcpy( d_new_threads, h_new_threads, sizeof(struct trans_thread) * total_addresses, hipMemcpyHostToDevice);
printf("Memory Copy h_new_threads from Host to Device");
if (cudaStat != hipSuccess){
printf("failed.\n");
return EXIT_FAILURE;
} else {
printf(" successful.\n");
}
cudaCheckErrors("hipMemcpy h_new_threads fail");
hipDeviceSynchronize();
double tTransferToGPU_threads = read_timer();
/* ----------------------------------- parallel code on GPU: kernel -----------------------------------*/
gpu_run_time<<<gridSize, blockSize>>>(d_new_threads, total_addresses);
hipError_t cudaerr = hipDeviceSynchronize();
if (cudaerr){
printf("kernel launch failed with error \"%s\".\n",
hipGetErrorString(cudaerr));
} else {
printf("kernel launch success!\n");
}
hipDeviceSynchronize();
double gpu_time = read_timer();
printf("GPU done!\n");
/* --------------------------------- sequential code on CPU; phase 3 ----------------------------------*/
printf("now do calculation on CPU for comparison!\n");
cpu_run_time(h_new_threads, total_addresses);
double cpu_time = read_timer();
fprintf(stderr, "The CPU took %lu microseconds to compute %d addresses. ""For a table of depth %d.\n", cpu_time - gpu_time , total_addresses, levels);
/* --------------------------------- sequential code on CPU; phase 4 ----------------------------------*/
printf("Timing results for n = %d\n", total_addresses);
//printf("page table Transfer to GPU time: %f\n", tTransferToGPU_pgtable - tInit);
//printf("threads Transfer to GPU time: %f\n", tTransferToGPU_threads - tInit2);
printf("Calculation time (GPU): %f\n", gpu_time - tTransferToGPU_threads);
//printf("Transfer from GPU time: %f\n", tTransferFromGPU - gpu_time);
printf("Calculation time (CPU): %f\n", cpu_time - gpu_time);
printf("Freeing memory...\n");
printf("====================================================\n");
free(pg_table);
free(h_new_threads);
hipFree(d_pg_table);
hipFree(d_new_threads);
return 0;
} | .text
.file "page_walk.hip"
.globl _Z13translate_cpuP12trans_thread # -- Begin function _Z13translate_cpuP12trans_thread
.p2align 4, 0x90
.type _Z13translate_cpuP12trans_thread,@function
_Z13translate_cpuP12trans_thread: # @_Z13translate_cpuP12trans_thread
.cfi_startproc
# %bb.0:
movq (%rdi), %rax
movslq 100(%rdi), %rdx
decq %rdx
movl 96(%rdi), %ecx
cmpl %edx, %ecx
jge .LBB0_3
# %bb.1: # %.lr.ph.preheader
movslq %ecx, %rcx
.p2align 4, 0x90
.LBB0_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl %ecx, %esi
movslq 16(%rdi,%rcx,4), %r8
movq (%rax,%r8,8), %rax
incq %rcx
incl %esi
movl %esi, 96(%rdi)
cmpq %rcx, %rdx
jne .LBB0_2
.LBB0_3: # %._crit_edge
movslq %ecx, %rcx
movslq 16(%rdi,%rcx,4), %rcx
movl (%rax,%rcx,4), %eax
retq
.Lfunc_end0:
.size _Z13translate_cpuP12trans_thread, .Lfunc_end0-_Z13translate_cpuP12trans_thread
.cfi_endproc
# -- End function
.globl _Z14translate_cpu2P12trans_thread # -- Begin function _Z14translate_cpu2P12trans_thread
.p2align 4, 0x90
.type _Z14translate_cpu2P12trans_thread,@function
_Z14translate_cpu2P12trans_thread: # @_Z14translate_cpu2P12trans_thread
.cfi_startproc
# %bb.0:
movslq 100(%rdi), %rcx
decq %rcx
movl 96(%rdi), %eax
cmpl %ecx, %eax
jge .LBB1_3
# %bb.1: # %.lr.ph
cltq
movq (%rdi), %rdx
.p2align 4, 0x90
.LBB1_2: # =>This Inner Loop Header: Depth=1
movl %eax, %esi
movslq 16(%rdi,%rax,4), %r8
movq (%rdx,%r8,8), %rdx
movq %rdx, (%rdi)
incq %rax
incl %esi
movl %esi, 96(%rdi)
cmpq %rax, %rcx
jne .LBB1_2
.LBB1_3: # %._crit_edge
movq (%rdi), %rcx
cltq
movslq 16(%rdi,%rax,4), %rax
movl (%rcx,%rax,4), %eax
retq
.Lfunc_end1:
.size _Z14translate_cpu2P12trans_thread, .Lfunc_end1-_Z14translate_cpu2P12trans_thread
.cfi_endproc
# -- End function
.globl _Z27__device_stub__gpu_run_timeP12trans_threadi # -- Begin function _Z27__device_stub__gpu_run_timeP12trans_threadi
.p2align 4, 0x90
.type _Z27__device_stub__gpu_run_timeP12trans_threadi,@function
_Z27__device_stub__gpu_run_timeP12trans_threadi: # @_Z27__device_stub__gpu_run_timeP12trans_threadi
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z12gpu_run_timeP12trans_threadi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end2:
.size _Z27__device_stub__gpu_run_timeP12trans_threadi, .Lfunc_end2-_Z27__device_stub__gpu_run_timeP12trans_threadi
.cfi_endproc
# -- End function
.globl _Z12cpu_run_timeP12trans_threadi # -- Begin function _Z12cpu_run_timeP12trans_threadi
.p2align 4, 0x90
.type _Z12cpu_run_timeP12trans_threadi,@function
_Z12cpu_run_timeP12trans_threadi: # @_Z12cpu_run_timeP12trans_threadi
.cfi_startproc
# %bb.0:
testl %esi, %esi
jle .LBB3_7
# %bb.1: # %.lr.ph.preheader
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset %rbx, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %esi, %eax
leaq 16(%rdi), %rcx
xorl %edx, %edx
jmp .LBB3_2
.p2align 4, 0x90
.LBB3_5: # %_Z14translate_cpu2P12trans_thread.exit
# in Loop: Header=BB3_2 Depth=1
incq %rdx
addq $104, %rcx
cmpq %rax, %rdx
je .LBB3_6
.LBB3_2: # %.lr.ph
# =>This Loop Header: Depth=1
# Child Loop BB3_4 Depth 2
imulq $104, %rdx, %r8
movslq 100(%rdi,%r8), %rbx
leal -1(%rbx), %esi
movslq 96(%rdi,%r8), %r14
cmpl %esi, %r14d
jge .LBB3_5
# %bb.3: # %.lr.ph.i
# in Loop: Header=BB3_2 Depth=1
leaq (%rdi,%r8), %rsi
addq %rdi, %r8
addq $96, %r8
movq (%rsi), %r9
leaq (%rcx,%r14,4), %r10
movq %r14, %r11
notq %r11
addq %rbx, %r11
leal 1(%r14), %ebx
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB3_4: # Parent Loop BB3_2 Depth=1
# => This Inner Loop Header: Depth=2
movslq (%r10,%r14,4), %r15
movq (%r9,%r15,8), %r9
movq %r9, (%rsi)
leal (%rbx,%r14), %ebp
movl %ebp, (%r8)
incq %r14
cmpq %r14, %r11
jne .LBB3_4
jmp .LBB3_5
.LBB3_6:
popq %rbx
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r14
.cfi_restore %r15
.cfi_restore %rbp
.LBB3_7: # %._crit_edge
xorps %xmm0, %xmm0
retq
.Lfunc_end3:
.size _Z12cpu_run_timeP12trans_threadi, .Lfunc_end3-_Z12cpu_run_timeP12trans_threadi
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z10read_timerv
.LCPI4_0:
.quad 0x3eb0c6f7a0b5ed8d # double 9.9999999999999995E-7
.text
.globl _Z10read_timerv
.p2align 4, 0x90
.type _Z10read_timerv,@function
_Z10read_timerv: # @_Z10read_timerv
.cfi_startproc
# %bb.0:
subq $24, %rsp
.cfi_def_cfa_offset 32
leaq 8(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
cvtsi2sdq 8(%rsp), %xmm1
cvtsi2sdq 16(%rsp), %xmm0
mulsd .LCPI4_0(%rip), %xmm0
addsd %xmm1, %xmm0
addq $24, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end4:
.size _Z10read_timerv, .Lfunc_end4-_Z10read_timerv
.cfi_endproc
# -- End function
.globl _Z15construct_tablePvPii # -- Begin function _Z15construct_tablePvPii
.p2align 4, 0x90
.type _Z15construct_tablePvPii,@function
_Z15construct_tablePvPii: # @_Z15construct_tablePvPii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $24, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
# kill: def $edx killed $edx def $rdx
movq %rsi, %r14
movq %rdi, %r15
leal -1(%rdx), %eax
movl $1, %ebx
cmpl $2, %edx
movl %eax, 12(%rsp) # 4-byte Spill
jl .LBB5_1
# %bb.6: # %.lr.ph50
movl %eax, %eax
movq %rax, 16(%rsp) # 8-byte Spill
movl $1, %ebx
xorl %r13d, %r13d
movq %r15, %r12
.LBB5_7: # =>This Loop Header: Depth=1
# Child Loop BB5_9 Depth 2
movslq (%r14,%r13,4), %rax
movslq %ebx, %rbx
imulq %rax, %rbx
leaq (%r15,%rbx,8), %rax
movq %r12, %r8
subq %r15, %r8
sarq $3, %r8
movq %r8, %rbp
andq $-8, %rbp
addq %rax, %rbp
movq stderr(%rip), %rdi
movq %rbp, %rcx
subq %r15, %rcx
sarq $3, %rcx
shrq $3, %rcx
movl $.L.str, %esi
movl %ebx, %edx
xorl %eax, %eax
callq fprintf
testl %ebx, %ebx
jle .LBB5_10
# %bb.8: # %.lr.ph
# in Loop: Header=BB5_7 Depth=1
movslq 4(%r14,%r13,4), %rax
movl %ebx, %ecx
shlq $3, %rax
xorl %edx, %edx
.p2align 4, 0x90
.LBB5_9: # Parent Loop BB5_7 Depth=1
# => This Inner Loop Header: Depth=2
movq %rbp, (%r12,%rdx,8)
incq %rdx
addq %rax, %rbp
cmpq %rdx, %rcx
jne .LBB5_9
.LBB5_10: # %._crit_edge
# in Loop: Header=BB5_7 Depth=1
leaq (%r12,%rbx,8), %r12
incq %r13
cmpq 16(%rsp), %r13 # 8-byte Folded Reload
jne .LBB5_7
jmp .LBB5_2
.LBB5_1:
movq %r15, %r12
.LBB5_2: # %.preheader
movslq 12(%rsp), %rax # 4-byte Folded Reload
imull (%r14,%rax,4), %ebx
testl %ebx, %ebx
jle .LBB5_5
# %bb.3: # %.lr.ph55.preheader
movl %ebx, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB5_4: # %.lr.ph55
# =>This Inner Loop Header: Depth=1
movq %rcx, (%r12,%rcx,8)
incq %rcx
cmpq %rcx, %rax
jne .LBB5_4
.LBB5_5: # %._crit_edge56
movl %ebx, %eax
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end5:
.size _Z15construct_tablePvPii, .Lfunc_end5-_Z15construct_tablePvPii
.cfi_endproc
# -- End function
.globl _Z13gen_addressesiiPiPPv # -- Begin function _Z13gen_addressesiiPiPPv
.p2align 4, 0x90
.type _Z13gen_addressesiiPiPPv,@function
_Z13gen_addressesiiPiPPv: # @_Z13gen_addressesiiPiPPv
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $24, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rcx, 16(%rsp) # 8-byte Spill
movq %rdx, %r14
movl %esi, 4(%rsp) # 4-byte Spill
movl %edi, %r12d
movslq %edi, %rax
imulq $104, %rax, %rdi
callq malloc
testq %rax, %rax
je .LBB6_8
# %bb.1: # %.preheader
movq %rax, %rbx
testl %r12d, %r12d
jle .LBB6_7
# %bb.2: # %.lr.ph25
movl %r12d, %eax
movq %rax, 8(%rsp) # 8-byte Spill
movl 4(%rsp), %r13d # 4-byte Reload
movq %rbx, %r15
addq $16, %r15
xorl %r12d, %r12d
jmp .LBB6_3
.p2align 4, 0x90
.LBB6_6: # %._crit_edge
# in Loop: Header=BB6_3 Depth=1
incq %r12
addq $104, %r15
cmpq 8(%rsp), %r12 # 8-byte Folded Reload
je .LBB6_7
.LBB6_3: # =>This Loop Header: Depth=1
# Child Loop BB6_5 Depth 2
imulq $104, %r12, %rax
movq 16(%rsp), %rcx # 8-byte Reload
movq %rcx, (%rbx,%rax)
movl 4(%rsp), %ecx # 4-byte Reload
movl %ecx, 100(%rbx,%rax)
movl $0, 96(%rbx,%rax)
testl %ecx, %ecx
jle .LBB6_6
# %bb.4: # %.lr.ph.preheader
# in Loop: Header=BB6_3 Depth=1
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB6_5: # %.lr.ph
# Parent Loop BB6_3 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
cltd
idivl (%r14,%rbp,4)
movl %edx, (%r15,%rbp,4)
incq %rbp
cmpq %rbp, %r13
jne .LBB6_5
jmp .LBB6_6
.LBB6_7: # %._crit_edge26
movq %rbx, %rax
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB6_8:
.cfi_def_cfa_offset 80
movq stderr(%rip), %rbx
callq __errno_location
movl (%rax), %edi
callq strerror
movl $.L.str.1, %esi
movq %rbx, %rdi
movq %rax, %rdx
xorl %eax, %eax
callq fprintf
movl $1, %edi
callq exit
.Lfunc_end6:
.size _Z13gen_addressesiiPiPPv, .Lfunc_end6-_Z13gen_addressesiiPiPPv
.cfi_endproc
# -- End function
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function main
.LCPI7_0:
.quad 0x7fffffffffffffff # double NaN
.quad 0x7fffffffffffffff # double NaN
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset %rbp, -16
movq %rsp, %rbp
.cfi_def_cfa_register %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $104, %rsp
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
movq %rsi, %r14
movl %edi, %r12d
movq %rsp, %r13
leal -3(%r12), %eax
movq %rsp, %rcx
movq %rax, -120(%rbp) # 8-byte Spill
leaq 15(,%rax,4), %rax
andq $-16, %rax
subq %rax, %rcx
movq %rcx, -56(%rbp) # 8-byte Spill
movq %rcx, %rsp
movl $.Lstr, %edi
callq puts@PLT
xorl %r15d, %r15d
xorl %edi, %edi
callq time
movl %eax, %edi
callq srand
# implicit-def: $ebx
movq %r12, -96(%rbp) # 8-byte Spill
cmpl $2, %r12d
jl .LBB7_7
# %bb.1: # %.lr.ph.preheader
xorl %eax, %eax
movq %rax, -64(%rbp) # 8-byte Spill
movq %r13, -72(%rbp) # 8-byte Spill
movl $1, %r12d
movl $0, -48(%rbp) # 4-byte Folded Spill
movl $1, %r13d
# implicit-def: $eax
movq %rax, -80(%rbp) # 8-byte Spill
movq %r14, %rbx
jmp .LBB7_2
.p2align 4, 0x90
.LBB7_4: # in Loop: Header=BB7_2 Depth=1
movq %r14, %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
imull %eax, %r13d
movq -64(%rbp), %rdx # 8-byte Reload
movslq %edx, %rcx
incl %edx
movq %rdx, -64(%rbp) # 8-byte Spill
movq -56(%rbp), %rdx # 8-byte Reload
movl %eax, (%rdx,%rcx,4)
addl %r13d, -48(%rbp) # 4-byte Folded Spill
.LBB7_5: # in Loop: Header=BB7_2 Depth=1
incl %r12d
cmpl -96(%rbp), %r12d # 4-byte Folded Reload
jge .LBB7_6
.LBB7_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movslq %r12d, %r15
movq (%rbx,%r15,8), %r14
movl $.L.str.3, %esi
movq %r14, %rdi
callq strcmp
testl %eax, %eax
jne .LBB7_4
# %bb.3: # in Loop: Header=BB7_2 Depth=1
leal 1(%r15), %r12d
movq 8(%rbx,%r15,8), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, -80(%rbp) # 8-byte Spill
jmp .LBB7_5
.LBB7_6: # %._crit_edge.loopexit
movslq -48(%rbp), %r15 # 4-byte Folded Reload
shlq $3, %r15
movq -72(%rbp), %r13 # 8-byte Reload
movq -80(%rbp), %rbx # 8-byte Reload
.LBB7_7: # %._crit_edge
leal 511(%rbx), %eax
testl %ebx, %ebx
cmovnsl %ebx, %eax
sarl $9, %eax
cvtsi2sd %eax, %xmm0
xorpd %xmm1, %xmm1
movq %r13, %r14
ucomisd %xmm1, %xmm0
jb .LBB7_9
# %bb.8:
sqrtsd %xmm0, %xmm0
jmp .LBB7_10
.LBB7_9: # %call.sqrt
callq sqrt@PLT
.LBB7_10: # %._crit_edge.split
andpd .LCPI7_0(%rip), %xmm0
callq ceil@PLT
cvttsd2si %xmm0, %r13d
movl $.L.str.4, %edi
movl %r13d, %esi
movl %r13d, %edx
xorl %eax, %eax
callq printf
movl %r13d, %esi
imull %r13d, %esi
shll $9, %esi
cmpl %ebx, %esi
jge .LBB7_12
# %bb.11:
movl $.L.str.5, %edi
movl %ebx, %esi
xorl %eax, %eax
callq printf
jmp .LBB7_13
.LBB7_12:
movl $.L.str.6, %edi
movl %ebx, %edx
xorl %eax, %eax
callq printf
.LBB7_13:
movq %r15, %rdi
callq malloc
testq %rax, %rax
je .LBB7_39
# %bb.14:
movq %rax, %r12
movl $.Lstr.1, %edi
callq puts@PLT
leaq -128(%rbp), %rdi
movq %r15, %rsi
callq hipMalloc
testl %eax, %eax
je .LBB7_16
# %bb.15:
movl $.Lstr.15, %edi
callq puts@PLT
movl $1, %ebx
.LBB7_38:
movq %r14, %rsp
movl %ebx, %eax
leaq -40(%rbp), %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
.cfi_def_cfa %rsp, 8
retq
.LBB7_16:
.cfi_def_cfa %rbp, 16
movq %r13, -136(%rbp) # 8-byte Spill
movq %r15, -64(%rbp) # 8-byte Spill
movq %rbx, -80(%rbp) # 8-byte Spill
movq %r14, -72(%rbp) # 8-byte Spill
movl $.Lstr.2, %edi
callq puts@PLT
movl $.Lstr.3, %edi
callq puts@PLT
movq -96(%rbp), %rax # 8-byte Reload
leal -4(%rax), %ecx
movl %ecx, -84(%rbp) # 4-byte Spill
movl $1, %r15d
movq %r12, -48(%rbp) # 8-byte Spill
movq %r12, %r14
cmpl $5, %eax
jl .LBB7_22
# %bb.17: # %.lr.ph50.i
movl -84(%rbp), %ebx # 4-byte Reload
movl $1, %r15d
xorl %r12d, %r12d
movq -48(%rbp), %r14 # 8-byte Reload
jmp .LBB7_18
.p2align 4, 0x90
.LBB7_21: # %._crit_edge.i
# in Loop: Header=BB7_18 Depth=1
leaq (%r14,%r15,8), %r14
incq %r12
cmpq %rbx, %r12
je .LBB7_22
.LBB7_18: # =>This Loop Header: Depth=1
# Child Loop BB7_20 Depth 2
movq -56(%rbp), %rax # 8-byte Reload
movslq (%rax,%r12,4), %rax
movslq %r15d, %r15
imulq %rax, %r15
movq -48(%rbp), %rdx # 8-byte Reload
leaq (%rdx,%r15,8), %rax
movq %r14, %r8
subq %rdx, %r8
sarq $3, %r8
movq %r8, %r13
andq $-8, %r13
addq %rax, %r13
movq stderr(%rip), %rdi
movq %r13, %rcx
subq %rdx, %rcx
sarq $3, %rcx
shrq $3, %rcx
movl $.L.str, %esi
movl %r15d, %edx
xorl %eax, %eax
callq fprintf
testl %r15d, %r15d
jle .LBB7_21
# %bb.19: # %.lr.ph.i
# in Loop: Header=BB7_18 Depth=1
movq -56(%rbp), %rax # 8-byte Reload
movslq 4(%rax,%r12,4), %rax
movl %r15d, %ecx
shlq $3, %rax
xorl %edx, %edx
.p2align 4, 0x90
.LBB7_20: # Parent Loop BB7_18 Depth=1
# => This Inner Loop Header: Depth=2
movq %r13, (%r14,%rdx,8)
incq %rdx
addq %rax, %r13
cmpq %rdx, %rcx
jne .LBB7_20
jmp .LBB7_21
.LBB7_22: # %.preheader.i
movslq -84(%rbp), %rax # 4-byte Folded Reload
movq -56(%rbp), %rcx # 8-byte Reload
imull (%rcx,%rax,4), %r15d
testl %r15d, %r15d
jle .LBB7_25
# %bb.23: # %.lr.ph55.preheader.i
movl %r15d, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB7_24: # %.lr.ph55.i
# =>This Inner Loop Header: Depth=1
movq %rcx, (%r14,%rcx,8)
incq %rcx
cmpq %rcx, %rax
jne .LBB7_24
.LBB7_25: # %_Z15construct_tablePvPii.exit
movq stderr(%rip), %rdi
movl $.L.str.12, %esi
movl %r15d, %edx
xorl %eax, %eax
callq fprintf
movq stderr(%rip), %rdi
movl $.L.str.13, %esi
movq -64(%rbp), %r14 # 8-byte Reload
movl %r14d, %edx
xorl %eax, %eax
callq fprintf
callq hipDeviceSynchronize
leaq -112(%rbp), %rdi
xorl %esi, %esi
callq gettimeofday
movq -128(%rbp), %rdi
movl $1, %ebx
movq -48(%rbp), %r15 # 8-byte Reload
movq %r15, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
movl %eax, %r14d
movl $.L.str.14, %edi
xorl %eax, %eax
callq printf
testl %r14d, %r14d
movq -136(%rbp), %r13 # 8-byte Reload
je .LBB7_28
.LBB7_26:
movl $.Lstr.14, %edi
jmp .LBB7_27
.LBB7_28:
movl $.Lstr.4, %edi
callq puts@PLT
callq hipDeviceSynchronize
leaq -112(%rbp), %rdi
xorl %esi, %esi
callq gettimeofday
movq -80(%rbp), %r14 # 8-byte Reload
movl %r14d, %edi
movq -120(%rbp), %rsi # 8-byte Reload
# kill: def $esi killed $esi killed $rsi
movq -56(%rbp), %rdx # 8-byte Reload
movq %r15, %rcx
callq _Z13gen_addressesiiPiPPv
movq %rax, %r12
callq hipDeviceSynchronize
leaq -112(%rbp), %rdi
xorl %esi, %esi
callq gettimeofday
movslq %r14d, %rax
imulq $104, %rax, %r15
leaq -112(%rbp), %rdi
movq %r15, %rsi
callq hipMalloc
testl %eax, %eax
je .LBB7_30
# %bb.29:
movl $.Lstr.13, %edi
.LBB7_27:
callq puts@PLT
movq -72(%rbp), %r14 # 8-byte Reload
jmp .LBB7_38
.LBB7_30:
movl $.Lstr.5, %edi
callq puts@PLT
movq -112(%rbp), %rdi
movq %r12, %rsi
movq %r15, %rdx
movl $1, %ecx
callq hipMemcpy
movl %eax, %r14d
movl $.L.str.19, %edi
xorl %eax, %eax
callq printf
testl %r14d, %r14d
jne .LBB7_26
# %bb.31:
movl $.Lstr.6, %edi
callq puts@PLT
callq hipGetLastError
testl %eax, %eax
movq -72(%rbp), %r14 # 8-byte Reload
jne .LBB7_40
# %bb.32:
movabsq $4294967297, %rbx # imm = 0x100000001
imulq %rbx, %r13
callq hipDeviceSynchronize
callq _Z10read_timerv
movsd %xmm0, -96(%rbp) # 8-byte Spill
addq $511, %rbx # imm = 0x1FF
movq %r13, %rdi
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
movq -80(%rbp), %rbx # 8-byte Reload
jne .LBB7_34
# %bb.33:
movq -112(%rbp), %rdi
movl %ebx, %esi
callq _Z27__device_stub__gpu_run_timeP12trans_threadi
.LBB7_34:
callq hipDeviceSynchronize
testl %eax, %eax
jne .LBB7_35
# %bb.36:
movl $.Lstr.7, %edi
callq puts@PLT
jmp .LBB7_37
.LBB7_35:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.25, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
.LBB7_37:
callq hipDeviceSynchronize
callq _Z10read_timerv
movsd %xmm0, -64(%rbp) # 8-byte Spill
movl $.Lstr.8, %edi
callq puts@PLT
movl $.Lstr.9, %edi
callq puts@PLT
movq %r12, %rdi
movl %ebx, %esi
callq _Z12cpu_run_timeP12trans_threadi
callq _Z10read_timerv
movq stderr(%rip), %rdi
subsd -64(%rbp), %xmm0 # 8-byte Folded Reload
movsd %xmm0, -56(%rbp) # 8-byte Spill
movl $.L.str.29, %esi
movl %ebx, %edx
movq -120(%rbp), %rcx # 8-byte Reload
# kill: def $ecx killed $ecx killed $rcx
movb $1, %al
callq fprintf
movq %rbx, %rsi
xorl %ebx, %ebx
movl $.L.str.30, %edi
# kill: def $esi killed $esi killed $rsi
xorl %eax, %eax
callq printf
movsd -64(%rbp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
subsd -96(%rbp), %xmm0 # 8-byte Folded Reload
movl $.L.str.31, %edi
movb $1, %al
callq printf
movl $.L.str.32, %edi
movsd -56(%rbp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
movb $1, %al
callq printf
movl $.Lstr.10, %edi
callq puts@PLT
movl $.Lstr.11, %edi
callq puts@PLT
movq -48(%rbp), %rdi # 8-byte Reload
callq free
movq %r12, %rdi
callq free
movq -128(%rbp), %rdi
callq hipFree
movq -112(%rbp), %rdi
callq hipFree
jmp .LBB7_38
.LBB7_39:
movq stderr(%rip), %rbx
callq __errno_location
movl (%rax), %edi
callq strerror
movl $.L.str.7, %esi
movq %rbx, %rdi
movq %rax, %rdx
xorl %eax, %eax
callq fprintf
movl $1, %edi
callq exit
.LBB7_40:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.21, %esi
movl $.L.str.22, %edx
movl $.L.str.23, %r8d
movq %rbx, %rdi
movq %rax, %rcx
movl $305, %r9d # imm = 0x131
xorl %eax, %eax
callq fprintf
movq stderr(%rip), %rcx
movl $.L.str.24, %edi
movl $22, %esi
movl $1, %edx
callq fwrite@PLT
movl $1, %edi
callq exit
.Lfunc_end7:
.size main, .Lfunc_end7-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB8_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB8_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12gpu_run_timeP12trans_threadi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end8:
.size __hip_module_ctor, .Lfunc_end8-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB9_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB9_2:
retq
.Lfunc_end9:
.size __hip_module_dtor, .Lfunc_end9-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z12gpu_run_timeP12trans_threadi,@object # @_Z12gpu_run_timeP12trans_threadi
.section .rodata,"a",@progbits
.globl _Z12gpu_run_timeP12trans_threadi
.p2align 3, 0x0
_Z12gpu_run_timeP12trans_threadi:
.quad _Z27__device_stub__gpu_run_timeP12trans_threadi
.size _Z12gpu_run_timeP12trans_threadi, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "level_size: %d, level_ptr: %d, table_ptr: %d\n"
.size .L.str, 46
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "malloc failed: %d\n"
.size .L.str.1, 19
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "-n"
.size .L.str.3, 3
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Grid dimension is %i x %i\n"
.size .L.str.4, 27
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "\n============ NOT ENOUGH THREADS TO COVER total addresses=%d ===============\n\n"
.size .L.str.5, 79
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "Launching %d threads (total_addresses=%d)\n"
.size .L.str.6, 43
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "host memory allocation failed: %d\n"
.size .L.str.7, 35
.type .L.str.12,@object # @.str.12
.L.str.12:
.asciz "number of translatable addresses: %d\n"
.size .L.str.12, 38
.type .L.str.13,@object # @.str.13
.L.str.13:
.asciz "total size of page table: %d\n"
.size .L.str.13, 30
.type .L.str.14,@object # @.str.14
.L.str.14:
.asciz "Memory Copy for page table from Host to Device"
.size .L.str.14, 47
.type .L.str.19,@object # @.str.19
.L.str.19:
.asciz "Memory Copy h_new_threads from Host to Device"
.size .L.str.19, 46
.type .L.str.21,@object # @.str.21
.L.str.21:
.asciz "Fatal error: %s (%s at %s:%d)\n"
.size .L.str.21, 31
.type .L.str.22,@object # @.str.22
.L.str.22:
.asciz "hipMemcpy h_new_threads fail"
.size .L.str.22, 29
.type .L.str.23,@object # @.str.23
.L.str.23:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/raphael-s-norwitz/arch_final_project/master/page_walk.hip"
.size .L.str.23, 115
.type .L.str.24,@object # @.str.24
.L.str.24:
.asciz "*** FAILED - ABORTING\n"
.size .L.str.24, 23
.type .L.str.25,@object # @.str.25
.L.str.25:
.asciz "kernel launch failed with error \"%s\".\n"
.size .L.str.25, 39
.type .L.str.29,@object # @.str.29
.L.str.29:
.asciz "The CPU took %lu microseconds to compute %d addresses. For a table of depth %d.\n"
.size .L.str.29, 81
.type .L.str.30,@object # @.str.30
.L.str.30:
.asciz "Timing results for n = %d\n"
.size .L.str.30, 27
.type .L.str.31,@object # @.str.31
.L.str.31:
.asciz "Calculation time (GPU): %f\n"
.size .L.str.31, 28
.type .L.str.32,@object # @.str.32
.L.str.32:
.asciz "Calculation time (CPU): %f\n"
.size .L.str.32, 28
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z12gpu_run_timeP12trans_threadi"
.size .L__unnamed_1, 33
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "==============================================================================="
.size .Lstr, 80
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "host memory allocation succeeded."
.size .Lstr.1, 34
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "device memory allocation succeeded."
.size .Lstr.2, 36
.type .Lstr.3,@object # @str.3
.Lstr.3:
.asciz "now construct the page table on the host."
.size .Lstr.3, 42
.type .Lstr.4,@object # @str.4
.Lstr.4:
.asciz "successful."
.size .Lstr.4, 12
.type .Lstr.5,@object # @str.5
.Lstr.5:
.asciz "device memory allocation for d_new_threads succeeded."
.size .Lstr.5, 54
.type .Lstr.6,@object # @str.6
.Lstr.6:
.asciz " successful."
.size .Lstr.6, 13
.type .Lstr.7,@object # @str.7
.Lstr.7:
.asciz "kernel launch success!"
.size .Lstr.7, 23
.type .Lstr.8,@object # @str.8
.Lstr.8:
.asciz "GPU done!"
.size .Lstr.8, 10
.type .Lstr.9,@object # @str.9
.Lstr.9:
.asciz "now do calculation on CPU for comparison!"
.size .Lstr.9, 42
.type .Lstr.10,@object # @str.10
.Lstr.10:
.asciz "Freeing memory..."
.size .Lstr.10, 18
.type .Lstr.11,@object # @str.11
.Lstr.11:
.asciz "===================================================="
.size .Lstr.11, 53
.type .Lstr.13,@object # @str.13
.Lstr.13:
.asciz "device memory allocation for d_new_threads failed."
.size .Lstr.13, 51
.type .Lstr.14,@object # @str.14
.Lstr.14:
.asciz "failed."
.size .Lstr.14, 8
.type .Lstr.15,@object # @str.15
.Lstr.15:
.asciz "device memory allocation failed."
.size .Lstr.15, 33
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__gpu_run_timeP12trans_threadi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12gpu_run_timeP12trans_threadi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z12gpu_run_timeP12trans_threadi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e280000002600 */
/*0030*/ S2R R5, SR_TID.Z ; /* 0x0000000000057919 */
/* 0x000e680000002300 */
/*0040*/ S2R R7, SR_TID.Y ; /* 0x0000000000077919 */
/* 0x000ea80000002200 */
/*0050*/ S2R R9, SR_TID.X ; /* 0x0000000000097919 */
/* 0x000ee20000002100 */
/*0060*/ IMAD R0, R3, c[0x0][0xc], R0 ; /* 0x0000030003007a24 */
/* 0x001fc800078e0200 */
/*0070*/ IMAD R0, R0, c[0x0][0x8], R5 ; /* 0x0000020000007a24 */
/* 0x002fc800078e0205 */
/*0080*/ IMAD R0, R0, c[0x0][0x4], R7 ; /* 0x0000010000007a24 */
/* 0x004fc800078e0207 */
/*0090*/ IMAD R0, R0, c[0x0][0x0], R9 ; /* 0x0000000000007a24 */
/* 0x008fca00078e0209 */
/*00a0*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x168], PT ; /* 0x00005a0000007a0c */
/* 0x000fda0003f06270 */
/*00b0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00c0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x68 ; /* 0x00000068ff037424 */
/* 0x000fe200078e00ff */
/*00d0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*00e0*/ IMAD.WIDE R2, R0, R3, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fca00078e0203 */
/*00f0*/ LDG.E.64 R4, [R2.64+0x60] ; /* 0x0000600402047981 */
/* 0x000ea4000c1e1b00 */
/*0100*/ IADD3 R7, R5, -0x1, RZ ; /* 0xffffffff05077810 */
/* 0x004fc80007ffe0ff */
/*0110*/ ISETP.GE.AND P0, PT, R4, R7, PT ; /* 0x000000070400720c */
/* 0x000fda0003f06270 */
/*0120*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0130*/ IMAD.IADD R0, R7, 0x1, -R4 ; /* 0x0000000107007824 */
/* 0x000fe200078e0a04 */
/*0140*/ BSSY B0, 0x200 ; /* 0x000000b000007945 */
/* 0x000fe20003800000 */
/*0150*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fc60003f0f070 */
/*0160*/ ISETP.GT.AND P1, PT, R0, 0x3, PT ; /* 0x000000030000780c */
/* 0x000fda0003f24270 */
/*0170*/ @!P1 BRA 0x1f0 ; /* 0x0000007000009947 */
/* 0x000fea0003800000 */
/*0180*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0190*/ IADD3 R0, R5, -0x4, RZ ; /* 0xfffffffc05007810 */
/* 0x000fe40007ffe0ff */
/*01a0*/ IADD3 R5, R4, 0x4, RZ ; /* 0x0000000404057810 */
/* 0x000fc80007ffe0ff */
/*01b0*/ ISETP.GE.AND P1, PT, R5, R0, PT ; /* 0x000000000500720c */
/* 0x000fe20003f26270 */
/*01c0*/ STG.E [R2.64+0x60], R5 ; /* 0x0000600502007986 */
/* 0x0001e2000c101904 */
/*01d0*/ IMAD.MOV.U32 R4, RZ, RZ, R5 ; /* 0x000000ffff047224 */
/* 0x000fd600078e0005 */
/*01e0*/ @!P1 BRA 0x1a0 ; /* 0xffffffb000009947 */
/* 0x001fea000383ffff */
/*01f0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0200*/ IMAD.IADD R0, R7, 0x1, -R4 ; /* 0x0000000107007824 */
/* 0x000fca00078e0a04 */
/*0210*/ ISETP.GT.AND P1, PT, R0, 0x1, PT ; /* 0x000000010000780c */
/* 0x000fda0003f24270 */
/*0220*/ @P1 PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000181c */
/* 0x000fe40003f0e170 */
/*0230*/ @P1 IADD3 R4, R4, 0x2, RZ ; /* 0x0000000204041810 */
/* 0x000fca0007ffe0ff */
/*0240*/ @P1 STG.E [R2.64+0x60], R4 ; /* 0x0000600402001986 */
/* 0x0001ec000c101904 */
/*0250*/ ISETP.LT.OR P0, PT, R4, R7, P0 ; /* 0x000000070400720c */
/* 0x000fda0000701670 */
/*0260*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0270*/ IADD3 R5, R4, 0x1, RZ ; /* 0x0000000104057810 */
/* 0x001fca0007ffe0ff */
/*0280*/ STG.E [R2.64+0x60], R5 ; /* 0x0000600502007986 */
/* 0x000fe2000c101904 */
/*0290*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*02a0*/ BRA 0x2a0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0300*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0310*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0320*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z12gpu_run_timeP12trans_threadi
.globl _Z12gpu_run_timeP12trans_threadi
.p2align 8
.type _Z12gpu_run_timeP12trans_threadi,@function
_Z12gpu_run_timeP12trans_threadi:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x10
s_load_b64 s[2:3], s[0:1], 0x1c
v_bfe_u32 v1, v0, 20, 10
s_waitcnt lgkmcnt(0)
s_mul_i32 s4, s4, s15
s_and_b32 s3, s3, 0xffff
s_add_i32 s4, s4, s14
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, s4, s3, v[1:2]
v_bfe_u32 v1, v0, 10, 10
s_load_b32 s3, s[0:1], 0x8
s_lshr_b32 s4, s2, 16
s_and_b32 s2, s2, 0xffff
v_mad_u64_u32 v[3:4], null, v2, s4, v[1:2]
v_and_b32_e32 v2, 0x3ff, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[0:1], null, v3, s2, v[2:3]
s_mov_b32 s2, exec_lo
s_waitcnt lgkmcnt(0)
v_cmpx_gt_i32_e64 s3, v0
s_cbranch_execz .LBB0_5
s_load_b64 s[0:1], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
v_mad_i64_i32 v[2:3], null, v0, 0x68, s[0:1]
global_load_b64 v[0:1], v[2:3], off offset:96
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v4, -1, v1
s_delay_alu instid0(VALU_DEP_1)
v_cmp_lt_i32_e32 vcc_lo, v0, v4
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_5
v_add_co_u32 v1, vcc_lo, v2, 0x60
v_add_co_ci_u32_e32 v2, vcc_lo, 0, v3, vcc_lo
s_mov_b32 s0, 0
.LBB0_3:
v_add_nc_u32_e32 v0, 1, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_ge_i32_e32 vcc_lo, v0, v4
s_or_b32 s0, vcc_lo, s0
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB0_3
s_or_b32 exec_lo, exec_lo, s0
global_store_b32 v[1:2], v0, off
.LBB0_5:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12gpu_run_timeP12trans_threadi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 2
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z12gpu_run_timeP12trans_threadi, .Lfunc_end0-_Z12gpu_run_timeP12trans_threadi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12gpu_run_timeP12trans_threadi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z12gpu_run_timeP12trans_threadi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #define W 500
#define H 500
#define TX 32 // number of threads per block along x-axis
#define TY 32 // number of threads per block along y-axis
__global__
void distanceKernel(float *d_out, int w, int h, float2 pos) {
const int c = blockIdx.x * blockDim.x + threadIdx.x;
const int r = blockIdx.y * blockDim.y + threadIdx.y;
const int i = r * w + c;
if ((c >= w) || (r >= h)) return;
// compute the distance and set d_out[i]
d_out[i] = sqrtf((c - pos.x) * (c - pos.x) + (r - pos.y) * (r - pos.y));
}
int main() {
float *out = (float*)calloc(W*H, sizeof(float));
float *d_out; // pointer for device array
cudaMalloc(&d_out, W * H * sizeof(float));
const float2 pos = {0.0f, 0.0f}; // set reference position
const dim3 blockSize(TX, TY);
const int bx = (W + TX - 1)/TX;
const int by = (W + TY - 1)/TY;
const dim3 gridSize = dim3(bx, by);
distanceKernel<<<gridSize, blockSize>>>(d_out, W, H, pos);
// copy the results to host
cudaMemcpy(out, d_out, W*H*sizeof(float), cudaMemcpyDeviceToHost);
cudaFree(d_out);
free(out);
return 0;
} | code for sm_80
Function : _Z14distanceKernelPfii6float2
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e280000002600 */
/*0020*/ S2R R3, SR_TID.Y ; /* 0x0000000000037919 */
/* 0x000e280000002200 */
/*0030*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x000e680000002500 */
/*0040*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e620000002100 */
/*0050*/ IMAD R0, R0, c[0x0][0x4], R3 ; /* 0x0000010000007a24 */
/* 0x001fca00078e0203 */
/*0060*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x16c], PT ; /* 0x00005b0000007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R5, R5, c[0x0][0x0], R2 ; /* 0x0000000005057a24 */
/* 0x002fca00078e0202 */
/*0080*/ ISETP.GE.OR P0, PT, R5, c[0x0][0x168], P0 ; /* 0x00005a0005007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ I2F R3, R0 ; /* 0x0000000000037306 */
/* 0x000e220000201400 */
/*00b0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00c0*/ BSSY B0, 0x1e0 ; /* 0x0000011000007945 */
/* 0x000fec0003800000 */
/*00d0*/ I2F R2, R5 ; /* 0x0000000500027306 */
/* 0x000e620000201400 */
/*00e0*/ FADD R3, R3, -c[0x0][0x174] ; /* 0x80005d0003037621 */
/* 0x001fc80000000000 */
/*00f0*/ FMUL R3, R3, R3 ; /* 0x0000000303037220 */
/* 0x000fe40000400000 */
/*0100*/ FADD R2, R2, -c[0x0][0x170] ; /* 0x80005c0002027621 */
/* 0x002fc80000000000 */
/*0110*/ FFMA R3, R2, R2, R3 ; /* 0x0000000202037223 */
/* 0x000fc80000000003 */
/*0120*/ MUFU.RSQ R2, R3 ; /* 0x0000000300027308 */
/* 0x0000620000001400 */
/*0130*/ IADD3 R4, R3, -0xd000000, RZ ; /* 0xf300000003047810 */
/* 0x000fc80007ffe0ff */
/*0140*/ ISETP.GT.U32.AND P0, PT, R4, 0x727fffff, PT ; /* 0x727fffff0400780c */
/* 0x000fda0003f04070 */
/*0150*/ @!P0 BRA 0x190 ; /* 0x0000003000008947 */
/* 0x000fea0003800000 */
/*0160*/ MOV R8, 0x180 ; /* 0x0000018000087802 */
/* 0x003fe40000000f00 */
/*0170*/ CALL.REL.NOINC 0x230 ; /* 0x000000b000007944 */
/* 0x000fea0003c00000 */
/*0180*/ BRA 0x1d0 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*0190*/ FMUL.FTZ R4, R3, R2 ; /* 0x0000000203047220 */
/* 0x003fe40000410000 */
/*01a0*/ FMUL.FTZ R2, R2, 0.5 ; /* 0x3f00000002027820 */
/* 0x000fe40000410000 */
/*01b0*/ FFMA R3, -R4, R4, R3 ; /* 0x0000000404037223 */
/* 0x000fc80000000103 */
/*01c0*/ FFMA R7, R3, R2, R4 ; /* 0x0000000203077223 */
/* 0x000fe40000000004 */
/*01d0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*01e0*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*01f0*/ IMAD R2, R0, c[0x0][0x168], R5 ; /* 0x00005a0000027a24 */
/* 0x000fd200078e0205 */
/*0200*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0203 */
/*0210*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x000fe2000c101904 */
/*0220*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0230*/ LOP3.LUT P0, RZ, R3, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff03ff7812 */
/* 0x000fda000780c0ff */
/*0240*/ @!P0 MOV R2, R3 ; /* 0x0000000300028202 */
/* 0x000fe20000000f00 */
/*0250*/ @!P0 BRA 0x360 ; /* 0x0000010000008947 */
/* 0x000fea0003800000 */
/*0260*/ FSETP.GEU.FTZ.AND P0, PT, R3, RZ, PT ; /* 0x000000ff0300720b */
/* 0x000fda0003f1e000 */
/*0270*/ @!P0 MOV R2, 0x7fffffff ; /* 0x7fffffff00028802 */
/* 0x000fe20000000f00 */
/*0280*/ @!P0 BRA 0x360 ; /* 0x000000d000008947 */
/* 0x000fea0003800000 */
/*0290*/ FSETP.GTU.FTZ.AND P0, PT, |R3|, +INF , PT ; /* 0x7f8000000300780b */
/* 0x000fda0003f1c200 */
/*02a0*/ @P0 FADD.FTZ R2, R3, 1 ; /* 0x3f80000003020421 */
/* 0x000fe20000010000 */
/*02b0*/ @P0 BRA 0x360 ; /* 0x000000a000000947 */
/* 0x000fea0003800000 */
/*02c0*/ FSETP.NEU.FTZ.AND P0, PT, |R3|, +INF , PT ; /* 0x7f8000000300780b */
/* 0x000fda0003f1d200 */
/*02d0*/ @P0 FFMA R4, R3, 1.84467440737095516160e+19, RZ ; /* 0x5f80000003040823 */
/* 0x000fc800000000ff */
/*02e0*/ @P0 MUFU.RSQ R7, R4 ; /* 0x0000000400070308 */
/* 0x000e240000001400 */
/*02f0*/ @P0 FMUL.FTZ R9, R4, R7 ; /* 0x0000000704090220 */
/* 0x001fe40000410000 */
/*0300*/ @P0 FMUL.FTZ R7, R7, 0.5 ; /* 0x3f00000007070820 */
/* 0x000fe40000410000 */
/*0310*/ @P0 FADD.FTZ R2, -R9, -RZ ; /* 0x800000ff09020221 */
/* 0x000fc80000010100 */
/*0320*/ @P0 FFMA R6, R9, R2, R4 ; /* 0x0000000209060223 */
/* 0x000fe20000000004 */
/*0330*/ @!P0 MOV R2, R3 ; /* 0x0000000300028202 */
/* 0x000fc60000000f00 */
/*0340*/ @P0 FFMA R6, R6, R7, R9 ; /* 0x0000000706060223 */
/* 0x000fc80000000009 */
/*0350*/ @P0 FMUL.FTZ R2, R6, 2.3283064365386962891e-10 ; /* 0x2f80000006020820 */
/* 0x000fc80000410000 */
/*0360*/ HFMA2.MMA R3, -RZ, RZ, 0, 0 ; /* 0x00000000ff037435 */
/* 0x000fe200000001ff */
/*0370*/ MOV R7, R2 ; /* 0x0000000200077202 */
/* 0x000fe40000000f00 */
/*0380*/ MOV R2, R8 ; /* 0x0000000800027202 */
/* 0x000fc80000000f00 */
/*0390*/ RET.REL.NODEC R2 0x0 ; /* 0xfffffc6002007950 */
/* 0x000fea0003c3ffff */
/*03a0*/ BRA 0x3a0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*03b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0400*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0410*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0420*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0430*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0440*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0450*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0460*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0470*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #define W 500
#define H 500
#define TX 32 // number of threads per block along x-axis
#define TY 32 // number of threads per block along y-axis
__global__
void distanceKernel(float *d_out, int w, int h, float2 pos) {
const int c = blockIdx.x * blockDim.x + threadIdx.x;
const int r = blockIdx.y * blockDim.y + threadIdx.y;
const int i = r * w + c;
if ((c >= w) || (r >= h)) return;
// compute the distance and set d_out[i]
d_out[i] = sqrtf((c - pos.x) * (c - pos.x) + (r - pos.y) * (r - pos.y));
}
int main() {
float *out = (float*)calloc(W*H, sizeof(float));
float *d_out; // pointer for device array
cudaMalloc(&d_out, W * H * sizeof(float));
const float2 pos = {0.0f, 0.0f}; // set reference position
const dim3 blockSize(TX, TY);
const int bx = (W + TX - 1)/TX;
const int by = (W + TY - 1)/TY;
const dim3 gridSize = dim3(bx, by);
distanceKernel<<<gridSize, blockSize>>>(d_out, W, H, pos);
// copy the results to host
cudaMemcpy(out, d_out, W*H*sizeof(float), cudaMemcpyDeviceToHost);
cudaFree(d_out);
free(out);
return 0;
} | .file "tmpxft_001369b2_00000000-6_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z43__device_stub__Z14distanceKernelPfii6float2PfiiR6float2
.type _Z43__device_stub__Z14distanceKernelPfii6float2PfiiR6float2, @function
_Z43__device_stub__Z14distanceKernelPfii6float2PfiiR6float2:
.LFB2052:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movq %rcx, 104(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 152
pushq 24(%rsp)
.cfi_def_cfa_offset 160
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z14distanceKernelPfii6float2(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2052:
.size _Z43__device_stub__Z14distanceKernelPfii6float2PfiiR6float2, .-_Z43__device_stub__Z14distanceKernelPfii6float2PfiiR6float2
.globl _Z14distanceKernelPfii6float2
.type _Z14distanceKernelPfii6float2, @function
_Z14distanceKernelPfii6float2:
.LFB2053:
.cfi_startproc
endbr64
subq $24, %rsp
.cfi_def_cfa_offset 32
movq %xmm0, 8(%rsp)
leaq 8(%rsp), %rcx
call _Z43__device_stub__Z14distanceKernelPfii6float2PfiiR6float2
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _Z14distanceKernelPfii6float2, .-_Z14distanceKernelPfii6float2
.globl main
.type main, @function
main:
.LFB2027:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $48, %rsp
.cfi_def_cfa_offset 64
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movl $4, %esi
movl $250000, %edi
call calloc@PLT
movq %rax, %rbx
movq %rsp, %rdi
movl $1000000, %esi
call cudaMalloc@PLT
movl $32, 16(%rsp)
movl $32, 20(%rsp)
movl $16, 28(%rsp)
movl $16, 32(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 16(%rsp), %rdx
movl $1, %ecx
movq 28(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L15
.L12:
movl $2, %ecx
movl $1000000, %edx
movq (%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movq (%rsp), %rdi
call cudaFree@PLT
movq %rbx, %rdi
call free@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L16
movl $0, %eax
addq $48, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
movl $0x00000000, 8(%rsp)
movl $0x00000000, 12(%rsp)
leaq 8(%rsp), %rcx
movl $500, %edx
movl $500, %esi
movq (%rsp), %rdi
call _Z43__device_stub__Z14distanceKernelPfii6float2PfiiR6float2
jmp .L12
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2027:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "_Z14distanceKernelPfii6float2"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z14distanceKernelPfii6float2(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #define W 500
#define H 500
#define TX 32 // number of threads per block along x-axis
#define TY 32 // number of threads per block along y-axis
__global__
void distanceKernel(float *d_out, int w, int h, float2 pos) {
const int c = blockIdx.x * blockDim.x + threadIdx.x;
const int r = blockIdx.y * blockDim.y + threadIdx.y;
const int i = r * w + c;
if ((c >= w) || (r >= h)) return;
// compute the distance and set d_out[i]
d_out[i] = sqrtf((c - pos.x) * (c - pos.x) + (r - pos.y) * (r - pos.y));
}
int main() {
float *out = (float*)calloc(W*H, sizeof(float));
float *d_out; // pointer for device array
cudaMalloc(&d_out, W * H * sizeof(float));
const float2 pos = {0.0f, 0.0f}; // set reference position
const dim3 blockSize(TX, TY);
const int bx = (W + TX - 1)/TX;
const int by = (W + TY - 1)/TY;
const dim3 gridSize = dim3(bx, by);
distanceKernel<<<gridSize, blockSize>>>(d_out, W, H, pos);
// copy the results to host
cudaMemcpy(out, d_out, W*H*sizeof(float), cudaMemcpyDeviceToHost);
cudaFree(d_out);
free(out);
return 0;
} | #include <hip/hip_runtime.h>
#define W 500
#define H 500
#define TX 32 // number of threads per block along x-axis
#define TY 32 // number of threads per block along y-axis
__global__
void distanceKernel(float *d_out, int w, int h, float2 pos) {
const int c = blockIdx.x * blockDim.x + threadIdx.x;
const int r = blockIdx.y * blockDim.y + threadIdx.y;
const int i = r * w + c;
if ((c >= w) || (r >= h)) return;
// compute the distance and set d_out[i]
d_out[i] = sqrtf((c - pos.x) * (c - pos.x) + (r - pos.y) * (r - pos.y));
}
int main() {
float *out = (float*)calloc(W*H, sizeof(float));
float *d_out; // pointer for device array
hipMalloc(&d_out, W * H * sizeof(float));
const float2 pos = {0.0f, 0.0f}; // set reference position
const dim3 blockSize(TX, TY);
const int bx = (W + TX - 1)/TX;
const int by = (W + TY - 1)/TY;
const dim3 gridSize = dim3(bx, by);
distanceKernel<<<gridSize, blockSize>>>(d_out, W, H, pos);
// copy the results to host
hipMemcpy(out, d_out, W*H*sizeof(float), hipMemcpyDeviceToHost);
hipFree(d_out);
free(out);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#define W 500
#define H 500
#define TX 32 // number of threads per block along x-axis
#define TY 32 // number of threads per block along y-axis
__global__
void distanceKernel(float *d_out, int w, int h, float2 pos) {
const int c = blockIdx.x * blockDim.x + threadIdx.x;
const int r = blockIdx.y * blockDim.y + threadIdx.y;
const int i = r * w + c;
if ((c >= w) || (r >= h)) return;
// compute the distance and set d_out[i]
d_out[i] = sqrtf((c - pos.x) * (c - pos.x) + (r - pos.y) * (r - pos.y));
}
int main() {
float *out = (float*)calloc(W*H, sizeof(float));
float *d_out; // pointer for device array
hipMalloc(&d_out, W * H * sizeof(float));
const float2 pos = {0.0f, 0.0f}; // set reference position
const dim3 blockSize(TX, TY);
const int bx = (W + TX - 1)/TX;
const int by = (W + TY - 1)/TY;
const dim3 gridSize = dim3(bx, by);
distanceKernel<<<gridSize, blockSize>>>(d_out, W, H, pos);
// copy the results to host
hipMemcpy(out, d_out, W*H*sizeof(float), hipMemcpyDeviceToHost);
hipFree(d_out);
free(out);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z14distanceKernelPfii15HIP_vector_typeIfLj2EE
.globl _Z14distanceKernelPfii15HIP_vector_typeIfLj2EE
.p2align 8
.type _Z14distanceKernelPfii15HIP_vector_typeIfLj2EE,@function
_Z14distanceKernelPfii15HIP_vector_typeIfLj2EE:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b64 s[4:5], s[0:1], 0x8
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_lshr_b32 s2, s2, 16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[0:1], null, s14, s3, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s2, v[3:4]
v_cmp_gt_i32_e32 vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i32_e64 s2, s5, v1
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_2
s_load_b64 s[2:3], s[0:1], 0x10
v_cvt_f32_i32_e32 v2, v0
v_cvt_f32_i32_e32 v3, v1
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_subrev_f32 v2, s2, v2 :: v_dual_subrev_f32 v3, s3, v3
v_mul_f32_e32 v2, v2, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v2, v3, v3
v_mul_f32_e32 v3, 0x4f800000, v2
v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v4, v2, v3, vcc_lo
v_sqrt_f32_e32 v2, v4
s_waitcnt_depctr 0xfff
v_add_nc_u32_e32 v3, -1, v2
v_add_nc_u32_e32 v5, 1, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v6, -v3, v2, v4
v_fma_f32 v7, -v5, v2, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_ge_f32_e64 s2, 0, v6
v_cndmask_b32_e64 v6, v2, v3, s2
s_load_b64 s[2:3], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cmp_lt_f32_e64 s0, 0, v7
v_mad_u64_u32 v[2:3], null, v1, s4, v[0:1]
v_cndmask_b32_e64 v0, v6, v5, s0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v3, 31, v2
v_mul_f32_e32 v1, 0x37800000, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cndmask_b32_e32 v5, v0, v1, vcc_lo
v_lshlrev_b64 v[0:1], 2, v[2:3]
v_cmp_class_f32_e64 vcc_lo, v4, 0x260
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_cndmask_b32_e32 v2, v5, v4, vcc_lo
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z14distanceKernelPfii15HIP_vector_typeIfLj2EE
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z14distanceKernelPfii15HIP_vector_typeIfLj2EE, .Lfunc_end0-_Z14distanceKernelPfii15HIP_vector_typeIfLj2EE
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 8
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z14distanceKernelPfii15HIP_vector_typeIfLj2EE
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z14distanceKernelPfii15HIP_vector_typeIfLj2EE.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#define W 500
#define H 500
#define TX 32 // number of threads per block along x-axis
#define TY 32 // number of threads per block along y-axis
__global__
void distanceKernel(float *d_out, int w, int h, float2 pos) {
const int c = blockIdx.x * blockDim.x + threadIdx.x;
const int r = blockIdx.y * blockDim.y + threadIdx.y;
const int i = r * w + c;
if ((c >= w) || (r >= h)) return;
// compute the distance and set d_out[i]
d_out[i] = sqrtf((c - pos.x) * (c - pos.x) + (r - pos.y) * (r - pos.y));
}
int main() {
float *out = (float*)calloc(W*H, sizeof(float));
float *d_out; // pointer for device array
hipMalloc(&d_out, W * H * sizeof(float));
const float2 pos = {0.0f, 0.0f}; // set reference position
const dim3 blockSize(TX, TY);
const int bx = (W + TX - 1)/TX;
const int by = (W + TY - 1)/TY;
const dim3 gridSize = dim3(bx, by);
distanceKernel<<<gridSize, blockSize>>>(d_out, W, H, pos);
// copy the results to host
hipMemcpy(out, d_out, W*H*sizeof(float), hipMemcpyDeviceToHost);
hipFree(d_out);
free(out);
return 0;
} | .text
.file "kernel.hip"
.globl _Z29__device_stub__distanceKernelPfii15HIP_vector_typeIfLj2EE # -- Begin function _Z29__device_stub__distanceKernelPfii15HIP_vector_typeIfLj2EE
.p2align 4, 0x90
.type _Z29__device_stub__distanceKernelPfii15HIP_vector_typeIfLj2EE,@function
_Z29__device_stub__distanceKernelPfii15HIP_vector_typeIfLj2EE: # @_Z29__device_stub__distanceKernelPfii15HIP_vector_typeIfLj2EE
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movsd %xmm0, 72(%rsp)
movq %rdi, 64(%rsp)
movl %esi, 12(%rsp)
movl %edx, 8(%rsp)
leaq 64(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 8(%rsp), %rax
movq %rax, 96(%rsp)
leaq 72(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z14distanceKernelPfii15HIP_vector_typeIfLj2EE, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z29__device_stub__distanceKernelPfii15HIP_vector_typeIfLj2EE, .Lfunc_end0-_Z29__device_stub__distanceKernelPfii15HIP_vector_typeIfLj2EE
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $112, %rsp
.cfi_def_cfa_offset 128
.cfi_offset %rbx, -16
movl $250000, %edi # imm = 0x3D090
movl $4, %esi
callq calloc
movq %rax, %rbx
movq %rsp, %rdi
movl $1000000, %esi # imm = 0xF4240
callq hipMalloc
movabsq $68719476752, %rdi # imm = 0x1000000010
movabsq $137438953504, %rdx # imm = 0x2000000020
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq (%rsp), %rax
movq $0, 72(%rsp)
movq %rax, 64(%rsp)
movl $500, 12(%rsp) # imm = 0x1F4
movl $500, 8(%rsp) # imm = 0x1F4
leaq 64(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 8(%rsp), %rax
movq %rax, 96(%rsp)
leaq 72(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z14distanceKernelPfii15HIP_vector_typeIfLj2EE, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
movq (%rsp), %rsi
movl $1000000, %edx # imm = 0xF4240
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
movq (%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq free
xorl %eax, %eax
addq $112, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14distanceKernelPfii15HIP_vector_typeIfLj2EE, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z14distanceKernelPfii15HIP_vector_typeIfLj2EE,@object # @_Z14distanceKernelPfii15HIP_vector_typeIfLj2EE
.section .rodata,"a",@progbits
.globl _Z14distanceKernelPfii15HIP_vector_typeIfLj2EE
.p2align 3, 0x0
_Z14distanceKernelPfii15HIP_vector_typeIfLj2EE:
.quad _Z29__device_stub__distanceKernelPfii15HIP_vector_typeIfLj2EE
.size _Z14distanceKernelPfii15HIP_vector_typeIfLj2EE, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z14distanceKernelPfii15HIP_vector_typeIfLj2EE"
.size .L__unnamed_1, 47
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z29__device_stub__distanceKernelPfii15HIP_vector_typeIfLj2EE
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z14distanceKernelPfii15HIP_vector_typeIfLj2EE
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z14distanceKernelPfii6float2
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e280000002600 */
/*0020*/ S2R R3, SR_TID.Y ; /* 0x0000000000037919 */
/* 0x000e280000002200 */
/*0030*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x000e680000002500 */
/*0040*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e620000002100 */
/*0050*/ IMAD R0, R0, c[0x0][0x4], R3 ; /* 0x0000010000007a24 */
/* 0x001fca00078e0203 */
/*0060*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x16c], PT ; /* 0x00005b0000007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R5, R5, c[0x0][0x0], R2 ; /* 0x0000000005057a24 */
/* 0x002fca00078e0202 */
/*0080*/ ISETP.GE.OR P0, PT, R5, c[0x0][0x168], P0 ; /* 0x00005a0005007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ I2F R3, R0 ; /* 0x0000000000037306 */
/* 0x000e220000201400 */
/*00b0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00c0*/ BSSY B0, 0x1e0 ; /* 0x0000011000007945 */
/* 0x000fec0003800000 */
/*00d0*/ I2F R2, R5 ; /* 0x0000000500027306 */
/* 0x000e620000201400 */
/*00e0*/ FADD R3, R3, -c[0x0][0x174] ; /* 0x80005d0003037621 */
/* 0x001fc80000000000 */
/*00f0*/ FMUL R3, R3, R3 ; /* 0x0000000303037220 */
/* 0x000fe40000400000 */
/*0100*/ FADD R2, R2, -c[0x0][0x170] ; /* 0x80005c0002027621 */
/* 0x002fc80000000000 */
/*0110*/ FFMA R3, R2, R2, R3 ; /* 0x0000000202037223 */
/* 0x000fc80000000003 */
/*0120*/ MUFU.RSQ R2, R3 ; /* 0x0000000300027308 */
/* 0x0000620000001400 */
/*0130*/ IADD3 R4, R3, -0xd000000, RZ ; /* 0xf300000003047810 */
/* 0x000fc80007ffe0ff */
/*0140*/ ISETP.GT.U32.AND P0, PT, R4, 0x727fffff, PT ; /* 0x727fffff0400780c */
/* 0x000fda0003f04070 */
/*0150*/ @!P0 BRA 0x190 ; /* 0x0000003000008947 */
/* 0x000fea0003800000 */
/*0160*/ MOV R8, 0x180 ; /* 0x0000018000087802 */
/* 0x003fe40000000f00 */
/*0170*/ CALL.REL.NOINC 0x230 ; /* 0x000000b000007944 */
/* 0x000fea0003c00000 */
/*0180*/ BRA 0x1d0 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*0190*/ FMUL.FTZ R4, R3, R2 ; /* 0x0000000203047220 */
/* 0x003fe40000410000 */
/*01a0*/ FMUL.FTZ R2, R2, 0.5 ; /* 0x3f00000002027820 */
/* 0x000fe40000410000 */
/*01b0*/ FFMA R3, -R4, R4, R3 ; /* 0x0000000404037223 */
/* 0x000fc80000000103 */
/*01c0*/ FFMA R7, R3, R2, R4 ; /* 0x0000000203077223 */
/* 0x000fe40000000004 */
/*01d0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*01e0*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*01f0*/ IMAD R2, R0, c[0x0][0x168], R5 ; /* 0x00005a0000027a24 */
/* 0x000fd200078e0205 */
/*0200*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0203 */
/*0210*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x000fe2000c101904 */
/*0220*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0230*/ LOP3.LUT P0, RZ, R3, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff03ff7812 */
/* 0x000fda000780c0ff */
/*0240*/ @!P0 MOV R2, R3 ; /* 0x0000000300028202 */
/* 0x000fe20000000f00 */
/*0250*/ @!P0 BRA 0x360 ; /* 0x0000010000008947 */
/* 0x000fea0003800000 */
/*0260*/ FSETP.GEU.FTZ.AND P0, PT, R3, RZ, PT ; /* 0x000000ff0300720b */
/* 0x000fda0003f1e000 */
/*0270*/ @!P0 MOV R2, 0x7fffffff ; /* 0x7fffffff00028802 */
/* 0x000fe20000000f00 */
/*0280*/ @!P0 BRA 0x360 ; /* 0x000000d000008947 */
/* 0x000fea0003800000 */
/*0290*/ FSETP.GTU.FTZ.AND P0, PT, |R3|, +INF , PT ; /* 0x7f8000000300780b */
/* 0x000fda0003f1c200 */
/*02a0*/ @P0 FADD.FTZ R2, R3, 1 ; /* 0x3f80000003020421 */
/* 0x000fe20000010000 */
/*02b0*/ @P0 BRA 0x360 ; /* 0x000000a000000947 */
/* 0x000fea0003800000 */
/*02c0*/ FSETP.NEU.FTZ.AND P0, PT, |R3|, +INF , PT ; /* 0x7f8000000300780b */
/* 0x000fda0003f1d200 */
/*02d0*/ @P0 FFMA R4, R3, 1.84467440737095516160e+19, RZ ; /* 0x5f80000003040823 */
/* 0x000fc800000000ff */
/*02e0*/ @P0 MUFU.RSQ R7, R4 ; /* 0x0000000400070308 */
/* 0x000e240000001400 */
/*02f0*/ @P0 FMUL.FTZ R9, R4, R7 ; /* 0x0000000704090220 */
/* 0x001fe40000410000 */
/*0300*/ @P0 FMUL.FTZ R7, R7, 0.5 ; /* 0x3f00000007070820 */
/* 0x000fe40000410000 */
/*0310*/ @P0 FADD.FTZ R2, -R9, -RZ ; /* 0x800000ff09020221 */
/* 0x000fc80000010100 */
/*0320*/ @P0 FFMA R6, R9, R2, R4 ; /* 0x0000000209060223 */
/* 0x000fe20000000004 */
/*0330*/ @!P0 MOV R2, R3 ; /* 0x0000000300028202 */
/* 0x000fc60000000f00 */
/*0340*/ @P0 FFMA R6, R6, R7, R9 ; /* 0x0000000706060223 */
/* 0x000fc80000000009 */
/*0350*/ @P0 FMUL.FTZ R2, R6, 2.3283064365386962891e-10 ; /* 0x2f80000006020820 */
/* 0x000fc80000410000 */
/*0360*/ HFMA2.MMA R3, -RZ, RZ, 0, 0 ; /* 0x00000000ff037435 */
/* 0x000fe200000001ff */
/*0370*/ MOV R7, R2 ; /* 0x0000000200077202 */
/* 0x000fe40000000f00 */
/*0380*/ MOV R2, R8 ; /* 0x0000000800027202 */
/* 0x000fc80000000f00 */
/*0390*/ RET.REL.NODEC R2 0x0 ; /* 0xfffffc6002007950 */
/* 0x000fea0003c3ffff */
/*03a0*/ BRA 0x3a0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*03b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0400*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0410*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0420*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0430*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0440*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0450*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0460*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0470*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z14distanceKernelPfii15HIP_vector_typeIfLj2EE
.globl _Z14distanceKernelPfii15HIP_vector_typeIfLj2EE
.p2align 8
.type _Z14distanceKernelPfii15HIP_vector_typeIfLj2EE,@function
_Z14distanceKernelPfii15HIP_vector_typeIfLj2EE:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b64 s[4:5], s[0:1], 0x8
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_lshr_b32 s2, s2, 16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[0:1], null, s14, s3, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s2, v[3:4]
v_cmp_gt_i32_e32 vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i32_e64 s2, s5, v1
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_2
s_load_b64 s[2:3], s[0:1], 0x10
v_cvt_f32_i32_e32 v2, v0
v_cvt_f32_i32_e32 v3, v1
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_subrev_f32 v2, s2, v2 :: v_dual_subrev_f32 v3, s3, v3
v_mul_f32_e32 v2, v2, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v2, v3, v3
v_mul_f32_e32 v3, 0x4f800000, v2
v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v4, v2, v3, vcc_lo
v_sqrt_f32_e32 v2, v4
s_waitcnt_depctr 0xfff
v_add_nc_u32_e32 v3, -1, v2
v_add_nc_u32_e32 v5, 1, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v6, -v3, v2, v4
v_fma_f32 v7, -v5, v2, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_ge_f32_e64 s2, 0, v6
v_cndmask_b32_e64 v6, v2, v3, s2
s_load_b64 s[2:3], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cmp_lt_f32_e64 s0, 0, v7
v_mad_u64_u32 v[2:3], null, v1, s4, v[0:1]
v_cndmask_b32_e64 v0, v6, v5, s0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v3, 31, v2
v_mul_f32_e32 v1, 0x37800000, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cndmask_b32_e32 v5, v0, v1, vcc_lo
v_lshlrev_b64 v[0:1], 2, v[2:3]
v_cmp_class_f32_e64 vcc_lo, v4, 0x260
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_cndmask_b32_e32 v2, v5, v4, vcc_lo
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z14distanceKernelPfii15HIP_vector_typeIfLj2EE
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z14distanceKernelPfii15HIP_vector_typeIfLj2EE, .Lfunc_end0-_Z14distanceKernelPfii15HIP_vector_typeIfLj2EE
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 8
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z14distanceKernelPfii15HIP_vector_typeIfLj2EE
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z14distanceKernelPfii15HIP_vector_typeIfLj2EE.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001369b2_00000000-6_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z43__device_stub__Z14distanceKernelPfii6float2PfiiR6float2
.type _Z43__device_stub__Z14distanceKernelPfii6float2PfiiR6float2, @function
_Z43__device_stub__Z14distanceKernelPfii6float2PfiiR6float2:
.LFB2052:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movq %rcx, 104(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 152
pushq 24(%rsp)
.cfi_def_cfa_offset 160
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z14distanceKernelPfii6float2(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2052:
.size _Z43__device_stub__Z14distanceKernelPfii6float2PfiiR6float2, .-_Z43__device_stub__Z14distanceKernelPfii6float2PfiiR6float2
.globl _Z14distanceKernelPfii6float2
.type _Z14distanceKernelPfii6float2, @function
_Z14distanceKernelPfii6float2:
.LFB2053:
.cfi_startproc
endbr64
subq $24, %rsp
.cfi_def_cfa_offset 32
movq %xmm0, 8(%rsp)
leaq 8(%rsp), %rcx
call _Z43__device_stub__Z14distanceKernelPfii6float2PfiiR6float2
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _Z14distanceKernelPfii6float2, .-_Z14distanceKernelPfii6float2
.globl main
.type main, @function
main:
.LFB2027:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $48, %rsp
.cfi_def_cfa_offset 64
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movl $4, %esi
movl $250000, %edi
call calloc@PLT
movq %rax, %rbx
movq %rsp, %rdi
movl $1000000, %esi
call cudaMalloc@PLT
movl $32, 16(%rsp)
movl $32, 20(%rsp)
movl $16, 28(%rsp)
movl $16, 32(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 16(%rsp), %rdx
movl $1, %ecx
movq 28(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L15
.L12:
movl $2, %ecx
movl $1000000, %edx
movq (%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movq (%rsp), %rdi
call cudaFree@PLT
movq %rbx, %rdi
call free@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L16
movl $0, %eax
addq $48, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
movl $0x00000000, 8(%rsp)
movl $0x00000000, 12(%rsp)
leaq 8(%rsp), %rcx
movl $500, %edx
movl $500, %esi
movq (%rsp), %rdi
call _Z43__device_stub__Z14distanceKernelPfii6float2PfiiR6float2
jmp .L12
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2027:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "_Z14distanceKernelPfii6float2"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z14distanceKernelPfii6float2(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "kernel.hip"
.globl _Z29__device_stub__distanceKernelPfii15HIP_vector_typeIfLj2EE # -- Begin function _Z29__device_stub__distanceKernelPfii15HIP_vector_typeIfLj2EE
.p2align 4, 0x90
.type _Z29__device_stub__distanceKernelPfii15HIP_vector_typeIfLj2EE,@function
_Z29__device_stub__distanceKernelPfii15HIP_vector_typeIfLj2EE: # @_Z29__device_stub__distanceKernelPfii15HIP_vector_typeIfLj2EE
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movsd %xmm0, 72(%rsp)
movq %rdi, 64(%rsp)
movl %esi, 12(%rsp)
movl %edx, 8(%rsp)
leaq 64(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 8(%rsp), %rax
movq %rax, 96(%rsp)
leaq 72(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z14distanceKernelPfii15HIP_vector_typeIfLj2EE, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z29__device_stub__distanceKernelPfii15HIP_vector_typeIfLj2EE, .Lfunc_end0-_Z29__device_stub__distanceKernelPfii15HIP_vector_typeIfLj2EE
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $112, %rsp
.cfi_def_cfa_offset 128
.cfi_offset %rbx, -16
movl $250000, %edi # imm = 0x3D090
movl $4, %esi
callq calloc
movq %rax, %rbx
movq %rsp, %rdi
movl $1000000, %esi # imm = 0xF4240
callq hipMalloc
movabsq $68719476752, %rdi # imm = 0x1000000010
movabsq $137438953504, %rdx # imm = 0x2000000020
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq (%rsp), %rax
movq $0, 72(%rsp)
movq %rax, 64(%rsp)
movl $500, 12(%rsp) # imm = 0x1F4
movl $500, 8(%rsp) # imm = 0x1F4
leaq 64(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 8(%rsp), %rax
movq %rax, 96(%rsp)
leaq 72(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z14distanceKernelPfii15HIP_vector_typeIfLj2EE, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
movq (%rsp), %rsi
movl $1000000, %edx # imm = 0xF4240
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
movq (%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq free
xorl %eax, %eax
addq $112, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14distanceKernelPfii15HIP_vector_typeIfLj2EE, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z14distanceKernelPfii15HIP_vector_typeIfLj2EE,@object # @_Z14distanceKernelPfii15HIP_vector_typeIfLj2EE
.section .rodata,"a",@progbits
.globl _Z14distanceKernelPfii15HIP_vector_typeIfLj2EE
.p2align 3, 0x0
_Z14distanceKernelPfii15HIP_vector_typeIfLj2EE:
.quad _Z29__device_stub__distanceKernelPfii15HIP_vector_typeIfLj2EE
.size _Z14distanceKernelPfii15HIP_vector_typeIfLj2EE, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z14distanceKernelPfii15HIP_vector_typeIfLj2EE"
.size .L__unnamed_1, 47
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z29__device_stub__distanceKernelPfii15HIP_vector_typeIfLj2EE
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z14distanceKernelPfii15HIP_vector_typeIfLj2EE
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void FillOnes(float *vec, int size)
{
int idx = blockIdx.x * blockDim.x + threadIdx.x;
if (idx >= size)
return;
vec[idx] = 1.0f;
} | code for sm_80
Function : _Z8FillOnesPfi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R2, R2, c[0x0][0x0], R3 ; /* 0x0000000002027a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R2, c[0x0][0x168], PT ; /* 0x00005a0002007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0070*/ MOV R5, 0x3f800000 ; /* 0x3f80000000057802 */
/* 0x000fe20000000f00 */
/*0080*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd00000000a00 */
/*0090*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0203 */
/*00a0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*00b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00c0*/ BRA 0xc0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void FillOnes(float *vec, int size)
{
int idx = blockIdx.x * blockDim.x + threadIdx.x;
if (idx >= size)
return;
vec[idx] = 1.0f;
} | .file "tmpxft_00168917_00000000-6_FillOnes.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z28__device_stub__Z8FillOnesPfiPfi
.type _Z28__device_stub__Z8FillOnesPfiPfi, @function
_Z28__device_stub__Z8FillOnesPfiPfi:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z8FillOnesPfi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z28__device_stub__Z8FillOnesPfiPfi, .-_Z28__device_stub__Z8FillOnesPfiPfi
.globl _Z8FillOnesPfi
.type _Z8FillOnesPfi, @function
_Z8FillOnesPfi:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z28__device_stub__Z8FillOnesPfiPfi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z8FillOnesPfi, .-_Z8FillOnesPfi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z8FillOnesPfi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z8FillOnesPfi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void FillOnes(float *vec, int size)
{
int idx = blockIdx.x * blockDim.x + threadIdx.x;
if (idx >= size)
return;
vec[idx] = 1.0f;
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void FillOnes(float *vec, int size)
{
int idx = blockIdx.x * blockDim.x + threadIdx.x;
if (idx >= size)
return;
vec[idx] = 1.0f;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void FillOnes(float *vec, int size)
{
int idx = blockIdx.x * blockDim.x + threadIdx.x;
if (idx >= size)
return;
vec[idx] = 1.0f;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z8FillOnesPfi
.globl _Z8FillOnesPfi
.p2align 8
.type _Z8FillOnesPfi,@function
_Z8FillOnesPfi:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x1c
s_load_b32 s3, s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b64 s[0:1], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_mov_b32_e32 v2, 1.0
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8FillOnesPfi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z8FillOnesPfi, .Lfunc_end0-_Z8FillOnesPfi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8FillOnesPfi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z8FillOnesPfi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void FillOnes(float *vec, int size)
{
int idx = blockIdx.x * blockDim.x + threadIdx.x;
if (idx >= size)
return;
vec[idx] = 1.0f;
} | .text
.file "FillOnes.hip"
.globl _Z23__device_stub__FillOnesPfi # -- Begin function _Z23__device_stub__FillOnesPfi
.p2align 4, 0x90
.type _Z23__device_stub__FillOnesPfi,@function
_Z23__device_stub__FillOnesPfi: # @_Z23__device_stub__FillOnesPfi
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z8FillOnesPfi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z23__device_stub__FillOnesPfi, .Lfunc_end0-_Z23__device_stub__FillOnesPfi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8FillOnesPfi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z8FillOnesPfi,@object # @_Z8FillOnesPfi
.section .rodata,"a",@progbits
.globl _Z8FillOnesPfi
.p2align 3, 0x0
_Z8FillOnesPfi:
.quad _Z23__device_stub__FillOnesPfi
.size _Z8FillOnesPfi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z8FillOnesPfi"
.size .L__unnamed_1, 15
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__FillOnesPfi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8FillOnesPfi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z8FillOnesPfi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R2, R2, c[0x0][0x0], R3 ; /* 0x0000000002027a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R2, c[0x0][0x168], PT ; /* 0x00005a0002007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0070*/ MOV R5, 0x3f800000 ; /* 0x3f80000000057802 */
/* 0x000fe20000000f00 */
/*0080*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd00000000a00 */
/*0090*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0203 */
/*00a0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*00b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00c0*/ BRA 0xc0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z8FillOnesPfi
.globl _Z8FillOnesPfi
.p2align 8
.type _Z8FillOnesPfi,@function
_Z8FillOnesPfi:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x1c
s_load_b32 s3, s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b64 s[0:1], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_mov_b32_e32 v2, 1.0
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8FillOnesPfi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z8FillOnesPfi, .Lfunc_end0-_Z8FillOnesPfi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8FillOnesPfi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z8FillOnesPfi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00168917_00000000-6_FillOnes.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z28__device_stub__Z8FillOnesPfiPfi
.type _Z28__device_stub__Z8FillOnesPfiPfi, @function
_Z28__device_stub__Z8FillOnesPfiPfi:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z8FillOnesPfi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z28__device_stub__Z8FillOnesPfiPfi, .-_Z28__device_stub__Z8FillOnesPfiPfi
.globl _Z8FillOnesPfi
.type _Z8FillOnesPfi, @function
_Z8FillOnesPfi:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z28__device_stub__Z8FillOnesPfiPfi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z8FillOnesPfi, .-_Z8FillOnesPfi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z8FillOnesPfi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z8FillOnesPfi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "FillOnes.hip"
.globl _Z23__device_stub__FillOnesPfi # -- Begin function _Z23__device_stub__FillOnesPfi
.p2align 4, 0x90
.type _Z23__device_stub__FillOnesPfi,@function
_Z23__device_stub__FillOnesPfi: # @_Z23__device_stub__FillOnesPfi
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z8FillOnesPfi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z23__device_stub__FillOnesPfi, .Lfunc_end0-_Z23__device_stub__FillOnesPfi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8FillOnesPfi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z8FillOnesPfi,@object # @_Z8FillOnesPfi
.section .rodata,"a",@progbits
.globl _Z8FillOnesPfi
.p2align 3, 0x0
_Z8FillOnesPfi:
.quad _Z23__device_stub__FillOnesPfi
.size _Z8FillOnesPfi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z8FillOnesPfi"
.size .L__unnamed_1, 15
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__FillOnesPfi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8FillOnesPfi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <stdlib.h>
#include "cuda_runtime.h"
#include "device_launch_parameters.h"
__global__ void register_usage_test(int *results, int size) {
int gid = blockDim.x * blockIdx.x + threadIdx.x;
int x1 = 3456;
int x2 = 1768;
int x3 = 453;
int x4 = x1 + x2 + x3;
if (gid < size) {
results[gid] = x4;
}
};
int main() {
int size = 1 << 22;
int byte_size = sizeof(int) * size;
int *h_ref = (int *)malloc(byte_size);
int *d_results;
cudaMalloc((void **)&d_results, byte_size);
cudaMemset(d_results, 0, byte_size);
dim3 blocks(128);
dim3 grid((size + blocks.x - 1) / blocks.x);
printf("launching the kernel \n");
register_usage_test<<<grid, blocks>>>(d_results, size);
cudaDeviceSynchronize();
return 0;
} | code for sm_80
Function : _Z19register_usage_testPii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R2, R2, c[0x0][0x0], R3 ; /* 0x0000000002027a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R2, c[0x0][0x168], PT ; /* 0x00005a0002007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0070*/ MOV R5, 0x162d ; /* 0x0000162d00057802 */
/* 0x000fe20000000f00 */
/*0080*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd00000000a00 */
/*0090*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0203 */
/*00a0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*00b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00c0*/ BRA 0xc0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <stdlib.h>
#include "cuda_runtime.h"
#include "device_launch_parameters.h"
__global__ void register_usage_test(int *results, int size) {
int gid = blockDim.x * blockIdx.x + threadIdx.x;
int x1 = 3456;
int x2 = 1768;
int x3 = 453;
int x4 = x1 + x2 + x3;
if (gid < size) {
results[gid] = x4;
}
};
int main() {
int size = 1 << 22;
int byte_size = sizeof(int) * size;
int *h_ref = (int *)malloc(byte_size);
int *d_results;
cudaMalloc((void **)&d_results, byte_size);
cudaMemset(d_results, 0, byte_size);
dim3 blocks(128);
dim3 grid((size + blocks.x - 1) / blocks.x);
printf("launching the kernel \n");
register_usage_test<<<grid, blocks>>>(d_results, size);
cudaDeviceSynchronize();
return 0;
} | .file "tmpxft_00147b58_00000000-6_register_usage.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z40__device_stub__Z19register_usage_testPiiPii
.type _Z40__device_stub__Z19register_usage_testPiiPii, @function
_Z40__device_stub__Z19register_usage_testPiiPii:
.LFB2082:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z19register_usage_testPii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z40__device_stub__Z19register_usage_testPiiPii, .-_Z40__device_stub__Z19register_usage_testPiiPii
.globl _Z19register_usage_testPii
.type _Z19register_usage_testPii, @function
_Z19register_usage_testPii:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z40__device_stub__Z19register_usage_testPiiPii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z19register_usage_testPii, .-_Z19register_usage_testPii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "launching the kernel \n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $56, %rsp
.cfi_def_cfa_offset 64
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rdi
movl $16777216, %esi
call cudaMalloc@PLT
movl $16777216, %edx
movl $0, %esi
movq 8(%rsp), %rdi
call cudaMemset@PLT
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $32768, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $128, 16(%rsp)
movl 24(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 16(%rsp), %rdx
movq 28(%rsp), %rdi
movl 36(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L15
.L12:
call cudaDeviceSynchronize@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L16
movl $0, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
movl $4194304, %esi
movq 8(%rsp), %rdi
call _Z40__device_stub__Z19register_usage_testPiiPii
jmp .L12
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z19register_usage_testPii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z19register_usage_testPii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <stdlib.h>
#include "cuda_runtime.h"
#include "device_launch_parameters.h"
__global__ void register_usage_test(int *results, int size) {
int gid = blockDim.x * blockIdx.x + threadIdx.x;
int x1 = 3456;
int x2 = 1768;
int x3 = 453;
int x4 = x1 + x2 + x3;
if (gid < size) {
results[gid] = x4;
}
};
int main() {
int size = 1 << 22;
int byte_size = sizeof(int) * size;
int *h_ref = (int *)malloc(byte_size);
int *d_results;
cudaMalloc((void **)&d_results, byte_size);
cudaMemset(d_results, 0, byte_size);
dim3 blocks(128);
dim3 grid((size + blocks.x - 1) / blocks.x);
printf("launching the kernel \n");
register_usage_test<<<grid, blocks>>>(d_results, size);
cudaDeviceSynchronize();
return 0;
} | #include <stdio.h>
#include <stdlib.h>
#include "hip/hip_runtime.h"
__global__ void register_usage_test(int *results, int size) {
int gid = blockDim.x * blockIdx.x + threadIdx.x;
int x1 = 3456;
int x2 = 1768;
int x3 = 453;
int x4 = x1 + x2 + x3;
if (gid < size) {
results[gid] = x4;
}
};
int main() {
int size = 1 << 22;
int byte_size = sizeof(int) * size;
int *h_ref = (int *)malloc(byte_size);
int *d_results;
hipMalloc((void **)&d_results, byte_size);
hipMemset(d_results, 0, byte_size);
dim3 blocks(128);
dim3 grid((size + blocks.x - 1) / blocks.x);
printf("launching the kernel \n");
register_usage_test<<<grid, blocks>>>(d_results, size);
hipDeviceSynchronize();
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <stdio.h>
#include <stdlib.h>
#include "hip/hip_runtime.h"
__global__ void register_usage_test(int *results, int size) {
int gid = blockDim.x * blockIdx.x + threadIdx.x;
int x1 = 3456;
int x2 = 1768;
int x3 = 453;
int x4 = x1 + x2 + x3;
if (gid < size) {
results[gid] = x4;
}
};
int main() {
int size = 1 << 22;
int byte_size = sizeof(int) * size;
int *h_ref = (int *)malloc(byte_size);
int *d_results;
hipMalloc((void **)&d_results, byte_size);
hipMemset(d_results, 0, byte_size);
dim3 blocks(128);
dim3 grid((size + blocks.x - 1) / blocks.x);
printf("launching the kernel \n");
register_usage_test<<<grid, blocks>>>(d_results, size);
hipDeviceSynchronize();
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z19register_usage_testPii
.globl _Z19register_usage_testPii
.p2align 8
.type _Z19register_usage_testPii,@function
_Z19register_usage_testPii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x1c
s_load_b32 s3, s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b64 s[0:1], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_mov_b32_e32 v2, 0x162d
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z19register_usage_testPii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z19register_usage_testPii, .Lfunc_end0-_Z19register_usage_testPii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z19register_usage_testPii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z19register_usage_testPii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <stdio.h>
#include <stdlib.h>
#include "hip/hip_runtime.h"
__global__ void register_usage_test(int *results, int size) {
int gid = blockDim.x * blockIdx.x + threadIdx.x;
int x1 = 3456;
int x2 = 1768;
int x3 = 453;
int x4 = x1 + x2 + x3;
if (gid < size) {
results[gid] = x4;
}
};
int main() {
int size = 1 << 22;
int byte_size = sizeof(int) * size;
int *h_ref = (int *)malloc(byte_size);
int *d_results;
hipMalloc((void **)&d_results, byte_size);
hipMemset(d_results, 0, byte_size);
dim3 blocks(128);
dim3 grid((size + blocks.x - 1) / blocks.x);
printf("launching the kernel \n");
register_usage_test<<<grid, blocks>>>(d_results, size);
hipDeviceSynchronize();
return 0;
} | .text
.file "register_usage.hip"
.globl _Z34__device_stub__register_usage_testPii # -- Begin function _Z34__device_stub__register_usage_testPii
.p2align 4, 0x90
.type _Z34__device_stub__register_usage_testPii,@function
_Z34__device_stub__register_usage_testPii: # @_Z34__device_stub__register_usage_testPii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z19register_usage_testPii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z34__device_stub__register_usage_testPii, .Lfunc_end0-_Z34__device_stub__register_usage_testPii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
leaq 16(%rsp), %rdi
movl $16777216, %esi # imm = 0x1000000
callq hipMalloc
movq 16(%rsp), %rdi
movl $16777216, %edx # imm = 0x1000000
xorl %esi, %esi
callq hipMemset
movl $.Lstr, %edi
callq puts@PLT
movabsq $4294967424, %rdx # imm = 0x100000080
leaq 32640(%rdx), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq 16(%rsp), %rax
movq %rax, 72(%rsp)
movl $4194304, 12(%rsp) # imm = 0x400000
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z19register_usage_testPii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
callq hipDeviceSynchronize
xorl %eax, %eax
addq $104, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z19register_usage_testPii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z19register_usage_testPii,@object # @_Z19register_usage_testPii
.section .rodata,"a",@progbits
.globl _Z19register_usage_testPii
.p2align 3, 0x0
_Z19register_usage_testPii:
.quad _Z34__device_stub__register_usage_testPii
.size _Z19register_usage_testPii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z19register_usage_testPii"
.size .L__unnamed_1, 27
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "launching the kernel "
.size .Lstr, 22
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z34__device_stub__register_usage_testPii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z19register_usage_testPii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z19register_usage_testPii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R2, R2, c[0x0][0x0], R3 ; /* 0x0000000002027a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R2, c[0x0][0x168], PT ; /* 0x00005a0002007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0070*/ MOV R5, 0x162d ; /* 0x0000162d00057802 */
/* 0x000fe20000000f00 */
/*0080*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd00000000a00 */
/*0090*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0203 */
/*00a0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*00b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00c0*/ BRA 0xc0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z19register_usage_testPii
.globl _Z19register_usage_testPii
.p2align 8
.type _Z19register_usage_testPii,@function
_Z19register_usage_testPii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x1c
s_load_b32 s3, s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b64 s[0:1], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_mov_b32_e32 v2, 0x162d
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z19register_usage_testPii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z19register_usage_testPii, .Lfunc_end0-_Z19register_usage_testPii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z19register_usage_testPii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z19register_usage_testPii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00147b58_00000000-6_register_usage.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z40__device_stub__Z19register_usage_testPiiPii
.type _Z40__device_stub__Z19register_usage_testPiiPii, @function
_Z40__device_stub__Z19register_usage_testPiiPii:
.LFB2082:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z19register_usage_testPii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z40__device_stub__Z19register_usage_testPiiPii, .-_Z40__device_stub__Z19register_usage_testPiiPii
.globl _Z19register_usage_testPii
.type _Z19register_usage_testPii, @function
_Z19register_usage_testPii:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z40__device_stub__Z19register_usage_testPiiPii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z19register_usage_testPii, .-_Z19register_usage_testPii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "launching the kernel \n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $56, %rsp
.cfi_def_cfa_offset 64
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rdi
movl $16777216, %esi
call cudaMalloc@PLT
movl $16777216, %edx
movl $0, %esi
movq 8(%rsp), %rdi
call cudaMemset@PLT
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $32768, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $128, 16(%rsp)
movl 24(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 16(%rsp), %rdx
movq 28(%rsp), %rdi
movl 36(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L15
.L12:
call cudaDeviceSynchronize@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L16
movl $0, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
movl $4194304, %esi
movq 8(%rsp), %rdi
call _Z40__device_stub__Z19register_usage_testPiiPii
jmp .L12
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z19register_usage_testPii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z19register_usage_testPii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "register_usage.hip"
.globl _Z34__device_stub__register_usage_testPii # -- Begin function _Z34__device_stub__register_usage_testPii
.p2align 4, 0x90
.type _Z34__device_stub__register_usage_testPii,@function
_Z34__device_stub__register_usage_testPii: # @_Z34__device_stub__register_usage_testPii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z19register_usage_testPii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z34__device_stub__register_usage_testPii, .Lfunc_end0-_Z34__device_stub__register_usage_testPii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
leaq 16(%rsp), %rdi
movl $16777216, %esi # imm = 0x1000000
callq hipMalloc
movq 16(%rsp), %rdi
movl $16777216, %edx # imm = 0x1000000
xorl %esi, %esi
callq hipMemset
movl $.Lstr, %edi
callq puts@PLT
movabsq $4294967424, %rdx # imm = 0x100000080
leaq 32640(%rdx), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq 16(%rsp), %rax
movq %rax, 72(%rsp)
movl $4194304, 12(%rsp) # imm = 0x400000
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z19register_usage_testPii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
callq hipDeviceSynchronize
xorl %eax, %eax
addq $104, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z19register_usage_testPii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z19register_usage_testPii,@object # @_Z19register_usage_testPii
.section .rodata,"a",@progbits
.globl _Z19register_usage_testPii
.p2align 3, 0x0
_Z19register_usage_testPii:
.quad _Z34__device_stub__register_usage_testPii
.size _Z19register_usage_testPii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z19register_usage_testPii"
.size .L__unnamed_1, 27
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "launching the kernel "
.size .Lstr, 22
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z34__device_stub__register_usage_testPii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z19register_usage_testPii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <iostream>
using namespace std;
__global__ void kernel( int* b, int* t)
{
*b = gridDim.x; // Blocks in the grid
*t = blockDim.x; // Treads per block
}
int main()
{
int b;
int* d_b;
int t;
int* d_t;
// store in d_b the address of a memory
// location on the device
cudaMalloc( (void**)&d_b, sizeof(int));
cudaMalloc( (void**)&d_t, sizeof(int));
kernel<<<1,1>>>(d_b,d_t);
cudaMemcpy( &b, d_b, sizeof(int), cudaMemcpyDeviceToHost);
cudaMemcpy( &t, d_t, sizeof(int), cudaMemcpyDeviceToHost);
cudaFree(d_b);
cudaFree(d_t);
cout << "Num blocks : " << b << endl;
cout << "Num threads per block: " << t << endl;
return 0;
} | code for sm_80
Function : _Z6kernelPiS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ MOV R7, c[0x0][0xc] ; /* 0x0000030000077a02 */
/* 0x000fe20000000f00 */
/*0020*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff037624 */
/* 0x000fe200078e00ff */
/*0030*/ MOV R2, c[0x0][0x160] ; /* 0x0000580000027a02 */
/* 0x000fe20000000f00 */
/*0040*/ IMAD.MOV.U32 R9, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff097624 */
/* 0x000fe200078e00ff */
/*0050*/ MOV R4, c[0x0][0x168] ; /* 0x00005a0000047a02 */
/* 0x000fe20000000f00 */
/*0060*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff057624 */
/* 0x000fe200078e00ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0080*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x000fe8000c101904 */
/*0090*/ STG.E [R4.64], R9 ; /* 0x0000000904007986 */
/* 0x000fe2000c101904 */
/*00a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00b0*/ BRA 0xb0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <iostream>
using namespace std;
__global__ void kernel( int* b, int* t)
{
*b = gridDim.x; // Blocks in the grid
*t = blockDim.x; // Treads per block
}
int main()
{
int b;
int* d_b;
int t;
int* d_t;
// store in d_b the address of a memory
// location on the device
cudaMalloc( (void**)&d_b, sizeof(int));
cudaMalloc( (void**)&d_t, sizeof(int));
kernel<<<1,1>>>(d_b,d_t);
cudaMemcpy( &b, d_b, sizeof(int), cudaMemcpyDeviceToHost);
cudaMemcpy( &t, d_t, sizeof(int), cudaMemcpyDeviceToHost);
cudaFree(d_b);
cudaFree(d_t);
cout << "Num blocks : " << b << endl;
cout << "Num threads per block: " << t << endl;
return 0;
} | .file "tmpxft_00003e12_00000000-6_03_cuda.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z27__device_stub__Z6kernelPiS_PiS_
.type _Z27__device_stub__Z6kernelPiS_PiS_, @function
_Z27__device_stub__Z6kernelPiS_PiS_:
.LFB3694:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z6kernelPiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3694:
.size _Z27__device_stub__Z6kernelPiS_PiS_, .-_Z27__device_stub__Z6kernelPiS_PiS_
.globl _Z6kernelPiS_
.type _Z6kernelPiS_, @function
_Z6kernelPiS_:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z27__device_stub__Z6kernelPiS_PiS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _Z6kernelPiS_, .-_Z6kernelPiS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Num blocks : "
.LC1:
.string "Num threads per block: "
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $48, %rsp
.cfi_def_cfa_offset 64
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movq %rsp, %rdi
movl $4, %esi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L15
.L12:
leaq 16(%rsp), %rdi
movl $2, %ecx
movl $4, %edx
movq (%rsp), %rsi
call cudaMemcpy@PLT
leaq 28(%rsp), %rdi
movl $2, %ecx
movl $4, %edx
movq 8(%rsp), %rsi
call cudaMemcpy@PLT
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
leaq .LC0(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl 16(%rsp), %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq .LC1(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl 28(%rsp), %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L16
movl $0, %eax
addq $48, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z27__device_stub__Z6kernelPiS_PiS_
jmp .L12
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size main, .-main
.section .rodata.str1.1
.LC2:
.string "_Z6kernelPiS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z6kernelPiS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <iostream>
using namespace std;
__global__ void kernel( int* b, int* t)
{
*b = gridDim.x; // Blocks in the grid
*t = blockDim.x; // Treads per block
}
int main()
{
int b;
int* d_b;
int t;
int* d_t;
// store in d_b the address of a memory
// location on the device
cudaMalloc( (void**)&d_b, sizeof(int));
cudaMalloc( (void**)&d_t, sizeof(int));
kernel<<<1,1>>>(d_b,d_t);
cudaMemcpy( &b, d_b, sizeof(int), cudaMemcpyDeviceToHost);
cudaMemcpy( &t, d_t, sizeof(int), cudaMemcpyDeviceToHost);
cudaFree(d_b);
cudaFree(d_t);
cout << "Num blocks : " << b << endl;
cout << "Num threads per block: " << t << endl;
return 0;
} | #include <hip/hip_runtime.h>
#include <iostream>
using namespace std;
__global__ void kernel( int* b, int* t)
{
*b = gridDim.x; // Blocks in the grid
*t = blockDim.x; // Treads per block
}
int main()
{
int b;
int* d_b;
int t;
int* d_t;
// store in d_b the address of a memory
// location on the device
hipMalloc( (void**)&d_b, sizeof(int));
hipMalloc( (void**)&d_t, sizeof(int));
kernel<<<1,1>>>(d_b,d_t);
hipMemcpy( &b, d_b, sizeof(int), hipMemcpyDeviceToHost);
hipMemcpy( &t, d_t, sizeof(int), hipMemcpyDeviceToHost);
hipFree(d_b);
hipFree(d_t);
cout << "Num blocks : " << b << endl;
cout << "Num threads per block: " << t << endl;
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <iostream>
using namespace std;
__global__ void kernel( int* b, int* t)
{
*b = gridDim.x; // Blocks in the grid
*t = blockDim.x; // Treads per block
}
int main()
{
int b;
int* d_b;
int t;
int* d_t;
// store in d_b the address of a memory
// location on the device
hipMalloc( (void**)&d_b, sizeof(int));
hipMalloc( (void**)&d_t, sizeof(int));
kernel<<<1,1>>>(d_b,d_t);
hipMemcpy( &b, d_b, sizeof(int), hipMemcpyDeviceToHost);
hipMemcpy( &t, d_t, sizeof(int), hipMemcpyDeviceToHost);
hipFree(d_b);
hipFree(d_t);
cout << "Num blocks : " << b << endl;
cout << "Num threads per block: " << t << endl;
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6kernelPiS_
.globl _Z6kernelPiS_
.p2align 8
.type _Z6kernelPiS_,@function
_Z6kernelPiS_:
s_clause 0x2
s_load_b32 s4, s[0:1], 0x1c
s_load_b32 s5, s[0:1], 0x10
s_load_b128 s[0:3], s[0:1], 0x0
v_mov_b32_e32 v0, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v1, s5 :: v_dual_mov_b32 v2, s4
s_clause 0x1
global_store_b32 v0, v1, s[0:1]
global_store_b32 v0, v2, s[2:3]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6kernelPiS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 6
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6kernelPiS_, .Lfunc_end0-_Z6kernelPiS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6kernelPiS_
.private_segment_fixed_size: 0
.sgpr_count: 6
.sgpr_spill_count: 0
.symbol: _Z6kernelPiS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <iostream>
using namespace std;
__global__ void kernel( int* b, int* t)
{
*b = gridDim.x; // Blocks in the grid
*t = blockDim.x; // Treads per block
}
int main()
{
int b;
int* d_b;
int t;
int* d_t;
// store in d_b the address of a memory
// location on the device
hipMalloc( (void**)&d_b, sizeof(int));
hipMalloc( (void**)&d_t, sizeof(int));
kernel<<<1,1>>>(d_b,d_t);
hipMemcpy( &b, d_b, sizeof(int), hipMemcpyDeviceToHost);
hipMemcpy( &t, d_t, sizeof(int), hipMemcpyDeviceToHost);
hipFree(d_b);
hipFree(d_t);
cout << "Num blocks : " << b << endl;
cout << "Num threads per block: " << t << endl;
return 0;
} | .text
.file "03_cuda.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z21__device_stub__kernelPiS_ # -- Begin function _Z21__device_stub__kernelPiS_
.p2align 4, 0x90
.type _Z21__device_stub__kernelPiS_,@function
_Z21__device_stub__kernelPiS_: # @_Z21__device_stub__kernelPiS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z6kernelPiS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z21__device_stub__kernelPiS_, .Lfunc_end0-_Z21__device_stub__kernelPiS_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $104, %rsp
.cfi_def_cfa_offset 128
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
leaq 8(%rsp), %rdi
movl $4, %esi
callq hipMalloc
movq %rsp, %rdi
movl $4, %esi
callq hipMalloc
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq 8(%rsp), %rax
movq (%rsp), %rcx
movq %rax, 96(%rsp)
movq %rcx, 88(%rsp)
leaq 96(%rsp), %rax
movq %rax, 32(%rsp)
leaq 88(%rsp), %rax
movq %rax, 40(%rsp)
leaq 16(%rsp), %rdi
leaq 72(%rsp), %rsi
leaq 64(%rsp), %rdx
leaq 56(%rsp), %rcx
callq __hipPopCallConfiguration
movq 16(%rsp), %rsi
movl 24(%rsp), %edx
movq 72(%rsp), %rcx
movl 80(%rsp), %r8d
leaq 32(%rsp), %r9
movl $_Z6kernelPiS_, %edi
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
movq 8(%rsp), %rsi
leaq 32(%rsp), %rdi
movl $4, %edx
movl $2, %ecx
callq hipMemcpy
movq (%rsp), %rsi
leaq 16(%rsp), %rdi
movl $4, %edx
movl $2, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $23, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl 32(%rsp), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB1_11
# %bb.3: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB1_5
# %bb.4:
movzbl 67(%rbx), %ecx
jmp .LBB1_6
.LBB1_5:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB1_6: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $23, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl 16(%rsp), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB1_11
# %bb.7: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i4
cmpb $0, 56(%rbx)
je .LBB1_9
# %bb.8:
movzbl 67(%rbx), %ecx
jmp .LBB1_10
.LBB1_9:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB1_10: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit7
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
xorl %eax, %eax
addq $104, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.LBB1_11:
.cfi_def_cfa_offset 128
callq _ZSt16__throw_bad_castv
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6kernelPiS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6kernelPiS_,@object # @_Z6kernelPiS_
.section .rodata,"a",@progbits
.globl _Z6kernelPiS_
.p2align 3, 0x0
_Z6kernelPiS_:
.quad _Z21__device_stub__kernelPiS_
.size _Z6kernelPiS_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Num blocks : "
.size .L.str, 24
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Num threads per block: "
.size .L.str.1, 24
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z6kernelPiS_"
.size .L__unnamed_1, 14
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__kernelPiS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6kernelPiS_
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z6kernelPiS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ MOV R7, c[0x0][0xc] ; /* 0x0000030000077a02 */
/* 0x000fe20000000f00 */
/*0020*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff037624 */
/* 0x000fe200078e00ff */
/*0030*/ MOV R2, c[0x0][0x160] ; /* 0x0000580000027a02 */
/* 0x000fe20000000f00 */
/*0040*/ IMAD.MOV.U32 R9, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff097624 */
/* 0x000fe200078e00ff */
/*0050*/ MOV R4, c[0x0][0x168] ; /* 0x00005a0000047a02 */
/* 0x000fe20000000f00 */
/*0060*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff057624 */
/* 0x000fe200078e00ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0080*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x000fe8000c101904 */
/*0090*/ STG.E [R4.64], R9 ; /* 0x0000000904007986 */
/* 0x000fe2000c101904 */
/*00a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00b0*/ BRA 0xb0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6kernelPiS_
.globl _Z6kernelPiS_
.p2align 8
.type _Z6kernelPiS_,@function
_Z6kernelPiS_:
s_clause 0x2
s_load_b32 s4, s[0:1], 0x1c
s_load_b32 s5, s[0:1], 0x10
s_load_b128 s[0:3], s[0:1], 0x0
v_mov_b32_e32 v0, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v1, s5 :: v_dual_mov_b32 v2, s4
s_clause 0x1
global_store_b32 v0, v1, s[0:1]
global_store_b32 v0, v2, s[2:3]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6kernelPiS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 6
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6kernelPiS_, .Lfunc_end0-_Z6kernelPiS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6kernelPiS_
.private_segment_fixed_size: 0
.sgpr_count: 6
.sgpr_spill_count: 0
.symbol: _Z6kernelPiS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00003e12_00000000-6_03_cuda.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z27__device_stub__Z6kernelPiS_PiS_
.type _Z27__device_stub__Z6kernelPiS_PiS_, @function
_Z27__device_stub__Z6kernelPiS_PiS_:
.LFB3694:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z6kernelPiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3694:
.size _Z27__device_stub__Z6kernelPiS_PiS_, .-_Z27__device_stub__Z6kernelPiS_PiS_
.globl _Z6kernelPiS_
.type _Z6kernelPiS_, @function
_Z6kernelPiS_:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z27__device_stub__Z6kernelPiS_PiS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _Z6kernelPiS_, .-_Z6kernelPiS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Num blocks : "
.LC1:
.string "Num threads per block: "
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $48, %rsp
.cfi_def_cfa_offset 64
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movq %rsp, %rdi
movl $4, %esi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L15
.L12:
leaq 16(%rsp), %rdi
movl $2, %ecx
movl $4, %edx
movq (%rsp), %rsi
call cudaMemcpy@PLT
leaq 28(%rsp), %rdi
movl $2, %ecx
movl $4, %edx
movq 8(%rsp), %rsi
call cudaMemcpy@PLT
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
leaq .LC0(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl 16(%rsp), %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq .LC1(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl 28(%rsp), %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L16
movl $0, %eax
addq $48, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z27__device_stub__Z6kernelPiS_PiS_
jmp .L12
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size main, .-main
.section .rodata.str1.1
.LC2:
.string "_Z6kernelPiS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z6kernelPiS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "03_cuda.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z21__device_stub__kernelPiS_ # -- Begin function _Z21__device_stub__kernelPiS_
.p2align 4, 0x90
.type _Z21__device_stub__kernelPiS_,@function
_Z21__device_stub__kernelPiS_: # @_Z21__device_stub__kernelPiS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z6kernelPiS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z21__device_stub__kernelPiS_, .Lfunc_end0-_Z21__device_stub__kernelPiS_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $104, %rsp
.cfi_def_cfa_offset 128
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
leaq 8(%rsp), %rdi
movl $4, %esi
callq hipMalloc
movq %rsp, %rdi
movl $4, %esi
callq hipMalloc
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq 8(%rsp), %rax
movq (%rsp), %rcx
movq %rax, 96(%rsp)
movq %rcx, 88(%rsp)
leaq 96(%rsp), %rax
movq %rax, 32(%rsp)
leaq 88(%rsp), %rax
movq %rax, 40(%rsp)
leaq 16(%rsp), %rdi
leaq 72(%rsp), %rsi
leaq 64(%rsp), %rdx
leaq 56(%rsp), %rcx
callq __hipPopCallConfiguration
movq 16(%rsp), %rsi
movl 24(%rsp), %edx
movq 72(%rsp), %rcx
movl 80(%rsp), %r8d
leaq 32(%rsp), %r9
movl $_Z6kernelPiS_, %edi
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
movq 8(%rsp), %rsi
leaq 32(%rsp), %rdi
movl $4, %edx
movl $2, %ecx
callq hipMemcpy
movq (%rsp), %rsi
leaq 16(%rsp), %rdi
movl $4, %edx
movl $2, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $23, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl 32(%rsp), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB1_11
# %bb.3: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB1_5
# %bb.4:
movzbl 67(%rbx), %ecx
jmp .LBB1_6
.LBB1_5:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB1_6: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $23, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl 16(%rsp), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB1_11
# %bb.7: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i4
cmpb $0, 56(%rbx)
je .LBB1_9
# %bb.8:
movzbl 67(%rbx), %ecx
jmp .LBB1_10
.LBB1_9:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB1_10: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit7
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
xorl %eax, %eax
addq $104, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.LBB1_11:
.cfi_def_cfa_offset 128
callq _ZSt16__throw_bad_castv
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6kernelPiS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6kernelPiS_,@object # @_Z6kernelPiS_
.section .rodata,"a",@progbits
.globl _Z6kernelPiS_
.p2align 3, 0x0
_Z6kernelPiS_:
.quad _Z21__device_stub__kernelPiS_
.size _Z6kernelPiS_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Num blocks : "
.size .L.str, 24
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Num threads per block: "
.size .L.str.1, 24
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z6kernelPiS_"
.size .L__unnamed_1, 14
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__kernelPiS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6kernelPiS_
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <cuda.h>
#include <cuda_runtime.h>
__constant__ float q = 1.60217646e-19;
__constant__ float m = 9.10938188e-31;
__constant__ float B0 = 1e-12;
__constant__ float alpha = 250000;
__global__ void kernel(float* x, float* y, float* z,
float* vx, float* vy, float* vz, int count, float tau)
{
int i = blockDim.x * blockIdx.x + threadIdx.x;
if(i < count)
{
float r = sqrtf(x[i]*x[i]+y[i]*y[i]+z[i]*z[i]);
float Bx = 0;
float By = 0;
float Bz = -B0 * expf(-r*r / alpha);
float vx1 = vx[i]; float vy1 = vy[i]; float vz1 = vz[i];
vx[i] = vx1 + tau * q * (vy1 * Bz - vz1 * By) / m;
vy[i] = vy1 + tau * q * (vz1 * Bx - vx1 * Bz) / m;
vz[i] = vz1 + tau * q * (vx1 * By - vy1 * Bx) / m;
x[i] += vx[i] * tau;
y[i] += vy[i] * tau;
z[i] += vz[i] * tau;
}
}
static float *d_x = NULL, *d_y = NULL, *d_z = NULL,
*d_vx = NULL, *d_vy = NULL, *d_vz = NULL;
static size_t oldcount = 0;
__host__ void process_particles(float* x, float* y, float* z,
float* vx, float* vy, float*vz, size_t count, float tau)
{
int size = count * sizeof(float);
if(!d_x || oldcount != count)
{
cudaFree(d_x);
cudaMalloc(&d_x, size);
cudaFree(d_y);
cudaMalloc(&d_y, size);
cudaFree(d_z);
cudaMalloc(&d_z, size);
cudaFree(d_vx);
cudaMalloc(&d_vx, size);
cudaFree(d_vy);
cudaMalloc(&d_vy, size);
cudaFree(d_vz);
cudaMalloc(&d_vz, size);
oldcount = count;
}
cudaMemcpy(d_x, x, size, cudaMemcpyHostToDevice);
cudaMemcpy(d_y, y, size, cudaMemcpyHostToDevice);
cudaMemcpy(d_z, z, size, cudaMemcpyHostToDevice);
cudaMemcpy(d_vx, vx, size, cudaMemcpyHostToDevice);
cudaMemcpy(d_vy, vy, size, cudaMemcpyHostToDevice);
cudaMemcpy(d_vz, vz, size, cudaMemcpyHostToDevice);
kernel<<<count / 256 + 1, 256>>>(d_x, d_y, d_z, d_vx, d_vy, d_vz, count, tau);
cudaMemcpy(x, d_x, size, cudaMemcpyDeviceToHost);
cudaMemcpy(y, d_y, size, cudaMemcpyDeviceToHost);
cudaMemcpy(z, d_z, size, cudaMemcpyDeviceToHost);
cudaMemcpy(vx, d_vx, size, cudaMemcpyDeviceToHost);
cudaMemcpy(vy, d_vy, size, cudaMemcpyDeviceToHost);
cudaMemcpy(vz, d_vz, size, cudaMemcpyDeviceToHost);
} | code for sm_80
Function : _Z6kernelPfS_S_S_S_S_if
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R2, R2, c[0x0][0x0], R3 ; /* 0x0000000002027a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R2, c[0x0][0x190], PT ; /* 0x0000640002007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R9, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff097435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R12, R2, R9, c[0x0][0x168] ; /* 0x00005a00020c7625 */
/* 0x000fc800078e0209 */
/*0090*/ IMAD.WIDE R10, R2.reuse, R9.reuse, c[0x0][0x160] ; /* 0x00005800020a7625 */
/* 0x0c0fe200078e0209 */
/*00a0*/ LDG.E R3, [R12.64] ; /* 0x000000040c037981 */
/* 0x000ea6000c1e1900 */
/*00b0*/ IMAD.WIDE R8, R2, R9, c[0x0][0x170] ; /* 0x00005c0002087625 */
/* 0x000fe200078e0209 */
/*00c0*/ LDG.E R0, [R10.64] ; /* 0x000000040a007981 */
/* 0x000ee8000c1e1900 */
/*00d0*/ LDG.E R4, [R8.64] ; /* 0x0000000408047981 */
/* 0x000f22000c1e1900 */
/*00e0*/ BSSY B0, 0x1e0 ; /* 0x000000f000007945 */
/* 0x000fe20003800000 */
/*00f0*/ FMUL R3, R3, R3 ; /* 0x0000000303037220 */
/* 0x004fc80000400000 */
/*0100*/ FFMA R3, R0, R0, R3 ; /* 0x0000000000037223 */
/* 0x008fc80000000003 */
/*0110*/ FFMA R3, R4, R4, R3 ; /* 0x0000000404037223 */
/* 0x010fc80000000003 */
/*0120*/ MUFU.RSQ R0, R3 ; /* 0x0000000300007308 */
/* 0x0000620000001400 */
/*0130*/ IADD3 R4, R3, -0xd000000, RZ ; /* 0xf300000003047810 */
/* 0x000fc80007ffe0ff */
/*0140*/ ISETP.GT.U32.AND P0, PT, R4, 0x727fffff, PT ; /* 0x727fffff0400780c */
/* 0x000fda0003f04070 */
/*0150*/ @!P0 BRA 0x190 ; /* 0x0000003000008947 */
/* 0x000fea0003800000 */
/*0160*/ MOV R14, 0x180 ; /* 0x00000180000e7802 */
/* 0x003fe40000000f00 */
/*0170*/ CALL.REL.NOINC 0x8b0 ; /* 0x0000073000007944 */
/* 0x000fea0003c00000 */
/*0180*/ BRA 0x1d0 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*0190*/ FMUL.FTZ R4, R3, R0 ; /* 0x0000000003047220 */
/* 0x003fe40000410000 */
/*01a0*/ FMUL.FTZ R0, R0, 0.5 ; /* 0x3f00000000007820 */
/* 0x000fe40000410000 */
/*01b0*/ FFMA R3, -R4, R4, R3 ; /* 0x0000000404037223 */
/* 0x000fc80000000103 */
/*01c0*/ FFMA R0, R3, R0, R4 ; /* 0x0000000003007223 */
/* 0x000fe40000000004 */
/*01d0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*01e0*/ MUFU.RCP R3, c[0x3][0xc] ; /* 0x00c0030000037b08 */
/* 0x000e220000001000 */
/*01f0*/ FMUL R24, R0, R0 ; /* 0x0000000000187220 */
/* 0x000fe20000400000 */
/*0200*/ BSSY B0, 0x2f0 ; /* 0x000000e000007945 */
/* 0x000fe20003800000 */
/*0210*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x3][0xc] ; /* 0x00c00300ff047624 */
/* 0x000fca00078e00ff */
/*0220*/ FCHK P0, -R24, c[0x3][0xc] ; /* 0x00c0030018007b02 */
/* 0x000e620000000100 */
/*0230*/ FFMA R4, R3, -R4, 1 ; /* 0x3f80000003047423 */
/* 0x001fc80000000804 */
/*0240*/ FFMA R4, R3, R4, R3 ; /* 0x0000000403047223 */
/* 0x000fc80000000003 */
/*0250*/ FFMA R3, -R24, R4, RZ ; /* 0x0000000418037223 */
/* 0x000fc800000001ff */
/*0260*/ FFMA R0, R3, -c[0x3][0xc], -R24 ; /* 0x80c0030003007a23 */
/* 0x000fc80000000818 */
/*0270*/ FFMA R15, R4, R0, R3 ; /* 0x00000000040f7223 */
/* 0x000fe20000000003 */
/*0280*/ @!P0 BRA 0x2e0 ; /* 0x0000005000008947 */
/* 0x002fea0003800000 */
/*0290*/ FADD R24, -R24, -RZ ; /* 0x800000ff18187221 */
/* 0x000fe20000000100 */
/*02a0*/ MOV R19, c[0x3][0xc] ; /* 0x00c0030000137a02 */
/* 0x000fe40000000f00 */
/*02b0*/ MOV R18, 0x2d0 ; /* 0x000002d000127802 */
/* 0x000fe40000000f00 */
/*02c0*/ CALL.REL.NOINC 0xa10 ; /* 0x0000074000007944 */
/* 0x000fea0003c00000 */
/*02d0*/ MOV R15, R26 ; /* 0x0000001a000f7202 */
/* 0x001fe40000000f00 */
/*02e0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*02f0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fc800078e00ff */
/*0300*/ IMAD.WIDE R6, R2, R3, c[0x0][0x188] ; /* 0x0000620002067625 */
/* 0x000fc800078e0203 */
/*0310*/ IMAD.WIDE R4, R2.reuse, R3.reuse, c[0x0][0x180] ; /* 0x0000600002047625 */
/* 0x0c0fe200078e0203 */
/*0320*/ LDG.E R0, [R6.64] ; /* 0x0000000406007981 */
/* 0x000ea8000c1e1900 */
/*0330*/ LDG.E R14, [R4.64] ; /* 0x00000004040e7981 */
/* 0x000ee2000c1e1900 */
/*0340*/ HFMA2.MMA R16, -RZ, RZ, 0.96630859375, -0.0022525787353515625 ; /* 0x3bbb989dff107435 */
/* 0x000fe200000001ff */
/*0350*/ MOV R17, 0x437c0000 ; /* 0x437c000000117802 */
/* 0x000fe20000000f00 */
/*0360*/ MUFU.RCP R19, c[0x3][0x4] ; /* 0x00c0010000137b08 */
/* 0x000e220000001000 */
/*0370*/ MOV R22, c[0x3][0x4] ; /* 0x00c0010000167a02 */
/* 0x000fe20000000f00 */
/*0380*/ BSSY B0, 0x540 ; /* 0x000001b000007945 */
/* 0x000fe20003800000 */
/*0390*/ IMAD.WIDE R2, R2, R3, c[0x0][0x178] ; /* 0x00005e0002027625 */
/* 0x000fca00078e0203 */
/*03a0*/ FFMA.SAT R16, R15, R16, 0.5 ; /* 0x3f0000000f107423 */
/* 0x000fc80000002010 */
/*03b0*/ FFMA.RM R16, R16, R17, 12582913 ; /* 0x4b40000110107423 */
/* 0x000fe20000004011 */
/*03c0*/ MOV R17, c[0x3][0x0] ; /* 0x00c0000000117a02 */
/* 0x000fc60000000f00 */
/*03d0*/ FADD R18, R16.reuse, -12583039 ; /* 0xcb40007f10127421 */
/* 0x040fe40000000000 */
/*03e0*/ IMAD.SHL.U32 R16, R16, 0x800000, RZ ; /* 0x0080000010107824 */
/* 0x000fe400078e00ff */
/*03f0*/ FFMA R18, R15, 1.4426950216293334961, -R18 ; /* 0x3fb8aa3b0f127823 */
/* 0x000fe40000000812 */
/*0400*/ FMUL R17, R17, c[0x0][0x194] ; /* 0x0000650011117a20 */
/* 0x000fe40000400000 */
/*0410*/ FFMA R18, R15, 1.925963033500011079e-08, R18 ; /* 0x32a570600f127823 */
/* 0x000fe40000000012 */
/*0420*/ FFMA R22, R19, -R22, 1 ; /* 0x3f80000013167423 */
/* 0x001fc40000000816 */
/*0430*/ MUFU.EX2 R15, R18 ; /* 0x00000012000f7308 */
/* 0x000e240000000800 */
/*0440*/ FFMA R22, R19, R22, R19 ; /* 0x0000001613167223 */
/* 0x000fe40000000013 */
/*0450*/ FMUL R16, R16, R15 ; /* 0x0000000f10107220 */
/* 0x001fc80000400000 */
/*0460*/ FMUL R16, R16, c[0x3][0x8] ; /* 0x00c0020010107a20 */
/* 0x000fe40000400000 */
/*0470*/ FMUL R15, RZ, R0 ; /* 0x00000000ff0f7220 */
/* 0x004fc80000400000 */
/*0480*/ FFMA R20, -R16, R14, -R15 ; /* 0x0000000e10147223 */
/* 0x008fc8000000090f */
/*0490*/ FMUL R24, R17, R20 ; /* 0x0000001411187220 */
/* 0x000fc80000400000 */
/*04a0*/ FCHK P0, R24, c[0x3][0x4] ; /* 0x00c0010018007b02 */
/* 0x000e220000000000 */
/*04b0*/ FFMA R19, R24, R22, RZ ; /* 0x0000001618137223 */
/* 0x000fc800000000ff */
/*04c0*/ FFMA R18, R19, -c[0x3][0x4], R24 ; /* 0x80c0010013127a23 */
/* 0x000fc80000000018 */
/*04d0*/ FFMA R19, R22, R18, R19 ; /* 0x0000001216137223 */
/* 0x000fe20000000013 */
/*04e0*/ @!P0 BRA 0x530 ; /* 0x0000004000008947 */
/* 0x001fea0003800000 */
/*04f0*/ IMAD.MOV.U32 R19, RZ, RZ, c[0x3][0x4] ; /* 0x00c00100ff137624 */
/* 0x000fe200078e00ff */
/*0500*/ MOV R18, 0x520 ; /* 0x0000052000127802 */
/* 0x000fe40000000f00 */
/*0510*/ CALL.REL.NOINC 0xa10 ; /* 0x000004f000007944 */
/* 0x000fea0003c00000 */
/*0520*/ MOV R19, R26 ; /* 0x0000001a00137202 */
/* 0x001fe40000000f00 */
/*0530*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0540*/ LDG.E R22, [R2.64] ; /* 0x0000000402167981 */
/* 0x000ea2000c1e1900 */
/*0550*/ MUFU.RCP R18, c[0x3][0x4] ; /* 0x00c0010000127b08 */
/* 0x000e220000001000 */
/*0560*/ MOV R21, c[0x3][0x4] ; /* 0x00c0010000157a02 */
/* 0x000fe20000000f00 */
/*0570*/ BSSY B0, 0x680 ; /* 0x0000010000007945 */
/* 0x000fe80003800000 */
/*0580*/ FFMA R21, R18, -R21, 1 ; /* 0x3f80000012157423 */
/* 0x001fc80000000815 */
/*0590*/ FFMA R21, R18, R21, R18 ; /* 0x0000001512157223 */
/* 0x000fe40000000012 */
/*05a0*/ FFMA R16, R16, R22, R15 ; /* 0x0000001610107223 */
/* 0x004fe4000000000f */
/*05b0*/ FADD R19, R22, R19 ; /* 0x0000001316137221 */
/* 0x000fe40000000000 */
/*05c0*/ FMUL R24, R17, R16 ; /* 0x0000001011187220 */
/* 0x000fc60000400000 */
/*05d0*/ STG.E [R2.64], R19 ; /* 0x0000001302007986 */
/* 0x0001e2000c101904 */
/*05e0*/ FCHK P0, R24, c[0x3][0x4] ; /* 0x00c0010018007b02 */
/* 0x000e620000000000 */
/*05f0*/ FFMA R15, R21, R24, RZ ; /* 0x00000018150f7223 */
/* 0x000fc800000000ff */
/*0600*/ FFMA R16, R15, -c[0x3][0x4], R24 ; /* 0x80c001000f107a23 */
/* 0x000fc80000000018 */
/*0610*/ FFMA R15, R21, R16, R15 ; /* 0x00000010150f7223 */
/* 0x000fe2000000000f */
/*0620*/ @!P0 BRA 0x670 ; /* 0x0000004000008947 */
/* 0x002fea0003800000 */
/*0630*/ IMAD.MOV.U32 R19, RZ, RZ, c[0x3][0x4] ; /* 0x00c00100ff137624 */
/* 0x001fe200078e00ff */
/*0640*/ MOV R18, 0x660 ; /* 0x0000066000127802 */
/* 0x000fe40000000f00 */
/*0650*/ CALL.REL.NOINC 0xa10 ; /* 0x000003b000007944 */
/* 0x000fea0003c00000 */
/*0660*/ MOV R15, R26 ; /* 0x0000001a000f7202 */
/* 0x001fe40000000f00 */
/*0670*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x001fea0003800000 */
/*0680*/ MUFU.RCP R16, c[0x3][0x4] ; /* 0x00c0010000107b08 */
/* 0x000e220000001000 */
/*0690*/ FMUL R19, RZ, R14 ; /* 0x0000000eff137220 */
/* 0x000fe20000400000 */
/*06a0*/ MOV R21, c[0x3][0x4] ; /* 0x00c0010000157a02 */
/* 0x000fe20000000f00 */
/*06b0*/ FADD R15, R14, R15 ; /* 0x0000000f0e0f7221 */
/* 0x000fe20000000000 */
/*06c0*/ BSSY B0, 0x7c0 ; /* 0x000000f000007945 */
/* 0x000fe20003800000 */
/*06d0*/ FFMA R22, RZ, R22, -R19 ; /* 0x00000016ff167223 */
/* 0x000fc60000000813 */
/*06e0*/ STG.E [R4.64], R15 ; /* 0x0000000f04007986 */
/* 0x0003e2000c101904 */
/*06f0*/ FMUL R24, R17, R22 ; /* 0x0000001611187220 */
/* 0x000fc80000400000 */
/*0700*/ FCHK P0, R24, c[0x3][0x4] ; /* 0x00c0010018007b02 */
/* 0x000ea20000000000 */
/*0710*/ FFMA R21, R16, -R21, 1 ; /* 0x3f80000010157423 */
/* 0x001fc80000000815 */
/*0720*/ FFMA R21, R16, R21, R16 ; /* 0x0000001510157223 */
/* 0x000fc80000000010 */
/*0730*/ FFMA R17, R21, R24, RZ ; /* 0x0000001815117223 */
/* 0x000fc800000000ff */
/*0740*/ FFMA R14, R17, -c[0x3][0x4], R24 ; /* 0x80c00100110e7a23 */
/* 0x000fc80000000018 */
/*0750*/ FFMA R17, R21, R14, R17 ; /* 0x0000000e15117223 */
/* 0x000fe20000000011 */
/*0760*/ @!P0 BRA 0x7b0 ; /* 0x0000004000008947 */
/* 0x004fea0003800000 */
/*0770*/ MOV R19, c[0x3][0x4] ; /* 0x00c0010000137a02 */
/* 0x002fe40000000f00 */
/*0780*/ MOV R18, 0x7a0 ; /* 0x000007a000127802 */
/* 0x000fe40000000f00 */
/*0790*/ CALL.REL.NOINC 0xa10 ; /* 0x0000027000007944 */
/* 0x000fea0003c00000 */
/*07a0*/ IMAD.MOV.U32 R17, RZ, RZ, R26 ; /* 0x000000ffff117224 */
/* 0x001fe400078e001a */
/*07b0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x002fea0003800000 */
/*07c0*/ FADD R17, R0, R17 ; /* 0x0000001100117221 */
/* 0x000fca0000000000 */
/*07d0*/ STG.E [R6.64], R17 ; /* 0x0000001106007986 */
/* 0x000fe8000c101904 */
/*07e0*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*07f0*/ LDG.E R15, [R10.64] ; /* 0x000000040a0f7981 */
/* 0x000ea4000c1e1900 */
/*0800*/ FFMA R15, R2, c[0x0][0x194], R15 ; /* 0x00006500020f7a23 */
/* 0x004fca000000000f */
/*0810*/ STG.E [R10.64], R15 ; /* 0x0000000f0a007986 */
/* 0x000fe8000c101904 */
/*0820*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*0830*/ LDG.E R19, [R12.64] ; /* 0x000000040c137981 */
/* 0x000ea4000c1e1900 */
/*0840*/ FFMA R19, R4, c[0x0][0x194], R19 ; /* 0x0000650004137a23 */
/* 0x004fca0000000013 */
/*0850*/ STG.E [R12.64], R19 ; /* 0x000000130c007986 */
/* 0x000fe8000c101904 */
/*0860*/ LDG.E R0, [R6.64] ; /* 0x0000000406007981 */
/* 0x000ea8000c1e1900 */
/*0870*/ LDG.E R21, [R8.64] ; /* 0x0000000408157981 */
/* 0x000ea4000c1e1900 */
/*0880*/ FFMA R21, R0, c[0x0][0x194], R21 ; /* 0x0000650000157a23 */
/* 0x004fca0000000015 */
/*0890*/ STG.E [R8.64], R21 ; /* 0x0000001508007986 */
/* 0x000fe2000c101904 */
/*08a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*08b0*/ LOP3.LUT P0, RZ, R3, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff03ff7812 */
/* 0x000fda000780c0ff */
/*08c0*/ @!P0 MOV R0, R3 ; /* 0x0000000300008202 */
/* 0x000fe20000000f00 */
/*08d0*/ @!P0 BRA 0x9e0 ; /* 0x0000010000008947 */
/* 0x000fea0003800000 */
/*08e0*/ FSETP.GEU.FTZ.AND P0, PT, R3, RZ, PT ; /* 0x000000ff0300720b */
/* 0x000fda0003f1e000 */
/*08f0*/ @!P0 MOV R0, 0x7fffffff ; /* 0x7fffffff00008802 */
/* 0x000fe20000000f00 */
/*0900*/ @!P0 BRA 0x9e0 ; /* 0x000000d000008947 */
/* 0x000fea0003800000 */
/*0910*/ FSETP.GTU.FTZ.AND P0, PT, |R3|, +INF , PT ; /* 0x7f8000000300780b */
/* 0x000fda0003f1c200 */
/*0920*/ @P0 FADD.FTZ R0, R3, 1 ; /* 0x3f80000003000421 */
/* 0x000fe20000010000 */
/*0930*/ @P0 BRA 0x9e0 ; /* 0x000000a000000947 */
/* 0x000fea0003800000 */
/*0940*/ FSETP.NEU.FTZ.AND P0, PT, |R3|, +INF , PT ; /* 0x7f8000000300780b */
/* 0x000fda0003f1d200 */
/*0950*/ @P0 FFMA R4, R3, 1.84467440737095516160e+19, RZ ; /* 0x5f80000003040823 */
/* 0x000fc800000000ff */
/*0960*/ @P0 MUFU.RSQ R5, R4 ; /* 0x0000000400050308 */
/* 0x000e240000001400 */
/*0970*/ @P0 FMUL.FTZ R7, R4, R5 ; /* 0x0000000504070220 */
/* 0x001fe40000410000 */
/*0980*/ @P0 FMUL.FTZ R5, R5, 0.5 ; /* 0x3f00000005050820 */
/* 0x000fe40000410000 */
/*0990*/ @P0 FADD.FTZ R0, -R7, -RZ ; /* 0x800000ff07000221 */
/* 0x000fc80000010100 */
/*09a0*/ @P0 FFMA R6, R7, R0, R4 ; /* 0x0000000007060223 */
/* 0x000fe20000000004 */
/*09b0*/ @!P0 MOV R0, R3 ; /* 0x0000000300008202 */
/* 0x000fc60000000f00 */
/*09c0*/ @P0 FFMA R5, R6, R5, R7 ; /* 0x0000000506050223 */
/* 0x000fc80000000007 */
/*09d0*/ @P0 FMUL.FTZ R0, R5, 2.3283064365386962891e-10 ; /* 0x2f80000005000820 */
/* 0x000fe40000410000 */
/*09e0*/ HFMA2.MMA R5, -RZ, RZ, 0, 0 ; /* 0x00000000ff057435 */
/* 0x000fe200000001ff */
/*09f0*/ IMAD.MOV.U32 R4, RZ, RZ, R14 ; /* 0x000000ffff047224 */
/* 0x000fca00078e000e */
/*0a00*/ RET.REL.NODEC R4 0x0 ; /* 0xfffff5f004007950 */
/* 0x000fea0003c3ffff */
/*0a10*/ SHF.R.U32.HI R20, RZ, 0x17, R19 ; /* 0x00000017ff147819 */
/* 0x000fe20000011613 */
/*0a20*/ BSSY B1, 0x1050 ; /* 0x0000062000017945 */
/* 0x000fe20003800000 */
/*0a30*/ SHF.R.U32.HI R23, RZ, 0x17, R24 ; /* 0x00000017ff177819 */
/* 0x000fe40000011618 */
/*0a40*/ LOP3.LUT R20, R20, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff14147812 */
/* 0x000fe400078ec0ff */
/*0a50*/ LOP3.LUT R23, R23, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff17177812 */
/* 0x000fe400078ec0ff */
/*0a60*/ IADD3 R26, R20, -0x1, RZ ; /* 0xffffffff141a7810 */
/* 0x000fe40007ffe0ff */
/*0a70*/ IADD3 R25, R23, -0x1, RZ ; /* 0xffffffff17197810 */
/* 0x000fc40007ffe0ff */
/*0a80*/ ISETP.GT.U32.AND P0, PT, R26, 0xfd, PT ; /* 0x000000fd1a00780c */
/* 0x000fc80003f04070 */
/*0a90*/ ISETP.GT.U32.OR P0, PT, R25, 0xfd, P0 ; /* 0x000000fd1900780c */
/* 0x000fda0000704470 */
/*0aa0*/ @!P0 MOV R21, RZ ; /* 0x000000ff00158202 */
/* 0x000fe20000000f00 */
/*0ab0*/ @!P0 BRA 0xc30 ; /* 0x0000017000008947 */
/* 0x000fea0003800000 */
/*0ac0*/ FSETP.GTU.FTZ.AND P0, PT, |R24|, +INF , PT ; /* 0x7f8000001800780b */
/* 0x000fe40003f1c200 */
/*0ad0*/ FSETP.GTU.FTZ.AND P1, PT, |R19|, +INF , PT ; /* 0x7f8000001300780b */
/* 0x000fc80003f3c200 */
/*0ae0*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000703570 */
/*0af0*/ @P0 BRA 0x1030 ; /* 0x0000053000000947 */
/* 0x000fea0003800000 */
/*0b00*/ LOP3.LUT P0, RZ, R19, 0x7fffffff, R24, 0xc8, !PT ; /* 0x7fffffff13ff7812 */
/* 0x000fda000780c818 */
/*0b10*/ @!P0 BRA 0x1010 ; /* 0x000004f000008947 */
/* 0x000fea0003800000 */
/*0b20*/ FSETP.NEU.FTZ.AND P2, PT, |R24|.reuse, +INF , PT ; /* 0x7f8000001800780b */
/* 0x040fe40003f5d200 */
/*0b30*/ FSETP.NEU.FTZ.AND P1, PT, |R19|, +INF , PT ; /* 0x7f8000001300780b */
/* 0x000fe40003f3d200 */
/*0b40*/ FSETP.NEU.FTZ.AND P0, PT, |R24|, +INF , PT ; /* 0x7f8000001800780b */
/* 0x000fd60003f1d200 */
/*0b50*/ @!P1 BRA !P2, 0x1010 ; /* 0x000004b000009947 */
/* 0x000fea0005000000 */
/*0b60*/ LOP3.LUT P2, RZ, R24, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff18ff7812 */
/* 0x000fc8000784c0ff */
/*0b70*/ PLOP3.LUT P1, PT, P1, P2, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000f24572 */
/*0b80*/ @P1 BRA 0xff0 ; /* 0x0000046000001947 */
/* 0x000fea0003800000 */
/*0b90*/ LOP3.LUT P1, RZ, R19, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff13ff7812 */
/* 0x000fc8000782c0ff */
/*0ba0*/ PLOP3.LUT P0, PT, P0, P1, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000702572 */
/*0bb0*/ @P0 BRA 0xfc0 ; /* 0x0000040000000947 */
/* 0x000fea0003800000 */
/*0bc0*/ ISETP.GE.AND P0, PT, R25, RZ, PT ; /* 0x000000ff1900720c */
/* 0x000fe40003f06270 */
/*0bd0*/ ISETP.GE.AND P1, PT, R26, RZ, PT ; /* 0x000000ff1a00720c */
/* 0x000fd60003f26270 */
/*0be0*/ @P0 MOV R21, RZ ; /* 0x000000ff00150202 */
/* 0x000fe20000000f00 */
/*0bf0*/ @!P0 IMAD.MOV.U32 R21, RZ, RZ, -0x40 ; /* 0xffffffc0ff158424 */
/* 0x000fe400078e00ff */
/*0c00*/ @!P0 FFMA R24, R24, 1.84467440737095516160e+19, RZ ; /* 0x5f80000018188823 */
/* 0x000fe400000000ff */
/*0c10*/ @!P1 FFMA R19, R19, 1.84467440737095516160e+19, RZ ; /* 0x5f80000013139823 */
/* 0x000fe200000000ff */
/*0c20*/ @!P1 IADD3 R21, R21, 0x40, RZ ; /* 0x0000004015159810 */
/* 0x000fe40007ffe0ff */
/*0c30*/ LEA R26, R20, 0xc0800000, 0x17 ; /* 0xc0800000141a7811 */
/* 0x000fe200078eb8ff */
/*0c40*/ BSSY B2, 0xfb0 ; /* 0x0000036000027945 */
/* 0x000fe20003800000 */
/*0c50*/ IADD3 R23, R23, -0x7f, RZ ; /* 0xffffff8117177810 */
/* 0x000fe40007ffe0ff */
/*0c60*/ IADD3 R27, -R26, R19, RZ ; /* 0x000000131a1b7210 */
/* 0x000fc60007ffe1ff */
/*0c70*/ IMAD R28, R23, -0x800000, R24 ; /* 0xff800000171c7824 */
/* 0x000fe200078e0218 */
/*0c80*/ MUFU.RCP R26, R27 ; /* 0x0000001b001a7308 */
/* 0x000e220000001000 */
/*0c90*/ FADD.FTZ R19, -R27, -RZ ; /* 0x800000ff1b137221 */
/* 0x000fc80000010100 */
/*0ca0*/ FFMA R25, R26, R19, 1 ; /* 0x3f8000001a197423 */
/* 0x001fc80000000013 */
/*0cb0*/ FFMA R25, R26, R25, R26 ; /* 0x000000191a197223 */
/* 0x000fc8000000001a */
/*0cc0*/ FFMA R24, R28, R25, RZ ; /* 0x000000191c187223 */
/* 0x000fc800000000ff */
/*0cd0*/ FFMA R26, R19, R24, R28 ; /* 0x00000018131a7223 */
/* 0x000fc8000000001c */
/*0ce0*/ FFMA R24, R25, R26, R24 ; /* 0x0000001a19187223 */
/* 0x000fc80000000018 */
/*0cf0*/ FFMA R19, R19, R24, R28 ; /* 0x0000001813137223 */
/* 0x000fe2000000001c */
/*0d00*/ IADD3 R28, R23, 0x7f, -R20 ; /* 0x0000007f171c7810 */
/* 0x000fc60007ffe814 */
/*0d10*/ FFMA R26, R25, R19, R24 ; /* 0x00000013191a7223 */
/* 0x000fe20000000018 */
/*0d20*/ IADD3 R21, R28, R21, RZ ; /* 0x000000151c157210 */
/* 0x000fc80007ffe0ff */
/*0d30*/ SHF.R.U32.HI R20, RZ, 0x17, R26 ; /* 0x00000017ff147819 */
/* 0x000fc8000001161a */
/*0d40*/ LOP3.LUT R20, R20, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff14147812 */
/* 0x000fc800078ec0ff */
/*0d50*/ IADD3 R20, R20, R21, RZ ; /* 0x0000001514147210 */
/* 0x000fc80007ffe0ff */
/*0d60*/ IADD3 R23, R20, -0x1, RZ ; /* 0xffffffff14177810 */
/* 0x000fc80007ffe0ff */
/*0d70*/ ISETP.GE.U32.AND P0, PT, R23, 0xfe, PT ; /* 0x000000fe1700780c */
/* 0x000fda0003f06070 */
/*0d80*/ @!P0 BRA 0xf90 ; /* 0x0000020000008947 */
/* 0x000fea0003800000 */
/*0d90*/ ISETP.GT.AND P0, PT, R20, 0xfe, PT ; /* 0x000000fe1400780c */
/* 0x000fda0003f04270 */
/*0da0*/ @P0 BRA 0xf60 ; /* 0x000001b000000947 */
/* 0x000fea0003800000 */
/*0db0*/ ISETP.GE.AND P0, PT, R20, 0x1, PT ; /* 0x000000011400780c */
/* 0x000fda0003f06270 */
/*0dc0*/ @P0 BRA 0xfa0 ; /* 0x000001d000000947 */
/* 0x000fea0003800000 */
/*0dd0*/ ISETP.GE.AND P0, PT, R20, -0x18, PT ; /* 0xffffffe81400780c */
/* 0x000fe40003f06270 */
/*0de0*/ LOP3.LUT R26, R26, 0x80000000, RZ, 0xc0, !PT ; /* 0x800000001a1a7812 */
/* 0x000fd600078ec0ff */
/*0df0*/ @!P0 BRA 0xfa0 ; /* 0x000001a000008947 */
/* 0x000fea0003800000 */
/*0e00*/ FFMA.RZ R21, R25, R19.reuse, R24.reuse ; /* 0x0000001319157223 */
/* 0x180fe2000000c018 */
/*0e10*/ IADD3 R28, R20.reuse, 0x20, RZ ; /* 0x00000020141c7810 */
/* 0x040fe40007ffe0ff */
/*0e20*/ ISETP.NE.AND P2, PT, R20.reuse, RZ, PT ; /* 0x000000ff1400720c */
/* 0x040fe40003f45270 */
/*0e30*/ LOP3.LUT R23, R21, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff15177812 */
/* 0x000fe200078ec0ff */
/*0e40*/ FFMA.RP R21, R25.reuse, R19.reuse, R24.reuse ; /* 0x0000001319157223 */
/* 0x1c0fe20000008018 */
/*0e50*/ ISETP.NE.AND P1, PT, R20, RZ, PT ; /* 0x000000ff1400720c */
/* 0x000fe20003f25270 */
/*0e60*/ FFMA.RM R24, R25, R19, R24 ; /* 0x0000001319187223 */
/* 0x000fe20000004018 */
/*0e70*/ LOP3.LUT R23, R23, 0x800000, RZ, 0xfc, !PT ; /* 0x0080000017177812 */
/* 0x000fe200078efcff */
/*0e80*/ IMAD.MOV R20, RZ, RZ, -R20 ; /* 0x000000ffff147224 */
/* 0x000fc600078e0a14 */
/*0e90*/ SHF.L.U32 R28, R23, R28, RZ ; /* 0x0000001c171c7219 */
/* 0x000fe400000006ff */
/*0ea0*/ FSETP.NEU.FTZ.AND P0, PT, R21, R24, PT ; /* 0x000000181500720b */
/* 0x000fe40003f1d000 */
/*0eb0*/ SEL R20, R20, RZ, P2 ; /* 0x000000ff14147207 */
/* 0x000fe40001000000 */
/*0ec0*/ ISETP.NE.AND P1, PT, R28, RZ, P1 ; /* 0x000000ff1c00720c */
/* 0x000fe40000f25270 */
/*0ed0*/ SHF.R.U32.HI R20, RZ, R20, R23 ; /* 0x00000014ff147219 */
/* 0x000fe40000011617 */
/*0ee0*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc40000703570 */
/*0ef0*/ SHF.R.U32.HI R24, RZ, 0x1, R20 ; /* 0x00000001ff187819 */
/* 0x000fe40000011614 */
/*0f00*/ SEL R19, RZ, 0x1, !P0 ; /* 0x00000001ff137807 */
/* 0x000fc80004000000 */
/*0f10*/ LOP3.LUT R19, R19, 0x1, R24, 0xf8, !PT ; /* 0x0000000113137812 */
/* 0x000fc800078ef818 */
/*0f20*/ LOP3.LUT R19, R19, R20, RZ, 0xc0, !PT ; /* 0x0000001413137212 */
/* 0x000fc800078ec0ff */
/*0f30*/ IADD3 R19, R24, R19, RZ ; /* 0x0000001318137210 */
/* 0x000fc80007ffe0ff */
/*0f40*/ LOP3.LUT R26, R19, R26, RZ, 0xfc, !PT ; /* 0x0000001a131a7212 */
/* 0x000fe200078efcff */
/*0f50*/ BRA 0xfa0 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*0f60*/ LOP3.LUT R26, R26, 0x80000000, RZ, 0xc0, !PT ; /* 0x800000001a1a7812 */
/* 0x000fc800078ec0ff */
/*0f70*/ LOP3.LUT R26, R26, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f8000001a1a7812 */
/* 0x000fe200078efcff */
/*0f80*/ BRA 0xfa0 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0f90*/ LEA R26, R21, R26, 0x17 ; /* 0x0000001a151a7211 */
/* 0x000fe400078eb8ff */
/*0fa0*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*0fb0*/ BRA 0x1040 ; /* 0x0000008000007947 */
/* 0x000fea0003800000 */
/*0fc0*/ LOP3.LUT R19, R19, 0x80000000, R24, 0x48, !PT ; /* 0x8000000013137812 */
/* 0x000fc800078e4818 */
/*0fd0*/ LOP3.LUT R26, R19, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f800000131a7812 */
/* 0x000fe200078efcff */
/*0fe0*/ BRA 0x1040 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*0ff0*/ LOP3.LUT R26, R19, 0x80000000, R24, 0x48, !PT ; /* 0x80000000131a7812 */
/* 0x000fe200078e4818 */
/*1000*/ BRA 0x1040 ; /* 0x0000003000007947 */
/* 0x000fea0003800000 */
/*1010*/ MUFU.RSQ R26, -QNAN ; /* 0xffc00000001a7908 */
/* 0x000e220000001400 */
/*1020*/ BRA 0x1040 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*1030*/ FADD.FTZ R26, R24, R19 ; /* 0x00000013181a7221 */
/* 0x000fe40000010000 */
/*1040*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*1050*/ HFMA2.MMA R19, -RZ, RZ, 0, 0 ; /* 0x00000000ff137435 */
/* 0x000fcc00000001ff */
/*1060*/ RET.REL.NODEC R18 0x0 ; /* 0xffffef9012007950 */
/* 0x000fea0003c3ffff */
/*1070*/ BRA 0x1070; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*1080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*10a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*10b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*10c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*10d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*10e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*10f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <cuda.h>
#include <cuda_runtime.h>
__constant__ float q = 1.60217646e-19;
__constant__ float m = 9.10938188e-31;
__constant__ float B0 = 1e-12;
__constant__ float alpha = 250000;
__global__ void kernel(float* x, float* y, float* z,
float* vx, float* vy, float* vz, int count, float tau)
{
int i = blockDim.x * blockIdx.x + threadIdx.x;
if(i < count)
{
float r = sqrtf(x[i]*x[i]+y[i]*y[i]+z[i]*z[i]);
float Bx = 0;
float By = 0;
float Bz = -B0 * expf(-r*r / alpha);
float vx1 = vx[i]; float vy1 = vy[i]; float vz1 = vz[i];
vx[i] = vx1 + tau * q * (vy1 * Bz - vz1 * By) / m;
vy[i] = vy1 + tau * q * (vz1 * Bx - vx1 * Bz) / m;
vz[i] = vz1 + tau * q * (vx1 * By - vy1 * Bx) / m;
x[i] += vx[i] * tau;
y[i] += vy[i] * tau;
z[i] += vz[i] * tau;
}
}
static float *d_x = NULL, *d_y = NULL, *d_z = NULL,
*d_vx = NULL, *d_vy = NULL, *d_vz = NULL;
static size_t oldcount = 0;
__host__ void process_particles(float* x, float* y, float* z,
float* vx, float* vy, float*vz, size_t count, float tau)
{
int size = count * sizeof(float);
if(!d_x || oldcount != count)
{
cudaFree(d_x);
cudaMalloc(&d_x, size);
cudaFree(d_y);
cudaMalloc(&d_y, size);
cudaFree(d_z);
cudaMalloc(&d_z, size);
cudaFree(d_vx);
cudaMalloc(&d_vx, size);
cudaFree(d_vy);
cudaMalloc(&d_vy, size);
cudaFree(d_vz);
cudaMalloc(&d_vz, size);
oldcount = count;
}
cudaMemcpy(d_x, x, size, cudaMemcpyHostToDevice);
cudaMemcpy(d_y, y, size, cudaMemcpyHostToDevice);
cudaMemcpy(d_z, z, size, cudaMemcpyHostToDevice);
cudaMemcpy(d_vx, vx, size, cudaMemcpyHostToDevice);
cudaMemcpy(d_vy, vy, size, cudaMemcpyHostToDevice);
cudaMemcpy(d_vz, vz, size, cudaMemcpyHostToDevice);
kernel<<<count / 256 + 1, 256>>>(d_x, d_y, d_z, d_vx, d_vy, d_vz, count, tau);
cudaMemcpy(x, d_x, size, cudaMemcpyDeviceToHost);
cudaMemcpy(y, d_y, size, cudaMemcpyDeviceToHost);
cudaMemcpy(z, d_z, size, cudaMemcpyDeviceToHost);
cudaMemcpy(vx, d_vx, size, cudaMemcpyDeviceToHost);
cudaMemcpy(vy, d_vy, size, cudaMemcpyDeviceToHost);
cudaMemcpy(vz, d_vz, size, cudaMemcpyDeviceToHost);
} | .file "tmpxft_0015454b_00000000-6_particles.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z37__device_stub__Z6kernelPfS_S_S_S_S_ifPfS_S_S_S_S_if
.type _Z37__device_stub__Z6kernelPfS_S_S_S_S_ifPfS_S_S_S_S_if, @function
_Z37__device_stub__Z6kernelPfS_S_S_S_S_ifPfS_S_S_S_S_if:
.LFB2052:
.cfi_startproc
endbr64
subq $216, %rsp
.cfi_def_cfa_offset 224
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
movq %rdx, 40(%rsp)
movq %rcx, 32(%rsp)
movq %r8, 24(%rsp)
movq %r9, 16(%rsp)
movss %xmm0, 12(%rsp)
movq %fs:40, %rax
movq %rax, 200(%rsp)
xorl %eax, %eax
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 40(%rsp), %rax
movq %rax, 144(%rsp)
leaq 32(%rsp), %rax
movq %rax, 152(%rsp)
leaq 24(%rsp), %rax
movq %rax, 160(%rsp)
leaq 16(%rsp), %rax
movq %rax, 168(%rsp)
leaq 224(%rsp), %rax
movq %rax, 176(%rsp)
leaq 12(%rsp), %rax
movq %rax, 184(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 200(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $216, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 232
pushq 72(%rsp)
.cfi_def_cfa_offset 240
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq _Z6kernelPfS_S_S_S_S_if(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 224
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2052:
.size _Z37__device_stub__Z6kernelPfS_S_S_S_S_ifPfS_S_S_S_S_if, .-_Z37__device_stub__Z6kernelPfS_S_S_S_S_ifPfS_S_S_S_S_if
.globl _Z6kernelPfS_S_S_S_S_if
.type _Z6kernelPfS_S_S_S_S_if, @function
_Z6kernelPfS_S_S_S_S_if:
.LFB2053:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
call _Z37__device_stub__Z6kernelPfS_S_S_S_S_ifPfS_S_S_S_S_if
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _Z6kernelPfS_S_S_S_S_if, .-_Z6kernelPfS_S_S_S_S_if
.globl _Z17process_particlesPfS_S_S_S_S_mf
.type _Z17process_particlesPfS_S_S_S_S_mf, @function
_Z17process_particlesPfS_S_S_S_S_mf:
.LFB2027:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $72, %rsp
.cfi_def_cfa_offset 128
movq %rdi, %r14
movq %rsi, %r13
movq %rdx, %r12
movq %rcx, (%rsp)
movq %r8, 8(%rsp)
movq %r9, 16(%rsp)
movq 128(%rsp), %r15
movss %xmm0, 28(%rsp)
leal 0(,%r15,4), %ebx
movq _ZL3d_x(%rip), %rdi
testq %rdi, %rdi
je .L12
cmpq %r15, _ZL8oldcount(%rip)
je .L13
.L12:
call cudaFree@PLT
movslq %ebx, %rbp
movq %rbp, %rsi
leaq _ZL3d_x(%rip), %rdi
call cudaMalloc@PLT
movq _ZL3d_y(%rip), %rdi
call cudaFree@PLT
movq %rbp, %rsi
leaq _ZL3d_y(%rip), %rdi
call cudaMalloc@PLT
movq _ZL3d_z(%rip), %rdi
call cudaFree@PLT
movq %rbp, %rsi
leaq _ZL3d_z(%rip), %rdi
call cudaMalloc@PLT
movq _ZL4d_vx(%rip), %rdi
call cudaFree@PLT
movq %rbp, %rsi
leaq _ZL4d_vx(%rip), %rdi
call cudaMalloc@PLT
movq _ZL4d_vy(%rip), %rdi
call cudaFree@PLT
movq %rbp, %rsi
leaq _ZL4d_vy(%rip), %rdi
call cudaMalloc@PLT
movq _ZL4d_vz(%rip), %rdi
call cudaFree@PLT
movq %rbp, %rsi
leaq _ZL4d_vz(%rip), %rdi
call cudaMalloc@PLT
movq %r15, _ZL8oldcount(%rip)
.L13:
movslq %ebx, %rbx
movl $1, %ecx
movq %rbx, %rdx
movq %r14, %rsi
movq _ZL3d_x(%rip), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %r13, %rsi
movq _ZL3d_y(%rip), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %r12, %rsi
movq _ZL3d_z(%rip), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %rbx, %rdx
movq (%rsp), %rsi
movq _ZL4d_vx(%rip), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %rbx, %rdx
movq 8(%rsp), %rsi
movq _ZL4d_vy(%rip), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %rbx, %rdx
movq 16(%rsp), %rsi
movq _ZL4d_vz(%rip), %rdi
call cudaMemcpy@PLT
movl $256, 52(%rsp)
movl $1, 56(%rsp)
movq %r15, %rax
shrq $8, %rax
addl $1, %eax
movl %eax, 40(%rsp)
movl $1, 44(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 52(%rsp), %rdx
movl $1, %ecx
movq 40(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L16
.L14:
movl $2, %ecx
movq %rbx, %rdx
movq _ZL3d_x(%rip), %rsi
movq %r14, %rdi
call cudaMemcpy@PLT
movl $2, %ecx
movq %rbx, %rdx
movq _ZL3d_y(%rip), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
movl $2, %ecx
movq %rbx, %rdx
movq _ZL3d_z(%rip), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movl $2, %ecx
movq %rbx, %rdx
movq _ZL4d_vx(%rip), %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
movl $2, %ecx
movq %rbx, %rdx
movq _ZL4d_vy(%rip), %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $2, %ecx
movq %rbx, %rdx
movq _ZL4d_vz(%rip), %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L16:
.cfi_restore_state
subq $8, %rsp
.cfi_def_cfa_offset 136
pushq %r15
.cfi_def_cfa_offset 144
movss 44(%rsp), %xmm0
movq _ZL4d_vz(%rip), %r9
movq _ZL4d_vy(%rip), %r8
movq _ZL4d_vx(%rip), %rcx
movq _ZL3d_z(%rip), %rdx
movq _ZL3d_y(%rip), %rsi
movq _ZL3d_x(%rip), %rdi
call _Z37__device_stub__Z6kernelPfS_S_S_S_S_ifPfS_S_S_S_S_if
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L14
.cfi_endproc
.LFE2027:
.size _Z17process_particlesPfS_S_S_S_S_mf, .-_Z17process_particlesPfS_S_S_S_S_mf
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z6kernelPfS_S_S_S_S_if"
.LC1:
.string "q"
.LC2:
.string "m"
.LC3:
.string "B0"
.LC4:
.string "alpha"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z6kernelPfS_S_S_S_S_if(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $4, %r9d
movl $0, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _ZL1q(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $4, %r9d
movl $0, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _ZL1m(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $4, %r9d
movl $0, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _ZL2B0(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $4, %r9d
movl $0, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _ZL5alpha(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL8oldcount
.comm _ZL8oldcount,8,8
.local _ZL4d_vz
.comm _ZL4d_vz,8,8
.local _ZL4d_vy
.comm _ZL4d_vy,8,8
.local _ZL4d_vx
.comm _ZL4d_vx,8,8
.local _ZL3d_z
.comm _ZL3d_z,8,8
.local _ZL3d_y
.comm _ZL3d_y,8,8
.local _ZL3d_x
.comm _ZL3d_x,8,8
.local _ZL5alpha
.comm _ZL5alpha,4,4
.local _ZL2B0
.comm _ZL2B0,4,4
.local _ZL1m
.comm _ZL1m,4,4
.local _ZL1q
.comm _ZL1q,4,4
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <cuda.h>
#include <cuda_runtime.h>
__constant__ float q = 1.60217646e-19;
__constant__ float m = 9.10938188e-31;
__constant__ float B0 = 1e-12;
__constant__ float alpha = 250000;
__global__ void kernel(float* x, float* y, float* z,
float* vx, float* vy, float* vz, int count, float tau)
{
int i = blockDim.x * blockIdx.x + threadIdx.x;
if(i < count)
{
float r = sqrtf(x[i]*x[i]+y[i]*y[i]+z[i]*z[i]);
float Bx = 0;
float By = 0;
float Bz = -B0 * expf(-r*r / alpha);
float vx1 = vx[i]; float vy1 = vy[i]; float vz1 = vz[i];
vx[i] = vx1 + tau * q * (vy1 * Bz - vz1 * By) / m;
vy[i] = vy1 + tau * q * (vz1 * Bx - vx1 * Bz) / m;
vz[i] = vz1 + tau * q * (vx1 * By - vy1 * Bx) / m;
x[i] += vx[i] * tau;
y[i] += vy[i] * tau;
z[i] += vz[i] * tau;
}
}
static float *d_x = NULL, *d_y = NULL, *d_z = NULL,
*d_vx = NULL, *d_vy = NULL, *d_vz = NULL;
static size_t oldcount = 0;
__host__ void process_particles(float* x, float* y, float* z,
float* vx, float* vy, float*vz, size_t count, float tau)
{
int size = count * sizeof(float);
if(!d_x || oldcount != count)
{
cudaFree(d_x);
cudaMalloc(&d_x, size);
cudaFree(d_y);
cudaMalloc(&d_y, size);
cudaFree(d_z);
cudaMalloc(&d_z, size);
cudaFree(d_vx);
cudaMalloc(&d_vx, size);
cudaFree(d_vy);
cudaMalloc(&d_vy, size);
cudaFree(d_vz);
cudaMalloc(&d_vz, size);
oldcount = count;
}
cudaMemcpy(d_x, x, size, cudaMemcpyHostToDevice);
cudaMemcpy(d_y, y, size, cudaMemcpyHostToDevice);
cudaMemcpy(d_z, z, size, cudaMemcpyHostToDevice);
cudaMemcpy(d_vx, vx, size, cudaMemcpyHostToDevice);
cudaMemcpy(d_vy, vy, size, cudaMemcpyHostToDevice);
cudaMemcpy(d_vz, vz, size, cudaMemcpyHostToDevice);
kernel<<<count / 256 + 1, 256>>>(d_x, d_y, d_z, d_vx, d_vy, d_vz, count, tau);
cudaMemcpy(x, d_x, size, cudaMemcpyDeviceToHost);
cudaMemcpy(y, d_y, size, cudaMemcpyDeviceToHost);
cudaMemcpy(z, d_z, size, cudaMemcpyDeviceToHost);
cudaMemcpy(vx, d_vx, size, cudaMemcpyDeviceToHost);
cudaMemcpy(vy, d_vy, size, cudaMemcpyDeviceToHost);
cudaMemcpy(vz, d_vz, size, cudaMemcpyDeviceToHost);
} | #include <hip/hip_runtime.h>
__constant__ float q = 1.60217646e-19;
__constant__ float m = 9.10938188e-31;
__constant__ float B0 = 1e-12;
__constant__ float alpha = 250000;
__global__ void kernel(float* x, float* y, float* z,
float* vx, float* vy, float* vz, int count, float tau)
{
int i = blockDim.x * blockIdx.x + threadIdx.x;
if(i < count)
{
float r = sqrtf(x[i]*x[i]+y[i]*y[i]+z[i]*z[i]);
float Bx = 0;
float By = 0;
float Bz = -B0 * expf(-r*r / alpha);
float vx1 = vx[i]; float vy1 = vy[i]; float vz1 = vz[i];
vx[i] = vx1 + tau * q * (vy1 * Bz - vz1 * By) / m;
vy[i] = vy1 + tau * q * (vz1 * Bx - vx1 * Bz) / m;
vz[i] = vz1 + tau * q * (vx1 * By - vy1 * Bx) / m;
x[i] += vx[i] * tau;
y[i] += vy[i] * tau;
z[i] += vz[i] * tau;
}
}
static float *d_x = NULL, *d_y = NULL, *d_z = NULL,
*d_vx = NULL, *d_vy = NULL, *d_vz = NULL;
static size_t oldcount = 0;
__host__ void process_particles(float* x, float* y, float* z,
float* vx, float* vy, float*vz, size_t count, float tau)
{
int size = count * sizeof(float);
if(!d_x || oldcount != count)
{
hipFree(d_x);
hipMalloc(&d_x, size);
hipFree(d_y);
hipMalloc(&d_y, size);
hipFree(d_z);
hipMalloc(&d_z, size);
hipFree(d_vx);
hipMalloc(&d_vx, size);
hipFree(d_vy);
hipMalloc(&d_vy, size);
hipFree(d_vz);
hipMalloc(&d_vz, size);
oldcount = count;
}
hipMemcpy(d_x, x, size, hipMemcpyHostToDevice);
hipMemcpy(d_y, y, size, hipMemcpyHostToDevice);
hipMemcpy(d_z, z, size, hipMemcpyHostToDevice);
hipMemcpy(d_vx, vx, size, hipMemcpyHostToDevice);
hipMemcpy(d_vy, vy, size, hipMemcpyHostToDevice);
hipMemcpy(d_vz, vz, size, hipMemcpyHostToDevice);
kernel<<<count / 256 + 1, 256>>>(d_x, d_y, d_z, d_vx, d_vy, d_vz, count, tau);
hipMemcpy(x, d_x, size, hipMemcpyDeviceToHost);
hipMemcpy(y, d_y, size, hipMemcpyDeviceToHost);
hipMemcpy(z, d_z, size, hipMemcpyDeviceToHost);
hipMemcpy(vx, d_vx, size, hipMemcpyDeviceToHost);
hipMemcpy(vy, d_vy, size, hipMemcpyDeviceToHost);
hipMemcpy(vz, d_vz, size, hipMemcpyDeviceToHost);
} |
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.