system stringclasses 7 values | input stringlengths 10 94.5k | output stringlengths 14 55.5k |
|---|---|---|
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
__constant__ float q = 1.60217646e-19;
__constant__ float m = 9.10938188e-31;
__constant__ float B0 = 1e-12;
__constant__ float alpha = 250000;
__global__ void kernel(float* x, float* y, float* z,
float* vx, float* vy, float* vz, int count, float tau)
{
int i = blockDim.x * blockIdx.x + threadIdx.x;
if(i < count)
{
float r = sqrtf(x[i]*x[i]+y[i]*y[i]+z[i]*z[i]);
float Bx = 0;
float By = 0;
float Bz = -B0 * expf(-r*r / alpha);
float vx1 = vx[i]; float vy1 = vy[i]; float vz1 = vz[i];
vx[i] = vx1 + tau * q * (vy1 * Bz - vz1 * By) / m;
vy[i] = vy1 + tau * q * (vz1 * Bx - vx1 * Bz) / m;
vz[i] = vz1 + tau * q * (vx1 * By - vy1 * Bx) / m;
x[i] += vx[i] * tau;
y[i] += vy[i] * tau;
z[i] += vz[i] * tau;
}
}
static float *d_x = NULL, *d_y = NULL, *d_z = NULL,
*d_vx = NULL, *d_vy = NULL, *d_vz = NULL;
static size_t oldcount = 0;
__host__ void process_particles(float* x, float* y, float* z,
float* vx, float* vy, float*vz, size_t count, float tau)
{
int size = count * sizeof(float);
if(!d_x || oldcount != count)
{
hipFree(d_x);
hipMalloc(&d_x, size);
hipFree(d_y);
hipMalloc(&d_y, size);
hipFree(d_z);
hipMalloc(&d_z, size);
hipFree(d_vx);
hipMalloc(&d_vx, size);
hipFree(d_vy);
hipMalloc(&d_vy, size);
hipFree(d_vz);
hipMalloc(&d_vz, size);
oldcount = count;
}
hipMemcpy(d_x, x, size, hipMemcpyHostToDevice);
hipMemcpy(d_y, y, size, hipMemcpyHostToDevice);
hipMemcpy(d_z, z, size, hipMemcpyHostToDevice);
hipMemcpy(d_vx, vx, size, hipMemcpyHostToDevice);
hipMemcpy(d_vy, vy, size, hipMemcpyHostToDevice);
hipMemcpy(d_vz, vz, size, hipMemcpyHostToDevice);
kernel<<<count / 256 + 1, 256>>>(d_x, d_y, d_z, d_vx, d_vy, d_vz, count, tau);
hipMemcpy(x, d_x, size, hipMemcpyDeviceToHost);
hipMemcpy(y, d_y, size, hipMemcpyDeviceToHost);
hipMemcpy(z, d_z, size, hipMemcpyDeviceToHost);
hipMemcpy(vx, d_vx, size, hipMemcpyDeviceToHost);
hipMemcpy(vy, d_vy, size, hipMemcpyDeviceToHost);
hipMemcpy(vz, d_vz, size, hipMemcpyDeviceToHost);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6kernelPfS_S_S_S_S_if
.globl _Z6kernelPfS_S_S_S_S_if
.p2align 8
.type _Z6kernelPfS_S_S_S_S_if,@function
_Z6kernelPfS_S_S_S_S_if:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x44
s_load_b32 s3, s[0:1], 0x30
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b256 s[4:11], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s6, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v1, vcc_lo
global_load_b32 v12, v[2:3], off
v_add_co_u32 v6, vcc_lo, s8, v0
v_add_co_ci_u32_e32 v7, vcc_lo, s9, v1, vcc_lo
global_load_b32 v13, v[4:5], off
global_load_b32 v14, v[6:7], off
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x20
s_load_b32 s2, s[0:1], 0x34
s_waitcnt lgkmcnt(0)
v_add_co_u32 v8, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v9, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v10, vcc_lo, s10, v0
v_add_co_ci_u32_e32 v11, vcc_lo, s11, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
global_load_b32 v15, v[8:9], off
global_load_b32 v16, v[10:11], off
global_load_b32 v17, v[0:1], off
s_getpc_b64 s[4:5]
s_add_u32 s4, s4, alpha@rel32@lo+4
s_addc_u32 s5, s5, alpha@rel32@hi+12
s_waitcnt vmcnt(5)
v_mul_f32_e32 v12, v12, v12
s_waitcnt vmcnt(4)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v12, v13, v13
s_waitcnt vmcnt(3)
v_fmac_f32_e32 v12, v14, v14
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_f32_e32 v13, 0x4f800000, v12
v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v12
v_cndmask_b32_e32 v12, v12, v13, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_sqrt_f32_e32 v13, v12
s_waitcnt_depctr 0xfff
v_add_nc_u32_e32 v14, -1, v13
v_add_nc_u32_e32 v18, 1, v13
v_fma_f32 v19, -v14, v13, v12
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v20, -v18, v13, v12
v_cmp_ge_f32_e64 s0, 0, v19
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cndmask_b32_e64 v13, v13, v14, s0
v_cmp_lt_f32_e64 s0, 0, v20
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cndmask_b32_e64 v13, v13, v18, s0
s_load_b32 s0, s[4:5], 0x0
v_mul_f32_e32 v14, 0x37800000, v13
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v13, v13, v14, vcc_lo
v_cmp_class_f32_e64 vcc_lo, v12, 0x260
v_cndmask_b32_e32 v12, v13, v12, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mul_f32_e64 v12, v12, -v12
s_waitcnt lgkmcnt(0)
v_div_scale_f32 v13, null, s0, s0, v12
v_div_scale_f32 v19, vcc_lo, v12, s0, v12
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v14, v13
s_waitcnt_depctr 0xfff
v_fma_f32 v18, -v13, v14, 1.0
v_fmac_f32_e32 v14, v18, v14
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v18, v19, v14
v_fma_f32 v20, -v13, v18, v19
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v18, v20, v14
v_fma_f32 v13, -v13, v18, v19
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fmas_f32 v13, v13, v14, v18
v_div_fixup_f32 v12, v13, s0, v12
s_getpc_b64 s[0:1]
s_add_u32 s0, s0, q@rel32@lo+4
s_addc_u32 s1, s1, q@rel32@hi+12
s_getpc_b64 s[4:5]
s_add_u32 s4, s4, B0@rel32@lo+4
s_addc_u32 s5, s5, B0@rel32@hi+12
s_load_b32 s3, s[0:1], 0x0
s_load_b32 s4, s[4:5], 0x0
v_mul_f32_e32 v13, 0x3fb8aa3b, v12
v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v12
s_getpc_b64 s[0:1]
s_add_u32 s0, s0, m@rel32@lo+4
s_addc_u32 s1, s1, m@rel32@hi+12
s_load_b32 s5, s[0:1], 0x0
v_fma_f32 v14, v12, 0x3fb8aa3b, -v13
v_rndne_f32_e32 v18, v13
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_fmamk_f32 v14, v12, 0x32a5705f, v14 :: v_dual_sub_f32 v13, v13, v18
v_add_f32_e32 v13, v13, v14
v_cvt_i32_f32_e32 v14, v18
s_waitcnt vmcnt(0)
v_mul_f32_e32 v18, 0, v17
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_exp_f32_e32 v13, v13
s_waitcnt_depctr 0xfff
v_ldexp_f32 v13, v13, v14
v_dual_mul_f32 v14, 0, v15 :: v_dual_cndmask_b32 v13, 0, v13
v_cmp_nlt_f32_e32 vcc_lo, 0x42b17218, v12
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fma_f32 v14, v16, 0, -v14
v_cndmask_b32_e32 v12, 0x7f800000, v13, vcc_lo
s_waitcnt lgkmcnt(0)
v_mul_f32_e64 v13, s3, s2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_f32_e64 v12, v12, -s4
v_mul_f32_e32 v14, v14, v13
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_fma_f32 v19, v15, v12, -v18
v_fma_f32 v12, -v16, v12, v18
v_div_scale_f32 v18, null, s5, s5, v14
v_div_scale_f32 v25, s0, v14, s5, v14
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_mul_f32_e32 v19, v13, v19
v_mul_f32_e32 v12, v13, v12
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
v_rcp_f32_e32 v13, v18
v_div_scale_f32 v20, null, s5, s5, v19
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_div_scale_f32 v21, null, s5, s5, v12
v_div_scale_f32 v27, vcc_lo, v19, s5, v19
v_rcp_f32_e32 v22, v20
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(TRANS32_DEP_3)
v_rcp_f32_e32 v23, v21
v_fma_f32 v24, -v18, v13, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_3)
v_fmac_f32_e32 v13, v24, v13
s_waitcnt_depctr 0xfff
v_fma_f32 v26, -v20, v22, 1.0
v_fma_f32 v24, -v21, v23, 1.0
v_mul_f32_e32 v28, v25, v13
v_fmac_f32_e32 v22, v26, v22
v_div_scale_f32 v26, s1, v12, s5, v12
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_fmac_f32_e32 v23, v24, v23
v_fma_f32 v31, -v18, v28, v25
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_dual_mul_f32 v24, v27, v22 :: v_dual_mul_f32 v29, v26, v23
v_fmac_f32_e32 v28, v31, v13
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fma_f32 v30, -v20, v24, v27
v_fma_f32 v32, -v21, v29, v26
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v18, -v18, v28, v25
v_dual_fmac_f32 v24, v30, v22 :: v_dual_fmac_f32 v29, v32, v23
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v20, -v20, v24, v27
v_fma_f32 v21, -v21, v29, v26
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_div_fmas_f32 v20, v20, v22, v24
s_mov_b32 vcc_lo, s1
v_div_fmas_f32 v21, v21, v23, v29
s_mov_b32 vcc_lo, s0
v_div_fmas_f32 v13, v18, v13, v28
v_div_fixup_f32 v18, v20, s5, v19
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_div_fixup_f32 v12, v21, s5, v12
v_div_fixup_f32 v13, v13, s5, v14
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f32_e32 v14, v16, v18
v_dual_add_f32 v12, v15, v12 :: v_dual_add_f32 v13, v17, v13
global_store_b32 v[10:11], v14, off
global_store_b32 v[8:9], v12, off
global_store_b32 v[0:1], v13, off
global_load_b32 v10, v[10:11], off
global_load_b32 v11, v[4:5], off
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v11, s2, v10
global_store_b32 v[4:5], v11, off
global_load_b32 v4, v[8:9], off
global_load_b32 v5, v[2:3], off
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v5, s2, v4
global_store_b32 v[2:3], v5, off
global_load_b32 v0, v[0:1], off
global_load_b32 v1, v[6:7], off
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v1, s2, v0
global_store_b32 v[6:7], v1, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6kernelPfS_S_S_S_S_if
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 312
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 33
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6kernelPfS_S_S_S_S_if, .Lfunc_end0-_Z6kernelPfS_S_S_S_S_if
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.protected q
.type q,@object
.data
.globl q
.p2align 2, 0x0
q:
.long 0x203d26d0
.size q, 4
.protected m
.type m,@object
.globl m
.p2align 2, 0x0
m:
.long 0x0d93cee4
.size m, 4
.protected B0
.type B0,@object
.globl B0
.p2align 2, 0x0
B0:
.long 0x2b8cbccc
.size B0, 4
.protected alpha
.type alpha,@object
.globl alpha
.p2align 2, 0x0
alpha:
.long 0x48742400
.size alpha, 4
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym q
.addrsig_sym m
.addrsig_sym B0
.addrsig_sym alpha
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
- .offset: 48
.size: 4
.value_kind: by_value
- .offset: 52
.size: 4
.value_kind: by_value
- .offset: 56
.size: 4
.value_kind: hidden_block_count_x
- .offset: 60
.size: 4
.value_kind: hidden_block_count_y
- .offset: 64
.size: 4
.value_kind: hidden_block_count_z
- .offset: 68
.size: 2
.value_kind: hidden_group_size_x
- .offset: 70
.size: 2
.value_kind: hidden_group_size_y
- .offset: 72
.size: 2
.value_kind: hidden_group_size_z
- .offset: 74
.size: 2
.value_kind: hidden_remainder_x
- .offset: 76
.size: 2
.value_kind: hidden_remainder_y
- .offset: 78
.size: 2
.value_kind: hidden_remainder_z
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 112
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 120
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 312
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6kernelPfS_S_S_S_S_if
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6kernelPfS_S_S_S_S_if.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 33
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
__constant__ float q = 1.60217646e-19;
__constant__ float m = 9.10938188e-31;
__constant__ float B0 = 1e-12;
__constant__ float alpha = 250000;
__global__ void kernel(float* x, float* y, float* z,
float* vx, float* vy, float* vz, int count, float tau)
{
int i = blockDim.x * blockIdx.x + threadIdx.x;
if(i < count)
{
float r = sqrtf(x[i]*x[i]+y[i]*y[i]+z[i]*z[i]);
float Bx = 0;
float By = 0;
float Bz = -B0 * expf(-r*r / alpha);
float vx1 = vx[i]; float vy1 = vy[i]; float vz1 = vz[i];
vx[i] = vx1 + tau * q * (vy1 * Bz - vz1 * By) / m;
vy[i] = vy1 + tau * q * (vz1 * Bx - vx1 * Bz) / m;
vz[i] = vz1 + tau * q * (vx1 * By - vy1 * Bx) / m;
x[i] += vx[i] * tau;
y[i] += vy[i] * tau;
z[i] += vz[i] * tau;
}
}
static float *d_x = NULL, *d_y = NULL, *d_z = NULL,
*d_vx = NULL, *d_vy = NULL, *d_vz = NULL;
static size_t oldcount = 0;
__host__ void process_particles(float* x, float* y, float* z,
float* vx, float* vy, float*vz, size_t count, float tau)
{
int size = count * sizeof(float);
if(!d_x || oldcount != count)
{
hipFree(d_x);
hipMalloc(&d_x, size);
hipFree(d_y);
hipMalloc(&d_y, size);
hipFree(d_z);
hipMalloc(&d_z, size);
hipFree(d_vx);
hipMalloc(&d_vx, size);
hipFree(d_vy);
hipMalloc(&d_vy, size);
hipFree(d_vz);
hipMalloc(&d_vz, size);
oldcount = count;
}
hipMemcpy(d_x, x, size, hipMemcpyHostToDevice);
hipMemcpy(d_y, y, size, hipMemcpyHostToDevice);
hipMemcpy(d_z, z, size, hipMemcpyHostToDevice);
hipMemcpy(d_vx, vx, size, hipMemcpyHostToDevice);
hipMemcpy(d_vy, vy, size, hipMemcpyHostToDevice);
hipMemcpy(d_vz, vz, size, hipMemcpyHostToDevice);
kernel<<<count / 256 + 1, 256>>>(d_x, d_y, d_z, d_vx, d_vy, d_vz, count, tau);
hipMemcpy(x, d_x, size, hipMemcpyDeviceToHost);
hipMemcpy(y, d_y, size, hipMemcpyDeviceToHost);
hipMemcpy(z, d_z, size, hipMemcpyDeviceToHost);
hipMemcpy(vx, d_vx, size, hipMemcpyDeviceToHost);
hipMemcpy(vy, d_vy, size, hipMemcpyDeviceToHost);
hipMemcpy(vz, d_vz, size, hipMemcpyDeviceToHost);
} | .text
.file "particles.hip"
.globl _Z21__device_stub__kernelPfS_S_S_S_S_if # -- Begin function _Z21__device_stub__kernelPfS_S_S_S_S_if
.p2align 4, 0x90
.type _Z21__device_stub__kernelPfS_S_S_S_S_if,@function
_Z21__device_stub__kernelPfS_S_S_S_S_if: # @_Z21__device_stub__kernelPfS_S_S_S_S_if
.cfi_startproc
# %bb.0:
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 104(%rsp)
movq %rsi, 96(%rsp)
movq %rdx, 88(%rsp)
movq %rcx, 80(%rsp)
movq %r8, 72(%rsp)
movq %r9, 64(%rsp)
movss %xmm0, 12(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 80(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rax
movq %rax, 144(%rsp)
leaq 64(%rsp), %rax
movq %rax, 152(%rsp)
leaq 192(%rsp), %rax
movq %rax, 160(%rsp)
leaq 12(%rsp), %rax
movq %rax, 168(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z6kernelPfS_S_S_S_S_if, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $200, %rsp
.cfi_adjust_cfa_offset -200
retq
.Lfunc_end0:
.size _Z21__device_stub__kernelPfS_S_S_S_S_if, .Lfunc_end0-_Z21__device_stub__kernelPfS_S_S_S_S_if
.cfi_endproc
# -- End function
.globl _Z17process_particlesPfS_S_S_S_S_mf # -- Begin function _Z17process_particlesPfS_S_S_S_S_mf
.p2align 4, 0x90
.type _Z17process_particlesPfS_S_S_S_S_mf,@function
_Z17process_particlesPfS_S_S_S_S_mf: # @_Z17process_particlesPfS_S_S_S_S_mf
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $200, %rsp
.cfi_def_cfa_offset 256
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movss %xmm0, 12(%rsp) # 4-byte Spill
movq %r9, %r12
movq %r8, %r13
movq %rcx, %rbp
movq %rdx, %r14
movq %rsi, %rbx
movq %rdi, %rcx
movq 256(%rsp), %rax
leal (,%rax,4), %eax
movq _ZL3d_x(%rip), %rdi
movslq %eax, %r15
testq %rdi, %rdi
movq %rcx, 24(%rsp) # 8-byte Spill
je .LBB1_2
# %bb.1:
movq 256(%rsp), %rax
cmpq %rax, _ZL8oldcount(%rip)
je .LBB1_3
.LBB1_2:
callq hipFree
movl $_ZL3d_x, %edi
movq %r15, %rsi
callq hipMalloc
movq _ZL3d_y(%rip), %rdi
callq hipFree
movl $_ZL3d_y, %edi
movq %r15, %rsi
callq hipMalloc
movq _ZL3d_z(%rip), %rdi
callq hipFree
movl $_ZL3d_z, %edi
movq %r15, %rsi
callq hipMalloc
movq _ZL4d_vx(%rip), %rdi
callq hipFree
movl $_ZL4d_vx, %edi
movq %r15, %rsi
callq hipMalloc
movq _ZL4d_vy(%rip), %rdi
callq hipFree
movl $_ZL4d_vy, %edi
movq %r15, %rsi
callq hipMalloc
movq _ZL4d_vz(%rip), %rdi
callq hipFree
movl $_ZL4d_vz, %edi
movq %r15, %rsi
callq hipMalloc
movq 24(%rsp), %rcx # 8-byte Reload
movq 256(%rsp), %rax
movq %rax, _ZL8oldcount(%rip)
.LBB1_3:
movq _ZL3d_x(%rip), %rdi
movq %rcx, %rsi
movq %r15, %rdx
movl $1, %ecx
callq hipMemcpy
movq _ZL3d_y(%rip), %rdi
movq %rbx, %rsi
movq %r15, %rdx
movl $1, %ecx
callq hipMemcpy
movq _ZL3d_z(%rip), %rdi
movq %r14, %rsi
movq %r15, %rdx
movl $1, %ecx
callq hipMemcpy
movq _ZL4d_vx(%rip), %rdi
movq %rbp, %rsi
movq %r15, %rdx
movl $1, %ecx
callq hipMemcpy
movq _ZL4d_vy(%rip), %rdi
movq %r13, %rsi
movq %r15, %rdx
movl $1, %ecx
callq hipMemcpy
movq _ZL4d_vz(%rip), %rdi
movq %r12, %rsi
movq %r15, %rdx
movl $1, %ecx
callq hipMemcpy
movq 256(%rsp), %rdi
shrq $8, %rdi
incl %edi
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %rdi
orq $256, %rdx # imm = 0x100
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_5
# %bb.4:
movq _ZL3d_x(%rip), %rax
movq _ZL3d_y(%rip), %rcx
movq _ZL3d_z(%rip), %rdx
movq _ZL4d_vx(%rip), %rsi
movq _ZL4d_vy(%rip), %rdi
movq _ZL4d_vz(%rip), %r8
movq %rax, 120(%rsp)
movq %rcx, 112(%rsp)
movq %rdx, 104(%rsp)
movq %rsi, 96(%rsp)
movq %rdi, 88(%rsp)
movq %r8, 80(%rsp)
movq 256(%rsp), %rax
movl %eax, 20(%rsp)
movss 12(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
movss %xmm0, 16(%rsp)
leaq 120(%rsp), %rax
movq %rax, 128(%rsp)
leaq 112(%rsp), %rax
movq %rax, 136(%rsp)
leaq 104(%rsp), %rax
movq %rax, 144(%rsp)
leaq 96(%rsp), %rax
movq %rax, 152(%rsp)
leaq 88(%rsp), %rax
movq %rax, 160(%rsp)
leaq 80(%rsp), %rax
movq %rax, 168(%rsp)
leaq 20(%rsp), %rax
movq %rax, 176(%rsp)
leaq 16(%rsp), %rax
movq %rax, 184(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 128(%rsp), %r9
movl $_Z6kernelPfS_S_S_S_S_if, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_5:
movq _ZL3d_x(%rip), %rsi
movq 24(%rsp), %rdi # 8-byte Reload
movq %r15, %rdx
movl $2, %ecx
callq hipMemcpy
movq _ZL3d_y(%rip), %rsi
movq %rbx, %rdi
movq %r15, %rdx
movl $2, %ecx
callq hipMemcpy
movq _ZL3d_z(%rip), %rsi
movq %r14, %rdi
movq %r15, %rdx
movl $2, %ecx
callq hipMemcpy
movq _ZL4d_vx(%rip), %rsi
movq %rbp, %rdi
movq %r15, %rdx
movl $2, %ecx
callq hipMemcpy
movq _ZL4d_vy(%rip), %rsi
movq %r13, %rdi
movq %r15, %rdx
movl $2, %ecx
callq hipMemcpy
movq _ZL4d_vz(%rip), %rsi
movq %r12, %rdi
movq %r15, %rdx
movl $2, %ecx
callq hipMemcpy
addq $200, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z17process_particlesPfS_S_S_S_S_mf, .Lfunc_end1-_Z17process_particlesPfS_S_S_S_S_mf
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rbx
subq $32, %rsp
.cfi_adjust_cfa_offset 32
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6kernelPfS_S_S_S_S_if, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
addq $32, %rsp
.cfi_adjust_cfa_offset -32
movl $q, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movl $4, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
pushq $0
.cfi_adjust_cfa_offset 8
pushq $1
.cfi_adjust_cfa_offset 8
callq __hipRegisterVar
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movl $m, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movl $4, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
pushq $0
.cfi_adjust_cfa_offset 8
pushq $1
.cfi_adjust_cfa_offset 8
callq __hipRegisterVar
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movl $B0, %esi
movl $.L__unnamed_4, %edx
movl $.L__unnamed_4, %ecx
movl $4, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
pushq $0
.cfi_adjust_cfa_offset 8
pushq $1
.cfi_adjust_cfa_offset 8
callq __hipRegisterVar
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movl $alpha, %esi
movl $.L__unnamed_5, %edx
movl $.L__unnamed_5, %ecx
movl $4, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
pushq $0
.cfi_adjust_cfa_offset 8
pushq $1
.cfi_adjust_cfa_offset 8
callq __hipRegisterVar
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movl $__hip_module_dtor, %edi
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type q,@object # @q
.local q
.comm q,4,4
.type m,@object # @m
.local m
.comm m,4,4
.type B0,@object # @B0
.local B0
.comm B0,4,4
.type alpha,@object # @alpha
.local alpha
.comm alpha,4,4
.type _Z6kernelPfS_S_S_S_S_if,@object # @_Z6kernelPfS_S_S_S_S_if
.section .rodata,"a",@progbits
.globl _Z6kernelPfS_S_S_S_S_if
.p2align 3, 0x0
_Z6kernelPfS_S_S_S_S_if:
.quad _Z21__device_stub__kernelPfS_S_S_S_S_if
.size _Z6kernelPfS_S_S_S_S_if, 8
.type _ZL3d_x,@object # @_ZL3d_x
.local _ZL3d_x
.comm _ZL3d_x,8,8
.type _ZL8oldcount,@object # @_ZL8oldcount
.local _ZL8oldcount
.comm _ZL8oldcount,8,8
.type _ZL3d_y,@object # @_ZL3d_y
.local _ZL3d_y
.comm _ZL3d_y,8,8
.type _ZL3d_z,@object # @_ZL3d_z
.local _ZL3d_z
.comm _ZL3d_z,8,8
.type _ZL4d_vx,@object # @_ZL4d_vx
.local _ZL4d_vx
.comm _ZL4d_vx,8,8
.type _ZL4d_vy,@object # @_ZL4d_vy
.local _ZL4d_vy
.comm _ZL4d_vy,8,8
.type _ZL4d_vz,@object # @_ZL4d_vz
.local _ZL4d_vz
.comm _ZL4d_vz,8,8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z6kernelPfS_S_S_S_S_if"
.size .L__unnamed_1, 24
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "q"
.size .L__unnamed_2, 2
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "m"
.size .L__unnamed_3, 2
.type .L__unnamed_4,@object # @3
.L__unnamed_4:
.asciz "B0"
.size .L__unnamed_4, 3
.type .L__unnamed_5,@object # @4
.L__unnamed_5:
.asciz "alpha"
.size .L__unnamed_5, 6
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__kernelPfS_S_S_S_S_if
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym q
.addrsig_sym m
.addrsig_sym B0
.addrsig_sym alpha
.addrsig_sym _Z6kernelPfS_S_S_S_S_if
.addrsig_sym _ZL3d_x
.addrsig_sym _ZL3d_y
.addrsig_sym _ZL3d_z
.addrsig_sym _ZL4d_vx
.addrsig_sym _ZL4d_vy
.addrsig_sym _ZL4d_vz
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0015454b_00000000-6_particles.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z37__device_stub__Z6kernelPfS_S_S_S_S_ifPfS_S_S_S_S_if
.type _Z37__device_stub__Z6kernelPfS_S_S_S_S_ifPfS_S_S_S_S_if, @function
_Z37__device_stub__Z6kernelPfS_S_S_S_S_ifPfS_S_S_S_S_if:
.LFB2052:
.cfi_startproc
endbr64
subq $216, %rsp
.cfi_def_cfa_offset 224
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
movq %rdx, 40(%rsp)
movq %rcx, 32(%rsp)
movq %r8, 24(%rsp)
movq %r9, 16(%rsp)
movss %xmm0, 12(%rsp)
movq %fs:40, %rax
movq %rax, 200(%rsp)
xorl %eax, %eax
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 40(%rsp), %rax
movq %rax, 144(%rsp)
leaq 32(%rsp), %rax
movq %rax, 152(%rsp)
leaq 24(%rsp), %rax
movq %rax, 160(%rsp)
leaq 16(%rsp), %rax
movq %rax, 168(%rsp)
leaq 224(%rsp), %rax
movq %rax, 176(%rsp)
leaq 12(%rsp), %rax
movq %rax, 184(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 200(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $216, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 232
pushq 72(%rsp)
.cfi_def_cfa_offset 240
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq _Z6kernelPfS_S_S_S_S_if(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 224
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2052:
.size _Z37__device_stub__Z6kernelPfS_S_S_S_S_ifPfS_S_S_S_S_if, .-_Z37__device_stub__Z6kernelPfS_S_S_S_S_ifPfS_S_S_S_S_if
.globl _Z6kernelPfS_S_S_S_S_if
.type _Z6kernelPfS_S_S_S_S_if, @function
_Z6kernelPfS_S_S_S_S_if:
.LFB2053:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
call _Z37__device_stub__Z6kernelPfS_S_S_S_S_ifPfS_S_S_S_S_if
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _Z6kernelPfS_S_S_S_S_if, .-_Z6kernelPfS_S_S_S_S_if
.globl _Z17process_particlesPfS_S_S_S_S_mf
.type _Z17process_particlesPfS_S_S_S_S_mf, @function
_Z17process_particlesPfS_S_S_S_S_mf:
.LFB2027:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $72, %rsp
.cfi_def_cfa_offset 128
movq %rdi, %r14
movq %rsi, %r13
movq %rdx, %r12
movq %rcx, (%rsp)
movq %r8, 8(%rsp)
movq %r9, 16(%rsp)
movq 128(%rsp), %r15
movss %xmm0, 28(%rsp)
leal 0(,%r15,4), %ebx
movq _ZL3d_x(%rip), %rdi
testq %rdi, %rdi
je .L12
cmpq %r15, _ZL8oldcount(%rip)
je .L13
.L12:
call cudaFree@PLT
movslq %ebx, %rbp
movq %rbp, %rsi
leaq _ZL3d_x(%rip), %rdi
call cudaMalloc@PLT
movq _ZL3d_y(%rip), %rdi
call cudaFree@PLT
movq %rbp, %rsi
leaq _ZL3d_y(%rip), %rdi
call cudaMalloc@PLT
movq _ZL3d_z(%rip), %rdi
call cudaFree@PLT
movq %rbp, %rsi
leaq _ZL3d_z(%rip), %rdi
call cudaMalloc@PLT
movq _ZL4d_vx(%rip), %rdi
call cudaFree@PLT
movq %rbp, %rsi
leaq _ZL4d_vx(%rip), %rdi
call cudaMalloc@PLT
movq _ZL4d_vy(%rip), %rdi
call cudaFree@PLT
movq %rbp, %rsi
leaq _ZL4d_vy(%rip), %rdi
call cudaMalloc@PLT
movq _ZL4d_vz(%rip), %rdi
call cudaFree@PLT
movq %rbp, %rsi
leaq _ZL4d_vz(%rip), %rdi
call cudaMalloc@PLT
movq %r15, _ZL8oldcount(%rip)
.L13:
movslq %ebx, %rbx
movl $1, %ecx
movq %rbx, %rdx
movq %r14, %rsi
movq _ZL3d_x(%rip), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %r13, %rsi
movq _ZL3d_y(%rip), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %r12, %rsi
movq _ZL3d_z(%rip), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %rbx, %rdx
movq (%rsp), %rsi
movq _ZL4d_vx(%rip), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %rbx, %rdx
movq 8(%rsp), %rsi
movq _ZL4d_vy(%rip), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %rbx, %rdx
movq 16(%rsp), %rsi
movq _ZL4d_vz(%rip), %rdi
call cudaMemcpy@PLT
movl $256, 52(%rsp)
movl $1, 56(%rsp)
movq %r15, %rax
shrq $8, %rax
addl $1, %eax
movl %eax, 40(%rsp)
movl $1, 44(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 52(%rsp), %rdx
movl $1, %ecx
movq 40(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L16
.L14:
movl $2, %ecx
movq %rbx, %rdx
movq _ZL3d_x(%rip), %rsi
movq %r14, %rdi
call cudaMemcpy@PLT
movl $2, %ecx
movq %rbx, %rdx
movq _ZL3d_y(%rip), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
movl $2, %ecx
movq %rbx, %rdx
movq _ZL3d_z(%rip), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movl $2, %ecx
movq %rbx, %rdx
movq _ZL4d_vx(%rip), %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
movl $2, %ecx
movq %rbx, %rdx
movq _ZL4d_vy(%rip), %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $2, %ecx
movq %rbx, %rdx
movq _ZL4d_vz(%rip), %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L16:
.cfi_restore_state
subq $8, %rsp
.cfi_def_cfa_offset 136
pushq %r15
.cfi_def_cfa_offset 144
movss 44(%rsp), %xmm0
movq _ZL4d_vz(%rip), %r9
movq _ZL4d_vy(%rip), %r8
movq _ZL4d_vx(%rip), %rcx
movq _ZL3d_z(%rip), %rdx
movq _ZL3d_y(%rip), %rsi
movq _ZL3d_x(%rip), %rdi
call _Z37__device_stub__Z6kernelPfS_S_S_S_S_ifPfS_S_S_S_S_if
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L14
.cfi_endproc
.LFE2027:
.size _Z17process_particlesPfS_S_S_S_S_mf, .-_Z17process_particlesPfS_S_S_S_S_mf
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z6kernelPfS_S_S_S_S_if"
.LC1:
.string "q"
.LC2:
.string "m"
.LC3:
.string "B0"
.LC4:
.string "alpha"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z6kernelPfS_S_S_S_S_if(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $4, %r9d
movl $0, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _ZL1q(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $4, %r9d
movl $0, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _ZL1m(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $4, %r9d
movl $0, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _ZL2B0(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $4, %r9d
movl $0, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _ZL5alpha(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL8oldcount
.comm _ZL8oldcount,8,8
.local _ZL4d_vz
.comm _ZL4d_vz,8,8
.local _ZL4d_vy
.comm _ZL4d_vy,8,8
.local _ZL4d_vx
.comm _ZL4d_vx,8,8
.local _ZL3d_z
.comm _ZL3d_z,8,8
.local _ZL3d_y
.comm _ZL3d_y,8,8
.local _ZL3d_x
.comm _ZL3d_x,8,8
.local _ZL5alpha
.comm _ZL5alpha,4,4
.local _ZL2B0
.comm _ZL2B0,4,4
.local _ZL1m
.comm _ZL1m,4,4
.local _ZL1q
.comm _ZL1q,4,4
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "particles.hip"
.globl _Z21__device_stub__kernelPfS_S_S_S_S_if # -- Begin function _Z21__device_stub__kernelPfS_S_S_S_S_if
.p2align 4, 0x90
.type _Z21__device_stub__kernelPfS_S_S_S_S_if,@function
_Z21__device_stub__kernelPfS_S_S_S_S_if: # @_Z21__device_stub__kernelPfS_S_S_S_S_if
.cfi_startproc
# %bb.0:
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 104(%rsp)
movq %rsi, 96(%rsp)
movq %rdx, 88(%rsp)
movq %rcx, 80(%rsp)
movq %r8, 72(%rsp)
movq %r9, 64(%rsp)
movss %xmm0, 12(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 80(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rax
movq %rax, 144(%rsp)
leaq 64(%rsp), %rax
movq %rax, 152(%rsp)
leaq 192(%rsp), %rax
movq %rax, 160(%rsp)
leaq 12(%rsp), %rax
movq %rax, 168(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z6kernelPfS_S_S_S_S_if, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $200, %rsp
.cfi_adjust_cfa_offset -200
retq
.Lfunc_end0:
.size _Z21__device_stub__kernelPfS_S_S_S_S_if, .Lfunc_end0-_Z21__device_stub__kernelPfS_S_S_S_S_if
.cfi_endproc
# -- End function
.globl _Z17process_particlesPfS_S_S_S_S_mf # -- Begin function _Z17process_particlesPfS_S_S_S_S_mf
.p2align 4, 0x90
.type _Z17process_particlesPfS_S_S_S_S_mf,@function
_Z17process_particlesPfS_S_S_S_S_mf: # @_Z17process_particlesPfS_S_S_S_S_mf
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $200, %rsp
.cfi_def_cfa_offset 256
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movss %xmm0, 12(%rsp) # 4-byte Spill
movq %r9, %r12
movq %r8, %r13
movq %rcx, %rbp
movq %rdx, %r14
movq %rsi, %rbx
movq %rdi, %rcx
movq 256(%rsp), %rax
leal (,%rax,4), %eax
movq _ZL3d_x(%rip), %rdi
movslq %eax, %r15
testq %rdi, %rdi
movq %rcx, 24(%rsp) # 8-byte Spill
je .LBB1_2
# %bb.1:
movq 256(%rsp), %rax
cmpq %rax, _ZL8oldcount(%rip)
je .LBB1_3
.LBB1_2:
callq hipFree
movl $_ZL3d_x, %edi
movq %r15, %rsi
callq hipMalloc
movq _ZL3d_y(%rip), %rdi
callq hipFree
movl $_ZL3d_y, %edi
movq %r15, %rsi
callq hipMalloc
movq _ZL3d_z(%rip), %rdi
callq hipFree
movl $_ZL3d_z, %edi
movq %r15, %rsi
callq hipMalloc
movq _ZL4d_vx(%rip), %rdi
callq hipFree
movl $_ZL4d_vx, %edi
movq %r15, %rsi
callq hipMalloc
movq _ZL4d_vy(%rip), %rdi
callq hipFree
movl $_ZL4d_vy, %edi
movq %r15, %rsi
callq hipMalloc
movq _ZL4d_vz(%rip), %rdi
callq hipFree
movl $_ZL4d_vz, %edi
movq %r15, %rsi
callq hipMalloc
movq 24(%rsp), %rcx # 8-byte Reload
movq 256(%rsp), %rax
movq %rax, _ZL8oldcount(%rip)
.LBB1_3:
movq _ZL3d_x(%rip), %rdi
movq %rcx, %rsi
movq %r15, %rdx
movl $1, %ecx
callq hipMemcpy
movq _ZL3d_y(%rip), %rdi
movq %rbx, %rsi
movq %r15, %rdx
movl $1, %ecx
callq hipMemcpy
movq _ZL3d_z(%rip), %rdi
movq %r14, %rsi
movq %r15, %rdx
movl $1, %ecx
callq hipMemcpy
movq _ZL4d_vx(%rip), %rdi
movq %rbp, %rsi
movq %r15, %rdx
movl $1, %ecx
callq hipMemcpy
movq _ZL4d_vy(%rip), %rdi
movq %r13, %rsi
movq %r15, %rdx
movl $1, %ecx
callq hipMemcpy
movq _ZL4d_vz(%rip), %rdi
movq %r12, %rsi
movq %r15, %rdx
movl $1, %ecx
callq hipMemcpy
movq 256(%rsp), %rdi
shrq $8, %rdi
incl %edi
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %rdi
orq $256, %rdx # imm = 0x100
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_5
# %bb.4:
movq _ZL3d_x(%rip), %rax
movq _ZL3d_y(%rip), %rcx
movq _ZL3d_z(%rip), %rdx
movq _ZL4d_vx(%rip), %rsi
movq _ZL4d_vy(%rip), %rdi
movq _ZL4d_vz(%rip), %r8
movq %rax, 120(%rsp)
movq %rcx, 112(%rsp)
movq %rdx, 104(%rsp)
movq %rsi, 96(%rsp)
movq %rdi, 88(%rsp)
movq %r8, 80(%rsp)
movq 256(%rsp), %rax
movl %eax, 20(%rsp)
movss 12(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
movss %xmm0, 16(%rsp)
leaq 120(%rsp), %rax
movq %rax, 128(%rsp)
leaq 112(%rsp), %rax
movq %rax, 136(%rsp)
leaq 104(%rsp), %rax
movq %rax, 144(%rsp)
leaq 96(%rsp), %rax
movq %rax, 152(%rsp)
leaq 88(%rsp), %rax
movq %rax, 160(%rsp)
leaq 80(%rsp), %rax
movq %rax, 168(%rsp)
leaq 20(%rsp), %rax
movq %rax, 176(%rsp)
leaq 16(%rsp), %rax
movq %rax, 184(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 128(%rsp), %r9
movl $_Z6kernelPfS_S_S_S_S_if, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_5:
movq _ZL3d_x(%rip), %rsi
movq 24(%rsp), %rdi # 8-byte Reload
movq %r15, %rdx
movl $2, %ecx
callq hipMemcpy
movq _ZL3d_y(%rip), %rsi
movq %rbx, %rdi
movq %r15, %rdx
movl $2, %ecx
callq hipMemcpy
movq _ZL3d_z(%rip), %rsi
movq %r14, %rdi
movq %r15, %rdx
movl $2, %ecx
callq hipMemcpy
movq _ZL4d_vx(%rip), %rsi
movq %rbp, %rdi
movq %r15, %rdx
movl $2, %ecx
callq hipMemcpy
movq _ZL4d_vy(%rip), %rsi
movq %r13, %rdi
movq %r15, %rdx
movl $2, %ecx
callq hipMemcpy
movq _ZL4d_vz(%rip), %rsi
movq %r12, %rdi
movq %r15, %rdx
movl $2, %ecx
callq hipMemcpy
addq $200, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z17process_particlesPfS_S_S_S_S_mf, .Lfunc_end1-_Z17process_particlesPfS_S_S_S_S_mf
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rbx
subq $32, %rsp
.cfi_adjust_cfa_offset 32
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6kernelPfS_S_S_S_S_if, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
addq $32, %rsp
.cfi_adjust_cfa_offset -32
movl $q, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movl $4, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
pushq $0
.cfi_adjust_cfa_offset 8
pushq $1
.cfi_adjust_cfa_offset 8
callq __hipRegisterVar
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movl $m, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movl $4, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
pushq $0
.cfi_adjust_cfa_offset 8
pushq $1
.cfi_adjust_cfa_offset 8
callq __hipRegisterVar
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movl $B0, %esi
movl $.L__unnamed_4, %edx
movl $.L__unnamed_4, %ecx
movl $4, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
pushq $0
.cfi_adjust_cfa_offset 8
pushq $1
.cfi_adjust_cfa_offset 8
callq __hipRegisterVar
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movl $alpha, %esi
movl $.L__unnamed_5, %edx
movl $.L__unnamed_5, %ecx
movl $4, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
pushq $0
.cfi_adjust_cfa_offset 8
pushq $1
.cfi_adjust_cfa_offset 8
callq __hipRegisterVar
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movl $__hip_module_dtor, %edi
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type q,@object # @q
.local q
.comm q,4,4
.type m,@object # @m
.local m
.comm m,4,4
.type B0,@object # @B0
.local B0
.comm B0,4,4
.type alpha,@object # @alpha
.local alpha
.comm alpha,4,4
.type _Z6kernelPfS_S_S_S_S_if,@object # @_Z6kernelPfS_S_S_S_S_if
.section .rodata,"a",@progbits
.globl _Z6kernelPfS_S_S_S_S_if
.p2align 3, 0x0
_Z6kernelPfS_S_S_S_S_if:
.quad _Z21__device_stub__kernelPfS_S_S_S_S_if
.size _Z6kernelPfS_S_S_S_S_if, 8
.type _ZL3d_x,@object # @_ZL3d_x
.local _ZL3d_x
.comm _ZL3d_x,8,8
.type _ZL8oldcount,@object # @_ZL8oldcount
.local _ZL8oldcount
.comm _ZL8oldcount,8,8
.type _ZL3d_y,@object # @_ZL3d_y
.local _ZL3d_y
.comm _ZL3d_y,8,8
.type _ZL3d_z,@object # @_ZL3d_z
.local _ZL3d_z
.comm _ZL3d_z,8,8
.type _ZL4d_vx,@object # @_ZL4d_vx
.local _ZL4d_vx
.comm _ZL4d_vx,8,8
.type _ZL4d_vy,@object # @_ZL4d_vy
.local _ZL4d_vy
.comm _ZL4d_vy,8,8
.type _ZL4d_vz,@object # @_ZL4d_vz
.local _ZL4d_vz
.comm _ZL4d_vz,8,8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z6kernelPfS_S_S_S_S_if"
.size .L__unnamed_1, 24
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "q"
.size .L__unnamed_2, 2
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "m"
.size .L__unnamed_3, 2
.type .L__unnamed_4,@object # @3
.L__unnamed_4:
.asciz "B0"
.size .L__unnamed_4, 3
.type .L__unnamed_5,@object # @4
.L__unnamed_5:
.asciz "alpha"
.size .L__unnamed_5, 6
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__kernelPfS_S_S_S_S_if
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym q
.addrsig_sym m
.addrsig_sym B0
.addrsig_sym alpha
.addrsig_sym _Z6kernelPfS_S_S_S_S_if
.addrsig_sym _ZL3d_x
.addrsig_sym _ZL3d_y
.addrsig_sym _ZL3d_z
.addrsig_sym _ZL4d_vx
.addrsig_sym _ZL4d_vy
.addrsig_sym _ZL4d_vz
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <cuda_runtime_api.h>
#include <time.h>
__device__ int is_a_match(char * attempt) {
char password1[] = "AP25";
char password2[] = "AN52";
char password3[] = "RA25";
char password4[] = "RC80";
char * a = attempt;
char * b = attempt;
char * c = attempt;
char * d = attempt;
char * pass1 = password1;
char * pass2 = password2;
char * pass3 = password3;
char * pass4 = password4;
while ( * a == * pass1) {
if ( * a == '\0') {
printf("password:%s\n", password1);
break;
}
a++;
pass1++;
}
while ( * b == * pass2) {
if ( * b == '\0') {
printf("password:%s\n", password2);
break;
}
b++;
pass2++;
}
while ( * c == * pass3) {
if ( * c == '\0') {
printf("password:%s\n", password3);
break;
}
c++;
pass3++;
}
while ( * d == * pass4) {
if ( * d == '\0') {
printf("password: %s\n", password4);
return 1;
}
d++;
pass4++;
}
return 0;
}
__global__ void kernel() {
char i1, i2;
char password[7];
password[6] = '\0';
int i = blockIdx.x + 65;
int j = threadIdx.x + 65;
char firstMatch = i;
char secondMatch = j;
password[0] = firstMatch;
password[1] = secondMatch;
for (i1 = '0'; i1 <= '9'; i1++) {
for (i2 = '0'; i2 <= '9'; i2++) {
password[2] = i1;
password[3] = i2;
if (is_a_match(password)) {} else {
//printf("tried: %s\n",password);
}
}
}
}
int time_difference(struct timespec * start, struct timespec * finish, long long int * difference) {
long long int ds = finish -> tv_sec - start -> tv_sec;
long long int dn = finish -> tv_nsec - start -> tv_nsec;
if (dn < 0) {
ds--;
dn += 1000000000;
}
* difference = ds * 1000000000 + dn;
return !( * difference > 0);
}
int main() {
struct timespec start, finish;
long long int time_elapsed;
clock_gettime(CLOCK_MONOTONIC, & start);
kernel <<< 26, 26 >>> ();
cudaThreadSynchronize();
clock_gettime(CLOCK_MONOTONIC, & finish);
time_difference( & start, & finish, & time_elapsed);
printf("Time elapsed was %lldns or %0.9lfs\n", time_elapsed,
(time_elapsed / 1.0e9));
return 0;
} | code for sm_80
Function : _Z6kernelv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fc800078e00ff */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e220000002100 */
/*0020*/ IADD3 R1, R1, -0x28, RZ ; /* 0xffffffd801017810 */
/* 0x000fe20007ffe0ff */
/*0030*/ ULDC UR36, c[0x0][0x20] ; /* 0x0000080000247ab9 */
/* 0x000fe20000000800 */
/*0040*/ BSSY B8, 0xdd0 ; /* 0x00000d8000087945 */
/* 0x000fe20003800000 */
/*0050*/ S2R R22, SR_CTAID.X ; /* 0x0000000000167919 */
/* 0x000e620000002500 */
/*0060*/ R2UR UR48, R1 ; /* 0x00000000013073c2 */
/* 0x000ea200000e0000 */
/*0070*/ ULDC UR37, c[0x0][0x24] ; /* 0x0000090000257ab9 */
/* 0x000fe20000000800 */
/*0080*/ IMAD.MOV.U32 R16, RZ, RZ, 0x30 ; /* 0x00000030ff107424 */
/* 0x000fe200078e00ff */
/*0090*/ STL.U8 [R1+0x26], RZ ; /* 0x000026ff01007387 */
/* 0x0007e20000100000 */
/*00a0*/ IADD3 R19, R1.reuse, 0x5, RZ ; /* 0x0000000501137810 */
/* 0x040fe40007ffe0ff */
/*00b0*/ IADD3 R17, R1, 0xa, RZ ; /* 0x0000000a01117810 */
/* 0x000fc40007ffe0ff */
/*00c0*/ IADD3 R0, R0, 0x41, RZ ; /* 0x0000004100007810 */
/* 0x001fe40007ffe0ff */
/*00d0*/ IADD3 R18, R22, 0x41, RZ ; /* 0x0000004116127810 */
/* 0x002fc60007ffe0ff */
/*00e0*/ STL.U8 [R1+0x21], R0 ; /* 0x0000210001007387 */
/* 0x0007e20000100000 */
/*00f0*/ UIADD3 UR36, UP0, UR48, UR36, URZ ; /* 0x0000002430247290 */
/* 0x004fe4000ff1e03f */
/*0100*/ UIADD3 UR41, UR48, 0xf, URZ ; /* 0x0000000f30297890 */
/* 0x000fe2000fffe03f */
/*0110*/ STL.U8 [R1+0x20], R18 ; /* 0x0000201201007387 */
/* 0x0007e20000100000 */
/*0120*/ UIADD3.X UR37, URZ, UR37, URZ, UP0, !UPT ; /* 0x000000253f257290 */
/* 0x000fe400087fe43f */
/*0130*/ UIADD3 UR46, UP0, UR36, 0x5, URZ ; /* 0x00000005242e7890 */
/* 0x000fe4000ff1e03f */
/*0140*/ UIADD3 UR44, UP1, UR36, 0xa, URZ ; /* 0x0000000a242c7890 */
/* 0x000fe4000ff3e03f */
/*0150*/ UIADD3 UR42, UP2, UR36, 0xf, URZ ; /* 0x0000000f242a7890 */
/* 0x000fc4000ff5e03f */
/*0160*/ UIADD3 UR39, UP3, UR36, 0x18, URZ ; /* 0x0000001824277890 */
/* 0x000fe4000ff7e03f */
/*0170*/ UIADD3 UR38, UR48, 0x20, URZ ; /* 0x0000002030267890 */
/* 0x000fe4000fffe03f */
/*0180*/ UIADD3.X UR47, URZ, UR37, URZ, UP0, !UPT ; /* 0x000000253f2f7290 */
/* 0x000fe400087fe43f */
/*0190*/ UIADD3.X UR45, URZ, UR37, URZ, UP1, !UPT ; /* 0x000000253f2d7290 */
/* 0x000fe40008ffe43f */
/*01a0*/ UIADD3.X UR43, URZ, UR37, URZ, UP2, !UPT ; /* 0x000000253f2b7290 */
/* 0x000fe400097fe43f */
/*01b0*/ UIADD3.X UR40, URZ, UR37, URZ, UP3, !UPT ; /* 0x000000253f287290 */
/* 0x008fc80009ffe43f */
/*01c0*/ BSSY B7, 0xd70 ; /* 0x00000ba000077945 */
/* 0x000fe20003800000 */
/*01d0*/ IMAD.MOV.U32 R2, RZ, RZ, 0x30 ; /* 0x00000030ff027424 */
/* 0x001fce00078e00ff */
/*01e0*/ IMAD.MOV.U32 R0, RZ, RZ, 0x41 ; /* 0x00000041ff007424 */
/* 0x000fe200078e00ff */
/*01f0*/ STL.U8 [R1+0x22], R16 ; /* 0x0000221001007387 */
/* 0x000fe20000100000 */
/*0200*/ IMAD.MOV.U32 R3, RZ, RZ, 0x50 ; /* 0x00000050ff037424 */
/* 0x000fe200078e00ff */
/*0210*/ LOP3.LUT P0, RZ, R22, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff16ff7812 */
/* 0x000fe2000780c0ff */
/*0220*/ IMAD.MOV.U32 R6, RZ, RZ, 0x4e ; /* 0x0000004eff067424 */
/* 0x000fe200078e00ff */
/*0230*/ STL.U8 [R1], R0 ; /* 0x0000000001007387 */
/* 0x000fe20000100000 */
/*0240*/ IMAD.MOV.U32 R7, RZ, RZ, 0x52 ; /* 0x00000052ff077424 */
/* 0x000fc400078e00ff */
/*0250*/ IMAD.MOV.U32 R4, RZ, RZ, 0x32 ; /* 0x00000032ff047424 */
/* 0x000fe200078e00ff */
/*0260*/ STL.U8 [R1+0x5], R0 ; /* 0x0000050001007387 */
/* 0x000fe20000100000 */
/*0270*/ IMAD.MOV.U32 R8, RZ, RZ, 0x30 ; /* 0x00000030ff087424 */
/* 0x000fe400078e00ff */
/*0280*/ IMAD.MOV.U32 R5, RZ, RZ, 0x35 ; /* 0x00000035ff057424 */
/* 0x000fe200078e00ff */
/*0290*/ STL.U8 [R1+0xb], R0 ; /* 0x00000b0001007387 */
/* 0x0011e80000100000 */
/*02a0*/ STL.U8 [R1+0x1], R3 ; /* 0x0000010301007387 */
/* 0x0003e80000100000 */
/*02b0*/ STL.U8 [R1+0x2], R4 ; /* 0x0000020401007387 */
/* 0x000fe20000100000 */
/*02c0*/ PRMT R0, R6, 0x7610, R0 ; /* 0x0000761006007816 */
/* 0x001fe20000000000 */
/*02d0*/ IMAD.MOV.U32 R6, RZ, RZ, 0x43 ; /* 0x00000043ff067424 */
/* 0x000fc400078e00ff */
/*02e0*/ STL.U8 [R1+0x8], R4 ; /* 0x0000080401007387 */
/* 0x000fe20000100000 */
/*02f0*/ PRMT R3, R7, 0x7610, R3 ; /* 0x0000761007037816 */
/* 0x002fe20000000003 */
/*0300*/ IMAD.MOV.U32 R7, RZ, RZ, 0x38 ; /* 0x00000038ff077424 */
/* 0x000fe400078e00ff */
/*0310*/ STL.U8 [R1+0xc], R4 ; /* 0x00000c0401007387 */
/* 0x0001e80000100000 */
/*0320*/ STL.U8 [R1+0x3], R5 ; /* 0x0000030501007387 */
/* 0x000fe80000100000 */
/*0330*/ STL.U8 [R1+0x7], R5 ; /* 0x0000070501007387 */
/* 0x000fe20000100000 */
/*0340*/ PRMT R4, R6, 0x7610, R4 ; /* 0x0000761006047816 */
/* 0x001fc40000000004 */
/*0350*/ PRMT R6, R7, 0x7610, R6 ; /* 0x0000761007067816 */
/* 0x000fe20000000006 */
/*0360*/ STL.U8 [R1+0xd], R5 ; /* 0x00000d0501007387 */
/* 0x000fe20000100000 */
/*0370*/ PRMT R7, R8, 0x7610, R7 ; /* 0x0000761008077816 */
/* 0x000fc60000000007 */
/*0380*/ STL.U8 [R1+0xa], R3 ; /* 0x00000a0301007387 */
/* 0x000fe80000100000 */
/*0390*/ STL.U8 [R1+0xf], R3 ; /* 0x00000f0301007387 */
/* 0x000fe80000100000 */
/*03a0*/ STL.U8 [R1+0x10], R4 ; /* 0x0000100401007387 */
/* 0x000fe80000100000 */
/*03b0*/ STL.U8 [R1+0x11], R6 ; /* 0x0000110601007387 */
/* 0x000fe80000100000 */
/*03c0*/ STL.U8 [R1+0x12], R7 ; /* 0x0000120701007387 */
/* 0x000fe80000100000 */
/*03d0*/ STL.U8 [R1+0x23], R2 ; /* 0x0000230201007387 */
/* 0x000fe80000100000 */
/*03e0*/ STL.U8 [R1+0x4], RZ ; /* 0x000004ff01007387 */
/* 0x000fe80000100000 */
/*03f0*/ STL.U8 [R1+0x9], RZ ; /* 0x000009ff01007387 */
/* 0x000fe80000100000 */
/*0400*/ STL.U8 [R1+0xe], RZ ; /* 0x00000eff01007387 */
/* 0x000fe80000100000 */
/*0410*/ STL.U8 [R1+0x13], RZ ; /* 0x000013ff01007387 */
/* 0x000fe80000100000 */
/*0420*/ STL.U8 [R1+0x6], R0 ; /* 0x0000060001007387 */
/* 0x0001e40000100000 */
/*0430*/ IMAD.MOV.U32 R0, RZ, RZ, 0x41 ; /* 0x00000041ff007424 */
/* 0x001fe200078e00ff */
/*0440*/ @P0 BRA 0x670 ; /* 0x0000022000000947 */
/* 0x000fea0003800000 */
/*0450*/ BSSY B6, 0x670 ; /* 0x0000021000067945 */
/* 0x000fe20003800000 */
/*0460*/ IMAD.MOV.U32 R3, RZ, RZ, 0x41 ; /* 0x00000041ff037424 */
/* 0x000fc400078e00ff */
/*0470*/ IMAD.U32 R5, RZ, RZ, UR38 ; /* 0x00000026ff057e24 */
/* 0x000fe4000f8e00ff */
/*0480*/ IMAD.MOV.U32 R0, RZ, RZ, R1 ; /* 0x000000ffff007224 */
/* 0x000fe400078e0001 */
/*0490*/ LOP3.LUT P0, RZ, R3, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff03ff7812 */
/* 0x000fda000780c0ff */
/*04a0*/ @!P0 BRA 0x540 ; /* 0x0000009000008947 */
/* 0x000fea0003800000 */
/*04b0*/ LDL.U8 R4, [R0+0x1] ; /* 0x0000010000047983 */
/* 0x0000a80000100000 */
/*04c0*/ LDL.U8 R3, [R5+0x1] ; /* 0x0000010005037983 */
/* 0x000ea20000100000 */
/*04d0*/ IADD3 R0, R0, 0x1, RZ ; /* 0x0000000100007810 */
/* 0x001fe40007ffe0ff */
/*04e0*/ ISETP.NE.AND P0, PT, R3, R4, PT ; /* 0x000000040300720c */
/* 0x004fe40003f05270 */
/*04f0*/ IADD3 R4, R5, 0x1, RZ ; /* 0x0000000105047810 */
/* 0x000fca0007ffe0ff */
/*0500*/ IMAD.MOV.U32 R5, RZ, RZ, R4 ; /* 0x000000ffff057224 */
/* 0x000fcc00078e0004 */
/*0510*/ @!P0 BRA 0x490 ; /* 0xffffff7000008947 */
/* 0x000fea000383ffff */
/*0520*/ IMAD.MOV.U32 R0, RZ, RZ, 0x41 ; /* 0x00000041ff007424 */
/* 0x000fe200078e00ff */
/*0530*/ BRA 0x660 ; /* 0x0000012000007947 */
/* 0x000fea0003800000 */
/*0540*/ MOV R8, 0x0 ; /* 0x0000000000087802 */
/* 0x000fe20000000f00 */
/*0550*/ IMAD.U32 R10, RZ, RZ, UR36 ; /* 0x00000024ff0a7e24 */
/* 0x000fe4000f8e00ff */
/*0560*/ IMAD.U32 R11, RZ, RZ, UR37 ; /* 0x00000025ff0b7e24 */
/* 0x000fe4000f8e00ff */
/*0570*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x8] ; /* 0x01000200ff047624 */
/* 0x000fe200078e00ff */
/*0580*/ LDC.64 R8, c[0x4][R8] ; /* 0x0100000008087b82 */
/* 0x000e220000000a00 */
/*0590*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0xc] ; /* 0x01000300ff057624 */
/* 0x000fe200078e00ff */
/*05a0*/ STL.64 [R1+0x18], R10 ; /* 0x0000180a01007387 */
/* 0x0003e20000100a00 */
/*05b0*/ IMAD.U32 R6, RZ, RZ, UR39 ; /* 0x00000027ff067e24 */
/* 0x000fc4000f8e00ff */
/*05c0*/ IMAD.U32 R7, RZ, RZ, UR40 ; /* 0x00000028ff077e24 */
/* 0x000fc6000f8e00ff */
/*05d0*/ LEPC R10 ; /* 0x00000000000a734e */
/* 0x002fe20000000000 */
/*05e0*/ MOV R3, 0x650 ; /* 0x0000065000037802 */
/* 0x000fe40000000f00 */
/*05f0*/ MOV R20, 0x5d0 ; /* 0x000005d000147802 */
/* 0x000fe40000000f00 */
/*0600*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*0610*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe40000000f00 */
/*0620*/ IADD3 R20, P0, P1, -R20, R3, R10 ; /* 0x0000000314147210 */
/* 0x000fc8000791e10a */
/*0630*/ IADD3.X R21, ~R0, R21, R11, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e250b */
/*0640*/ CALL.ABS.NOINC R8 ; /* 0x0000000008007343 */
/* 0x001fea0003c00000 */
/*0650*/ LDL.U8 R0, [R1+0x5] ; /* 0x0000050001007983 */
/* 0x0001640000100000 */
/*0660*/ BSYNC B6 ; /* 0x0000000000067941 */
/* 0x000fea0003800000 */
/*0670*/ LOP3.LUT R0, R0, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff00007812 */
/* 0x020fe200078ec0ff */
/*0680*/ BSSY B6, 0x8b0 ; /* 0x0000022000067945 */
/* 0x000fe20003800000 */
/*0690*/ LOP3.LUT R23, R18, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff12177812 */
/* 0x000fc800078ec0ff */
/*06a0*/ ISETP.NE.AND P0, PT, R23, R0, PT ; /* 0x000000001700720c */
/* 0x000fda0003f05270 */
/*06b0*/ @P0 BRA 0x8a0 ; /* 0x000001e000000947 */
/* 0x000fea0003800000 */
/*06c0*/ PRMT R0, R18, 0x7610, R0 ; /* 0x0000761012007816 */
/* 0x000fe20000000000 */
/*06d0*/ IMAD.U32 R4, RZ, RZ, UR38 ; /* 0x00000026ff047e24 */
/* 0x000fe4000f8e00ff */
/*06e0*/ IMAD.MOV.U32 R5, RZ, RZ, R19 ; /* 0x000000ffff057224 */
/* 0x000fe400078e0013 */
/*06f0*/ LOP3.LUT P0, RZ, R0, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff00ff7812 */
/* 0x000fda000780c0ff */
/*0700*/ @!P0 BRA 0x790 ; /* 0x0000008000008947 */
/* 0x000fea0003800000 */
/*0710*/ LDL.U8 R3, [R5+0x1] ; /* 0x0000010005037983 */
/* 0x000ea80000100000 */
/*0720*/ LDL.U8 R0, [R4+0x1] ; /* 0x0000010004007983 */
/* 0x0002a40000100000 */
/*0730*/ IADD3 R4, R4, 0x1, RZ ; /* 0x0000000104047810 */
/* 0x002fe40007ffe0ff */
/*0740*/ ISETP.NE.AND P0, PT, R0, R3, PT ; /* 0x000000030000720c */
/* 0x004fe40003f05270 */
/*0750*/ IADD3 R3, R5, 0x1, RZ ; /* 0x0000000105037810 */
/* 0x000fca0007ffe0ff */
/*0760*/ IMAD.MOV.U32 R5, RZ, RZ, R3 ; /* 0x000000ffff057224 */
/* 0x000fcc00078e0003 */
/*0770*/ @!P0 BRA 0x6f0 ; /* 0xffffff7000008947 */
/* 0x000fea000383ffff */
/*0780*/ BRA 0x8a0 ; /* 0x0000011000007947 */
/* 0x000fea0003800000 */
/*0790*/ MOV R8, 0x0 ; /* 0x0000000000087802 */
/* 0x000fe20000000f00 */
/*07a0*/ IMAD.U32 R10, RZ, RZ, UR46 ; /* 0x0000002eff0a7e24 */
/* 0x000fe4000f8e00ff */
/*07b0*/ IMAD.U32 R11, RZ, RZ, UR47 ; /* 0x0000002fff0b7e24 */
/* 0x000fe4000f8e00ff */
/*07c0*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x8] ; /* 0x01000200ff047624 */
/* 0x000fe200078e00ff */
/*07d0*/ LDC.64 R8, c[0x4][R8] ; /* 0x0100000008087b82 */
/* 0x000e620000000a00 */
/*07e0*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0xc] ; /* 0x01000300ff057624 */
/* 0x000fe200078e00ff */
/*07f0*/ STL.64 [R1+0x18], R10 ; /* 0x0000180a01007387 */
/* 0x0005e20000100a00 */
/*0800*/ IMAD.U32 R6, RZ, RZ, UR39 ; /* 0x00000027ff067e24 */
/* 0x000fe4000f8e00ff */
/*0810*/ IMAD.U32 R7, RZ, RZ, UR40 ; /* 0x00000028ff077e24 */
/* 0x000fc6000f8e00ff */
/*0820*/ LEPC R10 ; /* 0x00000000000a734e */
/* 0x004fe20000000000 */
/*0830*/ MOV R3, 0x8a0 ; /* 0x000008a000037802 */
/* 0x000fc40000000f00 */
/*0840*/ MOV R20, 0x820 ; /* 0x0000082000147802 */
/* 0x000fe40000000f00 */
/*0850*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*0860*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe40000000f00 */
/*0870*/ IADD3 R20, P0, P1, -R20, R3, R10 ; /* 0x0000000314147210 */
/* 0x000fc8000791e10a */
/*0880*/ IADD3.X R21, ~R0, R21, R11, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e250b */
/*0890*/ CALL.ABS.NOINC R8 ; /* 0x0000000008007343 */
/* 0x003fea0003c00000 */
/*08a0*/ BSYNC B6 ; /* 0x0000000000067941 */
/* 0x000fea0003800000 */
/*08b0*/ LDL.U8 R0, [R1+0xa] ; /* 0x00000a0001007983 */
/* 0x000ea20000100000 */
/*08c0*/ BSSY B6, 0xae0 ; /* 0x0000021000067945 */
/* 0x000fe20003800000 */
/*08d0*/ ISETP.NE.AND P0, PT, R23, R0, PT ; /* 0x000000001700720c */
/* 0x004fda0003f05270 */
/*08e0*/ @P0 BRA 0xad0 ; /* 0x000001e000000947 */
/* 0x000fea0003800000 */
/*08f0*/ PRMT R0, R18, 0x7610, R0 ; /* 0x0000761012007816 */
/* 0x000fe20000000000 */
/*0900*/ IMAD.U32 R4, RZ, RZ, UR38 ; /* 0x00000026ff047e24 */
/* 0x000fe4000f8e00ff */
/*0910*/ IMAD.MOV.U32 R5, RZ, RZ, R17 ; /* 0x000000ffff057224 */
/* 0x000fe400078e0011 */
/*0920*/ LOP3.LUT P0, RZ, R0, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff00ff7812 */
/* 0x000fda000780c0ff */
/*0930*/ @!P0 BRA 0x9c0 ; /* 0x0000008000008947 */
/* 0x000fea0003800000 */
/*0940*/ LDL.U8 R3, [R5+0x1] ; /* 0x0000010005037983 */
/* 0x000ea80000100000 */
/*0950*/ LDL.U8 R0, [R4+0x1] ; /* 0x0000010004007983 */
/* 0x0002a40000100000 */
/*0960*/ IADD3 R4, R4, 0x1, RZ ; /* 0x0000000104047810 */
/* 0x002fe40007ffe0ff */
/*0970*/ ISETP.NE.AND P0, PT, R0, R3, PT ; /* 0x000000030000720c */
/* 0x004fe40003f05270 */
/*0980*/ IADD3 R3, R5, 0x1, RZ ; /* 0x0000000105037810 */
/* 0x000fca0007ffe0ff */
/*0990*/ IMAD.MOV.U32 R5, RZ, RZ, R3 ; /* 0x000000ffff057224 */
/* 0x000fcc00078e0003 */
/*09a0*/ @!P0 BRA 0x920 ; /* 0xffffff7000008947 */
/* 0x000fea000383ffff */
/*09b0*/ BRA 0xad0 ; /* 0x0000011000007947 */
/* 0x000fea0003800000 */
/*09c0*/ MOV R8, 0x0 ; /* 0x0000000000087802 */
/* 0x000fe20000000f00 */
/*09d0*/ IMAD.U32 R10, RZ, RZ, UR44 ; /* 0x0000002cff0a7e24 */
/* 0x000fe4000f8e00ff */
/*09e0*/ IMAD.U32 R11, RZ, RZ, UR45 ; /* 0x0000002dff0b7e24 */
/* 0x000fe4000f8e00ff */
/*09f0*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x8] ; /* 0x01000200ff047624 */
/* 0x000fe200078e00ff */
/*0a00*/ LDC.64 R8, c[0x4][R8] ; /* 0x0100000008087b82 */
/* 0x000e620000000a00 */
/*0a10*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0xc] ; /* 0x01000300ff057624 */
/* 0x000fe200078e00ff */
/*0a20*/ STL.64 [R1+0x18], R10 ; /* 0x0000180a01007387 */
/* 0x0005e20000100a00 */
/*0a30*/ IMAD.U32 R6, RZ, RZ, UR39 ; /* 0x00000027ff067e24 */
/* 0x000fe4000f8e00ff */
/*0a40*/ IMAD.U32 R7, RZ, RZ, UR40 ; /* 0x00000028ff077e24 */
/* 0x000fc6000f8e00ff */
/*0a50*/ LEPC R10 ; /* 0x00000000000a734e */
/* 0x004fe20000000000 */
/*0a60*/ MOV R3, 0xad0 ; /* 0x00000ad000037802 */
/* 0x000fc40000000f00 */
/*0a70*/ MOV R20, 0xa50 ; /* 0x00000a5000147802 */
/* 0x000fe40000000f00 */
/*0a80*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*0a90*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe40000000f00 */
/*0aa0*/ IADD3 R20, P0, P1, -R20, R3, R10 ; /* 0x0000000314147210 */
/* 0x000fc8000791e10a */
/*0ab0*/ IADD3.X R21, ~R0, R21, R11, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e250b */
/*0ac0*/ CALL.ABS.NOINC R8 ; /* 0x0000000008007343 */
/* 0x003fea0003c00000 */
/*0ad0*/ BSYNC B6 ; /* 0x0000000000067941 */
/* 0x000fea0003800000 */
/*0ae0*/ LDL.U8 R0, [R1+0xf] ; /* 0x00000f0001007983 */
/* 0x000ea20000100000 */
/*0af0*/ BSSY B6, 0xd10 ; /* 0x0000021000067945 */
/* 0x000fe20003800000 */
/*0b00*/ ISETP.NE.AND P0, PT, R23, R0, PT ; /* 0x000000001700720c */
/* 0x004fda0003f05270 */
/*0b10*/ @P0 BRA 0xd00 ; /* 0x000001e000000947 */
/* 0x000fea0003800000 */
/*0b20*/ PRMT R0, R18, 0x7610, R0 ; /* 0x0000761012007816 */
/* 0x000fe20000000000 */
/*0b30*/ IMAD.U32 R5, RZ, RZ, UR41 ; /* 0x00000029ff057e24 */
/* 0x000fe4000f8e00ff */
/*0b40*/ IMAD.U32 R4, RZ, RZ, UR38 ; /* 0x00000026ff047e24 */
/* 0x000fe4000f8e00ff */
/*0b50*/ LOP3.LUT P0, RZ, R0, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff00ff7812 */
/* 0x000fda000780c0ff */
/*0b60*/ @!P0 BRA 0xbf0 ; /* 0x0000008000008947 */
/* 0x000fea0003800000 */
/*0b70*/ LDL.U8 R3, [R5+0x1] ; /* 0x0000010005037983 */
/* 0x000ea80000100000 */
/*0b80*/ LDL.U8 R0, [R4+0x1] ; /* 0x0000010004007983 */
/* 0x0002a40000100000 */
/*0b90*/ IADD3 R4, R4, 0x1, RZ ; /* 0x0000000104047810 */
/* 0x002fe40007ffe0ff */
/*0ba0*/ ISETP.NE.AND P0, PT, R0, R3, PT ; /* 0x000000030000720c */
/* 0x004fe40003f05270 */
/*0bb0*/ IADD3 R3, R5, 0x1, RZ ; /* 0x0000000105037810 */
/* 0x000fca0007ffe0ff */
/*0bc0*/ IMAD.MOV.U32 R5, RZ, RZ, R3 ; /* 0x000000ffff057224 */
/* 0x000fcc00078e0003 */
/*0bd0*/ @!P0 BRA 0xb50 ; /* 0xffffff7000008947 */
/* 0x000fea000383ffff */
/*0be0*/ BRA 0xd00 ; /* 0x0000011000007947 */
/* 0x000fea0003800000 */
/*0bf0*/ MOV R8, 0x0 ; /* 0x0000000000087802 */
/* 0x000fe20000000f00 */
/*0c00*/ IMAD.U32 R10, RZ, RZ, UR42 ; /* 0x0000002aff0a7e24 */
/* 0x000fe4000f8e00ff */
/*0c10*/ IMAD.U32 R11, RZ, RZ, UR43 ; /* 0x0000002bff0b7e24 */
/* 0x000fe4000f8e00ff */
/*0c20*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x10] ; /* 0x01000400ff047624 */
/* 0x000fe200078e00ff */
/*0c30*/ LDC.64 R8, c[0x4][R8] ; /* 0x0100000008087b82 */
/* 0x000e620000000a00 */
/*0c40*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0x14] ; /* 0x01000500ff057624 */
/* 0x000fe200078e00ff */
/*0c50*/ STL.64 [R1+0x18], R10 ; /* 0x0000180a01007387 */
/* 0x0005e20000100a00 */
/*0c60*/ IMAD.U32 R6, RZ, RZ, UR39 ; /* 0x00000027ff067e24 */
/* 0x000fe4000f8e00ff */
/*0c70*/ IMAD.U32 R7, RZ, RZ, UR40 ; /* 0x00000028ff077e24 */
/* 0x000fc6000f8e00ff */
/*0c80*/ LEPC R10 ; /* 0x00000000000a734e */
/* 0x004fe20000000000 */
/*0c90*/ MOV R3, 0xd00 ; /* 0x00000d0000037802 */
/* 0x000fc40000000f00 */
/*0ca0*/ MOV R20, 0xc80 ; /* 0x00000c8000147802 */
/* 0x000fe40000000f00 */
/*0cb0*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*0cc0*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe40000000f00 */
/*0cd0*/ IADD3 R20, P0, P1, -R20, R3, R10 ; /* 0x0000000314147210 */
/* 0x000fc8000791e10a */
/*0ce0*/ IADD3.X R21, ~R0, R21, R11, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e250b */
/*0cf0*/ CALL.ABS.NOINC R8 ; /* 0x0000000008007343 */
/* 0x003fea0003c00000 */
/*0d00*/ BSYNC B6 ; /* 0x0000000000067941 */
/* 0x000fea0003800000 */
/*0d10*/ IADD3 R2, R2, 0x1, RZ ; /* 0x0000000102027810 */
/* 0x000fc80007ffe0ff */
/*0d20*/ LOP3.LUT R0, R2, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff02007812 */
/* 0x000fc800078ec0ff */
/*0d30*/ ISETP.GE.U32.AND P0, PT, R0, 0x3a, PT ; /* 0x0000003a0000780c */
/* 0x000fda0003f06070 */
/*0d40*/ @P0 CALL.REL.NOINC 0xd60 ; /* 0x0000001000000944 */
/* 0x000fe20003c00000 */
/*0d50*/ BRA 0x1e0 ; /* 0xfffff48000007947 */
/* 0x000fea000383ffff */
/*0d60*/ BSYNC B7 ; /* 0x0000000000077941 */
/* 0x000fea0003800000 */
/*0d70*/ IADD3 R16, R16, 0x1, RZ ; /* 0x0000000110107810 */
/* 0x000fc80007ffe0ff */
/*0d80*/ LOP3.LUT R0, R16, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff10007812 */
/* 0x000fc800078ec0ff */
/*0d90*/ ISETP.GE.U32.AND P0, PT, R0, 0x3a, PT ; /* 0x0000003a0000780c */
/* 0x000fda0003f06070 */
/*0da0*/ @P0 CALL.REL.NOINC 0xdc0 ; /* 0x0000001000000944 */
/* 0x000fe20003c00000 */
/*0db0*/ BRA 0x1c0 ; /* 0xfffff40000007947 */
/* 0x000fea000383ffff */
/*0dc0*/ BSYNC B8 ; /* 0x0000000000087941 */
/* 0x000fea0003800000 */
/*0dd0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0de0*/ BRA 0xde0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0df0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <cuda_runtime_api.h>
#include <time.h>
__device__ int is_a_match(char * attempt) {
char password1[] = "AP25";
char password2[] = "AN52";
char password3[] = "RA25";
char password4[] = "RC80";
char * a = attempt;
char * b = attempt;
char * c = attempt;
char * d = attempt;
char * pass1 = password1;
char * pass2 = password2;
char * pass3 = password3;
char * pass4 = password4;
while ( * a == * pass1) {
if ( * a == '\0') {
printf("password:%s\n", password1);
break;
}
a++;
pass1++;
}
while ( * b == * pass2) {
if ( * b == '\0') {
printf("password:%s\n", password2);
break;
}
b++;
pass2++;
}
while ( * c == * pass3) {
if ( * c == '\0') {
printf("password:%s\n", password3);
break;
}
c++;
pass3++;
}
while ( * d == * pass4) {
if ( * d == '\0') {
printf("password: %s\n", password4);
return 1;
}
d++;
pass4++;
}
return 0;
}
__global__ void kernel() {
char i1, i2;
char password[7];
password[6] = '\0';
int i = blockIdx.x + 65;
int j = threadIdx.x + 65;
char firstMatch = i;
char secondMatch = j;
password[0] = firstMatch;
password[1] = secondMatch;
for (i1 = '0'; i1 <= '9'; i1++) {
for (i2 = '0'; i2 <= '9'; i2++) {
password[2] = i1;
password[3] = i2;
if (is_a_match(password)) {} else {
//printf("tried: %s\n",password);
}
}
}
}
int time_difference(struct timespec * start, struct timespec * finish, long long int * difference) {
long long int ds = finish -> tv_sec - start -> tv_sec;
long long int dn = finish -> tv_nsec - start -> tv_nsec;
if (dn < 0) {
ds--;
dn += 1000000000;
}
* difference = ds * 1000000000 + dn;
return !( * difference > 0);
}
int main() {
struct timespec start, finish;
long long int time_elapsed;
clock_gettime(CLOCK_MONOTONIC, & start);
kernel <<< 26, 26 >>> ();
cudaThreadSynchronize();
clock_gettime(CLOCK_MONOTONIC, & finish);
time_difference( & start, & finish, & time_elapsed);
printf("Time elapsed was %lldns or %0.9lfs\n", time_elapsed,
(time_elapsed / 1.0e9));
return 0;
} | .file "tmpxft_00124dea_00000000-6_passwordCrackWithCuda2Initials.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z10is_a_matchPc
.type _Z10is_a_matchPc, @function
_Z10is_a_matchPc:
.LFB2057:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size _Z10is_a_matchPc, .-_Z10is_a_matchPc
.globl _Z15time_differenceP8timespecS0_Px
.type _Z15time_differenceP8timespecS0_Px, @function
_Z15time_differenceP8timespecS0_Px:
.LFB2058:
.cfi_startproc
endbr64
movq (%rsi), %rax
subq (%rdi), %rax
movq 8(%rsi), %rcx
subq 8(%rdi), %rcx
js .L7
.L6:
imulq $1000000000, %rax, %rax
addq %rcx, %rax
movq %rax, (%rdx)
testq %rax, %rax
setle %al
movzbl %al, %eax
ret
.L7:
subq $1, %rax
addq $1000000000, %rcx
jmp .L6
.cfi_endproc
.LFE2058:
.size _Z15time_differenceP8timespecS0_Px, .-_Z15time_differenceP8timespecS0_Px
.globl _Z24__device_stub__Z6kernelvv
.type _Z24__device_stub__Z6kernelvv, @function
_Z24__device_stub__Z6kernelvv:
.LFB2084:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L12
.L8:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L13
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L12:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z6kernelv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L8
.L13:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z24__device_stub__Z6kernelvv, .-_Z24__device_stub__Z6kernelvv
.globl _Z6kernelv
.type _Z6kernelv, @function
_Z6kernelv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z24__device_stub__Z6kernelvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z6kernelv, .-_Z6kernelv
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "Time elapsed was %lldns or %0.9lfs\n"
.text
.globl main
.type main, @function
main:
.LFB2059:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $64, %rsp
.cfi_def_cfa_offset 80
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
leaq 16(%rsp), %rsi
movl $1, %edi
call clock_gettime@PLT
movl $26, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $26, (%rsp)
movl $1, 4(%rsp)
movl $1, 8(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 32(%rsp), %rdx
movl $1, %ecx
movq (%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L20
.L17:
call cudaThreadSynchronize@PLT
leaq 32(%rsp), %rbx
movq %rbx, %rsi
movl $1, %edi
call clock_gettime@PLT
movq %rsp, %rdx
leaq 16(%rsp), %rdi
movq %rbx, %rsi
call _Z15time_differenceP8timespecS0_Px
movq (%rsp), %rdx
pxor %xmm0, %xmm0
cvtsi2sdq %rdx, %xmm0
divsd .LC0(%rip), %xmm0
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L21
movl $0, %eax
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L20:
.cfi_restore_state
call _Z24__device_stub__Z6kernelvv
jmp .L17
.L21:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "_Z6kernelv"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z6kernelv(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long 0
.long 1104006501
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <cuda_runtime_api.h>
#include <time.h>
__device__ int is_a_match(char * attempt) {
char password1[] = "AP25";
char password2[] = "AN52";
char password3[] = "RA25";
char password4[] = "RC80";
char * a = attempt;
char * b = attempt;
char * c = attempt;
char * d = attempt;
char * pass1 = password1;
char * pass2 = password2;
char * pass3 = password3;
char * pass4 = password4;
while ( * a == * pass1) {
if ( * a == '\0') {
printf("password:%s\n", password1);
break;
}
a++;
pass1++;
}
while ( * b == * pass2) {
if ( * b == '\0') {
printf("password:%s\n", password2);
break;
}
b++;
pass2++;
}
while ( * c == * pass3) {
if ( * c == '\0') {
printf("password:%s\n", password3);
break;
}
c++;
pass3++;
}
while ( * d == * pass4) {
if ( * d == '\0') {
printf("password: %s\n", password4);
return 1;
}
d++;
pass4++;
}
return 0;
}
__global__ void kernel() {
char i1, i2;
char password[7];
password[6] = '\0';
int i = blockIdx.x + 65;
int j = threadIdx.x + 65;
char firstMatch = i;
char secondMatch = j;
password[0] = firstMatch;
password[1] = secondMatch;
for (i1 = '0'; i1 <= '9'; i1++) {
for (i2 = '0'; i2 <= '9'; i2++) {
password[2] = i1;
password[3] = i2;
if (is_a_match(password)) {} else {
//printf("tried: %s\n",password);
}
}
}
}
int time_difference(struct timespec * start, struct timespec * finish, long long int * difference) {
long long int ds = finish -> tv_sec - start -> tv_sec;
long long int dn = finish -> tv_nsec - start -> tv_nsec;
if (dn < 0) {
ds--;
dn += 1000000000;
}
* difference = ds * 1000000000 + dn;
return !( * difference > 0);
}
int main() {
struct timespec start, finish;
long long int time_elapsed;
clock_gettime(CLOCK_MONOTONIC, & start);
kernel <<< 26, 26 >>> ();
cudaThreadSynchronize();
clock_gettime(CLOCK_MONOTONIC, & finish);
time_difference( & start, & finish, & time_elapsed);
printf("Time elapsed was %lldns or %0.9lfs\n", time_elapsed,
(time_elapsed / 1.0e9));
return 0;
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <hip/hip_runtime_api.h>
#include <time.h>
__device__ int is_a_match(char * attempt) {
char password1[] = "AP25";
char password2[] = "AN52";
char password3[] = "RA25";
char password4[] = "RC80";
char * a = attempt;
char * b = attempt;
char * c = attempt;
char * d = attempt;
char * pass1 = password1;
char * pass2 = password2;
char * pass3 = password3;
char * pass4 = password4;
while ( * a == * pass1) {
if ( * a == '\0') {
printf("password:%s\n", password1);
break;
}
a++;
pass1++;
}
while ( * b == * pass2) {
if ( * b == '\0') {
printf("password:%s\n", password2);
break;
}
b++;
pass2++;
}
while ( * c == * pass3) {
if ( * c == '\0') {
printf("password:%s\n", password3);
break;
}
c++;
pass3++;
}
while ( * d == * pass4) {
if ( * d == '\0') {
printf("password: %s\n", password4);
return 1;
}
d++;
pass4++;
}
return 0;
}
__global__ void kernel() {
char i1, i2;
char password[7];
password[6] = '\0';
int i = blockIdx.x + 65;
int j = threadIdx.x + 65;
char firstMatch = i;
char secondMatch = j;
password[0] = firstMatch;
password[1] = secondMatch;
for (i1 = '0'; i1 <= '9'; i1++) {
for (i2 = '0'; i2 <= '9'; i2++) {
password[2] = i1;
password[3] = i2;
if (is_a_match(password)) {} else {
//printf("tried: %s\n",password);
}
}
}
}
int time_difference(struct timespec * start, struct timespec * finish, long long int * difference) {
long long int ds = finish -> tv_sec - start -> tv_sec;
long long int dn = finish -> tv_nsec - start -> tv_nsec;
if (dn < 0) {
ds--;
dn += 1000000000;
}
* difference = ds * 1000000000 + dn;
return !( * difference > 0);
}
int main() {
struct timespec start, finish;
long long int time_elapsed;
clock_gettime(CLOCK_MONOTONIC, & start);
kernel <<< 26, 26 >>> ();
hipDeviceSynchronize();
clock_gettime(CLOCK_MONOTONIC, & finish);
time_difference( & start, & finish, & time_elapsed);
printf("Time elapsed was %lldns or %0.9lfs\n", time_elapsed,
(time_elapsed / 1.0e9));
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <hip/hip_runtime_api.h>
#include <time.h>
__device__ int is_a_match(char * attempt) {
char password1[] = "AP25";
char password2[] = "AN52";
char password3[] = "RA25";
char password4[] = "RC80";
char * a = attempt;
char * b = attempt;
char * c = attempt;
char * d = attempt;
char * pass1 = password1;
char * pass2 = password2;
char * pass3 = password3;
char * pass4 = password4;
while ( * a == * pass1) {
if ( * a == '\0') {
printf("password:%s\n", password1);
break;
}
a++;
pass1++;
}
while ( * b == * pass2) {
if ( * b == '\0') {
printf("password:%s\n", password2);
break;
}
b++;
pass2++;
}
while ( * c == * pass3) {
if ( * c == '\0') {
printf("password:%s\n", password3);
break;
}
c++;
pass3++;
}
while ( * d == * pass4) {
if ( * d == '\0') {
printf("password: %s\n", password4);
return 1;
}
d++;
pass4++;
}
return 0;
}
__global__ void kernel() {
char i1, i2;
char password[7];
password[6] = '\0';
int i = blockIdx.x + 65;
int j = threadIdx.x + 65;
char firstMatch = i;
char secondMatch = j;
password[0] = firstMatch;
password[1] = secondMatch;
for (i1 = '0'; i1 <= '9'; i1++) {
for (i2 = '0'; i2 <= '9'; i2++) {
password[2] = i1;
password[3] = i2;
if (is_a_match(password)) {} else {
//printf("tried: %s\n",password);
}
}
}
}
int time_difference(struct timespec * start, struct timespec * finish, long long int * difference) {
long long int ds = finish -> tv_sec - start -> tv_sec;
long long int dn = finish -> tv_nsec - start -> tv_nsec;
if (dn < 0) {
ds--;
dn += 1000000000;
}
* difference = ds * 1000000000 + dn;
return !( * difference > 0);
}
int main() {
struct timespec start, finish;
long long int time_elapsed;
clock_gettime(CLOCK_MONOTONIC, & start);
kernel <<< 26, 26 >>> ();
hipDeviceSynchronize();
clock_gettime(CLOCK_MONOTONIC, & finish);
time_difference( & start, & finish, & time_elapsed);
printf("Time elapsed was %lldns or %0.9lfs\n", time_elapsed,
(time_elapsed / 1.0e9));
return 0;
} | .text
.file "passwordCrackWithCuda2Initials.hip"
.globl _Z21__device_stub__kernelv # -- Begin function _Z21__device_stub__kernelv
.p2align 4, 0x90
.type _Z21__device_stub__kernelv,@function
_Z21__device_stub__kernelv: # @_Z21__device_stub__kernelv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z6kernelv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z21__device_stub__kernelv, .Lfunc_end0-_Z21__device_stub__kernelv
.cfi_endproc
# -- End function
.globl _Z15time_differenceP8timespecS0_Px # -- Begin function _Z15time_differenceP8timespecS0_Px
.p2align 4, 0x90
.type _Z15time_differenceP8timespecS0_Px,@function
_Z15time_differenceP8timespecS0_Px: # @_Z15time_differenceP8timespecS0_Px
.cfi_startproc
# %bb.0:
movq (%rsi), %rax
subq (%rdi), %rax
movq 8(%rsi), %rcx
subq 8(%rdi), %rcx
leaq 1000000000(%rcx), %rsi
movq %rcx, %rdi
sarq $63, %rdi
addq %rax, %rdi
testq %rcx, %rcx
cmovnsq %rcx, %rsi
imulq $1000000000, %rdi, %rcx # imm = 0x3B9ACA00
xorl %eax, %eax
addq %rsi, %rcx
movq %rcx, (%rdx)
setle %al
retq
.Lfunc_end1:
.size _Z15time_differenceP8timespecS0_Px, .Lfunc_end1-_Z15time_differenceP8timespecS0_Px
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI2_0:
.quad 0x41cdcd6500000000 # double 1.0E+9
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
leaq 48(%rsp), %rsi
movl $1, %edi
callq clock_gettime
movabsq $4294967322, %rdi # imm = 0x10000001A
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_2
# %bb.1:
movq %rsp, %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq (%rsp), %rsi
movl 8(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z6kernelv, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_2:
callq hipDeviceSynchronize
movq %rsp, %rsi
movl $1, %edi
callq clock_gettime
movq (%rsp), %rax
subq 48(%rsp), %rax
movq 8(%rsp), %rcx
subq 56(%rsp), %rcx
leaq 1000000000(%rcx), %rdx
movq %rcx, %rsi
sarq $63, %rsi
addq %rax, %rsi
testq %rcx, %rcx
cmovnsq %rcx, %rdx
imulq $1000000000, %rsi, %rsi # imm = 0x3B9ACA00
addq %rdx, %rsi
cvtsi2sd %rsi, %xmm0
divsd .LCPI2_0(%rip), %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
xorl %eax, %eax
addq $72, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6kernelv, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6kernelv,@object # @_Z6kernelv
.section .rodata,"a",@progbits
.globl _Z6kernelv
.p2align 3, 0x0
_Z6kernelv:
.quad _Z21__device_stub__kernelv
.size _Z6kernelv, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Time elapsed was %lldns or %0.9lfs\n"
.size .L.str, 36
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z6kernelv"
.size .L__unnamed_1, 11
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__kernelv
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6kernelv
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00124dea_00000000-6_passwordCrackWithCuda2Initials.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z10is_a_matchPc
.type _Z10is_a_matchPc, @function
_Z10is_a_matchPc:
.LFB2057:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size _Z10is_a_matchPc, .-_Z10is_a_matchPc
.globl _Z15time_differenceP8timespecS0_Px
.type _Z15time_differenceP8timespecS0_Px, @function
_Z15time_differenceP8timespecS0_Px:
.LFB2058:
.cfi_startproc
endbr64
movq (%rsi), %rax
subq (%rdi), %rax
movq 8(%rsi), %rcx
subq 8(%rdi), %rcx
js .L7
.L6:
imulq $1000000000, %rax, %rax
addq %rcx, %rax
movq %rax, (%rdx)
testq %rax, %rax
setle %al
movzbl %al, %eax
ret
.L7:
subq $1, %rax
addq $1000000000, %rcx
jmp .L6
.cfi_endproc
.LFE2058:
.size _Z15time_differenceP8timespecS0_Px, .-_Z15time_differenceP8timespecS0_Px
.globl _Z24__device_stub__Z6kernelvv
.type _Z24__device_stub__Z6kernelvv, @function
_Z24__device_stub__Z6kernelvv:
.LFB2084:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L12
.L8:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L13
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L12:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z6kernelv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L8
.L13:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z24__device_stub__Z6kernelvv, .-_Z24__device_stub__Z6kernelvv
.globl _Z6kernelv
.type _Z6kernelv, @function
_Z6kernelv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z24__device_stub__Z6kernelvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z6kernelv, .-_Z6kernelv
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "Time elapsed was %lldns or %0.9lfs\n"
.text
.globl main
.type main, @function
main:
.LFB2059:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $64, %rsp
.cfi_def_cfa_offset 80
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
leaq 16(%rsp), %rsi
movl $1, %edi
call clock_gettime@PLT
movl $26, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $26, (%rsp)
movl $1, 4(%rsp)
movl $1, 8(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 32(%rsp), %rdx
movl $1, %ecx
movq (%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L20
.L17:
call cudaThreadSynchronize@PLT
leaq 32(%rsp), %rbx
movq %rbx, %rsi
movl $1, %edi
call clock_gettime@PLT
movq %rsp, %rdx
leaq 16(%rsp), %rdi
movq %rbx, %rsi
call _Z15time_differenceP8timespecS0_Px
movq (%rsp), %rdx
pxor %xmm0, %xmm0
cvtsi2sdq %rdx, %xmm0
divsd .LC0(%rip), %xmm0
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L21
movl $0, %eax
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L20:
.cfi_restore_state
call _Z24__device_stub__Z6kernelvv
jmp .L17
.L21:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "_Z6kernelv"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z6kernelv(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long 0
.long 1104006501
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "passwordCrackWithCuda2Initials.hip"
.globl _Z21__device_stub__kernelv # -- Begin function _Z21__device_stub__kernelv
.p2align 4, 0x90
.type _Z21__device_stub__kernelv,@function
_Z21__device_stub__kernelv: # @_Z21__device_stub__kernelv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z6kernelv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z21__device_stub__kernelv, .Lfunc_end0-_Z21__device_stub__kernelv
.cfi_endproc
# -- End function
.globl _Z15time_differenceP8timespecS0_Px # -- Begin function _Z15time_differenceP8timespecS0_Px
.p2align 4, 0x90
.type _Z15time_differenceP8timespecS0_Px,@function
_Z15time_differenceP8timespecS0_Px: # @_Z15time_differenceP8timespecS0_Px
.cfi_startproc
# %bb.0:
movq (%rsi), %rax
subq (%rdi), %rax
movq 8(%rsi), %rcx
subq 8(%rdi), %rcx
leaq 1000000000(%rcx), %rsi
movq %rcx, %rdi
sarq $63, %rdi
addq %rax, %rdi
testq %rcx, %rcx
cmovnsq %rcx, %rsi
imulq $1000000000, %rdi, %rcx # imm = 0x3B9ACA00
xorl %eax, %eax
addq %rsi, %rcx
movq %rcx, (%rdx)
setle %al
retq
.Lfunc_end1:
.size _Z15time_differenceP8timespecS0_Px, .Lfunc_end1-_Z15time_differenceP8timespecS0_Px
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI2_0:
.quad 0x41cdcd6500000000 # double 1.0E+9
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
leaq 48(%rsp), %rsi
movl $1, %edi
callq clock_gettime
movabsq $4294967322, %rdi # imm = 0x10000001A
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_2
# %bb.1:
movq %rsp, %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq (%rsp), %rsi
movl 8(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z6kernelv, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_2:
callq hipDeviceSynchronize
movq %rsp, %rsi
movl $1, %edi
callq clock_gettime
movq (%rsp), %rax
subq 48(%rsp), %rax
movq 8(%rsp), %rcx
subq 56(%rsp), %rcx
leaq 1000000000(%rcx), %rdx
movq %rcx, %rsi
sarq $63, %rsi
addq %rax, %rsi
testq %rcx, %rcx
cmovnsq %rcx, %rdx
imulq $1000000000, %rsi, %rsi # imm = 0x3B9ACA00
addq %rdx, %rsi
cvtsi2sd %rsi, %xmm0
divsd .LCPI2_0(%rip), %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
xorl %eax, %eax
addq $72, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6kernelv, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6kernelv,@object # @_Z6kernelv
.section .rodata,"a",@progbits
.globl _Z6kernelv
.p2align 3, 0x0
_Z6kernelv:
.quad _Z21__device_stub__kernelv
.size _Z6kernelv, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Time elapsed was %lldns or %0.9lfs\n"
.size .L.str, 36
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z6kernelv"
.size .L__unnamed_1, 11
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__kernelv
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6kernelv
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void simple_reduction(int *shared_var, int *input_values, int N, int iters)
{
__shared__ int local_mem[256];
int iter, i;
int tid = blockIdx.x * blockDim.x + threadIdx.x;
int local_tid = threadIdx.x;
int local_dim = blockDim.x;
int minThreadInThisBlock = blockIdx.x * blockDim.x;
int maxThreadInThisBlock = minThreadInThisBlock + (blockDim.x - 1);
if (maxThreadInThisBlock >= N)
{
local_dim = N - minThreadInThisBlock;
}
for (iter = 0; iter < iters; iter++)
{
if (tid < N)
{
local_mem[local_tid] = input_values[tid];
}
// Required for correctness
// __syncthreads();
/*
* Perform the local reduction across values written to shared memory
* by threads in this thread block.
*/
if (local_tid == 0)
{
int sum = 0;
for (i = 0; i < local_dim; i++)
{
sum = sum + local_mem[i];
}
atomicAdd(shared_var, sum);
}
// Required for correctness
// __syncthreads();
}
} | code for sm_80
Function : _Z16simple_reductionPiS_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R7, SR_CTAID.X ; /* 0x0000000000077919 */
/* 0x000e220000002500 */
/*0020*/ IMAD.MOV.U32 R6, RZ, RZ, c[0x0][0x174] ; /* 0x00005d00ff067624 */
/* 0x000fe400078e00ff */
/*0030*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff047624 */
/* 0x000fc600078e00ff */
/*0040*/ ISETP.GE.AND P0, PT, R6, 0x1, PT ; /* 0x000000010600780c */
/* 0x000fda0003f06270 */
/*0050*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0060*/ IMAD R2, R7, R4, c[0x0][0x0] ; /* 0x0000000007027624 */
/* 0x001fe200078e0204 */
/*0070*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e220000002100 */
/*0080*/ IMAD.MOV R3, RZ, RZ, -R7 ; /* 0x000000ffff037224 */
/* 0x000fe200078e0a07 */
/*0090*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*00a0*/ IMAD.MOV.U32 R25, RZ, RZ, 0x4 ; /* 0x00000004ff197424 */
/* 0x000fe200078e00ff */
/*00b0*/ IADD3 R2, R2, -0x1, RZ ; /* 0xffffffff02027810 */
/* 0x000fe20007ffe0ff */
/*00c0*/ IMAD R3, R4, R3, c[0x0][0x170] ; /* 0x00005c0004037624 */
/* 0x000fc600078e0203 */
/*00d0*/ ISETP.GE.AND P0, PT, R2, c[0x0][0x170], PT ; /* 0x00005c0002007a0c */
/* 0x000fc80003f06270 */
/*00e0*/ SEL R5, R3, c[0x0][0x0], P0 ; /* 0x0000000003057a07 */
/* 0x000fc80000000000 */
/*00f0*/ ISETP.GT.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe20003f04270 */
/*0100*/ IMAD R22, R7, c[0x0][0x0], R0 ; /* 0x0000000007167a24 */
/* 0x001fc800078e0200 */
/*0110*/ IMAD.WIDE R24, R22, R25, c[0x0][0x168] ; /* 0x00005a0016187625 */
/* 0x000fd000078e0219 */
/*0120*/ @P0 BRA 0x530 ; /* 0x0000040000000947 */
/* 0x000fea0003800000 */
/*0130*/ IADD3 R2, R6.reuse, -0x1, RZ ; /* 0xffffffff06027810 */
/* 0x040fe40007ffe0ff */
/*0140*/ LOP3.LUT R4, R6, 0x3, RZ, 0xc0, !PT ; /* 0x0000000306047812 */
/* 0x000fe400078ec0ff */
/*0150*/ ISETP.GE.U32.AND P0, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fda0003f06070 */
/*0160*/ @!P0 BRA 0x400 ; /* 0x0000029000008947 */
/* 0x000fea0003800000 */
/*0170*/ ISETP.GE.AND P0, PT, R22, c[0x0][0x170], PT ; /* 0x00005c0016007a0c */
/* 0x000fe40003f06270 */
/*0180*/ IADD3 R5, -R4, c[0x0][0x174], RZ ; /* 0x00005d0004057a10 */
/* 0x000fd60007ffe1ff */
/*0190*/ @!P0 LDG.E R7, [R24.64] ; /* 0x0000000618078981 */
/* 0x005ea2000c1e1900 */
/*01a0*/ ISETP.NE.AND P1, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe20003f25270 */
/*01b0*/ BSSY B0, 0x240 ; /* 0x0000008000007945 */
/* 0x000fe20003800000 */
/*01c0*/ IADD3 R5, R5, -0x4, RZ ; /* 0xfffffffc05057810 */
/* 0x000fe20007ffe0ff */
/*01d0*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff027624 */
/* 0x01afe400078e00ff */
/*01e0*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff037624 */
/* 0x000fe200078e00ff */
/*01f0*/ ISETP.NE.AND P2, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe20003f45270 */
/*0200*/ @!P0 STS [R0.X4], R7 ; /* 0x0000000700008388 */
/* 0x0041ec0000004800 */
/*0210*/ @P1 BRA 0x230 ; /* 0x0000001000001947 */
/* 0x000fea0003800000 */
/*0220*/ RED.E.ADD.STRONG.GPU [R2.64], RZ ; /* 0x000000ff0200798e */
/* 0x0003e4000c10e186 */
/*0230*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0240*/ BSSY B0, 0x290 ; /* 0x0000004000007945 */
/* 0x000fe20003800000 */
/*0250*/ @P0 BRA 0x280 ; /* 0x0000002000000947 */
/* 0x000fea0003800000 */
/*0260*/ LDG.E R7, [R24.64] ; /* 0x0000000618077981 */
/* 0x001ea8000c1e1900 */
/*0270*/ STS [R0.X4], R7 ; /* 0x0000000700007388 */
/* 0x0041e40000004800 */
/*0280*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0290*/ BSSY B0, 0x2d0 ; /* 0x0000003000007945 */
/* 0x000fe20003800000 */
/*02a0*/ @P1 BRA 0x2c0 ; /* 0x0000001000001947 */
/* 0x000fea0003800000 */
/*02b0*/ RED.E.ADD.STRONG.GPU [R2.64], RZ ; /* 0x000000ff0200798e */
/* 0x0005e4000c10e186 */
/*02c0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*02d0*/ BSSY B0, 0x320 ; /* 0x0000004000007945 */
/* 0x000fe20003800000 */
/*02e0*/ @P0 BRA 0x310 ; /* 0x0000002000000947 */
/* 0x000fea0003800000 */
/*02f0*/ LDG.E R7, [R24.64] ; /* 0x0000000618077981 */
/* 0x001ee8000c1e1900 */
/*0300*/ STS [R0.X4], R7 ; /* 0x0000000700007388 */
/* 0x0081e40000004800 */
/*0310*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0320*/ BSSY B0, 0x360 ; /* 0x0000003000007945 */
/* 0x000fe20003800000 */
/*0330*/ @P1 BRA 0x350 ; /* 0x0000001000001947 */
/* 0x000fea0003800000 */
/*0340*/ RED.E.ADD.STRONG.GPU [R2.64], RZ ; /* 0x000000ff0200798e */
/* 0x0007e4000c10e186 */
/*0350*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0360*/ BSSY B0, 0x3b0 ; /* 0x0000004000007945 */
/* 0x000fe20003800000 */
/*0370*/ @P0 BRA 0x3a0 ; /* 0x0000002000000947 */
/* 0x000fea0003800000 */
/*0380*/ LDG.E R7, [R24.64] ; /* 0x0000000618077981 */
/* 0x001f28000c1e1900 */
/*0390*/ STS [R0.X4], R7 ; /* 0x0000000700007388 */
/* 0x0101e40000004800 */
/*03a0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*03b0*/ BSSY B0, 0x3f0 ; /* 0x0000003000007945 */
/* 0x000fe20003800000 */
/*03c0*/ @P1 BRA 0x3e0 ; /* 0x0000001000001947 */
/* 0x000fea0003800000 */
/*03d0*/ RED.E.ADD.STRONG.GPU [R2.64], RZ ; /* 0x000000ff0200798e */
/* 0x0009e4000c10e186 */
/*03e0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*03f0*/ @P2 BRA 0x190 ; /* 0xfffffd9000002947 */
/* 0x000fea000383ffff */
/*0400*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fda0003f05270 */
/*0410*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0420*/ ISETP.GE.AND P1, PT, R22, c[0x0][0x170], PT ; /* 0x00005c0016007a0c */
/* 0x000fd00003f26270 */
/*0430*/ IADD3 R4, R4, -0x1, RZ ; /* 0xffffffff04047810 */
/* 0x000fe20007ffe0ff */
/*0440*/ BSSY B0, 0x4b0 ; /* 0x0000006000007945 */
/* 0x000fe20003800000 */
/*0450*/ ISETP.NE.AND P2, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe40003f45270 */
/*0460*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fe20003f05270 */
/*0470*/ @P1 BRA 0x4a0 ; /* 0x0000002000001947 */
/* 0x006fee0003800000 */
/*0480*/ LDG.E R3, [R24.64] ; /* 0x0000000618037981 */
/* 0x01eea8000c1e1900 */
/*0490*/ STS [R0.X4], R3 ; /* 0x0000000300007388 */
/* 0x0043e40000004800 */
/*04a0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*04b0*/ BSSY B0, 0x510 ; /* 0x0000005000007945 */
/* 0x000fe20003800000 */
/*04c0*/ @P2 BRA 0x500 ; /* 0x0000003000002947 */
/* 0x000fea0003800000 */
/*04d0*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff027624 */
/* 0x01efe400078e00ff */
/*04e0*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff037624 */
/* 0x000fca00078e00ff */
/*04f0*/ RED.E.ADD.STRONG.GPU [R2.64], RZ ; /* 0x000000ff0200798e */
/* 0x0003e4000c10e186 */
/*0500*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0510*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0520*/ BRA 0x430 ; /* 0xffffff0000007947 */
/* 0x000fea000383ffff */
/*0530*/ IADD3 R2, R5, -0x1, RZ ; /* 0xffffffff05027810 */
/* 0x000fe20007ffe0ff */
/*0540*/ IMAD.MOV.U32 R3, RZ, RZ, RZ ; /* 0x000000ffff037224 */
/* 0x000fc600078e00ff */
/*0550*/ ISETP.GE.U32.AND P1, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fe40003f26070 */
/*0560*/ LOP3.LUT R2, R5, 0x3, RZ, 0xc0, !PT ; /* 0x0000000305027812 */
/* 0x000fca00078ec0ff */
/*0570*/ IMAD.IADD R20, R5, 0x1, -R2 ; /* 0x0000000105147824 */
/* 0x000fe400078e0a02 */
/*0580*/ ISETP.GE.AND P0, PT, R22, c[0x0][0x170], PT ; /* 0x00005c0016007a0c */
/* 0x000fda0003f06270 */
/*0590*/ @!P0 LDG.E R5, [R24.64] ; /* 0x0000000618058981 */
/* 0x000ea2000c1e1900 */
/*05a0*/ IADD3 R3, R3, 0x1, RZ ; /* 0x0000000103037810 */
/* 0x000fe20007ffe0ff */
/*05b0*/ BSSY B0, 0xa10 ; /* 0x0000045000007945 */
/* 0x000fe60003800000 */
/*05c0*/ ISETP.GE.AND P2, PT, R3, c[0x0][0x174], PT ; /* 0x00005d0003007a0c */
/* 0x000fe20003f46270 */
/*05d0*/ @!P0 STS [R0.X4], R5 ; /* 0x0000000500008388 */
/* 0x0041e20000004800 */
/*05e0*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fda0003f05270 */
/*05f0*/ @P0 BRA 0xa00 ; /* 0x0000040000000947 */
/* 0x000fea0003800000 */
/*0600*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x001fe20008000000 */
/*0610*/ IMAD.MOV.U32 R21, RZ, RZ, RZ ; /* 0x000000ffff157224 */
/* 0x000fe200078e00ff */
/*0620*/ @!P1 BRA 0x930 ; /* 0x0000030000009947 */
/* 0x000fea0003800000 */
/*0630*/ ISETP.GT.AND P0, PT, R20, RZ, PT ; /* 0x000000ff1400720c */
/* 0x000fe20003f04270 */
/*0640*/ UMOV UR5, URZ ; /* 0x0000003f00057c82 */
/* 0x000fe20008000000 */
/*0650*/ IMAD.MOV.U32 R21, RZ, RZ, RZ ; /* 0x000000ffff157224 */
/* 0x000fe400078e00ff */
/*0660*/ IMAD.MOV.U32 R23, RZ, RZ, R20 ; /* 0x000000ffff177224 */
/* 0x000fd200078e0014 */
/*0670*/ @!P0 BRA 0x8b0 ; /* 0x0000023000008947 */
/* 0x000fea0003800000 */
/*0680*/ ISETP.GT.AND P3, PT, R23, 0xc, PT ; /* 0x0000000c1700780c */
/* 0x000fe40003f64270 */
/*0690*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*06a0*/ @!P3 BRA 0x7d0 ; /* 0x000001200000b947 */
/* 0x000fea0003800000 */
/*06b0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*06c0*/ LDS.128 R4, [UR5] ; /* 0x00000005ff047984 */
/* 0x000e220008000c00 */
/*06d0*/ IADD3 R23, R23, -0x10, RZ ; /* 0xfffffff017177810 */
/* 0x000fe20007ffe0ff */
/*06e0*/ UIADD3 UR4, UR4, 0x10, URZ ; /* 0x0000001004047890 */
/* 0x000fe4000fffe03f */
/*06f0*/ LDS.128 R8, [UR5+0x10] ; /* 0x00001005ff087984 */
/* 0x000e620008000c00 */
/*0700*/ ISETP.GT.AND P3, PT, R23, 0xc, PT ; /* 0x0000000c1700780c */
/* 0x000fc60003f64270 */
/*0710*/ LDS.128 R12, [UR5+0x20] ; /* 0x00002005ff0c7984 */
/* 0x000ea80008000c00 */
/*0720*/ LDS.128 R16, [UR5+0x30] ; /* 0x00003005ff107984 */
/* 0x000ee20008000c00 */
/*0730*/ UIADD3 UR5, UR5, 0x40, URZ ; /* 0x0000004005057890 */
/* 0x000fe2000fffe03f */
/*0740*/ IADD3 R4, R5, R4, R21 ; /* 0x0000000405047210 */
/* 0x001fc80007ffe015 */
/*0750*/ IADD3 R4, R7, R6, R4 ; /* 0x0000000607047210 */
/* 0x000fc80007ffe004 */
/*0760*/ IADD3 R4, R9, R8, R4 ; /* 0x0000000809047210 */
/* 0x002fc80007ffe004 */
/*0770*/ IADD3 R4, R11, R10, R4 ; /* 0x0000000a0b047210 */
/* 0x000fc80007ffe004 */
/*0780*/ IADD3 R4, R13, R12, R4 ; /* 0x0000000c0d047210 */
/* 0x004fc80007ffe004 */
/*0790*/ IADD3 R4, R15, R14, R4 ; /* 0x0000000e0f047210 */
/* 0x000fc80007ffe004 */
/*07a0*/ IADD3 R4, R17, R16, R4 ; /* 0x0000001011047210 */
/* 0x008fc80007ffe004 */
/*07b0*/ IADD3 R21, R19, R18, R4 ; /* 0x0000001213157210 */
/* 0x000fe20007ffe004 */
/*07c0*/ @P3 BRA 0x6c0 ; /* 0xfffffef000003947 */
/* 0x000fea000383ffff */
/*07d0*/ ISETP.GT.AND P3, PT, R23, 0x4, PT ; /* 0x000000041700780c */
/* 0x000fda0003f64270 */
/*07e0*/ @!P3 BRA 0x890 ; /* 0x000000a00000b947 */
/* 0x000fea0003800000 */
/*07f0*/ LDS.128 R4, [UR5] ; /* 0x00000005ff047984 */
/* 0x000e220008000c00 */
/*0800*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe20003f0e170 */
/*0810*/ UIADD3 UR4, UR4, 0x8, URZ ; /* 0x0000000804047890 */
/* 0x000fe2000fffe03f */
/*0820*/ IADD3 R23, R23, -0x8, RZ ; /* 0xfffffff817177810 */
/* 0x000fe20007ffe0ff */
/*0830*/ LDS.128 R8, [UR5+0x10] ; /* 0x00001005ff087984 */
/* 0x000e620008000c00 */
/*0840*/ UIADD3 UR5, UR5, 0x20, URZ ; /* 0x0000002005057890 */
/* 0x000fe2000fffe03f */
/*0850*/ IADD3 R4, R5, R4, R21 ; /* 0x0000000405047210 */
/* 0x001fc80007ffe015 */
/*0860*/ IADD3 R4, R7, R6, R4 ; /* 0x0000000607047210 */
/* 0x000fc80007ffe004 */
/*0870*/ IADD3 R4, R9, R8, R4 ; /* 0x0000000809047210 */
/* 0x002fc80007ffe004 */
/*0880*/ IADD3 R21, R11, R10, R4 ; /* 0x0000000a0b157210 */
/* 0x000fe40007ffe004 */
/*0890*/ ISETP.NE.OR P0, PT, R23, RZ, P0 ; /* 0x000000ff1700720c */
/* 0x000fda0000705670 */
/*08a0*/ @!P0 BRA 0x930 ; /* 0x0000008000008947 */
/* 0x000fea0003800000 */
/*08b0*/ LDS.128 R4, [UR5] ; /* 0x00000005ff047984 */
/* 0x000e220008000c00 */
/*08c0*/ IADD3 R23, R23, -0x4, RZ ; /* 0xfffffffc17177810 */
/* 0x000fe20007ffe0ff */
/*08d0*/ UIADD3 UR4, UR4, 0x4, URZ ; /* 0x0000000404047890 */
/* 0x000fe4000fffe03f */
/*08e0*/ UIADD3 UR5, UR5, 0x10, URZ ; /* 0x0000001005057890 */
/* 0x000fe2000fffe03f */
/*08f0*/ ISETP.NE.AND P0, PT, R23, RZ, PT ; /* 0x000000ff1700720c */
/* 0x000fe40003f05270 */
/*0900*/ IADD3 R4, R5, R4, R21 ; /* 0x0000000405047210 */
/* 0x001fc80007ffe015 */
/*0910*/ IADD3 R21, R7, R6, R4 ; /* 0x0000000607157210 */
/* 0x000fce0007ffe004 */
/*0920*/ @P0 BRA 0x8b0 ; /* 0xffffff8000000947 */
/* 0x000fea000383ffff */
/*0930*/ ISETP.NE.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fe20003f05270 */
/*0940*/ IMAD.MOV.U32 R8, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff087624 */
/* 0x000fe400078e00ff */
/*0950*/ IMAD.MOV.U32 R9, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff097624 */
/* 0x000fd400078e00ff */
/*0960*/ @!P0 BRA 0x9f0 ; /* 0x0000008000008947 */
/* 0x000fea0003800000 */
/*0970*/ USHF.L.U32 UR4, UR4, 0x2, URZ ; /* 0x0000000204047899 */
/* 0x000fe2000800063f */
/*0980*/ ISETP.NE.AND P0, PT, R2, 0x1, PT ; /* 0x000000010200780c */
/* 0x000fd00003f05270 */
/*0990*/ LDS.128 R4, [UR4] ; /* 0x00000004ff047984 */
/* 0x000e240008000c00 */
/*09a0*/ IMAD.IADD R21, R21, 0x1, R4 ; /* 0x0000000115157824 */
/* 0x001fc600078e0204 */
/*09b0*/ @!P0 BRA 0x9f0 ; /* 0x0000003000008947 */
/* 0x000fea0003800000 */
/*09c0*/ ISETP.NE.AND P0, PT, R2, 0x2, PT ; /* 0x000000020200780c */
/* 0x000fe20003f05270 */
/*09d0*/ IMAD.IADD R21, R21, 0x1, R5 ; /* 0x0000000115157824 */
/* 0x000fd800078e0205 */
/*09e0*/ @P0 IMAD.IADD R21, R21, 0x1, R6 ; /* 0x0000000115150824 */
/* 0x000fca00078e0206 */
/*09f0*/ RED.E.ADD.STRONG.GPU [R8.64], R21 ; /* 0x000000150800798e */
/* 0x0001e4000c10e186 */
/*0a00*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x001fea0003800000 */
/*0a10*/ @!P2 BRA 0x580 ; /* 0xfffffb600000a947 */
/* 0x000fea000383ffff */
/*0a20*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0a30*/ BRA 0xa30; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0a40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0aa0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ab0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ac0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ad0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ae0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0af0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void simple_reduction(int *shared_var, int *input_values, int N, int iters)
{
__shared__ int local_mem[256];
int iter, i;
int tid = blockIdx.x * blockDim.x + threadIdx.x;
int local_tid = threadIdx.x;
int local_dim = blockDim.x;
int minThreadInThisBlock = blockIdx.x * blockDim.x;
int maxThreadInThisBlock = minThreadInThisBlock + (blockDim.x - 1);
if (maxThreadInThisBlock >= N)
{
local_dim = N - minThreadInThisBlock;
}
for (iter = 0; iter < iters; iter++)
{
if (tid < N)
{
local_mem[local_tid] = input_values[tid];
}
// Required for correctness
// __syncthreads();
/*
* Perform the local reduction across values written to shared memory
* by threads in this thread block.
*/
if (local_tid == 0)
{
int sum = 0;
for (i = 0; i < local_dim; i++)
{
sum = sum + local_mem[i];
}
atomicAdd(shared_var, sum);
}
// Required for correctness
// __syncthreads();
}
} | .file "tmpxft_0007b913_00000000-6_simple_reduction.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z40__device_stub__Z16simple_reductionPiS_iiPiS_ii
.type _Z40__device_stub__Z16simple_reductionPiS_iiPiS_ii, @function
_Z40__device_stub__Z16simple_reductionPiS_iiPiS_ii:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z16simple_reductionPiS_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z40__device_stub__Z16simple_reductionPiS_iiPiS_ii, .-_Z40__device_stub__Z16simple_reductionPiS_iiPiS_ii
.globl _Z16simple_reductionPiS_ii
.type _Z16simple_reductionPiS_ii, @function
_Z16simple_reductionPiS_ii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z40__device_stub__Z16simple_reductionPiS_iiPiS_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z16simple_reductionPiS_ii, .-_Z16simple_reductionPiS_ii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z16simple_reductionPiS_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z16simple_reductionPiS_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void simple_reduction(int *shared_var, int *input_values, int N, int iters)
{
__shared__ int local_mem[256];
int iter, i;
int tid = blockIdx.x * blockDim.x + threadIdx.x;
int local_tid = threadIdx.x;
int local_dim = blockDim.x;
int minThreadInThisBlock = blockIdx.x * blockDim.x;
int maxThreadInThisBlock = minThreadInThisBlock + (blockDim.x - 1);
if (maxThreadInThisBlock >= N)
{
local_dim = N - minThreadInThisBlock;
}
for (iter = 0; iter < iters; iter++)
{
if (tid < N)
{
local_mem[local_tid] = input_values[tid];
}
// Required for correctness
// __syncthreads();
/*
* Perform the local reduction across values written to shared memory
* by threads in this thread block.
*/
if (local_tid == 0)
{
int sum = 0;
for (i = 0; i < local_dim; i++)
{
sum = sum + local_mem[i];
}
atomicAdd(shared_var, sum);
}
// Required for correctness
// __syncthreads();
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void simple_reduction(int *shared_var, int *input_values, int N, int iters)
{
__shared__ int local_mem[256];
int iter, i;
int tid = blockIdx.x * blockDim.x + threadIdx.x;
int local_tid = threadIdx.x;
int local_dim = blockDim.x;
int minThreadInThisBlock = blockIdx.x * blockDim.x;
int maxThreadInThisBlock = minThreadInThisBlock + (blockDim.x - 1);
if (maxThreadInThisBlock >= N)
{
local_dim = N - minThreadInThisBlock;
}
for (iter = 0; iter < iters; iter++)
{
if (tid < N)
{
local_mem[local_tid] = input_values[tid];
}
// Required for correctness
// __syncthreads();
/*
* Perform the local reduction across values written to shared memory
* by threads in this thread block.
*/
if (local_tid == 0)
{
int sum = 0;
for (i = 0; i < local_dim; i++)
{
sum = sum + local_mem[i];
}
atomicAdd(shared_var, sum);
}
// Required for correctness
// __syncthreads();
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void simple_reduction(int *shared_var, int *input_values, int N, int iters)
{
__shared__ int local_mem[256];
int iter, i;
int tid = blockIdx.x * blockDim.x + threadIdx.x;
int local_tid = threadIdx.x;
int local_dim = blockDim.x;
int minThreadInThisBlock = blockIdx.x * blockDim.x;
int maxThreadInThisBlock = minThreadInThisBlock + (blockDim.x - 1);
if (maxThreadInThisBlock >= N)
{
local_dim = N - minThreadInThisBlock;
}
for (iter = 0; iter < iters; iter++)
{
if (tid < N)
{
local_mem[local_tid] = input_values[tid];
}
// Required for correctness
// __syncthreads();
/*
* Perform the local reduction across values written to shared memory
* by threads in this thread block.
*/
if (local_tid == 0)
{
int sum = 0;
for (i = 0; i < local_dim; i++)
{
sum = sum + local_mem[i];
}
atomicAdd(shared_var, sum);
}
// Required for correctness
// __syncthreads();
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z16simple_reductionPiS_ii
.globl _Z16simple_reductionPiS_ii
.p2align 8
.type _Z16simple_reductionPiS_ii,@function
_Z16simple_reductionPiS_ii:
s_load_b32 s2, s[0:1], 0x14
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s2, 1
s_cbranch_scc1 .LBB0_11
s_clause 0x2
s_load_b32 s3, s[0:1], 0x24
s_load_b32 s8, s[0:1], 0x10
s_load_b128 s[4:7], s[0:1], 0x0
v_lshlrev_b32_e32 v2, 2, v0
s_waitcnt lgkmcnt(0)
s_and_b32 s1, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s15, s15, s1
v_add_nc_u32_e32 v3, s15, v0
s_add_i32 s0, s1, s15
s_sub_i32 s3, s8, s15
s_add_i32 s0, s0, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lt_i32 s0, s8
v_ashrrev_i32_e32 v4, 31, v3
v_cmp_eq_u32_e64 s0, 0, v0
s_cselect_b32 s3, s1, s3
v_cmp_gt_i32_e64 s1, s8, v3
s_cmp_gt_i32 s3, 0
v_lshlrev_b64 v[0:1], 2, v[3:4]
v_mov_b32_e32 v3, 0
s_cselect_b32 s8, -1, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v0, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
s_mov_b32 s6, 0
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_3
.p2align 6
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s7
s_add_i32 s6, s6, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lg_u32 s6, s2
s_cbranch_scc0 .LBB0_11
.LBB0_3:
s_and_saveexec_b32 s7, s1
s_cbranch_execz .LBB0_5
global_load_b32 v4, v[0:1], off
s_waitcnt vmcnt(0)
ds_store_b32 v2, v4
.LBB0_5:
s_or_b32 exec_lo, exec_lo, s7
s_and_saveexec_b32 s7, s0
s_cbranch_execz .LBB0_2
v_mov_b32_e32 v4, 0
s_and_not1_b32 vcc_lo, exec_lo, s8
s_cbranch_vccnz .LBB0_9
s_mov_b32 s9, 0
s_mov_b32 s10, s3
.LBB0_8:
v_mov_b32_e32 v5, s9
s_add_i32 s10, s10, -1
s_add_i32 s9, s9, 4
s_cmp_lg_u32 s10, 0
ds_load_b32 v5, v5
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v4, v5, v4
s_cbranch_scc1 .LBB0_8
.LBB0_9:
s_mov_b32 s9, exec_lo
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mbcnt_lo_u32_b32 v5, s9, 0
v_cmp_eq_u32_e32 vcc_lo, 0, v5
s_and_b32 s10, exec_lo, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 exec_lo, s10
s_cbranch_execz .LBB0_2
s_bcnt1_i32_b32 s9, s9
s_delay_alu instid0(SALU_CYCLE_1)
v_mul_lo_u32 v4, v4, s9
global_atomic_add_u32 v3, v4, s[4:5]
s_branch .LBB0_2
.LBB0_11:
s_set_inst_prefetch_distance 0x2
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z16simple_reductionPiS_ii
.amdhsa_group_segment_fixed_size 1024
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z16simple_reductionPiS_ii, .Lfunc_end0-_Z16simple_reductionPiS_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 1024
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z16simple_reductionPiS_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z16simple_reductionPiS_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void simple_reduction(int *shared_var, int *input_values, int N, int iters)
{
__shared__ int local_mem[256];
int iter, i;
int tid = blockIdx.x * blockDim.x + threadIdx.x;
int local_tid = threadIdx.x;
int local_dim = blockDim.x;
int minThreadInThisBlock = blockIdx.x * blockDim.x;
int maxThreadInThisBlock = minThreadInThisBlock + (blockDim.x - 1);
if (maxThreadInThisBlock >= N)
{
local_dim = N - minThreadInThisBlock;
}
for (iter = 0; iter < iters; iter++)
{
if (tid < N)
{
local_mem[local_tid] = input_values[tid];
}
// Required for correctness
// __syncthreads();
/*
* Perform the local reduction across values written to shared memory
* by threads in this thread block.
*/
if (local_tid == 0)
{
int sum = 0;
for (i = 0; i < local_dim; i++)
{
sum = sum + local_mem[i];
}
atomicAdd(shared_var, sum);
}
// Required for correctness
// __syncthreads();
}
} | .text
.file "simple_reduction.hip"
.globl _Z31__device_stub__simple_reductionPiS_ii # -- Begin function _Z31__device_stub__simple_reductionPiS_ii
.p2align 4, 0x90
.type _Z31__device_stub__simple_reductionPiS_ii,@function
_Z31__device_stub__simple_reductionPiS_ii: # @_Z31__device_stub__simple_reductionPiS_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z16simple_reductionPiS_ii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z31__device_stub__simple_reductionPiS_ii, .Lfunc_end0-_Z31__device_stub__simple_reductionPiS_ii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z16simple_reductionPiS_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z16simple_reductionPiS_ii,@object # @_Z16simple_reductionPiS_ii
.section .rodata,"a",@progbits
.globl _Z16simple_reductionPiS_ii
.p2align 3, 0x0
_Z16simple_reductionPiS_ii:
.quad _Z31__device_stub__simple_reductionPiS_ii
.size _Z16simple_reductionPiS_ii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z16simple_reductionPiS_ii"
.size .L__unnamed_1, 27
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z31__device_stub__simple_reductionPiS_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z16simple_reductionPiS_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z16simple_reductionPiS_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R7, SR_CTAID.X ; /* 0x0000000000077919 */
/* 0x000e220000002500 */
/*0020*/ IMAD.MOV.U32 R6, RZ, RZ, c[0x0][0x174] ; /* 0x00005d00ff067624 */
/* 0x000fe400078e00ff */
/*0030*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff047624 */
/* 0x000fc600078e00ff */
/*0040*/ ISETP.GE.AND P0, PT, R6, 0x1, PT ; /* 0x000000010600780c */
/* 0x000fda0003f06270 */
/*0050*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0060*/ IMAD R2, R7, R4, c[0x0][0x0] ; /* 0x0000000007027624 */
/* 0x001fe200078e0204 */
/*0070*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e220000002100 */
/*0080*/ IMAD.MOV R3, RZ, RZ, -R7 ; /* 0x000000ffff037224 */
/* 0x000fe200078e0a07 */
/*0090*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*00a0*/ IMAD.MOV.U32 R25, RZ, RZ, 0x4 ; /* 0x00000004ff197424 */
/* 0x000fe200078e00ff */
/*00b0*/ IADD3 R2, R2, -0x1, RZ ; /* 0xffffffff02027810 */
/* 0x000fe20007ffe0ff */
/*00c0*/ IMAD R3, R4, R3, c[0x0][0x170] ; /* 0x00005c0004037624 */
/* 0x000fc600078e0203 */
/*00d0*/ ISETP.GE.AND P0, PT, R2, c[0x0][0x170], PT ; /* 0x00005c0002007a0c */
/* 0x000fc80003f06270 */
/*00e0*/ SEL R5, R3, c[0x0][0x0], P0 ; /* 0x0000000003057a07 */
/* 0x000fc80000000000 */
/*00f0*/ ISETP.GT.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe20003f04270 */
/*0100*/ IMAD R22, R7, c[0x0][0x0], R0 ; /* 0x0000000007167a24 */
/* 0x001fc800078e0200 */
/*0110*/ IMAD.WIDE R24, R22, R25, c[0x0][0x168] ; /* 0x00005a0016187625 */
/* 0x000fd000078e0219 */
/*0120*/ @P0 BRA 0x530 ; /* 0x0000040000000947 */
/* 0x000fea0003800000 */
/*0130*/ IADD3 R2, R6.reuse, -0x1, RZ ; /* 0xffffffff06027810 */
/* 0x040fe40007ffe0ff */
/*0140*/ LOP3.LUT R4, R6, 0x3, RZ, 0xc0, !PT ; /* 0x0000000306047812 */
/* 0x000fe400078ec0ff */
/*0150*/ ISETP.GE.U32.AND P0, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fda0003f06070 */
/*0160*/ @!P0 BRA 0x400 ; /* 0x0000029000008947 */
/* 0x000fea0003800000 */
/*0170*/ ISETP.GE.AND P0, PT, R22, c[0x0][0x170], PT ; /* 0x00005c0016007a0c */
/* 0x000fe40003f06270 */
/*0180*/ IADD3 R5, -R4, c[0x0][0x174], RZ ; /* 0x00005d0004057a10 */
/* 0x000fd60007ffe1ff */
/*0190*/ @!P0 LDG.E R7, [R24.64] ; /* 0x0000000618078981 */
/* 0x005ea2000c1e1900 */
/*01a0*/ ISETP.NE.AND P1, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe20003f25270 */
/*01b0*/ BSSY B0, 0x240 ; /* 0x0000008000007945 */
/* 0x000fe20003800000 */
/*01c0*/ IADD3 R5, R5, -0x4, RZ ; /* 0xfffffffc05057810 */
/* 0x000fe20007ffe0ff */
/*01d0*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff027624 */
/* 0x01afe400078e00ff */
/*01e0*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff037624 */
/* 0x000fe200078e00ff */
/*01f0*/ ISETP.NE.AND P2, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe20003f45270 */
/*0200*/ @!P0 STS [R0.X4], R7 ; /* 0x0000000700008388 */
/* 0x0041ec0000004800 */
/*0210*/ @P1 BRA 0x230 ; /* 0x0000001000001947 */
/* 0x000fea0003800000 */
/*0220*/ RED.E.ADD.STRONG.GPU [R2.64], RZ ; /* 0x000000ff0200798e */
/* 0x0003e4000c10e186 */
/*0230*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0240*/ BSSY B0, 0x290 ; /* 0x0000004000007945 */
/* 0x000fe20003800000 */
/*0250*/ @P0 BRA 0x280 ; /* 0x0000002000000947 */
/* 0x000fea0003800000 */
/*0260*/ LDG.E R7, [R24.64] ; /* 0x0000000618077981 */
/* 0x001ea8000c1e1900 */
/*0270*/ STS [R0.X4], R7 ; /* 0x0000000700007388 */
/* 0x0041e40000004800 */
/*0280*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0290*/ BSSY B0, 0x2d0 ; /* 0x0000003000007945 */
/* 0x000fe20003800000 */
/*02a0*/ @P1 BRA 0x2c0 ; /* 0x0000001000001947 */
/* 0x000fea0003800000 */
/*02b0*/ RED.E.ADD.STRONG.GPU [R2.64], RZ ; /* 0x000000ff0200798e */
/* 0x0005e4000c10e186 */
/*02c0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*02d0*/ BSSY B0, 0x320 ; /* 0x0000004000007945 */
/* 0x000fe20003800000 */
/*02e0*/ @P0 BRA 0x310 ; /* 0x0000002000000947 */
/* 0x000fea0003800000 */
/*02f0*/ LDG.E R7, [R24.64] ; /* 0x0000000618077981 */
/* 0x001ee8000c1e1900 */
/*0300*/ STS [R0.X4], R7 ; /* 0x0000000700007388 */
/* 0x0081e40000004800 */
/*0310*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0320*/ BSSY B0, 0x360 ; /* 0x0000003000007945 */
/* 0x000fe20003800000 */
/*0330*/ @P1 BRA 0x350 ; /* 0x0000001000001947 */
/* 0x000fea0003800000 */
/*0340*/ RED.E.ADD.STRONG.GPU [R2.64], RZ ; /* 0x000000ff0200798e */
/* 0x0007e4000c10e186 */
/*0350*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0360*/ BSSY B0, 0x3b0 ; /* 0x0000004000007945 */
/* 0x000fe20003800000 */
/*0370*/ @P0 BRA 0x3a0 ; /* 0x0000002000000947 */
/* 0x000fea0003800000 */
/*0380*/ LDG.E R7, [R24.64] ; /* 0x0000000618077981 */
/* 0x001f28000c1e1900 */
/*0390*/ STS [R0.X4], R7 ; /* 0x0000000700007388 */
/* 0x0101e40000004800 */
/*03a0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*03b0*/ BSSY B0, 0x3f0 ; /* 0x0000003000007945 */
/* 0x000fe20003800000 */
/*03c0*/ @P1 BRA 0x3e0 ; /* 0x0000001000001947 */
/* 0x000fea0003800000 */
/*03d0*/ RED.E.ADD.STRONG.GPU [R2.64], RZ ; /* 0x000000ff0200798e */
/* 0x0009e4000c10e186 */
/*03e0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*03f0*/ @P2 BRA 0x190 ; /* 0xfffffd9000002947 */
/* 0x000fea000383ffff */
/*0400*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fda0003f05270 */
/*0410*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0420*/ ISETP.GE.AND P1, PT, R22, c[0x0][0x170], PT ; /* 0x00005c0016007a0c */
/* 0x000fd00003f26270 */
/*0430*/ IADD3 R4, R4, -0x1, RZ ; /* 0xffffffff04047810 */
/* 0x000fe20007ffe0ff */
/*0440*/ BSSY B0, 0x4b0 ; /* 0x0000006000007945 */
/* 0x000fe20003800000 */
/*0450*/ ISETP.NE.AND P2, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe40003f45270 */
/*0460*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fe20003f05270 */
/*0470*/ @P1 BRA 0x4a0 ; /* 0x0000002000001947 */
/* 0x006fee0003800000 */
/*0480*/ LDG.E R3, [R24.64] ; /* 0x0000000618037981 */
/* 0x01eea8000c1e1900 */
/*0490*/ STS [R0.X4], R3 ; /* 0x0000000300007388 */
/* 0x0043e40000004800 */
/*04a0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*04b0*/ BSSY B0, 0x510 ; /* 0x0000005000007945 */
/* 0x000fe20003800000 */
/*04c0*/ @P2 BRA 0x500 ; /* 0x0000003000002947 */
/* 0x000fea0003800000 */
/*04d0*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff027624 */
/* 0x01efe400078e00ff */
/*04e0*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff037624 */
/* 0x000fca00078e00ff */
/*04f0*/ RED.E.ADD.STRONG.GPU [R2.64], RZ ; /* 0x000000ff0200798e */
/* 0x0003e4000c10e186 */
/*0500*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0510*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0520*/ BRA 0x430 ; /* 0xffffff0000007947 */
/* 0x000fea000383ffff */
/*0530*/ IADD3 R2, R5, -0x1, RZ ; /* 0xffffffff05027810 */
/* 0x000fe20007ffe0ff */
/*0540*/ IMAD.MOV.U32 R3, RZ, RZ, RZ ; /* 0x000000ffff037224 */
/* 0x000fc600078e00ff */
/*0550*/ ISETP.GE.U32.AND P1, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fe40003f26070 */
/*0560*/ LOP3.LUT R2, R5, 0x3, RZ, 0xc0, !PT ; /* 0x0000000305027812 */
/* 0x000fca00078ec0ff */
/*0570*/ IMAD.IADD R20, R5, 0x1, -R2 ; /* 0x0000000105147824 */
/* 0x000fe400078e0a02 */
/*0580*/ ISETP.GE.AND P0, PT, R22, c[0x0][0x170], PT ; /* 0x00005c0016007a0c */
/* 0x000fda0003f06270 */
/*0590*/ @!P0 LDG.E R5, [R24.64] ; /* 0x0000000618058981 */
/* 0x000ea2000c1e1900 */
/*05a0*/ IADD3 R3, R3, 0x1, RZ ; /* 0x0000000103037810 */
/* 0x000fe20007ffe0ff */
/*05b0*/ BSSY B0, 0xa10 ; /* 0x0000045000007945 */
/* 0x000fe60003800000 */
/*05c0*/ ISETP.GE.AND P2, PT, R3, c[0x0][0x174], PT ; /* 0x00005d0003007a0c */
/* 0x000fe20003f46270 */
/*05d0*/ @!P0 STS [R0.X4], R5 ; /* 0x0000000500008388 */
/* 0x0041e20000004800 */
/*05e0*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fda0003f05270 */
/*05f0*/ @P0 BRA 0xa00 ; /* 0x0000040000000947 */
/* 0x000fea0003800000 */
/*0600*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x001fe20008000000 */
/*0610*/ IMAD.MOV.U32 R21, RZ, RZ, RZ ; /* 0x000000ffff157224 */
/* 0x000fe200078e00ff */
/*0620*/ @!P1 BRA 0x930 ; /* 0x0000030000009947 */
/* 0x000fea0003800000 */
/*0630*/ ISETP.GT.AND P0, PT, R20, RZ, PT ; /* 0x000000ff1400720c */
/* 0x000fe20003f04270 */
/*0640*/ UMOV UR5, URZ ; /* 0x0000003f00057c82 */
/* 0x000fe20008000000 */
/*0650*/ IMAD.MOV.U32 R21, RZ, RZ, RZ ; /* 0x000000ffff157224 */
/* 0x000fe400078e00ff */
/*0660*/ IMAD.MOV.U32 R23, RZ, RZ, R20 ; /* 0x000000ffff177224 */
/* 0x000fd200078e0014 */
/*0670*/ @!P0 BRA 0x8b0 ; /* 0x0000023000008947 */
/* 0x000fea0003800000 */
/*0680*/ ISETP.GT.AND P3, PT, R23, 0xc, PT ; /* 0x0000000c1700780c */
/* 0x000fe40003f64270 */
/*0690*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*06a0*/ @!P3 BRA 0x7d0 ; /* 0x000001200000b947 */
/* 0x000fea0003800000 */
/*06b0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*06c0*/ LDS.128 R4, [UR5] ; /* 0x00000005ff047984 */
/* 0x000e220008000c00 */
/*06d0*/ IADD3 R23, R23, -0x10, RZ ; /* 0xfffffff017177810 */
/* 0x000fe20007ffe0ff */
/*06e0*/ UIADD3 UR4, UR4, 0x10, URZ ; /* 0x0000001004047890 */
/* 0x000fe4000fffe03f */
/*06f0*/ LDS.128 R8, [UR5+0x10] ; /* 0x00001005ff087984 */
/* 0x000e620008000c00 */
/*0700*/ ISETP.GT.AND P3, PT, R23, 0xc, PT ; /* 0x0000000c1700780c */
/* 0x000fc60003f64270 */
/*0710*/ LDS.128 R12, [UR5+0x20] ; /* 0x00002005ff0c7984 */
/* 0x000ea80008000c00 */
/*0720*/ LDS.128 R16, [UR5+0x30] ; /* 0x00003005ff107984 */
/* 0x000ee20008000c00 */
/*0730*/ UIADD3 UR5, UR5, 0x40, URZ ; /* 0x0000004005057890 */
/* 0x000fe2000fffe03f */
/*0740*/ IADD3 R4, R5, R4, R21 ; /* 0x0000000405047210 */
/* 0x001fc80007ffe015 */
/*0750*/ IADD3 R4, R7, R6, R4 ; /* 0x0000000607047210 */
/* 0x000fc80007ffe004 */
/*0760*/ IADD3 R4, R9, R8, R4 ; /* 0x0000000809047210 */
/* 0x002fc80007ffe004 */
/*0770*/ IADD3 R4, R11, R10, R4 ; /* 0x0000000a0b047210 */
/* 0x000fc80007ffe004 */
/*0780*/ IADD3 R4, R13, R12, R4 ; /* 0x0000000c0d047210 */
/* 0x004fc80007ffe004 */
/*0790*/ IADD3 R4, R15, R14, R4 ; /* 0x0000000e0f047210 */
/* 0x000fc80007ffe004 */
/*07a0*/ IADD3 R4, R17, R16, R4 ; /* 0x0000001011047210 */
/* 0x008fc80007ffe004 */
/*07b0*/ IADD3 R21, R19, R18, R4 ; /* 0x0000001213157210 */
/* 0x000fe20007ffe004 */
/*07c0*/ @P3 BRA 0x6c0 ; /* 0xfffffef000003947 */
/* 0x000fea000383ffff */
/*07d0*/ ISETP.GT.AND P3, PT, R23, 0x4, PT ; /* 0x000000041700780c */
/* 0x000fda0003f64270 */
/*07e0*/ @!P3 BRA 0x890 ; /* 0x000000a00000b947 */
/* 0x000fea0003800000 */
/*07f0*/ LDS.128 R4, [UR5] ; /* 0x00000005ff047984 */
/* 0x000e220008000c00 */
/*0800*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe20003f0e170 */
/*0810*/ UIADD3 UR4, UR4, 0x8, URZ ; /* 0x0000000804047890 */
/* 0x000fe2000fffe03f */
/*0820*/ IADD3 R23, R23, -0x8, RZ ; /* 0xfffffff817177810 */
/* 0x000fe20007ffe0ff */
/*0830*/ LDS.128 R8, [UR5+0x10] ; /* 0x00001005ff087984 */
/* 0x000e620008000c00 */
/*0840*/ UIADD3 UR5, UR5, 0x20, URZ ; /* 0x0000002005057890 */
/* 0x000fe2000fffe03f */
/*0850*/ IADD3 R4, R5, R4, R21 ; /* 0x0000000405047210 */
/* 0x001fc80007ffe015 */
/*0860*/ IADD3 R4, R7, R6, R4 ; /* 0x0000000607047210 */
/* 0x000fc80007ffe004 */
/*0870*/ IADD3 R4, R9, R8, R4 ; /* 0x0000000809047210 */
/* 0x002fc80007ffe004 */
/*0880*/ IADD3 R21, R11, R10, R4 ; /* 0x0000000a0b157210 */
/* 0x000fe40007ffe004 */
/*0890*/ ISETP.NE.OR P0, PT, R23, RZ, P0 ; /* 0x000000ff1700720c */
/* 0x000fda0000705670 */
/*08a0*/ @!P0 BRA 0x930 ; /* 0x0000008000008947 */
/* 0x000fea0003800000 */
/*08b0*/ LDS.128 R4, [UR5] ; /* 0x00000005ff047984 */
/* 0x000e220008000c00 */
/*08c0*/ IADD3 R23, R23, -0x4, RZ ; /* 0xfffffffc17177810 */
/* 0x000fe20007ffe0ff */
/*08d0*/ UIADD3 UR4, UR4, 0x4, URZ ; /* 0x0000000404047890 */
/* 0x000fe4000fffe03f */
/*08e0*/ UIADD3 UR5, UR5, 0x10, URZ ; /* 0x0000001005057890 */
/* 0x000fe2000fffe03f */
/*08f0*/ ISETP.NE.AND P0, PT, R23, RZ, PT ; /* 0x000000ff1700720c */
/* 0x000fe40003f05270 */
/*0900*/ IADD3 R4, R5, R4, R21 ; /* 0x0000000405047210 */
/* 0x001fc80007ffe015 */
/*0910*/ IADD3 R21, R7, R6, R4 ; /* 0x0000000607157210 */
/* 0x000fce0007ffe004 */
/*0920*/ @P0 BRA 0x8b0 ; /* 0xffffff8000000947 */
/* 0x000fea000383ffff */
/*0930*/ ISETP.NE.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fe20003f05270 */
/*0940*/ IMAD.MOV.U32 R8, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff087624 */
/* 0x000fe400078e00ff */
/*0950*/ IMAD.MOV.U32 R9, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff097624 */
/* 0x000fd400078e00ff */
/*0960*/ @!P0 BRA 0x9f0 ; /* 0x0000008000008947 */
/* 0x000fea0003800000 */
/*0970*/ USHF.L.U32 UR4, UR4, 0x2, URZ ; /* 0x0000000204047899 */
/* 0x000fe2000800063f */
/*0980*/ ISETP.NE.AND P0, PT, R2, 0x1, PT ; /* 0x000000010200780c */
/* 0x000fd00003f05270 */
/*0990*/ LDS.128 R4, [UR4] ; /* 0x00000004ff047984 */
/* 0x000e240008000c00 */
/*09a0*/ IMAD.IADD R21, R21, 0x1, R4 ; /* 0x0000000115157824 */
/* 0x001fc600078e0204 */
/*09b0*/ @!P0 BRA 0x9f0 ; /* 0x0000003000008947 */
/* 0x000fea0003800000 */
/*09c0*/ ISETP.NE.AND P0, PT, R2, 0x2, PT ; /* 0x000000020200780c */
/* 0x000fe20003f05270 */
/*09d0*/ IMAD.IADD R21, R21, 0x1, R5 ; /* 0x0000000115157824 */
/* 0x000fd800078e0205 */
/*09e0*/ @P0 IMAD.IADD R21, R21, 0x1, R6 ; /* 0x0000000115150824 */
/* 0x000fca00078e0206 */
/*09f0*/ RED.E.ADD.STRONG.GPU [R8.64], R21 ; /* 0x000000150800798e */
/* 0x0001e4000c10e186 */
/*0a00*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x001fea0003800000 */
/*0a10*/ @!P2 BRA 0x580 ; /* 0xfffffb600000a947 */
/* 0x000fea000383ffff */
/*0a20*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0a30*/ BRA 0xa30; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0a40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0aa0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ab0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ac0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ad0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ae0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0af0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z16simple_reductionPiS_ii
.globl _Z16simple_reductionPiS_ii
.p2align 8
.type _Z16simple_reductionPiS_ii,@function
_Z16simple_reductionPiS_ii:
s_load_b32 s2, s[0:1], 0x14
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s2, 1
s_cbranch_scc1 .LBB0_11
s_clause 0x2
s_load_b32 s3, s[0:1], 0x24
s_load_b32 s8, s[0:1], 0x10
s_load_b128 s[4:7], s[0:1], 0x0
v_lshlrev_b32_e32 v2, 2, v0
s_waitcnt lgkmcnt(0)
s_and_b32 s1, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s15, s15, s1
v_add_nc_u32_e32 v3, s15, v0
s_add_i32 s0, s1, s15
s_sub_i32 s3, s8, s15
s_add_i32 s0, s0, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lt_i32 s0, s8
v_ashrrev_i32_e32 v4, 31, v3
v_cmp_eq_u32_e64 s0, 0, v0
s_cselect_b32 s3, s1, s3
v_cmp_gt_i32_e64 s1, s8, v3
s_cmp_gt_i32 s3, 0
v_lshlrev_b64 v[0:1], 2, v[3:4]
v_mov_b32_e32 v3, 0
s_cselect_b32 s8, -1, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v0, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
s_mov_b32 s6, 0
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_3
.p2align 6
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s7
s_add_i32 s6, s6, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lg_u32 s6, s2
s_cbranch_scc0 .LBB0_11
.LBB0_3:
s_and_saveexec_b32 s7, s1
s_cbranch_execz .LBB0_5
global_load_b32 v4, v[0:1], off
s_waitcnt vmcnt(0)
ds_store_b32 v2, v4
.LBB0_5:
s_or_b32 exec_lo, exec_lo, s7
s_and_saveexec_b32 s7, s0
s_cbranch_execz .LBB0_2
v_mov_b32_e32 v4, 0
s_and_not1_b32 vcc_lo, exec_lo, s8
s_cbranch_vccnz .LBB0_9
s_mov_b32 s9, 0
s_mov_b32 s10, s3
.LBB0_8:
v_mov_b32_e32 v5, s9
s_add_i32 s10, s10, -1
s_add_i32 s9, s9, 4
s_cmp_lg_u32 s10, 0
ds_load_b32 v5, v5
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v4, v5, v4
s_cbranch_scc1 .LBB0_8
.LBB0_9:
s_mov_b32 s9, exec_lo
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mbcnt_lo_u32_b32 v5, s9, 0
v_cmp_eq_u32_e32 vcc_lo, 0, v5
s_and_b32 s10, exec_lo, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 exec_lo, s10
s_cbranch_execz .LBB0_2
s_bcnt1_i32_b32 s9, s9
s_delay_alu instid0(SALU_CYCLE_1)
v_mul_lo_u32 v4, v4, s9
global_atomic_add_u32 v3, v4, s[4:5]
s_branch .LBB0_2
.LBB0_11:
s_set_inst_prefetch_distance 0x2
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z16simple_reductionPiS_ii
.amdhsa_group_segment_fixed_size 1024
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z16simple_reductionPiS_ii, .Lfunc_end0-_Z16simple_reductionPiS_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 1024
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z16simple_reductionPiS_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z16simple_reductionPiS_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0007b913_00000000-6_simple_reduction.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z40__device_stub__Z16simple_reductionPiS_iiPiS_ii
.type _Z40__device_stub__Z16simple_reductionPiS_iiPiS_ii, @function
_Z40__device_stub__Z16simple_reductionPiS_iiPiS_ii:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z16simple_reductionPiS_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z40__device_stub__Z16simple_reductionPiS_iiPiS_ii, .-_Z40__device_stub__Z16simple_reductionPiS_iiPiS_ii
.globl _Z16simple_reductionPiS_ii
.type _Z16simple_reductionPiS_ii, @function
_Z16simple_reductionPiS_ii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z40__device_stub__Z16simple_reductionPiS_iiPiS_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z16simple_reductionPiS_ii, .-_Z16simple_reductionPiS_ii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z16simple_reductionPiS_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z16simple_reductionPiS_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "simple_reduction.hip"
.globl _Z31__device_stub__simple_reductionPiS_ii # -- Begin function _Z31__device_stub__simple_reductionPiS_ii
.p2align 4, 0x90
.type _Z31__device_stub__simple_reductionPiS_ii,@function
_Z31__device_stub__simple_reductionPiS_ii: # @_Z31__device_stub__simple_reductionPiS_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z16simple_reductionPiS_ii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z31__device_stub__simple_reductionPiS_ii, .Lfunc_end0-_Z31__device_stub__simple_reductionPiS_ii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z16simple_reductionPiS_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z16simple_reductionPiS_ii,@object # @_Z16simple_reductionPiS_ii
.section .rodata,"a",@progbits
.globl _Z16simple_reductionPiS_ii
.p2align 3, 0x0
_Z16simple_reductionPiS_ii:
.quad _Z31__device_stub__simple_reductionPiS_ii
.size _Z16simple_reductionPiS_ii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z16simple_reductionPiS_ii"
.size .L__unnamed_1, 27
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z31__device_stub__simple_reductionPiS_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z16simple_reductionPiS_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <cmath>
#include <iostream>
#include <vector>
template<typename T>
class DevicePtr
{
T *ptr = nullptr;
__device__ __host__ __inline__ DevicePtr(T *ptr) : ptr(ptr) { }
public:
static DevicePtr<T> fromRaw(T *ptr)
{
return { ptr };
}
__device__ __inline__ T* operator->() const
{
return ptr;
}
__device__ __inline__ T& operator*() const
{
return *ptr;
}
__device__ __host__ __inline__ operator T*() const
{
return ptr;
}
};
template<typename T>
__global__ void vecAdd(
DevicePtr<T> a, DevicePtr<T> b, DevicePtr<T> c,
size_t n)
{
const size_t idx = blockIdx.x * blockDim.x + threadIdx.x;
if (idx < n) {
c[idx] = a[idx] + b[idx];
}
}
int main()
{
const size_t n = 1000;
const size_t bytes = n * sizeof(double);
std::vector<double> h_a(n);
std::vector<double> h_b(n);
for (double i = 0; i < n; i++) {
h_a[i] = sin(i) * sin(i);
h_b[i] = cos(i) * cos(i);
}
double *d_a, *d_b, *d_c;
cudaMalloc(&d_a, bytes);
cudaMalloc(&d_b, bytes);
cudaMalloc(&d_c, bytes);
cudaMemcpy(d_a, h_a.data(), bytes, cudaMemcpyHostToDevice);
cudaMemcpy(d_b, h_b.data(), bytes, cudaMemcpyHostToDevice);
const size_t blockDim = 1024;
const size_t gridDim = static_cast<size_t>(
ceil(static_cast<float>(n) / blockDim));
vecAdd<double><<<gridDim, blockDim>>>(
DevicePtr<double>::fromRaw(d_a),
DevicePtr<double>::fromRaw(d_b),
DevicePtr<double>::fromRaw(d_c),
n);
std::vector<double> h_c(n);
cudaMemcpy(h_c.data(), d_c, bytes, cudaMemcpyDeviceToHost);
double sum = 0;
for (double i = 0; i < n; i++) {
sum += h_c[i];
}
std::cout << "final result: " << sum << std::endl;
cudaFree(d_a);
cudaFree(d_b);
cudaFree(d_c);
return 0;
} | code for sm_80
Function : _Z6vecAddIdEv9DevicePtrIT_ES2_S2_m
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x178], PT ; /* 0x00005e0000007a0c */
/* 0x000fc80003f06070 */
/*0050*/ ISETP.GE.U32.AND.EX P0, PT, RZ, c[0x0][0x17c], PT, P0 ; /* 0x00005f00ff007a0c */
/* 0x000fda0003f06100 */
/*0060*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0070*/ IMAD.SHL.U32 R8, R0, 0x8, RZ ; /* 0x0000000800087824 */
/* 0x000fe200078e00ff */
/*0080*/ SHF.R.U32.HI R0, RZ, 0x1d, R0 ; /* 0x0000001dff007819 */
/* 0x000fe20000011600 */
/*0090*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*00a0*/ IADD3 R4, P0, R8.reuse, c[0x0][0x160], RZ ; /* 0x0000580008047a10 */
/* 0x040fe40007f1e0ff */
/*00b0*/ IADD3 R6, P1, R8, c[0x0][0x168], RZ ; /* 0x00005a0008067a10 */
/* 0x000fe40007f3e0ff */
/*00c0*/ IADD3.X R5, R0.reuse, c[0x0][0x164], RZ, P0, !PT ; /* 0x0000590000057a10 */
/* 0x040fe400007fe4ff */
/*00d0*/ IADD3.X R7, R0, c[0x0][0x16c], RZ, P1, !PT ; /* 0x00005b0000077a10 */
/* 0x000fc80000ffe4ff */
/*00e0*/ LDG.E.64 R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1b00 */
/*00f0*/ LDG.E.64 R2, [R6.64] ; /* 0x0000000406027981 */
/* 0x000ea2000c1e1b00 */
/*0100*/ IADD3 R8, P0, R8, c[0x0][0x170], RZ ; /* 0x00005c0008087a10 */
/* 0x000fc80007f1e0ff */
/*0110*/ IADD3.X R9, R0, c[0x0][0x174], RZ, P0, !PT ; /* 0x00005d0000097a10 */
/* 0x000fe200007fe4ff */
/*0120*/ DADD R2, R2, R4 ; /* 0x0000000002027229 */
/* 0x004e0e0000000004 */
/*0130*/ STG.E.64 [R8.64], R2 ; /* 0x0000000208007986 */
/* 0x001fe2000c101b04 */
/*0140*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0150*/ BRA 0x150; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <cmath>
#include <iostream>
#include <vector>
template<typename T>
class DevicePtr
{
T *ptr = nullptr;
__device__ __host__ __inline__ DevicePtr(T *ptr) : ptr(ptr) { }
public:
static DevicePtr<T> fromRaw(T *ptr)
{
return { ptr };
}
__device__ __inline__ T* operator->() const
{
return ptr;
}
__device__ __inline__ T& operator*() const
{
return *ptr;
}
__device__ __host__ __inline__ operator T*() const
{
return ptr;
}
};
template<typename T>
__global__ void vecAdd(
DevicePtr<T> a, DevicePtr<T> b, DevicePtr<T> c,
size_t n)
{
const size_t idx = blockIdx.x * blockDim.x + threadIdx.x;
if (idx < n) {
c[idx] = a[idx] + b[idx];
}
}
int main()
{
const size_t n = 1000;
const size_t bytes = n * sizeof(double);
std::vector<double> h_a(n);
std::vector<double> h_b(n);
for (double i = 0; i < n; i++) {
h_a[i] = sin(i) * sin(i);
h_b[i] = cos(i) * cos(i);
}
double *d_a, *d_b, *d_c;
cudaMalloc(&d_a, bytes);
cudaMalloc(&d_b, bytes);
cudaMalloc(&d_c, bytes);
cudaMemcpy(d_a, h_a.data(), bytes, cudaMemcpyHostToDevice);
cudaMemcpy(d_b, h_b.data(), bytes, cudaMemcpyHostToDevice);
const size_t blockDim = 1024;
const size_t gridDim = static_cast<size_t>(
ceil(static_cast<float>(n) / blockDim));
vecAdd<double><<<gridDim, blockDim>>>(
DevicePtr<double>::fromRaw(d_a),
DevicePtr<double>::fromRaw(d_b),
DevicePtr<double>::fromRaw(d_c),
n);
std::vector<double> h_c(n);
cudaMemcpy(h_c.data(), d_c, bytes, cudaMemcpyDeviceToHost);
double sum = 0;
for (double i = 0; i < n; i++) {
sum += h_c[i];
}
std::cout << "final result: " << sum << std::endl;
cudaFree(d_a);
cudaFree(d_b);
cudaFree(d_c);
return 0;
} | .file "tmpxft_0014f190_00000000-6_03-templates-device-ptr.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.section .text._Z6vecAddIdEv9DevicePtrIT_ES2_S2_m,"axG",@progbits,_Z6vecAddIdEv9DevicePtrIT_ES2_S2_m,comdat
.weak _Z6vecAddIdEv9DevicePtrIT_ES2_S2_m
.type _Z6vecAddIdEv9DevicePtrIT_ES2_S2_m, @function
_Z6vecAddIdEv9DevicePtrIT_ES2_S2_m:
.LFB4383:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
movq %rcx, 40(%rsp)
leaq 24(%rsp), %rax
movq %rax, 112(%rsp)
leaq 16(%rsp), %rax
movq %rax, 120(%rsp)
leaq 8(%rsp), %rax
movq %rax, 128(%rsp)
leaq 40(%rsp), %rax
movq %rax, 136(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L5
.L1:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L6
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L5:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 184
pushq 56(%rsp)
.cfi_def_cfa_offset 192
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z6vecAddIdEv9DevicePtrIT_ES2_S2_m(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L1
.L6:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4383:
.size _Z6vecAddIdEv9DevicePtrIT_ES2_S2_m, .-_Z6vecAddIdEv9DevicePtrIT_ES2_S2_m
.text
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB4042:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4042:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z6vecAddIdEv9DevicePtrIT_ES2_S2_m"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB4067:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z6vecAddIdEv9DevicePtrIT_ES2_S2_m(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4067:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .rodata._ZNSt6vectorIdSaIdEEC2EmRKS0_.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "cannot create std::vector larger than max_size()"
.section .text._ZNSt6vectorIdSaIdEEC2EmRKS0_,"axG",@progbits,_ZNSt6vectorIdSaIdEEC5EmRKS0_,comdat
.align 2
.weak _ZNSt6vectorIdSaIdEEC2EmRKS0_
.type _ZNSt6vectorIdSaIdEEC2EmRKS0_, @function
_ZNSt6vectorIdSaIdEEC2EmRKS0_:
.LFB4374:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
movq %rsi, %rax
shrq $60, %rax
jne .L21
movq %rdi, %rbx
movq %rsi, %rbp
movq $0, (%rdi)
movq $0, 8(%rdi)
movq $0, 16(%rdi)
testq %rsi, %rsi
je .L13
leaq 0(,%rsi,8), %r12
movq %r12, %rdi
call _Znwm@PLT
movq %rax, (%rbx)
movq %rax, 8(%rbx)
leaq (%rax,%r12), %rdx
movq %rdx, 16(%rbx)
movq $0x000000000, (%rax)
addq $8, %rax
cmpq $1, %rbp
je .L16
cmpq %rax, %rdx
je .L17
.L15:
movq $0x000000000, (%rax)
addq $8, %rax
cmpq %rax, %rdx
jne .L15
jmp .L14
.L21:
leaq .LC1(%rip), %rdi
call _ZSt20__throw_length_errorPKc@PLT
.L16:
movq %rax, %rdx
jmp .L14
.L17:
movq %rax, %rdx
jmp .L14
.L13:
movq $0, (%rdi)
movq $0, 16(%rdi)
movl $0, %edx
.L14:
movq %rdx, 8(%rbx)
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4374:
.size _ZNSt6vectorIdSaIdEEC2EmRKS0_, .-_ZNSt6vectorIdSaIdEEC2EmRKS0_
.weak _ZNSt6vectorIdSaIdEEC1EmRKS0_
.set _ZNSt6vectorIdSaIdEEC1EmRKS0_,_ZNSt6vectorIdSaIdEEC2EmRKS0_
.section .text._ZNSt6vectorIdSaIdEED2Ev,"axG",@progbits,_ZNSt6vectorIdSaIdEED5Ev,comdat
.align 2
.weak _ZNSt6vectorIdSaIdEED2Ev
.type _ZNSt6vectorIdSaIdEED2Ev, @function
_ZNSt6vectorIdSaIdEED2Ev:
.LFB4377:
.cfi_startproc
endbr64
movq (%rdi), %rax
testq %rax, %rax
je .L25
subq $8, %rsp
.cfi_def_cfa_offset 16
movq 16(%rdi), %rsi
subq %rax, %rsi
movq %rax, %rdi
call _ZdlPvm@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.L25:
ret
.cfi_endproc
.LFE4377:
.size _ZNSt6vectorIdSaIdEED2Ev, .-_ZNSt6vectorIdSaIdEED2Ev
.weak _ZNSt6vectorIdSaIdEED1Ev
.set _ZNSt6vectorIdSaIdEED1Ev,_ZNSt6vectorIdSaIdEED2Ev
.section .rodata.str1.1,"aMS",@progbits,1
.LC5:
.string "final result: "
.text
.globl main
.type main, @function
main:
.LFB4039:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA4039
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $184, %rsp
.cfi_def_cfa_offset 224
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 144(%rsp), %rbx
leaq 80(%rsp), %rdi
movq %rbx, %rdx
movl $1000, %esi
.LEHB0:
call _ZNSt6vectorIdSaIdEEC1EmRKS0_
.LEHE0:
leaq 112(%rsp), %rdi
movq %rbx, %rdx
movl $1000, %esi
.LEHB1:
call _ZNSt6vectorIdSaIdEEC1EmRKS0_
.LEHE1:
movq 80(%rsp), %r12
movq 112(%rsp), %rbp
movl $1000, %ebx
movq $0x000000000, 8(%rsp)
movabsq $-9223372036854775808, %r13
jmp .L31
.L29:
movsd 8(%rsp), %xmm2
subsd .LC3(%rip), %xmm2
cvttsd2siq %xmm2, %rax
xorq %r13, %rax
.L30:
mulsd %xmm1, %xmm1
movsd %xmm1, (%r12,%rax,8)
mulsd %xmm0, %xmm0
movsd %xmm0, 0(%rbp,%rax,8)
movsd .LC4(%rip), %xmm6
addsd 8(%rsp), %xmm6
movsd %xmm6, 8(%rsp)
subl $1, %ebx
je .L48
.L31:
leaq 24(%rsp), %rdi
leaq 16(%rsp), %rsi
movsd 8(%rsp), %xmm0
call sincos@PLT
movsd 16(%rsp), %xmm0
movsd 24(%rsp), %xmm1
movsd 8(%rsp), %xmm5
comisd .LC3(%rip), %xmm5
jnb .L29
cvttsd2siq %xmm5, %rax
jmp .L30
.L48:
leaq 40(%rsp), %rdi
movl $8000, %esi
.LEHB2:
call cudaMalloc@PLT
leaq 48(%rsp), %rdi
movl $8000, %esi
call cudaMalloc@PLT
leaq 56(%rsp), %rdi
movl $8000, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $8000, %edx
movq %r12, %rsi
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $8000, %edx
movq %rbp, %rsi
movq 48(%rsp), %rdi
call cudaMemcpy@PLT
movl $1024, 144(%rsp)
movl $1, 148(%rsp)
movl $1, 152(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 144(%rsp), %rdx
movl $1, %ecx
movq 68(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L32
movl $1000, %ecx
movq 56(%rsp), %rdx
movq 48(%rsp), %rsi
movq 40(%rsp), %rdi
call _Z6vecAddIdEv9DevicePtrIT_ES2_S2_m
.L32:
leaq 68(%rsp), %rdx
leaq 144(%rsp), %rdi
movl $1000, %esi
call _ZNSt6vectorIdSaIdEEC1EmRKS0_
.LEHE2:
movq 144(%rsp), %rbp
movl $2, %ecx
movl $8000, %edx
movq 56(%rsp), %rsi
movq %rbp, %rdi
.LEHB3:
call cudaMemcpy@PLT
movl $1000, %eax
pxor %xmm0, %xmm0
movq %xmm0, %rbx
movsd .LC3(%rip), %xmm2
movapd %xmm2, %xmm4
movabsq $-9223372036854775808, %rcx
movsd .LC4(%rip), %xmm1
jmp .L35
.L33:
movapd %xmm0, %xmm3
subsd %xmm4, %xmm3
cvttsd2siq %xmm3, %rdx
xorq %rcx, %rdx
.L34:
movq %rbx, %xmm7
addsd 0(%rbp,%rdx,8), %xmm7
movq %xmm7, %rbx
addsd %xmm1, %xmm0
subl $1, %eax
je .L49
.L35:
comisd %xmm2, %xmm0
jnb .L33
cvttsd2siq %xmm0, %rdx
jmp .L34
.L49:
leaq .LC5(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq %rbx, %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq 48(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rdi
call cudaFree@PLT
.LEHE3:
leaq 144(%rsp), %rdi
call _ZNSt6vectorIdSaIdEED1Ev
leaq 112(%rsp), %rdi
call _ZNSt6vectorIdSaIdEED1Ev
leaq 80(%rsp), %rdi
call _ZNSt6vectorIdSaIdEED1Ev
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L50
movl $0, %eax
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L43:
.cfi_restore_state
endbr64
movq %rax, %rbx
leaq 144(%rsp), %rdi
call _ZNSt6vectorIdSaIdEED1Ev
.L37:
leaq 112(%rsp), %rdi
call _ZNSt6vectorIdSaIdEED1Ev
.L38:
leaq 80(%rsp), %rdi
call _ZNSt6vectorIdSaIdEED1Ev
movq 168(%rsp), %rax
subq %fs:40, %rax
je .L39
call __stack_chk_fail@PLT
.L42:
endbr64
movq %rax, %rbx
jmp .L37
.L41:
endbr64
movq %rax, %rbx
jmp .L38
.L39:
movq %rbx, %rdi
.LEHB4:
call _Unwind_Resume@PLT
.LEHE4:
.L50:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4039:
.globl __gxx_personality_v0
.section .gcc_except_table,"a",@progbits
.LLSDA4039:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE4039-.LLSDACSB4039
.LLSDACSB4039:
.uleb128 .LEHB0-.LFB4039
.uleb128 .LEHE0-.LEHB0
.uleb128 0
.uleb128 0
.uleb128 .LEHB1-.LFB4039
.uleb128 .LEHE1-.LEHB1
.uleb128 .L41-.LFB4039
.uleb128 0
.uleb128 .LEHB2-.LFB4039
.uleb128 .LEHE2-.LEHB2
.uleb128 .L42-.LFB4039
.uleb128 0
.uleb128 .LEHB3-.LFB4039
.uleb128 .LEHE3-.LEHB3
.uleb128 .L43-.LFB4039
.uleb128 0
.uleb128 .LEHB4-.LFB4039
.uleb128 .LEHE4-.LEHB4
.uleb128 0
.uleb128 0
.LLSDACSE4039:
.text
.size main, .-main
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC3:
.long 0
.long 1138753536
.align 8
.LC4:
.long 0
.long 1072693248
.hidden DW.ref.__gxx_personality_v0
.weak DW.ref.__gxx_personality_v0
.section .data.rel.local.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat
.align 8
.type DW.ref.__gxx_personality_v0, @object
.size DW.ref.__gxx_personality_v0, 8
DW.ref.__gxx_personality_v0:
.quad __gxx_personality_v0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <cmath>
#include <iostream>
#include <vector>
template<typename T>
class DevicePtr
{
T *ptr = nullptr;
__device__ __host__ __inline__ DevicePtr(T *ptr) : ptr(ptr) { }
public:
static DevicePtr<T> fromRaw(T *ptr)
{
return { ptr };
}
__device__ __inline__ T* operator->() const
{
return ptr;
}
__device__ __inline__ T& operator*() const
{
return *ptr;
}
__device__ __host__ __inline__ operator T*() const
{
return ptr;
}
};
template<typename T>
__global__ void vecAdd(
DevicePtr<T> a, DevicePtr<T> b, DevicePtr<T> c,
size_t n)
{
const size_t idx = blockIdx.x * blockDim.x + threadIdx.x;
if (idx < n) {
c[idx] = a[idx] + b[idx];
}
}
int main()
{
const size_t n = 1000;
const size_t bytes = n * sizeof(double);
std::vector<double> h_a(n);
std::vector<double> h_b(n);
for (double i = 0; i < n; i++) {
h_a[i] = sin(i) * sin(i);
h_b[i] = cos(i) * cos(i);
}
double *d_a, *d_b, *d_c;
cudaMalloc(&d_a, bytes);
cudaMalloc(&d_b, bytes);
cudaMalloc(&d_c, bytes);
cudaMemcpy(d_a, h_a.data(), bytes, cudaMemcpyHostToDevice);
cudaMemcpy(d_b, h_b.data(), bytes, cudaMemcpyHostToDevice);
const size_t blockDim = 1024;
const size_t gridDim = static_cast<size_t>(
ceil(static_cast<float>(n) / blockDim));
vecAdd<double><<<gridDim, blockDim>>>(
DevicePtr<double>::fromRaw(d_a),
DevicePtr<double>::fromRaw(d_b),
DevicePtr<double>::fromRaw(d_c),
n);
std::vector<double> h_c(n);
cudaMemcpy(h_c.data(), d_c, bytes, cudaMemcpyDeviceToHost);
double sum = 0;
for (double i = 0; i < n; i++) {
sum += h_c[i];
}
std::cout << "final result: " << sum << std::endl;
cudaFree(d_a);
cudaFree(d_b);
cudaFree(d_c);
return 0;
} | #include <hip/hip_runtime.h>
#include <cmath>
#include <iostream>
#include <vector>
template<typename T>
class DevicePtr
{
T *ptr = nullptr;
__device__ __host__ __inline__ DevicePtr(T *ptr) : ptr(ptr) { }
public:
static DevicePtr<T> fromRaw(T *ptr)
{
return { ptr };
}
__device__ __inline__ T* operator->() const
{
return ptr;
}
__device__ __inline__ T& operator*() const
{
return *ptr;
}
__device__ __host__ __inline__ operator T*() const
{
return ptr;
}
};
template<typename T>
__global__ void vecAdd(
DevicePtr<T> a, DevicePtr<T> b, DevicePtr<T> c,
size_t n)
{
const size_t idx = blockIdx.x * blockDim.x + threadIdx.x;
if (idx < n) {
c[idx] = a[idx] + b[idx];
}
}
int main()
{
const size_t n = 1000;
const size_t bytes = n * sizeof(double);
std::vector<double> h_a(n);
std::vector<double> h_b(n);
for (double i = 0; i < n; i++) {
h_a[i] = sin(i) * sin(i);
h_b[i] = cos(i) * cos(i);
}
double *d_a, *d_b, *d_c;
hipMalloc(&d_a, bytes);
hipMalloc(&d_b, bytes);
hipMalloc(&d_c, bytes);
hipMemcpy(d_a, h_a.data(), bytes, hipMemcpyHostToDevice);
hipMemcpy(d_b, h_b.data(), bytes, hipMemcpyHostToDevice);
const size_t blockDim = 1024;
const size_t gridDim = static_cast<size_t>(
ceil(static_cast<float>(n) / blockDim));
vecAdd<double><<<gridDim, blockDim>>>(
DevicePtr<double>::fromRaw(d_a),
DevicePtr<double>::fromRaw(d_b),
DevicePtr<double>::fromRaw(d_c),
n);
std::vector<double> h_c(n);
hipMemcpy(h_c.data(), d_c, bytes, hipMemcpyDeviceToHost);
double sum = 0;
for (double i = 0; i < n; i++) {
sum += h_c[i];
}
std::cout << "final result: " << sum << std::endl;
hipFree(d_a);
hipFree(d_b);
hipFree(d_c);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <cmath>
#include <iostream>
#include <vector>
template<typename T>
class DevicePtr
{
T *ptr = nullptr;
__device__ __host__ __inline__ DevicePtr(T *ptr) : ptr(ptr) { }
public:
static DevicePtr<T> fromRaw(T *ptr)
{
return { ptr };
}
__device__ __inline__ T* operator->() const
{
return ptr;
}
__device__ __inline__ T& operator*() const
{
return *ptr;
}
__device__ __host__ __inline__ operator T*() const
{
return ptr;
}
};
template<typename T>
__global__ void vecAdd(
DevicePtr<T> a, DevicePtr<T> b, DevicePtr<T> c,
size_t n)
{
const size_t idx = blockIdx.x * blockDim.x + threadIdx.x;
if (idx < n) {
c[idx] = a[idx] + b[idx];
}
}
int main()
{
const size_t n = 1000;
const size_t bytes = n * sizeof(double);
std::vector<double> h_a(n);
std::vector<double> h_b(n);
for (double i = 0; i < n; i++) {
h_a[i] = sin(i) * sin(i);
h_b[i] = cos(i) * cos(i);
}
double *d_a, *d_b, *d_c;
hipMalloc(&d_a, bytes);
hipMalloc(&d_b, bytes);
hipMalloc(&d_c, bytes);
hipMemcpy(d_a, h_a.data(), bytes, hipMemcpyHostToDevice);
hipMemcpy(d_b, h_b.data(), bytes, hipMemcpyHostToDevice);
const size_t blockDim = 1024;
const size_t gridDim = static_cast<size_t>(
ceil(static_cast<float>(n) / blockDim));
vecAdd<double><<<gridDim, blockDim>>>(
DevicePtr<double>::fromRaw(d_a),
DevicePtr<double>::fromRaw(d_b),
DevicePtr<double>::fromRaw(d_c),
n);
std::vector<double> h_c(n);
hipMemcpy(h_c.data(), d_c, bytes, hipMemcpyDeviceToHost);
double sum = 0;
for (double i = 0; i < n; i++) {
sum += h_c[i];
}
std::cout << "final result: " << sum << std::endl;
hipFree(d_a);
hipFree(d_b);
hipFree(d_c);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.section .text._Z6vecAddIdEv9DevicePtrIT_ES2_S2_m,"axG",@progbits,_Z6vecAddIdEv9DevicePtrIT_ES2_S2_m,comdat
.protected _Z6vecAddIdEv9DevicePtrIT_ES2_S2_m
.globl _Z6vecAddIdEv9DevicePtrIT_ES2_S2_m
.p2align 8
.type _Z6vecAddIdEv9DevicePtrIT_ES2_S2_m,@function
_Z6vecAddIdEv9DevicePtrIT_ES2_S2_m:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x2c
s_load_b64 s[2:3], s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
v_mov_b32_e32 v2, 0
v_cmp_gt_u64_e32 vcc_lo, s[2:3], v[1:2]
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_lshlrev_b64 v[0:1], 3, v[1:2]
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b64 v[2:3], v[2:3], off
global_load_b64 v[4:5], v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_f64 v[2:3], v[2:3], v[4:5]
global_store_b64 v[0:1], v[2:3], off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6vecAddIdEv9DevicePtrIT_ES2_S2_m
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.section .text._Z6vecAddIdEv9DevicePtrIT_ES2_S2_m,"axG",@progbits,_Z6vecAddIdEv9DevicePtrIT_ES2_S2_m,comdat
.Lfunc_end0:
.size _Z6vecAddIdEv9DevicePtrIT_ES2_S2_m, .Lfunc_end0-_Z6vecAddIdEv9DevicePtrIT_ES2_S2_m
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 8
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6vecAddIdEv9DevicePtrIT_ES2_S2_m
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6vecAddIdEv9DevicePtrIT_ES2_S2_m.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <cmath>
#include <iostream>
#include <vector>
template<typename T>
class DevicePtr
{
T *ptr = nullptr;
__device__ __host__ __inline__ DevicePtr(T *ptr) : ptr(ptr) { }
public:
static DevicePtr<T> fromRaw(T *ptr)
{
return { ptr };
}
__device__ __inline__ T* operator->() const
{
return ptr;
}
__device__ __inline__ T& operator*() const
{
return *ptr;
}
__device__ __host__ __inline__ operator T*() const
{
return ptr;
}
};
template<typename T>
__global__ void vecAdd(
DevicePtr<T> a, DevicePtr<T> b, DevicePtr<T> c,
size_t n)
{
const size_t idx = blockIdx.x * blockDim.x + threadIdx.x;
if (idx < n) {
c[idx] = a[idx] + b[idx];
}
}
int main()
{
const size_t n = 1000;
const size_t bytes = n * sizeof(double);
std::vector<double> h_a(n);
std::vector<double> h_b(n);
for (double i = 0; i < n; i++) {
h_a[i] = sin(i) * sin(i);
h_b[i] = cos(i) * cos(i);
}
double *d_a, *d_b, *d_c;
hipMalloc(&d_a, bytes);
hipMalloc(&d_b, bytes);
hipMalloc(&d_c, bytes);
hipMemcpy(d_a, h_a.data(), bytes, hipMemcpyHostToDevice);
hipMemcpy(d_b, h_b.data(), bytes, hipMemcpyHostToDevice);
const size_t blockDim = 1024;
const size_t gridDim = static_cast<size_t>(
ceil(static_cast<float>(n) / blockDim));
vecAdd<double><<<gridDim, blockDim>>>(
DevicePtr<double>::fromRaw(d_a),
DevicePtr<double>::fromRaw(d_b),
DevicePtr<double>::fromRaw(d_c),
n);
std::vector<double> h_c(n);
hipMemcpy(h_c.data(), d_c, bytes, hipMemcpyDeviceToHost);
double sum = 0;
for (double i = 0; i < n; i++) {
sum += h_c[i];
}
std::cout << "final result: " << sum << std::endl;
hipFree(d_a);
hipFree(d_b);
hipFree(d_c);
return 0;
} | .text
.file "03-templates-device-ptr.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.Lfunc_begin0:
.cfi_startproc
.cfi_personality 3, __gxx_personality_v0
.cfi_lsda 3, .Lexception0
# %bb.0: # %_ZNSt6vectorIdSaIdEEC2EmRKS0_.exit
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $160, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
.cfi_escape 0x2e, 0x00
movl $8000, %edi # imm = 0x1F40
callq _Znwm
movq %rax, %rbx
.cfi_escape 0x2e, 0x00
movl $8000, %edx # imm = 0x1F40
movq %rax, %rdi
xorl %esi, %esi
callq memset@PLT
.Ltmp0:
.cfi_escape 0x2e, 0x00
movl $8000, %edi # imm = 0x1F40
callq _Znwm
.Ltmp1:
# %bb.1: # %_ZNSt6vectorIdSaIdEEC2EmRKS0_.exit36
movq %rax, %r14
.cfi_escape 0x2e, 0x00
xorl %r15d, %r15d
movl $8000, %edx # imm = 0x1F40
movq %rax, %rdi
xorl %esi, %esi
callq memset@PLT
.p2align 4, 0x90
.LBB0_2: # =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtsi2sd %r15d, %xmm0
movsd %xmm0, 8(%rsp) # 8-byte Spill
.cfi_escape 0x2e, 0x00
callq sin
movsd %xmm0, 16(%rsp) # 8-byte Spill
.cfi_escape 0x2e, 0x00
movsd 8(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
callq sin
mulsd 16(%rsp), %xmm0 # 8-byte Folded Reload
movsd %xmm0, (%rbx,%r15,8)
.cfi_escape 0x2e, 0x00
movsd 8(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
callq cos
movsd %xmm0, 16(%rsp) # 8-byte Spill
.cfi_escape 0x2e, 0x00
movsd 8(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
callq cos
mulsd 16(%rsp), %xmm0 # 8-byte Folded Reload
movsd %xmm0, (%r14,%r15,8)
incq %r15
cmpq $1000, %r15 # imm = 0x3E8
jne .LBB0_2
# %bb.3:
.Ltmp3:
.cfi_escape 0x2e, 0x00
leaq 40(%rsp), %rdi
movl $8000, %esi # imm = 0x1F40
callq hipMalloc
.Ltmp4:
# %bb.4: # %_ZL9hipMallocIdE10hipError_tPPT_m.exit
.Ltmp5:
.cfi_escape 0x2e, 0x00
leaq 32(%rsp), %rdi
movl $8000, %esi # imm = 0x1F40
callq hipMalloc
.Ltmp6:
# %bb.5: # %_ZL9hipMallocIdE10hipError_tPPT_m.exit37
.Ltmp7:
.cfi_escape 0x2e, 0x00
leaq 24(%rsp), %rdi
movl $8000, %esi # imm = 0x1F40
callq hipMalloc
.Ltmp8:
# %bb.6: # %_ZL9hipMallocIdE10hipError_tPPT_m.exit38
movq 40(%rsp), %rdi
.Ltmp9:
.cfi_escape 0x2e, 0x00
movl $8000, %edx # imm = 0x1F40
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
.Ltmp10:
# %bb.7:
movq 32(%rsp), %rdi
.Ltmp11:
.cfi_escape 0x2e, 0x00
movl $8000, %edx # imm = 0x1F40
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
.Ltmp12:
# %bb.8:
.Ltmp14:
.cfi_escape 0x2e, 0x00
movabsq $4294967297, %rdi # imm = 0x100000001
movabsq $4294968320, %rdx # imm = 0x100000400
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
.Ltmp15:
# %bb.9:
testl %eax, %eax
jne .LBB0_12
# %bb.10:
movq 40(%rsp), %rax
movq 32(%rsp), %rcx
movq 24(%rsp), %rdx
movq %rax, 120(%rsp)
movq %rcx, 112(%rsp)
movq %rdx, 104(%rsp)
movq $1000, 96(%rsp) # imm = 0x3E8
leaq 120(%rsp), %rax
movq %rax, 128(%rsp)
leaq 112(%rsp), %rax
movq %rax, 136(%rsp)
leaq 104(%rsp), %rax
movq %rax, 144(%rsp)
leaq 96(%rsp), %rax
movq %rax, 152(%rsp)
.Ltmp16:
.cfi_escape 0x2e, 0x00
leaq 80(%rsp), %rdi
leaq 64(%rsp), %rsi
leaq 56(%rsp), %rdx
leaq 48(%rsp), %rcx
callq __hipPopCallConfiguration
.Ltmp17:
# %bb.11: # %.noexc
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
movq 64(%rsp), %rcx
movl 72(%rsp), %r8d
.Ltmp18:
.cfi_escape 0x2e, 0x10
leaq 128(%rsp), %r9
movl $_Z6vecAddIdEv9DevicePtrIT_ES2_S2_m, %edi
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.Ltmp19:
.LBB0_12:
.Ltmp21:
.cfi_escape 0x2e, 0x00
movl $8000, %edi # imm = 0x1F40
callq _Znwm
.Ltmp22:
# %bb.13: # %_ZNSt6vectorIdSaIdEEC2EmRKS0_.exit41
movq %rax, %r15
.cfi_escape 0x2e, 0x00
movl $8000, %edx # imm = 0x1F40
movq %rax, %rdi
xorl %esi, %esi
callq memset@PLT
movq 24(%rsp), %rsi
.Ltmp24:
.cfi_escape 0x2e, 0x00
movl $8000, %edx # imm = 0x1F40
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
.Ltmp25:
# %bb.14: # %.preheader.preheader
xorpd %xmm0, %xmm0
xorl %eax, %eax
.p2align 4, 0x90
.LBB0_15: # %.preheader
# =>This Inner Loop Header: Depth=1
addsd (%r15,%rax,8), %xmm0
incq %rax
cmpq $1000, %rax # imm = 0x3E8
jne .LBB0_15
# %bb.16:
.Ltmp27:
movsd %xmm0, 8(%rsp) # 8-byte Spill
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $14, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp28:
# %bb.17: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit
.Ltmp29:
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
movsd 8(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
callq _ZNSo9_M_insertIdEERSoT_
.Ltmp30:
# %bb.18: # %_ZNSolsEd.exit
movq %rax, %r12
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%r12,%rax), %r13
testq %r13, %r13
je .LBB0_19
# %bb.25: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%r13)
je .LBB0_27
# %bb.26:
movzbl 67(%r13), %eax
jmp .LBB0_29
.LBB0_27:
.Ltmp31:
.cfi_escape 0x2e, 0x00
movq %r13, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
.Ltmp32:
# %bb.28: # %.noexc57
movq (%r13), %rax
.Ltmp33:
.cfi_escape 0x2e, 0x00
movq %r13, %rdi
movl $10, %esi
callq *48(%rax)
.Ltmp34:
.LBB0_29: # %_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc.exit.i
.Ltmp35:
.cfi_escape 0x2e, 0x00
movsbl %al, %esi
movq %r12, %rdi
callq _ZNSo3putEc
.Ltmp36:
# %bb.30: # %.noexc59
.Ltmp37:
.cfi_escape 0x2e, 0x00
movq %rax, %rdi
callq _ZNSo5flushEv
.Ltmp38:
# %bb.31: # %_ZNSolsEPFRSoS_E.exit
movq 40(%rsp), %rdi
.Ltmp39:
.cfi_escape 0x2e, 0x00
callq hipFree
.Ltmp40:
# %bb.32:
movq 32(%rsp), %rdi
.Ltmp41:
.cfi_escape 0x2e, 0x00
callq hipFree
.Ltmp42:
# %bb.33:
movq 24(%rsp), %rdi
.Ltmp43:
.cfi_escape 0x2e, 0x00
callq hipFree
.Ltmp44:
# %bb.34: # %_ZNSt6vectorIdSaIdEED2Ev.exit
.cfi_escape 0x2e, 0x00
movq %r15, %rdi
callq _ZdlPv
.cfi_escape 0x2e, 0x00
movq %r14, %rdi
callq _ZdlPv
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
callq _ZdlPv
xorl %eax, %eax
addq $160, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB0_19:
.cfi_def_cfa_offset 208
.Ltmp45:
.cfi_escape 0x2e, 0x00
callq _ZSt16__throw_bad_castv
.Ltmp46:
# %bb.24: # %.noexc56
.LBB0_23:
.Ltmp26:
jmp .LBB0_36
.LBB0_22:
.Ltmp23:
movq %rax, %r12
jmp .LBB0_37
.LBB0_39:
.Ltmp2:
movq %rax, %r12
jmp .LBB0_38
.LBB0_21:
.Ltmp20:
movq %rax, %r12
jmp .LBB0_37
.LBB0_20:
.Ltmp13:
movq %rax, %r12
jmp .LBB0_37
.LBB0_35:
.Ltmp47:
.LBB0_36: # %_ZNSt6vectorIdSaIdEED2Ev.exit50
movq %rax, %r12
.cfi_escape 0x2e, 0x00
movq %r15, %rdi
callq _ZdlPv
.LBB0_37: # %_ZNSt6vectorIdSaIdEED2Ev.exit52
.cfi_escape 0x2e, 0x00
movq %r14, %rdi
callq _ZdlPv
.LBB0_38: # %_ZNSt6vectorIdSaIdEED2Ev.exit54
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
callq _ZdlPv
.cfi_escape 0x2e, 0x00
movq %r12, %rdi
callq _Unwind_Resume@PLT
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
.section .gcc_except_table,"a",@progbits
.p2align 2, 0x0
GCC_except_table0:
.Lexception0:
.byte 255 # @LPStart Encoding = omit
.byte 255 # @TType Encoding = omit
.byte 1 # Call site Encoding = uleb128
.uleb128 .Lcst_end0-.Lcst_begin0
.Lcst_begin0:
.uleb128 .Lfunc_begin0-.Lfunc_begin0 # >> Call Site 1 <<
.uleb128 .Ltmp0-.Lfunc_begin0 # Call between .Lfunc_begin0 and .Ltmp0
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp0-.Lfunc_begin0 # >> Call Site 2 <<
.uleb128 .Ltmp1-.Ltmp0 # Call between .Ltmp0 and .Ltmp1
.uleb128 .Ltmp2-.Lfunc_begin0 # jumps to .Ltmp2
.byte 0 # On action: cleanup
.uleb128 .Ltmp1-.Lfunc_begin0 # >> Call Site 3 <<
.uleb128 .Ltmp3-.Ltmp1 # Call between .Ltmp1 and .Ltmp3
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp3-.Lfunc_begin0 # >> Call Site 4 <<
.uleb128 .Ltmp12-.Ltmp3 # Call between .Ltmp3 and .Ltmp12
.uleb128 .Ltmp13-.Lfunc_begin0 # jumps to .Ltmp13
.byte 0 # On action: cleanup
.uleb128 .Ltmp14-.Lfunc_begin0 # >> Call Site 5 <<
.uleb128 .Ltmp19-.Ltmp14 # Call between .Ltmp14 and .Ltmp19
.uleb128 .Ltmp20-.Lfunc_begin0 # jumps to .Ltmp20
.byte 0 # On action: cleanup
.uleb128 .Ltmp21-.Lfunc_begin0 # >> Call Site 6 <<
.uleb128 .Ltmp22-.Ltmp21 # Call between .Ltmp21 and .Ltmp22
.uleb128 .Ltmp23-.Lfunc_begin0 # jumps to .Ltmp23
.byte 0 # On action: cleanup
.uleb128 .Ltmp22-.Lfunc_begin0 # >> Call Site 7 <<
.uleb128 .Ltmp24-.Ltmp22 # Call between .Ltmp22 and .Ltmp24
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp24-.Lfunc_begin0 # >> Call Site 8 <<
.uleb128 .Ltmp25-.Ltmp24 # Call between .Ltmp24 and .Ltmp25
.uleb128 .Ltmp26-.Lfunc_begin0 # jumps to .Ltmp26
.byte 0 # On action: cleanup
.uleb128 .Ltmp27-.Lfunc_begin0 # >> Call Site 9 <<
.uleb128 .Ltmp46-.Ltmp27 # Call between .Ltmp27 and .Ltmp46
.uleb128 .Ltmp47-.Lfunc_begin0 # jumps to .Ltmp47
.byte 0 # On action: cleanup
.uleb128 .Ltmp46-.Lfunc_begin0 # >> Call Site 10 <<
.uleb128 .Lfunc_end0-.Ltmp46 # Call between .Ltmp46 and .Lfunc_end0
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.Lcst_end0:
.p2align 2, 0x0
# -- End function
.section .text._Z21__device_stub__vecAddIdEv9DevicePtrIT_ES2_S2_m,"axG",@progbits,_Z21__device_stub__vecAddIdEv9DevicePtrIT_ES2_S2_m,comdat
.weak _Z21__device_stub__vecAddIdEv9DevicePtrIT_ES2_S2_m # -- Begin function _Z21__device_stub__vecAddIdEv9DevicePtrIT_ES2_S2_m
.p2align 4, 0x90
.type _Z21__device_stub__vecAddIdEv9DevicePtrIT_ES2_S2_m,@function
_Z21__device_stub__vecAddIdEv9DevicePtrIT_ES2_S2_m: # @_Z21__device_stub__vecAddIdEv9DevicePtrIT_ES2_S2_m
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movq %rcx, 48(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rax
movq %rax, 104(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6vecAddIdEv9DevicePtrIT_ES2_S2_m, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end1:
.size _Z21__device_stub__vecAddIdEv9DevicePtrIT_ES2_S2_m, .Lfunc_end1-_Z21__device_stub__vecAddIdEv9DevicePtrIT_ES2_S2_m
.cfi_endproc
# -- End function
.text
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6vecAddIdEv9DevicePtrIT_ES2_S2_m, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6vecAddIdEv9DevicePtrIT_ES2_S2_m,@object # @_Z6vecAddIdEv9DevicePtrIT_ES2_S2_m
.section .rodata._Z6vecAddIdEv9DevicePtrIT_ES2_S2_m,"aG",@progbits,_Z6vecAddIdEv9DevicePtrIT_ES2_S2_m,comdat
.weak _Z6vecAddIdEv9DevicePtrIT_ES2_S2_m
.p2align 3, 0x0
_Z6vecAddIdEv9DevicePtrIT_ES2_S2_m:
.quad _Z21__device_stub__vecAddIdEv9DevicePtrIT_ES2_S2_m
.size _Z6vecAddIdEv9DevicePtrIT_ES2_S2_m, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "final result: "
.size .L.str, 15
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z6vecAddIdEv9DevicePtrIT_ES2_S2_m"
.size .L__unnamed_1, 35
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __gxx_personality_v0
.addrsig_sym _Z21__device_stub__vecAddIdEv9DevicePtrIT_ES2_S2_m
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Unwind_Resume
.addrsig_sym _Z6vecAddIdEv9DevicePtrIT_ES2_S2_m
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z6vecAddIdEv9DevicePtrIT_ES2_S2_m
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x178], PT ; /* 0x00005e0000007a0c */
/* 0x000fc80003f06070 */
/*0050*/ ISETP.GE.U32.AND.EX P0, PT, RZ, c[0x0][0x17c], PT, P0 ; /* 0x00005f00ff007a0c */
/* 0x000fda0003f06100 */
/*0060*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0070*/ IMAD.SHL.U32 R8, R0, 0x8, RZ ; /* 0x0000000800087824 */
/* 0x000fe200078e00ff */
/*0080*/ SHF.R.U32.HI R0, RZ, 0x1d, R0 ; /* 0x0000001dff007819 */
/* 0x000fe20000011600 */
/*0090*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*00a0*/ IADD3 R4, P0, R8.reuse, c[0x0][0x160], RZ ; /* 0x0000580008047a10 */
/* 0x040fe40007f1e0ff */
/*00b0*/ IADD3 R6, P1, R8, c[0x0][0x168], RZ ; /* 0x00005a0008067a10 */
/* 0x000fe40007f3e0ff */
/*00c0*/ IADD3.X R5, R0.reuse, c[0x0][0x164], RZ, P0, !PT ; /* 0x0000590000057a10 */
/* 0x040fe400007fe4ff */
/*00d0*/ IADD3.X R7, R0, c[0x0][0x16c], RZ, P1, !PT ; /* 0x00005b0000077a10 */
/* 0x000fc80000ffe4ff */
/*00e0*/ LDG.E.64 R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1b00 */
/*00f0*/ LDG.E.64 R2, [R6.64] ; /* 0x0000000406027981 */
/* 0x000ea2000c1e1b00 */
/*0100*/ IADD3 R8, P0, R8, c[0x0][0x170], RZ ; /* 0x00005c0008087a10 */
/* 0x000fc80007f1e0ff */
/*0110*/ IADD3.X R9, R0, c[0x0][0x174], RZ, P0, !PT ; /* 0x00005d0000097a10 */
/* 0x000fe200007fe4ff */
/*0120*/ DADD R2, R2, R4 ; /* 0x0000000002027229 */
/* 0x004e0e0000000004 */
/*0130*/ STG.E.64 [R8.64], R2 ; /* 0x0000000208007986 */
/* 0x001fe2000c101b04 */
/*0140*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0150*/ BRA 0x150; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.section .text._Z6vecAddIdEv9DevicePtrIT_ES2_S2_m,"axG",@progbits,_Z6vecAddIdEv9DevicePtrIT_ES2_S2_m,comdat
.protected _Z6vecAddIdEv9DevicePtrIT_ES2_S2_m
.globl _Z6vecAddIdEv9DevicePtrIT_ES2_S2_m
.p2align 8
.type _Z6vecAddIdEv9DevicePtrIT_ES2_S2_m,@function
_Z6vecAddIdEv9DevicePtrIT_ES2_S2_m:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x2c
s_load_b64 s[2:3], s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
v_mov_b32_e32 v2, 0
v_cmp_gt_u64_e32 vcc_lo, s[2:3], v[1:2]
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_lshlrev_b64 v[0:1], 3, v[1:2]
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b64 v[2:3], v[2:3], off
global_load_b64 v[4:5], v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_f64 v[2:3], v[2:3], v[4:5]
global_store_b64 v[0:1], v[2:3], off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6vecAddIdEv9DevicePtrIT_ES2_S2_m
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.section .text._Z6vecAddIdEv9DevicePtrIT_ES2_S2_m,"axG",@progbits,_Z6vecAddIdEv9DevicePtrIT_ES2_S2_m,comdat
.Lfunc_end0:
.size _Z6vecAddIdEv9DevicePtrIT_ES2_S2_m, .Lfunc_end0-_Z6vecAddIdEv9DevicePtrIT_ES2_S2_m
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 8
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6vecAddIdEv9DevicePtrIT_ES2_S2_m
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6vecAddIdEv9DevicePtrIT_ES2_S2_m.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0014f190_00000000-6_03-templates-device-ptr.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.section .text._Z6vecAddIdEv9DevicePtrIT_ES2_S2_m,"axG",@progbits,_Z6vecAddIdEv9DevicePtrIT_ES2_S2_m,comdat
.weak _Z6vecAddIdEv9DevicePtrIT_ES2_S2_m
.type _Z6vecAddIdEv9DevicePtrIT_ES2_S2_m, @function
_Z6vecAddIdEv9DevicePtrIT_ES2_S2_m:
.LFB4383:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
movq %rcx, 40(%rsp)
leaq 24(%rsp), %rax
movq %rax, 112(%rsp)
leaq 16(%rsp), %rax
movq %rax, 120(%rsp)
leaq 8(%rsp), %rax
movq %rax, 128(%rsp)
leaq 40(%rsp), %rax
movq %rax, 136(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L5
.L1:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L6
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L5:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 184
pushq 56(%rsp)
.cfi_def_cfa_offset 192
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z6vecAddIdEv9DevicePtrIT_ES2_S2_m(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L1
.L6:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4383:
.size _Z6vecAddIdEv9DevicePtrIT_ES2_S2_m, .-_Z6vecAddIdEv9DevicePtrIT_ES2_S2_m
.text
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB4042:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4042:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z6vecAddIdEv9DevicePtrIT_ES2_S2_m"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB4067:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z6vecAddIdEv9DevicePtrIT_ES2_S2_m(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4067:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .rodata._ZNSt6vectorIdSaIdEEC2EmRKS0_.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "cannot create std::vector larger than max_size()"
.section .text._ZNSt6vectorIdSaIdEEC2EmRKS0_,"axG",@progbits,_ZNSt6vectorIdSaIdEEC5EmRKS0_,comdat
.align 2
.weak _ZNSt6vectorIdSaIdEEC2EmRKS0_
.type _ZNSt6vectorIdSaIdEEC2EmRKS0_, @function
_ZNSt6vectorIdSaIdEEC2EmRKS0_:
.LFB4374:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
movq %rsi, %rax
shrq $60, %rax
jne .L21
movq %rdi, %rbx
movq %rsi, %rbp
movq $0, (%rdi)
movq $0, 8(%rdi)
movq $0, 16(%rdi)
testq %rsi, %rsi
je .L13
leaq 0(,%rsi,8), %r12
movq %r12, %rdi
call _Znwm@PLT
movq %rax, (%rbx)
movq %rax, 8(%rbx)
leaq (%rax,%r12), %rdx
movq %rdx, 16(%rbx)
movq $0x000000000, (%rax)
addq $8, %rax
cmpq $1, %rbp
je .L16
cmpq %rax, %rdx
je .L17
.L15:
movq $0x000000000, (%rax)
addq $8, %rax
cmpq %rax, %rdx
jne .L15
jmp .L14
.L21:
leaq .LC1(%rip), %rdi
call _ZSt20__throw_length_errorPKc@PLT
.L16:
movq %rax, %rdx
jmp .L14
.L17:
movq %rax, %rdx
jmp .L14
.L13:
movq $0, (%rdi)
movq $0, 16(%rdi)
movl $0, %edx
.L14:
movq %rdx, 8(%rbx)
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4374:
.size _ZNSt6vectorIdSaIdEEC2EmRKS0_, .-_ZNSt6vectorIdSaIdEEC2EmRKS0_
.weak _ZNSt6vectorIdSaIdEEC1EmRKS0_
.set _ZNSt6vectorIdSaIdEEC1EmRKS0_,_ZNSt6vectorIdSaIdEEC2EmRKS0_
.section .text._ZNSt6vectorIdSaIdEED2Ev,"axG",@progbits,_ZNSt6vectorIdSaIdEED5Ev,comdat
.align 2
.weak _ZNSt6vectorIdSaIdEED2Ev
.type _ZNSt6vectorIdSaIdEED2Ev, @function
_ZNSt6vectorIdSaIdEED2Ev:
.LFB4377:
.cfi_startproc
endbr64
movq (%rdi), %rax
testq %rax, %rax
je .L25
subq $8, %rsp
.cfi_def_cfa_offset 16
movq 16(%rdi), %rsi
subq %rax, %rsi
movq %rax, %rdi
call _ZdlPvm@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.L25:
ret
.cfi_endproc
.LFE4377:
.size _ZNSt6vectorIdSaIdEED2Ev, .-_ZNSt6vectorIdSaIdEED2Ev
.weak _ZNSt6vectorIdSaIdEED1Ev
.set _ZNSt6vectorIdSaIdEED1Ev,_ZNSt6vectorIdSaIdEED2Ev
.section .rodata.str1.1,"aMS",@progbits,1
.LC5:
.string "final result: "
.text
.globl main
.type main, @function
main:
.LFB4039:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA4039
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $184, %rsp
.cfi_def_cfa_offset 224
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 144(%rsp), %rbx
leaq 80(%rsp), %rdi
movq %rbx, %rdx
movl $1000, %esi
.LEHB0:
call _ZNSt6vectorIdSaIdEEC1EmRKS0_
.LEHE0:
leaq 112(%rsp), %rdi
movq %rbx, %rdx
movl $1000, %esi
.LEHB1:
call _ZNSt6vectorIdSaIdEEC1EmRKS0_
.LEHE1:
movq 80(%rsp), %r12
movq 112(%rsp), %rbp
movl $1000, %ebx
movq $0x000000000, 8(%rsp)
movabsq $-9223372036854775808, %r13
jmp .L31
.L29:
movsd 8(%rsp), %xmm2
subsd .LC3(%rip), %xmm2
cvttsd2siq %xmm2, %rax
xorq %r13, %rax
.L30:
mulsd %xmm1, %xmm1
movsd %xmm1, (%r12,%rax,8)
mulsd %xmm0, %xmm0
movsd %xmm0, 0(%rbp,%rax,8)
movsd .LC4(%rip), %xmm6
addsd 8(%rsp), %xmm6
movsd %xmm6, 8(%rsp)
subl $1, %ebx
je .L48
.L31:
leaq 24(%rsp), %rdi
leaq 16(%rsp), %rsi
movsd 8(%rsp), %xmm0
call sincos@PLT
movsd 16(%rsp), %xmm0
movsd 24(%rsp), %xmm1
movsd 8(%rsp), %xmm5
comisd .LC3(%rip), %xmm5
jnb .L29
cvttsd2siq %xmm5, %rax
jmp .L30
.L48:
leaq 40(%rsp), %rdi
movl $8000, %esi
.LEHB2:
call cudaMalloc@PLT
leaq 48(%rsp), %rdi
movl $8000, %esi
call cudaMalloc@PLT
leaq 56(%rsp), %rdi
movl $8000, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $8000, %edx
movq %r12, %rsi
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $8000, %edx
movq %rbp, %rsi
movq 48(%rsp), %rdi
call cudaMemcpy@PLT
movl $1024, 144(%rsp)
movl $1, 148(%rsp)
movl $1, 152(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 144(%rsp), %rdx
movl $1, %ecx
movq 68(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L32
movl $1000, %ecx
movq 56(%rsp), %rdx
movq 48(%rsp), %rsi
movq 40(%rsp), %rdi
call _Z6vecAddIdEv9DevicePtrIT_ES2_S2_m
.L32:
leaq 68(%rsp), %rdx
leaq 144(%rsp), %rdi
movl $1000, %esi
call _ZNSt6vectorIdSaIdEEC1EmRKS0_
.LEHE2:
movq 144(%rsp), %rbp
movl $2, %ecx
movl $8000, %edx
movq 56(%rsp), %rsi
movq %rbp, %rdi
.LEHB3:
call cudaMemcpy@PLT
movl $1000, %eax
pxor %xmm0, %xmm0
movq %xmm0, %rbx
movsd .LC3(%rip), %xmm2
movapd %xmm2, %xmm4
movabsq $-9223372036854775808, %rcx
movsd .LC4(%rip), %xmm1
jmp .L35
.L33:
movapd %xmm0, %xmm3
subsd %xmm4, %xmm3
cvttsd2siq %xmm3, %rdx
xorq %rcx, %rdx
.L34:
movq %rbx, %xmm7
addsd 0(%rbp,%rdx,8), %xmm7
movq %xmm7, %rbx
addsd %xmm1, %xmm0
subl $1, %eax
je .L49
.L35:
comisd %xmm2, %xmm0
jnb .L33
cvttsd2siq %xmm0, %rdx
jmp .L34
.L49:
leaq .LC5(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq %rbx, %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq 48(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rdi
call cudaFree@PLT
.LEHE3:
leaq 144(%rsp), %rdi
call _ZNSt6vectorIdSaIdEED1Ev
leaq 112(%rsp), %rdi
call _ZNSt6vectorIdSaIdEED1Ev
leaq 80(%rsp), %rdi
call _ZNSt6vectorIdSaIdEED1Ev
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L50
movl $0, %eax
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L43:
.cfi_restore_state
endbr64
movq %rax, %rbx
leaq 144(%rsp), %rdi
call _ZNSt6vectorIdSaIdEED1Ev
.L37:
leaq 112(%rsp), %rdi
call _ZNSt6vectorIdSaIdEED1Ev
.L38:
leaq 80(%rsp), %rdi
call _ZNSt6vectorIdSaIdEED1Ev
movq 168(%rsp), %rax
subq %fs:40, %rax
je .L39
call __stack_chk_fail@PLT
.L42:
endbr64
movq %rax, %rbx
jmp .L37
.L41:
endbr64
movq %rax, %rbx
jmp .L38
.L39:
movq %rbx, %rdi
.LEHB4:
call _Unwind_Resume@PLT
.LEHE4:
.L50:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4039:
.globl __gxx_personality_v0
.section .gcc_except_table,"a",@progbits
.LLSDA4039:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE4039-.LLSDACSB4039
.LLSDACSB4039:
.uleb128 .LEHB0-.LFB4039
.uleb128 .LEHE0-.LEHB0
.uleb128 0
.uleb128 0
.uleb128 .LEHB1-.LFB4039
.uleb128 .LEHE1-.LEHB1
.uleb128 .L41-.LFB4039
.uleb128 0
.uleb128 .LEHB2-.LFB4039
.uleb128 .LEHE2-.LEHB2
.uleb128 .L42-.LFB4039
.uleb128 0
.uleb128 .LEHB3-.LFB4039
.uleb128 .LEHE3-.LEHB3
.uleb128 .L43-.LFB4039
.uleb128 0
.uleb128 .LEHB4-.LFB4039
.uleb128 .LEHE4-.LEHB4
.uleb128 0
.uleb128 0
.LLSDACSE4039:
.text
.size main, .-main
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC3:
.long 0
.long 1138753536
.align 8
.LC4:
.long 0
.long 1072693248
.hidden DW.ref.__gxx_personality_v0
.weak DW.ref.__gxx_personality_v0
.section .data.rel.local.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat
.align 8
.type DW.ref.__gxx_personality_v0, @object
.size DW.ref.__gxx_personality_v0, 8
DW.ref.__gxx_personality_v0:
.quad __gxx_personality_v0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "03-templates-device-ptr.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.Lfunc_begin0:
.cfi_startproc
.cfi_personality 3, __gxx_personality_v0
.cfi_lsda 3, .Lexception0
# %bb.0: # %_ZNSt6vectorIdSaIdEEC2EmRKS0_.exit
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $160, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
.cfi_escape 0x2e, 0x00
movl $8000, %edi # imm = 0x1F40
callq _Znwm
movq %rax, %rbx
.cfi_escape 0x2e, 0x00
movl $8000, %edx # imm = 0x1F40
movq %rax, %rdi
xorl %esi, %esi
callq memset@PLT
.Ltmp0:
.cfi_escape 0x2e, 0x00
movl $8000, %edi # imm = 0x1F40
callq _Znwm
.Ltmp1:
# %bb.1: # %_ZNSt6vectorIdSaIdEEC2EmRKS0_.exit36
movq %rax, %r14
.cfi_escape 0x2e, 0x00
xorl %r15d, %r15d
movl $8000, %edx # imm = 0x1F40
movq %rax, %rdi
xorl %esi, %esi
callq memset@PLT
.p2align 4, 0x90
.LBB0_2: # =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtsi2sd %r15d, %xmm0
movsd %xmm0, 8(%rsp) # 8-byte Spill
.cfi_escape 0x2e, 0x00
callq sin
movsd %xmm0, 16(%rsp) # 8-byte Spill
.cfi_escape 0x2e, 0x00
movsd 8(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
callq sin
mulsd 16(%rsp), %xmm0 # 8-byte Folded Reload
movsd %xmm0, (%rbx,%r15,8)
.cfi_escape 0x2e, 0x00
movsd 8(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
callq cos
movsd %xmm0, 16(%rsp) # 8-byte Spill
.cfi_escape 0x2e, 0x00
movsd 8(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
callq cos
mulsd 16(%rsp), %xmm0 # 8-byte Folded Reload
movsd %xmm0, (%r14,%r15,8)
incq %r15
cmpq $1000, %r15 # imm = 0x3E8
jne .LBB0_2
# %bb.3:
.Ltmp3:
.cfi_escape 0x2e, 0x00
leaq 40(%rsp), %rdi
movl $8000, %esi # imm = 0x1F40
callq hipMalloc
.Ltmp4:
# %bb.4: # %_ZL9hipMallocIdE10hipError_tPPT_m.exit
.Ltmp5:
.cfi_escape 0x2e, 0x00
leaq 32(%rsp), %rdi
movl $8000, %esi # imm = 0x1F40
callq hipMalloc
.Ltmp6:
# %bb.5: # %_ZL9hipMallocIdE10hipError_tPPT_m.exit37
.Ltmp7:
.cfi_escape 0x2e, 0x00
leaq 24(%rsp), %rdi
movl $8000, %esi # imm = 0x1F40
callq hipMalloc
.Ltmp8:
# %bb.6: # %_ZL9hipMallocIdE10hipError_tPPT_m.exit38
movq 40(%rsp), %rdi
.Ltmp9:
.cfi_escape 0x2e, 0x00
movl $8000, %edx # imm = 0x1F40
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
.Ltmp10:
# %bb.7:
movq 32(%rsp), %rdi
.Ltmp11:
.cfi_escape 0x2e, 0x00
movl $8000, %edx # imm = 0x1F40
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
.Ltmp12:
# %bb.8:
.Ltmp14:
.cfi_escape 0x2e, 0x00
movabsq $4294967297, %rdi # imm = 0x100000001
movabsq $4294968320, %rdx # imm = 0x100000400
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
.Ltmp15:
# %bb.9:
testl %eax, %eax
jne .LBB0_12
# %bb.10:
movq 40(%rsp), %rax
movq 32(%rsp), %rcx
movq 24(%rsp), %rdx
movq %rax, 120(%rsp)
movq %rcx, 112(%rsp)
movq %rdx, 104(%rsp)
movq $1000, 96(%rsp) # imm = 0x3E8
leaq 120(%rsp), %rax
movq %rax, 128(%rsp)
leaq 112(%rsp), %rax
movq %rax, 136(%rsp)
leaq 104(%rsp), %rax
movq %rax, 144(%rsp)
leaq 96(%rsp), %rax
movq %rax, 152(%rsp)
.Ltmp16:
.cfi_escape 0x2e, 0x00
leaq 80(%rsp), %rdi
leaq 64(%rsp), %rsi
leaq 56(%rsp), %rdx
leaq 48(%rsp), %rcx
callq __hipPopCallConfiguration
.Ltmp17:
# %bb.11: # %.noexc
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
movq 64(%rsp), %rcx
movl 72(%rsp), %r8d
.Ltmp18:
.cfi_escape 0x2e, 0x10
leaq 128(%rsp), %r9
movl $_Z6vecAddIdEv9DevicePtrIT_ES2_S2_m, %edi
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.Ltmp19:
.LBB0_12:
.Ltmp21:
.cfi_escape 0x2e, 0x00
movl $8000, %edi # imm = 0x1F40
callq _Znwm
.Ltmp22:
# %bb.13: # %_ZNSt6vectorIdSaIdEEC2EmRKS0_.exit41
movq %rax, %r15
.cfi_escape 0x2e, 0x00
movl $8000, %edx # imm = 0x1F40
movq %rax, %rdi
xorl %esi, %esi
callq memset@PLT
movq 24(%rsp), %rsi
.Ltmp24:
.cfi_escape 0x2e, 0x00
movl $8000, %edx # imm = 0x1F40
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
.Ltmp25:
# %bb.14: # %.preheader.preheader
xorpd %xmm0, %xmm0
xorl %eax, %eax
.p2align 4, 0x90
.LBB0_15: # %.preheader
# =>This Inner Loop Header: Depth=1
addsd (%r15,%rax,8), %xmm0
incq %rax
cmpq $1000, %rax # imm = 0x3E8
jne .LBB0_15
# %bb.16:
.Ltmp27:
movsd %xmm0, 8(%rsp) # 8-byte Spill
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $14, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp28:
# %bb.17: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit
.Ltmp29:
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
movsd 8(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
callq _ZNSo9_M_insertIdEERSoT_
.Ltmp30:
# %bb.18: # %_ZNSolsEd.exit
movq %rax, %r12
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%r12,%rax), %r13
testq %r13, %r13
je .LBB0_19
# %bb.25: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%r13)
je .LBB0_27
# %bb.26:
movzbl 67(%r13), %eax
jmp .LBB0_29
.LBB0_27:
.Ltmp31:
.cfi_escape 0x2e, 0x00
movq %r13, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
.Ltmp32:
# %bb.28: # %.noexc57
movq (%r13), %rax
.Ltmp33:
.cfi_escape 0x2e, 0x00
movq %r13, %rdi
movl $10, %esi
callq *48(%rax)
.Ltmp34:
.LBB0_29: # %_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc.exit.i
.Ltmp35:
.cfi_escape 0x2e, 0x00
movsbl %al, %esi
movq %r12, %rdi
callq _ZNSo3putEc
.Ltmp36:
# %bb.30: # %.noexc59
.Ltmp37:
.cfi_escape 0x2e, 0x00
movq %rax, %rdi
callq _ZNSo5flushEv
.Ltmp38:
# %bb.31: # %_ZNSolsEPFRSoS_E.exit
movq 40(%rsp), %rdi
.Ltmp39:
.cfi_escape 0x2e, 0x00
callq hipFree
.Ltmp40:
# %bb.32:
movq 32(%rsp), %rdi
.Ltmp41:
.cfi_escape 0x2e, 0x00
callq hipFree
.Ltmp42:
# %bb.33:
movq 24(%rsp), %rdi
.Ltmp43:
.cfi_escape 0x2e, 0x00
callq hipFree
.Ltmp44:
# %bb.34: # %_ZNSt6vectorIdSaIdEED2Ev.exit
.cfi_escape 0x2e, 0x00
movq %r15, %rdi
callq _ZdlPv
.cfi_escape 0x2e, 0x00
movq %r14, %rdi
callq _ZdlPv
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
callq _ZdlPv
xorl %eax, %eax
addq $160, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB0_19:
.cfi_def_cfa_offset 208
.Ltmp45:
.cfi_escape 0x2e, 0x00
callq _ZSt16__throw_bad_castv
.Ltmp46:
# %bb.24: # %.noexc56
.LBB0_23:
.Ltmp26:
jmp .LBB0_36
.LBB0_22:
.Ltmp23:
movq %rax, %r12
jmp .LBB0_37
.LBB0_39:
.Ltmp2:
movq %rax, %r12
jmp .LBB0_38
.LBB0_21:
.Ltmp20:
movq %rax, %r12
jmp .LBB0_37
.LBB0_20:
.Ltmp13:
movq %rax, %r12
jmp .LBB0_37
.LBB0_35:
.Ltmp47:
.LBB0_36: # %_ZNSt6vectorIdSaIdEED2Ev.exit50
movq %rax, %r12
.cfi_escape 0x2e, 0x00
movq %r15, %rdi
callq _ZdlPv
.LBB0_37: # %_ZNSt6vectorIdSaIdEED2Ev.exit52
.cfi_escape 0x2e, 0x00
movq %r14, %rdi
callq _ZdlPv
.LBB0_38: # %_ZNSt6vectorIdSaIdEED2Ev.exit54
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
callq _ZdlPv
.cfi_escape 0x2e, 0x00
movq %r12, %rdi
callq _Unwind_Resume@PLT
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
.section .gcc_except_table,"a",@progbits
.p2align 2, 0x0
GCC_except_table0:
.Lexception0:
.byte 255 # @LPStart Encoding = omit
.byte 255 # @TType Encoding = omit
.byte 1 # Call site Encoding = uleb128
.uleb128 .Lcst_end0-.Lcst_begin0
.Lcst_begin0:
.uleb128 .Lfunc_begin0-.Lfunc_begin0 # >> Call Site 1 <<
.uleb128 .Ltmp0-.Lfunc_begin0 # Call between .Lfunc_begin0 and .Ltmp0
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp0-.Lfunc_begin0 # >> Call Site 2 <<
.uleb128 .Ltmp1-.Ltmp0 # Call between .Ltmp0 and .Ltmp1
.uleb128 .Ltmp2-.Lfunc_begin0 # jumps to .Ltmp2
.byte 0 # On action: cleanup
.uleb128 .Ltmp1-.Lfunc_begin0 # >> Call Site 3 <<
.uleb128 .Ltmp3-.Ltmp1 # Call between .Ltmp1 and .Ltmp3
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp3-.Lfunc_begin0 # >> Call Site 4 <<
.uleb128 .Ltmp12-.Ltmp3 # Call between .Ltmp3 and .Ltmp12
.uleb128 .Ltmp13-.Lfunc_begin0 # jumps to .Ltmp13
.byte 0 # On action: cleanup
.uleb128 .Ltmp14-.Lfunc_begin0 # >> Call Site 5 <<
.uleb128 .Ltmp19-.Ltmp14 # Call between .Ltmp14 and .Ltmp19
.uleb128 .Ltmp20-.Lfunc_begin0 # jumps to .Ltmp20
.byte 0 # On action: cleanup
.uleb128 .Ltmp21-.Lfunc_begin0 # >> Call Site 6 <<
.uleb128 .Ltmp22-.Ltmp21 # Call between .Ltmp21 and .Ltmp22
.uleb128 .Ltmp23-.Lfunc_begin0 # jumps to .Ltmp23
.byte 0 # On action: cleanup
.uleb128 .Ltmp22-.Lfunc_begin0 # >> Call Site 7 <<
.uleb128 .Ltmp24-.Ltmp22 # Call between .Ltmp22 and .Ltmp24
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp24-.Lfunc_begin0 # >> Call Site 8 <<
.uleb128 .Ltmp25-.Ltmp24 # Call between .Ltmp24 and .Ltmp25
.uleb128 .Ltmp26-.Lfunc_begin0 # jumps to .Ltmp26
.byte 0 # On action: cleanup
.uleb128 .Ltmp27-.Lfunc_begin0 # >> Call Site 9 <<
.uleb128 .Ltmp46-.Ltmp27 # Call between .Ltmp27 and .Ltmp46
.uleb128 .Ltmp47-.Lfunc_begin0 # jumps to .Ltmp47
.byte 0 # On action: cleanup
.uleb128 .Ltmp46-.Lfunc_begin0 # >> Call Site 10 <<
.uleb128 .Lfunc_end0-.Ltmp46 # Call between .Ltmp46 and .Lfunc_end0
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.Lcst_end0:
.p2align 2, 0x0
# -- End function
.section .text._Z21__device_stub__vecAddIdEv9DevicePtrIT_ES2_S2_m,"axG",@progbits,_Z21__device_stub__vecAddIdEv9DevicePtrIT_ES2_S2_m,comdat
.weak _Z21__device_stub__vecAddIdEv9DevicePtrIT_ES2_S2_m # -- Begin function _Z21__device_stub__vecAddIdEv9DevicePtrIT_ES2_S2_m
.p2align 4, 0x90
.type _Z21__device_stub__vecAddIdEv9DevicePtrIT_ES2_S2_m,@function
_Z21__device_stub__vecAddIdEv9DevicePtrIT_ES2_S2_m: # @_Z21__device_stub__vecAddIdEv9DevicePtrIT_ES2_S2_m
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movq %rcx, 48(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rax
movq %rax, 104(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6vecAddIdEv9DevicePtrIT_ES2_S2_m, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end1:
.size _Z21__device_stub__vecAddIdEv9DevicePtrIT_ES2_S2_m, .Lfunc_end1-_Z21__device_stub__vecAddIdEv9DevicePtrIT_ES2_S2_m
.cfi_endproc
# -- End function
.text
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6vecAddIdEv9DevicePtrIT_ES2_S2_m, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6vecAddIdEv9DevicePtrIT_ES2_S2_m,@object # @_Z6vecAddIdEv9DevicePtrIT_ES2_S2_m
.section .rodata._Z6vecAddIdEv9DevicePtrIT_ES2_S2_m,"aG",@progbits,_Z6vecAddIdEv9DevicePtrIT_ES2_S2_m,comdat
.weak _Z6vecAddIdEv9DevicePtrIT_ES2_S2_m
.p2align 3, 0x0
_Z6vecAddIdEv9DevicePtrIT_ES2_S2_m:
.quad _Z21__device_stub__vecAddIdEv9DevicePtrIT_ES2_S2_m
.size _Z6vecAddIdEv9DevicePtrIT_ES2_S2_m, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "final result: "
.size .L.str, 15
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z6vecAddIdEv9DevicePtrIT_ES2_S2_m"
.size .L__unnamed_1, 35
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __gxx_personality_v0
.addrsig_sym _Z21__device_stub__vecAddIdEv9DevicePtrIT_ES2_S2_m
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Unwind_Resume
.addrsig_sym _Z6vecAddIdEv9DevicePtrIT_ES2_S2_m
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void kernel_test7_write(char* _ptr, char* end_ptr, char* _start_ptr, unsigned int* err)
{
unsigned int i;
unsigned int* ptr = (unsigned int*) (_ptr + blockIdx.x*BLOCKSIZE);
unsigned int* start_ptr = (unsigned int*) _start_ptr;
if (ptr >= (unsigned int*) end_ptr) {
return;
}
for (i = 0;i < BLOCKSIZE/sizeof(unsigned int); i++){
ptr[i] = start_ptr[i];
}
return;
} | code for sm_80
Function : _Z18kernel_test7_writePcS_S_Pj
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e240000002500 */
/*0020*/ LEA R0, P1, R0, c[0x0][0x160], 0x14 ; /* 0x0000580000007a11 */
/* 0x001fc8000782a0ff */
/*0030*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x168], PT ; /* 0x00005a0000007a0c */
/* 0x000fe20003f06070 */
/*0040*/ IMAD.X R13, RZ, RZ, c[0x0][0x164], P1 ; /* 0x00005900ff0d7624 */
/* 0x000fca00008e06ff */
/*0050*/ ISETP.GE.U32.AND.EX P0, PT, R13, c[0x0][0x16c], PT, P0 ; /* 0x00005b000d007a0c */
/* 0x000fda0003f06100 */
/*0060*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0070*/ IADD3 R8, P0, R0, 0x40, RZ ; /* 0x0000004000087810 */
/* 0x000fe20007f1e0ff */
/*0080*/ HFMA2.MMA R0, -RZ, RZ, 0, 0 ; /* 0x00000000ff007435 */
/* 0x000fe200000001ff */
/*0090*/ IMAD.MOV.U32 R6, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff067624 */
/* 0x000fe200078e00ff */
/*00a0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00b0*/ IMAD.MOV.U32 R11, RZ, RZ, c[0x0][0x174] ; /* 0x00005d00ff0b7624 */
/* 0x000fe400078e00ff */
/*00c0*/ IMAD.X R13, RZ, RZ, R13, P0 ; /* 0x000000ffff0d7224 */
/* 0x000fe400000e060d */
/*00d0*/ IMAD.MOV.U32 R2, RZ, RZ, R6 ; /* 0x000000ffff027224 */
/* 0x000fe200078e0006 */
/*00e0*/ MOV R3, R11 ; /* 0x0000000b00037202 */
/* 0x000fca0000000f00 */
/*00f0*/ LDG.E R7, [R2.64] ; /* 0x0000000402077981 */
/* 0x008ea2000c1e1900 */
/*0100*/ IMAD.MOV.U32 R4, RZ, RZ, R8 ; /* 0x000000ffff047224 */
/* 0x000fe400078e0008 */
/*0110*/ IMAD.MOV.U32 R5, RZ, RZ, R13 ; /* 0x000000ffff057224 */
/* 0x000fca00078e000d */
/*0120*/ STG.E [R4.64+-0x40], R7 ; /* 0xffffc00704007986 */
/* 0x0041e8000c101904 */
/*0130*/ LDG.E R9, [R2.64+0x4] ; /* 0x0000040402097981 */
/* 0x000ea8000c1e1900 */
/*0140*/ STG.E [R4.64+-0x3c], R9 ; /* 0xffffc40904007986 */
/* 0x0043e8000c101904 */
/*0150*/ LDG.E R11, [R2.64+0x8] ; /* 0x00000804020b7981 */
/* 0x000ea8000c1e1900 */
/*0160*/ STG.E [R4.64+-0x38], R11 ; /* 0xffffc80b04007986 */
/* 0x0045e8000c101904 */
/*0170*/ LDG.E R13, [R2.64+0xc] ; /* 0x00000c04020d7981 */
/* 0x000ee8000c1e1900 */
/*0180*/ STG.E [R4.64+-0x34], R13 ; /* 0xffffcc0d04007986 */
/* 0x0087e8000c101904 */
/*0190*/ LDG.E R15, [R2.64+0x10] ; /* 0x00001004020f7981 */
/* 0x000f28000c1e1900 */
/*01a0*/ STG.E [R4.64+-0x30], R15 ; /* 0xffffd00f04007986 */
/* 0x0109e8000c101904 */
/*01b0*/ LDG.E R17, [R2.64+0x14] ; /* 0x0000140402117981 */
/* 0x000f68000c1e1900 */
/*01c0*/ STG.E [R4.64+-0x2c], R17 ; /* 0xffffd41104007986 */
/* 0x020be8000c101904 */
/*01d0*/ LDG.E R7, [R2.64+0x18] ; /* 0x0000180402077981 */
/* 0x001ea8000c1e1900 */
/*01e0*/ STG.E [R4.64+-0x28], R7 ; /* 0xffffd80704007986 */
/* 0x0041e8000c101904 */
/*01f0*/ LDG.E R9, [R2.64+0x1c] ; /* 0x00001c0402097981 */
/* 0x002ea8000c1e1900 */
/*0200*/ STG.E [R4.64+-0x24], R9 ; /* 0xffffdc0904007986 */
/* 0x0043e8000c101904 */
/*0210*/ LDG.E R11, [R2.64+0x20] ; /* 0x00002004020b7981 */
/* 0x000ea8000c1e1900 */
/*0220*/ STG.E [R4.64+-0x20], R11 ; /* 0xffffe00b04007986 */
/* 0x0045e8000c101904 */
/*0230*/ LDG.E R13, [R2.64+0x24] ; /* 0x00002404020d7981 */
/* 0x008ee8000c1e1900 */
/*0240*/ STG.E [R4.64+-0x1c], R13 ; /* 0xffffe40d04007986 */
/* 0x0087e8000c101904 */
/*0250*/ LDG.E R15, [R2.64+0x28] ; /* 0x00002804020f7981 */
/* 0x010f28000c1e1900 */
/*0260*/ STG.E [R4.64+-0x18], R15 ; /* 0xffffe80f04007986 */
/* 0x0109e8000c101904 */
/*0270*/ LDG.E R17, [R2.64+0x2c] ; /* 0x00002c0402117981 */
/* 0x020f68000c1e1900 */
/*0280*/ STG.E [R4.64+-0x14], R17 ; /* 0xffffec1104007986 */
/* 0x020be8000c101904 */
/*0290*/ LDG.E R7, [R2.64+0x30] ; /* 0x0000300402077981 */
/* 0x001ea8000c1e1900 */
/*02a0*/ STG.E [R4.64+-0x10], R7 ; /* 0xfffff00704007986 */
/* 0x0041e8000c101904 */
/*02b0*/ LDG.E R9, [R2.64+0x34] ; /* 0x0000340402097981 */
/* 0x002ea8000c1e1900 */
/*02c0*/ STG.E [R4.64+-0xc], R9 ; /* 0xfffff40904007986 */
/* 0x0043e8000c101904 */
/*02d0*/ LDG.E R11, [R2.64+0x38] ; /* 0x00003804020b7981 */
/* 0x000ea8000c1e1900 */
/*02e0*/ STG.E [R4.64+-0x8], R11 ; /* 0xfffff80b04007986 */
/* 0x0045e8000c101904 */
/*02f0*/ LDG.E R13, [R2.64+0x3c] ; /* 0x00003c04020d7981 */
/* 0x008ee8000c1e1900 */
/*0300*/ STG.E [R4.64+-0x4], R13 ; /* 0xfffffc0d04007986 */
/* 0x0087e8000c101904 */
/*0310*/ LDG.E R15, [R2.64+0x40] ; /* 0x00004004020f7981 */
/* 0x010f28000c1e1900 */
/*0320*/ STG.E [R4.64], R15 ; /* 0x0000000f04007986 */
/* 0x0109e8000c101904 */
/*0330*/ LDG.E R17, [R2.64+0x44] ; /* 0x0000440402117981 */
/* 0x020f68000c1e1900 */
/*0340*/ STG.E [R4.64+0x4], R17 ; /* 0x0000041104007986 */
/* 0x020be8000c101904 */
/*0350*/ LDG.E R7, [R2.64+0x48] ; /* 0x0000480402077981 */
/* 0x001ea8000c1e1900 */
/*0360*/ STG.E [R4.64+0x8], R7 ; /* 0x0000080704007986 */
/* 0x0041e8000c101904 */
/*0370*/ LDG.E R9, [R2.64+0x4c] ; /* 0x00004c0402097981 */
/* 0x002ea8000c1e1900 */
/*0380*/ STG.E [R4.64+0xc], R9 ; /* 0x00000c0904007986 */
/* 0x0043e8000c101904 */
/*0390*/ LDG.E R11, [R2.64+0x50] ; /* 0x00005004020b7981 */
/* 0x000ea8000c1e1900 */
/*03a0*/ STG.E [R4.64+0x10], R11 ; /* 0x0000100b04007986 */
/* 0x0045e8000c101904 */
/*03b0*/ LDG.E R13, [R2.64+0x54] ; /* 0x00005404020d7981 */
/* 0x008ee8000c1e1900 */
/*03c0*/ STG.E [R4.64+0x14], R13 ; /* 0x0000140d04007986 */
/* 0x0087e8000c101904 */
/*03d0*/ LDG.E R15, [R2.64+0x58] ; /* 0x00005804020f7981 */
/* 0x010f28000c1e1900 */
/*03e0*/ STG.E [R4.64+0x18], R15 ; /* 0x0000180f04007986 */
/* 0x0109e8000c101904 */
/*03f0*/ LDG.E R17, [R2.64+0x5c] ; /* 0x00005c0402117981 */
/* 0x020f68000c1e1900 */
/*0400*/ STG.E [R4.64+0x1c], R17 ; /* 0x00001c1104007986 */
/* 0x020be8000c101904 */
/*0410*/ LDG.E R7, [R2.64+0x60] ; /* 0x0000600402077981 */
/* 0x001ea8000c1e1900 */
/*0420*/ STG.E [R4.64+0x20], R7 ; /* 0x0000200704007986 */
/* 0x0041e8000c101904 */
/*0430*/ LDG.E R9, [R2.64+0x64] ; /* 0x0000640402097981 */
/* 0x002ea8000c1e1900 */
/*0440*/ STG.E [R4.64+0x24], R9 ; /* 0x0000240904007986 */
/* 0x0043e8000c101904 */
/*0450*/ LDG.E R11, [R2.64+0x68] ; /* 0x00006804020b7981 */
/* 0x000ea8000c1e1900 */
/*0460*/ STG.E [R4.64+0x28], R11 ; /* 0x0000280b04007986 */
/* 0x004fe8000c101904 */
/*0470*/ LDG.E R13, [R2.64+0x6c] ; /* 0x00006c04020d7981 */
/* 0x008ea8000c1e1900 */
/*0480*/ STG.E [R4.64+0x2c], R13 ; /* 0x00002c0d04007986 */
/* 0x0045e8000c101904 */
/*0490*/ LDG.E R15, [R2.64+0x70] ; /* 0x00007004020f7981 */
/* 0x010ee8000c1e1900 */
/*04a0*/ STG.E [R4.64+0x30], R15 ; /* 0x0000300f04007986 */
/* 0x0087e8000c101904 */
/*04b0*/ LDG.E R17, [R2.64+0x74] ; /* 0x0000740402117981 */
/* 0x020f28000c1e1900 */
/*04c0*/ STG.E [R4.64+0x34], R17 ; /* 0x0000341104007986 */
/* 0x0107e8000c101904 */
/*04d0*/ LDG.E R7, [R2.64+0x78] ; /* 0x0000780402077981 */
/* 0x001f22000c1e1900 */
/*04e0*/ IADD3 R0, R0, 0x20, RZ ; /* 0x0000002000007810 */
/* 0x000fc80007ffe0ff */
/*04f0*/ ISETP.NE.AND P0, PT, R0, 0x40000, PT ; /* 0x000400000000780c */
/* 0x000fe20003f05270 */
/*0500*/ STG.E [R4.64+0x38], R7 ; /* 0x0000380704007986 */
/* 0x0107e8000c101904 */
/*0510*/ LDG.E R9, [R2.64+0x7c] ; /* 0x00007c0402097981 */
/* 0x002f22000c1e1900 */
/*0520*/ IADD3 R8, P2, R4, 0x80, RZ ; /* 0x0000008004087810 */
/* 0x000fe40007f5e0ff */
/*0530*/ IADD3 R6, P1, R2, 0x80, RZ ; /* 0x0000008002067810 */
/* 0x000fc60007f3e0ff */
/*0540*/ IMAD.X R13, RZ, RZ, R5, P2 ; /* 0x000000ffff0d7224 */
/* 0x004fe200010e0605 */
/*0550*/ IADD3.X R11, RZ, R3, RZ, P1, !PT ; /* 0x00000003ff0b7210 */
/* 0x000fe20000ffe4ff */
/*0560*/ STG.E [R4.64+0x3c], R9 ; /* 0x00003c0904007986 */
/* 0x0107e2000c101904 */
/*0570*/ @P0 BRA 0xd0 ; /* 0xfffffb5000000947 */
/* 0x000fea000383ffff */
/*0580*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0590*/ BRA 0x590; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*05a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0600*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0610*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0620*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0630*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0640*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0650*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0660*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0670*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void kernel_test7_write(char* _ptr, char* end_ptr, char* _start_ptr, unsigned int* err)
{
unsigned int i;
unsigned int* ptr = (unsigned int*) (_ptr + blockIdx.x*BLOCKSIZE);
unsigned int* start_ptr = (unsigned int*) _start_ptr;
if (ptr >= (unsigned int*) end_ptr) {
return;
}
for (i = 0;i < BLOCKSIZE/sizeof(unsigned int); i++){
ptr[i] = start_ptr[i];
}
return;
} | .file "tmpxft_000b1424_00000000-6_kernel_test7_write.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z44__device_stub__Z18kernel_test7_writePcS_S_PjPcS_S_Pj
.type _Z44__device_stub__Z18kernel_test7_writePcS_S_PjPcS_S_Pj, @function
_Z44__device_stub__Z18kernel_test7_writePcS_S_PjPcS_S_Pj:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z18kernel_test7_writePcS_S_Pj(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z44__device_stub__Z18kernel_test7_writePcS_S_PjPcS_S_Pj, .-_Z44__device_stub__Z18kernel_test7_writePcS_S_PjPcS_S_Pj
.globl _Z18kernel_test7_writePcS_S_Pj
.type _Z18kernel_test7_writePcS_S_Pj, @function
_Z18kernel_test7_writePcS_S_Pj:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z44__device_stub__Z18kernel_test7_writePcS_S_PjPcS_S_Pj
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z18kernel_test7_writePcS_S_Pj, .-_Z18kernel_test7_writePcS_S_Pj
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z18kernel_test7_writePcS_S_Pj"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z18kernel_test7_writePcS_S_Pj(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void kernel_test7_write(char* _ptr, char* end_ptr, char* _start_ptr, unsigned int* err)
{
unsigned int i;
unsigned int* ptr = (unsigned int*) (_ptr + blockIdx.x*BLOCKSIZE);
unsigned int* start_ptr = (unsigned int*) _start_ptr;
if (ptr >= (unsigned int*) end_ptr) {
return;
}
for (i = 0;i < BLOCKSIZE/sizeof(unsigned int); i++){
ptr[i] = start_ptr[i];
}
return;
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void kernel_test7_write(char* _ptr, char* end_ptr, char* _start_ptr, unsigned int* err)
{
unsigned int i;
unsigned int* ptr = (unsigned int*) (_ptr + blockIdx.x*BLOCKSIZE);
unsigned int* start_ptr = (unsigned int*) _start_ptr;
if (ptr >= (unsigned int*) end_ptr) {
return;
}
for (i = 0;i < BLOCKSIZE/sizeof(unsigned int); i++){
ptr[i] = start_ptr[i];
}
return;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void kernel_test7_write(char* _ptr, char* end_ptr, char* _start_ptr, unsigned int* err)
{
unsigned int i;
unsigned int* ptr = (unsigned int*) (_ptr + blockIdx.x*BLOCKSIZE);
unsigned int* start_ptr = (unsigned int*) _start_ptr;
if (ptr >= (unsigned int*) end_ptr) {
return;
}
for (i = 0;i < BLOCKSIZE/sizeof(unsigned int); i++){
ptr[i] = start_ptr[i];
}
return;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z18kernel_test7_writePcS_S_Pj
.globl _Z18kernel_test7_writePcS_S_Pj
.p2align 8
.type _Z18kernel_test7_writePcS_S_Pj,@function
_Z18kernel_test7_writePcS_S_Pj:
s_load_b128 s[4:7], s[0:1], 0x0
s_lshl_b32 s2, s15, 20
s_waitcnt lgkmcnt(0)
s_add_u32 s2, s4, s2
s_addc_u32 s3, s5, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_ge_u64_e64 s4, s[2:3], s[6:7]
s_and_b32 vcc_lo, exec_lo, s4
s_cbranch_vccnz .LBB0_3
s_load_b64 s[0:1], s[0:1], 0x10
v_mov_b32_e32 v0, 0
s_mov_b64 s[4:5], 0
.LBB0_2:
s_waitcnt lgkmcnt(0)
s_add_u32 s6, s0, s4
s_addc_u32 s7, s1, s5
global_load_b32 v1, v0, s[6:7]
s_add_u32 s6, s2, s4
s_addc_u32 s7, s3, s5
s_add_u32 s4, s4, 4
s_addc_u32 s5, s5, 0
s_cmp_lg_u32 s4, 0x100000
s_waitcnt vmcnt(0)
global_store_b32 v0, v1, s[6:7]
s_cbranch_scc1 .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z18kernel_test7_writePcS_S_Pj
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 32
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z18kernel_test7_writePcS_S_Pj, .Lfunc_end0-_Z18kernel_test7_writePcS_S_Pj
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 32
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z18kernel_test7_writePcS_S_Pj
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z18kernel_test7_writePcS_S_Pj.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void kernel_test7_write(char* _ptr, char* end_ptr, char* _start_ptr, unsigned int* err)
{
unsigned int i;
unsigned int* ptr = (unsigned int*) (_ptr + blockIdx.x*BLOCKSIZE);
unsigned int* start_ptr = (unsigned int*) _start_ptr;
if (ptr >= (unsigned int*) end_ptr) {
return;
}
for (i = 0;i < BLOCKSIZE/sizeof(unsigned int); i++){
ptr[i] = start_ptr[i];
}
return;
} | .text
.file "kernel_test7_write.hip"
.globl _Z33__device_stub__kernel_test7_writePcS_S_Pj # -- Begin function _Z33__device_stub__kernel_test7_writePcS_S_Pj
.p2align 4, 0x90
.type _Z33__device_stub__kernel_test7_writePcS_S_Pj,@function
_Z33__device_stub__kernel_test7_writePcS_S_Pj: # @_Z33__device_stub__kernel_test7_writePcS_S_Pj
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movq %rcx, 48(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rax
movq %rax, 104(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z18kernel_test7_writePcS_S_Pj, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z33__device_stub__kernel_test7_writePcS_S_Pj, .Lfunc_end0-_Z33__device_stub__kernel_test7_writePcS_S_Pj
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z18kernel_test7_writePcS_S_Pj, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z18kernel_test7_writePcS_S_Pj,@object # @_Z18kernel_test7_writePcS_S_Pj
.section .rodata,"a",@progbits
.globl _Z18kernel_test7_writePcS_S_Pj
.p2align 3, 0x0
_Z18kernel_test7_writePcS_S_Pj:
.quad _Z33__device_stub__kernel_test7_writePcS_S_Pj
.size _Z18kernel_test7_writePcS_S_Pj, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z18kernel_test7_writePcS_S_Pj"
.size .L__unnamed_1, 31
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z33__device_stub__kernel_test7_writePcS_S_Pj
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z18kernel_test7_writePcS_S_Pj
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z18kernel_test7_writePcS_S_Pj
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e240000002500 */
/*0020*/ LEA R0, P1, R0, c[0x0][0x160], 0x14 ; /* 0x0000580000007a11 */
/* 0x001fc8000782a0ff */
/*0030*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x168], PT ; /* 0x00005a0000007a0c */
/* 0x000fe20003f06070 */
/*0040*/ IMAD.X R13, RZ, RZ, c[0x0][0x164], P1 ; /* 0x00005900ff0d7624 */
/* 0x000fca00008e06ff */
/*0050*/ ISETP.GE.U32.AND.EX P0, PT, R13, c[0x0][0x16c], PT, P0 ; /* 0x00005b000d007a0c */
/* 0x000fda0003f06100 */
/*0060*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0070*/ IADD3 R8, P0, R0, 0x40, RZ ; /* 0x0000004000087810 */
/* 0x000fe20007f1e0ff */
/*0080*/ HFMA2.MMA R0, -RZ, RZ, 0, 0 ; /* 0x00000000ff007435 */
/* 0x000fe200000001ff */
/*0090*/ IMAD.MOV.U32 R6, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff067624 */
/* 0x000fe200078e00ff */
/*00a0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00b0*/ IMAD.MOV.U32 R11, RZ, RZ, c[0x0][0x174] ; /* 0x00005d00ff0b7624 */
/* 0x000fe400078e00ff */
/*00c0*/ IMAD.X R13, RZ, RZ, R13, P0 ; /* 0x000000ffff0d7224 */
/* 0x000fe400000e060d */
/*00d0*/ IMAD.MOV.U32 R2, RZ, RZ, R6 ; /* 0x000000ffff027224 */
/* 0x000fe200078e0006 */
/*00e0*/ MOV R3, R11 ; /* 0x0000000b00037202 */
/* 0x000fca0000000f00 */
/*00f0*/ LDG.E R7, [R2.64] ; /* 0x0000000402077981 */
/* 0x008ea2000c1e1900 */
/*0100*/ IMAD.MOV.U32 R4, RZ, RZ, R8 ; /* 0x000000ffff047224 */
/* 0x000fe400078e0008 */
/*0110*/ IMAD.MOV.U32 R5, RZ, RZ, R13 ; /* 0x000000ffff057224 */
/* 0x000fca00078e000d */
/*0120*/ STG.E [R4.64+-0x40], R7 ; /* 0xffffc00704007986 */
/* 0x0041e8000c101904 */
/*0130*/ LDG.E R9, [R2.64+0x4] ; /* 0x0000040402097981 */
/* 0x000ea8000c1e1900 */
/*0140*/ STG.E [R4.64+-0x3c], R9 ; /* 0xffffc40904007986 */
/* 0x0043e8000c101904 */
/*0150*/ LDG.E R11, [R2.64+0x8] ; /* 0x00000804020b7981 */
/* 0x000ea8000c1e1900 */
/*0160*/ STG.E [R4.64+-0x38], R11 ; /* 0xffffc80b04007986 */
/* 0x0045e8000c101904 */
/*0170*/ LDG.E R13, [R2.64+0xc] ; /* 0x00000c04020d7981 */
/* 0x000ee8000c1e1900 */
/*0180*/ STG.E [R4.64+-0x34], R13 ; /* 0xffffcc0d04007986 */
/* 0x0087e8000c101904 */
/*0190*/ LDG.E R15, [R2.64+0x10] ; /* 0x00001004020f7981 */
/* 0x000f28000c1e1900 */
/*01a0*/ STG.E [R4.64+-0x30], R15 ; /* 0xffffd00f04007986 */
/* 0x0109e8000c101904 */
/*01b0*/ LDG.E R17, [R2.64+0x14] ; /* 0x0000140402117981 */
/* 0x000f68000c1e1900 */
/*01c0*/ STG.E [R4.64+-0x2c], R17 ; /* 0xffffd41104007986 */
/* 0x020be8000c101904 */
/*01d0*/ LDG.E R7, [R2.64+0x18] ; /* 0x0000180402077981 */
/* 0x001ea8000c1e1900 */
/*01e0*/ STG.E [R4.64+-0x28], R7 ; /* 0xffffd80704007986 */
/* 0x0041e8000c101904 */
/*01f0*/ LDG.E R9, [R2.64+0x1c] ; /* 0x00001c0402097981 */
/* 0x002ea8000c1e1900 */
/*0200*/ STG.E [R4.64+-0x24], R9 ; /* 0xffffdc0904007986 */
/* 0x0043e8000c101904 */
/*0210*/ LDG.E R11, [R2.64+0x20] ; /* 0x00002004020b7981 */
/* 0x000ea8000c1e1900 */
/*0220*/ STG.E [R4.64+-0x20], R11 ; /* 0xffffe00b04007986 */
/* 0x0045e8000c101904 */
/*0230*/ LDG.E R13, [R2.64+0x24] ; /* 0x00002404020d7981 */
/* 0x008ee8000c1e1900 */
/*0240*/ STG.E [R4.64+-0x1c], R13 ; /* 0xffffe40d04007986 */
/* 0x0087e8000c101904 */
/*0250*/ LDG.E R15, [R2.64+0x28] ; /* 0x00002804020f7981 */
/* 0x010f28000c1e1900 */
/*0260*/ STG.E [R4.64+-0x18], R15 ; /* 0xffffe80f04007986 */
/* 0x0109e8000c101904 */
/*0270*/ LDG.E R17, [R2.64+0x2c] ; /* 0x00002c0402117981 */
/* 0x020f68000c1e1900 */
/*0280*/ STG.E [R4.64+-0x14], R17 ; /* 0xffffec1104007986 */
/* 0x020be8000c101904 */
/*0290*/ LDG.E R7, [R2.64+0x30] ; /* 0x0000300402077981 */
/* 0x001ea8000c1e1900 */
/*02a0*/ STG.E [R4.64+-0x10], R7 ; /* 0xfffff00704007986 */
/* 0x0041e8000c101904 */
/*02b0*/ LDG.E R9, [R2.64+0x34] ; /* 0x0000340402097981 */
/* 0x002ea8000c1e1900 */
/*02c0*/ STG.E [R4.64+-0xc], R9 ; /* 0xfffff40904007986 */
/* 0x0043e8000c101904 */
/*02d0*/ LDG.E R11, [R2.64+0x38] ; /* 0x00003804020b7981 */
/* 0x000ea8000c1e1900 */
/*02e0*/ STG.E [R4.64+-0x8], R11 ; /* 0xfffff80b04007986 */
/* 0x0045e8000c101904 */
/*02f0*/ LDG.E R13, [R2.64+0x3c] ; /* 0x00003c04020d7981 */
/* 0x008ee8000c1e1900 */
/*0300*/ STG.E [R4.64+-0x4], R13 ; /* 0xfffffc0d04007986 */
/* 0x0087e8000c101904 */
/*0310*/ LDG.E R15, [R2.64+0x40] ; /* 0x00004004020f7981 */
/* 0x010f28000c1e1900 */
/*0320*/ STG.E [R4.64], R15 ; /* 0x0000000f04007986 */
/* 0x0109e8000c101904 */
/*0330*/ LDG.E R17, [R2.64+0x44] ; /* 0x0000440402117981 */
/* 0x020f68000c1e1900 */
/*0340*/ STG.E [R4.64+0x4], R17 ; /* 0x0000041104007986 */
/* 0x020be8000c101904 */
/*0350*/ LDG.E R7, [R2.64+0x48] ; /* 0x0000480402077981 */
/* 0x001ea8000c1e1900 */
/*0360*/ STG.E [R4.64+0x8], R7 ; /* 0x0000080704007986 */
/* 0x0041e8000c101904 */
/*0370*/ LDG.E R9, [R2.64+0x4c] ; /* 0x00004c0402097981 */
/* 0x002ea8000c1e1900 */
/*0380*/ STG.E [R4.64+0xc], R9 ; /* 0x00000c0904007986 */
/* 0x0043e8000c101904 */
/*0390*/ LDG.E R11, [R2.64+0x50] ; /* 0x00005004020b7981 */
/* 0x000ea8000c1e1900 */
/*03a0*/ STG.E [R4.64+0x10], R11 ; /* 0x0000100b04007986 */
/* 0x0045e8000c101904 */
/*03b0*/ LDG.E R13, [R2.64+0x54] ; /* 0x00005404020d7981 */
/* 0x008ee8000c1e1900 */
/*03c0*/ STG.E [R4.64+0x14], R13 ; /* 0x0000140d04007986 */
/* 0x0087e8000c101904 */
/*03d0*/ LDG.E R15, [R2.64+0x58] ; /* 0x00005804020f7981 */
/* 0x010f28000c1e1900 */
/*03e0*/ STG.E [R4.64+0x18], R15 ; /* 0x0000180f04007986 */
/* 0x0109e8000c101904 */
/*03f0*/ LDG.E R17, [R2.64+0x5c] ; /* 0x00005c0402117981 */
/* 0x020f68000c1e1900 */
/*0400*/ STG.E [R4.64+0x1c], R17 ; /* 0x00001c1104007986 */
/* 0x020be8000c101904 */
/*0410*/ LDG.E R7, [R2.64+0x60] ; /* 0x0000600402077981 */
/* 0x001ea8000c1e1900 */
/*0420*/ STG.E [R4.64+0x20], R7 ; /* 0x0000200704007986 */
/* 0x0041e8000c101904 */
/*0430*/ LDG.E R9, [R2.64+0x64] ; /* 0x0000640402097981 */
/* 0x002ea8000c1e1900 */
/*0440*/ STG.E [R4.64+0x24], R9 ; /* 0x0000240904007986 */
/* 0x0043e8000c101904 */
/*0450*/ LDG.E R11, [R2.64+0x68] ; /* 0x00006804020b7981 */
/* 0x000ea8000c1e1900 */
/*0460*/ STG.E [R4.64+0x28], R11 ; /* 0x0000280b04007986 */
/* 0x004fe8000c101904 */
/*0470*/ LDG.E R13, [R2.64+0x6c] ; /* 0x00006c04020d7981 */
/* 0x008ea8000c1e1900 */
/*0480*/ STG.E [R4.64+0x2c], R13 ; /* 0x00002c0d04007986 */
/* 0x0045e8000c101904 */
/*0490*/ LDG.E R15, [R2.64+0x70] ; /* 0x00007004020f7981 */
/* 0x010ee8000c1e1900 */
/*04a0*/ STG.E [R4.64+0x30], R15 ; /* 0x0000300f04007986 */
/* 0x0087e8000c101904 */
/*04b0*/ LDG.E R17, [R2.64+0x74] ; /* 0x0000740402117981 */
/* 0x020f28000c1e1900 */
/*04c0*/ STG.E [R4.64+0x34], R17 ; /* 0x0000341104007986 */
/* 0x0107e8000c101904 */
/*04d0*/ LDG.E R7, [R2.64+0x78] ; /* 0x0000780402077981 */
/* 0x001f22000c1e1900 */
/*04e0*/ IADD3 R0, R0, 0x20, RZ ; /* 0x0000002000007810 */
/* 0x000fc80007ffe0ff */
/*04f0*/ ISETP.NE.AND P0, PT, R0, 0x40000, PT ; /* 0x000400000000780c */
/* 0x000fe20003f05270 */
/*0500*/ STG.E [R4.64+0x38], R7 ; /* 0x0000380704007986 */
/* 0x0107e8000c101904 */
/*0510*/ LDG.E R9, [R2.64+0x7c] ; /* 0x00007c0402097981 */
/* 0x002f22000c1e1900 */
/*0520*/ IADD3 R8, P2, R4, 0x80, RZ ; /* 0x0000008004087810 */
/* 0x000fe40007f5e0ff */
/*0530*/ IADD3 R6, P1, R2, 0x80, RZ ; /* 0x0000008002067810 */
/* 0x000fc60007f3e0ff */
/*0540*/ IMAD.X R13, RZ, RZ, R5, P2 ; /* 0x000000ffff0d7224 */
/* 0x004fe200010e0605 */
/*0550*/ IADD3.X R11, RZ, R3, RZ, P1, !PT ; /* 0x00000003ff0b7210 */
/* 0x000fe20000ffe4ff */
/*0560*/ STG.E [R4.64+0x3c], R9 ; /* 0x00003c0904007986 */
/* 0x0107e2000c101904 */
/*0570*/ @P0 BRA 0xd0 ; /* 0xfffffb5000000947 */
/* 0x000fea000383ffff */
/*0580*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0590*/ BRA 0x590; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*05a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0600*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0610*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0620*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0630*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0640*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0650*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0660*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0670*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z18kernel_test7_writePcS_S_Pj
.globl _Z18kernel_test7_writePcS_S_Pj
.p2align 8
.type _Z18kernel_test7_writePcS_S_Pj,@function
_Z18kernel_test7_writePcS_S_Pj:
s_load_b128 s[4:7], s[0:1], 0x0
s_lshl_b32 s2, s15, 20
s_waitcnt lgkmcnt(0)
s_add_u32 s2, s4, s2
s_addc_u32 s3, s5, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_ge_u64_e64 s4, s[2:3], s[6:7]
s_and_b32 vcc_lo, exec_lo, s4
s_cbranch_vccnz .LBB0_3
s_load_b64 s[0:1], s[0:1], 0x10
v_mov_b32_e32 v0, 0
s_mov_b64 s[4:5], 0
.LBB0_2:
s_waitcnt lgkmcnt(0)
s_add_u32 s6, s0, s4
s_addc_u32 s7, s1, s5
global_load_b32 v1, v0, s[6:7]
s_add_u32 s6, s2, s4
s_addc_u32 s7, s3, s5
s_add_u32 s4, s4, 4
s_addc_u32 s5, s5, 0
s_cmp_lg_u32 s4, 0x100000
s_waitcnt vmcnt(0)
global_store_b32 v0, v1, s[6:7]
s_cbranch_scc1 .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z18kernel_test7_writePcS_S_Pj
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 32
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z18kernel_test7_writePcS_S_Pj, .Lfunc_end0-_Z18kernel_test7_writePcS_S_Pj
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 32
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z18kernel_test7_writePcS_S_Pj
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z18kernel_test7_writePcS_S_Pj.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000b1424_00000000-6_kernel_test7_write.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z44__device_stub__Z18kernel_test7_writePcS_S_PjPcS_S_Pj
.type _Z44__device_stub__Z18kernel_test7_writePcS_S_PjPcS_S_Pj, @function
_Z44__device_stub__Z18kernel_test7_writePcS_S_PjPcS_S_Pj:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z18kernel_test7_writePcS_S_Pj(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z44__device_stub__Z18kernel_test7_writePcS_S_PjPcS_S_Pj, .-_Z44__device_stub__Z18kernel_test7_writePcS_S_PjPcS_S_Pj
.globl _Z18kernel_test7_writePcS_S_Pj
.type _Z18kernel_test7_writePcS_S_Pj, @function
_Z18kernel_test7_writePcS_S_Pj:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z44__device_stub__Z18kernel_test7_writePcS_S_PjPcS_S_Pj
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z18kernel_test7_writePcS_S_Pj, .-_Z18kernel_test7_writePcS_S_Pj
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z18kernel_test7_writePcS_S_Pj"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z18kernel_test7_writePcS_S_Pj(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "kernel_test7_write.hip"
.globl _Z33__device_stub__kernel_test7_writePcS_S_Pj # -- Begin function _Z33__device_stub__kernel_test7_writePcS_S_Pj
.p2align 4, 0x90
.type _Z33__device_stub__kernel_test7_writePcS_S_Pj,@function
_Z33__device_stub__kernel_test7_writePcS_S_Pj: # @_Z33__device_stub__kernel_test7_writePcS_S_Pj
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movq %rcx, 48(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rax
movq %rax, 104(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z18kernel_test7_writePcS_S_Pj, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z33__device_stub__kernel_test7_writePcS_S_Pj, .Lfunc_end0-_Z33__device_stub__kernel_test7_writePcS_S_Pj
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z18kernel_test7_writePcS_S_Pj, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z18kernel_test7_writePcS_S_Pj,@object # @_Z18kernel_test7_writePcS_S_Pj
.section .rodata,"a",@progbits
.globl _Z18kernel_test7_writePcS_S_Pj
.p2align 3, 0x0
_Z18kernel_test7_writePcS_S_Pj:
.quad _Z33__device_stub__kernel_test7_writePcS_S_Pj
.size _Z18kernel_test7_writePcS_S_Pj, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z18kernel_test7_writePcS_S_Pj"
.size .L__unnamed_1, 31
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z33__device_stub__kernel_test7_writePcS_S_Pj
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z18kernel_test7_writePcS_S_Pj
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <assert.h>
#include <stdlib.h>
#include <stdio.h>
#include <cuda.h>
#include <time.h>
struct BITMAPFILEHEADER
{
char bfType[2];
int bfSize;
int bfReserved;
int bfOffBits;
};
struct BITMAPINFOHEADER {
int biSize;
int biWidth;
int biHeight;
short biPlanes;
short biBitCount;
int biCompression;
int biSizeImage;
int biXPelsPerMeter;
int biYPelsPerMeter;
int biClrUsed;
int biClrImportant;
};
int write_bitmap(const char *filename, int width, int height, char *red, char *green, char *blue)
{
int bytes_per_line = (3 * (width + 1) / 4) * 4;
unsigned char *image_line = (unsigned char *)malloc(bytes_per_line);
struct BITMAPFILEHEADER bmph;
bmph.bfType[0] = 'B';
bmph.bfType[1] = 'M';
bmph.bfReserved = 0;
bmph.bfOffBits = 54;
bmph.bfSize = bmph.bfOffBits + bytes_per_line * height;
struct BITMAPINFOHEADER bmih;
bmih.biSize = 40;
bmih.biWidth = width;
bmih.biHeight = height;
bmih.biPlanes = 1;
bmih.biBitCount = 24;
bmih.biCompression = 0;
bmih.biSizeImage = bytes_per_line * height;
bmih.biXPelsPerMeter = 0;
bmih.biYPelsPerMeter = 0;
bmih.biClrUsed = 0;
bmih.biClrImportant = 0;
FILE *fit;
if((fit = fopen (filename, "wb"))==0) {
free(image_line);
return -1;
}
fwrite(&bmph.bfType, 2, 1, fit);
fwrite(&bmph.bfSize, 4, 1, fit);
fwrite(&bmph.bfReserved, 4, 1, fit);
fwrite(&bmph.bfOffBits, 4, 1, fit);
fwrite(&bmih.biSize, 4, 1, fit);
fwrite(&bmih.biWidth, 4, 1, fit);
fwrite(&bmih.biHeight, 4, 1, fit);
fwrite(&bmih.biPlanes, 2, 1, fit);
fwrite(&bmih.biBitCount, 2, 1, fit);
fwrite(&bmih.biCompression, 4, 1, fit);
fwrite(&bmih.biSizeImage, 4, 1, fit);
fwrite(&bmih.biXPelsPerMeter, 4, 1, fit);
fwrite(&bmih.biYPelsPerMeter, 4, 1, fit);
fwrite(&bmih.biClrUsed, 4, 1, fit);
fwrite(&bmih.biClrImportant, 4, 1, fit);
for(int i=height-1;i>=0;i--) {
for (int j=0;j<width;j++) {
int pos = (width * i + j);
image_line[3*j] = blue[pos];
image_line[3*j+1] = green[pos];
image_line[3*j+2] = red[pos];
}
fwrite((void *)image_line, bytes_per_line, 1, fit);
}
free(image_line);
fclose(fit);
return 0;
}
void mandel_host(char *red, char *green, char *blue, int width, int height)
{
for(int pos_x=0;pos_x<width;pos_x++) {
for(int pos_y=0;pos_y<height;pos_y++) {
float x0 = ((float)pos_x)*3.5/((float)width)-2.5;
float y0 = ((float)pos_y)*2.0/((float)height)-1.0;
float x = 0.0;
float y = 0.0;
int iteration = 0;
int max_iteration = 256;
while(x*x + y*y <= 4 && iteration < max_iteration) {
float xtemp = x*x - y*y + x0;
y = 2*x*y + y0;
x = xtemp;
iteration++;
}
int index = width*pos_y + pos_x;
if(iteration==max_iteration) {
iteration = 0;
}
red[index] = iteration;
green[index] = iteration;
blue[index] = iteration;
}
}
}
__global__ void mandel_cuda(char *red, char *green, char *blue, int width, int height)
{
/* kernel que calcula un pixel */
/* Per saber quin pixel és, cal tenir en compte totes les dimensions
del grid (el número de blocs i el número de threads */
/* Podeu fer servir els valors de
blockIdx.x, blockIdx.y
gridDim.x, gridDim.y
threadIdx.x, threadIdx.y
blockDim.x, blockDim.y */
int pos_x = threadIdx.x+blockDim.x*blockIdx.x;
int pos_y = threadIdx.y+blockDim.y*blockIdx.y;
float x0 = ((float)pos_x)*3.5/((float)width)-2.5;
float y0 = ((float)pos_y)*2.0/((float)height)-1.0;
float x = 0.0;
float y = 0.0;
int iteration = 0;
int max_iteration = 256;
while(x*x + y*y <= 4 && iteration < max_iteration) {
float xtemp = x*x - y*y + x0;
y = 2*x*y + y0;
x = xtemp;
iteration++;
}
int index = width*pos_y + pos_x;
if(iteration==max_iteration) {
iteration = 0;
}
red[index] = iteration;
green[index] = iteration;
blue[index] = iteration;
}
void fes_host(int width, int height)
{
size_t buffer_size = sizeof(char) * width * height;
char *image_red = (char *)malloc(buffer_size);
char *image_green = (char *)malloc(buffer_size);
char *image_blue = (char *)malloc(buffer_size);
mandel_host(image_red, image_green, image_blue, width, height);
// Now write the file
write_bitmap("output_host.bmp", width, height, image_red,
image_green, image_blue);
free(image_red);
free(image_green);
free(image_blue);
}
void fes_cuda(int width, int height)
{
size_t buffer_size = sizeof(char) * width * height;
char *image_red;
char *image_green;
char *image_blue;
cudaMalloc((void**)&image_red, buffer_size);
cudaMalloc((void**)&image_green, buffer_size);
cudaMalloc((void**)&image_blue, buffer_size);
clock_t t_device = clock();
dim3 blockDim(6, 6,1);
dim3 gridDim(width / blockDim.x, height / blockDim.y,1);
mandel_cuda<<< gridDim, blockDim,0>>>(image_red, image_green, image_blue, width, height);
char *host_image_red = (char*)malloc(buffer_size);
char *host_image_green= (char*)malloc(buffer_size);
char *host_image_blue= (char*)malloc(buffer_size);
/* cal copiar els valors de la imatge al host */
cudaMemcpy(host_image_red,image_red,buffer_size,cudaMemcpyDeviceToHost);
cudaMemcpy(host_image_green,image_green,buffer_size,cudaMemcpyDeviceToHost);
cudaMemcpy(host_image_blue,image_blue,buffer_size,cudaMemcpyDeviceToHost);
// Now write the file
write_bitmap("output_cuda.bmp", width, height, host_image_red,
host_image_green, host_image_blue);
t_device = clock() - t_device;
double time_taken_device = ((double)t_device)/CLOCKS_PER_SEC;
printf("GPU %f segons with %d threats \n", time_taken_device,blockDim.x);
/* cal alliberar la memòria del dispositiu i del host */
cudaFree(image_blue);
cudaFree(image_green);
cudaFree(image_red);
free(host_image_blue);
free(host_image_green);
free(host_image_red);
}
unsigned char* readBMP(const char* filename)
{
int i;
FILE* f = fopen(filename, "rb");
unsigned char info[54];
fread(info, sizeof(unsigned char), 54, f); // read the 54-byte header
// extract image height and width from header
int width = *(int*)&info[18];
int height = *(int*)&info[22];
int size = 3 * width * height;
unsigned char* data = new unsigned char[size]; // allocate 3 bytes per pixel
fread(data, sizeof(unsigned char), size, f); // read the rest of the data at once
fclose(f);
for(i = 0; i < size; i += 3)
{
unsigned char tmp = data[i];
data[i] = data[i+2];
data[i+2] = tmp;
}
return data;
}
int main(int argc, const char * argv[]) {
fes_cuda(5120, 5120);
fes_host(5120, 5120);
unsigned char *c , *h;
c = readBMP("output_cuda.bmp");
h = readBMP("output_host.bmp");
int errors =0;
int lengc = 5120*5120;
for(int i = 0 ; i < lengc;++i){
if(c[i] != h[i]){
errors++;
}
}
if(errors)printf("There are no difference,have %d errors\n",errors);
else printf("There are no difference\n");
return 0;
} | code for sm_80
Function : _Z11mandel_cudaPcS_S_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ I2F R2, c[0x0][0x178] ; /* 0x00005e0000027b06 */
/* 0x000e220000201400 */
/*0020*/ S2R R11, SR_CTAID.X ; /* 0x00000000000b7919 */
/* 0x000e620000002500 */
/*0030*/ IMAD.MOV.U32 R6, RZ, RZ, 0x1 ; /* 0x00000001ff067424 */
/* 0x000fe200078e00ff */
/*0040*/ BSSY B0, 0x200 ; /* 0x000001b000007945 */
/* 0x000fe40003800000 */
/*0050*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e680000002100 */
/*0060*/ S2R R10, SR_CTAID.Y ; /* 0x00000000000a7919 */
/* 0x000ea80000002600 */
/*0070*/ S2R R15, SR_TID.Y ; /* 0x00000000000f7919 */
/* 0x000ea20000002200 */
/*0080*/ F2F.F64.F32 R2, R2 ; /* 0x0000000200027310 */
/* 0x001e220000201800 */
/*0090*/ IMAD R11, R11, c[0x0][0x0], R0 ; /* 0x000000000b0b7a24 */
/* 0x002fce00078e0200 */
/*00a0*/ MUFU.RCP64H R7, R3 ; /* 0x0000000300077308 */
/* 0x001e300000001800 */
/*00b0*/ I2F R0, R11 ; /* 0x0000000b00007306 */
/* 0x000e620000201400 */
/*00c0*/ DFMA R4, -R2, R6, 1 ; /* 0x3ff000000204742b */
/* 0x001e0c0000000106 */
/*00d0*/ DFMA R8, R4, R4, R4 ; /* 0x000000040408722b */
/* 0x0012080000000004 */
/*00e0*/ F2F.F64.F32 R4, R0 ; /* 0x0000000000047310 */
/* 0x0024640000201800 */
/*00f0*/ DFMA R8, R6, R8, R6 ; /* 0x000000080608722b */
/* 0x001e0c0000000006 */
/*0100*/ DFMA R12, -R2, R8, 1 ; /* 0x3ff00000020c742b */
/* 0x001e220000000108 */
/*0110*/ IMAD R0, R10, c[0x0][0x4], R15 ; /* 0x000001000a007a24 */
/* 0x004fca00078e020f */
/*0120*/ DFMA R12, R8, R12, R8 ; /* 0x0000000c080c722b */
/* 0x001fc80000000008 */
/*0130*/ DMUL R6, R4, 3.5 ; /* 0x400c000004067828 */
/* 0x002e0c0000000000 */
/*0140*/ DMUL R4, R6, R12 ; /* 0x0000000c06047228 */
/* 0x001e080000000000 */
/*0150*/ FSETP.GEU.AND P1, PT, |R7|, 6.5827683646048100446e-37, PT ; /* 0x036000000700780b */
/* 0x000fe40003f2e200 */
/*0160*/ DFMA R8, -R2, R4, R6 ; /* 0x000000040208722b */
/* 0x001e0c0000000106 */
/*0170*/ DFMA R4, R12, R8, R4 ; /* 0x000000080c04722b */
/* 0x001e140000000004 */
/*0180*/ FFMA R8, RZ, R3, R5 ; /* 0x00000003ff087223 */
/* 0x001fca0000000005 */
/*0190*/ FSETP.GT.AND P0, PT, |R8|, 1.469367938527859385e-39, PT ; /* 0x001000000800780b */
/* 0x000fda0003f04200 */
/*01a0*/ @P0 BRA P1, 0x1f0 ; /* 0x0000004000000947 */
/* 0x000fea0000800000 */
/*01b0*/ IMAD.MOV.U32 R8, RZ, RZ, R6 ; /* 0x000000ffff087224 */
/* 0x000fe200078e0006 */
/*01c0*/ MOV R12, 0x1f0 ; /* 0x000001f0000c7802 */
/* 0x000fe20000000f00 */
/*01d0*/ IMAD.MOV.U32 R9, RZ, RZ, R7 ; /* 0x000000ffff097224 */
/* 0x000fe400078e0007 */
/*01e0*/ CALL.REL.NOINC 0x5e0 ; /* 0x000003f000007944 */
/* 0x000fea0003c00000 */
/*01f0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0200*/ I2F R2, c[0x0][0x17c] ; /* 0x00005f0000027b06 */
/* 0x000e220000201400 */
/*0210*/ IMAD.MOV.U32 R8, RZ, RZ, 0x1 ; /* 0x00000001ff087424 */
/* 0x000fe200078e00ff */
/*0220*/ DADD R4, R4, -2.5 ; /* 0xc004000004047429 */
/* 0x000ea20000000000 */
/*0230*/ BSSY B0, 0x3d0 ; /* 0x0000019000007945 */
/* 0x000fea0003800000 */
/*0240*/ I2F R16, R0 ; /* 0x0000000000107306 */
/* 0x002ff00000201400 */
/*0250*/ F2F.F64.F32 R2, R2 ; /* 0x0000000200027310 */
/* 0x001e300000201800 */
/*0260*/ F2F.F32.F64 R10, R4 ; /* 0x00000004000a7310 */
/* 0x004ff00000301000 */
/*0270*/ MUFU.RCP64H R9, R3 ; /* 0x0000000300097308 */
/* 0x001e240000001800 */
/*0280*/ DFMA R6, -R2, R8, 1 ; /* 0x3ff000000206742b */
/* 0x001e0c0000000108 */
/*0290*/ DFMA R12, R6, R6, R6 ; /* 0x00000006060c722b */
/* 0x0010480000000006 */
/*02a0*/ F2F.F64.F32 R6, R16 ; /* 0x0000001000067310 */
/* 0x001e240000201800 */
/*02b0*/ DFMA R12, R8, R12, R8 ; /* 0x0000000c080c722b */
/* 0x002e4c0000000008 */
/*02c0*/ DFMA R8, -R2, R12, 1 ; /* 0x3ff000000208742b */
/* 0x002e4c000000010c */
/*02d0*/ DFMA R8, R12, R8, R12 ; /* 0x000000080c08722b */
/* 0x002fc8000000000c */
/*02e0*/ DADD R6, R6, R6 ; /* 0x0000000006067229 */
/* 0x001e0c0000000006 */
/*02f0*/ DMUL R12, R6, R8 ; /* 0x00000008060c7228 */
/* 0x001e080000000000 */
/*0300*/ FSETP.GEU.AND P1, PT, |R7|, 6.5827683646048100446e-37, PT ; /* 0x036000000700780b */
/* 0x000fe40003f2e200 */
/*0310*/ DFMA R14, -R2, R12, R6 ; /* 0x0000000c020e722b */
/* 0x001e0c0000000106 */
/*0320*/ DFMA R8, R8, R14, R12 ; /* 0x0000000e0808722b */
/* 0x001e14000000000c */
/*0330*/ FFMA R12, RZ, R3, R9 ; /* 0x00000003ff0c7223 */
/* 0x001fca0000000009 */
/*0340*/ FSETP.GT.AND P0, PT, |R12|, 1.469367938527859385e-39, PT ; /* 0x001000000c00780b */
/* 0x000fda0003f04200 */
/*0350*/ @P0 BRA P1, 0x3c0 ; /* 0x0000006000000947 */
/* 0x000fea0000800000 */
/*0360*/ IMAD.MOV.U32 R8, RZ, RZ, R6 ; /* 0x000000ffff087224 */
/* 0x000fe200078e0006 */
/*0370*/ MOV R12, 0x3a0 ; /* 0x000003a0000c7802 */
/* 0x000fe20000000f00 */
/*0380*/ IMAD.MOV.U32 R9, RZ, RZ, R7 ; /* 0x000000ffff097224 */
/* 0x000fe400078e0007 */
/*0390*/ CALL.REL.NOINC 0x5e0 ; /* 0x0000024000007944 */
/* 0x000fea0003c00000 */
/*03a0*/ IMAD.MOV.U32 R8, RZ, RZ, R4 ; /* 0x000000ffff087224 */
/* 0x000fe400078e0004 */
/*03b0*/ IMAD.MOV.U32 R9, RZ, RZ, R5 ; /* 0x000000ffff097224 */
/* 0x000fe400078e0005 */
/*03c0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*03d0*/ DADD R8, R8, -1 ; /* 0xbff0000008087429 */
/* 0x000e220000000000 */
/*03e0*/ BSSY B0, 0x500 ; /* 0x0000011000007945 */
/* 0x000fe20003800000 */
/*03f0*/ CS2R R2, SRZ ; /* 0x0000000000027805 */
/* 0x000fe2000001ff00 */
/*0400*/ IMAD.MOV.U32 R12, RZ, RZ, RZ ; /* 0x000000ffff0c7224 */
/* 0x000fe200078e00ff */
/*0410*/ CS2R R4, SRZ ; /* 0x0000000000047805 */
/* 0x000fe2000001ff00 */
/*0420*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fca0000000a00 */
/*0430*/ F2F.F32.F64 R8, R8 ; /* 0x0000000800087310 */
/* 0x0010a40000301000 */
/*0440*/ FADD R3, R3, -R2 ; /* 0x8000000203037221 */
/* 0x000fe20000000000 */
/*0450*/ IADD3 R12, R12, 0x1, RZ ; /* 0x000000010c0c7810 */
/* 0x000fe20007ffe0ff */
/*0460*/ FADD R7, R5, R5 ; /* 0x0000000505077221 */
/* 0x000fe40000000000 */
/*0470*/ FADD R5, R10, R3 ; /* 0x000000030a057221 */
/* 0x000fe20000000000 */
/*0480*/ ISETP.GE.U32.AND P0, PT, R12, 0x100, PT ; /* 0x000001000c00780c */
/* 0x000fe20003f06070 */
/*0490*/ FFMA R4, R7, R4, R8 ; /* 0x0000000407047223 */
/* 0x004fe40000000008 */
/*04a0*/ FMUL R3, R5, R5 ; /* 0x0000000505037220 */
/* 0x000fe40000400000 */
/*04b0*/ FMUL R2, R4, R4 ; /* 0x0000000404027220 */
/* 0x000fc80000400000 */
/*04c0*/ FADD R6, R3, R2 ; /* 0x0000000203067221 */
/* 0x000fca0000000000 */
/*04d0*/ FSETP.LE.AND P1, PT, R6, 4, PT ; /* 0x408000000600780b */
/* 0x000fda0003f23000 */
/*04e0*/ @!P0 BRA P1, 0x440 ; /* 0xffffff5000008947 */
/* 0x000fea000083ffff */
/*04f0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0500*/ IMAD R0, R0, c[0x0][0x178], R11 ; /* 0x00005e0000007a24 */
/* 0x000fe200078e020b */
/*0510*/ ISETP.NE.AND P0, PT, R12, 0x100, PT ; /* 0x000001000c00780c */
/* 0x000fc80003f05270 */
/*0520*/ SHF.R.S32.HI R7, RZ, 0x1f, R0 ; /* 0x0000001fff077819 */
/* 0x000fe40000011400 */
/*0530*/ IADD3 R2, P1, R0.reuse, c[0x0][0x160], RZ ; /* 0x0000580000027a10 */
/* 0x040fe40007f3e0ff */
/*0540*/ IADD3 R4, P2, R0.reuse, c[0x0][0x168], RZ ; /* 0x00005a0000047a10 */
/* 0x040fe40007f5e0ff */
/*0550*/ IADD3 R6, P3, R0, c[0x0][0x170], RZ ; /* 0x00005c0000067a10 */
/* 0x000fe40007f7e0ff */
/*0560*/ IADD3.X R3, R7, c[0x0][0x164], RZ, P1, !PT ; /* 0x0000590007037a10 */
/* 0x000fe40000ffe4ff */
/*0570*/ SEL R9, R12, RZ, P0 ; /* 0x000000ff0c097207 */
/* 0x001fc40000000000 */
/*0580*/ IADD3.X R5, R7.reuse, c[0x0][0x16c], RZ, P2, !PT ; /* 0x00005b0007057a10 */
/* 0x040fe400017fe4ff */
/*0590*/ IADD3.X R7, R7, c[0x0][0x174], RZ, P3, !PT ; /* 0x00005d0007077a10 */
/* 0x000fe20001ffe4ff */
/*05a0*/ STG.E.U8 [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x000fe8000c101104 */
/*05b0*/ STG.E.U8 [R4.64], R9 ; /* 0x0000000904007986 */
/* 0x000fe8000c101104 */
/*05c0*/ STG.E.U8 [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101104 */
/*05d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*05e0*/ FSETP.GEU.AND P0, PT, |R3|.reuse, 1.469367938527859385e-39, PT ; /* 0x001000000300780b */
/* 0x040fe20003f0e200 */
/*05f0*/ IMAD.MOV.U32 R6, RZ, RZ, R2.reuse ; /* 0x000000ffff067224 */
/* 0x100fe200078e0002 */
/*0600*/ LOP3.LUT R4, R3, 0x800fffff, RZ, 0xc0, !PT ; /* 0x800fffff03047812 */
/* 0x000fe200078ec0ff */
/*0610*/ IMAD.MOV.U32 R7, RZ, RZ, R3 ; /* 0x000000ffff077224 */
/* 0x000fe200078e0003 */
/*0620*/ FSETP.GEU.AND P2, PT, |R9|.reuse, 1.469367938527859385e-39, PT ; /* 0x001000000900780b */
/* 0x040fe20003f4e200 */
/*0630*/ IMAD.MOV.U32 R14, RZ, RZ, 0x1ca00000 ; /* 0x1ca00000ff0e7424 */
/* 0x000fe200078e00ff */
/*0640*/ LOP3.LUT R5, R4, 0x3ff00000, RZ, 0xfc, !PT ; /* 0x3ff0000004057812 */
/* 0x000fe200078efcff */
/*0650*/ IMAD.MOV.U32 R4, RZ, RZ, R2 ; /* 0x000000ffff047224 */
/* 0x000fe200078e0002 */
/*0660*/ LOP3.LUT R13, R9, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff00000090d7812 */
/* 0x000fe200078ec0ff */
/*0670*/ IMAD.MOV.U32 R18, RZ, RZ, 0x1 ; /* 0x00000001ff127424 */
/* 0x000fe200078e00ff */
/*0680*/ LOP3.LUT R20, R3, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff0000003147812 */
/* 0x000fe200078ec0ff */
/*0690*/ BSSY B1, 0xba0 ; /* 0x0000050000017945 */
/* 0x000fe40003800000 */
/*06a0*/ @!P0 DMUL R4, R6, 8.98846567431157953865e+307 ; /* 0x7fe0000006048828 */
/* 0x000e220000000000 */
/*06b0*/ ISETP.GE.U32.AND P1, PT, R13, R20, PT ; /* 0x000000140d00720c */
/* 0x000fc60003f26070 */
/*06c0*/ @!P2 LOP3.LUT R2, R7, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff000000702a812 */
/* 0x000fe200078ec0ff */
/*06d0*/ @!P2 IMAD.MOV.U32 R16, RZ, RZ, RZ ; /* 0x000000ffff10a224 */
/* 0x000fe200078e00ff */
/*06e0*/ MUFU.RCP64H R19, R5 ; /* 0x0000000500137308 */
/* 0x001e220000001800 */
/*06f0*/ SEL R3, R14.reuse, 0x63400000, !P1 ; /* 0x634000000e037807 */
/* 0x040fe40004800000 */
/*0700*/ @!P2 ISETP.GE.U32.AND P3, PT, R13, R2, PT ; /* 0x000000020d00a20c */
/* 0x000fe20003f66070 */
/*0710*/ IMAD.MOV.U32 R2, RZ, RZ, R8 ; /* 0x000000ffff027224 */
/* 0x000fe200078e0008 */
/*0720*/ LOP3.LUT R3, R3, 0x800fffff, R9, 0xf8, !PT ; /* 0x800fffff03037812 */
/* 0x000fe400078ef809 */
/*0730*/ @!P2 SEL R15, R14, 0x63400000, !P3 ; /* 0x634000000e0fa807 */
/* 0x000fc80005800000 */
/*0740*/ @!P2 LOP3.LUT R15, R15, 0x80000000, R9, 0xf8, !PT ; /* 0x800000000f0fa812 */
/* 0x000fc800078ef809 */
/*0750*/ @!P2 LOP3.LUT R17, R15, 0x100000, RZ, 0xfc, !PT ; /* 0x001000000f11a812 */
/* 0x000fe200078efcff */
/*0760*/ DFMA R22, R18, -R4, 1 ; /* 0x3ff000001216742b */
/* 0x001e220000000804 */
/*0770*/ IMAD.MOV.U32 R15, RZ, RZ, R13 ; /* 0x000000ffff0f7224 */
/* 0x000fc800078e000d */
/*0780*/ @!P2 DFMA R2, R2, 2, -R16 ; /* 0x400000000202a82b */
/* 0x000fc80000000810 */
/*0790*/ DFMA R22, R22, R22, R22 ; /* 0x000000161616722b */
/* 0x001e0c0000000016 */
/*07a0*/ DFMA R18, R18, R22, R18 ; /* 0x000000161212722b */
/* 0x0010620000000012 */
/*07b0*/ @!P2 LOP3.LUT R15, R3, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff00000030fa812 */
/* 0x000fe200078ec0ff */
/*07c0*/ IMAD.MOV.U32 R22, RZ, RZ, R20 ; /* 0x000000ffff167224 */
/* 0x001fe200078e0014 */
/*07d0*/ @!P0 LOP3.LUT R22, R5, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff0000005168812 */
/* 0x000fe400078ec0ff */
/*07e0*/ IADD3 R20, R15, -0x1, RZ ; /* 0xffffffff0f147810 */
/* 0x000fe20007ffe0ff */
/*07f0*/ DFMA R16, R18, -R4, 1 ; /* 0x3ff000001210742b */
/* 0x002e220000000804 */
/*0800*/ IADD3 R23, R22, -0x1, RZ ; /* 0xffffffff16177810 */
/* 0x000fe40007ffe0ff */
/*0810*/ ISETP.GT.U32.AND P0, PT, R20, 0x7feffffe, PT ; /* 0x7feffffe1400780c */
/* 0x000fc60003f04070 */
/*0820*/ DFMA R16, R18, R16, R18 ; /* 0x000000101210722b */
/* 0x001e220000000012 */
/*0830*/ ISETP.GT.U32.OR P0, PT, R23, 0x7feffffe, P0 ; /* 0x7feffffe1700780c */
/* 0x000fca0000704470 */
/*0840*/ DMUL R18, R16, R2 ; /* 0x0000000210127228 */
/* 0x001e0c0000000000 */
/*0850*/ DFMA R20, R18, -R4, R2 ; /* 0x800000041214722b */
/* 0x001e0c0000000002 */
/*0860*/ DFMA R16, R16, R20, R18 ; /* 0x000000141010722b */
/* 0x0010620000000012 */
/*0870*/ @P0 BRA 0xa40 ; /* 0x000001c000000947 */
/* 0x000fea0003800000 */
/*0880*/ LOP3.LUT R18, R7, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff0000007127812 */
/* 0x001fc800078ec0ff */
/*0890*/ ISETP.GE.U32.AND P0, PT, R13.reuse, R18, PT ; /* 0x000000120d00720c */
/* 0x040fe20003f06070 */
/*08a0*/ IMAD.IADD R8, R13, 0x1, -R18 ; /* 0x000000010d087824 */
/* 0x000fc600078e0a12 */
/*08b0*/ SEL R13, R14, 0x63400000, !P0 ; /* 0x634000000e0d7807 */
/* 0x000fe40004000000 */
/*08c0*/ IMNMX R8, R8, -0x46a00000, !PT ; /* 0xb960000008087817 */
/* 0x000fc80007800200 */
/*08d0*/ IMNMX R8, R8, 0x46a00000, PT ; /* 0x46a0000008087817 */
/* 0x000fca0003800200 */
/*08e0*/ IMAD.IADD R13, R8, 0x1, -R13 ; /* 0x00000001080d7824 */
/* 0x000fe400078e0a0d */
/*08f0*/ IMAD.MOV.U32 R8, RZ, RZ, RZ ; /* 0x000000ffff087224 */
/* 0x000fc600078e00ff */
/*0900*/ IADD3 R9, R13, 0x7fe00000, RZ ; /* 0x7fe000000d097810 */
/* 0x000fcc0007ffe0ff */
/*0910*/ DMUL R18, R16, R8 ; /* 0x0000000810127228 */
/* 0x002e140000000000 */
/*0920*/ FSETP.GTU.AND P0, PT, |R19|, 1.469367938527859385e-39, PT ; /* 0x001000001300780b */
/* 0x001fda0003f0c200 */
/*0930*/ @P0 BRA 0xb90 ; /* 0x0000025000000947 */
/* 0x000fea0003800000 */
/*0940*/ DFMA R2, R16, -R4, R2 ; /* 0x800000041002722b */
/* 0x000e220000000002 */
/*0950*/ IMAD.MOV.U32 R8, RZ, RZ, RZ ; /* 0x000000ffff087224 */
/* 0x000fd200078e00ff */
/*0960*/ FSETP.NEU.AND P0, PT, R3.reuse, RZ, PT ; /* 0x000000ff0300720b */
/* 0x041fe40003f0d000 */
/*0970*/ LOP3.LUT R7, R3, 0x80000000, R7, 0x48, !PT ; /* 0x8000000003077812 */
/* 0x000fc800078e4807 */
/*0980*/ LOP3.LUT R9, R7, R9, RZ, 0xfc, !PT ; /* 0x0000000907097212 */
/* 0x000fce00078efcff */
/*0990*/ @!P0 BRA 0xb90 ; /* 0x000001f000008947 */
/* 0x000fea0003800000 */
/*09a0*/ IMAD.MOV R3, RZ, RZ, -R13 ; /* 0x000000ffff037224 */
/* 0x000fe200078e0a0d */
/*09b0*/ DMUL.RP R8, R16, R8 ; /* 0x0000000810087228 */
/* 0x000e220000008000 */
/*09c0*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x000fcc00078e00ff */
/*09d0*/ DFMA R2, R18, -R2, R16 ; /* 0x800000021202722b */
/* 0x000e460000000010 */
/*09e0*/ LOP3.LUT R7, R9, R7, RZ, 0x3c, !PT ; /* 0x0000000709077212 */
/* 0x001fc600078e3cff */
/*09f0*/ IADD3 R2, -R13, -0x43300000, RZ ; /* 0xbcd000000d027810 */
/* 0x002fc80007ffe1ff */
/*0a00*/ FSETP.NEU.AND P0, PT, |R3|, R2, PT ; /* 0x000000020300720b */
/* 0x000fc80003f0d200 */
/*0a10*/ FSEL R18, R8, R18, !P0 ; /* 0x0000001208127208 */
/* 0x000fe40004000000 */
/*0a20*/ FSEL R19, R7, R19, !P0 ; /* 0x0000001307137208 */
/* 0x000fe20004000000 */
/*0a30*/ BRA 0xb90 ; /* 0x0000015000007947 */
/* 0x000fea0003800000 */
/*0a40*/ DSETP.NAN.AND P0, PT, R8, R8, PT ; /* 0x000000080800722a */
/* 0x000e9c0003f08000 */
/*0a50*/ @P0 BRA 0xb70 ; /* 0x0000011000000947 */
/* 0x004fea0003800000 */
/*0a60*/ DSETP.NAN.AND P0, PT, R6, R6, PT ; /* 0x000000060600722a */
/* 0x000e9c0003f08000 */
/*0a70*/ @P0 BRA 0xb40 ; /* 0x000000c000000947 */
/* 0x004fea0003800000 */
/*0a80*/ ISETP.NE.AND P0, PT, R15, R22, PT ; /* 0x000000160f00720c */
/* 0x000fe20003f05270 */
/*0a90*/ IMAD.MOV.U32 R18, RZ, RZ, 0x0 ; /* 0x00000000ff127424 */
/* 0x001fe400078e00ff */
/*0aa0*/ IMAD.MOV.U32 R19, RZ, RZ, -0x80000 ; /* 0xfff80000ff137424 */
/* 0x000fd400078e00ff */
/*0ab0*/ @!P0 BRA 0xb90 ; /* 0x000000d000008947 */
/* 0x000fea0003800000 */
/*0ac0*/ ISETP.NE.AND P0, PT, R15, 0x7ff00000, PT ; /* 0x7ff000000f00780c */
/* 0x000fe40003f05270 */
/*0ad0*/ LOP3.LUT R19, R9, 0x80000000, R7, 0x48, !PT ; /* 0x8000000009137812 */
/* 0x000fe400078e4807 */
/*0ae0*/ ISETP.EQ.OR P0, PT, R22, RZ, !P0 ; /* 0x000000ff1600720c */
/* 0x000fda0004702670 */
/*0af0*/ @P0 LOP3.LUT R2, R19, 0x7ff00000, RZ, 0xfc, !PT ; /* 0x7ff0000013020812 */
/* 0x000fe200078efcff */
/*0b00*/ @!P0 IMAD.MOV.U32 R18, RZ, RZ, RZ ; /* 0x000000ffff128224 */
/* 0x000fe400078e00ff */
/*0b10*/ @P0 IMAD.MOV.U32 R18, RZ, RZ, RZ ; /* 0x000000ffff120224 */
/* 0x000fe400078e00ff */
/*0b20*/ @P0 IMAD.MOV.U32 R19, RZ, RZ, R2 ; /* 0x000000ffff130224 */
/* 0x000fe200078e0002 */
/*0b30*/ BRA 0xb90 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*0b40*/ LOP3.LUT R19, R7, 0x80000, RZ, 0xfc, !PT ; /* 0x0008000007137812 */
/* 0x001fe200078efcff */
/*0b50*/ IMAD.MOV.U32 R18, RZ, RZ, R6 ; /* 0x000000ffff127224 */
/* 0x000fe200078e0006 */
/*0b60*/ BRA 0xb90 ; /* 0x0000002000007947 */
/* 0x000fea0003800000 */
/*0b70*/ LOP3.LUT R19, R9, 0x80000, RZ, 0xfc, !PT ; /* 0x0008000009137812 */
/* 0x001fe200078efcff */
/*0b80*/ IMAD.MOV.U32 R18, RZ, RZ, R8 ; /* 0x000000ffff127224 */
/* 0x000fe400078e0008 */
/*0b90*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0ba0*/ IMAD.MOV.U32 R13, RZ, RZ, 0x0 ; /* 0x00000000ff0d7424 */
/* 0x000fe400078e00ff */
/*0bb0*/ IMAD.MOV.U32 R4, RZ, RZ, R18 ; /* 0x000000ffff047224 */
/* 0x000fc400078e0012 */
/*0bc0*/ IMAD.MOV.U32 R5, RZ, RZ, R19 ; /* 0x000000ffff057224 */
/* 0x000fe200078e0013 */
/*0bd0*/ RET.REL.NODEC R12 0x0 ; /* 0xfffff4200c007950 */
/* 0x000fec0003c3ffff */
/*0be0*/ BRA 0xbe0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0bf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <assert.h>
#include <stdlib.h>
#include <stdio.h>
#include <cuda.h>
#include <time.h>
struct BITMAPFILEHEADER
{
char bfType[2];
int bfSize;
int bfReserved;
int bfOffBits;
};
struct BITMAPINFOHEADER {
int biSize;
int biWidth;
int biHeight;
short biPlanes;
short biBitCount;
int biCompression;
int biSizeImage;
int biXPelsPerMeter;
int biYPelsPerMeter;
int biClrUsed;
int biClrImportant;
};
int write_bitmap(const char *filename, int width, int height, char *red, char *green, char *blue)
{
int bytes_per_line = (3 * (width + 1) / 4) * 4;
unsigned char *image_line = (unsigned char *)malloc(bytes_per_line);
struct BITMAPFILEHEADER bmph;
bmph.bfType[0] = 'B';
bmph.bfType[1] = 'M';
bmph.bfReserved = 0;
bmph.bfOffBits = 54;
bmph.bfSize = bmph.bfOffBits + bytes_per_line * height;
struct BITMAPINFOHEADER bmih;
bmih.biSize = 40;
bmih.biWidth = width;
bmih.biHeight = height;
bmih.biPlanes = 1;
bmih.biBitCount = 24;
bmih.biCompression = 0;
bmih.biSizeImage = bytes_per_line * height;
bmih.biXPelsPerMeter = 0;
bmih.biYPelsPerMeter = 0;
bmih.biClrUsed = 0;
bmih.biClrImportant = 0;
FILE *fit;
if((fit = fopen (filename, "wb"))==0) {
free(image_line);
return -1;
}
fwrite(&bmph.bfType, 2, 1, fit);
fwrite(&bmph.bfSize, 4, 1, fit);
fwrite(&bmph.bfReserved, 4, 1, fit);
fwrite(&bmph.bfOffBits, 4, 1, fit);
fwrite(&bmih.biSize, 4, 1, fit);
fwrite(&bmih.biWidth, 4, 1, fit);
fwrite(&bmih.biHeight, 4, 1, fit);
fwrite(&bmih.biPlanes, 2, 1, fit);
fwrite(&bmih.biBitCount, 2, 1, fit);
fwrite(&bmih.biCompression, 4, 1, fit);
fwrite(&bmih.biSizeImage, 4, 1, fit);
fwrite(&bmih.biXPelsPerMeter, 4, 1, fit);
fwrite(&bmih.biYPelsPerMeter, 4, 1, fit);
fwrite(&bmih.biClrUsed, 4, 1, fit);
fwrite(&bmih.biClrImportant, 4, 1, fit);
for(int i=height-1;i>=0;i--) {
for (int j=0;j<width;j++) {
int pos = (width * i + j);
image_line[3*j] = blue[pos];
image_line[3*j+1] = green[pos];
image_line[3*j+2] = red[pos];
}
fwrite((void *)image_line, bytes_per_line, 1, fit);
}
free(image_line);
fclose(fit);
return 0;
}
void mandel_host(char *red, char *green, char *blue, int width, int height)
{
for(int pos_x=0;pos_x<width;pos_x++) {
for(int pos_y=0;pos_y<height;pos_y++) {
float x0 = ((float)pos_x)*3.5/((float)width)-2.5;
float y0 = ((float)pos_y)*2.0/((float)height)-1.0;
float x = 0.0;
float y = 0.0;
int iteration = 0;
int max_iteration = 256;
while(x*x + y*y <= 4 && iteration < max_iteration) {
float xtemp = x*x - y*y + x0;
y = 2*x*y + y0;
x = xtemp;
iteration++;
}
int index = width*pos_y + pos_x;
if(iteration==max_iteration) {
iteration = 0;
}
red[index] = iteration;
green[index] = iteration;
blue[index] = iteration;
}
}
}
__global__ void mandel_cuda(char *red, char *green, char *blue, int width, int height)
{
/* kernel que calcula un pixel */
/* Per saber quin pixel és, cal tenir en compte totes les dimensions
del grid (el número de blocs i el número de threads */
/* Podeu fer servir els valors de
blockIdx.x, blockIdx.y
gridDim.x, gridDim.y
threadIdx.x, threadIdx.y
blockDim.x, blockDim.y */
int pos_x = threadIdx.x+blockDim.x*blockIdx.x;
int pos_y = threadIdx.y+blockDim.y*blockIdx.y;
float x0 = ((float)pos_x)*3.5/((float)width)-2.5;
float y0 = ((float)pos_y)*2.0/((float)height)-1.0;
float x = 0.0;
float y = 0.0;
int iteration = 0;
int max_iteration = 256;
while(x*x + y*y <= 4 && iteration < max_iteration) {
float xtemp = x*x - y*y + x0;
y = 2*x*y + y0;
x = xtemp;
iteration++;
}
int index = width*pos_y + pos_x;
if(iteration==max_iteration) {
iteration = 0;
}
red[index] = iteration;
green[index] = iteration;
blue[index] = iteration;
}
void fes_host(int width, int height)
{
size_t buffer_size = sizeof(char) * width * height;
char *image_red = (char *)malloc(buffer_size);
char *image_green = (char *)malloc(buffer_size);
char *image_blue = (char *)malloc(buffer_size);
mandel_host(image_red, image_green, image_blue, width, height);
// Now write the file
write_bitmap("output_host.bmp", width, height, image_red,
image_green, image_blue);
free(image_red);
free(image_green);
free(image_blue);
}
void fes_cuda(int width, int height)
{
size_t buffer_size = sizeof(char) * width * height;
char *image_red;
char *image_green;
char *image_blue;
cudaMalloc((void**)&image_red, buffer_size);
cudaMalloc((void**)&image_green, buffer_size);
cudaMalloc((void**)&image_blue, buffer_size);
clock_t t_device = clock();
dim3 blockDim(6, 6,1);
dim3 gridDim(width / blockDim.x, height / blockDim.y,1);
mandel_cuda<<< gridDim, blockDim,0>>>(image_red, image_green, image_blue, width, height);
char *host_image_red = (char*)malloc(buffer_size);
char *host_image_green= (char*)malloc(buffer_size);
char *host_image_blue= (char*)malloc(buffer_size);
/* cal copiar els valors de la imatge al host */
cudaMemcpy(host_image_red,image_red,buffer_size,cudaMemcpyDeviceToHost);
cudaMemcpy(host_image_green,image_green,buffer_size,cudaMemcpyDeviceToHost);
cudaMemcpy(host_image_blue,image_blue,buffer_size,cudaMemcpyDeviceToHost);
// Now write the file
write_bitmap("output_cuda.bmp", width, height, host_image_red,
host_image_green, host_image_blue);
t_device = clock() - t_device;
double time_taken_device = ((double)t_device)/CLOCKS_PER_SEC;
printf("GPU %f segons with %d threats \n", time_taken_device,blockDim.x);
/* cal alliberar la memòria del dispositiu i del host */
cudaFree(image_blue);
cudaFree(image_green);
cudaFree(image_red);
free(host_image_blue);
free(host_image_green);
free(host_image_red);
}
unsigned char* readBMP(const char* filename)
{
int i;
FILE* f = fopen(filename, "rb");
unsigned char info[54];
fread(info, sizeof(unsigned char), 54, f); // read the 54-byte header
// extract image height and width from header
int width = *(int*)&info[18];
int height = *(int*)&info[22];
int size = 3 * width * height;
unsigned char* data = new unsigned char[size]; // allocate 3 bytes per pixel
fread(data, sizeof(unsigned char), size, f); // read the rest of the data at once
fclose(f);
for(i = 0; i < size; i += 3)
{
unsigned char tmp = data[i];
data[i] = data[i+2];
data[i+2] = tmp;
}
return data;
}
int main(int argc, const char * argv[]) {
fes_cuda(5120, 5120);
fes_host(5120, 5120);
unsigned char *c , *h;
c = readBMP("output_cuda.bmp");
h = readBMP("output_host.bmp");
int errors =0;
int lengc = 5120*5120;
for(int i = 0 ; i < lengc;++i){
if(c[i] != h[i]){
errors++;
}
}
if(errors)printf("There are no difference,have %d errors\n",errors);
else printf("There are no difference\n");
return 0;
} | .file "tmpxft_00080723_00000000-6_mandel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2065:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2065:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "wb"
.text
.globl _Z12write_bitmapPKciiPcS1_S1_
.type _Z12write_bitmapPKciiPcS1_S1_, @function
_Z12write_bitmapPKciiPcS1_S1_:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $120, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 8(%rsp)
movl %esi, %r15d
movl %edx, %r13d
movq %rcx, %rbx
movq %r8, %rbp
movq %r9, %r12
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leal 3(%rsi,%rsi,2), %edx
leal 3(%rdx), %eax
testl %edx, %edx
cmovns %edx, %eax
andl $-4, %eax
movl %eax, %r14d
cltq
movq %rax, 16(%rsp)
movq %rax, %rdi
call malloc@PLT
movq %rax, (%rsp)
movb $66, 80(%rsp)
movb $77, 81(%rsp)
movl $0, 88(%rsp)
movl $54, 92(%rsp)
imull %r13d, %r14d
leal 54(%r14), %eax
movl %eax, 84(%rsp)
movl $40, 32(%rsp)
movl %r15d, 36(%rsp)
movl %r13d, 40(%rsp)
movw $1, 44(%rsp)
movw $24, 46(%rsp)
movl $0, 48(%rsp)
movl %r14d, 52(%rsp)
movl $0, 56(%rsp)
movl $0, 60(%rsp)
movl $0, 64(%rsp)
movl $0, 68(%rsp)
leaq .LC0(%rip), %rsi
movq 8(%rsp), %rdi
call fopen@PLT
movq %rax, 8(%rsp)
testq %rax, %rax
je .L14
leaq 80(%rsp), %rdi
movq 8(%rsp), %r14
movq %r14, %rcx
movl $1, %edx
movl $2, %esi
call fwrite@PLT
leaq 84(%rsp), %rdi
movq %r14, %rcx
movl $1, %edx
movl $4, %esi
call fwrite@PLT
leaq 88(%rsp), %rdi
movq %r14, %rcx
movl $1, %edx
movl $4, %esi
call fwrite@PLT
leaq 92(%rsp), %rdi
movq %r14, %rcx
movl $1, %edx
movl $4, %esi
call fwrite@PLT
leaq 32(%rsp), %rdi
movq %r14, %rcx
movl $1, %edx
movl $4, %esi
call fwrite@PLT
leaq 36(%rsp), %rdi
movq %r14, %rcx
movl $1, %edx
movl $4, %esi
call fwrite@PLT
leaq 40(%rsp), %rdi
movq %r14, %rcx
movl $1, %edx
movl $4, %esi
call fwrite@PLT
leaq 44(%rsp), %rdi
movq %r14, %rcx
movl $1, %edx
movl $2, %esi
call fwrite@PLT
leaq 46(%rsp), %rdi
movq %r14, %rcx
movl $1, %edx
movl $2, %esi
call fwrite@PLT
leaq 48(%rsp), %rdi
movq %r14, %rcx
movl $1, %edx
movl $4, %esi
call fwrite@PLT
leaq 52(%rsp), %rdi
movq %r14, %rcx
movl $1, %edx
movl $4, %esi
call fwrite@PLT
leaq 56(%rsp), %rdi
movq %r14, %rcx
movl $1, %edx
movl $4, %esi
call fwrite@PLT
leaq 60(%rsp), %rdi
movq %r14, %rcx
movl $1, %edx
movl $4, %esi
call fwrite@PLT
leaq 64(%rsp), %rdi
movq %r14, %rcx
movl $1, %edx
movl $4, %esi
call fwrite@PLT
leaq 68(%rsp), %rdi
movq %r14, %rcx
movl $1, %edx
movl $4, %esi
call fwrite@PLT
subl $1, %r13d
js .L6
movl %r13d, %r14d
imull %r15d, %r14d
movslq %r15d, %rax
movq %rax, 24(%rsp)
jmp .L7
.L14:
movq (%rsp), %rdi
call free@PLT
movl $-1, %eax
jmp .L3
.L8:
movzbl (%r12,%rax), %ecx
movb %cl, (%rdx)
movzbl 0(%rbp,%rax), %ecx
movb %cl, 1(%rdx)
movzbl (%rbx,%rax), %ecx
movb %cl, 2(%rdx)
addq $3, %rdx
addq $1, %rax
cmpq %rsi, %rax
jne .L8
.L10:
movq 8(%rsp), %rcx
movl $1, %edx
movq 16(%rsp), %rsi
movq (%rsp), %rdi
call fwrite@PLT
subl $1, %r13d
subl %r15d, %r14d
cmpl $-1, %r13d
je .L6
.L7:
movq (%rsp), %rdx
movslq %r14d, %rax
movq 24(%rsp), %rdi
leaq (%rdi,%rax), %rsi
testl %r15d, %r15d
jg .L8
jmp .L10
.L6:
movq (%rsp), %rdi
call free@PLT
movq 8(%rsp), %rdi
call fclose@PLT
movl $0, %eax
.L3:
movq 104(%rsp), %rdx
subq %fs:40, %rdx
jne .L15
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size _Z12write_bitmapPKciiPcS1_S1_, .-_Z12write_bitmapPKciiPcS1_S1_
.globl _Z11mandel_hostPcS_S_ii
.type _Z11mandel_hostPcS_S_ii, @function
_Z11mandel_hostPcS_S_ii:
.LFB2058:
.cfi_startproc
endbr64
testl %ecx, %ecx
jle .L30
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
movq %rdi, %r9
movq %rsi, %r10
movq %rdx, %r11
movl %ecx, %ebx
movl %r8d, %esi
movslq %ecx, %rdi
movl $0, %ebp
movsd .LC2(%rip), %xmm12
movsd .LC3(%rip), %xmm11
movsd .LC4(%rip), %xmm10
pxor %xmm8, %xmm8
movss .LC5(%rip), %xmm7
movl $0, %r8d
jmp .L18
.L26:
cmpl $256, %eax
cmove %r8d, %eax
movb %al, (%r9,%rdx)
movb %al, (%r10,%rdx)
movb %al, (%r11,%rdx)
addl $1, %ecx
addq %rdi, %rdx
cmpl %ecx, %esi
je .L24
.L22:
pxor %xmm5, %xmm5
cvtsi2ssl %ecx, %xmm5
cvtss2sd %xmm5, %xmm5
addsd %xmm5, %xmm5
divsd %xmm9, %xmm5
subsd %xmm10, %xmm5
cvtsd2ss %xmm5, %xmm5
movl $0, %eax
movaps %xmm8, %xmm0
movaps %xmm8, %xmm3
movaps %xmm8, %xmm4
movaps %xmm8, %xmm1
.L19:
movaps %xmm3, %xmm2
subss %xmm4, %xmm1
movaps %xmm1, %xmm3
addss %xmm6, %xmm3
addss %xmm2, %xmm2
mulss %xmm2, %xmm0
addss %xmm5, %xmm0
addl $1, %eax
movaps %xmm3, %xmm1
mulss %xmm3, %xmm1
movaps %xmm0, %xmm4
mulss %xmm0, %xmm4
movaps %xmm1, %xmm2
addss %xmm4, %xmm2
comiss %xmm2, %xmm7
jb .L26
cmpl $255, %eax
jle .L19
jmp .L26
.L24:
addq $1, %rbp
cmpq %rdi, %rbp
je .L16
.L18:
testl %esi, %esi
jle .L24
pxor %xmm0, %xmm0
cvtsi2ssl %ebp, %xmm0
pxor %xmm6, %xmm6
cvtss2sd %xmm0, %xmm6
mulsd %xmm12, %xmm6
pxor %xmm0, %xmm0
cvtsi2ssl %ebx, %xmm0
cvtss2sd %xmm0, %xmm0
divsd %xmm0, %xmm6
subsd %xmm11, %xmm6
cvtsd2ss %xmm6, %xmm6
movq %rbp, %rdx
movl $0, %ecx
pxor %xmm9, %xmm9
cvtsi2ssl %esi, %xmm9
cvtss2sd %xmm9, %xmm9
jmp .L22
.L16:
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L30:
.cfi_restore 3
.cfi_restore 6
ret
.cfi_endproc
.LFE2058:
.size _Z11mandel_hostPcS_S_ii, .-_Z11mandel_hostPcS_S_ii
.section .rodata.str1.1
.LC6:
.string "output_host.bmp"
.text
.globl _Z8fes_hostii
.type _Z8fes_hostii, @function
_Z8fes_hostii:
.LFB2059:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
movl %edi, %r13d
movl %esi, %r14d
movslq %edi, %rbx
movslq %esi, %rax
imulq %rax, %rbx
movq %rbx, %rdi
call malloc@PLT
movq %rax, %r12
movq %rbx, %rdi
call malloc@PLT
movq %rax, %rbp
movq %rbx, %rdi
call malloc@PLT
movq %rax, %rbx
movl %r14d, %r8d
movl %r13d, %ecx
movq %rax, %rdx
movq %rbp, %rsi
movq %r12, %rdi
call _Z11mandel_hostPcS_S_ii
movq %rbx, %r9
movq %rbp, %r8
movq %r12, %rcx
movl %r14d, %edx
movl %r13d, %esi
leaq .LC6(%rip), %rdi
call _Z12write_bitmapPKciiPcS1_S1_
movq %r12, %rdi
call free@PLT
movq %rbp, %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size _Z8fes_hostii, .-_Z8fes_hostii
.section .rodata.str1.1
.LC7:
.string "rb"
.text
.globl _Z7readBMPPKc
.type _Z7readBMPPKc, @function
_Z7readBMPPKc:
.LFB2061:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $72, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
leaq .LC7(%rip), %rsi
call fopen@PLT
movq %rax, %r12
movq %rsp, %rdi
movq %rax, %r8
movl $54, %ecx
movl $1, %edx
movl $54, %esi
call __fread_chk@PLT
movl 18(%rsp), %eax
imull 22(%rsp), %eax
leal (%rax,%rax,2), %ebp
movslq %ebp, %r13
movq %r13, %rdi
call _Znam@PLT
movq %rax, %rbx
movq %r12, %r8
movq %r13, %rcx
movl $1, %edx
movq %r13, %rsi
movq %rax, %rdi
call __fread_chk@PLT
movq %r12, %rdi
call fclose@PLT
testl %ebp, %ebp
jle .L35
movl $0, %eax
.L37:
movzbl (%rbx,%rax), %edx
movzbl 2(%rbx,%rax), %ecx
movb %cl, (%rbx,%rax)
movb %dl, 2(%rbx,%rax)
addq $3, %rax
cmpl %eax, %ebp
jg .L37
.L35:
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L41
movq %rbx, %rax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L41:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2061:
.size _Z7readBMPPKc, .-_Z7readBMPPKc
.globl _Z37__device_stub__Z11mandel_cudaPcS_S_iiPcS_S_ii
.type _Z37__device_stub__Z11mandel_cudaPcS_S_iiPcS_S_ii, @function
_Z37__device_stub__Z11mandel_cudaPcS_S_iiPcS_S_ii:
.LFB2087:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L46
.L42:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L47
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L46:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z11mandel_cudaPcS_S_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L42
.L47:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2087:
.size _Z37__device_stub__Z11mandel_cudaPcS_S_iiPcS_S_ii, .-_Z37__device_stub__Z11mandel_cudaPcS_S_iiPcS_S_ii
.globl _Z11mandel_cudaPcS_S_ii
.type _Z11mandel_cudaPcS_S_ii, @function
_Z11mandel_cudaPcS_S_ii:
.LFB2088:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z37__device_stub__Z11mandel_cudaPcS_S_iiPcS_S_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2088:
.size _Z11mandel_cudaPcS_S_ii, .-_Z11mandel_cudaPcS_S_ii
.section .rodata.str1.1
.LC8:
.string "output_cuda.bmp"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC10:
.string "GPU %f segons with %d threats \n"
.text
.globl _Z8fes_cudaii
.type _Z8fes_cudaii, @function
_Z8fes_cudaii:
.LFB2060:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $88, %rsp
.cfi_def_cfa_offset 144
movl %edi, %ebp
movl %esi, %r12d
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movslq %edi, %rbx
movslq %esi, %rax
imulq %rax, %rbx
leaq 24(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 32(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 40(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
call clock@PLT
movq %rax, 8(%rsp)
movl %ebp, %eax
movl $2863311531, %edx
imulq %rdx, %rax
shrq $34, %rax
movl %eax, 60(%rsp)
movl %r12d, %eax
imulq %rdx, %rax
shrq $34, %rax
movl %eax, 64(%rsp)
movl $6, 48(%rsp)
movl $6, 52(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 48(%rsp), %rdx
movl $1, %ecx
movq 60(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L54
.L51:
movq %rbx, %rdi
call malloc@PLT
movq %rax, %r13
movq %rbx, %rdi
call malloc@PLT
movq %rax, %r14
movq %rbx, %rdi
call malloc@PLT
movq %rax, %r15
movl $2, %ecx
movq %rbx, %rdx
movq 24(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
movl $2, %ecx
movq %rbx, %rdx
movq 32(%rsp), %rsi
movq %r14, %rdi
call cudaMemcpy@PLT
movl $2, %ecx
movq %rbx, %rdx
movq 40(%rsp), %rsi
movq %r15, %rdi
call cudaMemcpy@PLT
movq %r15, %r9
movq %r14, %r8
movq %r13, %rcx
movl %r12d, %edx
movl %ebp, %esi
leaq .LC8(%rip), %rdi
call _Z12write_bitmapPKciiPcS1_S1_
call clock@PLT
movq 8(%rsp), %rcx
subq %rcx, %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
divsd .LC9(%rip), %xmm0
movl $6, %edx
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq %r15, %rdi
call free@PLT
movq %r14, %rdi
call free@PLT
movq %r13, %rdi
call free@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L55
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L54:
.cfi_restore_state
movl %r12d, %r8d
movl %ebp, %ecx
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z37__device_stub__Z11mandel_cudaPcS_S_iiPcS_S_ii
jmp .L51
.L55:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2060:
.size _Z8fes_cudaii, .-_Z8fes_cudaii
.section .rodata.str1.8
.align 8
.LC11:
.string "There are no difference,have %d errors\n"
.section .rodata.str1.1
.LC12:
.string "There are no difference\n"
.text
.globl main
.type main, @function
main:
.LFB2062:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movl $5120, %esi
movl $5120, %edi
call _Z8fes_cudaii
movl $5120, %esi
movl $5120, %edi
call _Z8fes_hostii
leaq .LC8(%rip), %rdi
call _Z7readBMPPKc
movq %rax, %rbx
leaq .LC6(%rip), %rdi
call _Z7readBMPPKc
movl $0, %edx
movl $0, %ecx
jmp .L58
.L57:
addq $1, %rdx
cmpq $26214400, %rdx
je .L63
.L58:
movzbl (%rax,%rdx), %esi
cmpb %sil, (%rbx,%rdx)
je .L57
addl $1, %ecx
jmp .L57
.L63:
testl %ecx, %ecx
je .L59
movl %ecx, %edx
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L60:
movl $0, %eax
popq %rbx
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L59:
.cfi_restore_state
leaq .LC12(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L60
.cfi_endproc
.LFE2062:
.size main, .-main
.section .rodata.str1.1
.LC13:
.string "_Z11mandel_cudaPcS_S_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2090:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC13(%rip), %rdx
movq %rdx, %rcx
leaq _Z11mandel_cudaPcS_S_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2090:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC2:
.long 0
.long 1074528256
.align 8
.LC3:
.long 0
.long 1074003968
.align 8
.LC4:
.long 0
.long 1072693248
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC5:
.long 1082130432
.section .rodata.cst8
.align 8
.LC9:
.long 0
.long 1093567616
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <assert.h>
#include <stdlib.h>
#include <stdio.h>
#include <cuda.h>
#include <time.h>
struct BITMAPFILEHEADER
{
char bfType[2];
int bfSize;
int bfReserved;
int bfOffBits;
};
struct BITMAPINFOHEADER {
int biSize;
int biWidth;
int biHeight;
short biPlanes;
short biBitCount;
int biCompression;
int biSizeImage;
int biXPelsPerMeter;
int biYPelsPerMeter;
int biClrUsed;
int biClrImportant;
};
int write_bitmap(const char *filename, int width, int height, char *red, char *green, char *blue)
{
int bytes_per_line = (3 * (width + 1) / 4) * 4;
unsigned char *image_line = (unsigned char *)malloc(bytes_per_line);
struct BITMAPFILEHEADER bmph;
bmph.bfType[0] = 'B';
bmph.bfType[1] = 'M';
bmph.bfReserved = 0;
bmph.bfOffBits = 54;
bmph.bfSize = bmph.bfOffBits + bytes_per_line * height;
struct BITMAPINFOHEADER bmih;
bmih.biSize = 40;
bmih.biWidth = width;
bmih.biHeight = height;
bmih.biPlanes = 1;
bmih.biBitCount = 24;
bmih.biCompression = 0;
bmih.biSizeImage = bytes_per_line * height;
bmih.biXPelsPerMeter = 0;
bmih.biYPelsPerMeter = 0;
bmih.biClrUsed = 0;
bmih.biClrImportant = 0;
FILE *fit;
if((fit = fopen (filename, "wb"))==0) {
free(image_line);
return -1;
}
fwrite(&bmph.bfType, 2, 1, fit);
fwrite(&bmph.bfSize, 4, 1, fit);
fwrite(&bmph.bfReserved, 4, 1, fit);
fwrite(&bmph.bfOffBits, 4, 1, fit);
fwrite(&bmih.biSize, 4, 1, fit);
fwrite(&bmih.biWidth, 4, 1, fit);
fwrite(&bmih.biHeight, 4, 1, fit);
fwrite(&bmih.biPlanes, 2, 1, fit);
fwrite(&bmih.biBitCount, 2, 1, fit);
fwrite(&bmih.biCompression, 4, 1, fit);
fwrite(&bmih.biSizeImage, 4, 1, fit);
fwrite(&bmih.biXPelsPerMeter, 4, 1, fit);
fwrite(&bmih.biYPelsPerMeter, 4, 1, fit);
fwrite(&bmih.biClrUsed, 4, 1, fit);
fwrite(&bmih.biClrImportant, 4, 1, fit);
for(int i=height-1;i>=0;i--) {
for (int j=0;j<width;j++) {
int pos = (width * i + j);
image_line[3*j] = blue[pos];
image_line[3*j+1] = green[pos];
image_line[3*j+2] = red[pos];
}
fwrite((void *)image_line, bytes_per_line, 1, fit);
}
free(image_line);
fclose(fit);
return 0;
}
void mandel_host(char *red, char *green, char *blue, int width, int height)
{
for(int pos_x=0;pos_x<width;pos_x++) {
for(int pos_y=0;pos_y<height;pos_y++) {
float x0 = ((float)pos_x)*3.5/((float)width)-2.5;
float y0 = ((float)pos_y)*2.0/((float)height)-1.0;
float x = 0.0;
float y = 0.0;
int iteration = 0;
int max_iteration = 256;
while(x*x + y*y <= 4 && iteration < max_iteration) {
float xtemp = x*x - y*y + x0;
y = 2*x*y + y0;
x = xtemp;
iteration++;
}
int index = width*pos_y + pos_x;
if(iteration==max_iteration) {
iteration = 0;
}
red[index] = iteration;
green[index] = iteration;
blue[index] = iteration;
}
}
}
__global__ void mandel_cuda(char *red, char *green, char *blue, int width, int height)
{
/* kernel que calcula un pixel */
/* Per saber quin pixel és, cal tenir en compte totes les dimensions
del grid (el número de blocs i el número de threads */
/* Podeu fer servir els valors de
blockIdx.x, blockIdx.y
gridDim.x, gridDim.y
threadIdx.x, threadIdx.y
blockDim.x, blockDim.y */
int pos_x = threadIdx.x+blockDim.x*blockIdx.x;
int pos_y = threadIdx.y+blockDim.y*blockIdx.y;
float x0 = ((float)pos_x)*3.5/((float)width)-2.5;
float y0 = ((float)pos_y)*2.0/((float)height)-1.0;
float x = 0.0;
float y = 0.0;
int iteration = 0;
int max_iteration = 256;
while(x*x + y*y <= 4 && iteration < max_iteration) {
float xtemp = x*x - y*y + x0;
y = 2*x*y + y0;
x = xtemp;
iteration++;
}
int index = width*pos_y + pos_x;
if(iteration==max_iteration) {
iteration = 0;
}
red[index] = iteration;
green[index] = iteration;
blue[index] = iteration;
}
void fes_host(int width, int height)
{
size_t buffer_size = sizeof(char) * width * height;
char *image_red = (char *)malloc(buffer_size);
char *image_green = (char *)malloc(buffer_size);
char *image_blue = (char *)malloc(buffer_size);
mandel_host(image_red, image_green, image_blue, width, height);
// Now write the file
write_bitmap("output_host.bmp", width, height, image_red,
image_green, image_blue);
free(image_red);
free(image_green);
free(image_blue);
}
void fes_cuda(int width, int height)
{
size_t buffer_size = sizeof(char) * width * height;
char *image_red;
char *image_green;
char *image_blue;
cudaMalloc((void**)&image_red, buffer_size);
cudaMalloc((void**)&image_green, buffer_size);
cudaMalloc((void**)&image_blue, buffer_size);
clock_t t_device = clock();
dim3 blockDim(6, 6,1);
dim3 gridDim(width / blockDim.x, height / blockDim.y,1);
mandel_cuda<<< gridDim, blockDim,0>>>(image_red, image_green, image_blue, width, height);
char *host_image_red = (char*)malloc(buffer_size);
char *host_image_green= (char*)malloc(buffer_size);
char *host_image_blue= (char*)malloc(buffer_size);
/* cal copiar els valors de la imatge al host */
cudaMemcpy(host_image_red,image_red,buffer_size,cudaMemcpyDeviceToHost);
cudaMemcpy(host_image_green,image_green,buffer_size,cudaMemcpyDeviceToHost);
cudaMemcpy(host_image_blue,image_blue,buffer_size,cudaMemcpyDeviceToHost);
// Now write the file
write_bitmap("output_cuda.bmp", width, height, host_image_red,
host_image_green, host_image_blue);
t_device = clock() - t_device;
double time_taken_device = ((double)t_device)/CLOCKS_PER_SEC;
printf("GPU %f segons with %d threats \n", time_taken_device,blockDim.x);
/* cal alliberar la memòria del dispositiu i del host */
cudaFree(image_blue);
cudaFree(image_green);
cudaFree(image_red);
free(host_image_blue);
free(host_image_green);
free(host_image_red);
}
unsigned char* readBMP(const char* filename)
{
int i;
FILE* f = fopen(filename, "rb");
unsigned char info[54];
fread(info, sizeof(unsigned char), 54, f); // read the 54-byte header
// extract image height and width from header
int width = *(int*)&info[18];
int height = *(int*)&info[22];
int size = 3 * width * height;
unsigned char* data = new unsigned char[size]; // allocate 3 bytes per pixel
fread(data, sizeof(unsigned char), size, f); // read the rest of the data at once
fclose(f);
for(i = 0; i < size; i += 3)
{
unsigned char tmp = data[i];
data[i] = data[i+2];
data[i+2] = tmp;
}
return data;
}
int main(int argc, const char * argv[]) {
fes_cuda(5120, 5120);
fes_host(5120, 5120);
unsigned char *c , *h;
c = readBMP("output_cuda.bmp");
h = readBMP("output_host.bmp");
int errors =0;
int lengc = 5120*5120;
for(int i = 0 ; i < lengc;++i){
if(c[i] != h[i]){
errors++;
}
}
if(errors)printf("There are no difference,have %d errors\n",errors);
else printf("There are no difference\n");
return 0;
} | #include <stdio.h>
#include <assert.h>
#include <stdlib.h>
#include <stdio.h>
#include <hip/hip_runtime.h>
#include <time.h>
struct BITMAPFILEHEADER
{
char bfType[2];
int bfSize;
int bfReserved;
int bfOffBits;
};
struct BITMAPINFOHEADER {
int biSize;
int biWidth;
int biHeight;
short biPlanes;
short biBitCount;
int biCompression;
int biSizeImage;
int biXPelsPerMeter;
int biYPelsPerMeter;
int biClrUsed;
int biClrImportant;
};
int write_bitmap(const char *filename, int width, int height, char *red, char *green, char *blue)
{
int bytes_per_line = (3 * (width + 1) / 4) * 4;
unsigned char *image_line = (unsigned char *)malloc(bytes_per_line);
struct BITMAPFILEHEADER bmph;
bmph.bfType[0] = 'B';
bmph.bfType[1] = 'M';
bmph.bfReserved = 0;
bmph.bfOffBits = 54;
bmph.bfSize = bmph.bfOffBits + bytes_per_line * height;
struct BITMAPINFOHEADER bmih;
bmih.biSize = 40;
bmih.biWidth = width;
bmih.biHeight = height;
bmih.biPlanes = 1;
bmih.biBitCount = 24;
bmih.biCompression = 0;
bmih.biSizeImage = bytes_per_line * height;
bmih.biXPelsPerMeter = 0;
bmih.biYPelsPerMeter = 0;
bmih.biClrUsed = 0;
bmih.biClrImportant = 0;
FILE *fit;
if((fit = fopen (filename, "wb"))==0) {
free(image_line);
return -1;
}
fwrite(&bmph.bfType, 2, 1, fit);
fwrite(&bmph.bfSize, 4, 1, fit);
fwrite(&bmph.bfReserved, 4, 1, fit);
fwrite(&bmph.bfOffBits, 4, 1, fit);
fwrite(&bmih.biSize, 4, 1, fit);
fwrite(&bmih.biWidth, 4, 1, fit);
fwrite(&bmih.biHeight, 4, 1, fit);
fwrite(&bmih.biPlanes, 2, 1, fit);
fwrite(&bmih.biBitCount, 2, 1, fit);
fwrite(&bmih.biCompression, 4, 1, fit);
fwrite(&bmih.biSizeImage, 4, 1, fit);
fwrite(&bmih.biXPelsPerMeter, 4, 1, fit);
fwrite(&bmih.biYPelsPerMeter, 4, 1, fit);
fwrite(&bmih.biClrUsed, 4, 1, fit);
fwrite(&bmih.biClrImportant, 4, 1, fit);
for(int i=height-1;i>=0;i--) {
for (int j=0;j<width;j++) {
int pos = (width * i + j);
image_line[3*j] = blue[pos];
image_line[3*j+1] = green[pos];
image_line[3*j+2] = red[pos];
}
fwrite((void *)image_line, bytes_per_line, 1, fit);
}
free(image_line);
fclose(fit);
return 0;
}
void mandel_host(char *red, char *green, char *blue, int width, int height)
{
for(int pos_x=0;pos_x<width;pos_x++) {
for(int pos_y=0;pos_y<height;pos_y++) {
float x0 = ((float)pos_x)*3.5/((float)width)-2.5;
float y0 = ((float)pos_y)*2.0/((float)height)-1.0;
float x = 0.0;
float y = 0.0;
int iteration = 0;
int max_iteration = 256;
while(x*x + y*y <= 4 && iteration < max_iteration) {
float xtemp = x*x - y*y + x0;
y = 2*x*y + y0;
x = xtemp;
iteration++;
}
int index = width*pos_y + pos_x;
if(iteration==max_iteration) {
iteration = 0;
}
red[index] = iteration;
green[index] = iteration;
blue[index] = iteration;
}
}
}
__global__ void mandel_cuda(char *red, char *green, char *blue, int width, int height)
{
/* kernel que calcula un pixel */
/* Per saber quin pixel és, cal tenir en compte totes les dimensions
del grid (el número de blocs i el número de threads */
/* Podeu fer servir els valors de
blockIdx.x, blockIdx.y
gridDim.x, gridDim.y
threadIdx.x, threadIdx.y
blockDim.x, blockDim.y */
int pos_x = threadIdx.x+blockDim.x*blockIdx.x;
int pos_y = threadIdx.y+blockDim.y*blockIdx.y;
float x0 = ((float)pos_x)*3.5/((float)width)-2.5;
float y0 = ((float)pos_y)*2.0/((float)height)-1.0;
float x = 0.0;
float y = 0.0;
int iteration = 0;
int max_iteration = 256;
while(x*x + y*y <= 4 && iteration < max_iteration) {
float xtemp = x*x - y*y + x0;
y = 2*x*y + y0;
x = xtemp;
iteration++;
}
int index = width*pos_y + pos_x;
if(iteration==max_iteration) {
iteration = 0;
}
red[index] = iteration;
green[index] = iteration;
blue[index] = iteration;
}
void fes_host(int width, int height)
{
size_t buffer_size = sizeof(char) * width * height;
char *image_red = (char *)malloc(buffer_size);
char *image_green = (char *)malloc(buffer_size);
char *image_blue = (char *)malloc(buffer_size);
mandel_host(image_red, image_green, image_blue, width, height);
// Now write the file
write_bitmap("output_host.bmp", width, height, image_red,
image_green, image_blue);
free(image_red);
free(image_green);
free(image_blue);
}
void fes_cuda(int width, int height)
{
size_t buffer_size = sizeof(char) * width * height;
char *image_red;
char *image_green;
char *image_blue;
hipMalloc((void**)&image_red, buffer_size);
hipMalloc((void**)&image_green, buffer_size);
hipMalloc((void**)&image_blue, buffer_size);
clock_t t_device = clock();
dim3 blockDim(6, 6,1);
dim3 gridDim(width / blockDim.x, height / blockDim.y,1);
mandel_cuda<<< gridDim, blockDim,0>>>(image_red, image_green, image_blue, width, height);
char *host_image_red = (char*)malloc(buffer_size);
char *host_image_green= (char*)malloc(buffer_size);
char *host_image_blue= (char*)malloc(buffer_size);
/* cal copiar els valors de la imatge al host */
hipMemcpy(host_image_red,image_red,buffer_size,hipMemcpyDeviceToHost);
hipMemcpy(host_image_green,image_green,buffer_size,hipMemcpyDeviceToHost);
hipMemcpy(host_image_blue,image_blue,buffer_size,hipMemcpyDeviceToHost);
// Now write the file
write_bitmap("output_cuda.bmp", width, height, host_image_red,
host_image_green, host_image_blue);
t_device = clock() - t_device;
double time_taken_device = ((double)t_device)/CLOCKS_PER_SEC;
printf("GPU %f segons with %d threats \n", time_taken_device,blockDim.x);
/* cal alliberar la memòria del dispositiu i del host */
hipFree(image_blue);
hipFree(image_green);
hipFree(image_red);
free(host_image_blue);
free(host_image_green);
free(host_image_red);
}
unsigned char* readBMP(const char* filename)
{
int i;
FILE* f = fopen(filename, "rb");
unsigned char info[54];
fread(info, sizeof(unsigned char), 54, f); // read the 54-byte header
// extract image height and width from header
int width = *(int*)&info[18];
int height = *(int*)&info[22];
int size = 3 * width * height;
unsigned char* data = new unsigned char[size]; // allocate 3 bytes per pixel
fread(data, sizeof(unsigned char), size, f); // read the rest of the data at once
fclose(f);
for(i = 0; i < size; i += 3)
{
unsigned char tmp = data[i];
data[i] = data[i+2];
data[i+2] = tmp;
}
return data;
}
int main(int argc, const char * argv[]) {
fes_cuda(5120, 5120);
fes_host(5120, 5120);
unsigned char *c , *h;
c = readBMP("output_cuda.bmp");
h = readBMP("output_host.bmp");
int errors =0;
int lengc = 5120*5120;
for(int i = 0 ; i < lengc;++i){
if(c[i] != h[i]){
errors++;
}
}
if(errors)printf("There are no difference,have %d errors\n",errors);
else printf("There are no difference\n");
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <stdio.h>
#include <assert.h>
#include <stdlib.h>
#include <stdio.h>
#include <hip/hip_runtime.h>
#include <time.h>
struct BITMAPFILEHEADER
{
char bfType[2];
int bfSize;
int bfReserved;
int bfOffBits;
};
struct BITMAPINFOHEADER {
int biSize;
int biWidth;
int biHeight;
short biPlanes;
short biBitCount;
int biCompression;
int biSizeImage;
int biXPelsPerMeter;
int biYPelsPerMeter;
int biClrUsed;
int biClrImportant;
};
int write_bitmap(const char *filename, int width, int height, char *red, char *green, char *blue)
{
int bytes_per_line = (3 * (width + 1) / 4) * 4;
unsigned char *image_line = (unsigned char *)malloc(bytes_per_line);
struct BITMAPFILEHEADER bmph;
bmph.bfType[0] = 'B';
bmph.bfType[1] = 'M';
bmph.bfReserved = 0;
bmph.bfOffBits = 54;
bmph.bfSize = bmph.bfOffBits + bytes_per_line * height;
struct BITMAPINFOHEADER bmih;
bmih.biSize = 40;
bmih.biWidth = width;
bmih.biHeight = height;
bmih.biPlanes = 1;
bmih.biBitCount = 24;
bmih.biCompression = 0;
bmih.biSizeImage = bytes_per_line * height;
bmih.biXPelsPerMeter = 0;
bmih.biYPelsPerMeter = 0;
bmih.biClrUsed = 0;
bmih.biClrImportant = 0;
FILE *fit;
if((fit = fopen (filename, "wb"))==0) {
free(image_line);
return -1;
}
fwrite(&bmph.bfType, 2, 1, fit);
fwrite(&bmph.bfSize, 4, 1, fit);
fwrite(&bmph.bfReserved, 4, 1, fit);
fwrite(&bmph.bfOffBits, 4, 1, fit);
fwrite(&bmih.biSize, 4, 1, fit);
fwrite(&bmih.biWidth, 4, 1, fit);
fwrite(&bmih.biHeight, 4, 1, fit);
fwrite(&bmih.biPlanes, 2, 1, fit);
fwrite(&bmih.biBitCount, 2, 1, fit);
fwrite(&bmih.biCompression, 4, 1, fit);
fwrite(&bmih.biSizeImage, 4, 1, fit);
fwrite(&bmih.biXPelsPerMeter, 4, 1, fit);
fwrite(&bmih.biYPelsPerMeter, 4, 1, fit);
fwrite(&bmih.biClrUsed, 4, 1, fit);
fwrite(&bmih.biClrImportant, 4, 1, fit);
for(int i=height-1;i>=0;i--) {
for (int j=0;j<width;j++) {
int pos = (width * i + j);
image_line[3*j] = blue[pos];
image_line[3*j+1] = green[pos];
image_line[3*j+2] = red[pos];
}
fwrite((void *)image_line, bytes_per_line, 1, fit);
}
free(image_line);
fclose(fit);
return 0;
}
void mandel_host(char *red, char *green, char *blue, int width, int height)
{
for(int pos_x=0;pos_x<width;pos_x++) {
for(int pos_y=0;pos_y<height;pos_y++) {
float x0 = ((float)pos_x)*3.5/((float)width)-2.5;
float y0 = ((float)pos_y)*2.0/((float)height)-1.0;
float x = 0.0;
float y = 0.0;
int iteration = 0;
int max_iteration = 256;
while(x*x + y*y <= 4 && iteration < max_iteration) {
float xtemp = x*x - y*y + x0;
y = 2*x*y + y0;
x = xtemp;
iteration++;
}
int index = width*pos_y + pos_x;
if(iteration==max_iteration) {
iteration = 0;
}
red[index] = iteration;
green[index] = iteration;
blue[index] = iteration;
}
}
}
__global__ void mandel_cuda(char *red, char *green, char *blue, int width, int height)
{
/* kernel que calcula un pixel */
/* Per saber quin pixel és, cal tenir en compte totes les dimensions
del grid (el número de blocs i el número de threads */
/* Podeu fer servir els valors de
blockIdx.x, blockIdx.y
gridDim.x, gridDim.y
threadIdx.x, threadIdx.y
blockDim.x, blockDim.y */
int pos_x = threadIdx.x+blockDim.x*blockIdx.x;
int pos_y = threadIdx.y+blockDim.y*blockIdx.y;
float x0 = ((float)pos_x)*3.5/((float)width)-2.5;
float y0 = ((float)pos_y)*2.0/((float)height)-1.0;
float x = 0.0;
float y = 0.0;
int iteration = 0;
int max_iteration = 256;
while(x*x + y*y <= 4 && iteration < max_iteration) {
float xtemp = x*x - y*y + x0;
y = 2*x*y + y0;
x = xtemp;
iteration++;
}
int index = width*pos_y + pos_x;
if(iteration==max_iteration) {
iteration = 0;
}
red[index] = iteration;
green[index] = iteration;
blue[index] = iteration;
}
void fes_host(int width, int height)
{
size_t buffer_size = sizeof(char) * width * height;
char *image_red = (char *)malloc(buffer_size);
char *image_green = (char *)malloc(buffer_size);
char *image_blue = (char *)malloc(buffer_size);
mandel_host(image_red, image_green, image_blue, width, height);
// Now write the file
write_bitmap("output_host.bmp", width, height, image_red,
image_green, image_blue);
free(image_red);
free(image_green);
free(image_blue);
}
void fes_cuda(int width, int height)
{
size_t buffer_size = sizeof(char) * width * height;
char *image_red;
char *image_green;
char *image_blue;
hipMalloc((void**)&image_red, buffer_size);
hipMalloc((void**)&image_green, buffer_size);
hipMalloc((void**)&image_blue, buffer_size);
clock_t t_device = clock();
dim3 blockDim(6, 6,1);
dim3 gridDim(width / blockDim.x, height / blockDim.y,1);
mandel_cuda<<< gridDim, blockDim,0>>>(image_red, image_green, image_blue, width, height);
char *host_image_red = (char*)malloc(buffer_size);
char *host_image_green= (char*)malloc(buffer_size);
char *host_image_blue= (char*)malloc(buffer_size);
/* cal copiar els valors de la imatge al host */
hipMemcpy(host_image_red,image_red,buffer_size,hipMemcpyDeviceToHost);
hipMemcpy(host_image_green,image_green,buffer_size,hipMemcpyDeviceToHost);
hipMemcpy(host_image_blue,image_blue,buffer_size,hipMemcpyDeviceToHost);
// Now write the file
write_bitmap("output_cuda.bmp", width, height, host_image_red,
host_image_green, host_image_blue);
t_device = clock() - t_device;
double time_taken_device = ((double)t_device)/CLOCKS_PER_SEC;
printf("GPU %f segons with %d threats \n", time_taken_device,blockDim.x);
/* cal alliberar la memòria del dispositiu i del host */
hipFree(image_blue);
hipFree(image_green);
hipFree(image_red);
free(host_image_blue);
free(host_image_green);
free(host_image_red);
}
unsigned char* readBMP(const char* filename)
{
int i;
FILE* f = fopen(filename, "rb");
unsigned char info[54];
fread(info, sizeof(unsigned char), 54, f); // read the 54-byte header
// extract image height and width from header
int width = *(int*)&info[18];
int height = *(int*)&info[22];
int size = 3 * width * height;
unsigned char* data = new unsigned char[size]; // allocate 3 bytes per pixel
fread(data, sizeof(unsigned char), size, f); // read the rest of the data at once
fclose(f);
for(i = 0; i < size; i += 3)
{
unsigned char tmp = data[i];
data[i] = data[i+2];
data[i+2] = tmp;
}
return data;
}
int main(int argc, const char * argv[]) {
fes_cuda(5120, 5120);
fes_host(5120, 5120);
unsigned char *c , *h;
c = readBMP("output_cuda.bmp");
h = readBMP("output_host.bmp");
int errors =0;
int lengc = 5120*5120;
for(int i = 0 ; i < lengc;++i){
if(c[i] != h[i]){
errors++;
}
}
if(errors)printf("There are no difference,have %d errors\n",errors);
else printf("There are no difference\n");
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11mandel_cudaPcS_S_ii
.globl _Z11mandel_cudaPcS_S_ii
.p2align 8
.type _Z11mandel_cudaPcS_S_ii,@function
_Z11mandel_cudaPcS_S_ii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b64 s[4:5], s[0:1], 0x18
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_lshr_b32 s2, s2, 16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_4)
v_mad_u64_u32 v[0:1], null, s14, s3, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s2, v[3:4]
v_cvt_f32_i32_e32 v6, s4
v_cvt_f32_i32_e32 v8, s5
s_mov_b32 s3, 0
v_cvt_f32_i32_e32 v2, v0
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
v_cvt_f64_f32_e32 v[6:7], v6
v_cvt_f32_i32_e32 v4, v1
v_cvt_f64_f32_e32 v[8:9], v8
v_cvt_f64_f32_e32 v[2:3], v2
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cvt_f64_f32_e32 v[4:5], v4
v_mul_f64 v[2:3], v[2:3], 0x400c0000
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[4:5], v[4:5], v[4:5]
v_div_scale_f64 v[10:11], null, v[6:7], v[6:7], v[2:3]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_div_scale_f64 v[12:13], null, v[8:9], v[8:9], v[4:5]
v_div_scale_f64 v[22:23], vcc_lo, v[2:3], v[6:7], v[2:3]
v_rcp_f64_e32 v[14:15], v[10:11]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_rcp_f64_e32 v[16:17], v[12:13]
s_waitcnt_depctr 0xfff
v_fma_f64 v[18:19], -v[10:11], v[14:15], 1.0
v_fma_f64 v[20:21], -v[12:13], v[16:17], 1.0
v_fma_f64 v[14:15], v[14:15], v[18:19], v[14:15]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f64 v[16:17], v[16:17], v[20:21], v[16:17]
v_fma_f64 v[18:19], -v[10:11], v[14:15], 1.0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f64 v[20:21], -v[12:13], v[16:17], 1.0
v_fma_f64 v[14:15], v[14:15], v[18:19], v[14:15]
v_div_scale_f64 v[18:19], s2, v[4:5], v[8:9], v[4:5]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fma_f64 v[16:17], v[16:17], v[20:21], v[16:17]
v_mul_f64 v[20:21], v[22:23], v[14:15]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_f64 v[24:25], v[18:19], v[16:17]
v_fma_f64 v[10:11], -v[10:11], v[20:21], v[22:23]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f64 v[12:13], -v[12:13], v[24:25], v[18:19]
v_div_fmas_f64 v[10:11], v[10:11], v[14:15], v[20:21]
s_mov_b32 vcc_lo, s2
s_mov_b32 s2, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_div_fmas_f64 v[12:13], v[12:13], v[16:17], v[24:25]
v_div_fixup_f64 v[2:3], v[10:11], v[6:7], v[2:3]
v_dual_mov_b32 v7, 0 :: v_dual_mov_b32 v6, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_div_fixup_f64 v[4:5], v[12:13], v[8:9], v[4:5]
v_mov_b32_e32 v8, 0
v_add_f64 v[2:3], v[2:3], 0xc0040000
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[4:5], v[4:5], -1.0
v_cvt_f32_f64_e32 v2, v[2:3]
s_delay_alu instid0(VALU_DEP_2)
v_cvt_f32_f64_e32 v3, v[4:5]
v_mov_b32_e32 v5, 0
.p2align 6
.LBB0_1:
v_sub_f32_e32 v4, v6, v7
v_add_f32_e32 v6, v8, v8
s_add_i32 s5, s3, 1
s_cmpk_gt_u32 s3, 0xfe
s_cselect_b32 s3, -1, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v5, v5, v6, v3
v_dual_mul_f32 v7, v5, v5 :: v_dual_add_f32 v8, v4, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v6, v8, v8
v_fma_f32 v4, v5, v5, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_cmp_nge_f32_e32 vcc_lo, 4.0, v4
v_mov_b32_e32 v4, s5
s_or_b32 s3, vcc_lo, s3
s_and_b32 s3, exec_lo, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 s2, s3, s2
s_mov_b32 s3, s5
s_and_not1_b32 exec_lo, exec_lo, s2
s_cbranch_execnz .LBB0_1
s_or_b32 exec_lo, exec_lo, s2
s_clause 0x1
s_load_b128 s[8:11], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
v_mad_u64_u32 v[2:3], null, v1, s4, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v3, 31, v2
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s8, v2
v_add_co_ci_u32_e32 v1, vcc_lo, s9, v3, vcc_lo
v_add_co_u32 v5, vcc_lo, s10, v2
v_add_co_ci_u32_e32 v6, vcc_lo, s11, v3, vcc_lo
v_add_co_u32 v2, vcc_lo, s0, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
global_store_b8 v[0:1], v4, off
global_store_b8 v[5:6], v4, off
global_store_b8 v[2:3], v4, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11mandel_cudaPcS_S_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 26
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z11mandel_cudaPcS_S_ii, .Lfunc_end0-_Z11mandel_cudaPcS_S_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11mandel_cudaPcS_S_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z11mandel_cudaPcS_S_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 26
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <stdio.h>
#include <assert.h>
#include <stdlib.h>
#include <stdio.h>
#include <hip/hip_runtime.h>
#include <time.h>
struct BITMAPFILEHEADER
{
char bfType[2];
int bfSize;
int bfReserved;
int bfOffBits;
};
struct BITMAPINFOHEADER {
int biSize;
int biWidth;
int biHeight;
short biPlanes;
short biBitCount;
int biCompression;
int biSizeImage;
int biXPelsPerMeter;
int biYPelsPerMeter;
int biClrUsed;
int biClrImportant;
};
int write_bitmap(const char *filename, int width, int height, char *red, char *green, char *blue)
{
int bytes_per_line = (3 * (width + 1) / 4) * 4;
unsigned char *image_line = (unsigned char *)malloc(bytes_per_line);
struct BITMAPFILEHEADER bmph;
bmph.bfType[0] = 'B';
bmph.bfType[1] = 'M';
bmph.bfReserved = 0;
bmph.bfOffBits = 54;
bmph.bfSize = bmph.bfOffBits + bytes_per_line * height;
struct BITMAPINFOHEADER bmih;
bmih.biSize = 40;
bmih.biWidth = width;
bmih.biHeight = height;
bmih.biPlanes = 1;
bmih.biBitCount = 24;
bmih.biCompression = 0;
bmih.biSizeImage = bytes_per_line * height;
bmih.biXPelsPerMeter = 0;
bmih.biYPelsPerMeter = 0;
bmih.biClrUsed = 0;
bmih.biClrImportant = 0;
FILE *fit;
if((fit = fopen (filename, "wb"))==0) {
free(image_line);
return -1;
}
fwrite(&bmph.bfType, 2, 1, fit);
fwrite(&bmph.bfSize, 4, 1, fit);
fwrite(&bmph.bfReserved, 4, 1, fit);
fwrite(&bmph.bfOffBits, 4, 1, fit);
fwrite(&bmih.biSize, 4, 1, fit);
fwrite(&bmih.biWidth, 4, 1, fit);
fwrite(&bmih.biHeight, 4, 1, fit);
fwrite(&bmih.biPlanes, 2, 1, fit);
fwrite(&bmih.biBitCount, 2, 1, fit);
fwrite(&bmih.biCompression, 4, 1, fit);
fwrite(&bmih.biSizeImage, 4, 1, fit);
fwrite(&bmih.biXPelsPerMeter, 4, 1, fit);
fwrite(&bmih.biYPelsPerMeter, 4, 1, fit);
fwrite(&bmih.biClrUsed, 4, 1, fit);
fwrite(&bmih.biClrImportant, 4, 1, fit);
for(int i=height-1;i>=0;i--) {
for (int j=0;j<width;j++) {
int pos = (width * i + j);
image_line[3*j] = blue[pos];
image_line[3*j+1] = green[pos];
image_line[3*j+2] = red[pos];
}
fwrite((void *)image_line, bytes_per_line, 1, fit);
}
free(image_line);
fclose(fit);
return 0;
}
void mandel_host(char *red, char *green, char *blue, int width, int height)
{
for(int pos_x=0;pos_x<width;pos_x++) {
for(int pos_y=0;pos_y<height;pos_y++) {
float x0 = ((float)pos_x)*3.5/((float)width)-2.5;
float y0 = ((float)pos_y)*2.0/((float)height)-1.0;
float x = 0.0;
float y = 0.0;
int iteration = 0;
int max_iteration = 256;
while(x*x + y*y <= 4 && iteration < max_iteration) {
float xtemp = x*x - y*y + x0;
y = 2*x*y + y0;
x = xtemp;
iteration++;
}
int index = width*pos_y + pos_x;
if(iteration==max_iteration) {
iteration = 0;
}
red[index] = iteration;
green[index] = iteration;
blue[index] = iteration;
}
}
}
__global__ void mandel_cuda(char *red, char *green, char *blue, int width, int height)
{
/* kernel que calcula un pixel */
/* Per saber quin pixel és, cal tenir en compte totes les dimensions
del grid (el número de blocs i el número de threads */
/* Podeu fer servir els valors de
blockIdx.x, blockIdx.y
gridDim.x, gridDim.y
threadIdx.x, threadIdx.y
blockDim.x, blockDim.y */
int pos_x = threadIdx.x+blockDim.x*blockIdx.x;
int pos_y = threadIdx.y+blockDim.y*blockIdx.y;
float x0 = ((float)pos_x)*3.5/((float)width)-2.5;
float y0 = ((float)pos_y)*2.0/((float)height)-1.0;
float x = 0.0;
float y = 0.0;
int iteration = 0;
int max_iteration = 256;
while(x*x + y*y <= 4 && iteration < max_iteration) {
float xtemp = x*x - y*y + x0;
y = 2*x*y + y0;
x = xtemp;
iteration++;
}
int index = width*pos_y + pos_x;
if(iteration==max_iteration) {
iteration = 0;
}
red[index] = iteration;
green[index] = iteration;
blue[index] = iteration;
}
void fes_host(int width, int height)
{
size_t buffer_size = sizeof(char) * width * height;
char *image_red = (char *)malloc(buffer_size);
char *image_green = (char *)malloc(buffer_size);
char *image_blue = (char *)malloc(buffer_size);
mandel_host(image_red, image_green, image_blue, width, height);
// Now write the file
write_bitmap("output_host.bmp", width, height, image_red,
image_green, image_blue);
free(image_red);
free(image_green);
free(image_blue);
}
void fes_cuda(int width, int height)
{
size_t buffer_size = sizeof(char) * width * height;
char *image_red;
char *image_green;
char *image_blue;
hipMalloc((void**)&image_red, buffer_size);
hipMalloc((void**)&image_green, buffer_size);
hipMalloc((void**)&image_blue, buffer_size);
clock_t t_device = clock();
dim3 blockDim(6, 6,1);
dim3 gridDim(width / blockDim.x, height / blockDim.y,1);
mandel_cuda<<< gridDim, blockDim,0>>>(image_red, image_green, image_blue, width, height);
char *host_image_red = (char*)malloc(buffer_size);
char *host_image_green= (char*)malloc(buffer_size);
char *host_image_blue= (char*)malloc(buffer_size);
/* cal copiar els valors de la imatge al host */
hipMemcpy(host_image_red,image_red,buffer_size,hipMemcpyDeviceToHost);
hipMemcpy(host_image_green,image_green,buffer_size,hipMemcpyDeviceToHost);
hipMemcpy(host_image_blue,image_blue,buffer_size,hipMemcpyDeviceToHost);
// Now write the file
write_bitmap("output_cuda.bmp", width, height, host_image_red,
host_image_green, host_image_blue);
t_device = clock() - t_device;
double time_taken_device = ((double)t_device)/CLOCKS_PER_SEC;
printf("GPU %f segons with %d threats \n", time_taken_device,blockDim.x);
/* cal alliberar la memòria del dispositiu i del host */
hipFree(image_blue);
hipFree(image_green);
hipFree(image_red);
free(host_image_blue);
free(host_image_green);
free(host_image_red);
}
unsigned char* readBMP(const char* filename)
{
int i;
FILE* f = fopen(filename, "rb");
unsigned char info[54];
fread(info, sizeof(unsigned char), 54, f); // read the 54-byte header
// extract image height and width from header
int width = *(int*)&info[18];
int height = *(int*)&info[22];
int size = 3 * width * height;
unsigned char* data = new unsigned char[size]; // allocate 3 bytes per pixel
fread(data, sizeof(unsigned char), size, f); // read the rest of the data at once
fclose(f);
for(i = 0; i < size; i += 3)
{
unsigned char tmp = data[i];
data[i] = data[i+2];
data[i+2] = tmp;
}
return data;
}
int main(int argc, const char * argv[]) {
fes_cuda(5120, 5120);
fes_host(5120, 5120);
unsigned char *c , *h;
c = readBMP("output_cuda.bmp");
h = readBMP("output_host.bmp");
int errors =0;
int lengc = 5120*5120;
for(int i = 0 ; i < lengc;++i){
if(c[i] != h[i]){
errors++;
}
}
if(errors)printf("There are no difference,have %d errors\n",errors);
else printf("There are no difference\n");
return 0;
} | .text
.file "mandel.hip"
.globl _Z12write_bitmapPKciiPcS1_S1_ # -- Begin function _Z12write_bitmapPKciiPcS1_S1_
.p2align 4, 0x90
.type _Z12write_bitmapPKciiPcS1_S1_,@function
_Z12write_bitmapPKciiPcS1_S1_: # @_Z12write_bitmapPKciiPcS1_S1_
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $104, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %r9, %rbx
movq %r8, %r14
movq %rcx, %r15
movl %edx, %ebp
movl %esi, %r12d
movq %rdi, (%rsp) # 8-byte Spill
leal (%r12,%r12,2), %eax
addl $3, %eax
leal (%r12,%r12,2), %ecx
addl $6, %ecx
testl %eax, %eax
cmovnsl %eax, %ecx
andl $-4, %ecx
movslq %ecx, %r13
movq %r13, %rdi
callq malloc
movq %rax, 8(%rsp) # 8-byte Spill
movw $19778, 16(%rsp) # imm = 0x4D42
movabsq $231928233984, %rax # imm = 0x3600000000
movq %rax, 24(%rsp)
movq %r13, 96(%rsp) # 8-byte Spill
movl %r13d, %eax
imull %ebp, %eax
leal 54(%rax), %ecx
movl %ecx, 20(%rsp)
movl $40, 32(%rsp)
movq %r12, 72(%rsp) # 8-byte Spill
movl %r12d, 36(%rsp)
movl %ebp, 40(%rsp)
movq $1572865, 44(%rsp) # imm = 0x180001
movl %eax, 52(%rsp)
xorps %xmm0, %xmm0
movups %xmm0, 56(%rsp)
movl $.L.str, %esi
movq (%rsp), %rdi # 8-byte Reload
callq fopen
testq %rax, %rax
je .LBB0_1
# %bb.2:
movq %rax, %r12
leaq 68(%rsp), %r13
leaq 16(%rsp), %rdi
movl $2, %esi
movl $1, %edx
movq %rax, %rcx
callq fwrite
movl $4, %esi
movl $1, %edx
leaq 20(%rsp), %rdi
movq %r12, %rcx
callq fwrite
movl $4, %esi
movl $1, %edx
leaq 24(%rsp), %rdi
movq %r12, %rcx
callq fwrite
movl $4, %esi
movl $1, %edx
leaq 28(%rsp), %rdi
movq %r12, %rcx
callq fwrite
leaq 32(%rsp), %rdi
movl $4, %esi
movl $1, %edx
movq %r12, %rcx
callq fwrite
movl $4, %esi
movl $1, %edx
leaq 36(%rsp), %rdi
movq %r12, %rcx
callq fwrite
movl $4, %esi
movl $1, %edx
leaq 40(%rsp), %rdi
movq %r12, %rcx
callq fwrite
movl $2, %esi
movl $1, %edx
leaq 44(%rsp), %rdi
movq %r12, %rcx
callq fwrite
movl $2, %esi
movl $1, %edx
leaq 46(%rsp), %rdi
movq %r12, %rcx
callq fwrite
movl $4, %esi
movl $1, %edx
leaq 48(%rsp), %rdi
movq %r12, %rcx
callq fwrite
movl $4, %esi
movl $1, %edx
leaq 52(%rsp), %rdi
movq %r12, %rcx
callq fwrite
movl $4, %esi
movl $1, %edx
leaq 56(%rsp), %rdi
movq %r12, %rcx
callq fwrite
movl $4, %esi
movl $1, %edx
leaq 60(%rsp), %rdi
movq %r12, %rcx
callq fwrite
movl $4, %esi
movl $1, %edx
leaq 64(%rsp), %rdi
movq %r12, %rcx
callq fwrite
movl $4, %esi
movl $1, %edx
movq %r13, %rdi
movq %r12, (%rsp) # 8-byte Spill
movq %r12, %rcx
callq fwrite
testl %ebp, %ebp
jle .LBB0_8
# %bb.3: # %.preheader.lr.ph
movl %ebp, %ebp
movq 72(%rsp), %rax # 8-byte Reload
movslq %eax, %rcx
movl %eax, %r12d
movq 8(%rsp), %rax # 8-byte Reload
addq $2, %rax
movq %rax, 80(%rsp) # 8-byte Spill
leaq -1(%rbp), %rax
imulq %rcx, %rax
addq %rax, %rbx
negq %rcx
movq %rcx, 88(%rsp) # 8-byte Spill
addq %rax, %r14
addq %rax, %r15
jmp .LBB0_4
.p2align 4, 0x90
.LBB0_7: # %._crit_edge
# in Loop: Header=BB0_4 Depth=1
leaq -1(%rbp), %r13
movl $1, %edx
movq 8(%rsp), %rdi # 8-byte Reload
movq 96(%rsp), %rsi # 8-byte Reload
movq (%rsp), %rcx # 8-byte Reload
callq fwrite
movq 88(%rsp), %rax # 8-byte Reload
addq %rax, %rbx
addq %rax, %r14
addq %rax, %r15
cmpq $1, %rbp
movq %r13, %rbp
jle .LBB0_8
.LBB0_4: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB0_6 Depth 2
cmpl $0, 72(%rsp) # 4-byte Folded Reload
jle .LBB0_7
# %bb.5: # %.lr.ph
# in Loop: Header=BB0_4 Depth=1
movq 80(%rsp), %rax # 8-byte Reload
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB0_6: # Parent Loop BB0_4 Depth=1
# => This Inner Loop Header: Depth=2
movzbl (%rbx,%rcx), %edx
movb %dl, -2(%rax)
movzbl (%r14,%rcx), %edx
movb %dl, -1(%rax)
movzbl (%r15,%rcx), %edx
movb %dl, (%rax)
incq %rcx
addq $3, %rax
cmpq %rcx, %r12
jne .LBB0_6
jmp .LBB0_7
.LBB0_8: # %._crit_edge58
movq 8(%rsp), %rdi # 8-byte Reload
callq free
movq (%rsp), %rdi # 8-byte Reload
callq fclose
xorl %eax, %eax
jmp .LBB0_9
.LBB0_1:
movq 8(%rsp), %rdi # 8-byte Reload
callq free
movl $-1, %eax
.LBB0_9:
addq $104, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z12write_bitmapPKciiPcS1_S1_, .Lfunc_end0-_Z12write_bitmapPKciiPcS1_S1_
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z11mandel_hostPcS_S_ii
.LCPI1_0:
.quad 0x400c000000000000 # double 3.5
.LCPI1_1:
.quad 0xc004000000000000 # double -2.5
.LCPI1_2:
.quad 0xbff0000000000000 # double -1
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0
.LCPI1_3:
.long 0x40800000 # float 4
.text
.globl _Z11mandel_hostPcS_S_ii
.p2align 4, 0x90
.type _Z11mandel_hostPcS_S_ii,@function
_Z11mandel_hostPcS_S_ii: # @_Z11mandel_hostPcS_S_ii
.cfi_startproc
# %bb.0:
testl %ecx, %ecx
jle .LBB1_10
# %bb.1: # %.preheader.lr.ph
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
cvtsi2ss %ecx, %xmm0
cvtss2sd %xmm0, %xmm0
cvtsi2ss %r8d, %xmm1
cvtss2sd %xmm1, %xmm1
movl %ecx, %eax
movl %r8d, %ecx
xorl %r9d, %r9d
movsd .LCPI1_0(%rip), %xmm2 # xmm2 = mem[0],zero
movsd .LCPI1_1(%rip), %xmm3 # xmm3 = mem[0],zero
movsd .LCPI1_2(%rip), %xmm4 # xmm4 = mem[0],zero
movss .LCPI1_3(%rip), %xmm5 # xmm5 = mem[0],zero,zero,zero
jmp .LBB1_2
.p2align 4, 0x90
.LBB1_8: # %._crit_edge
# in Loop: Header=BB1_2 Depth=1
incq %r9
cmpq %rax, %r9
je .LBB1_9
.LBB1_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_4 Depth 2
# Child Loop BB1_5 Depth 3
testl %r8d, %r8d
jle .LBB1_8
# %bb.3: # %.lr.ph
# in Loop: Header=BB1_2 Depth=1
xorps %xmm6, %xmm6
cvtsi2ss %r9d, %xmm6
cvtss2sd %xmm6, %xmm6
mulsd %xmm2, %xmm6
divsd %xmm0, %xmm6
addsd %xmm3, %xmm6
cvtsd2ss %xmm6, %xmm6
xorl %r10d, %r10d
jmp .LBB1_4
.p2align 4, 0x90
.LBB1_7: # in Loop: Header=BB1_4 Depth=2
movq %r10, %r11
imulq %rax, %r11
addq %r9, %r11
movb %bl, (%rdi,%r11)
movb %bl, (%rsi,%r11)
movb %bl, (%rdx,%r11)
incq %r10
cmpq %rcx, %r10
je .LBB1_8
.LBB1_4: # Parent Loop BB1_2 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB1_5 Depth 3
xorps %xmm7, %xmm7
cvtsi2ss %r10d, %xmm7
cvtss2sd %xmm7, %xmm7
addsd %xmm7, %xmm7
divsd %xmm1, %xmm7
addsd %xmm4, %xmm7
cvtsd2ss %xmm7, %xmm7
xorl %r11d, %r11d
xorps %xmm10, %xmm10
xorps %xmm9, %xmm9
xorps %xmm8, %xmm8
xorps %xmm11, %xmm11
.p2align 4, 0x90
.LBB1_5: # Parent Loop BB1_2 Depth=1
# Parent Loop BB1_4 Depth=2
# => This Inner Loop Header: Depth=3
subss %xmm10, %xmm9
addss %xmm11, %xmm11
mulss %xmm11, %xmm8
movaps %xmm9, %xmm11
addss %xmm6, %xmm11
addss %xmm7, %xmm8
leal 1(%r11), %ebx
movaps %xmm11, %xmm9
mulss %xmm11, %xmm9
movaps %xmm8, %xmm10
mulss %xmm8, %xmm10
movaps %xmm9, %xmm12
addss %xmm10, %xmm12
ucomiss %xmm12, %xmm5
jb .LBB1_7
# %bb.6: # in Loop: Header=BB1_5 Depth=3
cmpl $255, %r11d
movl %ebx, %r11d
jb .LBB1_5
jmp .LBB1_7
.LBB1_9:
popq %rbx
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.LBB1_10: # %._crit_edge50
retq
.Lfunc_end1:
.size _Z11mandel_hostPcS_S_ii, .Lfunc_end1-_Z11mandel_hostPcS_S_ii
.cfi_endproc
# -- End function
.globl _Z26__device_stub__mandel_cudaPcS_S_ii # -- Begin function _Z26__device_stub__mandel_cudaPcS_S_ii
.p2align 4, 0x90
.type _Z26__device_stub__mandel_cudaPcS_S_ii,@function
_Z26__device_stub__mandel_cudaPcS_S_ii: # @_Z26__device_stub__mandel_cudaPcS_S_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z11mandel_cudaPcS_S_ii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end2:
.size _Z26__device_stub__mandel_cudaPcS_S_ii, .Lfunc_end2-_Z26__device_stub__mandel_cudaPcS_S_ii
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z8fes_hostii
.LCPI3_0:
.quad 0x400c000000000000 # double 3.5
.LCPI3_1:
.quad 0xc004000000000000 # double -2.5
.LCPI3_2:
.quad 0xbff0000000000000 # double -1
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0
.LCPI3_3:
.long 0x40800000 # float 4
.text
.globl _Z8fes_hostii
.p2align 4, 0x90
.type _Z8fes_hostii,@function
_Z8fes_hostii: # @_Z8fes_hostii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
pushq %rax
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %esi, %ebx
movl %edi, %ebp
movslq %edi, %r13
movslq %esi, %r12
imulq %r13, %r12
movq %r12, %rdi
callq malloc
movq %rax, %r14
movq %r12, %rdi
callq malloc
movq %rax, %r15
movq %r12, %rdi
callq malloc
movq %rax, %r12
testl %r13d, %r13d
jle .LBB3_9
# %bb.1: # %.preheader.lr.ph.i
cvtsi2ss %ebp, %xmm0
cvtss2sd %xmm0, %xmm0
cvtsi2ss %ebx, %xmm1
cvtss2sd %xmm1, %xmm1
movl %ebp, %eax
movl %ebx, %ecx
xorl %edx, %edx
movsd .LCPI3_0(%rip), %xmm2 # xmm2 = mem[0],zero
movsd .LCPI3_1(%rip), %xmm3 # xmm3 = mem[0],zero
movsd .LCPI3_2(%rip), %xmm4 # xmm4 = mem[0],zero
movss .LCPI3_3(%rip), %xmm5 # xmm5 = mem[0],zero,zero,zero
jmp .LBB3_2
.p2align 4, 0x90
.LBB3_8: # %._crit_edge.i
# in Loop: Header=BB3_2 Depth=1
incq %rdx
cmpq %rax, %rdx
je .LBB3_9
.LBB3_2: # %.preheader.i
# =>This Loop Header: Depth=1
# Child Loop BB3_4 Depth 2
# Child Loop BB3_5 Depth 3
testl %ebx, %ebx
jle .LBB3_8
# %bb.3: # %.lr.ph.i
# in Loop: Header=BB3_2 Depth=1
xorps %xmm6, %xmm6
cvtsi2ss %edx, %xmm6
cvtss2sd %xmm6, %xmm6
mulsd %xmm2, %xmm6
divsd %xmm0, %xmm6
addsd %xmm3, %xmm6
cvtsd2ss %xmm6, %xmm6
xorl %esi, %esi
jmp .LBB3_4
.p2align 4, 0x90
.LBB3_7: # in Loop: Header=BB3_4 Depth=2
movq %rsi, %rdi
imulq %rax, %rdi
addq %rdx, %rdi
movb %r8b, (%r14,%rdi)
movb %r8b, (%r15,%rdi)
movb %r8b, (%r12,%rdi)
incq %rsi
cmpq %rcx, %rsi
je .LBB3_8
.LBB3_4: # Parent Loop BB3_2 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB3_5 Depth 3
xorps %xmm7, %xmm7
cvtsi2ss %esi, %xmm7
cvtss2sd %xmm7, %xmm7
addsd %xmm7, %xmm7
divsd %xmm1, %xmm7
addsd %xmm4, %xmm7
cvtsd2ss %xmm7, %xmm7
xorl %edi, %edi
xorps %xmm10, %xmm10
xorps %xmm9, %xmm9
xorps %xmm8, %xmm8
xorps %xmm11, %xmm11
.p2align 4, 0x90
.LBB3_5: # Parent Loop BB3_2 Depth=1
# Parent Loop BB3_4 Depth=2
# => This Inner Loop Header: Depth=3
subss %xmm10, %xmm9
addss %xmm11, %xmm11
mulss %xmm11, %xmm8
movaps %xmm9, %xmm11
addss %xmm6, %xmm11
addss %xmm7, %xmm8
leal 1(%rdi), %r8d
movaps %xmm11, %xmm9
mulss %xmm11, %xmm9
movaps %xmm8, %xmm10
mulss %xmm8, %xmm10
movaps %xmm9, %xmm12
addss %xmm10, %xmm12
ucomiss %xmm12, %xmm5
jb .LBB3_7
# %bb.6: # in Loop: Header=BB3_5 Depth=3
cmpl $255, %edi
movl %r8d, %edi
jb .LBB3_5
jmp .LBB3_7
.LBB3_9: # %_Z11mandel_hostPcS_S_ii.exit
movl $.L.str.1, %edi
movl %ebp, %esi
movl %ebx, %edx
movq %r14, %rcx
movq %r15, %r8
movq %r12, %r9
callq _Z12write_bitmapPKciiPcS1_S1_
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
movq %r12, %rdi
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
jmp free # TAILCALL
.Lfunc_end3:
.size _Z8fes_hostii, .Lfunc_end3-_Z8fes_hostii
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z8fes_cudaii
.LCPI4_0:
.quad 0x412e848000000000 # double 1.0E+6
.text
.globl _Z8fes_cudaii
.p2align 4, 0x90
.type _Z8fes_cudaii,@function
_Z8fes_cudaii: # @_Z8fes_cudaii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $152, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %esi, %ebx
movl %edi, %ebp
movslq %edi, %r12
movslq %esi, %r15
movq %r15, %r14
imulq %r12, %r14
leaq 16(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
leaq 8(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
movq %rsp, %rdi
movq %r14, %rsi
callq hipMalloc
callq clock
movq %rax, 32(%rsp) # 8-byte Spill
movl %r12d, %eax
movl $2863311531, %ecx # imm = 0xAAAAAAAB
imulq %rcx, %rax
shrq $34, %rax
movl %r15d, %edx
imulq %rcx, %rdx
shrq $2, %rdx
movabsq $4611686014132420608, %rdi # imm = 0x3FFFFFFF00000000
andq %rdx, %rdi
orq %rax, %rdi
movabsq $25769803782, %rdx # imm = 0x600000006
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_2
# %bb.1:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq (%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
movl %ebp, 28(%rsp)
movl %ebx, 24(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 28(%rsp), %rax
movq %rax, 136(%rsp)
leaq 24(%rsp), %rax
movq %rax, 144(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z11mandel_cudaPcS_S_ii, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_2:
movq %r14, %rdi
callq malloc
movq %rax, %r12
movq %r14, %rdi
callq malloc
movq %rax, %r13
movq %r14, %rdi
callq malloc
movq %rax, %r15
movq 16(%rsp), %rsi
movq %r12, %rdi
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
movq 8(%rsp), %rsi
movq %r13, %rdi
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
movq (%rsp), %rsi
movq %r15, %rdi
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
movl $.L.str.2, %edi
movl %ebp, %esi
movl %ebx, %edx
movq %r12, %rcx
movq %r13, %r8
movq %r15, %r9
callq _Z12write_bitmapPKciiPcS1_S1_
callq clock
subq 32(%rsp), %rax # 8-byte Folded Reload
cvtsi2sd %rax, %xmm0
divsd .LCPI4_0(%rip), %xmm0
movl $.L.str.3, %edi
movl $6, %esi
movb $1, %al
callq printf
movq (%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq %r15, %rdi
callq free
movq %r13, %rdi
callq free
movq %r12, %rdi
callq free
addq $152, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end4:
.size _Z8fes_cudaii, .Lfunc_end4-_Z8fes_cudaii
.cfi_endproc
# -- End function
.globl _Z7readBMPPKc # -- Begin function _Z7readBMPPKc
.p2align 4, 0x90
.type _Z7readBMPPKc,@function
_Z7readBMPPKc: # @_Z7readBMPPKc
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $64, %rsp
.cfi_def_cfa_offset 96
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $.L.str.4, %esi
callq fopen
movq %rax, %r14
movq %rsp, %rdi
movl $1, %esi
movl $54, %edx
movq %rax, %rcx
callq fread
movslq 18(%rsp), %rax
movslq 22(%rsp), %rcx
imulq %rax, %rcx
leaq (%rcx,%rcx,2), %r15
movq %r15, %rdi
callq _Znam
movq %rax, %rbx
movl $1, %esi
movq %rax, %rdi
movq %r15, %rdx
movq %r14, %rcx
callq fread
movq %r14, %rdi
callq fclose
testl %r15d, %r15d
jle .LBB5_3
# %bb.1: # %.lr.ph.preheader
movl %r15d, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB5_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movzbl (%rbx,%rcx), %edx
movzbl 2(%rbx,%rcx), %esi
movb %sil, (%rbx,%rcx)
movb %dl, 2(%rbx,%rcx)
addq $3, %rcx
cmpq %rax, %rcx
jb .LBB5_2
.LBB5_3: # %._crit_edge
movq %rbx, %rax
addq $64, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end5:
.size _Z7readBMPPKc, .Lfunc_end5-_Z7readBMPPKc
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
movl $5120, %edi # imm = 0x1400
movl $5120, %esi # imm = 0x1400
callq _Z8fes_cudaii
movl $5120, %edi # imm = 0x1400
movl $5120, %esi # imm = 0x1400
callq _Z8fes_hostii
movl $.L.str.2, %edi
callq _Z7readBMPPKc
movq %rax, %rbx
movl $.L.str.1, %edi
callq _Z7readBMPPKc
xorl %ecx, %ecx
xorl %esi, %esi
.p2align 4, 0x90
.LBB6_1: # =>This Inner Loop Header: Depth=1
movzbl (%rbx,%rcx), %edx
xorl %edi, %edi
cmpb (%rax,%rcx), %dl
setne %dil
addl %edi, %esi
incq %rcx
cmpq $26214400, %rcx # imm = 0x1900000
jne .LBB6_1
# %bb.2:
testl %esi, %esi
je .LBB6_4
# %bb.3:
movl $.L.str.5, %edi
xorl %eax, %eax
callq printf
jmp .LBB6_5
.LBB6_4:
movl $.Lstr, %edi
callq puts@PLT
.LBB6_5:
xorl %eax, %eax
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end6:
.size main, .Lfunc_end6-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB7_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB7_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11mandel_cudaPcS_S_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end7:
.size __hip_module_ctor, .Lfunc_end7-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB8_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB8_2:
retq
.Lfunc_end8:
.size __hip_module_dtor, .Lfunc_end8-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "wb"
.size .L.str, 3
.type _Z11mandel_cudaPcS_S_ii,@object # @_Z11mandel_cudaPcS_S_ii
.section .rodata,"a",@progbits
.globl _Z11mandel_cudaPcS_S_ii
.p2align 3, 0x0
_Z11mandel_cudaPcS_S_ii:
.quad _Z26__device_stub__mandel_cudaPcS_S_ii
.size _Z11mandel_cudaPcS_S_ii, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "output_host.bmp"
.size .L.str.1, 16
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "output_cuda.bmp"
.size .L.str.2, 16
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "GPU %f segons with %d threats \n"
.size .L.str.3, 32
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "rb"
.size .L.str.4, 3
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "There are no difference,have %d errors\n"
.size .L.str.5, 40
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z11mandel_cudaPcS_S_ii"
.size .L__unnamed_1, 24
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "There are no difference"
.size .Lstr, 24
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__mandel_cudaPcS_S_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11mandel_cudaPcS_S_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z11mandel_cudaPcS_S_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ I2F R2, c[0x0][0x178] ; /* 0x00005e0000027b06 */
/* 0x000e220000201400 */
/*0020*/ S2R R11, SR_CTAID.X ; /* 0x00000000000b7919 */
/* 0x000e620000002500 */
/*0030*/ IMAD.MOV.U32 R6, RZ, RZ, 0x1 ; /* 0x00000001ff067424 */
/* 0x000fe200078e00ff */
/*0040*/ BSSY B0, 0x200 ; /* 0x000001b000007945 */
/* 0x000fe40003800000 */
/*0050*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e680000002100 */
/*0060*/ S2R R10, SR_CTAID.Y ; /* 0x00000000000a7919 */
/* 0x000ea80000002600 */
/*0070*/ S2R R15, SR_TID.Y ; /* 0x00000000000f7919 */
/* 0x000ea20000002200 */
/*0080*/ F2F.F64.F32 R2, R2 ; /* 0x0000000200027310 */
/* 0x001e220000201800 */
/*0090*/ IMAD R11, R11, c[0x0][0x0], R0 ; /* 0x000000000b0b7a24 */
/* 0x002fce00078e0200 */
/*00a0*/ MUFU.RCP64H R7, R3 ; /* 0x0000000300077308 */
/* 0x001e300000001800 */
/*00b0*/ I2F R0, R11 ; /* 0x0000000b00007306 */
/* 0x000e620000201400 */
/*00c0*/ DFMA R4, -R2, R6, 1 ; /* 0x3ff000000204742b */
/* 0x001e0c0000000106 */
/*00d0*/ DFMA R8, R4, R4, R4 ; /* 0x000000040408722b */
/* 0x0012080000000004 */
/*00e0*/ F2F.F64.F32 R4, R0 ; /* 0x0000000000047310 */
/* 0x0024640000201800 */
/*00f0*/ DFMA R8, R6, R8, R6 ; /* 0x000000080608722b */
/* 0x001e0c0000000006 */
/*0100*/ DFMA R12, -R2, R8, 1 ; /* 0x3ff00000020c742b */
/* 0x001e220000000108 */
/*0110*/ IMAD R0, R10, c[0x0][0x4], R15 ; /* 0x000001000a007a24 */
/* 0x004fca00078e020f */
/*0120*/ DFMA R12, R8, R12, R8 ; /* 0x0000000c080c722b */
/* 0x001fc80000000008 */
/*0130*/ DMUL R6, R4, 3.5 ; /* 0x400c000004067828 */
/* 0x002e0c0000000000 */
/*0140*/ DMUL R4, R6, R12 ; /* 0x0000000c06047228 */
/* 0x001e080000000000 */
/*0150*/ FSETP.GEU.AND P1, PT, |R7|, 6.5827683646048100446e-37, PT ; /* 0x036000000700780b */
/* 0x000fe40003f2e200 */
/*0160*/ DFMA R8, -R2, R4, R6 ; /* 0x000000040208722b */
/* 0x001e0c0000000106 */
/*0170*/ DFMA R4, R12, R8, R4 ; /* 0x000000080c04722b */
/* 0x001e140000000004 */
/*0180*/ FFMA R8, RZ, R3, R5 ; /* 0x00000003ff087223 */
/* 0x001fca0000000005 */
/*0190*/ FSETP.GT.AND P0, PT, |R8|, 1.469367938527859385e-39, PT ; /* 0x001000000800780b */
/* 0x000fda0003f04200 */
/*01a0*/ @P0 BRA P1, 0x1f0 ; /* 0x0000004000000947 */
/* 0x000fea0000800000 */
/*01b0*/ IMAD.MOV.U32 R8, RZ, RZ, R6 ; /* 0x000000ffff087224 */
/* 0x000fe200078e0006 */
/*01c0*/ MOV R12, 0x1f0 ; /* 0x000001f0000c7802 */
/* 0x000fe20000000f00 */
/*01d0*/ IMAD.MOV.U32 R9, RZ, RZ, R7 ; /* 0x000000ffff097224 */
/* 0x000fe400078e0007 */
/*01e0*/ CALL.REL.NOINC 0x5e0 ; /* 0x000003f000007944 */
/* 0x000fea0003c00000 */
/*01f0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0200*/ I2F R2, c[0x0][0x17c] ; /* 0x00005f0000027b06 */
/* 0x000e220000201400 */
/*0210*/ IMAD.MOV.U32 R8, RZ, RZ, 0x1 ; /* 0x00000001ff087424 */
/* 0x000fe200078e00ff */
/*0220*/ DADD R4, R4, -2.5 ; /* 0xc004000004047429 */
/* 0x000ea20000000000 */
/*0230*/ BSSY B0, 0x3d0 ; /* 0x0000019000007945 */
/* 0x000fea0003800000 */
/*0240*/ I2F R16, R0 ; /* 0x0000000000107306 */
/* 0x002ff00000201400 */
/*0250*/ F2F.F64.F32 R2, R2 ; /* 0x0000000200027310 */
/* 0x001e300000201800 */
/*0260*/ F2F.F32.F64 R10, R4 ; /* 0x00000004000a7310 */
/* 0x004ff00000301000 */
/*0270*/ MUFU.RCP64H R9, R3 ; /* 0x0000000300097308 */
/* 0x001e240000001800 */
/*0280*/ DFMA R6, -R2, R8, 1 ; /* 0x3ff000000206742b */
/* 0x001e0c0000000108 */
/*0290*/ DFMA R12, R6, R6, R6 ; /* 0x00000006060c722b */
/* 0x0010480000000006 */
/*02a0*/ F2F.F64.F32 R6, R16 ; /* 0x0000001000067310 */
/* 0x001e240000201800 */
/*02b0*/ DFMA R12, R8, R12, R8 ; /* 0x0000000c080c722b */
/* 0x002e4c0000000008 */
/*02c0*/ DFMA R8, -R2, R12, 1 ; /* 0x3ff000000208742b */
/* 0x002e4c000000010c */
/*02d0*/ DFMA R8, R12, R8, R12 ; /* 0x000000080c08722b */
/* 0x002fc8000000000c */
/*02e0*/ DADD R6, R6, R6 ; /* 0x0000000006067229 */
/* 0x001e0c0000000006 */
/*02f0*/ DMUL R12, R6, R8 ; /* 0x00000008060c7228 */
/* 0x001e080000000000 */
/*0300*/ FSETP.GEU.AND P1, PT, |R7|, 6.5827683646048100446e-37, PT ; /* 0x036000000700780b */
/* 0x000fe40003f2e200 */
/*0310*/ DFMA R14, -R2, R12, R6 ; /* 0x0000000c020e722b */
/* 0x001e0c0000000106 */
/*0320*/ DFMA R8, R8, R14, R12 ; /* 0x0000000e0808722b */
/* 0x001e14000000000c */
/*0330*/ FFMA R12, RZ, R3, R9 ; /* 0x00000003ff0c7223 */
/* 0x001fca0000000009 */
/*0340*/ FSETP.GT.AND P0, PT, |R12|, 1.469367938527859385e-39, PT ; /* 0x001000000c00780b */
/* 0x000fda0003f04200 */
/*0350*/ @P0 BRA P1, 0x3c0 ; /* 0x0000006000000947 */
/* 0x000fea0000800000 */
/*0360*/ IMAD.MOV.U32 R8, RZ, RZ, R6 ; /* 0x000000ffff087224 */
/* 0x000fe200078e0006 */
/*0370*/ MOV R12, 0x3a0 ; /* 0x000003a0000c7802 */
/* 0x000fe20000000f00 */
/*0380*/ IMAD.MOV.U32 R9, RZ, RZ, R7 ; /* 0x000000ffff097224 */
/* 0x000fe400078e0007 */
/*0390*/ CALL.REL.NOINC 0x5e0 ; /* 0x0000024000007944 */
/* 0x000fea0003c00000 */
/*03a0*/ IMAD.MOV.U32 R8, RZ, RZ, R4 ; /* 0x000000ffff087224 */
/* 0x000fe400078e0004 */
/*03b0*/ IMAD.MOV.U32 R9, RZ, RZ, R5 ; /* 0x000000ffff097224 */
/* 0x000fe400078e0005 */
/*03c0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*03d0*/ DADD R8, R8, -1 ; /* 0xbff0000008087429 */
/* 0x000e220000000000 */
/*03e0*/ BSSY B0, 0x500 ; /* 0x0000011000007945 */
/* 0x000fe20003800000 */
/*03f0*/ CS2R R2, SRZ ; /* 0x0000000000027805 */
/* 0x000fe2000001ff00 */
/*0400*/ IMAD.MOV.U32 R12, RZ, RZ, RZ ; /* 0x000000ffff0c7224 */
/* 0x000fe200078e00ff */
/*0410*/ CS2R R4, SRZ ; /* 0x0000000000047805 */
/* 0x000fe2000001ff00 */
/*0420*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fca0000000a00 */
/*0430*/ F2F.F32.F64 R8, R8 ; /* 0x0000000800087310 */
/* 0x0010a40000301000 */
/*0440*/ FADD R3, R3, -R2 ; /* 0x8000000203037221 */
/* 0x000fe20000000000 */
/*0450*/ IADD3 R12, R12, 0x1, RZ ; /* 0x000000010c0c7810 */
/* 0x000fe20007ffe0ff */
/*0460*/ FADD R7, R5, R5 ; /* 0x0000000505077221 */
/* 0x000fe40000000000 */
/*0470*/ FADD R5, R10, R3 ; /* 0x000000030a057221 */
/* 0x000fe20000000000 */
/*0480*/ ISETP.GE.U32.AND P0, PT, R12, 0x100, PT ; /* 0x000001000c00780c */
/* 0x000fe20003f06070 */
/*0490*/ FFMA R4, R7, R4, R8 ; /* 0x0000000407047223 */
/* 0x004fe40000000008 */
/*04a0*/ FMUL R3, R5, R5 ; /* 0x0000000505037220 */
/* 0x000fe40000400000 */
/*04b0*/ FMUL R2, R4, R4 ; /* 0x0000000404027220 */
/* 0x000fc80000400000 */
/*04c0*/ FADD R6, R3, R2 ; /* 0x0000000203067221 */
/* 0x000fca0000000000 */
/*04d0*/ FSETP.LE.AND P1, PT, R6, 4, PT ; /* 0x408000000600780b */
/* 0x000fda0003f23000 */
/*04e0*/ @!P0 BRA P1, 0x440 ; /* 0xffffff5000008947 */
/* 0x000fea000083ffff */
/*04f0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0500*/ IMAD R0, R0, c[0x0][0x178], R11 ; /* 0x00005e0000007a24 */
/* 0x000fe200078e020b */
/*0510*/ ISETP.NE.AND P0, PT, R12, 0x100, PT ; /* 0x000001000c00780c */
/* 0x000fc80003f05270 */
/*0520*/ SHF.R.S32.HI R7, RZ, 0x1f, R0 ; /* 0x0000001fff077819 */
/* 0x000fe40000011400 */
/*0530*/ IADD3 R2, P1, R0.reuse, c[0x0][0x160], RZ ; /* 0x0000580000027a10 */
/* 0x040fe40007f3e0ff */
/*0540*/ IADD3 R4, P2, R0.reuse, c[0x0][0x168], RZ ; /* 0x00005a0000047a10 */
/* 0x040fe40007f5e0ff */
/*0550*/ IADD3 R6, P3, R0, c[0x0][0x170], RZ ; /* 0x00005c0000067a10 */
/* 0x000fe40007f7e0ff */
/*0560*/ IADD3.X R3, R7, c[0x0][0x164], RZ, P1, !PT ; /* 0x0000590007037a10 */
/* 0x000fe40000ffe4ff */
/*0570*/ SEL R9, R12, RZ, P0 ; /* 0x000000ff0c097207 */
/* 0x001fc40000000000 */
/*0580*/ IADD3.X R5, R7.reuse, c[0x0][0x16c], RZ, P2, !PT ; /* 0x00005b0007057a10 */
/* 0x040fe400017fe4ff */
/*0590*/ IADD3.X R7, R7, c[0x0][0x174], RZ, P3, !PT ; /* 0x00005d0007077a10 */
/* 0x000fe20001ffe4ff */
/*05a0*/ STG.E.U8 [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x000fe8000c101104 */
/*05b0*/ STG.E.U8 [R4.64], R9 ; /* 0x0000000904007986 */
/* 0x000fe8000c101104 */
/*05c0*/ STG.E.U8 [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101104 */
/*05d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*05e0*/ FSETP.GEU.AND P0, PT, |R3|.reuse, 1.469367938527859385e-39, PT ; /* 0x001000000300780b */
/* 0x040fe20003f0e200 */
/*05f0*/ IMAD.MOV.U32 R6, RZ, RZ, R2.reuse ; /* 0x000000ffff067224 */
/* 0x100fe200078e0002 */
/*0600*/ LOP3.LUT R4, R3, 0x800fffff, RZ, 0xc0, !PT ; /* 0x800fffff03047812 */
/* 0x000fe200078ec0ff */
/*0610*/ IMAD.MOV.U32 R7, RZ, RZ, R3 ; /* 0x000000ffff077224 */
/* 0x000fe200078e0003 */
/*0620*/ FSETP.GEU.AND P2, PT, |R9|.reuse, 1.469367938527859385e-39, PT ; /* 0x001000000900780b */
/* 0x040fe20003f4e200 */
/*0630*/ IMAD.MOV.U32 R14, RZ, RZ, 0x1ca00000 ; /* 0x1ca00000ff0e7424 */
/* 0x000fe200078e00ff */
/*0640*/ LOP3.LUT R5, R4, 0x3ff00000, RZ, 0xfc, !PT ; /* 0x3ff0000004057812 */
/* 0x000fe200078efcff */
/*0650*/ IMAD.MOV.U32 R4, RZ, RZ, R2 ; /* 0x000000ffff047224 */
/* 0x000fe200078e0002 */
/*0660*/ LOP3.LUT R13, R9, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff00000090d7812 */
/* 0x000fe200078ec0ff */
/*0670*/ IMAD.MOV.U32 R18, RZ, RZ, 0x1 ; /* 0x00000001ff127424 */
/* 0x000fe200078e00ff */
/*0680*/ LOP3.LUT R20, R3, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff0000003147812 */
/* 0x000fe200078ec0ff */
/*0690*/ BSSY B1, 0xba0 ; /* 0x0000050000017945 */
/* 0x000fe40003800000 */
/*06a0*/ @!P0 DMUL R4, R6, 8.98846567431157953865e+307 ; /* 0x7fe0000006048828 */
/* 0x000e220000000000 */
/*06b0*/ ISETP.GE.U32.AND P1, PT, R13, R20, PT ; /* 0x000000140d00720c */
/* 0x000fc60003f26070 */
/*06c0*/ @!P2 LOP3.LUT R2, R7, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff000000702a812 */
/* 0x000fe200078ec0ff */
/*06d0*/ @!P2 IMAD.MOV.U32 R16, RZ, RZ, RZ ; /* 0x000000ffff10a224 */
/* 0x000fe200078e00ff */
/*06e0*/ MUFU.RCP64H R19, R5 ; /* 0x0000000500137308 */
/* 0x001e220000001800 */
/*06f0*/ SEL R3, R14.reuse, 0x63400000, !P1 ; /* 0x634000000e037807 */
/* 0x040fe40004800000 */
/*0700*/ @!P2 ISETP.GE.U32.AND P3, PT, R13, R2, PT ; /* 0x000000020d00a20c */
/* 0x000fe20003f66070 */
/*0710*/ IMAD.MOV.U32 R2, RZ, RZ, R8 ; /* 0x000000ffff027224 */
/* 0x000fe200078e0008 */
/*0720*/ LOP3.LUT R3, R3, 0x800fffff, R9, 0xf8, !PT ; /* 0x800fffff03037812 */
/* 0x000fe400078ef809 */
/*0730*/ @!P2 SEL R15, R14, 0x63400000, !P3 ; /* 0x634000000e0fa807 */
/* 0x000fc80005800000 */
/*0740*/ @!P2 LOP3.LUT R15, R15, 0x80000000, R9, 0xf8, !PT ; /* 0x800000000f0fa812 */
/* 0x000fc800078ef809 */
/*0750*/ @!P2 LOP3.LUT R17, R15, 0x100000, RZ, 0xfc, !PT ; /* 0x001000000f11a812 */
/* 0x000fe200078efcff */
/*0760*/ DFMA R22, R18, -R4, 1 ; /* 0x3ff000001216742b */
/* 0x001e220000000804 */
/*0770*/ IMAD.MOV.U32 R15, RZ, RZ, R13 ; /* 0x000000ffff0f7224 */
/* 0x000fc800078e000d */
/*0780*/ @!P2 DFMA R2, R2, 2, -R16 ; /* 0x400000000202a82b */
/* 0x000fc80000000810 */
/*0790*/ DFMA R22, R22, R22, R22 ; /* 0x000000161616722b */
/* 0x001e0c0000000016 */
/*07a0*/ DFMA R18, R18, R22, R18 ; /* 0x000000161212722b */
/* 0x0010620000000012 */
/*07b0*/ @!P2 LOP3.LUT R15, R3, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff00000030fa812 */
/* 0x000fe200078ec0ff */
/*07c0*/ IMAD.MOV.U32 R22, RZ, RZ, R20 ; /* 0x000000ffff167224 */
/* 0x001fe200078e0014 */
/*07d0*/ @!P0 LOP3.LUT R22, R5, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff0000005168812 */
/* 0x000fe400078ec0ff */
/*07e0*/ IADD3 R20, R15, -0x1, RZ ; /* 0xffffffff0f147810 */
/* 0x000fe20007ffe0ff */
/*07f0*/ DFMA R16, R18, -R4, 1 ; /* 0x3ff000001210742b */
/* 0x002e220000000804 */
/*0800*/ IADD3 R23, R22, -0x1, RZ ; /* 0xffffffff16177810 */
/* 0x000fe40007ffe0ff */
/*0810*/ ISETP.GT.U32.AND P0, PT, R20, 0x7feffffe, PT ; /* 0x7feffffe1400780c */
/* 0x000fc60003f04070 */
/*0820*/ DFMA R16, R18, R16, R18 ; /* 0x000000101210722b */
/* 0x001e220000000012 */
/*0830*/ ISETP.GT.U32.OR P0, PT, R23, 0x7feffffe, P0 ; /* 0x7feffffe1700780c */
/* 0x000fca0000704470 */
/*0840*/ DMUL R18, R16, R2 ; /* 0x0000000210127228 */
/* 0x001e0c0000000000 */
/*0850*/ DFMA R20, R18, -R4, R2 ; /* 0x800000041214722b */
/* 0x001e0c0000000002 */
/*0860*/ DFMA R16, R16, R20, R18 ; /* 0x000000141010722b */
/* 0x0010620000000012 */
/*0870*/ @P0 BRA 0xa40 ; /* 0x000001c000000947 */
/* 0x000fea0003800000 */
/*0880*/ LOP3.LUT R18, R7, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff0000007127812 */
/* 0x001fc800078ec0ff */
/*0890*/ ISETP.GE.U32.AND P0, PT, R13.reuse, R18, PT ; /* 0x000000120d00720c */
/* 0x040fe20003f06070 */
/*08a0*/ IMAD.IADD R8, R13, 0x1, -R18 ; /* 0x000000010d087824 */
/* 0x000fc600078e0a12 */
/*08b0*/ SEL R13, R14, 0x63400000, !P0 ; /* 0x634000000e0d7807 */
/* 0x000fe40004000000 */
/*08c0*/ IMNMX R8, R8, -0x46a00000, !PT ; /* 0xb960000008087817 */
/* 0x000fc80007800200 */
/*08d0*/ IMNMX R8, R8, 0x46a00000, PT ; /* 0x46a0000008087817 */
/* 0x000fca0003800200 */
/*08e0*/ IMAD.IADD R13, R8, 0x1, -R13 ; /* 0x00000001080d7824 */
/* 0x000fe400078e0a0d */
/*08f0*/ IMAD.MOV.U32 R8, RZ, RZ, RZ ; /* 0x000000ffff087224 */
/* 0x000fc600078e00ff */
/*0900*/ IADD3 R9, R13, 0x7fe00000, RZ ; /* 0x7fe000000d097810 */
/* 0x000fcc0007ffe0ff */
/*0910*/ DMUL R18, R16, R8 ; /* 0x0000000810127228 */
/* 0x002e140000000000 */
/*0920*/ FSETP.GTU.AND P0, PT, |R19|, 1.469367938527859385e-39, PT ; /* 0x001000001300780b */
/* 0x001fda0003f0c200 */
/*0930*/ @P0 BRA 0xb90 ; /* 0x0000025000000947 */
/* 0x000fea0003800000 */
/*0940*/ DFMA R2, R16, -R4, R2 ; /* 0x800000041002722b */
/* 0x000e220000000002 */
/*0950*/ IMAD.MOV.U32 R8, RZ, RZ, RZ ; /* 0x000000ffff087224 */
/* 0x000fd200078e00ff */
/*0960*/ FSETP.NEU.AND P0, PT, R3.reuse, RZ, PT ; /* 0x000000ff0300720b */
/* 0x041fe40003f0d000 */
/*0970*/ LOP3.LUT R7, R3, 0x80000000, R7, 0x48, !PT ; /* 0x8000000003077812 */
/* 0x000fc800078e4807 */
/*0980*/ LOP3.LUT R9, R7, R9, RZ, 0xfc, !PT ; /* 0x0000000907097212 */
/* 0x000fce00078efcff */
/*0990*/ @!P0 BRA 0xb90 ; /* 0x000001f000008947 */
/* 0x000fea0003800000 */
/*09a0*/ IMAD.MOV R3, RZ, RZ, -R13 ; /* 0x000000ffff037224 */
/* 0x000fe200078e0a0d */
/*09b0*/ DMUL.RP R8, R16, R8 ; /* 0x0000000810087228 */
/* 0x000e220000008000 */
/*09c0*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x000fcc00078e00ff */
/*09d0*/ DFMA R2, R18, -R2, R16 ; /* 0x800000021202722b */
/* 0x000e460000000010 */
/*09e0*/ LOP3.LUT R7, R9, R7, RZ, 0x3c, !PT ; /* 0x0000000709077212 */
/* 0x001fc600078e3cff */
/*09f0*/ IADD3 R2, -R13, -0x43300000, RZ ; /* 0xbcd000000d027810 */
/* 0x002fc80007ffe1ff */
/*0a00*/ FSETP.NEU.AND P0, PT, |R3|, R2, PT ; /* 0x000000020300720b */
/* 0x000fc80003f0d200 */
/*0a10*/ FSEL R18, R8, R18, !P0 ; /* 0x0000001208127208 */
/* 0x000fe40004000000 */
/*0a20*/ FSEL R19, R7, R19, !P0 ; /* 0x0000001307137208 */
/* 0x000fe20004000000 */
/*0a30*/ BRA 0xb90 ; /* 0x0000015000007947 */
/* 0x000fea0003800000 */
/*0a40*/ DSETP.NAN.AND P0, PT, R8, R8, PT ; /* 0x000000080800722a */
/* 0x000e9c0003f08000 */
/*0a50*/ @P0 BRA 0xb70 ; /* 0x0000011000000947 */
/* 0x004fea0003800000 */
/*0a60*/ DSETP.NAN.AND P0, PT, R6, R6, PT ; /* 0x000000060600722a */
/* 0x000e9c0003f08000 */
/*0a70*/ @P0 BRA 0xb40 ; /* 0x000000c000000947 */
/* 0x004fea0003800000 */
/*0a80*/ ISETP.NE.AND P0, PT, R15, R22, PT ; /* 0x000000160f00720c */
/* 0x000fe20003f05270 */
/*0a90*/ IMAD.MOV.U32 R18, RZ, RZ, 0x0 ; /* 0x00000000ff127424 */
/* 0x001fe400078e00ff */
/*0aa0*/ IMAD.MOV.U32 R19, RZ, RZ, -0x80000 ; /* 0xfff80000ff137424 */
/* 0x000fd400078e00ff */
/*0ab0*/ @!P0 BRA 0xb90 ; /* 0x000000d000008947 */
/* 0x000fea0003800000 */
/*0ac0*/ ISETP.NE.AND P0, PT, R15, 0x7ff00000, PT ; /* 0x7ff000000f00780c */
/* 0x000fe40003f05270 */
/*0ad0*/ LOP3.LUT R19, R9, 0x80000000, R7, 0x48, !PT ; /* 0x8000000009137812 */
/* 0x000fe400078e4807 */
/*0ae0*/ ISETP.EQ.OR P0, PT, R22, RZ, !P0 ; /* 0x000000ff1600720c */
/* 0x000fda0004702670 */
/*0af0*/ @P0 LOP3.LUT R2, R19, 0x7ff00000, RZ, 0xfc, !PT ; /* 0x7ff0000013020812 */
/* 0x000fe200078efcff */
/*0b00*/ @!P0 IMAD.MOV.U32 R18, RZ, RZ, RZ ; /* 0x000000ffff128224 */
/* 0x000fe400078e00ff */
/*0b10*/ @P0 IMAD.MOV.U32 R18, RZ, RZ, RZ ; /* 0x000000ffff120224 */
/* 0x000fe400078e00ff */
/*0b20*/ @P0 IMAD.MOV.U32 R19, RZ, RZ, R2 ; /* 0x000000ffff130224 */
/* 0x000fe200078e0002 */
/*0b30*/ BRA 0xb90 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*0b40*/ LOP3.LUT R19, R7, 0x80000, RZ, 0xfc, !PT ; /* 0x0008000007137812 */
/* 0x001fe200078efcff */
/*0b50*/ IMAD.MOV.U32 R18, RZ, RZ, R6 ; /* 0x000000ffff127224 */
/* 0x000fe200078e0006 */
/*0b60*/ BRA 0xb90 ; /* 0x0000002000007947 */
/* 0x000fea0003800000 */
/*0b70*/ LOP3.LUT R19, R9, 0x80000, RZ, 0xfc, !PT ; /* 0x0008000009137812 */
/* 0x001fe200078efcff */
/*0b80*/ IMAD.MOV.U32 R18, RZ, RZ, R8 ; /* 0x000000ffff127224 */
/* 0x000fe400078e0008 */
/*0b90*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0ba0*/ IMAD.MOV.U32 R13, RZ, RZ, 0x0 ; /* 0x00000000ff0d7424 */
/* 0x000fe400078e00ff */
/*0bb0*/ IMAD.MOV.U32 R4, RZ, RZ, R18 ; /* 0x000000ffff047224 */
/* 0x000fc400078e0012 */
/*0bc0*/ IMAD.MOV.U32 R5, RZ, RZ, R19 ; /* 0x000000ffff057224 */
/* 0x000fe200078e0013 */
/*0bd0*/ RET.REL.NODEC R12 0x0 ; /* 0xfffff4200c007950 */
/* 0x000fec0003c3ffff */
/*0be0*/ BRA 0xbe0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0bf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11mandel_cudaPcS_S_ii
.globl _Z11mandel_cudaPcS_S_ii
.p2align 8
.type _Z11mandel_cudaPcS_S_ii,@function
_Z11mandel_cudaPcS_S_ii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b64 s[4:5], s[0:1], 0x18
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_lshr_b32 s2, s2, 16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_4)
v_mad_u64_u32 v[0:1], null, s14, s3, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s2, v[3:4]
v_cvt_f32_i32_e32 v6, s4
v_cvt_f32_i32_e32 v8, s5
s_mov_b32 s3, 0
v_cvt_f32_i32_e32 v2, v0
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
v_cvt_f64_f32_e32 v[6:7], v6
v_cvt_f32_i32_e32 v4, v1
v_cvt_f64_f32_e32 v[8:9], v8
v_cvt_f64_f32_e32 v[2:3], v2
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cvt_f64_f32_e32 v[4:5], v4
v_mul_f64 v[2:3], v[2:3], 0x400c0000
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[4:5], v[4:5], v[4:5]
v_div_scale_f64 v[10:11], null, v[6:7], v[6:7], v[2:3]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_div_scale_f64 v[12:13], null, v[8:9], v[8:9], v[4:5]
v_div_scale_f64 v[22:23], vcc_lo, v[2:3], v[6:7], v[2:3]
v_rcp_f64_e32 v[14:15], v[10:11]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_rcp_f64_e32 v[16:17], v[12:13]
s_waitcnt_depctr 0xfff
v_fma_f64 v[18:19], -v[10:11], v[14:15], 1.0
v_fma_f64 v[20:21], -v[12:13], v[16:17], 1.0
v_fma_f64 v[14:15], v[14:15], v[18:19], v[14:15]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f64 v[16:17], v[16:17], v[20:21], v[16:17]
v_fma_f64 v[18:19], -v[10:11], v[14:15], 1.0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f64 v[20:21], -v[12:13], v[16:17], 1.0
v_fma_f64 v[14:15], v[14:15], v[18:19], v[14:15]
v_div_scale_f64 v[18:19], s2, v[4:5], v[8:9], v[4:5]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fma_f64 v[16:17], v[16:17], v[20:21], v[16:17]
v_mul_f64 v[20:21], v[22:23], v[14:15]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_f64 v[24:25], v[18:19], v[16:17]
v_fma_f64 v[10:11], -v[10:11], v[20:21], v[22:23]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f64 v[12:13], -v[12:13], v[24:25], v[18:19]
v_div_fmas_f64 v[10:11], v[10:11], v[14:15], v[20:21]
s_mov_b32 vcc_lo, s2
s_mov_b32 s2, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_div_fmas_f64 v[12:13], v[12:13], v[16:17], v[24:25]
v_div_fixup_f64 v[2:3], v[10:11], v[6:7], v[2:3]
v_dual_mov_b32 v7, 0 :: v_dual_mov_b32 v6, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_div_fixup_f64 v[4:5], v[12:13], v[8:9], v[4:5]
v_mov_b32_e32 v8, 0
v_add_f64 v[2:3], v[2:3], 0xc0040000
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[4:5], v[4:5], -1.0
v_cvt_f32_f64_e32 v2, v[2:3]
s_delay_alu instid0(VALU_DEP_2)
v_cvt_f32_f64_e32 v3, v[4:5]
v_mov_b32_e32 v5, 0
.p2align 6
.LBB0_1:
v_sub_f32_e32 v4, v6, v7
v_add_f32_e32 v6, v8, v8
s_add_i32 s5, s3, 1
s_cmpk_gt_u32 s3, 0xfe
s_cselect_b32 s3, -1, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v5, v5, v6, v3
v_dual_mul_f32 v7, v5, v5 :: v_dual_add_f32 v8, v4, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v6, v8, v8
v_fma_f32 v4, v5, v5, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_cmp_nge_f32_e32 vcc_lo, 4.0, v4
v_mov_b32_e32 v4, s5
s_or_b32 s3, vcc_lo, s3
s_and_b32 s3, exec_lo, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 s2, s3, s2
s_mov_b32 s3, s5
s_and_not1_b32 exec_lo, exec_lo, s2
s_cbranch_execnz .LBB0_1
s_or_b32 exec_lo, exec_lo, s2
s_clause 0x1
s_load_b128 s[8:11], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
v_mad_u64_u32 v[2:3], null, v1, s4, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v3, 31, v2
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s8, v2
v_add_co_ci_u32_e32 v1, vcc_lo, s9, v3, vcc_lo
v_add_co_u32 v5, vcc_lo, s10, v2
v_add_co_ci_u32_e32 v6, vcc_lo, s11, v3, vcc_lo
v_add_co_u32 v2, vcc_lo, s0, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
global_store_b8 v[0:1], v4, off
global_store_b8 v[5:6], v4, off
global_store_b8 v[2:3], v4, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11mandel_cudaPcS_S_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 26
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z11mandel_cudaPcS_S_ii, .Lfunc_end0-_Z11mandel_cudaPcS_S_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11mandel_cudaPcS_S_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z11mandel_cudaPcS_S_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 26
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00080723_00000000-6_mandel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2065:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2065:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "wb"
.text
.globl _Z12write_bitmapPKciiPcS1_S1_
.type _Z12write_bitmapPKciiPcS1_S1_, @function
_Z12write_bitmapPKciiPcS1_S1_:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $120, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 8(%rsp)
movl %esi, %r15d
movl %edx, %r13d
movq %rcx, %rbx
movq %r8, %rbp
movq %r9, %r12
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leal 3(%rsi,%rsi,2), %edx
leal 3(%rdx), %eax
testl %edx, %edx
cmovns %edx, %eax
andl $-4, %eax
movl %eax, %r14d
cltq
movq %rax, 16(%rsp)
movq %rax, %rdi
call malloc@PLT
movq %rax, (%rsp)
movb $66, 80(%rsp)
movb $77, 81(%rsp)
movl $0, 88(%rsp)
movl $54, 92(%rsp)
imull %r13d, %r14d
leal 54(%r14), %eax
movl %eax, 84(%rsp)
movl $40, 32(%rsp)
movl %r15d, 36(%rsp)
movl %r13d, 40(%rsp)
movw $1, 44(%rsp)
movw $24, 46(%rsp)
movl $0, 48(%rsp)
movl %r14d, 52(%rsp)
movl $0, 56(%rsp)
movl $0, 60(%rsp)
movl $0, 64(%rsp)
movl $0, 68(%rsp)
leaq .LC0(%rip), %rsi
movq 8(%rsp), %rdi
call fopen@PLT
movq %rax, 8(%rsp)
testq %rax, %rax
je .L14
leaq 80(%rsp), %rdi
movq 8(%rsp), %r14
movq %r14, %rcx
movl $1, %edx
movl $2, %esi
call fwrite@PLT
leaq 84(%rsp), %rdi
movq %r14, %rcx
movl $1, %edx
movl $4, %esi
call fwrite@PLT
leaq 88(%rsp), %rdi
movq %r14, %rcx
movl $1, %edx
movl $4, %esi
call fwrite@PLT
leaq 92(%rsp), %rdi
movq %r14, %rcx
movl $1, %edx
movl $4, %esi
call fwrite@PLT
leaq 32(%rsp), %rdi
movq %r14, %rcx
movl $1, %edx
movl $4, %esi
call fwrite@PLT
leaq 36(%rsp), %rdi
movq %r14, %rcx
movl $1, %edx
movl $4, %esi
call fwrite@PLT
leaq 40(%rsp), %rdi
movq %r14, %rcx
movl $1, %edx
movl $4, %esi
call fwrite@PLT
leaq 44(%rsp), %rdi
movq %r14, %rcx
movl $1, %edx
movl $2, %esi
call fwrite@PLT
leaq 46(%rsp), %rdi
movq %r14, %rcx
movl $1, %edx
movl $2, %esi
call fwrite@PLT
leaq 48(%rsp), %rdi
movq %r14, %rcx
movl $1, %edx
movl $4, %esi
call fwrite@PLT
leaq 52(%rsp), %rdi
movq %r14, %rcx
movl $1, %edx
movl $4, %esi
call fwrite@PLT
leaq 56(%rsp), %rdi
movq %r14, %rcx
movl $1, %edx
movl $4, %esi
call fwrite@PLT
leaq 60(%rsp), %rdi
movq %r14, %rcx
movl $1, %edx
movl $4, %esi
call fwrite@PLT
leaq 64(%rsp), %rdi
movq %r14, %rcx
movl $1, %edx
movl $4, %esi
call fwrite@PLT
leaq 68(%rsp), %rdi
movq %r14, %rcx
movl $1, %edx
movl $4, %esi
call fwrite@PLT
subl $1, %r13d
js .L6
movl %r13d, %r14d
imull %r15d, %r14d
movslq %r15d, %rax
movq %rax, 24(%rsp)
jmp .L7
.L14:
movq (%rsp), %rdi
call free@PLT
movl $-1, %eax
jmp .L3
.L8:
movzbl (%r12,%rax), %ecx
movb %cl, (%rdx)
movzbl 0(%rbp,%rax), %ecx
movb %cl, 1(%rdx)
movzbl (%rbx,%rax), %ecx
movb %cl, 2(%rdx)
addq $3, %rdx
addq $1, %rax
cmpq %rsi, %rax
jne .L8
.L10:
movq 8(%rsp), %rcx
movl $1, %edx
movq 16(%rsp), %rsi
movq (%rsp), %rdi
call fwrite@PLT
subl $1, %r13d
subl %r15d, %r14d
cmpl $-1, %r13d
je .L6
.L7:
movq (%rsp), %rdx
movslq %r14d, %rax
movq 24(%rsp), %rdi
leaq (%rdi,%rax), %rsi
testl %r15d, %r15d
jg .L8
jmp .L10
.L6:
movq (%rsp), %rdi
call free@PLT
movq 8(%rsp), %rdi
call fclose@PLT
movl $0, %eax
.L3:
movq 104(%rsp), %rdx
subq %fs:40, %rdx
jne .L15
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size _Z12write_bitmapPKciiPcS1_S1_, .-_Z12write_bitmapPKciiPcS1_S1_
.globl _Z11mandel_hostPcS_S_ii
.type _Z11mandel_hostPcS_S_ii, @function
_Z11mandel_hostPcS_S_ii:
.LFB2058:
.cfi_startproc
endbr64
testl %ecx, %ecx
jle .L30
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
movq %rdi, %r9
movq %rsi, %r10
movq %rdx, %r11
movl %ecx, %ebx
movl %r8d, %esi
movslq %ecx, %rdi
movl $0, %ebp
movsd .LC2(%rip), %xmm12
movsd .LC3(%rip), %xmm11
movsd .LC4(%rip), %xmm10
pxor %xmm8, %xmm8
movss .LC5(%rip), %xmm7
movl $0, %r8d
jmp .L18
.L26:
cmpl $256, %eax
cmove %r8d, %eax
movb %al, (%r9,%rdx)
movb %al, (%r10,%rdx)
movb %al, (%r11,%rdx)
addl $1, %ecx
addq %rdi, %rdx
cmpl %ecx, %esi
je .L24
.L22:
pxor %xmm5, %xmm5
cvtsi2ssl %ecx, %xmm5
cvtss2sd %xmm5, %xmm5
addsd %xmm5, %xmm5
divsd %xmm9, %xmm5
subsd %xmm10, %xmm5
cvtsd2ss %xmm5, %xmm5
movl $0, %eax
movaps %xmm8, %xmm0
movaps %xmm8, %xmm3
movaps %xmm8, %xmm4
movaps %xmm8, %xmm1
.L19:
movaps %xmm3, %xmm2
subss %xmm4, %xmm1
movaps %xmm1, %xmm3
addss %xmm6, %xmm3
addss %xmm2, %xmm2
mulss %xmm2, %xmm0
addss %xmm5, %xmm0
addl $1, %eax
movaps %xmm3, %xmm1
mulss %xmm3, %xmm1
movaps %xmm0, %xmm4
mulss %xmm0, %xmm4
movaps %xmm1, %xmm2
addss %xmm4, %xmm2
comiss %xmm2, %xmm7
jb .L26
cmpl $255, %eax
jle .L19
jmp .L26
.L24:
addq $1, %rbp
cmpq %rdi, %rbp
je .L16
.L18:
testl %esi, %esi
jle .L24
pxor %xmm0, %xmm0
cvtsi2ssl %ebp, %xmm0
pxor %xmm6, %xmm6
cvtss2sd %xmm0, %xmm6
mulsd %xmm12, %xmm6
pxor %xmm0, %xmm0
cvtsi2ssl %ebx, %xmm0
cvtss2sd %xmm0, %xmm0
divsd %xmm0, %xmm6
subsd %xmm11, %xmm6
cvtsd2ss %xmm6, %xmm6
movq %rbp, %rdx
movl $0, %ecx
pxor %xmm9, %xmm9
cvtsi2ssl %esi, %xmm9
cvtss2sd %xmm9, %xmm9
jmp .L22
.L16:
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L30:
.cfi_restore 3
.cfi_restore 6
ret
.cfi_endproc
.LFE2058:
.size _Z11mandel_hostPcS_S_ii, .-_Z11mandel_hostPcS_S_ii
.section .rodata.str1.1
.LC6:
.string "output_host.bmp"
.text
.globl _Z8fes_hostii
.type _Z8fes_hostii, @function
_Z8fes_hostii:
.LFB2059:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
movl %edi, %r13d
movl %esi, %r14d
movslq %edi, %rbx
movslq %esi, %rax
imulq %rax, %rbx
movq %rbx, %rdi
call malloc@PLT
movq %rax, %r12
movq %rbx, %rdi
call malloc@PLT
movq %rax, %rbp
movq %rbx, %rdi
call malloc@PLT
movq %rax, %rbx
movl %r14d, %r8d
movl %r13d, %ecx
movq %rax, %rdx
movq %rbp, %rsi
movq %r12, %rdi
call _Z11mandel_hostPcS_S_ii
movq %rbx, %r9
movq %rbp, %r8
movq %r12, %rcx
movl %r14d, %edx
movl %r13d, %esi
leaq .LC6(%rip), %rdi
call _Z12write_bitmapPKciiPcS1_S1_
movq %r12, %rdi
call free@PLT
movq %rbp, %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size _Z8fes_hostii, .-_Z8fes_hostii
.section .rodata.str1.1
.LC7:
.string "rb"
.text
.globl _Z7readBMPPKc
.type _Z7readBMPPKc, @function
_Z7readBMPPKc:
.LFB2061:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $72, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
leaq .LC7(%rip), %rsi
call fopen@PLT
movq %rax, %r12
movq %rsp, %rdi
movq %rax, %r8
movl $54, %ecx
movl $1, %edx
movl $54, %esi
call __fread_chk@PLT
movl 18(%rsp), %eax
imull 22(%rsp), %eax
leal (%rax,%rax,2), %ebp
movslq %ebp, %r13
movq %r13, %rdi
call _Znam@PLT
movq %rax, %rbx
movq %r12, %r8
movq %r13, %rcx
movl $1, %edx
movq %r13, %rsi
movq %rax, %rdi
call __fread_chk@PLT
movq %r12, %rdi
call fclose@PLT
testl %ebp, %ebp
jle .L35
movl $0, %eax
.L37:
movzbl (%rbx,%rax), %edx
movzbl 2(%rbx,%rax), %ecx
movb %cl, (%rbx,%rax)
movb %dl, 2(%rbx,%rax)
addq $3, %rax
cmpl %eax, %ebp
jg .L37
.L35:
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L41
movq %rbx, %rax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L41:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2061:
.size _Z7readBMPPKc, .-_Z7readBMPPKc
.globl _Z37__device_stub__Z11mandel_cudaPcS_S_iiPcS_S_ii
.type _Z37__device_stub__Z11mandel_cudaPcS_S_iiPcS_S_ii, @function
_Z37__device_stub__Z11mandel_cudaPcS_S_iiPcS_S_ii:
.LFB2087:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L46
.L42:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L47
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L46:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z11mandel_cudaPcS_S_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L42
.L47:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2087:
.size _Z37__device_stub__Z11mandel_cudaPcS_S_iiPcS_S_ii, .-_Z37__device_stub__Z11mandel_cudaPcS_S_iiPcS_S_ii
.globl _Z11mandel_cudaPcS_S_ii
.type _Z11mandel_cudaPcS_S_ii, @function
_Z11mandel_cudaPcS_S_ii:
.LFB2088:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z37__device_stub__Z11mandel_cudaPcS_S_iiPcS_S_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2088:
.size _Z11mandel_cudaPcS_S_ii, .-_Z11mandel_cudaPcS_S_ii
.section .rodata.str1.1
.LC8:
.string "output_cuda.bmp"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC10:
.string "GPU %f segons with %d threats \n"
.text
.globl _Z8fes_cudaii
.type _Z8fes_cudaii, @function
_Z8fes_cudaii:
.LFB2060:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $88, %rsp
.cfi_def_cfa_offset 144
movl %edi, %ebp
movl %esi, %r12d
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movslq %edi, %rbx
movslq %esi, %rax
imulq %rax, %rbx
leaq 24(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 32(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 40(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
call clock@PLT
movq %rax, 8(%rsp)
movl %ebp, %eax
movl $2863311531, %edx
imulq %rdx, %rax
shrq $34, %rax
movl %eax, 60(%rsp)
movl %r12d, %eax
imulq %rdx, %rax
shrq $34, %rax
movl %eax, 64(%rsp)
movl $6, 48(%rsp)
movl $6, 52(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 48(%rsp), %rdx
movl $1, %ecx
movq 60(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L54
.L51:
movq %rbx, %rdi
call malloc@PLT
movq %rax, %r13
movq %rbx, %rdi
call malloc@PLT
movq %rax, %r14
movq %rbx, %rdi
call malloc@PLT
movq %rax, %r15
movl $2, %ecx
movq %rbx, %rdx
movq 24(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
movl $2, %ecx
movq %rbx, %rdx
movq 32(%rsp), %rsi
movq %r14, %rdi
call cudaMemcpy@PLT
movl $2, %ecx
movq %rbx, %rdx
movq 40(%rsp), %rsi
movq %r15, %rdi
call cudaMemcpy@PLT
movq %r15, %r9
movq %r14, %r8
movq %r13, %rcx
movl %r12d, %edx
movl %ebp, %esi
leaq .LC8(%rip), %rdi
call _Z12write_bitmapPKciiPcS1_S1_
call clock@PLT
movq 8(%rsp), %rcx
subq %rcx, %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
divsd .LC9(%rip), %xmm0
movl $6, %edx
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq %r15, %rdi
call free@PLT
movq %r14, %rdi
call free@PLT
movq %r13, %rdi
call free@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L55
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L54:
.cfi_restore_state
movl %r12d, %r8d
movl %ebp, %ecx
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z37__device_stub__Z11mandel_cudaPcS_S_iiPcS_S_ii
jmp .L51
.L55:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2060:
.size _Z8fes_cudaii, .-_Z8fes_cudaii
.section .rodata.str1.8
.align 8
.LC11:
.string "There are no difference,have %d errors\n"
.section .rodata.str1.1
.LC12:
.string "There are no difference\n"
.text
.globl main
.type main, @function
main:
.LFB2062:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movl $5120, %esi
movl $5120, %edi
call _Z8fes_cudaii
movl $5120, %esi
movl $5120, %edi
call _Z8fes_hostii
leaq .LC8(%rip), %rdi
call _Z7readBMPPKc
movq %rax, %rbx
leaq .LC6(%rip), %rdi
call _Z7readBMPPKc
movl $0, %edx
movl $0, %ecx
jmp .L58
.L57:
addq $1, %rdx
cmpq $26214400, %rdx
je .L63
.L58:
movzbl (%rax,%rdx), %esi
cmpb %sil, (%rbx,%rdx)
je .L57
addl $1, %ecx
jmp .L57
.L63:
testl %ecx, %ecx
je .L59
movl %ecx, %edx
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L60:
movl $0, %eax
popq %rbx
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L59:
.cfi_restore_state
leaq .LC12(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L60
.cfi_endproc
.LFE2062:
.size main, .-main
.section .rodata.str1.1
.LC13:
.string "_Z11mandel_cudaPcS_S_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2090:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC13(%rip), %rdx
movq %rdx, %rcx
leaq _Z11mandel_cudaPcS_S_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2090:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC2:
.long 0
.long 1074528256
.align 8
.LC3:
.long 0
.long 1074003968
.align 8
.LC4:
.long 0
.long 1072693248
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC5:
.long 1082130432
.section .rodata.cst8
.align 8
.LC9:
.long 0
.long 1093567616
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "mandel.hip"
.globl _Z12write_bitmapPKciiPcS1_S1_ # -- Begin function _Z12write_bitmapPKciiPcS1_S1_
.p2align 4, 0x90
.type _Z12write_bitmapPKciiPcS1_S1_,@function
_Z12write_bitmapPKciiPcS1_S1_: # @_Z12write_bitmapPKciiPcS1_S1_
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $104, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %r9, %rbx
movq %r8, %r14
movq %rcx, %r15
movl %edx, %ebp
movl %esi, %r12d
movq %rdi, (%rsp) # 8-byte Spill
leal (%r12,%r12,2), %eax
addl $3, %eax
leal (%r12,%r12,2), %ecx
addl $6, %ecx
testl %eax, %eax
cmovnsl %eax, %ecx
andl $-4, %ecx
movslq %ecx, %r13
movq %r13, %rdi
callq malloc
movq %rax, 8(%rsp) # 8-byte Spill
movw $19778, 16(%rsp) # imm = 0x4D42
movabsq $231928233984, %rax # imm = 0x3600000000
movq %rax, 24(%rsp)
movq %r13, 96(%rsp) # 8-byte Spill
movl %r13d, %eax
imull %ebp, %eax
leal 54(%rax), %ecx
movl %ecx, 20(%rsp)
movl $40, 32(%rsp)
movq %r12, 72(%rsp) # 8-byte Spill
movl %r12d, 36(%rsp)
movl %ebp, 40(%rsp)
movq $1572865, 44(%rsp) # imm = 0x180001
movl %eax, 52(%rsp)
xorps %xmm0, %xmm0
movups %xmm0, 56(%rsp)
movl $.L.str, %esi
movq (%rsp), %rdi # 8-byte Reload
callq fopen
testq %rax, %rax
je .LBB0_1
# %bb.2:
movq %rax, %r12
leaq 68(%rsp), %r13
leaq 16(%rsp), %rdi
movl $2, %esi
movl $1, %edx
movq %rax, %rcx
callq fwrite
movl $4, %esi
movl $1, %edx
leaq 20(%rsp), %rdi
movq %r12, %rcx
callq fwrite
movl $4, %esi
movl $1, %edx
leaq 24(%rsp), %rdi
movq %r12, %rcx
callq fwrite
movl $4, %esi
movl $1, %edx
leaq 28(%rsp), %rdi
movq %r12, %rcx
callq fwrite
leaq 32(%rsp), %rdi
movl $4, %esi
movl $1, %edx
movq %r12, %rcx
callq fwrite
movl $4, %esi
movl $1, %edx
leaq 36(%rsp), %rdi
movq %r12, %rcx
callq fwrite
movl $4, %esi
movl $1, %edx
leaq 40(%rsp), %rdi
movq %r12, %rcx
callq fwrite
movl $2, %esi
movl $1, %edx
leaq 44(%rsp), %rdi
movq %r12, %rcx
callq fwrite
movl $2, %esi
movl $1, %edx
leaq 46(%rsp), %rdi
movq %r12, %rcx
callq fwrite
movl $4, %esi
movl $1, %edx
leaq 48(%rsp), %rdi
movq %r12, %rcx
callq fwrite
movl $4, %esi
movl $1, %edx
leaq 52(%rsp), %rdi
movq %r12, %rcx
callq fwrite
movl $4, %esi
movl $1, %edx
leaq 56(%rsp), %rdi
movq %r12, %rcx
callq fwrite
movl $4, %esi
movl $1, %edx
leaq 60(%rsp), %rdi
movq %r12, %rcx
callq fwrite
movl $4, %esi
movl $1, %edx
leaq 64(%rsp), %rdi
movq %r12, %rcx
callq fwrite
movl $4, %esi
movl $1, %edx
movq %r13, %rdi
movq %r12, (%rsp) # 8-byte Spill
movq %r12, %rcx
callq fwrite
testl %ebp, %ebp
jle .LBB0_8
# %bb.3: # %.preheader.lr.ph
movl %ebp, %ebp
movq 72(%rsp), %rax # 8-byte Reload
movslq %eax, %rcx
movl %eax, %r12d
movq 8(%rsp), %rax # 8-byte Reload
addq $2, %rax
movq %rax, 80(%rsp) # 8-byte Spill
leaq -1(%rbp), %rax
imulq %rcx, %rax
addq %rax, %rbx
negq %rcx
movq %rcx, 88(%rsp) # 8-byte Spill
addq %rax, %r14
addq %rax, %r15
jmp .LBB0_4
.p2align 4, 0x90
.LBB0_7: # %._crit_edge
# in Loop: Header=BB0_4 Depth=1
leaq -1(%rbp), %r13
movl $1, %edx
movq 8(%rsp), %rdi # 8-byte Reload
movq 96(%rsp), %rsi # 8-byte Reload
movq (%rsp), %rcx # 8-byte Reload
callq fwrite
movq 88(%rsp), %rax # 8-byte Reload
addq %rax, %rbx
addq %rax, %r14
addq %rax, %r15
cmpq $1, %rbp
movq %r13, %rbp
jle .LBB0_8
.LBB0_4: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB0_6 Depth 2
cmpl $0, 72(%rsp) # 4-byte Folded Reload
jle .LBB0_7
# %bb.5: # %.lr.ph
# in Loop: Header=BB0_4 Depth=1
movq 80(%rsp), %rax # 8-byte Reload
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB0_6: # Parent Loop BB0_4 Depth=1
# => This Inner Loop Header: Depth=2
movzbl (%rbx,%rcx), %edx
movb %dl, -2(%rax)
movzbl (%r14,%rcx), %edx
movb %dl, -1(%rax)
movzbl (%r15,%rcx), %edx
movb %dl, (%rax)
incq %rcx
addq $3, %rax
cmpq %rcx, %r12
jne .LBB0_6
jmp .LBB0_7
.LBB0_8: # %._crit_edge58
movq 8(%rsp), %rdi # 8-byte Reload
callq free
movq (%rsp), %rdi # 8-byte Reload
callq fclose
xorl %eax, %eax
jmp .LBB0_9
.LBB0_1:
movq 8(%rsp), %rdi # 8-byte Reload
callq free
movl $-1, %eax
.LBB0_9:
addq $104, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z12write_bitmapPKciiPcS1_S1_, .Lfunc_end0-_Z12write_bitmapPKciiPcS1_S1_
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z11mandel_hostPcS_S_ii
.LCPI1_0:
.quad 0x400c000000000000 # double 3.5
.LCPI1_1:
.quad 0xc004000000000000 # double -2.5
.LCPI1_2:
.quad 0xbff0000000000000 # double -1
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0
.LCPI1_3:
.long 0x40800000 # float 4
.text
.globl _Z11mandel_hostPcS_S_ii
.p2align 4, 0x90
.type _Z11mandel_hostPcS_S_ii,@function
_Z11mandel_hostPcS_S_ii: # @_Z11mandel_hostPcS_S_ii
.cfi_startproc
# %bb.0:
testl %ecx, %ecx
jle .LBB1_10
# %bb.1: # %.preheader.lr.ph
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
cvtsi2ss %ecx, %xmm0
cvtss2sd %xmm0, %xmm0
cvtsi2ss %r8d, %xmm1
cvtss2sd %xmm1, %xmm1
movl %ecx, %eax
movl %r8d, %ecx
xorl %r9d, %r9d
movsd .LCPI1_0(%rip), %xmm2 # xmm2 = mem[0],zero
movsd .LCPI1_1(%rip), %xmm3 # xmm3 = mem[0],zero
movsd .LCPI1_2(%rip), %xmm4 # xmm4 = mem[0],zero
movss .LCPI1_3(%rip), %xmm5 # xmm5 = mem[0],zero,zero,zero
jmp .LBB1_2
.p2align 4, 0x90
.LBB1_8: # %._crit_edge
# in Loop: Header=BB1_2 Depth=1
incq %r9
cmpq %rax, %r9
je .LBB1_9
.LBB1_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_4 Depth 2
# Child Loop BB1_5 Depth 3
testl %r8d, %r8d
jle .LBB1_8
# %bb.3: # %.lr.ph
# in Loop: Header=BB1_2 Depth=1
xorps %xmm6, %xmm6
cvtsi2ss %r9d, %xmm6
cvtss2sd %xmm6, %xmm6
mulsd %xmm2, %xmm6
divsd %xmm0, %xmm6
addsd %xmm3, %xmm6
cvtsd2ss %xmm6, %xmm6
xorl %r10d, %r10d
jmp .LBB1_4
.p2align 4, 0x90
.LBB1_7: # in Loop: Header=BB1_4 Depth=2
movq %r10, %r11
imulq %rax, %r11
addq %r9, %r11
movb %bl, (%rdi,%r11)
movb %bl, (%rsi,%r11)
movb %bl, (%rdx,%r11)
incq %r10
cmpq %rcx, %r10
je .LBB1_8
.LBB1_4: # Parent Loop BB1_2 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB1_5 Depth 3
xorps %xmm7, %xmm7
cvtsi2ss %r10d, %xmm7
cvtss2sd %xmm7, %xmm7
addsd %xmm7, %xmm7
divsd %xmm1, %xmm7
addsd %xmm4, %xmm7
cvtsd2ss %xmm7, %xmm7
xorl %r11d, %r11d
xorps %xmm10, %xmm10
xorps %xmm9, %xmm9
xorps %xmm8, %xmm8
xorps %xmm11, %xmm11
.p2align 4, 0x90
.LBB1_5: # Parent Loop BB1_2 Depth=1
# Parent Loop BB1_4 Depth=2
# => This Inner Loop Header: Depth=3
subss %xmm10, %xmm9
addss %xmm11, %xmm11
mulss %xmm11, %xmm8
movaps %xmm9, %xmm11
addss %xmm6, %xmm11
addss %xmm7, %xmm8
leal 1(%r11), %ebx
movaps %xmm11, %xmm9
mulss %xmm11, %xmm9
movaps %xmm8, %xmm10
mulss %xmm8, %xmm10
movaps %xmm9, %xmm12
addss %xmm10, %xmm12
ucomiss %xmm12, %xmm5
jb .LBB1_7
# %bb.6: # in Loop: Header=BB1_5 Depth=3
cmpl $255, %r11d
movl %ebx, %r11d
jb .LBB1_5
jmp .LBB1_7
.LBB1_9:
popq %rbx
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.LBB1_10: # %._crit_edge50
retq
.Lfunc_end1:
.size _Z11mandel_hostPcS_S_ii, .Lfunc_end1-_Z11mandel_hostPcS_S_ii
.cfi_endproc
# -- End function
.globl _Z26__device_stub__mandel_cudaPcS_S_ii # -- Begin function _Z26__device_stub__mandel_cudaPcS_S_ii
.p2align 4, 0x90
.type _Z26__device_stub__mandel_cudaPcS_S_ii,@function
_Z26__device_stub__mandel_cudaPcS_S_ii: # @_Z26__device_stub__mandel_cudaPcS_S_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z11mandel_cudaPcS_S_ii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end2:
.size _Z26__device_stub__mandel_cudaPcS_S_ii, .Lfunc_end2-_Z26__device_stub__mandel_cudaPcS_S_ii
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z8fes_hostii
.LCPI3_0:
.quad 0x400c000000000000 # double 3.5
.LCPI3_1:
.quad 0xc004000000000000 # double -2.5
.LCPI3_2:
.quad 0xbff0000000000000 # double -1
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0
.LCPI3_3:
.long 0x40800000 # float 4
.text
.globl _Z8fes_hostii
.p2align 4, 0x90
.type _Z8fes_hostii,@function
_Z8fes_hostii: # @_Z8fes_hostii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
pushq %rax
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %esi, %ebx
movl %edi, %ebp
movslq %edi, %r13
movslq %esi, %r12
imulq %r13, %r12
movq %r12, %rdi
callq malloc
movq %rax, %r14
movq %r12, %rdi
callq malloc
movq %rax, %r15
movq %r12, %rdi
callq malloc
movq %rax, %r12
testl %r13d, %r13d
jle .LBB3_9
# %bb.1: # %.preheader.lr.ph.i
cvtsi2ss %ebp, %xmm0
cvtss2sd %xmm0, %xmm0
cvtsi2ss %ebx, %xmm1
cvtss2sd %xmm1, %xmm1
movl %ebp, %eax
movl %ebx, %ecx
xorl %edx, %edx
movsd .LCPI3_0(%rip), %xmm2 # xmm2 = mem[0],zero
movsd .LCPI3_1(%rip), %xmm3 # xmm3 = mem[0],zero
movsd .LCPI3_2(%rip), %xmm4 # xmm4 = mem[0],zero
movss .LCPI3_3(%rip), %xmm5 # xmm5 = mem[0],zero,zero,zero
jmp .LBB3_2
.p2align 4, 0x90
.LBB3_8: # %._crit_edge.i
# in Loop: Header=BB3_2 Depth=1
incq %rdx
cmpq %rax, %rdx
je .LBB3_9
.LBB3_2: # %.preheader.i
# =>This Loop Header: Depth=1
# Child Loop BB3_4 Depth 2
# Child Loop BB3_5 Depth 3
testl %ebx, %ebx
jle .LBB3_8
# %bb.3: # %.lr.ph.i
# in Loop: Header=BB3_2 Depth=1
xorps %xmm6, %xmm6
cvtsi2ss %edx, %xmm6
cvtss2sd %xmm6, %xmm6
mulsd %xmm2, %xmm6
divsd %xmm0, %xmm6
addsd %xmm3, %xmm6
cvtsd2ss %xmm6, %xmm6
xorl %esi, %esi
jmp .LBB3_4
.p2align 4, 0x90
.LBB3_7: # in Loop: Header=BB3_4 Depth=2
movq %rsi, %rdi
imulq %rax, %rdi
addq %rdx, %rdi
movb %r8b, (%r14,%rdi)
movb %r8b, (%r15,%rdi)
movb %r8b, (%r12,%rdi)
incq %rsi
cmpq %rcx, %rsi
je .LBB3_8
.LBB3_4: # Parent Loop BB3_2 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB3_5 Depth 3
xorps %xmm7, %xmm7
cvtsi2ss %esi, %xmm7
cvtss2sd %xmm7, %xmm7
addsd %xmm7, %xmm7
divsd %xmm1, %xmm7
addsd %xmm4, %xmm7
cvtsd2ss %xmm7, %xmm7
xorl %edi, %edi
xorps %xmm10, %xmm10
xorps %xmm9, %xmm9
xorps %xmm8, %xmm8
xorps %xmm11, %xmm11
.p2align 4, 0x90
.LBB3_5: # Parent Loop BB3_2 Depth=1
# Parent Loop BB3_4 Depth=2
# => This Inner Loop Header: Depth=3
subss %xmm10, %xmm9
addss %xmm11, %xmm11
mulss %xmm11, %xmm8
movaps %xmm9, %xmm11
addss %xmm6, %xmm11
addss %xmm7, %xmm8
leal 1(%rdi), %r8d
movaps %xmm11, %xmm9
mulss %xmm11, %xmm9
movaps %xmm8, %xmm10
mulss %xmm8, %xmm10
movaps %xmm9, %xmm12
addss %xmm10, %xmm12
ucomiss %xmm12, %xmm5
jb .LBB3_7
# %bb.6: # in Loop: Header=BB3_5 Depth=3
cmpl $255, %edi
movl %r8d, %edi
jb .LBB3_5
jmp .LBB3_7
.LBB3_9: # %_Z11mandel_hostPcS_S_ii.exit
movl $.L.str.1, %edi
movl %ebp, %esi
movl %ebx, %edx
movq %r14, %rcx
movq %r15, %r8
movq %r12, %r9
callq _Z12write_bitmapPKciiPcS1_S1_
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
movq %r12, %rdi
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
jmp free # TAILCALL
.Lfunc_end3:
.size _Z8fes_hostii, .Lfunc_end3-_Z8fes_hostii
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z8fes_cudaii
.LCPI4_0:
.quad 0x412e848000000000 # double 1.0E+6
.text
.globl _Z8fes_cudaii
.p2align 4, 0x90
.type _Z8fes_cudaii,@function
_Z8fes_cudaii: # @_Z8fes_cudaii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $152, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %esi, %ebx
movl %edi, %ebp
movslq %edi, %r12
movslq %esi, %r15
movq %r15, %r14
imulq %r12, %r14
leaq 16(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
leaq 8(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
movq %rsp, %rdi
movq %r14, %rsi
callq hipMalloc
callq clock
movq %rax, 32(%rsp) # 8-byte Spill
movl %r12d, %eax
movl $2863311531, %ecx # imm = 0xAAAAAAAB
imulq %rcx, %rax
shrq $34, %rax
movl %r15d, %edx
imulq %rcx, %rdx
shrq $2, %rdx
movabsq $4611686014132420608, %rdi # imm = 0x3FFFFFFF00000000
andq %rdx, %rdi
orq %rax, %rdi
movabsq $25769803782, %rdx # imm = 0x600000006
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_2
# %bb.1:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq (%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
movl %ebp, 28(%rsp)
movl %ebx, 24(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 28(%rsp), %rax
movq %rax, 136(%rsp)
leaq 24(%rsp), %rax
movq %rax, 144(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z11mandel_cudaPcS_S_ii, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_2:
movq %r14, %rdi
callq malloc
movq %rax, %r12
movq %r14, %rdi
callq malloc
movq %rax, %r13
movq %r14, %rdi
callq malloc
movq %rax, %r15
movq 16(%rsp), %rsi
movq %r12, %rdi
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
movq 8(%rsp), %rsi
movq %r13, %rdi
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
movq (%rsp), %rsi
movq %r15, %rdi
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
movl $.L.str.2, %edi
movl %ebp, %esi
movl %ebx, %edx
movq %r12, %rcx
movq %r13, %r8
movq %r15, %r9
callq _Z12write_bitmapPKciiPcS1_S1_
callq clock
subq 32(%rsp), %rax # 8-byte Folded Reload
cvtsi2sd %rax, %xmm0
divsd .LCPI4_0(%rip), %xmm0
movl $.L.str.3, %edi
movl $6, %esi
movb $1, %al
callq printf
movq (%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq %r15, %rdi
callq free
movq %r13, %rdi
callq free
movq %r12, %rdi
callq free
addq $152, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end4:
.size _Z8fes_cudaii, .Lfunc_end4-_Z8fes_cudaii
.cfi_endproc
# -- End function
.globl _Z7readBMPPKc # -- Begin function _Z7readBMPPKc
.p2align 4, 0x90
.type _Z7readBMPPKc,@function
_Z7readBMPPKc: # @_Z7readBMPPKc
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $64, %rsp
.cfi_def_cfa_offset 96
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $.L.str.4, %esi
callq fopen
movq %rax, %r14
movq %rsp, %rdi
movl $1, %esi
movl $54, %edx
movq %rax, %rcx
callq fread
movslq 18(%rsp), %rax
movslq 22(%rsp), %rcx
imulq %rax, %rcx
leaq (%rcx,%rcx,2), %r15
movq %r15, %rdi
callq _Znam
movq %rax, %rbx
movl $1, %esi
movq %rax, %rdi
movq %r15, %rdx
movq %r14, %rcx
callq fread
movq %r14, %rdi
callq fclose
testl %r15d, %r15d
jle .LBB5_3
# %bb.1: # %.lr.ph.preheader
movl %r15d, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB5_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movzbl (%rbx,%rcx), %edx
movzbl 2(%rbx,%rcx), %esi
movb %sil, (%rbx,%rcx)
movb %dl, 2(%rbx,%rcx)
addq $3, %rcx
cmpq %rax, %rcx
jb .LBB5_2
.LBB5_3: # %._crit_edge
movq %rbx, %rax
addq $64, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end5:
.size _Z7readBMPPKc, .Lfunc_end5-_Z7readBMPPKc
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
movl $5120, %edi # imm = 0x1400
movl $5120, %esi # imm = 0x1400
callq _Z8fes_cudaii
movl $5120, %edi # imm = 0x1400
movl $5120, %esi # imm = 0x1400
callq _Z8fes_hostii
movl $.L.str.2, %edi
callq _Z7readBMPPKc
movq %rax, %rbx
movl $.L.str.1, %edi
callq _Z7readBMPPKc
xorl %ecx, %ecx
xorl %esi, %esi
.p2align 4, 0x90
.LBB6_1: # =>This Inner Loop Header: Depth=1
movzbl (%rbx,%rcx), %edx
xorl %edi, %edi
cmpb (%rax,%rcx), %dl
setne %dil
addl %edi, %esi
incq %rcx
cmpq $26214400, %rcx # imm = 0x1900000
jne .LBB6_1
# %bb.2:
testl %esi, %esi
je .LBB6_4
# %bb.3:
movl $.L.str.5, %edi
xorl %eax, %eax
callq printf
jmp .LBB6_5
.LBB6_4:
movl $.Lstr, %edi
callq puts@PLT
.LBB6_5:
xorl %eax, %eax
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end6:
.size main, .Lfunc_end6-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB7_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB7_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11mandel_cudaPcS_S_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end7:
.size __hip_module_ctor, .Lfunc_end7-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB8_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB8_2:
retq
.Lfunc_end8:
.size __hip_module_dtor, .Lfunc_end8-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "wb"
.size .L.str, 3
.type _Z11mandel_cudaPcS_S_ii,@object # @_Z11mandel_cudaPcS_S_ii
.section .rodata,"a",@progbits
.globl _Z11mandel_cudaPcS_S_ii
.p2align 3, 0x0
_Z11mandel_cudaPcS_S_ii:
.quad _Z26__device_stub__mandel_cudaPcS_S_ii
.size _Z11mandel_cudaPcS_S_ii, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "output_host.bmp"
.size .L.str.1, 16
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "output_cuda.bmp"
.size .L.str.2, 16
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "GPU %f segons with %d threats \n"
.size .L.str.3, 32
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "rb"
.size .L.str.4, 3
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "There are no difference,have %d errors\n"
.size .L.str.5, 40
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z11mandel_cudaPcS_S_ii"
.size .L__unnamed_1, 24
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "There are no difference"
.size .Lstr, 24
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__mandel_cudaPcS_S_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11mandel_cudaPcS_S_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <stdlib.h>
#include <stdint.h>
#define BLOCKS 12
#define BLOCKSIZE 1024
//#define BSize 32
//#define QSize (BLOCKS*BLOCKSIZE)/BSize/32
#define BSize 24
#define QSize 16
struct kernel_para{
volatile int *A, *B, *C;
volatile int size;
volatile int block;
volatile int thread;
volatile int warp;
volatile int req;
volatile int funcId;
volatile int taskId;
volatile int doneHost;
int doneGPU;
};
struct kernel_para_GPU{
int warpId;
int baseId;
int queueId;
int locId;
int taskId;
int funcId;
};
typedef struct {
int contents[BSize][QSize]; // body of queue
int last[BSize]; // position of last element
}queue;
__device__ void init_queue(queue *q){
int tid = blockDim.x*blockIdx.x+threadIdx.x;
if(tid < BSize){
// start form 1, since 1st warp is used in scheduling
if(tid == 0){
q->last[tid] = 1;
}else{
q->last[tid] = 0;
}
for (int i = 0; i < QSize; i++){
q->contents[tid][i] = 0;
}
}
}
__device__ void MatMul_kernel(int *A, int *B, int *C, int M_height, int M_width, int N_width, int baseTid){
#if 1
int row = baseTid + (threadIdx.x & 0x1f);
if(row < M_height) {
for (int j = 0; j < N_width; j++){
int sum = 0;
for (int k = 0; k < M_width; k++){
int a = A[row * M_width + k];
int b = B[k * N_width + j];
sum += a * b;
}
C[row * N_width + j] = sum;
}
}
#endif
}
__global__ void deviceRT(volatile int *done, volatile int *totalExecTasks, volatile kernel_para_GPU *warpPool, volatile struct kernel_para *taskBuffer, struct kernel_para *taskArgs, queue *warpQ){
int tid = blockIdx.x*blockDim.x + threadIdx.x;
int warp;
int j;
if(tid < 32){
if(tid < BSize)
init_queue(warpQ);
warp = 0;
j = 0;
while(!(*done)){
if(*done) continue;
if(tid < BSize){
if(taskBuffer[tid].req == 1 && !(*done)){
warp = taskBuffer[tid].warp;
while(warp > 0){
if(warpQ->contents[tid][warpQ->last[tid]] == 0){
// printf("Scheduling:%d, %d\n", taskBuffer[tid].taskId, tid);
warpPool[tid*QSize + warpQ->last[tid]].queueId = tid;
warpPool[tid*QSize + warpQ->last[tid]].locId = warpQ->last[tid];
warpQ->contents[tid][warpQ->last[tid]] = 1;
warpPool[tid*QSize + warpQ->last[tid]].baseId = j*32;
warpPool[tid*QSize + warpQ->last[tid]].taskId = taskBuffer[tid].taskId;
warpPool[tid*QSize + warpQ->last[tid]].warpId = 1;
__threadfence();
warp--;
j++;
}
warpQ->last[tid]++;
if(warpQ->last[tid] == QSize){
if(tid == 0){
warpQ->last[tid] = 1;
}else{
warpQ->last[tid] = 0;
}
}
}
taskBuffer[tid].req = 0;
j = 0;
}
}
}
}else{
#if 1
int warpIdx = (blockIdx.x*blockDim.x + threadIdx.x)/32;
while(!(*done)){
while(warpPool[warpIdx].warpId == 0 && !(*done));
if(*done) return;
switch(taskArgs[warpPool[warpIdx].taskId].funcId){
case 1:
// if((threadIdx.x & 0x1f) == 0) printf("Before:%d, %d\n", warpPool[warpIdx].taskId, warpPool[warpIdx].baseId);
MatMul_kernel((int*)taskArgs[warpPool[warpIdx].taskId].A, (int*)taskArgs[warpPool[warpIdx].taskId].B, (int*)taskArgs[warpPool[warpIdx].taskId].C, taskArgs[warpPool[warpIdx].taskId].size, taskArgs[warpPool[warpIdx].taskId].size, taskArgs[warpPool[warpIdx].taskId].size, warpPool[warpIdx].baseId);
// if((threadIdx.x & 0x1f) == 0) printf("After:%p\n", taskArgs[warpPool[warpIdx].taskId].C);
break;
default: {
printf("kernel Type not found\n");
return;
}
}
#if 1
if((threadIdx.x & 0x1f) == 0){
if((atomicSub((int*)&taskArgs[warpPool[warpIdx].taskId].doneGPU,1)) ==1){
taskArgs[warpPool[warpIdx].taskId].doneHost = 0;
atomicAdd((int*)&totalExecTasks[0],1);
// printf("Kernel:%d\n", *totalExecTasks);
}
warpPool[warpIdx].warpId = 0;
warpQ->contents[warpPool[warpIdx].queueId][warpPool[warpIdx].locId] = 0;
__threadfence();
}
#endif
}
#endif
}
// }
} | .file "tmpxft_000b2df1_00000000-6_d5.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z10init_queueP5queue
.type _Z10init_queueP5queue, @function
_Z10init_queueP5queue:
.LFB2057:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size _Z10init_queueP5queue, .-_Z10init_queueP5queue
.globl _Z13MatMul_kernelPiS_S_iiii
.type _Z13MatMul_kernelPiS_S_iiii, @function
_Z13MatMul_kernelPiS_S_iiii:
.LFB2058:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2058:
.size _Z13MatMul_kernelPiS_S_iiii, .-_Z13MatMul_kernelPiS_S_iiii
.globl _Z76__device_stub__Z8deviceRTPViS0_PV15kernel_para_GPUPV11kernel_paraPS4_P5queuePViS0_PV15kernel_para_GPUPV11kernel_paraPS4_P5queue
.type _Z76__device_stub__Z8deviceRTPViS0_PV15kernel_para_GPUPV11kernel_paraPS4_P5queuePViS0_PV15kernel_para_GPUPV11kernel_paraPS4_P5queue, @function
_Z76__device_stub__Z8deviceRTPViS0_PV15kernel_para_GPUPV11kernel_paraPS4_P5queuePViS0_PV15kernel_para_GPUPV11kernel_paraPS4_P5queue:
.LFB2083:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movq %r8, 8(%rsp)
movq %r9, (%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
movq %rsp, %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L11
.L7:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L12
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z8deviceRTPViS0_PV15kernel_para_GPUPV11kernel_paraPS4_P5queue(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L7
.L12:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z76__device_stub__Z8deviceRTPViS0_PV15kernel_para_GPUPV11kernel_paraPS4_P5queuePViS0_PV15kernel_para_GPUPV11kernel_paraPS4_P5queue, .-_Z76__device_stub__Z8deviceRTPViS0_PV15kernel_para_GPUPV11kernel_paraPS4_P5queuePViS0_PV15kernel_para_GPUPV11kernel_paraPS4_P5queue
.globl _Z8deviceRTPViS0_PV15kernel_para_GPUPV11kernel_paraPS4_P5queue
.type _Z8deviceRTPViS0_PV15kernel_para_GPUPV11kernel_paraPS4_P5queue, @function
_Z8deviceRTPViS0_PV15kernel_para_GPUPV11kernel_paraPS4_P5queue:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z76__device_stub__Z8deviceRTPViS0_PV15kernel_para_GPUPV11kernel_paraPS4_P5queuePViS0_PV15kernel_para_GPUPV11kernel_paraPS4_P5queue
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z8deviceRTPViS0_PV15kernel_para_GPUPV11kernel_paraPS4_P5queue, .-_Z8deviceRTPViS0_PV15kernel_para_GPUPV11kernel_paraPS4_P5queue
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z8deviceRTPViS0_PV15kernel_para_GPUPV11kernel_paraPS4_P5queue"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z8deviceRTPViS0_PV15kernel_para_GPUPV11kernel_paraPS4_P5queue(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <stdlib.h>
#include <stdint.h>
#define BLOCKS 12
#define BLOCKSIZE 1024
//#define BSize 32
//#define QSize (BLOCKS*BLOCKSIZE)/BSize/32
#define BSize 24
#define QSize 16
struct kernel_para{
volatile int *A, *B, *C;
volatile int size;
volatile int block;
volatile int thread;
volatile int warp;
volatile int req;
volatile int funcId;
volatile int taskId;
volatile int doneHost;
int doneGPU;
};
struct kernel_para_GPU{
int warpId;
int baseId;
int queueId;
int locId;
int taskId;
int funcId;
};
typedef struct {
int contents[BSize][QSize]; // body of queue
int last[BSize]; // position of last element
}queue;
__device__ void init_queue(queue *q){
int tid = blockDim.x*blockIdx.x+threadIdx.x;
if(tid < BSize){
// start form 1, since 1st warp is used in scheduling
if(tid == 0){
q->last[tid] = 1;
}else{
q->last[tid] = 0;
}
for (int i = 0; i < QSize; i++){
q->contents[tid][i] = 0;
}
}
}
__device__ void MatMul_kernel(int *A, int *B, int *C, int M_height, int M_width, int N_width, int baseTid){
#if 1
int row = baseTid + (threadIdx.x & 0x1f);
if(row < M_height) {
for (int j = 0; j < N_width; j++){
int sum = 0;
for (int k = 0; k < M_width; k++){
int a = A[row * M_width + k];
int b = B[k * N_width + j];
sum += a * b;
}
C[row * N_width + j] = sum;
}
}
#endif
}
__global__ void deviceRT(volatile int *done, volatile int *totalExecTasks, volatile kernel_para_GPU *warpPool, volatile struct kernel_para *taskBuffer, struct kernel_para *taskArgs, queue *warpQ){
int tid = blockIdx.x*blockDim.x + threadIdx.x;
int warp;
int j;
if(tid < 32){
if(tid < BSize)
init_queue(warpQ);
warp = 0;
j = 0;
while(!(*done)){
if(*done) continue;
if(tid < BSize){
if(taskBuffer[tid].req == 1 && !(*done)){
warp = taskBuffer[tid].warp;
while(warp > 0){
if(warpQ->contents[tid][warpQ->last[tid]] == 0){
// printf("Scheduling:%d, %d\n", taskBuffer[tid].taskId, tid);
warpPool[tid*QSize + warpQ->last[tid]].queueId = tid;
warpPool[tid*QSize + warpQ->last[tid]].locId = warpQ->last[tid];
warpQ->contents[tid][warpQ->last[tid]] = 1;
warpPool[tid*QSize + warpQ->last[tid]].baseId = j*32;
warpPool[tid*QSize + warpQ->last[tid]].taskId = taskBuffer[tid].taskId;
warpPool[tid*QSize + warpQ->last[tid]].warpId = 1;
__threadfence();
warp--;
j++;
}
warpQ->last[tid]++;
if(warpQ->last[tid] == QSize){
if(tid == 0){
warpQ->last[tid] = 1;
}else{
warpQ->last[tid] = 0;
}
}
}
taskBuffer[tid].req = 0;
j = 0;
}
}
}
}else{
#if 1
int warpIdx = (blockIdx.x*blockDim.x + threadIdx.x)/32;
while(!(*done)){
while(warpPool[warpIdx].warpId == 0 && !(*done));
if(*done) return;
switch(taskArgs[warpPool[warpIdx].taskId].funcId){
case 1:
// if((threadIdx.x & 0x1f) == 0) printf("Before:%d, %d\n", warpPool[warpIdx].taskId, warpPool[warpIdx].baseId);
MatMul_kernel((int*)taskArgs[warpPool[warpIdx].taskId].A, (int*)taskArgs[warpPool[warpIdx].taskId].B, (int*)taskArgs[warpPool[warpIdx].taskId].C, taskArgs[warpPool[warpIdx].taskId].size, taskArgs[warpPool[warpIdx].taskId].size, taskArgs[warpPool[warpIdx].taskId].size, warpPool[warpIdx].baseId);
// if((threadIdx.x & 0x1f) == 0) printf("After:%p\n", taskArgs[warpPool[warpIdx].taskId].C);
break;
default: {
printf("kernel Type not found\n");
return;
}
}
#if 1
if((threadIdx.x & 0x1f) == 0){
if((atomicSub((int*)&taskArgs[warpPool[warpIdx].taskId].doneGPU,1)) ==1){
taskArgs[warpPool[warpIdx].taskId].doneHost = 0;
atomicAdd((int*)&totalExecTasks[0],1);
// printf("Kernel:%d\n", *totalExecTasks);
}
warpPool[warpIdx].warpId = 0;
warpQ->contents[warpPool[warpIdx].queueId][warpPool[warpIdx].locId] = 0;
__threadfence();
}
#endif
}
#endif
}
// }
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <stdint.h>
#define BLOCKS 12
#define BLOCKSIZE 1024
//#define BSize 32
//#define QSize (BLOCKS*BLOCKSIZE)/BSize/32
#define BSize 24
#define QSize 16
struct kernel_para{
volatile int *A, *B, *C;
volatile int size;
volatile int block;
volatile int thread;
volatile int warp;
volatile int req;
volatile int funcId;
volatile int taskId;
volatile int doneHost;
int doneGPU;
};
struct kernel_para_GPU{
int warpId;
int baseId;
int queueId;
int locId;
int taskId;
int funcId;
};
typedef struct {
int contents[BSize][QSize]; // body of queue
int last[BSize]; // position of last element
}queue;
__device__ void init_queue(queue *q){
int tid = blockDim.x*blockIdx.x+threadIdx.x;
if(tid < BSize){
// start form 1, since 1st warp is used in scheduling
if(tid == 0){
q->last[tid] = 1;
}else{
q->last[tid] = 0;
}
for (int i = 0; i < QSize; i++){
q->contents[tid][i] = 0;
}
}
}
__device__ void MatMul_kernel(int *A, int *B, int *C, int M_height, int M_width, int N_width, int baseTid){
#if 1
int row = baseTid + (threadIdx.x & 0x1f);
if(row < M_height) {
for (int j = 0; j < N_width; j++){
int sum = 0;
for (int k = 0; k < M_width; k++){
int a = A[row * M_width + k];
int b = B[k * N_width + j];
sum += a * b;
}
C[row * N_width + j] = sum;
}
}
#endif
}
__global__ void deviceRT(volatile int *done, volatile int *totalExecTasks, volatile kernel_para_GPU *warpPool, volatile struct kernel_para *taskBuffer, struct kernel_para *taskArgs, queue *warpQ){
int tid = blockIdx.x*blockDim.x + threadIdx.x;
int warp;
int j;
if(tid < 32){
if(tid < BSize)
init_queue(warpQ);
warp = 0;
j = 0;
while(!(*done)){
if(*done) continue;
if(tid < BSize){
if(taskBuffer[tid].req == 1 && !(*done)){
warp = taskBuffer[tid].warp;
while(warp > 0){
if(warpQ->contents[tid][warpQ->last[tid]] == 0){
// printf("Scheduling:%d, %d\n", taskBuffer[tid].taskId, tid);
warpPool[tid*QSize + warpQ->last[tid]].queueId = tid;
warpPool[tid*QSize + warpQ->last[tid]].locId = warpQ->last[tid];
warpQ->contents[tid][warpQ->last[tid]] = 1;
warpPool[tid*QSize + warpQ->last[tid]].baseId = j*32;
warpPool[tid*QSize + warpQ->last[tid]].taskId = taskBuffer[tid].taskId;
warpPool[tid*QSize + warpQ->last[tid]].warpId = 1;
__threadfence();
warp--;
j++;
}
warpQ->last[tid]++;
if(warpQ->last[tid] == QSize){
if(tid == 0){
warpQ->last[tid] = 1;
}else{
warpQ->last[tid] = 0;
}
}
}
taskBuffer[tid].req = 0;
j = 0;
}
}
}
}else{
#if 1
int warpIdx = (blockIdx.x*blockDim.x + threadIdx.x)/32;
while(!(*done)){
while(warpPool[warpIdx].warpId == 0 && !(*done));
if(*done) return;
switch(taskArgs[warpPool[warpIdx].taskId].funcId){
case 1:
// if((threadIdx.x & 0x1f) == 0) printf("Before:%d, %d\n", warpPool[warpIdx].taskId, warpPool[warpIdx].baseId);
MatMul_kernel((int*)taskArgs[warpPool[warpIdx].taskId].A, (int*)taskArgs[warpPool[warpIdx].taskId].B, (int*)taskArgs[warpPool[warpIdx].taskId].C, taskArgs[warpPool[warpIdx].taskId].size, taskArgs[warpPool[warpIdx].taskId].size, taskArgs[warpPool[warpIdx].taskId].size, warpPool[warpIdx].baseId);
// if((threadIdx.x & 0x1f) == 0) printf("After:%p\n", taskArgs[warpPool[warpIdx].taskId].C);
break;
default: {
printf("kernel Type not found\n");
return;
}
}
#if 1
if((threadIdx.x & 0x1f) == 0){
if((atomicSub((int*)&taskArgs[warpPool[warpIdx].taskId].doneGPU,1)) ==1){
taskArgs[warpPool[warpIdx].taskId].doneHost = 0;
atomicAdd((int*)&totalExecTasks[0],1);
// printf("Kernel:%d\n", *totalExecTasks);
}
warpPool[warpIdx].warpId = 0;
warpQ->contents[warpPool[warpIdx].queueId][warpPool[warpIdx].locId] = 0;
__threadfence();
}
#endif
}
#endif
}
// }
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <stdint.h>
#define BLOCKS 12
#define BLOCKSIZE 1024
//#define BSize 32
//#define QSize (BLOCKS*BLOCKSIZE)/BSize/32
#define BSize 24
#define QSize 16
struct kernel_para{
volatile int *A, *B, *C;
volatile int size;
volatile int block;
volatile int thread;
volatile int warp;
volatile int req;
volatile int funcId;
volatile int taskId;
volatile int doneHost;
int doneGPU;
};
struct kernel_para_GPU{
int warpId;
int baseId;
int queueId;
int locId;
int taskId;
int funcId;
};
typedef struct {
int contents[BSize][QSize]; // body of queue
int last[BSize]; // position of last element
}queue;
__device__ void init_queue(queue *q){
int tid = blockDim.x*blockIdx.x+threadIdx.x;
if(tid < BSize){
// start form 1, since 1st warp is used in scheduling
if(tid == 0){
q->last[tid] = 1;
}else{
q->last[tid] = 0;
}
for (int i = 0; i < QSize; i++){
q->contents[tid][i] = 0;
}
}
}
__device__ void MatMul_kernel(int *A, int *B, int *C, int M_height, int M_width, int N_width, int baseTid){
#if 1
int row = baseTid + (threadIdx.x & 0x1f);
if(row < M_height) {
for (int j = 0; j < N_width; j++){
int sum = 0;
for (int k = 0; k < M_width; k++){
int a = A[row * M_width + k];
int b = B[k * N_width + j];
sum += a * b;
}
C[row * N_width + j] = sum;
}
}
#endif
}
__global__ void deviceRT(volatile int *done, volatile int *totalExecTasks, volatile kernel_para_GPU *warpPool, volatile struct kernel_para *taskBuffer, struct kernel_para *taskArgs, queue *warpQ){
int tid = blockIdx.x*blockDim.x + threadIdx.x;
int warp;
int j;
if(tid < 32){
if(tid < BSize)
init_queue(warpQ);
warp = 0;
j = 0;
while(!(*done)){
if(*done) continue;
if(tid < BSize){
if(taskBuffer[tid].req == 1 && !(*done)){
warp = taskBuffer[tid].warp;
while(warp > 0){
if(warpQ->contents[tid][warpQ->last[tid]] == 0){
// printf("Scheduling:%d, %d\n", taskBuffer[tid].taskId, tid);
warpPool[tid*QSize + warpQ->last[tid]].queueId = tid;
warpPool[tid*QSize + warpQ->last[tid]].locId = warpQ->last[tid];
warpQ->contents[tid][warpQ->last[tid]] = 1;
warpPool[tid*QSize + warpQ->last[tid]].baseId = j*32;
warpPool[tid*QSize + warpQ->last[tid]].taskId = taskBuffer[tid].taskId;
warpPool[tid*QSize + warpQ->last[tid]].warpId = 1;
__threadfence();
warp--;
j++;
}
warpQ->last[tid]++;
if(warpQ->last[tid] == QSize){
if(tid == 0){
warpQ->last[tid] = 1;
}else{
warpQ->last[tid] = 0;
}
}
}
taskBuffer[tid].req = 0;
j = 0;
}
}
}
}else{
#if 1
int warpIdx = (blockIdx.x*blockDim.x + threadIdx.x)/32;
while(!(*done)){
while(warpPool[warpIdx].warpId == 0 && !(*done));
if(*done) return;
switch(taskArgs[warpPool[warpIdx].taskId].funcId){
case 1:
// if((threadIdx.x & 0x1f) == 0) printf("Before:%d, %d\n", warpPool[warpIdx].taskId, warpPool[warpIdx].baseId);
MatMul_kernel((int*)taskArgs[warpPool[warpIdx].taskId].A, (int*)taskArgs[warpPool[warpIdx].taskId].B, (int*)taskArgs[warpPool[warpIdx].taskId].C, taskArgs[warpPool[warpIdx].taskId].size, taskArgs[warpPool[warpIdx].taskId].size, taskArgs[warpPool[warpIdx].taskId].size, warpPool[warpIdx].baseId);
// if((threadIdx.x & 0x1f) == 0) printf("After:%p\n", taskArgs[warpPool[warpIdx].taskId].C);
break;
default: {
printf("kernel Type not found\n");
return;
}
}
#if 1
if((threadIdx.x & 0x1f) == 0){
if((atomicSub((int*)&taskArgs[warpPool[warpIdx].taskId].doneGPU,1)) ==1){
taskArgs[warpPool[warpIdx].taskId].doneHost = 0;
atomicAdd((int*)&totalExecTasks[0],1);
// printf("Kernel:%d\n", *totalExecTasks);
}
warpPool[warpIdx].warpId = 0;
warpQ->contents[warpPool[warpIdx].queueId][warpPool[warpIdx].locId] = 0;
__threadfence();
}
#endif
}
#endif
}
// }
} | .text
.file "d5.hip"
.globl _Z23__device_stub__deviceRTPViS0_PV15kernel_para_GPUPV11kernel_paraPS4_P5queue # -- Begin function _Z23__device_stub__deviceRTPViS0_PV15kernel_para_GPUPV11kernel_paraPS4_P5queue
.p2align 4, 0x90
.type _Z23__device_stub__deviceRTPViS0_PV15kernel_para_GPUPV11kernel_paraPS4_P5queue,@function
_Z23__device_stub__deviceRTPViS0_PV15kernel_para_GPUPV11kernel_paraPS4_P5queue: # @_Z23__device_stub__deviceRTPViS0_PV15kernel_para_GPUPV11kernel_paraPS4_P5queue
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
movq %r9, 48(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z8deviceRTPViS0_PV15kernel_para_GPUPV11kernel_paraPS4_P5queue, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z23__device_stub__deviceRTPViS0_PV15kernel_para_GPUPV11kernel_paraPS4_P5queue, .Lfunc_end0-_Z23__device_stub__deviceRTPViS0_PV15kernel_para_GPUPV11kernel_paraPS4_P5queue
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8deviceRTPViS0_PV15kernel_para_GPUPV11kernel_paraPS4_P5queue, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z8deviceRTPViS0_PV15kernel_para_GPUPV11kernel_paraPS4_P5queue,@object # @_Z8deviceRTPViS0_PV15kernel_para_GPUPV11kernel_paraPS4_P5queue
.section .rodata,"a",@progbits
.globl _Z8deviceRTPViS0_PV15kernel_para_GPUPV11kernel_paraPS4_P5queue
.p2align 3, 0x0
_Z8deviceRTPViS0_PV15kernel_para_GPUPV11kernel_paraPS4_P5queue:
.quad _Z23__device_stub__deviceRTPViS0_PV15kernel_para_GPUPV11kernel_paraPS4_P5queue
.size _Z8deviceRTPViS0_PV15kernel_para_GPUPV11kernel_paraPS4_P5queue, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z8deviceRTPViS0_PV15kernel_para_GPUPV11kernel_paraPS4_P5queue"
.size .L__unnamed_1, 63
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__deviceRTPViS0_PV15kernel_para_GPUPV11kernel_paraPS4_P5queue
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8deviceRTPViS0_PV15kernel_para_GPUPV11kernel_paraPS4_P5queue
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000b2df1_00000000-6_d5.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z10init_queueP5queue
.type _Z10init_queueP5queue, @function
_Z10init_queueP5queue:
.LFB2057:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size _Z10init_queueP5queue, .-_Z10init_queueP5queue
.globl _Z13MatMul_kernelPiS_S_iiii
.type _Z13MatMul_kernelPiS_S_iiii, @function
_Z13MatMul_kernelPiS_S_iiii:
.LFB2058:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2058:
.size _Z13MatMul_kernelPiS_S_iiii, .-_Z13MatMul_kernelPiS_S_iiii
.globl _Z76__device_stub__Z8deviceRTPViS0_PV15kernel_para_GPUPV11kernel_paraPS4_P5queuePViS0_PV15kernel_para_GPUPV11kernel_paraPS4_P5queue
.type _Z76__device_stub__Z8deviceRTPViS0_PV15kernel_para_GPUPV11kernel_paraPS4_P5queuePViS0_PV15kernel_para_GPUPV11kernel_paraPS4_P5queue, @function
_Z76__device_stub__Z8deviceRTPViS0_PV15kernel_para_GPUPV11kernel_paraPS4_P5queuePViS0_PV15kernel_para_GPUPV11kernel_paraPS4_P5queue:
.LFB2083:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movq %r8, 8(%rsp)
movq %r9, (%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
movq %rsp, %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L11
.L7:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L12
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z8deviceRTPViS0_PV15kernel_para_GPUPV11kernel_paraPS4_P5queue(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L7
.L12:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z76__device_stub__Z8deviceRTPViS0_PV15kernel_para_GPUPV11kernel_paraPS4_P5queuePViS0_PV15kernel_para_GPUPV11kernel_paraPS4_P5queue, .-_Z76__device_stub__Z8deviceRTPViS0_PV15kernel_para_GPUPV11kernel_paraPS4_P5queuePViS0_PV15kernel_para_GPUPV11kernel_paraPS4_P5queue
.globl _Z8deviceRTPViS0_PV15kernel_para_GPUPV11kernel_paraPS4_P5queue
.type _Z8deviceRTPViS0_PV15kernel_para_GPUPV11kernel_paraPS4_P5queue, @function
_Z8deviceRTPViS0_PV15kernel_para_GPUPV11kernel_paraPS4_P5queue:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z76__device_stub__Z8deviceRTPViS0_PV15kernel_para_GPUPV11kernel_paraPS4_P5queuePViS0_PV15kernel_para_GPUPV11kernel_paraPS4_P5queue
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z8deviceRTPViS0_PV15kernel_para_GPUPV11kernel_paraPS4_P5queue, .-_Z8deviceRTPViS0_PV15kernel_para_GPUPV11kernel_paraPS4_P5queue
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z8deviceRTPViS0_PV15kernel_para_GPUPV11kernel_paraPS4_P5queue"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z8deviceRTPViS0_PV15kernel_para_GPUPV11kernel_paraPS4_P5queue(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "d5.hip"
.globl _Z23__device_stub__deviceRTPViS0_PV15kernel_para_GPUPV11kernel_paraPS4_P5queue # -- Begin function _Z23__device_stub__deviceRTPViS0_PV15kernel_para_GPUPV11kernel_paraPS4_P5queue
.p2align 4, 0x90
.type _Z23__device_stub__deviceRTPViS0_PV15kernel_para_GPUPV11kernel_paraPS4_P5queue,@function
_Z23__device_stub__deviceRTPViS0_PV15kernel_para_GPUPV11kernel_paraPS4_P5queue: # @_Z23__device_stub__deviceRTPViS0_PV15kernel_para_GPUPV11kernel_paraPS4_P5queue
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
movq %r9, 48(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z8deviceRTPViS0_PV15kernel_para_GPUPV11kernel_paraPS4_P5queue, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z23__device_stub__deviceRTPViS0_PV15kernel_para_GPUPV11kernel_paraPS4_P5queue, .Lfunc_end0-_Z23__device_stub__deviceRTPViS0_PV15kernel_para_GPUPV11kernel_paraPS4_P5queue
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8deviceRTPViS0_PV15kernel_para_GPUPV11kernel_paraPS4_P5queue, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z8deviceRTPViS0_PV15kernel_para_GPUPV11kernel_paraPS4_P5queue,@object # @_Z8deviceRTPViS0_PV15kernel_para_GPUPV11kernel_paraPS4_P5queue
.section .rodata,"a",@progbits
.globl _Z8deviceRTPViS0_PV15kernel_para_GPUPV11kernel_paraPS4_P5queue
.p2align 3, 0x0
_Z8deviceRTPViS0_PV15kernel_para_GPUPV11kernel_paraPS4_P5queue:
.quad _Z23__device_stub__deviceRTPViS0_PV15kernel_para_GPUPV11kernel_paraPS4_P5queue
.size _Z8deviceRTPViS0_PV15kernel_para_GPUPV11kernel_paraPS4_P5queue, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z8deviceRTPViS0_PV15kernel_para_GPUPV11kernel_paraPS4_P5queue"
.size .L__unnamed_1, 63
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__deviceRTPViS0_PV15kernel_para_GPUPV11kernel_paraPS4_P5queue
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8deviceRTPViS0_PV15kernel_para_GPUPV11kernel_paraPS4_P5queue
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | extern "C"
__global__ void JCudaTextureKernel(
float * output,
cudaTextureObject_t texObj,
int width,
int height,
float theta
) {
// Calculate normalized texture coordinates
unsigned int x = blockIdx.x * blockDim.x + threadIdx.x;
unsigned int y = blockIdx.y * blockDim.y + threadIdx.y;
float u = x / (float)width;
float v = y / (float)height;
// Transform coordinates
u -= 0.5f;
v -= 0.5f;
float tu = u * cosf(theta) - v * sinf(theta) + 0.5f;
float tv = v * cosf(theta) + u * sinf(theta) + 0.5f;
// Read from texture and write to global memory
output[y * width + x] = tex2D<float>(texObj, tu, tv);
} | .file "tmpxft_0013255e_00000000-6_JCudaTextureKernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z42__device_stub__Z18JCudaTextureKernelPfyiifPfyiif
.type _Z42__device_stub__Z18JCudaTextureKernelPfyiifPfyiif, @function
_Z42__device_stub__Z18JCudaTextureKernelPfyiifPfyiif:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movss %xmm0, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq JCudaTextureKernel(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z42__device_stub__Z18JCudaTextureKernelPfyiifPfyiif, .-_Z42__device_stub__Z18JCudaTextureKernelPfyiifPfyiif
.globl JCudaTextureKernel
.type JCudaTextureKernel, @function
JCudaTextureKernel:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z42__device_stub__Z18JCudaTextureKernelPfyiifPfyiif
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size JCudaTextureKernel, .-JCudaTextureKernel
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "JCudaTextureKernel"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq JCudaTextureKernel(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | extern "C"
__global__ void JCudaTextureKernel(
float * output,
cudaTextureObject_t texObj,
int width,
int height,
float theta
) {
// Calculate normalized texture coordinates
unsigned int x = blockIdx.x * blockDim.x + threadIdx.x;
unsigned int y = blockIdx.y * blockDim.y + threadIdx.y;
float u = x / (float)width;
float v = y / (float)height;
// Transform coordinates
u -= 0.5f;
v -= 0.5f;
float tu = u * cosf(theta) - v * sinf(theta) + 0.5f;
float tv = v * cosf(theta) + u * sinf(theta) + 0.5f;
// Read from texture and write to global memory
output[y * width + x] = tex2D<float>(texObj, tu, tv);
} | #include <hip/hip_runtime.h>
extern "C"
__global__ void JCudaTextureKernel(
float * output,
hipTextureObject_t texObj,
int width,
int height,
float theta
) {
// Calculate normalized texture coordinates
unsigned int x = blockIdx.x * blockDim.x + threadIdx.x;
unsigned int y = blockIdx.y * blockDim.y + threadIdx.y;
float u = x / (float)width;
float v = y / (float)height;
// Transform coordinates
u -= 0.5f;
v -= 0.5f;
float tu = u * cosf(theta) - v * sinf(theta) + 0.5f;
float tv = v * cosf(theta) + u * sinf(theta) + 0.5f;
// Read from texture and write to global memory
output[y * width + x] = tex2D<float>(texObj, tu, tv);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
extern "C"
__global__ void JCudaTextureKernel(
float * output,
hipTextureObject_t texObj,
int width,
int height,
float theta
) {
// Calculate normalized texture coordinates
unsigned int x = blockIdx.x * blockDim.x + threadIdx.x;
unsigned int y = blockIdx.y * blockDim.y + threadIdx.y;
float u = x / (float)width;
float v = y / (float)height;
// Transform coordinates
u -= 0.5f;
v -= 0.5f;
float tu = u * cosf(theta) - v * sinf(theta) + 0.5f;
float tv = v * cosf(theta) + u * sinf(theta) + 0.5f;
// Read from texture and write to global memory
output[y * width + x] = tex2D<float>(texObj, tu, tv);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected JCudaTextureKernel
.globl JCudaTextureKernel
.p2align 8
.type JCudaTextureKernel,@function
JCudaTextureKernel:
s_load_b32 s8, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
v_cmp_ngt_f32_e64 s2, 0x48000000, |s8|
s_and_b32 s9, s8, 0x7fffffff
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, exec_lo, s2
s_mov_b32 vcc_lo, s2
s_cbranch_vccz .LBB0_7
s_and_b32 s3, s9, 0x7fffff
s_lshr_b32 s4, s9, 23
s_bitset1_b32 s3, 23
s_addk_i32 s4, 0xff88
s_mul_hi_u32 s5, s3, 0xfe5163ab
s_mul_i32 s6, s3, 0x3c439041
s_mul_hi_u32 s7, s3, 0x3c439041
s_add_u32 s5, s5, s6
s_addc_u32 s6, 0, s7
s_mul_i32 s7, s3, 0xdb629599
s_mul_hi_u32 s10, s3, 0xdb629599
s_add_u32 s6, s6, s7
s_addc_u32 s7, 0, s10
s_mul_i32 s10, s3, 0xf534ddc0
s_mul_hi_u32 s11, s3, 0xf534ddc0
s_add_u32 s7, s7, s10
s_addc_u32 s10, 0, s11
s_mul_i32 s11, s3, 0xfc2757d1
s_mul_hi_u32 s12, s3, 0xfc2757d1
s_add_u32 s10, s10, s11
s_addc_u32 s11, 0, s12
s_mul_i32 s12, s3, 0x4e441529
s_mul_hi_u32 s13, s3, 0x4e441529
s_add_u32 s11, s11, s12
s_addc_u32 s12, 0, s13
s_cmp_gt_u32 s4, 63
s_mul_i32 s13, s3, 0xfe5163ab
s_mul_hi_u32 s16, s3, 0xa2f9836e
s_mul_i32 s3, s3, 0xa2f9836e
s_cselect_b32 s17, s6, s10
s_cselect_b32 s5, s5, s7
s_cselect_b32 s6, s13, s6
s_add_u32 s3, s12, s3
s_addc_u32 s12, 0, s16
s_cmp_gt_u32 s4, 63
s_cselect_b32 s13, 0xffffffc0, 0
s_cselect_b32 s7, s7, s11
s_cselect_b32 s3, s10, s3
s_cselect_b32 s10, s11, s12
s_add_i32 s13, s13, s4
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_gt_u32 s13, 31
s_cselect_b32 s4, 0xffffffe0, 0
s_cselect_b32 s11, s7, s3
s_cselect_b32 s3, s3, s10
s_cselect_b32 s7, s17, s7
s_cselect_b32 s10, s5, s17
s_cselect_b32 s5, s6, s5
s_add_i32 s4, s4, s13
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_gt_u32 s4, 31
s_cselect_b32 s6, 0xffffffe0, 0
s_cselect_b32 s3, s11, s3
s_cselect_b32 s11, s7, s11
s_cselect_b32 s7, s10, s7
s_cselect_b32 s5, s5, s10
s_add_i32 s6, s6, s4
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
s_sub_i32 s4, 32, s6
s_cmp_eq_u32 s6, 0
v_mov_b32_e32 v1, s4
s_cselect_b32 s6, -1, 0
v_alignbit_b32 v2, s3, s11, v1
v_alignbit_b32 v3, s11, s7, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_readfirstlane_b32 s4, v2
v_cndmask_b32_e64 v2, v3, s11, s6
s_delay_alu instid0(VALU_DEP_2)
s_cselect_b32 s3, s3, s4
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_alignbit_b32 v3, s3, v2, 30
s_bfe_u32 s10, s3, 0x1001d
s_delay_alu instid0(SALU_CYCLE_1)
s_sub_i32 s4, 0, s10
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_xor_b32_e32 v3, s4, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_clz_i32_u32_e32 v4, v3
v_min_u32_e32 v4, 32, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_lshlrev_b32_e32 v6, 23, v4
v_alignbit_b32 v1, s7, s5, v1
v_sub_nc_u32_e32 v5, 31, v4
v_cndmask_b32_e64 v1, v1, s7, s6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_alignbit_b32 v2, v2, v1, 30
v_alignbit_b32 v1, v1, s5, 30
v_xor_b32_e32 v2, s4, v2
s_delay_alu instid0(VALU_DEP_2)
v_xor_b32_e32 v1, s4, v1
s_lshr_b32 s4, s3, 29
s_lshr_b32 s3, s3, 30
s_lshl_b32 s4, s4, 31
v_alignbit_b32 v3, v3, v2, v5
v_alignbit_b32 v1, v2, v1, v5
s_or_b32 s5, s4, 0.5
s_add_i32 s3, s10, s3
v_sub_nc_u32_e32 v6, s5, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_alignbit_b32 v2, v3, v1, 9
v_clz_i32_u32_e32 v5, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_min_u32_e32 v5, 32, v5
v_sub_nc_u32_e32 v7, 31, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_alignbit_b32 v1, v2, v1, v7
v_lshrrev_b32_e32 v2, 9, v3
v_lshrrev_b32_e32 v1, 9, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_or_b32_e32 v2, v2, v6
v_add_nc_u32_e32 v4, v5, v4
v_lshlrev_b32_e32 v3, 23, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
v_sub_nc_u32_e32 v1, v1, v3
v_mul_f32_e32 v3, 0x3fc90fda, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v1, 0x33000000, v1
v_fma_f32 v4, v2, 0x3fc90fda, -v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_or_b32_e32 v1, s4, v1
v_fmamk_f32 v2, v2, 0x33a22168, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v2, 0x3fc90fda, v1
v_add_f32_e32 v1, v3, v2
s_cbranch_execz .LBB0_8
v_mov_b32_e32 v2, s3
s_mov_b32 vcc_lo, s2
s_cbranch_vccnz .LBB0_9
.LBB0_3:
s_branch .LBB0_10
.LBB0_4:
v_mov_b32_e32 v4, s3
s_mov_b32 vcc_lo, s2
s_cbranch_vccnz .LBB0_11
.LBB0_5:
s_branch .LBB0_12
.LBB0_6:
v_mov_b32_e32 v6, s3
s_branch .LBB0_13
.LBB0_7:
.LBB0_8:
v_mul_f32_e64 v1, 0x3f22f983, |s8|
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_rndne_f32_e32 v2, v1
v_fma_f32 v1, v2, 0xbfc90fda, |s8|
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmamk_f32 v1, v2, 0xb3a22168, v1
v_fmamk_f32 v1, v2, 0xa7c234c4, v1
v_cvt_i32_f32_e32 v2, v2
s_mov_b32 vcc_lo, s2
s_cbranch_vccz .LBB0_3
.LBB0_9:
s_and_b32 s3, s9, 0x7fffff
s_lshr_b32 s4, s9, 23
s_bitset1_b32 s3, 23
s_addk_i32 s4, 0xff88
s_mul_hi_u32 s5, s3, 0xfe5163ab
s_mul_i32 s6, s3, 0x3c439041
s_mul_hi_u32 s7, s3, 0x3c439041
s_add_u32 s5, s5, s6
s_addc_u32 s6, 0, s7
s_mul_i32 s7, s3, 0xdb629599
s_mul_hi_u32 s10, s3, 0xdb629599
s_add_u32 s6, s6, s7
s_addc_u32 s7, 0, s10
s_mul_i32 s10, s3, 0xf534ddc0
s_mul_hi_u32 s11, s3, 0xf534ddc0
s_add_u32 s7, s7, s10
s_addc_u32 s10, 0, s11
s_mul_i32 s11, s3, 0xfc2757d1
s_mul_hi_u32 s12, s3, 0xfc2757d1
s_add_u32 s10, s10, s11
s_addc_u32 s11, 0, s12
s_mul_i32 s12, s3, 0x4e441529
s_mul_hi_u32 s13, s3, 0x4e441529
s_add_u32 s11, s11, s12
s_addc_u32 s12, 0, s13
s_cmp_gt_u32 s4, 63
s_mul_i32 s13, s3, 0xfe5163ab
s_mul_hi_u32 s16, s3, 0xa2f9836e
s_mul_i32 s3, s3, 0xa2f9836e
s_cselect_b32 s17, s6, s10
s_cselect_b32 s5, s5, s7
s_cselect_b32 s6, s13, s6
s_add_u32 s3, s12, s3
s_addc_u32 s12, 0, s16
s_cmp_gt_u32 s4, 63
s_cselect_b32 s13, 0xffffffc0, 0
s_cselect_b32 s7, s7, s11
s_cselect_b32 s3, s10, s3
s_cselect_b32 s10, s11, s12
s_add_i32 s13, s13, s4
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_gt_u32 s13, 31
s_cselect_b32 s4, 0xffffffe0, 0
s_cselect_b32 s11, s7, s3
s_cselect_b32 s3, s3, s10
s_cselect_b32 s7, s17, s7
s_cselect_b32 s10, s5, s17
s_cselect_b32 s5, s6, s5
s_add_i32 s4, s4, s13
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_gt_u32 s4, 31
s_cselect_b32 s6, 0xffffffe0, 0
s_cselect_b32 s3, s11, s3
s_cselect_b32 s11, s7, s11
s_cselect_b32 s7, s10, s7
s_cselect_b32 s5, s5, s10
s_add_i32 s6, s6, s4
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
s_sub_i32 s4, 32, s6
s_cmp_eq_u32 s6, 0
v_mov_b32_e32 v3, s4
s_cselect_b32 s6, -1, 0
v_alignbit_b32 v4, s3, s11, v3
v_alignbit_b32 v5, s11, s7, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_readfirstlane_b32 s4, v4
v_cndmask_b32_e64 v4, v5, s11, s6
s_delay_alu instid0(VALU_DEP_2)
s_cselect_b32 s3, s3, s4
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_alignbit_b32 v5, s3, v4, 30
s_bfe_u32 s10, s3, 0x1001d
s_delay_alu instid0(SALU_CYCLE_1)
s_sub_i32 s4, 0, s10
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_xor_b32_e32 v5, s4, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_clz_i32_u32_e32 v6, v5
v_min_u32_e32 v6, 32, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_lshlrev_b32_e32 v8, 23, v6
v_alignbit_b32 v3, s7, s5, v3
v_sub_nc_u32_e32 v7, 31, v6
v_cndmask_b32_e64 v3, v3, s7, s6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_alignbit_b32 v4, v4, v3, 30
v_alignbit_b32 v3, v3, s5, 30
v_xor_b32_e32 v4, s4, v4
s_delay_alu instid0(VALU_DEP_2)
v_xor_b32_e32 v3, s4, v3
s_lshr_b32 s4, s3, 29
s_lshr_b32 s3, s3, 30
s_lshl_b32 s4, s4, 31
v_alignbit_b32 v5, v5, v4, v7
v_alignbit_b32 v3, v4, v3, v7
s_or_b32 s5, s4, 0.5
s_add_i32 s3, s10, s3
v_sub_nc_u32_e32 v8, s5, v8
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_alignbit_b32 v4, v5, v3, 9
v_clz_i32_u32_e32 v7, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_min_u32_e32 v7, 32, v7
v_sub_nc_u32_e32 v9, 31, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_alignbit_b32 v3, v4, v3, v9
v_lshrrev_b32_e32 v4, 9, v5
v_lshrrev_b32_e32 v3, 9, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_or_b32_e32 v4, v4, v8
v_add_nc_u32_e32 v6, v7, v6
v_lshlrev_b32_e32 v5, 23, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
v_sub_nc_u32_e32 v3, v3, v5
v_mul_f32_e32 v5, 0x3fc90fda, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v3, 0x33000000, v3
v_fma_f32 v6, v4, 0x3fc90fda, -v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_or_b32_e32 v3, s4, v3
v_fmamk_f32 v4, v4, 0x33a22168, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v4, 0x3fc90fda, v3
v_add_f32_e32 v3, v5, v4
s_cbranch_execnz .LBB0_4
.LBB0_10:
v_mul_f32_e64 v3, 0x3f22f983, |s8|
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_rndne_f32_e32 v4, v3
v_fma_f32 v3, v4, 0xbfc90fda, |s8|
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmamk_f32 v3, v4, 0xb3a22168, v3
v_fmamk_f32 v3, v4, 0xa7c234c4, v3
v_cvt_i32_f32_e32 v4, v4
s_mov_b32 vcc_lo, s2
s_cbranch_vccz .LBB0_5
.LBB0_11:
s_and_b32 s3, s9, 0x7fffff
s_lshr_b32 s4, s9, 23
s_bitset1_b32 s3, 23
s_addk_i32 s4, 0xff88
s_mul_hi_u32 s5, s3, 0xfe5163ab
s_mul_i32 s6, s3, 0x3c439041
s_mul_hi_u32 s7, s3, 0x3c439041
s_add_u32 s5, s5, s6
s_addc_u32 s6, 0, s7
s_mul_i32 s7, s3, 0xdb629599
s_mul_hi_u32 s10, s3, 0xdb629599
s_add_u32 s6, s6, s7
s_addc_u32 s7, 0, s10
s_mul_i32 s10, s3, 0xf534ddc0
s_mul_hi_u32 s11, s3, 0xf534ddc0
s_add_u32 s7, s7, s10
s_addc_u32 s10, 0, s11
s_mul_i32 s11, s3, 0xfc2757d1
s_mul_hi_u32 s12, s3, 0xfc2757d1
s_add_u32 s10, s10, s11
s_addc_u32 s11, 0, s12
s_mul_i32 s12, s3, 0x4e441529
s_mul_hi_u32 s13, s3, 0x4e441529
s_add_u32 s11, s11, s12
s_addc_u32 s12, 0, s13
s_cmp_gt_u32 s4, 63
s_mul_i32 s13, s3, 0xfe5163ab
s_mul_hi_u32 s16, s3, 0xa2f9836e
s_mul_i32 s3, s3, 0xa2f9836e
s_cselect_b32 s17, s6, s10
s_cselect_b32 s5, s5, s7
s_cselect_b32 s6, s13, s6
s_add_u32 s3, s12, s3
s_addc_u32 s12, 0, s16
s_cmp_gt_u32 s4, 63
s_cselect_b32 s13, 0xffffffc0, 0
s_cselect_b32 s7, s7, s11
s_cselect_b32 s3, s10, s3
s_cselect_b32 s10, s11, s12
s_add_i32 s13, s13, s4
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_gt_u32 s13, 31
s_cselect_b32 s4, 0xffffffe0, 0
s_cselect_b32 s11, s7, s3
s_cselect_b32 s3, s3, s10
s_cselect_b32 s7, s17, s7
s_cselect_b32 s10, s5, s17
s_cselect_b32 s5, s6, s5
s_add_i32 s4, s4, s13
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_gt_u32 s4, 31
s_cselect_b32 s6, 0xffffffe0, 0
s_cselect_b32 s3, s11, s3
s_cselect_b32 s11, s7, s11
s_cselect_b32 s7, s10, s7
s_cselect_b32 s5, s5, s10
s_add_i32 s6, s6, s4
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
s_sub_i32 s4, 32, s6
s_cmp_eq_u32 s6, 0
v_mov_b32_e32 v5, s4
s_cselect_b32 s6, -1, 0
v_alignbit_b32 v6, s3, s11, v5
v_alignbit_b32 v7, s11, s7, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_readfirstlane_b32 s4, v6
v_cndmask_b32_e64 v6, v7, s11, s6
s_delay_alu instid0(VALU_DEP_2)
s_cselect_b32 s3, s3, s4
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_alignbit_b32 v7, s3, v6, 30
s_bfe_u32 s10, s3, 0x1001d
s_delay_alu instid0(SALU_CYCLE_1)
s_sub_i32 s4, 0, s10
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_xor_b32_e32 v7, s4, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_clz_i32_u32_e32 v8, v7
v_min_u32_e32 v8, 32, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_lshlrev_b32_e32 v10, 23, v8
v_alignbit_b32 v5, s7, s5, v5
v_sub_nc_u32_e32 v9, 31, v8
v_cndmask_b32_e64 v5, v5, s7, s6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_alignbit_b32 v6, v6, v5, 30
v_alignbit_b32 v5, v5, s5, 30
v_xor_b32_e32 v6, s4, v6
s_delay_alu instid0(VALU_DEP_2)
v_xor_b32_e32 v5, s4, v5
s_lshr_b32 s4, s3, 29
s_lshr_b32 s3, s3, 30
s_lshl_b32 s4, s4, 31
v_alignbit_b32 v7, v7, v6, v9
v_alignbit_b32 v5, v6, v5, v9
s_or_b32 s5, s4, 0.5
s_add_i32 s3, s10, s3
v_sub_nc_u32_e32 v10, s5, v10
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_alignbit_b32 v6, v7, v5, 9
v_clz_i32_u32_e32 v9, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_min_u32_e32 v9, 32, v9
v_sub_nc_u32_e32 v11, 31, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_alignbit_b32 v5, v6, v5, v11
v_lshrrev_b32_e32 v6, 9, v7
v_lshrrev_b32_e32 v5, 9, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_or_b32_e32 v6, v6, v10
v_add_nc_u32_e32 v8, v9, v8
v_lshlrev_b32_e32 v7, 23, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
v_sub_nc_u32_e32 v5, v5, v7
v_mul_f32_e32 v7, 0x3fc90fda, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v5, 0x33000000, v5
v_fma_f32 v8, v6, 0x3fc90fda, -v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_or_b32_e32 v5, s4, v5
v_fmamk_f32 v6, v6, 0x33a22168, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v6, 0x3fc90fda, v5
v_add_f32_e32 v5, v7, v6
s_cbranch_execnz .LBB0_6
.LBB0_12:
v_mul_f32_e64 v5, 0x3f22f983, |s8|
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_rndne_f32_e32 v6, v5
v_fma_f32 v5, v6, 0xbfc90fda, |s8|
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmamk_f32 v5, v6, 0xb3a22168, v5
v_fmamk_f32 v5, v6, 0xa7c234c4, v5
v_cvt_i32_f32_e32 v6, v6
.LBB0_13:
s_load_b32 s10, s[0:1], 0x2c
s_mov_b32 vcc_lo, s2
s_cbranch_vccz .LBB0_15
s_and_b32 s2, s9, 0x7fffff
s_lshr_b32 s3, s9, 23
s_bitset1_b32 s2, 23
s_addk_i32 s3, 0xff88
s_mul_hi_u32 s4, s2, 0xfe5163ab
s_mul_i32 s5, s2, 0x3c439041
s_mul_hi_u32 s6, s2, 0x3c439041
s_add_u32 s4, s4, s5
s_addc_u32 s5, 0, s6
s_mul_i32 s6, s2, 0xdb629599
s_mul_hi_u32 s7, s2, 0xdb629599
s_add_u32 s5, s5, s6
s_addc_u32 s6, 0, s7
s_mul_i32 s7, s2, 0xf534ddc0
s_mul_hi_u32 s11, s2, 0xf534ddc0
s_add_u32 s6, s6, s7
s_addc_u32 s7, 0, s11
s_mul_i32 s11, s2, 0xfc2757d1
s_mul_hi_u32 s12, s2, 0xfc2757d1
s_add_u32 s7, s7, s11
s_addc_u32 s11, 0, s12
s_mul_i32 s12, s2, 0x4e441529
s_mul_hi_u32 s13, s2, 0x4e441529
s_add_u32 s11, s11, s12
s_addc_u32 s12, 0, s13
s_cmp_gt_u32 s3, 63
s_mul_i32 s13, s2, 0xfe5163ab
s_mul_hi_u32 s16, s2, 0xa2f9836e
s_mul_i32 s2, s2, 0xa2f9836e
s_cselect_b32 s17, s5, s7
s_cselect_b32 s4, s4, s6
s_cselect_b32 s5, s13, s5
s_add_u32 s2, s12, s2
s_addc_u32 s12, 0, s16
s_cmp_gt_u32 s3, 63
s_cselect_b32 s13, 0xffffffc0, 0
s_cselect_b32 s6, s6, s11
s_cselect_b32 s2, s7, s2
s_cselect_b32 s7, s11, s12
s_add_i32 s13, s13, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_gt_u32 s13, 31
s_cselect_b32 s3, 0xffffffe0, 0
s_cselect_b32 s11, s6, s2
s_cselect_b32 s2, s2, s7
s_cselect_b32 s6, s17, s6
s_cselect_b32 s7, s4, s17
s_cselect_b32 s4, s5, s4
s_add_i32 s3, s3, s13
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_gt_u32 s3, 31
s_cselect_b32 s5, 0xffffffe0, 0
s_cselect_b32 s2, s11, s2
s_cselect_b32 s11, s6, s11
s_cselect_b32 s6, s7, s6
s_cselect_b32 s4, s4, s7
s_add_i32 s5, s5, s3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
s_sub_i32 s3, 32, s5
s_cmp_eq_u32 s5, 0
v_mov_b32_e32 v7, s3
s_cselect_b32 s5, -1, 0
v_alignbit_b32 v8, s2, s11, v7
v_alignbit_b32 v9, s11, s6, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_readfirstlane_b32 s3, v8
v_cndmask_b32_e64 v8, v9, s11, s5
s_delay_alu instid0(VALU_DEP_2)
s_cselect_b32 s2, s2, s3
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_alignbit_b32 v9, s2, v8, 30
s_bfe_u32 s7, s2, 0x1001d
s_delay_alu instid0(SALU_CYCLE_1)
s_sub_i32 s3, 0, s7
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_xor_b32_e32 v9, s3, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_clz_i32_u32_e32 v10, v9
v_min_u32_e32 v10, 32, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_lshlrev_b32_e32 v12, 23, v10
v_alignbit_b32 v7, s6, s4, v7
v_sub_nc_u32_e32 v11, 31, v10
v_cndmask_b32_e64 v7, v7, s6, s5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_alignbit_b32 v8, v8, v7, 30
v_alignbit_b32 v7, v7, s4, 30
v_xor_b32_e32 v8, s3, v8
s_delay_alu instid0(VALU_DEP_2)
v_xor_b32_e32 v7, s3, v7
s_lshr_b32 s3, s2, 29
s_lshr_b32 s2, s2, 30
s_lshl_b32 s3, s3, 31
v_alignbit_b32 v9, v9, v8, v11
v_alignbit_b32 v7, v8, v7, v11
s_or_b32 s4, s3, 0.5
s_add_i32 s2, s7, s2
v_sub_nc_u32_e32 v12, s4, v12
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_alignbit_b32 v8, v9, v7, 9
v_clz_i32_u32_e32 v11, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_min_u32_e32 v11, 32, v11
v_sub_nc_u32_e32 v13, 31, v11
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_alignbit_b32 v7, v8, v7, v13
v_lshrrev_b32_e32 v8, 9, v9
v_lshrrev_b32_e32 v7, 9, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_or_b32_e32 v8, v8, v12
v_add_nc_u32_e32 v10, v11, v10
v_lshlrev_b32_e32 v9, 23, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
v_sub_nc_u32_e32 v7, v7, v9
v_mul_f32_e32 v9, 0x3fc90fda, v8
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v7, 0x33000000, v7
v_fma_f32 v10, v8, 0x3fc90fda, -v9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_or_b32_e32 v7, s3, v7
v_fmamk_f32 v8, v8, 0x33a22168, v10
s_mov_b32 s3, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v8, 0x3fc90fda, v7
v_add_f32_e32 v7, v9, v8
s_branch .LBB0_16
.LBB0_15:
s_mov_b32 s3, -1
.LBB0_16:
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 vcc_lo, exec_lo, s3
s_waitcnt lgkmcnt(0)
s_lshr_b32 s11, s10, 16
s_cbranch_vccnz .LBB0_18
v_mul_f32_e64 v7, 0x3f22f983, |s8|
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_rndne_f32_e32 v8, v7
v_fma_f32 v7, v8, 0xbfc90fda, |s8|
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmamk_f32 v7, v8, 0xb3a22168, v7
v_fmamk_f32 v7, v8, 0xa7c234c4, v7
v_cvt_i32_f32_e32 v8, v8
s_branch .LBB0_19
.LBB0_18:
v_mov_b32_e32 v8, s2
.LBB0_19:
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x10
s_load_b128 s[4:7], s[0:1], 0x0
v_bfe_u32 v9, v0, 10, 10
s_and_b32 s1, 0xffff, s11
v_dual_mul_f32 v19, v1, v1 :: v_dual_and_b32 v0, 0x3ff, v0
s_and_b32 s0, 0xffff, s10
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[10:11], null, s15, s1, v[9:10]
v_mad_u64_u32 v[11:12], null, s14, s0, v[0:1]
v_lshlrev_b32_e32 v13, 30, v6
v_dual_mul_f32 v21, v7, v7 :: v_dual_and_b32 v0, 1, v6
v_mul_f32_e32 v6, v5, v5
v_cvt_f32_u32_e32 v12, v10
s_mov_b32 s0, 0xb94c1982
v_cvt_f32_u32_e32 v15, v11
v_dual_mul_f32 v20, v3, v3 :: v_dual_lshlrev_b32 v9, 30, v2
s_waitcnt lgkmcnt(0)
v_cvt_f32_i32_e32 v14, s3
v_cvt_f32_i32_e32 v16, s2
v_fmaak_f32 v25, s0, v6, 0x3c0881c4
s_mov_b32 s10, 0x37d75334
v_fmaak_f32 v28, s0, v20, 0x3c0881c4
v_div_scale_f32 v17, null, v14, v14, v12
v_div_scale_f32 v18, null, v16, v16, v15
v_div_scale_f32 v32, vcc_lo, v12, v14, v12
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_rcp_f32_e32 v22, v17
v_rcp_f32_e32 v23, v18
v_dual_fmaak_f32 v25, v6, v25, 0xbe2aaa9d :: v_dual_and_b32 v2, 1, v2
v_fmaak_f32 v27, s0, v19, 0x3c0881c4
v_cmp_eq_u32_e64 s1, 0, v0
s_load_b32 s3, s[6:7], 0x38
s_delay_alu instid0(VALU_DEP_3)
v_mul_f32_e32 v25, v6, v25
s_load_b128 s[16:19], s[6:7], 0x30
s_waitcnt_depctr 0xfff
v_fma_f32 v30, -v17, v22, 1.0
v_and_b32_e32 v13, 0x80000000, v13
v_fma_f32 v31, -v18, v23, 1.0
v_dual_fmaak_f32 v24, s10, v6, 0xbab64f3b :: v_dual_fmac_f32 v5, v5, v25
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_fmac_f32_e32 v22, v30, v22
v_fmaak_f32 v26, s10, v19, 0xbab64f3b
v_fmac_f32_e32 v23, v31, v23
v_fmaak_f32 v29, s0, v21, 0x3c0881c4
v_div_scale_f32 v33, s0, v15, v16, v15
v_dual_fmaak_f32 v24, v6, v24, 0x3d2aabf7 :: v_dual_mul_f32 v31, v32, v22
v_fmaak_f32 v26, v19, v26, 0x3d2aabf7
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_dual_mul_f32 v34, v33, v23 :: v_dual_and_b32 v9, 0x80000000, v9
v_fmaak_f32 v24, v6, v24, 0xbf000004
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_fma_f32 v35, -v17, v31, v32
v_fmaak_f32 v30, s10, v21, 0xbab64f3b
v_fma_f32 v36, -v18, v34, v33
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_fma_f32 v6, v6, v24, 1.0
v_fmac_f32_e32 v31, v35, v22
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_dual_fmaak_f32 v25, v21, v30, 0x3d2aabf7 :: v_dual_fmac_f32 v34, v36, v23
v_cndmask_b32_e64 v0, -v5, v6, s1
s_delay_alu instid0(VALU_DEP_3)
v_fma_f32 v5, -v17, v31, v32
v_fmaak_f32 v27, v19, v27, 0xbe2aaa9d
s_xor_b32 s1, s9, s8
v_fma_f32 v6, -v18, v34, v33
v_fmaak_f32 v18, v21, v29, 0xbe2aaa9d
v_div_fmas_f32 v5, v5, v22, v31
s_mov_b32 vcc_lo, s0
v_xor_b32_e32 v0, v13, v0
v_div_fmas_f32 v6, v6, v23, v34
v_mul_f32_e32 v18, v21, v18
v_div_fixup_f32 v5, v5, v14, v12
v_fmaak_f32 v24, v19, v26, 0xbf000004
v_and_b32_e32 v12, 1, v8
v_div_fixup_f32 v6, v6, v16, v15
v_fmaak_f32 v17, s10, v20, 0xbab64f3b
v_dual_add_f32 v5, -0.5, v5 :: v_dual_fmaak_f32 v14, v20, v28, 0xbe2aaa9d
v_dual_fmaak_f32 v22, v21, v25, 0xbf000004 :: v_dual_fmac_f32 v7, v7, v18
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_f32_e32 v6, -0.5, v6
v_dual_fmaak_f32 v15, v20, v17, 0x3d2aabf7 :: v_dual_lshlrev_b32 v8, 30, v8
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
v_fma_f32 v13, v21, v22, 1.0
v_cmp_eq_u32_e64 s0, 0, v12
v_cmp_class_f32_e64 vcc_lo, s8, 0x1f8
v_and_b32_e32 v8, 0x80000000, v8
v_fmaak_f32 v15, v20, v15, 0xbf000004
s_load_b32 s8, s[6:7], 0x30
v_cndmask_b32_e64 v7, v13, v7, s0
v_dual_mul_f32 v13, v20, v14 :: v_dual_lshlrev_b32 v14, 30, v4
v_and_b32_e32 v4, 1, v4
v_cndmask_b32_e32 v0, 0x7fc00000, v0, vcc_lo
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_xor_b32_e32 v7, v8, v7
v_fmac_f32_e32 v3, v3, v13
v_fma_f32 v8, v20, v15, 1.0
v_cmp_eq_u32_e64 s0, 0, v4
v_dual_mul_f32 v12, v19, v27 :: v_dual_and_b32 v13, 0x80000000, v14
v_xor_b32_e32 v7, s1, v7
s_clause 0x1
s_load_b32 s9, s[6:7], 0x8
s_load_b32 s10, s[6:7], 0x28
v_cndmask_b32_e64 v3, v8, v3, s0
v_dual_fmac_f32 v1, v1, v12 :: v_dual_cndmask_b32 v4, 0x7fc00000, v7
v_fma_f32 v7, v19, v24, 1.0
v_cmp_eq_u32_e64 s0, 0, v2
s_delay_alu instid0(VALU_DEP_4)
v_xor_b32_e32 v3, v13, v3
s_waitcnt lgkmcnt(0)
s_bitcmp0_b32 s3, 20
v_mul_f32_e32 v4, v6, v4
v_cndmask_b32_e64 v1, -v1, v7, s0
v_xor_b32_e32 v2, s1, v3
s_cselect_b32 s0, -1, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_fmac_f32_e32 v4, v5, v0
s_bitcmp0_b32 s8, 15
v_xor_b32_e32 v0, v9, v1
v_dual_cndmask_b32 v1, 0x7fc00000, v2 :: v_dual_add_f32 v2, 0.5, v4
s_delay_alu instid0(VALU_DEP_1)
v_dual_cndmask_b32 v0, 0x7fc00000, v0 :: v_dual_mul_f32 v1, v5, v1
s_cselect_b32 vcc_lo, -1, 0
s_bfe_u32 s1, s9, 0xe000e
v_cvt_f32_u32_e32 v4, s10
s_add_i32 s1, s1, 1
v_fma_f32 v0, v6, v0, -v1
v_cvt_f32_u32_e32 v3, s1
s_load_b256 s[8:15], s[6:7], 0x0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_dual_add_f32 v0, 0.5, v0 :: v_dual_cndmask_b32 v1, 1.0, v3
v_cndmask_b32_e32 v3, 1.0, v4, vcc_lo
v_rcp_f32_e32 v4, v1
v_mul_f32_e32 v1, v1, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_rcp_f32_e32 v5, v3
v_mul_f32_e32 v3, v0, v3
v_floor_f32_e32 v1, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_floor_f32_e32 v3, v3
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v1, v4, v1
v_mul_f32_e32 v3, v5, v3
v_cndmask_b32_e64 v1, v2, v1, s0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_1)
v_cndmask_b32_e64 v0, v0, v3, s0
s_waitcnt lgkmcnt(0)
image_sample_lz v2, v[0:1], s[8:15], s[16:19] dmask:0x1 dim:SQ_RSRC_IMG_2D
v_mad_u64_u32 v[0:1], null, v10, s2, v[11:12]
v_mov_b32_e32 v1, 0
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
s_waitcnt vmcnt(0)
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel JCudaTextureKernel
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 37
.amdhsa_next_free_sgpr 20
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size JCudaTextureKernel, .Lfunc_end0-JCudaTextureKernel
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: JCudaTextureKernel
.private_segment_fixed_size: 0
.sgpr_count: 22
.sgpr_spill_count: 0
.symbol: JCudaTextureKernel.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 37
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
extern "C"
__global__ void JCudaTextureKernel(
float * output,
hipTextureObject_t texObj,
int width,
int height,
float theta
) {
// Calculate normalized texture coordinates
unsigned int x = blockIdx.x * blockDim.x + threadIdx.x;
unsigned int y = blockIdx.y * blockDim.y + threadIdx.y;
float u = x / (float)width;
float v = y / (float)height;
// Transform coordinates
u -= 0.5f;
v -= 0.5f;
float tu = u * cosf(theta) - v * sinf(theta) + 0.5f;
float tv = v * cosf(theta) + u * sinf(theta) + 0.5f;
// Read from texture and write to global memory
output[y * width + x] = tex2D<float>(texObj, tu, tv);
} | .text
.file "JCudaTextureKernel.hip"
.globl __device_stub__JCudaTextureKernel # -- Begin function __device_stub__JCudaTextureKernel
.p2align 4, 0x90
.type __device_stub__JCudaTextureKernel,@function
__device_stub__JCudaTextureKernel: # @__device_stub__JCudaTextureKernel
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movss %xmm0, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $JCudaTextureKernel, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size __device_stub__JCudaTextureKernel, .Lfunc_end0-__device_stub__JCudaTextureKernel
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $JCudaTextureKernel, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type JCudaTextureKernel,@object # @JCudaTextureKernel
.section .rodata,"a",@progbits
.globl JCudaTextureKernel
.p2align 3, 0x0
JCudaTextureKernel:
.quad __device_stub__JCudaTextureKernel
.size JCudaTextureKernel, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "JCudaTextureKernel"
.size .L__unnamed_1, 19
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub__JCudaTextureKernel
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym JCudaTextureKernel
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0013255e_00000000-6_JCudaTextureKernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z42__device_stub__Z18JCudaTextureKernelPfyiifPfyiif
.type _Z42__device_stub__Z18JCudaTextureKernelPfyiifPfyiif, @function
_Z42__device_stub__Z18JCudaTextureKernelPfyiifPfyiif:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movss %xmm0, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq JCudaTextureKernel(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z42__device_stub__Z18JCudaTextureKernelPfyiifPfyiif, .-_Z42__device_stub__Z18JCudaTextureKernelPfyiifPfyiif
.globl JCudaTextureKernel
.type JCudaTextureKernel, @function
JCudaTextureKernel:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z42__device_stub__Z18JCudaTextureKernelPfyiifPfyiif
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size JCudaTextureKernel, .-JCudaTextureKernel
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "JCudaTextureKernel"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq JCudaTextureKernel(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "JCudaTextureKernel.hip"
.globl __device_stub__JCudaTextureKernel # -- Begin function __device_stub__JCudaTextureKernel
.p2align 4, 0x90
.type __device_stub__JCudaTextureKernel,@function
__device_stub__JCudaTextureKernel: # @__device_stub__JCudaTextureKernel
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movss %xmm0, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $JCudaTextureKernel, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size __device_stub__JCudaTextureKernel, .Lfunc_end0-__device_stub__JCudaTextureKernel
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $JCudaTextureKernel, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type JCudaTextureKernel,@object # @JCudaTextureKernel
.section .rodata,"a",@progbits
.globl JCudaTextureKernel
.p2align 3, 0x0
JCudaTextureKernel:
.quad __device_stub__JCudaTextureKernel
.size JCudaTextureKernel, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "JCudaTextureKernel"
.size .L__unnamed_1, 19
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub__JCudaTextureKernel
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym JCudaTextureKernel
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <thrust/sort.h>
struct t
{
int j,k,l;
};
int main()
{
const int N = 6;
int i;
int keys[N] = { 1, 4, 2, 8, 5, 7};
struct t values[N]= { {3,4,5},{5,6,7},{8,9,10},{11,12,13},{14,15,16},{17,18,19}};
//int *values2[N]= { {13,14,15},{15,16,17},{18,19,110},{111,112,113},{114,15,16},{17,18,19}};
thrust::sort_by_key(keys, keys + N, values );
for(i=0;i<N;i++)
{
printf("%d %d %d\n",values[i].j,values[i].k,values[i].l);
// printf("%d %d %d\n",values2[i][0],values2[i][1],values2[i][2]);
}
printf("i=%d\n",i);
} | code for sm_80
Function : _ZN3cub17CUB_200700_800_NS11EmptyKernelIvEEvv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <thrust/sort.h>
struct t
{
int j,k,l;
};
int main()
{
const int N = 6;
int i;
int keys[N] = { 1, 4, 2, 8, 5, 7};
struct t values[N]= { {3,4,5},{5,6,7},{8,9,10},{11,12,13},{14,15,16},{17,18,19}};
//int *values2[N]= { {13,14,15},{15,16,17},{18,19,110},{111,112,113},{114,15,16},{17,18,19}};
thrust::sort_by_key(keys, keys + N, values );
for(i=0;i<N;i++)
{
printf("%d %d %d\n",values[i].j,values[i].k,values[i].l);
// printf("%d %d %d\n",values2[i][0],values2[i][1],values2[i][2]);
}
printf("i=%d\n",i);
} | #include <hip/hip_runtime.h>
#include <thrust/sort.h>
struct t
{
int j,k,l;
};
int main()
{
const int N = 6;
int i;
int keys[N] = { 1, 4, 2, 8, 5, 7};
struct t values[N]= { {3,4,5},{5,6,7},{8,9,10},{11,12,13},{14,15,16},{17,18,19}};
//int *values2[N]= { {13,14,15},{15,16,17},{18,19,110},{111,112,113},{114,15,16},{17,18,19}};
thrust::sort_by_key(keys, keys + N, values );
for(i=0;i<N;i++)
{
printf("%d %d %d\n",values[i].j,values[i].k,values[i].l);
// printf("%d %d %d\n",values2[i][0],values2[i][1],values2[i][2]);
}
printf("i=%d\n",i);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <thrust/sort.h>
struct t
{
int j,k,l;
};
int main()
{
const int N = 6;
int i;
int keys[N] = { 1, 4, 2, 8, 5, 7};
struct t values[N]= { {3,4,5},{5,6,7},{8,9,10},{11,12,13},{14,15,16},{17,18,19}};
//int *values2[N]= { {13,14,15},{15,16,17},{18,19,110},{111,112,113},{114,15,16},{17,18,19}};
thrust::sort_by_key(keys, keys + N, values );
for(i=0;i<N;i++)
{
printf("%d %d %d\n",values[i].j,values[i].k,values[i].l);
// printf("%d %d %d\n",values2[i][0],values2[i][1],values2[i][2]);
}
printf("i=%d\n",i);
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _ZN3cub17CUB_200700_800_NS11EmptyKernelIvEEvv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <cuda_runtime.h>
#include <stdio.h>
__global__ void divergence_test_ker()
{
if(threadIdx.x % 2 == 0)
printf("threadIdx.x %d : This is an even thread.\n", threadIdx.x);
else
printf("threadIdx.x %d : This is an odd thread.\n", threadIdx.x);
}
__host__ int main()
{
cudaSetDevice(0);
divergence_test_ker <<<1, 32>>>();
cudaDeviceSynchronize();
cudaDeviceReset();
} | code for sm_80
Function : _Z19divergence_test_kerv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fc800078e00ff */
/*0010*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e220000002100 */
/*0020*/ IADD3 R1, R1, -0x8, RZ ; /* 0xfffffff801017810 */
/* 0x000fc80007ffe0ff */
/*0030*/ IADD3 R6, P1, R1, c[0x0][0x20], RZ ; /* 0x0000080001067a10 */
/* 0x000fca0007f3e0ff */
/*0040*/ IMAD.X R7, RZ, RZ, c[0x0][0x24], P1 ; /* 0x00000900ff077624 */
/* 0x000fe200008e06ff */
/*0050*/ STL [R1], R2 ; /* 0x0000000201007387 */
/* 0x0011e20000100800 */
/*0060*/ LOP3.LUT R0, R2, 0x1, RZ, 0xc0, !PT ; /* 0x0000000102007812 */
/* 0x000fc800078ec0ff */
/*0070*/ ISETP.NE.U32.AND P0, PT, R0, 0x1, PT ; /* 0x000000010000780c */
/* 0x000fda0003f05070 */
/*0080*/ @P0 BRA 0x160 ; /* 0x000000d000000947 */
/* 0x000fea0003800000 */
/*0090*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x001fe20000000f00 */
/*00a0*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x10] ; /* 0x01000400ff047624 */
/* 0x000fe400078e00ff */
/*00b0*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0x14] ; /* 0x01000500ff057624 */
/* 0x000fe200078e00ff */
/*00c0*/ LDC.64 R2, c[0x4][R0] ; /* 0x0100000000027b82 */
/* 0x00006c0000000a00 */
/*00d0*/ LEPC R8 ; /* 0x000000000008734e */
/* 0x000fe20000000000 */
/*00e0*/ MOV R11, 0x150 ; /* 0x00000150000b7802 */
/* 0x000fe40000000f00 */
/*00f0*/ MOV R20, 0xd0 ; /* 0x000000d000147802 */
/* 0x000fe40000000f00 */
/*0100*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*0110*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x001fc40000000f00 */
/*0120*/ IADD3 R20, P0, P1, -R20, R11, R8 ; /* 0x0000000b14147210 */
/* 0x000fc8000791e108 */
/*0130*/ IADD3.X R21, ~R0, R21, R9, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2509 */
/*0140*/ CALL.ABS.NOINC R2 ; /* 0x0000000002007343 */
/* 0x002fea0003c00000 */
/*0150*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0160*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x001fe20000000f00 */
/*0170*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x8] ; /* 0x01000200ff047624 */
/* 0x000fe400078e00ff */
/*0180*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0xc] ; /* 0x01000300ff057624 */
/* 0x000fe200078e00ff */
/*0190*/ LDC.64 R2, c[0x4][R0] ; /* 0x0100000000027b82 */
/* 0x00006c0000000a00 */
/*01a0*/ LEPC R8 ; /* 0x000000000008734e */
/* 0x000fe20000000000 */
/*01b0*/ MOV R11, 0x220 ; /* 0x00000220000b7802 */
/* 0x000fe40000000f00 */
/*01c0*/ MOV R20, 0x1a0 ; /* 0x000001a000147802 */
/* 0x000fe40000000f00 */
/*01d0*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*01e0*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x001fc40000000f00 */
/*01f0*/ IADD3 R20, P0, P1, -R20, R11, R8 ; /* 0x0000000b14147210 */
/* 0x000fc8000791e108 */
/*0200*/ IADD3.X R21, ~R0, R21, R9, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2509 */
/*0210*/ CALL.ABS.NOINC R2 ; /* 0x0000000002007343 */
/* 0x002fea0003c00000 */
/*0220*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0230*/ BRA 0x230; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <cuda_runtime.h>
#include <stdio.h>
__global__ void divergence_test_ker()
{
if(threadIdx.x % 2 == 0)
printf("threadIdx.x %d : This is an even thread.\n", threadIdx.x);
else
printf("threadIdx.x %d : This is an odd thread.\n", threadIdx.x);
}
__host__ int main()
{
cudaSetDevice(0);
divergence_test_ker <<<1, 32>>>();
cudaDeviceSynchronize();
cudaDeviceReset();
} | .file "tmpxft_0011046c_00000000-6_divergence_test.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z38__device_stub__Z19divergence_test_kervv
.type _Z38__device_stub__Z19divergence_test_kervv, @function
_Z38__device_stub__Z19divergence_test_kervv:
.LFB2082:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z19divergence_test_kerv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z38__device_stub__Z19divergence_test_kervv, .-_Z38__device_stub__Z19divergence_test_kervv
.globl _Z19divergence_test_kerv
.type _Z19divergence_test_kerv, @function
_Z19divergence_test_kerv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z38__device_stub__Z19divergence_test_kervv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z19divergence_test_kerv, .-_Z19divergence_test_kerv
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movl $0, %edi
call cudaSetDevice@PLT
movl $32, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L12:
call cudaDeviceSynchronize@PLT
call cudaDeviceReset@PLT
movl $0, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
call _Z38__device_stub__Z19divergence_test_kervv
jmp .L12
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z19divergence_test_kerv"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z19divergence_test_kerv(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <cuda_runtime.h>
#include <stdio.h>
__global__ void divergence_test_ker()
{
if(threadIdx.x % 2 == 0)
printf("threadIdx.x %d : This is an even thread.\n", threadIdx.x);
else
printf("threadIdx.x %d : This is an odd thread.\n", threadIdx.x);
}
__host__ int main()
{
cudaSetDevice(0);
divergence_test_ker <<<1, 32>>>();
cudaDeviceSynchronize();
cudaDeviceReset();
} | #include <hip/hip_runtime.h>
#include <stdio.h>
__global__ void divergence_test_ker()
{
if(threadIdx.x % 2 == 0)
printf("threadIdx.x %d : This is an even thread.\n", threadIdx.x);
else
printf("threadIdx.x %d : This is an odd thread.\n", threadIdx.x);
}
__host__ int main()
{
hipSetDevice(0);
divergence_test_ker <<<1, 32>>>();
hipDeviceSynchronize();
hipDeviceReset();
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
__global__ void divergence_test_ker()
{
if(threadIdx.x % 2 == 0)
printf("threadIdx.x %d : This is an even thread.\n", threadIdx.x);
else
printf("threadIdx.x %d : This is an odd thread.\n", threadIdx.x);
}
__host__ int main()
{
hipSetDevice(0);
divergence_test_ker <<<1, 32>>>();
hipDeviceSynchronize();
hipDeviceReset();
} | .text
.file "divergence_test.hip"
.globl _Z34__device_stub__divergence_test_kerv # -- Begin function _Z34__device_stub__divergence_test_kerv
.p2align 4, 0x90
.type _Z34__device_stub__divergence_test_kerv,@function
_Z34__device_stub__divergence_test_kerv: # @_Z34__device_stub__divergence_test_kerv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z19divergence_test_kerv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z34__device_stub__divergence_test_kerv, .Lfunc_end0-_Z34__device_stub__divergence_test_kerv
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
xorl %edi, %edi
callq hipSetDevice
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 31(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z19divergence_test_kerv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
callq hipDeviceSynchronize
callq hipDeviceReset
xorl %eax, %eax
addq $56, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z19divergence_test_kerv, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z19divergence_test_kerv,@object # @_Z19divergence_test_kerv
.section .rodata,"a",@progbits
.globl _Z19divergence_test_kerv
.p2align 3, 0x0
_Z19divergence_test_kerv:
.quad _Z34__device_stub__divergence_test_kerv
.size _Z19divergence_test_kerv, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z19divergence_test_kerv"
.size .L__unnamed_1, 25
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z34__device_stub__divergence_test_kerv
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z19divergence_test_kerv
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0011046c_00000000-6_divergence_test.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z38__device_stub__Z19divergence_test_kervv
.type _Z38__device_stub__Z19divergence_test_kervv, @function
_Z38__device_stub__Z19divergence_test_kervv:
.LFB2082:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z19divergence_test_kerv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z38__device_stub__Z19divergence_test_kervv, .-_Z38__device_stub__Z19divergence_test_kervv
.globl _Z19divergence_test_kerv
.type _Z19divergence_test_kerv, @function
_Z19divergence_test_kerv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z38__device_stub__Z19divergence_test_kervv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z19divergence_test_kerv, .-_Z19divergence_test_kerv
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movl $0, %edi
call cudaSetDevice@PLT
movl $32, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L12:
call cudaDeviceSynchronize@PLT
call cudaDeviceReset@PLT
movl $0, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
call _Z38__device_stub__Z19divergence_test_kervv
jmp .L12
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z19divergence_test_kerv"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z19divergence_test_kerv(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "divergence_test.hip"
.globl _Z34__device_stub__divergence_test_kerv # -- Begin function _Z34__device_stub__divergence_test_kerv
.p2align 4, 0x90
.type _Z34__device_stub__divergence_test_kerv,@function
_Z34__device_stub__divergence_test_kerv: # @_Z34__device_stub__divergence_test_kerv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z19divergence_test_kerv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z34__device_stub__divergence_test_kerv, .Lfunc_end0-_Z34__device_stub__divergence_test_kerv
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
xorl %edi, %edi
callq hipSetDevice
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 31(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z19divergence_test_kerv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
callq hipDeviceSynchronize
callq hipDeviceReset
xorl %eax, %eax
addq $56, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z19divergence_test_kerv, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z19divergence_test_kerv,@object # @_Z19divergence_test_kerv
.section .rodata,"a",@progbits
.globl _Z19divergence_test_kerv
.p2align 3, 0x0
_Z19divergence_test_kerv:
.quad _Z34__device_stub__divergence_test_kerv
.size _Z19divergence_test_kerv, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z19divergence_test_kerv"
.size .L__unnamed_1, 25
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z34__device_stub__divergence_test_kerv
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z19divergence_test_kerv
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | extern "C"
{
__global__ void binaryentropy(const int lengthX, const double *x, const double *y, double *z)
{
int i = threadIdx.x + blockIdx.x * blockDim.x;
if (i<lengthX)
{
z[i] = x[i]*log(x[i]/y[i])+ (1.0-x[i])*log((1.0-x[i])/(1.0-y[i]));
}
}
} | code for sm_80
Function : binaryentropy
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e280000002100 */
/*0020*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0030*/ IMAD R0, R3, c[0x0][0x0], R0 ; /* 0x0000000003007a24 */
/* 0x001fca00078e0200 */
/*0040*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x160], PT ; /* 0x0000580000007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ IMAD.MOV.U32 R23, RZ, RZ, 0x8 ; /* 0x00000008ff177424 */
/* 0x000fe200078e00ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0080*/ IMAD.WIDE R6, R0, R23, c[0x0][0x170] ; /* 0x00005c0000067625 */
/* 0x000fcc00078e0217 */
/*0090*/ LDG.E.64 R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000ea2000c1e1b00 */
/*00a0*/ IMAD.WIDE R22, R0, R23, c[0x0][0x168] ; /* 0x00005a0000167625 */
/* 0x000fcc00078e0217 */
/*00b0*/ LDG.E.64 R22, [R22.64] ; /* 0x0000000416167981 */
/* 0x000ee2000c1e1b00 */
/*00c0*/ IMAD.MOV.U32 R2, RZ, RZ, 0x1 ; /* 0x00000001ff027424 */
/* 0x000fe200078e00ff */
/*00d0*/ BSSY B0, 0x250 ; /* 0x0000017000007945 */
/* 0x000fe20003800000 */
/*00e0*/ MUFU.RCP64H R3, R7 ; /* 0x0000000700037308 */
/* 0x004e220000001800 */
/*00f0*/ FSETP.GEU.AND P1, PT, |R23|, 6.5827683646048100446e-37, PT ; /* 0x036000001700780b */
/* 0x008fc60003f2e200 */
/*0100*/ DFMA R4, -R6, R2, 1 ; /* 0x3ff000000604742b */
/* 0x001e0c0000000102 */
/*0110*/ DFMA R4, R4, R4, R4 ; /* 0x000000040404722b */
/* 0x001e0c0000000004 */
/*0120*/ DFMA R4, R2, R4, R2 ; /* 0x000000040204722b */
/* 0x001e0c0000000002 */
/*0130*/ DFMA R2, -R6, R4, 1 ; /* 0x3ff000000602742b */
/* 0x001e0c0000000104 */
/*0140*/ DFMA R2, R4, R2, R4 ; /* 0x000000020402722b */
/* 0x001e0c0000000004 */
/*0150*/ DMUL R16, R22, R2 ; /* 0x0000000216107228 */
/* 0x001e0c0000000000 */
/*0160*/ DFMA R4, -R6, R16, R22 ; /* 0x000000100604722b */
/* 0x001e0c0000000116 */
/*0170*/ DFMA R16, R2, R4, R16 ; /* 0x000000040210722b */
/* 0x0010640000000010 */
/*0180*/ SHF.R.S32.HI R3, RZ, 0x1f, R0 ; /* 0x0000001fff037819 */
/* 0x001fd00000011400 */
/*0190*/ FFMA R2, RZ, R7, R17 ; /* 0x00000007ff027223 */
/* 0x002fca0000000011 */
/*01a0*/ FSETP.GT.AND P0, PT, |R2|, 1.469367938527859385e-39, PT ; /* 0x001000000200780b */
/* 0x000fda0003f04200 */
/*01b0*/ @P0 BRA P1, 0x240 ; /* 0x0000008000000947 */
/* 0x000fea0000800000 */
/*01c0*/ IMAD.MOV.U32 R12, RZ, RZ, R22 ; /* 0x000000ffff0c7224 */
/* 0x000fe200078e0016 */
/*01d0*/ MOV R2, 0x220 ; /* 0x0000022000027802 */
/* 0x000fe20000000f00 */
/*01e0*/ IMAD.MOV.U32 R13, RZ, RZ, R23 ; /* 0x000000ffff0d7224 */
/* 0x000fe400078e0017 */
/*01f0*/ IMAD.MOV.U32 R4, RZ, RZ, R6 ; /* 0x000000ffff047224 */
/* 0x000fe400078e0006 */
/*0200*/ IMAD.MOV.U32 R11, RZ, RZ, R7 ; /* 0x000000ffff0b7224 */
/* 0x000fe400078e0007 */
/*0210*/ CALL.REL.NOINC 0xbd0 ; /* 0x000009b000007944 */
/* 0x000fea0003c00000 */
/*0220*/ IMAD.MOV.U32 R16, RZ, RZ, R8 ; /* 0x000000ffff107224 */
/* 0x001fe400078e0008 */
/*0230*/ IMAD.MOV.U32 R17, RZ, RZ, R9 ; /* 0x000000ffff117224 */
/* 0x000fe400078e0009 */
/*0240*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0250*/ DADD R4, -R6, 1 ; /* 0x3ff0000006047429 */
/* 0x0000a20000000100 */
/*0260*/ ISETP.GT.AND P2, PT, R17, 0xfffff, PT ; /* 0x000fffff1100780c */
/* 0x000fe20003f44270 */
/*0270*/ IMAD.MOV.U32 R6, RZ, RZ, 0x1 ; /* 0x00000001ff067424 */
/* 0x001fe200078e00ff */
/*0280*/ BSSY B0, 0x710 ; /* 0x0000048000007945 */
/* 0x000fe20003800000 */
/*0290*/ IMAD.MOV.U32 R10, RZ, RZ, R16 ; /* 0x000000ffff0a7224 */
/* 0x000fc400078e0010 */
/*02a0*/ MUFU.RCP64H R7, R5 ; /* 0x0000000500077308 */
/* 0x004e220000001800 */
/*02b0*/ IMAD.MOV.U32 R11, RZ, RZ, R17 ; /* 0x000000ffff0b7224 */
/* 0x000fe400078e0011 */
/*02c0*/ IMAD.MOV.U32 R18, RZ, RZ, R16 ; /* 0x000000ffff127224 */
/* 0x000fca00078e0010 */
/*02d0*/ @!P2 DMUL R10, R10, 1.80143985094819840000e+16 ; /* 0x435000000a0aa828 */
/* 0x000e880000000000 */
/*02e0*/ DFMA R8, -R4, R6, 1 ; /* 0x3ff000000408742b */
/* 0x001e0c0000000106 */
/*02f0*/ @!P2 IMAD.MOV.U32 R17, RZ, RZ, R11 ; /* 0x000000ffff11a224 */
/* 0x004fe400078e000b */
/*0300*/ @!P2 IMAD.MOV.U32 R18, RZ, RZ, R10 ; /* 0x000000ffff12a224 */
/* 0x000fe200078e000a */
/*0310*/ DFMA R8, R8, R8, R8 ; /* 0x000000080808722b */
/* 0x001e240000000008 */
/*0320*/ IADD3 R2, R17, -0x1, RZ ; /* 0xffffffff11027810 */
/* 0x000fc80007ffe0ff */
/*0330*/ ISETP.GE.U32.AND P3, PT, R2, 0x7fefffff, PT ; /* 0x7fefffff0200780c */
/* 0x000fe20003f66070 */
/*0340*/ DFMA R8, R6, R8, R6 ; /* 0x000000080608722b */
/* 0x001e080000000006 */
/*0350*/ DADD R6, -R22, 1 ; /* 0x3ff0000016067429 */
/* 0x000fc80000000100 */
/*0360*/ DFMA R12, -R4, R8, 1 ; /* 0x3ff00000040c742b */
/* 0x001e080000000108 */
/*0370*/ @P3 FSETP.NEU.AND P4, PT, R11, RZ, PT ; /* 0x000000ff0b00320b */
/* 0x000fe40003f8d000 */
/*0380*/ DFMA R8, R8, R12, R8 ; /* 0x0000000c0808722b */
/* 0x001e220000000008 */
/*0390*/ FSETP.GEU.AND P1, PT, |R7|, 6.5827683646048100446e-37, PT ; /* 0x036000000700780b */
/* 0x000fca0003f2e200 */
/*03a0*/ DMUL R12, R6, R8 ; /* 0x00000008060c7228 */
/* 0x001e0c0000000000 */
/*03b0*/ DFMA R14, -R4, R12, R6 ; /* 0x0000000c040e722b */
/* 0x001e0c0000000106 */
/*03c0*/ DFMA R8, R8, R14, R12 ; /* 0x0000000e0808722b */
/* 0x0010a4000000000c */
/*03d0*/ @P3 IMAD.MOV.U32 R12, RZ, RZ, 0x0 ; /* 0x00000000ff0c3424 */
/* 0x001fe400078e00ff */
/*03e0*/ @P3 IMAD.MOV.U32 R13, RZ, RZ, 0x7ff00000 ; /* 0x7ff00000ff0d3424 */
/* 0x000fcc00078e00ff */
/*03f0*/ @P3 DFMA R12, R10, R12, +INF ; /* 0x7ff000000a0c342b */
/* 0x000e22000000000c */
/*0400*/ FFMA R2, RZ, R5, R9 ; /* 0x00000005ff027223 */
/* 0x004fca0000000009 */
/*0410*/ FSETP.GT.AND P0, PT, |R2|, 1.469367938527859385e-39, PT ; /* 0x001000000200780b */
/* 0x000fe20003f04200 */
/*0420*/ IMAD.MOV.U32 R2, RZ, RZ, -0x3ff ; /* 0xfffffc01ff027424 */
/* 0x000fe400078e00ff */
/*0430*/ @!P2 IMAD.MOV.U32 R2, RZ, RZ, -0x435 ; /* 0xfffffbcbff02a424 */
/* 0x000fe200078e00ff */
/*0440*/ @P3 FSEL R14, R12, RZ, P4 ; /* 0x000000ff0c0e3208 */
/* 0x001fe40002000000 */
/*0450*/ @P3 FSEL R15, R13, -QNAN , P4 ; /* 0xfff000000d0f3808 */
/* 0x000fe20002000000 */
/*0460*/ @P3 BRA 0x700 ; /* 0x0000029000003947 */
/* 0x000fea0003800000 */
/*0470*/ LOP3.LUT R10, R17.reuse, 0x800fffff, RZ, 0xc0, !PT ; /* 0x800fffff110a7812 */
/* 0x040fe200078ec0ff */
/*0480*/ IMAD.MOV.U32 R14, RZ, RZ, RZ ; /* 0x000000ffff0e7224 */
/* 0x000fe200078e00ff */
/*0490*/ LEA.HI R17, R17, R2, RZ, 0xc ; /* 0x0000000211117211 */
/* 0x000fe200078f60ff */
/*04a0*/ IMAD.MOV.U32 R24, RZ, RZ, 0x3ae80f1e ; /* 0x3ae80f1eff187424 */
/* 0x000fe200078e00ff */
/*04b0*/ LOP3.LUT R19, R10, 0x3ff00000, RZ, 0xfc, !PT ; /* 0x3ff000000a137812 */
/* 0x000fe200078efcff */
/*04c0*/ IMAD.MOV.U32 R25, RZ, RZ, 0x3eb1380b ; /* 0x3eb1380bff197424 */
/* 0x000fc600078e00ff */
/*04d0*/ ISETP.GE.AND P2, PT, R19, 0x3ff6a09f, PT ; /* 0x3ff6a09f1300780c */
/* 0x000fda0003f46270 */
/*04e0*/ @P2 IADD3 R11, R19, -0x100000, RZ ; /* 0xfff00000130b2810 */
/* 0x000fe40007ffe0ff */
/*04f0*/ @P2 IADD3 R17, R17, 0x1, RZ ; /* 0x0000000111112810 */
/* 0x000fc60007ffe0ff */
/*0500*/ @P2 IMAD.MOV.U32 R19, RZ, RZ, R11 ; /* 0x000000ffff132224 */
/* 0x000fe200078e000b */
/*0510*/ LOP3.LUT R16, R17, 0x80000000, RZ, 0x3c, !PT ; /* 0x8000000011107812 */
/* 0x000fe200078e3cff */
/*0520*/ IMAD.MOV.U32 R17, RZ, RZ, 0x43300000 ; /* 0x43300000ff117424 */
/* 0x000fc800078e00ff */
/*0530*/ DADD R20, R18, 1 ; /* 0x3ff0000012147429 */
/* 0x002e080000000000 */
/*0540*/ DADD R18, R18, -1 ; /* 0xbff0000012127429 */
/* 0x000fe40000000000 */
/*0550*/ MUFU.RCP64H R15, R21 ; /* 0x00000015000f7308 */
/* 0x001e240000001800 */
/*0560*/ DADD R16, R16, c[0x2][0x38] ; /* 0x00800e0010107629 */
/* 0x000fc80000000000 */
/*0570*/ DFMA R10, -R20, R14, 1 ; /* 0x3ff00000140a742b */
/* 0x001e0c000000010e */
/*0580*/ DFMA R10, R10, R10, R10 ; /* 0x0000000a0a0a722b */
/* 0x001e0c000000000a */
/*0590*/ DFMA R14, R14, R10, R14 ; /* 0x0000000a0e0e722b */
/* 0x001e0c000000000e */
/*05a0*/ DMUL R12, R14, R18 ; /* 0x000000120e0c7228 */
/* 0x001e0c0000000000 */
/*05b0*/ DFMA R12, R14, R18, R12 ; /* 0x000000120e0c722b */
/* 0x001e0c000000000c */
/*05c0*/ DMUL R10, R12, R12 ; /* 0x0000000c0c0a7228 */
/* 0x001e080000000000 */
/*05d0*/ DADD R26, R18, -R12 ; /* 0x00000000121a7229 */
/* 0x000e48000000080c */
/*05e0*/ DFMA R24, R10, R24, c[0x2][0x0] ; /* 0x008000000a18762b */
/* 0x001e080000000018 */
/*05f0*/ DADD R26, R26, R26 ; /* 0x000000001a1a7229 */
/* 0x002e48000000001a */
/*0600*/ DFMA R24, R10, R24, c[0x2][0x8] ; /* 0x008002000a18762b */
/* 0x001e080000000018 */
/*0610*/ DFMA R26, R18, -R12, R26 ; /* 0x8000000c121a722b */
/* 0x002fc8000000001a */
/*0620*/ DFMA R24, R10, R24, c[0x2][0x10] ; /* 0x008004000a18762b */
/* 0x001e080000000018 */
/*0630*/ DFMA R18, R16, c[0x2][0x40], R12 ; /* 0x0080100010127a2b */
/* 0x000fc8000000000c */
/*0640*/ DFMA R24, R10, R24, c[0x2][0x18] ; /* 0x008006000a18762b */
/* 0x001e080000000018 */
/*0650*/ DMUL R14, R14, R26 ; /* 0x0000001a0e0e7228 */
/* 0x000fc80000000000 */
/*0660*/ DFMA R20, R10, R24, c[0x2][0x20] ; /* 0x008008000a14762b */
/* 0x001e080000000018 */
/*0670*/ DFMA R24, -R16, c[0x2][0x40], R18 ; /* 0x0080100010187a2b */
/* 0x000e480000000112 */
/*0680*/ DFMA R20, R10, R20, c[0x2][0x28] ; /* 0x00800a000a14762b */
/* 0x001e080000000014 */
/*0690*/ DADD R24, -R12, R24 ; /* 0x000000000c187229 */
/* 0x002fc80000000118 */
/*06a0*/ DFMA R20, R10, R20, c[0x2][0x30] ; /* 0x00800c000a14762b */
/* 0x001e0c0000000014 */
/*06b0*/ DMUL R20, R10, R20 ; /* 0x000000140a147228 */
/* 0x001e0c0000000000 */
/*06c0*/ DFMA R14, R12, R20, R14 ; /* 0x000000140c0e722b */
/* 0x001e0c000000000e */
/*06d0*/ DADD R14, R14, -R24 ; /* 0x000000000e0e7229 */
/* 0x001e0c0000000818 */
/*06e0*/ DFMA R14, R16, c[0x2][0x48], R14 ; /* 0x00801200100e7a2b */
/* 0x001e0c000000000e */
/*06f0*/ DADD R14, R18, R14 ; /* 0x00000000120e7229 */
/* 0x00104c000000000e */
/*0700*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0710*/ BSSY B0, 0x7a0 ; /* 0x0000008000007945 */
/* 0x000fe20003800000 */
/*0720*/ DMUL R22, R22, R14 ; /* 0x0000000e16167228 */
/* 0x0022a20000000000 */
/*0730*/ @P0 BRA P1, 0x790 ; /* 0x0000005000000947 */
/* 0x000fea0000800000 */
/*0740*/ IMAD.MOV.U32 R11, RZ, RZ, R5 ; /* 0x000000ffff0b7224 */
/* 0x000fe200078e0005 */
/*0750*/ MOV R2, 0x790 ; /* 0x0000079000027802 */
/* 0x000fe20000000f00 */
/*0760*/ IMAD.MOV.U32 R12, RZ, RZ, R6 ; /* 0x000000ffff0c7224 */
/* 0x000fe400078e0006 */
/*0770*/ IMAD.MOV.U32 R13, RZ, RZ, R7 ; /* 0x000000ffff0d7224 */
/* 0x000fe400078e0007 */
/*0780*/ CALL.REL.NOINC 0xbd0 ; /* 0x0000044000007944 */
/* 0x007fea0003c00000 */
/*0790*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*07a0*/ ISETP.GT.AND P0, PT, R9, 0xfffff, PT ; /* 0x000fffff0900780c */
/* 0x000fe20003f04270 */
/*07b0*/ IMAD.MOV.U32 R4, RZ, RZ, R8 ; /* 0x000000ffff047224 */
/* 0x000fe200078e0008 */
/*07c0*/ BSSY B0, 0xb90 ; /* 0x000003c000007945 */
/* 0x000fe20003800000 */
/*07d0*/ IMAD.MOV.U32 R5, RZ, RZ, R9.reuse ; /* 0x000000ffff057224 */
/* 0x100fe400078e0009 */
/*07e0*/ IMAD.MOV.U32 R14, RZ, RZ, R9 ; /* 0x000000ffff0e7224 */
/* 0x002fc400078e0009 */
/*07f0*/ IMAD.MOV.U32 R15, RZ, RZ, -0x3ff ; /* 0xfffffc01ff0f7424 */
/* 0x000fcc00078e00ff */
/*0800*/ @!P0 DMUL R4, R4, 1.80143985094819840000e+16 ; /* 0x4350000004048828 */
/* 0x000e620000000000 */
/*0810*/ @!P0 IMAD.MOV.U32 R15, RZ, RZ, -0x435 ; /* 0xfffffbcbff0f8424 */
/* 0x000fd200078e00ff */
/*0820*/ @!P0 IMAD.MOV.U32 R14, RZ, RZ, R5 ; /* 0x000000ffff0e8224 */
/* 0x002fe400078e0005 */
/*0830*/ @!P0 IMAD.MOV.U32 R8, RZ, RZ, R4 ; /* 0x000000ffff088224 */
/* 0x000fc600078e0004 */
/*0840*/ IADD3 R2, R14, -0x1, RZ ; /* 0xffffffff0e027810 */
/* 0x000fc80007ffe0ff */
/*0850*/ ISETP.GE.U32.AND P1, PT, R2, 0x7fefffff, PT ; /* 0x7fefffff0200780c */
/* 0x000fe40003f26070 */
/*0860*/ LEA R2, P3, R0, c[0x0][0x178], 0x3 ; /* 0x00005e0000027a11 */
/* 0x000fd600078618ff */
/*0870*/ @P1 IMAD.MOV.U32 R10, RZ, RZ, 0x0 ; /* 0x00000000ff0a1424 */
/* 0x000fe200078e00ff */
/*0880*/ @P1 FSETP.NEU.AND P2, PT, R5, RZ, PT ; /* 0x000000ff0500120b */
/* 0x000fe20003f4d000 */
/*0890*/ @P1 IMAD.MOV.U32 R11, RZ, RZ, 0x7ff00000 ; /* 0x7ff00000ff0b1424 */
/* 0x000fcc00078e00ff */
/*08a0*/ @P1 DFMA R10, R4, R10, +INF ; /* 0x7ff00000040a142b */
/* 0x000e54000000000a */
/*08b0*/ @P1 FSEL R12, R10, RZ, P2 ; /* 0x000000ff0a0c1208 */
/* 0x002fe40001000000 */
/*08c0*/ @P1 FSEL R13, R11, -QNAN , P2 ; /* 0xfff000000b0d1808 */
/* 0x000fe20001000000 */
/*08d0*/ @P1 BRA 0xb80 ; /* 0x000002a000001947 */
/* 0x000fea0003800000 */
/*08e0*/ LOP3.LUT R4, R14.reuse, 0x800fffff, RZ, 0xc0, !PT ; /* 0x800fffff0e047812 */
/* 0x040fe200078ec0ff */
/*08f0*/ IMAD.MOV.U32 R12, RZ, RZ, R8 ; /* 0x000000ffff0c7224 */
/* 0x000fe200078e0008 */
/*0900*/ LEA.HI R14, R14, R15, RZ, 0xc ; /* 0x0000000f0e0e7211 */
/* 0x000fe200078f60ff */
/*0910*/ IMAD.MOV.U32 R18, RZ, RZ, 0x3ae80f1e ; /* 0x3ae80f1eff127424 */
/* 0x001fe200078e00ff */
/*0920*/ LOP3.LUT R13, R4, 0x3ff00000, RZ, 0xfc, !PT ; /* 0x3ff00000040d7812 */
/* 0x000fe200078efcff */
/*0930*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x000fe400078e00ff */
/*0940*/ IMAD.MOV.U32 R19, RZ, RZ, 0x3eb1380b ; /* 0x3eb1380bff137424 */
/* 0x000fe200078e00ff */
/*0950*/ ISETP.GE.AND P0, PT, R13, 0x3ff6a09f, PT ; /* 0x3ff6a09f0d00780c */
/* 0x000fe20003f06270 */
/*0960*/ IMAD.MOV.U32 R15, RZ, RZ, 0x43300000 ; /* 0x43300000ff0f7424 */
/* 0x000fd800078e00ff */
/*0970*/ @P0 IADD3 R5, R13, -0x100000, RZ ; /* 0xfff000000d050810 */
/* 0x000fe40007ffe0ff */
/*0980*/ @P0 IADD3 R14, R14, 0x1, RZ ; /* 0x000000010e0e0810 */
/* 0x000fc60007ffe0ff */
/*0990*/ @P0 IMAD.MOV.U32 R13, RZ, RZ, R5 ; /* 0x000000ffff0d0224 */
/* 0x000fe200078e0005 */
/*09a0*/ LOP3.LUT R14, R14, 0x80000000, RZ, 0x3c, !PT ; /* 0x800000000e0e7812 */
/* 0x000fca00078e3cff */
/*09b0*/ DADD R16, R12, 1 ; /* 0x3ff000000c107429 */
/* 0x000e080000000000 */
/*09c0*/ DADD R12, R12, -1 ; /* 0xbff000000c0c7429 */
/* 0x000fe40000000000 */
/*09d0*/ MUFU.RCP64H R5, R17 ; /* 0x0000001100057308 */
/* 0x001e240000001800 */
/*09e0*/ DADD R14, R14, c[0x2][0x38] ; /* 0x00800e000e0e7629 */
/* 0x000fc80000000000 */
/*09f0*/ DFMA R8, -R16, R4, 1 ; /* 0x3ff000001008742b */
/* 0x001e0c0000000104 */
/*0a00*/ DFMA R8, R8, R8, R8 ; /* 0x000000080808722b */
/* 0x001e0c0000000008 */
/*0a10*/ DFMA R4, R4, R8, R4 ; /* 0x000000080404722b */
/* 0x001e0c0000000004 */
/*0a20*/ DMUL R8, R4, R12 ; /* 0x0000000c04087228 */
/* 0x001e0c0000000000 */
/*0a30*/ DFMA R8, R4, R12, R8 ; /* 0x0000000c0408722b */
/* 0x001e0c0000000008 */
/*0a40*/ DMUL R10, R8, R8 ; /* 0x00000008080a7228 */
/* 0x001e080000000000 */
/*0a50*/ DADD R16, R12, -R8 ; /* 0x000000000c107229 */
/* 0x000e480000000808 */
/*0a60*/ DFMA R18, R10, R18, c[0x2][0x0] ; /* 0x008000000a12762b */
/* 0x001e080000000012 */
/*0a70*/ DADD R20, R16, R16 ; /* 0x0000000010147229 */
/* 0x002fc80000000010 */
/*0a80*/ DFMA R18, R10, R18, c[0x2][0x8] ; /* 0x008002000a12762b */
/* 0x001e080000000012 */
/*0a90*/ DFMA R16, R14, c[0x2][0x40], R8 ; /* 0x008010000e107a2b */
/* 0x000fc80000000008 */
/*0aa0*/ DFMA R18, R10, R18, c[0x2][0x10] ; /* 0x008004000a12762b */
/* 0x001e080000000012 */
/*0ab0*/ DFMA R20, R12, -R8, R20 ; /* 0x800000080c14722b */
/* 0x000fc80000000014 */
/*0ac0*/ DFMA R18, R10, R18, c[0x2][0x18] ; /* 0x008006000a12762b */
/* 0x001e080000000012 */
/*0ad0*/ DFMA R12, -R14, c[0x2][0x40], R16 ; /* 0x008010000e0c7a2b */
/* 0x000fc80000000110 */
/*0ae0*/ DFMA R18, R10, R18, c[0x2][0x20] ; /* 0x008008000a12762b */
/* 0x001e080000000012 */
/*0af0*/ DMUL R20, R4, R20 ; /* 0x0000001404147228 */
/* 0x000fc80000000000 */
/*0b00*/ DFMA R18, R10, R18, c[0x2][0x28] ; /* 0x00800a000a12762b */
/* 0x001e080000000012 */
/*0b10*/ DADD R12, -R8, R12 ; /* 0x00000000080c7229 */
/* 0x000fc8000000010c */
/*0b20*/ DFMA R18, R10, R18, c[0x2][0x30] ; /* 0x00800c000a12762b */
/* 0x001e0c0000000012 */
/*0b30*/ DMUL R18, R10, R18 ; /* 0x000000120a127228 */
/* 0x001e0c0000000000 */
/*0b40*/ DFMA R18, R8, R18, R20 ; /* 0x000000120812722b */
/* 0x001e0c0000000014 */
/*0b50*/ DADD R12, R18, -R12 ; /* 0x00000000120c7229 */
/* 0x001e0c000000080c */
/*0b60*/ DFMA R12, R14, c[0x2][0x48], R12 ; /* 0x008012000e0c7a2b */
/* 0x001e0c000000000c */
/*0b70*/ DADD R12, R16, R12 ; /* 0x00000000100c7229 */
/* 0x00104c000000000c */
/*0b80*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0b90*/ DFMA R12, R6, R12, R22 ; /* 0x0000000c060c722b */
/* 0x006e620000000016 */
/*0ba0*/ LEA.HI.X R3, R0, c[0x0][0x17c], R3, 0x3, P3 ; /* 0x00005f0000037a11 */
/* 0x000fcc00018f1c03 */
/*0bb0*/ STG.E.64 [R2.64], R12 ; /* 0x0000000c02007986 */
/* 0x002fe2000c101b04 */
/*0bc0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0bd0*/ FSETP.GEU.AND P0, PT, |R11|, 1.469367938527859385e-39, PT ; /* 0x001000000b00780b */
/* 0x000fe20003f0e200 */
/*0be0*/ IMAD.MOV.U32 R10, RZ, RZ, R4 ; /* 0x000000ffff0a7224 */
/* 0x000fe200078e0004 */
/*0bf0*/ FSETP.GEU.AND P2, PT, |R13|, 1.469367938527859385e-39, PT ; /* 0x001000000d00780b */
/* 0x000fe20003f4e200 */
/*0c00*/ IMAD.MOV.U32 R20, RZ, RZ, 0x1 ; /* 0x00000001ff147424 */
/* 0x000fe200078e00ff */
/*0c10*/ LOP3.LUT R8, R11.reuse, 0x800fffff, RZ, 0xc0, !PT ; /* 0x800fffff0b087812 */
/* 0x040fe200078ec0ff */
/*0c20*/ IMAD.MOV.U32 R14, RZ, RZ, R12 ; /* 0x000000ffff0e7224 */
/* 0x000fe200078e000c */
/*0c30*/ LOP3.LUT R25, R11, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff000000b197812 */
/* 0x000fe200078ec0ff */
/*0c40*/ BSSY B1, 0x1170 ; /* 0x0000052000017945 */
/* 0x000fe20003800000 */
/*0c50*/ LOP3.LUT R9, R8, 0x3ff00000, RZ, 0xfc, !PT ; /* 0x3ff0000008097812 */
/* 0x000fe200078efcff */
/*0c60*/ IMAD.MOV.U32 R8, RZ, RZ, R4 ; /* 0x000000ffff087224 */
/* 0x000fe200078e0004 */
/*0c70*/ LOP3.LUT R4, R13, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff000000d047812 */
/* 0x000fc600078ec0ff */
/*0c80*/ @!P0 DMUL R8, R10, 8.98846567431157953865e+307 ; /* 0x7fe000000a088828 */
/* 0x000e220000000000 */
/*0c90*/ ISETP.GE.U32.AND P1, PT, R4.reuse, R25, PT ; /* 0x000000190400720c */
/* 0x040fe20003f26070 */
/*0ca0*/ @!P2 IMAD.MOV.U32 R16, RZ, RZ, RZ ; /* 0x000000ffff10a224 */
/* 0x000fe200078e00ff */
/*0cb0*/ @!P2 LOP3.LUT R5, R11, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff000000b05a812 */
/* 0x000fe200078ec0ff */
/*0cc0*/ IMAD.MOV.U32 R24, RZ, RZ, R4 ; /* 0x000000ffff187224 */
/* 0x000fe400078e0004 */
/*0cd0*/ MUFU.RCP64H R21, R9 ; /* 0x0000000900157308 */
/* 0x001e220000001800 */
/*0ce0*/ @!P2 ISETP.GE.U32.AND P3, PT, R4, R5, PT ; /* 0x000000050400a20c */
/* 0x000fe20003f66070 */
/*0cf0*/ IMAD.MOV.U32 R5, RZ, RZ, 0x1ca00000 ; /* 0x1ca00000ff057424 */
/* 0x000fe400078e00ff */
/*0d00*/ @!P0 LOP3.LUT R25, R9, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff0000009198812 */
/* 0x000fc600078ec0ff */
/*0d10*/ @!P2 SEL R17, R5.reuse, 0x63400000, !P3 ; /* 0x634000000511a807 */
/* 0x040fe40005800000 */
/*0d20*/ SEL R15, R5, 0x63400000, !P1 ; /* 0x63400000050f7807 */
/* 0x000fe40004800000 */
/*0d30*/ @!P2 LOP3.LUT R17, R17, 0x80000000, R13.reuse, 0xf8, !PT ; /* 0x800000001111a812 */
/* 0x100fe400078ef80d */
/*0d40*/ LOP3.LUT R15, R15, 0x800fffff, R13, 0xf8, !PT ; /* 0x800fffff0f0f7812 */
/* 0x000fe400078ef80d */
/*0d50*/ @!P2 LOP3.LUT R17, R17, 0x100000, RZ, 0xfc, !PT ; /* 0x001000001111a812 */
/* 0x000fe200078efcff */
/*0d60*/ DFMA R18, R20, -R8, 1 ; /* 0x3ff000001412742b */
/* 0x001e220000000808 */
/*0d70*/ IADD3 R26, R25, -0x1, RZ ; /* 0xffffffff191a7810 */
/* 0x000fc80007ffe0ff */
/*0d80*/ @!P2 DFMA R14, R14, 2, -R16 ; /* 0x400000000e0ea82b */
/* 0x000fc80000000810 */
/*0d90*/ DFMA R18, R18, R18, R18 ; /* 0x000000121212722b */
/* 0x001e0c0000000012 */
/*0da0*/ DFMA R18, R20, R18, R20 ; /* 0x000000121412722b */
/* 0x0010620000000014 */
/*0db0*/ @!P2 LOP3.LUT R24, R15, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff000000f18a812 */
/* 0x000fc800078ec0ff */
/*0dc0*/ IADD3 R20, R24, -0x1, RZ ; /* 0xffffffff18147810 */
/* 0x001fe20007ffe0ff */
/*0dd0*/ DFMA R16, R18, -R8, 1 ; /* 0x3ff000001210742b */
/* 0x002e060000000808 */
/*0de0*/ ISETP.GT.U32.AND P0, PT, R20, 0x7feffffe, PT ; /* 0x7feffffe1400780c */
/* 0x000fc60003f04070 */
/*0df0*/ DFMA R16, R18, R16, R18 ; /* 0x000000101210722b */
/* 0x001e220000000012 */
/*0e00*/ ISETP.GT.U32.OR P0, PT, R26, 0x7feffffe, P0 ; /* 0x7feffffe1a00780c */
/* 0x000fca0000704470 */
/*0e10*/ DMUL R18, R16, R14 ; /* 0x0000000e10127228 */
/* 0x001e0c0000000000 */
/*0e20*/ DFMA R20, R18, -R8, R14 ; /* 0x800000081214722b */
/* 0x001e0c000000000e */
/*0e30*/ DFMA R20, R16, R20, R18 ; /* 0x000000141014722b */
/* 0x0010620000000012 */
/*0e40*/ @P0 BRA 0x1010 ; /* 0x000001c000000947 */
/* 0x000fea0003800000 */
/*0e50*/ LOP3.LUT R13, R11, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff000000b0d7812 */
/* 0x000fc800078ec0ff */
/*0e60*/ ISETP.GE.U32.AND P0, PT, R4.reuse, R13, PT ; /* 0x0000000d0400720c */
/* 0x040fe20003f06070 */
/*0e70*/ IMAD.IADD R12, R4, 0x1, -R13 ; /* 0x00000001040c7824 */
/* 0x000fc600078e0a0d */
/*0e80*/ SEL R5, R5, 0x63400000, !P0 ; /* 0x6340000005057807 */
/* 0x000fe40004000000 */
/*0e90*/ IMNMX R12, R12, -0x46a00000, !PT ; /* 0xb96000000c0c7817 */
/* 0x000fc80007800200 */
/*0ea0*/ IMNMX R12, R12, 0x46a00000, PT ; /* 0x46a000000c0c7817 */
/* 0x000fca0003800200 */
/*0eb0*/ IMAD.IADD R16, R12, 0x1, -R5 ; /* 0x000000010c107824 */
/* 0x001fe400078e0a05 */
/*0ec0*/ IMAD.MOV.U32 R12, RZ, RZ, RZ ; /* 0x000000ffff0c7224 */
/* 0x000fc600078e00ff */
/*0ed0*/ IADD3 R13, R16, 0x7fe00000, RZ ; /* 0x7fe00000100d7810 */
/* 0x000fcc0007ffe0ff */
/*0ee0*/ DMUL R4, R20, R12 ; /* 0x0000000c14047228 */
/* 0x002e140000000000 */
/*0ef0*/ FSETP.GTU.AND P0, PT, |R5|, 1.469367938527859385e-39, PT ; /* 0x001000000500780b */
/* 0x001fda0003f0c200 */
/*0f00*/ @P0 BRA 0x1160 ; /* 0x0000025000000947 */
/* 0x000fea0003800000 */
/*0f10*/ DFMA R8, R20, -R8, R14 ; /* 0x800000081408722b */
/* 0x000e22000000000e */
/*0f20*/ IMAD.MOV.U32 R12, RZ, RZ, RZ ; /* 0x000000ffff0c7224 */
/* 0x000fd200078e00ff */
/*0f30*/ FSETP.NEU.AND P0, PT, R9.reuse, RZ, PT ; /* 0x000000ff0900720b */
/* 0x041fe40003f0d000 */
/*0f40*/ LOP3.LUT R11, R9, 0x80000000, R11, 0x48, !PT ; /* 0x80000000090b7812 */
/* 0x000fc800078e480b */
/*0f50*/ LOP3.LUT R13, R11, R13, RZ, 0xfc, !PT ; /* 0x0000000d0b0d7212 */
/* 0x000fce00078efcff */
/*0f60*/ @!P0 BRA 0x1160 ; /* 0x000001f000008947 */
/* 0x000fea0003800000 */
/*0f70*/ IMAD.MOV R9, RZ, RZ, -R16 ; /* 0x000000ffff097224 */
/* 0x000fe200078e0a10 */
/*0f80*/ DMUL.RP R12, R20, R12 ; /* 0x0000000c140c7228 */
/* 0x000e220000008000 */
/*0f90*/ IMAD.MOV.U32 R8, RZ, RZ, RZ ; /* 0x000000ffff087224 */
/* 0x000fcc00078e00ff */
/*0fa0*/ DFMA R8, R4, -R8, R20 ; /* 0x800000080408722b */
/* 0x000e460000000014 */
/*0fb0*/ LOP3.LUT R11, R13, R11, RZ, 0x3c, !PT ; /* 0x0000000b0d0b7212 */
/* 0x001fc600078e3cff */
/*0fc0*/ IADD3 R8, -R16, -0x43300000, RZ ; /* 0xbcd0000010087810 */
/* 0x002fc80007ffe1ff */
/*0fd0*/ FSETP.NEU.AND P0, PT, |R9|, R8, PT ; /* 0x000000080900720b */
/* 0x000fc80003f0d200 */
/*0fe0*/ FSEL R4, R12, R4, !P0 ; /* 0x000000040c047208 */
/* 0x000fe40004000000 */
/*0ff0*/ FSEL R5, R11, R5, !P0 ; /* 0x000000050b057208 */
/* 0x000fe20004000000 */
/*1000*/ BRA 0x1160 ; /* 0x0000015000007947 */
/* 0x000fea0003800000 */
/*1010*/ DSETP.NAN.AND P0, PT, R12, R12, PT ; /* 0x0000000c0c00722a */
/* 0x000e9c0003f08000 */
/*1020*/ @P0 BRA 0x1140 ; /* 0x0000011000000947 */
/* 0x004fea0003800000 */
/*1030*/ DSETP.NAN.AND P0, PT, R10, R10, PT ; /* 0x0000000a0a00722a */
/* 0x000e9c0003f08000 */
/*1040*/ @P0 BRA 0x1110 ; /* 0x000000c000000947 */
/* 0x004fea0003800000 */
/*1050*/ ISETP.NE.AND P0, PT, R24, R25, PT ; /* 0x000000191800720c */
/* 0x000fe20003f05270 */
/*1060*/ IMAD.MOV.U32 R4, RZ, RZ, 0x0 ; /* 0x00000000ff047424 */
/* 0x000fe400078e00ff */
/*1070*/ IMAD.MOV.U32 R5, RZ, RZ, -0x80000 ; /* 0xfff80000ff057424 */
/* 0x000fd400078e00ff */
/*1080*/ @!P0 BRA 0x1160 ; /* 0x000000d000008947 */
/* 0x000fea0003800000 */
/*1090*/ ISETP.NE.AND P0, PT, R24, 0x7ff00000, PT ; /* 0x7ff000001800780c */
/* 0x000fe40003f05270 */
/*10a0*/ LOP3.LUT R5, R13, 0x80000000, R11, 0x48, !PT ; /* 0x800000000d057812 */
/* 0x000fe400078e480b */
/*10b0*/ ISETP.EQ.OR P0, PT, R25, RZ, !P0 ; /* 0x000000ff1900720c */
/* 0x000fda0004702670 */
/*10c0*/ @P0 LOP3.LUT R8, R5, 0x7ff00000, RZ, 0xfc, !PT ; /* 0x7ff0000005080812 */
/* 0x000fe200078efcff */
/*10d0*/ @!P0 IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff048224 */
/* 0x000fe400078e00ff */
/*10e0*/ @P0 IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff040224 */
/* 0x000fe400078e00ff */
/*10f0*/ @P0 IMAD.MOV.U32 R5, RZ, RZ, R8 ; /* 0x000000ffff050224 */
/* 0x000fe200078e0008 */
/*1100*/ BRA 0x1160 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*1110*/ LOP3.LUT R5, R11, 0x80000, RZ, 0xfc, !PT ; /* 0x000800000b057812 */
/* 0x000fe200078efcff */
/*1120*/ IMAD.MOV.U32 R4, RZ, RZ, R10 ; /* 0x000000ffff047224 */
/* 0x000fe200078e000a */
/*1130*/ BRA 0x1160 ; /* 0x0000002000007947 */
/* 0x000fea0003800000 */
/*1140*/ LOP3.LUT R5, R13, 0x80000, RZ, 0xfc, !PT ; /* 0x000800000d057812 */
/* 0x000fe200078efcff */
/*1150*/ IMAD.MOV.U32 R4, RZ, RZ, R12 ; /* 0x000000ffff047224 */
/* 0x000fe400078e000c */
/*1160*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*1170*/ IMAD.MOV.U32 R8, RZ, RZ, R4 ; /* 0x000000ffff087224 */
/* 0x000fe400078e0004 */
/*1180*/ IMAD.MOV.U32 R9, RZ, RZ, R5 ; /* 0x000000ffff097224 */
/* 0x000fc400078e0005 */
/*1190*/ IMAD.MOV.U32 R4, RZ, RZ, R2 ; /* 0x000000ffff047224 */
/* 0x000fe400078e0002 */
/*11a0*/ IMAD.MOV.U32 R5, RZ, RZ, 0x0 ; /* 0x00000000ff057424 */
/* 0x000fc800078e00ff */
/*11b0*/ RET.REL.NODEC R4 0x0 ; /* 0xffffee4004007950 */
/* 0x000fea0003c3ffff */
/*11c0*/ BRA 0x11c0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*11d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*11e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*11f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | extern "C"
{
__global__ void binaryentropy(const int lengthX, const double *x, const double *y, double *z)
{
int i = threadIdx.x + blockIdx.x * blockDim.x;
if (i<lengthX)
{
z[i] = x[i]*log(x[i]/y[i])+ (1.0-x[i])*log((1.0-x[i])/(1.0-y[i]));
}
}
} | .file "tmpxft_0012c99e_00000000-6_binaryentropy.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z40__device_stub__Z13binaryentropyiPKdS0_PdiPKdS0_Pd
.type _Z40__device_stub__Z13binaryentropyiPKdS0_PdiPKdS0_Pd, @function
_Z40__device_stub__Z13binaryentropyiPKdS0_PdiPKdS0_Pd:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq binaryentropy(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z40__device_stub__Z13binaryentropyiPKdS0_PdiPKdS0_Pd, .-_Z40__device_stub__Z13binaryentropyiPKdS0_PdiPKdS0_Pd
.globl binaryentropy
.type binaryentropy, @function
binaryentropy:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z40__device_stub__Z13binaryentropyiPKdS0_PdiPKdS0_Pd
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size binaryentropy, .-binaryentropy
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "binaryentropy"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq binaryentropy(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | extern "C"
{
__global__ void binaryentropy(const int lengthX, const double *x, const double *y, double *z)
{
int i = threadIdx.x + blockIdx.x * blockDim.x;
if (i<lengthX)
{
z[i] = x[i]*log(x[i]/y[i])+ (1.0-x[i])*log((1.0-x[i])/(1.0-y[i]));
}
}
} | #include <hip/hip_runtime.h>
extern "C"
{
__global__ void binaryentropy(const int lengthX, const double *x, const double *y, double *z)
{
int i = threadIdx.x + blockIdx.x * blockDim.x;
if (i<lengthX)
{
z[i] = x[i]*log(x[i]/y[i])+ (1.0-x[i])*log((1.0-x[i])/(1.0-y[i]));
}
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
extern "C"
{
__global__ void binaryentropy(const int lengthX, const double *x, const double *y, double *z)
{
int i = threadIdx.x + blockIdx.x * blockDim.x;
if (i<lengthX)
{
z[i] = x[i]*log(x[i]/y[i])+ (1.0-x[i])*log((1.0-x[i])/(1.0-y[i]));
}
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected binaryentropy
.globl binaryentropy
.p2align 8
.type binaryentropy,@function
binaryentropy:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x8
s_load_b64 s[2:3], s[0:1], 0x18
v_ashrrev_i32_e32 v2, 31, v1
s_mov_b32 s1, 0x3fe55555
s_mov_b32 s9, 0x3fc7474d
s_mov_b32 s8, 0xd7f4df2e
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 3, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
s_mov_b32 s5, 0x3fc38538
global_load_b64 v[2:3], v[2:3], off
global_load_b64 v[4:5], v[4:5], off
s_mov_b32 s4, 0x6b47b09a
s_mov_b32 s7, 0x3fc3ab76
s_mov_b32 s6, 0xbf559e2b
s_waitcnt vmcnt(1)
v_add_f64 v[6:7], -v[2:3], 1.0
s_waitcnt vmcnt(0)
v_add_f64 v[8:9], -v[4:5], 1.0
v_div_scale_f64 v[10:11], null, v[4:5], v[4:5], v[2:3]
v_div_scale_f64 v[22:23], vcc_lo, v[2:3], v[4:5], v[2:3]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_div_scale_f64 v[12:13], null, v[8:9], v[8:9], v[6:7]
v_rcp_f64_e32 v[14:15], v[10:11]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_rcp_f64_e32 v[16:17], v[12:13]
s_waitcnt_depctr 0xfff
v_fma_f64 v[18:19], -v[10:11], v[14:15], 1.0
v_fma_f64 v[20:21], -v[12:13], v[16:17], 1.0
v_fma_f64 v[14:15], v[14:15], v[18:19], v[14:15]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f64 v[16:17], v[16:17], v[20:21], v[16:17]
v_fma_f64 v[18:19], -v[10:11], v[14:15], 1.0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f64 v[20:21], -v[12:13], v[16:17], 1.0
v_fma_f64 v[14:15], v[14:15], v[18:19], v[14:15]
v_div_scale_f64 v[18:19], s0, v[6:7], v[8:9], v[6:7]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fma_f64 v[16:17], v[16:17], v[20:21], v[16:17]
v_mul_f64 v[20:21], v[22:23], v[14:15]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_f64 v[24:25], v[18:19], v[16:17]
v_fma_f64 v[10:11], -v[10:11], v[20:21], v[22:23]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f64 v[12:13], -v[12:13], v[24:25], v[18:19]
v_div_fmas_f64 v[10:11], v[10:11], v[14:15], v[20:21]
s_mov_b32 vcc_lo, s0
s_mov_b32 s0, 0x55555555
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_div_fmas_f64 v[12:13], v[12:13], v[16:17], v[24:25]
v_div_fixup_f64 v[4:5], v[10:11], v[4:5], v[2:3]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_div_fixup_f64 v[8:9], v[12:13], v[8:9], v[6:7]
v_frexp_mant_f64_e32 v[12:13], v[4:5]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_frexp_mant_f64_e32 v[10:11], v[8:9]
v_cmp_gt_f64_e32 vcc_lo, s[0:1], v[10:11]
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_gt_f64_e64 s0, s[0:1], v[12:13]
v_cndmask_b32_e64 v14, 0, 1, vcc_lo
v_ldexp_f64 v[10:11], v[10:11], v14
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e64 v14, 0, 1, s0
v_ldexp_f64 v[12:13], v[12:13], v14
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_f64 v[14:15], v[10:11], 1.0
v_add_f64 v[26:27], v[10:11], -1.0
v_add_f64 v[16:17], v[12:13], 1.0
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_rcp_f64_e32 v[18:19], v[14:15]
v_add_f64 v[30:31], v[14:15], -1.0
v_rcp_f64_e32 v[20:21], v[16:17]
v_add_f64 v[34:35], v[16:17], -1.0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_add_f64 v[10:11], v[10:11], -v[30:31]
s_waitcnt_depctr 0xfff
v_fma_f64 v[22:23], -v[14:15], v[18:19], 1.0
v_fma_f64 v[24:25], -v[16:17], v[20:21], 1.0
v_fma_f64 v[18:19], v[22:23], v[18:19], v[18:19]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f64 v[20:21], v[24:25], v[20:21], v[20:21]
v_fma_f64 v[22:23], -v[14:15], v[18:19], 1.0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f64 v[24:25], -v[16:17], v[20:21], 1.0
v_fma_f64 v[18:19], v[22:23], v[18:19], v[18:19]
v_add_f64 v[22:23], v[12:13], -1.0
v_add_f64 v[12:13], v[12:13], -v[34:35]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_fma_f64 v[20:21], v[24:25], v[20:21], v[20:21]
v_mul_f64 v[24:25], v[26:27], v[18:19]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_f64 v[28:29], v[22:23], v[20:21]
v_mul_f64 v[32:33], v[14:15], v[24:25]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_f64 v[36:37], v[16:17], v[28:29]
v_fma_f64 v[14:15], v[24:25], v[14:15], -v[32:33]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f64 v[16:17], v[28:29], v[16:17], -v[36:37]
v_fma_f64 v[10:11], v[24:25], v[10:11], v[14:15]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f64 v[12:13], v[28:29], v[12:13], v[16:17]
v_add_f64 v[14:15], v[32:33], v[10:11]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[16:17], v[36:37], v[12:13]
v_add_f64 v[30:31], v[26:27], -v[14:15]
v_add_f64 v[32:33], v[14:15], -v[32:33]
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_add_f64 v[34:35], v[22:23], -v[16:17]
v_add_f64 v[36:37], v[16:17], -v[36:37]
v_add_f64 v[26:27], v[26:27], -v[30:31]
s_delay_alu instid0(VALU_DEP_4)
v_add_f64 v[10:11], v[32:33], -v[10:11]
v_frexp_exp_i32_f64_e32 v32, v[8:9]
v_frexp_exp_i32_f64_e32 v33, v[4:5]
v_add_f64 v[22:23], v[22:23], -v[34:35]
v_add_f64 v[12:13], v[36:37], -v[12:13]
v_add_f64 v[14:15], v[26:27], -v[14:15]
v_subrev_co_ci_u32_e32 v32, vcc_lo, 0, v32, vcc_lo
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f64 v[16:17], v[22:23], -v[16:17]
v_add_f64 v[10:11], v[10:11], v[14:15]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[12:13], v[12:13], v[16:17]
v_add_f64 v[10:11], v[30:31], v[10:11]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[12:13], v[34:35], v[12:13]
v_mul_f64 v[10:11], v[18:19], v[10:11]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_f64 v[12:13], v[20:21], v[12:13]
v_add_f64 v[14:15], v[24:25], v[10:11]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[16:17], v[28:29], v[12:13]
v_mul_f64 v[18:19], v[14:15], v[14:15]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_f64 v[20:21], v[16:17], v[16:17]
v_fma_f64 v[22:23], v[18:19], s[6:7], s[4:5]
v_mul_f64 v[30:31], v[14:15], v[18:19]
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_3)
v_fma_f64 v[26:27], v[20:21], s[6:7], s[4:5]
s_mov_b32 s5, 0x3fcc71c0
s_mov_b32 s4, 0x16291751
s_mov_b32 s7, 0x3fd24924
s_mov_b32 s6, 0x9b27acf1
v_fma_f64 v[22:23], v[18:19], v[22:23], s[8:9]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f64 v[26:27], v[20:21], v[26:27], s[8:9]
v_fma_f64 v[22:23], v[18:19], v[22:23], s[4:5]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_fma_f64 v[26:27], v[20:21], v[26:27], s[4:5]
s_mov_b32 s5, 0x3fd99999
s_mov_b32 s4, 0x998ef7b6
v_fma_f64 v[22:23], v[18:19], v[22:23], s[6:7]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_fma_f64 v[26:27], v[20:21], v[26:27], s[6:7]
s_mov_b32 s6, 0x55555780
s_mov_b32 s7, s1
s_mov_b32 s1, 0x3fe62e42
v_fma_f64 v[22:23], v[18:19], v[22:23], s[4:5]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_fma_f64 v[26:27], v[20:21], v[26:27], s[4:5]
s_mov_b32 s5, 0x3c7abc9e
s_mov_b32 s4, 0x3b39803f
v_fma_f64 v[18:19], v[18:19], v[22:23], s[6:7]
v_mul_f64 v[22:23], v[16:17], v[20:21]
s_delay_alu instid0(VALU_DEP_3)
v_fma_f64 v[20:21], v[20:21], v[26:27], s[6:7]
v_ldexp_f64 v[26:27], v[14:15], 1
v_add_f64 v[14:15], v[14:15], -v[24:25]
v_mul_f64 v[18:19], v[30:31], v[18:19]
v_ldexp_f64 v[30:31], v[16:17], 1
v_add_f64 v[16:17], v[16:17], -v[28:29]
v_mul_f64 v[20:21], v[22:23], v[20:21]
v_cvt_f64_i32_e32 v[22:23], v32
v_subrev_co_ci_u32_e64 v32, vcc_lo, 0, v33, s0
s_mov_b32 s0, 0xfefa39ef
v_add_f64 v[10:11], v[10:11], -v[14:15]
v_cmp_class_f64_e64 vcc_lo, v[8:9], 0x204
s_delay_alu instid0(VALU_DEP_3)
v_cvt_f64_i32_e32 v[32:33], v32
v_add_f64 v[24:25], v[26:27], v[18:19]
v_add_f64 v[12:13], v[12:13], -v[16:17]
v_add_f64 v[28:29], v[30:31], v[20:21]
v_mul_f64 v[34:35], v[22:23], s[0:1]
v_ldexp_f64 v[10:11], v[10:11], 1
v_add_f64 v[14:15], v[24:25], -v[26:27]
v_mul_f64 v[26:27], v[32:33], s[0:1]
v_ldexp_f64 v[12:13], v[12:13], 1
v_add_f64 v[16:17], v[28:29], -v[30:31]
v_fma_f64 v[30:31], v[22:23], s[0:1], -v[34:35]
v_add_f64 v[14:15], v[18:19], -v[14:15]
v_fma_f64 v[18:19], v[32:33], s[0:1], -v[26:27]
v_cmp_class_f64_e64 s0, v[4:5], 0x204
v_add_f64 v[16:17], v[20:21], -v[16:17]
v_fma_f64 v[20:21], v[22:23], s[4:5], v[30:31]
v_add_f64 v[10:11], v[10:11], v[14:15]
v_fma_f64 v[14:15], v[32:33], s[4:5], v[18:19]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_f64 v[12:13], v[12:13], v[16:17]
v_add_f64 v[16:17], v[34:35], v[20:21]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_f64 v[18:19], v[24:25], v[10:11]
v_add_f64 v[22:23], v[26:27], v[14:15]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_f64 v[30:31], v[28:29], v[12:13]
v_add_f64 v[34:35], v[16:17], -v[34:35]
s_delay_alu instid0(VALU_DEP_4)
v_add_f64 v[32:33], v[16:17], v[18:19]
v_add_f64 v[24:25], v[18:19], -v[24:25]
v_add_f64 v[26:27], v[22:23], -v[26:27]
v_add_f64 v[36:37], v[22:23], v[30:31]
v_add_f64 v[20:21], v[20:21], -v[34:35]
v_add_f64 v[28:29], v[30:31], -v[28:29]
v_add_f64 v[38:39], v[32:33], -v[16:17]
v_add_f64 v[10:11], v[10:11], -v[24:25]
v_add_f64 v[14:15], v[14:15], -v[26:27]
v_add_f64 v[40:41], v[36:37], -v[22:23]
v_add_f64 v[12:13], v[12:13], -v[28:29]
v_add_f64 v[42:43], v[32:33], -v[38:39]
v_add_f64 v[18:19], v[18:19], -v[38:39]
v_add_f64 v[26:27], v[20:21], v[10:11]
v_add_f64 v[34:35], v[36:37], -v[40:41]
v_add_f64 v[24:25], v[30:31], -v[40:41]
v_add_f64 v[16:17], v[16:17], -v[42:43]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[22:23], v[22:23], -v[34:35]
v_add_f64 v[16:17], v[18:19], v[16:17]
v_add_f64 v[18:19], v[14:15], v[12:13]
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_add_f64 v[22:23], v[24:25], v[22:23]
v_add_f64 v[24:25], v[26:27], -v[20:21]
v_add_f64 v[16:17], v[26:27], v[16:17]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_f64 v[28:29], v[18:19], -v[14:15]
v_add_f64 v[22:23], v[18:19], v[22:23]
s_delay_alu instid0(VALU_DEP_4)
v_add_f64 v[26:27], v[26:27], -v[24:25]
v_add_f64 v[10:11], v[10:11], -v[24:25]
v_add_f64 v[30:31], v[32:33], v[16:17]
v_add_f64 v[18:19], v[18:19], -v[28:29]
v_add_f64 v[12:13], v[12:13], -v[28:29]
v_add_f64 v[24:25], v[36:37], v[22:23]
v_add_f64 v[20:21], v[20:21], -v[26:27]
v_add_f64 v[26:27], v[30:31], -v[32:33]
v_add_f64 v[14:15], v[14:15], -v[18:19]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_f64 v[18:19], v[24:25], -v[36:37]
v_add_f64 v[10:11], v[10:11], v[20:21]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_f64 v[16:17], v[16:17], -v[26:27]
v_add_f64 v[12:13], v[12:13], v[14:15]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f64 v[14:15], v[22:23], -v[18:19]
v_add_f64 v[10:11], v[10:11], v[16:17]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[12:13], v[12:13], v[14:15]
v_add_f64 v[10:11], v[30:31], v[10:11]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[12:13], v[24:25], v[12:13]
v_dual_cndmask_b32 v10, v10, v8 :: v_dual_cndmask_b32 v11, v11, v9
v_cmp_ngt_f64_e32 vcc_lo, 0, v[8:9]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_cndmask_b32_e32 v11, 0x7ff80000, v11, vcc_lo
v_cmp_nge_f64_e32 vcc_lo, 0, v[8:9]
v_cndmask_b32_e32 v10, 0, v10, vcc_lo
v_cmp_neq_f64_e32 vcc_lo, 0, v[8:9]
v_cndmask_b32_e64 v9, v13, v5, s0
v_cndmask_b32_e64 v8, v12, v4, s0
v_cndmask_b32_e32 v11, 0xfff00000, v11, vcc_lo
v_cmp_ngt_f64_e32 vcc_lo, 0, v[4:5]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_4)
v_mul_f64 v[6:7], v[6:7], v[10:11]
v_cndmask_b32_e32 v9, 0x7ff80000, v9, vcc_lo
v_cmp_nge_f64_e32 vcc_lo, 0, v[4:5]
v_cndmask_b32_e32 v8, 0, v8, vcc_lo
v_cmp_neq_f64_e32 vcc_lo, 0, v[4:5]
v_cndmask_b32_e32 v9, 0xfff00000, v9, vcc_lo
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_3)
v_fma_f64 v[2:3], v[2:3], v[8:9], v[6:7]
global_store_b64 v[0:1], v[2:3], off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel binaryentropy
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 44
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size binaryentropy, .Lfunc_end0-binaryentropy
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: binaryentropy
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: binaryentropy.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 44
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
extern "C"
{
__global__ void binaryentropy(const int lengthX, const double *x, const double *y, double *z)
{
int i = threadIdx.x + blockIdx.x * blockDim.x;
if (i<lengthX)
{
z[i] = x[i]*log(x[i]/y[i])+ (1.0-x[i])*log((1.0-x[i])/(1.0-y[i]));
}
}
} | .text
.file "binaryentropy.hip"
.globl __device_stub__binaryentropy # -- Begin function __device_stub__binaryentropy
.p2align 4, 0x90
.type __device_stub__binaryentropy,@function
__device_stub__binaryentropy: # @__device_stub__binaryentropy
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 4(%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 64(%rsp)
movq %rcx, 56(%rsp)
leaq 4(%rsp), %rax
movq %rax, 80(%rsp)
leaq 72(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 56(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $binaryentropy, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size __device_stub__binaryentropy, .Lfunc_end0-__device_stub__binaryentropy
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $binaryentropy, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type binaryentropy,@object # @binaryentropy
.section .rodata,"a",@progbits
.globl binaryentropy
.p2align 3, 0x0
binaryentropy:
.quad __device_stub__binaryentropy
.size binaryentropy, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "binaryentropy"
.size .L__unnamed_1, 14
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub__binaryentropy
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym binaryentropy
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0012c99e_00000000-6_binaryentropy.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z40__device_stub__Z13binaryentropyiPKdS0_PdiPKdS0_Pd
.type _Z40__device_stub__Z13binaryentropyiPKdS0_PdiPKdS0_Pd, @function
_Z40__device_stub__Z13binaryentropyiPKdS0_PdiPKdS0_Pd:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq binaryentropy(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z40__device_stub__Z13binaryentropyiPKdS0_PdiPKdS0_Pd, .-_Z40__device_stub__Z13binaryentropyiPKdS0_PdiPKdS0_Pd
.globl binaryentropy
.type binaryentropy, @function
binaryentropy:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z40__device_stub__Z13binaryentropyiPKdS0_PdiPKdS0_Pd
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size binaryentropy, .-binaryentropy
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "binaryentropy"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq binaryentropy(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "binaryentropy.hip"
.globl __device_stub__binaryentropy # -- Begin function __device_stub__binaryentropy
.p2align 4, 0x90
.type __device_stub__binaryentropy,@function
__device_stub__binaryentropy: # @__device_stub__binaryentropy
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 4(%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 64(%rsp)
movq %rcx, 56(%rsp)
leaq 4(%rsp), %rax
movq %rax, 80(%rsp)
leaq 72(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 56(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $binaryentropy, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size __device_stub__binaryentropy, .Lfunc_end0-__device_stub__binaryentropy
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $binaryentropy, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type binaryentropy,@object # @binaryentropy
.section .rodata,"a",@progbits
.globl binaryentropy
.p2align 3, 0x0
binaryentropy:
.quad __device_stub__binaryentropy
.size binaryentropy, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "binaryentropy"
.size .L__unnamed_1, 14
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub__binaryentropy
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym binaryentropy
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <cstdio>
#include <climits>
#define SERIAL_SCALE 2
#define SERIAL_PART (1<<SERIAL_SCALE)
extern "C" {
__global__
void kernelMain(int *input, int *output){
int thid = (blockIdx.x * blockDim.x) + threadIdx.x;
__shared__ int mem[1024];
int m=input[thid*SERIAL_PART];
for(unsigned int i=1;i<SERIAL_PART;++i)
{
int t=input[thid*SERIAL_PART+i];
if(t<m)
m=t;
}
mem[threadIdx.x]=m;
__syncthreads();
for(unsigned int shift=1;shift<1024;shift*=2)
{
int val=mem[threadIdx.x];
if(threadIdx.x>=shift)
{
if(val>mem[threadIdx.x-shift])
val=mem[threadIdx.x-shift];
}
__syncthreads();
mem[threadIdx.x]=val;
}
if(threadIdx.x==1023)
output[blockIdx.x]=mem[1023];
}
__global__ void kernelPrepare(int *input, int *output, int* args)
{
const unsigned int count=args[0];
const unsigned int n=args[1];
int thid = (blockIdx.x * blockDim.x) + threadIdx.x;
if(thid*count>=n)
return;
int m=input[thid*count];
for(unsigned int i=1;i<count && thid*count+i<n;++i)
{
if(m>input[thid*count+i])
m=input[thid*count+i];
}
output[thid]=m;
}
} | code for sm_80
Function : kernelPrepare
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff047624 */
/* 0x000fe200078e00ff */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0030*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x174] ; /* 0x00005d00ff057624 */
/* 0x000fca00078e00ff */
/*0040*/ LDG.E R7, [R4.64] ; /* 0x0000000404077981 */
/* 0x000ea8000c1e1900 */
/*0050*/ LDG.E R9, [R4.64+0x4] ; /* 0x0000040404097981 */
/* 0x000ee8000c1e1900 */
/*0060*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0070*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0080*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fc800078e0203 */
/*0090*/ IMAD R2, R0, R7, RZ ; /* 0x0000000700027224 */
/* 0x004fca00078e02ff */
/*00a0*/ ISETP.GE.U32.AND P0, PT, R2, R9, PT ; /* 0x000000090200720c */
/* 0x008fda0003f06070 */
/*00b0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00c0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fc800078e00ff */
/*00d0*/ IMAD.WIDE.U32 R4, R2, R3, c[0x0][0x160] ; /* 0x0000580002047625 */
/* 0x000fcc00078e0003 */
/*00e0*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000162000c1e1900 */
/*00f0*/ IADD3 R6, R2, 0x1, RZ ; /* 0x0000000102067810 */
/* 0x000fe20007ffe0ff */
/*0100*/ BSSY B2, 0xbd0 ; /* 0x00000ac000027945 */
/* 0x000fe60003800000 */
/*0110*/ ISETP.GE.U32.AND P0, PT, R6, R9, PT ; /* 0x000000090600720c */
/* 0x000fc80003f06070 */
/*0120*/ ISETP.LT.U32.OR P0, PT, R7, 0x2, P0 ; /* 0x000000020700780c */
/* 0x000fda0000701470 */
/*0130*/ @P0 BRA 0xbc0 ; /* 0x00000a8000000947 */
/* 0x000fea0003800000 */
/*0140*/ IMAD.IADD R9, R6, 0x1, -R9 ; /* 0x0000000106097824 */
/* 0x001fe200078e0a09 */
/*0150*/ IADD3 R4, -R7, 0x1, RZ ; /* 0x0000000107047810 */
/* 0x000fe20007ffe1ff */
/*0160*/ BSSY B1, 0xb20 ; /* 0x000009b000017945 */
/* 0x000fe60003800000 */
/*0170*/ IMNMX.U32 R4, R9, R4, !PT ; /* 0x0000000409047217 */
/* 0x000fe20007800000 */
/*0180*/ IMAD.MOV.U32 R9, RZ, RZ, 0x1 ; /* 0x00000001ff097424 */
/* 0x000fc600078e00ff */
/*0190*/ ISETP.GT.U32.AND P0, PT, R4, -0x4, PT ; /* 0xfffffffc0400780c */
/* 0x000fe20003f04070 */
/*01a0*/ IMAD.MOV R7, RZ, RZ, -R4 ; /* 0x000000ffff077224 */
/* 0x000fca00078e0a04 */
/*01b0*/ LOP3.LUT R7, R7, 0x3, RZ, 0xc0, !PT ; /* 0x0000000307077812 */
/* 0x000fce00078ec0ff */
/*01c0*/ @P0 BRA 0xb10 ; /* 0x0000094000000947 */
/* 0x000fea0003800000 */
/*01d0*/ IMAD.IADD R10, R4, 0x1, R7 ; /* 0x00000001040a7824 */
/* 0x000fe200078e0207 */
/*01e0*/ BSSY B0, 0x9c0 ; /* 0x000007d000007945 */
/* 0x000fe20003800000 */
/*01f0*/ IMAD.MOV.U32 R9, RZ, RZ, 0x1 ; /* 0x00000001ff097424 */
/* 0x000fe400078e00ff */
/*0200*/ IMAD.MOV.U32 R4, RZ, RZ, R2 ; /* 0x000000ffff047224 */
/* 0x000fe200078e0002 */
/*0210*/ ISETP.GE.AND P0, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fda0003f06270 */
/*0220*/ @P0 BRA 0x9b0 ; /* 0x0000078000000947 */
/* 0x000fea0003800000 */
/*0230*/ IMAD.MOV R8, RZ, RZ, -R10 ; /* 0x000000ffff087224 */
/* 0x000fe200078e0a0a */
/*0240*/ BSSY B3, 0x6f0 ; /* 0x000004a000037945 */
/* 0x000fe20003800000 */
/*0250*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fc60003f0f070 */
/*0260*/ ISETP.GT.AND P1, PT, R8, 0xc, PT ; /* 0x0000000c0800780c */
/* 0x000fda0003f24270 */
/*0270*/ @!P1 BRA 0x6e0 ; /* 0x0000046000009947 */
/* 0x000fea0003800000 */
/*0280*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0290*/ IADD3 R16, R6.reuse, 0x1, RZ ; /* 0x0000000106107810 */
/* 0x040fe20007ffe0ff */
/*02a0*/ IMAD.WIDE.U32 R14, R6, R3, c[0x0][0x160] ; /* 0x00005800060e7625 */
/* 0x000fe200078e0003 */
/*02b0*/ IADD3 R12, R4, 0x3, RZ ; /* 0x00000003040c7810 */
/* 0x000fc60007ffe0ff */
/*02c0*/ IMAD.WIDE.U32 R16, R16, R3.reuse, c[0x0][0x160] ; /* 0x0000580010107625 */
/* 0x080fe200078e0003 */
/*02d0*/ LDG.E R8, [R14.64] ; /* 0x000000040e087981 */
/* 0x0000a2000c1e1900 */
/*02e0*/ IADD3 R22, R6, 0x3, RZ ; /* 0x0000000306167810 */
/* 0x000fe40007ffe0ff */
/*02f0*/ IMAD.WIDE.U32 R12, R12, R3.reuse, c[0x0][0x160] ; /* 0x000058000c0c7625 */
/* 0x080fe200078e0003 */
/*0300*/ LDG.E R11, [R16.64] ; /* 0x00000004100b7981 */
/* 0x0002e2000c1e1900 */
/*0310*/ IADD3 R18, R6, 0x4, RZ ; /* 0x0000000406127810 */
/* 0x000fe40007ffe0ff */
/*0320*/ IMAD.WIDE.U32 R22, R22, R3.reuse, c[0x0][0x160] ; /* 0x0000580016167625 */
/* 0x080fe400078e0003 */
/*0330*/ LDG.E R12, [R12.64] ; /* 0x000000040c0c7981 */
/* 0x0008e2000c1e1900 */
/*0340*/ IADD3 R28, R6, 0x5, RZ ; /* 0x00000005061c7810 */
/* 0x000fe20007ffe0ff */
/*0350*/ IMAD.WIDE.U32 R18, R18, R3.reuse, c[0x0][0x160] ; /* 0x0000580012127625 */
/* 0x080fe200078e0003 */
/*0360*/ IADD3 R20, R4, 0x7, RZ ; /* 0x0000000704147810 */
/* 0x000fe20007ffe0ff */
/*0370*/ LDG.E R27, [R22.64] ; /* 0x00000004161b7981 */
/* 0x0008e4000c1e1900 */
/*0380*/ IMAD.WIDE.U32 R28, R28, R3, c[0x0][0x160] ; /* 0x000058001c1c7625 */
/* 0x000fc400078e0003 */
/*0390*/ LDG.E R26, [R18.64] ; /* 0x00000004121a7981 */
/* 0x0008e2000c1e1900 */
/*03a0*/ IADD3 R16, R6, 0x7, RZ ; /* 0x0000000706107810 */
/* 0x002fe20007ffe0ff */
/*03b0*/ IMAD.WIDE.U32 R14, R20, R3.reuse, c[0x0][0x160] ; /* 0x00005800140e7625 */
/* 0x081fe400078e0003 */
/*03c0*/ LDG.E R25, [R28.64] ; /* 0x000000041c197981 */
/* 0x0000e2000c1e1900 */
/*03d0*/ IADD3 R20, R6, 0x8, RZ ; /* 0x0000000806147810 */
/* 0x000fe20007ffe0ff */
/*03e0*/ IMAD.WIDE.U32 R16, R16, R3.reuse, c[0x0][0x160] ; /* 0x0000580010107625 */
/* 0x080fe400078e0003 */
/*03f0*/ LDG.E R24, [R14.64] ; /* 0x000000040e187981 */
/* 0x0002e2000c1e1900 */
/*0400*/ IADD3 R13, R6, 0x9, RZ ; /* 0x00000009060d7810 */
/* 0x010fe20007ffe0ff */
/*0410*/ IMAD.WIDE.U32 R20, R20, R3, c[0x0][0x160] ; /* 0x0000580014147625 */
/* 0x000fc400078e0003 */
/*0420*/ LDG.E R23, [R16.64] ; /* 0x0000000410177981 */
/* 0x0008e2000c1e1900 */
/*0430*/ IADD3 R28, R4, 0xb, RZ ; /* 0x0000000b041c7810 */
/* 0x001fe20007ffe0ff */
/*0440*/ IMAD.WIDE.U32 R18, R13, R3.reuse, c[0x0][0x160] ; /* 0x000058000d127625 */
/* 0x080fe400078e0003 */
/*0450*/ LDG.E R22, [R20.64] ; /* 0x0000000414167981 */
/* 0x0000e2000c1e1900 */
/*0460*/ IADD3 R14, R6, 0xb, RZ ; /* 0x0000000b060e7810 */
/* 0x002fe20007ffe0ff */
/*0470*/ IMAD.WIDE.U32 R28, R28, R3.reuse, c[0x0][0x160] ; /* 0x000058001c1c7625 */
/* 0x080fe400078e0003 */
/*0480*/ LDG.E R13, [R18.64] ; /* 0x00000004120d7981 */
/* 0x0002e2000c1e1900 */
/*0490*/ IADD3 R16, R6, 0xc, RZ ; /* 0x0000000c06107810 */
/* 0x010fe20007ffe0ff */
/*04a0*/ IMAD.WIDE.U32 R14, R14, R3, c[0x0][0x160] ; /* 0x000058000e0e7625 */
/* 0x000fc400078e0003 */
/*04b0*/ LDG.E R28, [R28.64] ; /* 0x000000041c1c7981 */
/* 0x0008e2000c1e1900 */
/*04c0*/ IADD3 R18, R6, 0xd, RZ ; /* 0x0000000d06127810 */
/* 0x002fc60007ffe0ff */
/*04d0*/ LDG.E R29, [R14.64] ; /* 0x000000040e1d7981 */
/* 0x010322000c1e1900 */
/*04e0*/ IADD3 R20, R6, 0xf, RZ ; /* 0x0000000f06147810 */
/* 0x001fe20007ffe0ff */
/*04f0*/ IMAD.WIDE.U32 R14, R16, R3, c[0x0][0x160] ; /* 0x00005800100e7625 */
/* 0x002fc800078e0003 */
/*0500*/ IMAD.WIDE.U32 R16, R18, R3.reuse, c[0x0][0x160] ; /* 0x0000580012107625 */
/* 0x080fe200078e0003 */
/*0510*/ IADD3 R18, R4, 0xf, RZ ; /* 0x0000000f04127810 */
/* 0x000fe20007ffe0ff */
/*0520*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000f28000c1e1900 */
/*0530*/ IMAD.WIDE.U32 R18, R18, R3.reuse, c[0x0][0x160] ; /* 0x0000580012127625 */
/* 0x080fe200078e0003 */
/*0540*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x000f26000c1e1900 */
/*0550*/ IMAD.WIDE.U32 R20, R20, R3, c[0x0][0x160] ; /* 0x0000580014147625 */
/* 0x000fc400078e0003 */
/*0560*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x000f28000c1e1900 */
/*0570*/ LDG.E R20, [R20.64] ; /* 0x0000000414147981 */
/* 0x000f22000c1e1900 */
/*0580*/ IADD3 R10, R10, 0x10, RZ ; /* 0x000000100a0a7810 */
/* 0x000fc80007ffe0ff */
/*0590*/ ISETP.GE.AND P1, PT, R10, -0xc, PT ; /* 0xfffffff40a00780c */
/* 0x000fe40003f26270 */
/*05a0*/ IADD3 R9, R9, 0x10, RZ ; /* 0x0000001009097810 */
/* 0x000fe40007ffe0ff */
/*05b0*/ IADD3 R4, R4, 0x10, RZ ; /* 0x0000001004047810 */
/* 0x000fe40007ffe0ff */
/*05c0*/ IADD3 R6, R6, 0x10, RZ ; /* 0x0000001006067810 */
/* 0x000fe40007ffe0ff */
/*05d0*/ IMNMX R8, R8, R5, PT ; /* 0x0000000508087217 */
/* 0x024fc80003800200 */
/*05e0*/ IMNMX R11, R8, R11, PT ; /* 0x0000000b080b7217 */
/* 0x008fc80003800200 */
/*05f0*/ IMNMX R12, R11, R12, PT ; /* 0x0000000c0b0c7217 */
/* 0x000fc80003800200 */
/*0600*/ IMNMX R27, R12, R27, PT ; /* 0x0000001b0c1b7217 */
/* 0x000fc80003800200 */
/*0610*/ IMNMX R26, R27, R26, PT ; /* 0x0000001a1b1a7217 */
/* 0x000fc80003800200 */
/*0620*/ IMNMX R25, R26, R25, PT ; /* 0x000000191a197217 */
/* 0x000fc80003800200 */
/*0630*/ IMNMX R24, R25, R24, PT ; /* 0x0000001819187217 */
/* 0x000fc80003800200 */
/*0640*/ IMNMX R23, R24, R23, PT ; /* 0x0000001718177217 */
/* 0x000fc80003800200 */
/*0650*/ IMNMX R22, R23, R22, PT ; /* 0x0000001617167217 */
/* 0x000fc80003800200 */
/*0660*/ IMNMX R13, R22, R13, PT ; /* 0x0000000d160d7217 */
/* 0x000fc80003800200 */
/*0670*/ IMNMX R28, R13, R28, PT ; /* 0x0000001c0d1c7217 */
/* 0x000fc80003800200 */
/*0680*/ IMNMX R29, R28, R29, PT ; /* 0x0000001d1c1d7217 */
/* 0x010fc80003800200 */
/*0690*/ IMNMX R29, R29, R14, PT ; /* 0x0000000e1d1d7217 */
/* 0x000fc80003800200 */
/*06a0*/ IMNMX R29, R29, R16, PT ; /* 0x000000101d1d7217 */
/* 0x000fc80003800200 */
/*06b0*/ IMNMX R29, R29, R18, PT ; /* 0x000000121d1d7217 */
/* 0x000fc80003800200 */
/*06c0*/ IMNMX R5, R29, R20, PT ; /* 0x000000141d057217 */
/* 0x000fe20003800200 */
/*06d0*/ @!P1 BRA 0x290 ; /* 0xfffffbb000009947 */
/* 0x000fea000383ffff */
/*06e0*/ BSYNC B3 ; /* 0x0000000000037941 */
/* 0x000fea0003800000 */
/*06f0*/ IMAD.MOV R8, RZ, RZ, -R10 ; /* 0x000000ffff087224 */
/* 0x000fe200078e0a0a */
/*0700*/ BSSY B3, 0x980 ; /* 0x0000027000037945 */
/* 0x000fe80003800000 */
/*0710*/ ISETP.GT.AND P1, PT, R8, 0x4, PT ; /* 0x000000040800780c */
/* 0x000fda0003f24270 */
/*0720*/ @!P1 BRA 0x970 ; /* 0x0000024000009947 */
/* 0x000fea0003800000 */
/*0730*/ IADD3 R18, R6.reuse, 0x1, RZ ; /* 0x0000000106127810 */
/* 0x040fe20007ffe0ff */
/*0740*/ IMAD.WIDE.U32 R16, R6, R3, c[0x0][0x160] ; /* 0x0000580006107625 */
/* 0x000fe200078e0003 */
/*0750*/ IADD3 R22, R4, 0x3, RZ ; /* 0x0000000304167810 */
/* 0x000fc60007ffe0ff */
/*0760*/ IMAD.WIDE.U32 R18, R18, R3.reuse, c[0x0][0x160] ; /* 0x0000580012127625 */
/* 0x080fe200078e0003 */
/*0770*/ LDG.E R8, [R16.64] ; /* 0x0000000410087981 */
/* 0x0000a2000c1e1900 */
/*0780*/ IADD3 R12, R6, 0x3, RZ ; /* 0x00000003060c7810 */
/* 0x000fe40007ffe0ff */
/*0790*/ IMAD.WIDE.U32 R22, R22, R3.reuse, c[0x0][0x160] ; /* 0x0000580016167625 */
/* 0x080fe200078e0003 */
/*07a0*/ LDG.E R11, [R18.64] ; /* 0x00000004120b7981 */
/* 0x0002e2000c1e1900 */
/*07b0*/ IADD3 R14, R6, 0x4, RZ ; /* 0x00000004060e7810 */
/* 0x000fe40007ffe0ff */
/*07c0*/ IMAD.WIDE.U32 R12, R12, R3.reuse, c[0x0][0x160] ; /* 0x000058000c0c7625 */
/* 0x080fe200078e0003 */
/*07d0*/ IADD3 R20, R6, 0x5, RZ ; /* 0x0000000506147810 */
/* 0x000fe20007ffe0ff */
/*07e0*/ LDG.E R22, [R22.64] ; /* 0x0000000416167981 */
/* 0x000f24000c1e1900 */
/*07f0*/ IMAD.WIDE.U32 R14, R14, R3.reuse, c[0x0][0x160] ; /* 0x000058000e0e7625 */
/* 0x080fe200078e0003 */
/*0800*/ IADD3 R24, R4, 0x7, RZ ; /* 0x0000000704187810 */
/* 0x000fe20007ffe0ff */
/*0810*/ LDG.E R12, [R12.64] ; /* 0x000000040c0c7981 */
/* 0x000f24000c1e1900 */
/*0820*/ IMAD.WIDE.U32 R16, R20, R3.reuse, c[0x0][0x160] ; /* 0x0000580014107625 */
/* 0x081fe200078e0003 */
/*0830*/ IADD3 R20, R6, 0x7, RZ ; /* 0x0000000706147810 */
/* 0x000fe20007ffe0ff */
/*0840*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000f24000c1e1900 */
/*0850*/ IMAD.WIDE.U32 R18, R24, R3, c[0x0][0x160] ; /* 0x0000580018127625 */
/* 0x002fc400078e0003 */
/*0860*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x000f24000c1e1900 */
/*0870*/ IMAD.WIDE.U32 R20, R20, R3, c[0x0][0x160] ; /* 0x0000580014147625 */
/* 0x000fe400078e0003 */
/*0880*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x000f28000c1e1900 */
/*0890*/ LDG.E R20, [R20.64] ; /* 0x0000000414147981 */
/* 0x000f22000c1e1900 */
/*08a0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*08b0*/ IADD3 R9, R9, 0x8, RZ ; /* 0x0000000809097810 */
/* 0x000fc40007ffe0ff */
/*08c0*/ IADD3 R10, R10, 0x8, RZ ; /* 0x000000080a0a7810 */
/* 0x000fe40007ffe0ff */
/*08d0*/ IADD3 R4, R4, 0x8, RZ ; /* 0x0000000804047810 */
/* 0x000fe40007ffe0ff */
/*08e0*/ IADD3 R6, R6, 0x8, RZ ; /* 0x0000000806067810 */
/* 0x000fe40007ffe0ff */
/*08f0*/ IMNMX R8, R5, R8, PT ; /* 0x0000000805087217 */
/* 0x024fc80003800200 */
/*0900*/ IMNMX R11, R8, R11, PT ; /* 0x0000000b080b7217 */
/* 0x008fc80003800200 */
/*0910*/ IMNMX R11, R11, R22, PT ; /* 0x000000160b0b7217 */
/* 0x010fc80003800200 */
/*0920*/ IMNMX R11, R11, R12, PT ; /* 0x0000000c0b0b7217 */
/* 0x000fc80003800200 */
/*0930*/ IMNMX R11, R11, R14, PT ; /* 0x0000000e0b0b7217 */
/* 0x000fc80003800200 */
/*0940*/ IMNMX R11, R11, R16, PT ; /* 0x000000100b0b7217 */
/* 0x000fc80003800200 */
/*0950*/ IMNMX R11, R11, R18, PT ; /* 0x000000120b0b7217 */
/* 0x000fc80003800200 */
/*0960*/ IMNMX R5, R11, R20, PT ; /* 0x000000140b057217 */
/* 0x000fe40003800200 */
/*0970*/ BSYNC B3 ; /* 0x0000000000037941 */
/* 0x000fea0003800000 */
/*0980*/ ISETP.NE.OR P0, PT, R10, RZ, P0 ; /* 0x000000ff0a00720c */
/* 0x000fda0000705670 */
/*0990*/ @!P0 BREAK B0 ; /* 0x0000000000008942 */
/* 0x000fe20003800000 */
/*09a0*/ @!P0 BRA 0xb10 ; /* 0x0000016000008947 */
/* 0x000fea0003800000 */
/*09b0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*09c0*/ IADD3 R12, R6.reuse, 0x1, RZ ; /* 0x00000001060c7810 */
/* 0x040fe20007ffe0ff */
/*09d0*/ IMAD.WIDE.U32 R16, R6, R3, c[0x0][0x160] ; /* 0x0000580006107625 */
/* 0x000fe200078e0003 */
/*09e0*/ IADD3 R14, R4, 0x3, RZ ; /* 0x00000003040e7810 */
/* 0x000fc60007ffe0ff */
/*09f0*/ IMAD.WIDE.U32 R12, R12, R3.reuse, c[0x0][0x160] ; /* 0x000058000c0c7625 */
/* 0x080fe200078e0003 */
/*0a00*/ IADD3 R18, R6, 0x3, RZ ; /* 0x0000000306127810 */
/* 0x000fe20007ffe0ff */
/*0a10*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x000ea4000c1e1900 */
/*0a20*/ IMAD.WIDE.U32 R14, R14, R3.reuse, c[0x0][0x160] ; /* 0x000058000e0e7625 */
/* 0x080fe400078e0003 */
/*0a30*/ LDG.E R12, [R12.64] ; /* 0x000000040c0c7981 */
/* 0x000ee4000c1e1900 */
/*0a40*/ IMAD.WIDE.U32 R18, R18, R3, c[0x0][0x160] ; /* 0x0000580012127625 */
/* 0x000fe400078e0003 */
/*0a50*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000f28000c1e1900 */
/*0a60*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x000f22000c1e1900 */
/*0a70*/ IADD3 R10, R10, 0x4, RZ ; /* 0x000000040a0a7810 */
/* 0x000fc40007ffe0ff */
/*0a80*/ IADD3 R9, R9, 0x4, RZ ; /* 0x0000000409097810 */
/* 0x000fe40007ffe0ff */
/*0a90*/ ISETP.NE.AND P0, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fe40003f05270 */
/*0aa0*/ IADD3 R4, R4, 0x4, RZ ; /* 0x0000000404047810 */
/* 0x000fe40007ffe0ff */
/*0ab0*/ IADD3 R6, R6, 0x4, RZ ; /* 0x0000000406067810 */
/* 0x000fe40007ffe0ff */
/*0ac0*/ IMNMX R5, R16, R5, PT ; /* 0x0000000510057217 */
/* 0x024fc80003800200 */
/*0ad0*/ IMNMX R5, R5, R12, PT ; /* 0x0000000c05057217 */
/* 0x008fc80003800200 */
/*0ae0*/ IMNMX R5, R5, R14, PT ; /* 0x0000000e05057217 */
/* 0x010fc80003800200 */
/*0af0*/ IMNMX R5, R5, R18, PT ; /* 0x0000001205057217 */
/* 0x000fe20003800200 */
/*0b00*/ @P0 BRA 0x9c0 ; /* 0xfffffeb000000947 */
/* 0x000fea000383ffff */
/*0b10*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0b20*/ ISETP.NE.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fda0003f05270 */
/*0b30*/ @!P0 BRA 0xbc0 ; /* 0x0000008000008947 */
/* 0x000fea0003800000 */
/*0b40*/ IMAD.WIDE.U32 R10, R6, R3, c[0x0][0x160] ; /* 0x00005800060a7625 */
/* 0x000fcc00078e0003 */
/*0b50*/ LDG.E R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x000ea2000c1e1900 */
/*0b60*/ IADD3 R7, R7, -0x1, RZ ; /* 0xffffffff07077810 */
/* 0x000fe40007ffe0ff */
/*0b70*/ IADD3 R9, R9, 0x1, RZ ; /* 0x0000000109097810 */
/* 0x000fe40007ffe0ff */
/*0b80*/ ISETP.NE.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fc60003f05270 */
/*0b90*/ IMAD.IADD R6, R2, 0x1, R9 ; /* 0x0000000102067824 */
/* 0x000fe200078e0209 */
/*0ba0*/ IMNMX R5, R10, R5, PT ; /* 0x000000050a057217 */
/* 0x024fd20003800200 */
/*0bb0*/ @P0 BRA 0xb40 ; /* 0xffffff8000000947 */
/* 0x000fea000383ffff */
/*0bc0*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x001fea0003800000 */
/*0bd0*/ WARPSYNC 0xffffffff ; /* 0xffffffff00007948 */
/* 0x000fe20003800000 */
/*0be0*/ IMAD.WIDE R2, R0, R3, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x000fca00078e0203 */
/*0bf0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x020fe2000c101904 */
/*0c00*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0c10*/ BRA 0xc10; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0c20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ca0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ce0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : kernelMain
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e220000002500 */
/*0020*/ IMAD.MOV.U32 R13, RZ, RZ, 0x4 ; /* 0x00000004ff0d7424 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R11, SR_TID.X ; /* 0x00000000000b7919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R0, R6, c[0x0][0x0], R11 ; /* 0x0000000006007a24 */
/* 0x001fc800078e020b */
/*0060*/ IMAD.SHL.U32 R0, R0, 0x4, RZ ; /* 0x0000000400007824 */
/* 0x000fc800078e00ff */
/*0070*/ IMAD.WIDE R2, R0, R13, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fc800078e020d */
/*0080*/ IMAD.WIDE.U32 R4, R0, R13, c[0x0][0x160] ; /* 0x0000580000047625 */
/* 0x000fe400078e000d */
/*0090*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea8000c1e1900 */
/*00a0*/ LDG.E R0, [R4.64+0x4] ; /* 0x0000040404007981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R7, [R4.64+0x8] ; /* 0x0000080404077981 */
/* 0x000ee8000c1e1900 */
/*00c0*/ LDG.E R9, [R4.64+0xc] ; /* 0x00000c0404097981 */
/* 0x000f22000c1e1900 */
/*00d0*/ ISETP.NE.AND P2, PT, R11, RZ, PT ; /* 0x000000ff0b00720c */
/* 0x000fc40003f45270 */
/*00e0*/ ISETP.GE.U32.AND P0, PT, R11.reuse, 0x2, PT ; /* 0x000000020b00780c */
/* 0x040fe40003f06070 */
/*00f0*/ ISETP.GE.U32.AND P1, PT, R11, 0x4, PT ; /* 0x000000040b00780c */
/* 0x000fe40003f26070 */
/*0100*/ IMNMX R0, R0, R3, PT ; /* 0x0000000300007217 */
/* 0x004fc80003800200 */
/*0110*/ IMNMX R0, R0, R7, PT ; /* 0x0000000700007217 */
/* 0x008fc80003800200 */
/*0120*/ IMNMX R0, R0, R9, PT ; /* 0x0000000900007217 */
/* 0x010fca0003800200 */
/*0130*/ STS [R11.X4], R0 ; /* 0x000000000b007388 */
/* 0x000fe80000004800 */
/*0140*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0150*/ LDS R2, [R11.X4] ; /* 0x000000000b027984 */
/* 0x000fe80000004800 */
/*0160*/ @P2 LDS R3, [R11.X4+-0x4] ; /* 0xfffffc000b032984 */
/* 0x000e280000004800 */
/*0170*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0180*/ @P0 LDS R5, [R11.X4+-0x8] ; /* 0xfffff8000b050984 */
/* 0x000e620000004800 */
/*0190*/ @P2 IMNMX R2, R2, R3, PT ; /* 0x0000000302022217 */
/* 0x001fc40003800200 */
/*01a0*/ ISETP.GE.U32.AND P2, PT, R11, 0x8, PT ; /* 0x000000080b00780c */
/* 0x000fc60003f46070 */
/*01b0*/ STS [R11.X4], R2 ; /* 0x000000020b007388 */
/* 0x0003e80000004800 */
/*01c0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*01d0*/ @P0 IMNMX R2, R2, R5, PT ; /* 0x0000000502020217 */
/* 0x002fe40003800200 */
/*01e0*/ ISETP.GE.U32.AND P0, PT, R11, 0x10, PT ; /* 0x000000100b00780c */
/* 0x000fc60003f06070 */
/*01f0*/ @P1 LDS R3, [R11.X4+-0x10] ; /* 0xfffff0000b031984 */
/* 0x000e280000004800 */
/*0200*/ STS [R11.X4], R2 ; /* 0x000000020b007388 */
/* 0x0001e80000004800 */
/*0210*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0220*/ @P2 LDS R5, [R11.X4+-0x20] ; /* 0xffffe0000b052984 */
/* 0x000e620000004800 */
/*0230*/ @P1 IMNMX R2, R2, R3, PT ; /* 0x0000000302021217 */
/* 0x001fc40003800200 */
/*0240*/ ISETP.GE.U32.AND P1, PT, R11, 0x20, PT ; /* 0x000000200b00780c */
/* 0x000fc60003f26070 */
/*0250*/ STS [R11.X4], R2 ; /* 0x000000020b007388 */
/* 0x0003e80000004800 */
/*0260*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0270*/ @P2 IMNMX R2, R2, R5, PT ; /* 0x0000000502022217 */
/* 0x002fca0003800200 */
/*0280*/ @P0 LDS R3, [R11.X4+-0x40] ; /* 0xffffc0000b030984 */
/* 0x000e220000004800 */
/*0290*/ ISETP.GE.U32.AND P2, PT, R11, 0x40, PT ; /* 0x000000400b00780c */
/* 0x000fc60003f46070 */
/*02a0*/ STS [R11.X4], R2 ; /* 0x000000020b007388 */
/* 0x0001e80000004800 */
/*02b0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*02c0*/ @P1 LDS R5, [R11.X4+-0x80] ; /* 0xffff80000b051984 */
/* 0x000e620000004800 */
/*02d0*/ @P0 IMNMX R2, R2, R3, PT ; /* 0x0000000302020217 */
/* 0x001fc40003800200 */
/*02e0*/ ISETP.GE.U32.AND P0, PT, R11, 0x80, PT ; /* 0x000000800b00780c */
/* 0x000fc60003f06070 */
/*02f0*/ STS [R11.X4], R2 ; /* 0x000000020b007388 */
/* 0x0003e80000004800 */
/*0300*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0310*/ @P1 IMNMX R2, R2, R5, PT ; /* 0x0000000502021217 */
/* 0x002fca0003800200 */
/*0320*/ @P2 LDS R3, [R11.X4+-0x100] ; /* 0xffff00000b032984 */
/* 0x000e220000004800 */
/*0330*/ ISETP.GE.U32.AND P1, PT, R11, 0x100, PT ; /* 0x000001000b00780c */
/* 0x000fc60003f26070 */
/*0340*/ STS [R11.X4], R2 ; /* 0x000000020b007388 */
/* 0x0001e80000004800 */
/*0350*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0360*/ @P0 LDS R5, [R11.X4+-0x200] ; /* 0xfffe00000b050984 */
/* 0x000e620000004800 */
/*0370*/ @P2 IMNMX R2, R2, R3, PT ; /* 0x0000000302022217 */
/* 0x001fc40003800200 */
/*0380*/ ISETP.GE.U32.AND P2, PT, R11, 0x200, PT ; /* 0x000002000b00780c */
/* 0x000fc60003f46070 */
/*0390*/ STS [R11.X4], R2 ; /* 0x000000020b007388 */
/* 0x0003e80000004800 */
/*03a0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*03b0*/ @P0 IMNMX R2, R2, R5, PT ; /* 0x0000000502020217 */
/* 0x002fca0003800200 */
/*03c0*/ @P1 LDS R3, [R11.X4+-0x400] ; /* 0xfffc00000b031984 */
/* 0x000e220000004800 */
/*03d0*/ ISETP.NE.AND P0, PT, R11, 0x3ff, PT ; /* 0x000003ff0b00780c */
/* 0x000fc60003f05270 */
/*03e0*/ STS [R11.X4], R2 ; /* 0x000000020b007388 */
/* 0x0001e80000004800 */
/*03f0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0400*/ @P2 LDS R5, [R11.X4+-0x800] ; /* 0xfff800000b052984 */
/* 0x000e620000004800 */
/*0410*/ @P1 IMNMX R2, R2, R3, PT ; /* 0x0000000302021217 */
/* 0x001fca0003800200 */
/*0420*/ STS [R11.X4], R2 ; /* 0x000000020b007388 */
/* 0x0003e40000004800 */
/*0430*/ @P2 IMNMX R2, R2, R5, PT ; /* 0x0000000502022217 */
/* 0x002fe40003800200 */
/*0440*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0450*/ STS [R11.X4], R2 ; /* 0x000000020b007388 */
/* 0x0001e20000004800 */
/*0460*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0470*/ LDS R5, [0xffc] ; /* 0x000ffc00ff057984 */
/* 0x000e620000000800 */
/*0480*/ IMAD.WIDE.U32 R2, R6, R13, c[0x0][0x168] ; /* 0x00005a0006027625 */
/* 0x001fca00078e000d */
/*0490*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x002fe2000c101904 */
/*04a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*04b0*/ BRA 0x4b0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*04c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0500*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0510*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0520*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0530*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0540*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0550*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0560*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0570*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <cstdio>
#include <climits>
#define SERIAL_SCALE 2
#define SERIAL_PART (1<<SERIAL_SCALE)
extern "C" {
__global__
void kernelMain(int *input, int *output){
int thid = (blockIdx.x * blockDim.x) + threadIdx.x;
__shared__ int mem[1024];
int m=input[thid*SERIAL_PART];
for(unsigned int i=1;i<SERIAL_PART;++i)
{
int t=input[thid*SERIAL_PART+i];
if(t<m)
m=t;
}
mem[threadIdx.x]=m;
__syncthreads();
for(unsigned int shift=1;shift<1024;shift*=2)
{
int val=mem[threadIdx.x];
if(threadIdx.x>=shift)
{
if(val>mem[threadIdx.x-shift])
val=mem[threadIdx.x-shift];
}
__syncthreads();
mem[threadIdx.x]=val;
}
if(threadIdx.x==1023)
output[blockIdx.x]=mem[1023];
}
__global__ void kernelPrepare(int *input, int *output, int* args)
{
const unsigned int count=args[0];
const unsigned int n=args[1];
int thid = (blockIdx.x * blockDim.x) + threadIdx.x;
if(thid*count>=n)
return;
int m=input[thid*count];
for(unsigned int i=1;i<count && thid*count+i<n;++i)
{
if(m>input[thid*count+i])
m=input[thid*count+i];
}
output[thid]=m;
}
} | .file "tmpxft_0008d6bc_00000000-6_cuMin.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2059:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z32__device_stub__Z10kernelMainPiS_PiS_
.type _Z32__device_stub__Z10kernelMainPiS_PiS_, @function
_Z32__device_stub__Z10kernelMainPiS_PiS_:
.LFB2081:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq kernelMain(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2081:
.size _Z32__device_stub__Z10kernelMainPiS_PiS_, .-_Z32__device_stub__Z10kernelMainPiS_PiS_
.globl kernelMain
.type kernelMain, @function
kernelMain:
.LFB2082:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z10kernelMainPiS_PiS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2082:
.size kernelMain, .-kernelMain
.globl _Z37__device_stub__Z13kernelPreparePiS_S_PiS_S_
.type _Z37__device_stub__Z13kernelPreparePiS_S_PiS_S_, @function
_Z37__device_stub__Z13kernelPreparePiS_S_PiS_S_:
.LFB2083:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq kernelPrepare(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z37__device_stub__Z13kernelPreparePiS_S_PiS_S_, .-_Z37__device_stub__Z13kernelPreparePiS_S_PiS_S_
.globl kernelPrepare
.type kernelPrepare, @function
kernelPrepare:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z37__device_stub__Z13kernelPreparePiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size kernelPrepare, .-kernelPrepare
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "kernelPrepare"
.LC1:
.string "kernelMain"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq kernelPrepare(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq kernelMain(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <cstdio>
#include <climits>
#define SERIAL_SCALE 2
#define SERIAL_PART (1<<SERIAL_SCALE)
extern "C" {
__global__
void kernelMain(int *input, int *output){
int thid = (blockIdx.x * blockDim.x) + threadIdx.x;
__shared__ int mem[1024];
int m=input[thid*SERIAL_PART];
for(unsigned int i=1;i<SERIAL_PART;++i)
{
int t=input[thid*SERIAL_PART+i];
if(t<m)
m=t;
}
mem[threadIdx.x]=m;
__syncthreads();
for(unsigned int shift=1;shift<1024;shift*=2)
{
int val=mem[threadIdx.x];
if(threadIdx.x>=shift)
{
if(val>mem[threadIdx.x-shift])
val=mem[threadIdx.x-shift];
}
__syncthreads();
mem[threadIdx.x]=val;
}
if(threadIdx.x==1023)
output[blockIdx.x]=mem[1023];
}
__global__ void kernelPrepare(int *input, int *output, int* args)
{
const unsigned int count=args[0];
const unsigned int n=args[1];
int thid = (blockIdx.x * blockDim.x) + threadIdx.x;
if(thid*count>=n)
return;
int m=input[thid*count];
for(unsigned int i=1;i<count && thid*count+i<n;++i)
{
if(m>input[thid*count+i])
m=input[thid*count+i];
}
output[thid]=m;
}
} | #include <hip/hip_runtime.h>
#include <cstdio>
#include <climits>
#define SERIAL_SCALE 2
#define SERIAL_PART (1<<SERIAL_SCALE)
extern "C" {
__global__
void kernelMain(int *input, int *output){
int thid = (blockIdx.x * blockDim.x) + threadIdx.x;
__shared__ int mem[1024];
int m=input[thid*SERIAL_PART];
for(unsigned int i=1;i<SERIAL_PART;++i)
{
int t=input[thid*SERIAL_PART+i];
if(t<m)
m=t;
}
mem[threadIdx.x]=m;
__syncthreads();
for(unsigned int shift=1;shift<1024;shift*=2)
{
int val=mem[threadIdx.x];
if(threadIdx.x>=shift)
{
if(val>mem[threadIdx.x-shift])
val=mem[threadIdx.x-shift];
}
__syncthreads();
mem[threadIdx.x]=val;
}
if(threadIdx.x==1023)
output[blockIdx.x]=mem[1023];
}
__global__ void kernelPrepare(int *input, int *output, int* args)
{
const unsigned int count=args[0];
const unsigned int n=args[1];
int thid = (blockIdx.x * blockDim.x) + threadIdx.x;
if(thid*count>=n)
return;
int m=input[thid*count];
for(unsigned int i=1;i<count && thid*count+i<n;++i)
{
if(m>input[thid*count+i])
m=input[thid*count+i];
}
output[thid]=m;
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <cstdio>
#include <climits>
#define SERIAL_SCALE 2
#define SERIAL_PART (1<<SERIAL_SCALE)
extern "C" {
__global__
void kernelMain(int *input, int *output){
int thid = (blockIdx.x * blockDim.x) + threadIdx.x;
__shared__ int mem[1024];
int m=input[thid*SERIAL_PART];
for(unsigned int i=1;i<SERIAL_PART;++i)
{
int t=input[thid*SERIAL_PART+i];
if(t<m)
m=t;
}
mem[threadIdx.x]=m;
__syncthreads();
for(unsigned int shift=1;shift<1024;shift*=2)
{
int val=mem[threadIdx.x];
if(threadIdx.x>=shift)
{
if(val>mem[threadIdx.x-shift])
val=mem[threadIdx.x-shift];
}
__syncthreads();
mem[threadIdx.x]=val;
}
if(threadIdx.x==1023)
output[blockIdx.x]=mem[1023];
}
__global__ void kernelPrepare(int *input, int *output, int* args)
{
const unsigned int count=args[0];
const unsigned int n=args[1];
int thid = (blockIdx.x * blockDim.x) + threadIdx.x;
if(thid*count>=n)
return;
int m=input[thid*count];
for(unsigned int i=1;i<count && thid*count+i<n;++i)
{
if(m>input[thid*count+i])
m=input[thid*count+i];
}
output[thid]=m;
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected kernelMain
.globl kernelMain
.p2align 8
.type kernelMain,@function
kernelMain:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x1c
s_load_b64 s[4:5], s[0:1], 0x0
s_mov_b32 s2, s15
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s3, s15, s3
v_add_lshl_u32 v3, s3, v0, 2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v4, 31, v3
v_lshlrev_b64 v[1:2], 2, v[3:4]
v_mov_b32_e32 v4, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[3:4], 2, v[3:4]
v_add_co_u32 v1, vcc_lo, s4, v1
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v2, vcc_lo, s5, v2, vcc_lo
global_load_b32 v2, v[1:2], off
v_add_co_u32 v1, vcc_lo, s4, v3
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v4, vcc_lo
s_mov_b64 s[4:5], 4
.LBB0_1:
s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
v_add_co_u32 v4, vcc_lo, v1, s4
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v3, vcc_lo
s_add_u32 s4, s4, 4
s_addc_u32 s5, s5, 0
s_cmp_eq_u32 s4, 16
global_load_b32 v4, v[4:5], off
s_waitcnt vmcnt(0)
v_min_i32_e32 v2, v4, v2
s_cbranch_scc0 .LBB0_1
v_lshlrev_b32_e32 v1, 2, v0
s_mov_b32 s3, 1
ds_store_b32 v1, v2
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_branch .LBB0_4
.p2align 6
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s4
s_lshl_b32 s4, s3, 1
s_cmpk_gt_u32 s3, 0x1ff
s_mov_b32 s3, s4
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
ds_store_b32 v1, v2
s_cbranch_scc1 .LBB0_6
.LBB0_4:
ds_load_b32 v2, v1
s_mov_b32 s4, exec_lo
v_cmpx_le_u32_e64 s3, v0
s_cbranch_execz .LBB0_3
v_subrev_nc_u32_e32 v3, s3, v0
s_delay_alu instid0(VALU_DEP_1)
v_lshlrev_b32_e32 v3, 2, v3
ds_load_b32 v3, v3
s_waitcnt lgkmcnt(0)
v_min_i32_e32 v2, v2, v3
s_branch .LBB0_3
.LBB0_6:
s_mov_b32 s3, exec_lo
v_cmpx_eq_u32_e32 0x3ff, v0
s_cbranch_execz .LBB0_8
v_mov_b32_e32 v0, 0
s_load_b64 s[0:1], s[0:1], 0x8
s_mov_b32 s3, 0
s_delay_alu instid0(SALU_CYCLE_1)
s_lshl_b64 s[2:3], s[2:3], 2
ds_load_b32 v1, v0 offset:4092
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
global_store_b32 v0, v1, s[0:1]
.LBB0_8:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel kernelMain
.amdhsa_group_segment_fixed_size 4096
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size kernelMain, .Lfunc_end0-kernelMain
.section .AMDGPU.csdata,"",@progbits
.text
.protected kernelPrepare
.globl kernelPrepare
.p2align 8
.type kernelPrepare,@function
kernelPrepare:
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x10
s_load_b32 s4, s[0:1], 0x24
s_waitcnt lgkmcnt(0)
s_load_b64 s[2:3], s[2:3], 0x0
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
s_mov_b32 s4, exec_lo
s_waitcnt lgkmcnt(0)
v_mul_lo_u32 v4, v1, s2
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_u32_e64 s3, v4
s_cbranch_execz .LBB1_8
s_load_b64 s[4:5], s[0:1], 0x0
v_mov_b32_e32 v5, 0
s_cmp_lt_u32 s2, 2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[4:5]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v5, vcc_lo, s4, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v6, vcc_lo, s5, v3, vcc_lo
global_load_b32 v0, v[5:6], off
s_cbranch_scc1 .LBB1_7
v_add_co_u32 v2, vcc_lo, v2, s4
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
v_add_nc_u32_e32 v4, 1, v4
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v2, vcc_lo, v2, 4
v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
s_add_i32 s4, s2, -1
s_mov_b32 s2, 0
s_branch .LBB1_4
.p2align 6
.LBB1_3:
s_or_b32 exec_lo, exec_lo, s6
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s6, exec_lo, s5
s_or_b32 s2, s6, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s2
s_cbranch_execz .LBB1_6
.LBB1_4:
s_or_b32 s5, s5, exec_lo
s_mov_b32 s6, exec_lo
v_cmpx_gt_u32_e64 s3, v4
s_cbranch_execz .LBB1_3
global_load_b32 v5, v[2:3], off
s_add_i32 s4, s4, -1
v_add_co_u32 v2, vcc_lo, v2, 4
s_cmp_eq_u32 s4, 0
v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
s_cselect_b32 s7, -1, 0
s_and_not1_b32 s5, s5, exec_lo
s_and_b32 s7, s7, exec_lo
v_add_nc_u32_e32 v4, 1, v4
s_or_b32 s5, s5, s7
s_waitcnt vmcnt(0)
v_min_i32_e32 v0, v0, v5
s_branch .LBB1_3
.LBB1_6:
s_or_b32 exec_lo, exec_lo, s2
.LBB1_7:
s_load_b64 s[0:1], s[0:1], 0x8
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v1, vcc_lo, s0, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
s_waitcnt vmcnt(0)
global_store_b32 v[1:2], v0, off
.LBB1_8:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel kernelPrepare
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size kernelPrepare, .Lfunc_end1-kernelPrepare
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 4096
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: kernelMain
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: kernelMain.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: kernelPrepare
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: kernelPrepare.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <cstdio>
#include <climits>
#define SERIAL_SCALE 2
#define SERIAL_PART (1<<SERIAL_SCALE)
extern "C" {
__global__
void kernelMain(int *input, int *output){
int thid = (blockIdx.x * blockDim.x) + threadIdx.x;
__shared__ int mem[1024];
int m=input[thid*SERIAL_PART];
for(unsigned int i=1;i<SERIAL_PART;++i)
{
int t=input[thid*SERIAL_PART+i];
if(t<m)
m=t;
}
mem[threadIdx.x]=m;
__syncthreads();
for(unsigned int shift=1;shift<1024;shift*=2)
{
int val=mem[threadIdx.x];
if(threadIdx.x>=shift)
{
if(val>mem[threadIdx.x-shift])
val=mem[threadIdx.x-shift];
}
__syncthreads();
mem[threadIdx.x]=val;
}
if(threadIdx.x==1023)
output[blockIdx.x]=mem[1023];
}
__global__ void kernelPrepare(int *input, int *output, int* args)
{
const unsigned int count=args[0];
const unsigned int n=args[1];
int thid = (blockIdx.x * blockDim.x) + threadIdx.x;
if(thid*count>=n)
return;
int m=input[thid*count];
for(unsigned int i=1;i<count && thid*count+i<n;++i)
{
if(m>input[thid*count+i])
m=input[thid*count+i];
}
output[thid]=m;
}
} | .text
.file "cuMin.hip"
.globl __device_stub__kernelMain # -- Begin function __device_stub__kernelMain
.p2align 4, 0x90
.type __device_stub__kernelMain,@function
__device_stub__kernelMain: # @__device_stub__kernelMain
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $kernelMain, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size __device_stub__kernelMain, .Lfunc_end0-__device_stub__kernelMain
.cfi_endproc
# -- End function
.globl __device_stub__kernelPrepare # -- Begin function __device_stub__kernelPrepare
.p2align 4, 0x90
.type __device_stub__kernelPrepare,@function
__device_stub__kernelPrepare: # @__device_stub__kernelPrepare
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $kernelPrepare, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end1:
.size __device_stub__kernelPrepare, .Lfunc_end1-__device_stub__kernelPrepare
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $kernelMain, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $kernelPrepare, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type kernelMain,@object # @kernelMain
.section .rodata,"a",@progbits
.globl kernelMain
.p2align 3, 0x0
kernelMain:
.quad __device_stub__kernelMain
.size kernelMain, 8
.type kernelPrepare,@object # @kernelPrepare
.globl kernelPrepare
.p2align 3, 0x0
kernelPrepare:
.quad __device_stub__kernelPrepare
.size kernelPrepare, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "kernelMain"
.size .L__unnamed_1, 11
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "kernelPrepare"
.size .L__unnamed_2, 14
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub__kernelMain
.addrsig_sym __device_stub__kernelPrepare
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym kernelMain
.addrsig_sym kernelPrepare
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0008d6bc_00000000-6_cuMin.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2059:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z32__device_stub__Z10kernelMainPiS_PiS_
.type _Z32__device_stub__Z10kernelMainPiS_PiS_, @function
_Z32__device_stub__Z10kernelMainPiS_PiS_:
.LFB2081:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq kernelMain(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2081:
.size _Z32__device_stub__Z10kernelMainPiS_PiS_, .-_Z32__device_stub__Z10kernelMainPiS_PiS_
.globl kernelMain
.type kernelMain, @function
kernelMain:
.LFB2082:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z10kernelMainPiS_PiS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2082:
.size kernelMain, .-kernelMain
.globl _Z37__device_stub__Z13kernelPreparePiS_S_PiS_S_
.type _Z37__device_stub__Z13kernelPreparePiS_S_PiS_S_, @function
_Z37__device_stub__Z13kernelPreparePiS_S_PiS_S_:
.LFB2083:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq kernelPrepare(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z37__device_stub__Z13kernelPreparePiS_S_PiS_S_, .-_Z37__device_stub__Z13kernelPreparePiS_S_PiS_S_
.globl kernelPrepare
.type kernelPrepare, @function
kernelPrepare:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z37__device_stub__Z13kernelPreparePiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size kernelPrepare, .-kernelPrepare
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "kernelPrepare"
.LC1:
.string "kernelMain"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq kernelPrepare(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq kernelMain(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "cuMin.hip"
.globl __device_stub__kernelMain # -- Begin function __device_stub__kernelMain
.p2align 4, 0x90
.type __device_stub__kernelMain,@function
__device_stub__kernelMain: # @__device_stub__kernelMain
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $kernelMain, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size __device_stub__kernelMain, .Lfunc_end0-__device_stub__kernelMain
.cfi_endproc
# -- End function
.globl __device_stub__kernelPrepare # -- Begin function __device_stub__kernelPrepare
.p2align 4, 0x90
.type __device_stub__kernelPrepare,@function
__device_stub__kernelPrepare: # @__device_stub__kernelPrepare
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $kernelPrepare, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end1:
.size __device_stub__kernelPrepare, .Lfunc_end1-__device_stub__kernelPrepare
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $kernelMain, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $kernelPrepare, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type kernelMain,@object # @kernelMain
.section .rodata,"a",@progbits
.globl kernelMain
.p2align 3, 0x0
kernelMain:
.quad __device_stub__kernelMain
.size kernelMain, 8
.type kernelPrepare,@object # @kernelPrepare
.globl kernelPrepare
.p2align 3, 0x0
kernelPrepare:
.quad __device_stub__kernelPrepare
.size kernelPrepare, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "kernelMain"
.size .L__unnamed_1, 11
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "kernelPrepare"
.size .L__unnamed_2, 14
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub__kernelMain
.addrsig_sym __device_stub__kernelPrepare
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym kernelMain
.addrsig_sym kernelPrepare
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include<stdio.h>
#include<iostream>
using namespace std;
void __global__ test() {
}
//struct false_usage{
// enum{
//
// }
//}
int main(int argc ,char* argv[]) {
if(argc < 2) {
fprintf(stderr,"invalid Usager,-c blocksize -g gridsize\n");
exit(-1);
}
int flag = 0;
unsigned int blocksize;
unsigned int gridsize;
while(++flag < argc) {
if(flag < argc && strlen(argv[flag]) == 2 && argv[flag][0] == '-') {
if (flag + 1 > argc) {
fprintf(stderr,"invalid Usager! input should be:``-c blocksize -g gridsize\n");
exit(-2);
}
switch(argv[flag][1] - 'a') {
case 'c' - 'a':
//protected
blocksize = atoi(argv[++flag]);
break;
case ('g' - 'a'):
gridsize = atoi(argv[++flag]);
break;
default:
fprintf(stderr, "no match\n");
}
}
}
dim3 block(blocksize, 1);
//dim3 grid(, 1);
} | code for sm_80
Function : _Z4testv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include<stdio.h>
#include<iostream>
using namespace std;
void __global__ test() {
}
//struct false_usage{
// enum{
//
// }
//}
int main(int argc ,char* argv[]) {
if(argc < 2) {
fprintf(stderr,"invalid Usager,-c blocksize -g gridsize\n");
exit(-1);
}
int flag = 0;
unsigned int blocksize;
unsigned int gridsize;
while(++flag < argc) {
if(flag < argc && strlen(argv[flag]) == 2 && argv[flag][0] == '-') {
if (flag + 1 > argc) {
fprintf(stderr,"invalid Usager! input should be:``-c blocksize -g gridsize\n");
exit(-2);
}
switch(argv[flag][1] - 'a') {
case 'c' - 'a':
//protected
blocksize = atoi(argv[++flag]);
break;
case ('g' - 'a'):
gridsize = atoi(argv[++flag]);
break;
default:
fprintf(stderr, "no match\n");
}
}
}
dim3 block(blocksize, 1);
//dim3 grid(, 1);
} | .file "tmpxft_000e927b_00000000-6_template.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "invalid Usager,-c blocksize -g gridsize\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "no match\n"
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
cmpl $1, %edi
jle .L15
movl %edi, %r12d
movq %rsi, %r14
movl $1, %ebx
movl $0, %ebp
jmp .L4
.L15:
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L18:
cmpb $45, 0(%r13)
je .L16
movl %ebx, %ebp
.L5:
leal 1(%rbp), %ebx
cmpl %ebx, %r12d
jle .L17
.L4:
movslq %ebx, %rax
movq (%r14,%rax,8), %r13
movq %r13, %rdi
call strlen@PLT
cmpq $2, %rax
je .L18
movl %ebx, %ebp
jmp .L5
.L16:
movsbl 1(%r13), %eax
leal -97(%rax), %edx
cmpl $99, %eax
je .L6
cmpl $6, %edx
je .L7
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %ebx, %ebp
jmp .L5
.L6:
addl $2, %ebp
movslq %ebp, %rax
movq (%r14,%rax,8), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
jmp .L5
.L7:
addl $2, %ebp
movslq %ebp, %rax
movq (%r14,%rax,8), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
jmp .L5
.L17:
movl $0, %eax
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3669:
.size main, .-main
.globl _Z22__device_stub__Z4testvv
.type _Z22__device_stub__Z4testvv, @function
_Z22__device_stub__Z4testvv:
.LFB3694:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L23
.L19:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L24
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z4testv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L19
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3694:
.size _Z22__device_stub__Z4testvv, .-_Z22__device_stub__Z4testvv
.globl _Z4testv
.type _Z4testv, @function
_Z4testv:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z22__device_stub__Z4testvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _Z4testv, .-_Z4testv
.section .rodata.str1.1
.LC2:
.string "_Z4testv"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z4testv(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include<stdio.h>
#include<iostream>
using namespace std;
void __global__ test() {
}
//struct false_usage{
// enum{
//
// }
//}
int main(int argc ,char* argv[]) {
if(argc < 2) {
fprintf(stderr,"invalid Usager,-c blocksize -g gridsize\n");
exit(-1);
}
int flag = 0;
unsigned int blocksize;
unsigned int gridsize;
while(++flag < argc) {
if(flag < argc && strlen(argv[flag]) == 2 && argv[flag][0] == '-') {
if (flag + 1 > argc) {
fprintf(stderr,"invalid Usager! input should be:``-c blocksize -g gridsize\n");
exit(-2);
}
switch(argv[flag][1] - 'a') {
case 'c' - 'a':
//protected
blocksize = atoi(argv[++flag]);
break;
case ('g' - 'a'):
gridsize = atoi(argv[++flag]);
break;
default:
fprintf(stderr, "no match\n");
}
}
}
dim3 block(blocksize, 1);
//dim3 grid(, 1);
} | #include <hip/hip_runtime.h>
#include<stdio.h>
#include<iostream>
using namespace std;
void __global__ test() {
}
//struct false_usage{
// enum{
//
// }
//}
int main(int argc ,char* argv[]) {
if(argc < 2) {
fprintf(stderr,"invalid Usager,-c blocksize -g gridsize\n");
exit(-1);
}
int flag = 0;
unsigned int blocksize;
unsigned int gridsize;
while(++flag < argc) {
if(flag < argc && strlen(argv[flag]) == 2 && argv[flag][0] == '-') {
if (flag + 1 > argc) {
fprintf(stderr,"invalid Usager! input should be:``-c blocksize -g gridsize\n");
exit(-2);
}
switch(argv[flag][1] - 'a') {
case 'c' - 'a':
//protected
blocksize = atoi(argv[++flag]);
break;
case ('g' - 'a'):
gridsize = atoi(argv[++flag]);
break;
default:
fprintf(stderr, "no match\n");
}
}
}
dim3 block(blocksize, 1);
//dim3 grid(, 1);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include<stdio.h>
#include<iostream>
using namespace std;
void __global__ test() {
}
//struct false_usage{
// enum{
//
// }
//}
int main(int argc ,char* argv[]) {
if(argc < 2) {
fprintf(stderr,"invalid Usager,-c blocksize -g gridsize\n");
exit(-1);
}
int flag = 0;
unsigned int blocksize;
unsigned int gridsize;
while(++flag < argc) {
if(flag < argc && strlen(argv[flag]) == 2 && argv[flag][0] == '-') {
if (flag + 1 > argc) {
fprintf(stderr,"invalid Usager! input should be:``-c blocksize -g gridsize\n");
exit(-2);
}
switch(argv[flag][1] - 'a') {
case 'c' - 'a':
//protected
blocksize = atoi(argv[++flag]);
break;
case ('g' - 'a'):
gridsize = atoi(argv[++flag]);
break;
default:
fprintf(stderr, "no match\n");
}
}
}
dim3 block(blocksize, 1);
//dim3 grid(, 1);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z4testv
.globl _Z4testv
.p2align 8
.type _Z4testv,@function
_Z4testv:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z4testv
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 0
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 0
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 1
.amdhsa_next_free_sgpr 1
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z4testv, .Lfunc_end0-_Z4testv
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args: []
.group_segment_fixed_size: 0
.kernarg_segment_align: 4
.kernarg_segment_size: 0
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z4testv
.private_segment_fixed_size: 0
.sgpr_count: 0
.sgpr_spill_count: 0
.symbol: _Z4testv.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 0
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include<stdio.h>
#include<iostream>
using namespace std;
void __global__ test() {
}
//struct false_usage{
// enum{
//
// }
//}
int main(int argc ,char* argv[]) {
if(argc < 2) {
fprintf(stderr,"invalid Usager,-c blocksize -g gridsize\n");
exit(-1);
}
int flag = 0;
unsigned int blocksize;
unsigned int gridsize;
while(++flag < argc) {
if(flag < argc && strlen(argv[flag]) == 2 && argv[flag][0] == '-') {
if (flag + 1 > argc) {
fprintf(stderr,"invalid Usager! input should be:``-c blocksize -g gridsize\n");
exit(-2);
}
switch(argv[flag][1] - 'a') {
case 'c' - 'a':
//protected
blocksize = atoi(argv[++flag]);
break;
case ('g' - 'a'):
gridsize = atoi(argv[++flag]);
break;
default:
fprintf(stderr, "no match\n");
}
}
}
dim3 block(blocksize, 1);
//dim3 grid(, 1);
} | .text
.file "template.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z19__device_stub__testv # -- Begin function _Z19__device_stub__testv
.p2align 4, 0x90
.type _Z19__device_stub__testv,@function
_Z19__device_stub__testv: # @_Z19__device_stub__testv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z4testv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z19__device_stub__testv, .Lfunc_end0-_Z19__device_stub__testv
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
cmpl $2, %edi
jl .LBB1_12
# %bb.1: # %.preheader.preheader
movq %rsi, %rbx
movl %edi, %ebp
xorl %r15d, %r15d
movl $1, %r12d
jmp .LBB1_2
.LBB1_8: # in Loop: Header=BB1_2 Depth=1
movq stderr(%rip), %rcx
movl $.L.str.2, %edi
movl $9, %esi
movl $1, %edx
callq fwrite@PLT
.p2align 4, 0x90
.LBB1_9: # in Loop: Header=BB1_2 Depth=1
movl %r12d, %r15d
.LBB1_10: # in Loop: Header=BB1_2 Depth=1
leal 1(%r15), %r12d
cmpl %ebp, %r12d
jge .LBB1_11
.LBB1_2: # %.preheader
# =>This Inner Loop Header: Depth=1
movslq %r12d, %rax
movq (%rbx,%rax,8), %r14
movq %r14, %rdi
callq strlen
cmpq $2, %rax
jne .LBB1_9
# %bb.3: # in Loop: Header=BB1_2 Depth=1
cmpb $45, (%r14)
jne .LBB1_9
# %bb.4: # in Loop: Header=BB1_2 Depth=1
addl $2, %r15d
cmpl %ebp, %r15d
jg .LBB1_13
# %bb.5: # in Loop: Header=BB1_2 Depth=1
movzbl 1(%r14), %eax
cmpl $103, %eax
je .LBB1_10
# %bb.6: # in Loop: Header=BB1_2 Depth=1
cmpl $99, %eax
jne .LBB1_8
# %bb.7: # in Loop: Header=BB1_2 Depth=1
movslq %r15d, %rax
movq (%rbx,%rax,8), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
jmp .LBB1_10
.LBB1_11:
xorl %eax, %eax
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_13:
.cfi_def_cfa_offset 48
movq stderr(%rip), %rcx
movl $.L.str.1, %edi
movl $59, %esi
movl $1, %edx
callq fwrite@PLT
movl $-2, %edi
callq exit
.LBB1_12:
movq stderr(%rip), %rcx
movl $.L.str, %edi
movl $40, %esi
movl $1, %edx
callq fwrite@PLT
movl $-1, %edi
callq exit
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z4testv, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z4testv,@object # @_Z4testv
.section .rodata,"a",@progbits
.globl _Z4testv
.p2align 3, 0x0
_Z4testv:
.quad _Z19__device_stub__testv
.size _Z4testv, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "invalid Usager,-c blocksize -g gridsize\n"
.size .L.str, 41
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "invalid Usager! input should be:``-c blocksize -g gridsize\n"
.size .L.str.1, 60
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "no match\n"
.size .L.str.2, 10
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z4testv"
.size .L__unnamed_1, 9
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z19__device_stub__testv
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z4testv
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z4testv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z4testv
.globl _Z4testv
.p2align 8
.type _Z4testv,@function
_Z4testv:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z4testv
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 0
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 0
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 1
.amdhsa_next_free_sgpr 1
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z4testv, .Lfunc_end0-_Z4testv
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args: []
.group_segment_fixed_size: 0
.kernarg_segment_align: 4
.kernarg_segment_size: 0
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z4testv
.private_segment_fixed_size: 0
.sgpr_count: 0
.sgpr_spill_count: 0
.symbol: _Z4testv.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 0
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000e927b_00000000-6_template.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "invalid Usager,-c blocksize -g gridsize\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "no match\n"
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
cmpl $1, %edi
jle .L15
movl %edi, %r12d
movq %rsi, %r14
movl $1, %ebx
movl $0, %ebp
jmp .L4
.L15:
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L18:
cmpb $45, 0(%r13)
je .L16
movl %ebx, %ebp
.L5:
leal 1(%rbp), %ebx
cmpl %ebx, %r12d
jle .L17
.L4:
movslq %ebx, %rax
movq (%r14,%rax,8), %r13
movq %r13, %rdi
call strlen@PLT
cmpq $2, %rax
je .L18
movl %ebx, %ebp
jmp .L5
.L16:
movsbl 1(%r13), %eax
leal -97(%rax), %edx
cmpl $99, %eax
je .L6
cmpl $6, %edx
je .L7
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %ebx, %ebp
jmp .L5
.L6:
addl $2, %ebp
movslq %ebp, %rax
movq (%r14,%rax,8), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
jmp .L5
.L7:
addl $2, %ebp
movslq %ebp, %rax
movq (%r14,%rax,8), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
jmp .L5
.L17:
movl $0, %eax
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3669:
.size main, .-main
.globl _Z22__device_stub__Z4testvv
.type _Z22__device_stub__Z4testvv, @function
_Z22__device_stub__Z4testvv:
.LFB3694:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L23
.L19:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L24
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z4testv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L19
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3694:
.size _Z22__device_stub__Z4testvv, .-_Z22__device_stub__Z4testvv
.globl _Z4testv
.type _Z4testv, @function
_Z4testv:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z22__device_stub__Z4testvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _Z4testv, .-_Z4testv
.section .rodata.str1.1
.LC2:
.string "_Z4testv"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z4testv(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "template.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z19__device_stub__testv # -- Begin function _Z19__device_stub__testv
.p2align 4, 0x90
.type _Z19__device_stub__testv,@function
_Z19__device_stub__testv: # @_Z19__device_stub__testv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z4testv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z19__device_stub__testv, .Lfunc_end0-_Z19__device_stub__testv
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
cmpl $2, %edi
jl .LBB1_12
# %bb.1: # %.preheader.preheader
movq %rsi, %rbx
movl %edi, %ebp
xorl %r15d, %r15d
movl $1, %r12d
jmp .LBB1_2
.LBB1_8: # in Loop: Header=BB1_2 Depth=1
movq stderr(%rip), %rcx
movl $.L.str.2, %edi
movl $9, %esi
movl $1, %edx
callq fwrite@PLT
.p2align 4, 0x90
.LBB1_9: # in Loop: Header=BB1_2 Depth=1
movl %r12d, %r15d
.LBB1_10: # in Loop: Header=BB1_2 Depth=1
leal 1(%r15), %r12d
cmpl %ebp, %r12d
jge .LBB1_11
.LBB1_2: # %.preheader
# =>This Inner Loop Header: Depth=1
movslq %r12d, %rax
movq (%rbx,%rax,8), %r14
movq %r14, %rdi
callq strlen
cmpq $2, %rax
jne .LBB1_9
# %bb.3: # in Loop: Header=BB1_2 Depth=1
cmpb $45, (%r14)
jne .LBB1_9
# %bb.4: # in Loop: Header=BB1_2 Depth=1
addl $2, %r15d
cmpl %ebp, %r15d
jg .LBB1_13
# %bb.5: # in Loop: Header=BB1_2 Depth=1
movzbl 1(%r14), %eax
cmpl $103, %eax
je .LBB1_10
# %bb.6: # in Loop: Header=BB1_2 Depth=1
cmpl $99, %eax
jne .LBB1_8
# %bb.7: # in Loop: Header=BB1_2 Depth=1
movslq %r15d, %rax
movq (%rbx,%rax,8), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
jmp .LBB1_10
.LBB1_11:
xorl %eax, %eax
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_13:
.cfi_def_cfa_offset 48
movq stderr(%rip), %rcx
movl $.L.str.1, %edi
movl $59, %esi
movl $1, %edx
callq fwrite@PLT
movl $-2, %edi
callq exit
.LBB1_12:
movq stderr(%rip), %rcx
movl $.L.str, %edi
movl $40, %esi
movl $1, %edx
callq fwrite@PLT
movl $-1, %edi
callq exit
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z4testv, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z4testv,@object # @_Z4testv
.section .rodata,"a",@progbits
.globl _Z4testv
.p2align 3, 0x0
_Z4testv:
.quad _Z19__device_stub__testv
.size _Z4testv, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "invalid Usager,-c blocksize -g gridsize\n"
.size .L.str, 41
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "invalid Usager! input should be:``-c blocksize -g gridsize\n"
.size .L.str.1, 60
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "no match\n"
.size .L.str.2, 10
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z4testv"
.size .L__unnamed_1, 9
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z19__device_stub__testv
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z4testv
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | ///////////////////////////////////////////////////////////////////////////////
//
// The MIT License
//
// Copyright (c) 2006 Scientific Computing and Imaging Institute,
// University of Utah (USA)
//
// License for the specific language governing rights and limitations under
// Permission is hereby granted, free of charge, to any person obtaining a
// copy of this software and associated documentation files (the "Software"),
// to deal in the Software without restriction, including without limitation
// the rights to use, copy, modify, merge, publish, distribute, sublicense,
// and/or sell copies of the Software, and to permit persons to whom the
// Software is furnished to do so, subject to the following conditions:
//
// The above copyright notice and this permission notice shall be included
// in all copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
// OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
// THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
// FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
// DEALINGS IN THE SOFTWARE.
//
///////////////////////////////////////////////////////////////////////////////
#ifndef ELVIS_CORE_INNER_INTEGRAL_ADAPTIVE_TRAPEZOIDAL_CU
#define ELVIS_CORE_INNER_INTEGRAL_ADAPTIVE_TRAPEZOIDAL_CU
namespace ElVis
{
// /// Adaptive trapezoidal integration using a runtime stack to handle
// recursion.
// /// Value are kept for subsequent sampling.
// template<typename T, unsigned int n>
// struct InnerIntegralAdaptiveTrapezoidal
// {
// public:
// struct StackPoint
// {
// template<typename FieldFunc>
// __device__
// void Evaluate(const TransferFunction* densityFunc,
// TransferFunctionChannel channel,
// const FieldFunc& fieldFunc)
// {
// T s = fieldFunc(TVal);
// F = densityFunc->Sample(channel, s);
// }
// __device__ void Reset()
// {
// TVal = MAKE_FLOAT(1e30);
// }
// __device__ bool IsUninitialized() const
// {
// return TVal == MAKE_FLOAT(1e30);
// }
// __device__ StackPoint& operator=(const StackPoint& rhs)
// {
// TVal = rhs.TVal;
// F = rhs.F;
// return *this;
// }
// T TVal;
// T F;
// };
// struct StackEntry
// {
// __device__ void CalculateMidpointT()
// {
// Mid().TVal = Left().TVal + (Right().TVal -
// Left().TVal)/2.0;
// }
// __device__ void SetT(const T& t0, const T& t1)
// {
// Left().TVal = t0;
// Right().TVal = t1;
// CalculateMidpointT();
// }
// __device__ T GetH() const
// {
// return Right().TVal - Left().TVal;
// }
// template<typename FieldFunc>
// __device__ void EvaluateAll(const TransferFunction*
// densityFunc,
// TransferFunctionChannel channel,
// const FieldFunc& fieldFunc)
// {
// for(unsigned int i = 0; i < 3; ++i)
// {
// points[i].Evaluate(densityFunc, channel, fieldFunc);
// }
// }
// __device__ StackPoint& Left() { return points[0]; }
// __device__ StackPoint& Mid() { return points[1]; }
// __device__ StackPoint& Right() { return points[2]; }
// __device__ const StackPoint& Left() const { return
// points[0]; }
// __device__ const StackPoint& Mid() const { return
// points[1]; }
// __device__ const StackPoint& Right() const { return
// points[2]; }
// StackPoint points[3];
// };
// template<typename FieldFunctionType>
// __device__ void Integrate(const T& t0, const T& t1, const
// TransferFunction* transferFunction,
// TransferFunctionChannel channel,
// const FieldFunctionType& fieldFunction, const T&
// globalEpsilon,
// const T& globalIntegralEstimate,
// const T& maxFunctionValue, bool&
// reachedMaxRecursion,
// bool traceEnabled)
// {
// if( traceEnabled )
// {
// printf("Global Epsilon %f, globalIntegralEstimate %f,
// maxValue %f\n", globalEpsilon, globalIntegralEstimate,
// maxFunctionValue);
// }
// const unsigned int maxRecursion = n;
// reachedMaxRecursion = false;
// StackEntry stack[maxRecursion];
// stack[0].SetT(t0, t1);
// stack[0].EvaluateAll(transferFunction, channel,
// fieldFunction);
// stack[1].Left() = stack[0].Left();
// stack[1].Mid().Reset();
// stack[1].Right() = stack[0].Mid();
// unsigned int minimumDepth = 2;
// int i = 1;
// t[0] = t0;
// f[0] = stack[0].Left().F;
// I[0] = 0.0;
// adaptiveIndex = 0;
// while( i > 0 )
// {
// reachedMaxRecursion |= (i == maxRecursion-1);
// if( stack[i].Mid().IsUninitialized() )
// {
// bool needToSubdivide = false;
// stack[i].CalculateMidpointT();
// stack[i].Mid().Evaluate(transferFunction, channel,
// fieldFunction);
// if( i < minimumDepth )
// {
// needToSubdivide = true;
// }
// else
// {
// T I0 = stack[i].GetH()/MAKE_FLOAT(2.0) *
// (stack[i].Left().F + stack[i].Right().F);
// T I1 = stack[i].GetH()/MAKE_FLOAT(4.0) *
// (stack[i].Left().F + 2.0*stack[i].Mid().F +
// stack[i].Right().F);
// T localEpsilon =
// globalEpsilon*globalIntegralEstimate *
// (stack[i].GetH()/stack[0].GetH());
// if( traceEnabled )
// {
// printf("Level %d, Interval (%f, %f, %f),
// values (%f, %f, %f) I0 = %f, I1 = %f,
// localEpsilon = %f\n", i,
// stack[i].Left().TVal, stack[i].Mid().TVal,
// stack[i].Right().TVal,
// stack[i].Left().F, stack[i].Mid().F,
// stack[i].Right().F, I0, I1,
// localEpsilon);
// }
// ElVisFloat h = stack[i].GetH()/MAKE_FLOAT(2.0);
// if( stack[i].Left().F == MAKE_FLOAT(0.0) &&
// stack[i].Mid().F == MAKE_FLOAT(0.0) &&
// stack[i].Right().F == MAKE_FLOAT(0.0) )
// {
// ElVis::Interval<ElVisFloat> range =
// fieldFunction.EstimateRange(stack[i].Left().TVal,
// stack[i].Right().TVal);
// ElVisFloat maxValue =
// transferFunction->GetMaxValue(channel,
// range);
// T maxSegmentError =
// (maxFunctionValue*h)/globalIntegralEstimate;
// T updatedSegmentError =
// (maxValue*h)/globalIntegralEstimate;
// if( traceEnabled )
// {
// printf("All 3 values are 0. Scalar
// range is (%f, %f), maxSegmentError %f,
// updatedSegmentError %f\n",
// range.GetLow(), range.GetHigh(),
// maxSegmentError,
// updatedSegmentError);
// }
// if( updatedSegmentError > localEpsilon && i
// < maxRecursion-1 )
// {
// needToSubdivide = true;
// }
// }
// else if( stack[i].Left().F == MAKE_FLOAT(0.0) ||
// stack[i].Mid().F == MAKE_FLOAT(0.0) ||
// stack[i].Right().F == MAKE_FLOAT(0.0) )
// {
// // If any of the samples are 0, then we know
// there is a breakpoint somewhere and we
// should subdivide.
// T maxSegmentError =
// (maxFunctionValue*h)/globalIntegralEstimate;
// ElVis::Interval<ElVisFloat> range =
// fieldFunction.EstimateRange(stack[i].Left().TVal,
// stack[i].Right().TVal);
// ElVisFloat maxValue =
// transferFunction->GetMaxValue(channel,
// range);
// T updatedSegmentError =
// (maxValue*h)/globalIntegralEstimate;
// if( traceEnabled )
// {
// printf("At least one value is 0. Scalar
// range is (%f, %f), maxSegmentError %f,
// updatedSegmentError %f\n",
// range.GetLow(), range.GetHigh(),
// maxSegmentError,
// updatedSegmentError);
// }
// if( traceEnabled )
// {
// printf("One of the samples is 0,
// maxSegmentError = %f, localEpsilon =
// %f\n", maxSegmentError, localEpsilon);
// }
// if(updatedSegmentError > localEpsilon && i <
// maxRecursion-1 )
// {
// needToSubdivide = true;
// }
// }
// else
// {
// T errorEstimate =
// fabs(I0-I1)/globalIntegralEstimate;
// if( traceEnabled )
// {
// printf("No samples 0, errorEstimate =
// %f, localEpsilon = %f\n", errorEstimate,
// localEpsilon);
// }
// if( errorEstimate > localEpsilon && i <
// maxRecursion-1 )
// {
// needToSubdivide = true;
// }
// }
// }
// if( traceEnabled )
// {
// printf("Subdividing = %d\n", needToSubdivide? 1
// : 0);
// }
// if( needToSubdivide )
// {
// stack[i+1].Left() = stack[i].Left();
// stack[i+1].Mid().Reset();
// stack[i+1].Right() = stack[i].Mid();
// i = i + 1;
// }
// else
// {
// T prevValue = I[adaptiveIndex];
// T h = stack[i].GetH()/MAKE_FLOAT(4.0);
// T mid_f = stack[i].Mid().F;
// T right_f = stack[i].Right().F;
// t[adaptiveIndex+1] = stack[i].Mid().TVal;
// t[adaptiveIndex+2] = stack[i].Right().TVal;
// f[adaptiveIndex+1] = mid_f;
// f[adaptiveIndex+2] = right_f;
// T leftContribution = h * (stack[i].Left().F +
// mid_f);
// T rightContribution = h * (mid_f + right_f);
// I[adaptiveIndex+1] = prevValue +
// leftContribution;
// I[adaptiveIndex+2] = prevValue +
// leftContribution+rightContribution;
// if( traceEnabled )
// {
// printf("Integral Value at %f = %f\n",
// t[adaptiveIndex+1], I[adaptiveIndex+1]);
// printf("Integral Value at %f = %f\n",
// t[adaptiveIndex+2], I[adaptiveIndex+2]);
// }
// adaptiveIndex += 2;
// }
// }
// else
// {
// if( stack[i].Right().TVal == stack[i-1].Mid().TVal )
// {
// // We just finished traversing the left side,
// now go to
// // the right.
// stack[i].Left() = stack[i-1].Mid();
// stack[i].Mid().Reset();
// stack[i].Right() = stack[i-1].Right();
// }
// else
// {
// // We finished this branch. Remove it and go up
// to
// // the next one.
// i = i-1;
// }
// }
// }
// }
// __device__ T SampleInnerIntegral(T t_i, T sample,
// TransferFunctionChannel channel, const TransferFunction*
// densityFunc) const
// {
// if( t_i < t[0] ||
// t_i > t[adaptiveIndex] )
// {
// return MAKE_FLOAT(0.0);
// }
// if( t_i == t[0] ) return MAKE_FLOAT(0.0);
// if( t_i == t[adaptiveIndex] ) return I[adaptiveIndex];
// const T* a = &(t[0]);
// const T* b = &(t[adaptiveIndex]);
// while(b-a > 1 )
// {
// const T* mid = (b-a)/2 + a;
// if( *mid == t_i )
// {
// return I[mid-a];
// }
// if( t_i < *mid )
// {
// b = mid;
// }
// else
// {
// a = mid;
// }
// }
// T baseline = I[a-t];
// T segment = (t_i-*a)/MAKE_FLOAT(2.0) * ( f[a-t] +
// densityFunc->Sample(channel, sample));
// return baseline+segment;
// }
// __device__ T OverallValue() const
// {
// return I[adaptiveIndex];
// }
// static const unsigned int arraySize = (0x01 << n) + 1;
// T t[arraySize];
// T f[arraySize];
// T I[arraySize];
// private:
// unsigned int adaptiveIndex;
// };
}
#endif | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | ///////////////////////////////////////////////////////////////////////////////
//
// The MIT License
//
// Copyright (c) 2006 Scientific Computing and Imaging Institute,
// University of Utah (USA)
//
// License for the specific language governing rights and limitations under
// Permission is hereby granted, free of charge, to any person obtaining a
// copy of this software and associated documentation files (the "Software"),
// to deal in the Software without restriction, including without limitation
// the rights to use, copy, modify, merge, publish, distribute, sublicense,
// and/or sell copies of the Software, and to permit persons to whom the
// Software is furnished to do so, subject to the following conditions:
//
// The above copyright notice and this permission notice shall be included
// in all copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
// OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
// THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
// FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
// DEALINGS IN THE SOFTWARE.
//
///////////////////////////////////////////////////////////////////////////////
#ifndef ELVIS_CORE_INNER_INTEGRAL_ADAPTIVE_TRAPEZOIDAL_CU
#define ELVIS_CORE_INNER_INTEGRAL_ADAPTIVE_TRAPEZOIDAL_CU
namespace ElVis
{
// /// Adaptive trapezoidal integration using a runtime stack to handle
// recursion.
// /// Value are kept for subsequent sampling.
// template<typename T, unsigned int n>
// struct InnerIntegralAdaptiveTrapezoidal
// {
// public:
// struct StackPoint
// {
// template<typename FieldFunc>
// __device__
// void Evaluate(const TransferFunction* densityFunc,
// TransferFunctionChannel channel,
// const FieldFunc& fieldFunc)
// {
// T s = fieldFunc(TVal);
// F = densityFunc->Sample(channel, s);
// }
// __device__ void Reset()
// {
// TVal = MAKE_FLOAT(1e30);
// }
// __device__ bool IsUninitialized() const
// {
// return TVal == MAKE_FLOAT(1e30);
// }
// __device__ StackPoint& operator=(const StackPoint& rhs)
// {
// TVal = rhs.TVal;
// F = rhs.F;
// return *this;
// }
// T TVal;
// T F;
// };
// struct StackEntry
// {
// __device__ void CalculateMidpointT()
// {
// Mid().TVal = Left().TVal + (Right().TVal -
// Left().TVal)/2.0;
// }
// __device__ void SetT(const T& t0, const T& t1)
// {
// Left().TVal = t0;
// Right().TVal = t1;
// CalculateMidpointT();
// }
// __device__ T GetH() const
// {
// return Right().TVal - Left().TVal;
// }
// template<typename FieldFunc>
// __device__ void EvaluateAll(const TransferFunction*
// densityFunc,
// TransferFunctionChannel channel,
// const FieldFunc& fieldFunc)
// {
// for(unsigned int i = 0; i < 3; ++i)
// {
// points[i].Evaluate(densityFunc, channel, fieldFunc);
// }
// }
// __device__ StackPoint& Left() { return points[0]; }
// __device__ StackPoint& Mid() { return points[1]; }
// __device__ StackPoint& Right() { return points[2]; }
// __device__ const StackPoint& Left() const { return
// points[0]; }
// __device__ const StackPoint& Mid() const { return
// points[1]; }
// __device__ const StackPoint& Right() const { return
// points[2]; }
// StackPoint points[3];
// };
// template<typename FieldFunctionType>
// __device__ void Integrate(const T& t0, const T& t1, const
// TransferFunction* transferFunction,
// TransferFunctionChannel channel,
// const FieldFunctionType& fieldFunction, const T&
// globalEpsilon,
// const T& globalIntegralEstimate,
// const T& maxFunctionValue, bool&
// reachedMaxRecursion,
// bool traceEnabled)
// {
// if( traceEnabled )
// {
// printf("Global Epsilon %f, globalIntegralEstimate %f,
// maxValue %f\n", globalEpsilon, globalIntegralEstimate,
// maxFunctionValue);
// }
// const unsigned int maxRecursion = n;
// reachedMaxRecursion = false;
// StackEntry stack[maxRecursion];
// stack[0].SetT(t0, t1);
// stack[0].EvaluateAll(transferFunction, channel,
// fieldFunction);
// stack[1].Left() = stack[0].Left();
// stack[1].Mid().Reset();
// stack[1].Right() = stack[0].Mid();
// unsigned int minimumDepth = 2;
// int i = 1;
// t[0] = t0;
// f[0] = stack[0].Left().F;
// I[0] = 0.0;
// adaptiveIndex = 0;
// while( i > 0 )
// {
// reachedMaxRecursion |= (i == maxRecursion-1);
// if( stack[i].Mid().IsUninitialized() )
// {
// bool needToSubdivide = false;
// stack[i].CalculateMidpointT();
// stack[i].Mid().Evaluate(transferFunction, channel,
// fieldFunction);
// if( i < minimumDepth )
// {
// needToSubdivide = true;
// }
// else
// {
// T I0 = stack[i].GetH()/MAKE_FLOAT(2.0) *
// (stack[i].Left().F + stack[i].Right().F);
// T I1 = stack[i].GetH()/MAKE_FLOAT(4.0) *
// (stack[i].Left().F + 2.0*stack[i].Mid().F +
// stack[i].Right().F);
// T localEpsilon =
// globalEpsilon*globalIntegralEstimate *
// (stack[i].GetH()/stack[0].GetH());
// if( traceEnabled )
// {
// printf("Level %d, Interval (%f, %f, %f),
// values (%f, %f, %f) I0 = %f, I1 = %f,
// localEpsilon = %f\n", i,
// stack[i].Left().TVal, stack[i].Mid().TVal,
// stack[i].Right().TVal,
// stack[i].Left().F, stack[i].Mid().F,
// stack[i].Right().F, I0, I1,
// localEpsilon);
// }
// ElVisFloat h = stack[i].GetH()/MAKE_FLOAT(2.0);
// if( stack[i].Left().F == MAKE_FLOAT(0.0) &&
// stack[i].Mid().F == MAKE_FLOAT(0.0) &&
// stack[i].Right().F == MAKE_FLOAT(0.0) )
// {
// ElVis::Interval<ElVisFloat> range =
// fieldFunction.EstimateRange(stack[i].Left().TVal,
// stack[i].Right().TVal);
// ElVisFloat maxValue =
// transferFunction->GetMaxValue(channel,
// range);
// T maxSegmentError =
// (maxFunctionValue*h)/globalIntegralEstimate;
// T updatedSegmentError =
// (maxValue*h)/globalIntegralEstimate;
// if( traceEnabled )
// {
// printf("All 3 values are 0. Scalar
// range is (%f, %f), maxSegmentError %f,
// updatedSegmentError %f\n",
// range.GetLow(), range.GetHigh(),
// maxSegmentError,
// updatedSegmentError);
// }
// if( updatedSegmentError > localEpsilon && i
// < maxRecursion-1 )
// {
// needToSubdivide = true;
// }
// }
// else if( stack[i].Left().F == MAKE_FLOAT(0.0) ||
// stack[i].Mid().F == MAKE_FLOAT(0.0) ||
// stack[i].Right().F == MAKE_FLOAT(0.0) )
// {
// // If any of the samples are 0, then we know
// there is a breakpoint somewhere and we
// should subdivide.
// T maxSegmentError =
// (maxFunctionValue*h)/globalIntegralEstimate;
// ElVis::Interval<ElVisFloat> range =
// fieldFunction.EstimateRange(stack[i].Left().TVal,
// stack[i].Right().TVal);
// ElVisFloat maxValue =
// transferFunction->GetMaxValue(channel,
// range);
// T updatedSegmentError =
// (maxValue*h)/globalIntegralEstimate;
// if( traceEnabled )
// {
// printf("At least one value is 0. Scalar
// range is (%f, %f), maxSegmentError %f,
// updatedSegmentError %f\n",
// range.GetLow(), range.GetHigh(),
// maxSegmentError,
// updatedSegmentError);
// }
// if( traceEnabled )
// {
// printf("One of the samples is 0,
// maxSegmentError = %f, localEpsilon =
// %f\n", maxSegmentError, localEpsilon);
// }
// if(updatedSegmentError > localEpsilon && i <
// maxRecursion-1 )
// {
// needToSubdivide = true;
// }
// }
// else
// {
// T errorEstimate =
// fabs(I0-I1)/globalIntegralEstimate;
// if( traceEnabled )
// {
// printf("No samples 0, errorEstimate =
// %f, localEpsilon = %f\n", errorEstimate,
// localEpsilon);
// }
// if( errorEstimate > localEpsilon && i <
// maxRecursion-1 )
// {
// needToSubdivide = true;
// }
// }
// }
// if( traceEnabled )
// {
// printf("Subdividing = %d\n", needToSubdivide? 1
// : 0);
// }
// if( needToSubdivide )
// {
// stack[i+1].Left() = stack[i].Left();
// stack[i+1].Mid().Reset();
// stack[i+1].Right() = stack[i].Mid();
// i = i + 1;
// }
// else
// {
// T prevValue = I[adaptiveIndex];
// T h = stack[i].GetH()/MAKE_FLOAT(4.0);
// T mid_f = stack[i].Mid().F;
// T right_f = stack[i].Right().F;
// t[adaptiveIndex+1] = stack[i].Mid().TVal;
// t[adaptiveIndex+2] = stack[i].Right().TVal;
// f[adaptiveIndex+1] = mid_f;
// f[adaptiveIndex+2] = right_f;
// T leftContribution = h * (stack[i].Left().F +
// mid_f);
// T rightContribution = h * (mid_f + right_f);
// I[adaptiveIndex+1] = prevValue +
// leftContribution;
// I[adaptiveIndex+2] = prevValue +
// leftContribution+rightContribution;
// if( traceEnabled )
// {
// printf("Integral Value at %f = %f\n",
// t[adaptiveIndex+1], I[adaptiveIndex+1]);
// printf("Integral Value at %f = %f\n",
// t[adaptiveIndex+2], I[adaptiveIndex+2]);
// }
// adaptiveIndex += 2;
// }
// }
// else
// {
// if( stack[i].Right().TVal == stack[i-1].Mid().TVal )
// {
// // We just finished traversing the left side,
// now go to
// // the right.
// stack[i].Left() = stack[i-1].Mid();
// stack[i].Mid().Reset();
// stack[i].Right() = stack[i-1].Right();
// }
// else
// {
// // We finished this branch. Remove it and go up
// to
// // the next one.
// i = i-1;
// }
// }
// }
// }
// __device__ T SampleInnerIntegral(T t_i, T sample,
// TransferFunctionChannel channel, const TransferFunction*
// densityFunc) const
// {
// if( t_i < t[0] ||
// t_i > t[adaptiveIndex] )
// {
// return MAKE_FLOAT(0.0);
// }
// if( t_i == t[0] ) return MAKE_FLOAT(0.0);
// if( t_i == t[adaptiveIndex] ) return I[adaptiveIndex];
// const T* a = &(t[0]);
// const T* b = &(t[adaptiveIndex]);
// while(b-a > 1 )
// {
// const T* mid = (b-a)/2 + a;
// if( *mid == t_i )
// {
// return I[mid-a];
// }
// if( t_i < *mid )
// {
// b = mid;
// }
// else
// {
// a = mid;
// }
// }
// T baseline = I[a-t];
// T segment = (t_i-*a)/MAKE_FLOAT(2.0) * ( f[a-t] +
// densityFunc->Sample(channel, sample));
// return baseline+segment;
// }
// __device__ T OverallValue() const
// {
// return I[adaptiveIndex];
// }
// static const unsigned int arraySize = (0x01 << n) + 1;
// T t[arraySize];
// T f[arraySize];
// T I[arraySize];
// private:
// unsigned int adaptiveIndex;
// };
}
#endif | .file "tmpxft_000e97f9_00000000-6_InnerIntegralAdaptiveTrapezoidal.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | ///////////////////////////////////////////////////////////////////////////////
//
// The MIT License
//
// Copyright (c) 2006 Scientific Computing and Imaging Institute,
// University of Utah (USA)
//
// License for the specific language governing rights and limitations under
// Permission is hereby granted, free of charge, to any person obtaining a
// copy of this software and associated documentation files (the "Software"),
// to deal in the Software without restriction, including without limitation
// the rights to use, copy, modify, merge, publish, distribute, sublicense,
// and/or sell copies of the Software, and to permit persons to whom the
// Software is furnished to do so, subject to the following conditions:
//
// The above copyright notice and this permission notice shall be included
// in all copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
// OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
// THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
// FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
// DEALINGS IN THE SOFTWARE.
//
///////////////////////////////////////////////////////////////////////////////
#ifndef ELVIS_CORE_INNER_INTEGRAL_ADAPTIVE_TRAPEZOIDAL_CU
#define ELVIS_CORE_INNER_INTEGRAL_ADAPTIVE_TRAPEZOIDAL_CU
namespace ElVis
{
// /// Adaptive trapezoidal integration using a runtime stack to handle
// recursion.
// /// Value are kept for subsequent sampling.
// template<typename T, unsigned int n>
// struct InnerIntegralAdaptiveTrapezoidal
// {
// public:
// struct StackPoint
// {
// template<typename FieldFunc>
// __device__
// void Evaluate(const TransferFunction* densityFunc,
// TransferFunctionChannel channel,
// const FieldFunc& fieldFunc)
// {
// T s = fieldFunc(TVal);
// F = densityFunc->Sample(channel, s);
// }
// __device__ void Reset()
// {
// TVal = MAKE_FLOAT(1e30);
// }
// __device__ bool IsUninitialized() const
// {
// return TVal == MAKE_FLOAT(1e30);
// }
// __device__ StackPoint& operator=(const StackPoint& rhs)
// {
// TVal = rhs.TVal;
// F = rhs.F;
// return *this;
// }
// T TVal;
// T F;
// };
// struct StackEntry
// {
// __device__ void CalculateMidpointT()
// {
// Mid().TVal = Left().TVal + (Right().TVal -
// Left().TVal)/2.0;
// }
// __device__ void SetT(const T& t0, const T& t1)
// {
// Left().TVal = t0;
// Right().TVal = t1;
// CalculateMidpointT();
// }
// __device__ T GetH() const
// {
// return Right().TVal - Left().TVal;
// }
// template<typename FieldFunc>
// __device__ void EvaluateAll(const TransferFunction*
// densityFunc,
// TransferFunctionChannel channel,
// const FieldFunc& fieldFunc)
// {
// for(unsigned int i = 0; i < 3; ++i)
// {
// points[i].Evaluate(densityFunc, channel, fieldFunc);
// }
// }
// __device__ StackPoint& Left() { return points[0]; }
// __device__ StackPoint& Mid() { return points[1]; }
// __device__ StackPoint& Right() { return points[2]; }
// __device__ const StackPoint& Left() const { return
// points[0]; }
// __device__ const StackPoint& Mid() const { return
// points[1]; }
// __device__ const StackPoint& Right() const { return
// points[2]; }
// StackPoint points[3];
// };
// template<typename FieldFunctionType>
// __device__ void Integrate(const T& t0, const T& t1, const
// TransferFunction* transferFunction,
// TransferFunctionChannel channel,
// const FieldFunctionType& fieldFunction, const T&
// globalEpsilon,
// const T& globalIntegralEstimate,
// const T& maxFunctionValue, bool&
// reachedMaxRecursion,
// bool traceEnabled)
// {
// if( traceEnabled )
// {
// printf("Global Epsilon %f, globalIntegralEstimate %f,
// maxValue %f\n", globalEpsilon, globalIntegralEstimate,
// maxFunctionValue);
// }
// const unsigned int maxRecursion = n;
// reachedMaxRecursion = false;
// StackEntry stack[maxRecursion];
// stack[0].SetT(t0, t1);
// stack[0].EvaluateAll(transferFunction, channel,
// fieldFunction);
// stack[1].Left() = stack[0].Left();
// stack[1].Mid().Reset();
// stack[1].Right() = stack[0].Mid();
// unsigned int minimumDepth = 2;
// int i = 1;
// t[0] = t0;
// f[0] = stack[0].Left().F;
// I[0] = 0.0;
// adaptiveIndex = 0;
// while( i > 0 )
// {
// reachedMaxRecursion |= (i == maxRecursion-1);
// if( stack[i].Mid().IsUninitialized() )
// {
// bool needToSubdivide = false;
// stack[i].CalculateMidpointT();
// stack[i].Mid().Evaluate(transferFunction, channel,
// fieldFunction);
// if( i < minimumDepth )
// {
// needToSubdivide = true;
// }
// else
// {
// T I0 = stack[i].GetH()/MAKE_FLOAT(2.0) *
// (stack[i].Left().F + stack[i].Right().F);
// T I1 = stack[i].GetH()/MAKE_FLOAT(4.0) *
// (stack[i].Left().F + 2.0*stack[i].Mid().F +
// stack[i].Right().F);
// T localEpsilon =
// globalEpsilon*globalIntegralEstimate *
// (stack[i].GetH()/stack[0].GetH());
// if( traceEnabled )
// {
// printf("Level %d, Interval (%f, %f, %f),
// values (%f, %f, %f) I0 = %f, I1 = %f,
// localEpsilon = %f\n", i,
// stack[i].Left().TVal, stack[i].Mid().TVal,
// stack[i].Right().TVal,
// stack[i].Left().F, stack[i].Mid().F,
// stack[i].Right().F, I0, I1,
// localEpsilon);
// }
// ElVisFloat h = stack[i].GetH()/MAKE_FLOAT(2.0);
// if( stack[i].Left().F == MAKE_FLOAT(0.0) &&
// stack[i].Mid().F == MAKE_FLOAT(0.0) &&
// stack[i].Right().F == MAKE_FLOAT(0.0) )
// {
// ElVis::Interval<ElVisFloat> range =
// fieldFunction.EstimateRange(stack[i].Left().TVal,
// stack[i].Right().TVal);
// ElVisFloat maxValue =
// transferFunction->GetMaxValue(channel,
// range);
// T maxSegmentError =
// (maxFunctionValue*h)/globalIntegralEstimate;
// T updatedSegmentError =
// (maxValue*h)/globalIntegralEstimate;
// if( traceEnabled )
// {
// printf("All 3 values are 0. Scalar
// range is (%f, %f), maxSegmentError %f,
// updatedSegmentError %f\n",
// range.GetLow(), range.GetHigh(),
// maxSegmentError,
// updatedSegmentError);
// }
// if( updatedSegmentError > localEpsilon && i
// < maxRecursion-1 )
// {
// needToSubdivide = true;
// }
// }
// else if( stack[i].Left().F == MAKE_FLOAT(0.0) ||
// stack[i].Mid().F == MAKE_FLOAT(0.0) ||
// stack[i].Right().F == MAKE_FLOAT(0.0) )
// {
// // If any of the samples are 0, then we know
// there is a breakpoint somewhere and we
// should subdivide.
// T maxSegmentError =
// (maxFunctionValue*h)/globalIntegralEstimate;
// ElVis::Interval<ElVisFloat> range =
// fieldFunction.EstimateRange(stack[i].Left().TVal,
// stack[i].Right().TVal);
// ElVisFloat maxValue =
// transferFunction->GetMaxValue(channel,
// range);
// T updatedSegmentError =
// (maxValue*h)/globalIntegralEstimate;
// if( traceEnabled )
// {
// printf("At least one value is 0. Scalar
// range is (%f, %f), maxSegmentError %f,
// updatedSegmentError %f\n",
// range.GetLow(), range.GetHigh(),
// maxSegmentError,
// updatedSegmentError);
// }
// if( traceEnabled )
// {
// printf("One of the samples is 0,
// maxSegmentError = %f, localEpsilon =
// %f\n", maxSegmentError, localEpsilon);
// }
// if(updatedSegmentError > localEpsilon && i <
// maxRecursion-1 )
// {
// needToSubdivide = true;
// }
// }
// else
// {
// T errorEstimate =
// fabs(I0-I1)/globalIntegralEstimate;
// if( traceEnabled )
// {
// printf("No samples 0, errorEstimate =
// %f, localEpsilon = %f\n", errorEstimate,
// localEpsilon);
// }
// if( errorEstimate > localEpsilon && i <
// maxRecursion-1 )
// {
// needToSubdivide = true;
// }
// }
// }
// if( traceEnabled )
// {
// printf("Subdividing = %d\n", needToSubdivide? 1
// : 0);
// }
// if( needToSubdivide )
// {
// stack[i+1].Left() = stack[i].Left();
// stack[i+1].Mid().Reset();
// stack[i+1].Right() = stack[i].Mid();
// i = i + 1;
// }
// else
// {
// T prevValue = I[adaptiveIndex];
// T h = stack[i].GetH()/MAKE_FLOAT(4.0);
// T mid_f = stack[i].Mid().F;
// T right_f = stack[i].Right().F;
// t[adaptiveIndex+1] = stack[i].Mid().TVal;
// t[adaptiveIndex+2] = stack[i].Right().TVal;
// f[adaptiveIndex+1] = mid_f;
// f[adaptiveIndex+2] = right_f;
// T leftContribution = h * (stack[i].Left().F +
// mid_f);
// T rightContribution = h * (mid_f + right_f);
// I[adaptiveIndex+1] = prevValue +
// leftContribution;
// I[adaptiveIndex+2] = prevValue +
// leftContribution+rightContribution;
// if( traceEnabled )
// {
// printf("Integral Value at %f = %f\n",
// t[adaptiveIndex+1], I[adaptiveIndex+1]);
// printf("Integral Value at %f = %f\n",
// t[adaptiveIndex+2], I[adaptiveIndex+2]);
// }
// adaptiveIndex += 2;
// }
// }
// else
// {
// if( stack[i].Right().TVal == stack[i-1].Mid().TVal )
// {
// // We just finished traversing the left side,
// now go to
// // the right.
// stack[i].Left() = stack[i-1].Mid();
// stack[i].Mid().Reset();
// stack[i].Right() = stack[i-1].Right();
// }
// else
// {
// // We finished this branch. Remove it and go up
// to
// // the next one.
// i = i-1;
// }
// }
// }
// }
// __device__ T SampleInnerIntegral(T t_i, T sample,
// TransferFunctionChannel channel, const TransferFunction*
// densityFunc) const
// {
// if( t_i < t[0] ||
// t_i > t[adaptiveIndex] )
// {
// return MAKE_FLOAT(0.0);
// }
// if( t_i == t[0] ) return MAKE_FLOAT(0.0);
// if( t_i == t[adaptiveIndex] ) return I[adaptiveIndex];
// const T* a = &(t[0]);
// const T* b = &(t[adaptiveIndex]);
// while(b-a > 1 )
// {
// const T* mid = (b-a)/2 + a;
// if( *mid == t_i )
// {
// return I[mid-a];
// }
// if( t_i < *mid )
// {
// b = mid;
// }
// else
// {
// a = mid;
// }
// }
// T baseline = I[a-t];
// T segment = (t_i-*a)/MAKE_FLOAT(2.0) * ( f[a-t] +
// densityFunc->Sample(channel, sample));
// return baseline+segment;
// }
// __device__ T OverallValue() const
// {
// return I[adaptiveIndex];
// }
// static const unsigned int arraySize = (0x01 << n) + 1;
// T t[arraySize];
// T f[arraySize];
// T I[arraySize];
// private:
// unsigned int adaptiveIndex;
// };
}
#endif | ///////////////////////////////////////////////////////////////////////////////
//
// The MIT License
//
// Copyright (c) 2006 Scientific Computing and Imaging Institute,
// University of Utah (USA)
//
// License for the specific language governing rights and limitations under
// Permission is hereby granted, free of charge, to any person obtaining a
// copy of this software and associated documentation files (the "Software"),
// to deal in the Software without restriction, including without limitation
// the rights to use, copy, modify, merge, publish, distribute, sublicense,
// and/or sell copies of the Software, and to permit persons to whom the
// Software is furnished to do so, subject to the following conditions:
//
// The above copyright notice and this permission notice shall be included
// in all copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
// OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
// THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
// FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
// DEALINGS IN THE SOFTWARE.
//
///////////////////////////////////////////////////////////////////////////////
#ifndef ELVIS_CORE_INNER_INTEGRAL_ADAPTIVE_TRAPEZOIDAL_CU
#define ELVIS_CORE_INNER_INTEGRAL_ADAPTIVE_TRAPEZOIDAL_CU
namespace ElVis
{
// /// Adaptive trapezoidal integration using a runtime stack to handle
// recursion.
// /// Value are kept for subsequent sampling.
// template<typename T, unsigned int n>
// struct InnerIntegralAdaptiveTrapezoidal
// {
// public:
// struct StackPoint
// {
// template<typename FieldFunc>
// __device__
// void Evaluate(const TransferFunction* densityFunc,
// TransferFunctionChannel channel,
// const FieldFunc& fieldFunc)
// {
// T s = fieldFunc(TVal);
// F = densityFunc->Sample(channel, s);
// }
// __device__ void Reset()
// {
// TVal = MAKE_FLOAT(1e30);
// }
// __device__ bool IsUninitialized() const
// {
// return TVal == MAKE_FLOAT(1e30);
// }
// __device__ StackPoint& operator=(const StackPoint& rhs)
// {
// TVal = rhs.TVal;
// F = rhs.F;
// return *this;
// }
// T TVal;
// T F;
// };
// struct StackEntry
// {
// __device__ void CalculateMidpointT()
// {
// Mid().TVal = Left().TVal + (Right().TVal -
// Left().TVal)/2.0;
// }
// __device__ void SetT(const T& t0, const T& t1)
// {
// Left().TVal = t0;
// Right().TVal = t1;
// CalculateMidpointT();
// }
// __device__ T GetH() const
// {
// return Right().TVal - Left().TVal;
// }
// template<typename FieldFunc>
// __device__ void EvaluateAll(const TransferFunction*
// densityFunc,
// TransferFunctionChannel channel,
// const FieldFunc& fieldFunc)
// {
// for(unsigned int i = 0; i < 3; ++i)
// {
// points[i].Evaluate(densityFunc, channel, fieldFunc);
// }
// }
// __device__ StackPoint& Left() { return points[0]; }
// __device__ StackPoint& Mid() { return points[1]; }
// __device__ StackPoint& Right() { return points[2]; }
// __device__ const StackPoint& Left() const { return
// points[0]; }
// __device__ const StackPoint& Mid() const { return
// points[1]; }
// __device__ const StackPoint& Right() const { return
// points[2]; }
// StackPoint points[3];
// };
// template<typename FieldFunctionType>
// __device__ void Integrate(const T& t0, const T& t1, const
// TransferFunction* transferFunction,
// TransferFunctionChannel channel,
// const FieldFunctionType& fieldFunction, const T&
// globalEpsilon,
// const T& globalIntegralEstimate,
// const T& maxFunctionValue, bool&
// reachedMaxRecursion,
// bool traceEnabled)
// {
// if( traceEnabled )
// {
// printf("Global Epsilon %f, globalIntegralEstimate %f,
// maxValue %f\n", globalEpsilon, globalIntegralEstimate,
// maxFunctionValue);
// }
// const unsigned int maxRecursion = n;
// reachedMaxRecursion = false;
// StackEntry stack[maxRecursion];
// stack[0].SetT(t0, t1);
// stack[0].EvaluateAll(transferFunction, channel,
// fieldFunction);
// stack[1].Left() = stack[0].Left();
// stack[1].Mid().Reset();
// stack[1].Right() = stack[0].Mid();
// unsigned int minimumDepth = 2;
// int i = 1;
// t[0] = t0;
// f[0] = stack[0].Left().F;
// I[0] = 0.0;
// adaptiveIndex = 0;
// while( i > 0 )
// {
// reachedMaxRecursion |= (i == maxRecursion-1);
// if( stack[i].Mid().IsUninitialized() )
// {
// bool needToSubdivide = false;
// stack[i].CalculateMidpointT();
// stack[i].Mid().Evaluate(transferFunction, channel,
// fieldFunction);
// if( i < minimumDepth )
// {
// needToSubdivide = true;
// }
// else
// {
// T I0 = stack[i].GetH()/MAKE_FLOAT(2.0) *
// (stack[i].Left().F + stack[i].Right().F);
// T I1 = stack[i].GetH()/MAKE_FLOAT(4.0) *
// (stack[i].Left().F + 2.0*stack[i].Mid().F +
// stack[i].Right().F);
// T localEpsilon =
// globalEpsilon*globalIntegralEstimate *
// (stack[i].GetH()/stack[0].GetH());
// if( traceEnabled )
// {
// printf("Level %d, Interval (%f, %f, %f),
// values (%f, %f, %f) I0 = %f, I1 = %f,
// localEpsilon = %f\n", i,
// stack[i].Left().TVal, stack[i].Mid().TVal,
// stack[i].Right().TVal,
// stack[i].Left().F, stack[i].Mid().F,
// stack[i].Right().F, I0, I1,
// localEpsilon);
// }
// ElVisFloat h = stack[i].GetH()/MAKE_FLOAT(2.0);
// if( stack[i].Left().F == MAKE_FLOAT(0.0) &&
// stack[i].Mid().F == MAKE_FLOAT(0.0) &&
// stack[i].Right().F == MAKE_FLOAT(0.0) )
// {
// ElVis::Interval<ElVisFloat> range =
// fieldFunction.EstimateRange(stack[i].Left().TVal,
// stack[i].Right().TVal);
// ElVisFloat maxValue =
// transferFunction->GetMaxValue(channel,
// range);
// T maxSegmentError =
// (maxFunctionValue*h)/globalIntegralEstimate;
// T updatedSegmentError =
// (maxValue*h)/globalIntegralEstimate;
// if( traceEnabled )
// {
// printf("All 3 values are 0. Scalar
// range is (%f, %f), maxSegmentError %f,
// updatedSegmentError %f\n",
// range.GetLow(), range.GetHigh(),
// maxSegmentError,
// updatedSegmentError);
// }
// if( updatedSegmentError > localEpsilon && i
// < maxRecursion-1 )
// {
// needToSubdivide = true;
// }
// }
// else if( stack[i].Left().F == MAKE_FLOAT(0.0) ||
// stack[i].Mid().F == MAKE_FLOAT(0.0) ||
// stack[i].Right().F == MAKE_FLOAT(0.0) )
// {
// // If any of the samples are 0, then we know
// there is a breakpoint somewhere and we
// should subdivide.
// T maxSegmentError =
// (maxFunctionValue*h)/globalIntegralEstimate;
// ElVis::Interval<ElVisFloat> range =
// fieldFunction.EstimateRange(stack[i].Left().TVal,
// stack[i].Right().TVal);
// ElVisFloat maxValue =
// transferFunction->GetMaxValue(channel,
// range);
// T updatedSegmentError =
// (maxValue*h)/globalIntegralEstimate;
// if( traceEnabled )
// {
// printf("At least one value is 0. Scalar
// range is (%f, %f), maxSegmentError %f,
// updatedSegmentError %f\n",
// range.GetLow(), range.GetHigh(),
// maxSegmentError,
// updatedSegmentError);
// }
// if( traceEnabled )
// {
// printf("One of the samples is 0,
// maxSegmentError = %f, localEpsilon =
// %f\n", maxSegmentError, localEpsilon);
// }
// if(updatedSegmentError > localEpsilon && i <
// maxRecursion-1 )
// {
// needToSubdivide = true;
// }
// }
// else
// {
// T errorEstimate =
// fabs(I0-I1)/globalIntegralEstimate;
// if( traceEnabled )
// {
// printf("No samples 0, errorEstimate =
// %f, localEpsilon = %f\n", errorEstimate,
// localEpsilon);
// }
// if( errorEstimate > localEpsilon && i <
// maxRecursion-1 )
// {
// needToSubdivide = true;
// }
// }
// }
// if( traceEnabled )
// {
// printf("Subdividing = %d\n", needToSubdivide? 1
// : 0);
// }
// if( needToSubdivide )
// {
// stack[i+1].Left() = stack[i].Left();
// stack[i+1].Mid().Reset();
// stack[i+1].Right() = stack[i].Mid();
// i = i + 1;
// }
// else
// {
// T prevValue = I[adaptiveIndex];
// T h = stack[i].GetH()/MAKE_FLOAT(4.0);
// T mid_f = stack[i].Mid().F;
// T right_f = stack[i].Right().F;
// t[adaptiveIndex+1] = stack[i].Mid().TVal;
// t[adaptiveIndex+2] = stack[i].Right().TVal;
// f[adaptiveIndex+1] = mid_f;
// f[adaptiveIndex+2] = right_f;
// T leftContribution = h * (stack[i].Left().F +
// mid_f);
// T rightContribution = h * (mid_f + right_f);
// I[adaptiveIndex+1] = prevValue +
// leftContribution;
// I[adaptiveIndex+2] = prevValue +
// leftContribution+rightContribution;
// if( traceEnabled )
// {
// printf("Integral Value at %f = %f\n",
// t[adaptiveIndex+1], I[adaptiveIndex+1]);
// printf("Integral Value at %f = %f\n",
// t[adaptiveIndex+2], I[adaptiveIndex+2]);
// }
// adaptiveIndex += 2;
// }
// }
// else
// {
// if( stack[i].Right().TVal == stack[i-1].Mid().TVal )
// {
// // We just finished traversing the left side,
// now go to
// // the right.
// stack[i].Left() = stack[i-1].Mid();
// stack[i].Mid().Reset();
// stack[i].Right() = stack[i-1].Right();
// }
// else
// {
// // We finished this branch. Remove it and go up
// to
// // the next one.
// i = i-1;
// }
// }
// }
// }
// __device__ T SampleInnerIntegral(T t_i, T sample,
// TransferFunctionChannel channel, const TransferFunction*
// densityFunc) const
// {
// if( t_i < t[0] ||
// t_i > t[adaptiveIndex] )
// {
// return MAKE_FLOAT(0.0);
// }
// if( t_i == t[0] ) return MAKE_FLOAT(0.0);
// if( t_i == t[adaptiveIndex] ) return I[adaptiveIndex];
// const T* a = &(t[0]);
// const T* b = &(t[adaptiveIndex]);
// while(b-a > 1 )
// {
// const T* mid = (b-a)/2 + a;
// if( *mid == t_i )
// {
// return I[mid-a];
// }
// if( t_i < *mid )
// {
// b = mid;
// }
// else
// {
// a = mid;
// }
// }
// T baseline = I[a-t];
// T segment = (t_i-*a)/MAKE_FLOAT(2.0) * ( f[a-t] +
// densityFunc->Sample(channel, sample));
// return baseline+segment;
// }
// __device__ T OverallValue() const
// {
// return I[adaptiveIndex];
// }
// static const unsigned int arraySize = (0x01 << n) + 1;
// T t[arraySize];
// T f[arraySize];
// T I[arraySize];
// private:
// unsigned int adaptiveIndex;
// };
}
#endif |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | ///////////////////////////////////////////////////////////////////////////////
//
// The MIT License
//
// Copyright (c) 2006 Scientific Computing and Imaging Institute,
// University of Utah (USA)
//
// License for the specific language governing rights and limitations under
// Permission is hereby granted, free of charge, to any person obtaining a
// copy of this software and associated documentation files (the "Software"),
// to deal in the Software without restriction, including without limitation
// the rights to use, copy, modify, merge, publish, distribute, sublicense,
// and/or sell copies of the Software, and to permit persons to whom the
// Software is furnished to do so, subject to the following conditions:
//
// The above copyright notice and this permission notice shall be included
// in all copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
// OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
// THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
// FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
// DEALINGS IN THE SOFTWARE.
//
///////////////////////////////////////////////////////////////////////////////
#ifndef ELVIS_CORE_INNER_INTEGRAL_ADAPTIVE_TRAPEZOIDAL_CU
#define ELVIS_CORE_INNER_INTEGRAL_ADAPTIVE_TRAPEZOIDAL_CU
namespace ElVis
{
// /// Adaptive trapezoidal integration using a runtime stack to handle
// recursion.
// /// Value are kept for subsequent sampling.
// template<typename T, unsigned int n>
// struct InnerIntegralAdaptiveTrapezoidal
// {
// public:
// struct StackPoint
// {
// template<typename FieldFunc>
// __device__
// void Evaluate(const TransferFunction* densityFunc,
// TransferFunctionChannel channel,
// const FieldFunc& fieldFunc)
// {
// T s = fieldFunc(TVal);
// F = densityFunc->Sample(channel, s);
// }
// __device__ void Reset()
// {
// TVal = MAKE_FLOAT(1e30);
// }
// __device__ bool IsUninitialized() const
// {
// return TVal == MAKE_FLOAT(1e30);
// }
// __device__ StackPoint& operator=(const StackPoint& rhs)
// {
// TVal = rhs.TVal;
// F = rhs.F;
// return *this;
// }
// T TVal;
// T F;
// };
// struct StackEntry
// {
// __device__ void CalculateMidpointT()
// {
// Mid().TVal = Left().TVal + (Right().TVal -
// Left().TVal)/2.0;
// }
// __device__ void SetT(const T& t0, const T& t1)
// {
// Left().TVal = t0;
// Right().TVal = t1;
// CalculateMidpointT();
// }
// __device__ T GetH() const
// {
// return Right().TVal - Left().TVal;
// }
// template<typename FieldFunc>
// __device__ void EvaluateAll(const TransferFunction*
// densityFunc,
// TransferFunctionChannel channel,
// const FieldFunc& fieldFunc)
// {
// for(unsigned int i = 0; i < 3; ++i)
// {
// points[i].Evaluate(densityFunc, channel, fieldFunc);
// }
// }
// __device__ StackPoint& Left() { return points[0]; }
// __device__ StackPoint& Mid() { return points[1]; }
// __device__ StackPoint& Right() { return points[2]; }
// __device__ const StackPoint& Left() const { return
// points[0]; }
// __device__ const StackPoint& Mid() const { return
// points[1]; }
// __device__ const StackPoint& Right() const { return
// points[2]; }
// StackPoint points[3];
// };
// template<typename FieldFunctionType>
// __device__ void Integrate(const T& t0, const T& t1, const
// TransferFunction* transferFunction,
// TransferFunctionChannel channel,
// const FieldFunctionType& fieldFunction, const T&
// globalEpsilon,
// const T& globalIntegralEstimate,
// const T& maxFunctionValue, bool&
// reachedMaxRecursion,
// bool traceEnabled)
// {
// if( traceEnabled )
// {
// printf("Global Epsilon %f, globalIntegralEstimate %f,
// maxValue %f\n", globalEpsilon, globalIntegralEstimate,
// maxFunctionValue);
// }
// const unsigned int maxRecursion = n;
// reachedMaxRecursion = false;
// StackEntry stack[maxRecursion];
// stack[0].SetT(t0, t1);
// stack[0].EvaluateAll(transferFunction, channel,
// fieldFunction);
// stack[1].Left() = stack[0].Left();
// stack[1].Mid().Reset();
// stack[1].Right() = stack[0].Mid();
// unsigned int minimumDepth = 2;
// int i = 1;
// t[0] = t0;
// f[0] = stack[0].Left().F;
// I[0] = 0.0;
// adaptiveIndex = 0;
// while( i > 0 )
// {
// reachedMaxRecursion |= (i == maxRecursion-1);
// if( stack[i].Mid().IsUninitialized() )
// {
// bool needToSubdivide = false;
// stack[i].CalculateMidpointT();
// stack[i].Mid().Evaluate(transferFunction, channel,
// fieldFunction);
// if( i < minimumDepth )
// {
// needToSubdivide = true;
// }
// else
// {
// T I0 = stack[i].GetH()/MAKE_FLOAT(2.0) *
// (stack[i].Left().F + stack[i].Right().F);
// T I1 = stack[i].GetH()/MAKE_FLOAT(4.0) *
// (stack[i].Left().F + 2.0*stack[i].Mid().F +
// stack[i].Right().F);
// T localEpsilon =
// globalEpsilon*globalIntegralEstimate *
// (stack[i].GetH()/stack[0].GetH());
// if( traceEnabled )
// {
// printf("Level %d, Interval (%f, %f, %f),
// values (%f, %f, %f) I0 = %f, I1 = %f,
// localEpsilon = %f\n", i,
// stack[i].Left().TVal, stack[i].Mid().TVal,
// stack[i].Right().TVal,
// stack[i].Left().F, stack[i].Mid().F,
// stack[i].Right().F, I0, I1,
// localEpsilon);
// }
// ElVisFloat h = stack[i].GetH()/MAKE_FLOAT(2.0);
// if( stack[i].Left().F == MAKE_FLOAT(0.0) &&
// stack[i].Mid().F == MAKE_FLOAT(0.0) &&
// stack[i].Right().F == MAKE_FLOAT(0.0) )
// {
// ElVis::Interval<ElVisFloat> range =
// fieldFunction.EstimateRange(stack[i].Left().TVal,
// stack[i].Right().TVal);
// ElVisFloat maxValue =
// transferFunction->GetMaxValue(channel,
// range);
// T maxSegmentError =
// (maxFunctionValue*h)/globalIntegralEstimate;
// T updatedSegmentError =
// (maxValue*h)/globalIntegralEstimate;
// if( traceEnabled )
// {
// printf("All 3 values are 0. Scalar
// range is (%f, %f), maxSegmentError %f,
// updatedSegmentError %f\n",
// range.GetLow(), range.GetHigh(),
// maxSegmentError,
// updatedSegmentError);
// }
// if( updatedSegmentError > localEpsilon && i
// < maxRecursion-1 )
// {
// needToSubdivide = true;
// }
// }
// else if( stack[i].Left().F == MAKE_FLOAT(0.0) ||
// stack[i].Mid().F == MAKE_FLOAT(0.0) ||
// stack[i].Right().F == MAKE_FLOAT(0.0) )
// {
// // If any of the samples are 0, then we know
// there is a breakpoint somewhere and we
// should subdivide.
// T maxSegmentError =
// (maxFunctionValue*h)/globalIntegralEstimate;
// ElVis::Interval<ElVisFloat> range =
// fieldFunction.EstimateRange(stack[i].Left().TVal,
// stack[i].Right().TVal);
// ElVisFloat maxValue =
// transferFunction->GetMaxValue(channel,
// range);
// T updatedSegmentError =
// (maxValue*h)/globalIntegralEstimate;
// if( traceEnabled )
// {
// printf("At least one value is 0. Scalar
// range is (%f, %f), maxSegmentError %f,
// updatedSegmentError %f\n",
// range.GetLow(), range.GetHigh(),
// maxSegmentError,
// updatedSegmentError);
// }
// if( traceEnabled )
// {
// printf("One of the samples is 0,
// maxSegmentError = %f, localEpsilon =
// %f\n", maxSegmentError, localEpsilon);
// }
// if(updatedSegmentError > localEpsilon && i <
// maxRecursion-1 )
// {
// needToSubdivide = true;
// }
// }
// else
// {
// T errorEstimate =
// fabs(I0-I1)/globalIntegralEstimate;
// if( traceEnabled )
// {
// printf("No samples 0, errorEstimate =
// %f, localEpsilon = %f\n", errorEstimate,
// localEpsilon);
// }
// if( errorEstimate > localEpsilon && i <
// maxRecursion-1 )
// {
// needToSubdivide = true;
// }
// }
// }
// if( traceEnabled )
// {
// printf("Subdividing = %d\n", needToSubdivide? 1
// : 0);
// }
// if( needToSubdivide )
// {
// stack[i+1].Left() = stack[i].Left();
// stack[i+1].Mid().Reset();
// stack[i+1].Right() = stack[i].Mid();
// i = i + 1;
// }
// else
// {
// T prevValue = I[adaptiveIndex];
// T h = stack[i].GetH()/MAKE_FLOAT(4.0);
// T mid_f = stack[i].Mid().F;
// T right_f = stack[i].Right().F;
// t[adaptiveIndex+1] = stack[i].Mid().TVal;
// t[adaptiveIndex+2] = stack[i].Right().TVal;
// f[adaptiveIndex+1] = mid_f;
// f[adaptiveIndex+2] = right_f;
// T leftContribution = h * (stack[i].Left().F +
// mid_f);
// T rightContribution = h * (mid_f + right_f);
// I[adaptiveIndex+1] = prevValue +
// leftContribution;
// I[adaptiveIndex+2] = prevValue +
// leftContribution+rightContribution;
// if( traceEnabled )
// {
// printf("Integral Value at %f = %f\n",
// t[adaptiveIndex+1], I[adaptiveIndex+1]);
// printf("Integral Value at %f = %f\n",
// t[adaptiveIndex+2], I[adaptiveIndex+2]);
// }
// adaptiveIndex += 2;
// }
// }
// else
// {
// if( stack[i].Right().TVal == stack[i-1].Mid().TVal )
// {
// // We just finished traversing the left side,
// now go to
// // the right.
// stack[i].Left() = stack[i-1].Mid();
// stack[i].Mid().Reset();
// stack[i].Right() = stack[i-1].Right();
// }
// else
// {
// // We finished this branch. Remove it and go up
// to
// // the next one.
// i = i-1;
// }
// }
// }
// }
// __device__ T SampleInnerIntegral(T t_i, T sample,
// TransferFunctionChannel channel, const TransferFunction*
// densityFunc) const
// {
// if( t_i < t[0] ||
// t_i > t[adaptiveIndex] )
// {
// return MAKE_FLOAT(0.0);
// }
// if( t_i == t[0] ) return MAKE_FLOAT(0.0);
// if( t_i == t[adaptiveIndex] ) return I[adaptiveIndex];
// const T* a = &(t[0]);
// const T* b = &(t[adaptiveIndex]);
// while(b-a > 1 )
// {
// const T* mid = (b-a)/2 + a;
// if( *mid == t_i )
// {
// return I[mid-a];
// }
// if( t_i < *mid )
// {
// b = mid;
// }
// else
// {
// a = mid;
// }
// }
// T baseline = I[a-t];
// T segment = (t_i-*a)/MAKE_FLOAT(2.0) * ( f[a-t] +
// densityFunc->Sample(channel, sample));
// return baseline+segment;
// }
// __device__ T OverallValue() const
// {
// return I[adaptiveIndex];
// }
// static const unsigned int arraySize = (0x01 << n) + 1;
// T t[arraySize];
// T f[arraySize];
// T I[arraySize];
// private:
// unsigned int adaptiveIndex;
// };
}
#endif | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | ///////////////////////////////////////////////////////////////////////////////
//
// The MIT License
//
// Copyright (c) 2006 Scientific Computing and Imaging Institute,
// University of Utah (USA)
//
// License for the specific language governing rights and limitations under
// Permission is hereby granted, free of charge, to any person obtaining a
// copy of this software and associated documentation files (the "Software"),
// to deal in the Software without restriction, including without limitation
// the rights to use, copy, modify, merge, publish, distribute, sublicense,
// and/or sell copies of the Software, and to permit persons to whom the
// Software is furnished to do so, subject to the following conditions:
//
// The above copyright notice and this permission notice shall be included
// in all copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
// OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
// THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
// FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
// DEALINGS IN THE SOFTWARE.
//
///////////////////////////////////////////////////////////////////////////////
#ifndef ELVIS_CORE_INNER_INTEGRAL_ADAPTIVE_TRAPEZOIDAL_CU
#define ELVIS_CORE_INNER_INTEGRAL_ADAPTIVE_TRAPEZOIDAL_CU
namespace ElVis
{
// /// Adaptive trapezoidal integration using a runtime stack to handle
// recursion.
// /// Value are kept for subsequent sampling.
// template<typename T, unsigned int n>
// struct InnerIntegralAdaptiveTrapezoidal
// {
// public:
// struct StackPoint
// {
// template<typename FieldFunc>
// __device__
// void Evaluate(const TransferFunction* densityFunc,
// TransferFunctionChannel channel,
// const FieldFunc& fieldFunc)
// {
// T s = fieldFunc(TVal);
// F = densityFunc->Sample(channel, s);
// }
// __device__ void Reset()
// {
// TVal = MAKE_FLOAT(1e30);
// }
// __device__ bool IsUninitialized() const
// {
// return TVal == MAKE_FLOAT(1e30);
// }
// __device__ StackPoint& operator=(const StackPoint& rhs)
// {
// TVal = rhs.TVal;
// F = rhs.F;
// return *this;
// }
// T TVal;
// T F;
// };
// struct StackEntry
// {
// __device__ void CalculateMidpointT()
// {
// Mid().TVal = Left().TVal + (Right().TVal -
// Left().TVal)/2.0;
// }
// __device__ void SetT(const T& t0, const T& t1)
// {
// Left().TVal = t0;
// Right().TVal = t1;
// CalculateMidpointT();
// }
// __device__ T GetH() const
// {
// return Right().TVal - Left().TVal;
// }
// template<typename FieldFunc>
// __device__ void EvaluateAll(const TransferFunction*
// densityFunc,
// TransferFunctionChannel channel,
// const FieldFunc& fieldFunc)
// {
// for(unsigned int i = 0; i < 3; ++i)
// {
// points[i].Evaluate(densityFunc, channel, fieldFunc);
// }
// }
// __device__ StackPoint& Left() { return points[0]; }
// __device__ StackPoint& Mid() { return points[1]; }
// __device__ StackPoint& Right() { return points[2]; }
// __device__ const StackPoint& Left() const { return
// points[0]; }
// __device__ const StackPoint& Mid() const { return
// points[1]; }
// __device__ const StackPoint& Right() const { return
// points[2]; }
// StackPoint points[3];
// };
// template<typename FieldFunctionType>
// __device__ void Integrate(const T& t0, const T& t1, const
// TransferFunction* transferFunction,
// TransferFunctionChannel channel,
// const FieldFunctionType& fieldFunction, const T&
// globalEpsilon,
// const T& globalIntegralEstimate,
// const T& maxFunctionValue, bool&
// reachedMaxRecursion,
// bool traceEnabled)
// {
// if( traceEnabled )
// {
// printf("Global Epsilon %f, globalIntegralEstimate %f,
// maxValue %f\n", globalEpsilon, globalIntegralEstimate,
// maxFunctionValue);
// }
// const unsigned int maxRecursion = n;
// reachedMaxRecursion = false;
// StackEntry stack[maxRecursion];
// stack[0].SetT(t0, t1);
// stack[0].EvaluateAll(transferFunction, channel,
// fieldFunction);
// stack[1].Left() = stack[0].Left();
// stack[1].Mid().Reset();
// stack[1].Right() = stack[0].Mid();
// unsigned int minimumDepth = 2;
// int i = 1;
// t[0] = t0;
// f[0] = stack[0].Left().F;
// I[0] = 0.0;
// adaptiveIndex = 0;
// while( i > 0 )
// {
// reachedMaxRecursion |= (i == maxRecursion-1);
// if( stack[i].Mid().IsUninitialized() )
// {
// bool needToSubdivide = false;
// stack[i].CalculateMidpointT();
// stack[i].Mid().Evaluate(transferFunction, channel,
// fieldFunction);
// if( i < minimumDepth )
// {
// needToSubdivide = true;
// }
// else
// {
// T I0 = stack[i].GetH()/MAKE_FLOAT(2.0) *
// (stack[i].Left().F + stack[i].Right().F);
// T I1 = stack[i].GetH()/MAKE_FLOAT(4.0) *
// (stack[i].Left().F + 2.0*stack[i].Mid().F +
// stack[i].Right().F);
// T localEpsilon =
// globalEpsilon*globalIntegralEstimate *
// (stack[i].GetH()/stack[0].GetH());
// if( traceEnabled )
// {
// printf("Level %d, Interval (%f, %f, %f),
// values (%f, %f, %f) I0 = %f, I1 = %f,
// localEpsilon = %f\n", i,
// stack[i].Left().TVal, stack[i].Mid().TVal,
// stack[i].Right().TVal,
// stack[i].Left().F, stack[i].Mid().F,
// stack[i].Right().F, I0, I1,
// localEpsilon);
// }
// ElVisFloat h = stack[i].GetH()/MAKE_FLOAT(2.0);
// if( stack[i].Left().F == MAKE_FLOAT(0.0) &&
// stack[i].Mid().F == MAKE_FLOAT(0.0) &&
// stack[i].Right().F == MAKE_FLOAT(0.0) )
// {
// ElVis::Interval<ElVisFloat> range =
// fieldFunction.EstimateRange(stack[i].Left().TVal,
// stack[i].Right().TVal);
// ElVisFloat maxValue =
// transferFunction->GetMaxValue(channel,
// range);
// T maxSegmentError =
// (maxFunctionValue*h)/globalIntegralEstimate;
// T updatedSegmentError =
// (maxValue*h)/globalIntegralEstimate;
// if( traceEnabled )
// {
// printf("All 3 values are 0. Scalar
// range is (%f, %f), maxSegmentError %f,
// updatedSegmentError %f\n",
// range.GetLow(), range.GetHigh(),
// maxSegmentError,
// updatedSegmentError);
// }
// if( updatedSegmentError > localEpsilon && i
// < maxRecursion-1 )
// {
// needToSubdivide = true;
// }
// }
// else if( stack[i].Left().F == MAKE_FLOAT(0.0) ||
// stack[i].Mid().F == MAKE_FLOAT(0.0) ||
// stack[i].Right().F == MAKE_FLOAT(0.0) )
// {
// // If any of the samples are 0, then we know
// there is a breakpoint somewhere and we
// should subdivide.
// T maxSegmentError =
// (maxFunctionValue*h)/globalIntegralEstimate;
// ElVis::Interval<ElVisFloat> range =
// fieldFunction.EstimateRange(stack[i].Left().TVal,
// stack[i].Right().TVal);
// ElVisFloat maxValue =
// transferFunction->GetMaxValue(channel,
// range);
// T updatedSegmentError =
// (maxValue*h)/globalIntegralEstimate;
// if( traceEnabled )
// {
// printf("At least one value is 0. Scalar
// range is (%f, %f), maxSegmentError %f,
// updatedSegmentError %f\n",
// range.GetLow(), range.GetHigh(),
// maxSegmentError,
// updatedSegmentError);
// }
// if( traceEnabled )
// {
// printf("One of the samples is 0,
// maxSegmentError = %f, localEpsilon =
// %f\n", maxSegmentError, localEpsilon);
// }
// if(updatedSegmentError > localEpsilon && i <
// maxRecursion-1 )
// {
// needToSubdivide = true;
// }
// }
// else
// {
// T errorEstimate =
// fabs(I0-I1)/globalIntegralEstimate;
// if( traceEnabled )
// {
// printf("No samples 0, errorEstimate =
// %f, localEpsilon = %f\n", errorEstimate,
// localEpsilon);
// }
// if( errorEstimate > localEpsilon && i <
// maxRecursion-1 )
// {
// needToSubdivide = true;
// }
// }
// }
// if( traceEnabled )
// {
// printf("Subdividing = %d\n", needToSubdivide? 1
// : 0);
// }
// if( needToSubdivide )
// {
// stack[i+1].Left() = stack[i].Left();
// stack[i+1].Mid().Reset();
// stack[i+1].Right() = stack[i].Mid();
// i = i + 1;
// }
// else
// {
// T prevValue = I[adaptiveIndex];
// T h = stack[i].GetH()/MAKE_FLOAT(4.0);
// T mid_f = stack[i].Mid().F;
// T right_f = stack[i].Right().F;
// t[adaptiveIndex+1] = stack[i].Mid().TVal;
// t[adaptiveIndex+2] = stack[i].Right().TVal;
// f[adaptiveIndex+1] = mid_f;
// f[adaptiveIndex+2] = right_f;
// T leftContribution = h * (stack[i].Left().F +
// mid_f);
// T rightContribution = h * (mid_f + right_f);
// I[adaptiveIndex+1] = prevValue +
// leftContribution;
// I[adaptiveIndex+2] = prevValue +
// leftContribution+rightContribution;
// if( traceEnabled )
// {
// printf("Integral Value at %f = %f\n",
// t[adaptiveIndex+1], I[adaptiveIndex+1]);
// printf("Integral Value at %f = %f\n",
// t[adaptiveIndex+2], I[adaptiveIndex+2]);
// }
// adaptiveIndex += 2;
// }
// }
// else
// {
// if( stack[i].Right().TVal == stack[i-1].Mid().TVal )
// {
// // We just finished traversing the left side,
// now go to
// // the right.
// stack[i].Left() = stack[i-1].Mid();
// stack[i].Mid().Reset();
// stack[i].Right() = stack[i-1].Right();
// }
// else
// {
// // We finished this branch. Remove it and go up
// to
// // the next one.
// i = i-1;
// }
// }
// }
// }
// __device__ T SampleInnerIntegral(T t_i, T sample,
// TransferFunctionChannel channel, const TransferFunction*
// densityFunc) const
// {
// if( t_i < t[0] ||
// t_i > t[adaptiveIndex] )
// {
// return MAKE_FLOAT(0.0);
// }
// if( t_i == t[0] ) return MAKE_FLOAT(0.0);
// if( t_i == t[adaptiveIndex] ) return I[adaptiveIndex];
// const T* a = &(t[0]);
// const T* b = &(t[adaptiveIndex]);
// while(b-a > 1 )
// {
// const T* mid = (b-a)/2 + a;
// if( *mid == t_i )
// {
// return I[mid-a];
// }
// if( t_i < *mid )
// {
// b = mid;
// }
// else
// {
// a = mid;
// }
// }
// T baseline = I[a-t];
// T segment = (t_i-*a)/MAKE_FLOAT(2.0) * ( f[a-t] +
// densityFunc->Sample(channel, sample));
// return baseline+segment;
// }
// __device__ T OverallValue() const
// {
// return I[adaptiveIndex];
// }
// static const unsigned int arraySize = (0x01 << n) + 1;
// T t[arraySize];
// T f[arraySize];
// T I[arraySize];
// private:
// unsigned int adaptiveIndex;
// };
}
#endif | .text
.file "InnerIntegralAdaptiveTrapezoidal.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000e97f9_00000000-6_InnerIntegralAdaptiveTrapezoidal.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "InnerIntegralAdaptiveTrapezoidal.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /**
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership.
* The ASF licenses this file to You under the Apache License, Version 2.0
* (the "License"); you may not use this file except in compliance with
* the License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include <stdio.h>
__constant__ unsigned int shift1[4] = {6, 2, 13, 3};
__constant__ unsigned int shift2[4] = {13, 27, 21, 12};
__constant__ unsigned int shift3[4] = {18, 2, 7, 13};
__constant__ unsigned int offset[4] = {4294967294, 4294967288, 4294967280, 4294967168};
__shared__ unsigned int randStates[32];
__device__ unsigned int TausStep(unsigned int &z, int S1, int S2, int S3, unsigned int M) {
unsigned int b = (((z << S1) ^ z) >> S2);
return z = (((z &M) << S3) ^ b);
}
__device__ unsigned int randInt() {
TausStep(randStates[threadIdx.x&31], shift1[threadIdx.x&3], shift2[threadIdx.x&3],shift3[threadIdx.x&3],offset[threadIdx.x&3]);
return (randStates[(threadIdx.x)&31]^randStates[(threadIdx.x+1)&31]^randStates[(threadIdx.x+2)&31]^randStates[(threadIdx.x+3)&31]);
}
__global__ void sync_test(void) {
__shared__ int shared_int;
int count = 0;
long long timeout = 0;
if (threadIdx.x == 0) {
shared_int = 0;
}
__syncthreads();
if (threadIdx.x == 0) {
// occupy thread0
while (count < 100) {
for (int i=0; i<200; i++){
randInt();
}
if (++timeout > 1000000) {
break;
}
count++;
if (count > 50) {
count = 0;
}
}
shared_int = 1;
}
__syncthreads();
printf("%d\n", shared_int);
}
int main(void)
{
sync_test<<<1, 4>>>();
cudaDeviceSynchronize();
return 0;
}
/* prints:
1
1
1
1
*/ | .file "tmpxft_0007551d_00000000-6_sync_test2.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z8TausStepRjiiij
.type _Z8TausStepRjiiij, @function
_Z8TausStepRjiiij:
.LFB2057:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size _Z8TausStepRjiiij, .-_Z8TausStepRjiiij
.globl _Z7randIntv
.type _Z7randIntv, @function
_Z7randIntv:
.LFB2058:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2058:
.size _Z7randIntv, .-_Z7randIntv
.globl _Z27__device_stub__Z9sync_testvv
.type _Z27__device_stub__Z9sync_testvv, @function
_Z27__device_stub__Z9sync_testvv:
.LFB2084:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L11
.L7:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L12
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z9sync_testv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L7
.L12:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z27__device_stub__Z9sync_testvv, .-_Z27__device_stub__Z9sync_testvv
.globl _Z9sync_testv
.type _Z9sync_testv, @function
_Z9sync_testv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z27__device_stub__Z9sync_testvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z9sync_testv, .-_Z9sync_testv
.globl main
.type main, @function
main:
.LFB2059:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movl $4, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L18
.L16:
call cudaDeviceSynchronize@PLT
movl $0, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L18:
.cfi_restore_state
call _Z27__device_stub__Z9sync_testvv
jmp .L16
.cfi_endproc
.LFE2059:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z9sync_testv"
.LC1:
.string "shift1"
.LC2:
.string "shift2"
.LC3:
.string "shift3"
.LC4:
.string "offset"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z9sync_testv(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $16, %r9d
movl $0, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _ZL6shift1(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $16, %r9d
movl $0, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _ZL6shift2(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $16, %r9d
movl $0, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _ZL6shift3(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $16, %r9d
movl $0, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _ZL6offset(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL6offset
.comm _ZL6offset,16,16
.local _ZL6shift3
.comm _ZL6shift3,16,16
.local _ZL6shift2
.comm _ZL6shift2,16,16
.local _ZL6shift1
.comm _ZL6shift1,16,16
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /**
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership.
* The ASF licenses this file to You under the Apache License, Version 2.0
* (the "License"); you may not use this file except in compliance with
* the License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include <stdio.h>
__constant__ unsigned int shift1[4] = {6, 2, 13, 3};
__constant__ unsigned int shift2[4] = {13, 27, 21, 12};
__constant__ unsigned int shift3[4] = {18, 2, 7, 13};
__constant__ unsigned int offset[4] = {4294967294, 4294967288, 4294967280, 4294967168};
__shared__ unsigned int randStates[32];
__device__ unsigned int TausStep(unsigned int &z, int S1, int S2, int S3, unsigned int M) {
unsigned int b = (((z << S1) ^ z) >> S2);
return z = (((z &M) << S3) ^ b);
}
__device__ unsigned int randInt() {
TausStep(randStates[threadIdx.x&31], shift1[threadIdx.x&3], shift2[threadIdx.x&3],shift3[threadIdx.x&3],offset[threadIdx.x&3]);
return (randStates[(threadIdx.x)&31]^randStates[(threadIdx.x+1)&31]^randStates[(threadIdx.x+2)&31]^randStates[(threadIdx.x+3)&31]);
}
__global__ void sync_test(void) {
__shared__ int shared_int;
int count = 0;
long long timeout = 0;
if (threadIdx.x == 0) {
shared_int = 0;
}
__syncthreads();
if (threadIdx.x == 0) {
// occupy thread0
while (count < 100) {
for (int i=0; i<200; i++){
randInt();
}
if (++timeout > 1000000) {
break;
}
count++;
if (count > 50) {
count = 0;
}
}
shared_int = 1;
}
__syncthreads();
printf("%d\n", shared_int);
}
int main(void)
{
sync_test<<<1, 4>>>();
cudaDeviceSynchronize();
return 0;
}
/* prints:
1
1
1
1
*/ | /**
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership.
* The ASF licenses this file to You under the Apache License, Version 2.0
* (the "License"); you may not use this file except in compliance with
* the License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include <hip/hip_runtime.h>
#include <stdio.h>
__constant__ unsigned int shift1[4] = {6, 2, 13, 3};
__constant__ unsigned int shift2[4] = {13, 27, 21, 12};
__constant__ unsigned int shift3[4] = {18, 2, 7, 13};
__constant__ unsigned int offset[4] = {4294967294, 4294967288, 4294967280, 4294967168};
__shared__ unsigned int randStates[32];
__device__ unsigned int TausStep(unsigned int &z, int S1, int S2, int S3, unsigned int M) {
unsigned int b = (((z << S1) ^ z) >> S2);
return z = (((z &M) << S3) ^ b);
}
__device__ unsigned int randInt() {
TausStep(randStates[threadIdx.x&31], shift1[threadIdx.x&3], shift2[threadIdx.x&3],shift3[threadIdx.x&3],offset[threadIdx.x&3]);
return (randStates[(threadIdx.x)&31]^randStates[(threadIdx.x+1)&31]^randStates[(threadIdx.x+2)&31]^randStates[(threadIdx.x+3)&31]);
}
__global__ void sync_test(void) {
__shared__ int shared_int;
int count = 0;
long long timeout = 0;
if (threadIdx.x == 0) {
shared_int = 0;
}
__syncthreads();
if (threadIdx.x == 0) {
// occupy thread0
while (count < 100) {
for (int i=0; i<200; i++){
randInt();
}
if (++timeout > 1000000) {
break;
}
count++;
if (count > 50) {
count = 0;
}
}
shared_int = 1;
}
__syncthreads();
printf("%d\n", shared_int);
}
int main(void)
{
sync_test<<<1, 4>>>();
hipDeviceSynchronize();
return 0;
}
/* prints:
1
1
1
1
*/ |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | /**
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership.
* The ASF licenses this file to You under the Apache License, Version 2.0
* (the "License"); you may not use this file except in compliance with
* the License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include <hip/hip_runtime.h>
#include <stdio.h>
__constant__ unsigned int shift1[4] = {6, 2, 13, 3};
__constant__ unsigned int shift2[4] = {13, 27, 21, 12};
__constant__ unsigned int shift3[4] = {18, 2, 7, 13};
__constant__ unsigned int offset[4] = {4294967294, 4294967288, 4294967280, 4294967168};
__shared__ unsigned int randStates[32];
__device__ unsigned int TausStep(unsigned int &z, int S1, int S2, int S3, unsigned int M) {
unsigned int b = (((z << S1) ^ z) >> S2);
return z = (((z &M) << S3) ^ b);
}
__device__ unsigned int randInt() {
TausStep(randStates[threadIdx.x&31], shift1[threadIdx.x&3], shift2[threadIdx.x&3],shift3[threadIdx.x&3],offset[threadIdx.x&3]);
return (randStates[(threadIdx.x)&31]^randStates[(threadIdx.x+1)&31]^randStates[(threadIdx.x+2)&31]^randStates[(threadIdx.x+3)&31]);
}
__global__ void sync_test(void) {
__shared__ int shared_int;
int count = 0;
long long timeout = 0;
if (threadIdx.x == 0) {
shared_int = 0;
}
__syncthreads();
if (threadIdx.x == 0) {
// occupy thread0
while (count < 100) {
for (int i=0; i<200; i++){
randInt();
}
if (++timeout > 1000000) {
break;
}
count++;
if (count > 50) {
count = 0;
}
}
shared_int = 1;
}
__syncthreads();
printf("%d\n", shared_int);
}
int main(void)
{
sync_test<<<1, 4>>>();
hipDeviceSynchronize();
return 0;
}
/* prints:
1
1
1
1
*/ | .text
.file "sync_test2.hip"
.globl _Z24__device_stub__sync_testv # -- Begin function _Z24__device_stub__sync_testv
.p2align 4, 0x90
.type _Z24__device_stub__sync_testv,@function
_Z24__device_stub__sync_testv: # @_Z24__device_stub__sync_testv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z9sync_testv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z24__device_stub__sync_testv, .Lfunc_end0-_Z24__device_stub__sync_testv
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 3(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z9sync_testv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
callq hipDeviceSynchronize
xorl %eax, %eax
addq $56, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rbx
subq $32, %rsp
.cfi_adjust_cfa_offset 32
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9sync_testv, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
addq $32, %rsp
.cfi_adjust_cfa_offset -32
movl $shift1, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movl $16, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
pushq $0
.cfi_adjust_cfa_offset 8
pushq $1
.cfi_adjust_cfa_offset 8
callq __hipRegisterVar
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movl $shift2, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movl $16, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
pushq $0
.cfi_adjust_cfa_offset 8
pushq $1
.cfi_adjust_cfa_offset 8
callq __hipRegisterVar
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movl $shift3, %esi
movl $.L__unnamed_4, %edx
movl $.L__unnamed_4, %ecx
movl $16, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
pushq $0
.cfi_adjust_cfa_offset 8
pushq $1
.cfi_adjust_cfa_offset 8
callq __hipRegisterVar
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movl $offset, %esi
movl $.L__unnamed_5, %edx
movl $.L__unnamed_5, %ecx
movl $16, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
pushq $0
.cfi_adjust_cfa_offset 8
pushq $1
.cfi_adjust_cfa_offset 8
callq __hipRegisterVar
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movl $__hip_module_dtor, %edi
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type shift1,@object # @shift1
.local shift1
.comm shift1,16,16
.type shift2,@object # @shift2
.local shift2
.comm shift2,16,16
.type shift3,@object # @shift3
.local shift3
.comm shift3,16,16
.type offset,@object # @offset
.local offset
.comm offset,16,16
.type _Z9sync_testv,@object # @_Z9sync_testv
.section .rodata,"a",@progbits
.globl _Z9sync_testv
.p2align 3, 0x0
_Z9sync_testv:
.quad _Z24__device_stub__sync_testv
.size _Z9sync_testv, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z9sync_testv"
.size .L__unnamed_1, 14
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "shift1"
.size .L__unnamed_2, 7
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "shift2"
.size .L__unnamed_3, 7
.type .L__unnamed_4,@object # @3
.L__unnamed_4:
.asciz "shift3"
.size .L__unnamed_4, 7
.type .L__unnamed_5,@object # @4
.L__unnamed_5:
.asciz "offset"
.size .L__unnamed_5, 7
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__sync_testv
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym shift1
.addrsig_sym shift2
.addrsig_sym shift3
.addrsig_sym offset
.addrsig_sym _Z9sync_testv
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0007551d_00000000-6_sync_test2.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z8TausStepRjiiij
.type _Z8TausStepRjiiij, @function
_Z8TausStepRjiiij:
.LFB2057:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size _Z8TausStepRjiiij, .-_Z8TausStepRjiiij
.globl _Z7randIntv
.type _Z7randIntv, @function
_Z7randIntv:
.LFB2058:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2058:
.size _Z7randIntv, .-_Z7randIntv
.globl _Z27__device_stub__Z9sync_testvv
.type _Z27__device_stub__Z9sync_testvv, @function
_Z27__device_stub__Z9sync_testvv:
.LFB2084:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L11
.L7:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L12
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z9sync_testv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L7
.L12:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z27__device_stub__Z9sync_testvv, .-_Z27__device_stub__Z9sync_testvv
.globl _Z9sync_testv
.type _Z9sync_testv, @function
_Z9sync_testv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z27__device_stub__Z9sync_testvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z9sync_testv, .-_Z9sync_testv
.globl main
.type main, @function
main:
.LFB2059:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movl $4, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L18
.L16:
call cudaDeviceSynchronize@PLT
movl $0, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L18:
.cfi_restore_state
call _Z27__device_stub__Z9sync_testvv
jmp .L16
.cfi_endproc
.LFE2059:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z9sync_testv"
.LC1:
.string "shift1"
.LC2:
.string "shift2"
.LC3:
.string "shift3"
.LC4:
.string "offset"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z9sync_testv(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $16, %r9d
movl $0, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _ZL6shift1(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $16, %r9d
movl $0, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _ZL6shift2(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $16, %r9d
movl $0, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _ZL6shift3(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $16, %r9d
movl $0, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _ZL6offset(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL6offset
.comm _ZL6offset,16,16
.local _ZL6shift3
.comm _ZL6shift3,16,16
.local _ZL6shift2
.comm _ZL6shift2,16,16
.local _ZL6shift1
.comm _ZL6shift1,16,16
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "sync_test2.hip"
.globl _Z24__device_stub__sync_testv # -- Begin function _Z24__device_stub__sync_testv
.p2align 4, 0x90
.type _Z24__device_stub__sync_testv,@function
_Z24__device_stub__sync_testv: # @_Z24__device_stub__sync_testv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z9sync_testv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z24__device_stub__sync_testv, .Lfunc_end0-_Z24__device_stub__sync_testv
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 3(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z9sync_testv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
callq hipDeviceSynchronize
xorl %eax, %eax
addq $56, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rbx
subq $32, %rsp
.cfi_adjust_cfa_offset 32
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9sync_testv, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
addq $32, %rsp
.cfi_adjust_cfa_offset -32
movl $shift1, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movl $16, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
pushq $0
.cfi_adjust_cfa_offset 8
pushq $1
.cfi_adjust_cfa_offset 8
callq __hipRegisterVar
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movl $shift2, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movl $16, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
pushq $0
.cfi_adjust_cfa_offset 8
pushq $1
.cfi_adjust_cfa_offset 8
callq __hipRegisterVar
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movl $shift3, %esi
movl $.L__unnamed_4, %edx
movl $.L__unnamed_4, %ecx
movl $16, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
pushq $0
.cfi_adjust_cfa_offset 8
pushq $1
.cfi_adjust_cfa_offset 8
callq __hipRegisterVar
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movl $offset, %esi
movl $.L__unnamed_5, %edx
movl $.L__unnamed_5, %ecx
movl $16, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
pushq $0
.cfi_adjust_cfa_offset 8
pushq $1
.cfi_adjust_cfa_offset 8
callq __hipRegisterVar
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movl $__hip_module_dtor, %edi
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type shift1,@object # @shift1
.local shift1
.comm shift1,16,16
.type shift2,@object # @shift2
.local shift2
.comm shift2,16,16
.type shift3,@object # @shift3
.local shift3
.comm shift3,16,16
.type offset,@object # @offset
.local offset
.comm offset,16,16
.type _Z9sync_testv,@object # @_Z9sync_testv
.section .rodata,"a",@progbits
.globl _Z9sync_testv
.p2align 3, 0x0
_Z9sync_testv:
.quad _Z24__device_stub__sync_testv
.size _Z9sync_testv, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z9sync_testv"
.size .L__unnamed_1, 14
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "shift1"
.size .L__unnamed_2, 7
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "shift2"
.size .L__unnamed_3, 7
.type .L__unnamed_4,@object # @3
.L__unnamed_4:
.asciz "shift3"
.size .L__unnamed_4, 7
.type .L__unnamed_5,@object # @4
.L__unnamed_5:
.asciz "offset"
.size .L__unnamed_5, 7
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__sync_testv
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym shift1
.addrsig_sym shift2
.addrsig_sym shift3
.addrsig_sym offset
.addrsig_sym _Z9sync_testv
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void Sin( float * x, size_t idx, size_t N, float W0)
{
for (int i = blockIdx.x * blockDim.x + threadIdx.x; i < N; i += blockDim.x * gridDim.x)
{
x[(idx-1)*N+i] = sin(W0*x[(idx-1)*N+i]);
}
return;
} | code for sm_80
Function : _Z3SinPfmmf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R4, R4, c[0x0][0x0], R3 ; /* 0x0000000004047a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.U32.AND P0, PT, R4, c[0x0][0x170], PT ; /* 0x00005c0004007a0c */
/* 0x000fe40003f06070 */
/*0050*/ SHF.R.S32.HI R2, RZ, 0x1f, R4 ; /* 0x0000001fff027819 */
/* 0x000fc80000011404 */
/*0060*/ ISETP.GE.U32.AND.EX P0, PT, R2, c[0x0][0x174], PT, P0 ; /* 0x00005d0002007a0c */
/* 0x000fda0003f06100 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ IMAD.MOV.U32 R0, RZ, RZ, 0x1 ; /* 0x00000001ff007424 */
/* 0x000fe200078e00ff */
/*0090*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*00a0*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff057624 */
/* 0x000fe400078e00ff */
/*00b0*/ IMAD.MOV.U32 R9, RZ, RZ, R2 ; /* 0x000000ffff097224 */
/* 0x000fe200078e0002 */
/*00c0*/ IADD3 R0, P0, -R0, c[0x0][0x168], RZ ; /* 0x00005a0000007a10 */
/* 0x000fe20007f1e1ff */
/*00d0*/ IMAD.MOV.U32 R8, RZ, RZ, R4 ; /* 0x000000ffff087224 */
/* 0x000fc600078e0004 */
/*00e0*/ IADD3.X R5, R5, -0x1, RZ, P0, !PT ; /* 0xffffffff05057810 */
/* 0x000fca00007fe4ff */
/*00f0*/ IMAD R3, R5, c[0x0][0x170], RZ ; /* 0x00005c0005037a24 */
/* 0x000fe400078e02ff */
/*0100*/ IMAD.WIDE.U32 R8, R0, c[0x0][0x170], R8 ; /* 0x00005c0000087a25 */
/* 0x000fc800078e0008 */
/*0110*/ IMAD R3, R0, c[0x0][0x174], R3 ; /* 0x00005d0000037a24 */
/* 0x000fe200078e0203 */
/*0120*/ LEA R2, P0, R8, c[0x0][0x160], 0x2 ; /* 0x0000580008027a11 */
/* 0x000fc600078010ff */
/*0130*/ IMAD.IADD R3, R9, 0x1, R3 ; /* 0x0000000109037824 */
/* 0x000fca00078e0203 */
/*0140*/ LEA.HI.X R3, R8, c[0x0][0x164], R3, 0x2, P0 ; /* 0x0000590008037a11 */
/* 0x000fca00000f1403 */
/*0150*/ LDG.E R7, [R2.64] ; /* 0x0000000602077981 */
/* 0x000ea2000c1e1900 */
/*0160*/ BSSY B0, 0x8d0 ; /* 0x0000076000007945 */
/* 0x000fe20003800000 */
/*0170*/ FMUL R7, R7, c[0x0][0x178] ; /* 0x00005e0007077a20 */
/* 0x004fc80000400000 */
/*0180*/ FMUL R8, R7.reuse, 0.63661974668502807617 ; /* 0x3f22f98307087820 */
/* 0x040fe20000400000 */
/*0190*/ FSETP.GE.AND P0, PT, |R7|, 105615, PT ; /* 0x47ce47800700780b */
/* 0x000fca0003f06200 */
/*01a0*/ F2I.NTZ R8, R8 ; /* 0x0000000800087305 */
/* 0x000e300000203100 */
/*01b0*/ I2F R10, R8 ; /* 0x00000008000a7306 */
/* 0x001e240000201400 */
/*01c0*/ FFMA R9, R10, -1.5707962512969970703, R7 ; /* 0xbfc90fda0a097823 */
/* 0x001fc80000000007 */
/*01d0*/ FFMA R9, R10, -7.5497894158615963534e-08, R9 ; /* 0xb3a221680a097823 */
/* 0x000fc80000000009 */
/*01e0*/ FFMA R9, R10, -5.3903029534742383927e-15, R9 ; /* 0xa7c234c50a097823 */
/* 0x000fe20000000009 */
/*01f0*/ @!P0 BRA 0x8c0 ; /* 0x000006c000008947 */
/* 0x000fea0003800000 */
/*0200*/ FSETP.NEU.AND P0, PT, |R7|, +INF , PT ; /* 0x7f8000000700780b */
/* 0x000fda0003f0d200 */
/*0210*/ @!P0 BRA 0x8a0 ; /* 0x0000068000008947 */
/* 0x000fea0003800000 */
/*0220*/ SHF.R.U32.HI R8, RZ, 0x17, R7 ; /* 0x00000017ff087819 */
/* 0x000fe20000011607 */
/*0230*/ IMAD.SHL.U32 R9, R7, 0x100, RZ ; /* 0x0000010007097824 */
/* 0x000fe200078e00ff */
/*0240*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*0250*/ IMAD.MOV.U32 R13, RZ, RZ, RZ ; /* 0x000000ffff0d7224 */
/* 0x000fe200078e00ff */
/*0260*/ LOP3.LUT R8, R8, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff08087812 */
/* 0x000fe200078ec0ff */
/*0270*/ IMAD.MOV.U32 R19, RZ, RZ, RZ ; /* 0x000000ffff137224 */
/* 0x000fe200078e00ff */
/*0280*/ LOP3.LUT R21, R9, 0x80000000, RZ, 0xfc, !PT ; /* 0x8000000009157812 */
/* 0x000fe200078efcff */
/*0290*/ IMAD.MOV.U32 R22, RZ, RZ, RZ ; /* 0x000000ffff167224 */
/* 0x000fe200078e00ff */
/*02a0*/ IADD3 R20, R8, -0x80, RZ ; /* 0xffffff8008147810 */
/* 0x000fe20007ffe0ff */
/*02b0*/ ULDC.64 UR8, c[0x4][0x0] ; /* 0x0100000000087ab9 */
/* 0x000fc60000000a00 */
/*02c0*/ SHF.R.U32.HI R12, RZ, 0x5, R20 ; /* 0x00000005ff0c7819 */
/* 0x000fe40000011614 */
/*02d0*/ MOV R8, UR8 ; /* 0x0000000800087c02 */
/* 0x000fe20008000f00 */
/*02e0*/ IMAD.U32 R9, RZ, RZ, UR9 ; /* 0x00000009ff097e24 */
/* 0x000fca000f8e00ff */
/*02f0*/ LDG.E.CONSTANT R8, [R8.64] ; /* 0x0000000608087981 */
/* 0x000ea2000c1e9900 */
/*0300*/ IADD3 R19, R19, 0x1, RZ ; /* 0x0000000113137810 */
/* 0x000fe20007ffe0ff */
/*0310*/ UIADD3 UR8, UP0, UR8, 0x4, URZ ; /* 0x0000000408087890 */
/* 0x000fe2000ff1e03f */
/*0320*/ ISETP.EQ.AND P0, PT, R22.reuse, RZ, PT ; /* 0x000000ff1600720c */
/* 0x040fe40003f02270 */
/*0330*/ ISETP.EQ.AND P5, PT, R22.reuse, 0x4, PT ; /* 0x000000041600780c */
/* 0x040fe20003fa2270 */
/*0340*/ UIADD3.X UR9, URZ, UR9, URZ, UP0, !UPT ; /* 0x000000093f097290 */
/* 0x000fe200087fe43f */
/*0350*/ ISETP.EQ.AND P4, PT, R22.reuse, 0x8, PT ; /* 0x000000081600780c */
/* 0x040fe40003f82270 */
/*0360*/ ISETP.EQ.AND P3, PT, R22.reuse, 0xc, PT ; /* 0x0000000c1600780c */
/* 0x040fe40003f62270 */
/*0370*/ ISETP.EQ.AND P2, PT, R22, 0x10, PT ; /* 0x000000101600780c */
/* 0x000fc40003f42270 */
/*0380*/ ISETP.EQ.AND P1, PT, R22.reuse, 0x14, PT ; /* 0x000000141600780c */
/* 0x040fe40003f22270 */
/*0390*/ IADD3 R22, R22, 0x4, RZ ; /* 0x0000000416167810 */
/* 0x000fe20007ffe0ff */
/*03a0*/ IMAD.WIDE.U32 R10, R8, R21, RZ ; /* 0x00000015080a7225 */
/* 0x004fca00078e00ff */
/*03b0*/ IADD3 R10, P6, R10, R13, RZ ; /* 0x0000000d0a0a7210 */
/* 0x000fc80007fde0ff */
/*03c0*/ IADD3.X R13, R11, UR4, RZ, P6, !PT ; /* 0x000000040b0d7c10 */
/* 0x000fe2000b7fe4ff */
/*03d0*/ @P0 IMAD.MOV.U32 R6, RZ, RZ, R10.reuse ; /* 0x000000ffff060224 */
/* 0x100fe200078e000a */
/*03e0*/ ISETP.NE.AND P6, PT, R19, 0x6, PT ; /* 0x000000061300780c */
/* 0x000fe20003fc5270 */
/*03f0*/ @P5 IMAD.MOV.U32 R17, RZ, RZ, R10.reuse ; /* 0x000000ffff115224 */
/* 0x100fe400078e000a */
/*0400*/ @P4 IMAD.MOV.U32 R18, RZ, RZ, R10.reuse ; /* 0x000000ffff124224 */
/* 0x100fe400078e000a */
/*0410*/ @P3 IMAD.MOV.U32 R14, RZ, RZ, R10.reuse ; /* 0x000000ffff0e3224 */
/* 0x100fe400078e000a */
/*0420*/ @P2 IMAD.MOV.U32 R15, RZ, RZ, R10.reuse ; /* 0x000000ffff0f2224 */
/* 0x100fe400078e000a */
/*0430*/ @P1 IMAD.MOV.U32 R16, RZ, RZ, R10 ; /* 0x000000ffff101224 */
/* 0x000fc800078e000a */
/*0440*/ @P6 BRA 0x2d0 ; /* 0xfffffe8000006947 */
/* 0x000fea000383ffff */
/*0450*/ IADD3 R8, -R12, 0x6, RZ ; /* 0x000000060c087810 */
/* 0x000fe20007ffe1ff */
/*0460*/ BSSY B1, 0x790 ; /* 0x0000032000017945 */
/* 0x000fe80003800000 */
/*0470*/ IMAD.SHL.U32 R8, R8, 0x4, RZ ; /* 0x0000000408087824 */
/* 0x000fca00078e00ff */
/*0480*/ ISETP.EQ.AND P0, PT, R8.reuse, RZ, PT ; /* 0x000000ff0800720c */
/* 0x040fe40003f02270 */
/*0490*/ ISETP.EQ.AND P3, PT, R8.reuse, 0x4, PT ; /* 0x000000040800780c */
/* 0x040fe40003f62270 */
/*04a0*/ ISETP.EQ.AND P4, PT, R8.reuse, 0x8, PT ; /* 0x000000080800780c */
/* 0x040fe40003f82270 */
/*04b0*/ ISETP.EQ.AND P2, PT, R8.reuse, 0xc, PT ; /* 0x0000000c0800780c */
/* 0x040fe40003f42270 */
/*04c0*/ ISETP.EQ.AND P1, PT, R8, 0x10, PT ; /* 0x000000100800780c */
/* 0x000fca0003f22270 */
/*04d0*/ @P0 MOV R9, R6 ; /* 0x0000000600090202 */
/* 0x000fe40000000f00 */
/*04e0*/ @P3 IMAD.MOV.U32 R10, RZ, RZ, R6 ; /* 0x000000ffff0a3224 */
/* 0x000fe200078e0006 */
/*04f0*/ ISETP.EQ.AND P0, PT, R8.reuse, 0x14, PT ; /* 0x000000140800780c */
/* 0x040fe20003f02270 */
/*0500*/ @P3 IMAD.MOV.U32 R9, RZ, RZ, R17.reuse ; /* 0x000000ffff093224 */
/* 0x100fe200078e0011 */
/*0510*/ ISETP.EQ.AND P3, PT, R8.reuse, 0x18, PT ; /* 0x000000180800780c */
/* 0x040fe20003f62270 */
/*0520*/ @P4 IMAD.MOV.U32 R10, RZ, RZ, R17 ; /* 0x000000ffff0a4224 */
/* 0x000fe400078e0011 */
/*0530*/ @P4 IMAD.MOV.U32 R9, RZ, RZ, R18.reuse ; /* 0x000000ffff094224 */
/* 0x100fe200078e0012 */
/*0540*/ ISETP.EQ.AND P4, PT, R8, 0x1c, PT ; /* 0x0000001c0800780c */
/* 0x000fe20003f82270 */
/*0550*/ @P2 IMAD.MOV.U32 R10, RZ, RZ, R18 ; /* 0x000000ffff0a2224 */
/* 0x000fc400078e0012 */
/*0560*/ @P2 IMAD.MOV.U32 R9, RZ, RZ, R14.reuse ; /* 0x000000ffff092224 */
/* 0x100fe400078e000e */
/*0570*/ @P1 IMAD.MOV.U32 R10, RZ, RZ, R14 ; /* 0x000000ffff0a1224 */
/* 0x000fe400078e000e */
/*0580*/ @P1 IMAD.MOV.U32 R9, RZ, RZ, R15 ; /* 0x000000ffff091224 */
/* 0x000fe200078e000f */
/*0590*/ LOP3.LUT P1, R19, R20, 0x1f, RZ, 0xc0, !PT ; /* 0x0000001f14137812 */
/* 0x000fe2000782c0ff */
/*05a0*/ @P0 IMAD.MOV.U32 R9, RZ, RZ, R16.reuse ; /* 0x000000ffff090224 */
/* 0x100fe200078e0010 */
/*05b0*/ @P0 MOV R10, R15 ; /* 0x0000000f000a0202 */
/* 0x000fe20000000f00 */
/*05c0*/ @P3 IMAD.MOV.U32 R9, RZ, RZ, R13 ; /* 0x000000ffff093224 */
/* 0x000fe400078e000d */
/*05d0*/ @P3 IMAD.MOV.U32 R10, RZ, RZ, R16 ; /* 0x000000ffff0a3224 */
/* 0x000fc400078e0010 */
/*05e0*/ @P4 IMAD.MOV.U32 R10, RZ, RZ, R13 ; /* 0x000000ffff0a4224 */
/* 0x000fe400078e000d */
/*05f0*/ IMAD.MOV.U32 R8, RZ, RZ, R9 ; /* 0x000000ffff087224 */
/* 0x000fc800078e0009 */
/*0600*/ @!P1 BRA 0x780 ; /* 0x0000017000009947 */
/* 0x000fea0003800000 */
/*0610*/ IADD3 R9, -R12, 0x4, RZ ; /* 0x000000040c097810 */
/* 0x000fe40007ffe1ff */
/*0620*/ SHF.L.U32 R11, R8, R19.reuse, RZ ; /* 0x00000013080b7219 */
/* 0x080fe400000006ff */
/*0630*/ SHF.L.U32 R20, R10, R19, RZ ; /* 0x000000130a147219 */
/* 0x000fe200000006ff */
/*0640*/ IMAD.SHL.U32 R9, R9, 0x4, RZ ; /* 0x0000000409097824 */
/* 0x000fca00078e00ff */
/*0650*/ ISETP.EQ.AND P0, PT, R9.reuse, RZ, PT ; /* 0x000000ff0900720c */
/* 0x040fe40003f02270 */
/*0660*/ ISETP.EQ.AND P1, PT, R9.reuse, 0x4, PT ; /* 0x000000040900780c */
/* 0x040fe40003f22270 */
/*0670*/ ISETP.EQ.AND P2, PT, R9.reuse, 0x8, PT ; /* 0x000000080900780c */
/* 0x040fe40003f42270 */
/*0680*/ ISETP.EQ.AND P3, PT, R9, 0xc, PT ; /* 0x0000000c0900780c */
/* 0x000fce0003f62270 */
/*0690*/ @P0 IMAD.MOV.U32 R12, RZ, RZ, R6 ; /* 0x000000ffff0c0224 */
/* 0x000fe200078e0006 */
/*06a0*/ ISETP.EQ.AND P0, PT, R9.reuse, 0x10, PT ; /* 0x000000100900780c */
/* 0x040fe20003f02270 */
/*06b0*/ @P1 IMAD.MOV.U32 R12, RZ, RZ, R17 ; /* 0x000000ffff0c1224 */
/* 0x000fe200078e0011 */
/*06c0*/ ISETP.EQ.AND P1, PT, R9.reuse, 0x14, PT ; /* 0x000000140900780c */
/* 0x040fe40003f22270 */
/*06d0*/ @P2 MOV R12, R18 ; /* 0x00000012000c2202 */
/* 0x000fe20000000f00 */
/*06e0*/ @P3 IMAD.MOV.U32 R12, RZ, RZ, R14 ; /* 0x000000ffff0c3224 */
/* 0x000fe200078e000e */
/*06f0*/ ISETP.EQ.AND P2, PT, R9, 0x18, PT ; /* 0x000000180900780c */
/* 0x000fe40003f42270 */
/*0700*/ IADD3 R9, -R19, 0x20, RZ ; /* 0x0000002013097810 */
/* 0x000fc80007ffe1ff */
/*0710*/ SHF.R.U32.HI R8, RZ, R9, R10 ; /* 0x00000009ff087219 */
/* 0x000fe2000001160a */
/*0720*/ @P0 IMAD.MOV.U32 R12, RZ, RZ, R15 ; /* 0x000000ffff0c0224 */
/* 0x000fe400078e000f */
/*0730*/ @P1 IMAD.MOV.U32 R12, RZ, RZ, R16 ; /* 0x000000ffff0c1224 */
/* 0x000fe400078e0010 */
/*0740*/ IMAD.IADD R8, R8, 0x1, R11 ; /* 0x0000000108087824 */
/* 0x000fe400078e020b */
/*0750*/ @P2 IMAD.MOV.U32 R12, RZ, RZ, R13 ; /* 0x000000ffff0c2224 */
/* 0x000fca00078e000d */
/*0760*/ SHF.R.U32.HI R9, RZ, R9, R12 ; /* 0x00000009ff097219 */
/* 0x000fca000001160c */
/*0770*/ IMAD.IADD R10, R9, 0x1, R20 ; /* 0x00000001090a7824 */
/* 0x000fe400078e0214 */
/*0780*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0790*/ SHF.L.U32.HI R13, R10.reuse, 0x2, R8 ; /* 0x000000020a0d7819 */
/* 0x040fe20000010608 */
/*07a0*/ IMAD.SHL.U32 R12, R10, 0x4, RZ ; /* 0x000000040a0c7824 */
/* 0x000fe200078e00ff */
/*07b0*/ LOP3.LUT P1, R7, R7, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000007077812 */
/* 0x000fe4000782c0ff */
/*07c0*/ SHF.R.U32.HI R9, RZ, 0x1f, R13 ; /* 0x0000001fff097819 */
/* 0x000fc8000001160d */
/*07d0*/ ISETP.NE.AND P0, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x000fe40003f05270 */
/*07e0*/ LEA.HI R8, R8, R9, RZ, 0x2 ; /* 0x0000000908087211 */
/* 0x000fd600078f10ff */
/*07f0*/ @P0 LOP3.LUT R13, RZ, R13, RZ, 0x33, !PT ; /* 0x0000000dff0d0212 */
/* 0x000fe400078e33ff */
/*0800*/ @P0 LOP3.LUT R12, RZ, R12, RZ, 0x33, !PT ; /* 0x0000000cff0c0212 */
/* 0x000fe400078e33ff */
/*0810*/ @P0 LOP3.LUT R7, R7, 0x80000000, RZ, 0x3c, !PT ; /* 0x8000000007070812 */
/* 0x000fe400078e3cff */
/*0820*/ I2F.F64.S64 R10, R12 ; /* 0x0000000c000a7312 */
/* 0x000e240000301c00 */
/*0830*/ ISETP.NE.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fe20003f05270 */
/*0840*/ IMAD.MOV R7, RZ, RZ, -R8 ; /* 0x000000ffff077224 */
/* 0x000fca00078e0a08 */
/*0850*/ @P1 MOV R8, R7 ; /* 0x0000000700081202 */
/* 0x000fe20000000f00 */
/*0860*/ DMUL R10, R10, c[0x2][0x0] ; /* 0x008000000a0a7a28 */
/* 0x001e140000000000 */
/*0870*/ F2F.F32.F64 R10, R10 ; /* 0x0000000a000a7310 */
/* 0x001e240000301000 */
/*0880*/ FSEL R9, R10, -R10, !P0 ; /* 0x8000000a0a097208 */
/* 0x001fe20004000000 */
/*0890*/ BRA 0x8c0 ; /* 0x0000002000007947 */
/* 0x000fea0003800000 */
/*08a0*/ FMUL R9, RZ, R7 ; /* 0x00000007ff097220 */
/* 0x000fe40000400000 */
/*08b0*/ IMAD.MOV.U32 R8, RZ, RZ, RZ ; /* 0x000000ffff087224 */
/* 0x000fe400078e00ff */
/*08c0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*08d0*/ LOP3.LUT P1, RZ, R8.reuse, 0x1, RZ, 0xc0, !PT ; /* 0x0000000108ff7812 */
/* 0x040fe2000782c0ff */
/*08e0*/ IMAD.MOV.U32 R10, RZ, RZ, 0x3c0885e4 ; /* 0x3c0885e4ff0a7424 */
/* 0x000fe200078e00ff */
/*08f0*/ LOP3.LUT P0, RZ, R8, 0x2, RZ, 0xc0, !PT ; /* 0x0000000208ff7812 */
/* 0x000fe2000780c0ff */
/*0900*/ FMUL R20, R9.reuse, R9 ; /* 0x0000000909147220 */
/* 0x040fe20000400000 */
/*0910*/ FSEL R9, R9, 1, !P1 ; /* 0x3f80000009097808 */
/* 0x000fe20004800000 */
/*0920*/ IMAD.MOV.U32 R12, RZ, RZ, 0x3e2aaaa8 ; /* 0x3e2aaaa8ff0c7424 */
/* 0x000fe200078e00ff */
/*0930*/ FSEL R10, R10, 0.041666727513074874878, !P1 ; /* 0x3d2aaabb0a0a7808 */
/* 0x000fe20004800000 */
/*0940*/ IMAD.MOV.U32 R7, RZ, RZ, -0x46b2bead ; /* 0xb94d4153ff077424 */
/* 0x000fc600078e00ff */
/*0950*/ FSEL R8, -R12, -0.4999999701976776123, !P1 ; /* 0xbeffffff0c087808 */
/* 0x000fc60004800100 */
/*0960*/ @P1 IMAD.MOV.U32 R11, RZ, RZ, 0x37cbac00 ; /* 0x37cbac00ff0b1424 */
/* 0x000fc800078e00ff */
/*0970*/ @P1 FFMA R7, R20, R11, -0.0013887860113754868507 ; /* 0xbab607ed14071423 */
/* 0x000fc8000000000b */
/*0980*/ FFMA R7, R20.reuse, R7, R10 ; /* 0x0000000714077223 */
/* 0x040fe4000000000a */
/*0990*/ FFMA R10, R9, R20, RZ ; /* 0x00000014090a7223 */
/* 0x000fe400000000ff */
/*09a0*/ FFMA R7, R20, R7, R8 ; /* 0x0000000714077223 */
/* 0x000fc80000000008 */
/*09b0*/ FFMA R7, R7, R10, R9 ; /* 0x0000000a07077223 */
/* 0x000fe40000000009 */
/*09c0*/ IMAD.MOV.U32 R9, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff097624 */
/* 0x000fe400078e00ff */
/*09d0*/ @P0 FFMA R7, R7, -1, RZ ; /* 0xbf80000007070823 */
/* 0x000fe400000000ff */
/*09e0*/ IMAD R8, R9, c[0x0][0xc], R4 ; /* 0x0000030009087a24 */
/* 0x000fc600078e0204 */
/*09f0*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x0001e2000c101906 */
/*0a00*/ IMAD.MOV.U32 R4, RZ, RZ, R8.reuse ; /* 0x000000ffff047224 */
/* 0x100fe200078e0008 */
/*0a10*/ ISETP.GE.U32.AND P0, PT, R8, c[0x0][0x170], PT ; /* 0x00005c0008007a0c */
/* 0x000fe40003f06070 */
/*0a20*/ SHF.R.S32.HI R9, RZ, 0x1f, R8 ; /* 0x0000001fff097819 */
/* 0x000fc80000011408 */
/*0a30*/ ISETP.GE.U32.AND.EX P0, PT, R9, c[0x0][0x174], PT, P0 ; /* 0x00005d0009007a0c */
/* 0x000fda0003f06100 */
/*0a40*/ @!P0 BRA 0xf0 ; /* 0xfffff6a000008947 */
/* 0x001fea000383ffff */
/*0a50*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0a60*/ BRA 0xa60; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0a70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0aa0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ab0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ac0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ad0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ae0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0af0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void Sin( float * x, size_t idx, size_t N, float W0)
{
for (int i = blockIdx.x * blockDim.x + threadIdx.x; i < N; i += blockDim.x * gridDim.x)
{
x[(idx-1)*N+i] = sin(W0*x[(idx-1)*N+i]);
}
return;
} | .file "tmpxft_000f96a4_00000000-6_Sin.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z25__device_stub__Z3SinPfmmfPfmmf
.type _Z25__device_stub__Z3SinPfmmfPfmmf, @function
_Z25__device_stub__Z3SinPfmmfPfmmf:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movss %xmm0, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3SinPfmmf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z25__device_stub__Z3SinPfmmfPfmmf, .-_Z25__device_stub__Z3SinPfmmfPfmmf
.globl _Z3SinPfmmf
.type _Z3SinPfmmf, @function
_Z3SinPfmmf:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z25__device_stub__Z3SinPfmmfPfmmf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z3SinPfmmf, .-_Z3SinPfmmf
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z3SinPfmmf"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z3SinPfmmf(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void Sin( float * x, size_t idx, size_t N, float W0)
{
for (int i = blockIdx.x * blockDim.x + threadIdx.x; i < N; i += blockDim.x * gridDim.x)
{
x[(idx-1)*N+i] = sin(W0*x[(idx-1)*N+i]);
}
return;
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void Sin( float * x, size_t idx, size_t N, float W0)
{
for (int i = blockIdx.x * blockDim.x + threadIdx.x; i < N; i += blockDim.x * gridDim.x)
{
x[(idx-1)*N+i] = sin(W0*x[(idx-1)*N+i]);
}
return;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void Sin( float * x, size_t idx, size_t N, float W0)
{
for (int i = blockIdx.x * blockDim.x + threadIdx.x; i < N; i += blockDim.x * gridDim.x)
{
x[(idx-1)*N+i] = sin(W0*x[(idx-1)*N+i]);
}
return;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3SinPfmmf
.globl _Z3SinPfmmf
.p2align 8
.type _Z3SinPfmmf,@function
_Z3SinPfmmf:
s_clause 0x1
s_load_b32 s6, s[0:1], 0x2c
s_load_b64 s[2:3], s[0:1], 0x10
s_add_u32 s4, s0, 32
s_addc_u32 s5, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s7, s6, 0xffff
s_mov_b32 s6, exec_lo
v_mad_u64_u32 v[5:6], null, s15, s7, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v6, 31, v5
v_cmpx_gt_u64_e64 s[2:3], v[5:6]
s_cbranch_execz .LBB0_7
s_load_b128 s[8:11], s[0:1], 0x0
s_load_b32 s12, s[4:5], 0x0
s_load_b32 s4, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s10, -1
s_addc_u32 s1, s11, -1
s_mul_i32 s5, s0, s3
s_mul_hi_u32 s6, s0, s2
s_mul_i32 s1, s1, s2
s_add_i32 s5, s6, s5
s_mul_i32 s0, s0, s2
s_add_i32 s1, s5, s1
s_mov_b32 s10, 0xb94c1982
s_lshl_b64 s[0:1], s[0:1], 2
s_mov_b32 s11, 0x37d75334
s_add_u32 s5, s8, s0
s_addc_u32 s6, s9, s1
s_add_i32 s15, s15, s12
s_mov_b32 s8, 0
v_mad_u64_u32 v[1:2], null, s15, s7, v[0:1]
s_mul_i32 s7, s12, s7
s_mov_b32 s9, 0x7fffff
s_branch .LBB0_3
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_dual_mul_f32 v7, v5, v5 :: v_dual_and_b32 v10, 1, v6
v_cmp_class_f32_e64 s0, v0, 0x1f8
v_lshlrev_b32_e32 v6, 30, v6
v_fmaak_f32 v8, s10, v7, 0x3c0881c4
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cmp_eq_u32_e32 vcc_lo, 0, v10
v_and_b32_e32 v6, 0x80000000, v6
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmaak_f32 v8, v7, v8, 0xbe2aaa9d
v_dual_fmaak_f32 v9, s11, v7, 0xbab64f3b :: v_dual_mul_f32 v8, v7, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fmaak_f32 v9, v7, v9, 0x3d2aabf7
v_fmac_f32_e32 v5, v5, v8
v_xor_b32_e32 v8, v2, v0
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmaak_f32 v9, v7, v9, 0xbf000004
v_fma_f32 v7, v7, v9, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
v_cndmask_b32_e32 v5, v7, v5, vcc_lo
v_cmp_le_u64_e32 vcc_lo, s[2:3], v[1:2]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_xor3_b32 v5, v8, v6, v5
s_or_b32 s8, vcc_lo, s8
v_cndmask_b32_e64 v0, 0x7fc00000, v5, s0
v_dual_mov_b32 v6, v2 :: v_dual_mov_b32 v5, v1
v_add_nc_u32_e32 v1, s7, v1
global_store_b32 v[3:4], v0, off
s_and_not1_b32 exec_lo, exec_lo, s8
s_cbranch_execz .LBB0_7
.LBB0_3:
v_lshlrev_b64 v[3:4], 2, v[5:6]
s_mov_b32 s1, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v3, vcc_lo, s5, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s6, v4, vcc_lo
global_load_b32 v0, v[3:4], off
s_waitcnt vmcnt(0)
v_mul_f32_e32 v0, s4, v0
s_delay_alu instid0(VALU_DEP_1)
v_and_b32_e32 v2, 0x7fffffff, v0
v_cmpx_ngt_f32_e64 0x48000000, |v0|
s_xor_b32 s12, exec_lo, s1
s_cbranch_execz .LBB0_5
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_and_or_b32 v15, v2, s9, 0x800000
v_mov_b32_e32 v7, 0
v_lshrrev_b32_e32 v12, 23, v2
v_mad_u64_u32 v[5:6], null, v15, 0xfe5163ab, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v13, 0xffffff88, v12
v_cmp_lt_u32_e32 vcc_lo, 63, v13
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[8:9], null, v15, 0x3c439041, v[6:7]
v_cndmask_b32_e64 v14, 0, 0xffffffc0, vcc_lo
v_mov_b32_e32 v6, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v14, v14, v13
v_mad_u64_u32 v[9:10], null, v15, 0xdb629599, v[6:7]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_lt_u32_e64 s0, 31, v14
v_cndmask_b32_e64 v16, 0, 0xffffffe0, s0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_dual_mov_b32 v6, v10 :: v_dual_cndmask_b32 v5, v9, v5
v_add_nc_u32_e32 v16, v16, v14
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[10:11], null, v15, 0xf534ddc0, v[6:7]
v_cmp_lt_u32_e64 s1, 31, v16
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_mov_b32_e32 v6, v11
v_cndmask_b32_e32 v8, v10, v8, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[11:12], null, v15, 0xfc2757d1, v[6:7]
v_cndmask_b32_e64 v5, v8, v5, s0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mov_b32_e32 v6, v12
v_mad_u64_u32 v[12:13], null, v15, 0x4e441529, v[6:7]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mov_b32_e32 v6, v13
v_mad_u64_u32 v[13:14], null, v15, 0xa2f9836e, v[6:7]
v_cndmask_b32_e64 v6, 0, 0xffffffe0, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_dual_cndmask_b32 v7, v12, v10 :: v_dual_add_nc_u32 v6, v6, v16
v_dual_cndmask_b32 v13, v13, v11 :: v_dual_cndmask_b32 v12, v14, v12
v_cndmask_b32_e32 v11, v11, v9, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cmp_eq_u32_e32 vcc_lo, 0, v6
v_cndmask_b32_e64 v10, v13, v7, s0
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_cndmask_b32_e64 v12, v12, v13, s0
v_cndmask_b32_e64 v7, v7, v11, s0
v_sub_nc_u32_e32 v13, 32, v6
v_cndmask_b32_e64 v11, v11, v8, s0
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_cndmask_b32_e64 v12, v12, v10, s1
v_cndmask_b32_e64 v10, v10, v7, s1
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_cndmask_b32_e64 v7, v7, v11, s1
v_cndmask_b32_e64 v5, v11, v5, s1
v_alignbit_b32 v14, v12, v10, v13
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_alignbit_b32 v9, v10, v7, v13
v_cndmask_b32_e32 v6, v14, v12, vcc_lo
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_alignbit_b32 v12, v7, v5, v13
v_cndmask_b32_e32 v8, v9, v10, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_bfe_u32 v9, v6, 29, 1
v_cndmask_b32_e32 v7, v12, v7, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_alignbit_b32 v10, v6, v8, 30
v_sub_nc_u32_e32 v11, 0, v9
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_alignbit_b32 v8, v8, v7, 30
v_alignbit_b32 v5, v7, v5, 30
v_xor_b32_e32 v10, v10, v11
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_xor_b32_e32 v7, v8, v11
v_xor_b32_e32 v5, v5, v11
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_clz_i32_u32_e32 v12, v10
v_min_u32_e32 v12, 32, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v8, 31, v12
v_lshlrev_b32_e32 v14, 23, v12
v_alignbit_b32 v10, v10, v7, v8
v_alignbit_b32 v5, v7, v5, v8
v_lshrrev_b32_e32 v8, 29, v6
v_lshrrev_b32_e32 v6, 30, v6
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_alignbit_b32 v7, v10, v5, 9
v_lshlrev_b32_e32 v8, 31, v8
v_lshrrev_b32_e32 v10, 9, v10
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_nc_u32_e32 v6, v9, v6
v_clz_i32_u32_e32 v11, v7
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
v_or_b32_e32 v13, 0.5, v8
v_min_u32_e32 v11, 32, v11
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v13, v13, v14
v_sub_nc_u32_e32 v15, 31, v11
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_alignbit_b32 v5, v7, v5, v15
v_or_b32_e32 v7, v10, v13
v_add_lshl_u32 v10, v11, v12, 23
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_lshrrev_b32_e32 v5, 9, v5
v_mul_f32_e32 v11, 0x3fc90fda, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v5, v5, v10
v_fma_f32 v10, v7, 0x3fc90fda, -v11
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v5, 0x33000000, v5
v_fmac_f32_e32 v10, 0x33a22168, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_or_b32_e32 v5, v5, v8
v_fmac_f32_e32 v10, 0x3fc90fda, v5
s_delay_alu instid0(VALU_DEP_1)
v_add_f32_e32 v5, v11, v10
.LBB0_5:
s_and_not1_saveexec_b32 s0, s12
s_cbranch_execz .LBB0_2
v_mul_f32_e64 v5, 0x3f22f983, |v0|
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_rndne_f32_e32 v6, v5
v_fma_f32 v5, v6, 0xbfc90fda, |v0|
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v5, 0xb3a22168, v6
v_fmac_f32_e32 v5, 0xa7c234c4, v6
v_cvt_i32_f32_e32 v6, v6
s_branch .LBB0_2
.LBB0_7:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3SinPfmmf
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 17
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3SinPfmmf, .Lfunc_end0-_Z3SinPfmmf
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 8
.value_kind: by_value
- .offset: 16
.size: 8
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3SinPfmmf
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z3SinPfmmf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 17
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void Sin( float * x, size_t idx, size_t N, float W0)
{
for (int i = blockIdx.x * blockDim.x + threadIdx.x; i < N; i += blockDim.x * gridDim.x)
{
x[(idx-1)*N+i] = sin(W0*x[(idx-1)*N+i]);
}
return;
} | .text
.file "Sin.hip"
.globl _Z18__device_stub__SinPfmmf # -- Begin function _Z18__device_stub__SinPfmmf
.p2align 4, 0x90
.type _Z18__device_stub__SinPfmmf,@function
_Z18__device_stub__SinPfmmf: # @_Z18__device_stub__SinPfmmf
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movss %xmm0, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3SinPfmmf, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z18__device_stub__SinPfmmf, .Lfunc_end0-_Z18__device_stub__SinPfmmf
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3SinPfmmf, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3SinPfmmf,@object # @_Z3SinPfmmf
.section .rodata,"a",@progbits
.globl _Z3SinPfmmf
.p2align 3, 0x0
_Z3SinPfmmf:
.quad _Z18__device_stub__SinPfmmf
.size _Z3SinPfmmf, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z3SinPfmmf"
.size .L__unnamed_1, 12
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__SinPfmmf
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3SinPfmmf
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z3SinPfmmf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R4, R4, c[0x0][0x0], R3 ; /* 0x0000000004047a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.U32.AND P0, PT, R4, c[0x0][0x170], PT ; /* 0x00005c0004007a0c */
/* 0x000fe40003f06070 */
/*0050*/ SHF.R.S32.HI R2, RZ, 0x1f, R4 ; /* 0x0000001fff027819 */
/* 0x000fc80000011404 */
/*0060*/ ISETP.GE.U32.AND.EX P0, PT, R2, c[0x0][0x174], PT, P0 ; /* 0x00005d0002007a0c */
/* 0x000fda0003f06100 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ IMAD.MOV.U32 R0, RZ, RZ, 0x1 ; /* 0x00000001ff007424 */
/* 0x000fe200078e00ff */
/*0090*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*00a0*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff057624 */
/* 0x000fe400078e00ff */
/*00b0*/ IMAD.MOV.U32 R9, RZ, RZ, R2 ; /* 0x000000ffff097224 */
/* 0x000fe200078e0002 */
/*00c0*/ IADD3 R0, P0, -R0, c[0x0][0x168], RZ ; /* 0x00005a0000007a10 */
/* 0x000fe20007f1e1ff */
/*00d0*/ IMAD.MOV.U32 R8, RZ, RZ, R4 ; /* 0x000000ffff087224 */
/* 0x000fc600078e0004 */
/*00e0*/ IADD3.X R5, R5, -0x1, RZ, P0, !PT ; /* 0xffffffff05057810 */
/* 0x000fca00007fe4ff */
/*00f0*/ IMAD R3, R5, c[0x0][0x170], RZ ; /* 0x00005c0005037a24 */
/* 0x000fe400078e02ff */
/*0100*/ IMAD.WIDE.U32 R8, R0, c[0x0][0x170], R8 ; /* 0x00005c0000087a25 */
/* 0x000fc800078e0008 */
/*0110*/ IMAD R3, R0, c[0x0][0x174], R3 ; /* 0x00005d0000037a24 */
/* 0x000fe200078e0203 */
/*0120*/ LEA R2, P0, R8, c[0x0][0x160], 0x2 ; /* 0x0000580008027a11 */
/* 0x000fc600078010ff */
/*0130*/ IMAD.IADD R3, R9, 0x1, R3 ; /* 0x0000000109037824 */
/* 0x000fca00078e0203 */
/*0140*/ LEA.HI.X R3, R8, c[0x0][0x164], R3, 0x2, P0 ; /* 0x0000590008037a11 */
/* 0x000fca00000f1403 */
/*0150*/ LDG.E R7, [R2.64] ; /* 0x0000000602077981 */
/* 0x000ea2000c1e1900 */
/*0160*/ BSSY B0, 0x8d0 ; /* 0x0000076000007945 */
/* 0x000fe20003800000 */
/*0170*/ FMUL R7, R7, c[0x0][0x178] ; /* 0x00005e0007077a20 */
/* 0x004fc80000400000 */
/*0180*/ FMUL R8, R7.reuse, 0.63661974668502807617 ; /* 0x3f22f98307087820 */
/* 0x040fe20000400000 */
/*0190*/ FSETP.GE.AND P0, PT, |R7|, 105615, PT ; /* 0x47ce47800700780b */
/* 0x000fca0003f06200 */
/*01a0*/ F2I.NTZ R8, R8 ; /* 0x0000000800087305 */
/* 0x000e300000203100 */
/*01b0*/ I2F R10, R8 ; /* 0x00000008000a7306 */
/* 0x001e240000201400 */
/*01c0*/ FFMA R9, R10, -1.5707962512969970703, R7 ; /* 0xbfc90fda0a097823 */
/* 0x001fc80000000007 */
/*01d0*/ FFMA R9, R10, -7.5497894158615963534e-08, R9 ; /* 0xb3a221680a097823 */
/* 0x000fc80000000009 */
/*01e0*/ FFMA R9, R10, -5.3903029534742383927e-15, R9 ; /* 0xa7c234c50a097823 */
/* 0x000fe20000000009 */
/*01f0*/ @!P0 BRA 0x8c0 ; /* 0x000006c000008947 */
/* 0x000fea0003800000 */
/*0200*/ FSETP.NEU.AND P0, PT, |R7|, +INF , PT ; /* 0x7f8000000700780b */
/* 0x000fda0003f0d200 */
/*0210*/ @!P0 BRA 0x8a0 ; /* 0x0000068000008947 */
/* 0x000fea0003800000 */
/*0220*/ SHF.R.U32.HI R8, RZ, 0x17, R7 ; /* 0x00000017ff087819 */
/* 0x000fe20000011607 */
/*0230*/ IMAD.SHL.U32 R9, R7, 0x100, RZ ; /* 0x0000010007097824 */
/* 0x000fe200078e00ff */
/*0240*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*0250*/ IMAD.MOV.U32 R13, RZ, RZ, RZ ; /* 0x000000ffff0d7224 */
/* 0x000fe200078e00ff */
/*0260*/ LOP3.LUT R8, R8, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff08087812 */
/* 0x000fe200078ec0ff */
/*0270*/ IMAD.MOV.U32 R19, RZ, RZ, RZ ; /* 0x000000ffff137224 */
/* 0x000fe200078e00ff */
/*0280*/ LOP3.LUT R21, R9, 0x80000000, RZ, 0xfc, !PT ; /* 0x8000000009157812 */
/* 0x000fe200078efcff */
/*0290*/ IMAD.MOV.U32 R22, RZ, RZ, RZ ; /* 0x000000ffff167224 */
/* 0x000fe200078e00ff */
/*02a0*/ IADD3 R20, R8, -0x80, RZ ; /* 0xffffff8008147810 */
/* 0x000fe20007ffe0ff */
/*02b0*/ ULDC.64 UR8, c[0x4][0x0] ; /* 0x0100000000087ab9 */
/* 0x000fc60000000a00 */
/*02c0*/ SHF.R.U32.HI R12, RZ, 0x5, R20 ; /* 0x00000005ff0c7819 */
/* 0x000fe40000011614 */
/*02d0*/ MOV R8, UR8 ; /* 0x0000000800087c02 */
/* 0x000fe20008000f00 */
/*02e0*/ IMAD.U32 R9, RZ, RZ, UR9 ; /* 0x00000009ff097e24 */
/* 0x000fca000f8e00ff */
/*02f0*/ LDG.E.CONSTANT R8, [R8.64] ; /* 0x0000000608087981 */
/* 0x000ea2000c1e9900 */
/*0300*/ IADD3 R19, R19, 0x1, RZ ; /* 0x0000000113137810 */
/* 0x000fe20007ffe0ff */
/*0310*/ UIADD3 UR8, UP0, UR8, 0x4, URZ ; /* 0x0000000408087890 */
/* 0x000fe2000ff1e03f */
/*0320*/ ISETP.EQ.AND P0, PT, R22.reuse, RZ, PT ; /* 0x000000ff1600720c */
/* 0x040fe40003f02270 */
/*0330*/ ISETP.EQ.AND P5, PT, R22.reuse, 0x4, PT ; /* 0x000000041600780c */
/* 0x040fe20003fa2270 */
/*0340*/ UIADD3.X UR9, URZ, UR9, URZ, UP0, !UPT ; /* 0x000000093f097290 */
/* 0x000fe200087fe43f */
/*0350*/ ISETP.EQ.AND P4, PT, R22.reuse, 0x8, PT ; /* 0x000000081600780c */
/* 0x040fe40003f82270 */
/*0360*/ ISETP.EQ.AND P3, PT, R22.reuse, 0xc, PT ; /* 0x0000000c1600780c */
/* 0x040fe40003f62270 */
/*0370*/ ISETP.EQ.AND P2, PT, R22, 0x10, PT ; /* 0x000000101600780c */
/* 0x000fc40003f42270 */
/*0380*/ ISETP.EQ.AND P1, PT, R22.reuse, 0x14, PT ; /* 0x000000141600780c */
/* 0x040fe40003f22270 */
/*0390*/ IADD3 R22, R22, 0x4, RZ ; /* 0x0000000416167810 */
/* 0x000fe20007ffe0ff */
/*03a0*/ IMAD.WIDE.U32 R10, R8, R21, RZ ; /* 0x00000015080a7225 */
/* 0x004fca00078e00ff */
/*03b0*/ IADD3 R10, P6, R10, R13, RZ ; /* 0x0000000d0a0a7210 */
/* 0x000fc80007fde0ff */
/*03c0*/ IADD3.X R13, R11, UR4, RZ, P6, !PT ; /* 0x000000040b0d7c10 */
/* 0x000fe2000b7fe4ff */
/*03d0*/ @P0 IMAD.MOV.U32 R6, RZ, RZ, R10.reuse ; /* 0x000000ffff060224 */
/* 0x100fe200078e000a */
/*03e0*/ ISETP.NE.AND P6, PT, R19, 0x6, PT ; /* 0x000000061300780c */
/* 0x000fe20003fc5270 */
/*03f0*/ @P5 IMAD.MOV.U32 R17, RZ, RZ, R10.reuse ; /* 0x000000ffff115224 */
/* 0x100fe400078e000a */
/*0400*/ @P4 IMAD.MOV.U32 R18, RZ, RZ, R10.reuse ; /* 0x000000ffff124224 */
/* 0x100fe400078e000a */
/*0410*/ @P3 IMAD.MOV.U32 R14, RZ, RZ, R10.reuse ; /* 0x000000ffff0e3224 */
/* 0x100fe400078e000a */
/*0420*/ @P2 IMAD.MOV.U32 R15, RZ, RZ, R10.reuse ; /* 0x000000ffff0f2224 */
/* 0x100fe400078e000a */
/*0430*/ @P1 IMAD.MOV.U32 R16, RZ, RZ, R10 ; /* 0x000000ffff101224 */
/* 0x000fc800078e000a */
/*0440*/ @P6 BRA 0x2d0 ; /* 0xfffffe8000006947 */
/* 0x000fea000383ffff */
/*0450*/ IADD3 R8, -R12, 0x6, RZ ; /* 0x000000060c087810 */
/* 0x000fe20007ffe1ff */
/*0460*/ BSSY B1, 0x790 ; /* 0x0000032000017945 */
/* 0x000fe80003800000 */
/*0470*/ IMAD.SHL.U32 R8, R8, 0x4, RZ ; /* 0x0000000408087824 */
/* 0x000fca00078e00ff */
/*0480*/ ISETP.EQ.AND P0, PT, R8.reuse, RZ, PT ; /* 0x000000ff0800720c */
/* 0x040fe40003f02270 */
/*0490*/ ISETP.EQ.AND P3, PT, R8.reuse, 0x4, PT ; /* 0x000000040800780c */
/* 0x040fe40003f62270 */
/*04a0*/ ISETP.EQ.AND P4, PT, R8.reuse, 0x8, PT ; /* 0x000000080800780c */
/* 0x040fe40003f82270 */
/*04b0*/ ISETP.EQ.AND P2, PT, R8.reuse, 0xc, PT ; /* 0x0000000c0800780c */
/* 0x040fe40003f42270 */
/*04c0*/ ISETP.EQ.AND P1, PT, R8, 0x10, PT ; /* 0x000000100800780c */
/* 0x000fca0003f22270 */
/*04d0*/ @P0 MOV R9, R6 ; /* 0x0000000600090202 */
/* 0x000fe40000000f00 */
/*04e0*/ @P3 IMAD.MOV.U32 R10, RZ, RZ, R6 ; /* 0x000000ffff0a3224 */
/* 0x000fe200078e0006 */
/*04f0*/ ISETP.EQ.AND P0, PT, R8.reuse, 0x14, PT ; /* 0x000000140800780c */
/* 0x040fe20003f02270 */
/*0500*/ @P3 IMAD.MOV.U32 R9, RZ, RZ, R17.reuse ; /* 0x000000ffff093224 */
/* 0x100fe200078e0011 */
/*0510*/ ISETP.EQ.AND P3, PT, R8.reuse, 0x18, PT ; /* 0x000000180800780c */
/* 0x040fe20003f62270 */
/*0520*/ @P4 IMAD.MOV.U32 R10, RZ, RZ, R17 ; /* 0x000000ffff0a4224 */
/* 0x000fe400078e0011 */
/*0530*/ @P4 IMAD.MOV.U32 R9, RZ, RZ, R18.reuse ; /* 0x000000ffff094224 */
/* 0x100fe200078e0012 */
/*0540*/ ISETP.EQ.AND P4, PT, R8, 0x1c, PT ; /* 0x0000001c0800780c */
/* 0x000fe20003f82270 */
/*0550*/ @P2 IMAD.MOV.U32 R10, RZ, RZ, R18 ; /* 0x000000ffff0a2224 */
/* 0x000fc400078e0012 */
/*0560*/ @P2 IMAD.MOV.U32 R9, RZ, RZ, R14.reuse ; /* 0x000000ffff092224 */
/* 0x100fe400078e000e */
/*0570*/ @P1 IMAD.MOV.U32 R10, RZ, RZ, R14 ; /* 0x000000ffff0a1224 */
/* 0x000fe400078e000e */
/*0580*/ @P1 IMAD.MOV.U32 R9, RZ, RZ, R15 ; /* 0x000000ffff091224 */
/* 0x000fe200078e000f */
/*0590*/ LOP3.LUT P1, R19, R20, 0x1f, RZ, 0xc0, !PT ; /* 0x0000001f14137812 */
/* 0x000fe2000782c0ff */
/*05a0*/ @P0 IMAD.MOV.U32 R9, RZ, RZ, R16.reuse ; /* 0x000000ffff090224 */
/* 0x100fe200078e0010 */
/*05b0*/ @P0 MOV R10, R15 ; /* 0x0000000f000a0202 */
/* 0x000fe20000000f00 */
/*05c0*/ @P3 IMAD.MOV.U32 R9, RZ, RZ, R13 ; /* 0x000000ffff093224 */
/* 0x000fe400078e000d */
/*05d0*/ @P3 IMAD.MOV.U32 R10, RZ, RZ, R16 ; /* 0x000000ffff0a3224 */
/* 0x000fc400078e0010 */
/*05e0*/ @P4 IMAD.MOV.U32 R10, RZ, RZ, R13 ; /* 0x000000ffff0a4224 */
/* 0x000fe400078e000d */
/*05f0*/ IMAD.MOV.U32 R8, RZ, RZ, R9 ; /* 0x000000ffff087224 */
/* 0x000fc800078e0009 */
/*0600*/ @!P1 BRA 0x780 ; /* 0x0000017000009947 */
/* 0x000fea0003800000 */
/*0610*/ IADD3 R9, -R12, 0x4, RZ ; /* 0x000000040c097810 */
/* 0x000fe40007ffe1ff */
/*0620*/ SHF.L.U32 R11, R8, R19.reuse, RZ ; /* 0x00000013080b7219 */
/* 0x080fe400000006ff */
/*0630*/ SHF.L.U32 R20, R10, R19, RZ ; /* 0x000000130a147219 */
/* 0x000fe200000006ff */
/*0640*/ IMAD.SHL.U32 R9, R9, 0x4, RZ ; /* 0x0000000409097824 */
/* 0x000fca00078e00ff */
/*0650*/ ISETP.EQ.AND P0, PT, R9.reuse, RZ, PT ; /* 0x000000ff0900720c */
/* 0x040fe40003f02270 */
/*0660*/ ISETP.EQ.AND P1, PT, R9.reuse, 0x4, PT ; /* 0x000000040900780c */
/* 0x040fe40003f22270 */
/*0670*/ ISETP.EQ.AND P2, PT, R9.reuse, 0x8, PT ; /* 0x000000080900780c */
/* 0x040fe40003f42270 */
/*0680*/ ISETP.EQ.AND P3, PT, R9, 0xc, PT ; /* 0x0000000c0900780c */
/* 0x000fce0003f62270 */
/*0690*/ @P0 IMAD.MOV.U32 R12, RZ, RZ, R6 ; /* 0x000000ffff0c0224 */
/* 0x000fe200078e0006 */
/*06a0*/ ISETP.EQ.AND P0, PT, R9.reuse, 0x10, PT ; /* 0x000000100900780c */
/* 0x040fe20003f02270 */
/*06b0*/ @P1 IMAD.MOV.U32 R12, RZ, RZ, R17 ; /* 0x000000ffff0c1224 */
/* 0x000fe200078e0011 */
/*06c0*/ ISETP.EQ.AND P1, PT, R9.reuse, 0x14, PT ; /* 0x000000140900780c */
/* 0x040fe40003f22270 */
/*06d0*/ @P2 MOV R12, R18 ; /* 0x00000012000c2202 */
/* 0x000fe20000000f00 */
/*06e0*/ @P3 IMAD.MOV.U32 R12, RZ, RZ, R14 ; /* 0x000000ffff0c3224 */
/* 0x000fe200078e000e */
/*06f0*/ ISETP.EQ.AND P2, PT, R9, 0x18, PT ; /* 0x000000180900780c */
/* 0x000fe40003f42270 */
/*0700*/ IADD3 R9, -R19, 0x20, RZ ; /* 0x0000002013097810 */
/* 0x000fc80007ffe1ff */
/*0710*/ SHF.R.U32.HI R8, RZ, R9, R10 ; /* 0x00000009ff087219 */
/* 0x000fe2000001160a */
/*0720*/ @P0 IMAD.MOV.U32 R12, RZ, RZ, R15 ; /* 0x000000ffff0c0224 */
/* 0x000fe400078e000f */
/*0730*/ @P1 IMAD.MOV.U32 R12, RZ, RZ, R16 ; /* 0x000000ffff0c1224 */
/* 0x000fe400078e0010 */
/*0740*/ IMAD.IADD R8, R8, 0x1, R11 ; /* 0x0000000108087824 */
/* 0x000fe400078e020b */
/*0750*/ @P2 IMAD.MOV.U32 R12, RZ, RZ, R13 ; /* 0x000000ffff0c2224 */
/* 0x000fca00078e000d */
/*0760*/ SHF.R.U32.HI R9, RZ, R9, R12 ; /* 0x00000009ff097219 */
/* 0x000fca000001160c */
/*0770*/ IMAD.IADD R10, R9, 0x1, R20 ; /* 0x00000001090a7824 */
/* 0x000fe400078e0214 */
/*0780*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0790*/ SHF.L.U32.HI R13, R10.reuse, 0x2, R8 ; /* 0x000000020a0d7819 */
/* 0x040fe20000010608 */
/*07a0*/ IMAD.SHL.U32 R12, R10, 0x4, RZ ; /* 0x000000040a0c7824 */
/* 0x000fe200078e00ff */
/*07b0*/ LOP3.LUT P1, R7, R7, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000007077812 */
/* 0x000fe4000782c0ff */
/*07c0*/ SHF.R.U32.HI R9, RZ, 0x1f, R13 ; /* 0x0000001fff097819 */
/* 0x000fc8000001160d */
/*07d0*/ ISETP.NE.AND P0, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x000fe40003f05270 */
/*07e0*/ LEA.HI R8, R8, R9, RZ, 0x2 ; /* 0x0000000908087211 */
/* 0x000fd600078f10ff */
/*07f0*/ @P0 LOP3.LUT R13, RZ, R13, RZ, 0x33, !PT ; /* 0x0000000dff0d0212 */
/* 0x000fe400078e33ff */
/*0800*/ @P0 LOP3.LUT R12, RZ, R12, RZ, 0x33, !PT ; /* 0x0000000cff0c0212 */
/* 0x000fe400078e33ff */
/*0810*/ @P0 LOP3.LUT R7, R7, 0x80000000, RZ, 0x3c, !PT ; /* 0x8000000007070812 */
/* 0x000fe400078e3cff */
/*0820*/ I2F.F64.S64 R10, R12 ; /* 0x0000000c000a7312 */
/* 0x000e240000301c00 */
/*0830*/ ISETP.NE.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fe20003f05270 */
/*0840*/ IMAD.MOV R7, RZ, RZ, -R8 ; /* 0x000000ffff077224 */
/* 0x000fca00078e0a08 */
/*0850*/ @P1 MOV R8, R7 ; /* 0x0000000700081202 */
/* 0x000fe20000000f00 */
/*0860*/ DMUL R10, R10, c[0x2][0x0] ; /* 0x008000000a0a7a28 */
/* 0x001e140000000000 */
/*0870*/ F2F.F32.F64 R10, R10 ; /* 0x0000000a000a7310 */
/* 0x001e240000301000 */
/*0880*/ FSEL R9, R10, -R10, !P0 ; /* 0x8000000a0a097208 */
/* 0x001fe20004000000 */
/*0890*/ BRA 0x8c0 ; /* 0x0000002000007947 */
/* 0x000fea0003800000 */
/*08a0*/ FMUL R9, RZ, R7 ; /* 0x00000007ff097220 */
/* 0x000fe40000400000 */
/*08b0*/ IMAD.MOV.U32 R8, RZ, RZ, RZ ; /* 0x000000ffff087224 */
/* 0x000fe400078e00ff */
/*08c0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*08d0*/ LOP3.LUT P1, RZ, R8.reuse, 0x1, RZ, 0xc0, !PT ; /* 0x0000000108ff7812 */
/* 0x040fe2000782c0ff */
/*08e0*/ IMAD.MOV.U32 R10, RZ, RZ, 0x3c0885e4 ; /* 0x3c0885e4ff0a7424 */
/* 0x000fe200078e00ff */
/*08f0*/ LOP3.LUT P0, RZ, R8, 0x2, RZ, 0xc0, !PT ; /* 0x0000000208ff7812 */
/* 0x000fe2000780c0ff */
/*0900*/ FMUL R20, R9.reuse, R9 ; /* 0x0000000909147220 */
/* 0x040fe20000400000 */
/*0910*/ FSEL R9, R9, 1, !P1 ; /* 0x3f80000009097808 */
/* 0x000fe20004800000 */
/*0920*/ IMAD.MOV.U32 R12, RZ, RZ, 0x3e2aaaa8 ; /* 0x3e2aaaa8ff0c7424 */
/* 0x000fe200078e00ff */
/*0930*/ FSEL R10, R10, 0.041666727513074874878, !P1 ; /* 0x3d2aaabb0a0a7808 */
/* 0x000fe20004800000 */
/*0940*/ IMAD.MOV.U32 R7, RZ, RZ, -0x46b2bead ; /* 0xb94d4153ff077424 */
/* 0x000fc600078e00ff */
/*0950*/ FSEL R8, -R12, -0.4999999701976776123, !P1 ; /* 0xbeffffff0c087808 */
/* 0x000fc60004800100 */
/*0960*/ @P1 IMAD.MOV.U32 R11, RZ, RZ, 0x37cbac00 ; /* 0x37cbac00ff0b1424 */
/* 0x000fc800078e00ff */
/*0970*/ @P1 FFMA R7, R20, R11, -0.0013887860113754868507 ; /* 0xbab607ed14071423 */
/* 0x000fc8000000000b */
/*0980*/ FFMA R7, R20.reuse, R7, R10 ; /* 0x0000000714077223 */
/* 0x040fe4000000000a */
/*0990*/ FFMA R10, R9, R20, RZ ; /* 0x00000014090a7223 */
/* 0x000fe400000000ff */
/*09a0*/ FFMA R7, R20, R7, R8 ; /* 0x0000000714077223 */
/* 0x000fc80000000008 */
/*09b0*/ FFMA R7, R7, R10, R9 ; /* 0x0000000a07077223 */
/* 0x000fe40000000009 */
/*09c0*/ IMAD.MOV.U32 R9, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff097624 */
/* 0x000fe400078e00ff */
/*09d0*/ @P0 FFMA R7, R7, -1, RZ ; /* 0xbf80000007070823 */
/* 0x000fe400000000ff */
/*09e0*/ IMAD R8, R9, c[0x0][0xc], R4 ; /* 0x0000030009087a24 */
/* 0x000fc600078e0204 */
/*09f0*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x0001e2000c101906 */
/*0a00*/ IMAD.MOV.U32 R4, RZ, RZ, R8.reuse ; /* 0x000000ffff047224 */
/* 0x100fe200078e0008 */
/*0a10*/ ISETP.GE.U32.AND P0, PT, R8, c[0x0][0x170], PT ; /* 0x00005c0008007a0c */
/* 0x000fe40003f06070 */
/*0a20*/ SHF.R.S32.HI R9, RZ, 0x1f, R8 ; /* 0x0000001fff097819 */
/* 0x000fc80000011408 */
/*0a30*/ ISETP.GE.U32.AND.EX P0, PT, R9, c[0x0][0x174], PT, P0 ; /* 0x00005d0009007a0c */
/* 0x000fda0003f06100 */
/*0a40*/ @!P0 BRA 0xf0 ; /* 0xfffff6a000008947 */
/* 0x001fea000383ffff */
/*0a50*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0a60*/ BRA 0xa60; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0a70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0aa0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ab0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ac0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ad0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ae0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0af0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3SinPfmmf
.globl _Z3SinPfmmf
.p2align 8
.type _Z3SinPfmmf,@function
_Z3SinPfmmf:
s_clause 0x1
s_load_b32 s6, s[0:1], 0x2c
s_load_b64 s[2:3], s[0:1], 0x10
s_add_u32 s4, s0, 32
s_addc_u32 s5, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s7, s6, 0xffff
s_mov_b32 s6, exec_lo
v_mad_u64_u32 v[5:6], null, s15, s7, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v6, 31, v5
v_cmpx_gt_u64_e64 s[2:3], v[5:6]
s_cbranch_execz .LBB0_7
s_load_b128 s[8:11], s[0:1], 0x0
s_load_b32 s12, s[4:5], 0x0
s_load_b32 s4, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s10, -1
s_addc_u32 s1, s11, -1
s_mul_i32 s5, s0, s3
s_mul_hi_u32 s6, s0, s2
s_mul_i32 s1, s1, s2
s_add_i32 s5, s6, s5
s_mul_i32 s0, s0, s2
s_add_i32 s1, s5, s1
s_mov_b32 s10, 0xb94c1982
s_lshl_b64 s[0:1], s[0:1], 2
s_mov_b32 s11, 0x37d75334
s_add_u32 s5, s8, s0
s_addc_u32 s6, s9, s1
s_add_i32 s15, s15, s12
s_mov_b32 s8, 0
v_mad_u64_u32 v[1:2], null, s15, s7, v[0:1]
s_mul_i32 s7, s12, s7
s_mov_b32 s9, 0x7fffff
s_branch .LBB0_3
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_dual_mul_f32 v7, v5, v5 :: v_dual_and_b32 v10, 1, v6
v_cmp_class_f32_e64 s0, v0, 0x1f8
v_lshlrev_b32_e32 v6, 30, v6
v_fmaak_f32 v8, s10, v7, 0x3c0881c4
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cmp_eq_u32_e32 vcc_lo, 0, v10
v_and_b32_e32 v6, 0x80000000, v6
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmaak_f32 v8, v7, v8, 0xbe2aaa9d
v_dual_fmaak_f32 v9, s11, v7, 0xbab64f3b :: v_dual_mul_f32 v8, v7, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fmaak_f32 v9, v7, v9, 0x3d2aabf7
v_fmac_f32_e32 v5, v5, v8
v_xor_b32_e32 v8, v2, v0
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmaak_f32 v9, v7, v9, 0xbf000004
v_fma_f32 v7, v7, v9, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
v_cndmask_b32_e32 v5, v7, v5, vcc_lo
v_cmp_le_u64_e32 vcc_lo, s[2:3], v[1:2]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_xor3_b32 v5, v8, v6, v5
s_or_b32 s8, vcc_lo, s8
v_cndmask_b32_e64 v0, 0x7fc00000, v5, s0
v_dual_mov_b32 v6, v2 :: v_dual_mov_b32 v5, v1
v_add_nc_u32_e32 v1, s7, v1
global_store_b32 v[3:4], v0, off
s_and_not1_b32 exec_lo, exec_lo, s8
s_cbranch_execz .LBB0_7
.LBB0_3:
v_lshlrev_b64 v[3:4], 2, v[5:6]
s_mov_b32 s1, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v3, vcc_lo, s5, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s6, v4, vcc_lo
global_load_b32 v0, v[3:4], off
s_waitcnt vmcnt(0)
v_mul_f32_e32 v0, s4, v0
s_delay_alu instid0(VALU_DEP_1)
v_and_b32_e32 v2, 0x7fffffff, v0
v_cmpx_ngt_f32_e64 0x48000000, |v0|
s_xor_b32 s12, exec_lo, s1
s_cbranch_execz .LBB0_5
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_and_or_b32 v15, v2, s9, 0x800000
v_mov_b32_e32 v7, 0
v_lshrrev_b32_e32 v12, 23, v2
v_mad_u64_u32 v[5:6], null, v15, 0xfe5163ab, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v13, 0xffffff88, v12
v_cmp_lt_u32_e32 vcc_lo, 63, v13
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[8:9], null, v15, 0x3c439041, v[6:7]
v_cndmask_b32_e64 v14, 0, 0xffffffc0, vcc_lo
v_mov_b32_e32 v6, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v14, v14, v13
v_mad_u64_u32 v[9:10], null, v15, 0xdb629599, v[6:7]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_lt_u32_e64 s0, 31, v14
v_cndmask_b32_e64 v16, 0, 0xffffffe0, s0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_dual_mov_b32 v6, v10 :: v_dual_cndmask_b32 v5, v9, v5
v_add_nc_u32_e32 v16, v16, v14
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[10:11], null, v15, 0xf534ddc0, v[6:7]
v_cmp_lt_u32_e64 s1, 31, v16
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_mov_b32_e32 v6, v11
v_cndmask_b32_e32 v8, v10, v8, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[11:12], null, v15, 0xfc2757d1, v[6:7]
v_cndmask_b32_e64 v5, v8, v5, s0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mov_b32_e32 v6, v12
v_mad_u64_u32 v[12:13], null, v15, 0x4e441529, v[6:7]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mov_b32_e32 v6, v13
v_mad_u64_u32 v[13:14], null, v15, 0xa2f9836e, v[6:7]
v_cndmask_b32_e64 v6, 0, 0xffffffe0, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_dual_cndmask_b32 v7, v12, v10 :: v_dual_add_nc_u32 v6, v6, v16
v_dual_cndmask_b32 v13, v13, v11 :: v_dual_cndmask_b32 v12, v14, v12
v_cndmask_b32_e32 v11, v11, v9, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cmp_eq_u32_e32 vcc_lo, 0, v6
v_cndmask_b32_e64 v10, v13, v7, s0
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_cndmask_b32_e64 v12, v12, v13, s0
v_cndmask_b32_e64 v7, v7, v11, s0
v_sub_nc_u32_e32 v13, 32, v6
v_cndmask_b32_e64 v11, v11, v8, s0
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_cndmask_b32_e64 v12, v12, v10, s1
v_cndmask_b32_e64 v10, v10, v7, s1
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_cndmask_b32_e64 v7, v7, v11, s1
v_cndmask_b32_e64 v5, v11, v5, s1
v_alignbit_b32 v14, v12, v10, v13
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_alignbit_b32 v9, v10, v7, v13
v_cndmask_b32_e32 v6, v14, v12, vcc_lo
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_alignbit_b32 v12, v7, v5, v13
v_cndmask_b32_e32 v8, v9, v10, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_bfe_u32 v9, v6, 29, 1
v_cndmask_b32_e32 v7, v12, v7, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_alignbit_b32 v10, v6, v8, 30
v_sub_nc_u32_e32 v11, 0, v9
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_alignbit_b32 v8, v8, v7, 30
v_alignbit_b32 v5, v7, v5, 30
v_xor_b32_e32 v10, v10, v11
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_xor_b32_e32 v7, v8, v11
v_xor_b32_e32 v5, v5, v11
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_clz_i32_u32_e32 v12, v10
v_min_u32_e32 v12, 32, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v8, 31, v12
v_lshlrev_b32_e32 v14, 23, v12
v_alignbit_b32 v10, v10, v7, v8
v_alignbit_b32 v5, v7, v5, v8
v_lshrrev_b32_e32 v8, 29, v6
v_lshrrev_b32_e32 v6, 30, v6
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_alignbit_b32 v7, v10, v5, 9
v_lshlrev_b32_e32 v8, 31, v8
v_lshrrev_b32_e32 v10, 9, v10
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_nc_u32_e32 v6, v9, v6
v_clz_i32_u32_e32 v11, v7
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
v_or_b32_e32 v13, 0.5, v8
v_min_u32_e32 v11, 32, v11
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v13, v13, v14
v_sub_nc_u32_e32 v15, 31, v11
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_alignbit_b32 v5, v7, v5, v15
v_or_b32_e32 v7, v10, v13
v_add_lshl_u32 v10, v11, v12, 23
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_lshrrev_b32_e32 v5, 9, v5
v_mul_f32_e32 v11, 0x3fc90fda, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v5, v5, v10
v_fma_f32 v10, v7, 0x3fc90fda, -v11
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v5, 0x33000000, v5
v_fmac_f32_e32 v10, 0x33a22168, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_or_b32_e32 v5, v5, v8
v_fmac_f32_e32 v10, 0x3fc90fda, v5
s_delay_alu instid0(VALU_DEP_1)
v_add_f32_e32 v5, v11, v10
.LBB0_5:
s_and_not1_saveexec_b32 s0, s12
s_cbranch_execz .LBB0_2
v_mul_f32_e64 v5, 0x3f22f983, |v0|
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_rndne_f32_e32 v6, v5
v_fma_f32 v5, v6, 0xbfc90fda, |v0|
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v5, 0xb3a22168, v6
v_fmac_f32_e32 v5, 0xa7c234c4, v6
v_cvt_i32_f32_e32 v6, v6
s_branch .LBB0_2
.LBB0_7:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3SinPfmmf
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 17
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3SinPfmmf, .Lfunc_end0-_Z3SinPfmmf
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 8
.value_kind: by_value
- .offset: 16
.size: 8
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3SinPfmmf
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z3SinPfmmf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 17
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000f96a4_00000000-6_Sin.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z25__device_stub__Z3SinPfmmfPfmmf
.type _Z25__device_stub__Z3SinPfmmfPfmmf, @function
_Z25__device_stub__Z3SinPfmmfPfmmf:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movss %xmm0, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3SinPfmmf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z25__device_stub__Z3SinPfmmfPfmmf, .-_Z25__device_stub__Z3SinPfmmfPfmmf
.globl _Z3SinPfmmf
.type _Z3SinPfmmf, @function
_Z3SinPfmmf:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z25__device_stub__Z3SinPfmmfPfmmf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z3SinPfmmf, .-_Z3SinPfmmf
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z3SinPfmmf"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z3SinPfmmf(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "Sin.hip"
.globl _Z18__device_stub__SinPfmmf # -- Begin function _Z18__device_stub__SinPfmmf
.p2align 4, 0x90
.type _Z18__device_stub__SinPfmmf,@function
_Z18__device_stub__SinPfmmf: # @_Z18__device_stub__SinPfmmf
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movss %xmm0, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3SinPfmmf, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z18__device_stub__SinPfmmf, .Lfunc_end0-_Z18__device_stub__SinPfmmf
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3SinPfmmf, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3SinPfmmf,@object # @_Z3SinPfmmf
.section .rodata,"a",@progbits
.globl _Z3SinPfmmf
.p2align 3, 0x0
_Z3SinPfmmf:
.quad _Z18__device_stub__SinPfmmf
.size _Z3SinPfmmf, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z3SinPfmmf"
.size .L__unnamed_1, 12
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__SinPfmmf
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3SinPfmmf
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /**
* Copyright 1993-2012 NVIDIA Corporation. All rights reserved.
*
* Please refer to the NVIDIA end user license agreement (EULA) associated
* with this source code for terms and conditions that govern your use of
* this software. Any use, reproduction, disclosure, or distribution of
* this software and related documentation outside the terms of the EULA
* is strictly prohibited.
*/
#include <stdio.h>
#include <stdlib.h>
#include <algorithm>
#include <utility>
#include <iostream>
#include <bitset>
#include <math.h>
#include <time.h>
#include <chrono>
#include <cuda.h>
/**
* This macro checks return value of the CUDA runtime call and exits
* the application if the call failed.
*
* See cuda.h for error code descriptions.
*/
#ifndef BLOCK_SIZE
#define BLOCK_SIZE 1024
#endif
#ifndef ELAPSED_TIME
#define ELAPSED_TIME 0
#endif
#ifndef EXP_BITS_SIZE
#define EXP_BITS_SIZE 10
#endif
void print(int* h_data, int n) {
std::cout << "\n";
for (int i = 0; i < n; i++) {
std::cout << h_data[i] << " ";
}
std::cout << "\n";
}
void cudaTest(cudaError_t error) {
if (error != cudaSuccess) {
printf("cuda returned error %s (code %d), line(%d)\n",
cudaGetErrorString(error), error, __LINE__);
exit(EXIT_FAILURE);
}
}
template<int BITS_NUMBER = 64>
__global__ void radix_sort(int *d_vec, int *d_aux, int *d_seg,
int num_segments) {
int bx = blockIdx.x;
int tx = threadIdx.x;
if (bx * blockDim.x + tx < num_segments) {
int begin = d_seg[bx * blockDim.x + tx];
int end = d_seg[bx * blockDim.x + tx + 1];
int i, exp = 0;
for (exp = 0; exp < BITS_NUMBER; exp++) {
int one = 0;
int zero = 0;
for (i = begin; i < end; i++) {
int x = (d_vec[i] >> exp) & 1;
one += x;
zero += (1 - x);
}
one += zero;
for (i = end - 1; i >= begin; i--) {
int x = (d_vec[i] >> exp) & 1;
int index = begin + x * (one - 1) + (1 - x) * (zero - 1);
d_aux[index] = d_vec[i];
one -= x;
zero -= (1 - x);
}
for (i = begin; i < end; i++)
d_vec[i] = d_aux[i];
}
}
}
int main(int argc, char **argv) {
int num_of_segments;
int num_of_elements;
int i;
scanf("%d", &num_of_segments);
int mem_size_seg = sizeof(int) * (num_of_segments + 1);
int *h_seg = (int *) malloc(mem_size_seg);
for (i = 0; i < num_of_segments + 1; i++)
scanf("%d", &h_seg[i]);
scanf("%d", &num_of_elements);
int mem_size_vec = sizeof(int) * num_of_elements;
int *h_vec = (int *) malloc(mem_size_vec);
for (i = 0; i < num_of_elements; i++)
scanf("%d", &h_vec[i]);
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
// Allocate device memory
int *d_seg, *d_vec, *d_aux;
cudaTest(cudaMalloc((void **) &d_seg, mem_size_seg));
cudaTest(cudaMalloc((void **) &d_vec, mem_size_vec));
cudaTest(cudaMalloc((void **) &d_aux, mem_size_vec));
cudaTest(cudaMemcpy(d_seg, h_seg, mem_size_seg, cudaMemcpyHostToDevice));
cudaTest(cudaMemcpy(d_vec, h_vec, mem_size_vec, cudaMemcpyHostToDevice));
int blocksize = BLOCK_SIZE;
dim3 threads(blocksize, 1);
dim3 grid((num_of_segments - 1) / blocksize + 1, 1);
cudaEventRecord(start);
radix_sort<EXP_BITS_SIZE> <<<grid, threads>>>(d_vec, d_aux, d_seg,
num_of_segments);
cudaEventRecord(stop);
//cudaDeviceSynchronize();
//cudaTest(cudaPeekAtLastError());
cudaTest(cudaMemcpy(h_seg, d_seg, mem_size_seg, cudaMemcpyDeviceToHost));
cudaTest(cudaMemcpy(h_vec, d_vec, mem_size_vec, cudaMemcpyDeviceToHost));
if (ELAPSED_TIME == 1) {
cudaEventSynchronize(stop);
float milliseconds = 0;
cudaEventElapsedTime(&milliseconds, start, stop);
std::cout << milliseconds << "\n";
} else
print(h_vec, num_of_elements);
free(h_seg);
free(h_vec);
cudaFree(d_seg);
cudaFree(d_vec);
cudaFree(d_aux);
//cudaDeviceReset();
return 0;
}
/**
* // cudaDeviceReset causes the driver to clean up all state. While
// not mandatory in normal operation, it is good practice. It is also
// needed to ensure correct operation when the application is being
// profiled. Calling cudaDeviceReset causes all profile data to be
// flushed before the application exits
cudaDeviceReset();
*/
/*
printf("thread=%d | aux=%d %d %d %d\n", bx * blockDim.x + tx, d_aux[begin], d_aux[begin + 1], d_aux[begin + 2], d_aux[begin + 3]);
int devID = 0;
cudaDeviceProp deviceProp;
cudaTest(cudaGetDeviceProperties(&deviceProp, devID));
unsigned int multiprocessorNumber = deviceProp.multiProcessorCount;
unsigned int sharedMemoryTotal = deviceProp.sharedMemPerBlock/(sizeof(int));
std::cout << "multiprocessorNumber: " << multiprocessorNumber << "\n";
std::cout << "sharedMemoryTotal: " << sharedMemoryTotal << "\n";
std::cout << "numberOfSegmentsPerBlock: " << sharedMemoryTotal << "\n";
*/ | .file "tmpxft_00170831_00000000-6_globalv1.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.section .text._Z10radix_sortILi10EEvPiS0_S0_i,"axG",@progbits,_Z10radix_sortILi10EEvPiS0_S0_i,comdat
.weak _Z10radix_sortILi10EEvPiS0_S0_i
.type _Z10radix_sortILi10EEvPiS0_S0_i, @function
_Z10radix_sortILi10EEvPiS0_S0_i:
.LFB4544:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
movq %rdi, 8(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 4(%rsp)
leaq 8(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 24(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L5
.L1:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L6
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L5:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z10radix_sortILi10EEvPiS0_S0_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L1
.L6:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4544:
.size _Z10radix_sortILi10EEvPiS0_S0_i, .-_Z10radix_sortILi10EEvPiS0_S0_i
.text
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB4190:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4190:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "\n"
.LC1:
.string " "
.text
.globl _Z5printPii
.type _Z5printPii, @function
_Z5printPii:
.LFB4183:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $8, %rsp
.cfi_def_cfa_offset 48
movq %rdi, %r12
movl %esi, %ebp
movl $1, %edx
leaq .LC0(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
testl %ebp, %ebp
jle .L10
movq %r12, %rbx
movslq %ebp, %rbp
leaq (%r12,%rbp,4), %r13
leaq _ZSt4cout(%rip), %r12
leaq .LC1(%rip), %rbp
.L11:
movl (%rbx), %esi
movq %r12, %rdi
call _ZNSolsEi@PLT
movq %rax, %rdi
movl $1, %edx
movq %rbp, %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
addq $4, %rbx
cmpq %r13, %rbx
jne .L11
.L10:
movl $1, %edx
leaq .LC0(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4183:
.size _Z5printPii, .-_Z5printPii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC2:
.string "cuda returned error %s (code %d), line(%d)\n"
.text
.globl _Z8cudaTest9cudaError
.type _Z8cudaTest9cudaError, @function
_Z8cudaTest9cudaError:
.LFB4184:
.cfi_startproc
endbr64
testl %edi, %edi
jne .L19
ret
.L19:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movl %edi, %ebx
call cudaGetErrorString@PLT
movq %rax, %rdx
movl $51, %r8d
movl %ebx, %ecx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.cfi_endproc
.LFE4184:
.size _Z8cudaTest9cudaError, .-_Z8cudaTest9cudaError
.section .rodata.str1.1
.LC3:
.string "%d"
.text
.globl main
.type main, @function
main:
.LFB4187:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $104, %rsp
.cfi_def_cfa_offset 160
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 16(%rsp), %rsi
leaq .LC3(%rip), %rdi
call __isoc23_scanf@PLT
movl 16(%rsp), %ebx
leal 4(,%rbx,4), %r15d
movslq %r15d, %r15
movq %r15, %rdi
call malloc@PLT
movq %rax, 8(%rsp)
testl %ebx, %ebx
js .L21
movq %rax, %rbp
movl $0, %ebx
leaq .LC3(%rip), %r12
.L22:
movq %rbp, %rsi
movq %r12, %rdi
movl $0, %eax
call __isoc23_scanf@PLT
addl $1, %ebx
addq $4, %rbp
cmpl %ebx, 16(%rsp)
jge .L22
.L21:
leaq 20(%rsp), %rsi
leaq .LC3(%rip), %rdi
movl $0, %eax
call __isoc23_scanf@PLT
movl 20(%rsp), %ebx
leal 0(,%rbx,4), %r13d
movslq %r13d, %r13
movq %r13, %rdi
call malloc@PLT
movq %rax, %r14
testl %ebx, %ebx
jle .L23
movq %rax, %rbp
movl $0, %ebx
leaq .LC3(%rip), %r12
.L24:
movq %rbp, %rsi
movq %r12, %rdi
movl $0, %eax
call __isoc23_scanf@PLT
addl $1, %ebx
addq $4, %rbp
cmpl %ebx, 20(%rsp)
jg .L24
.L23:
leaq 24(%rsp), %rdi
call cudaEventCreate@PLT
leaq 32(%rsp), %rdi
call cudaEventCreate@PLT
leaq 40(%rsp), %rdi
movq %r15, %rsi
call cudaMalloc@PLT
movl %eax, %edi
call _Z8cudaTest9cudaError
leaq 48(%rsp), %rdi
movq %r13, %rsi
call cudaMalloc@PLT
movl %eax, %edi
call _Z8cudaTest9cudaError
leaq 56(%rsp), %rdi
movq %r13, %rsi
call cudaMalloc@PLT
movl %eax, %edi
call _Z8cudaTest9cudaError
movl $1, %ecx
movq %r15, %rdx
movq 8(%rsp), %rsi
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
call _Z8cudaTest9cudaError
movl $1, %ecx
movq %r13, %rdx
movq %r14, %rsi
movq 48(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
call _Z8cudaTest9cudaError
movl $1024, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl 16(%rsp), %edx
leal 1022(%rdx), %eax
subl $1, %edx
cmovns %edx, %eax
sarl $10, %eax
addl $1, %eax
movl %eax, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $0, %esi
movq 24(%rsp), %rdi
call cudaEventRecord@PLT
movl 72(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 64(%rsp), %rdx
movq 76(%rsp), %rdi
movl 84(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L30
.L25:
movl $0, %esi
movq 32(%rsp), %rdi
call cudaEventRecord@PLT
movl $2, %ecx
movq %r15, %rdx
movq 40(%rsp), %rsi
movq 8(%rsp), %rbx
movq %rbx, %rdi
call cudaMemcpy@PLT
movl %eax, %edi
call _Z8cudaTest9cudaError
movl $2, %ecx
movq %r13, %rdx
movq 48(%rsp), %rsi
movq %r14, %rdi
call cudaMemcpy@PLT
movl %eax, %edi
call _Z8cudaTest9cudaError
movl 20(%rsp), %esi
movq %r14, %rdi
call _Z5printPii
movq %rbx, %rdi
call free@PLT
movq %r14, %rdi
call free@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq 48(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rdi
call cudaFree@PLT
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L31
movl $0, %eax
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L30:
.cfi_restore_state
movl 16(%rsp), %ecx
movq 40(%rsp), %rdx
movq 56(%rsp), %rsi
movq 48(%rsp), %rdi
call _Z10radix_sortILi10EEvPiS0_S0_i
jmp .L25
.L31:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4187:
.size main, .-main
.section .rodata.str1.8
.align 8
.LC4:
.string "_Z10radix_sortILi10EEvPiS0_S0_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB4215:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z10radix_sortILi10EEvPiS0_S0_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4215:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /**
* Copyright 1993-2012 NVIDIA Corporation. All rights reserved.
*
* Please refer to the NVIDIA end user license agreement (EULA) associated
* with this source code for terms and conditions that govern your use of
* this software. Any use, reproduction, disclosure, or distribution of
* this software and related documentation outside the terms of the EULA
* is strictly prohibited.
*/
#include <stdio.h>
#include <stdlib.h>
#include <algorithm>
#include <utility>
#include <iostream>
#include <bitset>
#include <math.h>
#include <time.h>
#include <chrono>
#include <cuda.h>
/**
* This macro checks return value of the CUDA runtime call and exits
* the application if the call failed.
*
* See cuda.h for error code descriptions.
*/
#ifndef BLOCK_SIZE
#define BLOCK_SIZE 1024
#endif
#ifndef ELAPSED_TIME
#define ELAPSED_TIME 0
#endif
#ifndef EXP_BITS_SIZE
#define EXP_BITS_SIZE 10
#endif
void print(int* h_data, int n) {
std::cout << "\n";
for (int i = 0; i < n; i++) {
std::cout << h_data[i] << " ";
}
std::cout << "\n";
}
void cudaTest(cudaError_t error) {
if (error != cudaSuccess) {
printf("cuda returned error %s (code %d), line(%d)\n",
cudaGetErrorString(error), error, __LINE__);
exit(EXIT_FAILURE);
}
}
template<int BITS_NUMBER = 64>
__global__ void radix_sort(int *d_vec, int *d_aux, int *d_seg,
int num_segments) {
int bx = blockIdx.x;
int tx = threadIdx.x;
if (bx * blockDim.x + tx < num_segments) {
int begin = d_seg[bx * blockDim.x + tx];
int end = d_seg[bx * blockDim.x + tx + 1];
int i, exp = 0;
for (exp = 0; exp < BITS_NUMBER; exp++) {
int one = 0;
int zero = 0;
for (i = begin; i < end; i++) {
int x = (d_vec[i] >> exp) & 1;
one += x;
zero += (1 - x);
}
one += zero;
for (i = end - 1; i >= begin; i--) {
int x = (d_vec[i] >> exp) & 1;
int index = begin + x * (one - 1) + (1 - x) * (zero - 1);
d_aux[index] = d_vec[i];
one -= x;
zero -= (1 - x);
}
for (i = begin; i < end; i++)
d_vec[i] = d_aux[i];
}
}
}
int main(int argc, char **argv) {
int num_of_segments;
int num_of_elements;
int i;
scanf("%d", &num_of_segments);
int mem_size_seg = sizeof(int) * (num_of_segments + 1);
int *h_seg = (int *) malloc(mem_size_seg);
for (i = 0; i < num_of_segments + 1; i++)
scanf("%d", &h_seg[i]);
scanf("%d", &num_of_elements);
int mem_size_vec = sizeof(int) * num_of_elements;
int *h_vec = (int *) malloc(mem_size_vec);
for (i = 0; i < num_of_elements; i++)
scanf("%d", &h_vec[i]);
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
// Allocate device memory
int *d_seg, *d_vec, *d_aux;
cudaTest(cudaMalloc((void **) &d_seg, mem_size_seg));
cudaTest(cudaMalloc((void **) &d_vec, mem_size_vec));
cudaTest(cudaMalloc((void **) &d_aux, mem_size_vec));
cudaTest(cudaMemcpy(d_seg, h_seg, mem_size_seg, cudaMemcpyHostToDevice));
cudaTest(cudaMemcpy(d_vec, h_vec, mem_size_vec, cudaMemcpyHostToDevice));
int blocksize = BLOCK_SIZE;
dim3 threads(blocksize, 1);
dim3 grid((num_of_segments - 1) / blocksize + 1, 1);
cudaEventRecord(start);
radix_sort<EXP_BITS_SIZE> <<<grid, threads>>>(d_vec, d_aux, d_seg,
num_of_segments);
cudaEventRecord(stop);
//cudaDeviceSynchronize();
//cudaTest(cudaPeekAtLastError());
cudaTest(cudaMemcpy(h_seg, d_seg, mem_size_seg, cudaMemcpyDeviceToHost));
cudaTest(cudaMemcpy(h_vec, d_vec, mem_size_vec, cudaMemcpyDeviceToHost));
if (ELAPSED_TIME == 1) {
cudaEventSynchronize(stop);
float milliseconds = 0;
cudaEventElapsedTime(&milliseconds, start, stop);
std::cout << milliseconds << "\n";
} else
print(h_vec, num_of_elements);
free(h_seg);
free(h_vec);
cudaFree(d_seg);
cudaFree(d_vec);
cudaFree(d_aux);
//cudaDeviceReset();
return 0;
}
/**
* // cudaDeviceReset causes the driver to clean up all state. While
// not mandatory in normal operation, it is good practice. It is also
// needed to ensure correct operation when the application is being
// profiled. Calling cudaDeviceReset causes all profile data to be
// flushed before the application exits
cudaDeviceReset();
*/
/*
printf("thread=%d | aux=%d %d %d %d\n", bx * blockDim.x + tx, d_aux[begin], d_aux[begin + 1], d_aux[begin + 2], d_aux[begin + 3]);
int devID = 0;
cudaDeviceProp deviceProp;
cudaTest(cudaGetDeviceProperties(&deviceProp, devID));
unsigned int multiprocessorNumber = deviceProp.multiProcessorCount;
unsigned int sharedMemoryTotal = deviceProp.sharedMemPerBlock/(sizeof(int));
std::cout << "multiprocessorNumber: " << multiprocessorNumber << "\n";
std::cout << "sharedMemoryTotal: " << sharedMemoryTotal << "\n";
std::cout << "numberOfSegmentsPerBlock: " << sharedMemoryTotal << "\n";
*/ | /**
* Copyright 1993-2012 NVIDIA Corporation. All rights reserved.
*
* Please refer to the NVIDIA end user license agreement (EULA) associated
* with this source code for terms and conditions that govern your use of
* this software. Any use, reproduction, disclosure, or distribution of
* this software and related documentation outside the terms of the EULA
* is strictly prohibited.
*/
#include <stdio.h>
#include <stdlib.h>
#include <algorithm>
#include <utility>
#include <iostream>
#include <bitset>
#include <math.h>
#include <time.h>
#include <chrono>
#include <hip/hip_runtime.h>
/**
* This macro checks return value of the CUDA runtime call and exits
* the application if the call failed.
*
* See cuda.h for error code descriptions.
*/
#ifndef BLOCK_SIZE
#define BLOCK_SIZE 1024
#endif
#ifndef ELAPSED_TIME
#define ELAPSED_TIME 0
#endif
#ifndef EXP_BITS_SIZE
#define EXP_BITS_SIZE 10
#endif
void print(int* h_data, int n) {
std::cout << "\n";
for (int i = 0; i < n; i++) {
std::cout << h_data[i] << " ";
}
std::cout << "\n";
}
void cudaTest(hipError_t error) {
if (error != hipSuccess) {
printf("cuda returned error %s (code %d), line(%d)\n",
hipGetErrorString(error), error, __LINE__);
exit(EXIT_FAILURE);
}
}
template<int BITS_NUMBER = 64>
__global__ void radix_sort(int *d_vec, int *d_aux, int *d_seg,
int num_segments) {
int bx = blockIdx.x;
int tx = threadIdx.x;
if (bx * blockDim.x + tx < num_segments) {
int begin = d_seg[bx * blockDim.x + tx];
int end = d_seg[bx * blockDim.x + tx + 1];
int i, exp = 0;
for (exp = 0; exp < BITS_NUMBER; exp++) {
int one = 0;
int zero = 0;
for (i = begin; i < end; i++) {
int x = (d_vec[i] >> exp) & 1;
one += x;
zero += (1 - x);
}
one += zero;
for (i = end - 1; i >= begin; i--) {
int x = (d_vec[i] >> exp) & 1;
int index = begin + x * (one - 1) + (1 - x) * (zero - 1);
d_aux[index] = d_vec[i];
one -= x;
zero -= (1 - x);
}
for (i = begin; i < end; i++)
d_vec[i] = d_aux[i];
}
}
}
int main(int argc, char **argv) {
int num_of_segments;
int num_of_elements;
int i;
scanf("%d", &num_of_segments);
int mem_size_seg = sizeof(int) * (num_of_segments + 1);
int *h_seg = (int *) malloc(mem_size_seg);
for (i = 0; i < num_of_segments + 1; i++)
scanf("%d", &h_seg[i]);
scanf("%d", &num_of_elements);
int mem_size_vec = sizeof(int) * num_of_elements;
int *h_vec = (int *) malloc(mem_size_vec);
for (i = 0; i < num_of_elements; i++)
scanf("%d", &h_vec[i]);
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
// Allocate device memory
int *d_seg, *d_vec, *d_aux;
cudaTest(hipMalloc((void **) &d_seg, mem_size_seg));
cudaTest(hipMalloc((void **) &d_vec, mem_size_vec));
cudaTest(hipMalloc((void **) &d_aux, mem_size_vec));
cudaTest(hipMemcpy(d_seg, h_seg, mem_size_seg, hipMemcpyHostToDevice));
cudaTest(hipMemcpy(d_vec, h_vec, mem_size_vec, hipMemcpyHostToDevice));
int blocksize = BLOCK_SIZE;
dim3 threads(blocksize, 1);
dim3 grid((num_of_segments - 1) / blocksize + 1, 1);
hipEventRecord(start);
radix_sort<EXP_BITS_SIZE> <<<grid, threads>>>(d_vec, d_aux, d_seg,
num_of_segments);
hipEventRecord(stop);
//cudaDeviceSynchronize();
//cudaTest(cudaPeekAtLastError());
cudaTest(hipMemcpy(h_seg, d_seg, mem_size_seg, hipMemcpyDeviceToHost));
cudaTest(hipMemcpy(h_vec, d_vec, mem_size_vec, hipMemcpyDeviceToHost));
if (ELAPSED_TIME == 1) {
hipEventSynchronize(stop);
float milliseconds = 0;
hipEventElapsedTime(&milliseconds, start, stop);
std::cout << milliseconds << "\n";
} else
print(h_vec, num_of_elements);
free(h_seg);
free(h_vec);
hipFree(d_seg);
hipFree(d_vec);
hipFree(d_aux);
//cudaDeviceReset();
return 0;
}
/**
* // cudaDeviceReset causes the driver to clean up all state. While
// not mandatory in normal operation, it is good practice. It is also
// needed to ensure correct operation when the application is being
// profiled. Calling cudaDeviceReset causes all profile data to be
// flushed before the application exits
cudaDeviceReset();
*/
/*
printf("thread=%d | aux=%d %d %d %d\n", bx * blockDim.x + tx, d_aux[begin], d_aux[begin + 1], d_aux[begin + 2], d_aux[begin + 3]);
int devID = 0;
cudaDeviceProp deviceProp;
cudaTest(cudaGetDeviceProperties(&deviceProp, devID));
unsigned int multiprocessorNumber = deviceProp.multiProcessorCount;
unsigned int sharedMemoryTotal = deviceProp.sharedMemPerBlock/(sizeof(int));
std::cout << "multiprocessorNumber: " << multiprocessorNumber << "\n";
std::cout << "sharedMemoryTotal: " << sharedMemoryTotal << "\n";
std::cout << "numberOfSegmentsPerBlock: " << sharedMemoryTotal << "\n";
*/ |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | /**
* Copyright 1993-2012 NVIDIA Corporation. All rights reserved.
*
* Please refer to the NVIDIA end user license agreement (EULA) associated
* with this source code for terms and conditions that govern your use of
* this software. Any use, reproduction, disclosure, or distribution of
* this software and related documentation outside the terms of the EULA
* is strictly prohibited.
*/
#include <stdio.h>
#include <stdlib.h>
#include <algorithm>
#include <utility>
#include <iostream>
#include <bitset>
#include <math.h>
#include <time.h>
#include <chrono>
#include <hip/hip_runtime.h>
/**
* This macro checks return value of the CUDA runtime call and exits
* the application if the call failed.
*
* See cuda.h for error code descriptions.
*/
#ifndef BLOCK_SIZE
#define BLOCK_SIZE 1024
#endif
#ifndef ELAPSED_TIME
#define ELAPSED_TIME 0
#endif
#ifndef EXP_BITS_SIZE
#define EXP_BITS_SIZE 10
#endif
void print(int* h_data, int n) {
std::cout << "\n";
for (int i = 0; i < n; i++) {
std::cout << h_data[i] << " ";
}
std::cout << "\n";
}
void cudaTest(hipError_t error) {
if (error != hipSuccess) {
printf("cuda returned error %s (code %d), line(%d)\n",
hipGetErrorString(error), error, __LINE__);
exit(EXIT_FAILURE);
}
}
template<int BITS_NUMBER = 64>
__global__ void radix_sort(int *d_vec, int *d_aux, int *d_seg,
int num_segments) {
int bx = blockIdx.x;
int tx = threadIdx.x;
if (bx * blockDim.x + tx < num_segments) {
int begin = d_seg[bx * blockDim.x + tx];
int end = d_seg[bx * blockDim.x + tx + 1];
int i, exp = 0;
for (exp = 0; exp < BITS_NUMBER; exp++) {
int one = 0;
int zero = 0;
for (i = begin; i < end; i++) {
int x = (d_vec[i] >> exp) & 1;
one += x;
zero += (1 - x);
}
one += zero;
for (i = end - 1; i >= begin; i--) {
int x = (d_vec[i] >> exp) & 1;
int index = begin + x * (one - 1) + (1 - x) * (zero - 1);
d_aux[index] = d_vec[i];
one -= x;
zero -= (1 - x);
}
for (i = begin; i < end; i++)
d_vec[i] = d_aux[i];
}
}
}
int main(int argc, char **argv) {
int num_of_segments;
int num_of_elements;
int i;
scanf("%d", &num_of_segments);
int mem_size_seg = sizeof(int) * (num_of_segments + 1);
int *h_seg = (int *) malloc(mem_size_seg);
for (i = 0; i < num_of_segments + 1; i++)
scanf("%d", &h_seg[i]);
scanf("%d", &num_of_elements);
int mem_size_vec = sizeof(int) * num_of_elements;
int *h_vec = (int *) malloc(mem_size_vec);
for (i = 0; i < num_of_elements; i++)
scanf("%d", &h_vec[i]);
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
// Allocate device memory
int *d_seg, *d_vec, *d_aux;
cudaTest(hipMalloc((void **) &d_seg, mem_size_seg));
cudaTest(hipMalloc((void **) &d_vec, mem_size_vec));
cudaTest(hipMalloc((void **) &d_aux, mem_size_vec));
cudaTest(hipMemcpy(d_seg, h_seg, mem_size_seg, hipMemcpyHostToDevice));
cudaTest(hipMemcpy(d_vec, h_vec, mem_size_vec, hipMemcpyHostToDevice));
int blocksize = BLOCK_SIZE;
dim3 threads(blocksize, 1);
dim3 grid((num_of_segments - 1) / blocksize + 1, 1);
hipEventRecord(start);
radix_sort<EXP_BITS_SIZE> <<<grid, threads>>>(d_vec, d_aux, d_seg,
num_of_segments);
hipEventRecord(stop);
//cudaDeviceSynchronize();
//cudaTest(cudaPeekAtLastError());
cudaTest(hipMemcpy(h_seg, d_seg, mem_size_seg, hipMemcpyDeviceToHost));
cudaTest(hipMemcpy(h_vec, d_vec, mem_size_vec, hipMemcpyDeviceToHost));
if (ELAPSED_TIME == 1) {
hipEventSynchronize(stop);
float milliseconds = 0;
hipEventElapsedTime(&milliseconds, start, stop);
std::cout << milliseconds << "\n";
} else
print(h_vec, num_of_elements);
free(h_seg);
free(h_vec);
hipFree(d_seg);
hipFree(d_vec);
hipFree(d_aux);
//cudaDeviceReset();
return 0;
}
/**
* // cudaDeviceReset causes the driver to clean up all state. While
// not mandatory in normal operation, it is good practice. It is also
// needed to ensure correct operation when the application is being
// profiled. Calling cudaDeviceReset causes all profile data to be
// flushed before the application exits
cudaDeviceReset();
*/
/*
printf("thread=%d | aux=%d %d %d %d\n", bx * blockDim.x + tx, d_aux[begin], d_aux[begin + 1], d_aux[begin + 2], d_aux[begin + 3]);
int devID = 0;
cudaDeviceProp deviceProp;
cudaTest(cudaGetDeviceProperties(&deviceProp, devID));
unsigned int multiprocessorNumber = deviceProp.multiProcessorCount;
unsigned int sharedMemoryTotal = deviceProp.sharedMemPerBlock/(sizeof(int));
std::cout << "multiprocessorNumber: " << multiprocessorNumber << "\n";
std::cout << "sharedMemoryTotal: " << sharedMemoryTotal << "\n";
std::cout << "numberOfSegmentsPerBlock: " << sharedMemoryTotal << "\n";
*/ | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.section .text._Z10radix_sortILi10EEvPiS0_S0_i,"axG",@progbits,_Z10radix_sortILi10EEvPiS0_S0_i,comdat
.protected _Z10radix_sortILi10EEvPiS0_S0_i
.globl _Z10radix_sortILi10EEvPiS0_S0_i
.p2align 8
.type _Z10radix_sortILi10EEvPiS0_S0_i,@function
_Z10radix_sortILi10EEvPiS0_S0_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_u32_e64 s3, v1
s_cbranch_execz .LBB0_13
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x10
s_load_b128 s[4:7], s[0:1], 0x0
v_mov_b32_e32 v2, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[1:2]
v_add_nc_u32_e32 v1, 1, v1
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
v_add_co_u32 v2, vcc_lo, s2, v3
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v4, vcc_lo
s_mov_b32 s2, 0
s_clause 0x1
global_load_b32 v0, v[0:1], off
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(1)
v_ashrrev_i32_e32 v1, 31, v0
s_waitcnt vmcnt(0)
v_ashrrev_i32_e32 v3, 31, v2
v_cmp_lt_i32_e32 vcc_lo, v2, v0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[4:5], 2, v[0:1]
v_lshlrev_b64 v[7:8], 2, v[2:3]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v1, s0, v4, s4
v_add_co_ci_u32_e64 v6, s0, s5, v5, s0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v3, s0, s4, v7
v_add_co_ci_u32_e64 v4, s0, s5, v8, s0
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v5, s0, v1, -4
v_add_co_ci_u32_e64 v6, s0, -1, v6, s0
v_add_co_u32 v7, s0, s6, v7
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v8, s0, s7, v8, s0
s_branch .LBB0_3
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s3
s_add_i32 s2, s2, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lg_u32 s2, 10
s_cbranch_scc0 .LBB0_13
.LBB0_3:
v_mov_b32_e32 v11, 0
v_mov_b32_e32 v1, 0
s_mov_b32 s4, 0
s_and_saveexec_b32 s3, vcc_lo
s_cbranch_execz .LBB0_7
v_dual_mov_b32 v11, 0 :: v_dual_mov_b32 v10, v4
v_dual_mov_b32 v9, v3 :: v_dual_mov_b32 v12, v2
v_mov_b32_e32 v1, 0
.p2align 6
.LBB0_5:
global_load_b32 v13, v[9:10], off
v_add_nc_u32_e32 v12, 1, v12
v_add_co_u32 v9, s0, v9, 4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e64 v10, s0, 0, v10, s0
v_cmp_ge_i32_e64 s1, v12, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
s_or_b32 s4, s1, s4
s_waitcnt vmcnt(0)
v_bfe_u32 v13, v13, s2, 1
v_add_nc_u32_e32 v11, v13, v11
v_xad_u32 v1, v13, 1, v1
s_and_not1_b32 exec_lo, exec_lo, s4
s_cbranch_execnz .LBB0_5
s_or_b32 exec_lo, exec_lo, s4
.LBB0_7:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s3
s_and_saveexec_b32 s3, vcc_lo
s_cbranch_execz .LBB0_10
v_dual_mov_b32 v10, v6 :: v_dual_add_nc_u32 v11, v11, v1
v_dual_mov_b32 v9, v5 :: v_dual_mov_b32 v12, v0
s_mov_b32 s4, 0
s_set_inst_prefetch_distance 0x1
.p2align 6
.LBB0_9:
global_load_b32 v15, v[9:10], off
v_add_nc_u32_e32 v13, -1, v11
v_add_nc_u32_e32 v14, -1, v1
v_add_nc_u32_e32 v12, -1, v12
v_add_co_u32 v9, s0, v9, -4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e64 v10, s0, -1, v10, s0
v_cmp_le_i32_e64 s0, v12, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
s_or_b32 s4, s0, s4
s_waitcnt vmcnt(0)
v_bfe_u32 v16, v15, s2, 1
v_xor_b32_e32 v17, 1, v16
v_mul_lo_u32 v13, v16, v13
v_sub_nc_u32_e32 v11, v11, v16
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_lo_u32 v14, v17, v14
v_sub_nc_u32_e32 v1, v1, v17
v_add3_u32 v13, v13, v2, v14
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v14, 31, v13
v_lshlrev_b64 v[13:14], 2, v[13:14]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v13, s1, s6, v13
v_add_co_ci_u32_e64 v14, s1, s7, v14, s1
global_store_b32 v[13:14], v15, off
s_and_not1_b32 exec_lo, exec_lo, s4
s_cbranch_execnz .LBB0_9
.LBB0_10:
s_set_inst_prefetch_distance 0x2
s_or_b32 exec_lo, exec_lo, s3
s_and_saveexec_b32 s3, vcc_lo
s_cbranch_execz .LBB0_2
v_dual_mov_b32 v10, v4 :: v_dual_mov_b32 v9, v3
v_dual_mov_b32 v12, v8 :: v_dual_mov_b32 v11, v7
v_mov_b32_e32 v1, v2
s_mov_b32 s4, 0
.p2align 6
.LBB0_12:
global_load_b32 v13, v[11:12], off
v_add_nc_u32_e32 v1, 1, v1
v_add_co_u32 v11, s0, v11, 4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e64 v12, s0, 0, v12, s0
v_cmp_ge_i32_e64 s0, v1, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
s_or_b32 s4, s0, s4
s_waitcnt vmcnt(0)
global_store_b32 v[9:10], v13, off
v_add_co_u32 v9, s1, v9, 4
v_add_co_ci_u32_e64 v10, s1, 0, v10, s1
s_and_not1_b32 exec_lo, exec_lo, s4
s_cbranch_execnz .LBB0_12
s_branch .LBB0_2
.LBB0_13:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10radix_sortILi10EEvPiS0_S0_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 18
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.section .text._Z10radix_sortILi10EEvPiS0_S0_i,"axG",@progbits,_Z10radix_sortILi10EEvPiS0_S0_i,comdat
.Lfunc_end0:
.size _Z10radix_sortILi10EEvPiS0_S0_i, .Lfunc_end0-_Z10radix_sortILi10EEvPiS0_S0_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10radix_sortILi10EEvPiS0_S0_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z10radix_sortILi10EEvPiS0_S0_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 18
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | /**
* Copyright 1993-2012 NVIDIA Corporation. All rights reserved.
*
* Please refer to the NVIDIA end user license agreement (EULA) associated
* with this source code for terms and conditions that govern your use of
* this software. Any use, reproduction, disclosure, or distribution of
* this software and related documentation outside the terms of the EULA
* is strictly prohibited.
*/
#include <stdio.h>
#include <stdlib.h>
#include <algorithm>
#include <utility>
#include <iostream>
#include <bitset>
#include <math.h>
#include <time.h>
#include <chrono>
#include <hip/hip_runtime.h>
/**
* This macro checks return value of the CUDA runtime call and exits
* the application if the call failed.
*
* See cuda.h for error code descriptions.
*/
#ifndef BLOCK_SIZE
#define BLOCK_SIZE 1024
#endif
#ifndef ELAPSED_TIME
#define ELAPSED_TIME 0
#endif
#ifndef EXP_BITS_SIZE
#define EXP_BITS_SIZE 10
#endif
void print(int* h_data, int n) {
std::cout << "\n";
for (int i = 0; i < n; i++) {
std::cout << h_data[i] << " ";
}
std::cout << "\n";
}
void cudaTest(hipError_t error) {
if (error != hipSuccess) {
printf("cuda returned error %s (code %d), line(%d)\n",
hipGetErrorString(error), error, __LINE__);
exit(EXIT_FAILURE);
}
}
template<int BITS_NUMBER = 64>
__global__ void radix_sort(int *d_vec, int *d_aux, int *d_seg,
int num_segments) {
int bx = blockIdx.x;
int tx = threadIdx.x;
if (bx * blockDim.x + tx < num_segments) {
int begin = d_seg[bx * blockDim.x + tx];
int end = d_seg[bx * blockDim.x + tx + 1];
int i, exp = 0;
for (exp = 0; exp < BITS_NUMBER; exp++) {
int one = 0;
int zero = 0;
for (i = begin; i < end; i++) {
int x = (d_vec[i] >> exp) & 1;
one += x;
zero += (1 - x);
}
one += zero;
for (i = end - 1; i >= begin; i--) {
int x = (d_vec[i] >> exp) & 1;
int index = begin + x * (one - 1) + (1 - x) * (zero - 1);
d_aux[index] = d_vec[i];
one -= x;
zero -= (1 - x);
}
for (i = begin; i < end; i++)
d_vec[i] = d_aux[i];
}
}
}
int main(int argc, char **argv) {
int num_of_segments;
int num_of_elements;
int i;
scanf("%d", &num_of_segments);
int mem_size_seg = sizeof(int) * (num_of_segments + 1);
int *h_seg = (int *) malloc(mem_size_seg);
for (i = 0; i < num_of_segments + 1; i++)
scanf("%d", &h_seg[i]);
scanf("%d", &num_of_elements);
int mem_size_vec = sizeof(int) * num_of_elements;
int *h_vec = (int *) malloc(mem_size_vec);
for (i = 0; i < num_of_elements; i++)
scanf("%d", &h_vec[i]);
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
// Allocate device memory
int *d_seg, *d_vec, *d_aux;
cudaTest(hipMalloc((void **) &d_seg, mem_size_seg));
cudaTest(hipMalloc((void **) &d_vec, mem_size_vec));
cudaTest(hipMalloc((void **) &d_aux, mem_size_vec));
cudaTest(hipMemcpy(d_seg, h_seg, mem_size_seg, hipMemcpyHostToDevice));
cudaTest(hipMemcpy(d_vec, h_vec, mem_size_vec, hipMemcpyHostToDevice));
int blocksize = BLOCK_SIZE;
dim3 threads(blocksize, 1);
dim3 grid((num_of_segments - 1) / blocksize + 1, 1);
hipEventRecord(start);
radix_sort<EXP_BITS_SIZE> <<<grid, threads>>>(d_vec, d_aux, d_seg,
num_of_segments);
hipEventRecord(stop);
//cudaDeviceSynchronize();
//cudaTest(cudaPeekAtLastError());
cudaTest(hipMemcpy(h_seg, d_seg, mem_size_seg, hipMemcpyDeviceToHost));
cudaTest(hipMemcpy(h_vec, d_vec, mem_size_vec, hipMemcpyDeviceToHost));
if (ELAPSED_TIME == 1) {
hipEventSynchronize(stop);
float milliseconds = 0;
hipEventElapsedTime(&milliseconds, start, stop);
std::cout << milliseconds << "\n";
} else
print(h_vec, num_of_elements);
free(h_seg);
free(h_vec);
hipFree(d_seg);
hipFree(d_vec);
hipFree(d_aux);
//cudaDeviceReset();
return 0;
}
/**
* // cudaDeviceReset causes the driver to clean up all state. While
// not mandatory in normal operation, it is good practice. It is also
// needed to ensure correct operation when the application is being
// profiled. Calling cudaDeviceReset causes all profile data to be
// flushed before the application exits
cudaDeviceReset();
*/
/*
printf("thread=%d | aux=%d %d %d %d\n", bx * blockDim.x + tx, d_aux[begin], d_aux[begin + 1], d_aux[begin + 2], d_aux[begin + 3]);
int devID = 0;
cudaDeviceProp deviceProp;
cudaTest(cudaGetDeviceProperties(&deviceProp, devID));
unsigned int multiprocessorNumber = deviceProp.multiProcessorCount;
unsigned int sharedMemoryTotal = deviceProp.sharedMemPerBlock/(sizeof(int));
std::cout << "multiprocessorNumber: " << multiprocessorNumber << "\n";
std::cout << "sharedMemoryTotal: " << sharedMemoryTotal << "\n";
std::cout << "numberOfSegmentsPerBlock: " << sharedMemoryTotal << "\n";
*/ | .text
.file "globalv1.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z5printPii # -- Begin function _Z5printPii
.p2align 4, 0x90
.type _Z5printPii,@function
_Z5printPii: # @_Z5printPii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
pushq %rax
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %esi, %ebp
movq %rdi, %rbx
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $1, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
testl %ebp, %ebp
jle .LBB0_3
# %bb.1: # %.lr.ph.preheader
movl %ebp, %r14d
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB0_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl (%rbx,%r15,4), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movl $.L.str.1, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
incq %r15
cmpq %r15, %r14
jne .LBB0_2
.LBB0_3: # %._crit_edge
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $1, %edx
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
jmp _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l # TAILCALL
.Lfunc_end0:
.size _Z5printPii, .Lfunc_end0-_Z5printPii
.cfi_endproc
# -- End function
.globl _Z8cudaTest10hipError_t # -- Begin function _Z8cudaTest10hipError_t
.p2align 4, 0x90
.type _Z8cudaTest10hipError_t,@function
_Z8cudaTest10hipError_t: # @_Z8cudaTest10hipError_t
.cfi_startproc
# %bb.0:
testl %edi, %edi
jne .LBB1_2
# %bb.1:
retq
.LBB1_2:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
movl %edi, %ebx
callq hipGetErrorString
movl $.L.str.2, %edi
movq %rax, %rsi
movl %ebx, %edx
movl $51, %ecx
xorl %eax, %eax
callq printf
movl $1, %edi
callq exit
.Lfunc_end1:
.size _Z8cudaTest10hipError_t, .Lfunc_end1-_Z8cudaTest10hipError_t
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $168, %rsp
.cfi_def_cfa_offset 224
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsp, %rsi
movl $.L.str.3, %edi
xorl %eax, %eax
callq __isoc23_scanf
movl (%rsp), %r14d
leal 4(,%r14,4), %eax
movslq %eax, %r15
movq %r15, %rdi
callq malloc
movq %rax, %rbx
testl %r14d, %r14d
js .LBB2_3
# %bb.1: # %.lr.ph.preheader
movq $-1, %r12
movq %rbx, %r14
.p2align 4, 0x90
.LBB2_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl $.L.str.3, %edi
movq %r14, %rsi
xorl %eax, %eax
callq __isoc23_scanf
movslq (%rsp), %rax
incq %r12
addq $4, %r14
cmpq %rax, %r12
jl .LBB2_2
.LBB2_3: # %._crit_edge
leaq 4(%rsp), %rsi
movl $.L.str.3, %edi
xorl %eax, %eax
callq __isoc23_scanf
movl 4(%rsp), %r13d
leal (,%r13,4), %eax
movslq %eax, %r12
movq %r12, %rdi
callq malloc
movq %rax, %r14
testl %r13d, %r13d
jle .LBB2_6
# %bb.4: # %.lr.ph50.preheader
movq %r14, %r13
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB2_5: # %.lr.ph50
# =>This Inner Loop Header: Depth=1
movl $.L.str.3, %edi
movq %r13, %rsi
xorl %eax, %eax
callq __isoc23_scanf
incq %rbp
movslq 4(%rsp), %rax
addq $4, %r13
cmpq %rax, %rbp
jl .LBB2_5
.LBB2_6: # %._crit_edge51
leaq 48(%rsp), %rdi
callq hipEventCreate
leaq 40(%rsp), %rdi
callq hipEventCreate
leaq 16(%rsp), %rdi
movq %r15, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB2_19
# %bb.7: # %_Z8cudaTest10hipError_t.exit
leaq 8(%rsp), %rdi
movq %r12, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB2_19
# %bb.8: # %_Z8cudaTest10hipError_t.exit33
leaq 32(%rsp), %rdi
movq %r12, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB2_19
# %bb.9: # %_Z8cudaTest10hipError_t.exit35
movq 16(%rsp), %rdi
movq %rbx, %rsi
movq %r15, %rdx
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB2_19
# %bb.10: # %_Z8cudaTest10hipError_t.exit37
movq 8(%rsp), %rdi
movq %r14, %rsi
movq %r12, %rdx
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB2_19
# %bb.11: # %_Z8cudaTest10hipError_t.exit39
movl (%rsp), %r13d
leal -1(%r13), %eax
addl $1022, %r13d # imm = 0x3FE
testl %eax, %eax
cmovnsl %eax, %r13d
sarl $10, %r13d
incl %r13d
movabsq $4294967296, %rbp # imm = 0x100000000
orq %rbp, %r13
movq 48(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
orq $1024, %rbp # imm = 0x400
movq %r13, %rdi
movl $1, %esi
movq %rbp, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_13
# %bb.12:
movq 8(%rsp), %rax
movq 32(%rsp), %rcx
movq 16(%rsp), %rdx
movl (%rsp), %esi
movq %rax, 120(%rsp)
movq %rcx, 112(%rsp)
movq %rdx, 104(%rsp)
movl %esi, 28(%rsp)
leaq 120(%rsp), %rax
movq %rax, 128(%rsp)
leaq 112(%rsp), %rax
movq %rax, 136(%rsp)
leaq 104(%rsp), %rax
movq %rax, 144(%rsp)
leaq 28(%rsp), %rax
movq %rax, 152(%rsp)
leaq 88(%rsp), %rdi
leaq 72(%rsp), %rsi
leaq 64(%rsp), %rdx
leaq 56(%rsp), %rcx
callq __hipPopCallConfiguration
movq 88(%rsp), %rsi
movl 96(%rsp), %edx
movq 72(%rsp), %rcx
movl 80(%rsp), %r8d
leaq 128(%rsp), %r9
movl $_Z10radix_sortILi10EEvPiS0_S0_i, %edi
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_13:
movq 40(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 16(%rsp), %rsi
movq %rbx, %rdi
movq %r15, %rdx
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB2_19
# %bb.14: # %_Z8cudaTest10hipError_t.exit41
movq 8(%rsp), %rsi
movq %r14, %rdi
movq %r12, %rdx
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB2_19
# %bb.15: # %_Z8cudaTest10hipError_t.exit43
movl 4(%rsp), %r15d
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $1, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
testl %r15d, %r15d
jle .LBB2_18
# %bb.16: # %.lr.ph.preheader.i
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB2_17: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
movl (%r14,%r12,4), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movl $.L.str.1, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
incq %r12
cmpq %r12, %r15
jne .LBB2_17
.LBB2_18: # %_Z5printPii.exit
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $1, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq 32(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $168, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB2_19:
.cfi_def_cfa_offset 224
movl %eax, %edi
movl %eax, %ebx
callq hipGetErrorString
movl $.L.str.2, %edi
movq %rax, %rsi
movl %ebx, %edx
movl $51, %ecx
xorl %eax, %eax
callq printf
movl $1, %edi
callq exit
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.section .text._Z25__device_stub__radix_sortILi10EEvPiS0_S0_i,"axG",@progbits,_Z25__device_stub__radix_sortILi10EEvPiS0_S0_i,comdat
.weak _Z25__device_stub__radix_sortILi10EEvPiS0_S0_i # -- Begin function _Z25__device_stub__radix_sortILi10EEvPiS0_S0_i
.p2align 4, 0x90
.type _Z25__device_stub__radix_sortILi10EEvPiS0_S0_i,@function
_Z25__device_stub__radix_sortILi10EEvPiS0_S0_i: # @_Z25__device_stub__radix_sortILi10EEvPiS0_S0_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10radix_sortILi10EEvPiS0_S0_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end3:
.size _Z25__device_stub__radix_sortILi10EEvPiS0_S0_i, .Lfunc_end3-_Z25__device_stub__radix_sortILi10EEvPiS0_S0_i
.cfi_endproc
# -- End function
.text
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10radix_sortILi10EEvPiS0_S0_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "\n"
.size .L.str, 2
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz " "
.size .L.str.1, 2
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "cuda returned error %s (code %d), line(%d)\n"
.size .L.str.2, 44
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "%d"
.size .L.str.3, 3
.type _Z10radix_sortILi10EEvPiS0_S0_i,@object # @_Z10radix_sortILi10EEvPiS0_S0_i
.section .rodata._Z10radix_sortILi10EEvPiS0_S0_i,"aG",@progbits,_Z10radix_sortILi10EEvPiS0_S0_i,comdat
.weak _Z10radix_sortILi10EEvPiS0_S0_i
.p2align 3, 0x0
_Z10radix_sortILi10EEvPiS0_S0_i:
.quad _Z25__device_stub__radix_sortILi10EEvPiS0_S0_i
.size _Z10radix_sortILi10EEvPiS0_S0_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z10radix_sortILi10EEvPiS0_S0_i"
.size .L__unnamed_1, 32
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__radix_sortILi10EEvPiS0_S0_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _ZSt4cout
.addrsig_sym _Z10radix_sortILi10EEvPiS0_S0_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00170831_00000000-6_globalv1.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.section .text._Z10radix_sortILi10EEvPiS0_S0_i,"axG",@progbits,_Z10radix_sortILi10EEvPiS0_S0_i,comdat
.weak _Z10radix_sortILi10EEvPiS0_S0_i
.type _Z10radix_sortILi10EEvPiS0_S0_i, @function
_Z10radix_sortILi10EEvPiS0_S0_i:
.LFB4544:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
movq %rdi, 8(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 4(%rsp)
leaq 8(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 24(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L5
.L1:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L6
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L5:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z10radix_sortILi10EEvPiS0_S0_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L1
.L6:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4544:
.size _Z10radix_sortILi10EEvPiS0_S0_i, .-_Z10radix_sortILi10EEvPiS0_S0_i
.text
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB4190:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4190:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "\n"
.LC1:
.string " "
.text
.globl _Z5printPii
.type _Z5printPii, @function
_Z5printPii:
.LFB4183:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $8, %rsp
.cfi_def_cfa_offset 48
movq %rdi, %r12
movl %esi, %ebp
movl $1, %edx
leaq .LC0(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
testl %ebp, %ebp
jle .L10
movq %r12, %rbx
movslq %ebp, %rbp
leaq (%r12,%rbp,4), %r13
leaq _ZSt4cout(%rip), %r12
leaq .LC1(%rip), %rbp
.L11:
movl (%rbx), %esi
movq %r12, %rdi
call _ZNSolsEi@PLT
movq %rax, %rdi
movl $1, %edx
movq %rbp, %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
addq $4, %rbx
cmpq %r13, %rbx
jne .L11
.L10:
movl $1, %edx
leaq .LC0(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4183:
.size _Z5printPii, .-_Z5printPii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC2:
.string "cuda returned error %s (code %d), line(%d)\n"
.text
.globl _Z8cudaTest9cudaError
.type _Z8cudaTest9cudaError, @function
_Z8cudaTest9cudaError:
.LFB4184:
.cfi_startproc
endbr64
testl %edi, %edi
jne .L19
ret
.L19:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movl %edi, %ebx
call cudaGetErrorString@PLT
movq %rax, %rdx
movl $51, %r8d
movl %ebx, %ecx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.cfi_endproc
.LFE4184:
.size _Z8cudaTest9cudaError, .-_Z8cudaTest9cudaError
.section .rodata.str1.1
.LC3:
.string "%d"
.text
.globl main
.type main, @function
main:
.LFB4187:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $104, %rsp
.cfi_def_cfa_offset 160
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 16(%rsp), %rsi
leaq .LC3(%rip), %rdi
call __isoc23_scanf@PLT
movl 16(%rsp), %ebx
leal 4(,%rbx,4), %r15d
movslq %r15d, %r15
movq %r15, %rdi
call malloc@PLT
movq %rax, 8(%rsp)
testl %ebx, %ebx
js .L21
movq %rax, %rbp
movl $0, %ebx
leaq .LC3(%rip), %r12
.L22:
movq %rbp, %rsi
movq %r12, %rdi
movl $0, %eax
call __isoc23_scanf@PLT
addl $1, %ebx
addq $4, %rbp
cmpl %ebx, 16(%rsp)
jge .L22
.L21:
leaq 20(%rsp), %rsi
leaq .LC3(%rip), %rdi
movl $0, %eax
call __isoc23_scanf@PLT
movl 20(%rsp), %ebx
leal 0(,%rbx,4), %r13d
movslq %r13d, %r13
movq %r13, %rdi
call malloc@PLT
movq %rax, %r14
testl %ebx, %ebx
jle .L23
movq %rax, %rbp
movl $0, %ebx
leaq .LC3(%rip), %r12
.L24:
movq %rbp, %rsi
movq %r12, %rdi
movl $0, %eax
call __isoc23_scanf@PLT
addl $1, %ebx
addq $4, %rbp
cmpl %ebx, 20(%rsp)
jg .L24
.L23:
leaq 24(%rsp), %rdi
call cudaEventCreate@PLT
leaq 32(%rsp), %rdi
call cudaEventCreate@PLT
leaq 40(%rsp), %rdi
movq %r15, %rsi
call cudaMalloc@PLT
movl %eax, %edi
call _Z8cudaTest9cudaError
leaq 48(%rsp), %rdi
movq %r13, %rsi
call cudaMalloc@PLT
movl %eax, %edi
call _Z8cudaTest9cudaError
leaq 56(%rsp), %rdi
movq %r13, %rsi
call cudaMalloc@PLT
movl %eax, %edi
call _Z8cudaTest9cudaError
movl $1, %ecx
movq %r15, %rdx
movq 8(%rsp), %rsi
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
call _Z8cudaTest9cudaError
movl $1, %ecx
movq %r13, %rdx
movq %r14, %rsi
movq 48(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
call _Z8cudaTest9cudaError
movl $1024, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl 16(%rsp), %edx
leal 1022(%rdx), %eax
subl $1, %edx
cmovns %edx, %eax
sarl $10, %eax
addl $1, %eax
movl %eax, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $0, %esi
movq 24(%rsp), %rdi
call cudaEventRecord@PLT
movl 72(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 64(%rsp), %rdx
movq 76(%rsp), %rdi
movl 84(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L30
.L25:
movl $0, %esi
movq 32(%rsp), %rdi
call cudaEventRecord@PLT
movl $2, %ecx
movq %r15, %rdx
movq 40(%rsp), %rsi
movq 8(%rsp), %rbx
movq %rbx, %rdi
call cudaMemcpy@PLT
movl %eax, %edi
call _Z8cudaTest9cudaError
movl $2, %ecx
movq %r13, %rdx
movq 48(%rsp), %rsi
movq %r14, %rdi
call cudaMemcpy@PLT
movl %eax, %edi
call _Z8cudaTest9cudaError
movl 20(%rsp), %esi
movq %r14, %rdi
call _Z5printPii
movq %rbx, %rdi
call free@PLT
movq %r14, %rdi
call free@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq 48(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rdi
call cudaFree@PLT
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L31
movl $0, %eax
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L30:
.cfi_restore_state
movl 16(%rsp), %ecx
movq 40(%rsp), %rdx
movq 56(%rsp), %rsi
movq 48(%rsp), %rdi
call _Z10radix_sortILi10EEvPiS0_S0_i
jmp .L25
.L31:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4187:
.size main, .-main
.section .rodata.str1.8
.align 8
.LC4:
.string "_Z10radix_sortILi10EEvPiS0_S0_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB4215:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z10radix_sortILi10EEvPiS0_S0_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4215:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "globalv1.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z5printPii # -- Begin function _Z5printPii
.p2align 4, 0x90
.type _Z5printPii,@function
_Z5printPii: # @_Z5printPii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
pushq %rax
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %esi, %ebp
movq %rdi, %rbx
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $1, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
testl %ebp, %ebp
jle .LBB0_3
# %bb.1: # %.lr.ph.preheader
movl %ebp, %r14d
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB0_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl (%rbx,%r15,4), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movl $.L.str.1, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
incq %r15
cmpq %r15, %r14
jne .LBB0_2
.LBB0_3: # %._crit_edge
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $1, %edx
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
jmp _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l # TAILCALL
.Lfunc_end0:
.size _Z5printPii, .Lfunc_end0-_Z5printPii
.cfi_endproc
# -- End function
.globl _Z8cudaTest10hipError_t # -- Begin function _Z8cudaTest10hipError_t
.p2align 4, 0x90
.type _Z8cudaTest10hipError_t,@function
_Z8cudaTest10hipError_t: # @_Z8cudaTest10hipError_t
.cfi_startproc
# %bb.0:
testl %edi, %edi
jne .LBB1_2
# %bb.1:
retq
.LBB1_2:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
movl %edi, %ebx
callq hipGetErrorString
movl $.L.str.2, %edi
movq %rax, %rsi
movl %ebx, %edx
movl $51, %ecx
xorl %eax, %eax
callq printf
movl $1, %edi
callq exit
.Lfunc_end1:
.size _Z8cudaTest10hipError_t, .Lfunc_end1-_Z8cudaTest10hipError_t
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $168, %rsp
.cfi_def_cfa_offset 224
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsp, %rsi
movl $.L.str.3, %edi
xorl %eax, %eax
callq __isoc23_scanf
movl (%rsp), %r14d
leal 4(,%r14,4), %eax
movslq %eax, %r15
movq %r15, %rdi
callq malloc
movq %rax, %rbx
testl %r14d, %r14d
js .LBB2_3
# %bb.1: # %.lr.ph.preheader
movq $-1, %r12
movq %rbx, %r14
.p2align 4, 0x90
.LBB2_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl $.L.str.3, %edi
movq %r14, %rsi
xorl %eax, %eax
callq __isoc23_scanf
movslq (%rsp), %rax
incq %r12
addq $4, %r14
cmpq %rax, %r12
jl .LBB2_2
.LBB2_3: # %._crit_edge
leaq 4(%rsp), %rsi
movl $.L.str.3, %edi
xorl %eax, %eax
callq __isoc23_scanf
movl 4(%rsp), %r13d
leal (,%r13,4), %eax
movslq %eax, %r12
movq %r12, %rdi
callq malloc
movq %rax, %r14
testl %r13d, %r13d
jle .LBB2_6
# %bb.4: # %.lr.ph50.preheader
movq %r14, %r13
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB2_5: # %.lr.ph50
# =>This Inner Loop Header: Depth=1
movl $.L.str.3, %edi
movq %r13, %rsi
xorl %eax, %eax
callq __isoc23_scanf
incq %rbp
movslq 4(%rsp), %rax
addq $4, %r13
cmpq %rax, %rbp
jl .LBB2_5
.LBB2_6: # %._crit_edge51
leaq 48(%rsp), %rdi
callq hipEventCreate
leaq 40(%rsp), %rdi
callq hipEventCreate
leaq 16(%rsp), %rdi
movq %r15, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB2_19
# %bb.7: # %_Z8cudaTest10hipError_t.exit
leaq 8(%rsp), %rdi
movq %r12, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB2_19
# %bb.8: # %_Z8cudaTest10hipError_t.exit33
leaq 32(%rsp), %rdi
movq %r12, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB2_19
# %bb.9: # %_Z8cudaTest10hipError_t.exit35
movq 16(%rsp), %rdi
movq %rbx, %rsi
movq %r15, %rdx
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB2_19
# %bb.10: # %_Z8cudaTest10hipError_t.exit37
movq 8(%rsp), %rdi
movq %r14, %rsi
movq %r12, %rdx
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB2_19
# %bb.11: # %_Z8cudaTest10hipError_t.exit39
movl (%rsp), %r13d
leal -1(%r13), %eax
addl $1022, %r13d # imm = 0x3FE
testl %eax, %eax
cmovnsl %eax, %r13d
sarl $10, %r13d
incl %r13d
movabsq $4294967296, %rbp # imm = 0x100000000
orq %rbp, %r13
movq 48(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
orq $1024, %rbp # imm = 0x400
movq %r13, %rdi
movl $1, %esi
movq %rbp, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_13
# %bb.12:
movq 8(%rsp), %rax
movq 32(%rsp), %rcx
movq 16(%rsp), %rdx
movl (%rsp), %esi
movq %rax, 120(%rsp)
movq %rcx, 112(%rsp)
movq %rdx, 104(%rsp)
movl %esi, 28(%rsp)
leaq 120(%rsp), %rax
movq %rax, 128(%rsp)
leaq 112(%rsp), %rax
movq %rax, 136(%rsp)
leaq 104(%rsp), %rax
movq %rax, 144(%rsp)
leaq 28(%rsp), %rax
movq %rax, 152(%rsp)
leaq 88(%rsp), %rdi
leaq 72(%rsp), %rsi
leaq 64(%rsp), %rdx
leaq 56(%rsp), %rcx
callq __hipPopCallConfiguration
movq 88(%rsp), %rsi
movl 96(%rsp), %edx
movq 72(%rsp), %rcx
movl 80(%rsp), %r8d
leaq 128(%rsp), %r9
movl $_Z10radix_sortILi10EEvPiS0_S0_i, %edi
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_13:
movq 40(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 16(%rsp), %rsi
movq %rbx, %rdi
movq %r15, %rdx
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB2_19
# %bb.14: # %_Z8cudaTest10hipError_t.exit41
movq 8(%rsp), %rsi
movq %r14, %rdi
movq %r12, %rdx
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB2_19
# %bb.15: # %_Z8cudaTest10hipError_t.exit43
movl 4(%rsp), %r15d
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $1, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
testl %r15d, %r15d
jle .LBB2_18
# %bb.16: # %.lr.ph.preheader.i
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB2_17: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
movl (%r14,%r12,4), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movl $.L.str.1, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
incq %r12
cmpq %r12, %r15
jne .LBB2_17
.LBB2_18: # %_Z5printPii.exit
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $1, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq 32(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $168, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB2_19:
.cfi_def_cfa_offset 224
movl %eax, %edi
movl %eax, %ebx
callq hipGetErrorString
movl $.L.str.2, %edi
movq %rax, %rsi
movl %ebx, %edx
movl $51, %ecx
xorl %eax, %eax
callq printf
movl $1, %edi
callq exit
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.section .text._Z25__device_stub__radix_sortILi10EEvPiS0_S0_i,"axG",@progbits,_Z25__device_stub__radix_sortILi10EEvPiS0_S0_i,comdat
.weak _Z25__device_stub__radix_sortILi10EEvPiS0_S0_i # -- Begin function _Z25__device_stub__radix_sortILi10EEvPiS0_S0_i
.p2align 4, 0x90
.type _Z25__device_stub__radix_sortILi10EEvPiS0_S0_i,@function
_Z25__device_stub__radix_sortILi10EEvPiS0_S0_i: # @_Z25__device_stub__radix_sortILi10EEvPiS0_S0_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10radix_sortILi10EEvPiS0_S0_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end3:
.size _Z25__device_stub__radix_sortILi10EEvPiS0_S0_i, .Lfunc_end3-_Z25__device_stub__radix_sortILi10EEvPiS0_S0_i
.cfi_endproc
# -- End function
.text
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10radix_sortILi10EEvPiS0_S0_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "\n"
.size .L.str, 2
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz " "
.size .L.str.1, 2
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "cuda returned error %s (code %d), line(%d)\n"
.size .L.str.2, 44
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "%d"
.size .L.str.3, 3
.type _Z10radix_sortILi10EEvPiS0_S0_i,@object # @_Z10radix_sortILi10EEvPiS0_S0_i
.section .rodata._Z10radix_sortILi10EEvPiS0_S0_i,"aG",@progbits,_Z10radix_sortILi10EEvPiS0_S0_i,comdat
.weak _Z10radix_sortILi10EEvPiS0_S0_i
.p2align 3, 0x0
_Z10radix_sortILi10EEvPiS0_S0_i:
.quad _Z25__device_stub__radix_sortILi10EEvPiS0_S0_i
.size _Z10radix_sortILi10EEvPiS0_S0_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z10radix_sortILi10EEvPiS0_S0_i"
.size .L__unnamed_1, 32
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__radix_sortILi10EEvPiS0_S0_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _ZSt4cout
.addrsig_sym _Z10radix_sortILi10EEvPiS0_S0_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | //
// main.cpp
// pi_with_cuda
//
// Created by Mirco Meazzo on 21/10/2019.
// Copyright © 2019 Mirco Meazzo. All rights reserved.
//
#include <iostream>
#include <stdlib.h>
#include <math.h>
#include <typeinfo>
#define NLIM 10000000
__global__ void compute_r(int *mem, double *rand_real, double *rand_imag ) {
int index = threadIdx.x + blockIdx.x * blockDim.x;
int total_blocks= gridDim.x;
int stride= blockDim.x * total_blocks;
for (int i=index; i<(int(NLIM)); i+=stride) {
if ((sqrt(rand_real[i]*rand_real[i] + rand_imag[i]*rand_imag[i])) <= 1.0f) {
mem[i] = 1;
}
else
mem[i] = 0;
}
}
__global__ void reduction(int *mem, int *res) {
// Copy from global memory to shared memory the values
__shared__ int mem_gpu[512];
int tid = threadIdx.x;
mem_gpu[tid] = mem[tid + blockDim.x*blockIdx.x];
__syncthreads();
// Wait all threads within the block
// Start memory reduction process
if (blockDim.x >= 512) {
if (tid < 256) {
mem_gpu[tid] += mem_gpu[tid + 256];
}
__syncthreads();
}
if (blockDim.x >= 256) {
if (tid < 128) {
mem_gpu[tid] += mem_gpu[tid + 128];
}
__syncthreads();
}
if (blockDim.x >= 128) {
if (tid < 64) {
mem_gpu[tid] += mem_gpu[tid + 64];
}
__syncthreads();
}
if (tid < 32) { // Instruction within warps scope
volatile int *smem_gpu = mem_gpu; // Volatile means no schedule optimization, we're freezing
// the status on these 64 threads
smem_gpu[tid] += smem_gpu[tid + 32]; // Warps are synchronized, these rows are executed
smem_gpu[tid] += smem_gpu[tid + 16]; // one by one, no need of further sync
smem_gpu[tid] += smem_gpu[tid + 8];
smem_gpu[tid] += smem_gpu[tid + 4];
smem_gpu[tid] += smem_gpu[tid + 2];
smem_gpu[tid] += smem_gpu[tid + 1];
}
if (tid == 0) {
res[blockIdx.x] = mem_gpu[tid];
}
}
int main(int argc, const char * argv[]) {
std::cout << "Refine Pi using " << NLIM << " iterations" << std::endl;
double pi;
int *gpu_inner;
double *rand_imag, *rand_real;
// gpu_inner = new int[NLIM];
// rand_real = new double[NLIM];
// rand_imag = new double[NLIM];
cudaMallocManaged(&gpu_inner,int(NLIM)*sizeof(int));
cudaMallocManaged(&rand_real,int(NLIM)*sizeof(double));
cudaMallocManaged(&rand_imag,int(NLIM)*sizeof(double));
for (int i=0; i<(int(NLIM )-1); i++) {
rand_real[i] = double(rand()) / double(RAND_MAX);
rand_imag[i] = double(rand()) / double(RAND_MAX);
}
int block_size = 128;
int n_blocks = (int(NLIM) + block_size - 1) / block_size;
int *inner;
cudaMallocManaged(&inner, n_blocks*sizeof(int));
std::cout << "Executing Kernel with " << block_size << " threads on " << n_blocks << " blocks" << std::endl;
compute_r <<<n_blocks, block_size>>> (gpu_inner, rand_real, rand_imag);
cudaDeviceSynchronize();
reduction <<<n_blocks, block_size>>> (gpu_inner,inner);
// compute_r (gpu_inner,rand_real,rand_imag);
cudaDeviceSynchronize();
for (int i=1; i<n_blocks; i++) {
inner[0] += inner[i];
}
pi= 4.0f* (inner[0]/double(NLIM));
std::cout << "Pi is " << pi << std::endl;
cudaFree(gpu_inner);
cudaFree(rand_imag);
cudaFree(rand_real);
return 0;
} | .file "tmpxft_000fb9b3_00000000-6_main.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z33__device_stub__Z9compute_rPiPdS0_PiPdS0_
.type _Z33__device_stub__Z9compute_rPiPdS0_PiPdS0_, @function
_Z33__device_stub__Z9compute_rPiPdS0_PiPdS0_:
.LFB3694:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9compute_rPiPdS0_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3694:
.size _Z33__device_stub__Z9compute_rPiPdS0_PiPdS0_, .-_Z33__device_stub__Z9compute_rPiPdS0_PiPdS0_
.globl _Z9compute_rPiPdS0_
.type _Z9compute_rPiPdS0_, @function
_Z9compute_rPiPdS0_:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z9compute_rPiPdS0_PiPdS0_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _Z9compute_rPiPdS0_, .-_Z9compute_rPiPdS0_
.globl _Z30__device_stub__Z9reductionPiS_PiS_
.type _Z30__device_stub__Z9reductionPiS_PiS_, @function
_Z30__device_stub__Z9reductionPiS_PiS_:
.LFB3696:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z9reductionPiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3696:
.size _Z30__device_stub__Z9reductionPiS_PiS_, .-_Z30__device_stub__Z9reductionPiS_PiS_
.globl _Z9reductionPiS_
.type _Z9reductionPiS_, @function
_Z9reductionPiS_:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z9reductionPiS_PiS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _Z9reductionPiS_, .-_Z9reductionPiS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Refine Pi using "
.LC1:
.string " iterations"
.LC3:
.string "Executing Kernel with "
.LC4:
.string " threads on "
.LC5:
.string " blocks"
.LC8:
.string "Pi is "
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $64, %rsp
.cfi_def_cfa_offset 80
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
leaq .LC0(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl $10000000, %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
leaq .LC1(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq %rsp, %rdi
movl $1, %edx
movl $40000000, %esi
call cudaMallocManaged@PLT
leaq 16(%rsp), %rdi
movl $1, %edx
movl $80000000, %esi
call cudaMallocManaged@PLT
leaq 8(%rsp), %rdi
movl $1, %edx
movl $80000000, %esi
call cudaMallocManaged@PLT
movl $0, %ebx
.L20:
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
divsd .LC2(%rip), %xmm0
movq 16(%rsp), %rax
movsd %xmm0, (%rax,%rbx)
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
divsd .LC2(%rip), %xmm0
movq 8(%rsp), %rax
movsd %xmm0, (%rax,%rbx)
addq $8, %rbx
cmpq $79999992, %rbx
jne .L20
leaq 24(%rsp), %rdi
movl $1, %edx
movl $312500, %esi
call cudaMallocManaged@PLT
leaq .LC3(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl $128, %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
leaq .LC4(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl $78125, %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
leaq .LC5(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $128, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $78125, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L28
.L21:
call cudaDeviceSynchronize@PLT
movl $128, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $78125, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L29
.L22:
call cudaDeviceSynchronize@PLT
movl $4, %eax
.L23:
movq 24(%rsp), %rdx
movl (%rdx,%rax), %ecx
addl %ecx, (%rdx)
addq $4, %rax
cmpq $312500, %rax
jne .L23
movq 24(%rsp), %rax
pxor %xmm0, %xmm0
cvtsi2sdl (%rax), %xmm0
divsd .LC6(%rip), %xmm0
mulsd .LC7(%rip), %xmm0
movq %xmm0, %rbx
leaq .LC8(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq %rbx, %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L30
movl $0, %eax
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L28:
.cfi_restore_state
movq 8(%rsp), %rdx
movq 16(%rsp), %rsi
movq (%rsp), %rdi
call _Z33__device_stub__Z9compute_rPiPdS0_PiPdS0_
jmp .L21
.L29:
movq 24(%rsp), %rsi
movq (%rsp), %rdi
call _Z30__device_stub__Z9reductionPiS_PiS_
jmp .L22
.L30:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size main, .-main
.section .rodata.str1.1
.LC9:
.string "_Z9reductionPiS_"
.LC10:
.string "_Z9compute_rPiPdS0_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3699:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _Z9reductionPiS_(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC10(%rip), %rdx
movq %rdx, %rcx
leaq _Z9compute_rPiPdS0_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3699:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC2:
.long -4194304
.long 1105199103
.align 8
.LC6:
.long 0
.long 1097011920
.align 8
.LC7:
.long 0
.long 1074790400
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | //
// main.cpp
// pi_with_cuda
//
// Created by Mirco Meazzo on 21/10/2019.
// Copyright © 2019 Mirco Meazzo. All rights reserved.
//
#include <iostream>
#include <stdlib.h>
#include <math.h>
#include <typeinfo>
#define NLIM 10000000
__global__ void compute_r(int *mem, double *rand_real, double *rand_imag ) {
int index = threadIdx.x + blockIdx.x * blockDim.x;
int total_blocks= gridDim.x;
int stride= blockDim.x * total_blocks;
for (int i=index; i<(int(NLIM)); i+=stride) {
if ((sqrt(rand_real[i]*rand_real[i] + rand_imag[i]*rand_imag[i])) <= 1.0f) {
mem[i] = 1;
}
else
mem[i] = 0;
}
}
__global__ void reduction(int *mem, int *res) {
// Copy from global memory to shared memory the values
__shared__ int mem_gpu[512];
int tid = threadIdx.x;
mem_gpu[tid] = mem[tid + blockDim.x*blockIdx.x];
__syncthreads();
// Wait all threads within the block
// Start memory reduction process
if (blockDim.x >= 512) {
if (tid < 256) {
mem_gpu[tid] += mem_gpu[tid + 256];
}
__syncthreads();
}
if (blockDim.x >= 256) {
if (tid < 128) {
mem_gpu[tid] += mem_gpu[tid + 128];
}
__syncthreads();
}
if (blockDim.x >= 128) {
if (tid < 64) {
mem_gpu[tid] += mem_gpu[tid + 64];
}
__syncthreads();
}
if (tid < 32) { // Instruction within warps scope
volatile int *smem_gpu = mem_gpu; // Volatile means no schedule optimization, we're freezing
// the status on these 64 threads
smem_gpu[tid] += smem_gpu[tid + 32]; // Warps are synchronized, these rows are executed
smem_gpu[tid] += smem_gpu[tid + 16]; // one by one, no need of further sync
smem_gpu[tid] += smem_gpu[tid + 8];
smem_gpu[tid] += smem_gpu[tid + 4];
smem_gpu[tid] += smem_gpu[tid + 2];
smem_gpu[tid] += smem_gpu[tid + 1];
}
if (tid == 0) {
res[blockIdx.x] = mem_gpu[tid];
}
}
int main(int argc, const char * argv[]) {
std::cout << "Refine Pi using " << NLIM << " iterations" << std::endl;
double pi;
int *gpu_inner;
double *rand_imag, *rand_real;
// gpu_inner = new int[NLIM];
// rand_real = new double[NLIM];
// rand_imag = new double[NLIM];
cudaMallocManaged(&gpu_inner,int(NLIM)*sizeof(int));
cudaMallocManaged(&rand_real,int(NLIM)*sizeof(double));
cudaMallocManaged(&rand_imag,int(NLIM)*sizeof(double));
for (int i=0; i<(int(NLIM )-1); i++) {
rand_real[i] = double(rand()) / double(RAND_MAX);
rand_imag[i] = double(rand()) / double(RAND_MAX);
}
int block_size = 128;
int n_blocks = (int(NLIM) + block_size - 1) / block_size;
int *inner;
cudaMallocManaged(&inner, n_blocks*sizeof(int));
std::cout << "Executing Kernel with " << block_size << " threads on " << n_blocks << " blocks" << std::endl;
compute_r <<<n_blocks, block_size>>> (gpu_inner, rand_real, rand_imag);
cudaDeviceSynchronize();
reduction <<<n_blocks, block_size>>> (gpu_inner,inner);
// compute_r (gpu_inner,rand_real,rand_imag);
cudaDeviceSynchronize();
for (int i=1; i<n_blocks; i++) {
inner[0] += inner[i];
}
pi= 4.0f* (inner[0]/double(NLIM));
std::cout << "Pi is " << pi << std::endl;
cudaFree(gpu_inner);
cudaFree(rand_imag);
cudaFree(rand_real);
return 0;
} | //
// main.cpp
// pi_with_cuda
//
// Created by Mirco Meazzo on 21/10/2019.
// Copyright © 2019 Mirco Meazzo. All rights reserved.
//
#include <hip/hip_runtime.h>
#include <iostream>
#include <stdlib.h>
#include <math.h>
#include <typeinfo>
#define NLIM 10000000
__global__ void compute_r(int *mem, double *rand_real, double *rand_imag ) {
int index = threadIdx.x + blockIdx.x * blockDim.x;
int total_blocks= gridDim.x;
int stride= blockDim.x * total_blocks;
for (int i=index; i<(int(NLIM)); i+=stride) {
if ((sqrt(rand_real[i]*rand_real[i] + rand_imag[i]*rand_imag[i])) <= 1.0f) {
mem[i] = 1;
}
else
mem[i] = 0;
}
}
__global__ void reduction(int *mem, int *res) {
// Copy from global memory to shared memory the values
__shared__ int mem_gpu[512];
int tid = threadIdx.x;
mem_gpu[tid] = mem[tid + blockDim.x*blockIdx.x];
__syncthreads();
// Wait all threads within the block
// Start memory reduction process
if (blockDim.x >= 512) {
if (tid < 256) {
mem_gpu[tid] += mem_gpu[tid + 256];
}
__syncthreads();
}
if (blockDim.x >= 256) {
if (tid < 128) {
mem_gpu[tid] += mem_gpu[tid + 128];
}
__syncthreads();
}
if (blockDim.x >= 128) {
if (tid < 64) {
mem_gpu[tid] += mem_gpu[tid + 64];
}
__syncthreads();
}
if (tid < 32) { // Instruction within warps scope
volatile int *smem_gpu = mem_gpu; // Volatile means no schedule optimization, we're freezing
// the status on these 64 threads
smem_gpu[tid] += smem_gpu[tid + 32]; // Warps are synchronized, these rows are executed
smem_gpu[tid] += smem_gpu[tid + 16]; // one by one, no need of further sync
smem_gpu[tid] += smem_gpu[tid + 8];
smem_gpu[tid] += smem_gpu[tid + 4];
smem_gpu[tid] += smem_gpu[tid + 2];
smem_gpu[tid] += smem_gpu[tid + 1];
}
if (tid == 0) {
res[blockIdx.x] = mem_gpu[tid];
}
}
int main(int argc, const char * argv[]) {
std::cout << "Refine Pi using " << NLIM << " iterations" << std::endl;
double pi;
int *gpu_inner;
double *rand_imag, *rand_real;
// gpu_inner = new int[NLIM];
// rand_real = new double[NLIM];
// rand_imag = new double[NLIM];
hipMallocManaged(&gpu_inner,int(NLIM)*sizeof(int));
hipMallocManaged(&rand_real,int(NLIM)*sizeof(double));
hipMallocManaged(&rand_imag,int(NLIM)*sizeof(double));
for (int i=0; i<(int(NLIM )-1); i++) {
rand_real[i] = double(rand()) / double(RAND_MAX);
rand_imag[i] = double(rand()) / double(RAND_MAX);
}
int block_size = 128;
int n_blocks = (int(NLIM) + block_size - 1) / block_size;
int *inner;
hipMallocManaged(&inner, n_blocks*sizeof(int));
std::cout << "Executing Kernel with " << block_size << " threads on " << n_blocks << " blocks" << std::endl;
compute_r <<<n_blocks, block_size>>> (gpu_inner, rand_real, rand_imag);
hipDeviceSynchronize();
reduction <<<n_blocks, block_size>>> (gpu_inner,inner);
// compute_r (gpu_inner,rand_real,rand_imag);
hipDeviceSynchronize();
for (int i=1; i<n_blocks; i++) {
inner[0] += inner[i];
}
pi= 4.0f* (inner[0]/double(NLIM));
std::cout << "Pi is " << pi << std::endl;
hipFree(gpu_inner);
hipFree(rand_imag);
hipFree(rand_real);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | //
// main.cpp
// pi_with_cuda
//
// Created by Mirco Meazzo on 21/10/2019.
// Copyright © 2019 Mirco Meazzo. All rights reserved.
//
#include <hip/hip_runtime.h>
#include <iostream>
#include <stdlib.h>
#include <math.h>
#include <typeinfo>
#define NLIM 10000000
__global__ void compute_r(int *mem, double *rand_real, double *rand_imag ) {
int index = threadIdx.x + blockIdx.x * blockDim.x;
int total_blocks= gridDim.x;
int stride= blockDim.x * total_blocks;
for (int i=index; i<(int(NLIM)); i+=stride) {
if ((sqrt(rand_real[i]*rand_real[i] + rand_imag[i]*rand_imag[i])) <= 1.0f) {
mem[i] = 1;
}
else
mem[i] = 0;
}
}
__global__ void reduction(int *mem, int *res) {
// Copy from global memory to shared memory the values
__shared__ int mem_gpu[512];
int tid = threadIdx.x;
mem_gpu[tid] = mem[tid + blockDim.x*blockIdx.x];
__syncthreads();
// Wait all threads within the block
// Start memory reduction process
if (blockDim.x >= 512) {
if (tid < 256) {
mem_gpu[tid] += mem_gpu[tid + 256];
}
__syncthreads();
}
if (blockDim.x >= 256) {
if (tid < 128) {
mem_gpu[tid] += mem_gpu[tid + 128];
}
__syncthreads();
}
if (blockDim.x >= 128) {
if (tid < 64) {
mem_gpu[tid] += mem_gpu[tid + 64];
}
__syncthreads();
}
if (tid < 32) { // Instruction within warps scope
volatile int *smem_gpu = mem_gpu; // Volatile means no schedule optimization, we're freezing
// the status on these 64 threads
smem_gpu[tid] += smem_gpu[tid + 32]; // Warps are synchronized, these rows are executed
smem_gpu[tid] += smem_gpu[tid + 16]; // one by one, no need of further sync
smem_gpu[tid] += smem_gpu[tid + 8];
smem_gpu[tid] += smem_gpu[tid + 4];
smem_gpu[tid] += smem_gpu[tid + 2];
smem_gpu[tid] += smem_gpu[tid + 1];
}
if (tid == 0) {
res[blockIdx.x] = mem_gpu[tid];
}
}
int main(int argc, const char * argv[]) {
std::cout << "Refine Pi using " << NLIM << " iterations" << std::endl;
double pi;
int *gpu_inner;
double *rand_imag, *rand_real;
// gpu_inner = new int[NLIM];
// rand_real = new double[NLIM];
// rand_imag = new double[NLIM];
hipMallocManaged(&gpu_inner,int(NLIM)*sizeof(int));
hipMallocManaged(&rand_real,int(NLIM)*sizeof(double));
hipMallocManaged(&rand_imag,int(NLIM)*sizeof(double));
for (int i=0; i<(int(NLIM )-1); i++) {
rand_real[i] = double(rand()) / double(RAND_MAX);
rand_imag[i] = double(rand()) / double(RAND_MAX);
}
int block_size = 128;
int n_blocks = (int(NLIM) + block_size - 1) / block_size;
int *inner;
hipMallocManaged(&inner, n_blocks*sizeof(int));
std::cout << "Executing Kernel with " << block_size << " threads on " << n_blocks << " blocks" << std::endl;
compute_r <<<n_blocks, block_size>>> (gpu_inner, rand_real, rand_imag);
hipDeviceSynchronize();
reduction <<<n_blocks, block_size>>> (gpu_inner,inner);
// compute_r (gpu_inner,rand_real,rand_imag);
hipDeviceSynchronize();
for (int i=1; i<n_blocks; i++) {
inner[0] += inner[i];
}
pi= 4.0f* (inner[0]/double(NLIM));
std::cout << "Pi is " << pi << std::endl;
hipFree(gpu_inner);
hipFree(rand_imag);
hipFree(rand_real);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9compute_rPiPdS0_
.globl _Z9compute_rPiPdS0_
.p2align 8
.type _Z9compute_rPiPdS0_,@function
_Z9compute_rPiPdS0_:
s_load_b32 s4, s[0:1], 0x24
s_add_u32 s2, s0, 24
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s8, s4, 0xffff
s_mov_b32 s4, exec_lo
v_mad_u64_u32 v[1:2], null, s15, s8, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e32 0x989680, v1
s_cbranch_execz .LBB0_3
s_load_b32 s9, s[2:3], 0x0
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[2:3], s[0:1], 0x10
v_ashrrev_i32_e32 v2, 31, v1
s_mov_b32 s1, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[4:5], 2, v[1:2]
v_lshlrev_b64 v[2:3], 3, v[1:2]
s_waitcnt lgkmcnt(0)
s_mul_i32 s8, s9, s8
v_add_co_u32 v4, vcc_lo, s4, v4
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
s_ashr_i32 s9, s8, 31
s_lshl_b64 s[4:5], s[8:9], 3
s_lshl_b64 s[10:11], s[8:9], 2
.LBB0_2:
v_add_co_u32 v6, vcc_lo, s2, v2
v_add_co_ci_u32_e32 v7, vcc_lo, s3, v3, vcc_lo
v_add_co_u32 v8, vcc_lo, s6, v2
v_add_co_ci_u32_e32 v9, vcc_lo, s7, v3, vcc_lo
global_load_b64 v[6:7], v[6:7], off
v_add_co_u32 v2, s0, v2, s4
global_load_b64 v[8:9], v[8:9], off
v_add_co_ci_u32_e64 v3, s0, s5, v3, s0
s_waitcnt vmcnt(1)
v_mul_f64 v[6:7], v[6:7], v[6:7]
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[6:7], v[8:9], v[8:9], v[6:7]
v_cmp_gt_f64_e32 vcc_lo, 0x10000000, v[6:7]
v_cndmask_b32_e64 v0, 0, 1, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b32_e32 v0, 8, v0
v_ldexp_f64 v[6:7], v[6:7], v0
v_cndmask_b32_e64 v0, 0, 0xffffff80, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_1)
v_rsq_f64_e32 v[8:9], v[6:7]
v_cmp_class_f64_e64 vcc_lo, v[6:7], 0x260
s_waitcnt_depctr 0xfff
v_mul_f64 v[10:11], v[6:7], v[8:9]
v_mul_f64 v[8:9], v[8:9], 0.5
v_fma_f64 v[12:13], -v[8:9], v[10:11], 0.5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_fma_f64 v[10:11], v[10:11], v[12:13], v[10:11]
v_fma_f64 v[8:9], v[8:9], v[12:13], v[8:9]
v_fma_f64 v[12:13], -v[10:11], v[10:11], v[6:7]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[10:11], v[12:13], v[8:9], v[10:11]
v_fma_f64 v[12:13], -v[10:11], v[10:11], v[6:7]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[8:9], v[12:13], v[8:9], v[10:11]
v_ldexp_f64 v[8:9], v[8:9], v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_dual_cndmask_b32 v6, v8, v6 :: v_dual_add_nc_u32 v1, s8, v1
v_cndmask_b32_e32 v7, v9, v7, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_lt_i32_e64 s0, 0x98967f, v1
v_cmp_ge_f64_e32 vcc_lo, 1.0, v[6:7]
s_delay_alu instid0(VALU_DEP_2)
s_or_b32 s1, s0, s1
v_cndmask_b32_e64 v0, 0, 1, vcc_lo
global_store_b32 v[4:5], v0, off
v_add_co_u32 v4, vcc_lo, v4, s10
v_add_co_ci_u32_e32 v5, vcc_lo, s11, v5, vcc_lo
s_and_not1_b32 exec_lo, exec_lo, s1
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9compute_rPiPdS0_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 14
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9compute_rPiPdS0_, .Lfunc_end0-_Z9compute_rPiPdS0_
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z9reductionPiS_
.globl _Z9reductionPiS_
.p2align 8
.type _Z9reductionPiS_,@function
_Z9reductionPiS_:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x1c
s_load_b64 s[6:7], s[0:1], 0x0
s_mov_b32 s4, s15
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s3, 0xffff
v_cmp_gt_u16_e64 s5, 0x200, s3
v_mad_u64_u32 v[1:2], null, s4, s2, v[0:1]
v_mov_b32_e32 v2, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[1:2]
v_add_co_u32 v1, vcc_lo, s6, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, s7, v2, vcc_lo
s_and_b32 vcc_lo, exec_lo, s5
global_load_b32 v2, v[1:2], off
v_lshlrev_b32_e32 v1, 2, v0
s_waitcnt vmcnt(0)
ds_store_b32 v1, v2
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_vccnz .LBB1_4
s_mov_b32 s5, exec_lo
v_cmpx_gt_u32_e32 0x100, v0
s_cbranch_execz .LBB1_3
v_lshlrev_b32_e32 v2, 2, v0
ds_load_b32 v2, v2 offset:1024
ds_load_b32 v3, v1
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v2, v3, v2
ds_store_b32 v1, v2
.LBB1_3:
s_or_b32 exec_lo, exec_lo, s5
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
.LBB1_4:
v_cmp_gt_u16_e64 s3, 0x100, s3
s_delay_alu instid0(VALU_DEP_1)
s_and_b32 vcc_lo, exec_lo, s3
s_cbranch_vccnz .LBB1_8
s_mov_b32 s3, exec_lo
v_cmpx_gt_u32_e32 0x80, v0
s_cbranch_execz .LBB1_7
v_lshlrev_b32_e32 v2, 2, v0
ds_load_b32 v2, v2 offset:512
ds_load_b32 v3, v1
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v2, v3, v2
ds_store_b32 v1, v2
.LBB1_7:
s_or_b32 exec_lo, exec_lo, s3
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
.LBB1_8:
s_cmpk_lt_u32 s2, 0x80
s_cbranch_scc1 .LBB1_12
s_mov_b32 s2, exec_lo
v_cmpx_gt_u32_e32 64, v0
s_cbranch_execz .LBB1_11
v_lshlrev_b32_e32 v2, 2, v0
ds_load_b32 v2, v2 offset:256
ds_load_b32 v3, v1
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v2, v3, v2
ds_store_b32 v1, v2
.LBB1_11:
s_or_b32 exec_lo, exec_lo, s2
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
.LBB1_12:
s_mov_b32 s3, exec_lo
v_cmpx_gt_u32_e32 32, v0
s_cbranch_execz .LBB1_14
v_lshlrev_b32_e32 v6, 2, v0
s_mov_b64 s[6:7], src_shared_base
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v3, 0x80, v6
v_cmp_ne_u32_e64 s2, -1, v6
v_cmp_ne_u32_e32 vcc_lo, -1, v3
s_delay_alu instid0(VALU_DEP_2)
v_cndmask_b32_e64 v2, 0, v6, s2
v_cndmask_b32_e32 v4, 0, v3, vcc_lo
v_cndmask_b32_e64 v5, 0, s7, vcc_lo
v_cndmask_b32_e64 v3, 0, s7, s2
flat_load_b32 v5, v[4:5] glc dlc
s_waitcnt vmcnt(0)
flat_load_b32 v7, v[2:3] glc dlc
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v4, 64, v6
s_delay_alu instid0(VALU_DEP_1)
v_cmp_ne_u32_e32 vcc_lo, -1, v4
s_waitcnt lgkmcnt(0)
v_dual_cndmask_b32 v4, 0, v4 :: v_dual_add_nc_u32 v7, v7, v5
v_cndmask_b32_e64 v5, 0, s7, vcc_lo
flat_store_b32 v[2:3], v7 dlc
s_waitcnt_vscnt null, 0x0
flat_load_b32 v5, v[4:5] glc dlc
s_waitcnt vmcnt(0)
flat_load_b32 v7, v[2:3] glc dlc
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v4, 32, v6
s_delay_alu instid0(VALU_DEP_1)
v_cmp_ne_u32_e32 vcc_lo, -1, v4
s_waitcnt lgkmcnt(0)
v_dual_cndmask_b32 v4, 0, v4 :: v_dual_add_nc_u32 v7, v7, v5
v_cndmask_b32_e64 v5, 0, s7, vcc_lo
flat_store_b32 v[2:3], v7 dlc
s_waitcnt_vscnt null, 0x0
flat_load_b32 v5, v[4:5] glc dlc
s_waitcnt vmcnt(0)
flat_load_b32 v7, v[2:3] glc dlc
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v4, 16, v6
s_delay_alu instid0(VALU_DEP_1)
v_cmp_ne_u32_e32 vcc_lo, -1, v4
s_waitcnt lgkmcnt(0)
v_dual_cndmask_b32 v4, 0, v4 :: v_dual_add_nc_u32 v7, v7, v5
v_cndmask_b32_e64 v5, 0, s7, vcc_lo
flat_store_b32 v[2:3], v7 dlc
s_waitcnt_vscnt null, 0x0
flat_load_b32 v5, v[4:5] glc dlc
s_waitcnt vmcnt(0)
flat_load_b32 v7, v[2:3] glc dlc
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v4, 8, v6
s_delay_alu instid0(VALU_DEP_1)
v_cmp_ne_u32_e32 vcc_lo, -1, v4
s_waitcnt lgkmcnt(0)
v_dual_cndmask_b32 v4, 0, v4 :: v_dual_add_nc_u32 v7, v7, v5
v_cndmask_b32_e64 v5, 0, s7, vcc_lo
flat_store_b32 v[2:3], v7 dlc
s_waitcnt_vscnt null, 0x0
flat_load_b32 v5, v[4:5] glc dlc
s_waitcnt vmcnt(0)
flat_load_b32 v7, v[2:3] glc dlc
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v4, 4, v6
s_delay_alu instid0(VALU_DEP_1)
v_cmp_ne_u32_e32 vcc_lo, -1, v4
v_cndmask_b32_e32 v4, 0, v4, vcc_lo
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v6, v7, v5
v_cndmask_b32_e64 v5, 0, s7, vcc_lo
flat_store_b32 v[2:3], v6 dlc
s_waitcnt_vscnt null, 0x0
flat_load_b32 v4, v[4:5] glc dlc
s_waitcnt vmcnt(0)
flat_load_b32 v5, v[2:3] glc dlc
s_waitcnt vmcnt(0) lgkmcnt(0)
v_add_nc_u32_e32 v4, v5, v4
flat_store_b32 v[2:3], v4 dlc
s_waitcnt_vscnt null, 0x0
.LBB1_14:
s_or_b32 exec_lo, exec_lo, s3
s_mov_b32 s5, 0
s_mov_b32 s2, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB1_16
s_load_b64 s[0:1], s[0:1], 0x8
ds_load_b32 v0, v1
s_lshl_b64 s[2:3], s[4:5], 2
v_mov_b32_e32 v1, 0
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
global_store_b32 v1, v0, s[0:1]
.LBB1_16:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9reductionPiS_
.amdhsa_group_segment_fixed_size 2048
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z9reductionPiS_, .Lfunc_end1-_Z9reductionPiS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9compute_rPiPdS0_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9compute_rPiPdS0_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 14
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 2048
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9reductionPiS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9reductionPiS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | //
// main.cpp
// pi_with_cuda
//
// Created by Mirco Meazzo on 21/10/2019.
// Copyright © 2019 Mirco Meazzo. All rights reserved.
//
#include <hip/hip_runtime.h>
#include <iostream>
#include <stdlib.h>
#include <math.h>
#include <typeinfo>
#define NLIM 10000000
__global__ void compute_r(int *mem, double *rand_real, double *rand_imag ) {
int index = threadIdx.x + blockIdx.x * blockDim.x;
int total_blocks= gridDim.x;
int stride= blockDim.x * total_blocks;
for (int i=index; i<(int(NLIM)); i+=stride) {
if ((sqrt(rand_real[i]*rand_real[i] + rand_imag[i]*rand_imag[i])) <= 1.0f) {
mem[i] = 1;
}
else
mem[i] = 0;
}
}
__global__ void reduction(int *mem, int *res) {
// Copy from global memory to shared memory the values
__shared__ int mem_gpu[512];
int tid = threadIdx.x;
mem_gpu[tid] = mem[tid + blockDim.x*blockIdx.x];
__syncthreads();
// Wait all threads within the block
// Start memory reduction process
if (blockDim.x >= 512) {
if (tid < 256) {
mem_gpu[tid] += mem_gpu[tid + 256];
}
__syncthreads();
}
if (blockDim.x >= 256) {
if (tid < 128) {
mem_gpu[tid] += mem_gpu[tid + 128];
}
__syncthreads();
}
if (blockDim.x >= 128) {
if (tid < 64) {
mem_gpu[tid] += mem_gpu[tid + 64];
}
__syncthreads();
}
if (tid < 32) { // Instruction within warps scope
volatile int *smem_gpu = mem_gpu; // Volatile means no schedule optimization, we're freezing
// the status on these 64 threads
smem_gpu[tid] += smem_gpu[tid + 32]; // Warps are synchronized, these rows are executed
smem_gpu[tid] += smem_gpu[tid + 16]; // one by one, no need of further sync
smem_gpu[tid] += smem_gpu[tid + 8];
smem_gpu[tid] += smem_gpu[tid + 4];
smem_gpu[tid] += smem_gpu[tid + 2];
smem_gpu[tid] += smem_gpu[tid + 1];
}
if (tid == 0) {
res[blockIdx.x] = mem_gpu[tid];
}
}
int main(int argc, const char * argv[]) {
std::cout << "Refine Pi using " << NLIM << " iterations" << std::endl;
double pi;
int *gpu_inner;
double *rand_imag, *rand_real;
// gpu_inner = new int[NLIM];
// rand_real = new double[NLIM];
// rand_imag = new double[NLIM];
hipMallocManaged(&gpu_inner,int(NLIM)*sizeof(int));
hipMallocManaged(&rand_real,int(NLIM)*sizeof(double));
hipMallocManaged(&rand_imag,int(NLIM)*sizeof(double));
for (int i=0; i<(int(NLIM )-1); i++) {
rand_real[i] = double(rand()) / double(RAND_MAX);
rand_imag[i] = double(rand()) / double(RAND_MAX);
}
int block_size = 128;
int n_blocks = (int(NLIM) + block_size - 1) / block_size;
int *inner;
hipMallocManaged(&inner, n_blocks*sizeof(int));
std::cout << "Executing Kernel with " << block_size << " threads on " << n_blocks << " blocks" << std::endl;
compute_r <<<n_blocks, block_size>>> (gpu_inner, rand_real, rand_imag);
hipDeviceSynchronize();
reduction <<<n_blocks, block_size>>> (gpu_inner,inner);
// compute_r (gpu_inner,rand_real,rand_imag);
hipDeviceSynchronize();
for (int i=1; i<n_blocks; i++) {
inner[0] += inner[i];
}
pi= 4.0f* (inner[0]/double(NLIM));
std::cout << "Pi is " << pi << std::endl;
hipFree(gpu_inner);
hipFree(rand_imag);
hipFree(rand_real);
return 0;
} | .text
.file "main.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z24__device_stub__compute_rPiPdS0_ # -- Begin function _Z24__device_stub__compute_rPiPdS0_
.p2align 4, 0x90
.type _Z24__device_stub__compute_rPiPdS0_,@function
_Z24__device_stub__compute_rPiPdS0_: # @_Z24__device_stub__compute_rPiPdS0_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9compute_rPiPdS0_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z24__device_stub__compute_rPiPdS0_, .Lfunc_end0-_Z24__device_stub__compute_rPiPdS0_
.cfi_endproc
# -- End function
.globl _Z24__device_stub__reductionPiS_ # -- Begin function _Z24__device_stub__reductionPiS_
.p2align 4, 0x90
.type _Z24__device_stub__reductionPiS_,@function
_Z24__device_stub__reductionPiS_: # @_Z24__device_stub__reductionPiS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z9reductionPiS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end1:
.size _Z24__device_stub__reductionPiS_, .Lfunc_end1-_Z24__device_stub__reductionPiS_
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI2_0:
.quad 0x41dfffffffc00000 # double 2147483647
.LCPI2_1:
.quad 0x416312d000000000 # double 1.0E+7
.LCPI2_2:
.quad 0x4010000000000000 # double 4
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $136, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $16, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl $10000000, %esi # imm = 0x989680
callq _ZNSolsEi
movq %rax, %rbx
movl $.L.str.1, %esi
movl $11, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%rbx), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r14
testq %r14, %r14
je .LBB2_21
# %bb.1: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%r14)
je .LBB2_3
# %bb.2:
movzbl 67(%r14), %eax
jmp .LBB2_4
.LBB2_3:
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.LBB2_4: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movq %rbx, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
leaq 24(%rsp), %rdi
movl $40000000, %esi # imm = 0x2625A00
movl $1, %edx
callq hipMallocManaged
leaq 8(%rsp), %rdi
movl $80000000, %esi # imm = 0x4C4B400
movl $1, %edx
callq hipMallocManaged
leaq 16(%rsp), %rdi
movl $80000000, %esi # imm = 0x4C4B400
movl $1, %edx
callq hipMallocManaged
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB2_5: # =>This Inner Loop Header: Depth=1
callq rand
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
movsd .LCPI2_0(%rip), %xmm1 # xmm1 = mem[0],zero
divsd %xmm1, %xmm0
movq 8(%rsp), %rax
movsd %xmm0, (%rax,%rbx,8)
callq rand
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
divsd .LCPI2_0(%rip), %xmm0
movq 16(%rsp), %rax
movsd %xmm0, (%rax,%rbx,8)
incq %rbx
cmpq $9999999, %rbx # imm = 0x98967F
jne .LBB2_5
# %bb.6:
movq %rsp, %rdi
movl $312500, %esi # imm = 0x4C4B4
movl $1, %edx
callq hipMallocManaged
movl $_ZSt4cout, %edi
movl $.L.str.2, %esi
movl $22, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl $128, %esi
callq _ZNSolsEi
movq %rax, %rbx
movl $.L.str.3, %esi
movl $12, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq %rbx, %rdi
movl $78125, %esi # imm = 0x1312D
callq _ZNSolsEi
movq %rax, %r14
movl $.L.str.4, %esi
movl $7, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%r14), %rax
movq -24(%rax), %rax
movq 240(%r14,%rax), %rbx
testq %rbx, %rbx
je .LBB2_21
# %bb.7: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i32
cmpb $0, 56(%rbx)
je .LBB2_9
# %bb.8:
movzbl 67(%rbx), %eax
jmp .LBB2_10
.LBB2_9:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB2_10: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit35
movabsq $4294967424, %rbx # imm = 0x100000080
movsbl %al, %esi
movq %r14, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
leaq 77997(%rbx), %r14
movq %r14, %rdi
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_12
# %bb.11:
movq 24(%rsp), %rax
movq 8(%rsp), %rcx
movq 16(%rsp), %rdx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movq %rdx, 40(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 128(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z9compute_rPiPdS0_, %edi
pushq 128(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_12:
callq hipDeviceSynchronize
movq %r14, %rdi
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_14
# %bb.13:
movq 24(%rsp), %rax
movq (%rsp), %rcx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z9reductionPiS_, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_14:
callq hipDeviceSynchronize
movq (%rsp), %rax
movl (%rax), %ecx
movl $1, %edx
.p2align 4, 0x90
.LBB2_15: # =>This Inner Loop Header: Depth=1
addl (%rax,%rdx,4), %ecx
incq %rdx
cmpq $78125, %rdx # imm = 0x1312D
jne .LBB2_15
# %bb.16:
movl %ecx, (%rax)
movq (%rsp), %rax
cvtsi2sdl (%rax), %xmm0
divsd .LCPI2_1(%rip), %xmm0
mulsd .LCPI2_2(%rip), %xmm0
movsd %xmm0, 120(%rsp) # 8-byte Spill
movl $_ZSt4cout, %edi
movl $.L.str.5, %esi
movl $6, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movsd 120(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB2_21
# %bb.17: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i37
cmpb $0, 56(%rbx)
je .LBB2_19
# %bb.18:
movzbl 67(%rbx), %ecx
jmp .LBB2_20
.LBB2_19:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB2_20: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit40
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $136, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.LBB2_21:
.cfi_def_cfa_offset 160
callq _ZSt16__throw_bad_castv
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9compute_rPiPdS0_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9reductionPiS_, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9compute_rPiPdS0_,@object # @_Z9compute_rPiPdS0_
.section .rodata,"a",@progbits
.globl _Z9compute_rPiPdS0_
.p2align 3, 0x0
_Z9compute_rPiPdS0_:
.quad _Z24__device_stub__compute_rPiPdS0_
.size _Z9compute_rPiPdS0_, 8
.type _Z9reductionPiS_,@object # @_Z9reductionPiS_
.globl _Z9reductionPiS_
.p2align 3, 0x0
_Z9reductionPiS_:
.quad _Z24__device_stub__reductionPiS_
.size _Z9reductionPiS_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Refine Pi using "
.size .L.str, 17
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz " iterations"
.size .L.str.1, 12
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Executing Kernel with "
.size .L.str.2, 23
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz " threads on "
.size .L.str.3, 13
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz " blocks"
.size .L.str.4, 8
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Pi is "
.size .L.str.5, 7
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z9compute_rPiPdS0_"
.size .L__unnamed_1, 20
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z9reductionPiS_"
.size .L__unnamed_2, 17
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__compute_rPiPdS0_
.addrsig_sym _Z24__device_stub__reductionPiS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9compute_rPiPdS0_
.addrsig_sym _Z9reductionPiS_
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
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