system stringclasses 7 values | input stringlengths 10 94.5k | output stringlengths 14 55.5k |
|---|---|---|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void cuda_activateTanh(double* pA, int n)
{
int id = blockIdx.x * blockDim.x + threadIdx.x;
if (id < n) {
pA[id] = tanh(pA[id]);
}
} | code for sm_80
Function : _Z17cuda_activateTanhPdi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R2, R2, c[0x0][0x0], R3 ; /* 0x0000000002027a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R2, c[0x0][0x168], PT ; /* 0x00005a0002007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ IMAD.MOV.U32 R3, RZ, RZ, 0x8 ; /* 0x00000008ff037424 */
/* 0x000fe200078e00ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0080*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0203 */
/*0090*/ LDG.E.64 R4, [R2.64] ; /* 0x0000000402047981 */
/* 0x000ea2000c1e1b00 */
/*00a0*/ BSSY B0, 0x440 ; /* 0x0000039000007945 */
/* 0x000fe20003800000 */
/*00b0*/ LOP3.LUT R7, R5, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff05077812 */
/* 0x004fe400078ec0ff */
/*00c0*/ MOV R6, R4 ; /* 0x0000000400067202 */
/* 0x000fcc0000000f00 */
/*00d0*/ DSETP.GE.AND P0, PT, R6, c[0x2][0x0], PT ; /* 0x008000000600762a */
/* 0x000e1c0003f06000 */
/*00e0*/ @!P0 BRA 0x340 ; /* 0x0000025000008947 */
/* 0x001fea0003800000 */
/*00f0*/ DADD R10, R6, R6 ; /* 0x00000000060a7229 */
/* 0x000e220000000006 */
/*0100*/ IMAD.MOV.U32 R12, RZ, RZ, -0x5b8be47f ; /* 0xa4741b81ff0c7424 */
/* 0x000fe200078e00ff */
/*0110*/ MOV R13, 0x3e5ae904 ; /* 0x3e5ae904000d7802 */
/* 0x000fe40000000f00 */
/*0120*/ ISETP.GT.U32.AND P0, PT, R7, 0x40330fc1, PT ; /* 0x40330fc10700780c */
/* 0x000fe40003f04070 */
/*0130*/ F2F.F32.F64 R0, R10 ; /* 0x0000000a00007310 */
/* 0x001e240000301000 */
/*0140*/ FMUL R0, R0, 1.4426950216293334961 ; /* 0x3fb8aa3b00007820 */
/* 0x001fcc0000400000 */
/*0150*/ FRND R0, R0 ; /* 0x0000000000007307 */
/* 0x000e300000201000 */
/*0160*/ F2F.F64.F32 R8, R0 ; /* 0x0000000000087310 */
/* 0x001e300000201800 */
/*0170*/ MUFU.EX2 R4, R0 ; /* 0x0000000000047308 */
/* 0x000e620000000800 */
/*0180*/ DFMA R8, -R8, c[0x2][0x8], R10 ; /* 0x0080020008087a2b */
/* 0x001e0c000000010a */
/*0190*/ DFMA R12, R8.reuse, R12, c[0x2][0x10] ; /* 0x00800400080c762b */
/* 0x041e22000000000c */
/*01a0*/ F2F.F64.F32 R10, R4 ; /* 0x00000004000a7310 */
/* 0x002e6a0000201800 */
/*01b0*/ DFMA R12, R8, R12, c[0x2][0x18] ; /* 0x00800600080c762b */
/* 0x001e0c000000000c */
/*01c0*/ DFMA R12, R8, R12, c[0x2][0x20] ; /* 0x00800800080c762b */
/* 0x001e0c000000000c */
/*01d0*/ DFMA R12, R8, R12, c[0x2][0x28] ; /* 0x00800a00080c762b */
/* 0x001e08000000000c */
/*01e0*/ DADD R14, -R10, 1 ; /* 0x3ff000000a0e7429 */
/* 0x002fc80000000100 */
/*01f0*/ DFMA R12, R8, R12, c[0x2][0x30] ; /* 0x00800c00080c762b */
/* 0x001e0c000000000c */
/*0200*/ DFMA R12, R8, R12, c[0x2][0x38] ; /* 0x00800e00080c762b */
/* 0x001e0c000000000c */
/*0210*/ DFMA R12, R8, R12, c[0x2][0x40] ; /* 0x00801000080c762b */
/* 0x001e0c000000000c */
/*0220*/ DFMA R12, R8, R12, c[0x2][0x48] ; /* 0x00801200080c762b */
/* 0x001e0c000000000c */
/*0230*/ DFMA R12, R8, R12, c[0x2][0x50] ; /* 0x00801400080c762b */
/* 0x001e0c000000000c */
/*0240*/ DMUL R12, R8, R12 ; /* 0x0000000c080c7228 */
/* 0x001e0c0000000000 */
/*0250*/ DFMA R12, R8, R12, R8 ; /* 0x0000000c080c722b */
/* 0x0010640000000008 */
/*0260*/ IMAD.MOV.U32 R8, RZ, RZ, RZ ; /* 0x000000ffff087224 */
/* 0x001fc800078e00ff */
/*0270*/ DFMA R12, -R12, R10, R14 ; /* 0x0000000a0c0c722b */
/* 0x002064000000010e */
/*0280*/ MOV R14, 0x0 ; /* 0x00000000000e7802 */
/* 0x001fe20000000f00 */
/*0290*/ IMAD.MOV.U32 R15, RZ, RZ, 0x40000000 ; /* 0x40000000ff0f7424 */
/* 0x000fc600078e00ff */
/*02a0*/ DADD R12, -R12, 2 ; /* 0x400000000c0c7429 */
/* 0x002e0c0000000100 */
/*02b0*/ MUFU.RCP64H R9, R13 ; /* 0x0000000d00097308 */
/* 0x001e240000001800 */
/*02c0*/ DFMA R10, -R12, R8, 1 ; /* 0x3ff000000c0a742b */
/* 0x001e0c0000000108 */
/*02d0*/ DFMA R10, R10, R10, R10 ; /* 0x0000000a0a0a722b */
/* 0x001e0c000000000a */
/*02e0*/ DFMA R10, R8, R10, R8 ; /* 0x0000000a080a722b */
/* 0x001e0c0000000008 */
/*02f0*/ DFMA R10, -R10, R14, 1 ; /* 0x3ff000000a0a742b */
/* 0x001e14000000010e */
/*0300*/ FSEL R7, R11, 1.875, !P0 ; /* 0x3ff000000b077808 */
/* 0x001fe40004000000 */
/*0310*/ FSEL R4, R10, RZ, !P0 ; /* 0x000000ff0a047208 */
/* 0x000fe40004000000 */
/*0320*/ LOP3.LUT R5, R7, 0x80000000, R5, 0xf8, !PT ; /* 0x8000000007057812 */
/* 0x000fe200078ef805 */
/*0330*/ BRA 0x430 ; /* 0x000000f000007947 */
/* 0x000fea0003800000 */
/*0340*/ DMUL R6, R4, R4 ; /* 0x0000000404067228 */
/* 0x000e220000000000 */
/*0350*/ MOV R8, 0xe2f5e964 ; /* 0xe2f5e96400087802 */
/* 0x000fe20000000f00 */
/*0360*/ IMAD.MOV.U32 R9, RZ, RZ, 0x3ef0bc46 ; /* 0x3ef0bc46ff097424 */
/* 0x000fcc00078e00ff */
/*0370*/ DFMA R8, R6, -R8, c[0x2][0x58] ; /* 0x008016000608762b */
/* 0x001e0c0000000808 */
/*0380*/ DFMA R8, R6, R8, c[0x2][0x60] ; /* 0x008018000608762b */
/* 0x001e0c0000000008 */
/*0390*/ DFMA R8, R6, R8, c[0x2][0x68] ; /* 0x00801a000608762b */
/* 0x001e0c0000000008 */
/*03a0*/ DFMA R8, R6, R8, c[0x2][0x70] ; /* 0x00801c000608762b */
/* 0x001e0c0000000008 */
/*03b0*/ DFMA R8, R6, R8, c[0x2][0x78] ; /* 0x00801e000608762b */
/* 0x001e0c0000000008 */
/*03c0*/ DFMA R8, R6, R8, c[0x2][0x80] ; /* 0x008020000608762b */
/* 0x001e0c0000000008 */
/*03d0*/ DFMA R8, R6, R8, c[0x2][0x88] ; /* 0x008022000608762b */
/* 0x001e0c0000000008 */
/*03e0*/ DFMA R8, R6, R8, c[0x2][0x90] ; /* 0x008024000608762b */
/* 0x001e0c0000000008 */
/*03f0*/ DFMA R8, R6, R8, c[0x2][0x98] ; /* 0x008026000608762b */
/* 0x001e0c0000000008 */
/*0400*/ DFMA R8, R6, R8, c[0x2][0xa0] ; /* 0x008028000608762b */
/* 0x001e0c0000000008 */
/*0410*/ DFMA R8, R6, R8, RZ ; /* 0x000000080608722b */
/* 0x001e0c00000000ff */
/*0420*/ DFMA R4, R4, R8, R4 ; /* 0x000000080404722b */
/* 0x00104c0000000004 */
/*0430*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0440*/ STG.E.64 [R2.64], R4 ; /* 0x0000000402007986 */
/* 0x002fe2000c101b04 */
/*0450*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0460*/ BRA 0x460; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0470*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0480*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0490*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void cuda_activateTanh(double* pA, int n)
{
int id = blockIdx.x * blockDim.x + threadIdx.x;
if (id < n) {
pA[id] = tanh(pA[id]);
}
} | .file "tmpxft_00003d68_00000000-6_cuda_activateTanh.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z38__device_stub__Z17cuda_activateTanhPdiPdi
.type _Z38__device_stub__Z17cuda_activateTanhPdiPdi, @function
_Z38__device_stub__Z17cuda_activateTanhPdiPdi:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z17cuda_activateTanhPdi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z38__device_stub__Z17cuda_activateTanhPdiPdi, .-_Z38__device_stub__Z17cuda_activateTanhPdiPdi
.globl _Z17cuda_activateTanhPdi
.type _Z17cuda_activateTanhPdi, @function
_Z17cuda_activateTanhPdi:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z38__device_stub__Z17cuda_activateTanhPdiPdi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z17cuda_activateTanhPdi, .-_Z17cuda_activateTanhPdi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z17cuda_activateTanhPdi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z17cuda_activateTanhPdi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void cuda_activateTanh(double* pA, int n)
{
int id = blockIdx.x * blockDim.x + threadIdx.x;
if (id < n) {
pA[id] = tanh(pA[id]);
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void cuda_activateTanh(double* pA, int n)
{
int id = blockIdx.x * blockDim.x + threadIdx.x;
if (id < n) {
pA[id] = tanh(pA[id]);
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void cuda_activateTanh(double* pA, int n)
{
int id = blockIdx.x * blockDim.x + threadIdx.x;
if (id < n) {
pA[id] = tanh(pA[id]);
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z17cuda_activateTanhPdi
.globl _Z17cuda_activateTanhPdi
.p2align 8
.type _Z17cuda_activateTanhPdi,@function
_Z17cuda_activateTanhPdi:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x1c
s_load_b32 s3, s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b64 s[0:1], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_mov_b32 s3, 0x3e5ade15
s_mov_b32 s2, 0x6a5dcb37
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 3, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_mov_b32 s1, 0x3ff71547
s_mov_b32 s0, 0x652b82fe
global_load_b64 v[2:3], v[0:1], off
s_waitcnt vmcnt(0)
v_mul_f64 v[4:5], |v[2:3]|, s[0:1]
s_mov_b32 s1, 0xbfe62e42
s_mov_b32 s0, 0xfefa3000
v_cmp_nlt_f64_e64 vcc_lo, 0x40331000, |v[2:3]|
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_rndne_f64_e32 v[4:5], v[4:5]
v_fma_f64 v[6:7], v[4:5], s[0:1], |v[2:3]|
s_mov_b32 s1, 0xbd53de6a
s_mov_b32 s0, 0xf278e000
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_mul_f64 v[8:9], v[4:5], s[0:1]
s_mov_b32 s1, 0xbac9cc01
s_mov_b32 s0, 0xf97b57a0
v_add_f64 v[10:11], v[6:7], 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_f64 v[12:13], v[10:11], v[8:9]
v_add_f64 v[6:7], v[6:7], -v[10:11]
v_add_f64 v[10:11], v[10:11], -v[12:13]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[6:7], v[6:7], 0
v_add_f64 v[8:9], v[10:11], v[8:9]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_add_f64 v[6:7], v[6:7], v[8:9]
v_mul_f64 v[8:9], v[4:5], s[0:1]
s_mov_b32 s1, 0x3e928af3
s_mov_b32 s0, 0xfca7ab0c
v_add_f64 v[10:11], v[12:13], v[6:7]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_f64 v[14:15], v[10:11], v[8:9]
v_add_f64 v[12:13], v[12:13], -v[10:11]
v_add_f64 v[10:11], v[10:11], -v[14:15]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[6:7], v[6:7], v[12:13]
v_add_f64 v[8:9], v[10:11], v[8:9]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[6:7], v[6:7], v[8:9]
v_add_f64 v[8:9], v[14:15], v[6:7]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_3)
v_fma_f64 v[10:11], v[8:9], s[2:3], s[0:1]
s_mov_b32 s1, 0x3ec71dee
s_mov_b32 s0, 0x623fde64
v_add_f64 v[12:13], v[14:15], -v[8:9]
v_mul_f64 v[14:15], v[8:9], v[8:9]
v_fma_f64 v[10:11], v[8:9], v[10:11], s[0:1]
s_mov_b32 s1, 0x3efa0199
s_mov_b32 s0, 0x7c89e6b0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f64 v[6:7], v[6:7], v[12:13]
v_fma_f64 v[12:13], v[8:9], v[8:9], -v[14:15]
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_fma_f64 v[10:11], v[8:9], v[10:11], s[0:1]
s_mov_b32 s1, 0x3f2a01a0
s_mov_b32 s0, 0x14761f6e
v_add_f64 v[16:17], v[6:7], v[6:7]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_fma_f64 v[10:11], v[8:9], v[10:11], s[0:1]
s_mov_b32 s1, 0x3f56c16c
s_mov_b32 s0, 0x1852b7b0
v_fma_f64 v[12:13], v[8:9], v[16:17], v[12:13]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_fma_f64 v[10:11], v[8:9], v[10:11], s[0:1]
s_mov_b32 s1, 0x3f811111
s_mov_b32 s0, 0x11122322
v_add_f64 v[16:17], v[14:15], v[12:13]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_fma_f64 v[10:11], v[8:9], v[10:11], s[0:1]
s_mov_b32 s1, 0x3fa55555
s_mov_b32 s0, 0x555502a1
v_add_f64 v[14:15], v[16:17], -v[14:15]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_fma_f64 v[10:11], v[8:9], v[10:11], s[0:1]
s_mov_b32 s1, 0x3fc55555
s_mov_b32 s0, 0x55555511
v_add_f64 v[12:13], v[12:13], -v[14:15]
s_delay_alu instid0(VALU_DEP_2)
v_fma_f64 v[10:11], v[8:9], v[10:11], s[0:1]
s_mov_b32 s1, 0x3fe00000
s_mov_b32 s0, 11
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fma_f64 v[10:11], v[8:9], v[10:11], s[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[18:19], v[16:17], v[10:11]
v_fma_f64 v[14:15], v[16:17], v[10:11], -v[18:19]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[10:11], v[12:13], v[10:11], v[14:15]
v_add_f64 v[12:13], v[18:19], v[10:11]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_f64 v[14:15], v[8:9], v[12:13]
v_add_f64 v[16:17], v[12:13], -v[18:19]
v_add_f64 v[8:9], v[14:15], -v[8:9]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_f64 v[10:11], v[10:11], -v[16:17]
v_cvt_i32_f64_e32 v16, v[4:5]
v_add_f64 v[8:9], v[12:13], -v[8:9]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[6:7], v[6:7], v[10:11]
v_add_f64 v[6:7], v[6:7], v[8:9]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[8:9], v[14:15], v[6:7]
v_add_f64 v[10:11], v[8:9], 1.0
v_add_f64 v[12:13], v[8:9], -v[14:15]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[14:15], v[10:11], -1.0
v_add_f64 v[6:7], v[6:7], -v[12:13]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[8:9], v[8:9], -v[14:15]
v_add_f64 v[6:7], v[6:7], v[8:9]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[4:5], v[10:11], v[6:7]
v_ldexp_f64 v[8:9], v[4:5], v16
v_add_f64 v[4:5], v[4:5], -v[10:11]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_rcp_f64_e32 v[12:13], v[8:9]
v_add_f64 v[4:5], v[6:7], -v[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_ldexp_f64 v[4:5], v[4:5], v16
s_waitcnt_depctr 0xfff
v_fma_f64 v[14:15], -v[8:9], v[12:13], 1.0
v_fma_f64 v[12:13], v[14:15], v[12:13], v[12:13]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[14:15], -v[8:9], v[12:13], 1.0
v_fma_f64 v[10:11], v[14:15], v[12:13], v[12:13]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[6:7], v[8:9], v[10:11]
v_fma_f64 v[12:13], v[10:11], v[8:9], -v[6:7]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[12:13], v[10:11], v[4:5], v[12:13]
v_add_f64 v[14:15], v[6:7], v[12:13]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_f64 v[16:17], -v[14:15], 1.0
v_add_f64 v[6:7], v[14:15], -v[6:7]
v_add_f64 v[18:19], -v[16:17], 1.0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[6:7], v[6:7], -v[12:13]
v_add_f64 v[12:13], v[18:19], -v[14:15]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[6:7], v[6:7], v[12:13]
v_add_f64 v[12:13], v[16:17], v[6:7]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_f64 v[14:15], v[10:11], v[12:13]
v_add_f64 v[16:17], v[16:17], -v[12:13]
v_mul_f64 v[18:19], v[8:9], v[14:15]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[6:7], v[6:7], v[16:17]
v_fma_f64 v[20:21], v[14:15], v[8:9], -v[18:19]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[20:21], v[14:15], v[4:5], v[20:21]
v_add_f64 v[22:23], v[18:19], v[20:21]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_f64 v[24:25], v[12:13], -v[22:23]
v_add_f64 v[16:17], v[22:23], -v[18:19]
v_add_f64 v[12:13], v[12:13], -v[24:25]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[16:17], v[16:17], -v[20:21]
v_add_f64 v[12:13], v[12:13], -v[22:23]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_f64 v[6:7], v[6:7], v[12:13]
v_add_f64 v[12:13], v[10:11], v[14:15]
v_add_f64 v[6:7], v[16:17], v[6:7]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[16:17], v[12:13], -v[10:11]
v_add_f64 v[6:7], v[24:25], v[6:7]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[14:15], v[14:15], -v[16:17]
v_mul_f64 v[6:7], v[10:11], v[6:7]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[6:7], v[14:15], v[6:7]
v_add_f64 v[10:11], v[12:13], v[6:7]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_add_f64 v[14:15], v[8:9], v[10:11]
v_add_f64 v[12:13], v[10:11], -v[12:13]
v_add_f64 v[18:19], v[8:9], -v[10:11]
v_add_f64 v[16:17], v[14:15], -v[8:9]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f64 v[6:7], v[6:7], -v[12:13]
v_add_f64 v[8:9], v[8:9], -v[18:19]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f64 v[12:13], v[10:11], -v[16:17]
v_add_f64 v[16:17], v[4:5], v[6:7]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[8:9], v[8:9], -v[10:11]
v_add_f64 v[12:13], v[16:17], v[12:13]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[4:5], v[4:5], v[8:9]
v_add_f64 v[16:17], v[14:15], v[12:13]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[4:5], v[4:5], -v[6:7]
v_rcp_f64_e32 v[20:21], v[16:17]
v_add_f64 v[14:15], v[16:17], -v[14:15]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_add_f64 v[12:13], v[12:13], -v[14:15]
s_waitcnt_depctr 0xfff
v_fma_f64 v[10:11], -v[16:17], v[20:21], 1.0
v_fma_f64 v[8:9], v[10:11], v[20:21], v[20:21]
v_add_f64 v[10:11], v[18:19], v[4:5]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[6:7], -v[16:17], v[8:9], 1.0
v_fma_f64 v[6:7], v[6:7], v[8:9], v[8:9]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[8:9], v[10:11], v[6:7]
v_mul_f64 v[20:21], v[16:17], v[8:9]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[14:15], v[8:9], v[16:17], -v[20:21]
v_fma_f64 v[12:13], v[8:9], v[12:13], v[14:15]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[14:15], v[20:21], v[12:13]
v_add_f64 v[16:17], v[10:11], -v[14:15]
v_add_f64 v[20:21], v[14:15], -v[20:21]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_f64 v[22:23], v[10:11], -v[16:17]
v_add_f64 v[10:11], v[10:11], -v[18:19]
v_add_f64 v[12:13], v[12:13], -v[20:21]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f64 v[14:15], v[22:23], -v[14:15]
v_add_f64 v[4:5], v[4:5], -v[10:11]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[10:11], v[14:15], -v[12:13]
v_add_f64 v[4:5], v[4:5], v[10:11]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[4:5], v[16:17], v[4:5]
v_mul_f64 v[4:5], v[6:7], v[4:5]
v_and_b32_e32 v6, 0x7fffffff, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[4:5], v[8:9], v[4:5]
v_cndmask_b32_e32 v5, 0x3ff00000, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v4, 0, v4, vcc_lo
v_cmp_gt_f64_e64 vcc_lo, 0x3e400000, |v[2:3]|
v_cndmask_b32_e32 v2, v4, v2, vcc_lo
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v4, v5, v6, vcc_lo
v_bfi_b32 v3, 0x7fffffff, v4, v3
global_store_b64 v[0:1], v[2:3], off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z17cuda_activateTanhPdi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 26
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z17cuda_activateTanhPdi, .Lfunc_end0-_Z17cuda_activateTanhPdi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z17cuda_activateTanhPdi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z17cuda_activateTanhPdi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 26
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void cuda_activateTanh(double* pA, int n)
{
int id = blockIdx.x * blockDim.x + threadIdx.x;
if (id < n) {
pA[id] = tanh(pA[id]);
}
} | .text
.file "cuda_activateTanh.hip"
.globl _Z32__device_stub__cuda_activateTanhPdi # -- Begin function _Z32__device_stub__cuda_activateTanhPdi
.p2align 4, 0x90
.type _Z32__device_stub__cuda_activateTanhPdi,@function
_Z32__device_stub__cuda_activateTanhPdi: # @_Z32__device_stub__cuda_activateTanhPdi
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z17cuda_activateTanhPdi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z32__device_stub__cuda_activateTanhPdi, .Lfunc_end0-_Z32__device_stub__cuda_activateTanhPdi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z17cuda_activateTanhPdi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z17cuda_activateTanhPdi,@object # @_Z17cuda_activateTanhPdi
.section .rodata,"a",@progbits
.globl _Z17cuda_activateTanhPdi
.p2align 3, 0x0
_Z17cuda_activateTanhPdi:
.quad _Z32__device_stub__cuda_activateTanhPdi
.size _Z17cuda_activateTanhPdi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z17cuda_activateTanhPdi"
.size .L__unnamed_1, 25
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z32__device_stub__cuda_activateTanhPdi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z17cuda_activateTanhPdi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z17cuda_activateTanhPdi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R2, R2, c[0x0][0x0], R3 ; /* 0x0000000002027a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R2, c[0x0][0x168], PT ; /* 0x00005a0002007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ IMAD.MOV.U32 R3, RZ, RZ, 0x8 ; /* 0x00000008ff037424 */
/* 0x000fe200078e00ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0080*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0203 */
/*0090*/ LDG.E.64 R4, [R2.64] ; /* 0x0000000402047981 */
/* 0x000ea2000c1e1b00 */
/*00a0*/ BSSY B0, 0x440 ; /* 0x0000039000007945 */
/* 0x000fe20003800000 */
/*00b0*/ LOP3.LUT R7, R5, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff05077812 */
/* 0x004fe400078ec0ff */
/*00c0*/ MOV R6, R4 ; /* 0x0000000400067202 */
/* 0x000fcc0000000f00 */
/*00d0*/ DSETP.GE.AND P0, PT, R6, c[0x2][0x0], PT ; /* 0x008000000600762a */
/* 0x000e1c0003f06000 */
/*00e0*/ @!P0 BRA 0x340 ; /* 0x0000025000008947 */
/* 0x001fea0003800000 */
/*00f0*/ DADD R10, R6, R6 ; /* 0x00000000060a7229 */
/* 0x000e220000000006 */
/*0100*/ IMAD.MOV.U32 R12, RZ, RZ, -0x5b8be47f ; /* 0xa4741b81ff0c7424 */
/* 0x000fe200078e00ff */
/*0110*/ MOV R13, 0x3e5ae904 ; /* 0x3e5ae904000d7802 */
/* 0x000fe40000000f00 */
/*0120*/ ISETP.GT.U32.AND P0, PT, R7, 0x40330fc1, PT ; /* 0x40330fc10700780c */
/* 0x000fe40003f04070 */
/*0130*/ F2F.F32.F64 R0, R10 ; /* 0x0000000a00007310 */
/* 0x001e240000301000 */
/*0140*/ FMUL R0, R0, 1.4426950216293334961 ; /* 0x3fb8aa3b00007820 */
/* 0x001fcc0000400000 */
/*0150*/ FRND R0, R0 ; /* 0x0000000000007307 */
/* 0x000e300000201000 */
/*0160*/ F2F.F64.F32 R8, R0 ; /* 0x0000000000087310 */
/* 0x001e300000201800 */
/*0170*/ MUFU.EX2 R4, R0 ; /* 0x0000000000047308 */
/* 0x000e620000000800 */
/*0180*/ DFMA R8, -R8, c[0x2][0x8], R10 ; /* 0x0080020008087a2b */
/* 0x001e0c000000010a */
/*0190*/ DFMA R12, R8.reuse, R12, c[0x2][0x10] ; /* 0x00800400080c762b */
/* 0x041e22000000000c */
/*01a0*/ F2F.F64.F32 R10, R4 ; /* 0x00000004000a7310 */
/* 0x002e6a0000201800 */
/*01b0*/ DFMA R12, R8, R12, c[0x2][0x18] ; /* 0x00800600080c762b */
/* 0x001e0c000000000c */
/*01c0*/ DFMA R12, R8, R12, c[0x2][0x20] ; /* 0x00800800080c762b */
/* 0x001e0c000000000c */
/*01d0*/ DFMA R12, R8, R12, c[0x2][0x28] ; /* 0x00800a00080c762b */
/* 0x001e08000000000c */
/*01e0*/ DADD R14, -R10, 1 ; /* 0x3ff000000a0e7429 */
/* 0x002fc80000000100 */
/*01f0*/ DFMA R12, R8, R12, c[0x2][0x30] ; /* 0x00800c00080c762b */
/* 0x001e0c000000000c */
/*0200*/ DFMA R12, R8, R12, c[0x2][0x38] ; /* 0x00800e00080c762b */
/* 0x001e0c000000000c */
/*0210*/ DFMA R12, R8, R12, c[0x2][0x40] ; /* 0x00801000080c762b */
/* 0x001e0c000000000c */
/*0220*/ DFMA R12, R8, R12, c[0x2][0x48] ; /* 0x00801200080c762b */
/* 0x001e0c000000000c */
/*0230*/ DFMA R12, R8, R12, c[0x2][0x50] ; /* 0x00801400080c762b */
/* 0x001e0c000000000c */
/*0240*/ DMUL R12, R8, R12 ; /* 0x0000000c080c7228 */
/* 0x001e0c0000000000 */
/*0250*/ DFMA R12, R8, R12, R8 ; /* 0x0000000c080c722b */
/* 0x0010640000000008 */
/*0260*/ IMAD.MOV.U32 R8, RZ, RZ, RZ ; /* 0x000000ffff087224 */
/* 0x001fc800078e00ff */
/*0270*/ DFMA R12, -R12, R10, R14 ; /* 0x0000000a0c0c722b */
/* 0x002064000000010e */
/*0280*/ MOV R14, 0x0 ; /* 0x00000000000e7802 */
/* 0x001fe20000000f00 */
/*0290*/ IMAD.MOV.U32 R15, RZ, RZ, 0x40000000 ; /* 0x40000000ff0f7424 */
/* 0x000fc600078e00ff */
/*02a0*/ DADD R12, -R12, 2 ; /* 0x400000000c0c7429 */
/* 0x002e0c0000000100 */
/*02b0*/ MUFU.RCP64H R9, R13 ; /* 0x0000000d00097308 */
/* 0x001e240000001800 */
/*02c0*/ DFMA R10, -R12, R8, 1 ; /* 0x3ff000000c0a742b */
/* 0x001e0c0000000108 */
/*02d0*/ DFMA R10, R10, R10, R10 ; /* 0x0000000a0a0a722b */
/* 0x001e0c000000000a */
/*02e0*/ DFMA R10, R8, R10, R8 ; /* 0x0000000a080a722b */
/* 0x001e0c0000000008 */
/*02f0*/ DFMA R10, -R10, R14, 1 ; /* 0x3ff000000a0a742b */
/* 0x001e14000000010e */
/*0300*/ FSEL R7, R11, 1.875, !P0 ; /* 0x3ff000000b077808 */
/* 0x001fe40004000000 */
/*0310*/ FSEL R4, R10, RZ, !P0 ; /* 0x000000ff0a047208 */
/* 0x000fe40004000000 */
/*0320*/ LOP3.LUT R5, R7, 0x80000000, R5, 0xf8, !PT ; /* 0x8000000007057812 */
/* 0x000fe200078ef805 */
/*0330*/ BRA 0x430 ; /* 0x000000f000007947 */
/* 0x000fea0003800000 */
/*0340*/ DMUL R6, R4, R4 ; /* 0x0000000404067228 */
/* 0x000e220000000000 */
/*0350*/ MOV R8, 0xe2f5e964 ; /* 0xe2f5e96400087802 */
/* 0x000fe20000000f00 */
/*0360*/ IMAD.MOV.U32 R9, RZ, RZ, 0x3ef0bc46 ; /* 0x3ef0bc46ff097424 */
/* 0x000fcc00078e00ff */
/*0370*/ DFMA R8, R6, -R8, c[0x2][0x58] ; /* 0x008016000608762b */
/* 0x001e0c0000000808 */
/*0380*/ DFMA R8, R6, R8, c[0x2][0x60] ; /* 0x008018000608762b */
/* 0x001e0c0000000008 */
/*0390*/ DFMA R8, R6, R8, c[0x2][0x68] ; /* 0x00801a000608762b */
/* 0x001e0c0000000008 */
/*03a0*/ DFMA R8, R6, R8, c[0x2][0x70] ; /* 0x00801c000608762b */
/* 0x001e0c0000000008 */
/*03b0*/ DFMA R8, R6, R8, c[0x2][0x78] ; /* 0x00801e000608762b */
/* 0x001e0c0000000008 */
/*03c0*/ DFMA R8, R6, R8, c[0x2][0x80] ; /* 0x008020000608762b */
/* 0x001e0c0000000008 */
/*03d0*/ DFMA R8, R6, R8, c[0x2][0x88] ; /* 0x008022000608762b */
/* 0x001e0c0000000008 */
/*03e0*/ DFMA R8, R6, R8, c[0x2][0x90] ; /* 0x008024000608762b */
/* 0x001e0c0000000008 */
/*03f0*/ DFMA R8, R6, R8, c[0x2][0x98] ; /* 0x008026000608762b */
/* 0x001e0c0000000008 */
/*0400*/ DFMA R8, R6, R8, c[0x2][0xa0] ; /* 0x008028000608762b */
/* 0x001e0c0000000008 */
/*0410*/ DFMA R8, R6, R8, RZ ; /* 0x000000080608722b */
/* 0x001e0c00000000ff */
/*0420*/ DFMA R4, R4, R8, R4 ; /* 0x000000080404722b */
/* 0x00104c0000000004 */
/*0430*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0440*/ STG.E.64 [R2.64], R4 ; /* 0x0000000402007986 */
/* 0x002fe2000c101b04 */
/*0450*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0460*/ BRA 0x460; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0470*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0480*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0490*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z17cuda_activateTanhPdi
.globl _Z17cuda_activateTanhPdi
.p2align 8
.type _Z17cuda_activateTanhPdi,@function
_Z17cuda_activateTanhPdi:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x1c
s_load_b32 s3, s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b64 s[0:1], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_mov_b32 s3, 0x3e5ade15
s_mov_b32 s2, 0x6a5dcb37
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 3, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_mov_b32 s1, 0x3ff71547
s_mov_b32 s0, 0x652b82fe
global_load_b64 v[2:3], v[0:1], off
s_waitcnt vmcnt(0)
v_mul_f64 v[4:5], |v[2:3]|, s[0:1]
s_mov_b32 s1, 0xbfe62e42
s_mov_b32 s0, 0xfefa3000
v_cmp_nlt_f64_e64 vcc_lo, 0x40331000, |v[2:3]|
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_rndne_f64_e32 v[4:5], v[4:5]
v_fma_f64 v[6:7], v[4:5], s[0:1], |v[2:3]|
s_mov_b32 s1, 0xbd53de6a
s_mov_b32 s0, 0xf278e000
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_mul_f64 v[8:9], v[4:5], s[0:1]
s_mov_b32 s1, 0xbac9cc01
s_mov_b32 s0, 0xf97b57a0
v_add_f64 v[10:11], v[6:7], 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_f64 v[12:13], v[10:11], v[8:9]
v_add_f64 v[6:7], v[6:7], -v[10:11]
v_add_f64 v[10:11], v[10:11], -v[12:13]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[6:7], v[6:7], 0
v_add_f64 v[8:9], v[10:11], v[8:9]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_add_f64 v[6:7], v[6:7], v[8:9]
v_mul_f64 v[8:9], v[4:5], s[0:1]
s_mov_b32 s1, 0x3e928af3
s_mov_b32 s0, 0xfca7ab0c
v_add_f64 v[10:11], v[12:13], v[6:7]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_f64 v[14:15], v[10:11], v[8:9]
v_add_f64 v[12:13], v[12:13], -v[10:11]
v_add_f64 v[10:11], v[10:11], -v[14:15]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[6:7], v[6:7], v[12:13]
v_add_f64 v[8:9], v[10:11], v[8:9]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[6:7], v[6:7], v[8:9]
v_add_f64 v[8:9], v[14:15], v[6:7]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_3)
v_fma_f64 v[10:11], v[8:9], s[2:3], s[0:1]
s_mov_b32 s1, 0x3ec71dee
s_mov_b32 s0, 0x623fde64
v_add_f64 v[12:13], v[14:15], -v[8:9]
v_mul_f64 v[14:15], v[8:9], v[8:9]
v_fma_f64 v[10:11], v[8:9], v[10:11], s[0:1]
s_mov_b32 s1, 0x3efa0199
s_mov_b32 s0, 0x7c89e6b0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f64 v[6:7], v[6:7], v[12:13]
v_fma_f64 v[12:13], v[8:9], v[8:9], -v[14:15]
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_fma_f64 v[10:11], v[8:9], v[10:11], s[0:1]
s_mov_b32 s1, 0x3f2a01a0
s_mov_b32 s0, 0x14761f6e
v_add_f64 v[16:17], v[6:7], v[6:7]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_fma_f64 v[10:11], v[8:9], v[10:11], s[0:1]
s_mov_b32 s1, 0x3f56c16c
s_mov_b32 s0, 0x1852b7b0
v_fma_f64 v[12:13], v[8:9], v[16:17], v[12:13]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_fma_f64 v[10:11], v[8:9], v[10:11], s[0:1]
s_mov_b32 s1, 0x3f811111
s_mov_b32 s0, 0x11122322
v_add_f64 v[16:17], v[14:15], v[12:13]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_fma_f64 v[10:11], v[8:9], v[10:11], s[0:1]
s_mov_b32 s1, 0x3fa55555
s_mov_b32 s0, 0x555502a1
v_add_f64 v[14:15], v[16:17], -v[14:15]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_fma_f64 v[10:11], v[8:9], v[10:11], s[0:1]
s_mov_b32 s1, 0x3fc55555
s_mov_b32 s0, 0x55555511
v_add_f64 v[12:13], v[12:13], -v[14:15]
s_delay_alu instid0(VALU_DEP_2)
v_fma_f64 v[10:11], v[8:9], v[10:11], s[0:1]
s_mov_b32 s1, 0x3fe00000
s_mov_b32 s0, 11
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fma_f64 v[10:11], v[8:9], v[10:11], s[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[18:19], v[16:17], v[10:11]
v_fma_f64 v[14:15], v[16:17], v[10:11], -v[18:19]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[10:11], v[12:13], v[10:11], v[14:15]
v_add_f64 v[12:13], v[18:19], v[10:11]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_f64 v[14:15], v[8:9], v[12:13]
v_add_f64 v[16:17], v[12:13], -v[18:19]
v_add_f64 v[8:9], v[14:15], -v[8:9]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_f64 v[10:11], v[10:11], -v[16:17]
v_cvt_i32_f64_e32 v16, v[4:5]
v_add_f64 v[8:9], v[12:13], -v[8:9]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[6:7], v[6:7], v[10:11]
v_add_f64 v[6:7], v[6:7], v[8:9]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[8:9], v[14:15], v[6:7]
v_add_f64 v[10:11], v[8:9], 1.0
v_add_f64 v[12:13], v[8:9], -v[14:15]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[14:15], v[10:11], -1.0
v_add_f64 v[6:7], v[6:7], -v[12:13]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[8:9], v[8:9], -v[14:15]
v_add_f64 v[6:7], v[6:7], v[8:9]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[4:5], v[10:11], v[6:7]
v_ldexp_f64 v[8:9], v[4:5], v16
v_add_f64 v[4:5], v[4:5], -v[10:11]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_rcp_f64_e32 v[12:13], v[8:9]
v_add_f64 v[4:5], v[6:7], -v[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_ldexp_f64 v[4:5], v[4:5], v16
s_waitcnt_depctr 0xfff
v_fma_f64 v[14:15], -v[8:9], v[12:13], 1.0
v_fma_f64 v[12:13], v[14:15], v[12:13], v[12:13]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[14:15], -v[8:9], v[12:13], 1.0
v_fma_f64 v[10:11], v[14:15], v[12:13], v[12:13]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[6:7], v[8:9], v[10:11]
v_fma_f64 v[12:13], v[10:11], v[8:9], -v[6:7]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[12:13], v[10:11], v[4:5], v[12:13]
v_add_f64 v[14:15], v[6:7], v[12:13]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_f64 v[16:17], -v[14:15], 1.0
v_add_f64 v[6:7], v[14:15], -v[6:7]
v_add_f64 v[18:19], -v[16:17], 1.0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[6:7], v[6:7], -v[12:13]
v_add_f64 v[12:13], v[18:19], -v[14:15]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[6:7], v[6:7], v[12:13]
v_add_f64 v[12:13], v[16:17], v[6:7]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_f64 v[14:15], v[10:11], v[12:13]
v_add_f64 v[16:17], v[16:17], -v[12:13]
v_mul_f64 v[18:19], v[8:9], v[14:15]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[6:7], v[6:7], v[16:17]
v_fma_f64 v[20:21], v[14:15], v[8:9], -v[18:19]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[20:21], v[14:15], v[4:5], v[20:21]
v_add_f64 v[22:23], v[18:19], v[20:21]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_f64 v[24:25], v[12:13], -v[22:23]
v_add_f64 v[16:17], v[22:23], -v[18:19]
v_add_f64 v[12:13], v[12:13], -v[24:25]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[16:17], v[16:17], -v[20:21]
v_add_f64 v[12:13], v[12:13], -v[22:23]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_f64 v[6:7], v[6:7], v[12:13]
v_add_f64 v[12:13], v[10:11], v[14:15]
v_add_f64 v[6:7], v[16:17], v[6:7]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[16:17], v[12:13], -v[10:11]
v_add_f64 v[6:7], v[24:25], v[6:7]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[14:15], v[14:15], -v[16:17]
v_mul_f64 v[6:7], v[10:11], v[6:7]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[6:7], v[14:15], v[6:7]
v_add_f64 v[10:11], v[12:13], v[6:7]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_add_f64 v[14:15], v[8:9], v[10:11]
v_add_f64 v[12:13], v[10:11], -v[12:13]
v_add_f64 v[18:19], v[8:9], -v[10:11]
v_add_f64 v[16:17], v[14:15], -v[8:9]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f64 v[6:7], v[6:7], -v[12:13]
v_add_f64 v[8:9], v[8:9], -v[18:19]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f64 v[12:13], v[10:11], -v[16:17]
v_add_f64 v[16:17], v[4:5], v[6:7]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[8:9], v[8:9], -v[10:11]
v_add_f64 v[12:13], v[16:17], v[12:13]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[4:5], v[4:5], v[8:9]
v_add_f64 v[16:17], v[14:15], v[12:13]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[4:5], v[4:5], -v[6:7]
v_rcp_f64_e32 v[20:21], v[16:17]
v_add_f64 v[14:15], v[16:17], -v[14:15]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_add_f64 v[12:13], v[12:13], -v[14:15]
s_waitcnt_depctr 0xfff
v_fma_f64 v[10:11], -v[16:17], v[20:21], 1.0
v_fma_f64 v[8:9], v[10:11], v[20:21], v[20:21]
v_add_f64 v[10:11], v[18:19], v[4:5]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[6:7], -v[16:17], v[8:9], 1.0
v_fma_f64 v[6:7], v[6:7], v[8:9], v[8:9]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[8:9], v[10:11], v[6:7]
v_mul_f64 v[20:21], v[16:17], v[8:9]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[14:15], v[8:9], v[16:17], -v[20:21]
v_fma_f64 v[12:13], v[8:9], v[12:13], v[14:15]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[14:15], v[20:21], v[12:13]
v_add_f64 v[16:17], v[10:11], -v[14:15]
v_add_f64 v[20:21], v[14:15], -v[20:21]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_f64 v[22:23], v[10:11], -v[16:17]
v_add_f64 v[10:11], v[10:11], -v[18:19]
v_add_f64 v[12:13], v[12:13], -v[20:21]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f64 v[14:15], v[22:23], -v[14:15]
v_add_f64 v[4:5], v[4:5], -v[10:11]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[10:11], v[14:15], -v[12:13]
v_add_f64 v[4:5], v[4:5], v[10:11]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[4:5], v[16:17], v[4:5]
v_mul_f64 v[4:5], v[6:7], v[4:5]
v_and_b32_e32 v6, 0x7fffffff, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[4:5], v[8:9], v[4:5]
v_cndmask_b32_e32 v5, 0x3ff00000, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v4, 0, v4, vcc_lo
v_cmp_gt_f64_e64 vcc_lo, 0x3e400000, |v[2:3]|
v_cndmask_b32_e32 v2, v4, v2, vcc_lo
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v4, v5, v6, vcc_lo
v_bfi_b32 v3, 0x7fffffff, v4, v3
global_store_b64 v[0:1], v[2:3], off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z17cuda_activateTanhPdi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 26
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z17cuda_activateTanhPdi, .Lfunc_end0-_Z17cuda_activateTanhPdi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z17cuda_activateTanhPdi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z17cuda_activateTanhPdi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 26
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00003d68_00000000-6_cuda_activateTanh.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z38__device_stub__Z17cuda_activateTanhPdiPdi
.type _Z38__device_stub__Z17cuda_activateTanhPdiPdi, @function
_Z38__device_stub__Z17cuda_activateTanhPdiPdi:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z17cuda_activateTanhPdi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z38__device_stub__Z17cuda_activateTanhPdiPdi, .-_Z38__device_stub__Z17cuda_activateTanhPdiPdi
.globl _Z17cuda_activateTanhPdi
.type _Z17cuda_activateTanhPdi, @function
_Z17cuda_activateTanhPdi:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z38__device_stub__Z17cuda_activateTanhPdiPdi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z17cuda_activateTanhPdi, .-_Z17cuda_activateTanhPdi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z17cuda_activateTanhPdi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z17cuda_activateTanhPdi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "cuda_activateTanh.hip"
.globl _Z32__device_stub__cuda_activateTanhPdi # -- Begin function _Z32__device_stub__cuda_activateTanhPdi
.p2align 4, 0x90
.type _Z32__device_stub__cuda_activateTanhPdi,@function
_Z32__device_stub__cuda_activateTanhPdi: # @_Z32__device_stub__cuda_activateTanhPdi
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z17cuda_activateTanhPdi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z32__device_stub__cuda_activateTanhPdi, .Lfunc_end0-_Z32__device_stub__cuda_activateTanhPdi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z17cuda_activateTanhPdi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z17cuda_activateTanhPdi,@object # @_Z17cuda_activateTanhPdi
.section .rodata,"a",@progbits
.globl _Z17cuda_activateTanhPdi
.p2align 3, 0x0
_Z17cuda_activateTanhPdi:
.quad _Z32__device_stub__cuda_activateTanhPdi
.size _Z17cuda_activateTanhPdi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z17cuda_activateTanhPdi"
.size .L__unnamed_1, 25
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z32__device_stub__cuda_activateTanhPdi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z17cuda_activateTanhPdi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <assert.h>
#include <cuda_runtime.h>
#include <stdlib.h>
#include <time.h>
#include <math.h>
#include <string.h>
#define BLOCK_SIZE 16
void printDeviceProp(const cudaDeviceProp &prop) {
printf("Device Name : %s.\n", prop.name);
printf("totalGlobalMem : %lu.\n", prop.totalGlobalMem);
printf("sharedMemPerBlock : %lu.\n", prop.sharedMemPerBlock);
printf("regsPerBlock : %d.\n", prop.regsPerBlock);
printf("warpSize : %d.\n", prop.warpSize);
printf("memPitch : %lu.\n", prop.memPitch);
printf("maxThreadsPerBlock : %d.\n", prop.maxThreadsPerBlock);
printf("maxThreadsDim[0 - 2] : %d %d %d.\n", prop.maxThreadsDim[0], prop.maxThreadsDim[1], prop.maxThreadsDim[2]);
printf("maxGridSize[0 - 2] : %d %d %d.\n", prop.maxGridSize[0], prop.maxGridSize[1], prop.maxGridSize[2]);
printf("totalConstMem : %lu.\n", prop.totalConstMem);
printf("major.minor : %d.%d.\n", prop.major, prop.minor);
printf("clockRate : %d.\n", prop.clockRate);
printf("textureAlignment : %lu.\n", prop.textureAlignment);
printf("deviceOverlap : %d.\n", prop.deviceOverlap);
printf("multiProcessorCount : %d.\n", prop.multiProcessorCount);
}
bool InitCUDA() {
int count;
cudaGetDeviceCount(&count);
if (count == 0) {
fprintf(stderr, "There is no device.\n");
return false;
}
int i;
for (i = 0; i < count; i++) {
cudaDeviceProp prop;
cudaGetDeviceProperties(&prop, i);
printDeviceProp(prop);
if (cudaGetDeviceProperties(&prop, i) == cudaSuccess) {
if (prop.major >= 1) {
break;
}
}
}
if (i == count) {
fprintf(stderr, "There is no device supporting CUDA 1.x.\n");
return false;
}
cudaSetDevice(i);
return true;
}
//CPU
void matrixMulCPU(float* res,const float *matrixA,const float *matrixB,int colsA,int rowsA,int rowsB) {
float sum = 0;
for (int i = 0; i < rowsA; ++i) {
for (int j = 0; j < rowsB; ++j) {
sum = 0;
for (int k = 0; k < colsA; ++k) {
sum += (float)matrixA[i*colsA+k]*(float)matrixB[k*rowsB+ j];
}
res[i*rowsB+j] = (float)sum;
}
}
}
// GPU
// C(i,j) = sum{A(i, k)* B(k ,j)}
// each thread cal C(i, j)
__global__ void matrixMulGPUKernal0(float* matrixC,const float* matrixA,const float *matrixB,int colsA,int rowsB) {
float sum = 0;
int row = blockIdx.y*blockDim.y + threadIdx.y;
int col = blockIdx.x*blockDim.x + threadIdx.x;
for (int i = 0; i < colsA; ++i) {
sum += matrixA[row*colsA + i] * matrixB[i*rowsB + col];
}
matrixC[row*rowsB + col] = sum;
}
// Csub(i,j) = sum{A(i,ksub+offsetA)*B(ksub+offsetB,j)} 0 <= ksub < blockSize
// C(i,j) = sum{Csub(i,j)}
// each thread cal each block
__global__ void matrixMulGPUKernal1(float* matrixC,const float* matrixA,const float *matrixB,int colsA,int rowsB) {
int bx = blockIdx.x;
int by = blockIdx.y;
int tx = threadIdx.x;
int ty = threadIdx.y;
int aBegin = colsA*(by*BLOCK_SIZE);//A(0,by)
int aEnd = aBegin + colsA - 1;
int aStep = BLOCK_SIZE;//offsetA
int bBegin = BLOCK_SIZE*bx;//B(bx,0)
int bStep = BLOCK_SIZE*rowsB;//offsetB
float cSub = 0;
for (int a = aBegin,b = bBegin; a <= aEnd; a += aStep,b += bStep) {
__shared__ float As[BLOCK_SIZE][BLOCK_SIZE];
__shared__ float Bs[BLOCK_SIZE][BLOCK_SIZE];
As[ty][tx] = matrixA[a + colsA*ty + tx];
Bs[ty][tx] = matrixB[b + rowsB*ty + tx];
__syncthreads();
//i * j for each thread
for (int k = 0; k < BLOCK_SIZE; ++k) {
cSub += As[ty][k]*Bs[k][tx];
}
__syncthreads();
}
int cIndex = (by*BLOCK_SIZE + ty)*rowsB + (bx*BLOCK_SIZE + tx);
matrixC[cIndex] = cSub;
}
void copyFromCPUToGPU(const float *matrixA, float *d_a, int n) {
cudaMemcpy(d_a, matrixA, sizeof(float) * n, cudaMemcpyHostToDevice);
}
void copyFromGPUToCPU(const float *d_c, float *matrixC, int n) {
cudaMemcpy(matrixC, d_c, sizeof(float) * n, cudaMemcpyDeviceToHost);
}
void matrixMulGPU(float* matrixC,const float *matrixA,const float *matrixB,int colsA,int rowsA,int rowsB) {
float *d_a, *d_b, *d_c;
cudaMalloc((void**) &d_a, sizeof(float) * colsA*rowsA);
cudaMalloc((void**) &d_b, sizeof(float) * rowsB*colsA);
cudaMalloc((void**) &d_c, sizeof(float) * rowsB*rowsA);
copyFromCPUToGPU(matrixA,d_a,colsA*rowsA);
copyFromCPUToGPU(matrixB,d_b,rowsB*colsA);
dim3 blocks(rowsB/BLOCK_SIZE, rowsA/BLOCK_SIZE);
dim3 threads(BLOCK_SIZE, BLOCK_SIZE);
float time_elapsed = 0;
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaEventRecord(start, 0);
matrixMulGPUKernal0<<<blocks,threads>>>(d_c,d_a,d_b,colsA,rowsA);
cudaEventRecord(stop, 0);
cudaEventSynchronize(start);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&time_elapsed, start, stop);
cudaEventDestroy(start);
cudaEventDestroy(stop);
printf(" - Running time: %f ms\n", time_elapsed);
double gflop = (2.0 * (double)colsA * colsA * colsA) * 0.000001;
printf(" - GFlop: %.5f GFlop/sec\n\n", gflop/time_elapsed);
cudaThreadSynchronize();
copyFromGPUToCPU(d_c,matrixC,rowsB*rowsA);
cudaFree(d_a);
cudaFree(d_b);
cudaFree(d_c);
}
void randomInit(float* _data,int size) {
for (int i = 0; i < size; ++i) {
_data[i] = rand()/(float)RAND_MAX;
}
}
bool checkError(const float* matrixA, const float* matrixB, int size) {
for (int i = 0 ; i < size; ++i) {
if (fabs(matrixA[i] - matrixB[i]) > 1.0e-3) {
printf(" ! Wrong index: %d\n", i);
printf("%f \t %f\n",matrixA[i],matrixB[i]);
return false;
}
}
return true;
}
int main(int argc, char* argv[]) {
if (!InitCUDA()) return 0;
srand(63);
printf("\n - BLOCK_SIZE: %d\n", BLOCK_SIZE);
int N = (1 << 11);
int colsA, colsB, colsC, rowsA, rowsB, rowsC;
colsA = colsB = colsC = rowsA = rowsB = rowsC = N;
printf(" - Matrix size: %d * %d\n", rowsC, rowsC);
float* A , *B, *C, *C2;
A = (float*) malloc(sizeof(float) * colsA * rowsA);
B = (float*) malloc(sizeof(float) * colsB * rowsB);
randomInit(A,colsA*rowsA);
randomInit(B,colsB*rowsB);
C = (float*) malloc(sizeof(float) * colsC * rowsC);
memset(C,0,sizeof(float)*colsC*rowsC);
C2 = (float*) malloc(sizeof(float) * colsC * rowsC);
memset(C2,0,sizeof(float)*colsC*rowsC);
clock_t tick1 = clock();
matrixMulCPU(C2,A,B,colsA,rowsA,colsB);
printf(" - CPU use Time : %f ms\n",(double)(clock() - tick1)/CLOCKS_PER_SEC);
// unsigned int timer = 0;
// cutilCheckError(cutCreateTimer(&timer));
// cutilCheckError(cutStartTimer(timer));
matrixMulGPU(C,A,B,colsA,rowsA,colsB);
// cutilCheckError(cutStopTimer(timer));
// printf("GPU use time: %f (ms) \n", cutGetTimerValue(timer));
// cutilCheckError(cutDeleteTimer(timer));
if (checkError(C,C2,colsC*rowsC)) {
printf("Right Answer!\n");
}else{
printf("Worng Answer!\n");
}
free(A);
free(B);
free(C);
free(C2);
return 0;
} | code for sm_80
Function : _Z19matrixMulGPUKernal1PfPKfS1_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2UR UR4, SR_CTAID.Y ; /* 0x00000000000479c3 */
/* 0x000e220000002600 */
/*0020*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e620000002100 */
/*0030*/ ISETP.LT.AND P0, PT, RZ, c[0x0][0x178], PT ; /* 0x00005e00ff007a0c */
/* 0x000fe20003f01270 */
/*0040*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe40000000a00 */
/*0050*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x000e680000002500 */
/*0060*/ S2R R13, SR_TID.Y ; /* 0x00000000000d7919 */
/* 0x000eac0000002200 */
/*0070*/ @!P0 MOV R23, RZ ; /* 0x000000ff00178202 */
/* 0x000fe20000000f00 */
/*0080*/ USHF.L.U32 UR4, UR4, 0x4, URZ ; /* 0x0000000404047899 */
/* 0x001fe2000800063f */
/*0090*/ LEA R12, R5, R0, 0x4 ; /* 0x00000000050c7211 */
/* 0x002fe200078e20ff */
/*00a0*/ @!P0 BRA 0x4d0 ; /* 0x0000042000008947 */
/* 0x000fea0003800000 */
/*00b0*/ HFMA2.MMA R4, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff047435 */
/* 0x000fe200000001ff */
/*00c0*/ IADD3 R3, R13.reuse, UR4, RZ ; /* 0x000000040d037c10 */
/* 0x044fe2000fffe0ff */
/*00d0*/ ULDC UR5, c[0x0][0x178] ; /* 0x00005e0000057ab9 */
/* 0x000fe20000000800 */
/*00e0*/ IMAD R2, R13, c[0x0][0x17c], R0.reuse ; /* 0x00005f000d027a24 */
/* 0x100fe200078e0200 */
/*00f0*/ UIMAD UR5, UR4, UR5, URZ ; /* 0x00000005040572a4 */
/* 0x000fe2000f8e023f */
/*0100*/ MOV R19, c[0x0][0x17c] ; /* 0x00005f0000137a02 */
/* 0x000fe20000000f00 */
/*0110*/ IMAD R3, R3, c[0x0][0x178], R0 ; /* 0x00005e0003037a24 */
/* 0x000fe200078e0200 */
/*0120*/ SHF.L.U32 R17, R13, 0x6, RZ ; /* 0x000000060d117819 */
/* 0x000fe200000006ff */
/*0130*/ HFMA2.MMA R23, -RZ, RZ, 0, 0 ; /* 0x00000000ff177435 */
/* 0x000fe200000001ff */
/*0140*/ LEA R2, R5, R2, 0x4 ; /* 0x0000000205027211 */
/* 0x000fe200078e20ff */
/*0150*/ IMAD.WIDE R14, R3, R4, c[0x0][0x168] ; /* 0x00005a00030e7625 */
/* 0x000fe200078e0204 */
/*0160*/ MOV R16, UR5 ; /* 0x0000000500107c02 */
/* 0x000fc40008000f00 */
/*0170*/ SHF.L.U32 R19, R19, 0x4, RZ ; /* 0x0000000413137819 */
/* 0x000fe200000006ff */
/*0180*/ IMAD.WIDE R2, R2, R4, c[0x0][0x170] ; /* 0x00005c0002027625 */
/* 0x000fe200078e0204 */
/*0190*/ MOV R21, R15 ; /* 0x0000000f00157202 */
/* 0x000fe40000000f00 */
/*01a0*/ LEA R18, R0, R17, 0x2 ; /* 0x0000001100127211 */
/* 0x000fe400078e10ff */
/*01b0*/ IADD3 R15, R16, c[0x0][0x178], RZ ; /* 0x00005e00100f7a10 */
/* 0x000fe40007ffe0ff */
/*01c0*/ MOV R20, R14 ; /* 0x0000000e00147202 */
/* 0x000fe20000000f00 */
/*01d0*/ LDG.E R22, [R2.64] ; /* 0x0000000602167981 */
/* 0x0000a8000c1e1900 */
/*01e0*/ LDG.E R27, [R20.64] ; /* 0x00000006141b7981 */
/* 0x0002e2000c1e1900 */
/*01f0*/ IADD3 R16, R16, 0x10, RZ ; /* 0x0000001010107810 */
/* 0x000fc40007ffe0ff */
/*0200*/ IADD3 R14, P1, R14, 0x40, RZ ; /* 0x000000400e0e7810 */
/* 0x000fe40007f3e0ff */
/*0210*/ ISETP.GE.AND P0, PT, R16, R15, PT ; /* 0x0000000f1000720c */
/* 0x000fe20003f06270 */
/*0220*/ IMAD.WIDE R2, R19, 0x4, R2 ; /* 0x0000000413027825 */
/* 0x001fe200078e0202 */
/*0230*/ IADD3.X R21, RZ, R21, RZ, P1, !PT ; /* 0x00000015ff157210 */
/* 0x002fe20000ffe4ff */
/*0240*/ STS [R18+0x400], R22 ; /* 0x0004001612007388 */
/* 0x004fe80000000800 */
/*0250*/ STS [R18], R27 ; /* 0x0000001b12007388 */
/* 0x008fe80000000800 */
/*0260*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0270*/ LDS R24, [R0.X4+0x400] ; /* 0x0004000000187984 */
/* 0x000fe80000004800 */
/*0280*/ LDS.128 R8, [R17] ; /* 0x0000000011087984 */
/* 0x000e280000000c00 */
/*0290*/ LDS R26, [R0.X4+0x440] ; /* 0x00044000001a7984 */
/* 0x000e680000004800 */
/*02a0*/ LDS R29, [R0.X4+0x480] ; /* 0x00048000001d7984 */
/* 0x000ea80000004800 */
/*02b0*/ LDS R20, [R0.X4+0x4c0] ; /* 0x0004c00000147984 */
/* 0x000ee80000004800 */
/*02c0*/ LDS R25, [R0.X4+0x500] ; /* 0x0005000000197984 */
/* 0x000fe80000004800 */
/*02d0*/ LDS.128 R4, [R17+0x10] ; /* 0x0000100011047984 */
/* 0x000f280000000c00 */
/*02e0*/ LDS R22, [R0.X4+0x540] ; /* 0x0005400000167984 */
/* 0x000f680000004800 */
/*02f0*/ LDS R27, [R0.X4+0x580] ; /* 0x00058000001b7984 */
/* 0x000f620000004800 */
/*0300*/ FFMA R8, R24, R8, R23 ; /* 0x0000000818087223 */
/* 0x001fc60000000017 */
/*0310*/ LDS R24, [R0.X4+0x5c0] ; /* 0x0005c00000187984 */
/* 0x000e220000004800 */
/*0320*/ FFMA R8, R26, R9, R8 ; /* 0x000000091a087223 */
/* 0x002fc60000000008 */
/*0330*/ LDS R23, [R0.X4+0x600] ; /* 0x0006000000177984 */
/* 0x000fe20000004800 */
/*0340*/ FFMA R8, R29, R10, R8 ; /* 0x0000000a1d087223 */
/* 0x004fc80000000008 */
/*0350*/ FFMA R20, R20, R11, R8 ; /* 0x0000000b14147223 */
/* 0x008fe40000000008 */
/*0360*/ LDS.128 R8, [R17+0x20] ; /* 0x0000200011087984 */
/* 0x000e640000000c00 */
/*0370*/ FFMA R4, R25, R4, R20 ; /* 0x0000000419047223 */
/* 0x010fe40000000014 */
/*0380*/ LDS R20, [R0.X4+0x640] ; /* 0x0006400000147984 */
/* 0x000ea40000004800 */
/*0390*/ FFMA R4, R22, R5, R4 ; /* 0x0000000516047223 */
/* 0x020fe40000000004 */
/*03a0*/ LDS R25, [R0.X4+0x680] ; /* 0x0006800000197984 */
/* 0x000ee40000004800 */
/*03b0*/ FFMA R4, R27, R6, R4 ; /* 0x000000061b047223 */
/* 0x000fc40000000004 */
/*03c0*/ LDS R22, [R0.X4+0x6c0] ; /* 0x0006c00000167984 */
/* 0x000f280000004800 */
/*03d0*/ LDS R27, [R0.X4+0x700] ; /* 0x00070000001b7984 */
/* 0x000fe20000004800 */
/*03e0*/ FFMA R24, R24, R7, R4 ; /* 0x0000000718187223 */
/* 0x001fc60000000004 */
/*03f0*/ LDS.128 R4, [R17+0x30] ; /* 0x0000300011047984 */
/* 0x000e220000000c00 */
/*0400*/ FFMA R24, R23, R8, R24 ; /* 0x0000000817187223 */
/* 0x002fc60000000018 */
/*0410*/ LDS R8, [R0.X4+0x740] ; /* 0x0007400000087984 */
/* 0x000e680000004800 */
/*0420*/ LDS R23, [R0.X4+0x780] ; /* 0x0007800000177984 */
/* 0x000f620000004800 */
/*0430*/ FFMA R9, R20, R9, R24 ; /* 0x0000000914097223 */
/* 0x004fc60000000018 */
/*0440*/ LDS R20, [R0.X4+0x7c0] ; /* 0x0007c00000147984 */
/* 0x000ea20000004800 */
/*0450*/ FFMA R9, R25, R10, R9 ; /* 0x0000000a19097223 */
/* 0x008fc80000000009 */
/*0460*/ FFMA R9, R22, R11, R9 ; /* 0x0000000b16097223 */
/* 0x010fc80000000009 */
/*0470*/ FFMA R4, R27, R4, R9 ; /* 0x000000041b047223 */
/* 0x001fc80000000009 */
/*0480*/ FFMA R4, R8, R5, R4 ; /* 0x0000000508047223 */
/* 0x002fc80000000004 */
/*0490*/ FFMA R23, R23, R6, R4 ; /* 0x0000000617177223 */
/* 0x020fc80000000004 */
/*04a0*/ FFMA R23, R20, R7, R23 ; /* 0x0000000714177223 */
/* 0x004fe20000000017 */
/*04b0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*04c0*/ @!P0 BRA 0x1c0 ; /* 0xfffffcf000008947 */
/* 0x000fea000383ffff */
/*04d0*/ IADD3 R13, R13, UR4, RZ ; /* 0x000000040d0d7c10 */
/* 0x004fe4000fffe0ff */
/*04e0*/ MOV R3, 0x4 ; /* 0x0000000400037802 */
/* 0x000fc60000000f00 */
/*04f0*/ IMAD R2, R13, c[0x0][0x17c], R12 ; /* 0x00005f000d027a24 */
/* 0x000fc800078e020c */
/*0500*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0203 */
/*0510*/ STG.E [R2.64], R23 ; /* 0x0000001702007986 */
/* 0x000fe2000c101906 */
/*0520*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0530*/ BRA 0x530; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0540*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0550*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0560*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0570*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0580*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0590*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z19matrixMulGPUKernal0PfPKfS1_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e220000002600 */
/*0020*/ MOV R4, c[0x0][0x178] ; /* 0x00005e0000047a02 */
/* 0x000fe20000000f00 */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ HFMA2.MMA R24, -RZ, RZ, 0, 0 ; /* 0x00000000ff187435 */
/* 0x000fe200000001ff */
/*0050*/ S2R R3, SR_TID.Y ; /* 0x0000000000037919 */
/* 0x000e220000002200 */
/*0060*/ ISETP.GE.AND P0, PT, R4, 0x1, PT ; /* 0x000000010400780c */
/* 0x000fc60003f06270 */
/*0070*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e680000002500 */
/*0080*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0090*/ IMAD R0, R0, c[0x0][0x4], R3 ; /* 0x0000010000007a24 */
/* 0x001fe400078e0203 */
/*00a0*/ IMAD R3, R2, c[0x0][0x0], R5 ; /* 0x0000000002037a24 */
/* 0x002fc600078e0205 */
/*00b0*/ @!P0 BRA 0xc10 ; /* 0x00000b5000008947 */
/* 0x000fea0003800000 */
/*00c0*/ IADD3 R2, R4.reuse, -0x1, RZ ; /* 0xffffffff04027810 */
/* 0x040fe40007ffe0ff */
/*00d0*/ LOP3.LUT R4, R4, 0x3, RZ, 0xc0, !PT ; /* 0x0000000304047812 */
/* 0x000fe400078ec0ff */
/*00e0*/ ISETP.GE.U32.AND P0, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fe40003f06070 */
/*00f0*/ MOV R24, RZ ; /* 0x000000ff00187202 */
/* 0x000fe40000000f00 */
/*0100*/ MOV R2, RZ ; /* 0x000000ff00027202 */
/* 0x000fd20000000f00 */
/*0110*/ @!P0 BRA 0xb00 ; /* 0x000009e000008947 */
/* 0x000fea0003800000 */
/*0120*/ IADD3 R5, -R4, c[0x0][0x178], RZ ; /* 0x00005e0004057a10 */
/* 0x000fe20007ffe1ff */
/*0130*/ HFMA2.MMA R8, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff087435 */
/* 0x000fe200000001ff */
/*0140*/ ULDC.64 UR6, c[0x0][0x168] ; /* 0x00005a0000067ab9 */
/* 0x000fe20000000a00 */
/*0150*/ HFMA2.MMA R2, -RZ, RZ, 0, 0 ; /* 0x00000000ff027435 */
/* 0x000fe200000001ff */
/*0160*/ ISETP.GT.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe20003f04270 */
/*0170*/ IMAD R6, R0, c[0x0][0x178], RZ ; /* 0x00005e0000067a24 */
/* 0x000fe200078e02ff */
/*0180*/ MOV R24, RZ ; /* 0x000000ff00187202 */
/* 0x000fca0000000f00 */
/*0190*/ IMAD.WIDE R8, R3, R8, c[0x0][0x170] ; /* 0x00005c0003087625 */
/* 0x000fcc00078e0208 */
/*01a0*/ @!P0 BRA 0x960 ; /* 0x000007b000008947 */
/* 0x000fea0003800000 */
/*01b0*/ ISETP.GT.AND P1, PT, R5, 0xc, PT ; /* 0x0000000c0500780c */
/* 0x000fe40003f24270 */
/*01c0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*01d0*/ @!P1 BRA 0x690 ; /* 0x000004b000009947 */
/* 0x000fea0003800000 */
/*01e0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*01f0*/ MOV R12, UR6 ; /* 0x00000006000c7c02 */
/* 0x000fe20008000f00 */
/*0200*/ LDG.E R21, [R8.64] ; /* 0x0000000408157981 */
/* 0x0000a2000c1e1900 */
/*0210*/ MOV R13, UR7 ; /* 0x00000007000d7c02 */
/* 0x000fca0008000f00 */
/*0220*/ IMAD.WIDE R12, R6, 0x4, R12 ; /* 0x00000004060c7825 */
/* 0x000fca00078e020c */
/*0230*/ LDG.E R20, [R12.64] ; /* 0x000000040c147981 */
/* 0x000ea2000c1e1900 */
/*0240*/ MOV R7, c[0x0][0x17c] ; /* 0x00005f0000077a02 */
/* 0x000fc60000000f00 */
/*0250*/ LDG.E R14, [R12.64+0x4] ; /* 0x000004040c0e7981 */
/* 0x000ee4000c1e1900 */
/*0260*/ IMAD.WIDE R10, R7.reuse, 0x4, R8 ; /* 0x00000004070a7825 */
/* 0x040fe400078e0208 */
/*0270*/ LDG.E R27, [R12.64+0x8] ; /* 0x000008040c1b7981 */
/* 0x000f28000c1e1900 */
/*0280*/ LDG.E R15, [R10.64] ; /* 0x000000040a0f7981 */
/* 0x0002e2000c1e1900 */
/*0290*/ IMAD.WIDE R22, R7, 0x4, R10 ; /* 0x0000000407167825 */
/* 0x000fc600078e020a */
/*02a0*/ LDG.E R18, [R12.64+0xc] ; /* 0x00000c040c127981 */
/* 0x000f66000c1e1900 */
/*02b0*/ IMAD.WIDE R28, R7.reuse, 0x4, R22 ; /* 0x00000004071c7825 */
/* 0x040fe200078e0216 */
/*02c0*/ LDG.E R26, [R22.64] ; /* 0x00000004161a7981 */
/* 0x000328000c1e1900 */
/*02d0*/ LDG.E R19, [R28.64] ; /* 0x000000041c137981 */
/* 0x000362000c1e1900 */
/*02e0*/ IMAD.WIDE R16, R7, 0x4, R28 ; /* 0x0000000407107825 */
/* 0x000fc600078e021c */
/*02f0*/ LDG.E R8, [R12.64+0x10] ; /* 0x000010040c087981 */
/* 0x001f68000c1e1900 */
/*0300*/ LDG.E R9, [R16.64] ; /* 0x0000000410097981 */
/* 0x000168000c1e1900 */
/*0310*/ LDG.E R10, [R12.64+0x14] ; /* 0x000014040c0a7981 */
/* 0x002f68000c1e1900 */
/*0320*/ LDG.E R28, [R12.64+0x1c] ; /* 0x00001c040c1c7981 */
/* 0x000f62000c1e1900 */
/*0330*/ IMAD.WIDE R16, R7, 0x4, R16 ; /* 0x0000000407107825 */
/* 0x001fca00078e0210 */
/*0340*/ LDG.E R11, [R16.64] ; /* 0x00000004100b7981 */
/* 0x000562000c1e1900 */
/*0350*/ IMAD.WIDE R22, R7, 0x4, R16 ; /* 0x0000000407167825 */
/* 0x000fc800078e0210 */
/*0360*/ FFMA R16, R21, R20, R24 ; /* 0x0000001415107223 */
/* 0x004fe40000000018 */
/*0370*/ LDG.E R20, [R12.64+0x18] ; /* 0x000018040c147981 */
/* 0x000ea2000c1e1900 */
/*0380*/ IMAD.WIDE R24, R7, 0x4, R22 ; /* 0x0000000407187825 */
/* 0x000fc600078e0216 */
/*0390*/ LDG.E R21, [R22.64] ; /* 0x0000000416157981 */
/* 0x0000a8000c1e1900 */
/*03a0*/ LDG.E R29, [R24.64] ; /* 0x00000004181d7981 */
/* 0x0002a2000c1e1900 */
/*03b0*/ FFMA R16, R15, R14, R16 ; /* 0x0000000e0f107223 */
/* 0x008fe40000000010 */
/*03c0*/ IMAD.WIDE R14, R7.reuse, 0x4, R24 ; /* 0x00000004070e7825 */
/* 0x040fe200078e0218 */
/*03d0*/ LDG.E R23, [R12.64+0x20] ; /* 0x000020040c177981 */
/* 0x001ee6000c1e1900 */
/*03e0*/ FFMA R26, R26, R27, R16 ; /* 0x0000001b1a1a7223 */
/* 0x010fe20000000010 */
/*03f0*/ LDG.E R25, [R12.64+0x24] ; /* 0x000024040c197981 */
/* 0x002f22000c1e1900 */
/*0400*/ IMAD.WIDE R16, R7, 0x4, R14 ; /* 0x0000000407107825 */
/* 0x000fc600078e020e */
/*0410*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x0000e2000c1e1900 */
/*0420*/ FFMA R26, R19, R18, R26 ; /* 0x00000012131a7223 */
/* 0x020fe4000000001a */
/*0430*/ IMAD.WIDE R18, R7, 0x4, R16 ; /* 0x0000000407127825 */
/* 0x000fe200078e0210 */
/*0440*/ LDG.E R22, [R12.64+0x28] ; /* 0x000028040c167981 */
/* 0x000f66000c1e1900 */
/*0450*/ FFMA R26, R9, R8, R26 ; /* 0x00000008091a7223 */
/* 0x000fe2000000001a */
/*0460*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x000322000c1e1900 */
/*0470*/ IMAD.WIDE R8, R7, 0x4, R18 ; /* 0x0000000407087825 */
/* 0x000fc600078e0212 */
/*0480*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x000368000c1e1900 */
/*0490*/ LDG.E R24, [R8.64] ; /* 0x0000000408187981 */
/* 0x000568000c1e1900 */
/*04a0*/ LDG.E R15, [R12.64+0x2c] ; /* 0x00002c040c0f7981 */
/* 0x001f62000c1e1900 */
/*04b0*/ FFMA R26, R11, R10, R26 ; /* 0x0000000a0b1a7223 */
/* 0x000fe4000000001a */
/*04c0*/ IMAD.WIDE R10, R7, 0x4, R8 ; /* 0x00000004070a7825 */
/* 0x000fe200078e0208 */
/*04d0*/ LDG.E R17, [R12.64+0x30] ; /* 0x000030040c117981 */
/* 0x002f66000c1e1900 */
/*04e0*/ FFMA R26, R21, R20, R26 ; /* 0x00000014151a7223 */
/* 0x004fc4000000001a */
/*04f0*/ IMAD.WIDE R20, R7, 0x4, R10 ; /* 0x0000000407147825 */
/* 0x000fe400078e020a */
/*0500*/ LDG.E R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x0000a4000c1e1900 */
/*0510*/ FFMA R28, R29, R28, R26 ; /* 0x0000001c1d1c7223 */
/* 0x000fe4000000001a */
/*0520*/ IMAD.WIDE R26, R7.reuse, 0x4, R20 ; /* 0x00000004071a7825 */
/* 0x040fe200078e0214 */
/*0530*/ LDG.E R29, [R12.64+0x34] ; /* 0x000034040c1d7981 */
/* 0x000ea8000c1e1900 */
/*0540*/ LDG.E R20, [R20.64] ; /* 0x0000000414147981 */
/* 0x0002a2000c1e1900 */
/*0550*/ IMAD.WIDE R8, R7, 0x4, R26 ; /* 0x0000000407087825 */
/* 0x000fc600078e021a */
/*0560*/ LDG.E R19, [R26.64] ; /* 0x000000041a137981 */
/* 0x0006a8000c1e1900 */
/*0570*/ LDG.E R11, [R8.64] ; /* 0x00000004080b7981 */
/* 0x0010a8000c1e1900 */
/*0580*/ LDG.E R21, [R12.64+0x38] ; /* 0x000038040c157981 */
/* 0x002ea8000c1e1900 */
/*0590*/ LDG.E R26, [R12.64+0x3c] ; /* 0x00003c040c1a7981 */
/* 0x008ee2000c1e1900 */
/*05a0*/ FFMA R14, R14, R23, R28 ; /* 0x000000170e0e7223 */
/* 0x000fc8000000001c */
/*05b0*/ FFMA R25, R16, R25, R14 ; /* 0x0000001910197223 */
/* 0x010fe2000000000e */
/*05c0*/ IADD3 R5, R5, -0x10, RZ ; /* 0xfffffff005057810 */
/* 0x000fc60007ffe0ff */
/*05d0*/ FFMA R18, R18, R22, R25 ; /* 0x0000001612127223 */
/* 0x020fe20000000019 */
/*05e0*/ ISETP.GT.AND P1, PT, R5, 0xc, PT ; /* 0x0000000c0500780c */
/* 0x000fc60003f24270 */
/*05f0*/ FFMA R15, R24, R15, R18 ; /* 0x0000000f180f7223 */
/* 0x000fe20000000012 */
/*0600*/ UIADD3 UR6, UP0, UR6, 0x40, URZ ; /* 0x0000004006067890 */
/* 0x000fe2000ff1e03f */
/*0610*/ IMAD.WIDE R8, R7, 0x4, R8 ; /* 0x0000000407087825 */
/* 0x001fc600078e0208 */
/*0620*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0630*/ IADD3 R2, R2, 0x10, RZ ; /* 0x0000001002027810 */
/* 0x000fe20007ffe0ff */
/*0640*/ FFMA R10, R10, R17, R15 ; /* 0x000000110a0a7223 */
/* 0x004fc8000000000f */
/*0650*/ FFMA R10, R20, R29, R10 ; /* 0x0000001d140a7223 */
/* 0x000fc8000000000a */
/*0660*/ FFMA R10, R19, R21, R10 ; /* 0x00000015130a7223 */
/* 0x000fc8000000000a */
/*0670*/ FFMA R24, R11, R26, R10 ; /* 0x0000001a0b187223 */
/* 0x008fe2000000000a */
/*0680*/ @P1 BRA 0x1f0 ; /* 0xfffffb6000001947 */
/* 0x000fea000383ffff */
/*0690*/ ISETP.GT.AND P1, PT, R5, 0x4, PT ; /* 0x000000040500780c */
/* 0x000fda0003f24270 */
/*06a0*/ @!P1 BRA 0x940 ; /* 0x0000029000009947 */
/* 0x000fea0003800000 */
/*06b0*/ MOV R7, c[0x0][0x17c] ; /* 0x00005f0000077a02 */
/* 0x000fe20000000f00 */
/*06c0*/ LDG.E R23, [R8.64] ; /* 0x0000000408177981 */
/* 0x0000a2000c1e1900 */
/*06d0*/ MOV R10, UR6 ; /* 0x00000006000a7c02 */
/* 0x000fe40008000f00 */
/*06e0*/ MOV R11, UR7 ; /* 0x00000007000b7c02 */
/* 0x000fe20008000f00 */
/*06f0*/ IMAD.WIDE R16, R7, 0x4, R8 ; /* 0x0000000407107825 */
/* 0x000fc800078e0208 */
/*0700*/ IMAD.WIDE R10, R6, 0x4, R10 ; /* 0x00000004060a7825 */
/* 0x000fc800078e020a */
/*0710*/ IMAD.WIDE R12, R7.reuse, 0x4, R16 ; /* 0x00000004070c7825 */
/* 0x040fe200078e0210 */
/*0720*/ LDG.E R22, [R10.64] ; /* 0x000000040a167981 */
/* 0x000ea8000c1e1900 */
/*0730*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x0002e2000c1e1900 */
/*0740*/ IMAD.WIDE R14, R7, 0x4, R12 ; /* 0x00000004070e7825 */
/* 0x000fc600078e020c */
/*0750*/ LDG.E R25, [R10.64+0x4] ; /* 0x000004040a197981 */
/* 0x000ee6000c1e1900 */
/*0760*/ IMAD.WIDE R18, R7.reuse, 0x4, R14 ; /* 0x0000000407127825 */
/* 0x040fe200078e020e */
/*0770*/ LDG.E R26, [R12.64] ; /* 0x000000040c1a7981 */
/* 0x000968000c1e1900 */
/*0780*/ LDG.E R27, [R10.64+0x8] ; /* 0x000008040a1b7981 */
/* 0x000f62000c1e1900 */
/*0790*/ IMAD.WIDE R20, R7, 0x4, R18 ; /* 0x0000000407147825 */
/* 0x000fc600078e0212 */
/*07a0*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000368000c1e1900 */
/*07b0*/ LDG.E R29, [R10.64+0xc] ; /* 0x00000c040a1d7981 */
/* 0x000f62000c1e1900 */
/*07c0*/ IMAD.WIDE R8, R7, 0x4, R20 ; /* 0x0000000407087825 */
/* 0x001fc600078e0214 */
/*07d0*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x000168000c1e1900 */
/*07e0*/ LDG.E R28, [R10.64+0x10] ; /* 0x000010040a1c7981 */
/* 0x000f62000c1e1900 */
/*07f0*/ IMAD.WIDE R12, R7, 0x4, R8 ; /* 0x00000004070c7825 */
/* 0x010fc600078e0208 */
/*0800*/ LDG.E R20, [R20.64] ; /* 0x0000000414147981 */
/* 0x000968000c1e1900 */
/*0810*/ LDG.E R15, [R10.64+0x14] ; /* 0x000014040a0f7981 */
/* 0x002f68000c1e1900 */
/*0820*/ LDG.E R17, [R8.64] ; /* 0x0000000408117981 */
/* 0x000368000c1e1900 */
/*0830*/ LDG.E R21, [R10.64+0x1c] ; /* 0x00001c040a157981 */
/* 0x010f28000c1e1900 */
/*0840*/ LDG.E R19, [R12.64] ; /* 0x000000040c137981 */
/* 0x001f28000c1e1900 */
/*0850*/ LDG.E R8, [R10.64+0x18] ; /* 0x000018040a087981 */
/* 0x002f22000c1e1900 */
/*0860*/ UIADD3 UR6, UP0, UR6, 0x20, URZ ; /* 0x0000002006067890 */
/* 0x000fe2000ff1e03f */
/*0870*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc40003f0e170 */
/*0880*/ IADD3 R2, R2, 0x8, RZ ; /* 0x0000000802027810 */
/* 0x000fe40007ffe0ff */
/*0890*/ IADD3 R5, R5, -0x8, RZ ; /* 0xfffffff805057810 */
/* 0x000fe20007ffe0ff */
/*08a0*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*08b0*/ FFMA R22, R23, R22, R24 ; /* 0x0000001617167223 */
/* 0x004fc80000000018 */
/*08c0*/ FFMA R16, R16, R25, R22 ; /* 0x0000001910107223 */
/* 0x008fc80000000016 */
/*08d0*/ FFMA R16, R26, R27, R16 ; /* 0x0000001b1a107223 */
/* 0x020fc80000000010 */
/*08e0*/ FFMA R29, R14, R29, R16 ; /* 0x0000001d0e1d7223 */
/* 0x000fc80000000010 */
/*08f0*/ FFMA R18, R18, R28, R29 ; /* 0x0000001c12127223 */
/* 0x000fc8000000001d */
/*0900*/ FFMA R15, R20, R15, R18 ; /* 0x0000000f140f7223 */
/* 0x000fc80000000012 */
/*0910*/ FFMA R24, R17, R8, R15 ; /* 0x0000000811187223 */
/* 0x010fe4000000000f */
/*0920*/ IMAD.WIDE R8, R7, 0x4, R12 ; /* 0x0000000407087825 */
/* 0x000fc800078e020c */
/*0930*/ FFMA R24, R19, R21, R24 ; /* 0x0000001513187223 */
/* 0x000fe40000000018 */
/*0940*/ ISETP.NE.OR P0, PT, R5, RZ, P0 ; /* 0x000000ff0500720c */
/* 0x000fda0000705670 */
/*0950*/ @!P0 BRA 0xb00 ; /* 0x000001a000008947 */
/* 0x000fea0003800000 */
/*0960*/ MOV R10, UR6 ; /* 0x00000006000a7c02 */
/* 0x000fe40008000f00 */
/*0970*/ MOV R11, UR7 ; /* 0x00000007000b7c02 */
/* 0x000fe40008000f00 */
/*0980*/ MOV R7, c[0x0][0x17c] ; /* 0x00005f0000077a02 */
/* 0x000fc60000000f00 */
/*0990*/ IMAD.WIDE R10, R6, 0x4, R10 ; /* 0x00000004060a7825 */
/* 0x000fc800078e020a */
/*09a0*/ IMAD.WIDE R16, R7.reuse, 0x4, R8 ; /* 0x0000000407107825 */
/* 0x040fe200078e0208 */
/*09b0*/ LDG.E R18, [R10.64] ; /* 0x000000040a127981 */
/* 0x000ea8000c1e1900 */
/*09c0*/ LDG.E R9, [R8.64] ; /* 0x0000000408097981 */
/* 0x000ea2000c1e1900 */
/*09d0*/ IMAD.WIDE R12, R7, 0x4, R16 ; /* 0x00000004070c7825 */
/* 0x000fc600078e0210 */
/*09e0*/ LDG.E R17, [R16.64] ; /* 0x0000000410117981 */
/* 0x000ee8000c1e1900 */
/*09f0*/ LDG.E R19, [R10.64+0x4] ; /* 0x000004040a137981 */
/* 0x000ee2000c1e1900 */
/*0a00*/ IMAD.WIDE R14, R7, 0x4, R12 ; /* 0x00000004070e7825 */
/* 0x000fc600078e020c */
/*0a10*/ LDG.E R21, [R12.64] ; /* 0x000000040c157981 */
/* 0x000f28000c1e1900 */
/*0a20*/ LDG.E R20, [R10.64+0x8] ; /* 0x000008040a147981 */
/* 0x000f28000c1e1900 */
/*0a30*/ LDG.E R22, [R10.64+0xc] ; /* 0x00000c040a167981 */
/* 0x000f68000c1e1900 */
/*0a40*/ LDG.E R23, [R14.64] ; /* 0x000000040e177981 */
/* 0x000f62000c1e1900 */
/*0a50*/ IADD3 R5, R5, -0x4, RZ ; /* 0xfffffffc05057810 */
/* 0x000fc80007ffe0ff */
/*0a60*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe20003f05270 */
/*0a70*/ UIADD3 UR6, UP0, UR6, 0x10, URZ ; /* 0x0000001006067890 */
/* 0x000fe2000ff1e03f */
/*0a80*/ IADD3 R2, R2, 0x4, RZ ; /* 0x0000000402027810 */
/* 0x000fc60007ffe0ff */
/*0a90*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0aa0*/ FFMA R18, R9, R18, R24 ; /* 0x0000001209127223 */
/* 0x004fc80000000018 */
/*0ab0*/ FFMA R18, R17, R19, R18 ; /* 0x0000001311127223 */
/* 0x008fe40000000012 */
/*0ac0*/ IMAD.WIDE R8, R7, 0x4, R14 ; /* 0x0000000407087825 */
/* 0x000fc800078e020e */
/*0ad0*/ FFMA R18, R21, R20, R18 ; /* 0x0000001415127223 */
/* 0x010fc80000000012 */
/*0ae0*/ FFMA R24, R23, R22, R18 ; /* 0x0000001617187223 */
/* 0x020fe20000000012 */
/*0af0*/ @P0 BRA 0x960 ; /* 0xfffffe6000000947 */
/* 0x000fea000383ffff */
/*0b00*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fda0003f05270 */
/*0b10*/ @!P0 BRA 0xc10 ; /* 0x000000f000008947 */
/* 0x000fea0003800000 */
/*0b20*/ HFMA2.MMA R9, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff097435 */
/* 0x000fe200000001ff */
/*0b30*/ IMAD R6, R0, c[0x0][0x178], R2 ; /* 0x00005e0000067a24 */
/* 0x000fe400078e0202 */
/*0b40*/ IMAD R2, R2, c[0x0][0x17c], R3 ; /* 0x00005f0002027a24 */
/* 0x000fce00078e0203 */
/*0b50*/ IMAD.WIDE R6, R6, R9, c[0x0][0x168] ; /* 0x00005a0006067625 */
/* 0x000fc800078e0209 */
/*0b60*/ IMAD.WIDE R8, R2, R9, c[0x0][0x170] ; /* 0x00005c0002087625 */
/* 0x000fca00078e0209 */
/*0b70*/ LDG.E R5, [R8.64] ; /* 0x0000000408057981 */
/* 0x0000a8000c1e1900 */
/*0b80*/ LDG.E R2, [R6.64] ; /* 0x0000000406027981 */
/* 0x0002a2000c1e1900 */
/*0b90*/ IADD3 R4, R4, -0x1, RZ ; /* 0xffffffff04047810 */
/* 0x000fe40007ffe0ff */
/*0ba0*/ MOV R11, c[0x0][0x17c] ; /* 0x00005f00000b7a02 */
/* 0x000fe40000000f00 */
/*0bb0*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fc60003f05270 */
/*0bc0*/ IMAD.WIDE R8, R11, 0x4, R8 ; /* 0x000000040b087825 */
/* 0x001fe200078e0208 */
/*0bd0*/ IADD3 R6, P1, R6, 0x4, RZ ; /* 0x0000000406067810 */
/* 0x002fc80007f3e0ff */
/*0be0*/ IADD3.X R7, RZ, R7, RZ, P1, !PT ; /* 0x00000007ff077210 */
/* 0x000fe20000ffe4ff */
/*0bf0*/ FFMA R24, R5, R2, R24 ; /* 0x0000000205187223 */
/* 0x004fc80000000018 */
/*0c00*/ @P0 BRA 0xb70 ; /* 0xffffff6000000947 */
/* 0x000fea000383ffff */
/*0c10*/ MOV R2, 0x4 ; /* 0x0000000400027802 */
/* 0x000fe20000000f00 */
/*0c20*/ IMAD R3, R0, c[0x0][0x17c], R3 ; /* 0x00005f0000037a24 */
/* 0x000fc800078e0203 */
/*0c30*/ IMAD.WIDE R2, R3, R2, c[0x0][0x160] ; /* 0x0000580003027625 */
/* 0x000fca00078e0202 */
/*0c40*/ STG.E [R2.64], R24 ; /* 0x0000001802007986 */
/* 0x000fe2000c101904 */
/*0c50*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0c60*/ BRA 0xc60; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0c70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ca0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ce0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <assert.h>
#include <cuda_runtime.h>
#include <stdlib.h>
#include <time.h>
#include <math.h>
#include <string.h>
#define BLOCK_SIZE 16
void printDeviceProp(const cudaDeviceProp &prop) {
printf("Device Name : %s.\n", prop.name);
printf("totalGlobalMem : %lu.\n", prop.totalGlobalMem);
printf("sharedMemPerBlock : %lu.\n", prop.sharedMemPerBlock);
printf("regsPerBlock : %d.\n", prop.regsPerBlock);
printf("warpSize : %d.\n", prop.warpSize);
printf("memPitch : %lu.\n", prop.memPitch);
printf("maxThreadsPerBlock : %d.\n", prop.maxThreadsPerBlock);
printf("maxThreadsDim[0 - 2] : %d %d %d.\n", prop.maxThreadsDim[0], prop.maxThreadsDim[1], prop.maxThreadsDim[2]);
printf("maxGridSize[0 - 2] : %d %d %d.\n", prop.maxGridSize[0], prop.maxGridSize[1], prop.maxGridSize[2]);
printf("totalConstMem : %lu.\n", prop.totalConstMem);
printf("major.minor : %d.%d.\n", prop.major, prop.minor);
printf("clockRate : %d.\n", prop.clockRate);
printf("textureAlignment : %lu.\n", prop.textureAlignment);
printf("deviceOverlap : %d.\n", prop.deviceOverlap);
printf("multiProcessorCount : %d.\n", prop.multiProcessorCount);
}
bool InitCUDA() {
int count;
cudaGetDeviceCount(&count);
if (count == 0) {
fprintf(stderr, "There is no device.\n");
return false;
}
int i;
for (i = 0; i < count; i++) {
cudaDeviceProp prop;
cudaGetDeviceProperties(&prop, i);
printDeviceProp(prop);
if (cudaGetDeviceProperties(&prop, i) == cudaSuccess) {
if (prop.major >= 1) {
break;
}
}
}
if (i == count) {
fprintf(stderr, "There is no device supporting CUDA 1.x.\n");
return false;
}
cudaSetDevice(i);
return true;
}
//CPU
void matrixMulCPU(float* res,const float *matrixA,const float *matrixB,int colsA,int rowsA,int rowsB) {
float sum = 0;
for (int i = 0; i < rowsA; ++i) {
for (int j = 0; j < rowsB; ++j) {
sum = 0;
for (int k = 0; k < colsA; ++k) {
sum += (float)matrixA[i*colsA+k]*(float)matrixB[k*rowsB+ j];
}
res[i*rowsB+j] = (float)sum;
}
}
}
// GPU
// C(i,j) = sum{A(i, k)* B(k ,j)}
// each thread cal C(i, j)
__global__ void matrixMulGPUKernal0(float* matrixC,const float* matrixA,const float *matrixB,int colsA,int rowsB) {
float sum = 0;
int row = blockIdx.y*blockDim.y + threadIdx.y;
int col = blockIdx.x*blockDim.x + threadIdx.x;
for (int i = 0; i < colsA; ++i) {
sum += matrixA[row*colsA + i] * matrixB[i*rowsB + col];
}
matrixC[row*rowsB + col] = sum;
}
// Csub(i,j) = sum{A(i,ksub+offsetA)*B(ksub+offsetB,j)} 0 <= ksub < blockSize
// C(i,j) = sum{Csub(i,j)}
// each thread cal each block
__global__ void matrixMulGPUKernal1(float* matrixC,const float* matrixA,const float *matrixB,int colsA,int rowsB) {
int bx = blockIdx.x;
int by = blockIdx.y;
int tx = threadIdx.x;
int ty = threadIdx.y;
int aBegin = colsA*(by*BLOCK_SIZE);//A(0,by)
int aEnd = aBegin + colsA - 1;
int aStep = BLOCK_SIZE;//offsetA
int bBegin = BLOCK_SIZE*bx;//B(bx,0)
int bStep = BLOCK_SIZE*rowsB;//offsetB
float cSub = 0;
for (int a = aBegin,b = bBegin; a <= aEnd; a += aStep,b += bStep) {
__shared__ float As[BLOCK_SIZE][BLOCK_SIZE];
__shared__ float Bs[BLOCK_SIZE][BLOCK_SIZE];
As[ty][tx] = matrixA[a + colsA*ty + tx];
Bs[ty][tx] = matrixB[b + rowsB*ty + tx];
__syncthreads();
//i * j for each thread
for (int k = 0; k < BLOCK_SIZE; ++k) {
cSub += As[ty][k]*Bs[k][tx];
}
__syncthreads();
}
int cIndex = (by*BLOCK_SIZE + ty)*rowsB + (bx*BLOCK_SIZE + tx);
matrixC[cIndex] = cSub;
}
void copyFromCPUToGPU(const float *matrixA, float *d_a, int n) {
cudaMemcpy(d_a, matrixA, sizeof(float) * n, cudaMemcpyHostToDevice);
}
void copyFromGPUToCPU(const float *d_c, float *matrixC, int n) {
cudaMemcpy(matrixC, d_c, sizeof(float) * n, cudaMemcpyDeviceToHost);
}
void matrixMulGPU(float* matrixC,const float *matrixA,const float *matrixB,int colsA,int rowsA,int rowsB) {
float *d_a, *d_b, *d_c;
cudaMalloc((void**) &d_a, sizeof(float) * colsA*rowsA);
cudaMalloc((void**) &d_b, sizeof(float) * rowsB*colsA);
cudaMalloc((void**) &d_c, sizeof(float) * rowsB*rowsA);
copyFromCPUToGPU(matrixA,d_a,colsA*rowsA);
copyFromCPUToGPU(matrixB,d_b,rowsB*colsA);
dim3 blocks(rowsB/BLOCK_SIZE, rowsA/BLOCK_SIZE);
dim3 threads(BLOCK_SIZE, BLOCK_SIZE);
float time_elapsed = 0;
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaEventRecord(start, 0);
matrixMulGPUKernal0<<<blocks,threads>>>(d_c,d_a,d_b,colsA,rowsA);
cudaEventRecord(stop, 0);
cudaEventSynchronize(start);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&time_elapsed, start, stop);
cudaEventDestroy(start);
cudaEventDestroy(stop);
printf(" - Running time: %f ms\n", time_elapsed);
double gflop = (2.0 * (double)colsA * colsA * colsA) * 0.000001;
printf(" - GFlop: %.5f GFlop/sec\n\n", gflop/time_elapsed);
cudaThreadSynchronize();
copyFromGPUToCPU(d_c,matrixC,rowsB*rowsA);
cudaFree(d_a);
cudaFree(d_b);
cudaFree(d_c);
}
void randomInit(float* _data,int size) {
for (int i = 0; i < size; ++i) {
_data[i] = rand()/(float)RAND_MAX;
}
}
bool checkError(const float* matrixA, const float* matrixB, int size) {
for (int i = 0 ; i < size; ++i) {
if (fabs(matrixA[i] - matrixB[i]) > 1.0e-3) {
printf(" ! Wrong index: %d\n", i);
printf("%f \t %f\n",matrixA[i],matrixB[i]);
return false;
}
}
return true;
}
int main(int argc, char* argv[]) {
if (!InitCUDA()) return 0;
srand(63);
printf("\n - BLOCK_SIZE: %d\n", BLOCK_SIZE);
int N = (1 << 11);
int colsA, colsB, colsC, rowsA, rowsB, rowsC;
colsA = colsB = colsC = rowsA = rowsB = rowsC = N;
printf(" - Matrix size: %d * %d\n", rowsC, rowsC);
float* A , *B, *C, *C2;
A = (float*) malloc(sizeof(float) * colsA * rowsA);
B = (float*) malloc(sizeof(float) * colsB * rowsB);
randomInit(A,colsA*rowsA);
randomInit(B,colsB*rowsB);
C = (float*) malloc(sizeof(float) * colsC * rowsC);
memset(C,0,sizeof(float)*colsC*rowsC);
C2 = (float*) malloc(sizeof(float) * colsC * rowsC);
memset(C2,0,sizeof(float)*colsC*rowsC);
clock_t tick1 = clock();
matrixMulCPU(C2,A,B,colsA,rowsA,colsB);
printf(" - CPU use Time : %f ms\n",(double)(clock() - tick1)/CLOCKS_PER_SEC);
// unsigned int timer = 0;
// cutilCheckError(cutCreateTimer(&timer));
// cutilCheckError(cutStartTimer(timer));
matrixMulGPU(C,A,B,colsA,rowsA,colsB);
// cutilCheckError(cutStopTimer(timer));
// printf("GPU use time: %f (ms) \n", cutGetTimerValue(timer));
// cutilCheckError(cutDeleteTimer(timer));
if (checkError(C,C2,colsC*rowsC)) {
printf("Right Answer!\n");
}else{
printf("Worng Answer!\n");
}
free(A);
free(B);
free(C);
free(C2);
return 0;
} | .file "tmpxft_0002aa1e_00000000-6_matrixMul.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2068:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2068:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Device Name : %s.\n"
.LC1:
.string "totalGlobalMem : %lu.\n"
.LC2:
.string "sharedMemPerBlock : %lu.\n"
.LC3:
.string "regsPerBlock : %d.\n"
.LC4:
.string "warpSize : %d.\n"
.LC5:
.string "memPitch : %lu.\n"
.LC6:
.string "maxThreadsPerBlock : %d.\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC7:
.string "maxThreadsDim[0 - 2] : %d %d %d.\n"
.align 8
.LC8:
.string "maxGridSize[0 - 2] : %d %d %d.\n"
.section .rodata.str1.1
.LC9:
.string "totalConstMem : %lu.\n"
.LC10:
.string "major.minor : %d.%d.\n"
.LC11:
.string "clockRate : %d.\n"
.LC12:
.string "textureAlignment : %lu.\n"
.LC13:
.string "deviceOverlap : %d.\n"
.LC14:
.string "multiProcessorCount : %d.\n"
.text
.globl _Z15printDevicePropRK14cudaDeviceProp
.type _Z15printDevicePropRK14cudaDeviceProp, @function
_Z15printDevicePropRK14cudaDeviceProp:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movq %rdi, %rbx
movq %rdi, %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 288(%rbx), %rdx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 296(%rbx), %rdx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 304(%rbx), %edx
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 308(%rbx), %edx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 312(%rbx), %rdx
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 320(%rbx), %edx
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 328(%rbx), %ecx
movl 324(%rbx), %edx
movl 332(%rbx), %r8d
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 340(%rbx), %ecx
movl 336(%rbx), %edx
movl 344(%rbx), %r8d
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 352(%rbx), %rdx
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 364(%rbx), %ecx
movl 360(%rbx), %edx
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 348(%rbx), %edx
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 368(%rbx), %rdx
leaq .LC12(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 384(%rbx), %edx
leaq .LC13(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 388(%rbx), %edx
leaq .LC14(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _Z15printDevicePropRK14cudaDeviceProp, .-_Z15printDevicePropRK14cudaDeviceProp
.section .rodata.str1.1
.LC15:
.string "There is no device.\n"
.section .rodata.str1.8
.align 8
.LC16:
.string "There is no device supporting CUDA 1.x.\n"
.text
.globl _Z8InitCUDAv
.type _Z8InitCUDAv, @function
_Z8InitCUDAv:
.LFB2058:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $1064, %rsp
.cfi_def_cfa_offset 1088
movq %fs:40, %rax
movq %rax, 1048(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rdi
call cudaGetDeviceCount@PLT
movl 12(%rsp), %eax
testl %eax, %eax
je .L18
movl $0, %ebx
leaq 16(%rsp), %rbp
jg .L10
jmp .L12
.L18:
leaq .LC15(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
call __fprintf_chk@PLT
movl $0, %eax
jmp .L5
.L8:
addl $1, %ebx
cmpl %ebx, 12(%rsp)
jle .L11
.L10:
movl %ebx, %esi
movq %rbp, %rdi
call cudaGetDeviceProperties_v2@PLT
movq %rbp, %rdi
call _Z15printDevicePropRK14cudaDeviceProp
movl %ebx, %esi
movq %rbp, %rdi
call cudaGetDeviceProperties_v2@PLT
testl %eax, %eax
jne .L8
cmpl $0, 376(%rsp)
jle .L8
.L11:
cmpl %ebx, 12(%rsp)
je .L19
.L12:
movl %ebx, %edi
call cudaSetDevice@PLT
movl $1, %eax
.L5:
movq 1048(%rsp), %rdx
subq %fs:40, %rdx
jne .L20
addq $1064, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
leaq .LC16(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $0, %eax
jmp .L5
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size _Z8InitCUDAv, .-_Z8InitCUDAv
.globl _Z12matrixMulCPUPfPKfS1_iii
.type _Z12matrixMulCPUPfPKfS1_iii, @function
_Z12matrixMulCPUPfPKfS1_iii:
.LFB2059:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
movq %rdi, -16(%rsp)
movq %rdx, -8(%rsp)
movl %r8d, -20(%rsp)
testl %r8d, %r8d
jle .L21
movq %rsi, %rbp
movl %ecx, %r10d
movl %r9d, %r14d
movslq %r9d, %rbx
leaq 0(,%rbx,4), %rsi
movl $0, %r13d
movl $0, %r12d
movl $0, %edx
movslq %ecx, %r15
movq %r15, %rcx
jmp .L23
.L24:
movss (%rax), %xmm0
mulss (%rdx), %xmm0
addss %xmm0, %xmm1
addq $4, %rax
addq %rsi, %rdx
cmpq %rdi, %rax
jne .L24
.L26:
movss %xmm1, (%r11,%r8,4)
addq $1, %r8
addq $4, %r9
cmpq %r8, %rbx
je .L31
.L27:
movq %r9, %rdx
movq %r15, %rax
pxor %xmm1, %xmm1
testl %r10d, %r10d
jg .L24
jmp .L26
.L31:
movl -24(%rsp), %edx
.L25:
addl $1, %edx
addl %r14d, %r12d
addl %r10d, %r13d
cmpl %edx, -20(%rsp)
je .L21
.L23:
testl %r14d, %r14d
jle .L25
movq -8(%rsp), %r9
movslq %r13d, %rax
leaq 0(%rbp,%rax,4), %r15
addq %rcx, %rax
leaq 0(%rbp,%rax,4), %rdi
movslq %r12d, %rax
movq -16(%rsp), %r11
leaq (%r11,%rax,4), %r11
movl $0, %r8d
movl %edx, -24(%rsp)
jmp .L27
.L21:
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size _Z12matrixMulCPUPfPKfS1_iii, .-_Z12matrixMulCPUPfPKfS1_iii
.globl _Z16copyFromCPUToGPUPKfPfi
.type _Z16copyFromCPUToGPUPKfPfi, @function
_Z16copyFromCPUToGPUPKfPfi:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq %rdi, %rax
movq %rsi, %rdi
movslq %edx, %rdx
salq $2, %rdx
movl $1, %ecx
movq %rax, %rsi
call cudaMemcpy@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _Z16copyFromCPUToGPUPKfPfi, .-_Z16copyFromCPUToGPUPKfPfi
.globl _Z16copyFromGPUToCPUPKfPfi
.type _Z16copyFromGPUToCPUPKfPfi, @function
_Z16copyFromGPUToCPUPKfPfi:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq %rdi, %rax
movq %rsi, %rdi
movslq %edx, %rdx
salq $2, %rdx
movl $2, %ecx
movq %rax, %rsi
call cudaMemcpy@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _Z16copyFromGPUToCPUPKfPfi, .-_Z16copyFromGPUToCPUPKfPfi
.globl _Z10randomInitPfi
.type _Z10randomInitPfi, @function
_Z10randomInitPfi:
.LFB2063:
.cfi_startproc
endbr64
testl %esi, %esi
jle .L43
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movq %rdi, %rbx
movslq %esi, %rsi
leaq (%rdi,%rsi,4), %rbp
.L40:
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
mulss .LC18(%rip), %xmm0
movss %xmm0, (%rbx)
addq $4, %rbx
cmpq %rbp, %rbx
jne .L40
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L43:
.cfi_restore 3
.cfi_restore 6
ret
.cfi_endproc
.LFE2063:
.size _Z10randomInitPfi, .-_Z10randomInitPfi
.section .rodata.str1.1
.LC21:
.string " ! Wrong index: %d\n"
.LC22:
.string "%f \t %f\n"
.text
.globl _Z10checkErrorPKfS0_i
.type _Z10checkErrorPKfS0_i, @function
_Z10checkErrorPKfS0_i:
.LFB2064:
.cfi_startproc
endbr64
testl %edx, %edx
jle .L51
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movl %edx, %eax
movq %rdi, %rbp
movq %rsi, %rbx
movl $0, %edx
movss .LC19(%rip), %xmm2
movsd .LC20(%rip), %xmm1
.L50:
movss 0(%rbp), %xmm0
subss (%rbx), %xmm0
andps %xmm2, %xmm0
cvtss2sd %xmm0, %xmm0
comisd %xmm1, %xmm0
ja .L59
addl $1, %edx
addq $4, %rbp
addq $4, %rbx
cmpl %edx, %eax
jne .L50
movl $1, %eax
jmp .L46
.L59:
leaq .LC21(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
pxor %xmm0, %xmm0
cvtss2sd 0(%rbp), %xmm0
pxor %xmm1, %xmm1
cvtss2sd (%rbx), %xmm1
leaq .LC22(%rip), %rsi
movl $2, %edi
movl $2, %eax
call __printf_chk@PLT
movl $0, %eax
.L46:
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L51:
.cfi_restore 3
.cfi_restore 6
movl $1, %eax
ret
.cfi_endproc
.LFE2064:
.size _Z10checkErrorPKfS0_i, .-_Z10checkErrorPKfS0_i
.globl _Z47__device_stub__Z19matrixMulGPUKernal0PfPKfS1_iiPfPKfS1_ii
.type _Z47__device_stub__Z19matrixMulGPUKernal0PfPKfS1_iiPfPKfS1_ii, @function
_Z47__device_stub__Z19matrixMulGPUKernal0PfPKfS1_iiPfPKfS1_ii:
.LFB2090:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L64
.L60:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L65
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L64:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z19matrixMulGPUKernal0PfPKfS1_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L60
.L65:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2090:
.size _Z47__device_stub__Z19matrixMulGPUKernal0PfPKfS1_iiPfPKfS1_ii, .-_Z47__device_stub__Z19matrixMulGPUKernal0PfPKfS1_iiPfPKfS1_ii
.globl _Z19matrixMulGPUKernal0PfPKfS1_ii
.type _Z19matrixMulGPUKernal0PfPKfS1_ii, @function
_Z19matrixMulGPUKernal0PfPKfS1_ii:
.LFB2091:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z47__device_stub__Z19matrixMulGPUKernal0PfPKfS1_iiPfPKfS1_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2091:
.size _Z19matrixMulGPUKernal0PfPKfS1_ii, .-_Z19matrixMulGPUKernal0PfPKfS1_ii
.section .rodata.str1.1
.LC23:
.string " - Running time: %f ms\n"
.LC25:
.string " - GFlop: %.5f GFlop/sec\n\n"
.text
.globl _Z12matrixMulGPUPfPKfS1_iii
.type _Z12matrixMulGPUPfPKfS1_iii, @function
_Z12matrixMulGPUPfPKfS1_iii:
.LFB2062:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $120, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 8(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, %r12d
movl %r8d, %ebx
movl %r9d, %ebp
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
movslq %ecx, %r15
movslq %r8d, %r13
movq %r15, %rax
imulq %r13, %rax
movq %rax, %rsi
salq $2, %rsi
leaq 40(%rsp), %rdi
call cudaMalloc@PLT
movslq %ebp, %r14
salq $2, %r14
imulq %r14, %r15
movq %r15, %rsi
leaq 48(%rsp), %rdi
call cudaMalloc@PLT
imulq %r14, %r13
movq %r13, %rsi
leaq 56(%rsp), %rdi
call cudaMalloc@PLT
movl %r12d, %eax
imull %ebx, %eax
movl %eax, %edx
movq 40(%rsp), %rsi
movq 16(%rsp), %rdi
call _Z16copyFromCPUToGPUPKfPfi
movl %r12d, %eax
imull %ebp, %eax
movl %eax, %edx
movq 48(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z16copyFromCPUToGPUPKfPfi
leal 15(%rbp), %eax
testl %ebp, %ebp
cmovns %ebp, %eax
sarl $4, %eax
movl %eax, 80(%rsp)
leal 15(%rbx), %eax
testl %ebx, %ebx
cmovns %ebx, %eax
sarl $4, %eax
movl %eax, 84(%rsp)
movl $1, 88(%rsp)
movl $16, 92(%rsp)
movl $16, 96(%rsp)
movl $1, 100(%rsp)
movl $0x00000000, 36(%rsp)
leaq 64(%rsp), %rdi
call cudaEventCreate@PLT
leaq 72(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 64(%rsp), %rdi
call cudaEventRecord@PLT
movl 100(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 92(%rsp), %rdx
movq 80(%rsp), %rdi
movl 88(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L72
.L69:
movl $0, %esi
movq 72(%rsp), %rdi
call cudaEventRecord@PLT
movq 64(%rsp), %rdi
call cudaEventSynchronize@PLT
movq 72(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 36(%rsp), %rdi
movq 72(%rsp), %rdx
movq 64(%rsp), %rsi
call cudaEventElapsedTime@PLT
movq 64(%rsp), %rdi
call cudaEventDestroy@PLT
movq 72(%rsp), %rdi
call cudaEventDestroy@PLT
pxor %xmm0, %xmm0
cvtss2sd 36(%rsp), %xmm0
leaq .LC23(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
pxor %xmm1, %xmm1
cvtsi2sdl %r12d, %xmm1
movapd %xmm1, %xmm0
addsd %xmm1, %xmm0
mulsd %xmm1, %xmm0
mulsd %xmm1, %xmm0
mulsd .LC24(%rip), %xmm0
pxor %xmm1, %xmm1
cvtss2sd 36(%rsp), %xmm1
divsd %xmm1, %xmm0
leaq .LC25(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
call cudaThreadSynchronize@PLT
imull %ebp, %ebx
movl %ebx, %edx
movq 8(%rsp), %rsi
movq 56(%rsp), %rdi
call _Z16copyFromGPUToCPUPKfPfi
movq 40(%rsp), %rdi
call cudaFree@PLT
movq 48(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rdi
call cudaFree@PLT
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L73
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L72:
.cfi_restore_state
movl %ebx, %r8d
movl %r12d, %ecx
movq 48(%rsp), %rdx
movq 40(%rsp), %rsi
movq 56(%rsp), %rdi
call _Z47__device_stub__Z19matrixMulGPUKernal0PfPKfS1_iiPfPKfS1_ii
jmp .L69
.L73:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2062:
.size _Z12matrixMulGPUPfPKfS1_iii, .-_Z12matrixMulGPUPfPKfS1_iii
.section .rodata.str1.1
.LC26:
.string "\n - BLOCK_SIZE: %d\n"
.LC27:
.string " - Matrix size: %d * %d\n"
.LC29:
.string " - CPU use Time : %f ms\n"
.LC30:
.string "Right Answer!\n"
.LC31:
.string "Worng Answer!\n"
.text
.globl main
.type main, @function
main:
.LFB2065:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
call _Z8InitCUDAv
testb %al, %al
jne .L79
.L75:
movl $0, %eax
popq %rbx
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L79:
.cfi_restore_state
movl $63, %edi
call srand@PLT
movl $16, %edx
leaq .LC26(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $2048, %ecx
movl $2048, %edx
leaq .LC27(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $16777216, %edi
call malloc@PLT
movq %rax, %r13
movl $16777216, %edi
call malloc@PLT
movq %rax, %r12
movl $4194304, %esi
movq %r13, %rdi
call _Z10randomInitPfi
movl $4194304, %esi
movq %r12, %rdi
call _Z10randomInitPfi
movl $16777216, %edi
call malloc@PLT
movq %rax, %rbp
movl $16777216, %edx
movl $0, %esi
movq %rax, %rdi
call memset@PLT
movl $16777216, %edi
call malloc@PLT
movq %rax, %rbx
movl $16777216, %edx
movl $0, %esi
movq %rax, %rdi
call memset@PLT
call clock@PLT
movq %rax, %r14
movl $2048, %r9d
movl $2048, %r8d
movl $2048, %ecx
movq %r12, %rdx
movq %r13, %rsi
movq %rbx, %rdi
call _Z12matrixMulCPUPfPKfS1_iii
call clock@PLT
subq %r14, %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
divsd .LC28(%rip), %xmm0
leaq .LC29(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl $2048, %r9d
movl $2048, %r8d
movl $2048, %ecx
movq %r12, %rdx
movq %r13, %rsi
movq %rbp, %rdi
call _Z12matrixMulGPUPfPKfS1_iii
movl $4194304, %edx
movq %rbx, %rsi
movq %rbp, %rdi
call _Z10checkErrorPKfS0_i
testb %al, %al
je .L76
leaq .LC30(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L77:
movq %r13, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
movq %rbp, %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
jmp .L75
.L76:
leaq .LC31(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L77
.cfi_endproc
.LFE2065:
.size main, .-main
.globl _Z47__device_stub__Z19matrixMulGPUKernal1PfPKfS1_iiPfPKfS1_ii
.type _Z47__device_stub__Z19matrixMulGPUKernal1PfPKfS1_iiPfPKfS1_ii, @function
_Z47__device_stub__Z19matrixMulGPUKernal1PfPKfS1_iiPfPKfS1_ii:
.LFB2092:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L84
.L80:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L85
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L84:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z19matrixMulGPUKernal1PfPKfS1_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L80
.L85:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2092:
.size _Z47__device_stub__Z19matrixMulGPUKernal1PfPKfS1_iiPfPKfS1_ii, .-_Z47__device_stub__Z19matrixMulGPUKernal1PfPKfS1_iiPfPKfS1_ii
.globl _Z19matrixMulGPUKernal1PfPKfS1_ii
.type _Z19matrixMulGPUKernal1PfPKfS1_ii, @function
_Z19matrixMulGPUKernal1PfPKfS1_ii:
.LFB2093:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z47__device_stub__Z19matrixMulGPUKernal1PfPKfS1_iiPfPKfS1_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2093:
.size _Z19matrixMulGPUKernal1PfPKfS1_ii, .-_Z19matrixMulGPUKernal1PfPKfS1_ii
.section .rodata.str1.8
.align 8
.LC32:
.string "_Z19matrixMulGPUKernal1PfPKfS1_ii"
.align 8
.LC33:
.string "_Z19matrixMulGPUKernal0PfPKfS1_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2095:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC32(%rip), %rdx
movq %rdx, %rcx
leaq _Z19matrixMulGPUKernal1PfPKfS1_ii(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC33(%rip), %rdx
movq %rdx, %rcx
leaq _Z19matrixMulGPUKernal0PfPKfS1_ii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2095:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC18:
.long 805306368
.section .rodata.cst16,"aM",@progbits,16
.align 16
.LC19:
.long 2147483647
.long 0
.long 0
.long 0
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC20:
.long -755914244
.long 1062232653
.align 8
.LC24:
.long -1598689907
.long 1051772663
.align 8
.LC28:
.long 0
.long 1093567616
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <assert.h>
#include <cuda_runtime.h>
#include <stdlib.h>
#include <time.h>
#include <math.h>
#include <string.h>
#define BLOCK_SIZE 16
void printDeviceProp(const cudaDeviceProp &prop) {
printf("Device Name : %s.\n", prop.name);
printf("totalGlobalMem : %lu.\n", prop.totalGlobalMem);
printf("sharedMemPerBlock : %lu.\n", prop.sharedMemPerBlock);
printf("regsPerBlock : %d.\n", prop.regsPerBlock);
printf("warpSize : %d.\n", prop.warpSize);
printf("memPitch : %lu.\n", prop.memPitch);
printf("maxThreadsPerBlock : %d.\n", prop.maxThreadsPerBlock);
printf("maxThreadsDim[0 - 2] : %d %d %d.\n", prop.maxThreadsDim[0], prop.maxThreadsDim[1], prop.maxThreadsDim[2]);
printf("maxGridSize[0 - 2] : %d %d %d.\n", prop.maxGridSize[0], prop.maxGridSize[1], prop.maxGridSize[2]);
printf("totalConstMem : %lu.\n", prop.totalConstMem);
printf("major.minor : %d.%d.\n", prop.major, prop.minor);
printf("clockRate : %d.\n", prop.clockRate);
printf("textureAlignment : %lu.\n", prop.textureAlignment);
printf("deviceOverlap : %d.\n", prop.deviceOverlap);
printf("multiProcessorCount : %d.\n", prop.multiProcessorCount);
}
bool InitCUDA() {
int count;
cudaGetDeviceCount(&count);
if (count == 0) {
fprintf(stderr, "There is no device.\n");
return false;
}
int i;
for (i = 0; i < count; i++) {
cudaDeviceProp prop;
cudaGetDeviceProperties(&prop, i);
printDeviceProp(prop);
if (cudaGetDeviceProperties(&prop, i) == cudaSuccess) {
if (prop.major >= 1) {
break;
}
}
}
if (i == count) {
fprintf(stderr, "There is no device supporting CUDA 1.x.\n");
return false;
}
cudaSetDevice(i);
return true;
}
//CPU
void matrixMulCPU(float* res,const float *matrixA,const float *matrixB,int colsA,int rowsA,int rowsB) {
float sum = 0;
for (int i = 0; i < rowsA; ++i) {
for (int j = 0; j < rowsB; ++j) {
sum = 0;
for (int k = 0; k < colsA; ++k) {
sum += (float)matrixA[i*colsA+k]*(float)matrixB[k*rowsB+ j];
}
res[i*rowsB+j] = (float)sum;
}
}
}
// GPU
// C(i,j) = sum{A(i, k)* B(k ,j)}
// each thread cal C(i, j)
__global__ void matrixMulGPUKernal0(float* matrixC,const float* matrixA,const float *matrixB,int colsA,int rowsB) {
float sum = 0;
int row = blockIdx.y*blockDim.y + threadIdx.y;
int col = blockIdx.x*blockDim.x + threadIdx.x;
for (int i = 0; i < colsA; ++i) {
sum += matrixA[row*colsA + i] * matrixB[i*rowsB + col];
}
matrixC[row*rowsB + col] = sum;
}
// Csub(i,j) = sum{A(i,ksub+offsetA)*B(ksub+offsetB,j)} 0 <= ksub < blockSize
// C(i,j) = sum{Csub(i,j)}
// each thread cal each block
__global__ void matrixMulGPUKernal1(float* matrixC,const float* matrixA,const float *matrixB,int colsA,int rowsB) {
int bx = blockIdx.x;
int by = blockIdx.y;
int tx = threadIdx.x;
int ty = threadIdx.y;
int aBegin = colsA*(by*BLOCK_SIZE);//A(0,by)
int aEnd = aBegin + colsA - 1;
int aStep = BLOCK_SIZE;//offsetA
int bBegin = BLOCK_SIZE*bx;//B(bx,0)
int bStep = BLOCK_SIZE*rowsB;//offsetB
float cSub = 0;
for (int a = aBegin,b = bBegin; a <= aEnd; a += aStep,b += bStep) {
__shared__ float As[BLOCK_SIZE][BLOCK_SIZE];
__shared__ float Bs[BLOCK_SIZE][BLOCK_SIZE];
As[ty][tx] = matrixA[a + colsA*ty + tx];
Bs[ty][tx] = matrixB[b + rowsB*ty + tx];
__syncthreads();
//i * j for each thread
for (int k = 0; k < BLOCK_SIZE; ++k) {
cSub += As[ty][k]*Bs[k][tx];
}
__syncthreads();
}
int cIndex = (by*BLOCK_SIZE + ty)*rowsB + (bx*BLOCK_SIZE + tx);
matrixC[cIndex] = cSub;
}
void copyFromCPUToGPU(const float *matrixA, float *d_a, int n) {
cudaMemcpy(d_a, matrixA, sizeof(float) * n, cudaMemcpyHostToDevice);
}
void copyFromGPUToCPU(const float *d_c, float *matrixC, int n) {
cudaMemcpy(matrixC, d_c, sizeof(float) * n, cudaMemcpyDeviceToHost);
}
void matrixMulGPU(float* matrixC,const float *matrixA,const float *matrixB,int colsA,int rowsA,int rowsB) {
float *d_a, *d_b, *d_c;
cudaMalloc((void**) &d_a, sizeof(float) * colsA*rowsA);
cudaMalloc((void**) &d_b, sizeof(float) * rowsB*colsA);
cudaMalloc((void**) &d_c, sizeof(float) * rowsB*rowsA);
copyFromCPUToGPU(matrixA,d_a,colsA*rowsA);
copyFromCPUToGPU(matrixB,d_b,rowsB*colsA);
dim3 blocks(rowsB/BLOCK_SIZE, rowsA/BLOCK_SIZE);
dim3 threads(BLOCK_SIZE, BLOCK_SIZE);
float time_elapsed = 0;
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaEventRecord(start, 0);
matrixMulGPUKernal0<<<blocks,threads>>>(d_c,d_a,d_b,colsA,rowsA);
cudaEventRecord(stop, 0);
cudaEventSynchronize(start);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&time_elapsed, start, stop);
cudaEventDestroy(start);
cudaEventDestroy(stop);
printf(" - Running time: %f ms\n", time_elapsed);
double gflop = (2.0 * (double)colsA * colsA * colsA) * 0.000001;
printf(" - GFlop: %.5f GFlop/sec\n\n", gflop/time_elapsed);
cudaThreadSynchronize();
copyFromGPUToCPU(d_c,matrixC,rowsB*rowsA);
cudaFree(d_a);
cudaFree(d_b);
cudaFree(d_c);
}
void randomInit(float* _data,int size) {
for (int i = 0; i < size; ++i) {
_data[i] = rand()/(float)RAND_MAX;
}
}
bool checkError(const float* matrixA, const float* matrixB, int size) {
for (int i = 0 ; i < size; ++i) {
if (fabs(matrixA[i] - matrixB[i]) > 1.0e-3) {
printf(" ! Wrong index: %d\n", i);
printf("%f \t %f\n",matrixA[i],matrixB[i]);
return false;
}
}
return true;
}
int main(int argc, char* argv[]) {
if (!InitCUDA()) return 0;
srand(63);
printf("\n - BLOCK_SIZE: %d\n", BLOCK_SIZE);
int N = (1 << 11);
int colsA, colsB, colsC, rowsA, rowsB, rowsC;
colsA = colsB = colsC = rowsA = rowsB = rowsC = N;
printf(" - Matrix size: %d * %d\n", rowsC, rowsC);
float* A , *B, *C, *C2;
A = (float*) malloc(sizeof(float) * colsA * rowsA);
B = (float*) malloc(sizeof(float) * colsB * rowsB);
randomInit(A,colsA*rowsA);
randomInit(B,colsB*rowsB);
C = (float*) malloc(sizeof(float) * colsC * rowsC);
memset(C,0,sizeof(float)*colsC*rowsC);
C2 = (float*) malloc(sizeof(float) * colsC * rowsC);
memset(C2,0,sizeof(float)*colsC*rowsC);
clock_t tick1 = clock();
matrixMulCPU(C2,A,B,colsA,rowsA,colsB);
printf(" - CPU use Time : %f ms\n",(double)(clock() - tick1)/CLOCKS_PER_SEC);
// unsigned int timer = 0;
// cutilCheckError(cutCreateTimer(&timer));
// cutilCheckError(cutStartTimer(timer));
matrixMulGPU(C,A,B,colsA,rowsA,colsB);
// cutilCheckError(cutStopTimer(timer));
// printf("GPU use time: %f (ms) \n", cutGetTimerValue(timer));
// cutilCheckError(cutDeleteTimer(timer));
if (checkError(C,C2,colsC*rowsC)) {
printf("Right Answer!\n");
}else{
printf("Worng Answer!\n");
}
free(A);
free(B);
free(C);
free(C2);
return 0;
} | #include <stdio.h>
#include <assert.h>
#include <hip/hip_runtime.h>
#include <stdlib.h>
#include <time.h>
#include <math.h>
#include <string.h>
#define BLOCK_SIZE 16
void printDeviceProp(const hipDeviceProp_t &prop) {
printf("Device Name : %s.\n", prop.name);
printf("totalGlobalMem : %lu.\n", prop.totalGlobalMem);
printf("sharedMemPerBlock : %lu.\n", prop.sharedMemPerBlock);
printf("regsPerBlock : %d.\n", prop.regsPerBlock);
printf("warpSize : %d.\n", prop.warpSize);
printf("memPitch : %lu.\n", prop.memPitch);
printf("maxThreadsPerBlock : %d.\n", prop.maxThreadsPerBlock);
printf("maxThreadsDim[0 - 2] : %d %d %d.\n", prop.maxThreadsDim[0], prop.maxThreadsDim[1], prop.maxThreadsDim[2]);
printf("maxGridSize[0 - 2] : %d %d %d.\n", prop.maxGridSize[0], prop.maxGridSize[1], prop.maxGridSize[2]);
printf("totalConstMem : %lu.\n", prop.totalConstMem);
printf("major.minor : %d.%d.\n", prop.major, prop.minor);
printf("clockRate : %d.\n", prop.clockRate);
printf("textureAlignment : %lu.\n", prop.textureAlignment);
printf("deviceOverlap : %d.\n", prop.deviceOverlap);
printf("multiProcessorCount : %d.\n", prop.multiProcessorCount);
}
bool InitCUDA() {
int count;
hipGetDeviceCount(&count);
if (count == 0) {
fprintf(stderr, "There is no device.\n");
return false;
}
int i;
for (i = 0; i < count; i++) {
hipDeviceProp_t prop;
hipGetDeviceProperties(&prop, i);
printDeviceProp(prop);
if (hipGetDeviceProperties(&prop, i) == hipSuccess) {
if (prop.major >= 1) {
break;
}
}
}
if (i == count) {
fprintf(stderr, "There is no device supporting CUDA 1.x.\n");
return false;
}
hipSetDevice(i);
return true;
}
//CPU
void matrixMulCPU(float* res,const float *matrixA,const float *matrixB,int colsA,int rowsA,int rowsB) {
float sum = 0;
for (int i = 0; i < rowsA; ++i) {
for (int j = 0; j < rowsB; ++j) {
sum = 0;
for (int k = 0; k < colsA; ++k) {
sum += (float)matrixA[i*colsA+k]*(float)matrixB[k*rowsB+ j];
}
res[i*rowsB+j] = (float)sum;
}
}
}
// GPU
// C(i,j) = sum{A(i, k)* B(k ,j)}
// each thread cal C(i, j)
__global__ void matrixMulGPUKernal0(float* matrixC,const float* matrixA,const float *matrixB,int colsA,int rowsB) {
float sum = 0;
int row = blockIdx.y*blockDim.y + threadIdx.y;
int col = blockIdx.x*blockDim.x + threadIdx.x;
for (int i = 0; i < colsA; ++i) {
sum += matrixA[row*colsA + i] * matrixB[i*rowsB + col];
}
matrixC[row*rowsB + col] = sum;
}
// Csub(i,j) = sum{A(i,ksub+offsetA)*B(ksub+offsetB,j)} 0 <= ksub < blockSize
// C(i,j) = sum{Csub(i,j)}
// each thread cal each block
__global__ void matrixMulGPUKernal1(float* matrixC,const float* matrixA,const float *matrixB,int colsA,int rowsB) {
int bx = blockIdx.x;
int by = blockIdx.y;
int tx = threadIdx.x;
int ty = threadIdx.y;
int aBegin = colsA*(by*BLOCK_SIZE);//A(0,by)
int aEnd = aBegin + colsA - 1;
int aStep = BLOCK_SIZE;//offsetA
int bBegin = BLOCK_SIZE*bx;//B(bx,0)
int bStep = BLOCK_SIZE*rowsB;//offsetB
float cSub = 0;
for (int a = aBegin,b = bBegin; a <= aEnd; a += aStep,b += bStep) {
__shared__ float As[BLOCK_SIZE][BLOCK_SIZE];
__shared__ float Bs[BLOCK_SIZE][BLOCK_SIZE];
As[ty][tx] = matrixA[a + colsA*ty + tx];
Bs[ty][tx] = matrixB[b + rowsB*ty + tx];
__syncthreads();
//i * j for each thread
for (int k = 0; k < BLOCK_SIZE; ++k) {
cSub += As[ty][k]*Bs[k][tx];
}
__syncthreads();
}
int cIndex = (by*BLOCK_SIZE + ty)*rowsB + (bx*BLOCK_SIZE + tx);
matrixC[cIndex] = cSub;
}
void copyFromCPUToGPU(const float *matrixA, float *d_a, int n) {
hipMemcpy(d_a, matrixA, sizeof(float) * n, hipMemcpyHostToDevice);
}
void copyFromGPUToCPU(const float *d_c, float *matrixC, int n) {
hipMemcpy(matrixC, d_c, sizeof(float) * n, hipMemcpyDeviceToHost);
}
void matrixMulGPU(float* matrixC,const float *matrixA,const float *matrixB,int colsA,int rowsA,int rowsB) {
float *d_a, *d_b, *d_c;
hipMalloc((void**) &d_a, sizeof(float) * colsA*rowsA);
hipMalloc((void**) &d_b, sizeof(float) * rowsB*colsA);
hipMalloc((void**) &d_c, sizeof(float) * rowsB*rowsA);
copyFromCPUToGPU(matrixA,d_a,colsA*rowsA);
copyFromCPUToGPU(matrixB,d_b,rowsB*colsA);
dim3 blocks(rowsB/BLOCK_SIZE, rowsA/BLOCK_SIZE);
dim3 threads(BLOCK_SIZE, BLOCK_SIZE);
float time_elapsed = 0;
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
hipEventRecord(start, 0);
matrixMulGPUKernal0<<<blocks,threads>>>(d_c,d_a,d_b,colsA,rowsA);
hipEventRecord(stop, 0);
hipEventSynchronize(start);
hipEventSynchronize(stop);
hipEventElapsedTime(&time_elapsed, start, stop);
hipEventDestroy(start);
hipEventDestroy(stop);
printf(" - Running time: %f ms\n", time_elapsed);
double gflop = (2.0 * (double)colsA * colsA * colsA) * 0.000001;
printf(" - GFlop: %.5f GFlop/sec\n\n", gflop/time_elapsed);
hipDeviceSynchronize();
copyFromGPUToCPU(d_c,matrixC,rowsB*rowsA);
hipFree(d_a);
hipFree(d_b);
hipFree(d_c);
}
void randomInit(float* _data,int size) {
for (int i = 0; i < size; ++i) {
_data[i] = rand()/(float)RAND_MAX;
}
}
bool checkError(const float* matrixA, const float* matrixB, int size) {
for (int i = 0 ; i < size; ++i) {
if (fabs(matrixA[i] - matrixB[i]) > 1.0e-3) {
printf(" ! Wrong index: %d\n", i);
printf("%f \t %f\n",matrixA[i],matrixB[i]);
return false;
}
}
return true;
}
int main(int argc, char* argv[]) {
if (!InitCUDA()) return 0;
srand(63);
printf("\n - BLOCK_SIZE: %d\n", BLOCK_SIZE);
int N = (1 << 11);
int colsA, colsB, colsC, rowsA, rowsB, rowsC;
colsA = colsB = colsC = rowsA = rowsB = rowsC = N;
printf(" - Matrix size: %d * %d\n", rowsC, rowsC);
float* A , *B, *C, *C2;
A = (float*) malloc(sizeof(float) * colsA * rowsA);
B = (float*) malloc(sizeof(float) * colsB * rowsB);
randomInit(A,colsA*rowsA);
randomInit(B,colsB*rowsB);
C = (float*) malloc(sizeof(float) * colsC * rowsC);
memset(C,0,sizeof(float)*colsC*rowsC);
C2 = (float*) malloc(sizeof(float) * colsC * rowsC);
memset(C2,0,sizeof(float)*colsC*rowsC);
clock_t tick1 = clock();
matrixMulCPU(C2,A,B,colsA,rowsA,colsB);
printf(" - CPU use Time : %f ms\n",(double)(clock() - tick1)/CLOCKS_PER_SEC);
// unsigned int timer = 0;
// cutilCheckError(cutCreateTimer(&timer));
// cutilCheckError(cutStartTimer(timer));
matrixMulGPU(C,A,B,colsA,rowsA,colsB);
// cutilCheckError(cutStopTimer(timer));
// printf("GPU use time: %f (ms) \n", cutGetTimerValue(timer));
// cutilCheckError(cutDeleteTimer(timer));
if (checkError(C,C2,colsC*rowsC)) {
printf("Right Answer!\n");
}else{
printf("Worng Answer!\n");
}
free(A);
free(B);
free(C);
free(C2);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <stdio.h>
#include <assert.h>
#include <hip/hip_runtime.h>
#include <stdlib.h>
#include <time.h>
#include <math.h>
#include <string.h>
#define BLOCK_SIZE 16
void printDeviceProp(const hipDeviceProp_t &prop) {
printf("Device Name : %s.\n", prop.name);
printf("totalGlobalMem : %lu.\n", prop.totalGlobalMem);
printf("sharedMemPerBlock : %lu.\n", prop.sharedMemPerBlock);
printf("regsPerBlock : %d.\n", prop.regsPerBlock);
printf("warpSize : %d.\n", prop.warpSize);
printf("memPitch : %lu.\n", prop.memPitch);
printf("maxThreadsPerBlock : %d.\n", prop.maxThreadsPerBlock);
printf("maxThreadsDim[0 - 2] : %d %d %d.\n", prop.maxThreadsDim[0], prop.maxThreadsDim[1], prop.maxThreadsDim[2]);
printf("maxGridSize[0 - 2] : %d %d %d.\n", prop.maxGridSize[0], prop.maxGridSize[1], prop.maxGridSize[2]);
printf("totalConstMem : %lu.\n", prop.totalConstMem);
printf("major.minor : %d.%d.\n", prop.major, prop.minor);
printf("clockRate : %d.\n", prop.clockRate);
printf("textureAlignment : %lu.\n", prop.textureAlignment);
printf("deviceOverlap : %d.\n", prop.deviceOverlap);
printf("multiProcessorCount : %d.\n", prop.multiProcessorCount);
}
bool InitCUDA() {
int count;
hipGetDeviceCount(&count);
if (count == 0) {
fprintf(stderr, "There is no device.\n");
return false;
}
int i;
for (i = 0; i < count; i++) {
hipDeviceProp_t prop;
hipGetDeviceProperties(&prop, i);
printDeviceProp(prop);
if (hipGetDeviceProperties(&prop, i) == hipSuccess) {
if (prop.major >= 1) {
break;
}
}
}
if (i == count) {
fprintf(stderr, "There is no device supporting CUDA 1.x.\n");
return false;
}
hipSetDevice(i);
return true;
}
//CPU
void matrixMulCPU(float* res,const float *matrixA,const float *matrixB,int colsA,int rowsA,int rowsB) {
float sum = 0;
for (int i = 0; i < rowsA; ++i) {
for (int j = 0; j < rowsB; ++j) {
sum = 0;
for (int k = 0; k < colsA; ++k) {
sum += (float)matrixA[i*colsA+k]*(float)matrixB[k*rowsB+ j];
}
res[i*rowsB+j] = (float)sum;
}
}
}
// GPU
// C(i,j) = sum{A(i, k)* B(k ,j)}
// each thread cal C(i, j)
__global__ void matrixMulGPUKernal0(float* matrixC,const float* matrixA,const float *matrixB,int colsA,int rowsB) {
float sum = 0;
int row = blockIdx.y*blockDim.y + threadIdx.y;
int col = blockIdx.x*blockDim.x + threadIdx.x;
for (int i = 0; i < colsA; ++i) {
sum += matrixA[row*colsA + i] * matrixB[i*rowsB + col];
}
matrixC[row*rowsB + col] = sum;
}
// Csub(i,j) = sum{A(i,ksub+offsetA)*B(ksub+offsetB,j)} 0 <= ksub < blockSize
// C(i,j) = sum{Csub(i,j)}
// each thread cal each block
__global__ void matrixMulGPUKernal1(float* matrixC,const float* matrixA,const float *matrixB,int colsA,int rowsB) {
int bx = blockIdx.x;
int by = blockIdx.y;
int tx = threadIdx.x;
int ty = threadIdx.y;
int aBegin = colsA*(by*BLOCK_SIZE);//A(0,by)
int aEnd = aBegin + colsA - 1;
int aStep = BLOCK_SIZE;//offsetA
int bBegin = BLOCK_SIZE*bx;//B(bx,0)
int bStep = BLOCK_SIZE*rowsB;//offsetB
float cSub = 0;
for (int a = aBegin,b = bBegin; a <= aEnd; a += aStep,b += bStep) {
__shared__ float As[BLOCK_SIZE][BLOCK_SIZE];
__shared__ float Bs[BLOCK_SIZE][BLOCK_SIZE];
As[ty][tx] = matrixA[a + colsA*ty + tx];
Bs[ty][tx] = matrixB[b + rowsB*ty + tx];
__syncthreads();
//i * j for each thread
for (int k = 0; k < BLOCK_SIZE; ++k) {
cSub += As[ty][k]*Bs[k][tx];
}
__syncthreads();
}
int cIndex = (by*BLOCK_SIZE + ty)*rowsB + (bx*BLOCK_SIZE + tx);
matrixC[cIndex] = cSub;
}
void copyFromCPUToGPU(const float *matrixA, float *d_a, int n) {
hipMemcpy(d_a, matrixA, sizeof(float) * n, hipMemcpyHostToDevice);
}
void copyFromGPUToCPU(const float *d_c, float *matrixC, int n) {
hipMemcpy(matrixC, d_c, sizeof(float) * n, hipMemcpyDeviceToHost);
}
void matrixMulGPU(float* matrixC,const float *matrixA,const float *matrixB,int colsA,int rowsA,int rowsB) {
float *d_a, *d_b, *d_c;
hipMalloc((void**) &d_a, sizeof(float) * colsA*rowsA);
hipMalloc((void**) &d_b, sizeof(float) * rowsB*colsA);
hipMalloc((void**) &d_c, sizeof(float) * rowsB*rowsA);
copyFromCPUToGPU(matrixA,d_a,colsA*rowsA);
copyFromCPUToGPU(matrixB,d_b,rowsB*colsA);
dim3 blocks(rowsB/BLOCK_SIZE, rowsA/BLOCK_SIZE);
dim3 threads(BLOCK_SIZE, BLOCK_SIZE);
float time_elapsed = 0;
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
hipEventRecord(start, 0);
matrixMulGPUKernal0<<<blocks,threads>>>(d_c,d_a,d_b,colsA,rowsA);
hipEventRecord(stop, 0);
hipEventSynchronize(start);
hipEventSynchronize(stop);
hipEventElapsedTime(&time_elapsed, start, stop);
hipEventDestroy(start);
hipEventDestroy(stop);
printf(" - Running time: %f ms\n", time_elapsed);
double gflop = (2.0 * (double)colsA * colsA * colsA) * 0.000001;
printf(" - GFlop: %.5f GFlop/sec\n\n", gflop/time_elapsed);
hipDeviceSynchronize();
copyFromGPUToCPU(d_c,matrixC,rowsB*rowsA);
hipFree(d_a);
hipFree(d_b);
hipFree(d_c);
}
void randomInit(float* _data,int size) {
for (int i = 0; i < size; ++i) {
_data[i] = rand()/(float)RAND_MAX;
}
}
bool checkError(const float* matrixA, const float* matrixB, int size) {
for (int i = 0 ; i < size; ++i) {
if (fabs(matrixA[i] - matrixB[i]) > 1.0e-3) {
printf(" ! Wrong index: %d\n", i);
printf("%f \t %f\n",matrixA[i],matrixB[i]);
return false;
}
}
return true;
}
int main(int argc, char* argv[]) {
if (!InitCUDA()) return 0;
srand(63);
printf("\n - BLOCK_SIZE: %d\n", BLOCK_SIZE);
int N = (1 << 11);
int colsA, colsB, colsC, rowsA, rowsB, rowsC;
colsA = colsB = colsC = rowsA = rowsB = rowsC = N;
printf(" - Matrix size: %d * %d\n", rowsC, rowsC);
float* A , *B, *C, *C2;
A = (float*) malloc(sizeof(float) * colsA * rowsA);
B = (float*) malloc(sizeof(float) * colsB * rowsB);
randomInit(A,colsA*rowsA);
randomInit(B,colsB*rowsB);
C = (float*) malloc(sizeof(float) * colsC * rowsC);
memset(C,0,sizeof(float)*colsC*rowsC);
C2 = (float*) malloc(sizeof(float) * colsC * rowsC);
memset(C2,0,sizeof(float)*colsC*rowsC);
clock_t tick1 = clock();
matrixMulCPU(C2,A,B,colsA,rowsA,colsB);
printf(" - CPU use Time : %f ms\n",(double)(clock() - tick1)/CLOCKS_PER_SEC);
// unsigned int timer = 0;
// cutilCheckError(cutCreateTimer(&timer));
// cutilCheckError(cutStartTimer(timer));
matrixMulGPU(C,A,B,colsA,rowsA,colsB);
// cutilCheckError(cutStopTimer(timer));
// printf("GPU use time: %f (ms) \n", cutGetTimerValue(timer));
// cutilCheckError(cutDeleteTimer(timer));
if (checkError(C,C2,colsC*rowsC)) {
printf("Right Answer!\n");
}else{
printf("Worng Answer!\n");
}
free(A);
free(B);
free(C);
free(C2);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z19matrixMulGPUKernal0PfPKfS1_ii
.globl _Z19matrixMulGPUKernal0PfPKfS1_ii
.p2align 8
.type _Z19matrixMulGPUKernal0PfPKfS1_ii,@function
_Z19matrixMulGPUKernal0PfPKfS1_ii:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x2c
s_load_b64 s[2:3], s[0:1], 0x18
v_bfe_u32 v2, v0, 10, 10
v_and_b32_e32 v3, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s5, s4, 16
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(VALU_DEP_1)
v_mad_u64_u32 v[0:1], null, s15, s5, v[2:3]
v_mad_u64_u32 v[1:2], null, s14, s4, v[3:4]
s_cmp_lt_i32 s2, 1
s_cbranch_scc1 .LBB0_3
s_load_b128 s[4:7], s[0:1], 0x8
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_mul_lo_u32 v2, v0, s2
v_mov_b32_e32 v6, 0
v_mov_b32_e32 v4, v1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
.p2align 6
.LBB0_2:
v_ashrrev_i32_e32 v5, 31, v4
s_add_i32 s2, s2, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_cmp_eq_u32 s2, 0
v_lshlrev_b64 v[7:8], 2, v[4:5]
v_add_nc_u32_e32 v4, s3, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v7, vcc_lo, s6, v7
v_add_co_ci_u32_e32 v8, vcc_lo, s7, v8, vcc_lo
global_load_b32 v5, v[2:3], off
global_load_b32 v7, v[7:8], off
v_add_co_u32 v2, vcc_lo, v2, 4
v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v6, v5, v7
s_cbranch_scc0 .LBB0_2
s_branch .LBB0_4
.LBB0_3:
v_mov_b32_e32 v6, 0
.LBB0_4:
s_load_b64 s[0:1], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, v0, s3, v[1:2]
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[2:3]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v6, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z19matrixMulGPUKernal0PfPKfS1_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z19matrixMulGPUKernal0PfPKfS1_ii, .Lfunc_end0-_Z19matrixMulGPUKernal0PfPKfS1_ii
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z19matrixMulGPUKernal1PfPKfS1_ii
.globl _Z19matrixMulGPUKernal1PfPKfS1_ii
.p2align 8
.type _Z19matrixMulGPUKernal1PfPKfS1_ii,@function
_Z19matrixMulGPUKernal1PfPKfS1_ii:
s_load_b64 s[2:3], s[0:1], 0x18
v_and_b32_e32 v1, 0x3ff, v0
v_bfe_u32 v0, v0, 10, 10
s_lshl_b32 s9, s15, 4
s_lshl_b32 s8, s14, 4
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s2, 1
s_cbranch_scc1 .LBB1_5
s_load_b128 s[4:7], s[0:1], 0x8
v_mad_u64_u32 v[2:3], null, v0, s2, v[1:2]
v_lshlrev_b32_e32 v7, 2, v1
v_lshlrev_b32_e32 v5, 6, v0
s_mul_i32 s10, s9, s2
s_lshl_b32 s11, s3, 4
s_add_i32 s2, s10, s2
s_mov_b32 s12, s8
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[3:4], null, v0, s3, v[1:2]
v_mov_b32_e32 v4, 0
v_add_nc_u32_e32 v6, 0x400, v7
v_add_nc_u32_e32 v7, v5, v7
v_add_nc_u32_e32 v8, v6, v5
s_set_inst_prefetch_distance 0x1
.p2align 6
.LBB1_2:
v_add_nc_u32_e32 v9, s10, v2
v_add_nc_u32_e32 v11, s12, v3
s_mov_b32 s13, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v10, 31, v9
v_ashrrev_i32_e32 v12, 31, v11
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[9:10], 2, v[9:10]
v_lshlrev_b64 v[11:12], 2, v[11:12]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v9, vcc_lo, s4, v9
v_add_co_ci_u32_e32 v10, vcc_lo, s5, v10, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v11, vcc_lo, s6, v11
v_add_co_ci_u32_e32 v12, vcc_lo, s7, v12, vcc_lo
global_load_b32 v10, v[9:10], off
global_load_b32 v11, v[11:12], off
v_mov_b32_e32 v9, v6
s_waitcnt vmcnt(1)
ds_store_b32 v7, v10
s_waitcnt vmcnt(0)
ds_store_b32 v8, v11
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
.LBB1_3:
v_add_nc_u32_e32 v10, s13, v5
s_add_i32 s13, s13, 4
ds_load_b32 v11, v9
ds_load_b32 v10, v10
v_add_nc_u32_e32 v9, 64, v9
s_cmp_eq_u32 s13, 64
s_waitcnt lgkmcnt(0)
v_fmac_f32_e32 v4, v10, v11
s_cbranch_scc0 .LBB1_3
s_add_i32 s10, s10, 16
s_add_i32 s12, s12, s11
s_cmp_ge_i32 s10, s2
s_barrier
buffer_gl0_inv
s_cbranch_scc0 .LBB1_2
s_branch .LBB1_6
.LBB1_5:
v_mov_b32_e32 v4, 0
.LBB1_6:
s_set_inst_prefetch_distance 0x2
v_add_nc_u32_e32 v0, s9, v0
s_load_b64 s[0:1], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v0, v0, s3
v_add3_u32 v0, s8, v1, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v4, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z19matrixMulGPUKernal1PfPKfS1_ii
.amdhsa_group_segment_fixed_size 2048
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 32
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 13
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z19matrixMulGPUKernal1PfPKfS1_ii, .Lfunc_end1-_Z19matrixMulGPUKernal1PfPKfS1_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z19matrixMulGPUKernal0PfPKfS1_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z19matrixMulGPUKernal0PfPKfS1_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 2048
.kernarg_segment_align: 8
.kernarg_segment_size: 32
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z19matrixMulGPUKernal1PfPKfS1_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z19matrixMulGPUKernal1PfPKfS1_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 13
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <stdio.h>
#include <assert.h>
#include <hip/hip_runtime.h>
#include <stdlib.h>
#include <time.h>
#include <math.h>
#include <string.h>
#define BLOCK_SIZE 16
void printDeviceProp(const hipDeviceProp_t &prop) {
printf("Device Name : %s.\n", prop.name);
printf("totalGlobalMem : %lu.\n", prop.totalGlobalMem);
printf("sharedMemPerBlock : %lu.\n", prop.sharedMemPerBlock);
printf("regsPerBlock : %d.\n", prop.regsPerBlock);
printf("warpSize : %d.\n", prop.warpSize);
printf("memPitch : %lu.\n", prop.memPitch);
printf("maxThreadsPerBlock : %d.\n", prop.maxThreadsPerBlock);
printf("maxThreadsDim[0 - 2] : %d %d %d.\n", prop.maxThreadsDim[0], prop.maxThreadsDim[1], prop.maxThreadsDim[2]);
printf("maxGridSize[0 - 2] : %d %d %d.\n", prop.maxGridSize[0], prop.maxGridSize[1], prop.maxGridSize[2]);
printf("totalConstMem : %lu.\n", prop.totalConstMem);
printf("major.minor : %d.%d.\n", prop.major, prop.minor);
printf("clockRate : %d.\n", prop.clockRate);
printf("textureAlignment : %lu.\n", prop.textureAlignment);
printf("deviceOverlap : %d.\n", prop.deviceOverlap);
printf("multiProcessorCount : %d.\n", prop.multiProcessorCount);
}
bool InitCUDA() {
int count;
hipGetDeviceCount(&count);
if (count == 0) {
fprintf(stderr, "There is no device.\n");
return false;
}
int i;
for (i = 0; i < count; i++) {
hipDeviceProp_t prop;
hipGetDeviceProperties(&prop, i);
printDeviceProp(prop);
if (hipGetDeviceProperties(&prop, i) == hipSuccess) {
if (prop.major >= 1) {
break;
}
}
}
if (i == count) {
fprintf(stderr, "There is no device supporting CUDA 1.x.\n");
return false;
}
hipSetDevice(i);
return true;
}
//CPU
void matrixMulCPU(float* res,const float *matrixA,const float *matrixB,int colsA,int rowsA,int rowsB) {
float sum = 0;
for (int i = 0; i < rowsA; ++i) {
for (int j = 0; j < rowsB; ++j) {
sum = 0;
for (int k = 0; k < colsA; ++k) {
sum += (float)matrixA[i*colsA+k]*(float)matrixB[k*rowsB+ j];
}
res[i*rowsB+j] = (float)sum;
}
}
}
// GPU
// C(i,j) = sum{A(i, k)* B(k ,j)}
// each thread cal C(i, j)
__global__ void matrixMulGPUKernal0(float* matrixC,const float* matrixA,const float *matrixB,int colsA,int rowsB) {
float sum = 0;
int row = blockIdx.y*blockDim.y + threadIdx.y;
int col = blockIdx.x*blockDim.x + threadIdx.x;
for (int i = 0; i < colsA; ++i) {
sum += matrixA[row*colsA + i] * matrixB[i*rowsB + col];
}
matrixC[row*rowsB + col] = sum;
}
// Csub(i,j) = sum{A(i,ksub+offsetA)*B(ksub+offsetB,j)} 0 <= ksub < blockSize
// C(i,j) = sum{Csub(i,j)}
// each thread cal each block
__global__ void matrixMulGPUKernal1(float* matrixC,const float* matrixA,const float *matrixB,int colsA,int rowsB) {
int bx = blockIdx.x;
int by = blockIdx.y;
int tx = threadIdx.x;
int ty = threadIdx.y;
int aBegin = colsA*(by*BLOCK_SIZE);//A(0,by)
int aEnd = aBegin + colsA - 1;
int aStep = BLOCK_SIZE;//offsetA
int bBegin = BLOCK_SIZE*bx;//B(bx,0)
int bStep = BLOCK_SIZE*rowsB;//offsetB
float cSub = 0;
for (int a = aBegin,b = bBegin; a <= aEnd; a += aStep,b += bStep) {
__shared__ float As[BLOCK_SIZE][BLOCK_SIZE];
__shared__ float Bs[BLOCK_SIZE][BLOCK_SIZE];
As[ty][tx] = matrixA[a + colsA*ty + tx];
Bs[ty][tx] = matrixB[b + rowsB*ty + tx];
__syncthreads();
//i * j for each thread
for (int k = 0; k < BLOCK_SIZE; ++k) {
cSub += As[ty][k]*Bs[k][tx];
}
__syncthreads();
}
int cIndex = (by*BLOCK_SIZE + ty)*rowsB + (bx*BLOCK_SIZE + tx);
matrixC[cIndex] = cSub;
}
void copyFromCPUToGPU(const float *matrixA, float *d_a, int n) {
hipMemcpy(d_a, matrixA, sizeof(float) * n, hipMemcpyHostToDevice);
}
void copyFromGPUToCPU(const float *d_c, float *matrixC, int n) {
hipMemcpy(matrixC, d_c, sizeof(float) * n, hipMemcpyDeviceToHost);
}
void matrixMulGPU(float* matrixC,const float *matrixA,const float *matrixB,int colsA,int rowsA,int rowsB) {
float *d_a, *d_b, *d_c;
hipMalloc((void**) &d_a, sizeof(float) * colsA*rowsA);
hipMalloc((void**) &d_b, sizeof(float) * rowsB*colsA);
hipMalloc((void**) &d_c, sizeof(float) * rowsB*rowsA);
copyFromCPUToGPU(matrixA,d_a,colsA*rowsA);
copyFromCPUToGPU(matrixB,d_b,rowsB*colsA);
dim3 blocks(rowsB/BLOCK_SIZE, rowsA/BLOCK_SIZE);
dim3 threads(BLOCK_SIZE, BLOCK_SIZE);
float time_elapsed = 0;
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
hipEventRecord(start, 0);
matrixMulGPUKernal0<<<blocks,threads>>>(d_c,d_a,d_b,colsA,rowsA);
hipEventRecord(stop, 0);
hipEventSynchronize(start);
hipEventSynchronize(stop);
hipEventElapsedTime(&time_elapsed, start, stop);
hipEventDestroy(start);
hipEventDestroy(stop);
printf(" - Running time: %f ms\n", time_elapsed);
double gflop = (2.0 * (double)colsA * colsA * colsA) * 0.000001;
printf(" - GFlop: %.5f GFlop/sec\n\n", gflop/time_elapsed);
hipDeviceSynchronize();
copyFromGPUToCPU(d_c,matrixC,rowsB*rowsA);
hipFree(d_a);
hipFree(d_b);
hipFree(d_c);
}
void randomInit(float* _data,int size) {
for (int i = 0; i < size; ++i) {
_data[i] = rand()/(float)RAND_MAX;
}
}
bool checkError(const float* matrixA, const float* matrixB, int size) {
for (int i = 0 ; i < size; ++i) {
if (fabs(matrixA[i] - matrixB[i]) > 1.0e-3) {
printf(" ! Wrong index: %d\n", i);
printf("%f \t %f\n",matrixA[i],matrixB[i]);
return false;
}
}
return true;
}
int main(int argc, char* argv[]) {
if (!InitCUDA()) return 0;
srand(63);
printf("\n - BLOCK_SIZE: %d\n", BLOCK_SIZE);
int N = (1 << 11);
int colsA, colsB, colsC, rowsA, rowsB, rowsC;
colsA = colsB = colsC = rowsA = rowsB = rowsC = N;
printf(" - Matrix size: %d * %d\n", rowsC, rowsC);
float* A , *B, *C, *C2;
A = (float*) malloc(sizeof(float) * colsA * rowsA);
B = (float*) malloc(sizeof(float) * colsB * rowsB);
randomInit(A,colsA*rowsA);
randomInit(B,colsB*rowsB);
C = (float*) malloc(sizeof(float) * colsC * rowsC);
memset(C,0,sizeof(float)*colsC*rowsC);
C2 = (float*) malloc(sizeof(float) * colsC * rowsC);
memset(C2,0,sizeof(float)*colsC*rowsC);
clock_t tick1 = clock();
matrixMulCPU(C2,A,B,colsA,rowsA,colsB);
printf(" - CPU use Time : %f ms\n",(double)(clock() - tick1)/CLOCKS_PER_SEC);
// unsigned int timer = 0;
// cutilCheckError(cutCreateTimer(&timer));
// cutilCheckError(cutStartTimer(timer));
matrixMulGPU(C,A,B,colsA,rowsA,colsB);
// cutilCheckError(cutStopTimer(timer));
// printf("GPU use time: %f (ms) \n", cutGetTimerValue(timer));
// cutilCheckError(cutDeleteTimer(timer));
if (checkError(C,C2,colsC*rowsC)) {
printf("Right Answer!\n");
}else{
printf("Worng Answer!\n");
}
free(A);
free(B);
free(C);
free(C2);
return 0;
} | .text
.file "matrixMul.hip"
.globl _Z15printDevicePropRK20hipDeviceProp_tR0600 # -- Begin function _Z15printDevicePropRK20hipDeviceProp_tR0600
.p2align 4, 0x90
.type _Z15printDevicePropRK20hipDeviceProp_tR0600,@function
_Z15printDevicePropRK20hipDeviceProp_tR0600: # @_Z15printDevicePropRK20hipDeviceProp_tR0600
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
movq %rdi, %rbx
movl $.L.str, %edi
movq %rbx, %rsi
xorl %eax, %eax
callq printf
movq 288(%rbx), %rsi
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
movq 296(%rbx), %rsi
movl $.L.str.2, %edi
xorl %eax, %eax
callq printf
movl 304(%rbx), %esi
movl $.L.str.3, %edi
xorl %eax, %eax
callq printf
movl 308(%rbx), %esi
movl $.L.str.4, %edi
xorl %eax, %eax
callq printf
movq 312(%rbx), %rsi
movl $.L.str.5, %edi
xorl %eax, %eax
callq printf
movl 320(%rbx), %esi
movl $.L.str.6, %edi
xorl %eax, %eax
callq printf
movl 324(%rbx), %esi
movl 328(%rbx), %edx
movl 332(%rbx), %ecx
movl $.L.str.7, %edi
xorl %eax, %eax
callq printf
movl 336(%rbx), %esi
movl 340(%rbx), %edx
movl 344(%rbx), %ecx
movl $.L.str.8, %edi
xorl %eax, %eax
callq printf
movq 352(%rbx), %rsi
movl $.L.str.9, %edi
xorl %eax, %eax
callq printf
movl 360(%rbx), %esi
movl 364(%rbx), %edx
movl $.L.str.10, %edi
xorl %eax, %eax
callq printf
movl 348(%rbx), %esi
movl $.L.str.11, %edi
xorl %eax, %eax
callq printf
movq 368(%rbx), %rsi
movl $.L.str.12, %edi
xorl %eax, %eax
callq printf
movl 384(%rbx), %esi
movl $.L.str.13, %edi
xorl %eax, %eax
callq printf
movl 388(%rbx), %esi
movl $.L.str.14, %edi
xorl %eax, %eax
popq %rbx
.cfi_def_cfa_offset 8
jmp printf # TAILCALL
.Lfunc_end0:
.size _Z15printDevicePropRK20hipDeviceProp_tR0600, .Lfunc_end0-_Z15printDevicePropRK20hipDeviceProp_tR0600
.cfi_endproc
# -- End function
.globl _Z8InitCUDAv # -- Begin function _Z8InitCUDAv
.p2align 4, 0x90
.type _Z8InitCUDAv,@function
_Z8InitCUDAv: # @_Z8InitCUDAv
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $1480, %rsp # imm = 0x5C8
.cfi_def_cfa_offset 1504
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
leaq 4(%rsp), %rdi
callq hipGetDeviceCount
cmpl $0, 4(%rsp)
je .LBB1_3
# %bb.1: # %.preheader
cmpl $0, 4(%rsp)
jle .LBB1_2
# %bb.5: # %.lr.ph
xorl %ebx, %ebx
leaq 8(%rsp), %r14
jmp .LBB1_6
.p2align 4, 0x90
.LBB1_8: # in Loop: Header=BB1_6 Depth=1
incl %ebx
cmpl 4(%rsp), %ebx
jge .LBB1_9
.LBB1_6: # =>This Inner Loop Header: Depth=1
movq %r14, %rdi
movl %ebx, %esi
callq hipGetDevicePropertiesR0600
movq %r14, %rdi
callq _Z15printDevicePropRK20hipDeviceProp_tR0600
movq %r14, %rdi
movl %ebx, %esi
callq hipGetDevicePropertiesR0600
testl %eax, %eax
jne .LBB1_8
# %bb.7: # in Loop: Header=BB1_6 Depth=1
cmpl $0, 368(%rsp)
jle .LBB1_8
jmp .LBB1_9
.LBB1_2:
xorl %ebx, %ebx
.LBB1_9: # %._crit_edge
cmpl 4(%rsp), %ebx
je .LBB1_10
# %bb.11:
movl %ebx, %edi
callq hipSetDevice
movb $1, %al
.LBB1_12:
# kill: def $al killed $al killed $eax
addq $1480, %rsp # imm = 0x5C8
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.LBB1_3:
.cfi_def_cfa_offset 1504
movq stderr(%rip), %rcx
movl $.L.str.15, %edi
movl $20, %esi
jmp .LBB1_4
.LBB1_10:
movq stderr(%rip), %rcx
movl $.L.str.16, %edi
movl $40, %esi
.LBB1_4:
movl $1, %edx
callq fwrite@PLT
xorl %eax, %eax
jmp .LBB1_12
.Lfunc_end1:
.size _Z8InitCUDAv, .Lfunc_end1-_Z8InitCUDAv
.cfi_endproc
# -- End function
.globl _Z12matrixMulCPUPfPKfS1_iii # -- Begin function _Z12matrixMulCPUPfPKfS1_iii
.p2align 4, 0x90
.type _Z12matrixMulCPUPfPKfS1_iii,@function
_Z12matrixMulCPUPfPKfS1_iii: # @_Z12matrixMulCPUPfPKfS1_iii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rdx, -8(%rsp) # 8-byte Spill
movq %rsi, -16(%rsp) # 8-byte Spill
movq %rdi, -24(%rsp) # 8-byte Spill
testl %r8d, %r8d
jle .LBB2_9
# %bb.1: # %.preheader27.lr.ph
movslq %r9d, %rdi
movl %r8d, %r8d
movl %edi, %r10d
movl %ecx, %r11d
leaq (,%rdi,4), %rbx
xorl %r14d, %r14d
xorl %r15d, %r15d
jmp .LBB2_2
.p2align 4, 0x90
.LBB2_8: # %._crit_edge31
# in Loop: Header=BB2_2 Depth=1
incq %r15
addl %ecx, %r14d
cmpq %r8, %r15
je .LBB2_9
.LBB2_2: # %.preheader27
# =>This Loop Header: Depth=1
# Child Loop BB2_4 Depth 2
# Child Loop BB2_6 Depth 3
testl %r9d, %r9d
jle .LBB2_8
# %bb.3: # %.preheader.lr.ph
# in Loop: Header=BB2_2 Depth=1
movl %r14d, %eax
movq -16(%rsp), %rdx # 8-byte Reload
leaq (%rdx,%rax,4), %r12
movq %r15, %rax
imulq %rdi, %rax
movq -24(%rsp), %rdx # 8-byte Reload
leaq (%rdx,%rax,4), %r13
movq -8(%rsp), %rdx # 8-byte Reload
xorl %eax, %eax
jmp .LBB2_4
.p2align 4, 0x90
.LBB2_7: # %._crit_edge
# in Loop: Header=BB2_4 Depth=2
movss %xmm0, (%r13,%rax,4)
incq %rax
addq $4, %rdx
cmpq %r10, %rax
je .LBB2_8
.LBB2_4: # %.preheader
# Parent Loop BB2_2 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB2_6 Depth 3
xorps %xmm0, %xmm0
testl %ecx, %ecx
jle .LBB2_7
# %bb.5: # %.lr.ph.preheader
# in Loop: Header=BB2_4 Depth=2
movq %rdx, %rbp
xorl %esi, %esi
.p2align 4, 0x90
.LBB2_6: # %.lr.ph
# Parent Loop BB2_2 Depth=1
# Parent Loop BB2_4 Depth=2
# => This Inner Loop Header: Depth=3
movss (%r12,%rsi,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
mulss (%rbp), %xmm1
addss %xmm1, %xmm0
incq %rsi
addq %rbx, %rbp
cmpq %rsi, %r11
jne .LBB2_6
jmp .LBB2_7
.LBB2_9: # %._crit_edge33
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z12matrixMulCPUPfPKfS1_iii, .Lfunc_end2-_Z12matrixMulCPUPfPKfS1_iii
.cfi_endproc
# -- End function
.globl _Z34__device_stub__matrixMulGPUKernal0PfPKfS1_ii # -- Begin function _Z34__device_stub__matrixMulGPUKernal0PfPKfS1_ii
.p2align 4, 0x90
.type _Z34__device_stub__matrixMulGPUKernal0PfPKfS1_ii,@function
_Z34__device_stub__matrixMulGPUKernal0PfPKfS1_ii: # @_Z34__device_stub__matrixMulGPUKernal0PfPKfS1_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z19matrixMulGPUKernal0PfPKfS1_ii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end3:
.size _Z34__device_stub__matrixMulGPUKernal0PfPKfS1_ii, .Lfunc_end3-_Z34__device_stub__matrixMulGPUKernal0PfPKfS1_ii
.cfi_endproc
# -- End function
.globl _Z34__device_stub__matrixMulGPUKernal1PfPKfS1_ii # -- Begin function _Z34__device_stub__matrixMulGPUKernal1PfPKfS1_ii
.p2align 4, 0x90
.type _Z34__device_stub__matrixMulGPUKernal1PfPKfS1_ii,@function
_Z34__device_stub__matrixMulGPUKernal1PfPKfS1_ii: # @_Z34__device_stub__matrixMulGPUKernal1PfPKfS1_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z19matrixMulGPUKernal1PfPKfS1_ii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end4:
.size _Z34__device_stub__matrixMulGPUKernal1PfPKfS1_ii, .Lfunc_end4-_Z34__device_stub__matrixMulGPUKernal1PfPKfS1_ii
.cfi_endproc
# -- End function
.globl _Z16copyFromCPUToGPUPKfPfi # -- Begin function _Z16copyFromCPUToGPUPKfPfi
.p2align 4, 0x90
.type _Z16copyFromCPUToGPUPKfPfi,@function
_Z16copyFromCPUToGPUPKfPfi: # @_Z16copyFromCPUToGPUPKfPfi
.cfi_startproc
# %bb.0:
movq %rdi, %rax
movslq %edx, %rdx
shlq $2, %rdx
movq %rsi, %rdi
movq %rax, %rsi
movl $1, %ecx
jmp hipMemcpy # TAILCALL
.Lfunc_end5:
.size _Z16copyFromCPUToGPUPKfPfi, .Lfunc_end5-_Z16copyFromCPUToGPUPKfPfi
.cfi_endproc
# -- End function
.globl _Z16copyFromGPUToCPUPKfPfi # -- Begin function _Z16copyFromGPUToCPUPKfPfi
.p2align 4, 0x90
.type _Z16copyFromGPUToCPUPKfPfi,@function
_Z16copyFromGPUToCPUPKfPfi: # @_Z16copyFromGPUToCPUPKfPfi
.cfi_startproc
# %bb.0:
movq %rdi, %rax
movslq %edx, %rdx
shlq $2, %rdx
movq %rsi, %rdi
movq %rax, %rsi
movl $2, %ecx
jmp hipMemcpy # TAILCALL
.Lfunc_end6:
.size _Z16copyFromGPUToCPUPKfPfi, .Lfunc_end6-_Z16copyFromGPUToCPUPKfPfi
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z12matrixMulGPUPfPKfS1_iii
.LCPI7_0:
.quad 0x3eb0c6f7a0b5ed8d # double 9.9999999999999995E-7
.text
.globl _Z12matrixMulGPUPfPKfS1_iii
.p2align 4, 0x90
.type _Z12matrixMulGPUPfPKfS1_iii,@function
_Z12matrixMulGPUPfPKfS1_iii: # @_Z12matrixMulGPUPfPKfS1_iii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $200, %rsp
.cfi_def_cfa_offset 256
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %r9d, %ebx
movl %r8d, %r12d
movl %ecx, %r13d
movq %rdx, 72(%rsp) # 8-byte Spill
movq %rsi, 64(%rsp) # 8-byte Spill
movq %rdi, 80(%rsp) # 8-byte Spill
movslq %ecx, %r14
movslq %r8d, %rbp
movq %r14, %rsi
imulq %rbp, %rsi
shlq $2, %rsi
leaq 40(%rsp), %rdi
callq hipMalloc
movl %ebx, 52(%rsp) # 4-byte Spill
movslq %ebx, %r15
leaq (,%r15,4), %rbx
imulq %rbx, %r14
leaq 32(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
imulq %rbp, %rbx
leaq 24(%rsp), %rdi
movq %rbx, %rsi
movl %r12d, %ebx
callq hipMalloc
movq 40(%rsp), %rdi
movl %r12d, %eax
imull %r13d, %eax
movslq %eax, %rdx
shlq $2, %rdx
movq 64(%rsp), %rsi # 8-byte Reload
movl $1, %ecx
callq hipMemcpy
movq 32(%rsp), %rdi
movl %r15d, %eax
imull %r13d, %eax
movslq %eax, %rdx
shlq $2, %rdx
movq 72(%rsp), %rsi # 8-byte Reload
movl $1, %ecx
callq hipMemcpy
leal 15(%r15), %eax
testl %r15d, %r15d
cmovnsl %r15d, %eax
sarl $4, %eax
leal 15(%rbp), %r12d
testl %ebp, %ebp
cmovnsl %ebx, %r12d
sarl $4, %r12d
shlq $32, %r12
orq %rax, %r12
movl $0, 4(%rsp)
leaq 16(%rsp), %rdi
callq hipEventCreate
leaq 8(%rsp), %rdi
callq hipEventCreate
movq 16(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movabsq $68719476752, %rdx # imm = 0x1000000010
movq %r12, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB7_2
# %bb.1:
movq 24(%rsp), %rax
movq 40(%rsp), %rcx
movq 32(%rsp), %rdx
movq %rax, 152(%rsp)
movq %rcx, 144(%rsp)
movq %rdx, 136(%rsp)
movl %r13d, 60(%rsp)
movl %ebx, 56(%rsp)
leaq 152(%rsp), %rax
movq %rax, 160(%rsp)
leaq 144(%rsp), %rax
movq %rax, 168(%rsp)
leaq 136(%rsp), %rax
movq %rax, 176(%rsp)
leaq 60(%rsp), %rax
movq %rax, 184(%rsp)
leaq 56(%rsp), %rax
movq %rax, 192(%rsp)
leaq 120(%rsp), %rdi
leaq 104(%rsp), %rsi
leaq 96(%rsp), %rdx
leaq 88(%rsp), %rcx
callq __hipPopCallConfiguration
movq 120(%rsp), %rsi
movl 128(%rsp), %edx
movq 104(%rsp), %rcx
movl 112(%rsp), %r8d
leaq 160(%rsp), %r9
movl $_Z19matrixMulGPUKernal0PfPKfS1_ii, %edi
pushq 88(%rsp)
.cfi_adjust_cfa_offset 8
pushq 104(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB7_2:
movq 8(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 16(%rsp), %rdi
callq hipEventSynchronize
movq 8(%rsp), %rdi
callq hipEventSynchronize
movq 16(%rsp), %rsi
movq 8(%rsp), %rdx
leaq 4(%rsp), %rdi
callq hipEventElapsedTime
movq 16(%rsp), %rdi
callq hipEventDestroy
movq 8(%rsp), %rdi
callq hipEventDestroy
movss 4(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.17, %edi
movb $1, %al
callq printf
cvtsi2sd %r13d, %xmm1
movapd %xmm1, %xmm0
addsd %xmm1, %xmm0
mulsd %xmm1, %xmm0
mulsd %xmm1, %xmm0
mulsd .LCPI7_0(%rip), %xmm0
movss 4(%rsp), %xmm1 # xmm1 = mem[0],zero,zero,zero
cvtss2sd %xmm1, %xmm1
divsd %xmm1, %xmm0
movl $.L.str.18, %edi
movb $1, %al
callq printf
callq hipDeviceSynchronize
movq 24(%rsp), %rsi
movl 52(%rsp), %eax # 4-byte Reload
imull %ebx, %eax
movslq %eax, %rdx
shlq $2, %rdx
movq 80(%rsp), %rdi # 8-byte Reload
movl $2, %ecx
callq hipMemcpy
movq 40(%rsp), %rdi
callq hipFree
movq 32(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
addq $200, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end7:
.size _Z12matrixMulGPUPfPKfS1_iii, .Lfunc_end7-_Z12matrixMulGPUPfPKfS1_iii
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z10randomInitPfi
.LCPI8_0:
.long 0x30000000 # float 4.65661287E-10
.text
.globl _Z10randomInitPfi
.p2align 4, 0x90
.type _Z10randomInitPfi,@function
_Z10randomInitPfi: # @_Z10randomInitPfi
.cfi_startproc
# %bb.0:
testl %esi, %esi
jle .LBB8_4
# %bb.1: # %.lr.ph.preheader
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdi, %rbx
movl %esi, %r14d
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB8_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
callq rand
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
mulss .LCPI8_0(%rip), %xmm0
movss %xmm0, (%rbx,%r15,4)
incq %r15
cmpq %r15, %r14
jne .LBB8_2
# %bb.3:
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r14
.cfi_restore %r15
.LBB8_4: # %._crit_edge
retq
.Lfunc_end8:
.size _Z10randomInitPfi, .Lfunc_end8-_Z10randomInitPfi
.cfi_endproc
# -- End function
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function _Z10checkErrorPKfS0_i
.LCPI9_0:
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0
.LCPI9_1:
.quad 0x3f50624dd2f1a9fc # double 0.001
.text
.globl _Z10checkErrorPKfS0_i
.p2align 4, 0x90
.type _Z10checkErrorPKfS0_i,@function
_Z10checkErrorPKfS0_i: # @_Z10checkErrorPKfS0_i
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
pushq %rax
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
testl %edx, %edx
setle %bpl
jle .LBB9_9
# %bb.1: # %.lr.ph.preheader
movq %rsi, %rbx
movq %rdi, %r14
movss (%rdi), %xmm0 # xmm0 = mem[0],zero,zero,zero
subss (%rsi), %xmm0
andps .LCPI9_0(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
ucomisd .LCPI9_1(%rip), %xmm0
jbe .LBB9_6
# %bb.2:
xorl %r15d, %r15d
jmp .LBB9_5
.LBB9_6: # %.lr.ph31.preheader
movl %edx, %eax
movl $1, %r15d
movaps .LCPI9_0(%rip), %xmm0 # xmm0 = [NaN,NaN,NaN,NaN]
movsd .LCPI9_1(%rip), %xmm1 # xmm1 = mem[0],zero
.p2align 4, 0x90
.LBB9_7: # %.lr.ph31
# =>This Inner Loop Header: Depth=1
cmpq %r15, %rax
je .LBB9_8
# %bb.3: # %.lr.ph
# in Loop: Header=BB9_7 Depth=1
movss (%r14,%r15,4), %xmm2 # xmm2 = mem[0],zero,zero,zero
subss (%rbx,%r15,4), %xmm2
andps %xmm0, %xmm2
cvtss2sd %xmm2, %xmm2
incq %r15
ucomisd %xmm1, %xmm2
jbe .LBB9_7
# %bb.4: # %.lr.ph._crit_edge.loopexit
decq %r15
cmpq %rax, %r15
setae %bpl
.LBB9_5: # %.lr.ph._crit_edge
movl $.L.str.19, %edi
movl %r15d, %esi
xorl %eax, %eax
callq printf
movss (%r14,%r15,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movss (%rbx,%r15,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
cvtss2sd %xmm1, %xmm1
movl $.L.str.20, %edi
movb $2, %al
callq printf
jmp .LBB9_9
.LBB9_8: # %.loopexit.loopexit
setbe %bpl
.LBB9_9: # %.loopexit
movl %ebp, %eax
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end9:
.size _Z10checkErrorPKfS0_i, .Lfunc_end9-_Z10checkErrorPKfS0_i
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI10_0:
.long 0x30000000 # float 4.65661287E-10
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0
.LCPI10_1:
.quad 0x412e848000000000 # double 1.0E+6
.LCPI10_3:
.quad 0x3f50624dd2f1a9fc # double 0.001
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0
.LCPI10_2:
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
pushq %rax
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
callq _Z8InitCUDAv
testb %al, %al
je .LBB10_20
# %bb.1:
movl $63, %edi
callq srand
xorl %r15d, %r15d
movl $.L.str.21, %edi
movl $16, %esi
xorl %eax, %eax
callq printf
movl $.L.str.22, %edi
movl $2048, %esi # imm = 0x800
movl $2048, %edx # imm = 0x800
xorl %eax, %eax
callq printf
movl $16777216, %edi # imm = 0x1000000
callq malloc
movq %rax, %rbx
movl $16777216, %edi # imm = 0x1000000
callq malloc
movq %rax, %r14
.p2align 4, 0x90
.LBB10_2: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
callq rand
movss .LCPI10_0(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
mulss %xmm1, %xmm0
movss %xmm0, (%rbx,%r15,4)
incq %r15
cmpq $4194304, %r15 # imm = 0x400000
jne .LBB10_2
# %bb.3: # %.lr.ph.i45.preheader
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB10_4: # %.lr.ph.i45
# =>This Inner Loop Header: Depth=1
callq rand
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
mulss .LCPI10_0(%rip), %xmm0
movss %xmm0, (%r14,%r15,4)
incq %r15
cmpq $4194304, %r15 # imm = 0x400000
jne .LBB10_4
# %bb.5: # %_Z10randomInitPfi.exit49
movl $16777216, %edi # imm = 0x1000000
callq malloc
movq %rax, %r15
xorl %ebp, %ebp
movl $16777216, %edx # imm = 0x1000000
movq %rax, %rdi
xorl %esi, %esi
callq memset@PLT
movl $16777216, %edi # imm = 0x1000000
callq malloc
movq %rax, %r12
movl $16777216, %edx # imm = 0x1000000
movq %rax, %rdi
xorl %esi, %esi
callq memset@PLT
callq clock
movq %rax, %r13
movq %rbx, %rax
.p2align 4, 0x90
.LBB10_6: # %.preheader27.i
# =>This Loop Header: Depth=1
# Child Loop BB10_7 Depth 2
# Child Loop BB10_8 Depth 3
movq %rbp, %rcx
shlq $13, %rcx
addq %r12, %rcx
movq %r14, %rdx
xorl %esi, %esi
.p2align 4, 0x90
.LBB10_7: # %.preheader.i
# Parent Loop BB10_6 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB10_8 Depth 3
xorps %xmm0, %xmm0
movq %rdx, %rdi
xorl %r8d, %r8d
.p2align 4, 0x90
.LBB10_8: # %.lr.ph.i50
# Parent Loop BB10_6 Depth=1
# Parent Loop BB10_7 Depth=2
# => This Inner Loop Header: Depth=3
movss (%rax,%r8,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
mulss (%rdi), %xmm1
addss %xmm1, %xmm0
incq %r8
addq $8192, %rdi # imm = 0x2000
cmpq $2048, %r8 # imm = 0x800
jne .LBB10_8
# %bb.9: # %._crit_edge.i
# in Loop: Header=BB10_7 Depth=2
movss %xmm0, (%rcx,%rsi,4)
incq %rsi
addq $4, %rdx
cmpq $2048, %rsi # imm = 0x800
jne .LBB10_7
# %bb.10: # %._crit_edge31.i
# in Loop: Header=BB10_6 Depth=1
incq %rbp
addq $8192, %rax # imm = 0x2000
cmpq $2048, %rbp # imm = 0x800
jne .LBB10_6
# %bb.11: # %_Z12matrixMulCPUPfPKfS1_iii.exit
callq clock
subq %r13, %rax
xorps %xmm0, %xmm0
cvtsi2sd %rax, %xmm0
divsd .LCPI10_1(%rip), %xmm0
movl $.L.str.23, %edi
movb $1, %al
callq printf
movq %r15, %rdi
movq %rbx, %rsi
movq %r14, %rdx
movl $2048, %ecx # imm = 0x800
movl $2048, %r8d # imm = 0x800
movl $2048, %r9d # imm = 0x800
callq _Z12matrixMulGPUPfPKfS1_iii
movss (%r15), %xmm0 # xmm0 = mem[0],zero,zero,zero
movss (%r12), %xmm1 # xmm1 = mem[0],zero,zero,zero
subss %xmm1, %xmm0
andps .LCPI10_2(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
ucomisd .LCPI10_3(%rip), %xmm0
jbe .LBB10_16
# %bb.12:
movss %xmm1, 4(%rsp) # 4-byte Spill
xorl %r13d, %r13d
xorl %ebp, %ebp
jmp .LBB10_15
.LBB10_16: # %.lr.ph.preheader
xorl %r13d, %r13d
movaps .LCPI10_2(%rip), %xmm0 # xmm0 = [NaN,NaN,NaN,NaN]
movsd .LCPI10_3(%rip), %xmm1 # xmm1 = mem[0],zero
.p2align 4, 0x90
.LBB10_17: # %.lr.ph
# =>This Inner Loop Header: Depth=1
cmpq $4194303, %r13 # imm = 0x3FFFFF
je .LBB10_18
# %bb.13: # %.lr.ph.i54
# in Loop: Header=BB10_17 Depth=1
movss 4(%r15,%r13,4), %xmm2 # xmm2 = mem[0],zero,zero,zero
movss 4(%r12,%r13,4), %xmm3 # xmm3 = mem[0],zero,zero,zero
subss %xmm3, %xmm2
andps %xmm0, %xmm2
cvtss2sd %xmm2, %xmm2
incq %r13
ucomisd %xmm1, %xmm2
jbe .LBB10_17
# %bb.14: # %.lr.ph.i54._crit_edge.loopexit
movss %xmm3, 4(%rsp) # 4-byte Spill
leaq -1(%r13), %rax
cmpq $4194303, %rax # imm = 0x3FFFFF
setae %bpl
.LBB10_15: # %.lr.ph.i54._crit_edge
movl $.L.str.19, %edi
movl %r13d, %esi
xorl %eax, %eax
callq printf
movss (%r15,%r13,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movss 4(%rsp), %xmm1 # 4-byte Reload
# xmm1 = mem[0],zero,zero,zero
cvtss2sd %xmm1, %xmm1
movl $.L.str.20, %edi
movb $2, %al
callq printf
jmp .LBB10_19
.LBB10_18: # %_Z10checkErrorPKfS0_i.exit.loopexit
setae %bpl
.LBB10_19: # %_Z10checkErrorPKfS0_i.exit
movl $.Lstr.1, %eax
movl $.Lstr, %edi
testb %bpl, %bpl
cmovneq %rax, %rdi
callq puts@PLT
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
movq %r12, %rdi
callq free
.LBB10_20:
xorl %eax, %eax
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end10:
.size main, .Lfunc_end10-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB11_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB11_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z19matrixMulGPUKernal0PfPKfS1_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z19matrixMulGPUKernal1PfPKfS1_ii, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end11:
.size __hip_module_ctor, .Lfunc_end11-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB12_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB12_2:
retq
.Lfunc_end12:
.size __hip_module_dtor, .Lfunc_end12-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Device Name : %s.\n"
.size .L.str, 19
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "totalGlobalMem : %lu.\n"
.size .L.str.1, 23
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "sharedMemPerBlock : %lu.\n"
.size .L.str.2, 26
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "regsPerBlock : %d.\n"
.size .L.str.3, 20
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "warpSize : %d.\n"
.size .L.str.4, 16
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "memPitch : %lu.\n"
.size .L.str.5, 17
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "maxThreadsPerBlock : %d.\n"
.size .L.str.6, 26
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "maxThreadsDim[0 - 2] : %d %d %d.\n"
.size .L.str.7, 34
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "maxGridSize[0 - 2] : %d %d %d.\n"
.size .L.str.8, 32
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "totalConstMem : %lu.\n"
.size .L.str.9, 22
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "major.minor : %d.%d.\n"
.size .L.str.10, 22
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz "clockRate : %d.\n"
.size .L.str.11, 17
.type .L.str.12,@object # @.str.12
.L.str.12:
.asciz "textureAlignment : %lu.\n"
.size .L.str.12, 25
.type .L.str.13,@object # @.str.13
.L.str.13:
.asciz "deviceOverlap : %d.\n"
.size .L.str.13, 21
.type .L.str.14,@object # @.str.14
.L.str.14:
.asciz "multiProcessorCount : %d.\n"
.size .L.str.14, 27
.type .L.str.15,@object # @.str.15
.L.str.15:
.asciz "There is no device.\n"
.size .L.str.15, 21
.type .L.str.16,@object # @.str.16
.L.str.16:
.asciz "There is no device supporting CUDA 1.x.\n"
.size .L.str.16, 41
.type _Z19matrixMulGPUKernal0PfPKfS1_ii,@object # @_Z19matrixMulGPUKernal0PfPKfS1_ii
.section .rodata,"a",@progbits
.globl _Z19matrixMulGPUKernal0PfPKfS1_ii
.p2align 3, 0x0
_Z19matrixMulGPUKernal0PfPKfS1_ii:
.quad _Z34__device_stub__matrixMulGPUKernal0PfPKfS1_ii
.size _Z19matrixMulGPUKernal0PfPKfS1_ii, 8
.type _Z19matrixMulGPUKernal1PfPKfS1_ii,@object # @_Z19matrixMulGPUKernal1PfPKfS1_ii
.globl _Z19matrixMulGPUKernal1PfPKfS1_ii
.p2align 3, 0x0
_Z19matrixMulGPUKernal1PfPKfS1_ii:
.quad _Z34__device_stub__matrixMulGPUKernal1PfPKfS1_ii
.size _Z19matrixMulGPUKernal1PfPKfS1_ii, 8
.type .L.str.17,@object # @.str.17
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.17:
.asciz " - Running time: %f ms\n"
.size .L.str.17, 24
.type .L.str.18,@object # @.str.18
.L.str.18:
.asciz " - GFlop: %.5f GFlop/sec\n\n"
.size .L.str.18, 27
.type .L.str.19,@object # @.str.19
.L.str.19:
.asciz " ! Wrong index: %d\n"
.size .L.str.19, 20
.type .L.str.20,@object # @.str.20
.L.str.20:
.asciz "%f \t %f\n"
.size .L.str.20, 9
.type .L.str.21,@object # @.str.21
.L.str.21:
.asciz "\n - BLOCK_SIZE: %d\n"
.size .L.str.21, 20
.type .L.str.22,@object # @.str.22
.L.str.22:
.asciz " - Matrix size: %d * %d\n"
.size .L.str.22, 25
.type .L.str.23,@object # @.str.23
.L.str.23:
.asciz " - CPU use Time : %f ms\n"
.size .L.str.23, 25
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z19matrixMulGPUKernal0PfPKfS1_ii"
.size .L__unnamed_1, 34
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z19matrixMulGPUKernal1PfPKfS1_ii"
.size .L__unnamed_2, 34
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Worng Answer!"
.size .Lstr, 14
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "Right Answer!"
.size .Lstr.1, 14
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z34__device_stub__matrixMulGPUKernal0PfPKfS1_ii
.addrsig_sym _Z34__device_stub__matrixMulGPUKernal1PfPKfS1_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z19matrixMulGPUKernal0PfPKfS1_ii
.addrsig_sym _Z19matrixMulGPUKernal1PfPKfS1_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
#define DOUBLE
#ifdef DOUBLE
#define Complex cufftDoubleComplex
#define Real double
#define Transform CUFFT_Z2Z
#define TransformExec cufftExecZ2Z
#else
#define Complex cufftComplex
#define Real float
#define Transform CUFFT_C2C
#define TransformExec cufftExecC2C
#endif
#define TILE_DIM 8
// synchronize blocks
__global__ void spread_y_r(Real* src, Real* dst)
{
unsigned int tid = (blockIdx.y * gridDim.x + blockIdx.x) * blockDim.x + threadIdx.x;
unsigned int tid1 = (blockIdx.y * gridDim.x * 2 + blockIdx.x) * blockDim.x + threadIdx.x;
Real res = src[tid];
dst[tid1 + blockDim.x*gridDim.x] = res;
#ifdef DOUBLE
dst[tid1] = 0.;
#else
dst[tid1] = 0.f;
#endif
} | code for sm_80
Function : _Z10spread_y_rPdS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R5, SR_CTAID.Y ; /* 0x0000000000057919 */
/* 0x000e220000002600 */
/*0020*/ HFMA2.MMA R9, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff097435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0050*/ S2R R7, SR_TID.X ; /* 0x0000000000077919 */
/* 0x000e620000002100 */
/*0060*/ IMAD R0, R5, c[0x0][0xc], R0 ; /* 0x0000030005007a24 */
/* 0x001fc800078e0200 */
/*0070*/ IMAD R2, R0, c[0x0][0x0], R7 ; /* 0x0000000000027a24 */
/* 0x002fc800078e0207 */
/*0080*/ IMAD.WIDE.U32 R2, R2, R9, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fcc00078e0009 */
/*0090*/ LDG.E.64 R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1b00 */
/*00a0*/ IMAD R0, R5, c[0x0][0xc], R0 ; /* 0x0000030005007a24 */
/* 0x000fe200078e0200 */
/*00b0*/ MOV R5, c[0x0][0x0] ; /* 0x0000000000057a02 */
/* 0x000fc60000000f00 */
/*00c0*/ IMAD R0, R0, c[0x0][0x0], R7 ; /* 0x0000000000007a24 */
/* 0x000fc800078e0207 */
/*00d0*/ IMAD R4, R5, c[0x0][0xc], R0 ; /* 0x0000030005047a24 */
/* 0x000fe400078e0200 */
/*00e0*/ IMAD.WIDE.U32 R6, R0, R9, c[0x0][0x168] ; /* 0x00005a0000067625 */
/* 0x000fc800078e0009 */
/*00f0*/ IMAD.WIDE.U32 R4, R4, R9, c[0x0][0x168] ; /* 0x00005a0004047625 */
/* 0x000fca00078e0009 */
/*0100*/ STG.E.64 [R4.64], R2 ; /* 0x0000000204007986 */
/* 0x004fe8000c101b04 */
/*0110*/ STG.E.64 [R6.64], RZ ; /* 0x000000ff06007986 */
/* 0x000fe2000c101b04 */
/*0120*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0130*/ BRA 0x130; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
#define DOUBLE
#ifdef DOUBLE
#define Complex cufftDoubleComplex
#define Real double
#define Transform CUFFT_Z2Z
#define TransformExec cufftExecZ2Z
#else
#define Complex cufftComplex
#define Real float
#define Transform CUFFT_C2C
#define TransformExec cufftExecC2C
#endif
#define TILE_DIM 8
// synchronize blocks
__global__ void spread_y_r(Real* src, Real* dst)
{
unsigned int tid = (blockIdx.y * gridDim.x + blockIdx.x) * blockDim.x + threadIdx.x;
unsigned int tid1 = (blockIdx.y * gridDim.x * 2 + blockIdx.x) * blockDim.x + threadIdx.x;
Real res = src[tid];
dst[tid1 + blockDim.x*gridDim.x] = res;
#ifdef DOUBLE
dst[tid1] = 0.;
#else
dst[tid1] = 0.f;
#endif
} | .file "tmpxft_0013d975_00000000-6_spread_y_r.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z32__device_stub__Z10spread_y_rPdS_PdS_
.type _Z32__device_stub__Z10spread_y_rPdS_PdS_, @function
_Z32__device_stub__Z10spread_y_rPdS_PdS_:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z10spread_y_rPdS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z32__device_stub__Z10spread_y_rPdS_PdS_, .-_Z32__device_stub__Z10spread_y_rPdS_PdS_
.globl _Z10spread_y_rPdS_
.type _Z10spread_y_rPdS_, @function
_Z10spread_y_rPdS_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z10spread_y_rPdS_PdS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z10spread_y_rPdS_, .-_Z10spread_y_rPdS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z10spread_y_rPdS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z10spread_y_rPdS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
#define DOUBLE
#ifdef DOUBLE
#define Complex cufftDoubleComplex
#define Real double
#define Transform CUFFT_Z2Z
#define TransformExec cufftExecZ2Z
#else
#define Complex cufftComplex
#define Real float
#define Transform CUFFT_C2C
#define TransformExec cufftExecC2C
#endif
#define TILE_DIM 8
// synchronize blocks
__global__ void spread_y_r(Real* src, Real* dst)
{
unsigned int tid = (blockIdx.y * gridDim.x + blockIdx.x) * blockDim.x + threadIdx.x;
unsigned int tid1 = (blockIdx.y * gridDim.x * 2 + blockIdx.x) * blockDim.x + threadIdx.x;
Real res = src[tid];
dst[tid1 + blockDim.x*gridDim.x] = res;
#ifdef DOUBLE
dst[tid1] = 0.;
#else
dst[tid1] = 0.f;
#endif
} | #include <hip/hip_runtime.h>
#include "includes.h"
#define DOUBLE
#ifdef DOUBLE
#define Complex hipfftDoubleComplex
#define Real double
#define Transform HIPFFT_Z2Z
#define TransformExec hipfftExecZ2Z
#else
#define Complex hipfftComplex
#define Real float
#define Transform HIPFFT_C2C
#define TransformExec hipfftExecC2C
#endif
#define TILE_DIM 8
// synchronize blocks
__global__ void spread_y_r(Real* src, Real* dst)
{
unsigned int tid = (blockIdx.y * gridDim.x + blockIdx.x) * blockDim.x + threadIdx.x;
unsigned int tid1 = (blockIdx.y * gridDim.x * 2 + blockIdx.x) * blockDim.x + threadIdx.x;
Real res = src[tid];
dst[tid1 + blockDim.x*gridDim.x] = res;
#ifdef DOUBLE
dst[tid1] = 0.;
#else
dst[tid1] = 0.f;
#endif
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
#define DOUBLE
#ifdef DOUBLE
#define Complex hipfftDoubleComplex
#define Real double
#define Transform HIPFFT_Z2Z
#define TransformExec hipfftExecZ2Z
#else
#define Complex hipfftComplex
#define Real float
#define Transform HIPFFT_C2C
#define TransformExec hipfftExecC2C
#endif
#define TILE_DIM 8
// synchronize blocks
__global__ void spread_y_r(Real* src, Real* dst)
{
unsigned int tid = (blockIdx.y * gridDim.x + blockIdx.x) * blockDim.x + threadIdx.x;
unsigned int tid1 = (blockIdx.y * gridDim.x * 2 + blockIdx.x) * blockDim.x + threadIdx.x;
Real res = src[tid];
dst[tid1 + blockDim.x*gridDim.x] = res;
#ifdef DOUBLE
dst[tid1] = 0.;
#else
dst[tid1] = 0.f;
#endif
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10spread_y_rPdS_
.globl _Z10spread_y_rPdS_
.p2align 8
.type _Z10spread_y_rPdS_,@function
_Z10spread_y_rPdS_:
s_clause 0x2
s_load_b32 s4, s[0:1], 0x10
s_load_b32 s5, s[0:1], 0x1c
s_load_b128 s[0:3], s[0:1], 0x0
v_mov_b32_e32 v7, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
v_mov_b32_e32 v8, v7
s_waitcnt lgkmcnt(0)
s_mul_i32 s6, s4, s15
s_and_b32 s5, s5, 0xffff
s_add_i32 s7, s6, s14
v_mad_u64_u32 v[1:2], null, s7, s5, v[0:1]
v_mov_b32_e32 v2, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 3, v[1:2]
v_add_co_u32 v3, vcc_lo, s0, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
s_lshl_b32 s0, s6, 1
s_add_i32 s0, s0, s14
global_load_b64 v[3:4], v[3:4], off
v_mad_u64_u32 v[5:6], null, s0, s5, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[0:1], null, s4, s5, v[5:6]
v_mov_b32_e32 v1, v2
v_mov_b32_e32 v6, v2
v_lshlrev_b64 v[0:1], 3, v[0:1]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[5:6], 3, v[5:6]
v_add_co_u32 v0, vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
v_add_co_u32 v5, vcc_lo, s2, v5
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v6, vcc_lo, s3, v6, vcc_lo
s_waitcnt vmcnt(0)
s_clause 0x1
global_store_b64 v[0:1], v[3:4], off
global_store_b64 v[5:6], v[7:8], off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10spread_y_rPdS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10spread_y_rPdS_, .Lfunc_end0-_Z10spread_y_rPdS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10spread_y_rPdS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z10spread_y_rPdS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
#define DOUBLE
#ifdef DOUBLE
#define Complex hipfftDoubleComplex
#define Real double
#define Transform HIPFFT_Z2Z
#define TransformExec hipfftExecZ2Z
#else
#define Complex hipfftComplex
#define Real float
#define Transform HIPFFT_C2C
#define TransformExec hipfftExecC2C
#endif
#define TILE_DIM 8
// synchronize blocks
__global__ void spread_y_r(Real* src, Real* dst)
{
unsigned int tid = (blockIdx.y * gridDim.x + blockIdx.x) * blockDim.x + threadIdx.x;
unsigned int tid1 = (blockIdx.y * gridDim.x * 2 + blockIdx.x) * blockDim.x + threadIdx.x;
Real res = src[tid];
dst[tid1 + blockDim.x*gridDim.x] = res;
#ifdef DOUBLE
dst[tid1] = 0.;
#else
dst[tid1] = 0.f;
#endif
} | .text
.file "spread_y_r.hip"
.globl _Z25__device_stub__spread_y_rPdS_ # -- Begin function _Z25__device_stub__spread_y_rPdS_
.p2align 4, 0x90
.type _Z25__device_stub__spread_y_rPdS_,@function
_Z25__device_stub__spread_y_rPdS_: # @_Z25__device_stub__spread_y_rPdS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z10spread_y_rPdS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z25__device_stub__spread_y_rPdS_, .Lfunc_end0-_Z25__device_stub__spread_y_rPdS_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10spread_y_rPdS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10spread_y_rPdS_,@object # @_Z10spread_y_rPdS_
.section .rodata,"a",@progbits
.globl _Z10spread_y_rPdS_
.p2align 3, 0x0
_Z10spread_y_rPdS_:
.quad _Z25__device_stub__spread_y_rPdS_
.size _Z10spread_y_rPdS_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z10spread_y_rPdS_"
.size .L__unnamed_1, 19
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__spread_y_rPdS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10spread_y_rPdS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z10spread_y_rPdS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R5, SR_CTAID.Y ; /* 0x0000000000057919 */
/* 0x000e220000002600 */
/*0020*/ HFMA2.MMA R9, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff097435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0050*/ S2R R7, SR_TID.X ; /* 0x0000000000077919 */
/* 0x000e620000002100 */
/*0060*/ IMAD R0, R5, c[0x0][0xc], R0 ; /* 0x0000030005007a24 */
/* 0x001fc800078e0200 */
/*0070*/ IMAD R2, R0, c[0x0][0x0], R7 ; /* 0x0000000000027a24 */
/* 0x002fc800078e0207 */
/*0080*/ IMAD.WIDE.U32 R2, R2, R9, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fcc00078e0009 */
/*0090*/ LDG.E.64 R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1b00 */
/*00a0*/ IMAD R0, R5, c[0x0][0xc], R0 ; /* 0x0000030005007a24 */
/* 0x000fe200078e0200 */
/*00b0*/ MOV R5, c[0x0][0x0] ; /* 0x0000000000057a02 */
/* 0x000fc60000000f00 */
/*00c0*/ IMAD R0, R0, c[0x0][0x0], R7 ; /* 0x0000000000007a24 */
/* 0x000fc800078e0207 */
/*00d0*/ IMAD R4, R5, c[0x0][0xc], R0 ; /* 0x0000030005047a24 */
/* 0x000fe400078e0200 */
/*00e0*/ IMAD.WIDE.U32 R6, R0, R9, c[0x0][0x168] ; /* 0x00005a0000067625 */
/* 0x000fc800078e0009 */
/*00f0*/ IMAD.WIDE.U32 R4, R4, R9, c[0x0][0x168] ; /* 0x00005a0004047625 */
/* 0x000fca00078e0009 */
/*0100*/ STG.E.64 [R4.64], R2 ; /* 0x0000000204007986 */
/* 0x004fe8000c101b04 */
/*0110*/ STG.E.64 [R6.64], RZ ; /* 0x000000ff06007986 */
/* 0x000fe2000c101b04 */
/*0120*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0130*/ BRA 0x130; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10spread_y_rPdS_
.globl _Z10spread_y_rPdS_
.p2align 8
.type _Z10spread_y_rPdS_,@function
_Z10spread_y_rPdS_:
s_clause 0x2
s_load_b32 s4, s[0:1], 0x10
s_load_b32 s5, s[0:1], 0x1c
s_load_b128 s[0:3], s[0:1], 0x0
v_mov_b32_e32 v7, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
v_mov_b32_e32 v8, v7
s_waitcnt lgkmcnt(0)
s_mul_i32 s6, s4, s15
s_and_b32 s5, s5, 0xffff
s_add_i32 s7, s6, s14
v_mad_u64_u32 v[1:2], null, s7, s5, v[0:1]
v_mov_b32_e32 v2, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 3, v[1:2]
v_add_co_u32 v3, vcc_lo, s0, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
s_lshl_b32 s0, s6, 1
s_add_i32 s0, s0, s14
global_load_b64 v[3:4], v[3:4], off
v_mad_u64_u32 v[5:6], null, s0, s5, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[0:1], null, s4, s5, v[5:6]
v_mov_b32_e32 v1, v2
v_mov_b32_e32 v6, v2
v_lshlrev_b64 v[0:1], 3, v[0:1]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[5:6], 3, v[5:6]
v_add_co_u32 v0, vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
v_add_co_u32 v5, vcc_lo, s2, v5
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v6, vcc_lo, s3, v6, vcc_lo
s_waitcnt vmcnt(0)
s_clause 0x1
global_store_b64 v[0:1], v[3:4], off
global_store_b64 v[5:6], v[7:8], off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10spread_y_rPdS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10spread_y_rPdS_, .Lfunc_end0-_Z10spread_y_rPdS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10spread_y_rPdS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z10spread_y_rPdS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0013d975_00000000-6_spread_y_r.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z32__device_stub__Z10spread_y_rPdS_PdS_
.type _Z32__device_stub__Z10spread_y_rPdS_PdS_, @function
_Z32__device_stub__Z10spread_y_rPdS_PdS_:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z10spread_y_rPdS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z32__device_stub__Z10spread_y_rPdS_PdS_, .-_Z32__device_stub__Z10spread_y_rPdS_PdS_
.globl _Z10spread_y_rPdS_
.type _Z10spread_y_rPdS_, @function
_Z10spread_y_rPdS_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z10spread_y_rPdS_PdS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z10spread_y_rPdS_, .-_Z10spread_y_rPdS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z10spread_y_rPdS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z10spread_y_rPdS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "spread_y_r.hip"
.globl _Z25__device_stub__spread_y_rPdS_ # -- Begin function _Z25__device_stub__spread_y_rPdS_
.p2align 4, 0x90
.type _Z25__device_stub__spread_y_rPdS_,@function
_Z25__device_stub__spread_y_rPdS_: # @_Z25__device_stub__spread_y_rPdS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z10spread_y_rPdS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z25__device_stub__spread_y_rPdS_, .Lfunc_end0-_Z25__device_stub__spread_y_rPdS_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10spread_y_rPdS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10spread_y_rPdS_,@object # @_Z10spread_y_rPdS_
.section .rodata,"a",@progbits
.globl _Z10spread_y_rPdS_
.p2align 3, 0x0
_Z10spread_y_rPdS_:
.quad _Z25__device_stub__spread_y_rPdS_
.size _Z10spread_y_rPdS_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z10spread_y_rPdS_"
.size .L__unnamed_1, 19
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__spread_y_rPdS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10spread_y_rPdS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /*
* PROJECT: Pairwise sequence alignments on GPU
* FILE: psa_swgotoh_registers_32b_gpu
* AUTHOR(S): Alejandro Chacon <alejandro.chacon@uab.es>
* Jacopo Pantaleoni <jpantaleoni@nvidia.com>
* DESCRIPTION: Device functions for the SW-Gotoh GPU implementation:
* Using a 16 bits of representation per cell and intermediate column.
*/
extern "C" {
#include "../../../include/psa_pairwise_gpu.h"
}
#include <cuda_runtime.h>
#include <cuda.h>
#define MATCH_SCORE 2
#define MISMATCH_SCORE -5
#define OPEN_INDEL_SCORE -2
#define EXTEND_INDEL_SCORE -1
#define V4_PACKET1(NUM_A,NUM_B,NUM_C,NUM_D) ((NUM_A << 24) | (NUM_B << 16) | (NUM_C << 8) | NUM_D)
#define V4_PACKET4(NUM) ((NUM << 24) | (NUM << 16) | (NUM << 8) | NUM)
#ifndef QUERIES_SIZE
#define QUERIES_SIZE 100
#endif
#ifndef CANDIDATES_SIZE
#define CANDIDATES_SIZE 120
#endif
#define MAX3(a,b,c) (MAX(MAX(a, b), c))
#define WARP_SIZE 32
#define MAX_THREADS_PER_SM 128
#define CUDA_NUM_THREADS 128
#define THREADS_PER_SEGMENT 32
#define NUM_SW_PER_BLOCK (MAX_THREADS_PER_SM / THREADS_PER_SEGMENT)
#define NUM_WARPS (MAX_THREADS_PER_SM / WARP_SIZE)
#define BAND_LEN 8
#define MAX_QUERY_SIZE 200
inline __device__
int32_t max3(const int32_t op1, const int32_t op2, const int32_t op3)
{
uint32_t r;
asm( " vmax.s32.s32.s32.max %0, %1, %2, %3;" : "=r"(r) : "r"(op1), "r"(op2), "r"(op3) );
return r;
}
inline __device__
void update_band(int32_t idRow, char q_i, char *ref_cache, int32_t *H_band, int32_t *F_band,
int2 *temp, int32_t *H_maxScore)
{
int32_t H_diag = H_band[0];
H_band[0] = temp[idRow].x;
int32_t E = temp[idRow].y;
#pragma unroll
for (uint32_t j = 1; j <= BAND_LEN; ++j)
{
// update F
const int32_t ftop = F_band[j] + EXTEND_INDEL_SCORE;
const int32_t htop = H_band[j] + OPEN_INDEL_SCORE;
F_band[j] = MAX(ftop, htop);
// update E
const int32_t eleft = E + EXTEND_INDEL_SCORE;
const int32_t hleft = H_band[j-1] + OPEN_INDEL_SCORE;
E = MAX(eleft, hleft);
const int32_t r_j = ref_cache[j-1];
const int32_t W_ij = (r_j == q_i) ? MATCH_SCORE : MISMATCH_SCORE;
const int32_t diagonal = H_diag + W_ij;
const int32_t top = F_band[j];
const int32_t left = E;
int32_t hi = MAX3(left, top, diagonal);
hi = MAX(hi, 0);
H_diag = H_band[j];
H_band[j] = hi;
(*H_maxScore) = MAX((*H_maxScore), hi);
}
// save the last entry of the band
temp[idRow] = make_int2(H_band[BAND_LEN], E);
//(* H_maxScore) = MAX((* H_maxScore), H_band[BAND_LEN]);
}
__global__
void localProcessSWTiling(ASCIIEntry_t *d_CandidatesASCII, uint32_t *d_CandidatesASCIIposition,
ASCIIEntry_t *d_QueriesASCII, uint32_t *d_QueriesASCIIposition,
alignmentInfo_t *d_AlignmentsInfo, alignmentEntry_t *d_AlignmentsResults,
uint32_t querySize, uint32_t candidateSize, uint32_t candidatesNum)
{
const uint32_t idCandidate = blockIdx.x * MAX_THREADS_PER_SM + threadIdx.x;
if (idCandidate < candidatesNum)
{
const char* candidate = d_CandidatesASCII + d_CandidatesASCIIposition[idCandidate];
const char* query = d_QueriesASCII + d_QueriesASCIIposition[d_AlignmentsInfo[idCandidate]];
int2 temp[MAX_QUERY_SIZE];
char r_cache[BAND_LEN];
int32_t H_band[BAND_LEN + 1];
int32_t F_band[BAND_LEN + 1];
char q_i;
const int32_t numRows = querySize, numColumns = candidateSize;
int32_t idColumn, idRow, idBand;
int32_t H_maxScore = 0;
for(idBand = 0; idBand < MAX_QUERY_SIZE; ++idBand){
temp[idBand].x = 0;
temp[idBand].y = 0;
}
// Compute Score SW-GOTOH
for(idColumn = 0; idColumn < numColumns; idColumn += BAND_LEN){
// load a block of entries from the reference
#pragma unroll
for (uint32_t idBand = 0; idBand < BAND_LEN; ++idBand)
r_cache[idBand] = candidate[idColumn + idBand];
// initialize the first band
#pragma unroll
for (uint32_t idBand = 0; idBand <= BAND_LEN; ++idBand){
H_band[idBand] = 0;
F_band[idBand] = 0; /* ? */
}
for(idRow = 0; idRow < numRows; ++idRow){
q_i = query[idRow];
update_band(idRow, q_i, r_cache, H_band, F_band, temp, &H_maxScore);
}
}
d_AlignmentsResults[idCandidate].score = H_maxScore;
d_AlignmentsResults[idCandidate].column = 0;
//d_AlignmentsResults[idCandidate].column = maxColumn;
}
}
extern "C"
psaError_t localProcessPairwiseStream(sequences_t *candidates, sequences_t *queries, alignments_t *alignments)
{
uint32_t blocks = DIV_CEIL(candidates->num, CUDA_NUM_THREADS);
uint32_t threads = CUDA_NUM_THREADS;
uint32_t querySize = queries->h_size[0];
uint32_t candidateSize = candidates->h_size[0];
cudaThreadSetCacheConfig(cudaFuncCachePreferL1);
printf("Grid Size: %d, Block Size: %d, Total alignments: %d\n", blocks, threads, candidates->num);
localProcessSWTiling<<<blocks, threads>>>(candidates->d_ASCII, candidates->d_ASCIIposition,
queries->d_ASCII, queries->d_ASCIIposition,
alignments->d_info, alignments->d_results,
querySize, candidateSize, candidates->num);
cudaThreadSynchronize();
return (SUCCESS);
} | .file "tmpxft_000bb055_00000000-6_psa_swgotoh_registers_32b_gpu.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z72__device_stub__Z20localProcessSWTilingPcPjS_S0_S0_P16alignmentEntry_tjjjPcPjS_S0_S0_P16alignmentEntry_tjjj
.type _Z72__device_stub__Z20localProcessSWTilingPcPjS_S0_S0_P16alignmentEntry_tjjjPcPjS_S0_S0_P16alignmentEntry_tjjj, @function
_Z72__device_stub__Z20localProcessSWTilingPcPjS_S0_S0_P16alignmentEntry_tjjjPcPjS_S0_S0_P16alignmentEntry_tjjj:
.LFB2084:
.cfi_startproc
endbr64
subq $200, %rsp
.cfi_def_cfa_offset 208
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movq %r8, 8(%rsp)
movq %r9, (%rsp)
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
movq %rsp, %rax
movq %rax, 152(%rsp)
leaq 208(%rsp), %rax
movq %rax, 160(%rsp)
leaq 216(%rsp), %rax
movq %rax, 168(%rsp)
leaq 224(%rsp), %rax
movq %rax, 176(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 216
pushq 56(%rsp)
.cfi_def_cfa_offset 224
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z20localProcessSWTilingPcPjS_S0_S0_P16alignmentEntry_tjjj(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z72__device_stub__Z20localProcessSWTilingPcPjS_S0_S0_P16alignmentEntry_tjjjPcPjS_S0_S0_P16alignmentEntry_tjjj, .-_Z72__device_stub__Z20localProcessSWTilingPcPjS_S0_S0_P16alignmentEntry_tjjjPcPjS_S0_S0_P16alignmentEntry_tjjj
.globl _Z20localProcessSWTilingPcPjS_S0_S0_P16alignmentEntry_tjjj
.type _Z20localProcessSWTilingPcPjS_S0_S0_P16alignmentEntry_tjjj, @function
_Z20localProcessSWTilingPcPjS_S0_S0_P16alignmentEntry_tjjj:
.LFB2085:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 40
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 48
call _Z72__device_stub__Z20localProcessSWTilingPcPjS_S0_S0_P16alignmentEntry_tjjjPcPjS_S0_S0_P16alignmentEntry_tjjj
addq $40, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z20localProcessSWTilingPcPjS_S0_S0_P16alignmentEntry_tjjj, .-_Z20localProcessSWTilingPcPjS_S0_S0_P16alignmentEntry_tjjj
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "Grid Size: %d, Block Size: %d, Total alignments: %d\n"
.text
.globl localProcessPairwiseStream
.type localProcessPairwiseStream, @function
localProcessPairwiseStream:
.LFB2059:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $40, %rsp
.cfi_def_cfa_offset 96
movq %rdi, %rbp
movq %rsi, %r12
movq %rdx, %r13
movl (%rdi), %eax
leal 127(%rax), %ebx
shrl $7, %ebx
movq 184(%rsi), %rax
movl (%rax), %r14d
movq 184(%rdi), %rax
movl (%rax), %r15d
movl $2, %edi
call cudaThreadSetCacheConfig@PLT
movl 0(%rbp), %r8d
movl $128, %ecx
movl %ebx, %edx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $128, 20(%rsp)
movl $1, 24(%rsp)
movl %ebx, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L12:
call cudaThreadSynchronize@PLT
movl $0, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
movq 176(%r12), %rcx
movq 160(%r12), %rdx
movq 176(%rbp), %rsi
movq 160(%rbp), %rdi
subq $8, %rsp
.cfi_def_cfa_offset 104
movl 0(%rbp), %eax
pushq %rax
.cfi_def_cfa_offset 112
pushq %r15
.cfi_def_cfa_offset 120
pushq %r14
.cfi_def_cfa_offset 128
movq 32(%r13), %r9
movq 16(%r13), %r8
call _Z72__device_stub__Z20localProcessSWTilingPcPjS_S0_S0_P16alignmentEntry_tjjjPcPjS_S0_S0_P16alignmentEntry_tjjj
addq $32, %rsp
.cfi_def_cfa_offset 96
jmp .L12
.cfi_endproc
.LFE2059:
.size localProcessPairwiseStream, .-localProcessPairwiseStream
.section .rodata.str1.8
.align 8
.LC1:
.string "_Z20localProcessSWTilingPcPjS_S0_S0_P16alignmentEntry_tjjj"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z20localProcessSWTilingPcPjS_S0_S0_P16alignmentEntry_tjjj(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /*
* PROJECT: Pairwise sequence alignments on GPU
* FILE: psa_swgotoh_registers_32b_gpu
* AUTHOR(S): Alejandro Chacon <alejandro.chacon@uab.es>
* Jacopo Pantaleoni <jpantaleoni@nvidia.com>
* DESCRIPTION: Device functions for the SW-Gotoh GPU implementation:
* Using a 16 bits of representation per cell and intermediate column.
*/
extern "C" {
#include "../../../include/psa_pairwise_gpu.h"
}
#include <cuda_runtime.h>
#include <cuda.h>
#define MATCH_SCORE 2
#define MISMATCH_SCORE -5
#define OPEN_INDEL_SCORE -2
#define EXTEND_INDEL_SCORE -1
#define V4_PACKET1(NUM_A,NUM_B,NUM_C,NUM_D) ((NUM_A << 24) | (NUM_B << 16) | (NUM_C << 8) | NUM_D)
#define V4_PACKET4(NUM) ((NUM << 24) | (NUM << 16) | (NUM << 8) | NUM)
#ifndef QUERIES_SIZE
#define QUERIES_SIZE 100
#endif
#ifndef CANDIDATES_SIZE
#define CANDIDATES_SIZE 120
#endif
#define MAX3(a,b,c) (MAX(MAX(a, b), c))
#define WARP_SIZE 32
#define MAX_THREADS_PER_SM 128
#define CUDA_NUM_THREADS 128
#define THREADS_PER_SEGMENT 32
#define NUM_SW_PER_BLOCK (MAX_THREADS_PER_SM / THREADS_PER_SEGMENT)
#define NUM_WARPS (MAX_THREADS_PER_SM / WARP_SIZE)
#define BAND_LEN 8
#define MAX_QUERY_SIZE 200
inline __device__
int32_t max3(const int32_t op1, const int32_t op2, const int32_t op3)
{
uint32_t r;
asm( " vmax.s32.s32.s32.max %0, %1, %2, %3;" : "=r"(r) : "r"(op1), "r"(op2), "r"(op3) );
return r;
}
inline __device__
void update_band(int32_t idRow, char q_i, char *ref_cache, int32_t *H_band, int32_t *F_band,
int2 *temp, int32_t *H_maxScore)
{
int32_t H_diag = H_band[0];
H_band[0] = temp[idRow].x;
int32_t E = temp[idRow].y;
#pragma unroll
for (uint32_t j = 1; j <= BAND_LEN; ++j)
{
// update F
const int32_t ftop = F_band[j] + EXTEND_INDEL_SCORE;
const int32_t htop = H_band[j] + OPEN_INDEL_SCORE;
F_band[j] = MAX(ftop, htop);
// update E
const int32_t eleft = E + EXTEND_INDEL_SCORE;
const int32_t hleft = H_band[j-1] + OPEN_INDEL_SCORE;
E = MAX(eleft, hleft);
const int32_t r_j = ref_cache[j-1];
const int32_t W_ij = (r_j == q_i) ? MATCH_SCORE : MISMATCH_SCORE;
const int32_t diagonal = H_diag + W_ij;
const int32_t top = F_band[j];
const int32_t left = E;
int32_t hi = MAX3(left, top, diagonal);
hi = MAX(hi, 0);
H_diag = H_band[j];
H_band[j] = hi;
(*H_maxScore) = MAX((*H_maxScore), hi);
}
// save the last entry of the band
temp[idRow] = make_int2(H_band[BAND_LEN], E);
//(* H_maxScore) = MAX((* H_maxScore), H_band[BAND_LEN]);
}
__global__
void localProcessSWTiling(ASCIIEntry_t *d_CandidatesASCII, uint32_t *d_CandidatesASCIIposition,
ASCIIEntry_t *d_QueriesASCII, uint32_t *d_QueriesASCIIposition,
alignmentInfo_t *d_AlignmentsInfo, alignmentEntry_t *d_AlignmentsResults,
uint32_t querySize, uint32_t candidateSize, uint32_t candidatesNum)
{
const uint32_t idCandidate = blockIdx.x * MAX_THREADS_PER_SM + threadIdx.x;
if (idCandidate < candidatesNum)
{
const char* candidate = d_CandidatesASCII + d_CandidatesASCIIposition[idCandidate];
const char* query = d_QueriesASCII + d_QueriesASCIIposition[d_AlignmentsInfo[idCandidate]];
int2 temp[MAX_QUERY_SIZE];
char r_cache[BAND_LEN];
int32_t H_band[BAND_LEN + 1];
int32_t F_band[BAND_LEN + 1];
char q_i;
const int32_t numRows = querySize, numColumns = candidateSize;
int32_t idColumn, idRow, idBand;
int32_t H_maxScore = 0;
for(idBand = 0; idBand < MAX_QUERY_SIZE; ++idBand){
temp[idBand].x = 0;
temp[idBand].y = 0;
}
// Compute Score SW-GOTOH
for(idColumn = 0; idColumn < numColumns; idColumn += BAND_LEN){
// load a block of entries from the reference
#pragma unroll
for (uint32_t idBand = 0; idBand < BAND_LEN; ++idBand)
r_cache[idBand] = candidate[idColumn + idBand];
// initialize the first band
#pragma unroll
for (uint32_t idBand = 0; idBand <= BAND_LEN; ++idBand){
H_band[idBand] = 0;
F_band[idBand] = 0; /* ? */
}
for(idRow = 0; idRow < numRows; ++idRow){
q_i = query[idRow];
update_band(idRow, q_i, r_cache, H_band, F_band, temp, &H_maxScore);
}
}
d_AlignmentsResults[idCandidate].score = H_maxScore;
d_AlignmentsResults[idCandidate].column = 0;
//d_AlignmentsResults[idCandidate].column = maxColumn;
}
}
extern "C"
psaError_t localProcessPairwiseStream(sequences_t *candidates, sequences_t *queries, alignments_t *alignments)
{
uint32_t blocks = DIV_CEIL(candidates->num, CUDA_NUM_THREADS);
uint32_t threads = CUDA_NUM_THREADS;
uint32_t querySize = queries->h_size[0];
uint32_t candidateSize = candidates->h_size[0];
cudaThreadSetCacheConfig(cudaFuncCachePreferL1);
printf("Grid Size: %d, Block Size: %d, Total alignments: %d\n", blocks, threads, candidates->num);
localProcessSWTiling<<<blocks, threads>>>(candidates->d_ASCII, candidates->d_ASCIIposition,
queries->d_ASCII, queries->d_ASCIIposition,
alignments->d_info, alignments->d_results,
querySize, candidateSize, candidates->num);
cudaThreadSynchronize();
return (SUCCESS);
} | /*
* PROJECT: Pairwise sequence alignments on GPU
* FILE: psa_swgotoh_registers_32b_gpu
* AUTHOR(S): Alejandro Chacon <alejandro.chacon@uab.es>
* Jacopo Pantaleoni <jpantaleoni@nvidia.com>
* DESCRIPTION: Device functions for the SW-Gotoh GPU implementation:
* Using a 16 bits of representation per cell and intermediate column.
*/
extern "C" {
#include "../../../include/psa_pairwise_gpu.h"
}
#include <hip/hip_runtime.h>
#define MATCH_SCORE 2
#define MISMATCH_SCORE -5
#define OPEN_INDEL_SCORE -2
#define EXTEND_INDEL_SCORE -1
#define V4_PACKET1(NUM_A,NUM_B,NUM_C,NUM_D) ((NUM_A << 24) | (NUM_B << 16) | (NUM_C << 8) | NUM_D)
#define V4_PACKET4(NUM) ((NUM << 24) | (NUM << 16) | (NUM << 8) | NUM)
#ifndef QUERIES_SIZE
#define QUERIES_SIZE 100
#endif
#ifndef CANDIDATES_SIZE
#define CANDIDATES_SIZE 120
#endif
#define MAX3(a,b,c) (MAX(MAX(a, b), c))
#define WARP_SIZE 32
#define MAX_THREADS_PER_SM 128
#define CUDA_NUM_THREADS 128
#define THREADS_PER_SEGMENT 32
#define NUM_SW_PER_BLOCK (MAX_THREADS_PER_SM / THREADS_PER_SEGMENT)
#define NUM_WARPS (MAX_THREADS_PER_SM / WARP_SIZE)
#define BAND_LEN 8
#define MAX_QUERY_SIZE 200
inline __device__
int32_t max3(const int32_t op1, const int32_t op2, const int32_t op3)
{
uint32_t r;
asm( " vmax.s32.s32.s32.max %0, %1, %2, %3;" : "=r"(r) : "r"(op1), "r"(op2), "r"(op3) );
return r;
}
inline __device__
void update_band(int32_t idRow, char q_i, char *ref_cache, int32_t *H_band, int32_t *F_band,
int2 *temp, int32_t *H_maxScore)
{
int32_t H_diag = H_band[0];
H_band[0] = temp[idRow].x;
int32_t E = temp[idRow].y;
#pragma unroll
for (uint32_t j = 1; j <= BAND_LEN; ++j)
{
// update F
const int32_t ftop = F_band[j] + EXTEND_INDEL_SCORE;
const int32_t htop = H_band[j] + OPEN_INDEL_SCORE;
F_band[j] = MAX(ftop, htop);
// update E
const int32_t eleft = E + EXTEND_INDEL_SCORE;
const int32_t hleft = H_band[j-1] + OPEN_INDEL_SCORE;
E = MAX(eleft, hleft);
const int32_t r_j = ref_cache[j-1];
const int32_t W_ij = (r_j == q_i) ? MATCH_SCORE : MISMATCH_SCORE;
const int32_t diagonal = H_diag + W_ij;
const int32_t top = F_band[j];
const int32_t left = E;
int32_t hi = MAX3(left, top, diagonal);
hi = MAX(hi, 0);
H_diag = H_band[j];
H_band[j] = hi;
(*H_maxScore) = MAX((*H_maxScore), hi);
}
// save the last entry of the band
temp[idRow] = make_int2(H_band[BAND_LEN], E);
//(* H_maxScore) = MAX((* H_maxScore), H_band[BAND_LEN]);
}
__global__
void localProcessSWTiling(ASCIIEntry_t *d_CandidatesASCII, uint32_t *d_CandidatesASCIIposition,
ASCIIEntry_t *d_QueriesASCII, uint32_t *d_QueriesASCIIposition,
alignmentInfo_t *d_AlignmentsInfo, alignmentEntry_t *d_AlignmentsResults,
uint32_t querySize, uint32_t candidateSize, uint32_t candidatesNum)
{
const uint32_t idCandidate = blockIdx.x * MAX_THREADS_PER_SM + threadIdx.x;
if (idCandidate < candidatesNum)
{
const char* candidate = d_CandidatesASCII + d_CandidatesASCIIposition[idCandidate];
const char* query = d_QueriesASCII + d_QueriesASCIIposition[d_AlignmentsInfo[idCandidate]];
int2 temp[MAX_QUERY_SIZE];
char r_cache[BAND_LEN];
int32_t H_band[BAND_LEN + 1];
int32_t F_band[BAND_LEN + 1];
char q_i;
const int32_t numRows = querySize, numColumns = candidateSize;
int32_t idColumn, idRow, idBand;
int32_t H_maxScore = 0;
for(idBand = 0; idBand < MAX_QUERY_SIZE; ++idBand){
temp[idBand].x = 0;
temp[idBand].y = 0;
}
// Compute Score SW-GOTOH
for(idColumn = 0; idColumn < numColumns; idColumn += BAND_LEN){
// load a block of entries from the reference
#pragma unroll
for (uint32_t idBand = 0; idBand < BAND_LEN; ++idBand)
r_cache[idBand] = candidate[idColumn + idBand];
// initialize the first band
#pragma unroll
for (uint32_t idBand = 0; idBand <= BAND_LEN; ++idBand){
H_band[idBand] = 0;
F_band[idBand] = 0; /* ? */
}
for(idRow = 0; idRow < numRows; ++idRow){
q_i = query[idRow];
update_band(idRow, q_i, r_cache, H_band, F_band, temp, &H_maxScore);
}
}
d_AlignmentsResults[idCandidate].score = H_maxScore;
d_AlignmentsResults[idCandidate].column = 0;
//d_AlignmentsResults[idCandidate].column = maxColumn;
}
}
extern "C"
psaError_t localProcessPairwiseStream(sequences_t *candidates, sequences_t *queries, alignments_t *alignments)
{
uint32_t blocks = DIV_CEIL(candidates->num, CUDA_NUM_THREADS);
uint32_t threads = CUDA_NUM_THREADS;
uint32_t querySize = queries->h_size[0];
uint32_t candidateSize = candidates->h_size[0];
hipDeviceSetCacheConfig(hipFuncCachePreferL1);
printf("Grid Size: %d, Block Size: %d, Total alignments: %d\n", blocks, threads, candidates->num);
localProcessSWTiling<<<blocks, threads>>>(candidates->d_ASCII, candidates->d_ASCIIposition,
queries->d_ASCII, queries->d_ASCIIposition,
alignments->d_info, alignments->d_results,
querySize, candidateSize, candidates->num);
hipDeviceSynchronize();
return (SUCCESS);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | /*
* PROJECT: Pairwise sequence alignments on GPU
* FILE: psa_swgotoh_registers_32b_gpu
* AUTHOR(S): Alejandro Chacon <alejandro.chacon@uab.es>
* Jacopo Pantaleoni <jpantaleoni@nvidia.com>
* DESCRIPTION: Device functions for the SW-Gotoh GPU implementation:
* Using a 16 bits of representation per cell and intermediate column.
*/
extern "C" {
#include "../../../include/psa_pairwise_gpu.h"
}
#include <hip/hip_runtime.h>
#define MATCH_SCORE 2
#define MISMATCH_SCORE -5
#define OPEN_INDEL_SCORE -2
#define EXTEND_INDEL_SCORE -1
#define V4_PACKET1(NUM_A,NUM_B,NUM_C,NUM_D) ((NUM_A << 24) | (NUM_B << 16) | (NUM_C << 8) | NUM_D)
#define V4_PACKET4(NUM) ((NUM << 24) | (NUM << 16) | (NUM << 8) | NUM)
#ifndef QUERIES_SIZE
#define QUERIES_SIZE 100
#endif
#ifndef CANDIDATES_SIZE
#define CANDIDATES_SIZE 120
#endif
#define MAX3(a,b,c) (MAX(MAX(a, b), c))
#define WARP_SIZE 32
#define MAX_THREADS_PER_SM 128
#define CUDA_NUM_THREADS 128
#define THREADS_PER_SEGMENT 32
#define NUM_SW_PER_BLOCK (MAX_THREADS_PER_SM / THREADS_PER_SEGMENT)
#define NUM_WARPS (MAX_THREADS_PER_SM / WARP_SIZE)
#define BAND_LEN 8
#define MAX_QUERY_SIZE 200
inline __device__
int32_t max3(const int32_t op1, const int32_t op2, const int32_t op3)
{
uint32_t r;
asm( " vmax.s32.s32.s32.max %0, %1, %2, %3;" : "=r"(r) : "r"(op1), "r"(op2), "r"(op3) );
return r;
}
inline __device__
void update_band(int32_t idRow, char q_i, char *ref_cache, int32_t *H_band, int32_t *F_band,
int2 *temp, int32_t *H_maxScore)
{
int32_t H_diag = H_band[0];
H_band[0] = temp[idRow].x;
int32_t E = temp[idRow].y;
#pragma unroll
for (uint32_t j = 1; j <= BAND_LEN; ++j)
{
// update F
const int32_t ftop = F_band[j] + EXTEND_INDEL_SCORE;
const int32_t htop = H_band[j] + OPEN_INDEL_SCORE;
F_band[j] = MAX(ftop, htop);
// update E
const int32_t eleft = E + EXTEND_INDEL_SCORE;
const int32_t hleft = H_band[j-1] + OPEN_INDEL_SCORE;
E = MAX(eleft, hleft);
const int32_t r_j = ref_cache[j-1];
const int32_t W_ij = (r_j == q_i) ? MATCH_SCORE : MISMATCH_SCORE;
const int32_t diagonal = H_diag + W_ij;
const int32_t top = F_band[j];
const int32_t left = E;
int32_t hi = MAX3(left, top, diagonal);
hi = MAX(hi, 0);
H_diag = H_band[j];
H_band[j] = hi;
(*H_maxScore) = MAX((*H_maxScore), hi);
}
// save the last entry of the band
temp[idRow] = make_int2(H_band[BAND_LEN], E);
//(* H_maxScore) = MAX((* H_maxScore), H_band[BAND_LEN]);
}
__global__
void localProcessSWTiling(ASCIIEntry_t *d_CandidatesASCII, uint32_t *d_CandidatesASCIIposition,
ASCIIEntry_t *d_QueriesASCII, uint32_t *d_QueriesASCIIposition,
alignmentInfo_t *d_AlignmentsInfo, alignmentEntry_t *d_AlignmentsResults,
uint32_t querySize, uint32_t candidateSize, uint32_t candidatesNum)
{
const uint32_t idCandidate = blockIdx.x * MAX_THREADS_PER_SM + threadIdx.x;
if (idCandidate < candidatesNum)
{
const char* candidate = d_CandidatesASCII + d_CandidatesASCIIposition[idCandidate];
const char* query = d_QueriesASCII + d_QueriesASCIIposition[d_AlignmentsInfo[idCandidate]];
int2 temp[MAX_QUERY_SIZE];
char r_cache[BAND_LEN];
int32_t H_band[BAND_LEN + 1];
int32_t F_band[BAND_LEN + 1];
char q_i;
const int32_t numRows = querySize, numColumns = candidateSize;
int32_t idColumn, idRow, idBand;
int32_t H_maxScore = 0;
for(idBand = 0; idBand < MAX_QUERY_SIZE; ++idBand){
temp[idBand].x = 0;
temp[idBand].y = 0;
}
// Compute Score SW-GOTOH
for(idColumn = 0; idColumn < numColumns; idColumn += BAND_LEN){
// load a block of entries from the reference
#pragma unroll
for (uint32_t idBand = 0; idBand < BAND_LEN; ++idBand)
r_cache[idBand] = candidate[idColumn + idBand];
// initialize the first band
#pragma unroll
for (uint32_t idBand = 0; idBand <= BAND_LEN; ++idBand){
H_band[idBand] = 0;
F_band[idBand] = 0; /* ? */
}
for(idRow = 0; idRow < numRows; ++idRow){
q_i = query[idRow];
update_band(idRow, q_i, r_cache, H_band, F_band, temp, &H_maxScore);
}
}
d_AlignmentsResults[idCandidate].score = H_maxScore;
d_AlignmentsResults[idCandidate].column = 0;
//d_AlignmentsResults[idCandidate].column = maxColumn;
}
}
extern "C"
psaError_t localProcessPairwiseStream(sequences_t *candidates, sequences_t *queries, alignments_t *alignments)
{
uint32_t blocks = DIV_CEIL(candidates->num, CUDA_NUM_THREADS);
uint32_t threads = CUDA_NUM_THREADS;
uint32_t querySize = queries->h_size[0];
uint32_t candidateSize = candidates->h_size[0];
hipDeviceSetCacheConfig(hipFuncCachePreferL1);
printf("Grid Size: %d, Block Size: %d, Total alignments: %d\n", blocks, threads, candidates->num);
localProcessSWTiling<<<blocks, threads>>>(candidates->d_ASCII, candidates->d_ASCIIposition,
queries->d_ASCII, queries->d_ASCIIposition,
alignments->d_info, alignments->d_results,
querySize, candidateSize, candidates->num);
hipDeviceSynchronize();
return (SUCCESS);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z20localProcessSWTilingPcPjS_S0_S0_P16alignmentEntry_tjjj
.globl _Z20localProcessSWTilingPcPjS_S0_S0_P16alignmentEntry_tjjj
.p2align 8
.type _Z20localProcessSWTilingPcPjS_S0_S0_P16alignmentEntry_tjjj,@function
_Z20localProcessSWTilingPcPjS_S0_S0_P16alignmentEntry_tjjj:
s_load_b32 s2, s[0:1], 0x38
v_lshl_add_u32 v0, s15, 7, v0
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_cmp_gt_u32_e32 vcc_lo, s2, v0
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_11
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x18
s_load_b64 s[2:3], s[0:1], 0x8
v_mov_b32_e32 v2, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mov_b32_e32 v1, v2
v_lshlrev_b64 v[3:4], 2, v[0:1]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v5, vcc_lo, s6, v3
v_add_co_ci_u32_e32 v6, vcc_lo, s7, v4, vcc_lo
v_add_co_u32 v3, vcc_lo, s2, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v4, vcc_lo
global_load_b32 v5, v[5:6], off
v_mov_b32_e32 v6, v2
s_mov_b32 s2, 0
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[5:6], 2, v[5:6]
v_add_co_u32 v5, vcc_lo, s4, v5
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v6, vcc_lo, s5, v6, vcc_lo
global_load_b32 v4, v[3:4], off
global_load_b32 v5, v[5:6], off
.LBB0_2:
v_mov_b32_e32 v3, v2
s_add_i32 s3, s2, 16
s_add_i32 s2, s2, 8
s_delay_alu instid0(SALU_CYCLE_1)
s_cmpk_eq_i32 s2, 0x640
scratch_store_b64 off, v[2:3], s3
s_cbranch_scc0 .LBB0_2
s_load_b32 s2, s[0:1], 0x34
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s2, 1
s_cbranch_scc1 .LBB0_9
s_clause 0x2
s_load_b64 s[4:5], s[0:1], 0x0
s_load_b32 s3, s[0:1], 0x30
s_load_b64 s[6:7], s[0:1], 0x10
v_mov_b32_e32 v2, 0
v_or_b32_e64 v7, 16, 4
s_waitcnt vmcnt(1) lgkmcnt(0)
v_add_co_u32 v8, s4, s4, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e64 v9, null, s5, 0, s4
s_waitcnt vmcnt(0)
v_add_co_u32 v3, s4, s6, v5
v_add_co_ci_u32_e64 v4, null, s7, 0, s4
s_cmp_gt_i32 s3, 0
s_mov_b32 s5, 0
s_cselect_b32 s4, -1, 0
s_branch .LBB0_6
.LBB0_5:
s_add_i32 s5, s5, 8
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lt_i32 s5, s2
s_cbranch_scc0 .LBB0_10
.LBB0_6:
s_and_not1_b32 vcc_lo, exec_lo, s4
s_cbranch_vccnz .LBB0_5
v_add_co_u32 v5, vcc_lo, v8, s5
s_or_b32 s6, s5, 1
v_add_co_ci_u32_e32 v6, vcc_lo, 0, v9, vcc_lo
v_add_co_u32 v10, vcc_lo, v8, s6
s_or_b32 s6, s5, 2
v_add_co_ci_u32_e32 v11, vcc_lo, 0, v9, vcc_lo
v_add_co_u32 v12, vcc_lo, v8, s6
s_or_b32 s6, s5, 3
v_add_co_ci_u32_e32 v13, vcc_lo, 0, v9, vcc_lo
v_add_co_u32 v14, vcc_lo, v8, s6
s_or_b32 s6, s5, 4
v_add_co_ci_u32_e32 v15, vcc_lo, 0, v9, vcc_lo
v_add_co_u32 v16, vcc_lo, v8, s6
s_or_b32 s6, s5, 5
v_add_co_ci_u32_e32 v17, vcc_lo, 0, v9, vcc_lo
v_add_co_u32 v18, vcc_lo, v8, s6
s_or_b32 s6, s5, 6
v_add_co_ci_u32_e32 v19, vcc_lo, 0, v9, vcc_lo
v_add_co_u32 v20, vcc_lo, v8, s6
s_or_b32 s6, s5, 7
v_add_co_ci_u32_e32 v21, vcc_lo, 0, v9, vcc_lo
v_add_co_u32 v22, vcc_lo, v8, s6
v_add_co_ci_u32_e32 v23, vcc_lo, 0, v9, vcc_lo
s_clause 0x7
global_load_u8 v24, v[5:6], off
global_load_u8 v25, v[10:11], off
global_load_u8 v27, v[12:13], off
global_load_u8 v36, v[14:15], off
global_load_u8 v37, v[16:17], off
global_load_u8 v38, v[18:19], off
global_load_u8 v39, v[20:21], off
global_load_u8 v40, v[22:23], off
v_dual_mov_b32 v6, v4 :: v_dual_mov_b32 v33, 0
v_dual_mov_b32 v34, 0 :: v_dual_mov_b32 v5, v3
v_dual_mov_b32 v10, v7 :: v_dual_mov_b32 v35, 0
v_dual_mov_b32 v32, 0 :: v_dual_mov_b32 v31, 0
v_dual_mov_b32 v30, 0 :: v_dual_mov_b32 v29, 0
v_dual_mov_b32 v26, 0 :: v_dual_mov_b32 v11, 0
v_mov_b32_e32 v28, 0
v_mov_b32_e32 v12, 0
v_mov_b32_e32 v14, 0
v_mov_b32_e32 v16, 0
v_mov_b32_e32 v18, 0
v_mov_b32_e32 v20, 0
v_mov_b32_e32 v22, 0
s_mov_b32 s6, s3
s_waitcnt vmcnt(7)
v_and_b32_e32 v13, 0xff, v24
s_waitcnt vmcnt(6)
v_and_b32_e32 v15, 0xff, v25
s_waitcnt vmcnt(5)
v_and_b32_e32 v17, 0xff, v27
s_waitcnt vmcnt(4)
v_and_b32_e32 v19, 0xff, v36
s_waitcnt vmcnt(3)
v_and_b32_e32 v21, 0xff, v37
s_waitcnt vmcnt(2)
v_and_b32_e32 v23, 0xff, v38
s_waitcnt vmcnt(1)
v_dual_mov_b32 v27, 0 :: v_dual_and_b32 v24, 0xff, v39
s_waitcnt vmcnt(0)
v_and_b32_e32 v25, 0xff, v40
.LBB0_8:
s_clause 0x1
scratch_load_b32 v36, v10, off
scratch_load_b32 v37, v10, off offset:-4
global_load_u8 v38, v[5:6], off
v_add_nc_u32_e32 v11, -1, v11
v_add_nc_u32_e32 v39, -2, v35
v_add_nc_u32_e32 v12, -1, v12
v_add_nc_u32_e32 v14, -1, v14
v_add_nc_u32_e32 v16, -1, v16
v_add_nc_u32_e32 v18, -1, v18
v_max_i32_e32 v11, v11, v39
v_add_nc_u32_e32 v20, -1, v20
v_add_nc_u32_e32 v22, -1, v22
v_add_nc_u32_e32 v27, -1, v27
v_add_nc_u32_e32 v28, -2, v28
s_add_i32 s6, s6, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_cmp_lg_u32 s6, 0
v_max_i32_e32 v27, v27, v28
s_waitcnt vmcnt(2)
v_add_nc_u32_e32 v36, -1, v36
s_waitcnt vmcnt(1)
v_add_nc_u32_e32 v40, -2, v37
s_waitcnt vmcnt(0)
v_cmp_eq_u16_e32 vcc_lo, v13, v38
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_max_i32_e32 v36, v36, v40
v_cndmask_b32_e64 v39, -5, 2, vcc_lo
v_cmp_eq_u16_e32 vcc_lo, v15, v38
v_add_nc_u32_e32 v34, v39, v34
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_max_i32_e32 v39, v36, v11
v_add_nc_u32_e32 v36, -1, v36
v_max3_i32 v39, v39, v34, 0
v_add_nc_u32_e32 v34, -2, v33
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v40, -2, v39
v_max_i32_e32 v12, v12, v34
v_cndmask_b32_e64 v34, -5, 2, vcc_lo
v_cmp_eq_u16_e32 vcc_lo, v17, v38
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_max_i32_e32 v36, v36, v40
v_add_nc_u32_e32 v34, v34, v35
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_max_i32_e32 v35, v36, v12
v_max3_i32 v40, v35, v34, 0
v_add_nc_u32_e32 v34, -2, v32
v_add_nc_u32_e32 v35, -1, v36
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_nc_u32_e32 v36, -2, v40
v_max_i32_e32 v14, v14, v34
v_cndmask_b32_e64 v34, -5, 2, vcc_lo
v_cmp_eq_u16_e32 vcc_lo, v19, v38
v_max3_i32 v2, v2, v39, v40
v_max_i32_e32 v35, v35, v36
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v33, v34, v33
v_max_i32_e32 v34, v35, v14
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_max3_i32 v36, v34, v33, 0
v_add_nc_u32_e32 v33, -2, v31
v_add_nc_u32_e32 v34, -1, v35
v_add_nc_u32_e32 v35, -2, v36
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
v_max_i32_e32 v16, v16, v33
v_cndmask_b32_e64 v33, -5, 2, vcc_lo
v_cmp_eq_u16_e32 vcc_lo, v21, v38
v_max_i32_e32 v34, v34, v35
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_dual_mov_b32 v35, v39 :: v_dual_add_nc_u32 v32, v33, v32
v_max_i32_e32 v33, v34, v16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_max3_i32 v41, v33, v32, 0
v_add_nc_u32_e32 v32, -2, v30
v_add_nc_u32_e32 v33, -1, v34
v_add_nc_u32_e32 v34, -2, v41
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_4)
v_max_i32_e32 v18, v18, v32
v_cndmask_b32_e64 v32, -5, 2, vcc_lo
v_cmp_eq_u16_e32 vcc_lo, v23, v38
v_max3_i32 v2, v2, v36, v41
v_max_i32_e32 v33, v33, v34
v_dual_mov_b32 v34, v37 :: v_dual_add_nc_u32 v31, v32, v31
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_max_i32_e32 v32, v33, v18
v_max3_i32 v42, v32, v31, 0
v_add_nc_u32_e32 v31, -2, v29
v_add_nc_u32_e32 v32, -1, v33
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_nc_u32_e32 v33, -2, v42
v_max_i32_e32 v20, v20, v31
v_cndmask_b32_e64 v31, -5, 2, vcc_lo
v_cmp_eq_u16_e32 vcc_lo, v24, v38
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_max_i32_e32 v32, v32, v33
v_dual_mov_b32 v33, v40 :: v_dual_add_nc_u32 v30, v31, v30
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_max_i32_e32 v31, v32, v20
v_max3_i32 v43, v31, v30, 0
v_add_nc_u32_e32 v30, -2, v26
v_add_nc_u32_e32 v31, -1, v32
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_nc_u32_e32 v32, -2, v43
v_max_i32_e32 v22, v22, v30
v_cndmask_b32_e64 v30, -5, 2, vcc_lo
v_cmp_eq_u16_e32 vcc_lo, v25, v38
v_max3_i32 v2, v2, v42, v43
v_max_i32_e32 v31, v31, v32
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
v_dual_mov_b32 v32, v36 :: v_dual_add_nc_u32 v29, v30, v29
v_cndmask_b32_e64 v28, -5, 2, vcc_lo
v_add_co_u32 v5, vcc_lo, v5, 1
v_max_i32_e32 v30, v31, v22
v_add_co_ci_u32_e32 v6, vcc_lo, 0, v6, vcc_lo
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_nc_u32_e32 v26, v28, v26
v_max3_i32 v44, v30, v29, 0
v_add_nc_u32_e32 v29, -1, v31
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mov_b32 v31, v41 :: v_dual_add_nc_u32 v30, -2, v44
v_max_i32_e32 v38, v29, v30
v_dual_mov_b32 v30, v42 :: v_dual_mov_b32 v29, v43
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_max_i32_e32 v28, v38, v27
v_max3_i32 v28, v28, v26, 0
v_mov_b32_e32 v26, v44
s_clause 0x1
scratch_store_b32 v10, v28, off offset:-4
scratch_store_b32 v10, v38, off
v_max3_i32 v2, v2, v44, v28
v_add_nc_u32_e32 v10, 8, v10
s_cbranch_scc1 .LBB0_8
s_branch .LBB0_5
.LBB0_9:
v_mov_b32_e32 v2, 0
.LBB0_10:
s_load_b64 s[0:1], s[0:1], 0x28
v_lshlrev_b64 v[0:1], 3, v[0:1]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_co_u32 v3, vcc_lo, s0, v0
s_waitcnt vmcnt(1)
v_add_co_ci_u32_e32 v4, vcc_lo, s1, v1, vcc_lo
v_mov_b32_e32 v1, 0
global_store_b64 v[3:4], v[1:2], off
.LBB0_11:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z20localProcessSWTilingPcPjS_S0_S0_P16alignmentEntry_tjjj
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 1616
.amdhsa_kernarg_size 60
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 1
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 45
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z20localProcessSWTilingPcPjS_S0_S0_P16alignmentEntry_tjjj, .Lfunc_end0-_Z20localProcessSWTilingPcPjS_S0_S0_P16alignmentEntry_tjjj
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
- .offset: 48
.size: 4
.value_kind: by_value
- .offset: 52
.size: 4
.value_kind: by_value
- .offset: 56
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 60
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z20localProcessSWTilingPcPjS_S0_S0_P16alignmentEntry_tjjj
.private_segment_fixed_size: 1616
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z20localProcessSWTilingPcPjS_S0_S0_P16alignmentEntry_tjjj.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 45
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | /*
* PROJECT: Pairwise sequence alignments on GPU
* FILE: psa_swgotoh_registers_32b_gpu
* AUTHOR(S): Alejandro Chacon <alejandro.chacon@uab.es>
* Jacopo Pantaleoni <jpantaleoni@nvidia.com>
* DESCRIPTION: Device functions for the SW-Gotoh GPU implementation:
* Using a 16 bits of representation per cell and intermediate column.
*/
extern "C" {
#include "../../../include/psa_pairwise_gpu.h"
}
#include <hip/hip_runtime.h>
#define MATCH_SCORE 2
#define MISMATCH_SCORE -5
#define OPEN_INDEL_SCORE -2
#define EXTEND_INDEL_SCORE -1
#define V4_PACKET1(NUM_A,NUM_B,NUM_C,NUM_D) ((NUM_A << 24) | (NUM_B << 16) | (NUM_C << 8) | NUM_D)
#define V4_PACKET4(NUM) ((NUM << 24) | (NUM << 16) | (NUM << 8) | NUM)
#ifndef QUERIES_SIZE
#define QUERIES_SIZE 100
#endif
#ifndef CANDIDATES_SIZE
#define CANDIDATES_SIZE 120
#endif
#define MAX3(a,b,c) (MAX(MAX(a, b), c))
#define WARP_SIZE 32
#define MAX_THREADS_PER_SM 128
#define CUDA_NUM_THREADS 128
#define THREADS_PER_SEGMENT 32
#define NUM_SW_PER_BLOCK (MAX_THREADS_PER_SM / THREADS_PER_SEGMENT)
#define NUM_WARPS (MAX_THREADS_PER_SM / WARP_SIZE)
#define BAND_LEN 8
#define MAX_QUERY_SIZE 200
inline __device__
int32_t max3(const int32_t op1, const int32_t op2, const int32_t op3)
{
uint32_t r;
asm( " vmax.s32.s32.s32.max %0, %1, %2, %3;" : "=r"(r) : "r"(op1), "r"(op2), "r"(op3) );
return r;
}
inline __device__
void update_band(int32_t idRow, char q_i, char *ref_cache, int32_t *H_band, int32_t *F_band,
int2 *temp, int32_t *H_maxScore)
{
int32_t H_diag = H_band[0];
H_band[0] = temp[idRow].x;
int32_t E = temp[idRow].y;
#pragma unroll
for (uint32_t j = 1; j <= BAND_LEN; ++j)
{
// update F
const int32_t ftop = F_band[j] + EXTEND_INDEL_SCORE;
const int32_t htop = H_band[j] + OPEN_INDEL_SCORE;
F_band[j] = MAX(ftop, htop);
// update E
const int32_t eleft = E + EXTEND_INDEL_SCORE;
const int32_t hleft = H_band[j-1] + OPEN_INDEL_SCORE;
E = MAX(eleft, hleft);
const int32_t r_j = ref_cache[j-1];
const int32_t W_ij = (r_j == q_i) ? MATCH_SCORE : MISMATCH_SCORE;
const int32_t diagonal = H_diag + W_ij;
const int32_t top = F_band[j];
const int32_t left = E;
int32_t hi = MAX3(left, top, diagonal);
hi = MAX(hi, 0);
H_diag = H_band[j];
H_band[j] = hi;
(*H_maxScore) = MAX((*H_maxScore), hi);
}
// save the last entry of the band
temp[idRow] = make_int2(H_band[BAND_LEN], E);
//(* H_maxScore) = MAX((* H_maxScore), H_band[BAND_LEN]);
}
__global__
void localProcessSWTiling(ASCIIEntry_t *d_CandidatesASCII, uint32_t *d_CandidatesASCIIposition,
ASCIIEntry_t *d_QueriesASCII, uint32_t *d_QueriesASCIIposition,
alignmentInfo_t *d_AlignmentsInfo, alignmentEntry_t *d_AlignmentsResults,
uint32_t querySize, uint32_t candidateSize, uint32_t candidatesNum)
{
const uint32_t idCandidate = blockIdx.x * MAX_THREADS_PER_SM + threadIdx.x;
if (idCandidate < candidatesNum)
{
const char* candidate = d_CandidatesASCII + d_CandidatesASCIIposition[idCandidate];
const char* query = d_QueriesASCII + d_QueriesASCIIposition[d_AlignmentsInfo[idCandidate]];
int2 temp[MAX_QUERY_SIZE];
char r_cache[BAND_LEN];
int32_t H_band[BAND_LEN + 1];
int32_t F_band[BAND_LEN + 1];
char q_i;
const int32_t numRows = querySize, numColumns = candidateSize;
int32_t idColumn, idRow, idBand;
int32_t H_maxScore = 0;
for(idBand = 0; idBand < MAX_QUERY_SIZE; ++idBand){
temp[idBand].x = 0;
temp[idBand].y = 0;
}
// Compute Score SW-GOTOH
for(idColumn = 0; idColumn < numColumns; idColumn += BAND_LEN){
// load a block of entries from the reference
#pragma unroll
for (uint32_t idBand = 0; idBand < BAND_LEN; ++idBand)
r_cache[idBand] = candidate[idColumn + idBand];
// initialize the first band
#pragma unroll
for (uint32_t idBand = 0; idBand <= BAND_LEN; ++idBand){
H_band[idBand] = 0;
F_band[idBand] = 0; /* ? */
}
for(idRow = 0; idRow < numRows; ++idRow){
q_i = query[idRow];
update_band(idRow, q_i, r_cache, H_band, F_band, temp, &H_maxScore);
}
}
d_AlignmentsResults[idCandidate].score = H_maxScore;
d_AlignmentsResults[idCandidate].column = 0;
//d_AlignmentsResults[idCandidate].column = maxColumn;
}
}
extern "C"
psaError_t localProcessPairwiseStream(sequences_t *candidates, sequences_t *queries, alignments_t *alignments)
{
uint32_t blocks = DIV_CEIL(candidates->num, CUDA_NUM_THREADS);
uint32_t threads = CUDA_NUM_THREADS;
uint32_t querySize = queries->h_size[0];
uint32_t candidateSize = candidates->h_size[0];
hipDeviceSetCacheConfig(hipFuncCachePreferL1);
printf("Grid Size: %d, Block Size: %d, Total alignments: %d\n", blocks, threads, candidates->num);
localProcessSWTiling<<<blocks, threads>>>(candidates->d_ASCII, candidates->d_ASCIIposition,
queries->d_ASCII, queries->d_ASCIIposition,
alignments->d_info, alignments->d_results,
querySize, candidateSize, candidates->num);
hipDeviceSynchronize();
return (SUCCESS);
} | .text
.file "psa_swgotoh_registers_32b_gpu.hip"
.globl _Z35__device_stub__localProcessSWTilingPcPjS_S0_S0_P16alignmentEntry_tjjj # -- Begin function _Z35__device_stub__localProcessSWTilingPcPjS_S0_S0_P16alignmentEntry_tjjj
.p2align 4, 0x90
.type _Z35__device_stub__localProcessSWTilingPcPjS_S0_S0_P16alignmentEntry_tjjj,@function
_Z35__device_stub__localProcessSWTilingPcPjS_S0_S0_P16alignmentEntry_tjjj: # @_Z35__device_stub__localProcessSWTilingPcPjS_S0_S0_P16alignmentEntry_tjjj
.cfi_startproc
# %bb.0:
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
movq %r9, 48(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 176(%rsp), %rax
movq %rax, 144(%rsp)
leaq 184(%rsp), %rax
movq %rax, 152(%rsp)
leaq 192(%rsp), %rax
movq %rax, 160(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z20localProcessSWTilingPcPjS_S0_S0_P16alignmentEntry_tjjj, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $184, %rsp
.cfi_adjust_cfa_offset -184
retq
.Lfunc_end0:
.size _Z35__device_stub__localProcessSWTilingPcPjS_S0_S0_P16alignmentEntry_tjjj, .Lfunc_end0-_Z35__device_stub__localProcessSWTilingPcPjS_S0_S0_P16alignmentEntry_tjjj
.cfi_endproc
# -- End function
.globl localProcessPairwiseStream # -- Begin function localProcessPairwiseStream
.p2align 4, 0x90
.type localProcessPairwiseStream,@function
localProcessPairwiseStream: # @localProcessPairwiseStream
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $184, %rsp
.cfi_def_cfa_offset 240
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rdx, %rbx
movq %rsi, %r15
movq %rdi, %r14
movl (%rdi), %r12d
addl $127, %r12d
shrl $7, %r12d
movq 184(%rsi), %rax
movl (%rax), %ebp
movq 184(%rdi), %rax
movl (%rax), %r13d
movl $2, %edi
callq hipDeviceSetCacheConfig
movl (%r14), %ecx
movl $.L.str, %edi
movl %r12d, %esi
movl $128, %edx
xorl %eax, %eax
callq printf
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %r12
orq $128, %rdx
movq %r12, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq 160(%r14), %rax
movq 176(%r14), %rcx
movq 160(%r15), %rdx
movq 176(%r15), %rsi
movq 16(%rbx), %rdi
movq 32(%rbx), %r8
movl (%r14), %r9d
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdi, 72(%rsp)
movq %r8, 64(%rsp)
movl %ebp, 12(%rsp)
movl %r13d, 8(%rsp)
movl %r9d, 4(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 80(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rax
movq %rax, 144(%rsp)
leaq 64(%rsp), %rax
movq %rax, 152(%rsp)
leaq 12(%rsp), %rax
movq %rax, 160(%rsp)
leaq 8(%rsp), %rax
movq %rax, 168(%rsp)
leaq 4(%rsp), %rax
movq %rax, 176(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z20localProcessSWTilingPcPjS_S0_S0_P16alignmentEntry_tjjj, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
callq hipDeviceSynchronize
xorl %eax, %eax
addq $184, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size localProcessPairwiseStream, .Lfunc_end1-localProcessPairwiseStream
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z20localProcessSWTilingPcPjS_S0_S0_P16alignmentEntry_tjjj, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z20localProcessSWTilingPcPjS_S0_S0_P16alignmentEntry_tjjj,@object # @_Z20localProcessSWTilingPcPjS_S0_S0_P16alignmentEntry_tjjj
.section .rodata,"a",@progbits
.globl _Z20localProcessSWTilingPcPjS_S0_S0_P16alignmentEntry_tjjj
.p2align 3, 0x0
_Z20localProcessSWTilingPcPjS_S0_S0_P16alignmentEntry_tjjj:
.quad _Z35__device_stub__localProcessSWTilingPcPjS_S0_S0_P16alignmentEntry_tjjj
.size _Z20localProcessSWTilingPcPjS_S0_S0_P16alignmentEntry_tjjj, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Grid Size: %d, Block Size: %d, Total alignments: %d\n"
.size .L.str, 53
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z20localProcessSWTilingPcPjS_S0_S0_P16alignmentEntry_tjjj"
.size .L__unnamed_1, 59
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z35__device_stub__localProcessSWTilingPcPjS_S0_S0_P16alignmentEntry_tjjj
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z20localProcessSWTilingPcPjS_S0_S0_P16alignmentEntry_tjjj
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000bb055_00000000-6_psa_swgotoh_registers_32b_gpu.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z72__device_stub__Z20localProcessSWTilingPcPjS_S0_S0_P16alignmentEntry_tjjjPcPjS_S0_S0_P16alignmentEntry_tjjj
.type _Z72__device_stub__Z20localProcessSWTilingPcPjS_S0_S0_P16alignmentEntry_tjjjPcPjS_S0_S0_P16alignmentEntry_tjjj, @function
_Z72__device_stub__Z20localProcessSWTilingPcPjS_S0_S0_P16alignmentEntry_tjjjPcPjS_S0_S0_P16alignmentEntry_tjjj:
.LFB2084:
.cfi_startproc
endbr64
subq $200, %rsp
.cfi_def_cfa_offset 208
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movq %r8, 8(%rsp)
movq %r9, (%rsp)
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
movq %rsp, %rax
movq %rax, 152(%rsp)
leaq 208(%rsp), %rax
movq %rax, 160(%rsp)
leaq 216(%rsp), %rax
movq %rax, 168(%rsp)
leaq 224(%rsp), %rax
movq %rax, 176(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 216
pushq 56(%rsp)
.cfi_def_cfa_offset 224
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z20localProcessSWTilingPcPjS_S0_S0_P16alignmentEntry_tjjj(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z72__device_stub__Z20localProcessSWTilingPcPjS_S0_S0_P16alignmentEntry_tjjjPcPjS_S0_S0_P16alignmentEntry_tjjj, .-_Z72__device_stub__Z20localProcessSWTilingPcPjS_S0_S0_P16alignmentEntry_tjjjPcPjS_S0_S0_P16alignmentEntry_tjjj
.globl _Z20localProcessSWTilingPcPjS_S0_S0_P16alignmentEntry_tjjj
.type _Z20localProcessSWTilingPcPjS_S0_S0_P16alignmentEntry_tjjj, @function
_Z20localProcessSWTilingPcPjS_S0_S0_P16alignmentEntry_tjjj:
.LFB2085:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 40
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 48
call _Z72__device_stub__Z20localProcessSWTilingPcPjS_S0_S0_P16alignmentEntry_tjjjPcPjS_S0_S0_P16alignmentEntry_tjjj
addq $40, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z20localProcessSWTilingPcPjS_S0_S0_P16alignmentEntry_tjjj, .-_Z20localProcessSWTilingPcPjS_S0_S0_P16alignmentEntry_tjjj
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "Grid Size: %d, Block Size: %d, Total alignments: %d\n"
.text
.globl localProcessPairwiseStream
.type localProcessPairwiseStream, @function
localProcessPairwiseStream:
.LFB2059:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $40, %rsp
.cfi_def_cfa_offset 96
movq %rdi, %rbp
movq %rsi, %r12
movq %rdx, %r13
movl (%rdi), %eax
leal 127(%rax), %ebx
shrl $7, %ebx
movq 184(%rsi), %rax
movl (%rax), %r14d
movq 184(%rdi), %rax
movl (%rax), %r15d
movl $2, %edi
call cudaThreadSetCacheConfig@PLT
movl 0(%rbp), %r8d
movl $128, %ecx
movl %ebx, %edx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $128, 20(%rsp)
movl $1, 24(%rsp)
movl %ebx, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L12:
call cudaThreadSynchronize@PLT
movl $0, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
movq 176(%r12), %rcx
movq 160(%r12), %rdx
movq 176(%rbp), %rsi
movq 160(%rbp), %rdi
subq $8, %rsp
.cfi_def_cfa_offset 104
movl 0(%rbp), %eax
pushq %rax
.cfi_def_cfa_offset 112
pushq %r15
.cfi_def_cfa_offset 120
pushq %r14
.cfi_def_cfa_offset 128
movq 32(%r13), %r9
movq 16(%r13), %r8
call _Z72__device_stub__Z20localProcessSWTilingPcPjS_S0_S0_P16alignmentEntry_tjjjPcPjS_S0_S0_P16alignmentEntry_tjjj
addq $32, %rsp
.cfi_def_cfa_offset 96
jmp .L12
.cfi_endproc
.LFE2059:
.size localProcessPairwiseStream, .-localProcessPairwiseStream
.section .rodata.str1.8
.align 8
.LC1:
.string "_Z20localProcessSWTilingPcPjS_S0_S0_P16alignmentEntry_tjjj"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z20localProcessSWTilingPcPjS_S0_S0_P16alignmentEntry_tjjj(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "psa_swgotoh_registers_32b_gpu.hip"
.globl _Z35__device_stub__localProcessSWTilingPcPjS_S0_S0_P16alignmentEntry_tjjj # -- Begin function _Z35__device_stub__localProcessSWTilingPcPjS_S0_S0_P16alignmentEntry_tjjj
.p2align 4, 0x90
.type _Z35__device_stub__localProcessSWTilingPcPjS_S0_S0_P16alignmentEntry_tjjj,@function
_Z35__device_stub__localProcessSWTilingPcPjS_S0_S0_P16alignmentEntry_tjjj: # @_Z35__device_stub__localProcessSWTilingPcPjS_S0_S0_P16alignmentEntry_tjjj
.cfi_startproc
# %bb.0:
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
movq %r9, 48(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 176(%rsp), %rax
movq %rax, 144(%rsp)
leaq 184(%rsp), %rax
movq %rax, 152(%rsp)
leaq 192(%rsp), %rax
movq %rax, 160(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z20localProcessSWTilingPcPjS_S0_S0_P16alignmentEntry_tjjj, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $184, %rsp
.cfi_adjust_cfa_offset -184
retq
.Lfunc_end0:
.size _Z35__device_stub__localProcessSWTilingPcPjS_S0_S0_P16alignmentEntry_tjjj, .Lfunc_end0-_Z35__device_stub__localProcessSWTilingPcPjS_S0_S0_P16alignmentEntry_tjjj
.cfi_endproc
# -- End function
.globl localProcessPairwiseStream # -- Begin function localProcessPairwiseStream
.p2align 4, 0x90
.type localProcessPairwiseStream,@function
localProcessPairwiseStream: # @localProcessPairwiseStream
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $184, %rsp
.cfi_def_cfa_offset 240
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rdx, %rbx
movq %rsi, %r15
movq %rdi, %r14
movl (%rdi), %r12d
addl $127, %r12d
shrl $7, %r12d
movq 184(%rsi), %rax
movl (%rax), %ebp
movq 184(%rdi), %rax
movl (%rax), %r13d
movl $2, %edi
callq hipDeviceSetCacheConfig
movl (%r14), %ecx
movl $.L.str, %edi
movl %r12d, %esi
movl $128, %edx
xorl %eax, %eax
callq printf
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %r12
orq $128, %rdx
movq %r12, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq 160(%r14), %rax
movq 176(%r14), %rcx
movq 160(%r15), %rdx
movq 176(%r15), %rsi
movq 16(%rbx), %rdi
movq 32(%rbx), %r8
movl (%r14), %r9d
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdi, 72(%rsp)
movq %r8, 64(%rsp)
movl %ebp, 12(%rsp)
movl %r13d, 8(%rsp)
movl %r9d, 4(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 80(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rax
movq %rax, 144(%rsp)
leaq 64(%rsp), %rax
movq %rax, 152(%rsp)
leaq 12(%rsp), %rax
movq %rax, 160(%rsp)
leaq 8(%rsp), %rax
movq %rax, 168(%rsp)
leaq 4(%rsp), %rax
movq %rax, 176(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z20localProcessSWTilingPcPjS_S0_S0_P16alignmentEntry_tjjj, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
callq hipDeviceSynchronize
xorl %eax, %eax
addq $184, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size localProcessPairwiseStream, .Lfunc_end1-localProcessPairwiseStream
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z20localProcessSWTilingPcPjS_S0_S0_P16alignmentEntry_tjjj, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z20localProcessSWTilingPcPjS_S0_S0_P16alignmentEntry_tjjj,@object # @_Z20localProcessSWTilingPcPjS_S0_S0_P16alignmentEntry_tjjj
.section .rodata,"a",@progbits
.globl _Z20localProcessSWTilingPcPjS_S0_S0_P16alignmentEntry_tjjj
.p2align 3, 0x0
_Z20localProcessSWTilingPcPjS_S0_S0_P16alignmentEntry_tjjj:
.quad _Z35__device_stub__localProcessSWTilingPcPjS_S0_S0_P16alignmentEntry_tjjj
.size _Z20localProcessSWTilingPcPjS_S0_S0_P16alignmentEntry_tjjj, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Grid Size: %d, Block Size: %d, Total alignments: %d\n"
.size .L.str, 53
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z20localProcessSWTilingPcPjS_S0_S0_P16alignmentEntry_tjjj"
.size .L__unnamed_1, 59
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z35__device_stub__localProcessSWTilingPcPjS_S0_S0_P16alignmentEntry_tjjj
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z20localProcessSWTilingPcPjS_S0_S0_P16alignmentEntry_tjjj
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | /*!
\file arrays.cu
\author Andrew Kerr <arkerr@gatech.edu>
\brief tests implementation of cudaMallocArray(), among other things
\date Feb 12, 2010
*/
#include <stdlib.h>
#include <stdio.h>
//////////////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////////////
bool testMemcpy(bool verbose) {
bool passed = true;
int width = 1024, height = 512;
int errors = 0;
cudaChannelFormatDesc channel = cudaCreateChannelDesc(32, 0, 0, 0, cudaChannelFormatKindFloat);
cudaArray *cuArray;
cudaMallocArray(&cuArray, &channel, width, height);
srand(7);
size_t bytes = sizeof(float) * width * height;
float *hostSource = new float[width * height];
float *hostDest = new float[width * height];
for (int j = 0; j < height; j++) {
float *ptr = hostSource + j * width;
float *dstPtr = hostDest + j * width;
for (int i = 0; i < width; i++) {
float x = (float)( (rand() % 1024) / 125.0f);
ptr[i] = x;
dstPtr[i] = -1.0f;
}
}
cudaMemcpyToArray(cuArray, 0, 0, hostSource, bytes, cudaMemcpyHostToDevice);
cudaMemcpyFromArray(hostDest, cuArray, 0, 0, bytes, cudaMemcpyDeviceToHost);
for (int j = 0; j < height && errors < 5; j++) {
float *srcPtr = hostSource + j * width;
float *dstPtr = hostDest + j * width;
for (int i = 0; i < width && errors < 5; i++) {
float expected = srcPtr[i];
float got = dstPtr[i];
if (fabs(expected - got) > 0.001f) {
++errors;
if (verbose) {
printf("ERROR: (%d, %d) - expected %f, got %f\n", i, j, expected, got);
fflush(stdout);
}
}
}
}
cudaFreeArray(cuArray);
delete [] hostSource;
delete [] hostDest;
return passed;
}
//////////////////////////////////////////////////////////////////////////////////////////////////
int main(int argc, char *arg[]) {
bool result = testMemcpy(true);
if (result) {
printf("Test PASSED\n");
}
else {
printf("Test FAILED\n");
}
return 0;
}
////////////////////////////////////////////////////////////////////////////////////////////////// | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /*!
\file arrays.cu
\author Andrew Kerr <arkerr@gatech.edu>
\brief tests implementation of cudaMallocArray(), among other things
\date Feb 12, 2010
*/
#include <stdlib.h>
#include <stdio.h>
//////////////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////////////
bool testMemcpy(bool verbose) {
bool passed = true;
int width = 1024, height = 512;
int errors = 0;
cudaChannelFormatDesc channel = cudaCreateChannelDesc(32, 0, 0, 0, cudaChannelFormatKindFloat);
cudaArray *cuArray;
cudaMallocArray(&cuArray, &channel, width, height);
srand(7);
size_t bytes = sizeof(float) * width * height;
float *hostSource = new float[width * height];
float *hostDest = new float[width * height];
for (int j = 0; j < height; j++) {
float *ptr = hostSource + j * width;
float *dstPtr = hostDest + j * width;
for (int i = 0; i < width; i++) {
float x = (float)( (rand() % 1024) / 125.0f);
ptr[i] = x;
dstPtr[i] = -1.0f;
}
}
cudaMemcpyToArray(cuArray, 0, 0, hostSource, bytes, cudaMemcpyHostToDevice);
cudaMemcpyFromArray(hostDest, cuArray, 0, 0, bytes, cudaMemcpyDeviceToHost);
for (int j = 0; j < height && errors < 5; j++) {
float *srcPtr = hostSource + j * width;
float *dstPtr = hostDest + j * width;
for (int i = 0; i < width && errors < 5; i++) {
float expected = srcPtr[i];
float got = dstPtr[i];
if (fabs(expected - got) > 0.001f) {
++errors;
if (verbose) {
printf("ERROR: (%d, %d) - expected %f, got %f\n", i, j, expected, got);
fflush(stdout);
}
}
}
}
cudaFreeArray(cuArray);
delete [] hostSource;
delete [] hostDest;
return passed;
}
//////////////////////////////////////////////////////////////////////////////////////////////////
int main(int argc, char *arg[]) {
bool result = testMemcpy(true);
if (result) {
printf("Test PASSED\n");
}
else {
printf("Test FAILED\n");
}
return 0;
}
////////////////////////////////////////////////////////////////////////////////////////////////// | .file "tmpxft_00054818_00000000-6_arrays.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC4:
.string "ERROR: (%d, %d) - expected %f, got %f\n"
.text
.globl _Z10testMemcpyb
.type _Z10testMemcpyb, @function
_Z10testMemcpyb:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $88, %rsp
.cfi_def_cfa_offset 144
movb %dil, 27(%rsp)
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
leaq 48(%rsp), %rbx
movl $2, %r9d
movl $0, %r8d
movl $0, %ecx
movl $0, %edx
movl $32, %esi
movq %rbx, %rdi
call cudaCreateChannelDesc@PLT
leaq 40(%rsp), %rdi
movl $0, %r8d
movl $512, %ecx
movl $1024, %edx
movq %rbx, %rsi
call cudaMallocArray@PLT
movl $7, %edi
call srand@PLT
movl $2097152, %edi
call _Znam@PLT
movq %rax, %rbp
movq %rax, (%rsp)
movl $2097152, %edi
call _Znam@PLT
movq %rax, %r12
movq %rax, 8(%rsp)
movq %rbp, %r15
leaq 2097152(%rbp), %r14
movl .LC1(%rip), %r13d
movq %rax, 16(%rsp)
.L5:
movl $0, %ebx
.L4:
call rand@PLT
cltd
shrl $22, %edx
addl %edx, %eax
andl $1023, %eax
subl %edx, %eax
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
divss .LC0(%rip), %xmm0
movss %xmm0, 0(%rbp,%rbx)
movl %r13d, (%r12,%rbx)
addq $4, %rbx
cmpq $4096, %rbx
jne .L4
addq $4096, %rbp
addq $4096, %r12
cmpq %r14, %rbp
jne .L5
movq 16(%rsp), %rbx
movl $1, %r9d
movl $2097152, %r8d
movq (%rsp), %rcx
movl $0, %edx
movl $0, %esi
movq 40(%rsp), %rdi
call cudaMemcpyToArray@PLT
movl $2, %r9d
movl $2097152, %r8d
movl $0, %ecx
movl $0, %edx
movq 40(%rsp), %rsi
movq 8(%rsp), %rdi
call cudaMemcpyFromArray@PLT
movl $0, %r12d
movl $0, %r13d
movq %r12, %r14
jmp .L10
.L6:
cmpl $4, %r13d
setle %al
addq $1, %rbp
addl $1, %r12d
cmpl $1023, %r12d
jg .L14
testb %al, %al
je .L14
.L8:
movl %ebp, %r12d
movss (%r15,%rbp,4), %xmm0
movss (%rbx,%rbp,4), %xmm1
movaps %xmm0, %xmm2
subss %xmm1, %xmm2
andps .LC2(%rip), %xmm2
comiss .LC3(%rip), %xmm2
jbe .L6
addl $1, %r13d
cmpb $0, 27(%rsp)
je .L6
cvtss2sd %xmm0, %xmm0
cvtss2sd %xmm1, %xmm1
movl 28(%rsp), %ecx
movl %ebp, %edx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $2, %eax
call __printf_chk@PLT
movq stdout(%rip), %rdi
call fflush@PLT
jmp .L6
.L14:
addq $1, %r14
addq $4096, %r15
addq $4096, %rbx
movl 16(%rsp), %ecx
addl $1, %ecx
cmpl $511, %ecx
jg .L15
testb %al, %al
je .L15
.L10:
movl %r14d, 16(%rsp)
movl %r14d, 28(%rsp)
movl $0, %ebp
jmp .L8
.L15:
movq 40(%rsp), %rdi
call cudaFreeArray@PLT
movq (%rsp), %rdi
call _ZdaPv@PLT
movq 8(%rsp), %rdi
call _ZdaPv@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L21
movl $1, %eax
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L21:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size _Z10testMemcpyb, .-_Z10testMemcpyb
.section .rodata.str1.1,"aMS",@progbits,1
.LC5:
.string "Test PASSED\n"
.LC6:
.string "Test FAILED\n"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl $1, %edi
call _Z10testMemcpyb
testb %al, %al
je .L23
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L24:
movl $0, %eax
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L24
.cfi_endproc
.LFE2058:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC0:
.long 1123680256
.align 4
.LC1:
.long -1082130432
.section .rodata.cst16,"aM",@progbits,16
.align 16
.LC2:
.long 2147483647
.long 0
.long 0
.long 0
.section .rodata.cst4
.align 4
.LC3:
.long 981668463
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /*!
\file arrays.cu
\author Andrew Kerr <arkerr@gatech.edu>
\brief tests implementation of cudaMallocArray(), among other things
\date Feb 12, 2010
*/
#include <stdlib.h>
#include <stdio.h>
//////////////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////////////
bool testMemcpy(bool verbose) {
bool passed = true;
int width = 1024, height = 512;
int errors = 0;
cudaChannelFormatDesc channel = cudaCreateChannelDesc(32, 0, 0, 0, cudaChannelFormatKindFloat);
cudaArray *cuArray;
cudaMallocArray(&cuArray, &channel, width, height);
srand(7);
size_t bytes = sizeof(float) * width * height;
float *hostSource = new float[width * height];
float *hostDest = new float[width * height];
for (int j = 0; j < height; j++) {
float *ptr = hostSource + j * width;
float *dstPtr = hostDest + j * width;
for (int i = 0; i < width; i++) {
float x = (float)( (rand() % 1024) / 125.0f);
ptr[i] = x;
dstPtr[i] = -1.0f;
}
}
cudaMemcpyToArray(cuArray, 0, 0, hostSource, bytes, cudaMemcpyHostToDevice);
cudaMemcpyFromArray(hostDest, cuArray, 0, 0, bytes, cudaMemcpyDeviceToHost);
for (int j = 0; j < height && errors < 5; j++) {
float *srcPtr = hostSource + j * width;
float *dstPtr = hostDest + j * width;
for (int i = 0; i < width && errors < 5; i++) {
float expected = srcPtr[i];
float got = dstPtr[i];
if (fabs(expected - got) > 0.001f) {
++errors;
if (verbose) {
printf("ERROR: (%d, %d) - expected %f, got %f\n", i, j, expected, got);
fflush(stdout);
}
}
}
}
cudaFreeArray(cuArray);
delete [] hostSource;
delete [] hostDest;
return passed;
}
//////////////////////////////////////////////////////////////////////////////////////////////////
int main(int argc, char *arg[]) {
bool result = testMemcpy(true);
if (result) {
printf("Test PASSED\n");
}
else {
printf("Test FAILED\n");
}
return 0;
}
////////////////////////////////////////////////////////////////////////////////////////////////// | /*!
\file arrays.cu
\author Andrew Kerr <arkerr@gatech.edu>
\brief tests implementation of cudaMallocArray(), among other things
\date Feb 12, 2010
*/
#include <hip/hip_runtime.h>
#include <stdlib.h>
#include <stdio.h>
//////////////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////////////
bool testMemcpy(bool verbose) {
bool passed = true;
int width = 1024, height = 512;
int errors = 0;
hipChannelFormatDesc channel = hipCreateChannelDesc(32, 0, 0, 0, hipChannelFormatKindFloat);
hipArray *cuArray;
hipMallocArray(&cuArray, &channel, width, height);
srand(7);
size_t bytes = sizeof(float) * width * height;
float *hostSource = new float[width * height];
float *hostDest = new float[width * height];
for (int j = 0; j < height; j++) {
float *ptr = hostSource + j * width;
float *dstPtr = hostDest + j * width;
for (int i = 0; i < width; i++) {
float x = (float)( (rand() % 1024) / 125.0f);
ptr[i] = x;
dstPtr[i] = -1.0f;
}
}
hipMemcpyToArray(cuArray, 0, 0, hostSource, bytes, hipMemcpyHostToDevice);
hipMemcpyFromArray(hostDest, cuArray, 0, 0, bytes, hipMemcpyDeviceToHost);
for (int j = 0; j < height && errors < 5; j++) {
float *srcPtr = hostSource + j * width;
float *dstPtr = hostDest + j * width;
for (int i = 0; i < width && errors < 5; i++) {
float expected = srcPtr[i];
float got = dstPtr[i];
if (fabs(expected - got) > 0.001f) {
++errors;
if (verbose) {
printf("ERROR: (%d, %d) - expected %f, got %f\n", i, j, expected, got);
fflush(stdout);
}
}
}
}
hipFreeArray(cuArray);
delete [] hostSource;
delete [] hostDest;
return passed;
}
//////////////////////////////////////////////////////////////////////////////////////////////////
int main(int argc, char *arg[]) {
bool result = testMemcpy(true);
if (result) {
printf("Test PASSED\n");
}
else {
printf("Test FAILED\n");
}
return 0;
}
////////////////////////////////////////////////////////////////////////////////////////////////// |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | /*!
\file arrays.cu
\author Andrew Kerr <arkerr@gatech.edu>
\brief tests implementation of cudaMallocArray(), among other things
\date Feb 12, 2010
*/
#include <hip/hip_runtime.h>
#include <stdlib.h>
#include <stdio.h>
//////////////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////////////
bool testMemcpy(bool verbose) {
bool passed = true;
int width = 1024, height = 512;
int errors = 0;
hipChannelFormatDesc channel = hipCreateChannelDesc(32, 0, 0, 0, hipChannelFormatKindFloat);
hipArray *cuArray;
hipMallocArray(&cuArray, &channel, width, height);
srand(7);
size_t bytes = sizeof(float) * width * height;
float *hostSource = new float[width * height];
float *hostDest = new float[width * height];
for (int j = 0; j < height; j++) {
float *ptr = hostSource + j * width;
float *dstPtr = hostDest + j * width;
for (int i = 0; i < width; i++) {
float x = (float)( (rand() % 1024) / 125.0f);
ptr[i] = x;
dstPtr[i] = -1.0f;
}
}
hipMemcpyToArray(cuArray, 0, 0, hostSource, bytes, hipMemcpyHostToDevice);
hipMemcpyFromArray(hostDest, cuArray, 0, 0, bytes, hipMemcpyDeviceToHost);
for (int j = 0; j < height && errors < 5; j++) {
float *srcPtr = hostSource + j * width;
float *dstPtr = hostDest + j * width;
for (int i = 0; i < width && errors < 5; i++) {
float expected = srcPtr[i];
float got = dstPtr[i];
if (fabs(expected - got) > 0.001f) {
++errors;
if (verbose) {
printf("ERROR: (%d, %d) - expected %f, got %f\n", i, j, expected, got);
fflush(stdout);
}
}
}
}
hipFreeArray(cuArray);
delete [] hostSource;
delete [] hostDest;
return passed;
}
//////////////////////////////////////////////////////////////////////////////////////////////////
int main(int argc, char *arg[]) {
bool result = testMemcpy(true);
if (result) {
printf("Test PASSED\n");
}
else {
printf("Test FAILED\n");
}
return 0;
}
////////////////////////////////////////////////////////////////////////////////////////////////// | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | /*!
\file arrays.cu
\author Andrew Kerr <arkerr@gatech.edu>
\brief tests implementation of cudaMallocArray(), among other things
\date Feb 12, 2010
*/
#include <hip/hip_runtime.h>
#include <stdlib.h>
#include <stdio.h>
//////////////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////////////
bool testMemcpy(bool verbose) {
bool passed = true;
int width = 1024, height = 512;
int errors = 0;
hipChannelFormatDesc channel = hipCreateChannelDesc(32, 0, 0, 0, hipChannelFormatKindFloat);
hipArray *cuArray;
hipMallocArray(&cuArray, &channel, width, height);
srand(7);
size_t bytes = sizeof(float) * width * height;
float *hostSource = new float[width * height];
float *hostDest = new float[width * height];
for (int j = 0; j < height; j++) {
float *ptr = hostSource + j * width;
float *dstPtr = hostDest + j * width;
for (int i = 0; i < width; i++) {
float x = (float)( (rand() % 1024) / 125.0f);
ptr[i] = x;
dstPtr[i] = -1.0f;
}
}
hipMemcpyToArray(cuArray, 0, 0, hostSource, bytes, hipMemcpyHostToDevice);
hipMemcpyFromArray(hostDest, cuArray, 0, 0, bytes, hipMemcpyDeviceToHost);
for (int j = 0; j < height && errors < 5; j++) {
float *srcPtr = hostSource + j * width;
float *dstPtr = hostDest + j * width;
for (int i = 0; i < width && errors < 5; i++) {
float expected = srcPtr[i];
float got = dstPtr[i];
if (fabs(expected - got) > 0.001f) {
++errors;
if (verbose) {
printf("ERROR: (%d, %d) - expected %f, got %f\n", i, j, expected, got);
fflush(stdout);
}
}
}
}
hipFreeArray(cuArray);
delete [] hostSource;
delete [] hostDest;
return passed;
}
//////////////////////////////////////////////////////////////////////////////////////////////////
int main(int argc, char *arg[]) {
bool result = testMemcpy(true);
if (result) {
printf("Test PASSED\n");
}
else {
printf("Test FAILED\n");
}
return 0;
}
////////////////////////////////////////////////////////////////////////////////////////////////// | .text
.file "arrays.hip"
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z10testMemcpyb
.LCPI0_0:
.long 0x42fa0000 # float 125
.LCPI0_2:
.long 0x3a83126f # float 0.00100000005
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0
.LCPI0_1:
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.text
.globl _Z10testMemcpyb
.p2align 4, 0x90
.type _Z10testMemcpyb,@function
_Z10testMemcpyb: # @_Z10testMemcpyb
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $56, %rsp
.cfi_def_cfa_offset 112
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %edi, %ebx
leaq 36(%rsp), %r14
xorl %r12d, %r12d
movq %r14, %rdi
movl $32, %esi
xorl %edx, %edx
xorl %ecx, %ecx
xorl %r8d, %r8d
movl $2, %r9d
callq hipCreateChannelDesc
leaq 8(%rsp), %rdi
movl $1024, %edx # imm = 0x400
movl $512, %ecx # imm = 0x200
movq %r14, %rsi
xorl %r8d, %r8d
callq hipMallocArray
movl $7, %edi
callq srand
movl $2097152, %edi # imm = 0x200000
callq _Znam
movq %rax, %rbp
movl $2097152, %edi # imm = 0x200000
callq _Znam
movq %rbp, %r14
movq %rax, 16(%rsp) # 8-byte Spill
movq %rax, %r15
.p2align 4, 0x90
.LBB0_1: # =>This Loop Header: Depth=1
# Child Loop BB0_2 Depth 2
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB0_2: # Parent Loop BB0_1 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
movss .LCPI0_0(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
# kill: def $eax killed $eax def $rax
leal 1023(%rax), %ecx
testl %eax, %eax
cmovnsl %eax, %ecx
andl $-1024, %ecx # imm = 0xFC00
subl %ecx, %eax
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
divss %xmm1, %xmm0
movss %xmm0, (%r14,%r13,4)
movl $-1082130432, (%r15,%r13,4) # imm = 0xBF800000
incq %r13
cmpq $1024, %r13 # imm = 0x400
jne .LBB0_2
# %bb.3: # in Loop: Header=BB0_1 Depth=1
incq %r12
addq $4096, %r15 # imm = 0x1000
addq $4096, %r14 # imm = 0x1000
cmpq $512, %r12 # imm = 0x200
jne .LBB0_1
# %bb.4:
movq 8(%rsp), %rdi
xorl %r12d, %r12d
movl $2097152, %r8d # imm = 0x200000
xorl %esi, %esi
xorl %edx, %edx
movq %rbp, %rcx
movl $1, %r9d
callq hipMemcpyToArray
movq 8(%rsp), %rsi
movl $2097152, %r8d # imm = 0x200000
movq 16(%rsp), %r15 # 8-byte Reload
movq %r15, %rdi
xorl %edx, %edx
xorl %ecx, %ecx
movl $2, %r9d
callq hipMemcpyFromArray
movaps .LCPI0_1(%rip), %xmm3 # xmm3 = [NaN,NaN,NaN,NaN]
movss .LCPI0_2(%rip), %xmm4 # xmm4 = mem[0],zero,zero,zero
movq %rbp, 24(%rsp) # 8-byte Spill
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB0_5: # =>This Loop Header: Depth=1
# Child Loop BB0_6 Depth 2
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB0_6: # Parent Loop BB0_5 Depth=1
# => This Inner Loop Header: Depth=2
movss (%rbp,%r13,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
movss (%r15,%r13,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
movaps %xmm0, %xmm2
subss %xmm1, %xmm2
andps %xmm3, %xmm2
ucomiss %xmm4, %xmm2
jbe .LBB0_9
# %bb.7: # in Loop: Header=BB0_6 Depth=2
incl %r14d
testb %bl, %bl
je .LBB0_9
# %bb.8: # in Loop: Header=BB0_6 Depth=2
cvtss2sd %xmm0, %xmm0
cvtss2sd %xmm1, %xmm1
movl $.L.str, %edi
movl %r13d, %esi
movl %r12d, %edx
movb $2, %al
callq printf
movq stdout(%rip), %rdi
callq fflush
movss .LCPI0_2(%rip), %xmm4 # xmm4 = mem[0],zero,zero,zero
movaps .LCPI0_1(%rip), %xmm3 # xmm3 = [NaN,NaN,NaN,NaN]
.LBB0_9: # in Loop: Header=BB0_6 Depth=2
cmpq $1022, %r13 # imm = 0x3FE
ja .LBB0_10
# %bb.13: # in Loop: Header=BB0_6 Depth=2
incq %r13
cmpl $5, %r14d
jl .LBB0_6
.LBB0_10: # in Loop: Header=BB0_5 Depth=1
cmpq $510, %r12 # imm = 0x1FE
ja .LBB0_12
# %bb.11: # in Loop: Header=BB0_5 Depth=1
incq %r12
addq $4096, %r15 # imm = 0x1000
addq $4096, %rbp # imm = 0x1000
cmpl $5, %r14d
jl .LBB0_5
.LBB0_12:
movq 8(%rsp), %rdi
callq hipFreeArray
movq 24(%rsp), %rdi # 8-byte Reload
callq _ZdaPv
movq 16(%rsp), %rdi # 8-byte Reload
callq _ZdaPv
movb $1, %al
addq $56, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z10testMemcpyb, .Lfunc_end0-_Z10testMemcpyb
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
movl $1, %edi
callq _Z10testMemcpyb
movl $.Lstr, %edi
callq puts@PLT
xorl %eax, %eax
popq %rcx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "ERROR: (%d, %d) - expected %f, got %f\n"
.size .L.str, 39
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Test PASSED"
.size .Lstr, 12
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00054818_00000000-6_arrays.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC4:
.string "ERROR: (%d, %d) - expected %f, got %f\n"
.text
.globl _Z10testMemcpyb
.type _Z10testMemcpyb, @function
_Z10testMemcpyb:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $88, %rsp
.cfi_def_cfa_offset 144
movb %dil, 27(%rsp)
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
leaq 48(%rsp), %rbx
movl $2, %r9d
movl $0, %r8d
movl $0, %ecx
movl $0, %edx
movl $32, %esi
movq %rbx, %rdi
call cudaCreateChannelDesc@PLT
leaq 40(%rsp), %rdi
movl $0, %r8d
movl $512, %ecx
movl $1024, %edx
movq %rbx, %rsi
call cudaMallocArray@PLT
movl $7, %edi
call srand@PLT
movl $2097152, %edi
call _Znam@PLT
movq %rax, %rbp
movq %rax, (%rsp)
movl $2097152, %edi
call _Znam@PLT
movq %rax, %r12
movq %rax, 8(%rsp)
movq %rbp, %r15
leaq 2097152(%rbp), %r14
movl .LC1(%rip), %r13d
movq %rax, 16(%rsp)
.L5:
movl $0, %ebx
.L4:
call rand@PLT
cltd
shrl $22, %edx
addl %edx, %eax
andl $1023, %eax
subl %edx, %eax
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
divss .LC0(%rip), %xmm0
movss %xmm0, 0(%rbp,%rbx)
movl %r13d, (%r12,%rbx)
addq $4, %rbx
cmpq $4096, %rbx
jne .L4
addq $4096, %rbp
addq $4096, %r12
cmpq %r14, %rbp
jne .L5
movq 16(%rsp), %rbx
movl $1, %r9d
movl $2097152, %r8d
movq (%rsp), %rcx
movl $0, %edx
movl $0, %esi
movq 40(%rsp), %rdi
call cudaMemcpyToArray@PLT
movl $2, %r9d
movl $2097152, %r8d
movl $0, %ecx
movl $0, %edx
movq 40(%rsp), %rsi
movq 8(%rsp), %rdi
call cudaMemcpyFromArray@PLT
movl $0, %r12d
movl $0, %r13d
movq %r12, %r14
jmp .L10
.L6:
cmpl $4, %r13d
setle %al
addq $1, %rbp
addl $1, %r12d
cmpl $1023, %r12d
jg .L14
testb %al, %al
je .L14
.L8:
movl %ebp, %r12d
movss (%r15,%rbp,4), %xmm0
movss (%rbx,%rbp,4), %xmm1
movaps %xmm0, %xmm2
subss %xmm1, %xmm2
andps .LC2(%rip), %xmm2
comiss .LC3(%rip), %xmm2
jbe .L6
addl $1, %r13d
cmpb $0, 27(%rsp)
je .L6
cvtss2sd %xmm0, %xmm0
cvtss2sd %xmm1, %xmm1
movl 28(%rsp), %ecx
movl %ebp, %edx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $2, %eax
call __printf_chk@PLT
movq stdout(%rip), %rdi
call fflush@PLT
jmp .L6
.L14:
addq $1, %r14
addq $4096, %r15
addq $4096, %rbx
movl 16(%rsp), %ecx
addl $1, %ecx
cmpl $511, %ecx
jg .L15
testb %al, %al
je .L15
.L10:
movl %r14d, 16(%rsp)
movl %r14d, 28(%rsp)
movl $0, %ebp
jmp .L8
.L15:
movq 40(%rsp), %rdi
call cudaFreeArray@PLT
movq (%rsp), %rdi
call _ZdaPv@PLT
movq 8(%rsp), %rdi
call _ZdaPv@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L21
movl $1, %eax
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L21:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size _Z10testMemcpyb, .-_Z10testMemcpyb
.section .rodata.str1.1,"aMS",@progbits,1
.LC5:
.string "Test PASSED\n"
.LC6:
.string "Test FAILED\n"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl $1, %edi
call _Z10testMemcpyb
testb %al, %al
je .L23
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L24:
movl $0, %eax
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L24
.cfi_endproc
.LFE2058:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC0:
.long 1123680256
.align 4
.LC1:
.long -1082130432
.section .rodata.cst16,"aM",@progbits,16
.align 16
.LC2:
.long 2147483647
.long 0
.long 0
.long 0
.section .rodata.cst4
.align 4
.LC3:
.long 981668463
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "arrays.hip"
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z10testMemcpyb
.LCPI0_0:
.long 0x42fa0000 # float 125
.LCPI0_2:
.long 0x3a83126f # float 0.00100000005
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0
.LCPI0_1:
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.text
.globl _Z10testMemcpyb
.p2align 4, 0x90
.type _Z10testMemcpyb,@function
_Z10testMemcpyb: # @_Z10testMemcpyb
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $56, %rsp
.cfi_def_cfa_offset 112
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %edi, %ebx
leaq 36(%rsp), %r14
xorl %r12d, %r12d
movq %r14, %rdi
movl $32, %esi
xorl %edx, %edx
xorl %ecx, %ecx
xorl %r8d, %r8d
movl $2, %r9d
callq hipCreateChannelDesc
leaq 8(%rsp), %rdi
movl $1024, %edx # imm = 0x400
movl $512, %ecx # imm = 0x200
movq %r14, %rsi
xorl %r8d, %r8d
callq hipMallocArray
movl $7, %edi
callq srand
movl $2097152, %edi # imm = 0x200000
callq _Znam
movq %rax, %rbp
movl $2097152, %edi # imm = 0x200000
callq _Znam
movq %rbp, %r14
movq %rax, 16(%rsp) # 8-byte Spill
movq %rax, %r15
.p2align 4, 0x90
.LBB0_1: # =>This Loop Header: Depth=1
# Child Loop BB0_2 Depth 2
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB0_2: # Parent Loop BB0_1 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
movss .LCPI0_0(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
# kill: def $eax killed $eax def $rax
leal 1023(%rax), %ecx
testl %eax, %eax
cmovnsl %eax, %ecx
andl $-1024, %ecx # imm = 0xFC00
subl %ecx, %eax
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
divss %xmm1, %xmm0
movss %xmm0, (%r14,%r13,4)
movl $-1082130432, (%r15,%r13,4) # imm = 0xBF800000
incq %r13
cmpq $1024, %r13 # imm = 0x400
jne .LBB0_2
# %bb.3: # in Loop: Header=BB0_1 Depth=1
incq %r12
addq $4096, %r15 # imm = 0x1000
addq $4096, %r14 # imm = 0x1000
cmpq $512, %r12 # imm = 0x200
jne .LBB0_1
# %bb.4:
movq 8(%rsp), %rdi
xorl %r12d, %r12d
movl $2097152, %r8d # imm = 0x200000
xorl %esi, %esi
xorl %edx, %edx
movq %rbp, %rcx
movl $1, %r9d
callq hipMemcpyToArray
movq 8(%rsp), %rsi
movl $2097152, %r8d # imm = 0x200000
movq 16(%rsp), %r15 # 8-byte Reload
movq %r15, %rdi
xorl %edx, %edx
xorl %ecx, %ecx
movl $2, %r9d
callq hipMemcpyFromArray
movaps .LCPI0_1(%rip), %xmm3 # xmm3 = [NaN,NaN,NaN,NaN]
movss .LCPI0_2(%rip), %xmm4 # xmm4 = mem[0],zero,zero,zero
movq %rbp, 24(%rsp) # 8-byte Spill
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB0_5: # =>This Loop Header: Depth=1
# Child Loop BB0_6 Depth 2
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB0_6: # Parent Loop BB0_5 Depth=1
# => This Inner Loop Header: Depth=2
movss (%rbp,%r13,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
movss (%r15,%r13,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
movaps %xmm0, %xmm2
subss %xmm1, %xmm2
andps %xmm3, %xmm2
ucomiss %xmm4, %xmm2
jbe .LBB0_9
# %bb.7: # in Loop: Header=BB0_6 Depth=2
incl %r14d
testb %bl, %bl
je .LBB0_9
# %bb.8: # in Loop: Header=BB0_6 Depth=2
cvtss2sd %xmm0, %xmm0
cvtss2sd %xmm1, %xmm1
movl $.L.str, %edi
movl %r13d, %esi
movl %r12d, %edx
movb $2, %al
callq printf
movq stdout(%rip), %rdi
callq fflush
movss .LCPI0_2(%rip), %xmm4 # xmm4 = mem[0],zero,zero,zero
movaps .LCPI0_1(%rip), %xmm3 # xmm3 = [NaN,NaN,NaN,NaN]
.LBB0_9: # in Loop: Header=BB0_6 Depth=2
cmpq $1022, %r13 # imm = 0x3FE
ja .LBB0_10
# %bb.13: # in Loop: Header=BB0_6 Depth=2
incq %r13
cmpl $5, %r14d
jl .LBB0_6
.LBB0_10: # in Loop: Header=BB0_5 Depth=1
cmpq $510, %r12 # imm = 0x1FE
ja .LBB0_12
# %bb.11: # in Loop: Header=BB0_5 Depth=1
incq %r12
addq $4096, %r15 # imm = 0x1000
addq $4096, %rbp # imm = 0x1000
cmpl $5, %r14d
jl .LBB0_5
.LBB0_12:
movq 8(%rsp), %rdi
callq hipFreeArray
movq 24(%rsp), %rdi # 8-byte Reload
callq _ZdaPv
movq 16(%rsp), %rdi # 8-byte Reload
callq _ZdaPv
movb $1, %al
addq $56, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z10testMemcpyb, .Lfunc_end0-_Z10testMemcpyb
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
movl $1, %edi
callq _Z10testMemcpyb
movl $.Lstr, %edi
callq puts@PLT
xorl %eax, %eax
popq %rcx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "ERROR: (%d, %d) - expected %f, got %f\n"
.size .L.str, 39
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Test PASSED"
.size .Lstr, 12
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
//VERSION 0.8 MODIFIED 10/25/16 12:34 by Jack
// The number of threads per blocks in the kernel
// (if we define it here, then we can use its value in the kernel,
// for example to statically declare an array in shared memory)
const int threads_per_block = 256;
// Forward function declarations
float GPU_vector_max(float *A, int N, int kernel_code, float *kernel_time, float *transfer_time);
float CPU_vector_max(float *A, int N);
float *get_random_vector(int N);
float *get_increasing_vector(int N);
float usToSec(long long time);
long long start_timer();
long long stop_timer(long long start_time, const char *name);
void die(const char *message);
void checkError();
// Main program
__global__ void vector_max_kernel(float *in, float *out, int N) {
// Determine the "flattened" block id and thread id
int block_id = blockIdx.x + gridDim.x * blockIdx.y;
int thread_id = blockDim.x * block_id + threadIdx.x;
// A single "lead" thread in each block finds the maximum value over a range of size threads_per_block
float max = 0.0;
if (threadIdx.x == 0) {
//calculate out of bounds guard
//our block size will be 256, but our vector may not be a multiple of 256!
int end = threads_per_block;
if(thread_id + threads_per_block > N)
end = N - thread_id;
//grab the lead thread's value
max = in[thread_id];
//grab values from all other threads' locations
for(int i = 1; i < end; i++) {
//if larger, replace
if(max < in[thread_id + i])
max = in[thread_id + i];
}
out[block_id] = max;
}
} | code for sm_80
Function : _Z17vector_max_kernelPfS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e280000002100 */
/*0020*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e680000002600 */
/*0030*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e620000002500 */
/*0040*/ ISETP.NE.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x001fe20003f05270 */
/*0050*/ IMAD R0, R0, c[0x0][0xc], R3 ; /* 0x0000030000007a24 */
/* 0x002fd800078e0203 */
/*0060*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0070*/ IMAD R6, R0, c[0x0][0x0], RZ ; /* 0x0000000000067a24 */
/* 0x000fe200078e02ff */
/*0080*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0090*/ IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; /* 0x00000004ff057424 */
/* 0x000fc600078e00ff */
/*00a0*/ IADD3 R7, R6.reuse, 0x100, RZ ; /* 0x0000010006077810 */
/* 0x040fe20007ffe0ff */
/*00b0*/ IMAD.WIDE R2, R6.reuse, R5, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x040fe200078e0205 */
/*00c0*/ IADD3 R8, -R6, c[0x0][0x170], RZ ; /* 0x00005c0006087a10 */
/* 0x000fe40007ffe1ff */
/*00d0*/ ISETP.GT.AND P0, PT, R7, c[0x0][0x170], PT ; /* 0x00005c0007007a0c */
/* 0x000fe40003f04270 */
/*00e0*/ LDG.E R4, [R2.64] ; /* 0x0000000402047981 */
/* 0x000164000c1e1900 */
/*00f0*/ SEL R10, R8, 0x100, P0 ; /* 0x00000100080a7807 */
/* 0x000fc80000000000 */
/*0100*/ ISETP.GE.AND P0, PT, R10, 0x2, PT ; /* 0x000000020a00780c */
/* 0x000fda0003f06270 */
/*0110*/ @!P0 BRA 0xa00 ; /* 0x000008e000008947 */
/* 0x000fea0003800000 */
/*0120*/ IADD3 R2, R10.reuse, -0x2, RZ ; /* 0xfffffffe0a027810 */
/* 0x041fe20007ffe0ff */
/*0130*/ IMAD.MOV.U32 R9, RZ, RZ, 0x1 ; /* 0x00000001ff097424 */
/* 0x000fe200078e00ff */
/*0140*/ IADD3 R7, R10, -0x1, RZ ; /* 0xffffffff0a077810 */
/* 0x000fe40007ffe0ff */
/*0150*/ ISETP.GE.U32.AND P0, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fe40003f06070 */
/*0160*/ SHF.R.S32.HI R8, RZ, 0x1f, R6 ; /* 0x0000001fff087819 */
/* 0x000fe40000011406 */
/*0170*/ LOP3.LUT R7, R7, 0x3, RZ, 0xc0, !PT ; /* 0x0000000307077812 */
/* 0x000fd200078ec0ff */
/*0180*/ @!P0 BRA 0x910 ; /* 0x0000078000008947 */
/* 0x000fea0003800000 */
/*0190*/ LEA R2, P0, R6, c[0x0][0x160], 0x2 ; /* 0x0000580006027a11 */
/* 0x000fe200078010ff */
/*01a0*/ IMAD.IADD R10, R10, 0x1, -R7 ; /* 0x000000010a0a7824 */
/* 0x000fe400078e0a07 */
/*01b0*/ IMAD.MOV.U32 R9, RZ, RZ, 0x1 ; /* 0x00000001ff097424 */
/* 0x000fe200078e00ff */
/*01c0*/ LEA.HI.X R3, R6, c[0x0][0x164], R8, 0x2, P0 ; /* 0x0000590006037a11 */
/* 0x000fe400000f1408 */
/*01d0*/ ISETP.GT.AND P0, PT, R10, 0x1, PT ; /* 0x000000010a00780c */
/* 0x000fe40003f04270 */
/*01e0*/ IADD3 R2, P1, R2, 0x10, RZ ; /* 0x0000001002027810 */
/* 0x000fca0007f3e0ff */
/*01f0*/ IMAD.X R3, RZ, RZ, R3, P1 ; /* 0x000000ffff037224 */
/* 0x000fcc00008e0603 */
/*0200*/ @!P0 BRA 0x7e0 ; /* 0x000005d000008947 */
/* 0x000fea0003800000 */
/*0210*/ IADD3 R11, R10, -0x1, RZ ; /* 0xffffffff0a0b7810 */
/* 0x000fe40007ffe0ff */
/*0220*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0f070 */
/*0230*/ ISETP.GT.AND P1, PT, R11, 0xc, PT ; /* 0x0000000c0b00780c */
/* 0x000fda0003f24270 */
/*0240*/ @!P1 BRA 0x5c0 ; /* 0x0000037000009947 */
/* 0x000fea0003800000 */
/*0250*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0260*/ LDG.E R23, [R2.64+-0xc] ; /* 0xfffff40402177981 */
/* 0x0000a8000c1e1900 */
/*0270*/ LDG.E R25, [R2.64+-0x8] ; /* 0xfffff80402197981 */
/* 0x0000e8000c1e1900 */
/*0280*/ LDG.E R27, [R2.64+-0x4] ; /* 0xfffffc04021b7981 */
/* 0x000128000c1e1900 */
/*0290*/ LDG.E R29, [R2.64] ; /* 0x00000004021d7981 */
/* 0x000128000c1e1900 */
/*02a0*/ LDG.E R22, [R2.64+0x4] ; /* 0x0000040402167981 */
/* 0x000128000c1e1900 */
/*02b0*/ LDG.E R21, [R2.64+0x8] ; /* 0x0000080402157981 */
/* 0x000128000c1e1900 */
/*02c0*/ LDG.E R20, [R2.64+0xc] ; /* 0x00000c0402147981 */
/* 0x000128000c1e1900 */
/*02d0*/ LDG.E R19, [R2.64+0x10] ; /* 0x0000100402137981 */
/* 0x000128000c1e1900 */
/*02e0*/ LDG.E R18, [R2.64+0x14] ; /* 0x0000140402127981 */
/* 0x000128000c1e1900 */
/*02f0*/ LDG.E R17, [R2.64+0x18] ; /* 0x0000180402117981 */
/* 0x000128000c1e1900 */
/*0300*/ LDG.E R16, [R2.64+0x1c] ; /* 0x00001c0402107981 */
/* 0x000128000c1e1900 */
/*0310*/ LDG.E R15, [R2.64+0x20] ; /* 0x00002004020f7981 */
/* 0x000128000c1e1900 */
/*0320*/ LDG.E R14, [R2.64+0x24] ; /* 0x00002404020e7981 */
/* 0x000128000c1e1900 */
/*0330*/ LDG.E R13, [R2.64+0x28] ; /* 0x00002804020d7981 */
/* 0x000128000c1e1900 */
/*0340*/ LDG.E R12, [R2.64+0x2c] ; /* 0x00002c04020c7981 */
/* 0x000128000c1e1900 */
/*0350*/ LDG.E R11, [R2.64+0x30] ; /* 0x00003004020b7981 */
/* 0x000122000c1e1900 */
/*0360*/ IADD3 R10, R10, -0x10, RZ ; /* 0xfffffff00a0a7810 */
/* 0x000fc40007ffe0ff */
/*0370*/ IADD3 R9, R9, 0x10, RZ ; /* 0x0000001009097810 */
/* 0x000fe40007ffe0ff */
/*0380*/ ISETP.GT.AND P2, PT, R10, 0xd, PT ; /* 0x0000000d0a00780c */
/* 0x000fe40003f44270 */
/*0390*/ IADD3 R2, P3, R2, 0x40, RZ ; /* 0x0000004002027810 */
/* 0x001fca0007f7e0ff */
/*03a0*/ IMAD.X R3, RZ, RZ, R3, P3 ; /* 0x000000ffff037224 */
/* 0x000fe200018e0603 */
/*03b0*/ FSETP.GEU.AND P1, PT, R4, R23, PT ; /* 0x000000170400720b */
/* 0x024fc80003f2e000 */
/*03c0*/ FSEL R4, R23, R4, !P1 ; /* 0x0000000417047208 */
/* 0x000fc80004800000 */
/*03d0*/ FSETP.GEU.AND P1, PT, R4, R25, PT ; /* 0x000000190400720b */
/* 0x008fc80003f2e000 */
/*03e0*/ FSEL R4, R25, R4, !P1 ; /* 0x0000000419047208 */
/* 0x000fc80004800000 */
/*03f0*/ FSETP.GEU.AND P1, PT, R4, R27, PT ; /* 0x0000001b0400720b */
/* 0x010fc80003f2e000 */
/*0400*/ FSEL R4, R27, R4, !P1 ; /* 0x000000041b047208 */
/* 0x000fc80004800000 */
/*0410*/ FSETP.GEU.AND P1, PT, R4, R29, PT ; /* 0x0000001d0400720b */
/* 0x000fc80003f2e000 */
/*0420*/ FSEL R29, R29, R4, !P1 ; /* 0x000000041d1d7208 */
/* 0x000fc80004800000 */
/*0430*/ FSETP.GEU.AND P1, PT, R29, R22, PT ; /* 0x000000161d00720b */
/* 0x000fc80003f2e000 */
/*0440*/ FSEL R22, R22, R29, !P1 ; /* 0x0000001d16167208 */
/* 0x000fc80004800000 */
/*0450*/ FSETP.GEU.AND P1, PT, R22, R21, PT ; /* 0x000000151600720b */
/* 0x000fc80003f2e000 */
/*0460*/ FSEL R21, R21, R22, !P1 ; /* 0x0000001615157208 */
/* 0x000fc80004800000 */
/*0470*/ FSETP.GEU.AND P1, PT, R21, R20, PT ; /* 0x000000141500720b */
/* 0x000fc80003f2e000 */
/*0480*/ FSEL R20, R20, R21, !P1 ; /* 0x0000001514147208 */
/* 0x000fc80004800000 */
/*0490*/ FSETP.GEU.AND P1, PT, R20, R19, PT ; /* 0x000000131400720b */
/* 0x000fc80003f2e000 */
/*04a0*/ FSEL R19, R19, R20, !P1 ; /* 0x0000001413137208 */
/* 0x000fc80004800000 */
/*04b0*/ FSETP.GEU.AND P1, PT, R19, R18, PT ; /* 0x000000121300720b */
/* 0x000fc80003f2e000 */
/*04c0*/ FSEL R18, R18, R19, !P1 ; /* 0x0000001312127208 */
/* 0x000fc80004800000 */
/*04d0*/ FSETP.GEU.AND P1, PT, R18, R17, PT ; /* 0x000000111200720b */
/* 0x000fc80003f2e000 */
/*04e0*/ FSEL R17, R17, R18, !P1 ; /* 0x0000001211117208 */
/* 0x000fc80004800000 */
/*04f0*/ FSETP.GEU.AND P1, PT, R17, R16, PT ; /* 0x000000101100720b */
/* 0x000fc80003f2e000 */
/*0500*/ FSEL R16, R16, R17, !P1 ; /* 0x0000001110107208 */
/* 0x000fc80004800000 */
/*0510*/ FSETP.GEU.AND P1, PT, R16, R15, PT ; /* 0x0000000f1000720b */
/* 0x000fc80003f2e000 */
/*0520*/ FSEL R15, R15, R16, !P1 ; /* 0x000000100f0f7208 */
/* 0x000fc80004800000 */
/*0530*/ FSETP.GEU.AND P1, PT, R15, R14, PT ; /* 0x0000000e0f00720b */
/* 0x000fc80003f2e000 */
/*0540*/ FSEL R14, R14, R15, !P1 ; /* 0x0000000f0e0e7208 */
/* 0x000fc80004800000 */
/*0550*/ FSETP.GEU.AND P1, PT, R14, R13, PT ; /* 0x0000000d0e00720b */
/* 0x000fc80003f2e000 */
/*0560*/ FSEL R13, R13, R14, !P1 ; /* 0x0000000e0d0d7208 */
/* 0x000fc80004800000 */
/*0570*/ FSETP.GEU.AND P1, PT, R13, R12, PT ; /* 0x0000000c0d00720b */
/* 0x000fc80003f2e000 */
/*0580*/ FSEL R4, R12, R13, !P1 ; /* 0x0000000d0c047208 */
/* 0x000fc80004800000 */
/*0590*/ FSETP.GEU.AND P1, PT, R4, R11, PT ; /* 0x0000000b0400720b */
/* 0x000fc80003f2e000 */
/*05a0*/ FSEL R4, R11, R4, !P1 ; /* 0x000000040b047208 */
/* 0x000fe20004800000 */
/*05b0*/ @P2 BRA 0x260 ; /* 0xfffffca000002947 */
/* 0x000fea000383ffff */
/*05c0*/ IADD3 R11, R10, -0x1, RZ ; /* 0xffffffff0a0b7810 */
/* 0x000fc80007ffe0ff */
/*05d0*/ ISETP.GT.AND P1, PT, R11, 0x4, PT ; /* 0x000000040b00780c */
/* 0x000fda0003f24270 */
/*05e0*/ @!P1 BRA 0x7c0 ; /* 0x000001d000009947 */
/* 0x000fea0003800000 */
/*05f0*/ LDG.E R11, [R2.64+-0xc] ; /* 0xfffff404020b7981 */
/* 0x0000a8000c1e1900 */
/*0600*/ LDG.E R13, [R2.64+-0x8] ; /* 0xfffff804020d7981 */
/* 0x0000e8000c1e1900 */
/*0610*/ LDG.E R15, [R2.64+-0x4] ; /* 0xfffffc04020f7981 */
/* 0x000128000c1e1900 */
/*0620*/ LDG.E R17, [R2.64] ; /* 0x0000000402117981 */
/* 0x000128000c1e1900 */
/*0630*/ LDG.E R19, [R2.64+0x4] ; /* 0x0000040402137981 */
/* 0x000128000c1e1900 */
/*0640*/ LDG.E R21, [R2.64+0x8] ; /* 0x0000080402157981 */
/* 0x000128000c1e1900 */
/*0650*/ LDG.E R23, [R2.64+0xc] ; /* 0x00000c0402177981 */
/* 0x000128000c1e1900 */
/*0660*/ LDG.E R25, [R2.64+0x10] ; /* 0x0000100402197981 */
/* 0x000122000c1e1900 */
/*0670*/ IADD3 R9, R9, 0x8, RZ ; /* 0x0000000809097810 */
/* 0x000fc40007ffe0ff */
/*0680*/ IADD3 R10, R10, -0x8, RZ ; /* 0xfffffff80a0a7810 */
/* 0x000fe40007ffe0ff */
/*0690*/ IADD3 R2, P2, R2, 0x20, RZ ; /* 0x0000002002027810 */
/* 0x001fca0007f5e0ff */
/*06a0*/ IMAD.X R3, RZ, RZ, R3, P2 ; /* 0x000000ffff037224 */
/* 0x000fe200010e0603 */
/*06b0*/ FSETP.GEU.AND P0, PT, R4, R11, PT ; /* 0x0000000b0400720b */
/* 0x024fc80003f0e000 */
/*06c0*/ FSEL R4, R11, R4, !P0 ; /* 0x000000040b047208 */
/* 0x000fc80004000000 */
/*06d0*/ FSETP.GEU.AND P0, PT, R4, R13, PT ; /* 0x0000000d0400720b */
/* 0x008fc80003f0e000 */
/*06e0*/ FSEL R4, R13, R4, !P0 ; /* 0x000000040d047208 */
/* 0x000fc80004000000 */
/*06f0*/ FSETP.GEU.AND P0, PT, R4, R15, PT ; /* 0x0000000f0400720b */
/* 0x010fc80003f0e000 */
/*0700*/ FSEL R4, R15, R4, !P0 ; /* 0x000000040f047208 */
/* 0x000fc80004000000 */
/*0710*/ FSETP.GEU.AND P0, PT, R4, R17, PT ; /* 0x000000110400720b */
/* 0x000fc80003f0e000 */
/*0720*/ FSEL R4, R17, R4, !P0 ; /* 0x0000000411047208 */
/* 0x000fc80004000000 */
/*0730*/ FSETP.GEU.AND P0, PT, R4, R19, PT ; /* 0x000000130400720b */
/* 0x000fc80003f0e000 */
/*0740*/ FSEL R4, R19, R4, !P0 ; /* 0x0000000413047208 */
/* 0x000fc80004000000 */
/*0750*/ FSETP.GEU.AND P0, PT, R4, R21, PT ; /* 0x000000150400720b */
/* 0x000fc80003f0e000 */
/*0760*/ FSEL R4, R21, R4, !P0 ; /* 0x0000000415047208 */
/* 0x000fc80004000000 */
/*0770*/ FSETP.GEU.AND P0, PT, R4, R23, PT ; /* 0x000000170400720b */
/* 0x000fc80003f0e000 */
/*0780*/ FSEL R4, R23, R4, !P0 ; /* 0x0000000417047208 */
/* 0x000fe40004000000 */
/*0790*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*07a0*/ FSETP.GEU.AND P1, PT, R4, R25, PT ; /* 0x000000190400720b */
/* 0x000fc80003f2e000 */
/*07b0*/ FSEL R4, R25, R4, !P1 ; /* 0x0000000419047208 */
/* 0x000fe40004800000 */
/*07c0*/ ISETP.NE.OR P0, PT, R10, 0x1, P0 ; /* 0x000000010a00780c */
/* 0x000fda0000705670 */
/*07d0*/ @!P0 BRA 0x910 ; /* 0x0000013000008947 */
/* 0x000fea0003800000 */
/*07e0*/ LDG.E R11, [R2.64+-0xc] ; /* 0xfffff404020b7981 */
/* 0x000ea8000c1e1900 */
/*07f0*/ LDG.E R13, [R2.64+-0x8] ; /* 0xfffff804020d7981 */
/* 0x000ee8000c1e1900 */
/*0800*/ LDG.E R15, [R2.64+-0x4] ; /* 0xfffffc04020f7981 */
/* 0x000128000c1e1900 */
/*0810*/ LDG.E R17, [R2.64] ; /* 0x0000000402117981 */
/* 0x000122000c1e1900 */
/*0820*/ IADD3 R10, R10, -0x4, RZ ; /* 0xfffffffc0a0a7810 */
/* 0x000fc40007ffe0ff */
/*0830*/ IADD3 R9, R9, 0x4, RZ ; /* 0x0000000409097810 */
/* 0x000fe40007ffe0ff */
/*0840*/ ISETP.NE.AND P1, PT, R10, 0x1, PT ; /* 0x000000010a00780c */
/* 0x000fe40003f25270 */
/*0850*/ FSETP.GEU.AND P0, PT, R4, R11, PT ; /* 0x0000000b0400720b */
/* 0x024fc80003f0e000 */
/*0860*/ FSEL R4, R11, R4, !P0 ; /* 0x000000040b047208 */
/* 0x000fe40004000000 */
/*0870*/ IADD3 R11, P2, R2, 0x10, RZ ; /* 0x00000010020b7810 */
/* 0x000fe40007f5e0ff */
/*0880*/ FSETP.GEU.AND P0, PT, R4, R13, PT ; /* 0x0000000d0400720b */
/* 0x008fc60003f0e000 */
/*0890*/ IMAD.X R3, RZ, RZ, R3, P2 ; /* 0x000000ffff037224 */
/* 0x001fe200010e0603 */
/*08a0*/ FSEL R4, R13, R4, !P0 ; /* 0x000000040d047208 */
/* 0x000fe20004000000 */
/*08b0*/ IMAD.MOV.U32 R2, RZ, RZ, R11 ; /* 0x000000ffff027224 */
/* 0x000fc600078e000b */
/*08c0*/ FSETP.GEU.AND P0, PT, R4, R15, PT ; /* 0x0000000f0400720b */
/* 0x010fc80003f0e000 */
/*08d0*/ FSEL R4, R15, R4, !P0 ; /* 0x000000040f047208 */
/* 0x000fc80004000000 */
/*08e0*/ FSETP.GEU.AND P0, PT, R4, R17, PT ; /* 0x000000110400720b */
/* 0x000fc80003f0e000 */
/*08f0*/ FSEL R4, R17, R4, !P0 ; /* 0x0000000411047208 */
/* 0x000fe20004000000 */
/*0900*/ @P1 BRA 0x7e0 ; /* 0xfffffed000001947 */
/* 0x000fea000383ffff */
/*0910*/ ISETP.NE.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fda0003f05270 */
/*0920*/ @!P0 BRA 0xa00 ; /* 0x000000d000008947 */
/* 0x000fea0003800000 */
/*0930*/ IADD3 R6, P0, R6, R9, RZ ; /* 0x0000000906067210 */
/* 0x000fc80007f1e0ff */
/*0940*/ LEA R2, P1, R6, c[0x0][0x160], 0x2 ; /* 0x0000580006027a11 */
/* 0x000fe400078210ff */
/*0950*/ LEA.HI.X.SX32 R9, R9, R8, 0x1, P0 ; /* 0x0000000809097211 */
/* 0x000fc800000f0eff */
/*0960*/ LEA.HI.X R9, R6, c[0x0][0x164], R9, 0x2, P1 ; /* 0x0000590006097a11 */
/* 0x000fca00008f1409 */
/*0970*/ IMAD.MOV.U32 R3, RZ, RZ, R9 ; /* 0x000000ffff037224 */
/* 0x000fcc00078e0009 */
/*0980*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x0000a2000c1e1900 */
/*0990*/ IADD3 R7, R7, -0x1, RZ ; /* 0xffffffff07077810 */
/* 0x000fc80007ffe0ff */
/*09a0*/ ISETP.NE.AND P1, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fe40003f25270 */
/*09b0*/ IADD3 R2, P2, R2, 0x4, RZ ; /* 0x0000000402027810 */
/* 0x001fca0007f5e0ff */
/*09c0*/ IMAD.X R9, RZ, RZ, R9, P2 ; /* 0x000000ffff097224 */
/* 0x000fe200010e0609 */
/*09d0*/ FSETP.GEU.AND P0, PT, R4, R3, PT ; /* 0x000000030400720b */
/* 0x024fc80003f0e000 */
/*09e0*/ FSEL R4, R3, R4, !P0 ; /* 0x0000000403047208 */
/* 0x000fe20004000000 */
/*09f0*/ @P1 BRA 0x970 ; /* 0xffffff7000001947 */
/* 0x000fea000383ffff */
/*0a00*/ IMAD.WIDE R2, R0, R5, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x001fca00078e0205 */
/*0a10*/ STG.E [R2.64], R4 ; /* 0x0000000402007986 */
/* 0x020fe2000c101904 */
/*0a20*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0a30*/ BRA 0xa30; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0a40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0aa0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ab0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ac0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ad0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ae0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0af0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
//VERSION 0.8 MODIFIED 10/25/16 12:34 by Jack
// The number of threads per blocks in the kernel
// (if we define it here, then we can use its value in the kernel,
// for example to statically declare an array in shared memory)
const int threads_per_block = 256;
// Forward function declarations
float GPU_vector_max(float *A, int N, int kernel_code, float *kernel_time, float *transfer_time);
float CPU_vector_max(float *A, int N);
float *get_random_vector(int N);
float *get_increasing_vector(int N);
float usToSec(long long time);
long long start_timer();
long long stop_timer(long long start_time, const char *name);
void die(const char *message);
void checkError();
// Main program
__global__ void vector_max_kernel(float *in, float *out, int N) {
// Determine the "flattened" block id and thread id
int block_id = blockIdx.x + gridDim.x * blockIdx.y;
int thread_id = blockDim.x * block_id + threadIdx.x;
// A single "lead" thread in each block finds the maximum value over a range of size threads_per_block
float max = 0.0;
if (threadIdx.x == 0) {
//calculate out of bounds guard
//our block size will be 256, but our vector may not be a multiple of 256!
int end = threads_per_block;
if(thread_id + threads_per_block > N)
end = N - thread_id;
//grab the lead thread's value
max = in[thread_id];
//grab values from all other threads' locations
for(int i = 1; i < end; i++) {
//if larger, replace
if(max < in[thread_id + i])
max = in[thread_id + i];
}
out[block_id] = max;
}
} | .file "tmpxft_00079465_00000000-6_vector_max_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z40__device_stub__Z17vector_max_kernelPfS_iPfS_i
.type _Z40__device_stub__Z17vector_max_kernelPfS_iPfS_i, @function
_Z40__device_stub__Z17vector_max_kernelPfS_iPfS_i:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z17vector_max_kernelPfS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z40__device_stub__Z17vector_max_kernelPfS_iPfS_i, .-_Z40__device_stub__Z17vector_max_kernelPfS_iPfS_i
.globl _Z17vector_max_kernelPfS_i
.type _Z17vector_max_kernelPfS_i, @function
_Z17vector_max_kernelPfS_i:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z40__device_stub__Z17vector_max_kernelPfS_iPfS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z17vector_max_kernelPfS_i, .-_Z17vector_max_kernelPfS_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z17vector_max_kernelPfS_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z17vector_max_kernelPfS_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
//VERSION 0.8 MODIFIED 10/25/16 12:34 by Jack
// The number of threads per blocks in the kernel
// (if we define it here, then we can use its value in the kernel,
// for example to statically declare an array in shared memory)
const int threads_per_block = 256;
// Forward function declarations
float GPU_vector_max(float *A, int N, int kernel_code, float *kernel_time, float *transfer_time);
float CPU_vector_max(float *A, int N);
float *get_random_vector(int N);
float *get_increasing_vector(int N);
float usToSec(long long time);
long long start_timer();
long long stop_timer(long long start_time, const char *name);
void die(const char *message);
void checkError();
// Main program
__global__ void vector_max_kernel(float *in, float *out, int N) {
// Determine the "flattened" block id and thread id
int block_id = blockIdx.x + gridDim.x * blockIdx.y;
int thread_id = blockDim.x * block_id + threadIdx.x;
// A single "lead" thread in each block finds the maximum value over a range of size threads_per_block
float max = 0.0;
if (threadIdx.x == 0) {
//calculate out of bounds guard
//our block size will be 256, but our vector may not be a multiple of 256!
int end = threads_per_block;
if(thread_id + threads_per_block > N)
end = N - thread_id;
//grab the lead thread's value
max = in[thread_id];
//grab values from all other threads' locations
for(int i = 1; i < end; i++) {
//if larger, replace
if(max < in[thread_id + i])
max = in[thread_id + i];
}
out[block_id] = max;
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
//VERSION 0.8 MODIFIED 10/25/16 12:34 by Jack
// The number of threads per blocks in the kernel
// (if we define it here, then we can use its value in the kernel,
// for example to statically declare an array in shared memory)
const int threads_per_block = 256;
// Forward function declarations
float GPU_vector_max(float *A, int N, int kernel_code, float *kernel_time, float *transfer_time);
float CPU_vector_max(float *A, int N);
float *get_random_vector(int N);
float *get_increasing_vector(int N);
float usToSec(long long time);
long long start_timer();
long long stop_timer(long long start_time, const char *name);
void die(const char *message);
void checkError();
// Main program
__global__ void vector_max_kernel(float *in, float *out, int N) {
// Determine the "flattened" block id and thread id
int block_id = blockIdx.x + gridDim.x * blockIdx.y;
int thread_id = blockDim.x * block_id + threadIdx.x;
// A single "lead" thread in each block finds the maximum value over a range of size threads_per_block
float max = 0.0;
if (threadIdx.x == 0) {
//calculate out of bounds guard
//our block size will be 256, but our vector may not be a multiple of 256!
int end = threads_per_block;
if(thread_id + threads_per_block > N)
end = N - thread_id;
//grab the lead thread's value
max = in[thread_id];
//grab values from all other threads' locations
for(int i = 1; i < end; i++) {
//if larger, replace
if(max < in[thread_id + i])
max = in[thread_id + i];
}
out[block_id] = max;
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
//VERSION 0.8 MODIFIED 10/25/16 12:34 by Jack
// The number of threads per blocks in the kernel
// (if we define it here, then we can use its value in the kernel,
// for example to statically declare an array in shared memory)
const int threads_per_block = 256;
// Forward function declarations
float GPU_vector_max(float *A, int N, int kernel_code, float *kernel_time, float *transfer_time);
float CPU_vector_max(float *A, int N);
float *get_random_vector(int N);
float *get_increasing_vector(int N);
float usToSec(long long time);
long long start_timer();
long long stop_timer(long long start_time, const char *name);
void die(const char *message);
void checkError();
// Main program
__global__ void vector_max_kernel(float *in, float *out, int N) {
// Determine the "flattened" block id and thread id
int block_id = blockIdx.x + gridDim.x * blockIdx.y;
int thread_id = blockDim.x * block_id + threadIdx.x;
// A single "lead" thread in each block finds the maximum value over a range of size threads_per_block
float max = 0.0;
if (threadIdx.x == 0) {
//calculate out of bounds guard
//our block size will be 256, but our vector may not be a multiple of 256!
int end = threads_per_block;
if(thread_id + threads_per_block > N)
end = N - thread_id;
//grab the lead thread's value
max = in[thread_id];
//grab values from all other threads' locations
for(int i = 1; i < end; i++) {
//if larger, replace
if(max < in[thread_id + i])
max = in[thread_id + i];
}
out[block_id] = max;
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z17vector_max_kernelPfS_i
.globl _Z17vector_max_kernelPfS_i
.p2align 8
.type _Z17vector_max_kernelPfS_i,@function
_Z17vector_max_kernelPfS_i:
s_mov_b32 s2, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_6
s_clause 0x2
s_load_b32 s2, s[0:1], 0x18
s_load_b32 s3, s[0:1], 0x24
s_load_b64 s[6:7], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_mul_i32 s2, s2, s15
s_and_b32 s3, s3, 0xffff
s_add_i32 s4, s2, s14
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
s_mul_i32 s2, s4, s3
s_load_b32 s3, s[0:1], 0x10
v_add_nc_u32_e32 v1, s2, v0
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
v_add_co_u32 v2, vcc_lo, s6, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v3, vcc_lo
global_load_b32 v2, v[2:3], off
v_add_nc_u32_e32 v3, 0x100, v1
s_waitcnt lgkmcnt(0)
v_sub_nc_u32_e32 v1, s3, v1
v_cmp_lt_i32_e32 vcc_lo, s3, v3
s_mov_b32 s3, exec_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v1, 0x100, v1, vcc_lo
v_cmpx_lt_i32_e32 1, v1
s_cbranch_execz .LBB0_5
v_add_nc_u32_e32 v3, -1, v1
v_add3_u32 v0, v0, s2, 1
s_mov_b32 s5, 0
.p2align 6
.LBB0_3:
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_ashrrev_i32_e32 v1, 31, v0
v_add_nc_u32_e32 v3, -1, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[4:5], 2, v[0:1]
v_add_nc_u32_e32 v0, 1, v0
v_add_co_u32 v4, vcc_lo, s6, v4
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v5, vcc_lo
v_cmp_eq_u32_e32 vcc_lo, 0, v3
global_load_b32 v1, v[4:5], off
s_or_b32 s5, vcc_lo, s5
s_waitcnt vmcnt(0)
v_cmp_lt_f32_e64 s2, v2, v1
s_delay_alu instid0(VALU_DEP_1)
v_cndmask_b32_e64 v2, v2, v1, s2
s_and_not1_b32 exec_lo, exec_lo, s5
s_cbranch_execnz .LBB0_3
s_or_b32 exec_lo, exec_lo, s5
.LBB0_5:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s3
s_load_b64 s[0:1], s[0:1], 0x8
s_ashr_i32 s5, s4, 31
v_mov_b32_e32 v0, 0
s_lshl_b64 s[2:3], s[4:5], 2
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
s_waitcnt vmcnt(0)
global_store_b32 v0, v2, s[0:1]
.LBB0_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z17vector_max_kernelPfS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z17vector_max_kernelPfS_i, .Lfunc_end0-_Z17vector_max_kernelPfS_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z17vector_max_kernelPfS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z17vector_max_kernelPfS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
//VERSION 0.8 MODIFIED 10/25/16 12:34 by Jack
// The number of threads per blocks in the kernel
// (if we define it here, then we can use its value in the kernel,
// for example to statically declare an array in shared memory)
const int threads_per_block = 256;
// Forward function declarations
float GPU_vector_max(float *A, int N, int kernel_code, float *kernel_time, float *transfer_time);
float CPU_vector_max(float *A, int N);
float *get_random_vector(int N);
float *get_increasing_vector(int N);
float usToSec(long long time);
long long start_timer();
long long stop_timer(long long start_time, const char *name);
void die(const char *message);
void checkError();
// Main program
__global__ void vector_max_kernel(float *in, float *out, int N) {
// Determine the "flattened" block id and thread id
int block_id = blockIdx.x + gridDim.x * blockIdx.y;
int thread_id = blockDim.x * block_id + threadIdx.x;
// A single "lead" thread in each block finds the maximum value over a range of size threads_per_block
float max = 0.0;
if (threadIdx.x == 0) {
//calculate out of bounds guard
//our block size will be 256, but our vector may not be a multiple of 256!
int end = threads_per_block;
if(thread_id + threads_per_block > N)
end = N - thread_id;
//grab the lead thread's value
max = in[thread_id];
//grab values from all other threads' locations
for(int i = 1; i < end; i++) {
//if larger, replace
if(max < in[thread_id + i])
max = in[thread_id + i];
}
out[block_id] = max;
}
} | .text
.file "vector_max_kernel.hip"
.globl _Z32__device_stub__vector_max_kernelPfS_i # -- Begin function _Z32__device_stub__vector_max_kernelPfS_i
.p2align 4, 0x90
.type _Z32__device_stub__vector_max_kernelPfS_i,@function
_Z32__device_stub__vector_max_kernelPfS_i: # @_Z32__device_stub__vector_max_kernelPfS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z17vector_max_kernelPfS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z32__device_stub__vector_max_kernelPfS_i, .Lfunc_end0-_Z32__device_stub__vector_max_kernelPfS_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z17vector_max_kernelPfS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z17vector_max_kernelPfS_i,@object # @_Z17vector_max_kernelPfS_i
.section .rodata,"a",@progbits
.globl _Z17vector_max_kernelPfS_i
.p2align 3, 0x0
_Z17vector_max_kernelPfS_i:
.quad _Z32__device_stub__vector_max_kernelPfS_i
.size _Z17vector_max_kernelPfS_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z17vector_max_kernelPfS_i"
.size .L__unnamed_1, 27
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z32__device_stub__vector_max_kernelPfS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z17vector_max_kernelPfS_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z17vector_max_kernelPfS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e280000002100 */
/*0020*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e680000002600 */
/*0030*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e620000002500 */
/*0040*/ ISETP.NE.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x001fe20003f05270 */
/*0050*/ IMAD R0, R0, c[0x0][0xc], R3 ; /* 0x0000030000007a24 */
/* 0x002fd800078e0203 */
/*0060*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0070*/ IMAD R6, R0, c[0x0][0x0], RZ ; /* 0x0000000000067a24 */
/* 0x000fe200078e02ff */
/*0080*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0090*/ IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; /* 0x00000004ff057424 */
/* 0x000fc600078e00ff */
/*00a0*/ IADD3 R7, R6.reuse, 0x100, RZ ; /* 0x0000010006077810 */
/* 0x040fe20007ffe0ff */
/*00b0*/ IMAD.WIDE R2, R6.reuse, R5, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x040fe200078e0205 */
/*00c0*/ IADD3 R8, -R6, c[0x0][0x170], RZ ; /* 0x00005c0006087a10 */
/* 0x000fe40007ffe1ff */
/*00d0*/ ISETP.GT.AND P0, PT, R7, c[0x0][0x170], PT ; /* 0x00005c0007007a0c */
/* 0x000fe40003f04270 */
/*00e0*/ LDG.E R4, [R2.64] ; /* 0x0000000402047981 */
/* 0x000164000c1e1900 */
/*00f0*/ SEL R10, R8, 0x100, P0 ; /* 0x00000100080a7807 */
/* 0x000fc80000000000 */
/*0100*/ ISETP.GE.AND P0, PT, R10, 0x2, PT ; /* 0x000000020a00780c */
/* 0x000fda0003f06270 */
/*0110*/ @!P0 BRA 0xa00 ; /* 0x000008e000008947 */
/* 0x000fea0003800000 */
/*0120*/ IADD3 R2, R10.reuse, -0x2, RZ ; /* 0xfffffffe0a027810 */
/* 0x041fe20007ffe0ff */
/*0130*/ IMAD.MOV.U32 R9, RZ, RZ, 0x1 ; /* 0x00000001ff097424 */
/* 0x000fe200078e00ff */
/*0140*/ IADD3 R7, R10, -0x1, RZ ; /* 0xffffffff0a077810 */
/* 0x000fe40007ffe0ff */
/*0150*/ ISETP.GE.U32.AND P0, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fe40003f06070 */
/*0160*/ SHF.R.S32.HI R8, RZ, 0x1f, R6 ; /* 0x0000001fff087819 */
/* 0x000fe40000011406 */
/*0170*/ LOP3.LUT R7, R7, 0x3, RZ, 0xc0, !PT ; /* 0x0000000307077812 */
/* 0x000fd200078ec0ff */
/*0180*/ @!P0 BRA 0x910 ; /* 0x0000078000008947 */
/* 0x000fea0003800000 */
/*0190*/ LEA R2, P0, R6, c[0x0][0x160], 0x2 ; /* 0x0000580006027a11 */
/* 0x000fe200078010ff */
/*01a0*/ IMAD.IADD R10, R10, 0x1, -R7 ; /* 0x000000010a0a7824 */
/* 0x000fe400078e0a07 */
/*01b0*/ IMAD.MOV.U32 R9, RZ, RZ, 0x1 ; /* 0x00000001ff097424 */
/* 0x000fe200078e00ff */
/*01c0*/ LEA.HI.X R3, R6, c[0x0][0x164], R8, 0x2, P0 ; /* 0x0000590006037a11 */
/* 0x000fe400000f1408 */
/*01d0*/ ISETP.GT.AND P0, PT, R10, 0x1, PT ; /* 0x000000010a00780c */
/* 0x000fe40003f04270 */
/*01e0*/ IADD3 R2, P1, R2, 0x10, RZ ; /* 0x0000001002027810 */
/* 0x000fca0007f3e0ff */
/*01f0*/ IMAD.X R3, RZ, RZ, R3, P1 ; /* 0x000000ffff037224 */
/* 0x000fcc00008e0603 */
/*0200*/ @!P0 BRA 0x7e0 ; /* 0x000005d000008947 */
/* 0x000fea0003800000 */
/*0210*/ IADD3 R11, R10, -0x1, RZ ; /* 0xffffffff0a0b7810 */
/* 0x000fe40007ffe0ff */
/*0220*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0f070 */
/*0230*/ ISETP.GT.AND P1, PT, R11, 0xc, PT ; /* 0x0000000c0b00780c */
/* 0x000fda0003f24270 */
/*0240*/ @!P1 BRA 0x5c0 ; /* 0x0000037000009947 */
/* 0x000fea0003800000 */
/*0250*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0260*/ LDG.E R23, [R2.64+-0xc] ; /* 0xfffff40402177981 */
/* 0x0000a8000c1e1900 */
/*0270*/ LDG.E R25, [R2.64+-0x8] ; /* 0xfffff80402197981 */
/* 0x0000e8000c1e1900 */
/*0280*/ LDG.E R27, [R2.64+-0x4] ; /* 0xfffffc04021b7981 */
/* 0x000128000c1e1900 */
/*0290*/ LDG.E R29, [R2.64] ; /* 0x00000004021d7981 */
/* 0x000128000c1e1900 */
/*02a0*/ LDG.E R22, [R2.64+0x4] ; /* 0x0000040402167981 */
/* 0x000128000c1e1900 */
/*02b0*/ LDG.E R21, [R2.64+0x8] ; /* 0x0000080402157981 */
/* 0x000128000c1e1900 */
/*02c0*/ LDG.E R20, [R2.64+0xc] ; /* 0x00000c0402147981 */
/* 0x000128000c1e1900 */
/*02d0*/ LDG.E R19, [R2.64+0x10] ; /* 0x0000100402137981 */
/* 0x000128000c1e1900 */
/*02e0*/ LDG.E R18, [R2.64+0x14] ; /* 0x0000140402127981 */
/* 0x000128000c1e1900 */
/*02f0*/ LDG.E R17, [R2.64+0x18] ; /* 0x0000180402117981 */
/* 0x000128000c1e1900 */
/*0300*/ LDG.E R16, [R2.64+0x1c] ; /* 0x00001c0402107981 */
/* 0x000128000c1e1900 */
/*0310*/ LDG.E R15, [R2.64+0x20] ; /* 0x00002004020f7981 */
/* 0x000128000c1e1900 */
/*0320*/ LDG.E R14, [R2.64+0x24] ; /* 0x00002404020e7981 */
/* 0x000128000c1e1900 */
/*0330*/ LDG.E R13, [R2.64+0x28] ; /* 0x00002804020d7981 */
/* 0x000128000c1e1900 */
/*0340*/ LDG.E R12, [R2.64+0x2c] ; /* 0x00002c04020c7981 */
/* 0x000128000c1e1900 */
/*0350*/ LDG.E R11, [R2.64+0x30] ; /* 0x00003004020b7981 */
/* 0x000122000c1e1900 */
/*0360*/ IADD3 R10, R10, -0x10, RZ ; /* 0xfffffff00a0a7810 */
/* 0x000fc40007ffe0ff */
/*0370*/ IADD3 R9, R9, 0x10, RZ ; /* 0x0000001009097810 */
/* 0x000fe40007ffe0ff */
/*0380*/ ISETP.GT.AND P2, PT, R10, 0xd, PT ; /* 0x0000000d0a00780c */
/* 0x000fe40003f44270 */
/*0390*/ IADD3 R2, P3, R2, 0x40, RZ ; /* 0x0000004002027810 */
/* 0x001fca0007f7e0ff */
/*03a0*/ IMAD.X R3, RZ, RZ, R3, P3 ; /* 0x000000ffff037224 */
/* 0x000fe200018e0603 */
/*03b0*/ FSETP.GEU.AND P1, PT, R4, R23, PT ; /* 0x000000170400720b */
/* 0x024fc80003f2e000 */
/*03c0*/ FSEL R4, R23, R4, !P1 ; /* 0x0000000417047208 */
/* 0x000fc80004800000 */
/*03d0*/ FSETP.GEU.AND P1, PT, R4, R25, PT ; /* 0x000000190400720b */
/* 0x008fc80003f2e000 */
/*03e0*/ FSEL R4, R25, R4, !P1 ; /* 0x0000000419047208 */
/* 0x000fc80004800000 */
/*03f0*/ FSETP.GEU.AND P1, PT, R4, R27, PT ; /* 0x0000001b0400720b */
/* 0x010fc80003f2e000 */
/*0400*/ FSEL R4, R27, R4, !P1 ; /* 0x000000041b047208 */
/* 0x000fc80004800000 */
/*0410*/ FSETP.GEU.AND P1, PT, R4, R29, PT ; /* 0x0000001d0400720b */
/* 0x000fc80003f2e000 */
/*0420*/ FSEL R29, R29, R4, !P1 ; /* 0x000000041d1d7208 */
/* 0x000fc80004800000 */
/*0430*/ FSETP.GEU.AND P1, PT, R29, R22, PT ; /* 0x000000161d00720b */
/* 0x000fc80003f2e000 */
/*0440*/ FSEL R22, R22, R29, !P1 ; /* 0x0000001d16167208 */
/* 0x000fc80004800000 */
/*0450*/ FSETP.GEU.AND P1, PT, R22, R21, PT ; /* 0x000000151600720b */
/* 0x000fc80003f2e000 */
/*0460*/ FSEL R21, R21, R22, !P1 ; /* 0x0000001615157208 */
/* 0x000fc80004800000 */
/*0470*/ FSETP.GEU.AND P1, PT, R21, R20, PT ; /* 0x000000141500720b */
/* 0x000fc80003f2e000 */
/*0480*/ FSEL R20, R20, R21, !P1 ; /* 0x0000001514147208 */
/* 0x000fc80004800000 */
/*0490*/ FSETP.GEU.AND P1, PT, R20, R19, PT ; /* 0x000000131400720b */
/* 0x000fc80003f2e000 */
/*04a0*/ FSEL R19, R19, R20, !P1 ; /* 0x0000001413137208 */
/* 0x000fc80004800000 */
/*04b0*/ FSETP.GEU.AND P1, PT, R19, R18, PT ; /* 0x000000121300720b */
/* 0x000fc80003f2e000 */
/*04c0*/ FSEL R18, R18, R19, !P1 ; /* 0x0000001312127208 */
/* 0x000fc80004800000 */
/*04d0*/ FSETP.GEU.AND P1, PT, R18, R17, PT ; /* 0x000000111200720b */
/* 0x000fc80003f2e000 */
/*04e0*/ FSEL R17, R17, R18, !P1 ; /* 0x0000001211117208 */
/* 0x000fc80004800000 */
/*04f0*/ FSETP.GEU.AND P1, PT, R17, R16, PT ; /* 0x000000101100720b */
/* 0x000fc80003f2e000 */
/*0500*/ FSEL R16, R16, R17, !P1 ; /* 0x0000001110107208 */
/* 0x000fc80004800000 */
/*0510*/ FSETP.GEU.AND P1, PT, R16, R15, PT ; /* 0x0000000f1000720b */
/* 0x000fc80003f2e000 */
/*0520*/ FSEL R15, R15, R16, !P1 ; /* 0x000000100f0f7208 */
/* 0x000fc80004800000 */
/*0530*/ FSETP.GEU.AND P1, PT, R15, R14, PT ; /* 0x0000000e0f00720b */
/* 0x000fc80003f2e000 */
/*0540*/ FSEL R14, R14, R15, !P1 ; /* 0x0000000f0e0e7208 */
/* 0x000fc80004800000 */
/*0550*/ FSETP.GEU.AND P1, PT, R14, R13, PT ; /* 0x0000000d0e00720b */
/* 0x000fc80003f2e000 */
/*0560*/ FSEL R13, R13, R14, !P1 ; /* 0x0000000e0d0d7208 */
/* 0x000fc80004800000 */
/*0570*/ FSETP.GEU.AND P1, PT, R13, R12, PT ; /* 0x0000000c0d00720b */
/* 0x000fc80003f2e000 */
/*0580*/ FSEL R4, R12, R13, !P1 ; /* 0x0000000d0c047208 */
/* 0x000fc80004800000 */
/*0590*/ FSETP.GEU.AND P1, PT, R4, R11, PT ; /* 0x0000000b0400720b */
/* 0x000fc80003f2e000 */
/*05a0*/ FSEL R4, R11, R4, !P1 ; /* 0x000000040b047208 */
/* 0x000fe20004800000 */
/*05b0*/ @P2 BRA 0x260 ; /* 0xfffffca000002947 */
/* 0x000fea000383ffff */
/*05c0*/ IADD3 R11, R10, -0x1, RZ ; /* 0xffffffff0a0b7810 */
/* 0x000fc80007ffe0ff */
/*05d0*/ ISETP.GT.AND P1, PT, R11, 0x4, PT ; /* 0x000000040b00780c */
/* 0x000fda0003f24270 */
/*05e0*/ @!P1 BRA 0x7c0 ; /* 0x000001d000009947 */
/* 0x000fea0003800000 */
/*05f0*/ LDG.E R11, [R2.64+-0xc] ; /* 0xfffff404020b7981 */
/* 0x0000a8000c1e1900 */
/*0600*/ LDG.E R13, [R2.64+-0x8] ; /* 0xfffff804020d7981 */
/* 0x0000e8000c1e1900 */
/*0610*/ LDG.E R15, [R2.64+-0x4] ; /* 0xfffffc04020f7981 */
/* 0x000128000c1e1900 */
/*0620*/ LDG.E R17, [R2.64] ; /* 0x0000000402117981 */
/* 0x000128000c1e1900 */
/*0630*/ LDG.E R19, [R2.64+0x4] ; /* 0x0000040402137981 */
/* 0x000128000c1e1900 */
/*0640*/ LDG.E R21, [R2.64+0x8] ; /* 0x0000080402157981 */
/* 0x000128000c1e1900 */
/*0650*/ LDG.E R23, [R2.64+0xc] ; /* 0x00000c0402177981 */
/* 0x000128000c1e1900 */
/*0660*/ LDG.E R25, [R2.64+0x10] ; /* 0x0000100402197981 */
/* 0x000122000c1e1900 */
/*0670*/ IADD3 R9, R9, 0x8, RZ ; /* 0x0000000809097810 */
/* 0x000fc40007ffe0ff */
/*0680*/ IADD3 R10, R10, -0x8, RZ ; /* 0xfffffff80a0a7810 */
/* 0x000fe40007ffe0ff */
/*0690*/ IADD3 R2, P2, R2, 0x20, RZ ; /* 0x0000002002027810 */
/* 0x001fca0007f5e0ff */
/*06a0*/ IMAD.X R3, RZ, RZ, R3, P2 ; /* 0x000000ffff037224 */
/* 0x000fe200010e0603 */
/*06b0*/ FSETP.GEU.AND P0, PT, R4, R11, PT ; /* 0x0000000b0400720b */
/* 0x024fc80003f0e000 */
/*06c0*/ FSEL R4, R11, R4, !P0 ; /* 0x000000040b047208 */
/* 0x000fc80004000000 */
/*06d0*/ FSETP.GEU.AND P0, PT, R4, R13, PT ; /* 0x0000000d0400720b */
/* 0x008fc80003f0e000 */
/*06e0*/ FSEL R4, R13, R4, !P0 ; /* 0x000000040d047208 */
/* 0x000fc80004000000 */
/*06f0*/ FSETP.GEU.AND P0, PT, R4, R15, PT ; /* 0x0000000f0400720b */
/* 0x010fc80003f0e000 */
/*0700*/ FSEL R4, R15, R4, !P0 ; /* 0x000000040f047208 */
/* 0x000fc80004000000 */
/*0710*/ FSETP.GEU.AND P0, PT, R4, R17, PT ; /* 0x000000110400720b */
/* 0x000fc80003f0e000 */
/*0720*/ FSEL R4, R17, R4, !P0 ; /* 0x0000000411047208 */
/* 0x000fc80004000000 */
/*0730*/ FSETP.GEU.AND P0, PT, R4, R19, PT ; /* 0x000000130400720b */
/* 0x000fc80003f0e000 */
/*0740*/ FSEL R4, R19, R4, !P0 ; /* 0x0000000413047208 */
/* 0x000fc80004000000 */
/*0750*/ FSETP.GEU.AND P0, PT, R4, R21, PT ; /* 0x000000150400720b */
/* 0x000fc80003f0e000 */
/*0760*/ FSEL R4, R21, R4, !P0 ; /* 0x0000000415047208 */
/* 0x000fc80004000000 */
/*0770*/ FSETP.GEU.AND P0, PT, R4, R23, PT ; /* 0x000000170400720b */
/* 0x000fc80003f0e000 */
/*0780*/ FSEL R4, R23, R4, !P0 ; /* 0x0000000417047208 */
/* 0x000fe40004000000 */
/*0790*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*07a0*/ FSETP.GEU.AND P1, PT, R4, R25, PT ; /* 0x000000190400720b */
/* 0x000fc80003f2e000 */
/*07b0*/ FSEL R4, R25, R4, !P1 ; /* 0x0000000419047208 */
/* 0x000fe40004800000 */
/*07c0*/ ISETP.NE.OR P0, PT, R10, 0x1, P0 ; /* 0x000000010a00780c */
/* 0x000fda0000705670 */
/*07d0*/ @!P0 BRA 0x910 ; /* 0x0000013000008947 */
/* 0x000fea0003800000 */
/*07e0*/ LDG.E R11, [R2.64+-0xc] ; /* 0xfffff404020b7981 */
/* 0x000ea8000c1e1900 */
/*07f0*/ LDG.E R13, [R2.64+-0x8] ; /* 0xfffff804020d7981 */
/* 0x000ee8000c1e1900 */
/*0800*/ LDG.E R15, [R2.64+-0x4] ; /* 0xfffffc04020f7981 */
/* 0x000128000c1e1900 */
/*0810*/ LDG.E R17, [R2.64] ; /* 0x0000000402117981 */
/* 0x000122000c1e1900 */
/*0820*/ IADD3 R10, R10, -0x4, RZ ; /* 0xfffffffc0a0a7810 */
/* 0x000fc40007ffe0ff */
/*0830*/ IADD3 R9, R9, 0x4, RZ ; /* 0x0000000409097810 */
/* 0x000fe40007ffe0ff */
/*0840*/ ISETP.NE.AND P1, PT, R10, 0x1, PT ; /* 0x000000010a00780c */
/* 0x000fe40003f25270 */
/*0850*/ FSETP.GEU.AND P0, PT, R4, R11, PT ; /* 0x0000000b0400720b */
/* 0x024fc80003f0e000 */
/*0860*/ FSEL R4, R11, R4, !P0 ; /* 0x000000040b047208 */
/* 0x000fe40004000000 */
/*0870*/ IADD3 R11, P2, R2, 0x10, RZ ; /* 0x00000010020b7810 */
/* 0x000fe40007f5e0ff */
/*0880*/ FSETP.GEU.AND P0, PT, R4, R13, PT ; /* 0x0000000d0400720b */
/* 0x008fc60003f0e000 */
/*0890*/ IMAD.X R3, RZ, RZ, R3, P2 ; /* 0x000000ffff037224 */
/* 0x001fe200010e0603 */
/*08a0*/ FSEL R4, R13, R4, !P0 ; /* 0x000000040d047208 */
/* 0x000fe20004000000 */
/*08b0*/ IMAD.MOV.U32 R2, RZ, RZ, R11 ; /* 0x000000ffff027224 */
/* 0x000fc600078e000b */
/*08c0*/ FSETP.GEU.AND P0, PT, R4, R15, PT ; /* 0x0000000f0400720b */
/* 0x010fc80003f0e000 */
/*08d0*/ FSEL R4, R15, R4, !P0 ; /* 0x000000040f047208 */
/* 0x000fc80004000000 */
/*08e0*/ FSETP.GEU.AND P0, PT, R4, R17, PT ; /* 0x000000110400720b */
/* 0x000fc80003f0e000 */
/*08f0*/ FSEL R4, R17, R4, !P0 ; /* 0x0000000411047208 */
/* 0x000fe20004000000 */
/*0900*/ @P1 BRA 0x7e0 ; /* 0xfffffed000001947 */
/* 0x000fea000383ffff */
/*0910*/ ISETP.NE.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fda0003f05270 */
/*0920*/ @!P0 BRA 0xa00 ; /* 0x000000d000008947 */
/* 0x000fea0003800000 */
/*0930*/ IADD3 R6, P0, R6, R9, RZ ; /* 0x0000000906067210 */
/* 0x000fc80007f1e0ff */
/*0940*/ LEA R2, P1, R6, c[0x0][0x160], 0x2 ; /* 0x0000580006027a11 */
/* 0x000fe400078210ff */
/*0950*/ LEA.HI.X.SX32 R9, R9, R8, 0x1, P0 ; /* 0x0000000809097211 */
/* 0x000fc800000f0eff */
/*0960*/ LEA.HI.X R9, R6, c[0x0][0x164], R9, 0x2, P1 ; /* 0x0000590006097a11 */
/* 0x000fca00008f1409 */
/*0970*/ IMAD.MOV.U32 R3, RZ, RZ, R9 ; /* 0x000000ffff037224 */
/* 0x000fcc00078e0009 */
/*0980*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x0000a2000c1e1900 */
/*0990*/ IADD3 R7, R7, -0x1, RZ ; /* 0xffffffff07077810 */
/* 0x000fc80007ffe0ff */
/*09a0*/ ISETP.NE.AND P1, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fe40003f25270 */
/*09b0*/ IADD3 R2, P2, R2, 0x4, RZ ; /* 0x0000000402027810 */
/* 0x001fca0007f5e0ff */
/*09c0*/ IMAD.X R9, RZ, RZ, R9, P2 ; /* 0x000000ffff097224 */
/* 0x000fe200010e0609 */
/*09d0*/ FSETP.GEU.AND P0, PT, R4, R3, PT ; /* 0x000000030400720b */
/* 0x024fc80003f0e000 */
/*09e0*/ FSEL R4, R3, R4, !P0 ; /* 0x0000000403047208 */
/* 0x000fe20004000000 */
/*09f0*/ @P1 BRA 0x970 ; /* 0xffffff7000001947 */
/* 0x000fea000383ffff */
/*0a00*/ IMAD.WIDE R2, R0, R5, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x001fca00078e0205 */
/*0a10*/ STG.E [R2.64], R4 ; /* 0x0000000402007986 */
/* 0x020fe2000c101904 */
/*0a20*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0a30*/ BRA 0xa30; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0a40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0aa0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ab0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ac0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ad0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ae0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0af0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z17vector_max_kernelPfS_i
.globl _Z17vector_max_kernelPfS_i
.p2align 8
.type _Z17vector_max_kernelPfS_i,@function
_Z17vector_max_kernelPfS_i:
s_mov_b32 s2, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_6
s_clause 0x2
s_load_b32 s2, s[0:1], 0x18
s_load_b32 s3, s[0:1], 0x24
s_load_b64 s[6:7], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_mul_i32 s2, s2, s15
s_and_b32 s3, s3, 0xffff
s_add_i32 s4, s2, s14
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
s_mul_i32 s2, s4, s3
s_load_b32 s3, s[0:1], 0x10
v_add_nc_u32_e32 v1, s2, v0
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
v_add_co_u32 v2, vcc_lo, s6, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v3, vcc_lo
global_load_b32 v2, v[2:3], off
v_add_nc_u32_e32 v3, 0x100, v1
s_waitcnt lgkmcnt(0)
v_sub_nc_u32_e32 v1, s3, v1
v_cmp_lt_i32_e32 vcc_lo, s3, v3
s_mov_b32 s3, exec_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v1, 0x100, v1, vcc_lo
v_cmpx_lt_i32_e32 1, v1
s_cbranch_execz .LBB0_5
v_add_nc_u32_e32 v3, -1, v1
v_add3_u32 v0, v0, s2, 1
s_mov_b32 s5, 0
.p2align 6
.LBB0_3:
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_ashrrev_i32_e32 v1, 31, v0
v_add_nc_u32_e32 v3, -1, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[4:5], 2, v[0:1]
v_add_nc_u32_e32 v0, 1, v0
v_add_co_u32 v4, vcc_lo, s6, v4
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v5, vcc_lo
v_cmp_eq_u32_e32 vcc_lo, 0, v3
global_load_b32 v1, v[4:5], off
s_or_b32 s5, vcc_lo, s5
s_waitcnt vmcnt(0)
v_cmp_lt_f32_e64 s2, v2, v1
s_delay_alu instid0(VALU_DEP_1)
v_cndmask_b32_e64 v2, v2, v1, s2
s_and_not1_b32 exec_lo, exec_lo, s5
s_cbranch_execnz .LBB0_3
s_or_b32 exec_lo, exec_lo, s5
.LBB0_5:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s3
s_load_b64 s[0:1], s[0:1], 0x8
s_ashr_i32 s5, s4, 31
v_mov_b32_e32 v0, 0
s_lshl_b64 s[2:3], s[4:5], 2
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
s_waitcnt vmcnt(0)
global_store_b32 v0, v2, s[0:1]
.LBB0_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z17vector_max_kernelPfS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z17vector_max_kernelPfS_i, .Lfunc_end0-_Z17vector_max_kernelPfS_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z17vector_max_kernelPfS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z17vector_max_kernelPfS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00079465_00000000-6_vector_max_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z40__device_stub__Z17vector_max_kernelPfS_iPfS_i
.type _Z40__device_stub__Z17vector_max_kernelPfS_iPfS_i, @function
_Z40__device_stub__Z17vector_max_kernelPfS_iPfS_i:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z17vector_max_kernelPfS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z40__device_stub__Z17vector_max_kernelPfS_iPfS_i, .-_Z40__device_stub__Z17vector_max_kernelPfS_iPfS_i
.globl _Z17vector_max_kernelPfS_i
.type _Z17vector_max_kernelPfS_i, @function
_Z17vector_max_kernelPfS_i:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z40__device_stub__Z17vector_max_kernelPfS_iPfS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z17vector_max_kernelPfS_i, .-_Z17vector_max_kernelPfS_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z17vector_max_kernelPfS_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z17vector_max_kernelPfS_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "vector_max_kernel.hip"
.globl _Z32__device_stub__vector_max_kernelPfS_i # -- Begin function _Z32__device_stub__vector_max_kernelPfS_i
.p2align 4, 0x90
.type _Z32__device_stub__vector_max_kernelPfS_i,@function
_Z32__device_stub__vector_max_kernelPfS_i: # @_Z32__device_stub__vector_max_kernelPfS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z17vector_max_kernelPfS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z32__device_stub__vector_max_kernelPfS_i, .Lfunc_end0-_Z32__device_stub__vector_max_kernelPfS_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z17vector_max_kernelPfS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z17vector_max_kernelPfS_i,@object # @_Z17vector_max_kernelPfS_i
.section .rodata,"a",@progbits
.globl _Z17vector_max_kernelPfS_i
.p2align 3, 0x0
_Z17vector_max_kernelPfS_i:
.quad _Z32__device_stub__vector_max_kernelPfS_i
.size _Z17vector_max_kernelPfS_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z17vector_max_kernelPfS_i"
.size .L__unnamed_1, 27
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z32__device_stub__vector_max_kernelPfS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z17vector_max_kernelPfS_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include<bits/stdc++.h>
using namespace std;
#define MAX_VAL ((int)1e8)
#define cudaCatchError(error) { gpuAssert((error), __FILE__, __LINE__); }
// Catch Cuda errors
inline void gpuAssert(cudaError_t error, const char *file, int line, bool abort = false)
{
if (error != cudaSuccess)
{
printf("\n====== Cuda Error Code %i ======\n %s in CUDA %s\n", error, cudaGetErrorString(error));
printf("\nIn file :%s\nOn line: %d", file, line);
if(abort)
exit(-1);
}
}
__global__ void compute(int *d_r, int *d_c, int *d_depth, int *max_depth, int *Q1, int *Q2, int nodes){
int idx = threadIdx.x;
__shared__ int len1, len2, curr_depth;
int i;
for(i=idx; i<nodes; i+=1024){
d_depth[i] = MAX_VAL;
}
if(idx == 0){
d_depth[0] = 0;
curr_depth = 0;
len1 = 1;
len2 = 0;
Q1[0] = 0;
}
__syncthreads();
while(len1){
for(i=idx; i<len1; i+=1024){
for(int j=d_r[Q1[i]]; j<d_r[Q1[i]+1]; j++){
int v = d_c[j];
if(atomicCAS(&d_depth[v], MAX_VAL, d_depth[Q1[i]]+1) == MAX_VAL){
int t = atomicAdd(&len2,1);
Q2[t] = v;
}
}
}
__syncthreads();
if(idx==0){
for(i=0; i<len2; i++){
Q1[i] = Q2[i];
}
len1 = len2;
len2 = 0;
curr_depth++;
}
__syncthreads();
}
max_depth[0] = curr_depth;
}
int main(int argc, char *argv[]){
if(argc<2){
cout << "Usage: " << argv[0] << " <graph_file_name>\n";
return 0;
}
ifstream input;
input.open(argv[1]);
int nodes, edges, i;
input >> nodes;
input >> edges;
// allocating host memory
int *h_r = (int*)malloc((nodes+1)*sizeof(int));
int *h_c = (int*)malloc(edges*2*sizeof(int));
// reading inputs
for(i=0; i<nodes+1; i++){
input >> h_r[i];
}
for(i=0; i<edges*2; i++){
input >> h_c[i];
}
// allocating device memory
int *Q1, *Q2, *d_r, *d_c, *d_depth, *max_depth;
cudaMalloc((void**)&Q1, nodes*sizeof(int));
cudaMalloc((void**)&Q2, nodes*sizeof(int));
cudaMalloc((void**)&d_r, (nodes+1)*sizeof(int));
cudaMalloc((void**)&d_c, edges*2*sizeof(int));
cudaMalloc((void**)&d_depth, nodes*sizeof(int));
cudaMalloc((void**)&max_depth, sizeof(int));
// copying data to device
cudaMemcpy(d_r, h_r, (nodes+1)*sizeof(int), cudaMemcpyHostToDevice);
cudaMemcpy(d_c, h_c, edges*2*sizeof(int), cudaMemcpyHostToDevice);
// timer
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaEventRecord(start);
// kernel call
printf("Starting Computation\n");
compute <<<1, 1024>>> (d_r, d_c, d_depth, max_depth, Q1, Q2, nodes);
cudaThreadSynchronize();
printf("Finished Computation\n");
// timer
cudaEventRecord(stop);
cudaEventSynchronize(stop);
float milliseconds = 0;
cudaEventElapsedTime(&milliseconds, start, stop);
cout<<"Compute time in GPU: "<<milliseconds<<"ms"<<endl;
// copying results to host
int *result = (int *)malloc(sizeof(int));
cudaCatchError(cudaMemcpy(result, max_depth, sizeof(int), cudaMemcpyDeviceToHost));
printf("Depth : %d\n", result[0]-1);
// solution check
int *h_depth = (int*) malloc(nodes*sizeof(int));
cudaMemcpy(h_depth, d_depth, nodes*sizeof(int), cudaMemcpyDeviceToHost);
int *h_check_depth = (int*)malloc(nodes*sizeof(int));
freopen(argv[2], "r", stdin);
printf("malloc done\n");
for(int i = 0; i < nodes; i++) {
cin>>h_check_depth[i];
}
printf("Finished reading output file\n");
bool flag = true;
int count = 0;
printf("Starting checking\n");
for(int i = 0; i < nodes; i++) {
if(h_depth[i] != h_check_depth[i]) {
printf("Found %d, Expected %d\n",h_depth[i], h_check_depth[i]);
flag = false;
count++;
}
}
printf("Finished checking\n");
if(flag) {
cout<<"Solution is correct!\n";
}
else {
cout<<"Solution is incorrect!"<<endl;
cout<<count<<" testcases failed.\n";
}
return 0;
} | code for sm_80
Function : _Z7computePiS_S_S_S_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e220000002100 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0030*/ BSSY B0, 0x5b0 ; /* 0x0000057000007945 */
/* 0x000fe20003800000 */
/*0040*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x190], PT ; /* 0x0000640000007a0c */
/* 0x001fda0003f06270 */
/*0050*/ @P0 BRA 0x5a0 ; /* 0x0000054000000947 */
/* 0x000fea0003800000 */
/*0060*/ LOP3.LUT R2, RZ, R0, RZ, 0x33, !PT ; /* 0x00000000ff027212 */
/* 0x000fe200078e33ff */
/*0070*/ BSSY B1, 0x180 ; /* 0x0000010000017945 */
/* 0x000fe60003800000 */
/*0080*/ IADD3 R2, R2, c[0x0][0x190], RZ ; /* 0x0000640002027a10 */
/* 0x000fc80007ffe0ff */
/*0090*/ LEA.HI R3, R2.reuse, 0x1, RZ, 0x16 ; /* 0x0000000102037811 */
/* 0x040fe400078fb0ff */
/*00a0*/ ISETP.GE.U32.AND P1, PT, R2, 0xc00, PT ; /* 0x00000c000200780c */
/* 0x000fe20003f26070 */
/*00b0*/ IMAD.MOV.U32 R2, RZ, RZ, R0 ; /* 0x000000ffff027224 */
/* 0x000fe200078e0000 */
/*00c0*/ LOP3.LUT P0, R3, R3, 0x3, RZ, 0xc0, !PT ; /* 0x0000000303037812 */
/* 0x000fda000780c0ff */
/*00d0*/ @!P0 BRA 0x170 ; /* 0x0000009000008947 */
/* 0x000fea0003800000 */
/*00e0*/ IMAD.MOV.U32 R2, RZ, RZ, R0 ; /* 0x000000ffff027224 */
/* 0x000fe400078e0000 */
/*00f0*/ IMAD.MOV.U32 R7, RZ, RZ, 0x4 ; /* 0x00000004ff077424 */
/* 0x000fe400078e00ff */
/*0100*/ IMAD.MOV.U32 R9, RZ, RZ, 0x5f5e100 ; /* 0x05f5e100ff097424 */
/* 0x000fe400078e00ff */
/*0110*/ IMAD.WIDE R4, R2.reuse, R7, c[0x0][0x170] ; /* 0x00005c0002047625 */
/* 0x040fe200078e0207 */
/*0120*/ IADD3 R3, R3, -0x1, RZ ; /* 0xffffffff03037810 */
/* 0x000fe40007ffe0ff */
/*0130*/ IADD3 R2, R2, 0x400, RZ ; /* 0x0000040002027810 */
/* 0x000fe40007ffe0ff */
/*0140*/ STG.E [R4.64], R9 ; /* 0x0000000904007986 */
/* 0x0001e2000c101904 */
/*0150*/ ISETP.NE.AND P0, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fda0003f05270 */
/*0160*/ @P0 BRA 0x110 ; /* 0xffffffa000000947 */
/* 0x001fea000383ffff */
/*0170*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0180*/ @!P1 BRA 0x5a0 ; /* 0x0000041000009947 */
/* 0x000fea0003800000 */
/*0190*/ IADD3 R3, -R2, c[0x0][0x190], RZ ; /* 0x0000640002037a10 */
/* 0x000fe20007ffe1ff */
/*01a0*/ BSSY B1, 0x3e0 ; /* 0x0000023000017945 */
/* 0x000fe20003800000 */
/*01b0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0f070 */
/*01c0*/ ISETP.GT.AND P1, PT, R3, 0x3000, PT ; /* 0x000030000300780c */
/* 0x000fda0003f24270 */
/*01d0*/ @!P1 BRA 0x3d0 ; /* 0x000001f000009947 */
/* 0x000fea0003800000 */
/*01e0*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x190] ; /* 0x00006400ff037624 */
/* 0x000fe200078e00ff */
/*01f0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe20003f0e170 */
/*0200*/ IMAD.MOV.U32 R13, RZ, RZ, 0x4 ; /* 0x00000004ff0d7424 */
/* 0x000fe400078e00ff */
/*0210*/ IMAD.MOV.U32 R15, RZ, RZ, 0x5f5e100 ; /* 0x05f5e100ff0f7424 */
/* 0x000fe200078e00ff */
/*0220*/ IADD3 R3, R3, -0x3000, RZ ; /* 0xffffd00003037810 */
/* 0x000fe40007ffe0ff */
/*0230*/ IADD3 R4, R2.reuse, 0x1000, RZ ; /* 0x0000100002047810 */
/* 0x041fe20007ffe0ff */
/*0240*/ IMAD.WIDE R10, R2.reuse, R13.reuse, c[0x0][0x170] ; /* 0x00005c00020a7625 */
/* 0x0c0fe200078e020d */
/*0250*/ IADD3 R6, R2.reuse, 0x2000, RZ ; /* 0x0000200002067810 */
/* 0x040fe40007ffe0ff */
/*0260*/ IADD3 R8, R2, 0x3000, RZ ; /* 0x0000300002087810 */
/* 0x000fe20007ffe0ff */
/*0270*/ IMAD.WIDE R4, R4, R13, c[0x0][0x170] ; /* 0x00005c0004047625 */
/* 0x000fe200078e020d */
/*0280*/ STG.E [R10.64], R15 ; /* 0x0000000f0a007986 */
/* 0x0001e2000c101904 */
/*0290*/ IADD3 R2, R2, 0x4000, RZ ; /* 0x0000400002027810 */
/* 0x000fc40007ffe0ff */
/*02a0*/ IMAD.WIDE R6, R6, R13, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fe200078e020d */
/*02b0*/ STG.E [R10.64+0x1000], R15 ; /* 0x0010000f0a007986 */
/* 0x0001e2000c101904 */
/*02c0*/ ISETP.GE.AND P1, PT, R2, R3, PT ; /* 0x000000030200720c */
/* 0x000fe40003f26270 */
/*02d0*/ IMAD.WIDE R8, R8, R13, c[0x0][0x170] ; /* 0x00005c0008087625 */
/* 0x000fe200078e020d */
/*02e0*/ STG.E [R10.64+0x2000], R15 ; /* 0x0020000f0a007986 */
/* 0x0001e8000c101904 */
/*02f0*/ STG.E [R10.64+0x3000], R15 ; /* 0x0030000f0a007986 */
/* 0x0001e8000c101904 */
/*0300*/ STG.E [R4.64], R15 ; /* 0x0000000f04007986 */
/* 0x0001e8000c101904 */
/*0310*/ STG.E [R4.64+0x1000], R15 ; /* 0x0010000f04007986 */
/* 0x0001e8000c101904 */
/*0320*/ STG.E [R4.64+0x2000], R15 ; /* 0x0020000f04007986 */
/* 0x0001e8000c101904 */
/*0330*/ STG.E [R4.64+0x3000], R15 ; /* 0x0030000f04007986 */
/* 0x0001e8000c101904 */
/*0340*/ STG.E [R6.64], R15 ; /* 0x0000000f06007986 */
/* 0x0001e8000c101904 */
/*0350*/ STG.E [R6.64+0x1000], R15 ; /* 0x0010000f06007986 */
/* 0x0001e8000c101904 */
/*0360*/ STG.E [R6.64+0x2000], R15 ; /* 0x0020000f06007986 */
/* 0x0001e8000c101904 */
/*0370*/ STG.E [R6.64+0x3000], R15 ; /* 0x0030000f06007986 */
/* 0x0001e8000c101904 */
/*0380*/ STG.E [R8.64], R15 ; /* 0x0000000f08007986 */
/* 0x0001e8000c101904 */
/*0390*/ STG.E [R8.64+0x1000], R15 ; /* 0x0010000f08007986 */
/* 0x0001e8000c101904 */
/*03a0*/ STG.E [R8.64+0x2000], R15 ; /* 0x0020000f08007986 */
/* 0x0001e8000c101904 */
/*03b0*/ STG.E [R8.64+0x3000], R15 ; /* 0x0030000f08007986 */
/* 0x0001e2000c101904 */
/*03c0*/ @!P1 BRA 0x230 ; /* 0xfffffe6000009947 */
/* 0x000fea000383ffff */
/*03d0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*03e0*/ IADD3 R3, -R2, c[0x0][0x190], RZ ; /* 0x0000640002037a10 */
/* 0x000fe20007ffe1ff */
/*03f0*/ BSSY B1, 0x520 ; /* 0x0000012000017945 */
/* 0x000fe60003800000 */
/*0400*/ ISETP.GT.AND P1, PT, R3, 0x1000, PT ; /* 0x000010000300780c */
/* 0x000fda0003f24270 */
/*0410*/ @!P1 BRA 0x510 ; /* 0x000000f000009947 */
/* 0x000fea0003800000 */
/*0420*/ IMAD.MOV.U32 R7, RZ, RZ, 0x4 ; /* 0x00000004ff077424 */
/* 0x001fe200078e00ff */
/*0430*/ IADD3 R6, R2.reuse, 0x1000, RZ ; /* 0x0000100002067810 */
/* 0x040fe20007ffe0ff */
/*0440*/ IMAD.MOV.U32 R3, RZ, RZ, 0x5f5e100 ; /* 0x05f5e100ff037424 */
/* 0x000fe200078e00ff */
/*0450*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe20003f0e170 */
/*0460*/ IMAD.WIDE R4, R2.reuse, R7, c[0x0][0x170] ; /* 0x00005c0002047625 */
/* 0x040fe200078e0207 */
/*0470*/ IADD3 R2, R2, 0x2000, RZ ; /* 0x0000200002027810 */
/* 0x000fc60007ffe0ff */
/*0480*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fe200078e0207 */
/*0490*/ STG.E [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x0001e8000c101904 */
/*04a0*/ STG.E [R4.64+0x1000], R3 ; /* 0x0010000304007986 */
/* 0x0001e8000c101904 */
/*04b0*/ STG.E [R4.64+0x2000], R3 ; /* 0x0020000304007986 */
/* 0x0001e8000c101904 */
/*04c0*/ STG.E [R4.64+0x3000], R3 ; /* 0x0030000304007986 */
/* 0x0001e8000c101904 */
/*04d0*/ STG.E [R6.64], R3 ; /* 0x0000000306007986 */
/* 0x0001e8000c101904 */
/*04e0*/ STG.E [R6.64+0x1000], R3 ; /* 0x0010000306007986 */
/* 0x0001e8000c101904 */
/*04f0*/ STG.E [R6.64+0x2000], R3 ; /* 0x0020000306007986 */
/* 0x0001e8000c101904 */
/*0500*/ STG.E [R6.64+0x3000], R3 ; /* 0x0030000306007986 */
/* 0x0001e4000c101904 */
/*0510*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0520*/ ISETP.LT.OR P0, PT, R2, c[0x0][0x190], P0 ; /* 0x0000640002007a0c */
/* 0x000fda0000701670 */
/*0530*/ @P0 IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff030424 */
/* 0x001fe400078e00ff */
/*0540*/ @P0 IMAD.MOV.U32 R5, RZ, RZ, 0x5f5e100 ; /* 0x05f5e100ff050424 */
/* 0x000fe400078e00ff */
/*0550*/ @P0 IMAD.WIDE R2, R2, R3, c[0x0][0x170] ; /* 0x00005c0002020625 */
/* 0x000fca00078e0203 */
/*0560*/ @P0 STG.E [R2.64], R5 ; /* 0x0000000502000986 */
/* 0x0001e8000c101904 */
/*0570*/ @P0 STG.E [R2.64+0x1000], R5 ; /* 0x0010000502000986 */
/* 0x0001e8000c101904 */
/*0580*/ @P0 STG.E [R2.64+0x2000], R5 ; /* 0x0020000502000986 */
/* 0x0001e8000c101904 */
/*0590*/ @P0 STG.E [R2.64+0x3000], R5 ; /* 0x0030000502000986 */
/* 0x0001e4000c101904 */
/*05a0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*05b0*/ ISETP.NE.AND P1, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe20003f25270 */
/*05c0*/ IMAD.MOV.U32 R7, RZ, RZ, RZ ; /* 0x000000ffff077224 */
/* 0x000fd800078e00ff */
/*05d0*/ @!P1 IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff029624 */
/* 0x001fe200078e00ff */
/*05e0*/ @!P1 STS [0x8], RZ ; /* 0x000008ffff009388 */
/* 0x000fe20000000800 */
/*05f0*/ @!P1 IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x174] ; /* 0x00005d00ff039624 */
/* 0x000fe400078e00ff */
/*0600*/ @!P1 IMAD.MOV.U32 R6, RZ, RZ, 0x1 ; /* 0x00000001ff069424 */
/* 0x000fe400078e00ff */
/*0610*/ @!P1 IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x180] ; /* 0x00006000ff049624 */
/* 0x000fe200078e00ff */
/*0620*/ @!P1 STG.E [R2.64], RZ ; /* 0x000000ff02009986 */
/* 0x000fe2000c101904 */
/*0630*/ @!P1 IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x184] ; /* 0x00006100ff059624 */
/* 0x000fc600078e00ff */
/*0640*/ @!P1 STS.64 [RZ], R6 ; /* 0x00000006ff009388 */
/* 0x000fe80000000a00 */
/*0650*/ @!P1 STG.E [R4.64], RZ ; /* 0x000000ff04009986 */
/* 0x000fe8000c101904 */
/*0660*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0670*/ LDS R5, [RZ] ; /* 0x00000000ff057984 */
/* 0x000e240000000800 */
/*0680*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x001fda0003f05270 */
/*0690*/ @!P0 BRA 0x1290 ; /* 0x00000bf000008947 */
/* 0x000fea0003800000 */
/*06a0*/ ISETP.GE.AND P0, PT, R0, R5, PT ; /* 0x000000050000720c */
/* 0x000fda0003f06270 */
/*06b0*/ @P0 BRA 0xa00 ; /* 0x0000034000000947 */
/* 0x016fea0003800000 */
/*06c0*/ IMAD.MOV.U32 R4, RZ, RZ, R0 ; /* 0x000000ffff047224 */
/* 0x000fe400078e0000 */
/*06d0*/ IMAD.MOV.U32 R11, RZ, RZ, 0x4 ; /* 0x00000004ff0b7424 */
/* 0x000fc800078e00ff */
/*06e0*/ IMAD.WIDE R2, R4, R11, c[0x0][0x180] ; /* 0x0000600004027625 */
/* 0x000fca00078e020b */
/*06f0*/ LDG.E R10, [R2.64] ; /* 0x00000004020a7981 */
/* 0x000ea4000c1e1900 */
/*0700*/ IMAD.WIDE R6, R10, R11, c[0x0][0x160] ; /* 0x000058000a067625 */
/* 0x004fca00078e020b */
/*0710*/ LDG.E R8, [R6.64] ; /* 0x0000000406087981 */
/* 0x000ea8000c1e1900 */
/*0720*/ LDG.E R9, [R6.64+0x4] ; /* 0x0000040406097981 */
/* 0x000ea2000c1e1900 */
/*0730*/ IADD3 R4, R4, 0x400, RZ ; /* 0x0000040004047810 */
/* 0x000fe20007ffe0ff */
/*0740*/ BSSY B0, 0x9f0 ; /* 0x000002a000007945 */
/* 0x000fe60003800000 */
/*0750*/ ISETP.GE.AND P0, PT, R4, R5, PT ; /* 0x000000050400720c */
/* 0x000fe40003f06270 */
/*0760*/ ISETP.GE.AND P2, PT, R8, R9, PT ; /* 0x000000090800720c */
/* 0x004fda0003f46270 */
/*0770*/ @P2 BRA 0x9e0 ; /* 0x0000026000002947 */
/* 0x000fea0003800000 */
/*0780*/ IMAD.MOV.U32 R6, RZ, RZ, R8 ; /* 0x000000ffff067224 */
/* 0x000fe400078e0008 */
/*0790*/ IMAD.MOV.U32 R12, RZ, RZ, R10 ; /* 0x000000ffff0c7224 */
/* 0x000fe400078e000a */
/*07a0*/ IMAD.WIDE R8, R6, R11, c[0x0][0x168] ; /* 0x00005a0006087625 */
/* 0x000fc800078e020b */
/*07b0*/ IMAD.MOV.U32 R7, RZ, RZ, 0x4 ; /* 0x00000004ff077424 */
/* 0x000fe200078e00ff */
/*07c0*/ LDG.E R15, [R8.64] ; /* 0x00000004080f7981 */
/* 0x000ea6000c1e1900 */
/*07d0*/ IMAD.WIDE R12, R12, R7, c[0x0][0x170] ; /* 0x00005c000c0c7625 */
/* 0x000fcc00078e0207 */
/*07e0*/ LDG.E R12, [R12.64] ; /* 0x000000040c0c7981 */
/* 0x000ee2000c1e1900 */
/*07f0*/ IMAD.MOV.U32 R16, RZ, RZ, 0x5f5e100 ; /* 0x05f5e100ff107424 */
/* 0x000fe200078e00ff */
/*0800*/ YIELD ; /* 0x0000000000007946 */
/* 0x000fe20003800000 */
/*0810*/ IMAD.WIDE R10, R15, R7, c[0x0][0x170] ; /* 0x00005c000f0a7625 */
/* 0x004fe200078e0207 */
/*0820*/ IADD3 R17, R12, 0x1, RZ ; /* 0x000000010c117810 */
/* 0x008fca0007ffe0ff */
/*0830*/ ATOMG.E.CAS.STRONG.GPU PT, R10, [R10], R16, R17 ; /* 0x000000100a0a73a9 */
/* 0x000ea200001ee111 */
/*0840*/ BSSY B1, 0x950 ; /* 0x0000010000017945 */
/* 0x000fe20003800000 */
/*0850*/ ISETP.NE.AND P2, PT, R10, 0x5f5e100, PT ; /* 0x05f5e1000a00780c */
/* 0x004fda0003f45270 */
/*0860*/ @P2 BRA 0x940 ; /* 0x000000d000002947 */
/* 0x000fea0003800000 */
/*0870*/ S2R R10, SR_LANEID ; /* 0x00000000000a7919 */
/* 0x000e220000000000 */
/*0880*/ VOTEU.ANY UR6, UPT, PT ; /* 0x0000000000067886 */
/* 0x000fe400038e0100 */
/*0890*/ FLO.U32 R13, UR6 ; /* 0x00000006000d7d00 */
/* 0x000e2200080e0000 */
/*08a0*/ S2R R11, SR_LTMASK ; /* 0x00000000000b7919 */
/* 0x000e6e0000003900 */
/*08b0*/ POPC R12, UR6 ; /* 0x00000006000c7d09 */
/* 0x000ea20008000000 */
/*08c0*/ ISETP.EQ.U32.AND P2, PT, R13, R10, PT ; /* 0x0000000a0d00720c */
/* 0x001fc40003f42070 */
/*08d0*/ LOP3.LUT R14, R11, UR6, RZ, 0xc0, !PT ; /* 0x000000060b0e7c12 */
/* 0x002fca000f8ec0ff */
/*08e0*/ POPC R11, R14 ; /* 0x0000000e000b7309 */
/* 0x000e2c0000000000 */
/*08f0*/ @P2 ATOMS.ADD R12, [0x4], R12 ; /* 0x0000040cff0c238c */
/* 0x004e680000000000 */
/*0900*/ SHFL.IDX PT, R10, R12, R13, 0x1f ; /* 0x00001f0d0c0a7589 */
/* 0x002e2400000e0000 */
/*0910*/ IMAD.IADD R10, R10, 0x1, R11 ; /* 0x000000010a0a7824 */
/* 0x001fc800078e020b */
/*0920*/ IMAD.WIDE R10, R10, R7, c[0x0][0x188] ; /* 0x000062000a0a7625 */
/* 0x000fca00078e0207 */
/*0930*/ STG.E [R10.64], R15 ; /* 0x0000000f0a007986 */
/* 0x0001e4000c101904 */
/*0940*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0950*/ LDG.E R12, [R2.64] ; /* 0x00000004020c7981 */
/* 0x000ea4000c1e1900 */
/*0960*/ IADD3 R10, R12, 0x1, RZ ; /* 0x000000010c0a7810 */
/* 0x005fca0007ffe0ff */
/*0970*/ IMAD.WIDE R10, R10, R7, c[0x0][0x160] ; /* 0x000058000a0a7625 */
/* 0x000fcc00078e0207 */
/*0980*/ LDG.E R11, [R10.64] ; /* 0x000000040a0b7981 */
/* 0x000ea2000c1e1900 */
/*0990*/ IADD3 R6, R6, 0x1, RZ ; /* 0x0000000106067810 */
/* 0x000fe40007ffe0ff */
/*09a0*/ IADD3 R8, P3, R8, 0x4, RZ ; /* 0x0000000408087810 */
/* 0x000fca0007f7e0ff */
/*09b0*/ IMAD.X R9, RZ, RZ, R9, P3 ; /* 0x000000ffff097224 */
/* 0x000fe200018e0609 */
/*09c0*/ ISETP.GE.AND P2, PT, R6, R11, PT ; /* 0x0000000b0600720c */
/* 0x004fda0003f46270 */
/*09d0*/ @!P2 BRA 0x7b0 ; /* 0xfffffdd00000a947 */
/* 0x000fea000383ffff */
/*09e0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*09f0*/ @!P0 BRA 0x6d0 ; /* 0xfffffcd000008947 */
/* 0x000fea000383ffff */
/*0a00*/ WARPSYNC 0xffffffff ; /* 0xffffffff00007948 */
/* 0x000fe20003800000 */
/*0a10*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0a20*/ BSSY B0, 0x1250 ; /* 0x0000082000007945 */
/* 0x000fe20003800000 */
/*0a30*/ @P1 BRA 0x1240 ; /* 0x0000080000001947 */
/* 0x000fea0003800000 */
/*0a40*/ LDS R2, [0x4] ; /* 0x00000400ff027984 */
/* 0x000e240000000800 */
/*0a50*/ ISETP.GE.AND P0, PT, R2, 0x1, PT ; /* 0x000000010200780c */
/* 0x001fda0003f06270 */
/*0a60*/ @!P0 BRA 0x11f0 ; /* 0x0000078000008947 */
/* 0x000fea0003800000 */
/*0a70*/ IADD3 R3, R2, -0x1, RZ ; /* 0xffffffff02037810 */
/* 0x000fe20007ffe0ff */
/*0a80*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x000fc600078e00ff */
/*0a90*/ ISETP.GE.U32.AND P0, PT, R3, 0x3, PT ; /* 0x000000030300780c */
/* 0x000fe40003f06070 */
/*0aa0*/ LOP3.LUT R3, R2, 0x3, RZ, 0xc0, !PT ; /* 0x0000000302037812 */
/* 0x000fd600078ec0ff */
/*0ab0*/ @!P0 BRA 0x1100 ; /* 0x0000064000008947 */
/* 0x000fea0003800000 */
/*0ac0*/ IMAD.IADD R5, R2, 0x1, -R3 ; /* 0x0000000102057824 */
/* 0x000fe400078e0a03 */
/*0ad0*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x000fc600078e00ff */
/*0ae0*/ ISETP.GT.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fda0003f04270 */
/*0af0*/ @!P0 BRA 0x1010 ; /* 0x0000051000008947 */
/* 0x000fea0003800000 */
/*0b00*/ ISETP.GT.AND P2, PT, R5, 0xc, PT ; /* 0x0000000c0500780c */
/* 0x000fe40003f44270 */
/*0b10*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*0b20*/ @!P2 BRA 0xe40 ; /* 0x000003100000a947 */
/* 0x000fea0003800000 */
/*0b30*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0b40*/ IMAD.MOV.U32 R7, RZ, RZ, 0x4 ; /* 0x00000004ff077424 */
/* 0x010fc800078e00ff */
/*0b50*/ IMAD.WIDE R8, R4, R7, c[0x0][0x188] ; /* 0x0000620004087625 */
/* 0x000fca00078e0207 */
/*0b60*/ LDG.E R17, [R8.64] ; /* 0x0000000408117981 */
/* 0x000ea2000c1e1900 */
/*0b70*/ IMAD.WIDE R10, R4, R7, c[0x0][0x180] ; /* 0x00006000040a7625 */
/* 0x000fca00078e0207 */
/*0b80*/ STG.E [R10.64], R17 ; /* 0x000000110a007986 */
/* 0x0041e8000c101904 */
/*0b90*/ LDG.E R19, [R8.64+0x4] ; /* 0x0000040408137981 */
/* 0x000ea8000c1e1900 */
/*0ba0*/ STG.E [R10.64+0x4], R19 ; /* 0x000004130a007986 */
/* 0x0043e8000c101904 */
/*0bb0*/ LDG.E R21, [R8.64+0x8] ; /* 0x0000080408157981 */
/* 0x000ea2000c1e1900 */
/*0bc0*/ IADD3 R14, R4, 0x4, RZ ; /* 0x00000004040e7810 */
/* 0x000fc60007ffe0ff */
/*0bd0*/ STG.E [R10.64+0x8], R21 ; /* 0x000008150a007986 */
/* 0x0045e8000c101904 */
/*0be0*/ LDG.E R23, [R8.64+0xc] ; /* 0x00000c0408177981 */
/* 0x000ee2000c1e1900 */
/*0bf0*/ IMAD.WIDE R12, R14, R7, c[0x0][0x188] ; /* 0x000062000e0c7625 */
/* 0x000fc600078e0207 */
/*0c00*/ STG.E [R10.64+0xc], R23 ; /* 0x00000c170a007986 */
/* 0x0087e8000c101904 */
/*0c10*/ LDG.E R25, [R12.64] ; /* 0x000000040c197981 */
/* 0x000f22000c1e1900 */
/*0c20*/ IMAD.WIDE R14, R14, R7, c[0x0][0x180] ; /* 0x000060000e0e7625 */
/* 0x000fca00078e0207 */
/*0c30*/ STG.E [R14.64], R25 ; /* 0x000000190e007986 */
/* 0x0109e8000c101904 */
/*0c40*/ LDG.E R17, [R12.64+0x4] ; /* 0x000004040c117981 */
/* 0x001f68000c1e1900 */
/*0c50*/ STG.E [R14.64+0x4], R17 ; /* 0x000004110e007986 */
/* 0x0201e8000c101904 */
/*0c60*/ LDG.E R19, [R12.64+0x8] ; /* 0x000008040c137981 */
/* 0x002f62000c1e1900 */
/*0c70*/ IADD3 R6, R4, 0x8, RZ ; /* 0x0000000804067810 */
/* 0x000fc60007ffe0ff */
/*0c80*/ STG.E [R14.64+0x8], R19 ; /* 0x000008130e007986 */
/* 0x0203e8000c101904 */
/*0c90*/ LDG.E R21, [R12.64+0xc] ; /* 0x00000c040c157981 */
/* 0x004ea2000c1e1900 */
/*0ca0*/ IMAD.WIDE R8, R6, R7, c[0x0][0x188] ; /* 0x0000620006087625 */
/* 0x000fc600078e0207 */
/*0cb0*/ STG.E [R14.64+0xc], R21 ; /* 0x00000c150e007986 */
/* 0x0045e8000c101904 */
/*0cc0*/ LDG.E R23, [R8.64] ; /* 0x0000000408177981 */
/* 0x008ee2000c1e1900 */
/*0cd0*/ IMAD.WIDE R10, R6, R7, c[0x0][0x180] ; /* 0x00006000060a7625 */
/* 0x000fca00078e0207 */
/*0ce0*/ STG.E [R10.64], R23 ; /* 0x000000170a007986 */
/* 0x0087e8000c101904 */
/*0cf0*/ LDG.E R25, [R8.64+0x4] ; /* 0x0000040408197981 */
/* 0x010f28000c1e1900 */
/*0d00*/ STG.E [R10.64+0x4], R25 ; /* 0x000004190a007986 */
/* 0x0109e8000c101904 */
/*0d10*/ LDG.E R17, [R8.64+0x8] ; /* 0x0000080408117981 */
/* 0x001f62000c1e1900 */
/*0d20*/ IADD3 R6, R4, 0xc, RZ ; /* 0x0000000c04067810 */
/* 0x000fc60007ffe0ff */
/*0d30*/ STG.E [R10.64+0x8], R17 ; /* 0x000008110a007986 */
/* 0x0209e8000c101904 */
/*0d40*/ LDG.E R19, [R8.64+0xc] ; /* 0x00000c0408137981 */
/* 0x002f62000c1e1900 */
/*0d50*/ IMAD.WIDE R12, R6, R7, c[0x0][0x188] ; /* 0x00006200060c7625 */
/* 0x000fc600078e0207 */
/*0d60*/ STG.E [R10.64+0xc], R19 ; /* 0x00000c130a007986 */
/* 0x0209e8000c101904 */
/*0d70*/ LDG.E R15, [R12.64] ; /* 0x000000040c0f7981 */
/* 0x004ea2000c1e1900 */
/*0d80*/ IMAD.WIDE R6, R6, R7, c[0x0][0x180] ; /* 0x0000600006067625 */
/* 0x000fca00078e0207 */
/*0d90*/ STG.E [R6.64], R15 ; /* 0x0000000f06007986 */
/* 0x0049e8000c101904 */
/*0da0*/ LDG.E R21, [R12.64+0x4] ; /* 0x000004040c157981 */
/* 0x000ea8000c1e1900 */
/*0db0*/ STG.E [R6.64+0x4], R21 ; /* 0x0000041506007986 */
/* 0x0049e8000c101904 */
/*0dc0*/ LDG.E R23, [R12.64+0x8] ; /* 0x000008040c177981 */
/* 0x008ea8000c1e1900 */
/*0dd0*/ STG.E [R6.64+0x8], R23 ; /* 0x0000081706007986 */
/* 0x0049e8000c101904 */
/*0de0*/ LDG.E R9, [R12.64+0xc] ; /* 0x00000c040c097981 */
/* 0x000ea2000c1e1900 */
/*0df0*/ IADD3 R5, R5, -0x10, RZ ; /* 0xfffffff005057810 */
/* 0x000fc40007ffe0ff */
/*0e00*/ IADD3 R4, R4, 0x10, RZ ; /* 0x0000001004047810 */
/* 0x000fe40007ffe0ff */
/*0e10*/ ISETP.GT.AND P2, PT, R5, 0xc, PT ; /* 0x0000000c0500780c */
/* 0x000fe20003f44270 */
/*0e20*/ STG.E [R6.64+0xc], R9 ; /* 0x00000c0906007986 */
/* 0x0049d8000c101904 */
/*0e30*/ @P2 BRA 0xb40 ; /* 0xfffffd0000002947 */
/* 0x000fea000383ffff */
/*0e40*/ ISETP.GT.AND P2, PT, R5, 0x4, PT ; /* 0x000000040500780c */
/* 0x000fda0003f44270 */
/*0e50*/ @!P2 BRA 0xff0 ; /* 0x000001900000a947 */
/* 0x000fea0003800000 */
/*0e60*/ IMAD.MOV.U32 R13, RZ, RZ, 0x4 ; /* 0x00000004ff0d7424 */
/* 0x000fc800078e00ff */
/*0e70*/ IMAD.WIDE R6, R4, R13, c[0x0][0x188] ; /* 0x0000620004067625 */
/* 0x010fca00078e020d */
/*0e80*/ LDG.E R15, [R6.64] ; /* 0x00000004060f7981 */
/* 0x000ea2000c1e1900 */
/*0e90*/ IMAD.WIDE R8, R4, R13, c[0x0][0x180] ; /* 0x0000600004087625 */
/* 0x000fca00078e020d */
/*0ea0*/ STG.E [R8.64], R15 ; /* 0x0000000f08007986 */
/* 0x0041e8000c101904 */
/*0eb0*/ LDG.E R17, [R6.64+0x4] ; /* 0x0000040406117981 */
/* 0x000ea8000c1e1900 */
/*0ec0*/ STG.E [R8.64+0x4], R17 ; /* 0x0000041108007986 */
/* 0x0043e8000c101904 */
/*0ed0*/ LDG.E R19, [R6.64+0x8] ; /* 0x0000080406137981 */
/* 0x000ea2000c1e1900 */
/*0ee0*/ IADD3 R12, R4, 0x4, RZ ; /* 0x00000004040c7810 */
/* 0x000fc60007ffe0ff */
/*0ef0*/ STG.E [R8.64+0x8], R19 ; /* 0x0000081308007986 */
/* 0x0045e8000c101904 */
/*0f00*/ LDG.E R21, [R6.64+0xc] ; /* 0x00000c0406157981 */
/* 0x000ee2000c1e1900 */
/*0f10*/ IMAD.WIDE R10, R12, R13, c[0x0][0x188] ; /* 0x000062000c0a7625 */
/* 0x000fc600078e020d */
/*0f20*/ STG.E [R8.64+0xc], R21 ; /* 0x00000c1508007986 */
/* 0x0085e8000c101904 */
/*0f30*/ LDG.E R23, [R10.64] ; /* 0x000000040a177981 */
/* 0x000ee2000c1e1900 */
/*0f40*/ IMAD.WIDE R12, R12, R13, c[0x0][0x180] ; /* 0x000060000c0c7625 */
/* 0x000fca00078e020d */
/*0f50*/ STG.E [R12.64], R23 ; /* 0x000000170c007986 */
/* 0x0085e8000c101904 */
/*0f60*/ LDG.E R15, [R10.64+0x4] ; /* 0x000004040a0f7981 */
/* 0x001ee8000c1e1900 */
/*0f70*/ STG.E [R12.64+0x4], R15 ; /* 0x0000040f0c007986 */
/* 0x0085e8000c101904 */
/*0f80*/ LDG.E R17, [R10.64+0x8] ; /* 0x000008040a117981 */
/* 0x002ee8000c1e1900 */
/*0f90*/ STG.E [R12.64+0x8], R17 ; /* 0x000008110c007986 */
/* 0x0085e8000c101904 */
/*0fa0*/ LDG.E R7, [R10.64+0xc] ; /* 0x00000c040a077981 */
/* 0x000ee2000c1e1900 */
/*0fb0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc40003f0e170 */
/*0fc0*/ IADD3 R5, R5, -0x8, RZ ; /* 0xfffffff805057810 */
/* 0x000fe40007ffe0ff */
/*0fd0*/ IADD3 R4, R4, 0x8, RZ ; /* 0x0000000804047810 */
/* 0x000fe20007ffe0ff */
/*0fe0*/ STG.E [R12.64+0xc], R7 ; /* 0x00000c070c007986 */
/* 0x0085e8000c101904 */
/*0ff0*/ ISETP.NE.OR P0, PT, R5, RZ, P0 ; /* 0x000000ff0500720c */
/* 0x000fda0000705670 */
/*1000*/ @!P0 BRA 0x1100 ; /* 0x000000f000008947 */
/* 0x000fea0003800000 */
/*1010*/ IMAD.MOV.U32 R9, RZ, RZ, 0x4 ; /* 0x00000004ff097424 */
/* 0x014fc800078e00ff */
/*1020*/ IMAD.WIDE R6, R4, R9, c[0x0][0x188] ; /* 0x0000620004067625 */
/* 0x000fca00078e0209 */
/*1030*/ LDG.E R11, [R6.64] ; /* 0x00000004060b7981 */
/* 0x000ea2000c1e1900 */
/*1040*/ IMAD.WIDE R8, R4, R9, c[0x0][0x180] ; /* 0x0000600004087625 */
/* 0x000fca00078e0209 */
/*1050*/ STG.E [R8.64], R11 ; /* 0x0000000b08007986 */
/* 0x0041e8000c101904 */
/*1060*/ LDG.E R13, [R6.64+0x4] ; /* 0x00000404060d7981 */
/* 0x000ea8000c1e1900 */
/*1070*/ STG.E [R8.64+0x4], R13 ; /* 0x0000040d08007986 */
/* 0x0041e8000c101904 */
/*1080*/ LDG.E R15, [R6.64+0x8] ; /* 0x00000804060f7981 */
/* 0x000ea8000c1e1900 */
/*1090*/ STG.E [R8.64+0x8], R15 ; /* 0x0000080f08007986 */
/* 0x0041e8000c101904 */
/*10a0*/ LDG.E R17, [R6.64+0xc] ; /* 0x00000c0406117981 */
/* 0x000ea2000c1e1900 */
/*10b0*/ IADD3 R5, R5, -0x4, RZ ; /* 0xfffffffc05057810 */
/* 0x000fc40007ffe0ff */
/*10c0*/ IADD3 R4, R4, 0x4, RZ ; /* 0x0000000404047810 */
/* 0x000fe40007ffe0ff */
/*10d0*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe20003f05270 */
/*10e0*/ STG.E [R8.64+0xc], R17 ; /* 0x00000c1108007986 */
/* 0x0041d8000c101904 */
/*10f0*/ @P0 BRA 0x1010 ; /* 0xffffff1000000947 */
/* 0x001fea000383ffff */
/*1100*/ ISETP.NE.AND P0, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fda0003f05270 */
/*1110*/ @!P0 BRA 0x11f0 ; /* 0x000000d000008947 */
/* 0x000fea0003800000 */
/*1120*/ IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; /* 0x00000004ff057424 */
/* 0x000fc800078e00ff */
/*1130*/ IMAD.WIDE R6, R4, R5, c[0x0][0x188] ; /* 0x0000620004067625 */
/* 0x014fca00078e0205 */
/*1140*/ LDG.E R9, [R6.64] ; /* 0x0000000406097981 */
/* 0x000ea2000c1e1900 */
/*1150*/ IMAD.WIDE R4, R4, R5, c[0x0][0x180] ; /* 0x0000600004047625 */
/* 0x000fe200078e0205 */
/*1160*/ ISETP.NE.AND P0, PT, R3, 0x1, PT ; /* 0x000000010300780c */
/* 0x000fc80003f05270 */
/*1170*/ STG.E [R4.64], R9 ; /* 0x0000000904007986 */
/* 0x0041f2000c101904 */
/*1180*/ @!P0 BRA 0x11f0 ; /* 0x0000006000008947 */
/* 0x000fea0003800000 */
/*1190*/ LDG.E R9, [R6.64+0x4] ; /* 0x0000040406097981 */
/* 0x001ea2000c1e1900 */
/*11a0*/ ISETP.NE.AND P0, PT, R3, 0x2, PT ; /* 0x000000020300780c */
/* 0x000fc60003f05270 */
/*11b0*/ STG.E [R4.64+0x4], R9 ; /* 0x0000040904007986 */
/* 0x0041f4000c101904 */
/*11c0*/ @!P0 BRA 0x11f0 ; /* 0x0000002000008947 */
/* 0x000fea0003800000 */
/*11d0*/ LDG.E R7, [R6.64+0x8] ; /* 0x0000080406077981 */
/* 0x000ea8000c1e1900 */
/*11e0*/ STG.E [R4.64+0x8], R7 ; /* 0x0000080704007986 */
/* 0x0043e4000c101904 */
/*11f0*/ LDS R4, [0x8] ; /* 0x00000800ff047984 */
/* 0x003e220000000800 */
/*1200*/ IMAD.MOV.U32 R3, RZ, RZ, RZ ; /* 0x000000ffff037224 */
/* 0x000fca00078e00ff */
/*1210*/ STS.64 [RZ], R2 ; /* 0x00000002ff007388 */
/* 0x0003e20000000a00 */
/*1220*/ IADD3 R4, R4, 0x1, RZ ; /* 0x0000000104047810 */
/* 0x001fca0007ffe0ff */
/*1230*/ STS [0x8], R4 ; /* 0x00000804ff007388 */
/* 0x0003e40000000800 */
/*1240*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*1250*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*1260*/ LDS R5, [RZ] ; /* 0x00000000ff057984 */
/* 0x000e240000000800 */
/*1270*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x001fda0003f05270 */
/*1280*/ @P0 BRA 0x6a0 ; /* 0xfffff41000000947 */
/* 0x000fea000383ffff */
/*1290*/ LDS R5, [0x8] ; /* 0x00000800ff057984 */
/* 0x000e220000000800 */
/*12a0*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x178] ; /* 0x00005e00ff027624 */
/* 0x002fe400078e00ff */
/*12b0*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x17c] ; /* 0x00005f00ff037624 */
/* 0x000fca00078e00ff */
/*12c0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x001fe2000c101904 */
/*12d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*12e0*/ BRA 0x12e0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*12f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1300*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1310*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1320*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include<bits/stdc++.h>
using namespace std;
#define MAX_VAL ((int)1e8)
#define cudaCatchError(error) { gpuAssert((error), __FILE__, __LINE__); }
// Catch Cuda errors
inline void gpuAssert(cudaError_t error, const char *file, int line, bool abort = false)
{
if (error != cudaSuccess)
{
printf("\n====== Cuda Error Code %i ======\n %s in CUDA %s\n", error, cudaGetErrorString(error));
printf("\nIn file :%s\nOn line: %d", file, line);
if(abort)
exit(-1);
}
}
__global__ void compute(int *d_r, int *d_c, int *d_depth, int *max_depth, int *Q1, int *Q2, int nodes){
int idx = threadIdx.x;
__shared__ int len1, len2, curr_depth;
int i;
for(i=idx; i<nodes; i+=1024){
d_depth[i] = MAX_VAL;
}
if(idx == 0){
d_depth[0] = 0;
curr_depth = 0;
len1 = 1;
len2 = 0;
Q1[0] = 0;
}
__syncthreads();
while(len1){
for(i=idx; i<len1; i+=1024){
for(int j=d_r[Q1[i]]; j<d_r[Q1[i]+1]; j++){
int v = d_c[j];
if(atomicCAS(&d_depth[v], MAX_VAL, d_depth[Q1[i]]+1) == MAX_VAL){
int t = atomicAdd(&len2,1);
Q2[t] = v;
}
}
}
__syncthreads();
if(idx==0){
for(i=0; i<len2; i++){
Q1[i] = Q2[i];
}
len1 = len2;
len2 = 0;
curr_depth++;
}
__syncthreads();
}
max_depth[0] = curr_depth;
}
int main(int argc, char *argv[]){
if(argc<2){
cout << "Usage: " << argv[0] << " <graph_file_name>\n";
return 0;
}
ifstream input;
input.open(argv[1]);
int nodes, edges, i;
input >> nodes;
input >> edges;
// allocating host memory
int *h_r = (int*)malloc((nodes+1)*sizeof(int));
int *h_c = (int*)malloc(edges*2*sizeof(int));
// reading inputs
for(i=0; i<nodes+1; i++){
input >> h_r[i];
}
for(i=0; i<edges*2; i++){
input >> h_c[i];
}
// allocating device memory
int *Q1, *Q2, *d_r, *d_c, *d_depth, *max_depth;
cudaMalloc((void**)&Q1, nodes*sizeof(int));
cudaMalloc((void**)&Q2, nodes*sizeof(int));
cudaMalloc((void**)&d_r, (nodes+1)*sizeof(int));
cudaMalloc((void**)&d_c, edges*2*sizeof(int));
cudaMalloc((void**)&d_depth, nodes*sizeof(int));
cudaMalloc((void**)&max_depth, sizeof(int));
// copying data to device
cudaMemcpy(d_r, h_r, (nodes+1)*sizeof(int), cudaMemcpyHostToDevice);
cudaMemcpy(d_c, h_c, edges*2*sizeof(int), cudaMemcpyHostToDevice);
// timer
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaEventRecord(start);
// kernel call
printf("Starting Computation\n");
compute <<<1, 1024>>> (d_r, d_c, d_depth, max_depth, Q1, Q2, nodes);
cudaThreadSynchronize();
printf("Finished Computation\n");
// timer
cudaEventRecord(stop);
cudaEventSynchronize(stop);
float milliseconds = 0;
cudaEventElapsedTime(&milliseconds, start, stop);
cout<<"Compute time in GPU: "<<milliseconds<<"ms"<<endl;
// copying results to host
int *result = (int *)malloc(sizeof(int));
cudaCatchError(cudaMemcpy(result, max_depth, sizeof(int), cudaMemcpyDeviceToHost));
printf("Depth : %d\n", result[0]-1);
// solution check
int *h_depth = (int*) malloc(nodes*sizeof(int));
cudaMemcpy(h_depth, d_depth, nodes*sizeof(int), cudaMemcpyDeviceToHost);
int *h_check_depth = (int*)malloc(nodes*sizeof(int));
freopen(argv[2], "r", stdin);
printf("malloc done\n");
for(int i = 0; i < nodes; i++) {
cin>>h_check_depth[i];
}
printf("Finished reading output file\n");
bool flag = true;
int count = 0;
printf("Starting checking\n");
for(int i = 0; i < nodes; i++) {
if(h_depth[i] != h_check_depth[i]) {
printf("Found %d, Expected %d\n",h_depth[i], h_check_depth[i]);
flag = false;
count++;
}
}
printf("Finished checking\n");
if(flag) {
cout<<"Solution is correct!\n";
}
else {
cout<<"Solution is incorrect!"<<endl;
cout<<count<<" testcases failed.\n";
}
return 0;
} | .file "tmpxft_0005cd27_00000000-6_parallel_BFS_work_efficient.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB10863:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE10863:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z37__device_stub__Z7computePiS_S_S_S_S_iPiS_S_S_S_S_i
.type _Z37__device_stub__Z7computePiS_S_S_S_S_iPiS_S_S_S_S_i, @function
_Z37__device_stub__Z7computePiS_S_S_S_S_iPiS_S_S_S_S_i:
.LFB10885:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movq %r8, 8(%rsp)
movq %r9, (%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
movq %rsp, %rax
movq %rax, 152(%rsp)
leaq 192(%rsp), %rax
movq %rax, 160(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z7computePiS_S_S_S_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE10885:
.size _Z37__device_stub__Z7computePiS_S_S_S_S_iPiS_S_S_S_S_i, .-_Z37__device_stub__Z7computePiS_S_S_S_S_iPiS_S_S_S_S_i
.globl _Z7computePiS_S_S_S_S_i
.type _Z7computePiS_S_S_S_S_i, @function
_Z7computePiS_S_S_S_S_i:
.LFB10886:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
call _Z37__device_stub__Z7computePiS_S_S_S_S_iPiS_S_S_S_S_i
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE10886:
.size _Z7computePiS_S_S_S_S_i, .-_Z7computePiS_S_S_S_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z7computePiS_S_S_S_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB10888:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z7computePiS_S_S_S_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE10888:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .rodata.str1.1
.LC1:
.string "Usage: "
.LC2:
.string " <graph_file_name>\n"
.LC3:
.string "Starting Computation\n"
.LC4:
.string "Finished Computation\n"
.LC6:
.string "Compute time in GPU: "
.LC7:
.string "ms"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC8:
.string "\n====== Cuda Error Code %i ======\n %s in CUDA %s\n"
.align 8
.LC9:
.string "/home/ubuntu/Datasets/stackv2/train-structured/vrn25/CUDA-Playground/master/BreadthFirstSearch/parallel_BFS_work_efficient.cu"
.section .rodata.str1.1
.LC10:
.string "\nIn file :%s\nOn line: %d"
.LC11:
.string "Depth : %d\n"
.LC12:
.string "r"
.LC13:
.string "malloc done\n"
.LC14:
.string "Finished reading output file\n"
.LC15:
.string "Starting checking\n"
.LC16:
.string "Found %d, Expected %d\n"
.LC17:
.string "Finished checking\n"
.LC18:
.string "Solution is correct!\n"
.LC19:
.string "Solution is incorrect!"
.LC20:
.string " testcases failed.\n"
.text
.globl main
.type main, @function
main:
.LFB10860:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA10860
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
movq %rsp, %rbp
.cfi_def_cfa_register 6
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $648, %rsp
.cfi_offset 15, -24
.cfi_offset 14, -32
.cfi_offset 13, -40
.cfi_offset 12, -48
.cfi_offset 3, -56
movq %rsi, %r13
movq %fs:40, %rax
movq %rax, -56(%rbp)
xorl %eax, %eax
cmpl $1, %edi
jle .L40
leaq -576(%rbp), %rbx
movq %rbx, %rdi
.LEHB0:
call _ZNSt14basic_ifstreamIcSt11char_traitsIcEEC1Ev@PLT
.LEHE0:
movq 8(%r13), %rsi
movl $8, %edx
movq %rbx, %rdi
.LEHB1:
call _ZNSt14basic_ifstreamIcSt11char_traitsIcEE4openEPKcSt13_Ios_Openmode@PLT
.LEHE1:
jmp .L41
.L40:
leaq .LC1(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
.LEHB2:
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq 0(%r13), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
leaq .LC2(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
.LEHE2:
jmp .L15
.L41:
leaq -672(%rbp), %rsi
movq %rbx, %rdi
.LEHB3:
call _ZNSirsERi@PLT
leaq -668(%rbp), %rsi
movq %rbx, %rdi
call _ZNSirsERi@PLT
movl -672(%rbp), %ebx
leal 1(%rbx), %edi
movslq %edi, %rdi
salq $2, %rdi
call malloc@PLT
movq %rax, %r15
movl -668(%rbp), %eax
leal (%rax,%rax), %edi
movslq %edi, %rdi
salq $2, %rdi
call malloc@PLT
movq %rax, %r14
testl %ebx, %ebx
js .L16
movq %r15, -680(%rbp)
movl $0, %ebx
leaq -576(%rbp), %r12
jmp .L17
.L42:
addl $1, %ebx
addq $4, -680(%rbp)
cmpl %ebx, -672(%rbp)
jl .L16
.L17:
movq -680(%rbp), %rsi
movq %r12, %rdi
call _ZNSirsERi@PLT
jmp .L42
.L16:
cmpl $0, -668(%rbp)
jle .L18
movq %r14, -680(%rbp)
movl $0, %ebx
leaq -576(%rbp), %r12
jmp .L19
.L43:
addl $1, %ebx
addq $4, -680(%rbp)
movl -668(%rbp), %eax
addl %eax, %eax
cmpl %ebx, %eax
jle .L18
.L19:
movq -680(%rbp), %rsi
movq %r12, %rdi
call _ZNSirsERi@PLT
jmp .L43
.L18:
movslq -672(%rbp), %rsi
salq $2, %rsi
leaq -664(%rbp), %rdi
call cudaMalloc@PLT
movslq -672(%rbp), %rsi
salq $2, %rsi
leaq -656(%rbp), %rdi
call cudaMalloc@PLT
movl -672(%rbp), %eax
leal 1(%rax), %esi
movslq %esi, %rsi
salq $2, %rsi
leaq -648(%rbp), %rdi
call cudaMalloc@PLT
movl -668(%rbp), %eax
leal (%rax,%rax), %esi
movslq %esi, %rsi
salq $2, %rsi
leaq -640(%rbp), %rdi
call cudaMalloc@PLT
movslq -672(%rbp), %rsi
salq $2, %rsi
leaq -632(%rbp), %rdi
call cudaMalloc@PLT
leaq -624(%rbp), %rdi
movl $4, %esi
call cudaMalloc@PLT
movl -672(%rbp), %eax
leal 1(%rax), %edx
movslq %edx, %rdx
salq $2, %rdx
movl $1, %ecx
movq %r15, %rsi
movq -648(%rbp), %rdi
call cudaMemcpy@PLT
movl -668(%rbp), %eax
leal (%rax,%rax), %edx
movslq %edx, %rdx
salq $2, %rdx
movl $1, %ecx
movq %r14, %rsi
movq -640(%rbp), %rdi
call cudaMemcpy@PLT
leaq -616(%rbp), %rdi
call cudaEventCreate@PLT
leaq -608(%rbp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq -616(%rbp), %rdi
call cudaEventRecord@PLT
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1024, -588(%rbp)
movl $1, -584(%rbp)
movl $1, -580(%rbp)
movl $1, -600(%rbp)
movl $1, -596(%rbp)
movl $0, %r9d
movl $0, %r8d
movq -588(%rbp), %rdx
movl $1, %ecx
movq -600(%rbp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L20
subq $8, %rsp
movl -672(%rbp), %eax
pushq %rax
movq -656(%rbp), %r9
movq -664(%rbp), %r8
movq -624(%rbp), %rcx
movq -632(%rbp), %rdx
movq -640(%rbp), %rsi
movq -648(%rbp), %rdi
.cfi_escape 0x2e,0x10
call _Z37__device_stub__Z7computePiS_S_S_S_S_iPiS_S_S_S_S_i
addq $16, %rsp
.L20:
.cfi_escape 0x2e,0
call cudaThreadSynchronize@PLT
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %esi
movq -608(%rbp), %rdi
call cudaEventRecord@PLT
movq -608(%rbp), %rdi
call cudaEventSynchronize@PLT
movl $0x00000000, -588(%rbp)
leaq -588(%rbp), %rdi
movq -608(%rbp), %rdx
movq -616(%rbp), %rsi
call cudaEventElapsedTime@PLT
leaq .LC6(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
pxor %xmm0, %xmm0
cvtss2sd -588(%rbp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
leaq .LC7(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $4, %edi
call malloc@PLT
movq %rax, %rbx
movl $2, %ecx
movl $4, %edx
movq -624(%rbp), %rsi
movq %rax, %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L44
.L21:
movl (%rbx), %edx
subl $1, %edx
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L45
.L44:
movl %eax, %r14d
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl %r14d, %edx
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $124, %ecx
leaq .LC9(%rip), %rdx
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L21
.L45:
movslq -672(%rbp), %rbx
salq $2, %rbx
movq %rbx, %rdi
call malloc@PLT
movq %rax, %r12
movl $2, %ecx
movq %rbx, %rdx
movq -632(%rbp), %rsi
movq %rax, %rdi
call cudaMemcpy@PLT
movslq -672(%rbp), %rdi
salq $2, %rdi
call malloc@PLT
movq %rax, %r14
movq 16(%r13), %rdi
movq stdin(%rip), %rdx
leaq .LC12(%rip), %rsi
call freopen@PLT
leaq .LC13(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
cmpl $0, -672(%rbp)
jle .L22
movq %r14, %rax
movl $0, %ebx
leaq _ZSt3cin(%rip), %r13
jmp .L23
.L46:
addl $1, %ebx
movq %r15, %rax
addq $4, %rax
cmpl %ebx, -672(%rbp)
jle .L22
.L23:
movq %rax, %r15
movq %rax, %rsi
movq %r13, %rdi
call _ZNSirsERi@PLT
jmp .L46
.L22:
leaq .LC14(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC15(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
cmpl $0, -672(%rbp)
jle .L32
movl $0, %ebx
movl $0, -680(%rbp)
movl $1, %r13d
leaq .LC16(%rip), %r15
jmp .L26
.L47:
addl $1, -680(%rbp)
movl $0, %r13d
.L25:
addq $1, %rbx
cmpl %ebx, -672(%rbp)
jle .L24
.L26:
movl (%r12,%rbx,4), %edx
movl (%r14,%rbx,4), %ecx
cmpl %ecx, %edx
je .L25
movq %r15, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L47
.L32:
movl $0, -680(%rbp)
movl $1, %r13d
.L24:
leaq .LC17(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
testb %r13b, %r13b
je .L27
leaq .LC18(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
jmp .L28
.L27:
leaq .LC19(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl -680(%rbp), %esi
leaq _ZSt4cout(%rip), %rdi
call _ZNSolsEi@PLT
movq %rax, %rdi
leaq .LC20(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
.LEHE3:
.L28:
leaq -576(%rbp), %rdi
call _ZNSt14basic_ifstreamIcSt11char_traitsIcEED1Ev@PLT
.L15:
movq -56(%rbp), %rax
subq %fs:40, %rax
jne .L48
movl $0, %eax
leaq -40(%rbp), %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
.cfi_remember_state
.cfi_def_cfa 7, 8
ret
.L33:
.cfi_restore_state
endbr64
movq %rax, %rbx
leaq -576(%rbp), %rdi
call _ZNSt14basic_ifstreamIcSt11char_traitsIcEED1Ev@PLT
movq -56(%rbp), %rax
subq %fs:40, %rax
je .L30
call __stack_chk_fail@PLT
.L30:
movq %rbx, %rdi
.LEHB4:
call _Unwind_Resume@PLT
.LEHE4:
.L48:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE10860:
.globl __gxx_personality_v0
.section .gcc_except_table,"a",@progbits
.LLSDA10860:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE10860-.LLSDACSB10860
.LLSDACSB10860:
.uleb128 .LEHB0-.LFB10860
.uleb128 .LEHE0-.LEHB0
.uleb128 0
.uleb128 0
.uleb128 .LEHB1-.LFB10860
.uleb128 .LEHE1-.LEHB1
.uleb128 .L33-.LFB10860
.uleb128 0
.uleb128 .LEHB2-.LFB10860
.uleb128 .LEHE2-.LEHB2
.uleb128 0
.uleb128 0
.uleb128 .LEHB3-.LFB10860
.uleb128 .LEHE3-.LEHB3
.uleb128 .L33-.LFB10860
.uleb128 0
.uleb128 .LEHB4-.LFB10860
.uleb128 .LEHE4-.LEHB4
.uleb128 0
.uleb128 0
.LLSDACSE10860:
.text
.size main, .-main
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.hidden DW.ref.__gxx_personality_v0
.weak DW.ref.__gxx_personality_v0
.section .data.rel.local.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat
.align 8
.type DW.ref.__gxx_personality_v0, @object
.size DW.ref.__gxx_personality_v0, 8
DW.ref.__gxx_personality_v0:
.quad __gxx_personality_v0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include<bits/stdc++.h>
using namespace std;
#define MAX_VAL ((int)1e8)
#define cudaCatchError(error) { gpuAssert((error), __FILE__, __LINE__); }
// Catch Cuda errors
inline void gpuAssert(cudaError_t error, const char *file, int line, bool abort = false)
{
if (error != cudaSuccess)
{
printf("\n====== Cuda Error Code %i ======\n %s in CUDA %s\n", error, cudaGetErrorString(error));
printf("\nIn file :%s\nOn line: %d", file, line);
if(abort)
exit(-1);
}
}
__global__ void compute(int *d_r, int *d_c, int *d_depth, int *max_depth, int *Q1, int *Q2, int nodes){
int idx = threadIdx.x;
__shared__ int len1, len2, curr_depth;
int i;
for(i=idx; i<nodes; i+=1024){
d_depth[i] = MAX_VAL;
}
if(idx == 0){
d_depth[0] = 0;
curr_depth = 0;
len1 = 1;
len2 = 0;
Q1[0] = 0;
}
__syncthreads();
while(len1){
for(i=idx; i<len1; i+=1024){
for(int j=d_r[Q1[i]]; j<d_r[Q1[i]+1]; j++){
int v = d_c[j];
if(atomicCAS(&d_depth[v], MAX_VAL, d_depth[Q1[i]]+1) == MAX_VAL){
int t = atomicAdd(&len2,1);
Q2[t] = v;
}
}
}
__syncthreads();
if(idx==0){
for(i=0; i<len2; i++){
Q1[i] = Q2[i];
}
len1 = len2;
len2 = 0;
curr_depth++;
}
__syncthreads();
}
max_depth[0] = curr_depth;
}
int main(int argc, char *argv[]){
if(argc<2){
cout << "Usage: " << argv[0] << " <graph_file_name>\n";
return 0;
}
ifstream input;
input.open(argv[1]);
int nodes, edges, i;
input >> nodes;
input >> edges;
// allocating host memory
int *h_r = (int*)malloc((nodes+1)*sizeof(int));
int *h_c = (int*)malloc(edges*2*sizeof(int));
// reading inputs
for(i=0; i<nodes+1; i++){
input >> h_r[i];
}
for(i=0; i<edges*2; i++){
input >> h_c[i];
}
// allocating device memory
int *Q1, *Q2, *d_r, *d_c, *d_depth, *max_depth;
cudaMalloc((void**)&Q1, nodes*sizeof(int));
cudaMalloc((void**)&Q2, nodes*sizeof(int));
cudaMalloc((void**)&d_r, (nodes+1)*sizeof(int));
cudaMalloc((void**)&d_c, edges*2*sizeof(int));
cudaMalloc((void**)&d_depth, nodes*sizeof(int));
cudaMalloc((void**)&max_depth, sizeof(int));
// copying data to device
cudaMemcpy(d_r, h_r, (nodes+1)*sizeof(int), cudaMemcpyHostToDevice);
cudaMemcpy(d_c, h_c, edges*2*sizeof(int), cudaMemcpyHostToDevice);
// timer
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaEventRecord(start);
// kernel call
printf("Starting Computation\n");
compute <<<1, 1024>>> (d_r, d_c, d_depth, max_depth, Q1, Q2, nodes);
cudaThreadSynchronize();
printf("Finished Computation\n");
// timer
cudaEventRecord(stop);
cudaEventSynchronize(stop);
float milliseconds = 0;
cudaEventElapsedTime(&milliseconds, start, stop);
cout<<"Compute time in GPU: "<<milliseconds<<"ms"<<endl;
// copying results to host
int *result = (int *)malloc(sizeof(int));
cudaCatchError(cudaMemcpy(result, max_depth, sizeof(int), cudaMemcpyDeviceToHost));
printf("Depth : %d\n", result[0]-1);
// solution check
int *h_depth = (int*) malloc(nodes*sizeof(int));
cudaMemcpy(h_depth, d_depth, nodes*sizeof(int), cudaMemcpyDeviceToHost);
int *h_check_depth = (int*)malloc(nodes*sizeof(int));
freopen(argv[2], "r", stdin);
printf("malloc done\n");
for(int i = 0; i < nodes; i++) {
cin>>h_check_depth[i];
}
printf("Finished reading output file\n");
bool flag = true;
int count = 0;
printf("Starting checking\n");
for(int i = 0; i < nodes; i++) {
if(h_depth[i] != h_check_depth[i]) {
printf("Found %d, Expected %d\n",h_depth[i], h_check_depth[i]);
flag = false;
count++;
}
}
printf("Finished checking\n");
if(flag) {
cout<<"Solution is correct!\n";
}
else {
cout<<"Solution is incorrect!"<<endl;
cout<<count<<" testcases failed.\n";
}
return 0;
} | #include <hip/hip_runtime.h>
#include<bits/stdc++.h>
using namespace std;
#define MAX_VAL ((int)1e8)
#define cudaCatchError(error) { gpuAssert((error), __FILE__, __LINE__); }
// Catch Cuda errors
inline void gpuAssert(hipError_t error, const char *file, int line, bool abort = false)
{
if (error != hipSuccess)
{
printf("\n====== Cuda Error Code %i ======\n %s in CUDA %s\n", error, hipGetErrorString(error));
printf("\nIn file :%s\nOn line: %d", file, line);
if(abort)
exit(-1);
}
}
__global__ void compute(int *d_r, int *d_c, int *d_depth, int *max_depth, int *Q1, int *Q2, int nodes){
int idx = threadIdx.x;
__shared__ int len1, len2, curr_depth;
int i;
for(i=idx; i<nodes; i+=1024){
d_depth[i] = MAX_VAL;
}
if(idx == 0){
d_depth[0] = 0;
curr_depth = 0;
len1 = 1;
len2 = 0;
Q1[0] = 0;
}
__syncthreads();
while(len1){
for(i=idx; i<len1; i+=1024){
for(int j=d_r[Q1[i]]; j<d_r[Q1[i]+1]; j++){
int v = d_c[j];
if(atomicCAS(&d_depth[v], MAX_VAL, d_depth[Q1[i]]+1) == MAX_VAL){
int t = atomicAdd(&len2,1);
Q2[t] = v;
}
}
}
__syncthreads();
if(idx==0){
for(i=0; i<len2; i++){
Q1[i] = Q2[i];
}
len1 = len2;
len2 = 0;
curr_depth++;
}
__syncthreads();
}
max_depth[0] = curr_depth;
}
int main(int argc, char *argv[]){
if(argc<2){
cout << "Usage: " << argv[0] << " <graph_file_name>\n";
return 0;
}
ifstream input;
input.open(argv[1]);
int nodes, edges, i;
input >> nodes;
input >> edges;
// allocating host memory
int *h_r = (int*)malloc((nodes+1)*sizeof(int));
int *h_c = (int*)malloc(edges*2*sizeof(int));
// reading inputs
for(i=0; i<nodes+1; i++){
input >> h_r[i];
}
for(i=0; i<edges*2; i++){
input >> h_c[i];
}
// allocating device memory
int *Q1, *Q2, *d_r, *d_c, *d_depth, *max_depth;
hipMalloc((void**)&Q1, nodes*sizeof(int));
hipMalloc((void**)&Q2, nodes*sizeof(int));
hipMalloc((void**)&d_r, (nodes+1)*sizeof(int));
hipMalloc((void**)&d_c, edges*2*sizeof(int));
hipMalloc((void**)&d_depth, nodes*sizeof(int));
hipMalloc((void**)&max_depth, sizeof(int));
// copying data to device
hipMemcpy(d_r, h_r, (nodes+1)*sizeof(int), hipMemcpyHostToDevice);
hipMemcpy(d_c, h_c, edges*2*sizeof(int), hipMemcpyHostToDevice);
// timer
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
hipEventRecord(start);
// kernel call
printf("Starting Computation\n");
compute <<<1, 1024>>> (d_r, d_c, d_depth, max_depth, Q1, Q2, nodes);
hipDeviceSynchronize();
printf("Finished Computation\n");
// timer
hipEventRecord(stop);
hipEventSynchronize(stop);
float milliseconds = 0;
hipEventElapsedTime(&milliseconds, start, stop);
cout<<"Compute time in GPU: "<<milliseconds<<"ms"<<endl;
// copying results to host
int *result = (int *)malloc(sizeof(int));
cudaCatchError(hipMemcpy(result, max_depth, sizeof(int), hipMemcpyDeviceToHost));
printf("Depth : %d\n", result[0]-1);
// solution check
int *h_depth = (int*) malloc(nodes*sizeof(int));
hipMemcpy(h_depth, d_depth, nodes*sizeof(int), hipMemcpyDeviceToHost);
int *h_check_depth = (int*)malloc(nodes*sizeof(int));
freopen(argv[2], "r", stdin);
printf("malloc done\n");
for(int i = 0; i < nodes; i++) {
cin>>h_check_depth[i];
}
printf("Finished reading output file\n");
bool flag = true;
int count = 0;
printf("Starting checking\n");
for(int i = 0; i < nodes; i++) {
if(h_depth[i] != h_check_depth[i]) {
printf("Found %d, Expected %d\n",h_depth[i], h_check_depth[i]);
flag = false;
count++;
}
}
printf("Finished checking\n");
if(flag) {
cout<<"Solution is correct!\n";
}
else {
cout<<"Solution is incorrect!"<<endl;
cout<<count<<" testcases failed.\n";
}
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include<bits/stdc++.h>
using namespace std;
#define MAX_VAL ((int)1e8)
#define cudaCatchError(error) { gpuAssert((error), __FILE__, __LINE__); }
// Catch Cuda errors
inline void gpuAssert(hipError_t error, const char *file, int line, bool abort = false)
{
if (error != hipSuccess)
{
printf("\n====== Cuda Error Code %i ======\n %s in CUDA %s\n", error, hipGetErrorString(error));
printf("\nIn file :%s\nOn line: %d", file, line);
if(abort)
exit(-1);
}
}
__global__ void compute(int *d_r, int *d_c, int *d_depth, int *max_depth, int *Q1, int *Q2, int nodes){
int idx = threadIdx.x;
__shared__ int len1, len2, curr_depth;
int i;
for(i=idx; i<nodes; i+=1024){
d_depth[i] = MAX_VAL;
}
if(idx == 0){
d_depth[0] = 0;
curr_depth = 0;
len1 = 1;
len2 = 0;
Q1[0] = 0;
}
__syncthreads();
while(len1){
for(i=idx; i<len1; i+=1024){
for(int j=d_r[Q1[i]]; j<d_r[Q1[i]+1]; j++){
int v = d_c[j];
if(atomicCAS(&d_depth[v], MAX_VAL, d_depth[Q1[i]]+1) == MAX_VAL){
int t = atomicAdd(&len2,1);
Q2[t] = v;
}
}
}
__syncthreads();
if(idx==0){
for(i=0; i<len2; i++){
Q1[i] = Q2[i];
}
len1 = len2;
len2 = 0;
curr_depth++;
}
__syncthreads();
}
max_depth[0] = curr_depth;
}
int main(int argc, char *argv[]){
if(argc<2){
cout << "Usage: " << argv[0] << " <graph_file_name>\n";
return 0;
}
ifstream input;
input.open(argv[1]);
int nodes, edges, i;
input >> nodes;
input >> edges;
// allocating host memory
int *h_r = (int*)malloc((nodes+1)*sizeof(int));
int *h_c = (int*)malloc(edges*2*sizeof(int));
// reading inputs
for(i=0; i<nodes+1; i++){
input >> h_r[i];
}
for(i=0; i<edges*2; i++){
input >> h_c[i];
}
// allocating device memory
int *Q1, *Q2, *d_r, *d_c, *d_depth, *max_depth;
hipMalloc((void**)&Q1, nodes*sizeof(int));
hipMalloc((void**)&Q2, nodes*sizeof(int));
hipMalloc((void**)&d_r, (nodes+1)*sizeof(int));
hipMalloc((void**)&d_c, edges*2*sizeof(int));
hipMalloc((void**)&d_depth, nodes*sizeof(int));
hipMalloc((void**)&max_depth, sizeof(int));
// copying data to device
hipMemcpy(d_r, h_r, (nodes+1)*sizeof(int), hipMemcpyHostToDevice);
hipMemcpy(d_c, h_c, edges*2*sizeof(int), hipMemcpyHostToDevice);
// timer
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
hipEventRecord(start);
// kernel call
printf("Starting Computation\n");
compute <<<1, 1024>>> (d_r, d_c, d_depth, max_depth, Q1, Q2, nodes);
hipDeviceSynchronize();
printf("Finished Computation\n");
// timer
hipEventRecord(stop);
hipEventSynchronize(stop);
float milliseconds = 0;
hipEventElapsedTime(&milliseconds, start, stop);
cout<<"Compute time in GPU: "<<milliseconds<<"ms"<<endl;
// copying results to host
int *result = (int *)malloc(sizeof(int));
cudaCatchError(hipMemcpy(result, max_depth, sizeof(int), hipMemcpyDeviceToHost));
printf("Depth : %d\n", result[0]-1);
// solution check
int *h_depth = (int*) malloc(nodes*sizeof(int));
hipMemcpy(h_depth, d_depth, nodes*sizeof(int), hipMemcpyDeviceToHost);
int *h_check_depth = (int*)malloc(nodes*sizeof(int));
freopen(argv[2], "r", stdin);
printf("malloc done\n");
for(int i = 0; i < nodes; i++) {
cin>>h_check_depth[i];
}
printf("Finished reading output file\n");
bool flag = true;
int count = 0;
printf("Starting checking\n");
for(int i = 0; i < nodes; i++) {
if(h_depth[i] != h_check_depth[i]) {
printf("Found %d, Expected %d\n",h_depth[i], h_check_depth[i]);
flag = false;
count++;
}
}
printf("Finished checking\n");
if(flag) {
cout<<"Solution is correct!\n";
}
else {
cout<<"Solution is incorrect!"<<endl;
cout<<count<<" testcases failed.\n";
}
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z7computePiS_S_S_S_S_i
.globl _Z7computePiS_S_S_S_S_i
.p2align 8
.type _Z7computePiS_S_S_S_S_i,@function
_Z7computePiS_S_S_S_S_i:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x30
s_load_b64 s[8:9], s[0:1], 0x10
s_mov_b32 s4, exec_lo
s_waitcnt lgkmcnt(0)
v_cmpx_gt_i32_e64 s3, v0
s_cbranch_execz .LBB0_3
v_dual_mov_b32 v4, v0 :: v_dual_lshlrev_b32 v1, 2, v0
v_mov_b32_e32 v3, 0x5f5e100
s_mov_b32 s5, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v1, s2, s8, v1
v_add_co_ci_u32_e64 v2, null, s9, 0, s2
.LBB0_2:
v_add_nc_u32_e32 v4, 0x400, v4
global_store_b32 v[1:2], v3, off
v_add_co_u32 v1, s2, v1, 0x1000
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_add_co_ci_u32_e64 v2, s2, 0, v2, s2
v_cmp_le_i32_e32 vcc_lo, s3, v4
s_or_b32 s5, vcc_lo, s5
s_and_not1_b32 exec_lo, exec_lo, s5
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s4
s_load_b64 s[10:11], s[0:1], 0x20
v_cmp_eq_u32_e64 s2, 0, v0
s_delay_alu instid0(VALU_DEP_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_5
v_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v2, 1
v_mov_b32_e32 v1, 0
ds_store_b32 v3, v3 offset:8
ds_store_b64 v3, v[1:2]
global_store_b32 v3, v3, s[8:9]
s_waitcnt lgkmcnt(0)
global_store_b32 v3, v3, s[10:11]
.LBB0_5:
s_or_b32 exec_lo, exec_lo, s3
v_mov_b32_e32 v2, 0
s_waitcnt lgkmcnt(0)
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
ds_load_b32 v12, v2 offset:4
s_waitcnt lgkmcnt(0)
v_cmp_eq_u32_e32 vcc_lo, 0, v12
s_cbranch_vccnz .LBB0_22
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[12:13], s[0:1], 0x28
s_waitcnt lgkmcnt(0)
s_add_u32 s18, s4, 4
s_addc_u32 s19, s5, 0
s_branch .LBB0_9
.LBB0_7:
ds_load_b32 v3, v2
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v3, 1, v3
ds_store_b32 v2, v2 offset:8
ds_store_2addr_b32 v2, v3, v1 offset1:1
.LBB0_8:
s_or_b32 exec_lo, exec_lo, s3
s_waitcnt lgkmcnt(0)
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
ds_load_b32 v12, v2 offset:4
s_waitcnt lgkmcnt(0)
v_cmp_ne_u32_e32 vcc_lo, 0, v12
s_cbranch_vccz .LBB0_22
.LBB0_9:
s_mov_b32 s14, exec_lo
v_cmpx_lt_i32_e64 v0, v12
s_cbranch_execz .LBB0_19
v_mov_b32_e32 v1, v0
s_mov_b32 s15, 0
s_branch .LBB0_12
.LBB0_11:
s_or_b32 exec_lo, exec_lo, s16
v_add_nc_u32_e32 v1, 0x400, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_ge_i32_e32 vcc_lo, v1, v12
s_or_b32 s15, vcc_lo, s15
s_and_not1_b32 exec_lo, exec_lo, s15
s_cbranch_execz .LBB0_19
.LBB0_12:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[1:2]
s_mov_b32 s16, exec_lo
v_add_co_u32 v3, vcc_lo, s10, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v4, vcc_lo, s11, v4, vcc_lo
global_load_b32 v8, v[3:4], off
s_waitcnt vmcnt(0)
v_ashrrev_i32_e32 v9, 31, v8
v_lshlrev_b64 v[5:6], 2, v[8:9]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v10, vcc_lo, s4, v5
v_add_co_ci_u32_e32 v11, vcc_lo, s5, v6, vcc_lo
v_add_co_u32 v13, vcc_lo, s18, v5
v_add_co_ci_u32_e32 v14, vcc_lo, s19, v6, vcc_lo
s_clause 0x1
global_load_b32 v5, v[10:11], off
global_load_b32 v6, v[13:14], off
s_waitcnt vmcnt(0)
v_cmpx_lt_i32_e64 v5, v6
s_cbranch_execz .LBB0_11
v_ashrrev_i32_e32 v6, 31, v5
s_mov_b32 s17, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[6:7], 2, v[5:6]
v_add_co_u32 v6, vcc_lo, s6, v6
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v7, vcc_lo, s7, v7, vcc_lo
s_branch .LBB0_16
.LBB0_14:
s_or_b32 exec_lo, exec_lo, s20
s_waitcnt lgkmcnt(0)
v_readfirstlane_b32 s20, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v8, s20, v8
v_ashrrev_i32_e32 v9, 31, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[8:9], 2, v[8:9]
v_add_co_u32 v8, vcc_lo, s12, v8
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v9, vcc_lo, s13, v9, vcc_lo
global_store_b32 v[8:9], v10, off
.LBB0_15:
s_or_b32 exec_lo, exec_lo, s3
global_load_b32 v8, v[3:4], off
v_add_nc_u32_e32 v5, 1, v5
v_add_co_u32 v6, s3, v6, 4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e64 v7, s3, 0, v7, s3
s_waitcnt vmcnt(0)
v_ashrrev_i32_e32 v9, 31, v8
v_lshlrev_b64 v[10:11], 2, v[8:9]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v10, vcc_lo, s18, v10
v_add_co_ci_u32_e32 v11, vcc_lo, s19, v11, vcc_lo
global_load_b32 v10, v[10:11], off
s_waitcnt vmcnt(0)
v_cmp_ge_i32_e32 vcc_lo, v5, v10
s_or_b32 s17, vcc_lo, s17
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s17
s_cbranch_execz .LBB0_11
.LBB0_16:
global_load_b32 v10, v[6:7], off
v_lshlrev_b64 v[8:9], 2, v[8:9]
s_mov_b32 s3, exec_lo
v_mov_b32_e32 v14, 0x5f5e100
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v8, vcc_lo, s8, v8
v_add_co_ci_u32_e32 v9, vcc_lo, s9, v9, vcc_lo
global_load_b32 v13, v[8:9], off
s_waitcnt vmcnt(1)
v_ashrrev_i32_e32 v11, 31, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[8:9], 2, v[10:11]
v_add_co_u32 v8, vcc_lo, s8, v8
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v9, vcc_lo, s9, v9, vcc_lo
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v13, 1, v13
global_atomic_cmpswap_b32 v8, v[8:9], v[13:14], off glc
s_waitcnt vmcnt(0)
v_cmpx_eq_u32_e32 0x5f5e100, v8
s_cbranch_execz .LBB0_15
s_mov_b32 s21, exec_lo
s_mov_b32 s20, exec_lo
v_mbcnt_lo_u32_b32 v8, s21, 0
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_eq_u32_e32 0, v8
s_cbranch_execz .LBB0_14
s_bcnt1_i32_b32 s21, s21
s_delay_alu instid0(SALU_CYCLE_1)
v_mov_b32_e32 v9, s21
ds_add_rtn_u32 v9, v2, v9 offset:8
s_branch .LBB0_14
.LBB0_19:
s_or_b32 exec_lo, exec_lo, s14
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_8
ds_load_b32 v1, v2 offset:8
s_mov_b64 s[14:15], s[10:11]
s_mov_b64 s[16:17], s[12:13]
s_waitcnt lgkmcnt(0)
v_cmp_gt_i32_e32 vcc_lo, 1, v1
v_mov_b32_e32 v3, v1
s_cbranch_vccnz .LBB0_7
.LBB0_21:
global_load_b32 v4, v2, s[16:17]
v_add_nc_u32_e32 v3, -1, v3
s_add_u32 s16, s16, 4
s_addc_u32 s17, s17, 0
s_delay_alu instid0(VALU_DEP_1)
v_cmp_ne_u32_e32 vcc_lo, 0, v3
s_waitcnt vmcnt(0)
global_store_b32 v2, v4, s[14:15]
s_add_u32 s14, s14, 4
s_addc_u32 s15, s15, 0
s_cbranch_vccnz .LBB0_21
s_branch .LBB0_7
.LBB0_22:
s_load_b64 s[0:1], s[0:1], 0x18
ds_load_b32 v0, v2
s_waitcnt lgkmcnt(0)
global_store_b32 v2, v0, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7computePiS_S_S_S_S_i
.amdhsa_group_segment_fixed_size 12
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 52
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 15
.amdhsa_next_free_sgpr 22
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z7computePiS_S_S_S_S_i, .Lfunc_end0-_Z7computePiS_S_S_S_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
- .offset: 48
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 12
.kernarg_segment_align: 8
.kernarg_segment_size: 52
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7computePiS_S_S_S_S_i
.private_segment_fixed_size: 0
.sgpr_count: 24
.sgpr_spill_count: 0
.symbol: _Z7computePiS_S_S_S_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 15
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include<bits/stdc++.h>
using namespace std;
#define MAX_VAL ((int)1e8)
#define cudaCatchError(error) { gpuAssert((error), __FILE__, __LINE__); }
// Catch Cuda errors
inline void gpuAssert(hipError_t error, const char *file, int line, bool abort = false)
{
if (error != hipSuccess)
{
printf("\n====== Cuda Error Code %i ======\n %s in CUDA %s\n", error, hipGetErrorString(error));
printf("\nIn file :%s\nOn line: %d", file, line);
if(abort)
exit(-1);
}
}
__global__ void compute(int *d_r, int *d_c, int *d_depth, int *max_depth, int *Q1, int *Q2, int nodes){
int idx = threadIdx.x;
__shared__ int len1, len2, curr_depth;
int i;
for(i=idx; i<nodes; i+=1024){
d_depth[i] = MAX_VAL;
}
if(idx == 0){
d_depth[0] = 0;
curr_depth = 0;
len1 = 1;
len2 = 0;
Q1[0] = 0;
}
__syncthreads();
while(len1){
for(i=idx; i<len1; i+=1024){
for(int j=d_r[Q1[i]]; j<d_r[Q1[i]+1]; j++){
int v = d_c[j];
if(atomicCAS(&d_depth[v], MAX_VAL, d_depth[Q1[i]]+1) == MAX_VAL){
int t = atomicAdd(&len2,1);
Q2[t] = v;
}
}
}
__syncthreads();
if(idx==0){
for(i=0; i<len2; i++){
Q1[i] = Q2[i];
}
len1 = len2;
len2 = 0;
curr_depth++;
}
__syncthreads();
}
max_depth[0] = curr_depth;
}
int main(int argc, char *argv[]){
if(argc<2){
cout << "Usage: " << argv[0] << " <graph_file_name>\n";
return 0;
}
ifstream input;
input.open(argv[1]);
int nodes, edges, i;
input >> nodes;
input >> edges;
// allocating host memory
int *h_r = (int*)malloc((nodes+1)*sizeof(int));
int *h_c = (int*)malloc(edges*2*sizeof(int));
// reading inputs
for(i=0; i<nodes+1; i++){
input >> h_r[i];
}
for(i=0; i<edges*2; i++){
input >> h_c[i];
}
// allocating device memory
int *Q1, *Q2, *d_r, *d_c, *d_depth, *max_depth;
hipMalloc((void**)&Q1, nodes*sizeof(int));
hipMalloc((void**)&Q2, nodes*sizeof(int));
hipMalloc((void**)&d_r, (nodes+1)*sizeof(int));
hipMalloc((void**)&d_c, edges*2*sizeof(int));
hipMalloc((void**)&d_depth, nodes*sizeof(int));
hipMalloc((void**)&max_depth, sizeof(int));
// copying data to device
hipMemcpy(d_r, h_r, (nodes+1)*sizeof(int), hipMemcpyHostToDevice);
hipMemcpy(d_c, h_c, edges*2*sizeof(int), hipMemcpyHostToDevice);
// timer
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
hipEventRecord(start);
// kernel call
printf("Starting Computation\n");
compute <<<1, 1024>>> (d_r, d_c, d_depth, max_depth, Q1, Q2, nodes);
hipDeviceSynchronize();
printf("Finished Computation\n");
// timer
hipEventRecord(stop);
hipEventSynchronize(stop);
float milliseconds = 0;
hipEventElapsedTime(&milliseconds, start, stop);
cout<<"Compute time in GPU: "<<milliseconds<<"ms"<<endl;
// copying results to host
int *result = (int *)malloc(sizeof(int));
cudaCatchError(hipMemcpy(result, max_depth, sizeof(int), hipMemcpyDeviceToHost));
printf("Depth : %d\n", result[0]-1);
// solution check
int *h_depth = (int*) malloc(nodes*sizeof(int));
hipMemcpy(h_depth, d_depth, nodes*sizeof(int), hipMemcpyDeviceToHost);
int *h_check_depth = (int*)malloc(nodes*sizeof(int));
freopen(argv[2], "r", stdin);
printf("malloc done\n");
for(int i = 0; i < nodes; i++) {
cin>>h_check_depth[i];
}
printf("Finished reading output file\n");
bool flag = true;
int count = 0;
printf("Starting checking\n");
for(int i = 0; i < nodes; i++) {
if(h_depth[i] != h_check_depth[i]) {
printf("Found %d, Expected %d\n",h_depth[i], h_check_depth[i]);
flag = false;
count++;
}
}
printf("Finished checking\n");
if(flag) {
cout<<"Solution is correct!\n";
}
else {
cout<<"Solution is incorrect!"<<endl;
cout<<count<<" testcases failed.\n";
}
return 0;
} | .text
.file "parallel_BFS_work_efficient.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z22__device_stub__computePiS_S_S_S_S_i # -- Begin function _Z22__device_stub__computePiS_S_S_S_S_i
.p2align 4, 0x90
.type _Z22__device_stub__computePiS_S_S_S_S_i,@function
_Z22__device_stub__computePiS_S_S_S_S_i: # @_Z22__device_stub__computePiS_S_S_S_S_i
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
movq %r9, 48(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 160(%rsp), %rax
movq %rax, 144(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z7computePiS_S_S_S_S_i, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z22__device_stub__computePiS_S_S_S_S_i, .Lfunc_end0-_Z22__device_stub__computePiS_S_S_S_S_i
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.Lfunc_begin0:
.cfi_startproc
.cfi_personality 3, __gxx_personality_v0
.cfi_lsda 3, .Lexception0
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $760, %rsp # imm = 0x2F8
.cfi_def_cfa_offset 816
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %rbx
cmpl $1, %edi
jg .LBB1_5
# %bb.1:
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $7, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%rbx), %rbx
testq %rbx, %rbx
je .LBB1_2
# %bb.3:
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
callq strlen
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
movq %rbx, %rsi
movq %rax, %rdx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
jmp .LBB1_4
.LBB1_5:
.cfi_escape 0x2e, 0x00
leaq 240(%rsp), %r14
movq %r14, %rdi
callq _ZNSt14basic_ifstreamIcSt11char_traitsIcEEC1Ev
movq 8(%rbx), %rsi
leaq 256(%rsp), %rdi
.Ltmp0:
.cfi_escape 0x2e, 0x00
movl $8, %edx
callq _ZNSt13basic_filebufIcSt11char_traitsIcEE4openEPKcSt13_Ios_Openmode
.Ltmp1:
# %bb.6: # %.noexc
movq 240(%rsp), %rcx
addq -24(%rcx), %r14
xorl %esi, %esi
testq %rax, %rax
jne .LBB1_8
# %bb.7:
movl 32(%r14), %esi
orl $4, %esi
.LBB1_8: # %.invoke
.Ltmp2:
.cfi_escape 0x2e, 0x00
movq %r14, %rdi
callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate
.Ltmp3:
# %bb.9: # %_ZNSt14basic_ifstreamIcSt11char_traitsIcEE4openEPKcSt13_Ios_Openmode.exit
.Ltmp5:
.cfi_escape 0x2e, 0x00
leaq 240(%rsp), %rdi
movq %rsp, %rsi
callq _ZNSirsERi
.Ltmp6:
# %bb.10:
.Ltmp7:
.cfi_escape 0x2e, 0x00
leaq 240(%rsp), %rdi
leaq 4(%rsp), %rsi
callq _ZNSirsERi
.Ltmp8:
# %bb.11:
movslq (%rsp), %rax
leaq 4(,%rax,4), %rdi
.cfi_escape 0x2e, 0x00
callq malloc
movq %rax, %r15
movslq 4(%rsp), %rdi
shlq $3, %rdi
.cfi_escape 0x2e, 0x00
callq malloc
movq %rax, %r14
cmpl $0, (%rsp)
js .LBB1_15
# %bb.12: # %.lr.ph.preheader
movq $-1, %rbp
leaq 240(%rsp), %r12
movq %r15, %r13
.p2align 4, 0x90
.LBB1_13: # %.lr.ph
# =>This Inner Loop Header: Depth=1
.Ltmp10:
.cfi_escape 0x2e, 0x00
movq %r12, %rdi
movq %r13, %rsi
callq _ZNSirsERi
.Ltmp11:
# %bb.14: # in Loop: Header=BB1_13 Depth=1
movslq (%rsp), %rax
incq %rbp
addq $4, %r13
cmpq %rax, %rbp
jl .LBB1_13
.LBB1_15: # %.preheader
cmpl $0, 4(%rsp)
jle .LBB1_19
# %bb.16: # %.lr.ph119.preheader
xorl %ebp, %ebp
leaq 240(%rsp), %r12
movq %r14, %r13
.p2align 4, 0x90
.LBB1_17: # %.lr.ph119
# =>This Inner Loop Header: Depth=1
.Ltmp13:
.cfi_escape 0x2e, 0x00
movq %r12, %rdi
movq %r13, %rsi
callq _ZNSirsERi
.Ltmp14:
# %bb.18: # in Loop: Header=BB1_17 Depth=1
incq %rbp
movslq 4(%rsp), %rax
addq %rax, %rax
addq $4, %r13
cmpq %rax, %rbp
jl .LBB1_17
.LBB1_19: # %._crit_edge
movslq (%rsp), %rsi
shlq $2, %rsi
.Ltmp16:
.cfi_escape 0x2e, 0x00
leaq 72(%rsp), %rdi
callq hipMalloc
.Ltmp17:
# %bb.20:
movslq (%rsp), %rsi
shlq $2, %rsi
.Ltmp18:
.cfi_escape 0x2e, 0x00
leaq 64(%rsp), %rdi
callq hipMalloc
.Ltmp19:
# %bb.21:
movslq (%rsp), %rax
leaq 4(,%rax,4), %rsi
.Ltmp20:
.cfi_escape 0x2e, 0x00
leaq 56(%rsp), %rdi
callq hipMalloc
.Ltmp21:
# %bb.22:
movslq 4(%rsp), %rsi
shlq $3, %rsi
.Ltmp22:
.cfi_escape 0x2e, 0x00
leaq 48(%rsp), %rdi
callq hipMalloc
.Ltmp23:
# %bb.23:
movslq (%rsp), %rsi
shlq $2, %rsi
.Ltmp24:
.cfi_escape 0x2e, 0x00
leaq 40(%rsp), %rdi
callq hipMalloc
.Ltmp25:
# %bb.24:
.Ltmp26:
.cfi_escape 0x2e, 0x00
leaq 32(%rsp), %rdi
movl $4, %esi
callq hipMalloc
.Ltmp27:
# %bb.25:
movq 56(%rsp), %rdi
movslq (%rsp), %rax
leaq 4(,%rax,4), %rdx
.Ltmp28:
.cfi_escape 0x2e, 0x00
movq %r15, %rsi
movl $1, %ecx
callq hipMemcpy
.Ltmp29:
# %bb.26:
movq 48(%rsp), %rdi
movslq 4(%rsp), %rdx
shlq $3, %rdx
.Ltmp30:
.cfi_escape 0x2e, 0x00
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
.Ltmp31:
# %bb.27:
.Ltmp33:
.cfi_escape 0x2e, 0x00
leaq 24(%rsp), %rdi
callq hipEventCreate
.Ltmp34:
# %bb.28:
.Ltmp35:
.cfi_escape 0x2e, 0x00
leaq 8(%rsp), %rdi
callq hipEventCreate
.Ltmp36:
# %bb.29:
movq 24(%rsp), %rdi
.Ltmp37:
.cfi_escape 0x2e, 0x00
xorl %esi, %esi
callq hipEventRecord
.Ltmp38:
# %bb.30:
.cfi_escape 0x2e, 0x00
movl $.Lstr, %edi
callq puts@PLT
.Ltmp39:
.cfi_escape 0x2e, 0x00
movabsq $4294967297, %rdi # imm = 0x100000001
movabsq $4294968320, %rdx # imm = 0x100000400
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
.Ltmp40:
# %bb.31:
testl %eax, %eax
jne .LBB1_34
# %bb.32:
movq 56(%rsp), %rax
movq 48(%rsp), %rcx
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
movq 72(%rsp), %rdi
movq 64(%rsp), %r8
movl (%rsp), %r9d
movq %rax, 168(%rsp)
movq %rcx, 160(%rsp)
movq %rdx, 152(%rsp)
movq %rsi, 144(%rsp)
movq %rdi, 136(%rsp)
movq %r8, 128(%rsp)
movl %r9d, 20(%rsp)
leaq 168(%rsp), %rax
movq %rax, 176(%rsp)
leaq 160(%rsp), %rax
movq %rax, 184(%rsp)
leaq 152(%rsp), %rax
movq %rax, 192(%rsp)
leaq 144(%rsp), %rax
movq %rax, 200(%rsp)
leaq 136(%rsp), %rax
movq %rax, 208(%rsp)
leaq 128(%rsp), %rax
movq %rax, 216(%rsp)
leaq 20(%rsp), %rax
movq %rax, 224(%rsp)
.Ltmp41:
.cfi_escape 0x2e, 0x00
leaq 112(%rsp), %rdi
leaq 96(%rsp), %rsi
leaq 88(%rsp), %rdx
leaq 80(%rsp), %rcx
callq __hipPopCallConfiguration
.Ltmp42:
# %bb.33: # %.noexc79
movq 112(%rsp), %rsi
movl 120(%rsp), %edx
movq 96(%rsp), %rcx
movl 104(%rsp), %r8d
.Ltmp43:
.cfi_escape 0x2e, 0x10
leaq 176(%rsp), %r9
movl $_Z7computePiS_S_S_S_S_i, %edi
pushq 80(%rsp)
.cfi_adjust_cfa_offset 8
pushq 96(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.Ltmp44:
.LBB1_34:
.Ltmp45:
.cfi_escape 0x2e, 0x00
callq hipDeviceSynchronize
.Ltmp46:
# %bb.35:
.cfi_escape 0x2e, 0x00
movl $.Lstr.1, %edi
callq puts@PLT
movq 8(%rsp), %rdi
.Ltmp47:
.cfi_escape 0x2e, 0x00
xorl %esi, %esi
callq hipEventRecord
.Ltmp48:
# %bb.36:
movq 8(%rsp), %rdi
.Ltmp49:
.cfi_escape 0x2e, 0x00
callq hipEventSynchronize
.Ltmp50:
# %bb.37:
movl $0, 176(%rsp)
movq 24(%rsp), %rsi
movq 8(%rsp), %rdx
.Ltmp52:
.cfi_escape 0x2e, 0x00
leaq 176(%rsp), %rdi
callq hipEventElapsedTime
.Ltmp53:
# %bb.38:
.Ltmp54:
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
movl $.L.str.4, %esi
movl $21, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp55:
# %bb.39: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit82
movss 176(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
.Ltmp56:
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
.Ltmp57:
# %bb.40: # %_ZNSolsEf.exit
.Ltmp58:
movq %rax, %r14
.cfi_escape 0x2e, 0x00
movl $.L.str.5, %esi
movl $2, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp59:
# %bb.41: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit85
movq (%r14), %rax
movq -24(%rax), %rax
movq 240(%r14,%rax), %r15
testq %r15, %r15
je .LBB1_42
# %bb.50: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%r15)
je .LBB1_52
# %bb.51:
movzbl 67(%r15), %eax
jmp .LBB1_54
.LBB1_2:
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
leaq _ZSt4cout(%rax), %rdi
movl _ZSt4cout+32(%rax), %esi
orl $1, %esi
.cfi_escape 0x2e, 0x00
callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate
.LBB1_4: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $19, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
jmp .LBB1_94
.LBB1_52:
.Ltmp60:
.cfi_escape 0x2e, 0x00
movq %r15, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
.Ltmp61:
# %bb.53: # %.noexc98
movq (%r15), %rax
.Ltmp62:
.cfi_escape 0x2e, 0x00
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
.Ltmp63:
.LBB1_54: # %_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc.exit.i
.Ltmp64:
.cfi_escape 0x2e, 0x00
movsbl %al, %esi
movq %r14, %rdi
callq _ZNSo3putEc
.Ltmp65:
# %bb.55: # %.noexc100
.Ltmp66:
.cfi_escape 0x2e, 0x00
movq %rax, %rdi
callq _ZNSo5flushEv
.Ltmp67:
# %bb.56: # %_ZNSolsEPFRSoS_E.exit
.cfi_escape 0x2e, 0x00
movl $4, %edi
callq malloc
movq %rax, %r14
movq 32(%rsp), %rsi
.Ltmp68:
.cfi_escape 0x2e, 0x00
movl $4, %edx
movq %rax, %rdi
movl $2, %ecx
callq hipMemcpy
.Ltmp69:
# %bb.57:
movl %eax, %ebp
testl %eax, %eax
je .LBB1_60
# %bb.58:
.Ltmp70:
.cfi_escape 0x2e, 0x00
movl %ebp, %edi
callq hipGetErrorString
.Ltmp71:
# %bb.59: # %.noexc88
.cfi_escape 0x2e, 0x00
movl $.L.str.17, %edi
movl %ebp, %esi
movq %rax, %rdx
xorl %eax, %eax
callq printf
.cfi_escape 0x2e, 0x00
movl $.L.str.18, %edi
movl $.L.str.6, %esi
movl $126, %edx
xorl %eax, %eax
callq printf
.LBB1_60: # %_Z9gpuAssert10hipError_tPKcib.exit
movl (%r14), %esi
decl %esi
.cfi_escape 0x2e, 0x00
movl $.L.str.7, %edi
xorl %eax, %eax
callq printf
movslq (%rsp), %r15
shlq $2, %r15
.cfi_escape 0x2e, 0x00
movq %r15, %rdi
callq malloc
movq %rax, %r14
movq 40(%rsp), %rsi
.Ltmp73:
.cfi_escape 0x2e, 0x00
movq %rax, %rdi
movq %r15, %rdx
movl $2, %ecx
callq hipMemcpy
.Ltmp74:
# %bb.61:
movslq (%rsp), %rdi
shlq $2, %rdi
.cfi_escape 0x2e, 0x00
callq malloc
movq %rax, %r15
movq 16(%rbx), %rdi
movq stdin(%rip), %rdx
.Ltmp76:
.cfi_escape 0x2e, 0x00
movl $.L.str.8, %esi
callq freopen
.Ltmp77:
# %bb.62:
.cfi_escape 0x2e, 0x00
movl $.Lstr.2, %edi
callq puts@PLT
cmpl $0, (%rsp)
jle .LBB1_66
# %bb.63: # %.lr.ph122.preheader
xorl %r12d, %r12d
movq %r15, %rbx
.p2align 4, 0x90
.LBB1_64: # %.lr.ph122
# =>This Inner Loop Header: Depth=1
.Ltmp79:
.cfi_escape 0x2e, 0x00
movl $_ZSt3cin, %edi
movq %rbx, %rsi
callq _ZNSirsERi
.Ltmp80:
# %bb.65: # in Loop: Header=BB1_64 Depth=1
incq %r12
movslq (%rsp), %rax
addq $4, %rbx
cmpq %rax, %r12
jl .LBB1_64
.LBB1_66: # %._crit_edge123
.cfi_escape 0x2e, 0x00
movl $.Lstr.3, %edi
callq puts@PLT
.cfi_escape 0x2e, 0x00
movl $.Lstr.4, %edi
callq puts@PLT
cmpl $0, (%rsp)
jle .LBB1_67
# %bb.76: # %.lr.ph128.preheader
movb $1, %bpl
xorl %r12d, %r12d
xorl %ebx, %ebx
jmp .LBB1_77
.p2align 4, 0x90
.LBB1_79: # in Loop: Header=BB1_77 Depth=1
incq %r12
movslq (%rsp), %rax
cmpq %rax, %r12
jge .LBB1_72
.LBB1_77: # %.lr.ph128
# =>This Inner Loop Header: Depth=1
movl (%r14,%r12,4), %esi
movl (%r15,%r12,4), %edx
cmpl %edx, %esi
je .LBB1_79
# %bb.78: # in Loop: Header=BB1_77 Depth=1
.cfi_escape 0x2e, 0x00
xorl %ebp, %ebp
movl $.L.str.12, %edi
xorl %eax, %eax
callq printf
incl %ebx
jmp .LBB1_79
.LBB1_72: # %._crit_edge129.loopexit
testb $1, %bpl
sete %bpl
jmp .LBB1_73
.LBB1_67:
xorl %ebp, %ebp
xorl %ebx, %ebx
.LBB1_73: # %._crit_edge129
.cfi_escape 0x2e, 0x00
movl $.Lstr.5, %edi
callq puts@PLT
testb %bpl, %bpl
je .LBB1_74
# %bb.80:
.Ltmp82:
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
movl $.L.str.15, %esi
movl $22, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp83:
# %bb.81: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit92
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r14
testq %r14, %r14
je .LBB1_82
# %bb.84: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i103
cmpb $0, 56(%r14)
je .LBB1_86
# %bb.85:
movzbl 67(%r14), %eax
jmp .LBB1_88
.LBB1_74:
movl $21, %edx
movl $.L.str.14, %esi
movl $_ZSt4cout, %edi
jmp .LBB1_92
.LBB1_86:
.Ltmp84:
.cfi_escape 0x2e, 0x00
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
.Ltmp85:
# %bb.87: # %.noexc108
movq (%r14), %rax
.Ltmp86:
.cfi_escape 0x2e, 0x00
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.Ltmp87:
.LBB1_88: # %_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc.exit.i105
.Ltmp88:
.cfi_escape 0x2e, 0x00
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
.Ltmp89:
# %bb.89: # %.noexc110
.Ltmp90:
.cfi_escape 0x2e, 0x00
movq %rax, %rdi
callq _ZNSo5flushEv
.Ltmp91:
# %bb.90: # %_ZNSolsEPFRSoS_E.exit94
.Ltmp92:
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
movl %ebx, %esi
callq _ZNSolsEi
.Ltmp93:
# %bb.91:
movq %rax, %rdi
movl $19, %edx
movl $.L.str.16, %esi
.LBB1_92: # %.invoke140
.Ltmp94:
.cfi_escape 0x2e, 0x00
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp95:
# %bb.93: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit90
.cfi_escape 0x2e, 0x00
leaq 240(%rsp), %rdi
movl $_ZTTSt14basic_ifstreamIcSt11char_traitsIcEE, %esi
callq _ZNSt14basic_ifstreamIcSt11char_traitsIcEED2Ev
leaq 496(%rsp), %rdi
.cfi_escape 0x2e, 0x00
callq _ZNSt8ios_baseD2Ev
.LBB1_94:
xorl %eax, %eax
addq $760, %rsp # imm = 0x2F8
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_42:
.cfi_def_cfa_offset 816
.Ltmp99:
.cfi_escape 0x2e, 0x00
callq _ZSt16__throw_bad_castv
.Ltmp100:
# %bb.49: # %.noexc97
.LBB1_82:
.Ltmp96:
.cfi_escape 0x2e, 0x00
callq _ZSt16__throw_bad_castv
.Ltmp97:
# %bb.83: # %.noexc107
.LBB1_70:
.Ltmp78:
jmp .LBB1_96
.LBB1_69:
.Ltmp75:
jmp .LBB1_96
.LBB1_68:
.Ltmp72:
jmp .LBB1_96
.LBB1_44:
.Ltmp9:
jmp .LBB1_96
.LBB1_43:
.Ltmp4:
jmp .LBB1_96
.LBB1_75:
.Ltmp98:
jmp .LBB1_96
.LBB1_95:
.Ltmp101:
jmp .LBB1_96
.LBB1_48:
.Ltmp51:
jmp .LBB1_96
.LBB1_47:
.Ltmp32:
jmp .LBB1_96
.LBB1_71:
.Ltmp81:
jmp .LBB1_96
.LBB1_45: # %.loopexit
.Ltmp15:
jmp .LBB1_96
.LBB1_46: # %.loopexit.split-lp
.Ltmp12:
.LBB1_96:
movq %rax, %rbx
.cfi_escape 0x2e, 0x00
leaq 240(%rsp), %rdi
movl $_ZTTSt14basic_ifstreamIcSt11char_traitsIcEE, %esi
callq _ZNSt14basic_ifstreamIcSt11char_traitsIcEED2Ev
leaq 496(%rsp), %rdi
.cfi_escape 0x2e, 0x00
callq _ZNSt8ios_baseD2Ev
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
callq _Unwind_Resume@PLT
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
.section .gcc_except_table,"a",@progbits
.p2align 2, 0x0
GCC_except_table1:
.Lexception0:
.byte 255 # @LPStart Encoding = omit
.byte 255 # @TType Encoding = omit
.byte 1 # Call site Encoding = uleb128
.uleb128 .Lcst_end0-.Lcst_begin0
.Lcst_begin0:
.uleb128 .Lfunc_begin0-.Lfunc_begin0 # >> Call Site 1 <<
.uleb128 .Ltmp0-.Lfunc_begin0 # Call between .Lfunc_begin0 and .Ltmp0
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp0-.Lfunc_begin0 # >> Call Site 2 <<
.uleb128 .Ltmp3-.Ltmp0 # Call between .Ltmp0 and .Ltmp3
.uleb128 .Ltmp4-.Lfunc_begin0 # jumps to .Ltmp4
.byte 0 # On action: cleanup
.uleb128 .Ltmp5-.Lfunc_begin0 # >> Call Site 3 <<
.uleb128 .Ltmp8-.Ltmp5 # Call between .Ltmp5 and .Ltmp8
.uleb128 .Ltmp9-.Lfunc_begin0 # jumps to .Ltmp9
.byte 0 # On action: cleanup
.uleb128 .Ltmp10-.Lfunc_begin0 # >> Call Site 4 <<
.uleb128 .Ltmp11-.Ltmp10 # Call between .Ltmp10 and .Ltmp11
.uleb128 .Ltmp12-.Lfunc_begin0 # jumps to .Ltmp12
.byte 0 # On action: cleanup
.uleb128 .Ltmp13-.Lfunc_begin0 # >> Call Site 5 <<
.uleb128 .Ltmp14-.Ltmp13 # Call between .Ltmp13 and .Ltmp14
.uleb128 .Ltmp15-.Lfunc_begin0 # jumps to .Ltmp15
.byte 0 # On action: cleanup
.uleb128 .Ltmp16-.Lfunc_begin0 # >> Call Site 6 <<
.uleb128 .Ltmp31-.Ltmp16 # Call between .Ltmp16 and .Ltmp31
.uleb128 .Ltmp32-.Lfunc_begin0 # jumps to .Ltmp32
.byte 0 # On action: cleanup
.uleb128 .Ltmp33-.Lfunc_begin0 # >> Call Site 7 <<
.uleb128 .Ltmp50-.Ltmp33 # Call between .Ltmp33 and .Ltmp50
.uleb128 .Ltmp51-.Lfunc_begin0 # jumps to .Ltmp51
.byte 0 # On action: cleanup
.uleb128 .Ltmp52-.Lfunc_begin0 # >> Call Site 8 <<
.uleb128 .Ltmp59-.Ltmp52 # Call between .Ltmp52 and .Ltmp59
.uleb128 .Ltmp101-.Lfunc_begin0 # jumps to .Ltmp101
.byte 0 # On action: cleanup
.uleb128 .Ltmp59-.Lfunc_begin0 # >> Call Site 9 <<
.uleb128 .Ltmp60-.Ltmp59 # Call between .Ltmp59 and .Ltmp60
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp60-.Lfunc_begin0 # >> Call Site 10 <<
.uleb128 .Ltmp67-.Ltmp60 # Call between .Ltmp60 and .Ltmp67
.uleb128 .Ltmp101-.Lfunc_begin0 # jumps to .Ltmp101
.byte 0 # On action: cleanup
.uleb128 .Ltmp68-.Lfunc_begin0 # >> Call Site 11 <<
.uleb128 .Ltmp71-.Ltmp68 # Call between .Ltmp68 and .Ltmp71
.uleb128 .Ltmp72-.Lfunc_begin0 # jumps to .Ltmp72
.byte 0 # On action: cleanup
.uleb128 .Ltmp73-.Lfunc_begin0 # >> Call Site 12 <<
.uleb128 .Ltmp74-.Ltmp73 # Call between .Ltmp73 and .Ltmp74
.uleb128 .Ltmp75-.Lfunc_begin0 # jumps to .Ltmp75
.byte 0 # On action: cleanup
.uleb128 .Ltmp76-.Lfunc_begin0 # >> Call Site 13 <<
.uleb128 .Ltmp77-.Ltmp76 # Call between .Ltmp76 and .Ltmp77
.uleb128 .Ltmp78-.Lfunc_begin0 # jumps to .Ltmp78
.byte 0 # On action: cleanup
.uleb128 .Ltmp79-.Lfunc_begin0 # >> Call Site 14 <<
.uleb128 .Ltmp80-.Ltmp79 # Call between .Ltmp79 and .Ltmp80
.uleb128 .Ltmp81-.Lfunc_begin0 # jumps to .Ltmp81
.byte 0 # On action: cleanup
.uleb128 .Ltmp82-.Lfunc_begin0 # >> Call Site 15 <<
.uleb128 .Ltmp95-.Ltmp82 # Call between .Ltmp82 and .Ltmp95
.uleb128 .Ltmp98-.Lfunc_begin0 # jumps to .Ltmp98
.byte 0 # On action: cleanup
.uleb128 .Ltmp99-.Lfunc_begin0 # >> Call Site 16 <<
.uleb128 .Ltmp100-.Ltmp99 # Call between .Ltmp99 and .Ltmp100
.uleb128 .Ltmp101-.Lfunc_begin0 # jumps to .Ltmp101
.byte 0 # On action: cleanup
.uleb128 .Ltmp96-.Lfunc_begin0 # >> Call Site 17 <<
.uleb128 .Ltmp97-.Ltmp96 # Call between .Ltmp96 and .Ltmp97
.uleb128 .Ltmp98-.Lfunc_begin0 # jumps to .Ltmp98
.byte 0 # On action: cleanup
.uleb128 .Ltmp97-.Lfunc_begin0 # >> Call Site 18 <<
.uleb128 .Lfunc_end1-.Ltmp97 # Call between .Ltmp97 and .Lfunc_end1
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.Lcst_end0:
.p2align 2, 0x0
# -- End function
.text
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7computePiS_S_S_S_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z7computePiS_S_S_S_S_i,@object # @_Z7computePiS_S_S_S_S_i
.section .rodata,"a",@progbits
.globl _Z7computePiS_S_S_S_S_i
.p2align 3, 0x0
_Z7computePiS_S_S_S_S_i:
.quad _Z22__device_stub__computePiS_S_S_S_S_i
.size _Z7computePiS_S_S_S_S_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Usage: "
.size .L.str, 8
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz " <graph_file_name>\n"
.size .L.str.1, 20
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Compute time in GPU: "
.size .L.str.4, 22
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "ms"
.size .L.str.5, 3
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/vrn25/CUDA-Playground/master/BreadthFirstSearch/parallel_BFS_work_efficient.hip"
.size .L.str.6, 137
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "Depth : %d\n"
.size .L.str.7, 12
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "r"
.size .L.str.8, 2
.type .L.str.12,@object # @.str.12
.L.str.12:
.asciz "Found %d, Expected %d\n"
.size .L.str.12, 23
.type .L.str.14,@object # @.str.14
.L.str.14:
.asciz "Solution is correct!\n"
.size .L.str.14, 22
.type .L.str.15,@object # @.str.15
.L.str.15:
.asciz "Solution is incorrect!"
.size .L.str.15, 23
.type .L.str.16,@object # @.str.16
.L.str.16:
.asciz " testcases failed.\n"
.size .L.str.16, 20
.type .L.str.17,@object # @.str.17
.L.str.17:
.asciz "\n====== Cuda Error Code %i ======\n %s in CUDA %s\n"
.size .L.str.17, 50
.type .L.str.18,@object # @.str.18
.L.str.18:
.asciz "\nIn file :%s\nOn line: %d"
.size .L.str.18, 25
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z7computePiS_S_S_S_S_i"
.size .L__unnamed_1, 24
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Starting Computation"
.size .Lstr, 21
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "Finished Computation"
.size .Lstr.1, 21
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "malloc done"
.size .Lstr.2, 12
.type .Lstr.3,@object # @str.3
.Lstr.3:
.asciz "Finished reading output file"
.size .Lstr.3, 29
.type .Lstr.4,@object # @str.4
.Lstr.4:
.asciz "Starting checking"
.size .Lstr.4, 18
.type .Lstr.5,@object # @str.5
.Lstr.5:
.asciz "Finished checking"
.size .Lstr.5, 18
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__computePiS_S_S_S_S_i
.addrsig_sym __gxx_personality_v0
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Unwind_Resume
.addrsig_sym _Z7computePiS_S_S_S_S_i
.addrsig_sym _ZSt4cout
.addrsig_sym _ZSt3cin
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0005cd27_00000000-6_parallel_BFS_work_efficient.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB10863:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE10863:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z37__device_stub__Z7computePiS_S_S_S_S_iPiS_S_S_S_S_i
.type _Z37__device_stub__Z7computePiS_S_S_S_S_iPiS_S_S_S_S_i, @function
_Z37__device_stub__Z7computePiS_S_S_S_S_iPiS_S_S_S_S_i:
.LFB10885:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movq %r8, 8(%rsp)
movq %r9, (%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
movq %rsp, %rax
movq %rax, 152(%rsp)
leaq 192(%rsp), %rax
movq %rax, 160(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z7computePiS_S_S_S_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE10885:
.size _Z37__device_stub__Z7computePiS_S_S_S_S_iPiS_S_S_S_S_i, .-_Z37__device_stub__Z7computePiS_S_S_S_S_iPiS_S_S_S_S_i
.globl _Z7computePiS_S_S_S_S_i
.type _Z7computePiS_S_S_S_S_i, @function
_Z7computePiS_S_S_S_S_i:
.LFB10886:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
call _Z37__device_stub__Z7computePiS_S_S_S_S_iPiS_S_S_S_S_i
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE10886:
.size _Z7computePiS_S_S_S_S_i, .-_Z7computePiS_S_S_S_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z7computePiS_S_S_S_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB10888:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z7computePiS_S_S_S_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE10888:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .rodata.str1.1
.LC1:
.string "Usage: "
.LC2:
.string " <graph_file_name>\n"
.LC3:
.string "Starting Computation\n"
.LC4:
.string "Finished Computation\n"
.LC6:
.string "Compute time in GPU: "
.LC7:
.string "ms"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC8:
.string "\n====== Cuda Error Code %i ======\n %s in CUDA %s\n"
.align 8
.LC9:
.string "/home/ubuntu/Datasets/stackv2/train-structured/vrn25/CUDA-Playground/master/BreadthFirstSearch/parallel_BFS_work_efficient.cu"
.section .rodata.str1.1
.LC10:
.string "\nIn file :%s\nOn line: %d"
.LC11:
.string "Depth : %d\n"
.LC12:
.string "r"
.LC13:
.string "malloc done\n"
.LC14:
.string "Finished reading output file\n"
.LC15:
.string "Starting checking\n"
.LC16:
.string "Found %d, Expected %d\n"
.LC17:
.string "Finished checking\n"
.LC18:
.string "Solution is correct!\n"
.LC19:
.string "Solution is incorrect!"
.LC20:
.string " testcases failed.\n"
.text
.globl main
.type main, @function
main:
.LFB10860:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA10860
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
movq %rsp, %rbp
.cfi_def_cfa_register 6
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $648, %rsp
.cfi_offset 15, -24
.cfi_offset 14, -32
.cfi_offset 13, -40
.cfi_offset 12, -48
.cfi_offset 3, -56
movq %rsi, %r13
movq %fs:40, %rax
movq %rax, -56(%rbp)
xorl %eax, %eax
cmpl $1, %edi
jle .L40
leaq -576(%rbp), %rbx
movq %rbx, %rdi
.LEHB0:
call _ZNSt14basic_ifstreamIcSt11char_traitsIcEEC1Ev@PLT
.LEHE0:
movq 8(%r13), %rsi
movl $8, %edx
movq %rbx, %rdi
.LEHB1:
call _ZNSt14basic_ifstreamIcSt11char_traitsIcEE4openEPKcSt13_Ios_Openmode@PLT
.LEHE1:
jmp .L41
.L40:
leaq .LC1(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
.LEHB2:
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq 0(%r13), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
leaq .LC2(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
.LEHE2:
jmp .L15
.L41:
leaq -672(%rbp), %rsi
movq %rbx, %rdi
.LEHB3:
call _ZNSirsERi@PLT
leaq -668(%rbp), %rsi
movq %rbx, %rdi
call _ZNSirsERi@PLT
movl -672(%rbp), %ebx
leal 1(%rbx), %edi
movslq %edi, %rdi
salq $2, %rdi
call malloc@PLT
movq %rax, %r15
movl -668(%rbp), %eax
leal (%rax,%rax), %edi
movslq %edi, %rdi
salq $2, %rdi
call malloc@PLT
movq %rax, %r14
testl %ebx, %ebx
js .L16
movq %r15, -680(%rbp)
movl $0, %ebx
leaq -576(%rbp), %r12
jmp .L17
.L42:
addl $1, %ebx
addq $4, -680(%rbp)
cmpl %ebx, -672(%rbp)
jl .L16
.L17:
movq -680(%rbp), %rsi
movq %r12, %rdi
call _ZNSirsERi@PLT
jmp .L42
.L16:
cmpl $0, -668(%rbp)
jle .L18
movq %r14, -680(%rbp)
movl $0, %ebx
leaq -576(%rbp), %r12
jmp .L19
.L43:
addl $1, %ebx
addq $4, -680(%rbp)
movl -668(%rbp), %eax
addl %eax, %eax
cmpl %ebx, %eax
jle .L18
.L19:
movq -680(%rbp), %rsi
movq %r12, %rdi
call _ZNSirsERi@PLT
jmp .L43
.L18:
movslq -672(%rbp), %rsi
salq $2, %rsi
leaq -664(%rbp), %rdi
call cudaMalloc@PLT
movslq -672(%rbp), %rsi
salq $2, %rsi
leaq -656(%rbp), %rdi
call cudaMalloc@PLT
movl -672(%rbp), %eax
leal 1(%rax), %esi
movslq %esi, %rsi
salq $2, %rsi
leaq -648(%rbp), %rdi
call cudaMalloc@PLT
movl -668(%rbp), %eax
leal (%rax,%rax), %esi
movslq %esi, %rsi
salq $2, %rsi
leaq -640(%rbp), %rdi
call cudaMalloc@PLT
movslq -672(%rbp), %rsi
salq $2, %rsi
leaq -632(%rbp), %rdi
call cudaMalloc@PLT
leaq -624(%rbp), %rdi
movl $4, %esi
call cudaMalloc@PLT
movl -672(%rbp), %eax
leal 1(%rax), %edx
movslq %edx, %rdx
salq $2, %rdx
movl $1, %ecx
movq %r15, %rsi
movq -648(%rbp), %rdi
call cudaMemcpy@PLT
movl -668(%rbp), %eax
leal (%rax,%rax), %edx
movslq %edx, %rdx
salq $2, %rdx
movl $1, %ecx
movq %r14, %rsi
movq -640(%rbp), %rdi
call cudaMemcpy@PLT
leaq -616(%rbp), %rdi
call cudaEventCreate@PLT
leaq -608(%rbp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq -616(%rbp), %rdi
call cudaEventRecord@PLT
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1024, -588(%rbp)
movl $1, -584(%rbp)
movl $1, -580(%rbp)
movl $1, -600(%rbp)
movl $1, -596(%rbp)
movl $0, %r9d
movl $0, %r8d
movq -588(%rbp), %rdx
movl $1, %ecx
movq -600(%rbp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L20
subq $8, %rsp
movl -672(%rbp), %eax
pushq %rax
movq -656(%rbp), %r9
movq -664(%rbp), %r8
movq -624(%rbp), %rcx
movq -632(%rbp), %rdx
movq -640(%rbp), %rsi
movq -648(%rbp), %rdi
.cfi_escape 0x2e,0x10
call _Z37__device_stub__Z7computePiS_S_S_S_S_iPiS_S_S_S_S_i
addq $16, %rsp
.L20:
.cfi_escape 0x2e,0
call cudaThreadSynchronize@PLT
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %esi
movq -608(%rbp), %rdi
call cudaEventRecord@PLT
movq -608(%rbp), %rdi
call cudaEventSynchronize@PLT
movl $0x00000000, -588(%rbp)
leaq -588(%rbp), %rdi
movq -608(%rbp), %rdx
movq -616(%rbp), %rsi
call cudaEventElapsedTime@PLT
leaq .LC6(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
pxor %xmm0, %xmm0
cvtss2sd -588(%rbp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
leaq .LC7(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $4, %edi
call malloc@PLT
movq %rax, %rbx
movl $2, %ecx
movl $4, %edx
movq -624(%rbp), %rsi
movq %rax, %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L44
.L21:
movl (%rbx), %edx
subl $1, %edx
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L45
.L44:
movl %eax, %r14d
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl %r14d, %edx
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $124, %ecx
leaq .LC9(%rip), %rdx
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L21
.L45:
movslq -672(%rbp), %rbx
salq $2, %rbx
movq %rbx, %rdi
call malloc@PLT
movq %rax, %r12
movl $2, %ecx
movq %rbx, %rdx
movq -632(%rbp), %rsi
movq %rax, %rdi
call cudaMemcpy@PLT
movslq -672(%rbp), %rdi
salq $2, %rdi
call malloc@PLT
movq %rax, %r14
movq 16(%r13), %rdi
movq stdin(%rip), %rdx
leaq .LC12(%rip), %rsi
call freopen@PLT
leaq .LC13(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
cmpl $0, -672(%rbp)
jle .L22
movq %r14, %rax
movl $0, %ebx
leaq _ZSt3cin(%rip), %r13
jmp .L23
.L46:
addl $1, %ebx
movq %r15, %rax
addq $4, %rax
cmpl %ebx, -672(%rbp)
jle .L22
.L23:
movq %rax, %r15
movq %rax, %rsi
movq %r13, %rdi
call _ZNSirsERi@PLT
jmp .L46
.L22:
leaq .LC14(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC15(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
cmpl $0, -672(%rbp)
jle .L32
movl $0, %ebx
movl $0, -680(%rbp)
movl $1, %r13d
leaq .LC16(%rip), %r15
jmp .L26
.L47:
addl $1, -680(%rbp)
movl $0, %r13d
.L25:
addq $1, %rbx
cmpl %ebx, -672(%rbp)
jle .L24
.L26:
movl (%r12,%rbx,4), %edx
movl (%r14,%rbx,4), %ecx
cmpl %ecx, %edx
je .L25
movq %r15, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L47
.L32:
movl $0, -680(%rbp)
movl $1, %r13d
.L24:
leaq .LC17(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
testb %r13b, %r13b
je .L27
leaq .LC18(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
jmp .L28
.L27:
leaq .LC19(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl -680(%rbp), %esi
leaq _ZSt4cout(%rip), %rdi
call _ZNSolsEi@PLT
movq %rax, %rdi
leaq .LC20(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
.LEHE3:
.L28:
leaq -576(%rbp), %rdi
call _ZNSt14basic_ifstreamIcSt11char_traitsIcEED1Ev@PLT
.L15:
movq -56(%rbp), %rax
subq %fs:40, %rax
jne .L48
movl $0, %eax
leaq -40(%rbp), %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
.cfi_remember_state
.cfi_def_cfa 7, 8
ret
.L33:
.cfi_restore_state
endbr64
movq %rax, %rbx
leaq -576(%rbp), %rdi
call _ZNSt14basic_ifstreamIcSt11char_traitsIcEED1Ev@PLT
movq -56(%rbp), %rax
subq %fs:40, %rax
je .L30
call __stack_chk_fail@PLT
.L30:
movq %rbx, %rdi
.LEHB4:
call _Unwind_Resume@PLT
.LEHE4:
.L48:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE10860:
.globl __gxx_personality_v0
.section .gcc_except_table,"a",@progbits
.LLSDA10860:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE10860-.LLSDACSB10860
.LLSDACSB10860:
.uleb128 .LEHB0-.LFB10860
.uleb128 .LEHE0-.LEHB0
.uleb128 0
.uleb128 0
.uleb128 .LEHB1-.LFB10860
.uleb128 .LEHE1-.LEHB1
.uleb128 .L33-.LFB10860
.uleb128 0
.uleb128 .LEHB2-.LFB10860
.uleb128 .LEHE2-.LEHB2
.uleb128 0
.uleb128 0
.uleb128 .LEHB3-.LFB10860
.uleb128 .LEHE3-.LEHB3
.uleb128 .L33-.LFB10860
.uleb128 0
.uleb128 .LEHB4-.LFB10860
.uleb128 .LEHE4-.LEHB4
.uleb128 0
.uleb128 0
.LLSDACSE10860:
.text
.size main, .-main
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.hidden DW.ref.__gxx_personality_v0
.weak DW.ref.__gxx_personality_v0
.section .data.rel.local.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat
.align 8
.type DW.ref.__gxx_personality_v0, @object
.size DW.ref.__gxx_personality_v0, 8
DW.ref.__gxx_personality_v0:
.quad __gxx_personality_v0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "parallel_BFS_work_efficient.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z22__device_stub__computePiS_S_S_S_S_i # -- Begin function _Z22__device_stub__computePiS_S_S_S_S_i
.p2align 4, 0x90
.type _Z22__device_stub__computePiS_S_S_S_S_i,@function
_Z22__device_stub__computePiS_S_S_S_S_i: # @_Z22__device_stub__computePiS_S_S_S_S_i
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
movq %r9, 48(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 160(%rsp), %rax
movq %rax, 144(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z7computePiS_S_S_S_S_i, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z22__device_stub__computePiS_S_S_S_S_i, .Lfunc_end0-_Z22__device_stub__computePiS_S_S_S_S_i
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.Lfunc_begin0:
.cfi_startproc
.cfi_personality 3, __gxx_personality_v0
.cfi_lsda 3, .Lexception0
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $760, %rsp # imm = 0x2F8
.cfi_def_cfa_offset 816
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %rbx
cmpl $1, %edi
jg .LBB1_5
# %bb.1:
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $7, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%rbx), %rbx
testq %rbx, %rbx
je .LBB1_2
# %bb.3:
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
callq strlen
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
movq %rbx, %rsi
movq %rax, %rdx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
jmp .LBB1_4
.LBB1_5:
.cfi_escape 0x2e, 0x00
leaq 240(%rsp), %r14
movq %r14, %rdi
callq _ZNSt14basic_ifstreamIcSt11char_traitsIcEEC1Ev
movq 8(%rbx), %rsi
leaq 256(%rsp), %rdi
.Ltmp0:
.cfi_escape 0x2e, 0x00
movl $8, %edx
callq _ZNSt13basic_filebufIcSt11char_traitsIcEE4openEPKcSt13_Ios_Openmode
.Ltmp1:
# %bb.6: # %.noexc
movq 240(%rsp), %rcx
addq -24(%rcx), %r14
xorl %esi, %esi
testq %rax, %rax
jne .LBB1_8
# %bb.7:
movl 32(%r14), %esi
orl $4, %esi
.LBB1_8: # %.invoke
.Ltmp2:
.cfi_escape 0x2e, 0x00
movq %r14, %rdi
callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate
.Ltmp3:
# %bb.9: # %_ZNSt14basic_ifstreamIcSt11char_traitsIcEE4openEPKcSt13_Ios_Openmode.exit
.Ltmp5:
.cfi_escape 0x2e, 0x00
leaq 240(%rsp), %rdi
movq %rsp, %rsi
callq _ZNSirsERi
.Ltmp6:
# %bb.10:
.Ltmp7:
.cfi_escape 0x2e, 0x00
leaq 240(%rsp), %rdi
leaq 4(%rsp), %rsi
callq _ZNSirsERi
.Ltmp8:
# %bb.11:
movslq (%rsp), %rax
leaq 4(,%rax,4), %rdi
.cfi_escape 0x2e, 0x00
callq malloc
movq %rax, %r15
movslq 4(%rsp), %rdi
shlq $3, %rdi
.cfi_escape 0x2e, 0x00
callq malloc
movq %rax, %r14
cmpl $0, (%rsp)
js .LBB1_15
# %bb.12: # %.lr.ph.preheader
movq $-1, %rbp
leaq 240(%rsp), %r12
movq %r15, %r13
.p2align 4, 0x90
.LBB1_13: # %.lr.ph
# =>This Inner Loop Header: Depth=1
.Ltmp10:
.cfi_escape 0x2e, 0x00
movq %r12, %rdi
movq %r13, %rsi
callq _ZNSirsERi
.Ltmp11:
# %bb.14: # in Loop: Header=BB1_13 Depth=1
movslq (%rsp), %rax
incq %rbp
addq $4, %r13
cmpq %rax, %rbp
jl .LBB1_13
.LBB1_15: # %.preheader
cmpl $0, 4(%rsp)
jle .LBB1_19
# %bb.16: # %.lr.ph119.preheader
xorl %ebp, %ebp
leaq 240(%rsp), %r12
movq %r14, %r13
.p2align 4, 0x90
.LBB1_17: # %.lr.ph119
# =>This Inner Loop Header: Depth=1
.Ltmp13:
.cfi_escape 0x2e, 0x00
movq %r12, %rdi
movq %r13, %rsi
callq _ZNSirsERi
.Ltmp14:
# %bb.18: # in Loop: Header=BB1_17 Depth=1
incq %rbp
movslq 4(%rsp), %rax
addq %rax, %rax
addq $4, %r13
cmpq %rax, %rbp
jl .LBB1_17
.LBB1_19: # %._crit_edge
movslq (%rsp), %rsi
shlq $2, %rsi
.Ltmp16:
.cfi_escape 0x2e, 0x00
leaq 72(%rsp), %rdi
callq hipMalloc
.Ltmp17:
# %bb.20:
movslq (%rsp), %rsi
shlq $2, %rsi
.Ltmp18:
.cfi_escape 0x2e, 0x00
leaq 64(%rsp), %rdi
callq hipMalloc
.Ltmp19:
# %bb.21:
movslq (%rsp), %rax
leaq 4(,%rax,4), %rsi
.Ltmp20:
.cfi_escape 0x2e, 0x00
leaq 56(%rsp), %rdi
callq hipMalloc
.Ltmp21:
# %bb.22:
movslq 4(%rsp), %rsi
shlq $3, %rsi
.Ltmp22:
.cfi_escape 0x2e, 0x00
leaq 48(%rsp), %rdi
callq hipMalloc
.Ltmp23:
# %bb.23:
movslq (%rsp), %rsi
shlq $2, %rsi
.Ltmp24:
.cfi_escape 0x2e, 0x00
leaq 40(%rsp), %rdi
callq hipMalloc
.Ltmp25:
# %bb.24:
.Ltmp26:
.cfi_escape 0x2e, 0x00
leaq 32(%rsp), %rdi
movl $4, %esi
callq hipMalloc
.Ltmp27:
# %bb.25:
movq 56(%rsp), %rdi
movslq (%rsp), %rax
leaq 4(,%rax,4), %rdx
.Ltmp28:
.cfi_escape 0x2e, 0x00
movq %r15, %rsi
movl $1, %ecx
callq hipMemcpy
.Ltmp29:
# %bb.26:
movq 48(%rsp), %rdi
movslq 4(%rsp), %rdx
shlq $3, %rdx
.Ltmp30:
.cfi_escape 0x2e, 0x00
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
.Ltmp31:
# %bb.27:
.Ltmp33:
.cfi_escape 0x2e, 0x00
leaq 24(%rsp), %rdi
callq hipEventCreate
.Ltmp34:
# %bb.28:
.Ltmp35:
.cfi_escape 0x2e, 0x00
leaq 8(%rsp), %rdi
callq hipEventCreate
.Ltmp36:
# %bb.29:
movq 24(%rsp), %rdi
.Ltmp37:
.cfi_escape 0x2e, 0x00
xorl %esi, %esi
callq hipEventRecord
.Ltmp38:
# %bb.30:
.cfi_escape 0x2e, 0x00
movl $.Lstr, %edi
callq puts@PLT
.Ltmp39:
.cfi_escape 0x2e, 0x00
movabsq $4294967297, %rdi # imm = 0x100000001
movabsq $4294968320, %rdx # imm = 0x100000400
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
.Ltmp40:
# %bb.31:
testl %eax, %eax
jne .LBB1_34
# %bb.32:
movq 56(%rsp), %rax
movq 48(%rsp), %rcx
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
movq 72(%rsp), %rdi
movq 64(%rsp), %r8
movl (%rsp), %r9d
movq %rax, 168(%rsp)
movq %rcx, 160(%rsp)
movq %rdx, 152(%rsp)
movq %rsi, 144(%rsp)
movq %rdi, 136(%rsp)
movq %r8, 128(%rsp)
movl %r9d, 20(%rsp)
leaq 168(%rsp), %rax
movq %rax, 176(%rsp)
leaq 160(%rsp), %rax
movq %rax, 184(%rsp)
leaq 152(%rsp), %rax
movq %rax, 192(%rsp)
leaq 144(%rsp), %rax
movq %rax, 200(%rsp)
leaq 136(%rsp), %rax
movq %rax, 208(%rsp)
leaq 128(%rsp), %rax
movq %rax, 216(%rsp)
leaq 20(%rsp), %rax
movq %rax, 224(%rsp)
.Ltmp41:
.cfi_escape 0x2e, 0x00
leaq 112(%rsp), %rdi
leaq 96(%rsp), %rsi
leaq 88(%rsp), %rdx
leaq 80(%rsp), %rcx
callq __hipPopCallConfiguration
.Ltmp42:
# %bb.33: # %.noexc79
movq 112(%rsp), %rsi
movl 120(%rsp), %edx
movq 96(%rsp), %rcx
movl 104(%rsp), %r8d
.Ltmp43:
.cfi_escape 0x2e, 0x10
leaq 176(%rsp), %r9
movl $_Z7computePiS_S_S_S_S_i, %edi
pushq 80(%rsp)
.cfi_adjust_cfa_offset 8
pushq 96(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.Ltmp44:
.LBB1_34:
.Ltmp45:
.cfi_escape 0x2e, 0x00
callq hipDeviceSynchronize
.Ltmp46:
# %bb.35:
.cfi_escape 0x2e, 0x00
movl $.Lstr.1, %edi
callq puts@PLT
movq 8(%rsp), %rdi
.Ltmp47:
.cfi_escape 0x2e, 0x00
xorl %esi, %esi
callq hipEventRecord
.Ltmp48:
# %bb.36:
movq 8(%rsp), %rdi
.Ltmp49:
.cfi_escape 0x2e, 0x00
callq hipEventSynchronize
.Ltmp50:
# %bb.37:
movl $0, 176(%rsp)
movq 24(%rsp), %rsi
movq 8(%rsp), %rdx
.Ltmp52:
.cfi_escape 0x2e, 0x00
leaq 176(%rsp), %rdi
callq hipEventElapsedTime
.Ltmp53:
# %bb.38:
.Ltmp54:
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
movl $.L.str.4, %esi
movl $21, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp55:
# %bb.39: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit82
movss 176(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
.Ltmp56:
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
.Ltmp57:
# %bb.40: # %_ZNSolsEf.exit
.Ltmp58:
movq %rax, %r14
.cfi_escape 0x2e, 0x00
movl $.L.str.5, %esi
movl $2, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp59:
# %bb.41: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit85
movq (%r14), %rax
movq -24(%rax), %rax
movq 240(%r14,%rax), %r15
testq %r15, %r15
je .LBB1_42
# %bb.50: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%r15)
je .LBB1_52
# %bb.51:
movzbl 67(%r15), %eax
jmp .LBB1_54
.LBB1_2:
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
leaq _ZSt4cout(%rax), %rdi
movl _ZSt4cout+32(%rax), %esi
orl $1, %esi
.cfi_escape 0x2e, 0x00
callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate
.LBB1_4: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $19, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
jmp .LBB1_94
.LBB1_52:
.Ltmp60:
.cfi_escape 0x2e, 0x00
movq %r15, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
.Ltmp61:
# %bb.53: # %.noexc98
movq (%r15), %rax
.Ltmp62:
.cfi_escape 0x2e, 0x00
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
.Ltmp63:
.LBB1_54: # %_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc.exit.i
.Ltmp64:
.cfi_escape 0x2e, 0x00
movsbl %al, %esi
movq %r14, %rdi
callq _ZNSo3putEc
.Ltmp65:
# %bb.55: # %.noexc100
.Ltmp66:
.cfi_escape 0x2e, 0x00
movq %rax, %rdi
callq _ZNSo5flushEv
.Ltmp67:
# %bb.56: # %_ZNSolsEPFRSoS_E.exit
.cfi_escape 0x2e, 0x00
movl $4, %edi
callq malloc
movq %rax, %r14
movq 32(%rsp), %rsi
.Ltmp68:
.cfi_escape 0x2e, 0x00
movl $4, %edx
movq %rax, %rdi
movl $2, %ecx
callq hipMemcpy
.Ltmp69:
# %bb.57:
movl %eax, %ebp
testl %eax, %eax
je .LBB1_60
# %bb.58:
.Ltmp70:
.cfi_escape 0x2e, 0x00
movl %ebp, %edi
callq hipGetErrorString
.Ltmp71:
# %bb.59: # %.noexc88
.cfi_escape 0x2e, 0x00
movl $.L.str.17, %edi
movl %ebp, %esi
movq %rax, %rdx
xorl %eax, %eax
callq printf
.cfi_escape 0x2e, 0x00
movl $.L.str.18, %edi
movl $.L.str.6, %esi
movl $126, %edx
xorl %eax, %eax
callq printf
.LBB1_60: # %_Z9gpuAssert10hipError_tPKcib.exit
movl (%r14), %esi
decl %esi
.cfi_escape 0x2e, 0x00
movl $.L.str.7, %edi
xorl %eax, %eax
callq printf
movslq (%rsp), %r15
shlq $2, %r15
.cfi_escape 0x2e, 0x00
movq %r15, %rdi
callq malloc
movq %rax, %r14
movq 40(%rsp), %rsi
.Ltmp73:
.cfi_escape 0x2e, 0x00
movq %rax, %rdi
movq %r15, %rdx
movl $2, %ecx
callq hipMemcpy
.Ltmp74:
# %bb.61:
movslq (%rsp), %rdi
shlq $2, %rdi
.cfi_escape 0x2e, 0x00
callq malloc
movq %rax, %r15
movq 16(%rbx), %rdi
movq stdin(%rip), %rdx
.Ltmp76:
.cfi_escape 0x2e, 0x00
movl $.L.str.8, %esi
callq freopen
.Ltmp77:
# %bb.62:
.cfi_escape 0x2e, 0x00
movl $.Lstr.2, %edi
callq puts@PLT
cmpl $0, (%rsp)
jle .LBB1_66
# %bb.63: # %.lr.ph122.preheader
xorl %r12d, %r12d
movq %r15, %rbx
.p2align 4, 0x90
.LBB1_64: # %.lr.ph122
# =>This Inner Loop Header: Depth=1
.Ltmp79:
.cfi_escape 0x2e, 0x00
movl $_ZSt3cin, %edi
movq %rbx, %rsi
callq _ZNSirsERi
.Ltmp80:
# %bb.65: # in Loop: Header=BB1_64 Depth=1
incq %r12
movslq (%rsp), %rax
addq $4, %rbx
cmpq %rax, %r12
jl .LBB1_64
.LBB1_66: # %._crit_edge123
.cfi_escape 0x2e, 0x00
movl $.Lstr.3, %edi
callq puts@PLT
.cfi_escape 0x2e, 0x00
movl $.Lstr.4, %edi
callq puts@PLT
cmpl $0, (%rsp)
jle .LBB1_67
# %bb.76: # %.lr.ph128.preheader
movb $1, %bpl
xorl %r12d, %r12d
xorl %ebx, %ebx
jmp .LBB1_77
.p2align 4, 0x90
.LBB1_79: # in Loop: Header=BB1_77 Depth=1
incq %r12
movslq (%rsp), %rax
cmpq %rax, %r12
jge .LBB1_72
.LBB1_77: # %.lr.ph128
# =>This Inner Loop Header: Depth=1
movl (%r14,%r12,4), %esi
movl (%r15,%r12,4), %edx
cmpl %edx, %esi
je .LBB1_79
# %bb.78: # in Loop: Header=BB1_77 Depth=1
.cfi_escape 0x2e, 0x00
xorl %ebp, %ebp
movl $.L.str.12, %edi
xorl %eax, %eax
callq printf
incl %ebx
jmp .LBB1_79
.LBB1_72: # %._crit_edge129.loopexit
testb $1, %bpl
sete %bpl
jmp .LBB1_73
.LBB1_67:
xorl %ebp, %ebp
xorl %ebx, %ebx
.LBB1_73: # %._crit_edge129
.cfi_escape 0x2e, 0x00
movl $.Lstr.5, %edi
callq puts@PLT
testb %bpl, %bpl
je .LBB1_74
# %bb.80:
.Ltmp82:
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
movl $.L.str.15, %esi
movl $22, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp83:
# %bb.81: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit92
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r14
testq %r14, %r14
je .LBB1_82
# %bb.84: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i103
cmpb $0, 56(%r14)
je .LBB1_86
# %bb.85:
movzbl 67(%r14), %eax
jmp .LBB1_88
.LBB1_74:
movl $21, %edx
movl $.L.str.14, %esi
movl $_ZSt4cout, %edi
jmp .LBB1_92
.LBB1_86:
.Ltmp84:
.cfi_escape 0x2e, 0x00
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
.Ltmp85:
# %bb.87: # %.noexc108
movq (%r14), %rax
.Ltmp86:
.cfi_escape 0x2e, 0x00
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.Ltmp87:
.LBB1_88: # %_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc.exit.i105
.Ltmp88:
.cfi_escape 0x2e, 0x00
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
.Ltmp89:
# %bb.89: # %.noexc110
.Ltmp90:
.cfi_escape 0x2e, 0x00
movq %rax, %rdi
callq _ZNSo5flushEv
.Ltmp91:
# %bb.90: # %_ZNSolsEPFRSoS_E.exit94
.Ltmp92:
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
movl %ebx, %esi
callq _ZNSolsEi
.Ltmp93:
# %bb.91:
movq %rax, %rdi
movl $19, %edx
movl $.L.str.16, %esi
.LBB1_92: # %.invoke140
.Ltmp94:
.cfi_escape 0x2e, 0x00
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp95:
# %bb.93: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit90
.cfi_escape 0x2e, 0x00
leaq 240(%rsp), %rdi
movl $_ZTTSt14basic_ifstreamIcSt11char_traitsIcEE, %esi
callq _ZNSt14basic_ifstreamIcSt11char_traitsIcEED2Ev
leaq 496(%rsp), %rdi
.cfi_escape 0x2e, 0x00
callq _ZNSt8ios_baseD2Ev
.LBB1_94:
xorl %eax, %eax
addq $760, %rsp # imm = 0x2F8
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_42:
.cfi_def_cfa_offset 816
.Ltmp99:
.cfi_escape 0x2e, 0x00
callq _ZSt16__throw_bad_castv
.Ltmp100:
# %bb.49: # %.noexc97
.LBB1_82:
.Ltmp96:
.cfi_escape 0x2e, 0x00
callq _ZSt16__throw_bad_castv
.Ltmp97:
# %bb.83: # %.noexc107
.LBB1_70:
.Ltmp78:
jmp .LBB1_96
.LBB1_69:
.Ltmp75:
jmp .LBB1_96
.LBB1_68:
.Ltmp72:
jmp .LBB1_96
.LBB1_44:
.Ltmp9:
jmp .LBB1_96
.LBB1_43:
.Ltmp4:
jmp .LBB1_96
.LBB1_75:
.Ltmp98:
jmp .LBB1_96
.LBB1_95:
.Ltmp101:
jmp .LBB1_96
.LBB1_48:
.Ltmp51:
jmp .LBB1_96
.LBB1_47:
.Ltmp32:
jmp .LBB1_96
.LBB1_71:
.Ltmp81:
jmp .LBB1_96
.LBB1_45: # %.loopexit
.Ltmp15:
jmp .LBB1_96
.LBB1_46: # %.loopexit.split-lp
.Ltmp12:
.LBB1_96:
movq %rax, %rbx
.cfi_escape 0x2e, 0x00
leaq 240(%rsp), %rdi
movl $_ZTTSt14basic_ifstreamIcSt11char_traitsIcEE, %esi
callq _ZNSt14basic_ifstreamIcSt11char_traitsIcEED2Ev
leaq 496(%rsp), %rdi
.cfi_escape 0x2e, 0x00
callq _ZNSt8ios_baseD2Ev
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
callq _Unwind_Resume@PLT
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
.section .gcc_except_table,"a",@progbits
.p2align 2, 0x0
GCC_except_table1:
.Lexception0:
.byte 255 # @LPStart Encoding = omit
.byte 255 # @TType Encoding = omit
.byte 1 # Call site Encoding = uleb128
.uleb128 .Lcst_end0-.Lcst_begin0
.Lcst_begin0:
.uleb128 .Lfunc_begin0-.Lfunc_begin0 # >> Call Site 1 <<
.uleb128 .Ltmp0-.Lfunc_begin0 # Call between .Lfunc_begin0 and .Ltmp0
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp0-.Lfunc_begin0 # >> Call Site 2 <<
.uleb128 .Ltmp3-.Ltmp0 # Call between .Ltmp0 and .Ltmp3
.uleb128 .Ltmp4-.Lfunc_begin0 # jumps to .Ltmp4
.byte 0 # On action: cleanup
.uleb128 .Ltmp5-.Lfunc_begin0 # >> Call Site 3 <<
.uleb128 .Ltmp8-.Ltmp5 # Call between .Ltmp5 and .Ltmp8
.uleb128 .Ltmp9-.Lfunc_begin0 # jumps to .Ltmp9
.byte 0 # On action: cleanup
.uleb128 .Ltmp10-.Lfunc_begin0 # >> Call Site 4 <<
.uleb128 .Ltmp11-.Ltmp10 # Call between .Ltmp10 and .Ltmp11
.uleb128 .Ltmp12-.Lfunc_begin0 # jumps to .Ltmp12
.byte 0 # On action: cleanup
.uleb128 .Ltmp13-.Lfunc_begin0 # >> Call Site 5 <<
.uleb128 .Ltmp14-.Ltmp13 # Call between .Ltmp13 and .Ltmp14
.uleb128 .Ltmp15-.Lfunc_begin0 # jumps to .Ltmp15
.byte 0 # On action: cleanup
.uleb128 .Ltmp16-.Lfunc_begin0 # >> Call Site 6 <<
.uleb128 .Ltmp31-.Ltmp16 # Call between .Ltmp16 and .Ltmp31
.uleb128 .Ltmp32-.Lfunc_begin0 # jumps to .Ltmp32
.byte 0 # On action: cleanup
.uleb128 .Ltmp33-.Lfunc_begin0 # >> Call Site 7 <<
.uleb128 .Ltmp50-.Ltmp33 # Call between .Ltmp33 and .Ltmp50
.uleb128 .Ltmp51-.Lfunc_begin0 # jumps to .Ltmp51
.byte 0 # On action: cleanup
.uleb128 .Ltmp52-.Lfunc_begin0 # >> Call Site 8 <<
.uleb128 .Ltmp59-.Ltmp52 # Call between .Ltmp52 and .Ltmp59
.uleb128 .Ltmp101-.Lfunc_begin0 # jumps to .Ltmp101
.byte 0 # On action: cleanup
.uleb128 .Ltmp59-.Lfunc_begin0 # >> Call Site 9 <<
.uleb128 .Ltmp60-.Ltmp59 # Call between .Ltmp59 and .Ltmp60
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp60-.Lfunc_begin0 # >> Call Site 10 <<
.uleb128 .Ltmp67-.Ltmp60 # Call between .Ltmp60 and .Ltmp67
.uleb128 .Ltmp101-.Lfunc_begin0 # jumps to .Ltmp101
.byte 0 # On action: cleanup
.uleb128 .Ltmp68-.Lfunc_begin0 # >> Call Site 11 <<
.uleb128 .Ltmp71-.Ltmp68 # Call between .Ltmp68 and .Ltmp71
.uleb128 .Ltmp72-.Lfunc_begin0 # jumps to .Ltmp72
.byte 0 # On action: cleanup
.uleb128 .Ltmp73-.Lfunc_begin0 # >> Call Site 12 <<
.uleb128 .Ltmp74-.Ltmp73 # Call between .Ltmp73 and .Ltmp74
.uleb128 .Ltmp75-.Lfunc_begin0 # jumps to .Ltmp75
.byte 0 # On action: cleanup
.uleb128 .Ltmp76-.Lfunc_begin0 # >> Call Site 13 <<
.uleb128 .Ltmp77-.Ltmp76 # Call between .Ltmp76 and .Ltmp77
.uleb128 .Ltmp78-.Lfunc_begin0 # jumps to .Ltmp78
.byte 0 # On action: cleanup
.uleb128 .Ltmp79-.Lfunc_begin0 # >> Call Site 14 <<
.uleb128 .Ltmp80-.Ltmp79 # Call between .Ltmp79 and .Ltmp80
.uleb128 .Ltmp81-.Lfunc_begin0 # jumps to .Ltmp81
.byte 0 # On action: cleanup
.uleb128 .Ltmp82-.Lfunc_begin0 # >> Call Site 15 <<
.uleb128 .Ltmp95-.Ltmp82 # Call between .Ltmp82 and .Ltmp95
.uleb128 .Ltmp98-.Lfunc_begin0 # jumps to .Ltmp98
.byte 0 # On action: cleanup
.uleb128 .Ltmp99-.Lfunc_begin0 # >> Call Site 16 <<
.uleb128 .Ltmp100-.Ltmp99 # Call between .Ltmp99 and .Ltmp100
.uleb128 .Ltmp101-.Lfunc_begin0 # jumps to .Ltmp101
.byte 0 # On action: cleanup
.uleb128 .Ltmp96-.Lfunc_begin0 # >> Call Site 17 <<
.uleb128 .Ltmp97-.Ltmp96 # Call between .Ltmp96 and .Ltmp97
.uleb128 .Ltmp98-.Lfunc_begin0 # jumps to .Ltmp98
.byte 0 # On action: cleanup
.uleb128 .Ltmp97-.Lfunc_begin0 # >> Call Site 18 <<
.uleb128 .Lfunc_end1-.Ltmp97 # Call between .Ltmp97 and .Lfunc_end1
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.Lcst_end0:
.p2align 2, 0x0
# -- End function
.text
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7computePiS_S_S_S_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z7computePiS_S_S_S_S_i,@object # @_Z7computePiS_S_S_S_S_i
.section .rodata,"a",@progbits
.globl _Z7computePiS_S_S_S_S_i
.p2align 3, 0x0
_Z7computePiS_S_S_S_S_i:
.quad _Z22__device_stub__computePiS_S_S_S_S_i
.size _Z7computePiS_S_S_S_S_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Usage: "
.size .L.str, 8
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz " <graph_file_name>\n"
.size .L.str.1, 20
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Compute time in GPU: "
.size .L.str.4, 22
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "ms"
.size .L.str.5, 3
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/vrn25/CUDA-Playground/master/BreadthFirstSearch/parallel_BFS_work_efficient.hip"
.size .L.str.6, 137
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "Depth : %d\n"
.size .L.str.7, 12
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "r"
.size .L.str.8, 2
.type .L.str.12,@object # @.str.12
.L.str.12:
.asciz "Found %d, Expected %d\n"
.size .L.str.12, 23
.type .L.str.14,@object # @.str.14
.L.str.14:
.asciz "Solution is correct!\n"
.size .L.str.14, 22
.type .L.str.15,@object # @.str.15
.L.str.15:
.asciz "Solution is incorrect!"
.size .L.str.15, 23
.type .L.str.16,@object # @.str.16
.L.str.16:
.asciz " testcases failed.\n"
.size .L.str.16, 20
.type .L.str.17,@object # @.str.17
.L.str.17:
.asciz "\n====== Cuda Error Code %i ======\n %s in CUDA %s\n"
.size .L.str.17, 50
.type .L.str.18,@object # @.str.18
.L.str.18:
.asciz "\nIn file :%s\nOn line: %d"
.size .L.str.18, 25
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z7computePiS_S_S_S_S_i"
.size .L__unnamed_1, 24
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Starting Computation"
.size .Lstr, 21
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "Finished Computation"
.size .Lstr.1, 21
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "malloc done"
.size .Lstr.2, 12
.type .Lstr.3,@object # @str.3
.Lstr.3:
.asciz "Finished reading output file"
.size .Lstr.3, 29
.type .Lstr.4,@object # @str.4
.Lstr.4:
.asciz "Starting checking"
.size .Lstr.4, 18
.type .Lstr.5,@object # @str.5
.Lstr.5:
.asciz "Finished checking"
.size .Lstr.5, 18
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__computePiS_S_S_S_S_i
.addrsig_sym __gxx_personality_v0
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Unwind_Resume
.addrsig_sym _Z7computePiS_S_S_S_S_i
.addrsig_sym _ZSt4cout
.addrsig_sym _ZSt3cin
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <cuda.h>
#include <cuda_runtime.h>
#define N 20000
#define GRID_D1 20
#define GRID_D2 2
#define BLOCK_D1 512
#define BLOCK_D2 1
#define BLOCK_D3 1
// this is the kernel function called for each thread
// we use the CUDA variables {threadIdx, blockIdx, blockDim, gridDim} to determine a unique ID for each thread
__global__ void hello(void)
{
// id of the block
int myblock = blockIdx.x + blockIdx.y * gridDim.x;
// size of each block (within grid of blocks)
int blocksize = blockDim.x * blockDim.y * blockDim.z;
// id of thread in a given block
int subthread = threadIdx.z*(blockDim.x * blockDim.y) + threadIdx.y*blockDim.x + threadIdx.x;
// assign overall id/index of the thread
int idx = myblock * blocksize + subthread;
if(idx < 2000 || idx > 19000) {
// print buffer from within the kernel is limited so only print for first and last chunks of thread
if (idx < N){
printf("Hello World! My block index is (%d, %d) [Grid dims=(%d,%d)], 3D-thread index within blocks=(%d,%d,%d) => \
thread index=%d\n", blockIdx.x, blockIdx.y, gridDim.x, gridDim.y, threadIdx.x, threadIdx.y, threadIdx.z, idx);
} else {
printf("Hello world! My block index is (%d,%d) [Grid dims=(%d,%d)], 3D-thread index within block=(%d,%d,%d) => \
thread index=%d [### this thread would not be used for N=%d ###]\n", blockIdx.x, blockIdx.y, gridDim.x, gridDim.y,
threadIdx.x, threadIdx.y, threadIdx.z, idx, N);
}
}
}
int main(int argc, char **argv)
{
// objects containing the block and grid info
const dim3 blockSize(BLOCK_D1, BLOCK_D2, BLOCK_D3);
const dim3 gridSize(GRID_D1, GRID_D2, 1);
int nthreads = BLOCK_D1*BLOCK_D2*BLOCK_D3*GRID_D1*GRID_D2;
if (nthreads < N){
printf("\n================ NOT ENOUGH THREADS TO COVER N=%d ===================\n\n",N);
} else {
printf("Launching %d threads (N=%d)\n", nthreads, N);
}
// launch the kernel on the specified grid of thread blocks
hello<<<gridSize, blockSize>>>();
// Need to flush prints, otherwise none of the prints from within the kernel will show up
// as program exit does not flush the print buffer.
cudaError_t cudaerr = cudaDeviceSynchronize();
if (cudaerr) {
printf("kernel launch failed with error \"%s\".\n",
cudaGetErrorString(cudaerr));
} else {
printf("kernel launch success!\n");
}
printf("That's all!\n");
return 0;
} | code for sm_80
Function : _Z5hellov
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fc800078e00ff */
/*0010*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e220000002600 */
/*0020*/ IADD3 R1, R1, -0x28, RZ ; /* 0xffffffd801017810 */
/* 0x000fc60007ffe0ff */
/*0030*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e280000002500 */
/*0040*/ S2R R4, SR_TID.Z ; /* 0x0000000000047919 */
/* 0x000e680000002300 */
/*0050*/ S2R R7, SR_TID.Y ; /* 0x0000000000077919 */
/* 0x000ea80000002200 */
/*0060*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000ee20000002100 */
/*0070*/ IMAD R5, R3, c[0x0][0xc], R2 ; /* 0x0000030003057a24 */
/* 0x001fc800078e0202 */
/*0080*/ IMAD R0, R5, c[0x0][0x8], R4 ; /* 0x0000020005007a24 */
/* 0x002fc800078e0204 */
/*0090*/ IMAD R5, R0, c[0x0][0x4], R7 ; /* 0x0000010000057a24 */
/* 0x004fc800078e0207 */
/*00a0*/ IMAD R5, R5, c[0x0][0x0], R6 ; /* 0x0000000005057a24 */
/* 0x008fca00078e0206 */
/*00b0*/ IADD3 R0, R5, -0x7d0, RZ ; /* 0xfffff83005007810 */
/* 0x000fc80007ffe0ff */
/*00c0*/ ISETP.GE.U32.AND P0, PT, R0, 0x4269, PT ; /* 0x000042690000780c */
/* 0x000fda0003f06070 */
/*00d0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*00e0*/ IMAD.MOV.U32 R8, RZ, RZ, c[0x0][0xc] ; /* 0x00000300ff087624 */
/* 0x000fe200078e00ff */
/*00f0*/ STL.64 [R1], R2 ; /* 0x0000000201007387 */
/* 0x000fe20000100a00 */
/*0100*/ IMAD.MOV.U32 R9, RZ, RZ, c[0x0][0x10] ; /* 0x00000400ff097624 */
/* 0x000fe200078e00ff */
/*0110*/ ISETP.GE.AND P0, PT, R5, 0x4e20, PT ; /* 0x00004e200500780c */
/* 0x000fe40003f06270 */
/*0120*/ STL.64 [R1+0x18], R4 ; /* 0x0000180401007387 */
/* 0x000fe80000100a00 */
/*0130*/ STL.64 [R1+0x8], R8 ; /* 0x0000080801007387 */
/* 0x000fe80000100a00 */
/*0140*/ STL.64 [R1+0x10], R6 ; /* 0x0000100601007387 */
/* 0x0001e40000100a00 */
/*0150*/ IADD3 R6, P1, R1, c[0x0][0x20], RZ ; /* 0x0000080001067a10 */
/* 0x001fca0007f3e0ff */
/*0160*/ IMAD.X R7, RZ, RZ, c[0x0][0x24], P1 ; /* 0x00000900ff077624 */
/* 0x000fe200008e06ff */
/*0170*/ @!P0 BRA 0x270 ; /* 0x000000f000008947 */
/* 0x000fea0003800000 */
/*0180*/ IMAD.MOV.U32 R8, RZ, RZ, 0x4e20 ; /* 0x00004e20ff087424 */
/* 0x000fe200078e00ff */
/*0190*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe20000000f00 */
/*01a0*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x10] ; /* 0x01000400ff047624 */
/* 0x000fe400078e00ff */
/*01b0*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0x14] ; /* 0x01000500ff057624 */
/* 0x000fe200078e00ff */
/*01c0*/ STL [R1+0x20], R8 ; /* 0x0000200801007387 */
/* 0x0001e20000100800 */
/*01d0*/ LDC.64 R2, c[0x4][R0] ; /* 0x0100000000027b82 */
/* 0x00006a0000000a00 */
/*01e0*/ LEPC R8 ; /* 0x000000000008734e */
/* 0x001fe20000000000 */
/*01f0*/ MOV R11, 0x260 ; /* 0x00000260000b7802 */
/* 0x000fe40000000f00 */
/*0200*/ MOV R20, 0x1e0 ; /* 0x000001e000147802 */
/* 0x000fc40000000f00 */
/*0210*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*0220*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe40000000f00 */
/*0230*/ IADD3 R20, P0, P1, -R20, R11, R8 ; /* 0x0000000b14147210 */
/* 0x000fc8000791e108 */
/*0240*/ IADD3.X R21, ~R0, R21, R9, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2509 */
/*0250*/ CALL.ABS.NOINC R2 ; /* 0x0000000002007343 */
/* 0x002fea0003c00000 */
/*0260*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0270*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe20000000f00 */
/*0280*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x8] ; /* 0x01000200ff047624 */
/* 0x000fe400078e00ff */
/*0290*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0xc] ; /* 0x01000300ff057624 */
/* 0x000fe200078e00ff */
/*02a0*/ LDC.64 R2, c[0x4][R0] ; /* 0x0100000000027b82 */
/* 0x00006c0000000a00 */
/*02b0*/ LEPC R8 ; /* 0x000000000008734e */
/* 0x000fe20000000000 */
/*02c0*/ MOV R11, 0x330 ; /* 0x00000330000b7802 */
/* 0x000fe40000000f00 */
/*02d0*/ MOV R20, 0x2b0 ; /* 0x000002b000147802 */
/* 0x000fe40000000f00 */
/*02e0*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*02f0*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x001fc40000000f00 */
/*0300*/ IADD3 R20, P0, P1, -R20, R11, R8 ; /* 0x0000000b14147210 */
/* 0x000fc8000791e108 */
/*0310*/ IADD3.X R21, ~R0, R21, R9, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2509 */
/*0320*/ CALL.ABS.NOINC R2 ; /* 0x0000000002007343 */
/* 0x002fea0003c00000 */
/*0330*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0340*/ BRA 0x340; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0380*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0390*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <cuda.h>
#include <cuda_runtime.h>
#define N 20000
#define GRID_D1 20
#define GRID_D2 2
#define BLOCK_D1 512
#define BLOCK_D2 1
#define BLOCK_D3 1
// this is the kernel function called for each thread
// we use the CUDA variables {threadIdx, blockIdx, blockDim, gridDim} to determine a unique ID for each thread
__global__ void hello(void)
{
// id of the block
int myblock = blockIdx.x + blockIdx.y * gridDim.x;
// size of each block (within grid of blocks)
int blocksize = blockDim.x * blockDim.y * blockDim.z;
// id of thread in a given block
int subthread = threadIdx.z*(blockDim.x * blockDim.y) + threadIdx.y*blockDim.x + threadIdx.x;
// assign overall id/index of the thread
int idx = myblock * blocksize + subthread;
if(idx < 2000 || idx > 19000) {
// print buffer from within the kernel is limited so only print for first and last chunks of thread
if (idx < N){
printf("Hello World! My block index is (%d, %d) [Grid dims=(%d,%d)], 3D-thread index within blocks=(%d,%d,%d) => \
thread index=%d\n", blockIdx.x, blockIdx.y, gridDim.x, gridDim.y, threadIdx.x, threadIdx.y, threadIdx.z, idx);
} else {
printf("Hello world! My block index is (%d,%d) [Grid dims=(%d,%d)], 3D-thread index within block=(%d,%d,%d) => \
thread index=%d [### this thread would not be used for N=%d ###]\n", blockIdx.x, blockIdx.y, gridDim.x, gridDim.y,
threadIdx.x, threadIdx.y, threadIdx.z, idx, N);
}
}
}
int main(int argc, char **argv)
{
// objects containing the block and grid info
const dim3 blockSize(BLOCK_D1, BLOCK_D2, BLOCK_D3);
const dim3 gridSize(GRID_D1, GRID_D2, 1);
int nthreads = BLOCK_D1*BLOCK_D2*BLOCK_D3*GRID_D1*GRID_D2;
if (nthreads < N){
printf("\n================ NOT ENOUGH THREADS TO COVER N=%d ===================\n\n",N);
} else {
printf("Launching %d threads (N=%d)\n", nthreads, N);
}
// launch the kernel on the specified grid of thread blocks
hello<<<gridSize, blockSize>>>();
// Need to flush prints, otherwise none of the prints from within the kernel will show up
// as program exit does not flush the print buffer.
cudaError_t cudaerr = cudaDeviceSynchronize();
if (cudaerr) {
printf("kernel launch failed with error \"%s\".\n",
cudaGetErrorString(cudaerr));
} else {
printf("kernel launch success!\n");
}
printf("That's all!\n");
return 0;
} | .file "tmpxft_000ea869_00000000-6_helloWorld.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z23__device_stub__Z5hellovv
.type _Z23__device_stub__Z5hellovv, @function
_Z23__device_stub__Z5hellovv:
.LFB2082:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z5hellov(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z23__device_stub__Z5hellovv, .-_Z23__device_stub__Z5hellovv
.globl _Z5hellov
.type _Z5hellov, @function
_Z5hellov:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z23__device_stub__Z5hellovv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z5hellov, .-_Z5hellov
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Launching %d threads (N=%d)\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "kernel launch failed with error \"%s\".\n"
.section .rodata.str1.1
.LC2:
.string "kernel launch success!\n"
.LC3:
.string "That's all!\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movl $512, 8(%rsp)
movl $1, 12(%rsp)
movl $1, 16(%rsp)
movl $20, 20(%rsp)
movl $2, 24(%rsp)
movl $1, 28(%rsp)
movl $20000, %ecx
movl $20480, %edx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 16(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 8(%rsp), %rdx
movq 20(%rsp), %rdi
movl 28(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L16
.L12:
call cudaDeviceSynchronize@PLT
testl %eax, %eax
je .L13
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L14:
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L16:
.cfi_restore_state
call _Z23__device_stub__Z5hellovv
jmp .L12
.L13:
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L14
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC4:
.string "_Z5hellov"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z5hellov(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <cuda.h>
#include <cuda_runtime.h>
#define N 20000
#define GRID_D1 20
#define GRID_D2 2
#define BLOCK_D1 512
#define BLOCK_D2 1
#define BLOCK_D3 1
// this is the kernel function called for each thread
// we use the CUDA variables {threadIdx, blockIdx, blockDim, gridDim} to determine a unique ID for each thread
__global__ void hello(void)
{
// id of the block
int myblock = blockIdx.x + blockIdx.y * gridDim.x;
// size of each block (within grid of blocks)
int blocksize = blockDim.x * blockDim.y * blockDim.z;
// id of thread in a given block
int subthread = threadIdx.z*(blockDim.x * blockDim.y) + threadIdx.y*blockDim.x + threadIdx.x;
// assign overall id/index of the thread
int idx = myblock * blocksize + subthread;
if(idx < 2000 || idx > 19000) {
// print buffer from within the kernel is limited so only print for first and last chunks of thread
if (idx < N){
printf("Hello World! My block index is (%d, %d) [Grid dims=(%d,%d)], 3D-thread index within blocks=(%d,%d,%d) => \
thread index=%d\n", blockIdx.x, blockIdx.y, gridDim.x, gridDim.y, threadIdx.x, threadIdx.y, threadIdx.z, idx);
} else {
printf("Hello world! My block index is (%d,%d) [Grid dims=(%d,%d)], 3D-thread index within block=(%d,%d,%d) => \
thread index=%d [### this thread would not be used for N=%d ###]\n", blockIdx.x, blockIdx.y, gridDim.x, gridDim.y,
threadIdx.x, threadIdx.y, threadIdx.z, idx, N);
}
}
}
int main(int argc, char **argv)
{
// objects containing the block and grid info
const dim3 blockSize(BLOCK_D1, BLOCK_D2, BLOCK_D3);
const dim3 gridSize(GRID_D1, GRID_D2, 1);
int nthreads = BLOCK_D1*BLOCK_D2*BLOCK_D3*GRID_D1*GRID_D2;
if (nthreads < N){
printf("\n================ NOT ENOUGH THREADS TO COVER N=%d ===================\n\n",N);
} else {
printf("Launching %d threads (N=%d)\n", nthreads, N);
}
// launch the kernel on the specified grid of thread blocks
hello<<<gridSize, blockSize>>>();
// Need to flush prints, otherwise none of the prints from within the kernel will show up
// as program exit does not flush the print buffer.
cudaError_t cudaerr = cudaDeviceSynchronize();
if (cudaerr) {
printf("kernel launch failed with error \"%s\".\n",
cudaGetErrorString(cudaerr));
} else {
printf("kernel launch success!\n");
}
printf("That's all!\n");
return 0;
} | #include <stdio.h>
#include <hip/hip_runtime.h>
#define N 20000
#define GRID_D1 20
#define GRID_D2 2
#define BLOCK_D1 512
#define BLOCK_D2 1
#define BLOCK_D3 1
// this is the kernel function called for each thread
// we use the CUDA variables {threadIdx, blockIdx, blockDim, gridDim} to determine a unique ID for each thread
__global__ void hello(void)
{
// id of the block
int myblock = blockIdx.x + blockIdx.y * gridDim.x;
// size of each block (within grid of blocks)
int blocksize = blockDim.x * blockDim.y * blockDim.z;
// id of thread in a given block
int subthread = threadIdx.z*(blockDim.x * blockDim.y) + threadIdx.y*blockDim.x + threadIdx.x;
// assign overall id/index of the thread
int idx = myblock * blocksize + subthread;
if(idx < 2000 || idx > 19000) {
// print buffer from within the kernel is limited so only print for first and last chunks of thread
if (idx < N){
printf("Hello World! My block index is (%d, %d) [Grid dims=(%d,%d)], 3D-thread index within blocks=(%d,%d,%d) => \
thread index=%d\n", blockIdx.x, blockIdx.y, gridDim.x, gridDim.y, threadIdx.x, threadIdx.y, threadIdx.z, idx);
} else {
printf("Hello world! My block index is (%d,%d) [Grid dims=(%d,%d)], 3D-thread index within block=(%d,%d,%d) => \
thread index=%d [### this thread would not be used for N=%d ###]\n", blockIdx.x, blockIdx.y, gridDim.x, gridDim.y,
threadIdx.x, threadIdx.y, threadIdx.z, idx, N);
}
}
}
int main(int argc, char **argv)
{
// objects containing the block and grid info
const dim3 blockSize(BLOCK_D1, BLOCK_D2, BLOCK_D3);
const dim3 gridSize(GRID_D1, GRID_D2, 1);
int nthreads = BLOCK_D1*BLOCK_D2*BLOCK_D3*GRID_D1*GRID_D2;
if (nthreads < N){
printf("\n================ NOT ENOUGH THREADS TO COVER N=%d ===================\n\n",N);
} else {
printf("Launching %d threads (N=%d)\n", nthreads, N);
}
// launch the kernel on the specified grid of thread blocks
hello<<<gridSize, blockSize>>>();
// Need to flush prints, otherwise none of the prints from within the kernel will show up
// as program exit does not flush the print buffer.
hipError_t cudaerr = hipDeviceSynchronize();
if (cudaerr) {
printf("kernel launch failed with error \"%s\".\n",
hipGetErrorString(cudaerr));
} else {
printf("kernel launch success!\n");
}
printf("That's all!\n");
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <stdio.h>
#include <hip/hip_runtime.h>
#define N 20000
#define GRID_D1 20
#define GRID_D2 2
#define BLOCK_D1 512
#define BLOCK_D2 1
#define BLOCK_D3 1
// this is the kernel function called for each thread
// we use the CUDA variables {threadIdx, blockIdx, blockDim, gridDim} to determine a unique ID for each thread
__global__ void hello(void)
{
// id of the block
int myblock = blockIdx.x + blockIdx.y * gridDim.x;
// size of each block (within grid of blocks)
int blocksize = blockDim.x * blockDim.y * blockDim.z;
// id of thread in a given block
int subthread = threadIdx.z*(blockDim.x * blockDim.y) + threadIdx.y*blockDim.x + threadIdx.x;
// assign overall id/index of the thread
int idx = myblock * blocksize + subthread;
if(idx < 2000 || idx > 19000) {
// print buffer from within the kernel is limited so only print for first and last chunks of thread
if (idx < N){
printf("Hello World! My block index is (%d, %d) [Grid dims=(%d,%d)], 3D-thread index within blocks=(%d,%d,%d) => \
thread index=%d\n", blockIdx.x, blockIdx.y, gridDim.x, gridDim.y, threadIdx.x, threadIdx.y, threadIdx.z, idx);
} else {
printf("Hello world! My block index is (%d,%d) [Grid dims=(%d,%d)], 3D-thread index within block=(%d,%d,%d) => \
thread index=%d [### this thread would not be used for N=%d ###]\n", blockIdx.x, blockIdx.y, gridDim.x, gridDim.y,
threadIdx.x, threadIdx.y, threadIdx.z, idx, N);
}
}
}
int main(int argc, char **argv)
{
// objects containing the block and grid info
const dim3 blockSize(BLOCK_D1, BLOCK_D2, BLOCK_D3);
const dim3 gridSize(GRID_D1, GRID_D2, 1);
int nthreads = BLOCK_D1*BLOCK_D2*BLOCK_D3*GRID_D1*GRID_D2;
if (nthreads < N){
printf("\n================ NOT ENOUGH THREADS TO COVER N=%d ===================\n\n",N);
} else {
printf("Launching %d threads (N=%d)\n", nthreads, N);
}
// launch the kernel on the specified grid of thread blocks
hello<<<gridSize, blockSize>>>();
// Need to flush prints, otherwise none of the prints from within the kernel will show up
// as program exit does not flush the print buffer.
hipError_t cudaerr = hipDeviceSynchronize();
if (cudaerr) {
printf("kernel launch failed with error \"%s\".\n",
hipGetErrorString(cudaerr));
} else {
printf("kernel launch success!\n");
}
printf("That's all!\n");
return 0;
} | .text
.file "helloWorld.hip"
.globl _Z20__device_stub__hellov # -- Begin function _Z20__device_stub__hellov
.p2align 4, 0x90
.type _Z20__device_stub__hellov,@function
_Z20__device_stub__hellov: # @_Z20__device_stub__hellov
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z5hellov, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z20__device_stub__hellov, .Lfunc_end0-_Z20__device_stub__hellov
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
movl $.L.str.1, %edi
movl $20480, %esi # imm = 0x5000
movl $20000, %edx # imm = 0x4E20
xorl %eax, %eax
callq printf
movabsq $8589934612, %rdi # imm = 0x200000014
movabsq $4294967808, %rdx # imm = 0x100000200
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z5hellov, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
callq hipDeviceSynchronize
testl %eax, %eax
je .LBB1_4
# %bb.3:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
jmp .LBB1_5
.LBB1_4:
movl $.Lstr, %edi
callq puts@PLT
.LBB1_5:
movl $.Lstr.1, %edi
callq puts@PLT
xorl %eax, %eax
addq $56, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z5hellov, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z5hellov,@object # @_Z5hellov
.section .rodata,"a",@progbits
.globl _Z5hellov
.p2align 3, 0x0
_Z5hellov:
.quad _Z20__device_stub__hellov
.size _Z5hellov, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "Launching %d threads (N=%d)\n"
.size .L.str.1, 29
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "kernel launch failed with error \"%s\".\n"
.size .L.str.2, 39
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z5hellov"
.size .L__unnamed_1, 10
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "kernel launch success!"
.size .Lstr, 23
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "That's all!"
.size .Lstr.1, 12
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z20__device_stub__hellov
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z5hellov
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000ea869_00000000-6_helloWorld.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z23__device_stub__Z5hellovv
.type _Z23__device_stub__Z5hellovv, @function
_Z23__device_stub__Z5hellovv:
.LFB2082:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z5hellov(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z23__device_stub__Z5hellovv, .-_Z23__device_stub__Z5hellovv
.globl _Z5hellov
.type _Z5hellov, @function
_Z5hellov:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z23__device_stub__Z5hellovv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z5hellov, .-_Z5hellov
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Launching %d threads (N=%d)\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "kernel launch failed with error \"%s\".\n"
.section .rodata.str1.1
.LC2:
.string "kernel launch success!\n"
.LC3:
.string "That's all!\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movl $512, 8(%rsp)
movl $1, 12(%rsp)
movl $1, 16(%rsp)
movl $20, 20(%rsp)
movl $2, 24(%rsp)
movl $1, 28(%rsp)
movl $20000, %ecx
movl $20480, %edx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 16(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 8(%rsp), %rdx
movq 20(%rsp), %rdi
movl 28(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L16
.L12:
call cudaDeviceSynchronize@PLT
testl %eax, %eax
je .L13
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L14:
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L16:
.cfi_restore_state
call _Z23__device_stub__Z5hellovv
jmp .L12
.L13:
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L14
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC4:
.string "_Z5hellov"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z5hellov(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "helloWorld.hip"
.globl _Z20__device_stub__hellov # -- Begin function _Z20__device_stub__hellov
.p2align 4, 0x90
.type _Z20__device_stub__hellov,@function
_Z20__device_stub__hellov: # @_Z20__device_stub__hellov
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z5hellov, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z20__device_stub__hellov, .Lfunc_end0-_Z20__device_stub__hellov
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
movl $.L.str.1, %edi
movl $20480, %esi # imm = 0x5000
movl $20000, %edx # imm = 0x4E20
xorl %eax, %eax
callq printf
movabsq $8589934612, %rdi # imm = 0x200000014
movabsq $4294967808, %rdx # imm = 0x100000200
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z5hellov, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
callq hipDeviceSynchronize
testl %eax, %eax
je .LBB1_4
# %bb.3:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
jmp .LBB1_5
.LBB1_4:
movl $.Lstr, %edi
callq puts@PLT
.LBB1_5:
movl $.Lstr.1, %edi
callq puts@PLT
xorl %eax, %eax
addq $56, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z5hellov, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z5hellov,@object # @_Z5hellov
.section .rodata,"a",@progbits
.globl _Z5hellov
.p2align 3, 0x0
_Z5hellov:
.quad _Z20__device_stub__hellov
.size _Z5hellov, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "Launching %d threads (N=%d)\n"
.size .L.str.1, 29
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "kernel launch failed with error \"%s\".\n"
.size .L.str.2, 39
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z5hellov"
.size .L__unnamed_1, 10
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "kernel launch success!"
.size .Lstr, 23
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "That's all!"
.size .Lstr.1, 12
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z20__device_stub__hellov
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z5hellov
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <stdlib.h>
#include <cuda.h>
__global__
void MyKernel()
{
printf("threadId[%u]=Hello World\n",threadIdx.x);
return;
}
int main()
{
MyKernel<<<1,1>>>();
printf("****Kernel launched****\n\n");
cudaDeviceSynchronize();
printf("\n****Kernel finished****\n");
return 0;
} | code for sm_80
Function : _Z8MyKernelv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fc800078e00ff */
/*0010*/ S2R R8, SR_TID.X ; /* 0x0000000000087919 */
/* 0x000e220000002100 */
/*0020*/ IADD3 R1, R1, -0x8, RZ ; /* 0xfffffff801017810 */
/* 0x000fe20007ffe0ff */
/*0030*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x8] ; /* 0x01000200ff047624 */
/* 0x000fe200078e00ff */
/*0040*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe20000000f00 */
/*0050*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0xc] ; /* 0x01000300ff057624 */
/* 0x000fe200078e00ff */
/*0060*/ IADD3 R6, P0, R1, c[0x0][0x20], RZ ; /* 0x0000080001067a10 */
/* 0x000fe40007f1e0ff */
/*0070*/ LDC.64 R2, c[0x4][R0] ; /* 0x0100000000027b82 */
/* 0x0002a60000000a00 */
/*0080*/ IMAD.X R7, RZ, RZ, c[0x0][0x24], P0 ; /* 0x00000900ff077624 */
/* 0x000fe200000e06ff */
/*0090*/ STL [R1], R8 ; /* 0x0000000801007387 */
/* 0x0013e80000100800 */
/*00a0*/ LEPC R8 ; /* 0x000000000008734e */
/* 0x002fc60000000000 */
/*00b0*/ MOV R11, 0x120 ; /* 0x00000120000b7802 */
/* 0x000fe40000000f00 */
/*00c0*/ MOV R20, 0xa0 ; /* 0x000000a000147802 */
/* 0x000fc40000000f00 */
/*00d0*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*00e0*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe40000000f00 */
/*00f0*/ IADD3 R20, P0, P1, -R20, R11, R8 ; /* 0x0000000b14147210 */
/* 0x000fc8000791e108 */
/*0100*/ IADD3.X R21, ~R0, R21, R9, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2509 */
/*0110*/ CALL.ABS.NOINC R2 ; /* 0x0000000002007343 */
/* 0x004fea0003c00000 */
/*0120*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0130*/ BRA 0x130; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <stdlib.h>
#include <cuda.h>
__global__
void MyKernel()
{
printf("threadId[%u]=Hello World\n",threadIdx.x);
return;
}
int main()
{
MyKernel<<<1,1>>>();
printf("****Kernel launched****\n\n");
cudaDeviceSynchronize();
printf("\n****Kernel finished****\n");
return 0;
} | .file "tmpxft_000ab73c_00000000-6_hello_world.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z26__device_stub__Z8MyKernelvv
.type _Z26__device_stub__Z8MyKernelvv, @function
_Z26__device_stub__Z8MyKernelvv:
.LFB2082:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z8MyKernelv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z26__device_stub__Z8MyKernelvv, .-_Z26__device_stub__Z8MyKernelvv
.globl _Z8MyKernelv
.type _Z8MyKernelv, @function
_Z8MyKernelv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z8MyKernelvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z8MyKernelv, .-_Z8MyKernelv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "****Kernel launched****\n\n"
.LC1:
.string "\n****Kernel finished****\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L12:
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
call cudaDeviceSynchronize@PLT
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
call _Z26__device_stub__Z8MyKernelvv
jmp .L12
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC2:
.string "_Z8MyKernelv"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z8MyKernelv(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <stdlib.h>
#include <cuda.h>
__global__
void MyKernel()
{
printf("threadId[%u]=Hello World\n",threadIdx.x);
return;
}
int main()
{
MyKernel<<<1,1>>>();
printf("****Kernel launched****\n\n");
cudaDeviceSynchronize();
printf("\n****Kernel finished****\n");
return 0;
} | #include <stdio.h>
#include <stdlib.h>
#include <hip/hip_runtime.h>
__global__
void MyKernel()
{
printf("threadId[%u]=Hello World\n",threadIdx.x);
return;
}
int main()
{
MyKernel<<<1,1>>>();
printf("****Kernel launched****\n\n");
hipDeviceSynchronize();
printf("\n****Kernel finished****\n");
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <stdio.h>
#include <stdlib.h>
#include <hip/hip_runtime.h>
__global__
void MyKernel()
{
printf("threadId[%u]=Hello World\n",threadIdx.x);
return;
}
int main()
{
MyKernel<<<1,1>>>();
printf("****Kernel launched****\n\n");
hipDeviceSynchronize();
printf("\n****Kernel finished****\n");
return 0;
} | .text
.file "hello_world.hip"
.globl _Z23__device_stub__MyKernelv # -- Begin function _Z23__device_stub__MyKernelv
.p2align 4, 0x90
.type _Z23__device_stub__MyKernelv,@function
_Z23__device_stub__MyKernelv: # @_Z23__device_stub__MyKernelv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z8MyKernelv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z23__device_stub__MyKernelv, .Lfunc_end0-_Z23__device_stub__MyKernelv
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z8MyKernelv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
movl $.Lstr, %edi
callq puts@PLT
callq hipDeviceSynchronize
movl $.Lstr.1, %edi
callq puts@PLT
xorl %eax, %eax
addq $56, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8MyKernelv, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z8MyKernelv,@object # @_Z8MyKernelv
.section .rodata,"a",@progbits
.globl _Z8MyKernelv
.p2align 3, 0x0
_Z8MyKernelv:
.quad _Z23__device_stub__MyKernelv
.size _Z8MyKernelv, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z8MyKernelv"
.size .L__unnamed_1, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "****Kernel launched****\n"
.size .Lstr, 25
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "\n****Kernel finished****"
.size .Lstr.1, 25
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__MyKernelv
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8MyKernelv
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000ab73c_00000000-6_hello_world.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z26__device_stub__Z8MyKernelvv
.type _Z26__device_stub__Z8MyKernelvv, @function
_Z26__device_stub__Z8MyKernelvv:
.LFB2082:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z8MyKernelv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z26__device_stub__Z8MyKernelvv, .-_Z26__device_stub__Z8MyKernelvv
.globl _Z8MyKernelv
.type _Z8MyKernelv, @function
_Z8MyKernelv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z8MyKernelvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z8MyKernelv, .-_Z8MyKernelv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "****Kernel launched****\n\n"
.LC1:
.string "\n****Kernel finished****\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L12:
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
call cudaDeviceSynchronize@PLT
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
call _Z26__device_stub__Z8MyKernelvv
jmp .L12
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC2:
.string "_Z8MyKernelv"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z8MyKernelv(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "hello_world.hip"
.globl _Z23__device_stub__MyKernelv # -- Begin function _Z23__device_stub__MyKernelv
.p2align 4, 0x90
.type _Z23__device_stub__MyKernelv,@function
_Z23__device_stub__MyKernelv: # @_Z23__device_stub__MyKernelv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z8MyKernelv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z23__device_stub__MyKernelv, .Lfunc_end0-_Z23__device_stub__MyKernelv
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z8MyKernelv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
movl $.Lstr, %edi
callq puts@PLT
callq hipDeviceSynchronize
movl $.Lstr.1, %edi
callq puts@PLT
xorl %eax, %eax
addq $56, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8MyKernelv, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z8MyKernelv,@object # @_Z8MyKernelv
.section .rodata,"a",@progbits
.globl _Z8MyKernelv
.p2align 3, 0x0
_Z8MyKernelv:
.quad _Z23__device_stub__MyKernelv
.size _Z8MyKernelv, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z8MyKernelv"
.size .L__unnamed_1, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "****Kernel launched****\n"
.size .Lstr, 25
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "\n****Kernel finished****"
.size .Lstr.1, 25
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__MyKernelv
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8MyKernelv
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <iostream>
#include <chrono>
using namespace std;
//CPU
typedef unsigned int uint;
uint i = 0;
int gpuCount = 0;
void initalizeHost( float *ip, uint size );
//GPU
cudaDeviceProp gpuProperties;
const uint N = 1E7;
const uint nThreads = 512;
const uint nBlocks = ( N / nThreads ) + 1;
const uint UNROLLING = 16; //check [ 8 16 32 64 ]; I would guess sixteen times unrolling;
__global__ void nop(){};
__global__ void trivialLoop()
{
uint a = 0;
for ( uint32_t i = 0; i < N; i++ )
{
a = i;
a++;
}
};
__global__ void unrollTrivialLoop()
{
uint a = 0;
#pragma unroll UNROLLING //briliant feature
for ( uint32_t i = 0; i < N; i++ )
{
a = i;
a++;
}
};
__global__ void initializeDevice( float *d_in, const uint streamSize )
{
uint tid = threadIdx.x;
uint idx = blockIdx.x * blockDim.x + tid;
if( idx < streamSize )
{
d_in[ idx ] *= 0.9f;
}
};
__global__ void loop( float *d_in, const uint streamNo, const uint streamSize )
{
size_t ii = 0;
for ( ii = 0; ii < streamSize; ii++ )
{
d_in[ ii ] += float( ii );
}
};
__global__ void unrollLoop( float *d_in, const uint streamNo, const uint streamSize )
{
size_t ii = 0;
#pragma unroll UNROLLING //adjustable mainly to register-only, high performance computations - described at unrollTrivialLoop device kernel
for ( ii = 0; ii < streamSize; ii++ )
{
d_in[ ii ] += float( ii );
}
};
int main( void )
{
cudaGetDeviceCount( &gpuCount );
//HOST
float *h_arr[ gpuCount ]; // float **h_arr = ( float** )malloc( sizeof( float * ) * gpuCount ); //alternatively
uint perDevN = N / gpuCount;
uint perDevNBytes = sizeof( float ) * perDevN ;
//DEVICE
cudaStream_t stream[ gpuCount ];
float *d_arr[ gpuCount ]; // float **d_arr = ( float** )malloc( sizeof( float * ) * gpuCount ); //alternatively
//alocate & initialize H,D memories
for ( i = 0; i < gpuCount; i++ )
{
//HOST
cudaMallocHost( ( void** ) &h_arr[ i ], perDevNBytes );
initalizeHost( h_arr[ i ], perDevN );
//DEVICE
cudaSetDevice( i );
cudaMalloc( ( void** ) &d_arr[ i ], perDevNBytes );
cudaStreamCreate( &stream[ i ] );
}
//DEVICE computations
for ( i = 0; i < gpuCount; i++ )
{
cudaSetDevice( i );
cudaGetDeviceProperties( &gpuProperties, i );
cout << endl << gpuProperties.name << ": " << endl;
auto t1 = chrono::high_resolution_clock::now();
trivialLoop<<< 1, 1 >>>();
nop<<< 1, 1 >>>();
auto t2 = chrono::high_resolution_clock::now();
uint elapsed = uint( chrono::duration_cast< chrono::nanoseconds >( t2 - t1 ).count() );
printf( "trivial loop elapsed: %d \n", elapsed );
t1 = chrono::high_resolution_clock::now();
unrollTrivialLoop<<< 1, 1 >>>();
nop<<< 1, 1 >>>();
t2 = chrono::high_resolution_clock::now();
elapsed = chrono::duration_cast< chrono::nanoseconds >( t2 - t1 ).count();
printf( "trivial unrolled loop elapsed: %d \n", elapsed );
cudaMemcpyAsync( d_arr[ i ], h_arr[ i ], perDevNBytes, cudaMemcpyHostToDevice, stream[ i ] );
initializeDevice<<< nBlocks, nThreads, 0, stream[ i ] >>>( d_arr[ i ], perDevN );
nop<<< 1, 1 >>>();
t1 = chrono::high_resolution_clock::now();
loop<<< 1, 1, 0, stream[ i ] >>>( d_arr[ i ], i, perDevN );
nop<<< 1, 1 >>>();
t2 = chrono::high_resolution_clock::now();
elapsed = chrono::duration_cast< chrono::nanoseconds >( t2 - t1 ).count();
printf( "loop elapsed: %d \n", elapsed );
t1 = chrono::high_resolution_clock::now();
unrollLoop<<< 1, 1, 0, stream[ i ] >>>( d_arr[ i ], i, perDevN );
nop<<< 1, 1 >>>();
t2 = chrono::high_resolution_clock::now();
elapsed = chrono::duration_cast< chrono::nanoseconds >( t2 - t1 ).count();
printf( "unrolled loop elapsed: %d \n", elapsed );
}
//free memories
for ( i = 0; i < gpuCount; i++ )
{
//HOST
cudaFreeHost( h_arr[ i ] );
//DEVICE
cudaSetDevice( i );
cudaFree( d_arr[ i ] );
cudaStreamDestroy( stream[ i ] );
}
cudaDeviceReset();
return 0;
}
void initalizeHost( float *ip, uint size )
{
for ( size_t i = 0; i < size; i++ )
ip[ i ] = 1.2f;
};
//Post Scriptum: In my professional opinion, coprocessors: GTX1080ti is brand-new and off-the-shell optimal; GTX770 is used optimal - I've heard about R9Nano and HD5770 ( GFLOPS/USD; GFLOPS/W; QualityWithBandwidthAndMemSize/Price; );
//Post Post Scriptum: I do strongly recommend profiling with NVidia's NVPROF profiling tool, instead of CPU high-resolution timer. | code for sm_80
Function : _Z10unrollLoopPfjj
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ ISETP.NE.U32.AND P0, PT, RZ, c[0x0][0x16c], PT ; /* 0x00005b00ff007a0c */
/* 0x000fc80003f05070 */
/*0020*/ ISETP.NE.AND.EX P0, PT, RZ, RZ, PT, P0 ; /* 0x000000ffff00720c */
/* 0x000fda0003f05300 */
/*0030*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0040*/ HFMA2.MMA R0, -RZ, RZ, 0, 5.9604644775390625e-08 ; /* 0x00000001ff007435 */
/* 0x000fe200000001ff */
/*0050*/ UMOV UR8, 0xf ; /* 0x0000000f00087882 */
/* 0x000fe40000000000 */
/*0060*/ ULDC UR4, c[0x0][0x16c] ; /* 0x00005b0000047ab9 */
/* 0x000fe40000000800 */
/*0070*/ ULOP3.LUT UR8, UR8, UR4, URZ, 0xc0, !UPT ; /* 0x0000000408087292 */
/* 0x000fe4000f8ec03f */
/*0080*/ UMOV UR5, URZ ; /* 0x0000003f00057c82 */
/* 0x000fe40008000000 */
/*0090*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*00a0*/ IADD3 R0, P0, -R0, c[0x0][0x16c], RZ ; /* 0x00005b0000007a10 */
/* 0x000fe20007f1e1ff */
/*00b0*/ ULDC.64 UR12, c[0x0][0x118] ; /* 0x00004600000c7ab9 */
/* 0x000fc60000000a00 */
/*00c0*/ ISETP.GE.U32.AND P1, PT, R0, 0xf, PT ; /* 0x0000000f0000780c */
/* 0x000fe20003f26070 */
/*00d0*/ IMAD.X R0, RZ, RZ, -0x1, P0 ; /* 0xffffffffff007424 */
/* 0x000fe200000e06ff */
/*00e0*/ ISETP.NE.U32.AND P0, PT, RZ, UR8, PT ; /* 0x00000008ff007c0c */
/* 0x000fc8000bf05070 */
/*00f0*/ ISETP.GE.U32.AND.EX P1, PT, R0, RZ, PT, P1 ; /* 0x000000ff0000720c */
/* 0x000fe40003f26110 */
/*0100*/ ISETP.NE.AND.EX P0, PT, RZ, RZ, PT, P0 ; /* 0x000000ffff00720c */
/* 0x000fd60003f05300 */
/*0110*/ @!P1 BRA 0x820 ; /* 0x0000070000009947 */
/* 0x000fea0003800000 */
/*0120*/ ULDC UR6, c[0x0][0x16c] ; /* 0x00005b0000067ab9 */
/* 0x000fe20000000800 */
/*0130*/ MOV R0, c[0x0][0x160] ; /* 0x0000580000007a02 */
/* 0x000fe20000000f00 */
/*0140*/ UIADD3 UR6, UP0, UR8, -UR6, URZ ; /* 0x8000000608067290 */
/* 0x000fe2000ff1e03f */
/*0150*/ IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff077624 */
/* 0x000fe200078e00ff */
/*0160*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe40008000000 */
/*0170*/ UIADD3.X UR10, URZ, -0x1, URZ, UP0, !UPT ; /* 0xffffffff3f0a7890 */
/* 0x000fe400087fe43f */
/*0180*/ UMOV UR5, URZ ; /* 0x0000003f00057c82 */
/* 0x000fe40008000000 */
/*0190*/ MOV R2, R0 ; /* 0x0000000000027202 */
/* 0x002fe40000000f00 */
/*01a0*/ MOV R3, R7 ; /* 0x0000000700037202 */
/* 0x000fca0000000f00 */
/*01b0*/ LDG.E R11, [R2.64] ; /* 0x0000000c020b7981 */
/* 0x000ea8000c1e1900 */
/*01c0*/ LDG.E R25, [R2.64+0x8] ; /* 0x0000080c02197981 */
/* 0x000ee8000c1e1900 */
/*01d0*/ LDG.E R29, [R2.64+0x4] ; /* 0x0000040c021d7981 */
/* 0x000f28000c1e1900 */
/*01e0*/ LDG.E R22, [R2.64+0xc] ; /* 0x00000c0c02167981 */
/* 0x000f68000c1e1900 */
/*01f0*/ LDG.E R17, [R2.64+0x14] ; /* 0x0000140c02117981 */
/* 0x000f28000c1e1900 */
/*0200*/ LDG.E R21, [R2.64+0x10] ; /* 0x0000100c02157981 */
/* 0x000f28000c1e1900 */
/*0210*/ LDG.E R18, [R2.64+0x18] ; /* 0x0000180c02127981 */
/* 0x000f28000c1e1900 */
/*0220*/ LDG.E R16, [R2.64+0x1c] ; /* 0x00001c0c02107981 */
/* 0x000f68000c1e1900 */
/*0230*/ LDG.E R7, [R2.64+0x20] ; /* 0x0000200c02077981 */
/* 0x000f68000c1e1900 */
/*0240*/ LDG.E R10, [R2.64+0x24] ; /* 0x0000240c020a7981 */
/* 0x000f68000c1e1900 */
/*0250*/ LDG.E R9, [R2.64+0x28] ; /* 0x0000280c02097981 */
/* 0x000f68000c1e1900 */
/*0260*/ LDG.E R8, [R2.64+0x2c] ; /* 0x00002c0c02087981 */
/* 0x000f68000c1e1900 */
/*0270*/ LDG.E R6, [R2.64+0x30] ; /* 0x0000300c02067981 */
/* 0x000f68000c1e1900 */
/*0280*/ LDG.E R0, [R2.64+0x34] ; /* 0x0000340c02007981 */
/* 0x000f68000c1e1900 */
/*0290*/ LDG.E R5, [R2.64+0x38] ; /* 0x0000380c02057981 */
/* 0x000f68000c1e1900 */
/*02a0*/ LDG.E R4, [R2.64+0x3c] ; /* 0x00003c0c02047981 */
/* 0x000f62000c1e1900 */
/*02b0*/ UIADD3 UR14, UP0, UR4, 0x1, URZ ; /* 0x00000001040e7890 */
/* 0x000fc8000ff1e03f */
/*02c0*/ UIADD3.X UR15, URZ, UR5, URZ, UP0, !UPT ; /* 0x000000053f0f7290 */
/* 0x000fe400087fe43f */
/*02d0*/ UIADD3 UR16, UP0, UR4, 0x2, URZ ; /* 0x0000000204107890 */
/* 0x000fc8000ff1e03f */
/*02e0*/ UIADD3.X UR17, URZ, UR5, URZ, UP0, !UPT ; /* 0x000000053f117290 */
/* 0x000fc600087fe43f */
/*02f0*/ I2F.U64 R28, UR14 ; /* 0x0000000e001c7d12 */
/* 0x000fe20008301000 */
/*0300*/ UIADD3 UR14, UP0, UR4, 0x3, URZ ; /* 0x00000003040e7890 */
/* 0x000fc8000ff1e03f */
/*0310*/ UIADD3.X UR15, URZ, UR5, URZ, UP0, !UPT ; /* 0x000000053f0f7290 */
/* 0x000fc600087fe43f */
/*0320*/ I2F.U64 R26, UR16 ; /* 0x00000010001a7d12 */
/* 0x000fe20008301000 */
/*0330*/ UIADD3 UR16, UP0, UR4, 0x4, URZ ; /* 0x0000000404107890 */
/* 0x000fc8000ff1e03f */
/*0340*/ UIADD3.X UR17, URZ, UR5, URZ, UP0, !UPT ; /* 0x000000053f117290 */
/* 0x000fc600087fe43f */
/*0350*/ I2F.U64 R23, UR14 ; /* 0x0000000e00177d12 */
/* 0x000fe20008301000 */
/*0360*/ UIADD3 UR14, UP0, UR4, 0x5, URZ ; /* 0x00000005040e7890 */
/* 0x000fc8000ff1e03f */
/*0370*/ UIADD3.X UR15, URZ, UR5, URZ, UP0, !UPT ; /* 0x000000053f0f7290 */
/* 0x000fc600087fe43f */
/*0380*/ I2F.U64 R24, UR16 ; /* 0x0000001000187d12 */
/* 0x000fe20008301000 */
/*0390*/ UIADD3 UR16, UP0, UR4, 0x6, URZ ; /* 0x0000000604107890 */
/* 0x000fc8000ff1e03f */
/*03a0*/ UIADD3.X UR17, URZ, UR5, URZ, UP0, !UPT ; /* 0x000000053f117290 */
/* 0x000fc600087fe43f */
/*03b0*/ I2F.U64 R20, UR14 ; /* 0x0000000e00147d12 */
/* 0x000fe20008301000 */
/*03c0*/ UIADD3 UR14, UP0, UR4, 0x7, URZ ; /* 0x00000007040e7890 */
/* 0x000fc8000ff1e03f */
/*03d0*/ UIADD3.X UR15, URZ, UR5, URZ, UP0, !UPT ; /* 0x000000053f0f7290 */
/* 0x000fc600087fe43f */
/*03e0*/ I2F.U64 R19, UR16 ; /* 0x0000001000137d12 */
/* 0x000fe20008301000 */
/*03f0*/ UIADD3 UR16, UP0, UR4, 0x8, URZ ; /* 0x0000000804107890 */
/* 0x000fc8000ff1e03f */
/*0400*/ UIADD3.X UR17, URZ, UR5, URZ, UP0, !UPT ; /* 0x000000053f117290 */
/* 0x000fc600087fe43f */
/*0410*/ I2F.U64 R15, UR14 ; /* 0x0000000e000f7d12 */
/* 0x000fe20008301000 */
/*0420*/ UIADD3 UR14, UP0, UR4, 0x9, URZ ; /* 0x00000009040e7890 */
/* 0x000fc8000ff1e03f */
/*0430*/ UIADD3.X UR15, URZ, UR5, URZ, UP0, !UPT ; /* 0x000000053f0f7290 */
/* 0x000fc600087fe43f */
/*0440*/ I2F.U64 R12, UR4 ; /* 0x00000004000c7d12 */
/* 0x000eb00008301000 */
/*0450*/ I2F.U64 R14, UR16 ; /* 0x00000010000e7d12 */
/* 0x000e220008301000 */
/*0460*/ UIADD3 UR16, UP0, UR4, 0xa, URZ ; /* 0x0000000a04107890 */
/* 0x000fc8000ff1e03f */
/*0470*/ UIADD3.X UR17, URZ, UR5, URZ, UP0, !UPT ; /* 0x000000053f117290 */
/* 0x000fc600087fe43f */
/*0480*/ I2F.U64 R13, UR14 ; /* 0x0000000e000d7d12 */
/* 0x000e620008301000 */
/*0490*/ UIADD3 UR14, UP0, UR4, 0xb, URZ ; /* 0x0000000b040e7890 */
/* 0x000fc8000ff1e03f */
/*04a0*/ UIADD3.X UR15, URZ, UR5, URZ, UP0, !UPT ; /* 0x000000053f0f7290 */
/* 0x000fe200087fe43f */
/*04b0*/ FADD R27, R11, R12 ; /* 0x0000000c0b1b7221 */
/* 0x004fe40000000000 */
/*04c0*/ I2F.U64 R12, UR16 ; /* 0x00000010000c7d12 */
/* 0x000ea20008301000 */
/*04d0*/ UIADD3 UR16, UP0, UR4, 0xc, URZ ; /* 0x0000000c04107890 */
/* 0x000fc8000ff1e03f */
/*04e0*/ UIADD3.X UR17, URZ, UR5, URZ, UP0, !UPT ; /* 0x000000053f117290 */
/* 0x000fc600087fe43f */
/*04f0*/ I2F.U64 R11, UR14 ; /* 0x0000000e000b7d12 */
/* 0x000e220008301000 */
/*0500*/ UIADD3 UR14, UP0, UR4, 0xd, URZ ; /* 0x0000000d040e7890 */
/* 0x000fe2000ff1e03f */
/*0510*/ FADD R26, R26, R25 ; /* 0x000000191a1a7221 */
/* 0x008fc60000000000 */
/*0520*/ UIADD3.X UR15, URZ, UR5, URZ, UP0, !UPT ; /* 0x000000053f0f7290 */
/* 0x000fc600087fe43f */
/*0530*/ I2F.U64 R25, UR16 ; /* 0x0000001000197d12 */
/* 0x000ee20008301000 */
/*0540*/ UIADD3 UR16, UP0, UR4, 0xe, URZ ; /* 0x0000000e04107890 */
/* 0x000fe2000ff1e03f */
/*0550*/ STG.E [R2.64], R27 ; /* 0x0000001b02007986 */
/* 0x0001e6000c10190c */
/*0560*/ UIADD3.X UR17, URZ, UR5, URZ, UP0, !UPT ; /* 0x000000053f117290 */
/* 0x000fe200087fe43f */
/*0570*/ FADD R29, R28, R29 ; /* 0x0000001d1c1d7221 */
/* 0x010fe40000000000 */
/*0580*/ I2F.U64 R27, UR14 ; /* 0x0000000e001b7d12 */
/* 0x001e220008301000 */
/*0590*/ UIADD3 UR14, UP0, UR4, 0xf, URZ ; /* 0x0000000f040e7890 */
/* 0x000fc8000ff1e03f */
/*05a0*/ UIADD3.X UR15, URZ, UR5, URZ, UP0, !UPT ; /* 0x000000053f0f7290 */
/* 0x000fe400087fe43f */
/*05b0*/ UIADD3 UR4, UP0, UR4, 0x10, URZ ; /* 0x0000001004047890 */
/* 0x000fe2000ff1e03f */
/*05c0*/ STG.E [R2.64+0x4], R29 ; /* 0x0000041d02007986 */
/* 0x0009e2000c10190c */
/*05d0*/ FADD R23, R23, R22 ; /* 0x0000001617177221 */
/* 0x020fe40000000000 */
/*05e0*/ UIADD3.X UR5, URZ, UR5, URZ, UP0, !UPT ; /* 0x000000053f057290 */
/* 0x000fe200087fe43f */
/*05f0*/ I2F.U64 R22, UR16 ; /* 0x0000001000167d12 */
/* 0x000f620008301000 */
/*0600*/ UIADD3 UR7, UP0, UR4, UR6, URZ ; /* 0x0000000604077290 */
/* 0x000fe2000ff1e03f */
/*0610*/ FADD R29, R20, R17 ; /* 0x00000011141d7221 */
/* 0x010fcc0000000000 */
/*0620*/ I2F.U64 R17, UR14 ; /* 0x0000000e00117d12 */
/* 0x000f220008301000 */
/*0630*/ UIADD3.X UR9, UR5, UR10, URZ, UP0, !UPT ; /* 0x0000000a05097290 */
/* 0x000fe200087fe43f */
/*0640*/ ISETP.NE.U32.AND P1, PT, RZ, UR7, PT ; /* 0x00000007ff007c0c */
/* 0x000fca000bf25070 */
/*0650*/ ISETP.NE.AND.EX P1, PT, RZ, UR9, PT, P1 ; /* 0x00000009ff007c0c */
/* 0x000fe2000bf25310 */
/*0660*/ FADD R21, R24, R21 ; /* 0x0000001518157221 */
/* 0x000fe40000000000 */
/*0670*/ FADD R19, R19, R18 ; /* 0x0000001213137221 */
/* 0x000fe40000000000 */
/*0680*/ FADD R15, R15, R16 ; /* 0x000000100f0f7221 */
/* 0x000fe40000000000 */
/*0690*/ FADD R7, R14, R7 ; /* 0x000000070e077221 */
/* 0x000fe40000000000 */
/*06a0*/ FADD R13, R13, R10 ; /* 0x0000000a0d0d7221 */
/* 0x002fe40000000000 */
/*06b0*/ FADD R9, R12, R9 ; /* 0x000000090c097221 */
/* 0x004fc40000000000 */
/*06c0*/ FADD R11, R11, R8 ; /* 0x000000080b0b7221 */
/* 0x000fe40000000000 */
/*06d0*/ FADD R25, R25, R6 ; /* 0x0000000619197221 */
/* 0x008fe40000000000 */
/*06e0*/ FADD R27, R27, R0 ; /* 0x000000001b1b7221 */
/* 0x001fe40000000000 */
/*06f0*/ FADD R5, R22, R5 ; /* 0x0000000516057221 */
/* 0x020fe40000000000 */
/*0700*/ FADD R17, R17, R4 ; /* 0x0000000411117221 */
/* 0x010fe20000000000 */
/*0710*/ IADD3 R0, P2, R2, 0x40, RZ ; /* 0x0000004002007810 */
/* 0x000fe20007f5e0ff */
/*0720*/ STG.E [R2.64+0x8], R26 ; /* 0x0000081a02007986 */
/* 0x000fe8000c10190c */
/*0730*/ STG.E [R2.64+0xc], R23 ; /* 0x00000c1702007986 */
/* 0x000fe8000c10190c */
/*0740*/ STG.E [R2.64+0x10], R21 ; /* 0x0000101502007986 */
/* 0x000fe8000c10190c */
/*0750*/ STG.E [R2.64+0x14], R29 ; /* 0x0000141d02007986 */
/* 0x000fe8000c10190c */
/*0760*/ STG.E [R2.64+0x18], R19 ; /* 0x0000181302007986 */
/* 0x000fe8000c10190c */
/*0770*/ STG.E [R2.64+0x1c], R15 ; /* 0x00001c0f02007986 */
/* 0x000fe8000c10190c */
/*0780*/ STG.E [R2.64+0x20], R7 ; /* 0x0000200702007986 */
/* 0x0001e8000c10190c */
/*0790*/ STG.E [R2.64+0x24], R13 ; /* 0x0000240d02007986 */
/* 0x0003e8000c10190c */
/*07a0*/ STG.E [R2.64+0x28], R9 ; /* 0x0000280902007986 */
/* 0x0003e8000c10190c */
/*07b0*/ STG.E [R2.64+0x2c], R11 ; /* 0x00002c0b02007986 */
/* 0x0003e2000c10190c */
/*07c0*/ IMAD.X R7, RZ, RZ, R3, P2 ; /* 0x000000ffff077224 */
/* 0x001fc600010e0603 */
/*07d0*/ STG.E [R2.64+0x30], R25 ; /* 0x0000301902007986 */
/* 0x0003e8000c10190c */
/*07e0*/ STG.E [R2.64+0x34], R27 ; /* 0x0000341b02007986 */
/* 0x0003e8000c10190c */
/*07f0*/ STG.E [R2.64+0x38], R5 ; /* 0x0000380502007986 */
/* 0x0003e8000c10190c */
/*0800*/ STG.E [R2.64+0x3c], R17 ; /* 0x00003c1102007986 */
/* 0x0003e2000c10190c */
/*0810*/ @P1 BRA 0x190 ; /* 0xfffff97000001947 */
/* 0x000fea000383ffff */
/*0820*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0830*/ ULDC.64 UR10, c[0x0][0x160] ; /* 0x00005800000a7ab9 */
/* 0x000fe40000000a00 */
/*0840*/ ULEA UR7, UP0, UR4, UR10, 0x2 ; /* 0x0000000a04077291 */
/* 0x000fc4000f80103f */
/*0850*/ UIADD3 UR6, UP1, URZ, -UR8, URZ ; /* 0x800000083f067290 */
/* 0x000fe4000ff3e03f */
/*0860*/ ULEA.HI.X UR8, UR4, UR11, UR5, 0x2, UP0 ; /* 0x0000000b04087291 */
/* 0x000fe400080f1405 */
/*0870*/ MOV R0, UR7 ; /* 0x0000000700007c02 */
/* 0x000fe20008000f00 */
/*0880*/ UIADD3.X UR9, URZ, -0x1, URZ, UP1, !UPT ; /* 0xffffffff3f097890 */
/* 0x000fc60008ffe43f */
/*0890*/ MOV R7, UR8 ; /* 0x0000000800077c02 */
/* 0x000fc60008000f00 */
/*08a0*/ IMAD.MOV.U32 R2, RZ, RZ, R0 ; /* 0x000000ffff027224 */
/* 0x003fe200078e0000 */
/*08b0*/ MOV R3, R7 ; /* 0x0000000700037202 */
/* 0x000fca0000000f00 */
/*08c0*/ LDG.E R0, [R2.64] ; /* 0x0000000c02007981 */
/* 0x000ea2000c1e1900 */
/*08d0*/ UIADD3 UR6, UP0, UR6, 0x1, URZ ; /* 0x0000000106067890 */
/* 0x000fe2000ff1e03f */
/*08e0*/ I2F.U64 R5, UR4 ; /* 0x0000000400057d12 */
/* 0x000ea60008301000 */
/*08f0*/ UIADD3.X UR9, URZ, UR9, URZ, UP0, !UPT ; /* 0x000000093f097290 */
/* 0x000fe400087fe43f */
/*0900*/ ISETP.NE.U32.AND P0, PT, RZ, UR6, PT ; /* 0x00000006ff007c0c */
/* 0x000fe2000bf05070 */
/*0910*/ UIADD3 UR4, UP0, UR4, 0x1, URZ ; /* 0x0000000104047890 */
/* 0x000fc6000ff1e03f */
/*0920*/ ISETP.NE.AND.EX P0, PT, RZ, UR9, PT, P0 ; /* 0x00000009ff007c0c */
/* 0x000fe2000bf05300 */
/*0930*/ UIADD3.X UR5, URZ, UR5, URZ, UP0, !UPT ; /* 0x000000053f057290 */
/* 0x000fe200087fe43f */
/*0940*/ FADD R5, R5, R0 ; /* 0x0000000005057221 */
/* 0x004fe20000000000 */
/*0950*/ IADD3 R0, P1, R2, 0x4, RZ ; /* 0x0000000402007810 */
/* 0x000fc80007f3e0ff */
/*0960*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x0001e2000c10190c */
/*0970*/ IADD3.X R7, RZ, R3, RZ, P1, !PT ; /* 0x00000003ff077210 */
/* 0x000fca0000ffe4ff */
/*0980*/ @P0 BRA 0x8a0 ; /* 0xffffff1000000947 */
/* 0x000fea000383ffff */
/*0990*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*09a0*/ BRA 0x9a0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*09b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z4loopPfjj
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ ISETP.NE.U32.AND P0, PT, RZ, c[0x0][0x16c], PT ; /* 0x00005b00ff007a0c */
/* 0x000fc80003f05070 */
/*0020*/ ISETP.NE.AND.EX P0, PT, RZ, RZ, PT, P0 ; /* 0x000000ffff00720c */
/* 0x000fda0003f05300 */
/*0030*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0040*/ IMAD.MOV.U32 R0, RZ, RZ, 0x1 ; /* 0x00000001ff007424 */
/* 0x000fe200078e00ff */
/*0050*/ UMOV UR8, 0x3 ; /* 0x0000000300087882 */
/* 0x000fe40000000000 */
/*0060*/ ULDC UR4, c[0x0][0x16c] ; /* 0x00005b0000047ab9 */
/* 0x000fe40000000800 */
/*0070*/ IADD3 R0, P0, -R0, c[0x0][0x16c], RZ ; /* 0x00005b0000007a10 */
/* 0x000fe20007f1e1ff */
/*0080*/ ULOP3.LUT UR8, UR8, UR4, URZ, 0xc0, !UPT ; /* 0x0000000408087292 */
/* 0x000fe4000f8ec03f */
/*0090*/ UMOV UR5, URZ ; /* 0x0000003f00057c82 */
/* 0x000fe20008000000 */
/*00a0*/ ISETP.GE.U32.AND P1, PT, R0, 0x3, PT ; /* 0x000000030000780c */
/* 0x000fe20003f26070 */
/*00b0*/ IMAD.X R0, RZ, RZ, -0x1, P0 ; /* 0xffffffffff007424 */
/* 0x000fe200000e06ff */
/*00c0*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*00d0*/ ISETP.NE.U32.AND P0, PT, RZ, UR8, PT ; /* 0x00000008ff007c0c */
/* 0x000fe2000bf05070 */
/*00e0*/ ULDC.64 UR12, c[0x0][0x118] ; /* 0x00004600000c7ab9 */
/* 0x000fc40000000a00 */
/*00f0*/ ISETP.GE.U32.AND.EX P1, PT, R0, RZ, PT, P1 ; /* 0x000000ff0000720c */
/* 0x000fe40003f26110 */
/*0100*/ ISETP.NE.AND.EX P0, PT, RZ, RZ, PT, P0 ; /* 0x000000ffff00720c */
/* 0x000fd60003f05300 */
/*0110*/ @!P1 BRA 0x3a0 ; /* 0x0000028000009947 */
/* 0x000fea0003800000 */
/*0120*/ ULDC UR6, c[0x0][0x16c] ; /* 0x00005b0000067ab9 */
/* 0x000fe20000000800 */
/*0130*/ MOV R0, c[0x0][0x160] ; /* 0x0000580000007a02 */
/* 0x000fe20000000f00 */
/*0140*/ UIADD3 UR6, UP0, UR8, -UR6, URZ ; /* 0x8000000608067290 */
/* 0x000fe2000ff1e03f */
/*0150*/ IMAD.MOV.U32 R13, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff0d7624 */
/* 0x000fe200078e00ff */
/*0160*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe40008000000 */
/*0170*/ UIADD3.X UR10, URZ, -0x1, URZ, UP0, !UPT ; /* 0xffffffff3f0a7890 */
/* 0x000fe400087fe43f */
/*0180*/ UMOV UR5, URZ ; /* 0x0000003f00057c82 */
/* 0x000fe40008000000 */
/*0190*/ IMAD.MOV.U32 R2, RZ, RZ, R0 ; /* 0x000000ffff027224 */
/* 0x001fe200078e0000 */
/*01a0*/ MOV R3, R13 ; /* 0x0000000d00037202 */
/* 0x000fca0000000f00 */
/*01b0*/ LDG.E R0, [R2.64] ; /* 0x0000000c02007981 */
/* 0x000ea8000c1e1900 */
/*01c0*/ LDG.E R7, [R2.64+0x4] ; /* 0x0000040c02077981 */
/* 0x000ee8000c1e1900 */
/*01d0*/ LDG.E R9, [R2.64+0x8] ; /* 0x0000080c02097981 */
/* 0x000f28000c1e1900 */
/*01e0*/ LDG.E R11, [R2.64+0xc] ; /* 0x00000c0c020b7981 */
/* 0x000f62000c1e1900 */
/*01f0*/ UIADD3 UR14, UP0, UR4, 0x1, URZ ; /* 0x00000001040e7890 */
/* 0x000fe2000ff1e03f */
/*0200*/ I2F.U64 R5, UR4 ; /* 0x0000000400057d12 */
/* 0x000ea60008301000 */
/*0210*/ UIADD3.X UR15, URZ, UR5, URZ, UP0, !UPT ; /* 0x000000053f0f7290 */
/* 0x000fc400087fe43f */
/*0220*/ UIADD3 UR16, UP0, UR4, 0x2, URZ ; /* 0x0000000204107890 */
/* 0x000fc8000ff1e03f */
/*0230*/ UIADD3.X UR17, URZ, UR5, URZ, UP0, !UPT ; /* 0x000000053f117290 */
/* 0x000fc600087fe43f */
/*0240*/ I2F.U64 R4, UR14 ; /* 0x0000000e00047d12 */
/* 0x000ee20008301000 */
/*0250*/ UIADD3 UR14, UP0, UR4, 0x3, URZ ; /* 0x00000003040e7890 */
/* 0x000fc8000ff1e03f */
/*0260*/ UIADD3.X UR15, URZ, UR5, URZ, UP0, !UPT ; /* 0x000000053f0f7290 */
/* 0x000fe400087fe43f */
/*0270*/ UIADD3 UR4, UP0, UR4, 0x4, URZ ; /* 0x0000000404047890 */
/* 0x000fe2000ff1e03f */
/*0280*/ I2F.U64 R6, UR16 ; /* 0x0000001000067d12 */
/* 0x000f260008301000 */
/*0290*/ UIADD3.X UR5, URZ, UR5, URZ, UP0, !UPT ; /* 0x000000053f057290 */
/* 0x000fe400087fe43f */
/*02a0*/ UIADD3 UR7, UP0, UR4, UR6, URZ ; /* 0x0000000604077290 */
/* 0x000fc6000ff1e03f */
/*02b0*/ I2F.U64 R8, UR14 ; /* 0x0000000e00087d12 */
/* 0x000f620008301000 */
/*02c0*/ UIADD3.X UR9, UR5, UR10, URZ, UP0, !UPT ; /* 0x0000000a05097290 */
/* 0x000fe400087fe43f */
/*02d0*/ ISETP.NE.U32.AND P1, PT, RZ, UR7, PT ; /* 0x00000007ff007c0c */
/* 0x000fc8000bf25070 */
/*02e0*/ ISETP.NE.AND.EX P1, PT, RZ, UR9, PT, P1 ; /* 0x00000009ff007c0c */
/* 0x000fe2000bf25310 */
/*02f0*/ FADD R5, R0, R5 ; /* 0x0000000500057221 */
/* 0x004fe20000000000 */
/*0300*/ IADD3 R0, P2, R2, 0x10, RZ ; /* 0x0000001002007810 */
/* 0x000fe20007f5e0ff */
/*0310*/ FADD R7, R4, R7 ; /* 0x0000000704077221 */
/* 0x008fc60000000000 */
/*0320*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x0001e2000c10190c */
/*0330*/ IMAD.X R13, RZ, RZ, R3, P2 ; /* 0x000000ffff0d7224 */
/* 0x000fe400010e0603 */
/*0340*/ FADD R9, R6, R9 ; /* 0x0000000906097221 */
/* 0x010fe20000000000 */
/*0350*/ STG.E [R2.64+0x4], R7 ; /* 0x0000040702007986 */
/* 0x0001e2000c10190c */
/*0360*/ FADD R11, R8, R11 ; /* 0x0000000b080b7221 */
/* 0x020fc60000000000 */
/*0370*/ STG.E [R2.64+0x8], R9 ; /* 0x0000080902007986 */
/* 0x0001e8000c10190c */
/*0380*/ STG.E [R2.64+0xc], R11 ; /* 0x00000c0b02007986 */
/* 0x0001e2000c10190c */
/*0390*/ @P1 BRA 0x190 ; /* 0xfffffdf000001947 */
/* 0x000fea000383ffff */
/*03a0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*03b0*/ ULDC.64 UR10, c[0x0][0x160] ; /* 0x00005800000a7ab9 */
/* 0x000fe40000000a00 */
/*03c0*/ ULEA UR7, UP0, UR4, UR10, 0x2 ; /* 0x0000000a04077291 */
/* 0x000fe4000f80103f */
/*03d0*/ UIADD3 UR6, UP1, URZ, -UR8, URZ ; /* 0x800000083f067290 */
/* 0x000fe4000ff3e03f */
/*03e0*/ ULEA.HI.X UR8, UR4, UR11, UR5, 0x2, UP0 ; /* 0x0000000b04087291 */
/* 0x000fc400080f1405 */
/*03f0*/ IMAD.U32 R0, RZ, RZ, UR7 ; /* 0x00000007ff007e24 */
/* 0x000fe2000f8e00ff */
/*0400*/ UIADD3.X UR9, URZ, -0x1, URZ, UP1, !UPT ; /* 0xffffffff3f097890 */
/* 0x000fc60008ffe43f */
/*0410*/ MOV R7, UR8 ; /* 0x0000000800077c02 */
/* 0x001fc60008000f00 */
/*0420*/ IMAD.MOV.U32 R2, RZ, RZ, R0 ; /* 0x000000ffff027224 */
/* 0x001fe400078e0000 */
/*0430*/ IMAD.MOV.U32 R3, RZ, RZ, R7 ; /* 0x000000ffff037224 */
/* 0x000fca00078e0007 */
/*0440*/ LDG.E R0, [R2.64] ; /* 0x0000000c02007981 */
/* 0x000ea2000c1e1900 */
/*0450*/ UIADD3 UR6, UP0, UR6, 0x1, URZ ; /* 0x0000000106067890 */
/* 0x000fe2000ff1e03f */
/*0460*/ I2F.U64 R5, UR4 ; /* 0x0000000400057d12 */
/* 0x000ea60008301000 */
/*0470*/ UIADD3.X UR9, URZ, UR9, URZ, UP0, !UPT ; /* 0x000000093f097290 */
/* 0x000fe400087fe43f */
/*0480*/ ISETP.NE.U32.AND P0, PT, RZ, UR6, PT ; /* 0x00000006ff007c0c */
/* 0x000fe2000bf05070 */
/*0490*/ UIADD3 UR4, UP0, UR4, 0x1, URZ ; /* 0x0000000104047890 */
/* 0x000fc6000ff1e03f */
/*04a0*/ ISETP.NE.AND.EX P0, PT, RZ, UR9, PT, P0 ; /* 0x00000009ff007c0c */
/* 0x000fe2000bf05300 */
/*04b0*/ UIADD3.X UR5, URZ, UR5, URZ, UP0, !UPT ; /* 0x000000053f057290 */
/* 0x000fe200087fe43f */
/*04c0*/ FADD R5, R5, R0 ; /* 0x0000000005057221 */
/* 0x004fe20000000000 */
/*04d0*/ IADD3 R0, P1, R2, 0x4, RZ ; /* 0x0000000402007810 */
/* 0x000fc80007f3e0ff */
/*04e0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x0001e2000c10190c */
/*04f0*/ IADD3.X R7, RZ, R3, RZ, P1, !PT ; /* 0x00000003ff077210 */
/* 0x000fca0000ffe4ff */
/*0500*/ @P0 BRA 0x420 ; /* 0xffffff1000000947 */
/* 0x000fea000383ffff */
/*0510*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0520*/ BRA 0x520; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0530*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0540*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0550*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0560*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0570*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0580*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0590*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z16initializeDevicePfj
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e280000002100 */
/*0020*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0030*/ IMAD R2, R3, c[0x0][0x0], R2 ; /* 0x0000000003027a24 */
/* 0x001fca00078e0202 */
/*0040*/ ISETP.GE.U32.AND P0, PT, R2, c[0x0][0x168], PT ; /* 0x00005a0002007a0c */
/* 0x000fda0003f06070 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE.U32 R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0003 */
/*0090*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea4000c1e1900 */
/*00a0*/ FMUL R5, R0, 0.89999997615814208984 ; /* 0x3f66666600057820 */
/* 0x004fca0000400000 */
/*00b0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*00c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00d0*/ BRA 0xd0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z17unrollTrivialLoopv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z11trivialLoopv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z3nopv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <iostream>
#include <chrono>
using namespace std;
//CPU
typedef unsigned int uint;
uint i = 0;
int gpuCount = 0;
void initalizeHost( float *ip, uint size );
//GPU
cudaDeviceProp gpuProperties;
const uint N = 1E7;
const uint nThreads = 512;
const uint nBlocks = ( N / nThreads ) + 1;
const uint UNROLLING = 16; //check [ 8 16 32 64 ]; I would guess sixteen times unrolling;
__global__ void nop(){};
__global__ void trivialLoop()
{
uint a = 0;
for ( uint32_t i = 0; i < N; i++ )
{
a = i;
a++;
}
};
__global__ void unrollTrivialLoop()
{
uint a = 0;
#pragma unroll UNROLLING //briliant feature
for ( uint32_t i = 0; i < N; i++ )
{
a = i;
a++;
}
};
__global__ void initializeDevice( float *d_in, const uint streamSize )
{
uint tid = threadIdx.x;
uint idx = blockIdx.x * blockDim.x + tid;
if( idx < streamSize )
{
d_in[ idx ] *= 0.9f;
}
};
__global__ void loop( float *d_in, const uint streamNo, const uint streamSize )
{
size_t ii = 0;
for ( ii = 0; ii < streamSize; ii++ )
{
d_in[ ii ] += float( ii );
}
};
__global__ void unrollLoop( float *d_in, const uint streamNo, const uint streamSize )
{
size_t ii = 0;
#pragma unroll UNROLLING //adjustable mainly to register-only, high performance computations - described at unrollTrivialLoop device kernel
for ( ii = 0; ii < streamSize; ii++ )
{
d_in[ ii ] += float( ii );
}
};
int main( void )
{
cudaGetDeviceCount( &gpuCount );
//HOST
float *h_arr[ gpuCount ]; // float **h_arr = ( float** )malloc( sizeof( float * ) * gpuCount ); //alternatively
uint perDevN = N / gpuCount;
uint perDevNBytes = sizeof( float ) * perDevN ;
//DEVICE
cudaStream_t stream[ gpuCount ];
float *d_arr[ gpuCount ]; // float **d_arr = ( float** )malloc( sizeof( float * ) * gpuCount ); //alternatively
//alocate & initialize H,D memories
for ( i = 0; i < gpuCount; i++ )
{
//HOST
cudaMallocHost( ( void** ) &h_arr[ i ], perDevNBytes );
initalizeHost( h_arr[ i ], perDevN );
//DEVICE
cudaSetDevice( i );
cudaMalloc( ( void** ) &d_arr[ i ], perDevNBytes );
cudaStreamCreate( &stream[ i ] );
}
//DEVICE computations
for ( i = 0; i < gpuCount; i++ )
{
cudaSetDevice( i );
cudaGetDeviceProperties( &gpuProperties, i );
cout << endl << gpuProperties.name << ": " << endl;
auto t1 = chrono::high_resolution_clock::now();
trivialLoop<<< 1, 1 >>>();
nop<<< 1, 1 >>>();
auto t2 = chrono::high_resolution_clock::now();
uint elapsed = uint( chrono::duration_cast< chrono::nanoseconds >( t2 - t1 ).count() );
printf( "trivial loop elapsed: %d \n", elapsed );
t1 = chrono::high_resolution_clock::now();
unrollTrivialLoop<<< 1, 1 >>>();
nop<<< 1, 1 >>>();
t2 = chrono::high_resolution_clock::now();
elapsed = chrono::duration_cast< chrono::nanoseconds >( t2 - t1 ).count();
printf( "trivial unrolled loop elapsed: %d \n", elapsed );
cudaMemcpyAsync( d_arr[ i ], h_arr[ i ], perDevNBytes, cudaMemcpyHostToDevice, stream[ i ] );
initializeDevice<<< nBlocks, nThreads, 0, stream[ i ] >>>( d_arr[ i ], perDevN );
nop<<< 1, 1 >>>();
t1 = chrono::high_resolution_clock::now();
loop<<< 1, 1, 0, stream[ i ] >>>( d_arr[ i ], i, perDevN );
nop<<< 1, 1 >>>();
t2 = chrono::high_resolution_clock::now();
elapsed = chrono::duration_cast< chrono::nanoseconds >( t2 - t1 ).count();
printf( "loop elapsed: %d \n", elapsed );
t1 = chrono::high_resolution_clock::now();
unrollLoop<<< 1, 1, 0, stream[ i ] >>>( d_arr[ i ], i, perDevN );
nop<<< 1, 1 >>>();
t2 = chrono::high_resolution_clock::now();
elapsed = chrono::duration_cast< chrono::nanoseconds >( t2 - t1 ).count();
printf( "unrolled loop elapsed: %d \n", elapsed );
}
//free memories
for ( i = 0; i < gpuCount; i++ )
{
//HOST
cudaFreeHost( h_arr[ i ] );
//DEVICE
cudaSetDevice( i );
cudaFree( d_arr[ i ] );
cudaStreamDestroy( stream[ i ] );
}
cudaDeviceReset();
return 0;
}
void initalizeHost( float *ip, uint size )
{
for ( size_t i = 0; i < size; i++ )
ip[ i ] = 1.2f;
};
//Post Scriptum: In my professional opinion, coprocessors: GTX1080ti is brand-new and off-the-shell optimal; GTX770 is used optimal - I've heard about R9Nano and HD5770 ( GFLOPS/USD; GFLOPS/W; QualityWithBandwidthAndMemSize/Price; );
//Post Post Scriptum: I do strongly recommend profiling with NVidia's NVPROF profiling tool, instead of CPU high-resolution timer. | .file "tmpxft_000f72c0_00000000-6_mgpgpu.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3774:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3774:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z13initalizeHostPfj
.type _Z13initalizeHostPfj, @function
_Z13initalizeHostPfj:
.LFB3771:
.cfi_startproc
endbr64
movl %esi, %edx
testl %esi, %esi
je .L3
movq %rdi, %rax
leaq (%rdi,%rdx,4), %rdx
movss .LC0(%rip), %xmm0
.L5:
movss %xmm0, (%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L5
.L3:
ret
.cfi_endproc
.LFE3771:
.size _Z13initalizeHostPfj, .-_Z13initalizeHostPfj
.globl _Z21__device_stub__Z3nopvv
.type _Z21__device_stub__Z3nopvv, @function
_Z21__device_stub__Z3nopvv:
.LFB3796:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L11
.L7:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L12
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z3nopv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L7
.L12:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3796:
.size _Z21__device_stub__Z3nopvv, .-_Z21__device_stub__Z3nopvv
.globl _Z3nopv
.type _Z3nopv, @function
_Z3nopv:
.LFB3797:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z21__device_stub__Z3nopvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3797:
.size _Z3nopv, .-_Z3nopv
.globl _Z30__device_stub__Z11trivialLoopvv
.type _Z30__device_stub__Z11trivialLoopvv, @function
_Z30__device_stub__Z11trivialLoopvv:
.LFB3798:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L19
.L15:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L20
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z11trivialLoopv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L15
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3798:
.size _Z30__device_stub__Z11trivialLoopvv, .-_Z30__device_stub__Z11trivialLoopvv
.globl _Z11trivialLoopv
.type _Z11trivialLoopv, @function
_Z11trivialLoopv:
.LFB3799:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z11trivialLoopvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3799:
.size _Z11trivialLoopv, .-_Z11trivialLoopv
.globl _Z36__device_stub__Z17unrollTrivialLoopvv
.type _Z36__device_stub__Z17unrollTrivialLoopvv, @function
_Z36__device_stub__Z17unrollTrivialLoopvv:
.LFB3800:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L27
.L23:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L28
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L27:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z17unrollTrivialLoopv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L23
.L28:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3800:
.size _Z36__device_stub__Z17unrollTrivialLoopvv, .-_Z36__device_stub__Z17unrollTrivialLoopvv
.globl _Z17unrollTrivialLoopv
.type _Z17unrollTrivialLoopv, @function
_Z17unrollTrivialLoopv:
.LFB3801:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z36__device_stub__Z17unrollTrivialLoopvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3801:
.size _Z17unrollTrivialLoopv, .-_Z17unrollTrivialLoopv
.globl _Z37__device_stub__Z16initializeDevicePfjPfj
.type _Z37__device_stub__Z16initializeDevicePfjPfj, @function
_Z37__device_stub__Z16initializeDevicePfjPfj:
.LFB3802:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L35
.L31:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L36
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L35:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z16initializeDevicePfj(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L31
.L36:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3802:
.size _Z37__device_stub__Z16initializeDevicePfjPfj, .-_Z37__device_stub__Z16initializeDevicePfjPfj
.globl _Z16initializeDevicePfj
.type _Z16initializeDevicePfj, @function
_Z16initializeDevicePfj:
.LFB3803:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z37__device_stub__Z16initializeDevicePfjPfj
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3803:
.size _Z16initializeDevicePfj, .-_Z16initializeDevicePfj
.globl _Z25__device_stub__Z4loopPfjjPfjj
.type _Z25__device_stub__Z4loopPfjjPfjj, @function
_Z25__device_stub__Z4loopPfjjPfjj:
.LFB3804:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L43
.L39:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L44
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L43:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z4loopPfjj(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L39
.L44:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3804:
.size _Z25__device_stub__Z4loopPfjjPfjj, .-_Z25__device_stub__Z4loopPfjjPfjj
.globl _Z4loopPfjj
.type _Z4loopPfjj, @function
_Z4loopPfjj:
.LFB3805:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z25__device_stub__Z4loopPfjjPfjj
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3805:
.size _Z4loopPfjj, .-_Z4loopPfjj
.globl _Z32__device_stub__Z10unrollLoopPfjjPfjj
.type _Z32__device_stub__Z10unrollLoopPfjjPfjj, @function
_Z32__device_stub__Z10unrollLoopPfjjPfjj:
.LFB3806:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L51
.L47:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L52
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L51:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z10unrollLoopPfjj(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L47
.L52:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3806:
.size _Z32__device_stub__Z10unrollLoopPfjjPfjj, .-_Z32__device_stub__Z10unrollLoopPfjjPfjj
.globl _Z10unrollLoopPfjj
.type _Z10unrollLoopPfjj, @function
_Z10unrollLoopPfjj:
.LFB3807:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z10unrollLoopPfjjPfjj
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3807:
.size _Z10unrollLoopPfjj, .-_Z10unrollLoopPfjj
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string ": "
.LC2:
.string "trivial loop elapsed: %d \n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC3:
.string "trivial unrolled loop elapsed: %d \n"
.section .rodata.str1.1
.LC4:
.string "loop elapsed: %d \n"
.LC5:
.string "unrolled loop elapsed: %d \n"
.text
.globl main
.type main, @function
main:
.LFB3768:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
movq %rsp, %rbp
.cfi_def_cfa_register 6
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $56, %rsp
.cfi_offset 15, -24
.cfi_offset 14, -32
.cfi_offset 13, -40
.cfi_offset 12, -48
.cfi_offset 3, -56
movq %fs:40, %rax
movq %rax, -56(%rbp)
xorl %eax, %eax
leaq gpuCount(%rip), %rdi
call cudaGetDeviceCount@PLT
movl gpuCount(%rip), %esi
movslq %esi, %rcx
salq $3, %rcx
leaq 15(%rcx), %rax
movq %rax, %rdi
andq $-16, %rdi
andq $-4096, %rax
movq %rsp, %rdx
subq %rax, %rdx
.L56:
cmpq %rdx, %rsp
je .L57
subq $4096, %rsp
orq $0, 4088(%rsp)
jmp .L56
.L57:
movq %rdi, %rax
andl $4095, %eax
subq %rax, %rsp
testq %rax, %rax
je .L58
orq $0, -8(%rsp,%rax)
.L58:
movq %rsp, %r14
movl $10000000, %eax
movl $0, %edx
divl %esi
movl %eax, -88(%rbp)
sall $2, %eax
movl %eax, -84(%rbp)
leaq 15(%rcx), %rax
movq %rax, %rdi
andq $-16, %rdi
andq $-4096, %rax
movq %rsp, %rdx
subq %rax, %rdx
.L59:
cmpq %rdx, %rsp
je .L60
subq $4096, %rsp
orq $0, 4088(%rsp)
jmp .L59
.L60:
movq %rdi, %rax
andl $4095, %eax
subq %rax, %rsp
testq %rax, %rax
je .L61
orq $0, -8(%rsp,%rax)
.L61:
movq %rsp, %r12
addq $15, %rcx
movq %rcx, %rdx
andq $-16, %rdx
andq $-4096, %rcx
movq %rsp, %rax
subq %rcx, %rax
.L62:
cmpq %rax, %rsp
je .L63
subq $4096, %rsp
orq $0, 4088(%rsp)
jmp .L62
.L63:
movq %rdx, %rax
andl $4095, %eax
subq %rax, %rsp
testq %rax, %rax
je .L64
orq $0, -8(%rsp,%rax)
.L64:
movq %rsp, %r15
movl $0, i(%rip)
testl %esi, %esi
je .L65
movl $0, %eax
movl -84(%rbp), %ebx
movl -88(%rbp), %r13d
.L66:
movl %eax, %eax
leaq (%r14,%rax,8), %rdi
movq %rbx, %rsi
call cudaMallocHost@PLT
movl i(%rip), %eax
movq (%r14,%rax,8), %rdi
movl %r13d, %esi
call _Z13initalizeHostPfj
movl i(%rip), %edi
call cudaSetDevice@PLT
movl i(%rip), %eax
leaq (%r15,%rax,8), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl i(%rip), %eax
leaq (%r12,%rax,8), %rdi
call cudaStreamCreate@PLT
movl i(%rip), %eax
addl $1, %eax
movl %eax, i(%rip)
cmpl gpuCount(%rip), %eax
jb .L66
.L65:
movl $0, i(%rip)
cmpl $0, gpuCount(%rip)
je .L67
movl $0, %edi
jmp .L86
.L106:
movq -56(%rbp), %rax
subq %fs:40, %rax
jne .L94
call _ZSt16__throw_bad_castv@PLT
.L94:
call __stack_chk_fail@PLT
.L70:
movq %rbx, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%rbx), %rax
movl $10, %esi
movq %rbx, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L71
.L107:
movq -56(%rbp), %rax
subq %fs:40, %rax
jne .L95
call _ZSt16__throw_bad_castv@PLT
.L95:
call __stack_chk_fail@PLT
.L74:
movq %r13, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq 0(%r13), %rax
movl $10, %esi
movq %r13, %rdi
call *48(%rax)
movl %eax, %esi
.L75:
movsbl %sil, %esi
movq %rbx, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
call _ZNSt6chrono3_V212system_clock3nowEv@PLT
movq %rax, %rbx
movl $1, -68(%rbp)
movl $1, -64(%rbp)
movl $1, -60(%rbp)
movl $1, -80(%rbp)
movl $1, -76(%rbp)
movl $1, -72(%rbp)
movl $0, %r9d
movl $0, %r8d
movq -68(%rbp), %rdx
movl $1, %ecx
movq -80(%rbp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L96
.L76:
movl $1, -68(%rbp)
movl $1, -64(%rbp)
movl $1, -60(%rbp)
movl $1, -80(%rbp)
movl $1, -76(%rbp)
movl $1, -72(%rbp)
movl $0, %r9d
movl $0, %r8d
movq -68(%rbp), %rdx
movl $1, %ecx
movq -80(%rbp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L97
.L77:
call _ZNSt6chrono3_V212system_clock3nowEv@PLT
movl %eax, %edx
subl %ebx, %edx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
call _ZNSt6chrono3_V212system_clock3nowEv@PLT
movq %rax, %rbx
movl $1, -68(%rbp)
movl $1, -64(%rbp)
movl $1, -60(%rbp)
movl $1, -80(%rbp)
movl $1, -76(%rbp)
movl $1, -72(%rbp)
movl $0, %r9d
movl $0, %r8d
movq -68(%rbp), %rdx
movl $1, %ecx
movq -80(%rbp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L98
.L78:
movl $1, -68(%rbp)
movl $1, -64(%rbp)
movl $1, -60(%rbp)
movl $1, -80(%rbp)
movl $1, -76(%rbp)
movl $1, -72(%rbp)
movl $0, %r9d
movl $0, %r8d
movq -68(%rbp), %rdx
movl $1, %ecx
movq -80(%rbp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L99
.L79:
call _ZNSt6chrono3_V212system_clock3nowEv@PLT
movl %eax, %edx
subl %ebx, %edx
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl i(%rip), %eax
movl -84(%rbp), %edx
movq (%r14,%rax,8), %rsi
movq (%r15,%rax,8), %rdi
movq (%r12,%rax,8), %r8
movl $1, %ecx
call cudaMemcpyAsync@PLT
movl i(%rip), %eax
movl $512, -68(%rbp)
movl $1, -64(%rbp)
movl $1, -60(%rbp)
movl $19532, -80(%rbp)
movl $1, -76(%rbp)
movl $1, -72(%rbp)
movq (%r12,%rax,8), %r9
movl $0, %r8d
movq -68(%rbp), %rdx
movl $1, %ecx
movq -80(%rbp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L100
.L80:
movl $1, -68(%rbp)
movl $1, -64(%rbp)
movl $1, -60(%rbp)
movl $1, -80(%rbp)
movl $1, -76(%rbp)
movl $1, -72(%rbp)
movl $0, %r9d
movl $0, %r8d
movq -68(%rbp), %rdx
movl $1, %ecx
movq -80(%rbp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L101
.L81:
call _ZNSt6chrono3_V212system_clock3nowEv@PLT
movq %rax, %rbx
movl i(%rip), %eax
movl $1, -68(%rbp)
movl $1, -64(%rbp)
movl $1, -60(%rbp)
movl $1, -80(%rbp)
movl $1, -76(%rbp)
movl $1, -72(%rbp)
movq (%r12,%rax,8), %r9
movl $0, %r8d
movq -68(%rbp), %rdx
movl $1, %ecx
movq -80(%rbp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L102
.L82:
movl $1, -68(%rbp)
movl $1, -64(%rbp)
movl $1, -60(%rbp)
movl $1, -80(%rbp)
movl $1, -76(%rbp)
movl $1, -72(%rbp)
movl $0, %r9d
movl $0, %r8d
movq -68(%rbp), %rdx
movl $1, %ecx
movq -80(%rbp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L103
.L83:
call _ZNSt6chrono3_V212system_clock3nowEv@PLT
movl %eax, %edx
subl %ebx, %edx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
call _ZNSt6chrono3_V212system_clock3nowEv@PLT
movq %rax, %rbx
movl i(%rip), %eax
movl $1, -68(%rbp)
movl $1, -64(%rbp)
movl $1, -60(%rbp)
movl $1, -80(%rbp)
movl $1, -76(%rbp)
movl $1, -72(%rbp)
movq (%r12,%rax,8), %r9
movl $0, %r8d
movq -68(%rbp), %rdx
movl $1, %ecx
movq -80(%rbp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L104
.L84:
movl $1, -68(%rbp)
movl $1, -64(%rbp)
movl $1, -60(%rbp)
movl $1, -80(%rbp)
movl $1, -76(%rbp)
movl $1, -72(%rbp)
movl $0, %r9d
movl $0, %r8d
movq -68(%rbp), %rdx
movl $1, %ecx
movq -80(%rbp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L105
.L85:
call _ZNSt6chrono3_V212system_clock3nowEv@PLT
movl %eax, %edx
subl %ebx, %edx
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl i(%rip), %eax
leal 1(%rax), %edi
movl %edi, i(%rip)
cmpl gpuCount(%rip), %edi
jnb .L67
.L86:
call cudaSetDevice@PLT
movl i(%rip), %esi
leaq gpuProperties(%rip), %rdi
call cudaGetDeviceProperties_v2@PLT
leaq _ZSt4cout(%rip), %rcx
movq (%rcx), %rax
movq -24(%rax), %rax
movq 240(%rcx,%rax), %rbx
testq %rbx, %rbx
je .L106
cmpb $0, 56(%rbx)
je .L70
movzbl 67(%rbx), %esi
.L71:
movsbl %sil, %esi
leaq _ZSt4cout(%rip), %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movq %rax, %rbx
leaq gpuProperties(%rip), %rdi
call strlen@PLT
movq %rax, %rdx
leaq gpuProperties(%rip), %rsi
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl $2, %edx
leaq .LC1(%rip), %rsi
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq (%rbx), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r13
testq %r13, %r13
je .L107
cmpb $0, 56(%r13)
je .L74
movzbl 67(%r13), %esi
jmp .L75
.L96:
call _Z30__device_stub__Z11trivialLoopvv
jmp .L76
.L97:
call _Z21__device_stub__Z3nopvv
jmp .L77
.L98:
call _Z36__device_stub__Z17unrollTrivialLoopvv
jmp .L78
.L99:
call _Z21__device_stub__Z3nopvv
jmp .L79
.L100:
movl i(%rip), %eax
movq (%r15,%rax,8), %rdi
movl -88(%rbp), %esi
call _Z37__device_stub__Z16initializeDevicePfjPfj
jmp .L80
.L101:
call _Z21__device_stub__Z3nopvv
jmp .L81
.L102:
movl i(%rip), %esi
movl %esi, %eax
movq (%r15,%rax,8), %rdi
movl -88(%rbp), %edx
call _Z25__device_stub__Z4loopPfjjPfjj
jmp .L82
.L103:
call _Z21__device_stub__Z3nopvv
jmp .L83
.L104:
movl i(%rip), %esi
movl %esi, %eax
movq (%r15,%rax,8), %rdi
movl -88(%rbp), %edx
call _Z32__device_stub__Z10unrollLoopPfjjPfjj
jmp .L84
.L105:
call _Z21__device_stub__Z3nopvv
jmp .L85
.L67:
movl $0, i(%rip)
cmpl $0, gpuCount(%rip)
je .L87
movl $0, %eax
.L88:
movl %eax, %eax
movq (%r14,%rax,8), %rdi
call cudaFreeHost@PLT
movl i(%rip), %edi
call cudaSetDevice@PLT
movl i(%rip), %eax
movq (%r15,%rax,8), %rdi
call cudaFree@PLT
movl i(%rip), %eax
movq (%r12,%rax,8), %rdi
call cudaStreamDestroy@PLT
movl i(%rip), %eax
addl $1, %eax
movl %eax, i(%rip)
cmpl gpuCount(%rip), %eax
jb .L88
.L87:
call cudaDeviceReset@PLT
movq -56(%rbp), %rax
subq %fs:40, %rax
jne .L108
movl $0, %eax
leaq -40(%rbp), %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
.cfi_remember_state
.cfi_def_cfa 7, 8
ret
.L108:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3768:
.size main, .-main
.section .rodata.str1.1
.LC6:
.string "_Z10unrollLoopPfjj"
.LC7:
.string "_Z4loopPfjj"
.LC8:
.string "_Z16initializeDevicePfj"
.LC9:
.string "_Z17unrollTrivialLoopv"
.LC10:
.string "_Z11trivialLoopv"
.LC11:
.string "_Z3nopv"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3809:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _Z10unrollLoopPfjj(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _Z4loopPfjj(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _Z16initializeDevicePfj(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _Z17unrollTrivialLoopv(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC10(%rip), %rdx
movq %rdx, %rcx
leaq _Z11trivialLoopv(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC11(%rip), %rdx
movq %rdx, %rcx
leaq _Z3nopv(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3809:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl gpuProperties
.bss
.align 32
.type gpuProperties, @object
.size gpuProperties, 1032
gpuProperties:
.zero 1032
.globl gpuCount
.align 4
.type gpuCount, @object
.size gpuCount, 4
gpuCount:
.zero 4
.globl i
.align 4
.type i, @object
.size i, 4
i:
.zero 4
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC0:
.long 1067030938
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <iostream>
#include <chrono>
using namespace std;
//CPU
typedef unsigned int uint;
uint i = 0;
int gpuCount = 0;
void initalizeHost( float *ip, uint size );
//GPU
cudaDeviceProp gpuProperties;
const uint N = 1E7;
const uint nThreads = 512;
const uint nBlocks = ( N / nThreads ) + 1;
const uint UNROLLING = 16; //check [ 8 16 32 64 ]; I would guess sixteen times unrolling;
__global__ void nop(){};
__global__ void trivialLoop()
{
uint a = 0;
for ( uint32_t i = 0; i < N; i++ )
{
a = i;
a++;
}
};
__global__ void unrollTrivialLoop()
{
uint a = 0;
#pragma unroll UNROLLING //briliant feature
for ( uint32_t i = 0; i < N; i++ )
{
a = i;
a++;
}
};
__global__ void initializeDevice( float *d_in, const uint streamSize )
{
uint tid = threadIdx.x;
uint idx = blockIdx.x * blockDim.x + tid;
if( idx < streamSize )
{
d_in[ idx ] *= 0.9f;
}
};
__global__ void loop( float *d_in, const uint streamNo, const uint streamSize )
{
size_t ii = 0;
for ( ii = 0; ii < streamSize; ii++ )
{
d_in[ ii ] += float( ii );
}
};
__global__ void unrollLoop( float *d_in, const uint streamNo, const uint streamSize )
{
size_t ii = 0;
#pragma unroll UNROLLING //adjustable mainly to register-only, high performance computations - described at unrollTrivialLoop device kernel
for ( ii = 0; ii < streamSize; ii++ )
{
d_in[ ii ] += float( ii );
}
};
int main( void )
{
cudaGetDeviceCount( &gpuCount );
//HOST
float *h_arr[ gpuCount ]; // float **h_arr = ( float** )malloc( sizeof( float * ) * gpuCount ); //alternatively
uint perDevN = N / gpuCount;
uint perDevNBytes = sizeof( float ) * perDevN ;
//DEVICE
cudaStream_t stream[ gpuCount ];
float *d_arr[ gpuCount ]; // float **d_arr = ( float** )malloc( sizeof( float * ) * gpuCount ); //alternatively
//alocate & initialize H,D memories
for ( i = 0; i < gpuCount; i++ )
{
//HOST
cudaMallocHost( ( void** ) &h_arr[ i ], perDevNBytes );
initalizeHost( h_arr[ i ], perDevN );
//DEVICE
cudaSetDevice( i );
cudaMalloc( ( void** ) &d_arr[ i ], perDevNBytes );
cudaStreamCreate( &stream[ i ] );
}
//DEVICE computations
for ( i = 0; i < gpuCount; i++ )
{
cudaSetDevice( i );
cudaGetDeviceProperties( &gpuProperties, i );
cout << endl << gpuProperties.name << ": " << endl;
auto t1 = chrono::high_resolution_clock::now();
trivialLoop<<< 1, 1 >>>();
nop<<< 1, 1 >>>();
auto t2 = chrono::high_resolution_clock::now();
uint elapsed = uint( chrono::duration_cast< chrono::nanoseconds >( t2 - t1 ).count() );
printf( "trivial loop elapsed: %d \n", elapsed );
t1 = chrono::high_resolution_clock::now();
unrollTrivialLoop<<< 1, 1 >>>();
nop<<< 1, 1 >>>();
t2 = chrono::high_resolution_clock::now();
elapsed = chrono::duration_cast< chrono::nanoseconds >( t2 - t1 ).count();
printf( "trivial unrolled loop elapsed: %d \n", elapsed );
cudaMemcpyAsync( d_arr[ i ], h_arr[ i ], perDevNBytes, cudaMemcpyHostToDevice, stream[ i ] );
initializeDevice<<< nBlocks, nThreads, 0, stream[ i ] >>>( d_arr[ i ], perDevN );
nop<<< 1, 1 >>>();
t1 = chrono::high_resolution_clock::now();
loop<<< 1, 1, 0, stream[ i ] >>>( d_arr[ i ], i, perDevN );
nop<<< 1, 1 >>>();
t2 = chrono::high_resolution_clock::now();
elapsed = chrono::duration_cast< chrono::nanoseconds >( t2 - t1 ).count();
printf( "loop elapsed: %d \n", elapsed );
t1 = chrono::high_resolution_clock::now();
unrollLoop<<< 1, 1, 0, stream[ i ] >>>( d_arr[ i ], i, perDevN );
nop<<< 1, 1 >>>();
t2 = chrono::high_resolution_clock::now();
elapsed = chrono::duration_cast< chrono::nanoseconds >( t2 - t1 ).count();
printf( "unrolled loop elapsed: %d \n", elapsed );
}
//free memories
for ( i = 0; i < gpuCount; i++ )
{
//HOST
cudaFreeHost( h_arr[ i ] );
//DEVICE
cudaSetDevice( i );
cudaFree( d_arr[ i ] );
cudaStreamDestroy( stream[ i ] );
}
cudaDeviceReset();
return 0;
}
void initalizeHost( float *ip, uint size )
{
for ( size_t i = 0; i < size; i++ )
ip[ i ] = 1.2f;
};
//Post Scriptum: In my professional opinion, coprocessors: GTX1080ti is brand-new and off-the-shell optimal; GTX770 is used optimal - I've heard about R9Nano and HD5770 ( GFLOPS/USD; GFLOPS/W; QualityWithBandwidthAndMemSize/Price; );
//Post Post Scriptum: I do strongly recommend profiling with NVidia's NVPROF profiling tool, instead of CPU high-resolution timer. | #include <hip/hip_runtime.h>
#include <iostream>
#include <chrono>
using namespace std;
//CPU
typedef unsigned int uint;
uint i = 0;
int gpuCount = 0;
void initalizeHost( float *ip, uint size );
//GPU
hipDeviceProp_t gpuProperties;
const uint N = 1E7;
const uint nThreads = 512;
const uint nBlocks = ( N / nThreads ) + 1;
const uint UNROLLING = 16; //check [ 8 16 32 64 ]; I would guess sixteen times unrolling;
__global__ void nop(){};
__global__ void trivialLoop()
{
uint a = 0;
for ( uint32_t i = 0; i < N; i++ )
{
a = i;
a++;
}
};
__global__ void unrollTrivialLoop()
{
uint a = 0;
#pragma unroll UNROLLING //briliant feature
for ( uint32_t i = 0; i < N; i++ )
{
a = i;
a++;
}
};
__global__ void initializeDevice( float *d_in, const uint streamSize )
{
uint tid = threadIdx.x;
uint idx = blockIdx.x * blockDim.x + tid;
if( idx < streamSize )
{
d_in[ idx ] *= 0.9f;
}
};
__global__ void loop( float *d_in, const uint streamNo, const uint streamSize )
{
size_t ii = 0;
for ( ii = 0; ii < streamSize; ii++ )
{
d_in[ ii ] += float( ii );
}
};
__global__ void unrollLoop( float *d_in, const uint streamNo, const uint streamSize )
{
size_t ii = 0;
#pragma unroll UNROLLING //adjustable mainly to register-only, high performance computations - described at unrollTrivialLoop device kernel
for ( ii = 0; ii < streamSize; ii++ )
{
d_in[ ii ] += float( ii );
}
};
int main( void )
{
hipGetDeviceCount( &gpuCount );
//HOST
float *h_arr[ gpuCount ]; // float **h_arr = ( float** )malloc( sizeof( float * ) * gpuCount ); //alternatively
uint perDevN = N / gpuCount;
uint perDevNBytes = sizeof( float ) * perDevN ;
//DEVICE
hipStream_t stream[ gpuCount ];
float *d_arr[ gpuCount ]; // float **d_arr = ( float** )malloc( sizeof( float * ) * gpuCount ); //alternatively
//alocate & initialize H,D memories
for ( i = 0; i < gpuCount; i++ )
{
//HOST
hipHostMalloc( ( void** ) &h_arr[ i ], perDevNBytes , hipHostMallocDefault);
initalizeHost( h_arr[ i ], perDevN );
//DEVICE
hipSetDevice( i );
hipMalloc( ( void** ) &d_arr[ i ], perDevNBytes );
hipStreamCreate( &stream[ i ] );
}
//DEVICE computations
for ( i = 0; i < gpuCount; i++ )
{
hipSetDevice( i );
hipGetDeviceProperties( &gpuProperties, i );
cout << endl << gpuProperties.name << ": " << endl;
auto t1 = chrono::high_resolution_clock::now();
trivialLoop<<< 1, 1 >>>();
nop<<< 1, 1 >>>();
auto t2 = chrono::high_resolution_clock::now();
uint elapsed = uint( chrono::duration_cast< chrono::nanoseconds >( t2 - t1 ).count() );
printf( "trivial loop elapsed: %d \n", elapsed );
t1 = chrono::high_resolution_clock::now();
unrollTrivialLoop<<< 1, 1 >>>();
nop<<< 1, 1 >>>();
t2 = chrono::high_resolution_clock::now();
elapsed = chrono::duration_cast< chrono::nanoseconds >( t2 - t1 ).count();
printf( "trivial unrolled loop elapsed: %d \n", elapsed );
hipMemcpyAsync( d_arr[ i ], h_arr[ i ], perDevNBytes, hipMemcpyHostToDevice, stream[ i ] );
initializeDevice<<< nBlocks, nThreads, 0, stream[ i ] >>>( d_arr[ i ], perDevN );
nop<<< 1, 1 >>>();
t1 = chrono::high_resolution_clock::now();
loop<<< 1, 1, 0, stream[ i ] >>>( d_arr[ i ], i, perDevN );
nop<<< 1, 1 >>>();
t2 = chrono::high_resolution_clock::now();
elapsed = chrono::duration_cast< chrono::nanoseconds >( t2 - t1 ).count();
printf( "loop elapsed: %d \n", elapsed );
t1 = chrono::high_resolution_clock::now();
unrollLoop<<< 1, 1, 0, stream[ i ] >>>( d_arr[ i ], i, perDevN );
nop<<< 1, 1 >>>();
t2 = chrono::high_resolution_clock::now();
elapsed = chrono::duration_cast< chrono::nanoseconds >( t2 - t1 ).count();
printf( "unrolled loop elapsed: %d \n", elapsed );
}
//free memories
for ( i = 0; i < gpuCount; i++ )
{
//HOST
hipHostFree( h_arr[ i ] );
//DEVICE
hipSetDevice( i );
hipFree( d_arr[ i ] );
hipStreamDestroy( stream[ i ] );
}
hipDeviceReset();
return 0;
}
void initalizeHost( float *ip, uint size )
{
for ( size_t i = 0; i < size; i++ )
ip[ i ] = 1.2f;
};
//Post Scriptum: In my professional opinion, coprocessors: GTX1080ti is brand-new and off-the-shell optimal; GTX770 is used optimal - I've heard about R9Nano and HD5770 ( GFLOPS/USD; GFLOPS/W; QualityWithBandwidthAndMemSize/Price; );
//Post Post Scriptum: I do strongly recommend profiling with NVidia's NVPROF profiling tool, instead of CPU high-resolution timer. |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <iostream>
#include <chrono>
using namespace std;
//CPU
typedef unsigned int uint;
uint i = 0;
int gpuCount = 0;
void initalizeHost( float *ip, uint size );
//GPU
hipDeviceProp_t gpuProperties;
const uint N = 1E7;
const uint nThreads = 512;
const uint nBlocks = ( N / nThreads ) + 1;
const uint UNROLLING = 16; //check [ 8 16 32 64 ]; I would guess sixteen times unrolling;
__global__ void nop(){};
__global__ void trivialLoop()
{
uint a = 0;
for ( uint32_t i = 0; i < N; i++ )
{
a = i;
a++;
}
};
__global__ void unrollTrivialLoop()
{
uint a = 0;
#pragma unroll UNROLLING //briliant feature
for ( uint32_t i = 0; i < N; i++ )
{
a = i;
a++;
}
};
__global__ void initializeDevice( float *d_in, const uint streamSize )
{
uint tid = threadIdx.x;
uint idx = blockIdx.x * blockDim.x + tid;
if( idx < streamSize )
{
d_in[ idx ] *= 0.9f;
}
};
__global__ void loop( float *d_in, const uint streamNo, const uint streamSize )
{
size_t ii = 0;
for ( ii = 0; ii < streamSize; ii++ )
{
d_in[ ii ] += float( ii );
}
};
__global__ void unrollLoop( float *d_in, const uint streamNo, const uint streamSize )
{
size_t ii = 0;
#pragma unroll UNROLLING //adjustable mainly to register-only, high performance computations - described at unrollTrivialLoop device kernel
for ( ii = 0; ii < streamSize; ii++ )
{
d_in[ ii ] += float( ii );
}
};
int main( void )
{
hipGetDeviceCount( &gpuCount );
//HOST
float *h_arr[ gpuCount ]; // float **h_arr = ( float** )malloc( sizeof( float * ) * gpuCount ); //alternatively
uint perDevN = N / gpuCount;
uint perDevNBytes = sizeof( float ) * perDevN ;
//DEVICE
hipStream_t stream[ gpuCount ];
float *d_arr[ gpuCount ]; // float **d_arr = ( float** )malloc( sizeof( float * ) * gpuCount ); //alternatively
//alocate & initialize H,D memories
for ( i = 0; i < gpuCount; i++ )
{
//HOST
hipHostMalloc( ( void** ) &h_arr[ i ], perDevNBytes , hipHostMallocDefault);
initalizeHost( h_arr[ i ], perDevN );
//DEVICE
hipSetDevice( i );
hipMalloc( ( void** ) &d_arr[ i ], perDevNBytes );
hipStreamCreate( &stream[ i ] );
}
//DEVICE computations
for ( i = 0; i < gpuCount; i++ )
{
hipSetDevice( i );
hipGetDeviceProperties( &gpuProperties, i );
cout << endl << gpuProperties.name << ": " << endl;
auto t1 = chrono::high_resolution_clock::now();
trivialLoop<<< 1, 1 >>>();
nop<<< 1, 1 >>>();
auto t2 = chrono::high_resolution_clock::now();
uint elapsed = uint( chrono::duration_cast< chrono::nanoseconds >( t2 - t1 ).count() );
printf( "trivial loop elapsed: %d \n", elapsed );
t1 = chrono::high_resolution_clock::now();
unrollTrivialLoop<<< 1, 1 >>>();
nop<<< 1, 1 >>>();
t2 = chrono::high_resolution_clock::now();
elapsed = chrono::duration_cast< chrono::nanoseconds >( t2 - t1 ).count();
printf( "trivial unrolled loop elapsed: %d \n", elapsed );
hipMemcpyAsync( d_arr[ i ], h_arr[ i ], perDevNBytes, hipMemcpyHostToDevice, stream[ i ] );
initializeDevice<<< nBlocks, nThreads, 0, stream[ i ] >>>( d_arr[ i ], perDevN );
nop<<< 1, 1 >>>();
t1 = chrono::high_resolution_clock::now();
loop<<< 1, 1, 0, stream[ i ] >>>( d_arr[ i ], i, perDevN );
nop<<< 1, 1 >>>();
t2 = chrono::high_resolution_clock::now();
elapsed = chrono::duration_cast< chrono::nanoseconds >( t2 - t1 ).count();
printf( "loop elapsed: %d \n", elapsed );
t1 = chrono::high_resolution_clock::now();
unrollLoop<<< 1, 1, 0, stream[ i ] >>>( d_arr[ i ], i, perDevN );
nop<<< 1, 1 >>>();
t2 = chrono::high_resolution_clock::now();
elapsed = chrono::duration_cast< chrono::nanoseconds >( t2 - t1 ).count();
printf( "unrolled loop elapsed: %d \n", elapsed );
}
//free memories
for ( i = 0; i < gpuCount; i++ )
{
//HOST
hipHostFree( h_arr[ i ] );
//DEVICE
hipSetDevice( i );
hipFree( d_arr[ i ] );
hipStreamDestroy( stream[ i ] );
}
hipDeviceReset();
return 0;
}
void initalizeHost( float *ip, uint size )
{
for ( size_t i = 0; i < size; i++ )
ip[ i ] = 1.2f;
};
//Post Scriptum: In my professional opinion, coprocessors: GTX1080ti is brand-new and off-the-shell optimal; GTX770 is used optimal - I've heard about R9Nano and HD5770 ( GFLOPS/USD; GFLOPS/W; QualityWithBandwidthAndMemSize/Price; );
//Post Post Scriptum: I do strongly recommend profiling with NVidia's NVPROF profiling tool, instead of CPU high-resolution timer. | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3nopv
.globl _Z3nopv
.p2align 8
.type _Z3nopv,@function
_Z3nopv:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3nopv
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 0
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 0
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 1
.amdhsa_next_free_sgpr 1
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3nopv, .Lfunc_end0-_Z3nopv
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z11trivialLoopv
.globl _Z11trivialLoopv
.p2align 8
.type _Z11trivialLoopv,@function
_Z11trivialLoopv:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11trivialLoopv
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 0
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 0
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 1
.amdhsa_next_free_sgpr 1
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z11trivialLoopv, .Lfunc_end1-_Z11trivialLoopv
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z17unrollTrivialLoopv
.globl _Z17unrollTrivialLoopv
.p2align 8
.type _Z17unrollTrivialLoopv,@function
_Z17unrollTrivialLoopv:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z17unrollTrivialLoopv
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 0
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 0
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 1
.amdhsa_next_free_sgpr 1
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end2:
.size _Z17unrollTrivialLoopv, .Lfunc_end2-_Z17unrollTrivialLoopv
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z16initializeDevicePfj
.globl _Z16initializeDevicePfj
.p2align 8
.type _Z16initializeDevicePfj,@function
_Z16initializeDevicePfj:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x1c
s_load_b32 s3, s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_u32_e64 s3, v1
s_cbranch_execz .LBB3_2
s_load_b64 s[0:1], s[0:1], 0x0
v_mov_b32_e32 v2, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b32 v2, v[0:1], off
s_waitcnt vmcnt(0)
v_mul_f32_e32 v2, 0x3f666666, v2
global_store_b32 v[0:1], v2, off
.LBB3_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z16initializeDevicePfj
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end3:
.size _Z16initializeDevicePfj, .Lfunc_end3-_Z16initializeDevicePfj
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z4loopPfjj
.globl _Z4loopPfjj
.p2align 8
.type _Z4loopPfjj,@function
_Z4loopPfjj:
s_load_b32 s2, s[0:1], 0xc
s_mov_b32 s3, 0
s_waitcnt lgkmcnt(0)
s_cmp_eq_u32 s2, 0
s_cbranch_scc1 .LBB4_3
s_load_b64 s[0:1], s[0:1], 0x0
v_mov_b32_e32 v0, 0
s_mov_b64 s[4:5], 0
.p2align 6
.LBB4_2:
s_waitcnt lgkmcnt(0)
global_load_b32 v1, v0, s[0:1]
s_clz_i32_u32 s6, s5
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_min_u32 s8, s6, 32
s_lshl_b64 s[6:7], s[4:5], s8
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_min_u32 s6, s6, 1
s_or_b32 s6, s7, s6
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_cvt_f32_u32_e32 v2, s6
s_sub_i32 s6, 32, s8
s_add_u32 s4, s4, 1
s_addc_u32 s5, s5, 0
v_ldexp_f32 v2, v2, s6
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_add_f32_e32 v1, v1, v2
global_store_b32 v0, v1, s[0:1]
s_add_u32 s0, s0, 4
s_addc_u32 s1, s1, 0
s_cmp_lg_u64 s[2:3], s[4:5]
s_cbranch_scc1 .LBB4_2
.LBB4_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z4loopPfjj
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 16
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 9
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end4:
.size _Z4loopPfjj, .Lfunc_end4-_Z4loopPfjj
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z10unrollLoopPfjj
.globl _Z10unrollLoopPfjj
.p2align 8
.type _Z10unrollLoopPfjj,@function
_Z10unrollLoopPfjj:
s_load_b32 s8, s[0:1], 0xc
s_waitcnt lgkmcnt(0)
s_cmp_eq_u32 s8, 0
s_cbranch_scc1 .LBB5_7
s_load_b64 s[2:3], s[0:1], 0x0
s_cmp_lt_u32 s8, 16
s_mov_b64 s[0:1], 0
s_cbranch_scc1 .LBB5_4
v_mov_b32_e32 v4, 0
s_and_b32 s4, s8, -16
s_waitcnt lgkmcnt(0)
s_add_u32 s6, s2, 60
s_mov_b32 s5, 0
s_addc_u32 s7, s3, 0
.LBB5_3:
s_clause 0x4
global_load_b128 v[0:3], v4, s[6:7] offset:-60
global_load_b128 v[5:8], v4, s[6:7] offset:-44
global_load_b128 v[9:12], v4, s[6:7] offset:-28
global_load_b96 v[13:15], v4, s[6:7] offset:-12
global_load_b32 v16, v4, s[6:7]
s_clz_i32_u32 s9, s1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_min_u32 s9, s9, 32
s_lshl_b64 s[10:11], s[0:1], s9
s_sub_i32 s9, 32, s9
s_min_u32 s10, s10, 1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
s_or_b32 s11, s11, s10
s_add_u32 s10, s0, 1
v_cvt_f32_u32_e32 v17, s11
s_addc_u32 s11, s1, 0
s_clz_i32_u32 s12, s11
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_min_u32 s12, s12, 32
v_ldexp_f32 v17, v17, s9
s_lshl_b64 s[10:11], s[10:11], s12
s_sub_i32 s9, 32, s12
s_min_u32 s10, s10, 1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
s_or_b32 s11, s11, s10
s_add_u32 s10, s0, 2
v_cvt_f32_u32_e32 v18, s11
s_addc_u32 s11, s1, 0
s_clz_i32_u32 s12, s11
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_min_u32 s12, s12, 32
v_ldexp_f32 v18, v18, s9
s_lshl_b64 s[10:11], s[10:11], s12
s_sub_i32 s9, 32, s12
s_min_u32 s10, s10, 1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
s_or_b32 s11, s11, s10
s_add_u32 s10, s0, 3
v_cvt_f32_u32_e32 v19, s11
s_addc_u32 s11, s1, 0
s_clz_i32_u32 s12, s11
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_min_u32 s12, s12, 32
v_ldexp_f32 v19, v19, s9
s_lshl_b64 s[10:11], s[10:11], s12
s_sub_i32 s9, 32, s12
s_min_u32 s10, s10, 1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
s_or_b32 s11, s11, s10
s_add_u32 s10, s0, 4
v_cvt_f32_u32_e32 v20, s11
s_addc_u32 s11, s1, 0
s_clz_i32_u32 s12, s11
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_min_u32 s12, s12, 32
v_ldexp_f32 v20, v20, s9
s_lshl_b64 s[10:11], s[10:11], s12
s_sub_i32 s9, 32, s12
s_min_u32 s10, s10, 1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
s_or_b32 s11, s11, s10
s_add_u32 s10, s0, 5
v_cvt_f32_u32_e32 v21, s11
s_addc_u32 s11, s1, 0
s_clz_i32_u32 s12, s11
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_min_u32 s12, s12, 32
v_ldexp_f32 v21, v21, s9
s_lshl_b64 s[10:11], s[10:11], s12
s_sub_i32 s9, 32, s12
s_min_u32 s10, s10, 1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
s_or_b32 s11, s11, s10
s_add_u32 s10, s0, 6
v_cvt_f32_u32_e32 v22, s11
s_addc_u32 s11, s1, 0
s_clz_i32_u32 s12, s11
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_min_u32 s12, s12, 32
v_ldexp_f32 v22, v22, s9
s_lshl_b64 s[10:11], s[10:11], s12
s_sub_i32 s9, 32, s12
s_min_u32 s10, s10, 1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
s_or_b32 s11, s11, s10
s_add_u32 s10, s0, 7
v_cvt_f32_u32_e32 v23, s11
s_addc_u32 s11, s1, 0
s_clz_i32_u32 s12, s11
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_min_u32 s12, s12, 32
v_ldexp_f32 v23, v23, s9
s_lshl_b64 s[10:11], s[10:11], s12
s_sub_i32 s9, 32, s12
s_min_u32 s10, s10, 1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
s_or_b32 s11, s11, s10
s_add_u32 s10, s0, 8
v_cvt_f32_u32_e32 v24, s11
s_addc_u32 s11, s1, 0
s_clz_i32_u32 s12, s11
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_min_u32 s12, s12, 32
v_ldexp_f32 v24, v24, s9
s_lshl_b64 s[10:11], s[10:11], s12
s_sub_i32 s9, 32, s12
s_min_u32 s10, s10, 1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
s_or_b32 s11, s11, s10
s_add_u32 s10, s0, 9
v_cvt_f32_u32_e32 v25, s11
s_addc_u32 s11, s1, 0
s_clz_i32_u32 s12, s11
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_min_u32 s12, s12, 32
v_ldexp_f32 v25, v25, s9
s_lshl_b64 s[10:11], s[10:11], s12
s_sub_i32 s9, 32, s12
s_min_u32 s10, s10, 1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
s_or_b32 s11, s11, s10
s_add_u32 s10, s0, 10
v_cvt_f32_u32_e32 v26, s11
s_addc_u32 s11, s1, 0
s_clz_i32_u32 s12, s11
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_min_u32 s12, s12, 32
v_ldexp_f32 v26, v26, s9
s_lshl_b64 s[10:11], s[10:11], s12
s_sub_i32 s9, 32, s12
s_min_u32 s10, s10, 1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
s_or_b32 s11, s11, s10
s_add_u32 s10, s0, 11
v_cvt_f32_u32_e32 v27, s11
s_addc_u32 s11, s1, 0
s_clz_i32_u32 s12, s11
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_min_u32 s12, s12, 32
v_ldexp_f32 v27, v27, s9
s_lshl_b64 s[10:11], s[10:11], s12
s_sub_i32 s9, 32, s12
s_min_u32 s10, s10, 1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
s_or_b32 s11, s11, s10
s_add_u32 s10, s0, 12
v_cvt_f32_u32_e32 v28, s11
s_addc_u32 s11, s1, 0
s_clz_i32_u32 s12, s11
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_min_u32 s12, s12, 32
v_ldexp_f32 v28, v28, s9
s_lshl_b64 s[10:11], s[10:11], s12
s_sub_i32 s9, 32, s12
s_min_u32 s10, s10, 1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
s_or_b32 s11, s11, s10
s_add_u32 s10, s0, 13
v_cvt_f32_u32_e32 v29, s11
s_addc_u32 s11, s1, 0
s_clz_i32_u32 s12, s11
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_min_u32 s12, s12, 32
v_ldexp_f32 v29, v29, s9
s_lshl_b64 s[10:11], s[10:11], s12
s_sub_i32 s9, 32, s12
s_min_u32 s10, s10, 1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
s_or_b32 s11, s11, s10
s_add_u32 s10, s0, 14
v_cvt_f32_u32_e32 v30, s11
s_addc_u32 s11, s1, 0
s_clz_i32_u32 s12, s11
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_min_u32 s12, s12, 32
v_ldexp_f32 v30, v30, s9
s_lshl_b64 s[10:11], s[10:11], s12
s_sub_i32 s9, 32, s12
s_min_u32 s10, s10, 1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
s_or_b32 s11, s11, s10
s_add_u32 s10, s0, 15
v_cvt_f32_u32_e32 v31, s11
s_addc_u32 s11, s1, 0
s_clz_i32_u32 s12, s11
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_min_u32 s12, s12, 32
v_ldexp_f32 v31, v31, s9
s_lshl_b64 s[10:11], s[10:11], s12
s_sub_i32 s9, 32, s12
s_min_u32 s10, s10, 1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
s_or_b32 s10, s11, s10
s_add_u32 s0, s0, 16
v_cvt_f32_u32_e32 v32, s10
s_addc_u32 s1, s1, 0
v_ldexp_f32 v32, v32, s9
s_waitcnt vmcnt(3)
v_dual_add_f32 v2, v2, v19 :: v_dual_add_f32 v5, v5, v21
v_dual_add_f32 v6, v6, v22 :: v_dual_add_f32 v7, v7, v23
s_waitcnt vmcnt(2)
v_dual_add_f32 v8, v8, v24 :: v_dual_add_f32 v9, v9, v25
v_dual_add_f32 v10, v10, v26 :: v_dual_add_f32 v11, v11, v27
s_waitcnt vmcnt(1)
v_dual_add_f32 v12, v12, v28 :: v_dual_add_f32 v13, v13, v29
v_dual_add_f32 v14, v14, v30 :: v_dual_add_f32 v15, v15, v31
v_dual_add_f32 v0, v0, v17 :: v_dual_add_f32 v1, v1, v18
v_add_f32_e32 v3, v3, v20
s_waitcnt vmcnt(0)
v_add_f32_e32 v16, v16, v32
s_clause 0x4
global_store_b128 v4, v[5:8], s[6:7] offset:-44
global_store_b128 v4, v[9:12], s[6:7] offset:-28
global_store_b96 v4, v[13:15], s[6:7] offset:-12
global_store_b128 v4, v[0:3], s[6:7] offset:-60
global_store_b32 v4, v16, s[6:7]
s_add_u32 s6, s6, 64
s_addc_u32 s7, s7, 0
s_cmp_lg_u64 s[0:1], s[4:5]
s_cbranch_scc1 .LBB5_3
.LBB5_4:
s_and_b32 s4, s8, 15
s_mov_b32 s5, 0
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u64 s[4:5], 0
s_cbranch_scc1 .LBB5_7
s_lshl_b64 s[6:7], s[0:1], 2
v_mov_b32_e32 v0, 0
s_waitcnt lgkmcnt(0)
s_add_u32 s2, s2, s6
s_addc_u32 s3, s3, s7
.p2align 6
.LBB5_6:
global_load_b32 v1, v0, s[2:3]
s_clz_i32_u32 s6, s1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_min_u32 s8, s6, 32
s_lshl_b64 s[6:7], s[0:1], s8
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_min_u32 s6, s6, 1
s_or_b32 s6, s7, s6
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_cvt_f32_u32_e32 v2, s6
s_sub_i32 s6, 32, s8
s_add_u32 s0, s0, 1
s_addc_u32 s1, s1, 0
v_ldexp_f32 v2, v2, s6
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_add_f32_e32 v1, v1, v2
global_store_b32 v0, v1, s[2:3]
s_add_u32 s2, s2, 4
s_addc_u32 s3, s3, 0
s_add_u32 s4, s4, -1
s_addc_u32 s5, s5, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lg_u64 s[4:5], 0
s_cbranch_scc1 .LBB5_6
.LBB5_7:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10unrollLoopPfjj
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 16
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 33
.amdhsa_next_free_sgpr 13
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end5:
.size _Z10unrollLoopPfjj, .Lfunc_end5-_Z10unrollLoopPfjj
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args: []
.group_segment_fixed_size: 0
.kernarg_segment_align: 4
.kernarg_segment_size: 0
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3nopv
.private_segment_fixed_size: 0
.sgpr_count: 0
.sgpr_spill_count: 0
.symbol: _Z3nopv.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 0
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args: []
.group_segment_fixed_size: 0
.kernarg_segment_align: 4
.kernarg_segment_size: 0
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11trivialLoopv
.private_segment_fixed_size: 0
.sgpr_count: 0
.sgpr_spill_count: 0
.symbol: _Z11trivialLoopv.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 0
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args: []
.group_segment_fixed_size: 0
.kernarg_segment_align: 4
.kernarg_segment_size: 0
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z17unrollTrivialLoopv
.private_segment_fixed_size: 0
.sgpr_count: 0
.sgpr_spill_count: 0
.symbol: _Z17unrollTrivialLoopv.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 0
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z16initializeDevicePfj
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z16initializeDevicePfj.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 16
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z4loopPfjj
.private_segment_fixed_size: 0
.sgpr_count: 9
.sgpr_spill_count: 0
.symbol: _Z4loopPfjj.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 16
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10unrollLoopPfjj
.private_segment_fixed_size: 0
.sgpr_count: 13
.sgpr_spill_count: 0
.symbol: _Z10unrollLoopPfjj.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 33
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <iostream>
#include <chrono>
using namespace std;
//CPU
typedef unsigned int uint;
uint i = 0;
int gpuCount = 0;
void initalizeHost( float *ip, uint size );
//GPU
hipDeviceProp_t gpuProperties;
const uint N = 1E7;
const uint nThreads = 512;
const uint nBlocks = ( N / nThreads ) + 1;
const uint UNROLLING = 16; //check [ 8 16 32 64 ]; I would guess sixteen times unrolling;
__global__ void nop(){};
__global__ void trivialLoop()
{
uint a = 0;
for ( uint32_t i = 0; i < N; i++ )
{
a = i;
a++;
}
};
__global__ void unrollTrivialLoop()
{
uint a = 0;
#pragma unroll UNROLLING //briliant feature
for ( uint32_t i = 0; i < N; i++ )
{
a = i;
a++;
}
};
__global__ void initializeDevice( float *d_in, const uint streamSize )
{
uint tid = threadIdx.x;
uint idx = blockIdx.x * blockDim.x + tid;
if( idx < streamSize )
{
d_in[ idx ] *= 0.9f;
}
};
__global__ void loop( float *d_in, const uint streamNo, const uint streamSize )
{
size_t ii = 0;
for ( ii = 0; ii < streamSize; ii++ )
{
d_in[ ii ] += float( ii );
}
};
__global__ void unrollLoop( float *d_in, const uint streamNo, const uint streamSize )
{
size_t ii = 0;
#pragma unroll UNROLLING //adjustable mainly to register-only, high performance computations - described at unrollTrivialLoop device kernel
for ( ii = 0; ii < streamSize; ii++ )
{
d_in[ ii ] += float( ii );
}
};
int main( void )
{
hipGetDeviceCount( &gpuCount );
//HOST
float *h_arr[ gpuCount ]; // float **h_arr = ( float** )malloc( sizeof( float * ) * gpuCount ); //alternatively
uint perDevN = N / gpuCount;
uint perDevNBytes = sizeof( float ) * perDevN ;
//DEVICE
hipStream_t stream[ gpuCount ];
float *d_arr[ gpuCount ]; // float **d_arr = ( float** )malloc( sizeof( float * ) * gpuCount ); //alternatively
//alocate & initialize H,D memories
for ( i = 0; i < gpuCount; i++ )
{
//HOST
hipHostMalloc( ( void** ) &h_arr[ i ], perDevNBytes , hipHostMallocDefault);
initalizeHost( h_arr[ i ], perDevN );
//DEVICE
hipSetDevice( i );
hipMalloc( ( void** ) &d_arr[ i ], perDevNBytes );
hipStreamCreate( &stream[ i ] );
}
//DEVICE computations
for ( i = 0; i < gpuCount; i++ )
{
hipSetDevice( i );
hipGetDeviceProperties( &gpuProperties, i );
cout << endl << gpuProperties.name << ": " << endl;
auto t1 = chrono::high_resolution_clock::now();
trivialLoop<<< 1, 1 >>>();
nop<<< 1, 1 >>>();
auto t2 = chrono::high_resolution_clock::now();
uint elapsed = uint( chrono::duration_cast< chrono::nanoseconds >( t2 - t1 ).count() );
printf( "trivial loop elapsed: %d \n", elapsed );
t1 = chrono::high_resolution_clock::now();
unrollTrivialLoop<<< 1, 1 >>>();
nop<<< 1, 1 >>>();
t2 = chrono::high_resolution_clock::now();
elapsed = chrono::duration_cast< chrono::nanoseconds >( t2 - t1 ).count();
printf( "trivial unrolled loop elapsed: %d \n", elapsed );
hipMemcpyAsync( d_arr[ i ], h_arr[ i ], perDevNBytes, hipMemcpyHostToDevice, stream[ i ] );
initializeDevice<<< nBlocks, nThreads, 0, stream[ i ] >>>( d_arr[ i ], perDevN );
nop<<< 1, 1 >>>();
t1 = chrono::high_resolution_clock::now();
loop<<< 1, 1, 0, stream[ i ] >>>( d_arr[ i ], i, perDevN );
nop<<< 1, 1 >>>();
t2 = chrono::high_resolution_clock::now();
elapsed = chrono::duration_cast< chrono::nanoseconds >( t2 - t1 ).count();
printf( "loop elapsed: %d \n", elapsed );
t1 = chrono::high_resolution_clock::now();
unrollLoop<<< 1, 1, 0, stream[ i ] >>>( d_arr[ i ], i, perDevN );
nop<<< 1, 1 >>>();
t2 = chrono::high_resolution_clock::now();
elapsed = chrono::duration_cast< chrono::nanoseconds >( t2 - t1 ).count();
printf( "unrolled loop elapsed: %d \n", elapsed );
}
//free memories
for ( i = 0; i < gpuCount; i++ )
{
//HOST
hipHostFree( h_arr[ i ] );
//DEVICE
hipSetDevice( i );
hipFree( d_arr[ i ] );
hipStreamDestroy( stream[ i ] );
}
hipDeviceReset();
return 0;
}
void initalizeHost( float *ip, uint size )
{
for ( size_t i = 0; i < size; i++ )
ip[ i ] = 1.2f;
};
//Post Scriptum: In my professional opinion, coprocessors: GTX1080ti is brand-new and off-the-shell optimal; GTX770 is used optimal - I've heard about R9Nano and HD5770 ( GFLOPS/USD; GFLOPS/W; QualityWithBandwidthAndMemSize/Price; );
//Post Post Scriptum: I do strongly recommend profiling with NVidia's NVPROF profiling tool, instead of CPU high-resolution timer. | .text
.file "mgpgpu.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z18__device_stub__nopv # -- Begin function _Z18__device_stub__nopv
.p2align 4, 0x90
.type _Z18__device_stub__nopv,@function
_Z18__device_stub__nopv: # @_Z18__device_stub__nopv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z3nopv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z18__device_stub__nopv, .Lfunc_end0-_Z18__device_stub__nopv
.cfi_endproc
# -- End function
.globl _Z26__device_stub__trivialLoopv # -- Begin function _Z26__device_stub__trivialLoopv
.p2align 4, 0x90
.type _Z26__device_stub__trivialLoopv,@function
_Z26__device_stub__trivialLoopv: # @_Z26__device_stub__trivialLoopv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z11trivialLoopv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end1:
.size _Z26__device_stub__trivialLoopv, .Lfunc_end1-_Z26__device_stub__trivialLoopv
.cfi_endproc
# -- End function
.globl _Z32__device_stub__unrollTrivialLoopv # -- Begin function _Z32__device_stub__unrollTrivialLoopv
.p2align 4, 0x90
.type _Z32__device_stub__unrollTrivialLoopv,@function
_Z32__device_stub__unrollTrivialLoopv: # @_Z32__device_stub__unrollTrivialLoopv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z17unrollTrivialLoopv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end2:
.size _Z32__device_stub__unrollTrivialLoopv, .Lfunc_end2-_Z32__device_stub__unrollTrivialLoopv
.cfi_endproc
# -- End function
.globl _Z31__device_stub__initializeDevicePfj # -- Begin function _Z31__device_stub__initializeDevicePfj
.p2align 4, 0x90
.type _Z31__device_stub__initializeDevicePfj,@function
_Z31__device_stub__initializeDevicePfj: # @_Z31__device_stub__initializeDevicePfj
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z16initializeDevicePfj, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end3:
.size _Z31__device_stub__initializeDevicePfj, .Lfunc_end3-_Z31__device_stub__initializeDevicePfj
.cfi_endproc
# -- End function
.globl _Z19__device_stub__loopPfjj # -- Begin function _Z19__device_stub__loopPfjj
.p2align 4, 0x90
.type _Z19__device_stub__loopPfjj,@function
_Z19__device_stub__loopPfjj: # @_Z19__device_stub__loopPfjj
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z4loopPfjj, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end4:
.size _Z19__device_stub__loopPfjj, .Lfunc_end4-_Z19__device_stub__loopPfjj
.cfi_endproc
# -- End function
.globl _Z25__device_stub__unrollLoopPfjj # -- Begin function _Z25__device_stub__unrollLoopPfjj
.p2align 4, 0x90
.type _Z25__device_stub__unrollLoopPfjj,@function
_Z25__device_stub__unrollLoopPfjj: # @_Z25__device_stub__unrollLoopPfjj
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z10unrollLoopPfjj, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end5:
.size _Z25__device_stub__unrollLoopPfjj, .Lfunc_end5-_Z25__device_stub__unrollLoopPfjj
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset %rbp, -16
movq %rsp, %rbp
.cfi_def_cfa_register %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $152, %rsp
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
movl $gpuCount, %edi
callq hipGetDeviceCount
movl gpuCount(%rip), %edi
movq %rsp, %rax
leaq 15(,%rdi,8), %rsi
andq $-16, %rsi
subq %rsi, %rax
movq %rax, %r12
movq %rax, %rsp
xorl %ecx, %ecx
movl $10000000, %eax # imm = 0x989680
xorl %edx, %edx
movq %rdi, -160(%rbp) # 8-byte Spill
divl %edi
# kill: def $eax killed $eax def $rax
movq %rax, -152(%rbp) # 8-byte Spill
leal (,%rax,4), %eax
movq %rsp, %rdx
subq %rsi, %rdx
movq %rdx, %rbx
movq %rdx, %rsp
movq %rsp, %rdx
subq %rsi, %rdx
movq %rdx, %r14
movq %rdx, %rsp
movl $0, i(%rip)
cmpl $0, gpuCount(%rip)
movl %eax, %r13d
movq %r13, -168(%rbp) # 8-byte Spill
je .LBB6_6
# %bb.1: # %.lr.ph
movl -152(%rbp), %r15d # 4-byte Reload
jmp .LBB6_2
.p2align 4, 0x90
.LBB6_5: # %_Z13initalizeHostPfj.exit
# in Loop: Header=BB6_2 Depth=1
# kill: def $edi killed $edi killed $rdi
callq hipSetDevice
movl i(%rip), %eax
leaq (%r14,%rax,8), %rdi
movq -168(%rbp), %r13 # 8-byte Reload
movq %r13, %rsi
callq hipMalloc
movl i(%rip), %eax
leaq (%rbx,%rax,8), %rdi
callq hipStreamCreate
movl i(%rip), %ecx
incl %ecx
movl %ecx, i(%rip)
cmpl gpuCount(%rip), %ecx
jae .LBB6_6
.LBB6_2: # =>This Loop Header: Depth=1
# Child Loop BB6_4 Depth 2
movl %ecx, %eax
leaq (%r12,%rax,8), %rdi
movq %r13, %rsi
xorl %edx, %edx
callq hipHostMalloc
movl i(%rip), %edi
cmpl $10000000, -160(%rbp) # 4-byte Folded Reload
# imm = 0x989680
ja .LBB6_5
# %bb.3: # %.lr.ph.i.preheader
# in Loop: Header=BB6_2 Depth=1
movq (%r12,%rdi,8), %rax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB6_4: # %.lr.ph.i
# Parent Loop BB6_2 Depth=1
# => This Inner Loop Header: Depth=2
movl $1067030938, (%rax,%rcx,4) # imm = 0x3F99999A
incq %rcx
cmpq %rcx, %r15
jne .LBB6_4
jmp .LBB6_5
.LBB6_6: # %.preheader212
movl $0, i(%rip)
cmpl $0, gpuCount(%rip)
movq %r14, %r13
movq %rbx, %r14
je .LBB6_10
# %bb.7: # %.lr.ph215
movabsq $4294967297, %r15 # imm = 0x100000001
leaq 511(%r15), %rax
movq %rax, -184(%rbp) # 8-byte Spill
leaq 19531(%r15), %rax
movq %rax, -176(%rbp) # 8-byte Spill
xorl %edi, %edi
movq %r12, -160(%rbp) # 8-byte Spill
jmp .LBB6_8
.p2align 4, 0x90
.LBB6_41: # in Loop: Header=BB6_8 Depth=1
callq _ZNSt6chrono3_V212system_clock3nowEv
subl %ebx, %eax
movl $.L.str.4, %edi
movl %eax, %esi
xorl %eax, %eax
callq printf
movl i(%rip), %edi
incl %edi
movl %edi, i(%rip)
cmpl gpuCount(%rip), %edi
jae .LBB6_10
.LBB6_8: # =>This Inner Loop Header: Depth=1
callq hipSetDevice
movl i(%rip), %esi
movl $gpuProperties, %edi
callq hipGetDevicePropertiesR0600
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB6_9
# %bb.14: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
# in Loop: Header=BB6_8 Depth=1
cmpb $0, 56(%rbx)
je .LBB6_16
# %bb.15: # in Loop: Header=BB6_8 Depth=1
movzbl 67(%rbx), %eax
jmp .LBB6_17
.p2align 4, 0x90
.LBB6_16: # in Loop: Header=BB6_8 Depth=1
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB6_17: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
# in Loop: Header=BB6_8 Depth=1
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq %rax, %rbx
movl $gpuProperties, %edi
callq strlen
movl $gpuProperties, %esi
movq %rbx, %rdi
movq %rax, %rdx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $.L.str, %esi
movl $2, %edx
movq %rbx, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%rbx), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r12
testq %r12, %r12
je .LBB6_9
# %bb.18: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i135
# in Loop: Header=BB6_8 Depth=1
cmpb $0, 56(%r12)
je .LBB6_20
# %bb.19: # in Loop: Header=BB6_8 Depth=1
movzbl 67(%r12), %eax
jmp .LBB6_21
.p2align 4, 0x90
.LBB6_20: # in Loop: Header=BB6_8 Depth=1
movq %r12, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r12), %rax
movq %r12, %rdi
movl $10, %esi
callq *48(%rax)
.LBB6_21: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit138
# in Loop: Header=BB6_8 Depth=1
movsbl %al, %esi
movq %rbx, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
callq _ZNSt6chrono3_V212system_clock3nowEv
movq %rax, %rbx
movq %r15, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
movq -160(%rbp), %r12 # 8-byte Reload
jne .LBB6_23
# %bb.22: # in Loop: Header=BB6_8 Depth=1
leaq -128(%rbp), %rdi
leaq -64(%rbp), %rsi
leaq -80(%rbp), %rdx
leaq -48(%rbp), %rcx
callq __hipPopCallConfiguration
movq -128(%rbp), %rsi
movl -120(%rbp), %edx
movq -64(%rbp), %rcx
movl -56(%rbp), %r8d
movl $_Z11trivialLoopv, %edi
leaq -96(%rbp), %r9
pushq -48(%rbp)
pushq -80(%rbp)
callq hipLaunchKernel
addq $16, %rsp
.LBB6_23: # in Loop: Header=BB6_8 Depth=1
movq %r15, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB6_25
# %bb.24: # in Loop: Header=BB6_8 Depth=1
leaq -128(%rbp), %rdi
leaq -64(%rbp), %rsi
leaq -80(%rbp), %rdx
leaq -48(%rbp), %rcx
callq __hipPopCallConfiguration
movq -128(%rbp), %rsi
movl -120(%rbp), %edx
movq -64(%rbp), %rcx
movl -56(%rbp), %r8d
movl $_Z3nopv, %edi
leaq -96(%rbp), %r9
pushq -48(%rbp)
pushq -80(%rbp)
callq hipLaunchKernel
addq $16, %rsp
.LBB6_25: # in Loop: Header=BB6_8 Depth=1
callq _ZNSt6chrono3_V212system_clock3nowEv
subl %ebx, %eax
movl $.L.str.1, %edi
movl %eax, %esi
xorl %eax, %eax
callq printf
callq _ZNSt6chrono3_V212system_clock3nowEv
movq %rax, %rbx
movq %r15, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB6_27
# %bb.26: # in Loop: Header=BB6_8 Depth=1
leaq -128(%rbp), %rdi
leaq -64(%rbp), %rsi
leaq -80(%rbp), %rdx
leaq -48(%rbp), %rcx
callq __hipPopCallConfiguration
movq -128(%rbp), %rsi
movl -120(%rbp), %edx
movq -64(%rbp), %rcx
movl -56(%rbp), %r8d
movl $_Z17unrollTrivialLoopv, %edi
leaq -96(%rbp), %r9
pushq -48(%rbp)
pushq -80(%rbp)
callq hipLaunchKernel
addq $16, %rsp
.LBB6_27: # in Loop: Header=BB6_8 Depth=1
movq %r15, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB6_29
# %bb.28: # in Loop: Header=BB6_8 Depth=1
leaq -128(%rbp), %rdi
leaq -64(%rbp), %rsi
leaq -80(%rbp), %rdx
leaq -48(%rbp), %rcx
callq __hipPopCallConfiguration
movq -128(%rbp), %rsi
movl -120(%rbp), %edx
movq -64(%rbp), %rcx
movl -56(%rbp), %r8d
movl $_Z3nopv, %edi
leaq -96(%rbp), %r9
pushq -48(%rbp)
pushq -80(%rbp)
callq hipLaunchKernel
addq $16, %rsp
.LBB6_29: # in Loop: Header=BB6_8 Depth=1
callq _ZNSt6chrono3_V212system_clock3nowEv
subl %ebx, %eax
movl $.L.str.2, %edi
movl %eax, %esi
xorl %eax, %eax
callq printf
movl i(%rip), %eax
movq (%r13,%rax,8), %rdi
movq (%r12,%rax,8), %rsi
movq (%r14,%rax,8), %r8
movq -168(%rbp), %rdx # 8-byte Reload
movl $1, %ecx
callq hipMemcpyAsync
movl i(%rip), %eax
movq (%r14,%rax,8), %r9
movq -176(%rbp), %rdi # 8-byte Reload
movl $1, %esi
movq -184(%rbp), %rdx # 8-byte Reload
movl $1, %ecx
xorl %r8d, %r8d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB6_31
# %bb.30: # in Loop: Header=BB6_8 Depth=1
movl i(%rip), %eax
movq (%r13,%rax,8), %rax
movq %rax, -48(%rbp)
movq -152(%rbp), %rax # 8-byte Reload
movl %eax, -100(%rbp)
leaq -48(%rbp), %rax
movq %rax, -128(%rbp)
leaq -100(%rbp), %rax
movq %rax, -120(%rbp)
leaq -64(%rbp), %rdi
leaq -80(%rbp), %rsi
leaq -96(%rbp), %rdx
leaq -144(%rbp), %rcx
callq __hipPopCallConfiguration
movq -64(%rbp), %rsi
movl -56(%rbp), %edx
movq -80(%rbp), %rcx
movl -72(%rbp), %r8d
movl $_Z16initializeDevicePfj, %edi
leaq -128(%rbp), %r9
pushq -144(%rbp)
pushq -96(%rbp)
callq hipLaunchKernel
addq $16, %rsp
.LBB6_31: # in Loop: Header=BB6_8 Depth=1
movq %r15, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB6_33
# %bb.32: # in Loop: Header=BB6_8 Depth=1
leaq -128(%rbp), %rdi
leaq -64(%rbp), %rsi
leaq -80(%rbp), %rdx
leaq -48(%rbp), %rcx
callq __hipPopCallConfiguration
movq -128(%rbp), %rsi
movl -120(%rbp), %edx
movq -64(%rbp), %rcx
movl -56(%rbp), %r8d
movl $_Z3nopv, %edi
leaq -96(%rbp), %r9
pushq -48(%rbp)
pushq -80(%rbp)
callq hipLaunchKernel
addq $16, %rsp
.LBB6_33: # in Loop: Header=BB6_8 Depth=1
callq _ZNSt6chrono3_V212system_clock3nowEv
movq %rax, %rbx
movl i(%rip), %eax
movq (%r14,%rax,8), %r9
movq %r15, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB6_35
# %bb.34: # in Loop: Header=BB6_8 Depth=1
movl i(%rip), %eax
movq (%r13,%rax,8), %rcx
movq %rcx, -48(%rbp)
movl %eax, -100(%rbp)
movq -152(%rbp), %rax # 8-byte Reload
movl %eax, -132(%rbp)
leaq -48(%rbp), %rax
movq %rax, -128(%rbp)
leaq -100(%rbp), %rax
movq %rax, -120(%rbp)
leaq -132(%rbp), %rax
movq %rax, -112(%rbp)
leaq -64(%rbp), %rdi
leaq -80(%rbp), %rsi
leaq -96(%rbp), %rdx
leaq -144(%rbp), %rcx
callq __hipPopCallConfiguration
movq -64(%rbp), %rsi
movl -56(%rbp), %edx
movq -80(%rbp), %rcx
movl -72(%rbp), %r8d
movl $_Z4loopPfjj, %edi
leaq -128(%rbp), %r9
pushq -144(%rbp)
pushq -96(%rbp)
callq hipLaunchKernel
addq $16, %rsp
.LBB6_35: # in Loop: Header=BB6_8 Depth=1
movq %r15, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB6_37
# %bb.36: # in Loop: Header=BB6_8 Depth=1
leaq -128(%rbp), %rdi
leaq -64(%rbp), %rsi
leaq -80(%rbp), %rdx
leaq -48(%rbp), %rcx
callq __hipPopCallConfiguration
movq -128(%rbp), %rsi
movl -120(%rbp), %edx
movq -64(%rbp), %rcx
movl -56(%rbp), %r8d
movl $_Z3nopv, %edi
leaq -96(%rbp), %r9
pushq -48(%rbp)
pushq -80(%rbp)
callq hipLaunchKernel
addq $16, %rsp
.LBB6_37: # in Loop: Header=BB6_8 Depth=1
callq _ZNSt6chrono3_V212system_clock3nowEv
subl %ebx, %eax
movl $.L.str.3, %edi
movl %eax, %esi
xorl %eax, %eax
callq printf
callq _ZNSt6chrono3_V212system_clock3nowEv
movq %rax, %rbx
movl i(%rip), %eax
movq (%r14,%rax,8), %r9
movq %r15, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB6_39
# %bb.38: # in Loop: Header=BB6_8 Depth=1
movl i(%rip), %eax
movq (%r13,%rax,8), %rcx
movq %rcx, -48(%rbp)
movl %eax, -100(%rbp)
movq -152(%rbp), %rax # 8-byte Reload
movl %eax, -132(%rbp)
leaq -48(%rbp), %rax
movq %rax, -128(%rbp)
leaq -100(%rbp), %rax
movq %rax, -120(%rbp)
leaq -132(%rbp), %rax
movq %rax, -112(%rbp)
leaq -64(%rbp), %rdi
leaq -80(%rbp), %rsi
leaq -96(%rbp), %rdx
leaq -144(%rbp), %rcx
callq __hipPopCallConfiguration
movq -64(%rbp), %rsi
movl -56(%rbp), %edx
movq -80(%rbp), %rcx
movl -72(%rbp), %r8d
movl $_Z10unrollLoopPfjj, %edi
leaq -128(%rbp), %r9
pushq -144(%rbp)
pushq -96(%rbp)
callq hipLaunchKernel
addq $16, %rsp
.LBB6_39: # in Loop: Header=BB6_8 Depth=1
movq %r15, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB6_41
# %bb.40: # in Loop: Header=BB6_8 Depth=1
leaq -128(%rbp), %rdi
leaq -64(%rbp), %rsi
leaq -80(%rbp), %rdx
leaq -48(%rbp), %rcx
callq __hipPopCallConfiguration
movq -128(%rbp), %rsi
movl -120(%rbp), %edx
movq -64(%rbp), %rcx
movl -56(%rbp), %r8d
movl $_Z3nopv, %edi
leaq -96(%rbp), %r9
pushq -48(%rbp)
pushq -80(%rbp)
callq hipLaunchKernel
addq $16, %rsp
jmp .LBB6_41
.LBB6_10: # %.preheader
movl $0, i(%rip)
cmpl $0, gpuCount(%rip)
je .LBB6_13
# %bb.11: # %.lr.ph217.preheader
xorl %eax, %eax
.p2align 4, 0x90
.LBB6_12: # %.lr.ph217
# =>This Inner Loop Header: Depth=1
movl %eax, %eax
movq (%r12,%rax,8), %rdi
callq hipHostFree
movl i(%rip), %edi
callq hipSetDevice
movl i(%rip), %eax
movq (%r13,%rax,8), %rdi
callq hipFree
movl i(%rip), %eax
movq (%r14,%rax,8), %rdi
callq hipStreamDestroy
movl i(%rip), %eax
incl %eax
movl %eax, i(%rip)
cmpl gpuCount(%rip), %eax
jb .LBB6_12
.LBB6_13: # %._crit_edge
callq hipDeviceReset
xorl %eax, %eax
leaq -40(%rbp), %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
.cfi_def_cfa %rsp, 8
retq
.LBB6_9:
.cfi_def_cfa %rbp, 16
callq _ZSt16__throw_bad_castv
.Lfunc_end6:
.size main, .Lfunc_end6-main
.cfi_endproc
# -- End function
.globl _Z13initalizeHostPfj # -- Begin function _Z13initalizeHostPfj
.p2align 4, 0x90
.type _Z13initalizeHostPfj,@function
_Z13initalizeHostPfj: # @_Z13initalizeHostPfj
.cfi_startproc
# %bb.0:
testl %esi, %esi
je .LBB7_3
# %bb.1: # %.lr.ph.preheader
movl %esi, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB7_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl $1067030938, (%rdi,%rcx,4) # imm = 0x3F99999A
incq %rcx
cmpq %rcx, %rax
jne .LBB7_2
.LBB7_3: # %._crit_edge
retq
.Lfunc_end7:
.size _Z13initalizeHostPfj, .Lfunc_end7-_Z13initalizeHostPfj
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB8_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB8_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3nopv, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11trivialLoopv, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z17unrollTrivialLoopv, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z16initializeDevicePfj, %esi
movl $.L__unnamed_4, %edx
movl $.L__unnamed_4, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z4loopPfjj, %esi
movl $.L__unnamed_5, %edx
movl $.L__unnamed_5, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10unrollLoopPfjj, %esi
movl $.L__unnamed_6, %edx
movl $.L__unnamed_6, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end8:
.size __hip_module_ctor, .Lfunc_end8-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB9_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB9_2:
retq
.Lfunc_end9:
.size __hip_module_dtor, .Lfunc_end9-__hip_module_dtor
.cfi_endproc
# -- End function
.type i,@object # @i
.bss
.globl i
.p2align 2, 0x0
i:
.long 0 # 0x0
.size i, 4
.type gpuCount,@object # @gpuCount
.globl gpuCount
.p2align 2, 0x0
gpuCount:
.long 0 # 0x0
.size gpuCount, 4
.type gpuProperties,@object # @gpuProperties
.globl gpuProperties
.p2align 3, 0x0
gpuProperties:
.zero 1472
.size gpuProperties, 1472
.type _Z3nopv,@object # @_Z3nopv
.section .rodata,"a",@progbits
.globl _Z3nopv
.p2align 3, 0x0
_Z3nopv:
.quad _Z18__device_stub__nopv
.size _Z3nopv, 8
.type _Z11trivialLoopv,@object # @_Z11trivialLoopv
.globl _Z11trivialLoopv
.p2align 3, 0x0
_Z11trivialLoopv:
.quad _Z26__device_stub__trivialLoopv
.size _Z11trivialLoopv, 8
.type _Z17unrollTrivialLoopv,@object # @_Z17unrollTrivialLoopv
.globl _Z17unrollTrivialLoopv
.p2align 3, 0x0
_Z17unrollTrivialLoopv:
.quad _Z32__device_stub__unrollTrivialLoopv
.size _Z17unrollTrivialLoopv, 8
.type _Z16initializeDevicePfj,@object # @_Z16initializeDevicePfj
.globl _Z16initializeDevicePfj
.p2align 3, 0x0
_Z16initializeDevicePfj:
.quad _Z31__device_stub__initializeDevicePfj
.size _Z16initializeDevicePfj, 8
.type _Z4loopPfjj,@object # @_Z4loopPfjj
.globl _Z4loopPfjj
.p2align 3, 0x0
_Z4loopPfjj:
.quad _Z19__device_stub__loopPfjj
.size _Z4loopPfjj, 8
.type _Z10unrollLoopPfjj,@object # @_Z10unrollLoopPfjj
.globl _Z10unrollLoopPfjj
.p2align 3, 0x0
_Z10unrollLoopPfjj:
.quad _Z25__device_stub__unrollLoopPfjj
.size _Z10unrollLoopPfjj, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz ": "
.size .L.str, 3
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "trivial loop elapsed: %d \n"
.size .L.str.1, 27
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "trivial unrolled loop elapsed: %d \n"
.size .L.str.2, 36
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "loop elapsed: %d \n"
.size .L.str.3, 19
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "unrolled loop elapsed: %d \n"
.size .L.str.4, 28
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z3nopv"
.size .L__unnamed_1, 8
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z11trivialLoopv"
.size .L__unnamed_2, 17
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z17unrollTrivialLoopv"
.size .L__unnamed_3, 23
.type .L__unnamed_4,@object # @3
.L__unnamed_4:
.asciz "_Z16initializeDevicePfj"
.size .L__unnamed_4, 24
.type .L__unnamed_5,@object # @4
.L__unnamed_5:
.asciz "_Z4loopPfjj"
.size .L__unnamed_5, 12
.type .L__unnamed_6,@object # @5
.L__unnamed_6:
.asciz "_Z10unrollLoopPfjj"
.size .L__unnamed_6, 19
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__nopv
.addrsig_sym _Z26__device_stub__trivialLoopv
.addrsig_sym _Z32__device_stub__unrollTrivialLoopv
.addrsig_sym _Z31__device_stub__initializeDevicePfj
.addrsig_sym _Z19__device_stub__loopPfjj
.addrsig_sym _Z25__device_stub__unrollLoopPfjj
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym gpuCount
.addrsig_sym gpuProperties
.addrsig_sym _Z3nopv
.addrsig_sym _Z11trivialLoopv
.addrsig_sym _Z17unrollTrivialLoopv
.addrsig_sym _Z16initializeDevicePfj
.addrsig_sym _Z4loopPfjj
.addrsig_sym _Z10unrollLoopPfjj
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void ComputeSpeQtyKernel (double *Label, double *Dens, double *ExtLabel, int nrad, int nsec)
{
int j = threadIdx.x + blockDim.x*blockIdx.x;
int i = threadIdx.y + blockDim.y*blockIdx.y;
if (i<nrad && j<nsec){
Label[i*nsec + j] = ExtLabel[i*nsec + j]/Dens[i*nsec + j];
/* Compressive flow if line commentarized
Label[i*nsec + j] = ExtLabel[i*nsec + j] */
}
} | code for sm_80
Function : _Z19ComputeSpeQtyKernelPdS_S_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R10, SR_TID.X ; /* 0x00000000000a7919 */
/* 0x000e280000002100 */
/*0020*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e280000002500 */
/*0030*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e680000002600 */
/*0040*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e620000002200 */
/*0050*/ IMAD R10, R3, c[0x0][0x0], R10 ; /* 0x00000000030a7a24 */
/* 0x001fca00078e020a */
/*0060*/ ISETP.GE.AND P0, PT, R10, c[0x0][0x17c], PT ; /* 0x00005f000a007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R3, R0, c[0x0][0x4], R5 ; /* 0x0000010000037a24 */
/* 0x002fca00078e0205 */
/*0080*/ ISETP.GE.OR P0, PT, R3, c[0x0][0x178], P0 ; /* 0x00005e0003007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ IMAD.MOV.U32 R5, RZ, RZ, 0x8 ; /* 0x00000008ff057424 */
/* 0x000fe200078e00ff */
/*00b0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00c0*/ IMAD R10, R3, c[0x0][0x17c], R10 ; /* 0x00005f00030a7a24 */
/* 0x000fc800078e020a */
/*00d0*/ IMAD.WIDE R6, R10, R5, c[0x0][0x168] ; /* 0x00005a000a067625 */
/* 0x000fcc00078e0205 */
/*00e0*/ LDG.E.64 R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000ea2000c1e1b00 */
/*00f0*/ IMAD.WIDE R4, R10, R5, c[0x0][0x170] ; /* 0x00005c000a047625 */
/* 0x000fcc00078e0205 */
/*0100*/ LDG.E.64 R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ee2000c1e1b00 */
/*0110*/ IMAD.MOV.U32 R2, RZ, RZ, 0x1 ; /* 0x00000001ff027424 */
/* 0x000fe200078e00ff */
/*0120*/ BSSY B0, 0x250 ; /* 0x0000012000007945 */
/* 0x000fe20003800000 */
/*0130*/ MUFU.RCP64H R3, R7 ; /* 0x0000000700037308 */
/* 0x004e220000001800 */
/*0140*/ FSETP.GEU.AND P1, PT, |R5|, 6.5827683646048100446e-37, PT ; /* 0x036000000500780b */
/* 0x008fc60003f2e200 */
/*0150*/ DFMA R8, -R6, R2, 1 ; /* 0x3ff000000608742b */
/* 0x001e0c0000000102 */
/*0160*/ DFMA R8, R8, R8, R8 ; /* 0x000000080808722b */
/* 0x001e0c0000000008 */
/*0170*/ DFMA R8, R2, R8, R2 ; /* 0x000000080208722b */
/* 0x001e0c0000000002 */
/*0180*/ DFMA R2, -R6, R8, 1 ; /* 0x3ff000000602742b */
/* 0x001e0c0000000108 */
/*0190*/ DFMA R2, R8, R2, R8 ; /* 0x000000020802722b */
/* 0x001e0c0000000008 */
/*01a0*/ DMUL R8, R4, R2 ; /* 0x0000000204087228 */
/* 0x001e0c0000000000 */
/*01b0*/ DFMA R12, -R6, R8, R4 ; /* 0x00000008060c722b */
/* 0x001e0c0000000104 */
/*01c0*/ DFMA R2, R2, R12, R8 ; /* 0x0000000c0202722b */
/* 0x001e140000000008 */
/*01d0*/ FFMA R0, RZ, R7, R3 ; /* 0x00000007ff007223 */
/* 0x001fca0000000003 */
/*01e0*/ FSETP.GT.AND P0, PT, |R0|, 1.469367938527859385e-39, PT ; /* 0x001000000000780b */
/* 0x000fda0003f04200 */
/*01f0*/ @P0 BRA P1, 0x240 ; /* 0x0000004000000947 */
/* 0x000fea0000800000 */
/*0200*/ MOV R0, 0x220 ; /* 0x0000022000007802 */
/* 0x000fe40000000f00 */
/*0210*/ CALL.REL.NOINC 0x290 ; /* 0x0000007000007944 */
/* 0x000fea0003c00000 */
/*0220*/ IMAD.MOV.U32 R2, RZ, RZ, R12 ; /* 0x000000ffff027224 */
/* 0x000fe400078e000c */
/*0230*/ IMAD.MOV.U32 R3, RZ, RZ, R13 ; /* 0x000000ffff037224 */
/* 0x000fe400078e000d */
/*0240*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0250*/ IMAD.MOV.U32 R11, RZ, RZ, 0x8 ; /* 0x00000008ff0b7424 */
/* 0x000fc800078e00ff */
/*0260*/ IMAD.WIDE R10, R10, R11, c[0x0][0x160] ; /* 0x000058000a0a7625 */
/* 0x000fca00078e020b */
/*0270*/ STG.E.64 [R10.64], R2 ; /* 0x000000020a007986 */
/* 0x000fe2000c101b04 */
/*0280*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0290*/ FSETP.GEU.AND P0, PT, |R7|.reuse, 1.469367938527859385e-39, PT ; /* 0x001000000700780b */
/* 0x040fe20003f0e200 */
/*02a0*/ IMAD.MOV.U32 R12, RZ, RZ, 0x1ca00000 ; /* 0x1ca00000ff0c7424 */
/* 0x000fe200078e00ff */
/*02b0*/ LOP3.LUT R2, R7, 0x800fffff, RZ, 0xc0, !PT ; /* 0x800fffff07027812 */
/* 0x000fe200078ec0ff */
/*02c0*/ IMAD.MOV.U32 R14, RZ, RZ, 0x1 ; /* 0x00000001ff0e7424 */
/* 0x000fe200078e00ff */
/*02d0*/ FSETP.GEU.AND P2, PT, |R5|.reuse, 1.469367938527859385e-39, PT ; /* 0x001000000500780b */
/* 0x040fe20003f4e200 */
/*02e0*/ BSSY B1, 0x820 ; /* 0x0000053000017945 */
/* 0x000fe20003800000 */
/*02f0*/ LOP3.LUT R3, R2, 0x3ff00000, RZ, 0xfc, !PT ; /* 0x3ff0000002037812 */
/* 0x000fe200078efcff */
/*0300*/ IMAD.MOV.U32 R2, RZ, RZ, R6 ; /* 0x000000ffff027224 */
/* 0x000fe200078e0006 */
/*0310*/ LOP3.LUT R11, R5, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff00000050b7812 */
/* 0x000fe400078ec0ff */
/*0320*/ LOP3.LUT R16, R7, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff0000007107812 */
/* 0x000fc600078ec0ff */
/*0330*/ @!P0 DMUL R2, R6, 8.98846567431157953865e+307 ; /* 0x7fe0000006028828 */
/* 0x000e220000000000 */
/*0340*/ ISETP.GE.U32.AND P1, PT, R11, R16, PT ; /* 0x000000100b00720c */
/* 0x000fe20003f26070 */
/*0350*/ IMAD.MOV.U32 R17, RZ, RZ, R11 ; /* 0x000000ffff117224 */
/* 0x000fe400078e000b */
/*0360*/ @!P2 LOP3.LUT R8, R7, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff000000708a812 */
/* 0x000fe200078ec0ff */
/*0370*/ @!P2 IMAD.MOV.U32 R20, RZ, RZ, RZ ; /* 0x000000ffff14a224 */
/* 0x000fe200078e00ff */
/*0380*/ MUFU.RCP64H R15, R3 ; /* 0x00000003000f7308 */
/* 0x001e220000001800 */
/*0390*/ SEL R9, R12, 0x63400000, !P1 ; /* 0x634000000c097807 */
/* 0x000fe40004800000 */
/*03a0*/ @!P2 ISETP.GE.U32.AND P3, PT, R11, R8, PT ; /* 0x000000080b00a20c */
/* 0x000fe20003f66070 */
/*03b0*/ IMAD.MOV.U32 R8, RZ, RZ, R4 ; /* 0x000000ffff087224 */
/* 0x000fe200078e0004 */
/*03c0*/ LOP3.LUT R9, R9, 0x800fffff, R5, 0xf8, !PT ; /* 0x800fffff09097812 */
/* 0x000fc400078ef805 */
/*03d0*/ @!P2 SEL R13, R12, 0x63400000, !P3 ; /* 0x634000000c0da807 */
/* 0x000fe40005800000 */
/*03e0*/ @!P0 LOP3.LUT R16, R3, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff0000003108812 */
/* 0x000fe400078ec0ff */
/*03f0*/ @!P2 LOP3.LUT R13, R13, 0x80000000, R5, 0xf8, !PT ; /* 0x800000000d0da812 */
/* 0x000fe400078ef805 */
/*0400*/ IADD3 R22, R16, -0x1, RZ ; /* 0xffffffff10167810 */
/* 0x000fe40007ffe0ff */
/*0410*/ @!P2 LOP3.LUT R21, R13, 0x100000, RZ, 0xfc, !PT ; /* 0x001000000d15a812 */
/* 0x000fe200078efcff */
/*0420*/ DFMA R18, R14, -R2, 1 ; /* 0x3ff000000e12742b */
/* 0x001e0a0000000802 */
/*0430*/ @!P2 DFMA R8, R8, 2, -R20 ; /* 0x400000000808a82b */
/* 0x000fc80000000814 */
/*0440*/ DFMA R18, R18, R18, R18 ; /* 0x000000121212722b */
/* 0x001e0c0000000012 */
/*0450*/ DFMA R14, R14, R18, R14 ; /* 0x000000120e0e722b */
/* 0x001e22000000000e */
/*0460*/ @!P2 LOP3.LUT R17, R9, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff000000911a812 */
/* 0x000fc800078ec0ff */
/*0470*/ IADD3 R13, R17, -0x1, RZ ; /* 0xffffffff110d7810 */
/* 0x000fe20007ffe0ff */
/*0480*/ DFMA R18, R14, -R2, 1 ; /* 0x3ff000000e12742b */
/* 0x001e060000000802 */
/*0490*/ ISETP.GT.U32.AND P0, PT, R13, 0x7feffffe, PT ; /* 0x7feffffe0d00780c */
/* 0x000fc60003f04070 */
/*04a0*/ DFMA R14, R14, R18, R14 ; /* 0x000000120e0e722b */
/* 0x001e22000000000e */
/*04b0*/ ISETP.GT.U32.OR P0, PT, R22, 0x7feffffe, P0 ; /* 0x7feffffe1600780c */
/* 0x000fca0000704470 */
/*04c0*/ DMUL R18, R14, R8 ; /* 0x000000080e127228 */
/* 0x001e0c0000000000 */
/*04d0*/ DFMA R20, R18, -R2, R8 ; /* 0x800000021214722b */
/* 0x001e0c0000000008 */
/*04e0*/ DFMA R14, R14, R20, R18 ; /* 0x000000140e0e722b */
/* 0x0010620000000012 */
/*04f0*/ @P0 BRA 0x6c0 ; /* 0x000001c000000947 */
/* 0x000fea0003800000 */
/*0500*/ LOP3.LUT R16, R7, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff0000007107812 */
/* 0x000fc800078ec0ff */
/*0510*/ ISETP.GE.U32.AND P0, PT, R11.reuse, R16, PT ; /* 0x000000100b00720c */
/* 0x040fe20003f06070 */
/*0520*/ IMAD.IADD R4, R11, 0x1, -R16 ; /* 0x000000010b047824 */
/* 0x000fc600078e0a10 */
/*0530*/ SEL R11, R12, 0x63400000, !P0 ; /* 0x634000000c0b7807 */
/* 0x000fe40004000000 */
/*0540*/ IMNMX R4, R4, -0x46a00000, !PT ; /* 0xb960000004047817 */
/* 0x000fc80007800200 */
/*0550*/ IMNMX R4, R4, 0x46a00000, PT ; /* 0x46a0000004047817 */
/* 0x000fca0003800200 */
/*0560*/ IMAD.IADD R11, R4, 0x1, -R11 ; /* 0x00000001040b7824 */
/* 0x000fe400078e0a0b */
/*0570*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x000fc600078e00ff */
/*0580*/ IADD3 R5, R11, 0x7fe00000, RZ ; /* 0x7fe000000b057810 */
/* 0x000fcc0007ffe0ff */
/*0590*/ DMUL R12, R14, R4 ; /* 0x000000040e0c7228 */
/* 0x002e540000000000 */
/*05a0*/ FSETP.GTU.AND P0, PT, |R13|, 1.469367938527859385e-39, PT ; /* 0x001000000d00780b */
/* 0x002fda0003f0c200 */
/*05b0*/ @P0 BRA 0x810 ; /* 0x0000025000000947 */
/* 0x000fea0003800000 */
/*05c0*/ DFMA R2, R14, -R2, R8 ; /* 0x800000020e02722b */
/* 0x000e620000000008 */
/*05d0*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x000fd200078e00ff */
/*05e0*/ FSETP.NEU.AND P0, PT, R3.reuse, RZ, PT ; /* 0x000000ff0300720b */
/* 0x042fe40003f0d000 */
/*05f0*/ LOP3.LUT R7, R3, 0x80000000, R7, 0x48, !PT ; /* 0x8000000003077812 */
/* 0x000fc800078e4807 */
/*0600*/ LOP3.LUT R5, R7, R5, RZ, 0xfc, !PT ; /* 0x0000000507057212 */
/* 0x000fce00078efcff */
/*0610*/ @!P0 BRA 0x810 ; /* 0x000001f000008947 */
/* 0x000fea0003800000 */
/*0620*/ IMAD.MOV R3, RZ, RZ, -R11 ; /* 0x000000ffff037224 */
/* 0x000fe200078e0a0b */
/*0630*/ DMUL.RP R4, R14, R4 ; /* 0x000000040e047228 */
/* 0x000e620000008000 */
/*0640*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x000fe200078e00ff */
/*0650*/ IADD3 R11, -R11, -0x43300000, RZ ; /* 0xbcd000000b0b7810 */
/* 0x000fca0007ffe1ff */
/*0660*/ DFMA R2, R12, -R2, R14 ; /* 0x800000020c02722b */
/* 0x000e86000000000e */
/*0670*/ LOP3.LUT R7, R5, R7, RZ, 0x3c, !PT ; /* 0x0000000705077212 */
/* 0x002fce00078e3cff */
/*0680*/ FSETP.NEU.AND P0, PT, |R3|, R11, PT ; /* 0x0000000b0300720b */
/* 0x004fc80003f0d200 */
/*0690*/ FSEL R12, R4, R12, !P0 ; /* 0x0000000c040c7208 */
/* 0x000fe40004000000 */
/*06a0*/ FSEL R13, R7, R13, !P0 ; /* 0x0000000d070d7208 */
/* 0x000fe20004000000 */
/*06b0*/ BRA 0x810 ; /* 0x0000015000007947 */
/* 0x000fea0003800000 */
/*06c0*/ DSETP.NAN.AND P0, PT, R4, R4, PT ; /* 0x000000040400722a */
/* 0x000e9c0003f08000 */
/*06d0*/ @P0 BRA 0x7f0 ; /* 0x0000011000000947 */
/* 0x004fea0003800000 */
/*06e0*/ DSETP.NAN.AND P0, PT, R6, R6, PT ; /* 0x000000060600722a */
/* 0x000e9c0003f08000 */
/*06f0*/ @P0 BRA 0x7c0 ; /* 0x000000c000000947 */
/* 0x004fea0003800000 */
/*0700*/ ISETP.NE.AND P0, PT, R17, R16, PT ; /* 0x000000101100720c */
/* 0x000fe20003f05270 */
/*0710*/ IMAD.MOV.U32 R12, RZ, RZ, 0x0 ; /* 0x00000000ff0c7424 */
/* 0x000fe400078e00ff */
/*0720*/ IMAD.MOV.U32 R13, RZ, RZ, -0x80000 ; /* 0xfff80000ff0d7424 */
/* 0x000fd400078e00ff */
/*0730*/ @!P0 BRA 0x810 ; /* 0x000000d000008947 */
/* 0x000fea0003800000 */
/*0740*/ ISETP.NE.AND P0, PT, R17, 0x7ff00000, PT ; /* 0x7ff000001100780c */
/* 0x000fe40003f05270 */
/*0750*/ LOP3.LUT R13, R5, 0x80000000, R7, 0x48, !PT ; /* 0x80000000050d7812 */
/* 0x000fe400078e4807 */
/*0760*/ ISETP.EQ.OR P0, PT, R16, RZ, !P0 ; /* 0x000000ff1000720c */
/* 0x000fda0004702670 */
/*0770*/ @P0 LOP3.LUT R2, R13, 0x7ff00000, RZ, 0xfc, !PT ; /* 0x7ff000000d020812 */
/* 0x000fe200078efcff */
/*0780*/ @!P0 IMAD.MOV.U32 R12, RZ, RZ, RZ ; /* 0x000000ffff0c8224 */
/* 0x000fe400078e00ff */
/*0790*/ @P0 IMAD.MOV.U32 R12, RZ, RZ, RZ ; /* 0x000000ffff0c0224 */
/* 0x000fe400078e00ff */
/*07a0*/ @P0 IMAD.MOV.U32 R13, RZ, RZ, R2 ; /* 0x000000ffff0d0224 */
/* 0x000fe200078e0002 */
/*07b0*/ BRA 0x810 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*07c0*/ LOP3.LUT R13, R7, 0x80000, RZ, 0xfc, !PT ; /* 0x00080000070d7812 */
/* 0x000fe200078efcff */
/*07d0*/ IMAD.MOV.U32 R12, RZ, RZ, R6 ; /* 0x000000ffff0c7224 */
/* 0x000fe200078e0006 */
/*07e0*/ BRA 0x810 ; /* 0x0000002000007947 */
/* 0x000fea0003800000 */
/*07f0*/ LOP3.LUT R13, R5, 0x80000, RZ, 0xfc, !PT ; /* 0x00080000050d7812 */
/* 0x000fe200078efcff */
/*0800*/ IMAD.MOV.U32 R12, RZ, RZ, R4 ; /* 0x000000ffff0c7224 */
/* 0x000fe400078e0004 */
/*0810*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0820*/ IMAD.MOV.U32 R2, RZ, RZ, R0 ; /* 0x000000ffff027224 */
/* 0x000fe400078e0000 */
/*0830*/ IMAD.MOV.U32 R3, RZ, RZ, 0x0 ; /* 0x00000000ff037424 */
/* 0x000fc800078e00ff */
/*0840*/ RET.REL.NODEC R2 0x0 ; /* 0xfffff7b002007950 */
/* 0x000fea0003c3ffff */
/*0850*/ BRA 0x850; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0860*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0870*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0880*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0890*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void ComputeSpeQtyKernel (double *Label, double *Dens, double *ExtLabel, int nrad, int nsec)
{
int j = threadIdx.x + blockDim.x*blockIdx.x;
int i = threadIdx.y + blockDim.y*blockIdx.y;
if (i<nrad && j<nsec){
Label[i*nsec + j] = ExtLabel[i*nsec + j]/Dens[i*nsec + j];
/* Compressive flow if line commentarized
Label[i*nsec + j] = ExtLabel[i*nsec + j] */
}
} | .file "tmpxft_00134222_00000000-6_ComputeSpeQtyKernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z45__device_stub__Z19ComputeSpeQtyKernelPdS_S_iiPdS_S_ii
.type _Z45__device_stub__Z19ComputeSpeQtyKernelPdS_S_iiPdS_S_ii, @function
_Z45__device_stub__Z19ComputeSpeQtyKernelPdS_S_iiPdS_S_ii:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z19ComputeSpeQtyKernelPdS_S_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z45__device_stub__Z19ComputeSpeQtyKernelPdS_S_iiPdS_S_ii, .-_Z45__device_stub__Z19ComputeSpeQtyKernelPdS_S_iiPdS_S_ii
.globl _Z19ComputeSpeQtyKernelPdS_S_ii
.type _Z19ComputeSpeQtyKernelPdS_S_ii, @function
_Z19ComputeSpeQtyKernelPdS_S_ii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z45__device_stub__Z19ComputeSpeQtyKernelPdS_S_iiPdS_S_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z19ComputeSpeQtyKernelPdS_S_ii, .-_Z19ComputeSpeQtyKernelPdS_S_ii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z19ComputeSpeQtyKernelPdS_S_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z19ComputeSpeQtyKernelPdS_S_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void ComputeSpeQtyKernel (double *Label, double *Dens, double *ExtLabel, int nrad, int nsec)
{
int j = threadIdx.x + blockDim.x*blockIdx.x;
int i = threadIdx.y + blockDim.y*blockIdx.y;
if (i<nrad && j<nsec){
Label[i*nsec + j] = ExtLabel[i*nsec + j]/Dens[i*nsec + j];
/* Compressive flow if line commentarized
Label[i*nsec + j] = ExtLabel[i*nsec + j] */
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void ComputeSpeQtyKernel (double *Label, double *Dens, double *ExtLabel, int nrad, int nsec)
{
int j = threadIdx.x + blockDim.x*blockIdx.x;
int i = threadIdx.y + blockDim.y*blockIdx.y;
if (i<nrad && j<nsec){
Label[i*nsec + j] = ExtLabel[i*nsec + j]/Dens[i*nsec + j];
/* Compressive flow if line commentarized
Label[i*nsec + j] = ExtLabel[i*nsec + j] */
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void ComputeSpeQtyKernel (double *Label, double *Dens, double *ExtLabel, int nrad, int nsec)
{
int j = threadIdx.x + blockDim.x*blockIdx.x;
int i = threadIdx.y + blockDim.y*blockIdx.y;
if (i<nrad && j<nsec){
Label[i*nsec + j] = ExtLabel[i*nsec + j]/Dens[i*nsec + j];
/* Compressive flow if line commentarized
Label[i*nsec + j] = ExtLabel[i*nsec + j] */
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z19ComputeSpeQtyKernelPdS_S_ii
.globl _Z19ComputeSpeQtyKernelPdS_S_ii
.p2align 8
.type _Z19ComputeSpeQtyKernelPdS_S_ii,@function
_Z19ComputeSpeQtyKernelPdS_S_ii:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x2c
s_load_b64 s[2:3], s[0:1], 0x18
v_bfe_u32 v2, v0, 10, 10
v_and_b32_e32 v3, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_and_b32 s5, s4, 0xffff
s_lshr_b32 s4, s4, 16
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[0:1], null, s15, s4, v[2:3]
v_mad_u64_u32 v[1:2], null, s14, s5, v[3:4]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_gt_i32_e32 vcc_lo, s2, v0
v_cmp_gt_i32_e64 s2, s3, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, s2, vcc_lo
s_and_saveexec_b32 s4, s2
s_cbranch_execz .LBB0_2
s_load_b64 s[4:5], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, v0, s3, v[1:2]
s_load_b128 s[0:3], s[0:1], 0x0
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 3, v[2:3]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v1, vcc_lo
global_load_b64 v[2:3], v[2:3], off
global_load_b64 v[4:5], v[4:5], off
s_waitcnt vmcnt(0)
v_div_scale_f64 v[6:7], null, v[4:5], v[4:5], v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f64_e32 v[8:9], v[6:7]
s_waitcnt_depctr 0xfff
v_fma_f64 v[10:11], -v[6:7], v[8:9], 1.0
v_fma_f64 v[8:9], v[8:9], v[10:11], v[8:9]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[10:11], -v[6:7], v[8:9], 1.0
v_fma_f64 v[8:9], v[8:9], v[10:11], v[8:9]
v_div_scale_f64 v[10:11], vcc_lo, v[2:3], v[4:5], v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[12:13], v[10:11], v[8:9]
v_fma_f64 v[6:7], -v[6:7], v[12:13], v[10:11]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_div_fmas_f64 v[6:7], v[6:7], v[8:9], v[12:13]
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
v_div_fixup_f64 v[2:3], v[6:7], v[4:5], v[2:3]
global_store_b64 v[0:1], v[2:3], off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z19ComputeSpeQtyKernelPdS_S_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 14
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z19ComputeSpeQtyKernelPdS_S_ii, .Lfunc_end0-_Z19ComputeSpeQtyKernelPdS_S_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z19ComputeSpeQtyKernelPdS_S_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z19ComputeSpeQtyKernelPdS_S_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 14
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void ComputeSpeQtyKernel (double *Label, double *Dens, double *ExtLabel, int nrad, int nsec)
{
int j = threadIdx.x + blockDim.x*blockIdx.x;
int i = threadIdx.y + blockDim.y*blockIdx.y;
if (i<nrad && j<nsec){
Label[i*nsec + j] = ExtLabel[i*nsec + j]/Dens[i*nsec + j];
/* Compressive flow if line commentarized
Label[i*nsec + j] = ExtLabel[i*nsec + j] */
}
} | .text
.file "ComputeSpeQtyKernel.hip"
.globl _Z34__device_stub__ComputeSpeQtyKernelPdS_S_ii # -- Begin function _Z34__device_stub__ComputeSpeQtyKernelPdS_S_ii
.p2align 4, 0x90
.type _Z34__device_stub__ComputeSpeQtyKernelPdS_S_ii,@function
_Z34__device_stub__ComputeSpeQtyKernelPdS_S_ii: # @_Z34__device_stub__ComputeSpeQtyKernelPdS_S_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z19ComputeSpeQtyKernelPdS_S_ii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z34__device_stub__ComputeSpeQtyKernelPdS_S_ii, .Lfunc_end0-_Z34__device_stub__ComputeSpeQtyKernelPdS_S_ii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z19ComputeSpeQtyKernelPdS_S_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z19ComputeSpeQtyKernelPdS_S_ii,@object # @_Z19ComputeSpeQtyKernelPdS_S_ii
.section .rodata,"a",@progbits
.globl _Z19ComputeSpeQtyKernelPdS_S_ii
.p2align 3, 0x0
_Z19ComputeSpeQtyKernelPdS_S_ii:
.quad _Z34__device_stub__ComputeSpeQtyKernelPdS_S_ii
.size _Z19ComputeSpeQtyKernelPdS_S_ii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z19ComputeSpeQtyKernelPdS_S_ii"
.size .L__unnamed_1, 32
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z34__device_stub__ComputeSpeQtyKernelPdS_S_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z19ComputeSpeQtyKernelPdS_S_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z19ComputeSpeQtyKernelPdS_S_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R10, SR_TID.X ; /* 0x00000000000a7919 */
/* 0x000e280000002100 */
/*0020*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e280000002500 */
/*0030*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e680000002600 */
/*0040*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e620000002200 */
/*0050*/ IMAD R10, R3, c[0x0][0x0], R10 ; /* 0x00000000030a7a24 */
/* 0x001fca00078e020a */
/*0060*/ ISETP.GE.AND P0, PT, R10, c[0x0][0x17c], PT ; /* 0x00005f000a007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R3, R0, c[0x0][0x4], R5 ; /* 0x0000010000037a24 */
/* 0x002fca00078e0205 */
/*0080*/ ISETP.GE.OR P0, PT, R3, c[0x0][0x178], P0 ; /* 0x00005e0003007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ IMAD.MOV.U32 R5, RZ, RZ, 0x8 ; /* 0x00000008ff057424 */
/* 0x000fe200078e00ff */
/*00b0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00c0*/ IMAD R10, R3, c[0x0][0x17c], R10 ; /* 0x00005f00030a7a24 */
/* 0x000fc800078e020a */
/*00d0*/ IMAD.WIDE R6, R10, R5, c[0x0][0x168] ; /* 0x00005a000a067625 */
/* 0x000fcc00078e0205 */
/*00e0*/ LDG.E.64 R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000ea2000c1e1b00 */
/*00f0*/ IMAD.WIDE R4, R10, R5, c[0x0][0x170] ; /* 0x00005c000a047625 */
/* 0x000fcc00078e0205 */
/*0100*/ LDG.E.64 R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ee2000c1e1b00 */
/*0110*/ IMAD.MOV.U32 R2, RZ, RZ, 0x1 ; /* 0x00000001ff027424 */
/* 0x000fe200078e00ff */
/*0120*/ BSSY B0, 0x250 ; /* 0x0000012000007945 */
/* 0x000fe20003800000 */
/*0130*/ MUFU.RCP64H R3, R7 ; /* 0x0000000700037308 */
/* 0x004e220000001800 */
/*0140*/ FSETP.GEU.AND P1, PT, |R5|, 6.5827683646048100446e-37, PT ; /* 0x036000000500780b */
/* 0x008fc60003f2e200 */
/*0150*/ DFMA R8, -R6, R2, 1 ; /* 0x3ff000000608742b */
/* 0x001e0c0000000102 */
/*0160*/ DFMA R8, R8, R8, R8 ; /* 0x000000080808722b */
/* 0x001e0c0000000008 */
/*0170*/ DFMA R8, R2, R8, R2 ; /* 0x000000080208722b */
/* 0x001e0c0000000002 */
/*0180*/ DFMA R2, -R6, R8, 1 ; /* 0x3ff000000602742b */
/* 0x001e0c0000000108 */
/*0190*/ DFMA R2, R8, R2, R8 ; /* 0x000000020802722b */
/* 0x001e0c0000000008 */
/*01a0*/ DMUL R8, R4, R2 ; /* 0x0000000204087228 */
/* 0x001e0c0000000000 */
/*01b0*/ DFMA R12, -R6, R8, R4 ; /* 0x00000008060c722b */
/* 0x001e0c0000000104 */
/*01c0*/ DFMA R2, R2, R12, R8 ; /* 0x0000000c0202722b */
/* 0x001e140000000008 */
/*01d0*/ FFMA R0, RZ, R7, R3 ; /* 0x00000007ff007223 */
/* 0x001fca0000000003 */
/*01e0*/ FSETP.GT.AND P0, PT, |R0|, 1.469367938527859385e-39, PT ; /* 0x001000000000780b */
/* 0x000fda0003f04200 */
/*01f0*/ @P0 BRA P1, 0x240 ; /* 0x0000004000000947 */
/* 0x000fea0000800000 */
/*0200*/ MOV R0, 0x220 ; /* 0x0000022000007802 */
/* 0x000fe40000000f00 */
/*0210*/ CALL.REL.NOINC 0x290 ; /* 0x0000007000007944 */
/* 0x000fea0003c00000 */
/*0220*/ IMAD.MOV.U32 R2, RZ, RZ, R12 ; /* 0x000000ffff027224 */
/* 0x000fe400078e000c */
/*0230*/ IMAD.MOV.U32 R3, RZ, RZ, R13 ; /* 0x000000ffff037224 */
/* 0x000fe400078e000d */
/*0240*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0250*/ IMAD.MOV.U32 R11, RZ, RZ, 0x8 ; /* 0x00000008ff0b7424 */
/* 0x000fc800078e00ff */
/*0260*/ IMAD.WIDE R10, R10, R11, c[0x0][0x160] ; /* 0x000058000a0a7625 */
/* 0x000fca00078e020b */
/*0270*/ STG.E.64 [R10.64], R2 ; /* 0x000000020a007986 */
/* 0x000fe2000c101b04 */
/*0280*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0290*/ FSETP.GEU.AND P0, PT, |R7|.reuse, 1.469367938527859385e-39, PT ; /* 0x001000000700780b */
/* 0x040fe20003f0e200 */
/*02a0*/ IMAD.MOV.U32 R12, RZ, RZ, 0x1ca00000 ; /* 0x1ca00000ff0c7424 */
/* 0x000fe200078e00ff */
/*02b0*/ LOP3.LUT R2, R7, 0x800fffff, RZ, 0xc0, !PT ; /* 0x800fffff07027812 */
/* 0x000fe200078ec0ff */
/*02c0*/ IMAD.MOV.U32 R14, RZ, RZ, 0x1 ; /* 0x00000001ff0e7424 */
/* 0x000fe200078e00ff */
/*02d0*/ FSETP.GEU.AND P2, PT, |R5|.reuse, 1.469367938527859385e-39, PT ; /* 0x001000000500780b */
/* 0x040fe20003f4e200 */
/*02e0*/ BSSY B1, 0x820 ; /* 0x0000053000017945 */
/* 0x000fe20003800000 */
/*02f0*/ LOP3.LUT R3, R2, 0x3ff00000, RZ, 0xfc, !PT ; /* 0x3ff0000002037812 */
/* 0x000fe200078efcff */
/*0300*/ IMAD.MOV.U32 R2, RZ, RZ, R6 ; /* 0x000000ffff027224 */
/* 0x000fe200078e0006 */
/*0310*/ LOP3.LUT R11, R5, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff00000050b7812 */
/* 0x000fe400078ec0ff */
/*0320*/ LOP3.LUT R16, R7, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff0000007107812 */
/* 0x000fc600078ec0ff */
/*0330*/ @!P0 DMUL R2, R6, 8.98846567431157953865e+307 ; /* 0x7fe0000006028828 */
/* 0x000e220000000000 */
/*0340*/ ISETP.GE.U32.AND P1, PT, R11, R16, PT ; /* 0x000000100b00720c */
/* 0x000fe20003f26070 */
/*0350*/ IMAD.MOV.U32 R17, RZ, RZ, R11 ; /* 0x000000ffff117224 */
/* 0x000fe400078e000b */
/*0360*/ @!P2 LOP3.LUT R8, R7, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff000000708a812 */
/* 0x000fe200078ec0ff */
/*0370*/ @!P2 IMAD.MOV.U32 R20, RZ, RZ, RZ ; /* 0x000000ffff14a224 */
/* 0x000fe200078e00ff */
/*0380*/ MUFU.RCP64H R15, R3 ; /* 0x00000003000f7308 */
/* 0x001e220000001800 */
/*0390*/ SEL R9, R12, 0x63400000, !P1 ; /* 0x634000000c097807 */
/* 0x000fe40004800000 */
/*03a0*/ @!P2 ISETP.GE.U32.AND P3, PT, R11, R8, PT ; /* 0x000000080b00a20c */
/* 0x000fe20003f66070 */
/*03b0*/ IMAD.MOV.U32 R8, RZ, RZ, R4 ; /* 0x000000ffff087224 */
/* 0x000fe200078e0004 */
/*03c0*/ LOP3.LUT R9, R9, 0x800fffff, R5, 0xf8, !PT ; /* 0x800fffff09097812 */
/* 0x000fc400078ef805 */
/*03d0*/ @!P2 SEL R13, R12, 0x63400000, !P3 ; /* 0x634000000c0da807 */
/* 0x000fe40005800000 */
/*03e0*/ @!P0 LOP3.LUT R16, R3, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff0000003108812 */
/* 0x000fe400078ec0ff */
/*03f0*/ @!P2 LOP3.LUT R13, R13, 0x80000000, R5, 0xf8, !PT ; /* 0x800000000d0da812 */
/* 0x000fe400078ef805 */
/*0400*/ IADD3 R22, R16, -0x1, RZ ; /* 0xffffffff10167810 */
/* 0x000fe40007ffe0ff */
/*0410*/ @!P2 LOP3.LUT R21, R13, 0x100000, RZ, 0xfc, !PT ; /* 0x001000000d15a812 */
/* 0x000fe200078efcff */
/*0420*/ DFMA R18, R14, -R2, 1 ; /* 0x3ff000000e12742b */
/* 0x001e0a0000000802 */
/*0430*/ @!P2 DFMA R8, R8, 2, -R20 ; /* 0x400000000808a82b */
/* 0x000fc80000000814 */
/*0440*/ DFMA R18, R18, R18, R18 ; /* 0x000000121212722b */
/* 0x001e0c0000000012 */
/*0450*/ DFMA R14, R14, R18, R14 ; /* 0x000000120e0e722b */
/* 0x001e22000000000e */
/*0460*/ @!P2 LOP3.LUT R17, R9, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff000000911a812 */
/* 0x000fc800078ec0ff */
/*0470*/ IADD3 R13, R17, -0x1, RZ ; /* 0xffffffff110d7810 */
/* 0x000fe20007ffe0ff */
/*0480*/ DFMA R18, R14, -R2, 1 ; /* 0x3ff000000e12742b */
/* 0x001e060000000802 */
/*0490*/ ISETP.GT.U32.AND P0, PT, R13, 0x7feffffe, PT ; /* 0x7feffffe0d00780c */
/* 0x000fc60003f04070 */
/*04a0*/ DFMA R14, R14, R18, R14 ; /* 0x000000120e0e722b */
/* 0x001e22000000000e */
/*04b0*/ ISETP.GT.U32.OR P0, PT, R22, 0x7feffffe, P0 ; /* 0x7feffffe1600780c */
/* 0x000fca0000704470 */
/*04c0*/ DMUL R18, R14, R8 ; /* 0x000000080e127228 */
/* 0x001e0c0000000000 */
/*04d0*/ DFMA R20, R18, -R2, R8 ; /* 0x800000021214722b */
/* 0x001e0c0000000008 */
/*04e0*/ DFMA R14, R14, R20, R18 ; /* 0x000000140e0e722b */
/* 0x0010620000000012 */
/*04f0*/ @P0 BRA 0x6c0 ; /* 0x000001c000000947 */
/* 0x000fea0003800000 */
/*0500*/ LOP3.LUT R16, R7, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff0000007107812 */
/* 0x000fc800078ec0ff */
/*0510*/ ISETP.GE.U32.AND P0, PT, R11.reuse, R16, PT ; /* 0x000000100b00720c */
/* 0x040fe20003f06070 */
/*0520*/ IMAD.IADD R4, R11, 0x1, -R16 ; /* 0x000000010b047824 */
/* 0x000fc600078e0a10 */
/*0530*/ SEL R11, R12, 0x63400000, !P0 ; /* 0x634000000c0b7807 */
/* 0x000fe40004000000 */
/*0540*/ IMNMX R4, R4, -0x46a00000, !PT ; /* 0xb960000004047817 */
/* 0x000fc80007800200 */
/*0550*/ IMNMX R4, R4, 0x46a00000, PT ; /* 0x46a0000004047817 */
/* 0x000fca0003800200 */
/*0560*/ IMAD.IADD R11, R4, 0x1, -R11 ; /* 0x00000001040b7824 */
/* 0x000fe400078e0a0b */
/*0570*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x000fc600078e00ff */
/*0580*/ IADD3 R5, R11, 0x7fe00000, RZ ; /* 0x7fe000000b057810 */
/* 0x000fcc0007ffe0ff */
/*0590*/ DMUL R12, R14, R4 ; /* 0x000000040e0c7228 */
/* 0x002e540000000000 */
/*05a0*/ FSETP.GTU.AND P0, PT, |R13|, 1.469367938527859385e-39, PT ; /* 0x001000000d00780b */
/* 0x002fda0003f0c200 */
/*05b0*/ @P0 BRA 0x810 ; /* 0x0000025000000947 */
/* 0x000fea0003800000 */
/*05c0*/ DFMA R2, R14, -R2, R8 ; /* 0x800000020e02722b */
/* 0x000e620000000008 */
/*05d0*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x000fd200078e00ff */
/*05e0*/ FSETP.NEU.AND P0, PT, R3.reuse, RZ, PT ; /* 0x000000ff0300720b */
/* 0x042fe40003f0d000 */
/*05f0*/ LOP3.LUT R7, R3, 0x80000000, R7, 0x48, !PT ; /* 0x8000000003077812 */
/* 0x000fc800078e4807 */
/*0600*/ LOP3.LUT R5, R7, R5, RZ, 0xfc, !PT ; /* 0x0000000507057212 */
/* 0x000fce00078efcff */
/*0610*/ @!P0 BRA 0x810 ; /* 0x000001f000008947 */
/* 0x000fea0003800000 */
/*0620*/ IMAD.MOV R3, RZ, RZ, -R11 ; /* 0x000000ffff037224 */
/* 0x000fe200078e0a0b */
/*0630*/ DMUL.RP R4, R14, R4 ; /* 0x000000040e047228 */
/* 0x000e620000008000 */
/*0640*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x000fe200078e00ff */
/*0650*/ IADD3 R11, -R11, -0x43300000, RZ ; /* 0xbcd000000b0b7810 */
/* 0x000fca0007ffe1ff */
/*0660*/ DFMA R2, R12, -R2, R14 ; /* 0x800000020c02722b */
/* 0x000e86000000000e */
/*0670*/ LOP3.LUT R7, R5, R7, RZ, 0x3c, !PT ; /* 0x0000000705077212 */
/* 0x002fce00078e3cff */
/*0680*/ FSETP.NEU.AND P0, PT, |R3|, R11, PT ; /* 0x0000000b0300720b */
/* 0x004fc80003f0d200 */
/*0690*/ FSEL R12, R4, R12, !P0 ; /* 0x0000000c040c7208 */
/* 0x000fe40004000000 */
/*06a0*/ FSEL R13, R7, R13, !P0 ; /* 0x0000000d070d7208 */
/* 0x000fe20004000000 */
/*06b0*/ BRA 0x810 ; /* 0x0000015000007947 */
/* 0x000fea0003800000 */
/*06c0*/ DSETP.NAN.AND P0, PT, R4, R4, PT ; /* 0x000000040400722a */
/* 0x000e9c0003f08000 */
/*06d0*/ @P0 BRA 0x7f0 ; /* 0x0000011000000947 */
/* 0x004fea0003800000 */
/*06e0*/ DSETP.NAN.AND P0, PT, R6, R6, PT ; /* 0x000000060600722a */
/* 0x000e9c0003f08000 */
/*06f0*/ @P0 BRA 0x7c0 ; /* 0x000000c000000947 */
/* 0x004fea0003800000 */
/*0700*/ ISETP.NE.AND P0, PT, R17, R16, PT ; /* 0x000000101100720c */
/* 0x000fe20003f05270 */
/*0710*/ IMAD.MOV.U32 R12, RZ, RZ, 0x0 ; /* 0x00000000ff0c7424 */
/* 0x000fe400078e00ff */
/*0720*/ IMAD.MOV.U32 R13, RZ, RZ, -0x80000 ; /* 0xfff80000ff0d7424 */
/* 0x000fd400078e00ff */
/*0730*/ @!P0 BRA 0x810 ; /* 0x000000d000008947 */
/* 0x000fea0003800000 */
/*0740*/ ISETP.NE.AND P0, PT, R17, 0x7ff00000, PT ; /* 0x7ff000001100780c */
/* 0x000fe40003f05270 */
/*0750*/ LOP3.LUT R13, R5, 0x80000000, R7, 0x48, !PT ; /* 0x80000000050d7812 */
/* 0x000fe400078e4807 */
/*0760*/ ISETP.EQ.OR P0, PT, R16, RZ, !P0 ; /* 0x000000ff1000720c */
/* 0x000fda0004702670 */
/*0770*/ @P0 LOP3.LUT R2, R13, 0x7ff00000, RZ, 0xfc, !PT ; /* 0x7ff000000d020812 */
/* 0x000fe200078efcff */
/*0780*/ @!P0 IMAD.MOV.U32 R12, RZ, RZ, RZ ; /* 0x000000ffff0c8224 */
/* 0x000fe400078e00ff */
/*0790*/ @P0 IMAD.MOV.U32 R12, RZ, RZ, RZ ; /* 0x000000ffff0c0224 */
/* 0x000fe400078e00ff */
/*07a0*/ @P0 IMAD.MOV.U32 R13, RZ, RZ, R2 ; /* 0x000000ffff0d0224 */
/* 0x000fe200078e0002 */
/*07b0*/ BRA 0x810 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*07c0*/ LOP3.LUT R13, R7, 0x80000, RZ, 0xfc, !PT ; /* 0x00080000070d7812 */
/* 0x000fe200078efcff */
/*07d0*/ IMAD.MOV.U32 R12, RZ, RZ, R6 ; /* 0x000000ffff0c7224 */
/* 0x000fe200078e0006 */
/*07e0*/ BRA 0x810 ; /* 0x0000002000007947 */
/* 0x000fea0003800000 */
/*07f0*/ LOP3.LUT R13, R5, 0x80000, RZ, 0xfc, !PT ; /* 0x00080000050d7812 */
/* 0x000fe200078efcff */
/*0800*/ IMAD.MOV.U32 R12, RZ, RZ, R4 ; /* 0x000000ffff0c7224 */
/* 0x000fe400078e0004 */
/*0810*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0820*/ IMAD.MOV.U32 R2, RZ, RZ, R0 ; /* 0x000000ffff027224 */
/* 0x000fe400078e0000 */
/*0830*/ IMAD.MOV.U32 R3, RZ, RZ, 0x0 ; /* 0x00000000ff037424 */
/* 0x000fc800078e00ff */
/*0840*/ RET.REL.NODEC R2 0x0 ; /* 0xfffff7b002007950 */
/* 0x000fea0003c3ffff */
/*0850*/ BRA 0x850; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0860*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0870*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0880*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0890*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z19ComputeSpeQtyKernelPdS_S_ii
.globl _Z19ComputeSpeQtyKernelPdS_S_ii
.p2align 8
.type _Z19ComputeSpeQtyKernelPdS_S_ii,@function
_Z19ComputeSpeQtyKernelPdS_S_ii:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x2c
s_load_b64 s[2:3], s[0:1], 0x18
v_bfe_u32 v2, v0, 10, 10
v_and_b32_e32 v3, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_and_b32 s5, s4, 0xffff
s_lshr_b32 s4, s4, 16
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[0:1], null, s15, s4, v[2:3]
v_mad_u64_u32 v[1:2], null, s14, s5, v[3:4]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_gt_i32_e32 vcc_lo, s2, v0
v_cmp_gt_i32_e64 s2, s3, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, s2, vcc_lo
s_and_saveexec_b32 s4, s2
s_cbranch_execz .LBB0_2
s_load_b64 s[4:5], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, v0, s3, v[1:2]
s_load_b128 s[0:3], s[0:1], 0x0
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 3, v[2:3]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v1, vcc_lo
global_load_b64 v[2:3], v[2:3], off
global_load_b64 v[4:5], v[4:5], off
s_waitcnt vmcnt(0)
v_div_scale_f64 v[6:7], null, v[4:5], v[4:5], v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f64_e32 v[8:9], v[6:7]
s_waitcnt_depctr 0xfff
v_fma_f64 v[10:11], -v[6:7], v[8:9], 1.0
v_fma_f64 v[8:9], v[8:9], v[10:11], v[8:9]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[10:11], -v[6:7], v[8:9], 1.0
v_fma_f64 v[8:9], v[8:9], v[10:11], v[8:9]
v_div_scale_f64 v[10:11], vcc_lo, v[2:3], v[4:5], v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[12:13], v[10:11], v[8:9]
v_fma_f64 v[6:7], -v[6:7], v[12:13], v[10:11]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_div_fmas_f64 v[6:7], v[6:7], v[8:9], v[12:13]
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
v_div_fixup_f64 v[2:3], v[6:7], v[4:5], v[2:3]
global_store_b64 v[0:1], v[2:3], off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z19ComputeSpeQtyKernelPdS_S_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 14
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z19ComputeSpeQtyKernelPdS_S_ii, .Lfunc_end0-_Z19ComputeSpeQtyKernelPdS_S_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z19ComputeSpeQtyKernelPdS_S_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z19ComputeSpeQtyKernelPdS_S_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 14
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00134222_00000000-6_ComputeSpeQtyKernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z45__device_stub__Z19ComputeSpeQtyKernelPdS_S_iiPdS_S_ii
.type _Z45__device_stub__Z19ComputeSpeQtyKernelPdS_S_iiPdS_S_ii, @function
_Z45__device_stub__Z19ComputeSpeQtyKernelPdS_S_iiPdS_S_ii:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z19ComputeSpeQtyKernelPdS_S_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z45__device_stub__Z19ComputeSpeQtyKernelPdS_S_iiPdS_S_ii, .-_Z45__device_stub__Z19ComputeSpeQtyKernelPdS_S_iiPdS_S_ii
.globl _Z19ComputeSpeQtyKernelPdS_S_ii
.type _Z19ComputeSpeQtyKernelPdS_S_ii, @function
_Z19ComputeSpeQtyKernelPdS_S_ii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z45__device_stub__Z19ComputeSpeQtyKernelPdS_S_iiPdS_S_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z19ComputeSpeQtyKernelPdS_S_ii, .-_Z19ComputeSpeQtyKernelPdS_S_ii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z19ComputeSpeQtyKernelPdS_S_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z19ComputeSpeQtyKernelPdS_S_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "ComputeSpeQtyKernel.hip"
.globl _Z34__device_stub__ComputeSpeQtyKernelPdS_S_ii # -- Begin function _Z34__device_stub__ComputeSpeQtyKernelPdS_S_ii
.p2align 4, 0x90
.type _Z34__device_stub__ComputeSpeQtyKernelPdS_S_ii,@function
_Z34__device_stub__ComputeSpeQtyKernelPdS_S_ii: # @_Z34__device_stub__ComputeSpeQtyKernelPdS_S_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z19ComputeSpeQtyKernelPdS_S_ii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z34__device_stub__ComputeSpeQtyKernelPdS_S_ii, .Lfunc_end0-_Z34__device_stub__ComputeSpeQtyKernelPdS_S_ii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z19ComputeSpeQtyKernelPdS_S_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z19ComputeSpeQtyKernelPdS_S_ii,@object # @_Z19ComputeSpeQtyKernelPdS_S_ii
.section .rodata,"a",@progbits
.globl _Z19ComputeSpeQtyKernelPdS_S_ii
.p2align 3, 0x0
_Z19ComputeSpeQtyKernelPdS_S_ii:
.quad _Z34__device_stub__ComputeSpeQtyKernelPdS_S_ii
.size _Z19ComputeSpeQtyKernelPdS_S_ii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z19ComputeSpeQtyKernelPdS_S_ii"
.size .L__unnamed_1, 32
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z34__device_stub__ComputeSpeQtyKernelPdS_S_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z19ComputeSpeQtyKernelPdS_S_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void helper(float * output, float * blocksum, int len) {
int i = blockIdx.x*blockDim.x + threadIdx.x;
if (i < len){
for (int j=0; j<i/blockDim.x; j++)
output[i] += blocksum[j];
}
} | code for sm_80
Function : _Z6helperPfS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x0], PT ; /* 0x0000000000007a0c */
/* 0x000fda0003f06070 */
/*0070*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0080*/ I2F.U32.RP R4, c[0x0][0x0] ; /* 0x0000000000047b06 */
/* 0x000e220000209000 */
/*0090*/ ISETP.NE.U32.AND P2, PT, RZ, c[0x0][0x0], PT ; /* 0x00000000ff007a0c */
/* 0x000fe20003f45070 */
/*00a0*/ HFMA2.MMA R17, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff117435 */
/* 0x000fe200000001ff */
/*00b0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00c0*/ BSSY B0, 0x3f0 ; /* 0x0000032000007945 */
/* 0x000fe20003800000 */
/*00d0*/ IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff067224 */
/* 0x000fc600078e00ff */
/*00e0*/ MUFU.RCP R4, R4 ; /* 0x0000000400047308 */
/* 0x001e240000001000 */
/*00f0*/ IADD3 R2, R4, 0xffffffe, RZ ; /* 0x0ffffffe04027810 */
/* 0x001fcc0007ffe0ff */
/*0100*/ F2I.FTZ.U32.TRUNC.NTZ R3, R2 ; /* 0x0000000200037305 */
/* 0x000064000021f000 */
/*0110*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x001fe400078e00ff */
/*0120*/ IMAD.MOV R5, RZ, RZ, -R3 ; /* 0x000000ffff057224 */
/* 0x002fc800078e0a03 */
/*0130*/ IMAD R5, R5, c[0x0][0x0], RZ ; /* 0x0000000005057a24 */
/* 0x000fc800078e02ff */
/*0140*/ IMAD.HI.U32 R3, R3, R5, R2 ; /* 0x0000000503037227 */
/* 0x000fcc00078e0002 */
/*0150*/ IMAD.HI.U32 R3, R3, R0, RZ ; /* 0x0000000003037227 */
/* 0x000fc800078e00ff */
/*0160*/ IMAD.MOV R5, RZ, RZ, -R3 ; /* 0x000000ffff057224 */
/* 0x000fc800078e0a03 */
/*0170*/ IMAD R5, R5, c[0x0][0x0], R0 ; /* 0x0000000005057a24 */
/* 0x000fca00078e0200 */
/*0180*/ ISETP.GE.U32.AND P0, PT, R5, c[0x0][0x0], PT ; /* 0x0000000005007a0c */
/* 0x000fda0003f06070 */
/*0190*/ @P0 IADD3 R5, R5, -c[0x0][0x0], RZ ; /* 0x8000000005050a10 */
/* 0x000fe40007ffe0ff */
/*01a0*/ @P0 IADD3 R3, R3, 0x1, RZ ; /* 0x0000000103030810 */
/* 0x000fe40007ffe0ff */
/*01b0*/ ISETP.GE.U32.AND P1, PT, R5, c[0x0][0x0], PT ; /* 0x0000000005007a0c */
/* 0x000fda0003f26070 */
/*01c0*/ @P1 IADD3 R3, R3, 0x1, RZ ; /* 0x0000000103031810 */
/* 0x000fe40007ffe0ff */
/*01d0*/ @!P2 LOP3.LUT R3, RZ, c[0x0][0x0], RZ, 0x33, !PT ; /* 0x00000000ff03aa12 */
/* 0x000fc800078e33ff */
/*01e0*/ IMNMX.U32 R4, R3, 0x1, !PT ; /* 0x0000000103047817 */
/* 0x000fc80007800000 */
/*01f0*/ IADD3 R2, R4.reuse, -0x1, RZ ; /* 0xffffffff04027810 */
/* 0x040fe40007ffe0ff */
/*0200*/ LOP3.LUT R7, R4, 0x3, RZ, 0xc0, !PT ; /* 0x0000000304077812 */
/* 0x000fe400078ec0ff */
/*0210*/ ISETP.GE.U32.AND P1, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fe20003f26070 */
/*0220*/ IMAD.WIDE R2, R0, R17, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fe200078e0211 */
/*0230*/ ISETP.NE.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fd60003f05270 */
/*0240*/ @!P1 BRA 0x3e0 ; /* 0x0000019000009947 */
/* 0x000fea0003800000 */
/*0250*/ LDG.E R9, [R2.64] ; /* 0x0000000402097981 */
/* 0x000162000c1e1900 */
/*0260*/ IMAD.IADD R0, R4, 0x1, -R7 ; /* 0x0000000104007824 */
/* 0x000fe200078e0a07 */
/*0270*/ MOV R8, c[0x0][0x168] ; /* 0x00005a0000087a02 */
/* 0x000fe20000000f00 */
/*0280*/ IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff067224 */
/* 0x000fe400078e00ff */
/*0290*/ IMAD.MOV.U32 R11, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff0b7624 */
/* 0x000fe400078e00ff */
/*02a0*/ IMAD.MOV.U32 R4, RZ, RZ, R8 ; /* 0x000000ffff047224 */
/* 0x000fe400078e0008 */
/*02b0*/ IMAD.MOV.U32 R5, RZ, RZ, R11 ; /* 0x000000ffff057224 */
/* 0x000fca00078e000b */
/*02c0*/ LDG.E R8, [R4.64] ; /* 0x0000000404087981 */
/* 0x004ea4000c1e1900 */
/*02d0*/ FADD R11, R8, R9 ; /* 0x00000009080b7221 */
/* 0x024fca0000000000 */
/*02e0*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x0003e8000c101904 */
/*02f0*/ LDG.E R8, [R4.64+0x4] ; /* 0x0000040404087981 */
/* 0x000ea4000c1e1900 */
/*0300*/ FADD R13, R11, R8 ; /* 0x000000080b0d7221 */
/* 0x004fca0000000000 */
/*0310*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x0005e8000c101904 */
/*0320*/ LDG.E R8, [R4.64+0x8] ; /* 0x0000080404087981 */
/* 0x000ee4000c1e1900 */
/*0330*/ FADD R15, R13, R8 ; /* 0x000000080d0f7221 */
/* 0x008fca0000000000 */
/*0340*/ STG.E [R2.64], R15 ; /* 0x0000000f02007986 */
/* 0x0005e8000c101904 */
/*0350*/ LDG.E R8, [R4.64+0xc] ; /* 0x00000c0404087981 */
/* 0x000ee2000c1e1900 */
/*0360*/ IADD3 R0, R0, -0x4, RZ ; /* 0xfffffffc00007810 */
/* 0x000fe40007ffe0ff */
/*0370*/ IADD3 R6, R6, 0x4, RZ ; /* 0x0000000406067810 */
/* 0x000fe40007ffe0ff */
/*0380*/ ISETP.NE.AND P1, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe20003f25270 */
/*0390*/ FADD R9, R15, R8 ; /* 0x000000080f097221 */
/* 0x008fe20000000000 */
/*03a0*/ IADD3 R8, P2, R4, 0x10, RZ ; /* 0x0000001004087810 */
/* 0x000fc80007f5e0ff */
/*03b0*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x0005e2000c101904 */
/*03c0*/ IADD3.X R11, RZ, R5, RZ, P2, !PT ; /* 0x00000005ff0b7210 */
/* 0x002fcc00017fe4ff */
/*03d0*/ @P1 BRA 0x2a0 ; /* 0xfffffec000001947 */
/* 0x000fea000383ffff */
/*03e0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*03f0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0400*/ LDG.E R9, [R2.64] ; /* 0x0000000402097981 */
/* 0x004362000c1e1900 */
/*0410*/ IMAD.WIDE R4, R6, R17, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x000fca00078e0211 */
/*0420*/ LDG.E R0, [R4.64] ; /* 0x0000000404007981 */
/* 0x0044e2000c1e1900 */
/*0430*/ IADD3 R7, R7, -0x1, RZ ; /* 0xffffffff07077810 */
/* 0x000fc80007ffe0ff */
/*0440*/ ISETP.NE.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fe40003f05270 */
/*0450*/ IADD3 R4, P1, R4, 0x4, RZ ; /* 0x0000000404047810 */
/* 0x004fca0007f3e0ff */
/*0460*/ IMAD.X R5, RZ, RZ, R5, P1 ; /* 0x000000ffff057224 */
/* 0x000fe400008e0605 */
/*0470*/ FADD R9, R0, R9 ; /* 0x0000000900097221 */
/* 0x028fca0000000000 */
/*0480*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x0005e2000c101904 */
/*0490*/ @P0 BRA 0x420 ; /* 0xffffff8000000947 */
/* 0x000fea000383ffff */
/*04a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*04b0*/ BRA 0x4b0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*04c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0500*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0510*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0520*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0530*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0540*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0550*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0560*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0570*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void helper(float * output, float * blocksum, int len) {
int i = blockIdx.x*blockDim.x + threadIdx.x;
if (i < len){
for (int j=0; j<i/blockDim.x; j++)
output[i] += blocksum[j];
}
} | .file "tmpxft_001164f3_00000000-6_helper.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z28__device_stub__Z6helperPfS_iPfS_i
.type _Z28__device_stub__Z6helperPfS_iPfS_i, @function
_Z28__device_stub__Z6helperPfS_iPfS_i:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6helperPfS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z28__device_stub__Z6helperPfS_iPfS_i, .-_Z28__device_stub__Z6helperPfS_iPfS_i
.globl _Z6helperPfS_i
.type _Z6helperPfS_i, @function
_Z6helperPfS_i:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z28__device_stub__Z6helperPfS_iPfS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z6helperPfS_i, .-_Z6helperPfS_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z6helperPfS_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z6helperPfS_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void helper(float * output, float * blocksum, int len) {
int i = blockIdx.x*blockDim.x + threadIdx.x;
if (i < len){
for (int j=0; j<i/blockDim.x; j++)
output[i] += blocksum[j];
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void helper(float * output, float * blocksum, int len) {
int i = blockIdx.x*blockDim.x + threadIdx.x;
if (i < len){
for (int j=0; j<i/blockDim.x; j++)
output[i] += blocksum[j];
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void helper(float * output, float * blocksum, int len) {
int i = blockIdx.x*blockDim.x + threadIdx.x;
if (i < len){
for (int j=0; j<i/blockDim.x; j++)
output[i] += blocksum[j];
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6helperPfS_i
.globl _Z6helperPfS_i
.p2align 8
.type _Z6helperPfS_i,@function
_Z6helperPfS_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s2, 0xffff
s_mov_b32 s2, exec_lo
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_4
v_cmp_le_u32_e32 vcc_lo, s4, v1
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_4
s_load_b128 s[0:3], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
v_cvt_f32_u32_e32 v4, s4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[2:3], 2, v[1:2]
v_rcp_iflag_f32_e32 v4, v4
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v4, 0x4f7ffffe, v4
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s0, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_3)
v_cvt_u32_f32_e32 v4, v4
s_sub_i32 s0, 0, s4
s_mov_b32 s1, 0
global_load_b32 v0, v[2:3], off
v_mul_lo_u32 v5, s0, v4
s_mov_b32 s0, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v5, v4, v5
v_add_nc_u32_e32 v6, v4, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[4:5], null, v1, v6, 0
v_mul_lo_u32 v4, v5, s4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v1, v1, v4
v_add_nc_u32_e32 v4, 1, v5
v_subrev_nc_u32_e32 v6, s4, v1
v_cmp_le_u32_e32 vcc_lo, s4, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_cndmask_b32_e32 v1, v1, v6, vcc_lo
v_cndmask_b32_e32 v4, v5, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_le_u32_e32 vcc_lo, s4, v1
v_add_nc_u32_e32 v5, 1, v4
s_delay_alu instid0(VALU_DEP_1)
v_dual_cndmask_b32 v1, v4, v5 :: v_dual_mov_b32 v4, 0
.LBB0_3:
global_load_b32 v5, v4, s[2:3]
s_add_i32 s1, s1, 1
s_add_u32 s2, s2, 4
v_cmp_ge_u32_e32 vcc_lo, s1, v1
s_addc_u32 s3, s3, 0
s_or_b32 s0, vcc_lo, s0
s_waitcnt vmcnt(0)
v_add_f32_e32 v0, v5, v0
global_store_b32 v[2:3], v0, off
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB0_3
.LBB0_4:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6helperPfS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6helperPfS_i, .Lfunc_end0-_Z6helperPfS_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6helperPfS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6helperPfS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void helper(float * output, float * blocksum, int len) {
int i = blockIdx.x*blockDim.x + threadIdx.x;
if (i < len){
for (int j=0; j<i/blockDim.x; j++)
output[i] += blocksum[j];
}
} | .text
.file "helper.hip"
.globl _Z21__device_stub__helperPfS_i # -- Begin function _Z21__device_stub__helperPfS_i
.p2align 4, 0x90
.type _Z21__device_stub__helperPfS_i,@function
_Z21__device_stub__helperPfS_i: # @_Z21__device_stub__helperPfS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6helperPfS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z21__device_stub__helperPfS_i, .Lfunc_end0-_Z21__device_stub__helperPfS_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6helperPfS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6helperPfS_i,@object # @_Z6helperPfS_i
.section .rodata,"a",@progbits
.globl _Z6helperPfS_i
.p2align 3, 0x0
_Z6helperPfS_i:
.quad _Z21__device_stub__helperPfS_i
.size _Z6helperPfS_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z6helperPfS_i"
.size .L__unnamed_1, 15
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__helperPfS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6helperPfS_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z6helperPfS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x0], PT ; /* 0x0000000000007a0c */
/* 0x000fda0003f06070 */
/*0070*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0080*/ I2F.U32.RP R4, c[0x0][0x0] ; /* 0x0000000000047b06 */
/* 0x000e220000209000 */
/*0090*/ ISETP.NE.U32.AND P2, PT, RZ, c[0x0][0x0], PT ; /* 0x00000000ff007a0c */
/* 0x000fe20003f45070 */
/*00a0*/ HFMA2.MMA R17, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff117435 */
/* 0x000fe200000001ff */
/*00b0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00c0*/ BSSY B0, 0x3f0 ; /* 0x0000032000007945 */
/* 0x000fe20003800000 */
/*00d0*/ IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff067224 */
/* 0x000fc600078e00ff */
/*00e0*/ MUFU.RCP R4, R4 ; /* 0x0000000400047308 */
/* 0x001e240000001000 */
/*00f0*/ IADD3 R2, R4, 0xffffffe, RZ ; /* 0x0ffffffe04027810 */
/* 0x001fcc0007ffe0ff */
/*0100*/ F2I.FTZ.U32.TRUNC.NTZ R3, R2 ; /* 0x0000000200037305 */
/* 0x000064000021f000 */
/*0110*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x001fe400078e00ff */
/*0120*/ IMAD.MOV R5, RZ, RZ, -R3 ; /* 0x000000ffff057224 */
/* 0x002fc800078e0a03 */
/*0130*/ IMAD R5, R5, c[0x0][0x0], RZ ; /* 0x0000000005057a24 */
/* 0x000fc800078e02ff */
/*0140*/ IMAD.HI.U32 R3, R3, R5, R2 ; /* 0x0000000503037227 */
/* 0x000fcc00078e0002 */
/*0150*/ IMAD.HI.U32 R3, R3, R0, RZ ; /* 0x0000000003037227 */
/* 0x000fc800078e00ff */
/*0160*/ IMAD.MOV R5, RZ, RZ, -R3 ; /* 0x000000ffff057224 */
/* 0x000fc800078e0a03 */
/*0170*/ IMAD R5, R5, c[0x0][0x0], R0 ; /* 0x0000000005057a24 */
/* 0x000fca00078e0200 */
/*0180*/ ISETP.GE.U32.AND P0, PT, R5, c[0x0][0x0], PT ; /* 0x0000000005007a0c */
/* 0x000fda0003f06070 */
/*0190*/ @P0 IADD3 R5, R5, -c[0x0][0x0], RZ ; /* 0x8000000005050a10 */
/* 0x000fe40007ffe0ff */
/*01a0*/ @P0 IADD3 R3, R3, 0x1, RZ ; /* 0x0000000103030810 */
/* 0x000fe40007ffe0ff */
/*01b0*/ ISETP.GE.U32.AND P1, PT, R5, c[0x0][0x0], PT ; /* 0x0000000005007a0c */
/* 0x000fda0003f26070 */
/*01c0*/ @P1 IADD3 R3, R3, 0x1, RZ ; /* 0x0000000103031810 */
/* 0x000fe40007ffe0ff */
/*01d0*/ @!P2 LOP3.LUT R3, RZ, c[0x0][0x0], RZ, 0x33, !PT ; /* 0x00000000ff03aa12 */
/* 0x000fc800078e33ff */
/*01e0*/ IMNMX.U32 R4, R3, 0x1, !PT ; /* 0x0000000103047817 */
/* 0x000fc80007800000 */
/*01f0*/ IADD3 R2, R4.reuse, -0x1, RZ ; /* 0xffffffff04027810 */
/* 0x040fe40007ffe0ff */
/*0200*/ LOP3.LUT R7, R4, 0x3, RZ, 0xc0, !PT ; /* 0x0000000304077812 */
/* 0x000fe400078ec0ff */
/*0210*/ ISETP.GE.U32.AND P1, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fe20003f26070 */
/*0220*/ IMAD.WIDE R2, R0, R17, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fe200078e0211 */
/*0230*/ ISETP.NE.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fd60003f05270 */
/*0240*/ @!P1 BRA 0x3e0 ; /* 0x0000019000009947 */
/* 0x000fea0003800000 */
/*0250*/ LDG.E R9, [R2.64] ; /* 0x0000000402097981 */
/* 0x000162000c1e1900 */
/*0260*/ IMAD.IADD R0, R4, 0x1, -R7 ; /* 0x0000000104007824 */
/* 0x000fe200078e0a07 */
/*0270*/ MOV R8, c[0x0][0x168] ; /* 0x00005a0000087a02 */
/* 0x000fe20000000f00 */
/*0280*/ IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff067224 */
/* 0x000fe400078e00ff */
/*0290*/ IMAD.MOV.U32 R11, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff0b7624 */
/* 0x000fe400078e00ff */
/*02a0*/ IMAD.MOV.U32 R4, RZ, RZ, R8 ; /* 0x000000ffff047224 */
/* 0x000fe400078e0008 */
/*02b0*/ IMAD.MOV.U32 R5, RZ, RZ, R11 ; /* 0x000000ffff057224 */
/* 0x000fca00078e000b */
/*02c0*/ LDG.E R8, [R4.64] ; /* 0x0000000404087981 */
/* 0x004ea4000c1e1900 */
/*02d0*/ FADD R11, R8, R9 ; /* 0x00000009080b7221 */
/* 0x024fca0000000000 */
/*02e0*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x0003e8000c101904 */
/*02f0*/ LDG.E R8, [R4.64+0x4] ; /* 0x0000040404087981 */
/* 0x000ea4000c1e1900 */
/*0300*/ FADD R13, R11, R8 ; /* 0x000000080b0d7221 */
/* 0x004fca0000000000 */
/*0310*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x0005e8000c101904 */
/*0320*/ LDG.E R8, [R4.64+0x8] ; /* 0x0000080404087981 */
/* 0x000ee4000c1e1900 */
/*0330*/ FADD R15, R13, R8 ; /* 0x000000080d0f7221 */
/* 0x008fca0000000000 */
/*0340*/ STG.E [R2.64], R15 ; /* 0x0000000f02007986 */
/* 0x0005e8000c101904 */
/*0350*/ LDG.E R8, [R4.64+0xc] ; /* 0x00000c0404087981 */
/* 0x000ee2000c1e1900 */
/*0360*/ IADD3 R0, R0, -0x4, RZ ; /* 0xfffffffc00007810 */
/* 0x000fe40007ffe0ff */
/*0370*/ IADD3 R6, R6, 0x4, RZ ; /* 0x0000000406067810 */
/* 0x000fe40007ffe0ff */
/*0380*/ ISETP.NE.AND P1, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe20003f25270 */
/*0390*/ FADD R9, R15, R8 ; /* 0x000000080f097221 */
/* 0x008fe20000000000 */
/*03a0*/ IADD3 R8, P2, R4, 0x10, RZ ; /* 0x0000001004087810 */
/* 0x000fc80007f5e0ff */
/*03b0*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x0005e2000c101904 */
/*03c0*/ IADD3.X R11, RZ, R5, RZ, P2, !PT ; /* 0x00000005ff0b7210 */
/* 0x002fcc00017fe4ff */
/*03d0*/ @P1 BRA 0x2a0 ; /* 0xfffffec000001947 */
/* 0x000fea000383ffff */
/*03e0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*03f0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0400*/ LDG.E R9, [R2.64] ; /* 0x0000000402097981 */
/* 0x004362000c1e1900 */
/*0410*/ IMAD.WIDE R4, R6, R17, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x000fca00078e0211 */
/*0420*/ LDG.E R0, [R4.64] ; /* 0x0000000404007981 */
/* 0x0044e2000c1e1900 */
/*0430*/ IADD3 R7, R7, -0x1, RZ ; /* 0xffffffff07077810 */
/* 0x000fc80007ffe0ff */
/*0440*/ ISETP.NE.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fe40003f05270 */
/*0450*/ IADD3 R4, P1, R4, 0x4, RZ ; /* 0x0000000404047810 */
/* 0x004fca0007f3e0ff */
/*0460*/ IMAD.X R5, RZ, RZ, R5, P1 ; /* 0x000000ffff057224 */
/* 0x000fe400008e0605 */
/*0470*/ FADD R9, R0, R9 ; /* 0x0000000900097221 */
/* 0x028fca0000000000 */
/*0480*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x0005e2000c101904 */
/*0490*/ @P0 BRA 0x420 ; /* 0xffffff8000000947 */
/* 0x000fea000383ffff */
/*04a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*04b0*/ BRA 0x4b0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*04c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0500*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0510*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0520*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0530*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0540*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0550*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0560*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0570*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6helperPfS_i
.globl _Z6helperPfS_i
.p2align 8
.type _Z6helperPfS_i,@function
_Z6helperPfS_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s2, 0xffff
s_mov_b32 s2, exec_lo
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_4
v_cmp_le_u32_e32 vcc_lo, s4, v1
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_4
s_load_b128 s[0:3], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
v_cvt_f32_u32_e32 v4, s4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[2:3], 2, v[1:2]
v_rcp_iflag_f32_e32 v4, v4
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v4, 0x4f7ffffe, v4
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s0, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_3)
v_cvt_u32_f32_e32 v4, v4
s_sub_i32 s0, 0, s4
s_mov_b32 s1, 0
global_load_b32 v0, v[2:3], off
v_mul_lo_u32 v5, s0, v4
s_mov_b32 s0, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v5, v4, v5
v_add_nc_u32_e32 v6, v4, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[4:5], null, v1, v6, 0
v_mul_lo_u32 v4, v5, s4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v1, v1, v4
v_add_nc_u32_e32 v4, 1, v5
v_subrev_nc_u32_e32 v6, s4, v1
v_cmp_le_u32_e32 vcc_lo, s4, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_cndmask_b32_e32 v1, v1, v6, vcc_lo
v_cndmask_b32_e32 v4, v5, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_le_u32_e32 vcc_lo, s4, v1
v_add_nc_u32_e32 v5, 1, v4
s_delay_alu instid0(VALU_DEP_1)
v_dual_cndmask_b32 v1, v4, v5 :: v_dual_mov_b32 v4, 0
.LBB0_3:
global_load_b32 v5, v4, s[2:3]
s_add_i32 s1, s1, 1
s_add_u32 s2, s2, 4
v_cmp_ge_u32_e32 vcc_lo, s1, v1
s_addc_u32 s3, s3, 0
s_or_b32 s0, vcc_lo, s0
s_waitcnt vmcnt(0)
v_add_f32_e32 v0, v5, v0
global_store_b32 v[2:3], v0, off
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB0_3
.LBB0_4:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6helperPfS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6helperPfS_i, .Lfunc_end0-_Z6helperPfS_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6helperPfS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6helperPfS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001164f3_00000000-6_helper.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z28__device_stub__Z6helperPfS_iPfS_i
.type _Z28__device_stub__Z6helperPfS_iPfS_i, @function
_Z28__device_stub__Z6helperPfS_iPfS_i:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6helperPfS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z28__device_stub__Z6helperPfS_iPfS_i, .-_Z28__device_stub__Z6helperPfS_iPfS_i
.globl _Z6helperPfS_i
.type _Z6helperPfS_i, @function
_Z6helperPfS_i:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z28__device_stub__Z6helperPfS_iPfS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z6helperPfS_i, .-_Z6helperPfS_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z6helperPfS_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z6helperPfS_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "helper.hip"
.globl _Z21__device_stub__helperPfS_i # -- Begin function _Z21__device_stub__helperPfS_i
.p2align 4, 0x90
.type _Z21__device_stub__helperPfS_i,@function
_Z21__device_stub__helperPfS_i: # @_Z21__device_stub__helperPfS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6helperPfS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z21__device_stub__helperPfS_i, .Lfunc_end0-_Z21__device_stub__helperPfS_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6helperPfS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6helperPfS_i,@object # @_Z6helperPfS_i
.section .rodata,"a",@progbits
.globl _Z6helperPfS_i
.p2align 3, 0x0
_Z6helperPfS_i:
.quad _Z21__device_stub__helperPfS_i
.size _Z6helperPfS_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z6helperPfS_i"
.size .L__unnamed_1, 15
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__helperPfS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6helperPfS_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void LoadVec(float *vector , float2 *FFT) {
int idx = threadIdx.x + blockIdx.x*blockDim.x; // this should span the full range of the vector
FFT[idx].x = vector[idx]; // The real part is replaced by the vector value
FFT[idx].y = 0.0f; // The imaginary part is zero. The following kernel also replaces the imaginary part
} | code for sm_80
Function : _Z7LoadVecPfP6float2
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_TID.X ; /* 0x0000000000047919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0050*/ IMAD R4, R3, c[0x0][0x0], R4 ; /* 0x0000000003047a24 */
/* 0x001fca00078e0204 */
/*0060*/ IMAD.WIDE R2, R4, R5, c[0x0][0x160] ; /* 0x0000580004027625 */
/* 0x000fca00078e0205 */
/*0070*/ LDG.E R6, [R2.64] ; /* 0x0000000402067981 */
/* 0x000ea2000c1e1900 */
/*0080*/ HFMA2.MMA R5, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff057435 */
/* 0x000fe200000001ff */
/*0090*/ MOV R7, RZ ; /* 0x000000ff00077202 */
/* 0x000fd20000000f00 */
/*00a0*/ IMAD.WIDE R4, R4, R5, c[0x0][0x168] ; /* 0x00005a0004047625 */
/* 0x000fca00078e0205 */
/*00b0*/ STG.E.64 [R4.64], R6 ; /* 0x0000000604007986 */
/* 0x004fe2000c101b04 */
/*00c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00d0*/ BRA 0xd0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void LoadVec(float *vector , float2 *FFT) {
int idx = threadIdx.x + blockIdx.x*blockDim.x; // this should span the full range of the vector
FFT[idx].x = vector[idx]; // The real part is replaced by the vector value
FFT[idx].y = 0.0f; // The imaginary part is zero. The following kernel also replaces the imaginary part
} | .file "tmpxft_0001aca8_00000000-6_LoadVec.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z34__device_stub__Z7LoadVecPfP6float2PfP6float2
.type _Z34__device_stub__Z7LoadVecPfP6float2PfP6float2, @function
_Z34__device_stub__Z7LoadVecPfP6float2PfP6float2:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z7LoadVecPfP6float2(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z34__device_stub__Z7LoadVecPfP6float2PfP6float2, .-_Z34__device_stub__Z7LoadVecPfP6float2PfP6float2
.globl _Z7LoadVecPfP6float2
.type _Z7LoadVecPfP6float2, @function
_Z7LoadVecPfP6float2:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z34__device_stub__Z7LoadVecPfP6float2PfP6float2
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z7LoadVecPfP6float2, .-_Z7LoadVecPfP6float2
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z7LoadVecPfP6float2"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z7LoadVecPfP6float2(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void LoadVec(float *vector , float2 *FFT) {
int idx = threadIdx.x + blockIdx.x*blockDim.x; // this should span the full range of the vector
FFT[idx].x = vector[idx]; // The real part is replaced by the vector value
FFT[idx].y = 0.0f; // The imaginary part is zero. The following kernel also replaces the imaginary part
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void LoadVec(float *vector , float2 *FFT) {
int idx = threadIdx.x + blockIdx.x*blockDim.x; // this should span the full range of the vector
FFT[idx].x = vector[idx]; // The real part is replaced by the vector value
FFT[idx].y = 0.0f; // The imaginary part is zero. The following kernel also replaces the imaginary part
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void LoadVec(float *vector , float2 *FFT) {
int idx = threadIdx.x + blockIdx.x*blockDim.x; // this should span the full range of the vector
FFT[idx].x = vector[idx]; // The real part is replaced by the vector value
FFT[idx].y = 0.0f; // The imaginary part is zero. The following kernel also replaces the imaginary part
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z7LoadVecPfP15HIP_vector_typeIfLj2EE
.globl _Z7LoadVecPfP15HIP_vector_typeIfLj2EE
.p2align 8
.type _Z7LoadVecPfP15HIP_vector_typeIfLj2EE,@function
_Z7LoadVecPfP15HIP_vector_typeIfLj2EE:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x1c
s_load_b128 s[0:3], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[3:4], 2, v[1:2]
v_lshlrev_b64 v[1:2], 3, v[1:2]
v_add_co_u32 v3, vcc_lo, s0, v3
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
global_load_b32 v0, v[3:4], off
v_add_co_u32 v3, vcc_lo, s2, v1
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v2, vcc_lo
v_mov_b32_e32 v1, 0
s_waitcnt vmcnt(0)
global_store_b64 v[3:4], v[0:1], off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7LoadVecPfP15HIP_vector_typeIfLj2EE
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z7LoadVecPfP15HIP_vector_typeIfLj2EE, .Lfunc_end0-_Z7LoadVecPfP15HIP_vector_typeIfLj2EE
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7LoadVecPfP15HIP_vector_typeIfLj2EE
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z7LoadVecPfP15HIP_vector_typeIfLj2EE.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void LoadVec(float *vector , float2 *FFT) {
int idx = threadIdx.x + blockIdx.x*blockDim.x; // this should span the full range of the vector
FFT[idx].x = vector[idx]; // The real part is replaced by the vector value
FFT[idx].y = 0.0f; // The imaginary part is zero. The following kernel also replaces the imaginary part
} | .text
.file "LoadVec.hip"
.globl _Z22__device_stub__LoadVecPfP15HIP_vector_typeIfLj2EE # -- Begin function _Z22__device_stub__LoadVecPfP15HIP_vector_typeIfLj2EE
.p2align 4, 0x90
.type _Z22__device_stub__LoadVecPfP15HIP_vector_typeIfLj2EE,@function
_Z22__device_stub__LoadVecPfP15HIP_vector_typeIfLj2EE: # @_Z22__device_stub__LoadVecPfP15HIP_vector_typeIfLj2EE
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z7LoadVecPfP15HIP_vector_typeIfLj2EE, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z22__device_stub__LoadVecPfP15HIP_vector_typeIfLj2EE, .Lfunc_end0-_Z22__device_stub__LoadVecPfP15HIP_vector_typeIfLj2EE
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7LoadVecPfP15HIP_vector_typeIfLj2EE, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z7LoadVecPfP15HIP_vector_typeIfLj2EE,@object # @_Z7LoadVecPfP15HIP_vector_typeIfLj2EE
.section .rodata,"a",@progbits
.globl _Z7LoadVecPfP15HIP_vector_typeIfLj2EE
.p2align 3, 0x0
_Z7LoadVecPfP15HIP_vector_typeIfLj2EE:
.quad _Z22__device_stub__LoadVecPfP15HIP_vector_typeIfLj2EE
.size _Z7LoadVecPfP15HIP_vector_typeIfLj2EE, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z7LoadVecPfP15HIP_vector_typeIfLj2EE"
.size .L__unnamed_1, 38
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__LoadVecPfP15HIP_vector_typeIfLj2EE
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7LoadVecPfP15HIP_vector_typeIfLj2EE
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z7LoadVecPfP6float2
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_TID.X ; /* 0x0000000000047919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0050*/ IMAD R4, R3, c[0x0][0x0], R4 ; /* 0x0000000003047a24 */
/* 0x001fca00078e0204 */
/*0060*/ IMAD.WIDE R2, R4, R5, c[0x0][0x160] ; /* 0x0000580004027625 */
/* 0x000fca00078e0205 */
/*0070*/ LDG.E R6, [R2.64] ; /* 0x0000000402067981 */
/* 0x000ea2000c1e1900 */
/*0080*/ HFMA2.MMA R5, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff057435 */
/* 0x000fe200000001ff */
/*0090*/ MOV R7, RZ ; /* 0x000000ff00077202 */
/* 0x000fd20000000f00 */
/*00a0*/ IMAD.WIDE R4, R4, R5, c[0x0][0x168] ; /* 0x00005a0004047625 */
/* 0x000fca00078e0205 */
/*00b0*/ STG.E.64 [R4.64], R6 ; /* 0x0000000604007986 */
/* 0x004fe2000c101b04 */
/*00c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00d0*/ BRA 0xd0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z7LoadVecPfP15HIP_vector_typeIfLj2EE
.globl _Z7LoadVecPfP15HIP_vector_typeIfLj2EE
.p2align 8
.type _Z7LoadVecPfP15HIP_vector_typeIfLj2EE,@function
_Z7LoadVecPfP15HIP_vector_typeIfLj2EE:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x1c
s_load_b128 s[0:3], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[3:4], 2, v[1:2]
v_lshlrev_b64 v[1:2], 3, v[1:2]
v_add_co_u32 v3, vcc_lo, s0, v3
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
global_load_b32 v0, v[3:4], off
v_add_co_u32 v3, vcc_lo, s2, v1
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v2, vcc_lo
v_mov_b32_e32 v1, 0
s_waitcnt vmcnt(0)
global_store_b64 v[3:4], v[0:1], off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7LoadVecPfP15HIP_vector_typeIfLj2EE
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z7LoadVecPfP15HIP_vector_typeIfLj2EE, .Lfunc_end0-_Z7LoadVecPfP15HIP_vector_typeIfLj2EE
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7LoadVecPfP15HIP_vector_typeIfLj2EE
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z7LoadVecPfP15HIP_vector_typeIfLj2EE.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0001aca8_00000000-6_LoadVec.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z34__device_stub__Z7LoadVecPfP6float2PfP6float2
.type _Z34__device_stub__Z7LoadVecPfP6float2PfP6float2, @function
_Z34__device_stub__Z7LoadVecPfP6float2PfP6float2:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z7LoadVecPfP6float2(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z34__device_stub__Z7LoadVecPfP6float2PfP6float2, .-_Z34__device_stub__Z7LoadVecPfP6float2PfP6float2
.globl _Z7LoadVecPfP6float2
.type _Z7LoadVecPfP6float2, @function
_Z7LoadVecPfP6float2:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z34__device_stub__Z7LoadVecPfP6float2PfP6float2
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z7LoadVecPfP6float2, .-_Z7LoadVecPfP6float2
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z7LoadVecPfP6float2"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z7LoadVecPfP6float2(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "LoadVec.hip"
.globl _Z22__device_stub__LoadVecPfP15HIP_vector_typeIfLj2EE # -- Begin function _Z22__device_stub__LoadVecPfP15HIP_vector_typeIfLj2EE
.p2align 4, 0x90
.type _Z22__device_stub__LoadVecPfP15HIP_vector_typeIfLj2EE,@function
_Z22__device_stub__LoadVecPfP15HIP_vector_typeIfLj2EE: # @_Z22__device_stub__LoadVecPfP15HIP_vector_typeIfLj2EE
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z7LoadVecPfP15HIP_vector_typeIfLj2EE, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z22__device_stub__LoadVecPfP15HIP_vector_typeIfLj2EE, .Lfunc_end0-_Z22__device_stub__LoadVecPfP15HIP_vector_typeIfLj2EE
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7LoadVecPfP15HIP_vector_typeIfLj2EE, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z7LoadVecPfP15HIP_vector_typeIfLj2EE,@object # @_Z7LoadVecPfP15HIP_vector_typeIfLj2EE
.section .rodata,"a",@progbits
.globl _Z7LoadVecPfP15HIP_vector_typeIfLj2EE
.p2align 3, 0x0
_Z7LoadVecPfP15HIP_vector_typeIfLj2EE:
.quad _Z22__device_stub__LoadVecPfP15HIP_vector_typeIfLj2EE
.size _Z7LoadVecPfP15HIP_vector_typeIfLj2EE, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z7LoadVecPfP15HIP_vector_typeIfLj2EE"
.size .L__unnamed_1, 38
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__LoadVecPfP15HIP_vector_typeIfLj2EE
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7LoadVecPfP15HIP_vector_typeIfLj2EE
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <cuda_runtime_api.h>
#include <cassert>
#include <cstdio>
#include <cstdlib>
#include <cmath>
#include <random>
#include <cooperative_groups.h>
/*
WRITE CUDA KERNEL FOR COUNT HERE
*/
__device__
int log_2(float x){
int count = 0;
while(x>1){
x/=2;
count++;
}
return count;
}
__global__
void parallel_implementation(int * data, int vals,int * tmp_data, int * output_data){
int blocks = gridDim.x;
int start_index = threadIdx.x + (vals*blockIdx.x)/blocks;
int end_index = (vals*(blockIdx.x+1))/blocks;
int layers = log_2(vals);
//printf("Layers = %d",layers);
//sync stuff
//grid_group g = this_grid();
//data works as previous layer holder
//output_data works as current layer holder
//Hillis-Steele Algorithm
for(int layer = 0; layer < layers; layer++){
//for each layer
//if(blockIdx.x==0 && threadIdx.x==vals) printf("layer %d",layer);
for(int i = start_index;i<end_index;i+=blockDim.x){//move in strides the size of the block
//for each element in the array
int neighbor_i = i-pow(2,layer);
if(neighbor_i>=0){
output_data[i]+=data[neighbor_i];//update output
//tmp_data[i]+=data[i-pow(2,layer)];//update holder container
//test removal tmp_data[i]=output_data[i];
}
}
__syncthreads();/*
if(blockIdx.x==0 && threadIdx.x==0){//copy new array over to data
//swap new layers data int "data" for next round
//int * tmp = data;
//data = tmp_data;
//tmp_data = tmp;
for i
}*/
//if(blockIdx.x==0 && threadIdx.x==0) for (int i = 0; i<vals;i++) printf("%d\n",output_data[i]);
//prep for next layer
for(int i = start_index;i<end_index;i+=blockDim.x){
data[i] = output_data[i];
}
__syncthreads();//sync threads across all blocks before next layer
}
//bug removal fix later
__syncthreads();
if(blockIdx.x==0 && threadIdx.x==0)for(int i = 2047; i<vals;i+=4096) output_data[i]-=data[0];
}
int * serial_implementation(int * data, int vals) {
int * output = (int *)malloc(sizeof(int) * vals);
output[0] = 0;
for (int i = 1; i < vals; i++) {
output[i] = output[i-1] + data[i-1];
}
return output;
}
int main(int argc, char ** argv) {
assert(argc == 2);
int values = atoi(argv[1]); // Values is guaranteed to be no more than 10000000
int * data = (int *)malloc(sizeof(int) * values);
// Generate "random" vector
std::mt19937 gen(13); // Keep constant to maintain determinism between runs
std::uniform_int_distribution<> dist(0, 50);
for (int i = 0; i < values; i++) {
data[i] = dist(gen);
}
cudaStream_t stream;
cudaEvent_t begin, end;
cudaStreamCreate(&stream);
cudaEventCreate(&begin);
cudaEventCreate(&end);
int * h_output = (int *)malloc(sizeof(int) * (1+values)); // THIS VARIABLE SHOULD HOLD THE TOTAL COUNT BY THE END
/*
PERFORM NECESSARY VARIABLE DECLARATIONS HERE
PERFORM NECESSARY DATA TRANSFER HERE
*/
int * gpu_data;
int * gpu_output_data;
int * gpu_tmp_data;
//Determine allocation size
int array_size = sizeof(int)*values;
//Allocate memory on GPU
cudaMalloc(&gpu_data, array_size);
cudaMalloc(&gpu_output_data, array_size);
cudaMalloc(&gpu_tmp_data, array_size);
//cudaMalloc(&gpu_data, array_size+sizeof(int));
//cudaMalloc(&gpu_output_data, array_size+sizeof(int));
//cudaMalloc(&gpu_tmp_data, array_size+sizeof(int));
//Copy data to GPU
cudaMemcpy(gpu_data,data,array_size,cudaMemcpyHostToDevice);
cudaMemcpy(gpu_output_data,data,array_size,cudaMemcpyHostToDevice);
cudaMemcpy(gpu_tmp_data,data,array_size,cudaMemcpyHostToDevice);
//cudaMemcpy(gpu_data+sizeof(int),data,array_size,cudaMemcpyHostToDevice);
//cudaMemcpy(gpu_output_data+sizeof(int),data,array_size,cudaMemcpyHostToDevice);
//cudaMemcpy(gpu_tmp_data+sizeof(int),data,array_size,cudaMemcpyHostToDevice);
cudaEventRecord(begin, stream);
/*
LAUNCH KERNEL HERE
*/
int THREADS_PER_BLOCK = 1024;//128 ideal
int BLOCKS = 1;//16 ideal
dim3 block(THREADS_PER_BLOCK);
dim3 grid(BLOCKS);
parallel_implementation<<<grid,block,0,stream>>>(gpu_data,values,gpu_tmp_data,gpu_output_data);
cudaEventRecord(end, stream);
/*
PERFORM NECESSARY DATA TRANSFER HERE
*/
cudaMemcpy(h_output+1, gpu_output_data, array_size, cudaMemcpyDeviceToHost);
h_output[0] = 0;
cudaStreamSynchronize(stream);
float ms;
cudaEventElapsedTime(&ms, begin, end);
printf("Elapsed time: %f ms\n", ms);
/*
DEALLOCATE RESOURCES HERE
*/
cudaFree(gpu_data);
cudaFree(gpu_output_data);
cudaFree(gpu_tmp_data);
int * reference_output = serial_implementation(data, values);
for (int i = 0; i < values; i++) {
if (reference_output[i] != h_output[i]) {
printf("ERROR: %d != %d at index %d. Off by %d\n", reference_output[i], h_output[i], i,reference_output[i]- h_output[i]);
/* printf("V | C | GPU\n");
for(int j = 0; j< values;j++){
printf("%d | %d | %d\n",data[j],reference_output[j],h_output[j]);
}*/
//abort();
}
}
cudaEventDestroy(begin);
cudaEventDestroy(end);
cudaStreamDestroy(stream);
free(data);
free(reference_output);
free(h_output);
return 0;
} | .file "tmpxft_001826c0_00000000-6_scan.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB7682:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE7682:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z5log_2f
.type _Z5log_2f, @function
_Z5log_2f:
.LFB7677:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE7677:
.size _Z5log_2f, .-_Z5log_2f
.globl _Z21serial_implementationPii
.type _Z21serial_implementationPii, @function
_Z21serial_implementationPii:
.LFB7678:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movq %rdi, %rbx
movl %esi, %ebp
movslq %esi, %rdi
salq $2, %rdi
call malloc@PLT
movl $0, (%rax)
cmpl $1, %ebp
jle .L5
leal -1(%rbp), %esi
movl $0, %edx
.L7:
movl (%rbx,%rdx,4), %ecx
addl (%rax,%rdx,4), %ecx
movl %ecx, 4(%rax,%rdx,4)
addq $1, %rdx
cmpq %rsi, %rdx
jne .L7
.L5:
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE7678:
.size _Z21serial_implementationPii, .-_Z21serial_implementationPii
.globl _Z48__device_stub__Z23parallel_implementationPiiS_S_PiiS_S_
.type _Z48__device_stub__Z23parallel_implementationPiiS_S_PiiS_S_, @function
_Z48__device_stub__Z23parallel_implementationPiiS_S_PiiS_S_:
.LFB7704:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movq %rdx, 8(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L14
.L10:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L15
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z23parallel_implementationPiiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L10
.L15:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE7704:
.size _Z48__device_stub__Z23parallel_implementationPiiS_S_PiiS_S_, .-_Z48__device_stub__Z23parallel_implementationPiiS_S_PiiS_S_
.globl _Z23parallel_implementationPiiS_S_
.type _Z23parallel_implementationPiiS_S_, @function
_Z23parallel_implementationPiiS_S_:
.LFB7705:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z48__device_stub__Z23parallel_implementationPiiS_S_PiiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE7705:
.size _Z23parallel_implementationPiiS_S_, .-_Z23parallel_implementationPiiS_S_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z23parallel_implementationPiiS_S_"
.align 8
.LC1:
.string "_ZN37_INTERNAL_feca0e03_7_scan_cu_99bbe6644cuda3std3__419piecewise_constructE"
.align 8
.LC2:
.string "_ZN37_INTERNAL_feca0e03_7_scan_cu_99bbe6644cuda3std6ranges3__45__cpo4swapE"
.align 8
.LC3:
.string "_ZN37_INTERNAL_feca0e03_7_scan_cu_99bbe6644cuda3std6ranges3__45__cpo9iter_moveE"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB7707:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z23parallel_implementationPiiS_S_(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $1, %r9d
movl $0, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _ZN4cuda3std3__419piecewise_constructE(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $1, %r9d
movl $0, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _ZN4cuda3std6ranges3__45__cpo4swapE(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $1, %r9d
movl $0, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _ZN4cuda3std6ranges3__45__cpo9iter_moveE(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE7707:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .text._ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EE11_M_gen_randEv,"axG",@progbits,_ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EE11_M_gen_randEv,comdat
.align 2
.weak _ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EE11_M_gen_randEv
.type _ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EE11_M_gen_randEv, @function
_ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EE11_M_gen_randEv:
.LFB8565:
.cfi_startproc
endbr64
movq %rdi, %rdx
leaq 1816(%rdi), %r9
movq %rdi, %rcx
movl $2567483615, %r8d
.L22:
movq (%rcx), %rax
andq $-2147483648, %rax
movq 8(%rcx), %rsi
andl $2147483647, %esi
orq %rsi, %rax
movq %rax, %rsi
shrq %rsi
xorq 3176(%rcx), %rsi
andl $1, %eax
cmovne %r8, %rax
xorq %rsi, %rax
movq %rax, (%rcx)
addq $8, %rcx
cmpq %r9, %rcx
jne .L22
leaq 3168(%rdi), %r8
movl $2567483615, %esi
.L24:
movq 1816(%rdx), %rax
andq $-2147483648, %rax
movq 1824(%rdx), %rcx
andl $2147483647, %ecx
orq %rcx, %rax
movq %rax, %rcx
shrq %rcx
xorq (%rdx), %rcx
andl $1, %eax
cmovne %rsi, %rax
xorq %rcx, %rax
movq %rax, 1816(%rdx)
addq $8, %rdx
cmpq %r8, %rdx
jne .L24
movq 4984(%rdi), %rax
andq $-2147483648, %rax
movq (%rdi), %rdx
andl $2147483647, %edx
orq %rdx, %rax
movq %rax, %rdx
shrq %rdx
xorq 3168(%rdi), %rdx
andl $1, %eax
movl $2567483615, %ecx
cmovne %rcx, %rax
xorq %rdx, %rax
movq %rax, 4984(%rdi)
movq $0, 4992(%rdi)
ret
.cfi_endproc
.LFE8565:
.size _ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EE11_M_gen_randEv, .-_ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EE11_M_gen_randEv
.section .text._ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv,"axG",@progbits,_ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv,comdat
.align 2
.weak _ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv
.type _ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv, @function
_ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv:
.LFB8476:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movq %rdi, %rbx
cmpq $623, 4992(%rdi)
ja .L31
.L29:
movq 4992(%rbx), %rax
leaq 1(%rax), %rdx
movq %rdx, 4992(%rbx)
movq (%rbx,%rax,8), %rax
movq %rax, %rdx
shrq $11, %rdx
movl %edx, %edx
xorq %rax, %rdx
movq %rdx, %rax
salq $7, %rax
andl $2636928640, %eax
xorq %rdx, %rax
movq %rax, %rdx
salq $15, %rdx
andl $4022730752, %edx
xorq %rax, %rdx
movq %rdx, %rax
shrq $18, %rax
xorq %rdx, %rax
popq %rbx
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L31:
.cfi_restore_state
call _ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EE11_M_gen_randEv
jmp .L29
.cfi_endproc
.LFE8476:
.size _ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv, .-_ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv
.section .text._ZNSt24uniform_int_distributionIiEclISt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEEEiRT_RKNS0_10param_typeE,"axG",@progbits,_ZNSt24uniform_int_distributionIiEclISt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEEEiRT_RKNS0_10param_typeE,comdat
.align 2
.weak _ZNSt24uniform_int_distributionIiEclISt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEEEiRT_RKNS0_10param_typeE
.type _ZNSt24uniform_int_distributionIiEclISt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEEEiRT_RKNS0_10param_typeE, @function
_ZNSt24uniform_int_distributionIiEclISt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEEEiRT_RKNS0_10param_typeE:
.LFB8362:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $24, %rsp
.cfi_def_cfa_offset 80
movq %rsi, %rbp
movq %rdx, %r12
movq %fs:40, %rax
movq %rax, 8(%rsp)
xorl %eax, %eax
movslq 4(%rdx), %rbx
movslq (%rdx), %rax
subq %rax, %rbx
movl $4294967294, %eax
cmpq %rbx, %rax
jnb .L43
movq %rdi, %r14
movq %rbx, %rax
shrq $32, %rax
je .L37
movq %rsp, %r15
.L41:
movl $0, (%rsp)
movl $-1, 4(%rsp)
movq %r15, %rdx
movq %rbp, %rsi
movq %r14, %rdi
call _ZNSt24uniform_int_distributionIiEclISt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEEEiRT_RKNS0_10param_typeE
movq %rax, %r13
salq $32, %r13
movq %rbp, %rdi
call _ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv
addq %r13, %rax
cmpq %rax, %rbx
jb .L41
cmpq %r13, %rax
jb .L41
jmp .L36
.L43:
addq $1, %rbx
movq %rsi, %rdi
call _ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv
imulq %rbx, %rax
movq %rax, %rcx
cmpl %ebx, %eax
jnb .L34
movl %ebx, %eax
negl %eax
movl $0, %edx
divl %ebx
movl %edx, %r13d
cmpl %edx, %ecx
jnb .L34
.L35:
movq %rbp, %rdi
call _ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv
imulq %rbx, %rax
movq %rax, %rcx
cmpl %r13d, %eax
jb .L35
.L34:
movq %rcx, %rax
shrq $32, %rax
.L36:
addl (%r12), %eax
movq 8(%rsp), %rdx
subq %fs:40, %rdx
jne .L44
addq $24, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L37:
.cfi_restore_state
movq %rsi, %rdi
call _ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv
jmp .L36
.L44:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE8362:
.size _ZNSt24uniform_int_distributionIiEclISt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEEEiRT_RKNS0_10param_typeE, .-_ZNSt24uniform_int_distributionIiEclISt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEEEiRT_RKNS0_10param_typeE
.section .rodata.str1.1,"aMS",@progbits,1
.LC4:
.string "Elapsed time: %f ms\n"
.section .rodata.str1.8
.align 8
.LC5:
.string "ERROR: %d != %d at index %d. Off by %d\n"
.text
.globl main
.type main, @function
main:
.LFB7679:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $4096, %rsp
.cfi_def_cfa_offset 4152
orq $0, (%rsp)
subq $1032, %rsp
.cfi_def_cfa_offset 5184
movq %fs:40, %rax
movq %rax, 5112(%rsp)
xorl %eax, %eax
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %r15
movl %eax, 4(%rsp)
movslq %eax, %r12
leaq 0(,%r12,4), %rax
movq %rax, 8(%rsp)
movq %rax, %rdi
call malloc@PLT
movq %rax, %r13
movq $13, 112(%rsp)
movl $1, %ecx
movabsq $945986875574848801, %rdi
.L46:
movq 104(%rsp,%rcx,8), %rax
movq %rax, %rdx
shrq $30, %rdx
xorq %rdx, %rax
imulq $1812433253, %rax, %rsi
movq %rcx, %rdx
shrq $4, %rdx
movq %rdx, %rax
mulq %rdi
shrq %rdx
imulq $624, %rdx, %rdx
movq %rcx, %rax
subq %rdx, %rax
addl %esi, %eax
movq %rax, 112(%rsp,%rcx,8)
addq $1, %rcx
cmpq $624, %rcx
jne .L46
movq $624, 5104(%rsp)
movl $0, 80(%rsp)
movl $50, 84(%rsp)
testl %r15d, %r15d
jle .L47
movq %r13, %rbx
leal -1(%r15), %eax
leaq 4(%r13,%rax,4), %r14
leaq 80(%rsp), %rbp
.L48:
leaq 112(%rsp), %rsi
movq %rbp, %rdx
movq %rbp, %rdi
call _ZNSt24uniform_int_distributionIiEclISt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEEEiRT_RKNS0_10param_typeE
movl %eax, (%rbx)
addq $4, %rbx
cmpq %r14, %rbx
jne .L48
.L47:
leaq 32(%rsp), %rdi
call cudaStreamCreate@PLT
leaq 40(%rsp), %rdi
call cudaEventCreate@PLT
leaq 48(%rsp), %rdi
call cudaEventCreate@PLT
movq 8(%rsp), %rdi
addq $4, %rdi
call malloc@PLT
movq %rax, %rbp
leal 0(,%r12,4), %ebx
movslq %ebx, %rbx
leaq 56(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 64(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 72(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %r13, %rsi
movq 56(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %r13, %rsi
movq 64(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %r13, %rsi
movq 72(%rsp), %rdi
call cudaMemcpy@PLT
movq 32(%rsp), %rsi
movq 40(%rsp), %rdi
call cudaEventRecord@PLT
movl $1024, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
movl $1, 104(%rsp)
movl $1, 108(%rsp)
movq 32(%rsp), %r9
movl $0, %r8d
movq 88(%rsp), %rdx
movl $1, %ecx
movq 100(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L58
.L49:
movq 32(%rsp), %rsi
movq 48(%rsp), %rdi
call cudaEventRecord@PLT
leaq 4(%rbp), %rdi
movl $2, %ecx
movq %rbx, %rdx
movq 64(%rsp), %rsi
call cudaMemcpy@PLT
movl $0, 0(%rbp)
movq 32(%rsp), %rdi
call cudaStreamSynchronize@PLT
leaq 28(%rsp), %rdi
movq 48(%rsp), %rdx
movq 40(%rsp), %rsi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtss2sd 28(%rsp), %xmm0
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 56(%rsp), %rdi
call cudaFree@PLT
movq 64(%rsp), %rdi
call cudaFree@PLT
movq 72(%rsp), %rdi
call cudaFree@PLT
movl 4(%rsp), %esi
movq %r13, %rdi
call _Z21serial_implementationPii
movq %rax, %r12
testl %r15d, %r15d
jle .L50
leal -1(%r15), %r14d
movl $0, %ebx
leaq .LC5(%rip), %r15
jmp .L52
.L58:
movq 64(%rsp), %rcx
movq 72(%rsp), %rdx
movl 4(%rsp), %esi
movq 56(%rsp), %rdi
call _Z48__device_stub__Z23parallel_implementationPiiS_S_PiiS_S_
jmp .L49
.L51:
leaq 1(%rbx), %rax
cmpq %r14, %rbx
je .L50
movq %rax, %rbx
.L52:
movl (%r12,%rbx,4), %edx
movl 0(%rbp,%rbx,4), %ecx
cmpl %ecx, %edx
je .L51
movl %edx, %r9d
subl %ecx, %r9d
movl %ebx, %r8d
movq %r15, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L51
.L50:
movq 40(%rsp), %rdi
call cudaEventDestroy@PLT
movq 48(%rsp), %rdi
call cudaEventDestroy@PLT
movq 32(%rsp), %rdi
call cudaStreamDestroy@PLT
movq %r13, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
movq %rbp, %rdi
call free@PLT
movq 5112(%rsp), %rax
subq %fs:40, %rax
jne .L59
movl $0, %eax
addq $5128, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L59:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE7679:
.size main, .-main
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.weak _ZN4cuda3std3__419piecewise_constructE
.section .rodata._ZN4cuda3std3__419piecewise_constructE,"aG",@progbits,_ZN4cuda3std3__419piecewise_constructE,comdat
.type _ZN4cuda3std3__419piecewise_constructE, @gnu_unique_object
.size _ZN4cuda3std3__419piecewise_constructE, 1
_ZN4cuda3std3__419piecewise_constructE:
.zero 1
.weak _ZN4cuda3std6ranges3__45__cpo9iter_moveE
.section .rodata._ZN4cuda3std6ranges3__45__cpo9iter_moveE,"aG",@progbits,_ZN4cuda3std6ranges3__45__cpo9iter_moveE,comdat
.type _ZN4cuda3std6ranges3__45__cpo9iter_moveE, @gnu_unique_object
.size _ZN4cuda3std6ranges3__45__cpo9iter_moveE, 1
_ZN4cuda3std6ranges3__45__cpo9iter_moveE:
.zero 1
.weak _ZN4cuda3std6ranges3__45__cpo4swapE
.section .rodata._ZN4cuda3std6ranges3__45__cpo4swapE,"aG",@progbits,_ZN4cuda3std6ranges3__45__cpo4swapE,comdat
.type _ZN4cuda3std6ranges3__45__cpo4swapE, @gnu_unique_object
.size _ZN4cuda3std6ranges3__45__cpo4swapE, 1
_ZN4cuda3std6ranges3__45__cpo4swapE:
.zero 1
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <cuda_runtime_api.h>
#include <cassert>
#include <cstdio>
#include <cstdlib>
#include <cmath>
#include <random>
#include <cooperative_groups.h>
/*
WRITE CUDA KERNEL FOR COUNT HERE
*/
__device__
int log_2(float x){
int count = 0;
while(x>1){
x/=2;
count++;
}
return count;
}
__global__
void parallel_implementation(int * data, int vals,int * tmp_data, int * output_data){
int blocks = gridDim.x;
int start_index = threadIdx.x + (vals*blockIdx.x)/blocks;
int end_index = (vals*(blockIdx.x+1))/blocks;
int layers = log_2(vals);
//printf("Layers = %d",layers);
//sync stuff
//grid_group g = this_grid();
//data works as previous layer holder
//output_data works as current layer holder
//Hillis-Steele Algorithm
for(int layer = 0; layer < layers; layer++){
//for each layer
//if(blockIdx.x==0 && threadIdx.x==vals) printf("layer %d",layer);
for(int i = start_index;i<end_index;i+=blockDim.x){//move in strides the size of the block
//for each element in the array
int neighbor_i = i-pow(2,layer);
if(neighbor_i>=0){
output_data[i]+=data[neighbor_i];//update output
//tmp_data[i]+=data[i-pow(2,layer)];//update holder container
//test removal tmp_data[i]=output_data[i];
}
}
__syncthreads();/*
if(blockIdx.x==0 && threadIdx.x==0){//copy new array over to data
//swap new layers data int "data" for next round
//int * tmp = data;
//data = tmp_data;
//tmp_data = tmp;
for i
}*/
//if(blockIdx.x==0 && threadIdx.x==0) for (int i = 0; i<vals;i++) printf("%d\n",output_data[i]);
//prep for next layer
for(int i = start_index;i<end_index;i+=blockDim.x){
data[i] = output_data[i];
}
__syncthreads();//sync threads across all blocks before next layer
}
//bug removal fix later
__syncthreads();
if(blockIdx.x==0 && threadIdx.x==0)for(int i = 2047; i<vals;i+=4096) output_data[i]-=data[0];
}
int * serial_implementation(int * data, int vals) {
int * output = (int *)malloc(sizeof(int) * vals);
output[0] = 0;
for (int i = 1; i < vals; i++) {
output[i] = output[i-1] + data[i-1];
}
return output;
}
int main(int argc, char ** argv) {
assert(argc == 2);
int values = atoi(argv[1]); // Values is guaranteed to be no more than 10000000
int * data = (int *)malloc(sizeof(int) * values);
// Generate "random" vector
std::mt19937 gen(13); // Keep constant to maintain determinism between runs
std::uniform_int_distribution<> dist(0, 50);
for (int i = 0; i < values; i++) {
data[i] = dist(gen);
}
cudaStream_t stream;
cudaEvent_t begin, end;
cudaStreamCreate(&stream);
cudaEventCreate(&begin);
cudaEventCreate(&end);
int * h_output = (int *)malloc(sizeof(int) * (1+values)); // THIS VARIABLE SHOULD HOLD THE TOTAL COUNT BY THE END
/*
PERFORM NECESSARY VARIABLE DECLARATIONS HERE
PERFORM NECESSARY DATA TRANSFER HERE
*/
int * gpu_data;
int * gpu_output_data;
int * gpu_tmp_data;
//Determine allocation size
int array_size = sizeof(int)*values;
//Allocate memory on GPU
cudaMalloc(&gpu_data, array_size);
cudaMalloc(&gpu_output_data, array_size);
cudaMalloc(&gpu_tmp_data, array_size);
//cudaMalloc(&gpu_data, array_size+sizeof(int));
//cudaMalloc(&gpu_output_data, array_size+sizeof(int));
//cudaMalloc(&gpu_tmp_data, array_size+sizeof(int));
//Copy data to GPU
cudaMemcpy(gpu_data,data,array_size,cudaMemcpyHostToDevice);
cudaMemcpy(gpu_output_data,data,array_size,cudaMemcpyHostToDevice);
cudaMemcpy(gpu_tmp_data,data,array_size,cudaMemcpyHostToDevice);
//cudaMemcpy(gpu_data+sizeof(int),data,array_size,cudaMemcpyHostToDevice);
//cudaMemcpy(gpu_output_data+sizeof(int),data,array_size,cudaMemcpyHostToDevice);
//cudaMemcpy(gpu_tmp_data+sizeof(int),data,array_size,cudaMemcpyHostToDevice);
cudaEventRecord(begin, stream);
/*
LAUNCH KERNEL HERE
*/
int THREADS_PER_BLOCK = 1024;//128 ideal
int BLOCKS = 1;//16 ideal
dim3 block(THREADS_PER_BLOCK);
dim3 grid(BLOCKS);
parallel_implementation<<<grid,block,0,stream>>>(gpu_data,values,gpu_tmp_data,gpu_output_data);
cudaEventRecord(end, stream);
/*
PERFORM NECESSARY DATA TRANSFER HERE
*/
cudaMemcpy(h_output+1, gpu_output_data, array_size, cudaMemcpyDeviceToHost);
h_output[0] = 0;
cudaStreamSynchronize(stream);
float ms;
cudaEventElapsedTime(&ms, begin, end);
printf("Elapsed time: %f ms\n", ms);
/*
DEALLOCATE RESOURCES HERE
*/
cudaFree(gpu_data);
cudaFree(gpu_output_data);
cudaFree(gpu_tmp_data);
int * reference_output = serial_implementation(data, values);
for (int i = 0; i < values; i++) {
if (reference_output[i] != h_output[i]) {
printf("ERROR: %d != %d at index %d. Off by %d\n", reference_output[i], h_output[i], i,reference_output[i]- h_output[i]);
/* printf("V | C | GPU\n");
for(int j = 0; j< values;j++){
printf("%d | %d | %d\n",data[j],reference_output[j],h_output[j]);
}*/
//abort();
}
}
cudaEventDestroy(begin);
cudaEventDestroy(end);
cudaStreamDestroy(stream);
free(data);
free(reference_output);
free(h_output);
return 0;
} | #include <hip/hip_runtime.h>
#include <hip/hip_runtime_api.h>
#include <cassert>
#include <cstdio>
#include <cstdlib>
#include <cmath>
#include <random>
#include <hip/hip_cooperative_groups.h>
/*
WRITE CUDA KERNEL FOR COUNT HERE
*/
__device__
int log_2(float x){
int count = 0;
while(x>1){
x/=2;
count++;
}
return count;
}
__global__
void parallel_implementation(int * data, int vals,int * tmp_data, int * output_data){
int blocks = gridDim.x;
int start_index = threadIdx.x + (vals*blockIdx.x)/blocks;
int end_index = (vals*(blockIdx.x+1))/blocks;
int layers = log_2(vals);
//printf("Layers = %d",layers);
//sync stuff
//grid_group g = this_grid();
//data works as previous layer holder
//output_data works as current layer holder
//Hillis-Steele Algorithm
for(int layer = 0; layer < layers; layer++){
//for each layer
//if(blockIdx.x==0 && threadIdx.x==vals) printf("layer %d",layer);
for(int i = start_index;i<end_index;i+=blockDim.x){//move in strides the size of the block
//for each element in the array
int neighbor_i = i-pow(2,layer);
if(neighbor_i>=0){
output_data[i]+=data[neighbor_i];//update output
//tmp_data[i]+=data[i-pow(2,layer)];//update holder container
//test removal tmp_data[i]=output_data[i];
}
}
__syncthreads();/*
if(blockIdx.x==0 && threadIdx.x==0){//copy new array over to data
//swap new layers data int "data" for next round
//int * tmp = data;
//data = tmp_data;
//tmp_data = tmp;
for i
}*/
//if(blockIdx.x==0 && threadIdx.x==0) for (int i = 0; i<vals;i++) printf("%d\n",output_data[i]);
//prep for next layer
for(int i = start_index;i<end_index;i+=blockDim.x){
data[i] = output_data[i];
}
__syncthreads();//sync threads across all blocks before next layer
}
//bug removal fix later
__syncthreads();
if(blockIdx.x==0 && threadIdx.x==0)for(int i = 2047; i<vals;i+=4096) output_data[i]-=data[0];
}
int * serial_implementation(int * data, int vals) {
int * output = (int *)malloc(sizeof(int) * vals);
output[0] = 0;
for (int i = 1; i < vals; i++) {
output[i] = output[i-1] + data[i-1];
}
return output;
}
int main(int argc, char ** argv) {
assert(argc == 2);
int values = atoi(argv[1]); // Values is guaranteed to be no more than 10000000
int * data = (int *)malloc(sizeof(int) * values);
// Generate "random" vector
std::mt19937 gen(13); // Keep constant to maintain determinism between runs
std::uniform_int_distribution<> dist(0, 50);
for (int i = 0; i < values; i++) {
data[i] = dist(gen);
}
hipStream_t stream;
hipEvent_t begin, end;
hipStreamCreate(&stream);
hipEventCreate(&begin);
hipEventCreate(&end);
int * h_output = (int *)malloc(sizeof(int) * (1+values)); // THIS VARIABLE SHOULD HOLD THE TOTAL COUNT BY THE END
/*
PERFORM NECESSARY VARIABLE DECLARATIONS HERE
PERFORM NECESSARY DATA TRANSFER HERE
*/
int * gpu_data;
int * gpu_output_data;
int * gpu_tmp_data;
//Determine allocation size
int array_size = sizeof(int)*values;
//Allocate memory on GPU
hipMalloc(&gpu_data, array_size);
hipMalloc(&gpu_output_data, array_size);
hipMalloc(&gpu_tmp_data, array_size);
//cudaMalloc(&gpu_data, array_size+sizeof(int));
//cudaMalloc(&gpu_output_data, array_size+sizeof(int));
//cudaMalloc(&gpu_tmp_data, array_size+sizeof(int));
//Copy data to GPU
hipMemcpy(gpu_data,data,array_size,hipMemcpyHostToDevice);
hipMemcpy(gpu_output_data,data,array_size,hipMemcpyHostToDevice);
hipMemcpy(gpu_tmp_data,data,array_size,hipMemcpyHostToDevice);
//cudaMemcpy(gpu_data+sizeof(int),data,array_size,cudaMemcpyHostToDevice);
//cudaMemcpy(gpu_output_data+sizeof(int),data,array_size,cudaMemcpyHostToDevice);
//cudaMemcpy(gpu_tmp_data+sizeof(int),data,array_size,cudaMemcpyHostToDevice);
hipEventRecord(begin, stream);
/*
LAUNCH KERNEL HERE
*/
int THREADS_PER_BLOCK = 1024;//128 ideal
int BLOCKS = 1;//16 ideal
dim3 block(THREADS_PER_BLOCK);
dim3 grid(BLOCKS);
parallel_implementation<<<grid,block,0,stream>>>(gpu_data,values,gpu_tmp_data,gpu_output_data);
hipEventRecord(end, stream);
/*
PERFORM NECESSARY DATA TRANSFER HERE
*/
hipMemcpy(h_output+1, gpu_output_data, array_size, hipMemcpyDeviceToHost);
h_output[0] = 0;
hipStreamSynchronize(stream);
float ms;
hipEventElapsedTime(&ms, begin, end);
printf("Elapsed time: %f ms\n", ms);
/*
DEALLOCATE RESOURCES HERE
*/
hipFree(gpu_data);
hipFree(gpu_output_data);
hipFree(gpu_tmp_data);
int * reference_output = serial_implementation(data, values);
for (int i = 0; i < values; i++) {
if (reference_output[i] != h_output[i]) {
printf("ERROR: %d != %d at index %d. Off by %d\n", reference_output[i], h_output[i], i,reference_output[i]- h_output[i]);
/* printf("V | C | GPU\n");
for(int j = 0; j< values;j++){
printf("%d | %d | %d\n",data[j],reference_output[j],h_output[j]);
}*/
//abort();
}
}
hipEventDestroy(begin);
hipEventDestroy(end);
hipStreamDestroy(stream);
free(data);
free(reference_output);
free(h_output);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <hip/hip_runtime_api.h>
#include <cassert>
#include <cstdio>
#include <cstdlib>
#include <cmath>
#include <random>
#include <hip/hip_cooperative_groups.h>
/*
WRITE CUDA KERNEL FOR COUNT HERE
*/
__device__
int log_2(float x){
int count = 0;
while(x>1){
x/=2;
count++;
}
return count;
}
__global__
void parallel_implementation(int * data, int vals,int * tmp_data, int * output_data){
int blocks = gridDim.x;
int start_index = threadIdx.x + (vals*blockIdx.x)/blocks;
int end_index = (vals*(blockIdx.x+1))/blocks;
int layers = log_2(vals);
//printf("Layers = %d",layers);
//sync stuff
//grid_group g = this_grid();
//data works as previous layer holder
//output_data works as current layer holder
//Hillis-Steele Algorithm
for(int layer = 0; layer < layers; layer++){
//for each layer
//if(blockIdx.x==0 && threadIdx.x==vals) printf("layer %d",layer);
for(int i = start_index;i<end_index;i+=blockDim.x){//move in strides the size of the block
//for each element in the array
int neighbor_i = i-pow(2,layer);
if(neighbor_i>=0){
output_data[i]+=data[neighbor_i];//update output
//tmp_data[i]+=data[i-pow(2,layer)];//update holder container
//test removal tmp_data[i]=output_data[i];
}
}
__syncthreads();/*
if(blockIdx.x==0 && threadIdx.x==0){//copy new array over to data
//swap new layers data int "data" for next round
//int * tmp = data;
//data = tmp_data;
//tmp_data = tmp;
for i
}*/
//if(blockIdx.x==0 && threadIdx.x==0) for (int i = 0; i<vals;i++) printf("%d\n",output_data[i]);
//prep for next layer
for(int i = start_index;i<end_index;i+=blockDim.x){
data[i] = output_data[i];
}
__syncthreads();//sync threads across all blocks before next layer
}
//bug removal fix later
__syncthreads();
if(blockIdx.x==0 && threadIdx.x==0)for(int i = 2047; i<vals;i+=4096) output_data[i]-=data[0];
}
int * serial_implementation(int * data, int vals) {
int * output = (int *)malloc(sizeof(int) * vals);
output[0] = 0;
for (int i = 1; i < vals; i++) {
output[i] = output[i-1] + data[i-1];
}
return output;
}
int main(int argc, char ** argv) {
assert(argc == 2);
int values = atoi(argv[1]); // Values is guaranteed to be no more than 10000000
int * data = (int *)malloc(sizeof(int) * values);
// Generate "random" vector
std::mt19937 gen(13); // Keep constant to maintain determinism between runs
std::uniform_int_distribution<> dist(0, 50);
for (int i = 0; i < values; i++) {
data[i] = dist(gen);
}
hipStream_t stream;
hipEvent_t begin, end;
hipStreamCreate(&stream);
hipEventCreate(&begin);
hipEventCreate(&end);
int * h_output = (int *)malloc(sizeof(int) * (1+values)); // THIS VARIABLE SHOULD HOLD THE TOTAL COUNT BY THE END
/*
PERFORM NECESSARY VARIABLE DECLARATIONS HERE
PERFORM NECESSARY DATA TRANSFER HERE
*/
int * gpu_data;
int * gpu_output_data;
int * gpu_tmp_data;
//Determine allocation size
int array_size = sizeof(int)*values;
//Allocate memory on GPU
hipMalloc(&gpu_data, array_size);
hipMalloc(&gpu_output_data, array_size);
hipMalloc(&gpu_tmp_data, array_size);
//cudaMalloc(&gpu_data, array_size+sizeof(int));
//cudaMalloc(&gpu_output_data, array_size+sizeof(int));
//cudaMalloc(&gpu_tmp_data, array_size+sizeof(int));
//Copy data to GPU
hipMemcpy(gpu_data,data,array_size,hipMemcpyHostToDevice);
hipMemcpy(gpu_output_data,data,array_size,hipMemcpyHostToDevice);
hipMemcpy(gpu_tmp_data,data,array_size,hipMemcpyHostToDevice);
//cudaMemcpy(gpu_data+sizeof(int),data,array_size,cudaMemcpyHostToDevice);
//cudaMemcpy(gpu_output_data+sizeof(int),data,array_size,cudaMemcpyHostToDevice);
//cudaMemcpy(gpu_tmp_data+sizeof(int),data,array_size,cudaMemcpyHostToDevice);
hipEventRecord(begin, stream);
/*
LAUNCH KERNEL HERE
*/
int THREADS_PER_BLOCK = 1024;//128 ideal
int BLOCKS = 1;//16 ideal
dim3 block(THREADS_PER_BLOCK);
dim3 grid(BLOCKS);
parallel_implementation<<<grid,block,0,stream>>>(gpu_data,values,gpu_tmp_data,gpu_output_data);
hipEventRecord(end, stream);
/*
PERFORM NECESSARY DATA TRANSFER HERE
*/
hipMemcpy(h_output+1, gpu_output_data, array_size, hipMemcpyDeviceToHost);
h_output[0] = 0;
hipStreamSynchronize(stream);
float ms;
hipEventElapsedTime(&ms, begin, end);
printf("Elapsed time: %f ms\n", ms);
/*
DEALLOCATE RESOURCES HERE
*/
hipFree(gpu_data);
hipFree(gpu_output_data);
hipFree(gpu_tmp_data);
int * reference_output = serial_implementation(data, values);
for (int i = 0; i < values; i++) {
if (reference_output[i] != h_output[i]) {
printf("ERROR: %d != %d at index %d. Off by %d\n", reference_output[i], h_output[i], i,reference_output[i]- h_output[i]);
/* printf("V | C | GPU\n");
for(int j = 0; j< values;j++){
printf("%d | %d | %d\n",data[j],reference_output[j],h_output[j]);
}*/
//abort();
}
}
hipEventDestroy(begin);
hipEventDestroy(end);
hipStreamDestroy(stream);
free(data);
free(reference_output);
free(h_output);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z23parallel_implementationPiiS_S_
.globl _Z23parallel_implementationPiiS_S_
.p2align 8
.type _Z23parallel_implementationPiiS_S_,@function
_Z23parallel_implementationPiiS_S_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x20
s_load_b32 s14, s[0:1], 0x8
s_add_u32 s6, s0, 32
s_addc_u32 s7, s1, 0
s_add_i32 s5, s15, 1
s_mov_b32 s33, 0
s_waitcnt lgkmcnt(0)
v_cvt_f32_u32_e32 v1, s2
s_sub_i32 s3, 0, s2
s_mul_i32 s12, s15, s14
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v1, v1
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v1, 0x4f7ffffe, v1
v_cvt_u32_f32_e32 v1, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s4, v1
s_mul_i32 s3, s3, s4
s_delay_alu instid0(SALU_CYCLE_1)
s_mul_hi_u32 s8, s4, s3
s_mul_i32 s3, s5, s14
s_add_i32 s4, s4, s8
s_cmp_lt_i32 s14, 2
s_mul_hi_u32 s11, s12, s4
s_mul_hi_u32 s10, s3, s4
s_cbranch_scc1 .LBB0_3
v_cvt_f32_i32_e32 v1, s14
.LBB0_2:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mul_f32_e32 v1, 0.5, v1
s_add_i32 s33, s33, 1
v_cmp_lt_f32_e32 vcc_lo, 1.0, v1
s_cbranch_vccnz .LBB0_2
.LBB0_3:
s_clause 0x1
s_load_b64 s[4:5], s[0:1], 0x0
s_load_b64 s[8:9], s[0:1], 0x18
s_cmp_lt_i32 s33, 1
s_cbranch_scc1 .LBB0_14
s_mul_i32 s0, s11, s2
s_add_i32 s1, s11, 1
s_sub_i32 s0, s12, s0
s_mul_i32 s13, s10, s2
s_sub_i32 s12, s0, s2
s_cmp_ge_u32 s0, s2
v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v4, 0
s_cselect_b32 s1, s1, s11
s_cselect_b32 s0, s12, s0
s_add_i32 s11, s1, 1
s_cmp_ge_u32 s0, s2
s_mov_b32 s68, 0
s_cselect_b32 s0, s11, s1
s_sub_i32 s1, s3, s13
s_add_i32 s3, s10, 1
s_sub_i32 s11, s1, s2
s_cmp_ge_u32 s1, s2
v_dual_mov_b32 v2, 0 :: v_dual_add_nc_u32 v9, s0, v0
s_cselect_b32 s0, s3, s10
s_cselect_b32 s1, s11, s1
s_add_i32 s3, s0, 1
s_cmp_ge_u32 s1, s2
s_mov_b32 s11, 0x3fe55555
s_cselect_b32 s69, s3, s0
s_mov_b32 s10, 0x55555555
v_cmp_gt_i32_e32 vcc_lo, s69, v9
s_mov_b32 s13, 0x3fba6564
s_mov_b32 s12, 0x968915a9
s_mov_b32 s17, 0x3fbdee67
s_mov_b32 s16, 0x4222de17
s_mov_b32 s19, 0x3fbe25e4
s_mov_b32 s18, 0x3abe935a
s_mov_b32 s21, 0x3fc110ef
s_mov_b32 s20, 0x47e6c9c2
s_mov_b32 s23, 0x3fc3b13b
s_mov_b32 s22, 0xcfa74449
s_mov_b32 s25, 0x3fc745d1
s_mov_b32 s24, 0x71bf3c30
s_mov_b32 s27, 0x3fcc71c7
s_mov_b32 s26, 0x1c7792ce
s_mov_b32 s29, 0x3fd24924
s_mov_b32 s28, 0x924920da
s_mov_b32 s31, 0x3fd99999
s_mov_b32 s30, 0x9999999c
s_mov_b32 s35, 0x3fe62e42
s_mov_b32 s34, 0xfefa39ef
s_mov_b32 s37, 0x3c7abc9e
s_mov_b32 s36, 0x3b39803f
s_mov_b32 s3, 0xbfe55555
s_mov_b32 s39, 0x3c8543b0
s_mov_b32 s38, 0xd5df274d
s_mov_b32 s41, 0x3ff71547
s_mov_b32 s40, 0x652b82fe
s_mov_b32 s43, 0xbfe62e42
s_mov_b32 s45, 0xbc7abc9e
s_mov_b32 s47, 0x3e928af3
s_mov_b32 s46, 0xfca7ab0c
s_mov_b32 s49, 0x3e5ade15
s_mov_b32 s48, 0x6a5dcb37
s_mov_b32 s51, 0x3ec71dee
s_mov_b32 s50, 0x623fde64
s_mov_b32 s53, 0x3efa0199
s_mov_b32 s52, 0x7c89e6b0
s_mov_b32 s55, 0x3f2a01a0
s_mov_b32 s54, 0x14761f6e
s_mov_b32 s57, 0x3f56c16c
s_mov_b32 s56, 0x1852b7b0
s_mov_b32 s59, 0x3f811111
s_mov_b32 s58, 0x11122322
s_mov_b32 s61, 0x3fa55555
s_mov_b32 s60, 0x555502a1
s_mov_b32 s63, 0x3fc55555
s_mov_b32 s62, 0x55555511
s_mov_b32 s65, 0x3fe00000
s_mov_b32 s64, 11
s_branch .LBB0_6
.LBB0_5:
s_or_b32 exec_lo, exec_lo, s2
v_add_f64 v[1:2], v[1:2], 1.0
s_add_i32 s68, s68, 1
s_waitcnt_vscnt null, 0x0
s_cmp_eq_u32 s68, s33
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_14
.LBB0_6:
s_and_saveexec_b32 s70, vcc_lo
s_cbranch_execz .LBB0_11
s_cmp_eq_u32 s68, 0
s_mov_b32 s66, 0
s_cselect_b32 s67, 0x3ff00000, 2.0
s_mov_b32 s2, s10
v_frexp_mant_f64_e32 v[5:6], s[66:67]
s_mov_b32 s42, s34
s_mov_b32 s44, s36
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_f64_e64 s0, s[10:11], v[5:6]
v_cndmask_b32_e64 v3, 0, 1, s0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_ldexp_f64 v[5:6], v[5:6], v3
v_frexp_exp_i32_f64_e32 v3, s[66:67]
v_add_f64 v[7:8], v[5:6], 1.0
v_add_f64 v[14:15], v[5:6], -1.0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_subrev_co_ci_u32_e64 v3, s0, 0, v3, s0
v_rcp_f64_e32 v[10:11], v[7:8]
v_add_f64 v[16:17], v[7:8], -1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_add_f64 v[5:6], v[5:6], -v[16:17]
s_waitcnt_depctr 0xfff
v_fma_f64 v[12:13], -v[7:8], v[10:11], 1.0
v_fma_f64 v[10:11], v[12:13], v[10:11], v[10:11]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[12:13], -v[7:8], v[10:11], 1.0
v_fma_f64 v[10:11], v[12:13], v[10:11], v[10:11]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[12:13], v[14:15], v[10:11]
v_mul_f64 v[18:19], v[7:8], v[12:13]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[7:8], v[12:13], v[7:8], -v[18:19]
v_fma_f64 v[5:6], v[12:13], v[5:6], v[7:8]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[7:8], v[18:19], v[5:6]
v_add_f64 v[16:17], v[14:15], -v[7:8]
v_add_f64 v[18:19], v[7:8], -v[18:19]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[14:15], v[14:15], -v[16:17]
v_add_f64 v[5:6], v[18:19], -v[5:6]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[7:8], v[14:15], -v[7:8]
v_add_f64 v[5:6], v[5:6], v[7:8]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[5:6], v[16:17], v[5:6]
v_mul_f64 v[5:6], v[10:11], v[5:6]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[7:8], v[12:13], v[5:6]
v_add_f64 v[10:11], v[7:8], -v[12:13]
v_mul_f64 v[12:13], v[7:8], v[7:8]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[5:6], v[5:6], -v[10:11]
v_fma_f64 v[10:11], v[7:8], v[7:8], -v[12:13]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[14:15], v[5:6], v[5:6]
v_fma_f64 v[10:11], v[7:8], v[14:15], v[10:11]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[14:15], v[12:13], v[10:11]
v_fma_f64 v[16:17], v[14:15], s[16:17], s[12:13]
v_add_f64 v[12:13], v[14:15], -v[12:13]
v_mul_f64 v[22:23], v[7:8], v[14:15]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fma_f64 v[16:17], v[14:15], v[16:17], s[18:19]
v_add_f64 v[10:11], v[10:11], -v[12:13]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[16:17], v[14:15], v[16:17], s[20:21]
v_fma_f64 v[16:17], v[14:15], v[16:17], s[22:23]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[16:17], v[14:15], v[16:17], s[24:25]
v_fma_f64 v[16:17], v[14:15], v[16:17], s[26:27]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[16:17], v[14:15], v[16:17], s[28:29]
v_fma_f64 v[16:17], v[14:15], v[16:17], s[30:31]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[18:19], v[14:15], v[16:17]
v_fma_f64 v[12:13], v[14:15], v[16:17], -v[18:19]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[12:13], v[10:11], v[16:17], v[12:13]
v_add_f64 v[16:17], v[18:19], v[12:13]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_f64 v[20:21], v[16:17], s[10:11]
v_add_f64 v[18:19], v[16:17], -v[18:19]
v_add_f64 v[24:25], v[20:21], s[2:3]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_f64 v[12:13], v[12:13], -v[18:19]
v_fma_f64 v[18:19], v[14:15], v[7:8], -v[22:23]
v_add_f64 v[16:17], v[16:17], -v[24:25]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f64 v[12:13], v[12:13], s[38:39]
v_fma_f64 v[14:15], v[14:15], v[5:6], v[18:19]
v_ldexp_f64 v[5:6], v[5:6], 1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f64 v[12:13], v[12:13], v[16:17]
v_fma_f64 v[10:11], v[10:11], v[7:8], v[14:15]
v_ldexp_f64 v[7:8], v[7:8], 1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f64 v[14:15], v[20:21], v[12:13]
v_add_f64 v[16:17], v[22:23], v[10:11]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[18:19], v[20:21], -v[14:15]
v_mul_f64 v[20:21], v[16:17], v[14:15]
v_add_f64 v[22:23], v[16:17], -v[22:23]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f64 v[12:13], v[12:13], v[18:19]
v_fma_f64 v[18:19], v[16:17], v[14:15], -v[20:21]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[10:11], v[10:11], -v[22:23]
v_fma_f64 v[12:13], v[16:17], v[12:13], v[18:19]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_fma_f64 v[10:11], v[10:11], v[14:15], v[12:13]
v_cvt_f64_i32_e32 v[14:15], v3
v_add_f64 v[12:13], v[20:21], v[10:11]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_add_f64 v[16:17], v[7:8], v[12:13]
v_add_f64 v[18:19], v[12:13], -v[20:21]
v_mul_f64 v[20:21], v[14:15], s[34:35]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f64 v[7:8], v[16:17], -v[7:8]
v_add_f64 v[10:11], v[10:11], -v[18:19]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fma_f64 v[18:19], v[14:15], s[34:35], -v[20:21]
v_add_f64 v[7:8], v[12:13], -v[7:8]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f64 v[5:6], v[5:6], v[10:11]
v_fma_f64 v[10:11], v[14:15], s[36:37], v[18:19]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[5:6], v[5:6], v[7:8]
v_add_f64 v[7:8], v[20:21], v[10:11]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[12:13], v[16:17], v[5:6]
v_add_f64 v[20:21], v[7:8], -v[20:21]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_f64 v[14:15], v[7:8], v[12:13]
v_add_f64 v[16:17], v[12:13], -v[16:17]
v_add_f64 v[10:11], v[10:11], -v[20:21]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f64 v[18:19], v[14:15], -v[7:8]
v_add_f64 v[5:6], v[5:6], -v[16:17]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_f64 v[22:23], v[14:15], -v[18:19]
v_add_f64 v[12:13], v[12:13], -v[18:19]
v_add_f64 v[16:17], v[10:11], v[5:6]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[7:8], v[7:8], -v[22:23]
v_add_f64 v[7:8], v[12:13], v[7:8]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[12:13], v[16:17], -v[10:11]
v_add_f64 v[7:8], v[16:17], v[7:8]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_f64 v[16:17], v[16:17], -v[12:13]
v_add_f64 v[5:6], v[5:6], -v[12:13]
v_add_f64 v[18:19], v[14:15], v[7:8]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[10:11], v[10:11], -v[16:17]
v_add_f64 v[12:13], v[18:19], -v[14:15]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[5:6], v[5:6], v[10:11]
v_add_f64 v[7:8], v[7:8], -v[12:13]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[5:6], v[5:6], v[7:8]
v_add_f64 v[7:8], v[18:19], v[5:6]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_f64 v[10:11], v[7:8], -v[18:19]
v_mul_f64 v[12:13], v[7:8], v[1:2]
v_add_f64 v[5:6], v[5:6], -v[10:11]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_fma_f64 v[7:8], v[1:2], v[7:8], -v[12:13]
v_cmp_class_f64_e64 s0, v[12:13], 0x204
v_fma_f64 v[5:6], v[1:2], v[5:6], v[7:8]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[7:8], v[12:13], v[5:6]
v_cndmask_b32_e64 v11, v8, v13, s0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cndmask_b32_e64 v10, v7, v12, s0
v_add_f64 v[7:8], v[7:8], -v[12:13]
v_mul_f64 v[14:15], v[10:11], s[40:41]
v_cmp_nlt_f64_e64 s1, 0x40900000, v[10:11]
v_cmp_neq_f64_e64 s0, 0x7ff00000, |v[10:11]|
v_cmp_ngt_f64_e64 s2, 0xc090cc00, v[10:11]
v_add_f64 v[5:6], v[5:6], -v[7:8]
v_rndne_f64_e32 v[14:15], v[14:15]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cndmask_b32_e64 v6, 0, v6, s0
v_cndmask_b32_e64 v5, 0, v5, s0
s_and_b32 s0, s2, s1
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_fma_f64 v[16:17], v[14:15], s[42:43], v[10:11]
v_cvt_i32_f64_e32 v3, v[14:15]
v_fma_f64 v[16:17], v[14:15], s[44:45], v[16:17]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[18:19], v[16:17], s[48:49], s[46:47]
v_fma_f64 v[18:19], v[16:17], v[18:19], s[50:51]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[18:19], v[16:17], v[18:19], s[52:53]
v_fma_f64 v[18:19], v[16:17], v[18:19], s[54:55]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[18:19], v[16:17], v[18:19], s[56:57]
v_fma_f64 v[18:19], v[16:17], v[18:19], s[58:59]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[18:19], v[16:17], v[18:19], s[60:61]
v_fma_f64 v[18:19], v[16:17], v[18:19], s[62:63]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[18:19], v[16:17], v[18:19], s[64:65]
v_fma_f64 v[18:19], v[16:17], v[18:19], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[14:15], v[16:17], v[18:19], 1.0
v_ldexp_f64 v[12:13], v[14:15], v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cndmask_b32_e64 v3, 0x7ff00000, v13, s1
v_cndmask_b32_e64 v7, 0, v12, s0
s_load_b32 s1, s[6:7], 0xc
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e64 v8, 0, v3, s2
v_fma_f64 v[5:6], v[7:8], v[5:6], v[7:8]
v_cmp_class_f64_e64 s0, v[7:8], 0x204
s_waitcnt lgkmcnt(0)
s_and_b32 s1, s1, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cndmask_b32_e64 v6, v6, v8, s0
v_cndmask_b32_e64 v5, v5, v7, s0
v_mov_b32_e32 v7, v9
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_9
.p2align 6
.LBB0_8:
s_or_b32 exec_lo, exec_lo, s2
v_add_nc_u32_e32 v7, s1, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_le_i32_e64 s0, s69, v7
s_or_b32 s66, s0, s66
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s66
s_cbranch_execz .LBB0_11
.LBB0_9:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cvt_f64_i32_e32 v[10:11], v7
s_mov_b32 s2, exec_lo
v_add_f64 v[10:11], v[10:11], -|v[5:6]|
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_i32_f64_e32 v3, v[10:11]
v_cmpx_lt_i32_e32 -1, v3
s_cbranch_execz .LBB0_8
v_ashrrev_i32_e32 v8, 31, v7
v_lshlrev_b64 v[10:11], 2, v[3:4]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[12:13], 2, v[7:8]
v_add_co_u32 v10, s0, s4, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e64 v11, s0, s5, v11, s0
v_add_co_u32 v12, s0, s8, v12
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v13, s0, s9, v13, s0
global_load_b32 v3, v[10:11], off
global_load_b32 v8, v[12:13], off
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v3, v8, v3
global_store_b32 v[12:13], v3, off
s_branch .LBB0_8
.LBB0_11:
s_set_inst_prefetch_distance 0x2
s_or_b32 exec_lo, exec_lo, s70
s_waitcnt lgkmcnt(0)
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_5
s_load_b32 s0, s[6:7], 0xc
v_mov_b32_e32 v5, v9
s_mov_b32 s44, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s42, s0, 0xffff
.p2align 6
.LBB0_13:
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v6, 31, v5
v_lshlrev_b64 v[6:7], 2, v[5:6]
v_add_nc_u32_e32 v5, s42, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v10, s0, s8, v6
v_add_co_ci_u32_e64 v11, s0, s9, v7, s0
s_delay_alu instid0(VALU_DEP_3)
v_cmp_le_i32_e64 s0, s69, v5
v_add_co_u32 v6, s1, s4, v6
global_load_b32 v3, v[10:11], off
v_add_co_ci_u32_e64 v7, s1, s5, v7, s1
s_or_b32 s44, s0, s44
s_waitcnt vmcnt(0)
global_store_b32 v[6:7], v3, off
s_and_not1_b32 exec_lo, exec_lo, s44
s_cbranch_execnz .LBB0_13
s_branch .LBB0_5
.LBB0_14:
v_or_b32_e32 v0, s15, v0
s_cmpk_gt_i32 s14, 0x7ff
s_movk_i32 s2, 0x7ff
s_cselect_b32 s0, -1, 0
s_waitcnt lgkmcnt(0)
v_cmp_eq_u32_e32 vcc_lo, 0, v0
s_barrier
buffer_gl0_inv
s_and_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_17
v_mov_b32_e32 v0, 0
s_add_u32 s0, s8, 0x1ffc
s_addc_u32 s1, s9, 0
.LBB0_16:
s_clause 0x1
global_load_b32 v1, v0, s[4:5]
global_load_b32 v2, v0, s[0:1]
s_addk_i32 s2, 0x1000
s_waitcnt vmcnt(0)
v_sub_nc_u32_e32 v1, v2, v1
global_store_b32 v0, v1, s[0:1]
s_add_u32 s0, s0, 0x4000
s_addc_u32 s1, s1, 0
s_cmp_lt_i32 s2, s14
s_cbranch_scc1 .LBB0_16
.LBB0_17:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z23parallel_implementationPiiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 26
.amdhsa_next_free_sgpr 71
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z23parallel_implementationPiiS_S_, .Lfunc_end0-_Z23parallel_implementationPiiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z23parallel_implementationPiiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 73
.sgpr_spill_count: 0
.symbol: _Z23parallel_implementationPiiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 26
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <hip/hip_runtime_api.h>
#include <cassert>
#include <cstdio>
#include <cstdlib>
#include <cmath>
#include <random>
#include <hip/hip_cooperative_groups.h>
/*
WRITE CUDA KERNEL FOR COUNT HERE
*/
__device__
int log_2(float x){
int count = 0;
while(x>1){
x/=2;
count++;
}
return count;
}
__global__
void parallel_implementation(int * data, int vals,int * tmp_data, int * output_data){
int blocks = gridDim.x;
int start_index = threadIdx.x + (vals*blockIdx.x)/blocks;
int end_index = (vals*(blockIdx.x+1))/blocks;
int layers = log_2(vals);
//printf("Layers = %d",layers);
//sync stuff
//grid_group g = this_grid();
//data works as previous layer holder
//output_data works as current layer holder
//Hillis-Steele Algorithm
for(int layer = 0; layer < layers; layer++){
//for each layer
//if(blockIdx.x==0 && threadIdx.x==vals) printf("layer %d",layer);
for(int i = start_index;i<end_index;i+=blockDim.x){//move in strides the size of the block
//for each element in the array
int neighbor_i = i-pow(2,layer);
if(neighbor_i>=0){
output_data[i]+=data[neighbor_i];//update output
//tmp_data[i]+=data[i-pow(2,layer)];//update holder container
//test removal tmp_data[i]=output_data[i];
}
}
__syncthreads();/*
if(blockIdx.x==0 && threadIdx.x==0){//copy new array over to data
//swap new layers data int "data" for next round
//int * tmp = data;
//data = tmp_data;
//tmp_data = tmp;
for i
}*/
//if(blockIdx.x==0 && threadIdx.x==0) for (int i = 0; i<vals;i++) printf("%d\n",output_data[i]);
//prep for next layer
for(int i = start_index;i<end_index;i+=blockDim.x){
data[i] = output_data[i];
}
__syncthreads();//sync threads across all blocks before next layer
}
//bug removal fix later
__syncthreads();
if(blockIdx.x==0 && threadIdx.x==0)for(int i = 2047; i<vals;i+=4096) output_data[i]-=data[0];
}
int * serial_implementation(int * data, int vals) {
int * output = (int *)malloc(sizeof(int) * vals);
output[0] = 0;
for (int i = 1; i < vals; i++) {
output[i] = output[i-1] + data[i-1];
}
return output;
}
int main(int argc, char ** argv) {
assert(argc == 2);
int values = atoi(argv[1]); // Values is guaranteed to be no more than 10000000
int * data = (int *)malloc(sizeof(int) * values);
// Generate "random" vector
std::mt19937 gen(13); // Keep constant to maintain determinism between runs
std::uniform_int_distribution<> dist(0, 50);
for (int i = 0; i < values; i++) {
data[i] = dist(gen);
}
hipStream_t stream;
hipEvent_t begin, end;
hipStreamCreate(&stream);
hipEventCreate(&begin);
hipEventCreate(&end);
int * h_output = (int *)malloc(sizeof(int) * (1+values)); // THIS VARIABLE SHOULD HOLD THE TOTAL COUNT BY THE END
/*
PERFORM NECESSARY VARIABLE DECLARATIONS HERE
PERFORM NECESSARY DATA TRANSFER HERE
*/
int * gpu_data;
int * gpu_output_data;
int * gpu_tmp_data;
//Determine allocation size
int array_size = sizeof(int)*values;
//Allocate memory on GPU
hipMalloc(&gpu_data, array_size);
hipMalloc(&gpu_output_data, array_size);
hipMalloc(&gpu_tmp_data, array_size);
//cudaMalloc(&gpu_data, array_size+sizeof(int));
//cudaMalloc(&gpu_output_data, array_size+sizeof(int));
//cudaMalloc(&gpu_tmp_data, array_size+sizeof(int));
//Copy data to GPU
hipMemcpy(gpu_data,data,array_size,hipMemcpyHostToDevice);
hipMemcpy(gpu_output_data,data,array_size,hipMemcpyHostToDevice);
hipMemcpy(gpu_tmp_data,data,array_size,hipMemcpyHostToDevice);
//cudaMemcpy(gpu_data+sizeof(int),data,array_size,cudaMemcpyHostToDevice);
//cudaMemcpy(gpu_output_data+sizeof(int),data,array_size,cudaMemcpyHostToDevice);
//cudaMemcpy(gpu_tmp_data+sizeof(int),data,array_size,cudaMemcpyHostToDevice);
hipEventRecord(begin, stream);
/*
LAUNCH KERNEL HERE
*/
int THREADS_PER_BLOCK = 1024;//128 ideal
int BLOCKS = 1;//16 ideal
dim3 block(THREADS_PER_BLOCK);
dim3 grid(BLOCKS);
parallel_implementation<<<grid,block,0,stream>>>(gpu_data,values,gpu_tmp_data,gpu_output_data);
hipEventRecord(end, stream);
/*
PERFORM NECESSARY DATA TRANSFER HERE
*/
hipMemcpy(h_output+1, gpu_output_data, array_size, hipMemcpyDeviceToHost);
h_output[0] = 0;
hipStreamSynchronize(stream);
float ms;
hipEventElapsedTime(&ms, begin, end);
printf("Elapsed time: %f ms\n", ms);
/*
DEALLOCATE RESOURCES HERE
*/
hipFree(gpu_data);
hipFree(gpu_output_data);
hipFree(gpu_tmp_data);
int * reference_output = serial_implementation(data, values);
for (int i = 0; i < values; i++) {
if (reference_output[i] != h_output[i]) {
printf("ERROR: %d != %d at index %d. Off by %d\n", reference_output[i], h_output[i], i,reference_output[i]- h_output[i]);
/* printf("V | C | GPU\n");
for(int j = 0; j< values;j++){
printf("%d | %d | %d\n",data[j],reference_output[j],h_output[j]);
}*/
//abort();
}
}
hipEventDestroy(begin);
hipEventDestroy(end);
hipStreamDestroy(stream);
free(data);
free(reference_output);
free(h_output);
return 0;
} | .text
.file "scan.hip"
.globl _Z38__device_stub__parallel_implementationPiiS_S_ # -- Begin function _Z38__device_stub__parallel_implementationPiiS_S_
.p2align 4, 0x90
.type _Z38__device_stub__parallel_implementationPiiS_S_,@function
_Z38__device_stub__parallel_implementationPiiS_S_: # @_Z38__device_stub__parallel_implementationPiiS_S_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movl %esi, 4(%rsp)
movq %rdx, 64(%rsp)
movq %rcx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 56(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z23parallel_implementationPiiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z38__device_stub__parallel_implementationPiiS_S_, .Lfunc_end0-_Z38__device_stub__parallel_implementationPiiS_S_
.cfi_endproc
# -- End function
.globl _Z21serial_implementationPii # -- Begin function _Z21serial_implementationPii
.p2align 4, 0x90
.type _Z21serial_implementationPii,@function
_Z21serial_implementationPii: # @_Z21serial_implementationPii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %rbp, -16
movl %esi, %ebp
movq %rdi, %rbx
movslq %esi, %r14
leaq (,%r14,4), %rdi
callq malloc
movl $0, (%rax)
cmpl $2, %r14d
jl .LBB1_3
# %bb.1: # %.lr.ph.preheader
movl %ebp, %ecx
movl (%rax), %edx
decq %rcx
xorl %esi, %esi
.p2align 4, 0x90
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
addl (%rbx,%rsi,4), %edx
movl %edx, 4(%rax,%rsi,4)
incq %rsi
cmpq %rsi, %rcx
jne .LBB1_2
.LBB1_3: # %._crit_edge
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z21serial_implementationPii, .Lfunc_end1-_Z21serial_implementationPii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $5176, %rsp # imm = 0x1438
.cfi_def_cfa_offset 5232
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq 8(%rsi), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r14
movslq %r14d, %rdi
shlq $2, %rdi
movq %rdi, 56(%rsp) # 8-byte Spill
callq malloc
movq %rax, %rbx
movq $13, 176(%rsp)
movl $1, %eax
movl $13, %ecx
.p2align 4, 0x90
.LBB2_1: # =>This Inner Loop Header: Depth=1
movq %rcx, %rdx
shrq $30, %rdx
xorl %ecx, %edx
imull $1812433253, %edx, %ecx # imm = 0x6C078965
addl %eax, %ecx
movq %rcx, 176(%rsp,%rax,8)
incq %rax
cmpq $624, %rax # imm = 0x270
jne .LBB2_1
# %bb.2: # %_ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEC2Em.exit
movq $624, 5168(%rsp) # imm = 0x270
movabsq $214748364800, %rax # imm = 0x3200000000
movq %rax, 136(%rsp)
testl %r14d, %r14d
jle .LBB2_5
# %bb.3: # %.lr.ph.preheader
movl %r14d, %ebp
xorl %r12d, %r12d
leaq 176(%rsp), %r15
leaq 136(%rsp), %r13
.p2align 4, 0x90
.LBB2_4: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movq %r13, %rdi
movq %r15, %rsi
movq %r13, %rdx
callq _ZNSt24uniform_int_distributionIiEclISt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEEEiRT_RKNS0_10param_typeE
movl %eax, (%rbx,%r12,4)
incq %r12
cmpq %r12, %rbp
jne .LBB2_4
.LBB2_5: # %._crit_edge
movq %rsp, %rdi
callq hipStreamCreate
leaq 40(%rsp), %rdi
callq hipEventCreate
leaq 32(%rsp), %rdi
callq hipEventCreate
movq %r14, %rdi
shlq $32, %rdi
movabsq $4294967296, %rbp # imm = 0x100000000
addq %rbp, %rdi
sarq $30, %rdi
callq malloc
movq %rax, %r15
movq %r14, %r13
shlq $34, %r13
sarq $32, %r13
leaq 24(%rsp), %rdi
movq %r13, %rsi
callq hipMalloc
leaq 8(%rsp), %rdi
movq %r13, %rsi
callq hipMalloc
leaq 16(%rsp), %rdi
movq %r13, %rsi
callq hipMalloc
movq 24(%rsp), %rdi
movq %rbx, %rsi
movq %r13, %rdx
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
movq %rbx, %rsi
movq %r13, %rdx
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
movq %rbx, %rsi
movq %r13, %rdx
movl $1, %ecx
callq hipMemcpy
movq 40(%rsp), %rdi
movq (%rsp), %rsi
callq hipEventRecord
movq (%rsp), %r9
leaq 1(%rbp), %rdi
orq $1024, %rbp # imm = 0x400
movl $1, %esi
movq %rbp, %rdx
movl $1, %ecx
xorl %r8d, %r8d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_7
# %bb.6:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 128(%rsp)
movl %r14d, 52(%rsp)
movq %rcx, 120(%rsp)
movq %rdx, 112(%rsp)
leaq 128(%rsp), %rax
movq %rax, 144(%rsp)
leaq 52(%rsp), %rax
movq %rax, 152(%rsp)
leaq 120(%rsp), %rax
movq %rax, 160(%rsp)
leaq 112(%rsp), %rax
movq %rax, 168(%rsp)
leaq 96(%rsp), %rdi
leaq 80(%rsp), %rsi
leaq 72(%rsp), %rdx
leaq 64(%rsp), %rcx
callq __hipPopCallConfiguration
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
movq 80(%rsp), %rcx
movl 88(%rsp), %r8d
leaq 144(%rsp), %r9
movl $_Z23parallel_implementationPiiS_S_, %edi
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
pushq 80(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_7:
movq 32(%rsp), %rdi
movq (%rsp), %rsi
callq hipEventRecord
movq %r15, %rdi
addq $4, %rdi
movq 8(%rsp), %rsi
movq %r13, %rdx
movl $2, %ecx
callq hipMemcpy
movl $0, (%r15)
movq (%rsp), %rdi
callq hipStreamSynchronize
movq 40(%rsp), %rsi
movq 32(%rsp), %rdx
leaq 144(%rsp), %rdi
callq hipEventElapsedTime
movss 144(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
movq 24(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 56(%rsp), %rdi # 8-byte Reload
callq malloc
movq %rax, %r12
movl $0, (%rax)
cmpl $2, %r14d
jl .LBB2_10
# %bb.8: # %.lr.ph.preheader.i
movl %r14d, %eax
movl (%r12), %ecx
decq %rax
xorl %edx, %edx
.p2align 4, 0x90
.LBB2_9: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
addl (%rbx,%rdx,4), %ecx
movl %ecx, 4(%r12,%rdx,4)
incq %rdx
cmpq %rdx, %rax
jne .LBB2_9
.LBB2_10: # %_Z21serial_implementationPii.exit
testl %r14d, %r14d
jle .LBB2_15
# %bb.11: # %.lr.ph61.preheader
movl %r14d, %r13d
xorl %r14d, %r14d
jmp .LBB2_12
.p2align 4, 0x90
.LBB2_14: # in Loop: Header=BB2_12 Depth=1
incq %r14
cmpq %r14, %r13
je .LBB2_15
.LBB2_12: # %.lr.ph61
# =>This Inner Loop Header: Depth=1
movl (%r12,%r14,4), %esi
movl (%r15,%r14,4), %edx
movl %esi, %r8d
subl %edx, %r8d
je .LBB2_14
# %bb.13: # in Loop: Header=BB2_12 Depth=1
movl $.L.str.1, %edi
movl %r14d, %ecx
xorl %eax, %eax
callq printf
jmp .LBB2_14
.LBB2_15: # %._crit_edge62
movq 40(%rsp), %rdi
callq hipEventDestroy
movq 32(%rsp), %rdi
callq hipEventDestroy
movq (%rsp), %rdi
callq hipStreamDestroy
movq %rbx, %rdi
callq free
movq %r12, %rdi
callq free
movq %r15, %rdi
callq free
xorl %eax, %eax
addq $5176, %rsp # imm = 0x1438
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.section .text._ZNSt24uniform_int_distributionIiEclISt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEEEiRT_RKNS0_10param_typeE,"axG",@progbits,_ZNSt24uniform_int_distributionIiEclISt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEEEiRT_RKNS0_10param_typeE,comdat
.weak _ZNSt24uniform_int_distributionIiEclISt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEEEiRT_RKNS0_10param_typeE # -- Begin function _ZNSt24uniform_int_distributionIiEclISt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEEEiRT_RKNS0_10param_typeE
.p2align 4, 0x90
.type _ZNSt24uniform_int_distributionIiEclISt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEEEiRT_RKNS0_10param_typeE,@function
_ZNSt24uniform_int_distributionIiEclISt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEEEiRT_RKNS0_10param_typeE: # @_ZNSt24uniform_int_distributionIiEclISt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEEEiRT_RKNS0_10param_typeE
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $24, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %r14
movslq 4(%rdx), %r15
movq %rdx, 8(%rsp) # 8-byte Spill
movslq (%rdx), %rax
subq %rax, %r15
movl $4294967294, %eax # imm = 0xFFFFFFFE
cmpq %rax, %r15
ja .LBB3_6
# %bb.1:
leal 1(%r15), %r12d
movq %r14, %rdi
callq _ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv
imulq %r12, %rax
cmpl %eax, %r12d
jbe .LBB3_5
# %bb.2:
notl %r15d
movq %rax, %rcx
movl %r15d, %eax
xorl %edx, %edx
divl %r12d
movq %rcx, %rax
cmpl %eax, %edx
jbe .LBB3_5
# %bb.3: # %.lr.ph.i.preheader
movl %edx, %ebp
.p2align 4, 0x90
.LBB3_4: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
movq %r14, %rdi
callq _ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv
imulq %r12, %rax
cmpl %eax, %ebp
ja .LBB3_4
.LBB3_5: # %_ZNSt24uniform_int_distributionIiE5_S_ndImSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEjEET1_RT0_S4_.exit
shrq $32, %rax
jmp .LBB3_11
.LBB3_6:
movl $4294967295, %eax # imm = 0xFFFFFFFF
cmpq %rax, %r15
jne .LBB3_7
# %bb.10:
movq %r14, %rdi
callq _ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv
jmp .LBB3_11
.LBB3_7: # %.preheader
movq %rdi, %r12
movabsq $-4294967296, %rbx # imm = 0xFFFFFFFF00000000
leaq 16(%rsp), %r13
.p2align 4, 0x90
.LBB3_8: # =>This Inner Loop Header: Depth=1
movq %rbx, 16(%rsp)
movq %r12, %rdi
movq %r14, %rsi
movq %r13, %rdx
callq _ZNSt24uniform_int_distributionIiEclISt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEEEiRT_RKNS0_10param_typeE
movl %eax, %ebp
shlq $32, %rbp
movq %r14, %rdi
callq _ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv
addq %rbp, %rax
setb %cl
cmpq %r15, %rax
ja .LBB3_8
# %bb.9: # in Loop: Header=BB3_8 Depth=1
testb %cl, %cl
jne .LBB3_8
.LBB3_11: # %.loopexit
movq 8(%rsp), %rcx # 8-byte Reload
addl (%rcx), %eax
# kill: def $eax killed $eax killed $rax
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size _ZNSt24uniform_int_distributionIiEclISt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEEEiRT_RKNS0_10param_typeE, .Lfunc_end3-_ZNSt24uniform_int_distributionIiEclISt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEEEiRT_RKNS0_10param_typeE
.cfi_endproc
# -- End function
.section .text._ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv,"axG",@progbits,_ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv,comdat
.weak _ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv # -- Begin function _ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv
.p2align 4, 0x90
.type _ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv,@function
_ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv: # @_ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv
.cfi_startproc
# %bb.0:
cmpq $624, 4992(%rdi) # imm = 0x270
jb .LBB4_6
# %bb.1: # %.preheader.preheader
movl $2567483615, %eax # imm = 0x9908B0DF
xorl %edx, %edx
movq $-2147483648, %rcx # imm = 0x80000000
.p2align 4, 0x90
.LBB4_2: # %.preheader
# =>This Inner Loop Header: Depth=1
movq (%rdi,%rdx,8), %rsi
andq %rcx, %rsi
movq 8(%rdi,%rdx,8), %r8
movl %r8d, %r9d
andl $2147483646, %r9d # imm = 0x7FFFFFFE
orq %rsi, %r9
shrq %r9
xorq 3176(%rdi,%rdx,8), %r9
andl $1, %r8d
negl %r8d
andl %eax, %r8d
xorq %r9, %r8
movq %r8, (%rdi,%rdx,8)
leaq 1(%rdx), %rsi
movq %rsi, %rdx
cmpq $227, %rsi
jne .LBB4_2
# %bb.3: # %.preheader.i.preheader
movl $228, %ecx
movq $-2147483648, %rdx # imm = 0x80000000
.p2align 4, 0x90
.LBB4_4: # %.preheader.i
# =>This Inner Loop Header: Depth=1
movq -8(%rdi,%rcx,8), %rsi
andq %rdx, %rsi
movq (%rdi,%rcx,8), %r8
movl %r8d, %r9d
andl $2147483646, %r9d # imm = 0x7FFFFFFE
orq %rsi, %r9
shrq %r9
xorq -1824(%rdi,%rcx,8), %r9
andl $1, %r8d
negl %r8d
andl %eax, %r8d
xorq %r9, %r8
movq %r8, -8(%rdi,%rcx,8)
incq %rcx
cmpq $624, %rcx # imm = 0x270
jne .LBB4_4
# %bb.5: # %_ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EE11_M_gen_randEv.exit
movq $-2147483648, %rcx # imm = 0x80000000
andq 4984(%rdi), %rcx
movq (%rdi), %rdx
movl %edx, %esi
andl $2147483646, %esi # imm = 0x7FFFFFFE
orq %rcx, %rsi
shrq %rsi
xorq 3168(%rdi), %rsi
andl $1, %edx
negl %edx
andl %eax, %edx
xorq %rsi, %rdx
movq %rdx, 4984(%rdi)
movq $0, 4992(%rdi)
.LBB4_6:
movq 4992(%rdi), %rax
leaq 1(%rax), %rcx
movq %rcx, 4992(%rdi)
movq (%rdi,%rax,8), %rax
movq %rax, %rcx
shrq $11, %rcx
movl %ecx, %ecx
xorq %rax, %rcx
movl %ecx, %eax
shll $7, %eax
andl $-1658038656, %eax # imm = 0x9D2C5680
xorq %rcx, %rax
movl %eax, %ecx
shll $15, %ecx
andl $-272236544, %ecx # imm = 0xEFC60000
xorq %rax, %rcx
movq %rcx, %rax
shrq $18, %rax
xorq %rcx, %rax
retq
.Lfunc_end4:
.size _ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv, .Lfunc_end4-_ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv
.cfi_endproc
# -- End function
.text
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z23parallel_implementationPiiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z23parallel_implementationPiiS_S_,@object # @_Z23parallel_implementationPiiS_S_
.section .rodata,"a",@progbits
.globl _Z23parallel_implementationPiiS_S_
.p2align 3, 0x0
_Z23parallel_implementationPiiS_S_:
.quad _Z38__device_stub__parallel_implementationPiiS_S_
.size _Z23parallel_implementationPiiS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Elapsed time: %f ms\n"
.size .L.str, 21
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "ERROR: %d != %d at index %d. Off by %d\n"
.size .L.str.1, 40
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z23parallel_implementationPiiS_S_"
.size .L__unnamed_1, 35
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z38__device_stub__parallel_implementationPiiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z23parallel_implementationPiiS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001826c0_00000000-6_scan.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB7682:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE7682:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z5log_2f
.type _Z5log_2f, @function
_Z5log_2f:
.LFB7677:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE7677:
.size _Z5log_2f, .-_Z5log_2f
.globl _Z21serial_implementationPii
.type _Z21serial_implementationPii, @function
_Z21serial_implementationPii:
.LFB7678:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movq %rdi, %rbx
movl %esi, %ebp
movslq %esi, %rdi
salq $2, %rdi
call malloc@PLT
movl $0, (%rax)
cmpl $1, %ebp
jle .L5
leal -1(%rbp), %esi
movl $0, %edx
.L7:
movl (%rbx,%rdx,4), %ecx
addl (%rax,%rdx,4), %ecx
movl %ecx, 4(%rax,%rdx,4)
addq $1, %rdx
cmpq %rsi, %rdx
jne .L7
.L5:
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE7678:
.size _Z21serial_implementationPii, .-_Z21serial_implementationPii
.globl _Z48__device_stub__Z23parallel_implementationPiiS_S_PiiS_S_
.type _Z48__device_stub__Z23parallel_implementationPiiS_S_PiiS_S_, @function
_Z48__device_stub__Z23parallel_implementationPiiS_S_PiiS_S_:
.LFB7704:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movq %rdx, 8(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L14
.L10:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L15
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z23parallel_implementationPiiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L10
.L15:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE7704:
.size _Z48__device_stub__Z23parallel_implementationPiiS_S_PiiS_S_, .-_Z48__device_stub__Z23parallel_implementationPiiS_S_PiiS_S_
.globl _Z23parallel_implementationPiiS_S_
.type _Z23parallel_implementationPiiS_S_, @function
_Z23parallel_implementationPiiS_S_:
.LFB7705:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z48__device_stub__Z23parallel_implementationPiiS_S_PiiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE7705:
.size _Z23parallel_implementationPiiS_S_, .-_Z23parallel_implementationPiiS_S_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z23parallel_implementationPiiS_S_"
.align 8
.LC1:
.string "_ZN37_INTERNAL_feca0e03_7_scan_cu_99bbe6644cuda3std3__419piecewise_constructE"
.align 8
.LC2:
.string "_ZN37_INTERNAL_feca0e03_7_scan_cu_99bbe6644cuda3std6ranges3__45__cpo4swapE"
.align 8
.LC3:
.string "_ZN37_INTERNAL_feca0e03_7_scan_cu_99bbe6644cuda3std6ranges3__45__cpo9iter_moveE"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB7707:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z23parallel_implementationPiiS_S_(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $1, %r9d
movl $0, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _ZN4cuda3std3__419piecewise_constructE(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $1, %r9d
movl $0, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _ZN4cuda3std6ranges3__45__cpo4swapE(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $1, %r9d
movl $0, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _ZN4cuda3std6ranges3__45__cpo9iter_moveE(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE7707:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .text._ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EE11_M_gen_randEv,"axG",@progbits,_ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EE11_M_gen_randEv,comdat
.align 2
.weak _ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EE11_M_gen_randEv
.type _ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EE11_M_gen_randEv, @function
_ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EE11_M_gen_randEv:
.LFB8565:
.cfi_startproc
endbr64
movq %rdi, %rdx
leaq 1816(%rdi), %r9
movq %rdi, %rcx
movl $2567483615, %r8d
.L22:
movq (%rcx), %rax
andq $-2147483648, %rax
movq 8(%rcx), %rsi
andl $2147483647, %esi
orq %rsi, %rax
movq %rax, %rsi
shrq %rsi
xorq 3176(%rcx), %rsi
andl $1, %eax
cmovne %r8, %rax
xorq %rsi, %rax
movq %rax, (%rcx)
addq $8, %rcx
cmpq %r9, %rcx
jne .L22
leaq 3168(%rdi), %r8
movl $2567483615, %esi
.L24:
movq 1816(%rdx), %rax
andq $-2147483648, %rax
movq 1824(%rdx), %rcx
andl $2147483647, %ecx
orq %rcx, %rax
movq %rax, %rcx
shrq %rcx
xorq (%rdx), %rcx
andl $1, %eax
cmovne %rsi, %rax
xorq %rcx, %rax
movq %rax, 1816(%rdx)
addq $8, %rdx
cmpq %r8, %rdx
jne .L24
movq 4984(%rdi), %rax
andq $-2147483648, %rax
movq (%rdi), %rdx
andl $2147483647, %edx
orq %rdx, %rax
movq %rax, %rdx
shrq %rdx
xorq 3168(%rdi), %rdx
andl $1, %eax
movl $2567483615, %ecx
cmovne %rcx, %rax
xorq %rdx, %rax
movq %rax, 4984(%rdi)
movq $0, 4992(%rdi)
ret
.cfi_endproc
.LFE8565:
.size _ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EE11_M_gen_randEv, .-_ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EE11_M_gen_randEv
.section .text._ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv,"axG",@progbits,_ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv,comdat
.align 2
.weak _ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv
.type _ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv, @function
_ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv:
.LFB8476:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movq %rdi, %rbx
cmpq $623, 4992(%rdi)
ja .L31
.L29:
movq 4992(%rbx), %rax
leaq 1(%rax), %rdx
movq %rdx, 4992(%rbx)
movq (%rbx,%rax,8), %rax
movq %rax, %rdx
shrq $11, %rdx
movl %edx, %edx
xorq %rax, %rdx
movq %rdx, %rax
salq $7, %rax
andl $2636928640, %eax
xorq %rdx, %rax
movq %rax, %rdx
salq $15, %rdx
andl $4022730752, %edx
xorq %rax, %rdx
movq %rdx, %rax
shrq $18, %rax
xorq %rdx, %rax
popq %rbx
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L31:
.cfi_restore_state
call _ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EE11_M_gen_randEv
jmp .L29
.cfi_endproc
.LFE8476:
.size _ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv, .-_ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv
.section .text._ZNSt24uniform_int_distributionIiEclISt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEEEiRT_RKNS0_10param_typeE,"axG",@progbits,_ZNSt24uniform_int_distributionIiEclISt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEEEiRT_RKNS0_10param_typeE,comdat
.align 2
.weak _ZNSt24uniform_int_distributionIiEclISt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEEEiRT_RKNS0_10param_typeE
.type _ZNSt24uniform_int_distributionIiEclISt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEEEiRT_RKNS0_10param_typeE, @function
_ZNSt24uniform_int_distributionIiEclISt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEEEiRT_RKNS0_10param_typeE:
.LFB8362:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $24, %rsp
.cfi_def_cfa_offset 80
movq %rsi, %rbp
movq %rdx, %r12
movq %fs:40, %rax
movq %rax, 8(%rsp)
xorl %eax, %eax
movslq 4(%rdx), %rbx
movslq (%rdx), %rax
subq %rax, %rbx
movl $4294967294, %eax
cmpq %rbx, %rax
jnb .L43
movq %rdi, %r14
movq %rbx, %rax
shrq $32, %rax
je .L37
movq %rsp, %r15
.L41:
movl $0, (%rsp)
movl $-1, 4(%rsp)
movq %r15, %rdx
movq %rbp, %rsi
movq %r14, %rdi
call _ZNSt24uniform_int_distributionIiEclISt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEEEiRT_RKNS0_10param_typeE
movq %rax, %r13
salq $32, %r13
movq %rbp, %rdi
call _ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv
addq %r13, %rax
cmpq %rax, %rbx
jb .L41
cmpq %r13, %rax
jb .L41
jmp .L36
.L43:
addq $1, %rbx
movq %rsi, %rdi
call _ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv
imulq %rbx, %rax
movq %rax, %rcx
cmpl %ebx, %eax
jnb .L34
movl %ebx, %eax
negl %eax
movl $0, %edx
divl %ebx
movl %edx, %r13d
cmpl %edx, %ecx
jnb .L34
.L35:
movq %rbp, %rdi
call _ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv
imulq %rbx, %rax
movq %rax, %rcx
cmpl %r13d, %eax
jb .L35
.L34:
movq %rcx, %rax
shrq $32, %rax
.L36:
addl (%r12), %eax
movq 8(%rsp), %rdx
subq %fs:40, %rdx
jne .L44
addq $24, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L37:
.cfi_restore_state
movq %rsi, %rdi
call _ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv
jmp .L36
.L44:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE8362:
.size _ZNSt24uniform_int_distributionIiEclISt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEEEiRT_RKNS0_10param_typeE, .-_ZNSt24uniform_int_distributionIiEclISt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEEEiRT_RKNS0_10param_typeE
.section .rodata.str1.1,"aMS",@progbits,1
.LC4:
.string "Elapsed time: %f ms\n"
.section .rodata.str1.8
.align 8
.LC5:
.string "ERROR: %d != %d at index %d. Off by %d\n"
.text
.globl main
.type main, @function
main:
.LFB7679:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $4096, %rsp
.cfi_def_cfa_offset 4152
orq $0, (%rsp)
subq $1032, %rsp
.cfi_def_cfa_offset 5184
movq %fs:40, %rax
movq %rax, 5112(%rsp)
xorl %eax, %eax
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %r15
movl %eax, 4(%rsp)
movslq %eax, %r12
leaq 0(,%r12,4), %rax
movq %rax, 8(%rsp)
movq %rax, %rdi
call malloc@PLT
movq %rax, %r13
movq $13, 112(%rsp)
movl $1, %ecx
movabsq $945986875574848801, %rdi
.L46:
movq 104(%rsp,%rcx,8), %rax
movq %rax, %rdx
shrq $30, %rdx
xorq %rdx, %rax
imulq $1812433253, %rax, %rsi
movq %rcx, %rdx
shrq $4, %rdx
movq %rdx, %rax
mulq %rdi
shrq %rdx
imulq $624, %rdx, %rdx
movq %rcx, %rax
subq %rdx, %rax
addl %esi, %eax
movq %rax, 112(%rsp,%rcx,8)
addq $1, %rcx
cmpq $624, %rcx
jne .L46
movq $624, 5104(%rsp)
movl $0, 80(%rsp)
movl $50, 84(%rsp)
testl %r15d, %r15d
jle .L47
movq %r13, %rbx
leal -1(%r15), %eax
leaq 4(%r13,%rax,4), %r14
leaq 80(%rsp), %rbp
.L48:
leaq 112(%rsp), %rsi
movq %rbp, %rdx
movq %rbp, %rdi
call _ZNSt24uniform_int_distributionIiEclISt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEEEiRT_RKNS0_10param_typeE
movl %eax, (%rbx)
addq $4, %rbx
cmpq %r14, %rbx
jne .L48
.L47:
leaq 32(%rsp), %rdi
call cudaStreamCreate@PLT
leaq 40(%rsp), %rdi
call cudaEventCreate@PLT
leaq 48(%rsp), %rdi
call cudaEventCreate@PLT
movq 8(%rsp), %rdi
addq $4, %rdi
call malloc@PLT
movq %rax, %rbp
leal 0(,%r12,4), %ebx
movslq %ebx, %rbx
leaq 56(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 64(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 72(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %r13, %rsi
movq 56(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %r13, %rsi
movq 64(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %r13, %rsi
movq 72(%rsp), %rdi
call cudaMemcpy@PLT
movq 32(%rsp), %rsi
movq 40(%rsp), %rdi
call cudaEventRecord@PLT
movl $1024, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
movl $1, 104(%rsp)
movl $1, 108(%rsp)
movq 32(%rsp), %r9
movl $0, %r8d
movq 88(%rsp), %rdx
movl $1, %ecx
movq 100(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L58
.L49:
movq 32(%rsp), %rsi
movq 48(%rsp), %rdi
call cudaEventRecord@PLT
leaq 4(%rbp), %rdi
movl $2, %ecx
movq %rbx, %rdx
movq 64(%rsp), %rsi
call cudaMemcpy@PLT
movl $0, 0(%rbp)
movq 32(%rsp), %rdi
call cudaStreamSynchronize@PLT
leaq 28(%rsp), %rdi
movq 48(%rsp), %rdx
movq 40(%rsp), %rsi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtss2sd 28(%rsp), %xmm0
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 56(%rsp), %rdi
call cudaFree@PLT
movq 64(%rsp), %rdi
call cudaFree@PLT
movq 72(%rsp), %rdi
call cudaFree@PLT
movl 4(%rsp), %esi
movq %r13, %rdi
call _Z21serial_implementationPii
movq %rax, %r12
testl %r15d, %r15d
jle .L50
leal -1(%r15), %r14d
movl $0, %ebx
leaq .LC5(%rip), %r15
jmp .L52
.L58:
movq 64(%rsp), %rcx
movq 72(%rsp), %rdx
movl 4(%rsp), %esi
movq 56(%rsp), %rdi
call _Z48__device_stub__Z23parallel_implementationPiiS_S_PiiS_S_
jmp .L49
.L51:
leaq 1(%rbx), %rax
cmpq %r14, %rbx
je .L50
movq %rax, %rbx
.L52:
movl (%r12,%rbx,4), %edx
movl 0(%rbp,%rbx,4), %ecx
cmpl %ecx, %edx
je .L51
movl %edx, %r9d
subl %ecx, %r9d
movl %ebx, %r8d
movq %r15, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L51
.L50:
movq 40(%rsp), %rdi
call cudaEventDestroy@PLT
movq 48(%rsp), %rdi
call cudaEventDestroy@PLT
movq 32(%rsp), %rdi
call cudaStreamDestroy@PLT
movq %r13, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
movq %rbp, %rdi
call free@PLT
movq 5112(%rsp), %rax
subq %fs:40, %rax
jne .L59
movl $0, %eax
addq $5128, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L59:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE7679:
.size main, .-main
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.weak _ZN4cuda3std3__419piecewise_constructE
.section .rodata._ZN4cuda3std3__419piecewise_constructE,"aG",@progbits,_ZN4cuda3std3__419piecewise_constructE,comdat
.type _ZN4cuda3std3__419piecewise_constructE, @gnu_unique_object
.size _ZN4cuda3std3__419piecewise_constructE, 1
_ZN4cuda3std3__419piecewise_constructE:
.zero 1
.weak _ZN4cuda3std6ranges3__45__cpo9iter_moveE
.section .rodata._ZN4cuda3std6ranges3__45__cpo9iter_moveE,"aG",@progbits,_ZN4cuda3std6ranges3__45__cpo9iter_moveE,comdat
.type _ZN4cuda3std6ranges3__45__cpo9iter_moveE, @gnu_unique_object
.size _ZN4cuda3std6ranges3__45__cpo9iter_moveE, 1
_ZN4cuda3std6ranges3__45__cpo9iter_moveE:
.zero 1
.weak _ZN4cuda3std6ranges3__45__cpo4swapE
.section .rodata._ZN4cuda3std6ranges3__45__cpo4swapE,"aG",@progbits,_ZN4cuda3std6ranges3__45__cpo4swapE,comdat
.type _ZN4cuda3std6ranges3__45__cpo4swapE, @gnu_unique_object
.size _ZN4cuda3std6ranges3__45__cpo4swapE, 1
_ZN4cuda3std6ranges3__45__cpo4swapE:
.zero 1
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "scan.hip"
.globl _Z38__device_stub__parallel_implementationPiiS_S_ # -- Begin function _Z38__device_stub__parallel_implementationPiiS_S_
.p2align 4, 0x90
.type _Z38__device_stub__parallel_implementationPiiS_S_,@function
_Z38__device_stub__parallel_implementationPiiS_S_: # @_Z38__device_stub__parallel_implementationPiiS_S_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movl %esi, 4(%rsp)
movq %rdx, 64(%rsp)
movq %rcx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 56(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z23parallel_implementationPiiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z38__device_stub__parallel_implementationPiiS_S_, .Lfunc_end0-_Z38__device_stub__parallel_implementationPiiS_S_
.cfi_endproc
# -- End function
.globl _Z21serial_implementationPii # -- Begin function _Z21serial_implementationPii
.p2align 4, 0x90
.type _Z21serial_implementationPii,@function
_Z21serial_implementationPii: # @_Z21serial_implementationPii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %rbp, -16
movl %esi, %ebp
movq %rdi, %rbx
movslq %esi, %r14
leaq (,%r14,4), %rdi
callq malloc
movl $0, (%rax)
cmpl $2, %r14d
jl .LBB1_3
# %bb.1: # %.lr.ph.preheader
movl %ebp, %ecx
movl (%rax), %edx
decq %rcx
xorl %esi, %esi
.p2align 4, 0x90
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
addl (%rbx,%rsi,4), %edx
movl %edx, 4(%rax,%rsi,4)
incq %rsi
cmpq %rsi, %rcx
jne .LBB1_2
.LBB1_3: # %._crit_edge
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z21serial_implementationPii, .Lfunc_end1-_Z21serial_implementationPii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $5176, %rsp # imm = 0x1438
.cfi_def_cfa_offset 5232
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq 8(%rsi), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r14
movslq %r14d, %rdi
shlq $2, %rdi
movq %rdi, 56(%rsp) # 8-byte Spill
callq malloc
movq %rax, %rbx
movq $13, 176(%rsp)
movl $1, %eax
movl $13, %ecx
.p2align 4, 0x90
.LBB2_1: # =>This Inner Loop Header: Depth=1
movq %rcx, %rdx
shrq $30, %rdx
xorl %ecx, %edx
imull $1812433253, %edx, %ecx # imm = 0x6C078965
addl %eax, %ecx
movq %rcx, 176(%rsp,%rax,8)
incq %rax
cmpq $624, %rax # imm = 0x270
jne .LBB2_1
# %bb.2: # %_ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEC2Em.exit
movq $624, 5168(%rsp) # imm = 0x270
movabsq $214748364800, %rax # imm = 0x3200000000
movq %rax, 136(%rsp)
testl %r14d, %r14d
jle .LBB2_5
# %bb.3: # %.lr.ph.preheader
movl %r14d, %ebp
xorl %r12d, %r12d
leaq 176(%rsp), %r15
leaq 136(%rsp), %r13
.p2align 4, 0x90
.LBB2_4: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movq %r13, %rdi
movq %r15, %rsi
movq %r13, %rdx
callq _ZNSt24uniform_int_distributionIiEclISt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEEEiRT_RKNS0_10param_typeE
movl %eax, (%rbx,%r12,4)
incq %r12
cmpq %r12, %rbp
jne .LBB2_4
.LBB2_5: # %._crit_edge
movq %rsp, %rdi
callq hipStreamCreate
leaq 40(%rsp), %rdi
callq hipEventCreate
leaq 32(%rsp), %rdi
callq hipEventCreate
movq %r14, %rdi
shlq $32, %rdi
movabsq $4294967296, %rbp # imm = 0x100000000
addq %rbp, %rdi
sarq $30, %rdi
callq malloc
movq %rax, %r15
movq %r14, %r13
shlq $34, %r13
sarq $32, %r13
leaq 24(%rsp), %rdi
movq %r13, %rsi
callq hipMalloc
leaq 8(%rsp), %rdi
movq %r13, %rsi
callq hipMalloc
leaq 16(%rsp), %rdi
movq %r13, %rsi
callq hipMalloc
movq 24(%rsp), %rdi
movq %rbx, %rsi
movq %r13, %rdx
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
movq %rbx, %rsi
movq %r13, %rdx
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
movq %rbx, %rsi
movq %r13, %rdx
movl $1, %ecx
callq hipMemcpy
movq 40(%rsp), %rdi
movq (%rsp), %rsi
callq hipEventRecord
movq (%rsp), %r9
leaq 1(%rbp), %rdi
orq $1024, %rbp # imm = 0x400
movl $1, %esi
movq %rbp, %rdx
movl $1, %ecx
xorl %r8d, %r8d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_7
# %bb.6:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 128(%rsp)
movl %r14d, 52(%rsp)
movq %rcx, 120(%rsp)
movq %rdx, 112(%rsp)
leaq 128(%rsp), %rax
movq %rax, 144(%rsp)
leaq 52(%rsp), %rax
movq %rax, 152(%rsp)
leaq 120(%rsp), %rax
movq %rax, 160(%rsp)
leaq 112(%rsp), %rax
movq %rax, 168(%rsp)
leaq 96(%rsp), %rdi
leaq 80(%rsp), %rsi
leaq 72(%rsp), %rdx
leaq 64(%rsp), %rcx
callq __hipPopCallConfiguration
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
movq 80(%rsp), %rcx
movl 88(%rsp), %r8d
leaq 144(%rsp), %r9
movl $_Z23parallel_implementationPiiS_S_, %edi
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
pushq 80(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_7:
movq 32(%rsp), %rdi
movq (%rsp), %rsi
callq hipEventRecord
movq %r15, %rdi
addq $4, %rdi
movq 8(%rsp), %rsi
movq %r13, %rdx
movl $2, %ecx
callq hipMemcpy
movl $0, (%r15)
movq (%rsp), %rdi
callq hipStreamSynchronize
movq 40(%rsp), %rsi
movq 32(%rsp), %rdx
leaq 144(%rsp), %rdi
callq hipEventElapsedTime
movss 144(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
movq 24(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 56(%rsp), %rdi # 8-byte Reload
callq malloc
movq %rax, %r12
movl $0, (%rax)
cmpl $2, %r14d
jl .LBB2_10
# %bb.8: # %.lr.ph.preheader.i
movl %r14d, %eax
movl (%r12), %ecx
decq %rax
xorl %edx, %edx
.p2align 4, 0x90
.LBB2_9: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
addl (%rbx,%rdx,4), %ecx
movl %ecx, 4(%r12,%rdx,4)
incq %rdx
cmpq %rdx, %rax
jne .LBB2_9
.LBB2_10: # %_Z21serial_implementationPii.exit
testl %r14d, %r14d
jle .LBB2_15
# %bb.11: # %.lr.ph61.preheader
movl %r14d, %r13d
xorl %r14d, %r14d
jmp .LBB2_12
.p2align 4, 0x90
.LBB2_14: # in Loop: Header=BB2_12 Depth=1
incq %r14
cmpq %r14, %r13
je .LBB2_15
.LBB2_12: # %.lr.ph61
# =>This Inner Loop Header: Depth=1
movl (%r12,%r14,4), %esi
movl (%r15,%r14,4), %edx
movl %esi, %r8d
subl %edx, %r8d
je .LBB2_14
# %bb.13: # in Loop: Header=BB2_12 Depth=1
movl $.L.str.1, %edi
movl %r14d, %ecx
xorl %eax, %eax
callq printf
jmp .LBB2_14
.LBB2_15: # %._crit_edge62
movq 40(%rsp), %rdi
callq hipEventDestroy
movq 32(%rsp), %rdi
callq hipEventDestroy
movq (%rsp), %rdi
callq hipStreamDestroy
movq %rbx, %rdi
callq free
movq %r12, %rdi
callq free
movq %r15, %rdi
callq free
xorl %eax, %eax
addq $5176, %rsp # imm = 0x1438
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.section .text._ZNSt24uniform_int_distributionIiEclISt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEEEiRT_RKNS0_10param_typeE,"axG",@progbits,_ZNSt24uniform_int_distributionIiEclISt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEEEiRT_RKNS0_10param_typeE,comdat
.weak _ZNSt24uniform_int_distributionIiEclISt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEEEiRT_RKNS0_10param_typeE # -- Begin function _ZNSt24uniform_int_distributionIiEclISt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEEEiRT_RKNS0_10param_typeE
.p2align 4, 0x90
.type _ZNSt24uniform_int_distributionIiEclISt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEEEiRT_RKNS0_10param_typeE,@function
_ZNSt24uniform_int_distributionIiEclISt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEEEiRT_RKNS0_10param_typeE: # @_ZNSt24uniform_int_distributionIiEclISt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEEEiRT_RKNS0_10param_typeE
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $24, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %r14
movslq 4(%rdx), %r15
movq %rdx, 8(%rsp) # 8-byte Spill
movslq (%rdx), %rax
subq %rax, %r15
movl $4294967294, %eax # imm = 0xFFFFFFFE
cmpq %rax, %r15
ja .LBB3_6
# %bb.1:
leal 1(%r15), %r12d
movq %r14, %rdi
callq _ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv
imulq %r12, %rax
cmpl %eax, %r12d
jbe .LBB3_5
# %bb.2:
notl %r15d
movq %rax, %rcx
movl %r15d, %eax
xorl %edx, %edx
divl %r12d
movq %rcx, %rax
cmpl %eax, %edx
jbe .LBB3_5
# %bb.3: # %.lr.ph.i.preheader
movl %edx, %ebp
.p2align 4, 0x90
.LBB3_4: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
movq %r14, %rdi
callq _ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv
imulq %r12, %rax
cmpl %eax, %ebp
ja .LBB3_4
.LBB3_5: # %_ZNSt24uniform_int_distributionIiE5_S_ndImSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEjEET1_RT0_S4_.exit
shrq $32, %rax
jmp .LBB3_11
.LBB3_6:
movl $4294967295, %eax # imm = 0xFFFFFFFF
cmpq %rax, %r15
jne .LBB3_7
# %bb.10:
movq %r14, %rdi
callq _ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv
jmp .LBB3_11
.LBB3_7: # %.preheader
movq %rdi, %r12
movabsq $-4294967296, %rbx # imm = 0xFFFFFFFF00000000
leaq 16(%rsp), %r13
.p2align 4, 0x90
.LBB3_8: # =>This Inner Loop Header: Depth=1
movq %rbx, 16(%rsp)
movq %r12, %rdi
movq %r14, %rsi
movq %r13, %rdx
callq _ZNSt24uniform_int_distributionIiEclISt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEEEiRT_RKNS0_10param_typeE
movl %eax, %ebp
shlq $32, %rbp
movq %r14, %rdi
callq _ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv
addq %rbp, %rax
setb %cl
cmpq %r15, %rax
ja .LBB3_8
# %bb.9: # in Loop: Header=BB3_8 Depth=1
testb %cl, %cl
jne .LBB3_8
.LBB3_11: # %.loopexit
movq 8(%rsp), %rcx # 8-byte Reload
addl (%rcx), %eax
# kill: def $eax killed $eax killed $rax
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size _ZNSt24uniform_int_distributionIiEclISt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEEEiRT_RKNS0_10param_typeE, .Lfunc_end3-_ZNSt24uniform_int_distributionIiEclISt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEEEiRT_RKNS0_10param_typeE
.cfi_endproc
# -- End function
.section .text._ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv,"axG",@progbits,_ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv,comdat
.weak _ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv # -- Begin function _ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv
.p2align 4, 0x90
.type _ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv,@function
_ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv: # @_ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv
.cfi_startproc
# %bb.0:
cmpq $624, 4992(%rdi) # imm = 0x270
jb .LBB4_6
# %bb.1: # %.preheader.preheader
movl $2567483615, %eax # imm = 0x9908B0DF
xorl %edx, %edx
movq $-2147483648, %rcx # imm = 0x80000000
.p2align 4, 0x90
.LBB4_2: # %.preheader
# =>This Inner Loop Header: Depth=1
movq (%rdi,%rdx,8), %rsi
andq %rcx, %rsi
movq 8(%rdi,%rdx,8), %r8
movl %r8d, %r9d
andl $2147483646, %r9d # imm = 0x7FFFFFFE
orq %rsi, %r9
shrq %r9
xorq 3176(%rdi,%rdx,8), %r9
andl $1, %r8d
negl %r8d
andl %eax, %r8d
xorq %r9, %r8
movq %r8, (%rdi,%rdx,8)
leaq 1(%rdx), %rsi
movq %rsi, %rdx
cmpq $227, %rsi
jne .LBB4_2
# %bb.3: # %.preheader.i.preheader
movl $228, %ecx
movq $-2147483648, %rdx # imm = 0x80000000
.p2align 4, 0x90
.LBB4_4: # %.preheader.i
# =>This Inner Loop Header: Depth=1
movq -8(%rdi,%rcx,8), %rsi
andq %rdx, %rsi
movq (%rdi,%rcx,8), %r8
movl %r8d, %r9d
andl $2147483646, %r9d # imm = 0x7FFFFFFE
orq %rsi, %r9
shrq %r9
xorq -1824(%rdi,%rcx,8), %r9
andl $1, %r8d
negl %r8d
andl %eax, %r8d
xorq %r9, %r8
movq %r8, -8(%rdi,%rcx,8)
incq %rcx
cmpq $624, %rcx # imm = 0x270
jne .LBB4_4
# %bb.5: # %_ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EE11_M_gen_randEv.exit
movq $-2147483648, %rcx # imm = 0x80000000
andq 4984(%rdi), %rcx
movq (%rdi), %rdx
movl %edx, %esi
andl $2147483646, %esi # imm = 0x7FFFFFFE
orq %rcx, %rsi
shrq %rsi
xorq 3168(%rdi), %rsi
andl $1, %edx
negl %edx
andl %eax, %edx
xorq %rsi, %rdx
movq %rdx, 4984(%rdi)
movq $0, 4992(%rdi)
.LBB4_6:
movq 4992(%rdi), %rax
leaq 1(%rax), %rcx
movq %rcx, 4992(%rdi)
movq (%rdi,%rax,8), %rax
movq %rax, %rcx
shrq $11, %rcx
movl %ecx, %ecx
xorq %rax, %rcx
movl %ecx, %eax
shll $7, %eax
andl $-1658038656, %eax # imm = 0x9D2C5680
xorq %rcx, %rax
movl %eax, %ecx
shll $15, %ecx
andl $-272236544, %ecx # imm = 0xEFC60000
xorq %rax, %rcx
movq %rcx, %rax
shrq $18, %rax
xorq %rcx, %rax
retq
.Lfunc_end4:
.size _ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv, .Lfunc_end4-_ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv
.cfi_endproc
# -- End function
.text
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z23parallel_implementationPiiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z23parallel_implementationPiiS_S_,@object # @_Z23parallel_implementationPiiS_S_
.section .rodata,"a",@progbits
.globl _Z23parallel_implementationPiiS_S_
.p2align 3, 0x0
_Z23parallel_implementationPiiS_S_:
.quad _Z38__device_stub__parallel_implementationPiiS_S_
.size _Z23parallel_implementationPiiS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Elapsed time: %f ms\n"
.size .L.str, 21
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "ERROR: %d != %d at index %d. Off by %d\n"
.size .L.str.1, 40
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z23parallel_implementationPiiS_S_"
.size .L__unnamed_1, 35
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z38__device_stub__parallel_implementationPiiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z23parallel_implementationPiiS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <assert.h>
#include <unistd.h>
#include <sys/time.h>
/* Problem size */
#define M 1024
#define N 1024
#define FLOAT_N 3214212.01
void init_arrays(double* data)
{
int i, j;
for (i = 1; i < (M+1); i++) {
for (j = 1; j < (N+1); j++) {
data[i*(N+1) + j] = ((double) i*j) / M;
}
}
}
__global__ void mean_kernel(double* data, double* mean)
{
int j = blockIdx.x * blockDim.x + threadIdx.x + 1;
__shared__ double mean_shared;
if (j < (M+1))
{
mean_shared = 0.0;
int i;
for(i = 1; i < (N+1); i++)
{
mean_shared += data[i * (M+1) + j];
}
mean_shared /= FLOAT_N;
mean[j] = mean_shared;
}
}
__global__ void data_kernel(double* data, double* mean)
{
int j = blockIdx.x * blockDim.x + threadIdx.x + 1;
int i = blockIdx.y * blockDim.y + threadIdx.y + 1;
if ((i < (N+1)) && (j < (M+1)))
{
data[i * (M+1) + j] -= mean[j];
}
}
__global__ void symmat_kernel(double* symmat, double* data)
{
int j1 = blockIdx.x * blockDim.x + threadIdx.x + 1;
int i, j2;
__shared__ double symmat_shared;
if (j1 < (M+1))
{
for (j2 = j1; j2 < (M+1); j2++)
{
symmat_shared = 0.0;
for(i = 1; i < (N+1); i++)
{
symmat_shared += data[i * (M+1) + j1] * data[i * (M+1) + j2];
}
symmat[j1 * (M+1) + j2] = symmat_shared;
symmat[j2 * (M+1) + j1] = symmat[j1 * (M+1) + j2];
}
}
}
int main(int argc, char *argv[])
{
double *data_h, *data_d;
double *symmat_h, *symmat_d;
double *mean_h, *mean_d;
struct timeval cpu_start, cpu_end;
data_h = (double*)malloc((M+1)*(N+1)*sizeof(double));
mean_h = (double*)malloc((M+1)*sizeof(double));
symmat_h = (double*)malloc((M+1)*(M+1)*sizeof(double));
// Δέσμευση μνήμης στο device για τα διανύσματα
cudaMalloc((void **) &data_d, (M+1)*(N+1)*sizeof(double));
cudaMalloc((void **) &mean_d, (M+1)*sizeof(double));
cudaMalloc((void **) &symmat_d, (M+1)*(M+1)*sizeof(double));
cudaMemset(data_d, 0, (M+1)*(N+1)*sizeof(double));
// cudaMemset(symmat_d, 0, (M+1)*(M+1)*sizeof(double));
// cudaMemset(mean_d, 0, (M+1)*sizeof(double));
init_arrays(data_h);
// Αντιγραφή data στο device
cudaMemcpy(data_d, data_h, (M+1)*(N+1)*sizeof(double), cudaMemcpyHostToDevice);
//cudaMemcpy(symmat_d, symmat_h, (M+1)*(M+1)*sizeof(double), cudaMemcpyHostToDevice);
//cudaMemcpy(mean_d, mean_h, (M+1)*sizeof(double), cudaMemcpyHostToDevice);
//----------------------------------------------------------------------
// Κάθε block θα έχει διάσταση 16x16
unsigned int BLOCK_SIZE_PER_DIM = 16;
// Ορισμός διαστάσεων πλέγματος
dim3 dimGrid1((M - 1) / BLOCK_SIZE_PER_DIM + 1, 1);
dim3 dimGrid2((M - 1) / BLOCK_SIZE_PER_DIM + 1, (N - 1) / BLOCK_SIZE_PER_DIM + 1);
dim3 dimGrid3((M - 1) / BLOCK_SIZE_PER_DIM + 1, 1);
// Ορισμός διαστάσεων block
dim3 dimBlock(BLOCK_SIZE_PER_DIM, BLOCK_SIZE_PER_DIM, 1);
//----------------------------------------------------------------------
gettimeofday(&cpu_start, NULL);
mean_kernel<<<dimGrid1, dimBlock>>>(data_d, mean_d);
cudaThreadSynchronize();
data_kernel<<<dimGrid2, dimBlock>>>(data_d, mean_d);
cudaThreadSynchronize();
symmat_kernel<<<dimGrid3, dimBlock>>>(symmat_d,data_d);
cudaThreadSynchronize();
cudaMemcpy(symmat_h, symmat_d, (M+1)*(M+1)*sizeof(double), cudaMemcpyDeviceToHost);
gettimeofday(&cpu_end, NULL);
fprintf(stdout, "GPU Runtime: %0.6lfs\n", ((cpu_end.tv_sec - cpu_start.tv_sec) * 1000000.0 + (cpu_end.tv_usec - cpu_start.tv_usec)) / 1000000.0);
printf("================================\n");
FILE *f = fopen("ask3_cuda_output.txt", "w+");
if (f == NULL)
{
printf("Error opening ask3_cuda_output.txt!\n");
exit(1);
}
for(int i = 1; i < (M+1); i++) {
for(int j = 1; j < (M+1); j++){
fprintf(f, "%f\n", symmat_h[i * (M+1) + j]);
}
}
if(f) { printf("Results saved in ask3_cuda_output.txt!\n"); }
fclose(f);
// Αποδέσμευση μνήμης στον host
free(data_h);
free(mean_h);
free(symmat_h);
// Αποδέσμευση μνήμης στον host
cudaFree(data_d);
cudaFree(mean_d);
cudaFree(symmat_d);
return 0;
} | .file "tmpxft_0010af47_00000000-6_ask3_cuda.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2074:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2074:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z11init_arraysPd
.type _Z11init_arraysPd, @function
_Z11init_arraysPd:
.LFB2070:
.cfi_startproc
endbr64
leaq 8200(%rdi), %rdx
movl $1, %ecx
movsd .LC0(%rip), %xmm2
.L4:
movl $1, %eax
pxor %xmm1, %xmm1
cvtsi2sdl %ecx, %xmm1
.L5:
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
mulsd %xmm1, %xmm0
mulsd %xmm2, %xmm0
movsd %xmm0, (%rdx,%rax,8)
addq $1, %rax
cmpq $1025, %rax
jne .L5
addl $1, %ecx
addq $8200, %rdx
cmpl $1025, %ecx
jne .L4
ret
.cfi_endproc
.LFE2070:
.size _Z11init_arraysPd, .-_Z11init_arraysPd
.globl _Z33__device_stub__Z11mean_kernelPdS_PdS_
.type _Z33__device_stub__Z11mean_kernelPdS_PdS_, @function
_Z33__device_stub__Z11mean_kernelPdS_PdS_:
.LFB2096:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L12
.L8:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L13
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L12:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z11mean_kernelPdS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L8
.L13:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2096:
.size _Z33__device_stub__Z11mean_kernelPdS_PdS_, .-_Z33__device_stub__Z11mean_kernelPdS_PdS_
.globl _Z11mean_kernelPdS_
.type _Z11mean_kernelPdS_, @function
_Z11mean_kernelPdS_:
.LFB2097:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z11mean_kernelPdS_PdS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2097:
.size _Z11mean_kernelPdS_, .-_Z11mean_kernelPdS_
.globl _Z33__device_stub__Z11data_kernelPdS_PdS_
.type _Z33__device_stub__Z11data_kernelPdS_PdS_, @function
_Z33__device_stub__Z11data_kernelPdS_PdS_:
.LFB2098:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L20
.L16:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L21
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L20:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z11data_kernelPdS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L16
.L21:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2098:
.size _Z33__device_stub__Z11data_kernelPdS_PdS_, .-_Z33__device_stub__Z11data_kernelPdS_PdS_
.globl _Z11data_kernelPdS_
.type _Z11data_kernelPdS_, @function
_Z11data_kernelPdS_:
.LFB2099:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z11data_kernelPdS_PdS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2099:
.size _Z11data_kernelPdS_, .-_Z11data_kernelPdS_
.globl _Z35__device_stub__Z13symmat_kernelPdS_PdS_
.type _Z35__device_stub__Z13symmat_kernelPdS_PdS_, @function
_Z35__device_stub__Z13symmat_kernelPdS_PdS_:
.LFB2100:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L28
.L24:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L29
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L28:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z13symmat_kernelPdS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L24
.L29:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2100:
.size _Z35__device_stub__Z13symmat_kernelPdS_PdS_, .-_Z35__device_stub__Z13symmat_kernelPdS_PdS_
.globl _Z13symmat_kernelPdS_
.type _Z13symmat_kernelPdS_, @function
_Z13symmat_kernelPdS_:
.LFB2101:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z13symmat_kernelPdS_PdS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2101:
.size _Z13symmat_kernelPdS_, .-_Z13symmat_kernelPdS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "GPU Runtime: %0.6lfs\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC3:
.string "================================\n"
.section .rodata.str1.1
.LC4:
.string "w+"
.LC5:
.string "ask3_cuda_output.txt"
.section .rodata.str1.8
.align 8
.LC6:
.string "Error opening ask3_cuda_output.txt!\n"
.section .rodata.str1.1
.LC7:
.string "%f\n"
.section .rodata.str1.8
.align 8
.LC8:
.string "Results saved in ask3_cuda_output.txt!\n"
.text
.globl main
.type main, @function
main:
.LFB2071:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $152, %rsp
.cfi_def_cfa_offset 208
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
movl $8405000, %edi
call malloc@PLT
movq %rax, %rbx
movq %rax, 8(%rsp)
movl $8405000, %edi
call malloc@PLT
movq %rax, %r15
leaq 24(%rsp), %rdi
movl $8405000, %esi
call cudaMalloc@PLT
leaq 40(%rsp), %rdi
movl $8200, %esi
call cudaMalloc@PLT
leaq 32(%rsp), %rdi
movl $8405000, %esi
call cudaMalloc@PLT
movl $8405000, %edx
movl $0, %esi
movq 24(%rsp), %rdi
call cudaMemset@PLT
movq %rbx, %rdi
call _Z11init_arraysPd
movl $1, %ecx
movl $8405000, %edx
movq %rbx, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl $64, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $64, 60(%rsp)
movl $64, 64(%rsp)
movl $1, 68(%rsp)
movl $64, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $16, 84(%rsp)
movl $16, 88(%rsp)
movl $1, 92(%rsp)
leaq 96(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
movl 92(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 84(%rsp), %rdx
movq 48(%rsp), %rdi
movl 56(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L43
.L33:
call cudaThreadSynchronize@PLT
movl 92(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 84(%rsp), %rdx
movq 60(%rsp), %rdi
movl 68(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L44
.L34:
call cudaThreadSynchronize@PLT
movl 92(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 84(%rsp), %rdx
movq 72(%rsp), %rdi
movl 80(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L45
.L35:
call cudaThreadSynchronize@PLT
movl $2, %ecx
movl $8405000, %edx
movq 32(%rsp), %rsi
movq %r15, %rdi
call cudaMemcpy@PLT
leaq 112(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
movq 112(%rsp), %rax
subq 96(%rsp), %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
movsd .LC1(%rip), %xmm1
mulsd %xmm1, %xmm0
movq 120(%rsp), %rax
subq 104(%rsp), %rax
pxor %xmm2, %xmm2
cvtsi2sdq %rax, %xmm2
addsd %xmm2, %xmm0
divsd %xmm1, %xmm0
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $1, %eax
call __fprintf_chk@PLT
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC4(%rip), %rsi
leaq .LC5(%rip), %rdi
call fopen@PLT
movq %rax, %r12
testq %rax, %rax
je .L36
leaq 16400(%r15), %rbp
leaq 8413200(%r15), %r14
leaq .LC7(%rip), %r13
.L37:
leaq -8192(%rbp), %rbx
.L38:
movsd (%rbx), %xmm0
movq %r13, %rdx
movl $2, %esi
movq %r12, %rdi
movl $1, %eax
call __fprintf_chk@PLT
addq $8, %rbx
cmpq %rbp, %rbx
jne .L38
addq $8200, %rbp
cmpq %r14, %rbp
jne .L37
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %r12, %rdi
call fclose@PLT
movq 8(%rsp), %rdi
call free@PLT
movq %r15, %rdi
call free@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L46
movl $0, %eax
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L43:
.cfi_restore_state
movq 40(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z33__device_stub__Z11mean_kernelPdS_PdS_
jmp .L33
.L44:
movq 40(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z33__device_stub__Z11data_kernelPdS_PdS_
jmp .L34
.L45:
movq 24(%rsp), %rsi
movq 32(%rsp), %rdi
call _Z35__device_stub__Z13symmat_kernelPdS_PdS_
jmp .L35
.L36:
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L46:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2071:
.size main, .-main
.section .rodata.str1.1
.LC9:
.string "_Z13symmat_kernelPdS_"
.LC10:
.string "_Z11data_kernelPdS_"
.LC11:
.string "_Z11mean_kernelPdS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2103:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _Z13symmat_kernelPdS_(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC10(%rip), %rdx
movq %rdx, %rcx
leaq _Z11data_kernelPdS_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC11(%rip), %rdx
movq %rdx, %rcx
leaq _Z11mean_kernelPdS_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2103:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long 0
.long 1062207488
.align 8
.LC1:
.long 0
.long 1093567616
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <assert.h>
#include <unistd.h>
#include <sys/time.h>
/* Problem size */
#define M 1024
#define N 1024
#define FLOAT_N 3214212.01
void init_arrays(double* data)
{
int i, j;
for (i = 1; i < (M+1); i++) {
for (j = 1; j < (N+1); j++) {
data[i*(N+1) + j] = ((double) i*j) / M;
}
}
}
__global__ void mean_kernel(double* data, double* mean)
{
int j = blockIdx.x * blockDim.x + threadIdx.x + 1;
__shared__ double mean_shared;
if (j < (M+1))
{
mean_shared = 0.0;
int i;
for(i = 1; i < (N+1); i++)
{
mean_shared += data[i * (M+1) + j];
}
mean_shared /= FLOAT_N;
mean[j] = mean_shared;
}
}
__global__ void data_kernel(double* data, double* mean)
{
int j = blockIdx.x * blockDim.x + threadIdx.x + 1;
int i = blockIdx.y * blockDim.y + threadIdx.y + 1;
if ((i < (N+1)) && (j < (M+1)))
{
data[i * (M+1) + j] -= mean[j];
}
}
__global__ void symmat_kernel(double* symmat, double* data)
{
int j1 = blockIdx.x * blockDim.x + threadIdx.x + 1;
int i, j2;
__shared__ double symmat_shared;
if (j1 < (M+1))
{
for (j2 = j1; j2 < (M+1); j2++)
{
symmat_shared = 0.0;
for(i = 1; i < (N+1); i++)
{
symmat_shared += data[i * (M+1) + j1] * data[i * (M+1) + j2];
}
symmat[j1 * (M+1) + j2] = symmat_shared;
symmat[j2 * (M+1) + j1] = symmat[j1 * (M+1) + j2];
}
}
}
int main(int argc, char *argv[])
{
double *data_h, *data_d;
double *symmat_h, *symmat_d;
double *mean_h, *mean_d;
struct timeval cpu_start, cpu_end;
data_h = (double*)malloc((M+1)*(N+1)*sizeof(double));
mean_h = (double*)malloc((M+1)*sizeof(double));
symmat_h = (double*)malloc((M+1)*(M+1)*sizeof(double));
// Δέσμευση μνήμης στο device για τα διανύσματα
cudaMalloc((void **) &data_d, (M+1)*(N+1)*sizeof(double));
cudaMalloc((void **) &mean_d, (M+1)*sizeof(double));
cudaMalloc((void **) &symmat_d, (M+1)*(M+1)*sizeof(double));
cudaMemset(data_d, 0, (M+1)*(N+1)*sizeof(double));
// cudaMemset(symmat_d, 0, (M+1)*(M+1)*sizeof(double));
// cudaMemset(mean_d, 0, (M+1)*sizeof(double));
init_arrays(data_h);
// Αντιγραφή data στο device
cudaMemcpy(data_d, data_h, (M+1)*(N+1)*sizeof(double), cudaMemcpyHostToDevice);
//cudaMemcpy(symmat_d, symmat_h, (M+1)*(M+1)*sizeof(double), cudaMemcpyHostToDevice);
//cudaMemcpy(mean_d, mean_h, (M+1)*sizeof(double), cudaMemcpyHostToDevice);
//----------------------------------------------------------------------
// Κάθε block θα έχει διάσταση 16x16
unsigned int BLOCK_SIZE_PER_DIM = 16;
// Ορισμός διαστάσεων πλέγματος
dim3 dimGrid1((M - 1) / BLOCK_SIZE_PER_DIM + 1, 1);
dim3 dimGrid2((M - 1) / BLOCK_SIZE_PER_DIM + 1, (N - 1) / BLOCK_SIZE_PER_DIM + 1);
dim3 dimGrid3((M - 1) / BLOCK_SIZE_PER_DIM + 1, 1);
// Ορισμός διαστάσεων block
dim3 dimBlock(BLOCK_SIZE_PER_DIM, BLOCK_SIZE_PER_DIM, 1);
//----------------------------------------------------------------------
gettimeofday(&cpu_start, NULL);
mean_kernel<<<dimGrid1, dimBlock>>>(data_d, mean_d);
cudaThreadSynchronize();
data_kernel<<<dimGrid2, dimBlock>>>(data_d, mean_d);
cudaThreadSynchronize();
symmat_kernel<<<dimGrid3, dimBlock>>>(symmat_d,data_d);
cudaThreadSynchronize();
cudaMemcpy(symmat_h, symmat_d, (M+1)*(M+1)*sizeof(double), cudaMemcpyDeviceToHost);
gettimeofday(&cpu_end, NULL);
fprintf(stdout, "GPU Runtime: %0.6lfs\n", ((cpu_end.tv_sec - cpu_start.tv_sec) * 1000000.0 + (cpu_end.tv_usec - cpu_start.tv_usec)) / 1000000.0);
printf("================================\n");
FILE *f = fopen("ask3_cuda_output.txt", "w+");
if (f == NULL)
{
printf("Error opening ask3_cuda_output.txt!\n");
exit(1);
}
for(int i = 1; i < (M+1); i++) {
for(int j = 1; j < (M+1); j++){
fprintf(f, "%f\n", symmat_h[i * (M+1) + j]);
}
}
if(f) { printf("Results saved in ask3_cuda_output.txt!\n"); }
fclose(f);
// Αποδέσμευση μνήμης στον host
free(data_h);
free(mean_h);
free(symmat_h);
// Αποδέσμευση μνήμης στον host
cudaFree(data_d);
cudaFree(mean_d);
cudaFree(symmat_d);
return 0;
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <assert.h>
#include <unistd.h>
#include <sys/time.h>
/* Problem size */
#define M 1024
#define N 1024
#define FLOAT_N 3214212.01
void init_arrays(double* data)
{
int i, j;
for (i = 1; i < (M+1); i++) {
for (j = 1; j < (N+1); j++) {
data[i*(N+1) + j] = ((double) i*j) / M;
}
}
}
__global__ void mean_kernel(double* data, double* mean)
{
int j = blockIdx.x * blockDim.x + threadIdx.x + 1;
__shared__ double mean_shared;
if (j < (M+1))
{
mean_shared = 0.0;
int i;
for(i = 1; i < (N+1); i++)
{
mean_shared += data[i * (M+1) + j];
}
mean_shared /= FLOAT_N;
mean[j] = mean_shared;
}
}
__global__ void data_kernel(double* data, double* mean)
{
int j = blockIdx.x * blockDim.x + threadIdx.x + 1;
int i = blockIdx.y * blockDim.y + threadIdx.y + 1;
if ((i < (N+1)) && (j < (M+1)))
{
data[i * (M+1) + j] -= mean[j];
}
}
__global__ void symmat_kernel(double* symmat, double* data)
{
int j1 = blockIdx.x * blockDim.x + threadIdx.x + 1;
int i, j2;
__shared__ double symmat_shared;
if (j1 < (M+1))
{
for (j2 = j1; j2 < (M+1); j2++)
{
symmat_shared = 0.0;
for(i = 1; i < (N+1); i++)
{
symmat_shared += data[i * (M+1) + j1] * data[i * (M+1) + j2];
}
symmat[j1 * (M+1) + j2] = symmat_shared;
symmat[j2 * (M+1) + j1] = symmat[j1 * (M+1) + j2];
}
}
}
int main(int argc, char *argv[])
{
double *data_h, *data_d;
double *symmat_h, *symmat_d;
double *mean_h, *mean_d;
struct timeval cpu_start, cpu_end;
data_h = (double*)malloc((M+1)*(N+1)*sizeof(double));
mean_h = (double*)malloc((M+1)*sizeof(double));
symmat_h = (double*)malloc((M+1)*(M+1)*sizeof(double));
// Δέσμευση μνήμης στο device για τα διανύσματα
hipMalloc((void **) &data_d, (M+1)*(N+1)*sizeof(double));
hipMalloc((void **) &mean_d, (M+1)*sizeof(double));
hipMalloc((void **) &symmat_d, (M+1)*(M+1)*sizeof(double));
hipMemset(data_d, 0, (M+1)*(N+1)*sizeof(double));
// cudaMemset(symmat_d, 0, (M+1)*(M+1)*sizeof(double));
// cudaMemset(mean_d, 0, (M+1)*sizeof(double));
init_arrays(data_h);
// Αντιγραφή data στο device
hipMemcpy(data_d, data_h, (M+1)*(N+1)*sizeof(double), hipMemcpyHostToDevice);
//cudaMemcpy(symmat_d, symmat_h, (M+1)*(M+1)*sizeof(double), cudaMemcpyHostToDevice);
//cudaMemcpy(mean_d, mean_h, (M+1)*sizeof(double), cudaMemcpyHostToDevice);
//----------------------------------------------------------------------
// Κάθε block θα έχει διάσταση 16x16
unsigned int BLOCK_SIZE_PER_DIM = 16;
// Ορισμός διαστάσεων πλέγματος
dim3 dimGrid1((M - 1) / BLOCK_SIZE_PER_DIM + 1, 1);
dim3 dimGrid2((M - 1) / BLOCK_SIZE_PER_DIM + 1, (N - 1) / BLOCK_SIZE_PER_DIM + 1);
dim3 dimGrid3((M - 1) / BLOCK_SIZE_PER_DIM + 1, 1);
// Ορισμός διαστάσεων block
dim3 dimBlock(BLOCK_SIZE_PER_DIM, BLOCK_SIZE_PER_DIM, 1);
//----------------------------------------------------------------------
gettimeofday(&cpu_start, NULL);
mean_kernel<<<dimGrid1, dimBlock>>>(data_d, mean_d);
hipDeviceSynchronize();
data_kernel<<<dimGrid2, dimBlock>>>(data_d, mean_d);
hipDeviceSynchronize();
symmat_kernel<<<dimGrid3, dimBlock>>>(symmat_d,data_d);
hipDeviceSynchronize();
hipMemcpy(symmat_h, symmat_d, (M+1)*(M+1)*sizeof(double), hipMemcpyDeviceToHost);
gettimeofday(&cpu_end, NULL);
fprintf(stdout, "GPU Runtime: %0.6lfs\n", ((cpu_end.tv_sec - cpu_start.tv_sec) * 1000000.0 + (cpu_end.tv_usec - cpu_start.tv_usec)) / 1000000.0);
printf("================================\n");
FILE *f = fopen("ask3_cuda_output.txt", "w+");
if (f == NULL)
{
printf("Error opening ask3_cuda_output.txt!\n");
exit(1);
}
for(int i = 1; i < (M+1); i++) {
for(int j = 1; j < (M+1); j++){
fprintf(f, "%f\n", symmat_h[i * (M+1) + j]);
}
}
if(f) { printf("Results saved in ask3_cuda_output.txt!\n"); }
fclose(f);
// Αποδέσμευση μνήμης στον host
free(data_h);
free(mean_h);
free(symmat_h);
// Αποδέσμευση μνήμης στον host
hipFree(data_d);
hipFree(mean_d);
hipFree(symmat_d);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <assert.h>
#include <unistd.h>
#include <sys/time.h>
/* Problem size */
#define M 1024
#define N 1024
#define FLOAT_N 3214212.01
void init_arrays(double* data)
{
int i, j;
for (i = 1; i < (M+1); i++) {
for (j = 1; j < (N+1); j++) {
data[i*(N+1) + j] = ((double) i*j) / M;
}
}
}
__global__ void mean_kernel(double* data, double* mean)
{
int j = blockIdx.x * blockDim.x + threadIdx.x + 1;
__shared__ double mean_shared;
if (j < (M+1))
{
mean_shared = 0.0;
int i;
for(i = 1; i < (N+1); i++)
{
mean_shared += data[i * (M+1) + j];
}
mean_shared /= FLOAT_N;
mean[j] = mean_shared;
}
}
__global__ void data_kernel(double* data, double* mean)
{
int j = blockIdx.x * blockDim.x + threadIdx.x + 1;
int i = blockIdx.y * blockDim.y + threadIdx.y + 1;
if ((i < (N+1)) && (j < (M+1)))
{
data[i * (M+1) + j] -= mean[j];
}
}
__global__ void symmat_kernel(double* symmat, double* data)
{
int j1 = blockIdx.x * blockDim.x + threadIdx.x + 1;
int i, j2;
__shared__ double symmat_shared;
if (j1 < (M+1))
{
for (j2 = j1; j2 < (M+1); j2++)
{
symmat_shared = 0.0;
for(i = 1; i < (N+1); i++)
{
symmat_shared += data[i * (M+1) + j1] * data[i * (M+1) + j2];
}
symmat[j1 * (M+1) + j2] = symmat_shared;
symmat[j2 * (M+1) + j1] = symmat[j1 * (M+1) + j2];
}
}
}
int main(int argc, char *argv[])
{
double *data_h, *data_d;
double *symmat_h, *symmat_d;
double *mean_h, *mean_d;
struct timeval cpu_start, cpu_end;
data_h = (double*)malloc((M+1)*(N+1)*sizeof(double));
mean_h = (double*)malloc((M+1)*sizeof(double));
symmat_h = (double*)malloc((M+1)*(M+1)*sizeof(double));
// Δέσμευση μνήμης στο device για τα διανύσματα
hipMalloc((void **) &data_d, (M+1)*(N+1)*sizeof(double));
hipMalloc((void **) &mean_d, (M+1)*sizeof(double));
hipMalloc((void **) &symmat_d, (M+1)*(M+1)*sizeof(double));
hipMemset(data_d, 0, (M+1)*(N+1)*sizeof(double));
// cudaMemset(symmat_d, 0, (M+1)*(M+1)*sizeof(double));
// cudaMemset(mean_d, 0, (M+1)*sizeof(double));
init_arrays(data_h);
// Αντιγραφή data στο device
hipMemcpy(data_d, data_h, (M+1)*(N+1)*sizeof(double), hipMemcpyHostToDevice);
//cudaMemcpy(symmat_d, symmat_h, (M+1)*(M+1)*sizeof(double), cudaMemcpyHostToDevice);
//cudaMemcpy(mean_d, mean_h, (M+1)*sizeof(double), cudaMemcpyHostToDevice);
//----------------------------------------------------------------------
// Κάθε block θα έχει διάσταση 16x16
unsigned int BLOCK_SIZE_PER_DIM = 16;
// Ορισμός διαστάσεων πλέγματος
dim3 dimGrid1((M - 1) / BLOCK_SIZE_PER_DIM + 1, 1);
dim3 dimGrid2((M - 1) / BLOCK_SIZE_PER_DIM + 1, (N - 1) / BLOCK_SIZE_PER_DIM + 1);
dim3 dimGrid3((M - 1) / BLOCK_SIZE_PER_DIM + 1, 1);
// Ορισμός διαστάσεων block
dim3 dimBlock(BLOCK_SIZE_PER_DIM, BLOCK_SIZE_PER_DIM, 1);
//----------------------------------------------------------------------
gettimeofday(&cpu_start, NULL);
mean_kernel<<<dimGrid1, dimBlock>>>(data_d, mean_d);
hipDeviceSynchronize();
data_kernel<<<dimGrid2, dimBlock>>>(data_d, mean_d);
hipDeviceSynchronize();
symmat_kernel<<<dimGrid3, dimBlock>>>(symmat_d,data_d);
hipDeviceSynchronize();
hipMemcpy(symmat_h, symmat_d, (M+1)*(M+1)*sizeof(double), hipMemcpyDeviceToHost);
gettimeofday(&cpu_end, NULL);
fprintf(stdout, "GPU Runtime: %0.6lfs\n", ((cpu_end.tv_sec - cpu_start.tv_sec) * 1000000.0 + (cpu_end.tv_usec - cpu_start.tv_usec)) / 1000000.0);
printf("================================\n");
FILE *f = fopen("ask3_cuda_output.txt", "w+");
if (f == NULL)
{
printf("Error opening ask3_cuda_output.txt!\n");
exit(1);
}
for(int i = 1; i < (M+1); i++) {
for(int j = 1; j < (M+1); j++){
fprintf(f, "%f\n", symmat_h[i * (M+1) + j]);
}
}
if(f) { printf("Results saved in ask3_cuda_output.txt!\n"); }
fclose(f);
// Αποδέσμευση μνήμης στον host
free(data_h);
free(mean_h);
free(symmat_h);
// Αποδέσμευση μνήμης στον host
hipFree(data_d);
hipFree(mean_d);
hipFree(symmat_d);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11mean_kernelPdS_
.globl _Z11mean_kernelPdS_
.p2align 8
.type _Z11mean_kernelPdS_,@function
_Z11mean_kernelPdS_:
s_load_b32 s2, s[0:1], 0x1c
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
s_mul_i32 s15, s15, s2
s_mov_b32 s2, exec_lo
v_add3_u32 v1, v0, s15, 1
v_cmpx_gt_i32_e32 0x401, v1
s_cbranch_execz .LBB0_4
s_load_b64 s[2:3], s[0:1], 0x0
v_mov_b32_e32 v2, 0
v_dual_mov_b32 v3, 0 :: v_dual_add_nc_u32 v0, s15, v0
s_movk_i32 s4, 0x402
.LBB0_2:
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_add_nc_u32_e32 v4, s4, v0
s_addk_i32 s4, 0x401
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_cmp_lg_u32 s4, 0x100802
v_ashrrev_i32_e32 v5, 31, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[4:5], 3, v[4:5]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v4, vcc_lo, s2, v4
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v5, vcc_lo
global_load_b64 v[4:5], v[4:5], off
s_waitcnt vmcnt(0)
v_add_f64 v[2:3], v[4:5], v[2:3]
s_cbranch_scc1 .LBB0_2
s_mov_b32 s3, 0x414885c2
s_mov_b32 s2, 0x147ae14
s_load_b64 s[0:1], s[0:1], 0x8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_scale_f64 v[4:5], null, s[2:3], s[2:3], v[2:3]
v_rcp_f64_e32 v[6:7], v[4:5]
s_waitcnt_depctr 0xfff
v_fma_f64 v[8:9], -v[4:5], v[6:7], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7]
v_fma_f64 v[8:9], -v[4:5], v[6:7], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7]
v_div_scale_f64 v[8:9], vcc_lo, v[2:3], s[2:3], v[2:3]
v_mul_f64 v[10:11], v[8:9], v[6:7]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[4:5], -v[4:5], v[10:11], v[8:9]
v_div_fmas_f64 v[4:5], v[4:5], v[6:7], v[10:11]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_div_fixup_f64 v[3:4], v[4:5], s[2:3], v[2:3]
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[0:1], 3, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b64 v[0:1], v[3:4], off
.LBB0_4:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11mean_kernelPdS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 12
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z11mean_kernelPdS_, .Lfunc_end0-_Z11mean_kernelPdS_
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z11data_kernelPdS_
.globl _Z11data_kernelPdS_
.p2align 8
.type _Z11data_kernelPdS_,@function
_Z11data_kernelPdS_:
s_load_b32 s2, s[0:1], 0x1c
v_and_b32_e32 v1, 0x3ff, v0
v_bfe_u32 v2, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_lshr_b32 s2, s2, 16
s_mul_i32 s14, s14, s3
s_mul_i32 s15, s15, s2
v_add3_u32 v0, v1, s14, 1
v_add3_u32 v2, v2, s15, 1
s_mov_b32 s2, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_max_i32_e32 v1, v0, v2
v_cmpx_gt_i32_e32 0x401, v1
s_cbranch_execz .LBB1_2
v_ashrrev_i32_e32 v1, 31, v0
s_load_b128 s[0:3], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[3:4], null, v2, 0x401, v[0:1]
v_lshlrev_b64 v[0:1], 3, v[0:1]
v_ashrrev_i32_e32 v4, 31, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[2:3], 3, v[3:4]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
v_add_co_u32 v2, vcc_lo, s0, v2
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
global_load_b64 v[0:1], v[0:1], off
global_load_b64 v[4:5], v[2:3], off
s_waitcnt vmcnt(0)
v_add_f64 v[0:1], v[4:5], -v[0:1]
global_store_b64 v[2:3], v[0:1], off
.LBB1_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11data_kernelPdS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z11data_kernelPdS_, .Lfunc_end1-_Z11data_kernelPdS_
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z13symmat_kernelPdS_
.globl _Z13symmat_kernelPdS_
.p2align 8
.type _Z13symmat_kernelPdS_,@function
_Z13symmat_kernelPdS_:
s_load_b32 s2, s[0:1], 0x1c
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
s_mul_i32 s15, s15, s2
s_mov_b32 s2, exec_lo
v_add3_u32 v1, v0, s15, 1
v_cmpx_gt_i32_e32 0x401, v1
s_cbranch_execz .LBB2_5
v_dual_mov_b32 v9, v1 :: v_dual_add_nc_u32 v0, s15, v0
s_load_b128 s[4:7], s[0:1], 0x0
v_lshl_add_u32 v8, v1, 10, v1
s_mov_b32 s1, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v2, 0x402, v0
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 3, v[2:3]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s6, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v3, vcc_lo
.LBB2_2:
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_dual_mov_b32 v4, 0 :: v_dual_mov_b32 v7, v3
v_dual_mov_b32 v5, 0 :: v_dual_mov_b32 v6, v2
s_movk_i32 s0, 0x402
.p2align 6
.LBB2_3:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_add_nc_u32_e32 v10, s0, v0
s_addk_i32 s0, 0x401
s_cmp_lg_u32 s0, 0x100802
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v11, 31, v10
v_lshlrev_b64 v[10:11], 3, v[10:11]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v10, vcc_lo, s6, v10
v_add_co_ci_u32_e32 v11, vcc_lo, s7, v11, vcc_lo
global_load_b64 v[12:13], v[6:7], off
global_load_b64 v[10:11], v[10:11], off
v_add_co_u32 v6, vcc_lo, v6, 0x2008
v_add_co_ci_u32_e32 v7, vcc_lo, 0, v7, vcc_lo
s_waitcnt vmcnt(0)
v_fma_f64 v[4:5], v[10:11], v[12:13], v[4:5]
s_cbranch_scc1 .LBB2_3
v_add_nc_u32_e32 v6, v9, v8
v_mad_u64_u32 v[10:11], null, v9, 0x401, v[1:2]
v_add_nc_u32_e32 v13, 1, v9
v_cmp_lt_i32_e32 vcc_lo, 0x3ff, v9
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_ashrrev_i32_e32 v7, 31, v6
s_or_b32 s1, vcc_lo, s1
v_ashrrev_i32_e32 v11, 31, v10
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[6:7], 3, v[6:7]
v_lshlrev_b64 v[9:10], 3, v[10:11]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v6, s0, s4, v6
v_add_co_ci_u32_e64 v7, s0, s5, v7, s0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v11, s0, s4, v9
v_add_co_ci_u32_e64 v12, s0, s5, v10, s0
v_add_co_u32 v2, s0, v2, 8
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v3, s0, 0, v3, s0
v_mov_b32_e32 v9, v13
s_clause 0x1
global_store_b64 v[6:7], v[4:5], off
global_store_b64 v[11:12], v[4:5], off
s_and_not1_b32 exec_lo, exec_lo, s1
s_cbranch_execnz .LBB2_2
.LBB2_5:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13symmat_kernelPdS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 14
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end2:
.size _Z13symmat_kernelPdS_, .Lfunc_end2-_Z13symmat_kernelPdS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11mean_kernelPdS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z11mean_kernelPdS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 12
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11data_kernelPdS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z11data_kernelPdS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13symmat_kernelPdS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z13symmat_kernelPdS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 14
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <assert.h>
#include <unistd.h>
#include <sys/time.h>
/* Problem size */
#define M 1024
#define N 1024
#define FLOAT_N 3214212.01
void init_arrays(double* data)
{
int i, j;
for (i = 1; i < (M+1); i++) {
for (j = 1; j < (N+1); j++) {
data[i*(N+1) + j] = ((double) i*j) / M;
}
}
}
__global__ void mean_kernel(double* data, double* mean)
{
int j = blockIdx.x * blockDim.x + threadIdx.x + 1;
__shared__ double mean_shared;
if (j < (M+1))
{
mean_shared = 0.0;
int i;
for(i = 1; i < (N+1); i++)
{
mean_shared += data[i * (M+1) + j];
}
mean_shared /= FLOAT_N;
mean[j] = mean_shared;
}
}
__global__ void data_kernel(double* data, double* mean)
{
int j = blockIdx.x * blockDim.x + threadIdx.x + 1;
int i = blockIdx.y * blockDim.y + threadIdx.y + 1;
if ((i < (N+1)) && (j < (M+1)))
{
data[i * (M+1) + j] -= mean[j];
}
}
__global__ void symmat_kernel(double* symmat, double* data)
{
int j1 = blockIdx.x * blockDim.x + threadIdx.x + 1;
int i, j2;
__shared__ double symmat_shared;
if (j1 < (M+1))
{
for (j2 = j1; j2 < (M+1); j2++)
{
symmat_shared = 0.0;
for(i = 1; i < (N+1); i++)
{
symmat_shared += data[i * (M+1) + j1] * data[i * (M+1) + j2];
}
symmat[j1 * (M+1) + j2] = symmat_shared;
symmat[j2 * (M+1) + j1] = symmat[j1 * (M+1) + j2];
}
}
}
int main(int argc, char *argv[])
{
double *data_h, *data_d;
double *symmat_h, *symmat_d;
double *mean_h, *mean_d;
struct timeval cpu_start, cpu_end;
data_h = (double*)malloc((M+1)*(N+1)*sizeof(double));
mean_h = (double*)malloc((M+1)*sizeof(double));
symmat_h = (double*)malloc((M+1)*(M+1)*sizeof(double));
// Δέσμευση μνήμης στο device για τα διανύσματα
hipMalloc((void **) &data_d, (M+1)*(N+1)*sizeof(double));
hipMalloc((void **) &mean_d, (M+1)*sizeof(double));
hipMalloc((void **) &symmat_d, (M+1)*(M+1)*sizeof(double));
hipMemset(data_d, 0, (M+1)*(N+1)*sizeof(double));
// cudaMemset(symmat_d, 0, (M+1)*(M+1)*sizeof(double));
// cudaMemset(mean_d, 0, (M+1)*sizeof(double));
init_arrays(data_h);
// Αντιγραφή data στο device
hipMemcpy(data_d, data_h, (M+1)*(N+1)*sizeof(double), hipMemcpyHostToDevice);
//cudaMemcpy(symmat_d, symmat_h, (M+1)*(M+1)*sizeof(double), cudaMemcpyHostToDevice);
//cudaMemcpy(mean_d, mean_h, (M+1)*sizeof(double), cudaMemcpyHostToDevice);
//----------------------------------------------------------------------
// Κάθε block θα έχει διάσταση 16x16
unsigned int BLOCK_SIZE_PER_DIM = 16;
// Ορισμός διαστάσεων πλέγματος
dim3 dimGrid1((M - 1) / BLOCK_SIZE_PER_DIM + 1, 1);
dim3 dimGrid2((M - 1) / BLOCK_SIZE_PER_DIM + 1, (N - 1) / BLOCK_SIZE_PER_DIM + 1);
dim3 dimGrid3((M - 1) / BLOCK_SIZE_PER_DIM + 1, 1);
// Ορισμός διαστάσεων block
dim3 dimBlock(BLOCK_SIZE_PER_DIM, BLOCK_SIZE_PER_DIM, 1);
//----------------------------------------------------------------------
gettimeofday(&cpu_start, NULL);
mean_kernel<<<dimGrid1, dimBlock>>>(data_d, mean_d);
hipDeviceSynchronize();
data_kernel<<<dimGrid2, dimBlock>>>(data_d, mean_d);
hipDeviceSynchronize();
symmat_kernel<<<dimGrid3, dimBlock>>>(symmat_d,data_d);
hipDeviceSynchronize();
hipMemcpy(symmat_h, symmat_d, (M+1)*(M+1)*sizeof(double), hipMemcpyDeviceToHost);
gettimeofday(&cpu_end, NULL);
fprintf(stdout, "GPU Runtime: %0.6lfs\n", ((cpu_end.tv_sec - cpu_start.tv_sec) * 1000000.0 + (cpu_end.tv_usec - cpu_start.tv_usec)) / 1000000.0);
printf("================================\n");
FILE *f = fopen("ask3_cuda_output.txt", "w+");
if (f == NULL)
{
printf("Error opening ask3_cuda_output.txt!\n");
exit(1);
}
for(int i = 1; i < (M+1); i++) {
for(int j = 1; j < (M+1); j++){
fprintf(f, "%f\n", symmat_h[i * (M+1) + j]);
}
}
if(f) { printf("Results saved in ask3_cuda_output.txt!\n"); }
fclose(f);
// Αποδέσμευση μνήμης στον host
free(data_h);
free(mean_h);
free(symmat_h);
// Αποδέσμευση μνήμης στον host
hipFree(data_d);
hipFree(mean_d);
hipFree(symmat_d);
return 0;
} | .text
.file "ask3_cuda.hip"
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z11init_arraysPd
.LCPI0_0:
.quad 0x3f50000000000000 # double 9.765625E-4
.text
.globl _Z11init_arraysPd
.p2align 4, 0x90
.type _Z11init_arraysPd,@function
_Z11init_arraysPd: # @_Z11init_arraysPd
.cfi_startproc
# %bb.0:
addq $8208, %rdi # imm = 0x2010
movl $1, %eax
movsd .LCPI0_0(%rip), %xmm0 # xmm0 = mem[0],zero
.p2align 4, 0x90
.LBB0_1: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB0_2 Depth 2
xorps %xmm1, %xmm1
cvtsi2sd %eax, %xmm1
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB0_2: # Parent Loop BB0_1 Depth=1
# => This Inner Loop Header: Depth=2
leaq 1(%rcx), %rdx
xorps %xmm2, %xmm2
cvtsi2sd %edx, %xmm2
mulsd %xmm1, %xmm2
mulsd %xmm0, %xmm2
movsd %xmm2, (%rdi,%rcx,8)
movq %rdx, %rcx
cmpq $1024, %rdx # imm = 0x400
jne .LBB0_2
# %bb.3: # in Loop: Header=BB0_1 Depth=1
incq %rax
addq $8200, %rdi # imm = 0x2008
cmpq $1025, %rax # imm = 0x401
jne .LBB0_1
# %bb.4:
retq
.Lfunc_end0:
.size _Z11init_arraysPd, .Lfunc_end0-_Z11init_arraysPd
.cfi_endproc
# -- End function
.globl _Z26__device_stub__mean_kernelPdS_ # -- Begin function _Z26__device_stub__mean_kernelPdS_
.p2align 4, 0x90
.type _Z26__device_stub__mean_kernelPdS_,@function
_Z26__device_stub__mean_kernelPdS_: # @_Z26__device_stub__mean_kernelPdS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z11mean_kernelPdS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end1:
.size _Z26__device_stub__mean_kernelPdS_, .Lfunc_end1-_Z26__device_stub__mean_kernelPdS_
.cfi_endproc
# -- End function
.globl _Z26__device_stub__data_kernelPdS_ # -- Begin function _Z26__device_stub__data_kernelPdS_
.p2align 4, 0x90
.type _Z26__device_stub__data_kernelPdS_,@function
_Z26__device_stub__data_kernelPdS_: # @_Z26__device_stub__data_kernelPdS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z11data_kernelPdS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end2:
.size _Z26__device_stub__data_kernelPdS_, .Lfunc_end2-_Z26__device_stub__data_kernelPdS_
.cfi_endproc
# -- End function
.globl _Z28__device_stub__symmat_kernelPdS_ # -- Begin function _Z28__device_stub__symmat_kernelPdS_
.p2align 4, 0x90
.type _Z28__device_stub__symmat_kernelPdS_,@function
_Z28__device_stub__symmat_kernelPdS_: # @_Z28__device_stub__symmat_kernelPdS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z13symmat_kernelPdS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end3:
.size _Z28__device_stub__symmat_kernelPdS_, .Lfunc_end3-_Z28__device_stub__symmat_kernelPdS_
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI4_0:
.quad 0x3f50000000000000 # double 9.765625E-4
.LCPI4_1:
.quad 0x412e848000000000 # double 1.0E+6
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $136, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $8405000, %edi # imm = 0x804008
callq malloc
movq %rax, %rbx
movl $8405000, %edi # imm = 0x804008
callq malloc
movq %rax, %r14
leaq 8(%rsp), %rdi
movl $8405000, %esi # imm = 0x804008
callq hipMalloc
leaq 104(%rsp), %rdi
movl $8200, %esi # imm = 0x2008
callq hipMalloc
leaq 112(%rsp), %rdi
movl $8405000, %esi # imm = 0x804008
callq hipMalloc
movq 8(%rsp), %rdi
movl $8405000, %edx # imm = 0x804008
xorl %esi, %esi
callq hipMemset
movq %rbx, %rax
addq $8208, %rax # imm = 0x2010
movl $1, %ecx
movsd .LCPI4_0(%rip), %xmm0 # xmm0 = mem[0],zero
.p2align 4, 0x90
.LBB4_1: # %.preheader.i
# =>This Loop Header: Depth=1
# Child Loop BB4_2 Depth 2
xorps %xmm1, %xmm1
cvtsi2sd %ecx, %xmm1
xorl %edx, %edx
.p2align 4, 0x90
.LBB4_2: # Parent Loop BB4_1 Depth=1
# => This Inner Loop Header: Depth=2
leaq 1(%rdx), %rsi
xorps %xmm2, %xmm2
cvtsi2sd %esi, %xmm2
mulsd %xmm1, %xmm2
mulsd %xmm0, %xmm2
movsd %xmm2, (%rax,%rdx,8)
movq %rsi, %rdx
cmpq $1024, %rsi # imm = 0x400
jne .LBB4_2
# %bb.3: # in Loop: Header=BB4_1 Depth=1
incq %rcx
addq $8200, %rax # imm = 0x2008
cmpq $1025, %rcx # imm = 0x401
jne .LBB4_1
# %bb.4: # %_Z11init_arraysPd.exit
movabsq $68719476752, %r15 # imm = 0x1000000010
movabsq $4294967360, %r12 # imm = 0x100000040
movq 8(%rsp), %rdi
movl $8405000, %edx # imm = 0x804008
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
leaq 120(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movq %r12, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_6
# %bb.5:
movq 8(%rsp), %rax
movq 104(%rsp), %rcx
movq %rax, 96(%rsp)
movq %rcx, 88(%rsp)
leaq 96(%rsp), %rax
movq %rax, 16(%rsp)
leaq 88(%rsp), %rax
movq %rax, 24(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z11mean_kernelPdS_, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_6:
callq hipDeviceSynchronize
movabsq $274877907008, %rdi # imm = 0x4000000040
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_8
# %bb.7:
movq 8(%rsp), %rax
movq 104(%rsp), %rcx
movq %rax, 96(%rsp)
movq %rcx, 88(%rsp)
leaq 96(%rsp), %rax
movq %rax, 16(%rsp)
leaq 88(%rsp), %rax
movq %rax, 24(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z11data_kernelPdS_, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_8:
callq hipDeviceSynchronize
movq %r12, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_10
# %bb.9:
movq 112(%rsp), %rax
movq 8(%rsp), %rcx
movq %rax, 96(%rsp)
movq %rcx, 88(%rsp)
leaq 96(%rsp), %rax
movq %rax, 16(%rsp)
leaq 88(%rsp), %rax
movq %rax, 24(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z13symmat_kernelPdS_, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_10:
callq hipDeviceSynchronize
movq 112(%rsp), %rsi
movl $8405000, %edx # imm = 0x804008
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
leaq 16(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movq stdout(%rip), %rdi
movq 16(%rsp), %rax
movq 24(%rsp), %rcx
subq 120(%rsp), %rax
cvtsi2sd %rax, %xmm1
movsd .LCPI4_1(%rip), %xmm2 # xmm2 = mem[0],zero
mulsd %xmm2, %xmm1
subq 128(%rsp), %rcx
cvtsi2sd %rcx, %xmm0
addsd %xmm1, %xmm0
divsd %xmm2, %xmm0
movl $.L.str, %esi
movb $1, %al
callq fprintf
movl $.Lstr, %edi
callq puts@PLT
movl $.L.str.2, %edi
movl $.L.str.3, %esi
callq fopen
testq %rax, %rax
je .LBB4_16
# %bb.11: # %.preheader.preheader
movq %rax, %r15
movq %r14, %r12
addq $8208, %r12 # imm = 0x2010
movl $1, %r13d
.p2align 4, 0x90
.LBB4_12: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB4_13 Depth 2
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB4_13: # Parent Loop BB4_12 Depth=1
# => This Inner Loop Header: Depth=2
movsd (%r12,%rbp,8), %xmm0 # xmm0 = mem[0],zero
movl $.L.str.5, %esi
movq %r15, %rdi
movb $1, %al
callq fprintf
incq %rbp
cmpq $1024, %rbp # imm = 0x400
jne .LBB4_13
# %bb.14: # in Loop: Header=BB4_12 Depth=1
incq %r13
addq $8200, %r12 # imm = 0x2008
cmpq $1025, %r13 # imm = 0x401
jne .LBB4_12
# %bb.15:
movl $.Lstr.1, %edi
callq puts@PLT
movq %r15, %rdi
callq fclose
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq 8(%rsp), %rdi
callq hipFree
movq 104(%rsp), %rdi
callq hipFree
movq 112(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $136, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB4_16:
.cfi_def_cfa_offset 192
movl $.Lstr.2, %edi
callq puts@PLT
movl $1, %edi
callq exit
.Lfunc_end4:
.size main, .Lfunc_end4-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11mean_kernelPdS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11data_kernelPdS_, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13symmat_kernelPdS_, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z11mean_kernelPdS_,@object # @_Z11mean_kernelPdS_
.section .rodata,"a",@progbits
.globl _Z11mean_kernelPdS_
.p2align 3, 0x0
_Z11mean_kernelPdS_:
.quad _Z26__device_stub__mean_kernelPdS_
.size _Z11mean_kernelPdS_, 8
.type _Z11data_kernelPdS_,@object # @_Z11data_kernelPdS_
.globl _Z11data_kernelPdS_
.p2align 3, 0x0
_Z11data_kernelPdS_:
.quad _Z26__device_stub__data_kernelPdS_
.size _Z11data_kernelPdS_, 8
.type _Z13symmat_kernelPdS_,@object # @_Z13symmat_kernelPdS_
.globl _Z13symmat_kernelPdS_
.p2align 3, 0x0
_Z13symmat_kernelPdS_:
.quad _Z28__device_stub__symmat_kernelPdS_
.size _Z13symmat_kernelPdS_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "GPU Runtime: %0.6lfs\n"
.size .L.str, 22
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "ask3_cuda_output.txt"
.size .L.str.2, 21
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "w+"
.size .L.str.3, 3
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "%f\n"
.size .L.str.5, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z11mean_kernelPdS_"
.size .L__unnamed_1, 20
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z11data_kernelPdS_"
.size .L__unnamed_2, 20
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z13symmat_kernelPdS_"
.size .L__unnamed_3, 22
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "================================"
.size .Lstr, 33
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "Results saved in ask3_cuda_output.txt!"
.size .Lstr.1, 39
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "Error opening ask3_cuda_output.txt!"
.size .Lstr.2, 36
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__mean_kernelPdS_
.addrsig_sym _Z26__device_stub__data_kernelPdS_
.addrsig_sym _Z28__device_stub__symmat_kernelPdS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11mean_kernelPdS_
.addrsig_sym _Z11data_kernelPdS_
.addrsig_sym _Z13symmat_kernelPdS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0010af47_00000000-6_ask3_cuda.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2074:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2074:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z11init_arraysPd
.type _Z11init_arraysPd, @function
_Z11init_arraysPd:
.LFB2070:
.cfi_startproc
endbr64
leaq 8200(%rdi), %rdx
movl $1, %ecx
movsd .LC0(%rip), %xmm2
.L4:
movl $1, %eax
pxor %xmm1, %xmm1
cvtsi2sdl %ecx, %xmm1
.L5:
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
mulsd %xmm1, %xmm0
mulsd %xmm2, %xmm0
movsd %xmm0, (%rdx,%rax,8)
addq $1, %rax
cmpq $1025, %rax
jne .L5
addl $1, %ecx
addq $8200, %rdx
cmpl $1025, %ecx
jne .L4
ret
.cfi_endproc
.LFE2070:
.size _Z11init_arraysPd, .-_Z11init_arraysPd
.globl _Z33__device_stub__Z11mean_kernelPdS_PdS_
.type _Z33__device_stub__Z11mean_kernelPdS_PdS_, @function
_Z33__device_stub__Z11mean_kernelPdS_PdS_:
.LFB2096:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L12
.L8:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L13
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L12:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z11mean_kernelPdS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L8
.L13:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2096:
.size _Z33__device_stub__Z11mean_kernelPdS_PdS_, .-_Z33__device_stub__Z11mean_kernelPdS_PdS_
.globl _Z11mean_kernelPdS_
.type _Z11mean_kernelPdS_, @function
_Z11mean_kernelPdS_:
.LFB2097:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z11mean_kernelPdS_PdS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2097:
.size _Z11mean_kernelPdS_, .-_Z11mean_kernelPdS_
.globl _Z33__device_stub__Z11data_kernelPdS_PdS_
.type _Z33__device_stub__Z11data_kernelPdS_PdS_, @function
_Z33__device_stub__Z11data_kernelPdS_PdS_:
.LFB2098:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L20
.L16:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L21
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L20:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z11data_kernelPdS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L16
.L21:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2098:
.size _Z33__device_stub__Z11data_kernelPdS_PdS_, .-_Z33__device_stub__Z11data_kernelPdS_PdS_
.globl _Z11data_kernelPdS_
.type _Z11data_kernelPdS_, @function
_Z11data_kernelPdS_:
.LFB2099:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z11data_kernelPdS_PdS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2099:
.size _Z11data_kernelPdS_, .-_Z11data_kernelPdS_
.globl _Z35__device_stub__Z13symmat_kernelPdS_PdS_
.type _Z35__device_stub__Z13symmat_kernelPdS_PdS_, @function
_Z35__device_stub__Z13symmat_kernelPdS_PdS_:
.LFB2100:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L28
.L24:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L29
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L28:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z13symmat_kernelPdS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L24
.L29:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2100:
.size _Z35__device_stub__Z13symmat_kernelPdS_PdS_, .-_Z35__device_stub__Z13symmat_kernelPdS_PdS_
.globl _Z13symmat_kernelPdS_
.type _Z13symmat_kernelPdS_, @function
_Z13symmat_kernelPdS_:
.LFB2101:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z13symmat_kernelPdS_PdS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2101:
.size _Z13symmat_kernelPdS_, .-_Z13symmat_kernelPdS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "GPU Runtime: %0.6lfs\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC3:
.string "================================\n"
.section .rodata.str1.1
.LC4:
.string "w+"
.LC5:
.string "ask3_cuda_output.txt"
.section .rodata.str1.8
.align 8
.LC6:
.string "Error opening ask3_cuda_output.txt!\n"
.section .rodata.str1.1
.LC7:
.string "%f\n"
.section .rodata.str1.8
.align 8
.LC8:
.string "Results saved in ask3_cuda_output.txt!\n"
.text
.globl main
.type main, @function
main:
.LFB2071:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $152, %rsp
.cfi_def_cfa_offset 208
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
movl $8405000, %edi
call malloc@PLT
movq %rax, %rbx
movq %rax, 8(%rsp)
movl $8405000, %edi
call malloc@PLT
movq %rax, %r15
leaq 24(%rsp), %rdi
movl $8405000, %esi
call cudaMalloc@PLT
leaq 40(%rsp), %rdi
movl $8200, %esi
call cudaMalloc@PLT
leaq 32(%rsp), %rdi
movl $8405000, %esi
call cudaMalloc@PLT
movl $8405000, %edx
movl $0, %esi
movq 24(%rsp), %rdi
call cudaMemset@PLT
movq %rbx, %rdi
call _Z11init_arraysPd
movl $1, %ecx
movl $8405000, %edx
movq %rbx, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl $64, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $64, 60(%rsp)
movl $64, 64(%rsp)
movl $1, 68(%rsp)
movl $64, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $16, 84(%rsp)
movl $16, 88(%rsp)
movl $1, 92(%rsp)
leaq 96(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
movl 92(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 84(%rsp), %rdx
movq 48(%rsp), %rdi
movl 56(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L43
.L33:
call cudaThreadSynchronize@PLT
movl 92(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 84(%rsp), %rdx
movq 60(%rsp), %rdi
movl 68(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L44
.L34:
call cudaThreadSynchronize@PLT
movl 92(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 84(%rsp), %rdx
movq 72(%rsp), %rdi
movl 80(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L45
.L35:
call cudaThreadSynchronize@PLT
movl $2, %ecx
movl $8405000, %edx
movq 32(%rsp), %rsi
movq %r15, %rdi
call cudaMemcpy@PLT
leaq 112(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
movq 112(%rsp), %rax
subq 96(%rsp), %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
movsd .LC1(%rip), %xmm1
mulsd %xmm1, %xmm0
movq 120(%rsp), %rax
subq 104(%rsp), %rax
pxor %xmm2, %xmm2
cvtsi2sdq %rax, %xmm2
addsd %xmm2, %xmm0
divsd %xmm1, %xmm0
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $1, %eax
call __fprintf_chk@PLT
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC4(%rip), %rsi
leaq .LC5(%rip), %rdi
call fopen@PLT
movq %rax, %r12
testq %rax, %rax
je .L36
leaq 16400(%r15), %rbp
leaq 8413200(%r15), %r14
leaq .LC7(%rip), %r13
.L37:
leaq -8192(%rbp), %rbx
.L38:
movsd (%rbx), %xmm0
movq %r13, %rdx
movl $2, %esi
movq %r12, %rdi
movl $1, %eax
call __fprintf_chk@PLT
addq $8, %rbx
cmpq %rbp, %rbx
jne .L38
addq $8200, %rbp
cmpq %r14, %rbp
jne .L37
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %r12, %rdi
call fclose@PLT
movq 8(%rsp), %rdi
call free@PLT
movq %r15, %rdi
call free@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L46
movl $0, %eax
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L43:
.cfi_restore_state
movq 40(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z33__device_stub__Z11mean_kernelPdS_PdS_
jmp .L33
.L44:
movq 40(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z33__device_stub__Z11data_kernelPdS_PdS_
jmp .L34
.L45:
movq 24(%rsp), %rsi
movq 32(%rsp), %rdi
call _Z35__device_stub__Z13symmat_kernelPdS_PdS_
jmp .L35
.L36:
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L46:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2071:
.size main, .-main
.section .rodata.str1.1
.LC9:
.string "_Z13symmat_kernelPdS_"
.LC10:
.string "_Z11data_kernelPdS_"
.LC11:
.string "_Z11mean_kernelPdS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2103:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _Z13symmat_kernelPdS_(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC10(%rip), %rdx
movq %rdx, %rcx
leaq _Z11data_kernelPdS_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC11(%rip), %rdx
movq %rdx, %rcx
leaq _Z11mean_kernelPdS_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2103:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long 0
.long 1062207488
.align 8
.LC1:
.long 0
.long 1093567616
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "ask3_cuda.hip"
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z11init_arraysPd
.LCPI0_0:
.quad 0x3f50000000000000 # double 9.765625E-4
.text
.globl _Z11init_arraysPd
.p2align 4, 0x90
.type _Z11init_arraysPd,@function
_Z11init_arraysPd: # @_Z11init_arraysPd
.cfi_startproc
# %bb.0:
addq $8208, %rdi # imm = 0x2010
movl $1, %eax
movsd .LCPI0_0(%rip), %xmm0 # xmm0 = mem[0],zero
.p2align 4, 0x90
.LBB0_1: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB0_2 Depth 2
xorps %xmm1, %xmm1
cvtsi2sd %eax, %xmm1
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB0_2: # Parent Loop BB0_1 Depth=1
# => This Inner Loop Header: Depth=2
leaq 1(%rcx), %rdx
xorps %xmm2, %xmm2
cvtsi2sd %edx, %xmm2
mulsd %xmm1, %xmm2
mulsd %xmm0, %xmm2
movsd %xmm2, (%rdi,%rcx,8)
movq %rdx, %rcx
cmpq $1024, %rdx # imm = 0x400
jne .LBB0_2
# %bb.3: # in Loop: Header=BB0_1 Depth=1
incq %rax
addq $8200, %rdi # imm = 0x2008
cmpq $1025, %rax # imm = 0x401
jne .LBB0_1
# %bb.4:
retq
.Lfunc_end0:
.size _Z11init_arraysPd, .Lfunc_end0-_Z11init_arraysPd
.cfi_endproc
# -- End function
.globl _Z26__device_stub__mean_kernelPdS_ # -- Begin function _Z26__device_stub__mean_kernelPdS_
.p2align 4, 0x90
.type _Z26__device_stub__mean_kernelPdS_,@function
_Z26__device_stub__mean_kernelPdS_: # @_Z26__device_stub__mean_kernelPdS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z11mean_kernelPdS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end1:
.size _Z26__device_stub__mean_kernelPdS_, .Lfunc_end1-_Z26__device_stub__mean_kernelPdS_
.cfi_endproc
# -- End function
.globl _Z26__device_stub__data_kernelPdS_ # -- Begin function _Z26__device_stub__data_kernelPdS_
.p2align 4, 0x90
.type _Z26__device_stub__data_kernelPdS_,@function
_Z26__device_stub__data_kernelPdS_: # @_Z26__device_stub__data_kernelPdS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z11data_kernelPdS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end2:
.size _Z26__device_stub__data_kernelPdS_, .Lfunc_end2-_Z26__device_stub__data_kernelPdS_
.cfi_endproc
# -- End function
.globl _Z28__device_stub__symmat_kernelPdS_ # -- Begin function _Z28__device_stub__symmat_kernelPdS_
.p2align 4, 0x90
.type _Z28__device_stub__symmat_kernelPdS_,@function
_Z28__device_stub__symmat_kernelPdS_: # @_Z28__device_stub__symmat_kernelPdS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z13symmat_kernelPdS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end3:
.size _Z28__device_stub__symmat_kernelPdS_, .Lfunc_end3-_Z28__device_stub__symmat_kernelPdS_
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI4_0:
.quad 0x3f50000000000000 # double 9.765625E-4
.LCPI4_1:
.quad 0x412e848000000000 # double 1.0E+6
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $136, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $8405000, %edi # imm = 0x804008
callq malloc
movq %rax, %rbx
movl $8405000, %edi # imm = 0x804008
callq malloc
movq %rax, %r14
leaq 8(%rsp), %rdi
movl $8405000, %esi # imm = 0x804008
callq hipMalloc
leaq 104(%rsp), %rdi
movl $8200, %esi # imm = 0x2008
callq hipMalloc
leaq 112(%rsp), %rdi
movl $8405000, %esi # imm = 0x804008
callq hipMalloc
movq 8(%rsp), %rdi
movl $8405000, %edx # imm = 0x804008
xorl %esi, %esi
callq hipMemset
movq %rbx, %rax
addq $8208, %rax # imm = 0x2010
movl $1, %ecx
movsd .LCPI4_0(%rip), %xmm0 # xmm0 = mem[0],zero
.p2align 4, 0x90
.LBB4_1: # %.preheader.i
# =>This Loop Header: Depth=1
# Child Loop BB4_2 Depth 2
xorps %xmm1, %xmm1
cvtsi2sd %ecx, %xmm1
xorl %edx, %edx
.p2align 4, 0x90
.LBB4_2: # Parent Loop BB4_1 Depth=1
# => This Inner Loop Header: Depth=2
leaq 1(%rdx), %rsi
xorps %xmm2, %xmm2
cvtsi2sd %esi, %xmm2
mulsd %xmm1, %xmm2
mulsd %xmm0, %xmm2
movsd %xmm2, (%rax,%rdx,8)
movq %rsi, %rdx
cmpq $1024, %rsi # imm = 0x400
jne .LBB4_2
# %bb.3: # in Loop: Header=BB4_1 Depth=1
incq %rcx
addq $8200, %rax # imm = 0x2008
cmpq $1025, %rcx # imm = 0x401
jne .LBB4_1
# %bb.4: # %_Z11init_arraysPd.exit
movabsq $68719476752, %r15 # imm = 0x1000000010
movabsq $4294967360, %r12 # imm = 0x100000040
movq 8(%rsp), %rdi
movl $8405000, %edx # imm = 0x804008
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
leaq 120(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movq %r12, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_6
# %bb.5:
movq 8(%rsp), %rax
movq 104(%rsp), %rcx
movq %rax, 96(%rsp)
movq %rcx, 88(%rsp)
leaq 96(%rsp), %rax
movq %rax, 16(%rsp)
leaq 88(%rsp), %rax
movq %rax, 24(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z11mean_kernelPdS_, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_6:
callq hipDeviceSynchronize
movabsq $274877907008, %rdi # imm = 0x4000000040
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_8
# %bb.7:
movq 8(%rsp), %rax
movq 104(%rsp), %rcx
movq %rax, 96(%rsp)
movq %rcx, 88(%rsp)
leaq 96(%rsp), %rax
movq %rax, 16(%rsp)
leaq 88(%rsp), %rax
movq %rax, 24(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z11data_kernelPdS_, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_8:
callq hipDeviceSynchronize
movq %r12, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_10
# %bb.9:
movq 112(%rsp), %rax
movq 8(%rsp), %rcx
movq %rax, 96(%rsp)
movq %rcx, 88(%rsp)
leaq 96(%rsp), %rax
movq %rax, 16(%rsp)
leaq 88(%rsp), %rax
movq %rax, 24(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z13symmat_kernelPdS_, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_10:
callq hipDeviceSynchronize
movq 112(%rsp), %rsi
movl $8405000, %edx # imm = 0x804008
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
leaq 16(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movq stdout(%rip), %rdi
movq 16(%rsp), %rax
movq 24(%rsp), %rcx
subq 120(%rsp), %rax
cvtsi2sd %rax, %xmm1
movsd .LCPI4_1(%rip), %xmm2 # xmm2 = mem[0],zero
mulsd %xmm2, %xmm1
subq 128(%rsp), %rcx
cvtsi2sd %rcx, %xmm0
addsd %xmm1, %xmm0
divsd %xmm2, %xmm0
movl $.L.str, %esi
movb $1, %al
callq fprintf
movl $.Lstr, %edi
callq puts@PLT
movl $.L.str.2, %edi
movl $.L.str.3, %esi
callq fopen
testq %rax, %rax
je .LBB4_16
# %bb.11: # %.preheader.preheader
movq %rax, %r15
movq %r14, %r12
addq $8208, %r12 # imm = 0x2010
movl $1, %r13d
.p2align 4, 0x90
.LBB4_12: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB4_13 Depth 2
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB4_13: # Parent Loop BB4_12 Depth=1
# => This Inner Loop Header: Depth=2
movsd (%r12,%rbp,8), %xmm0 # xmm0 = mem[0],zero
movl $.L.str.5, %esi
movq %r15, %rdi
movb $1, %al
callq fprintf
incq %rbp
cmpq $1024, %rbp # imm = 0x400
jne .LBB4_13
# %bb.14: # in Loop: Header=BB4_12 Depth=1
incq %r13
addq $8200, %r12 # imm = 0x2008
cmpq $1025, %r13 # imm = 0x401
jne .LBB4_12
# %bb.15:
movl $.Lstr.1, %edi
callq puts@PLT
movq %r15, %rdi
callq fclose
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq 8(%rsp), %rdi
callq hipFree
movq 104(%rsp), %rdi
callq hipFree
movq 112(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $136, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB4_16:
.cfi_def_cfa_offset 192
movl $.Lstr.2, %edi
callq puts@PLT
movl $1, %edi
callq exit
.Lfunc_end4:
.size main, .Lfunc_end4-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11mean_kernelPdS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11data_kernelPdS_, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13symmat_kernelPdS_, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z11mean_kernelPdS_,@object # @_Z11mean_kernelPdS_
.section .rodata,"a",@progbits
.globl _Z11mean_kernelPdS_
.p2align 3, 0x0
_Z11mean_kernelPdS_:
.quad _Z26__device_stub__mean_kernelPdS_
.size _Z11mean_kernelPdS_, 8
.type _Z11data_kernelPdS_,@object # @_Z11data_kernelPdS_
.globl _Z11data_kernelPdS_
.p2align 3, 0x0
_Z11data_kernelPdS_:
.quad _Z26__device_stub__data_kernelPdS_
.size _Z11data_kernelPdS_, 8
.type _Z13symmat_kernelPdS_,@object # @_Z13symmat_kernelPdS_
.globl _Z13symmat_kernelPdS_
.p2align 3, 0x0
_Z13symmat_kernelPdS_:
.quad _Z28__device_stub__symmat_kernelPdS_
.size _Z13symmat_kernelPdS_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "GPU Runtime: %0.6lfs\n"
.size .L.str, 22
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "ask3_cuda_output.txt"
.size .L.str.2, 21
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "w+"
.size .L.str.3, 3
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "%f\n"
.size .L.str.5, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z11mean_kernelPdS_"
.size .L__unnamed_1, 20
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z11data_kernelPdS_"
.size .L__unnamed_2, 20
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z13symmat_kernelPdS_"
.size .L__unnamed_3, 22
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "================================"
.size .Lstr, 33
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "Results saved in ask3_cuda_output.txt!"
.size .Lstr.1, 39
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "Error opening ask3_cuda_output.txt!"
.size .Lstr.2, 36
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__mean_kernelPdS_
.addrsig_sym _Z26__device_stub__data_kernelPdS_
.addrsig_sym _Z28__device_stub__symmat_kernelPdS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11mean_kernelPdS_
.addrsig_sym _Z11data_kernelPdS_
.addrsig_sym _Z13symmat_kernelPdS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <cstdio>
#include <cstdlib>
#include <cuda_runtime.h>
#include <time.h>
#define random(a, b) (rand() % (b - a) + a)
void FillMatrix(float *matrix, int row, int col);
void PrintMatrix(float *A, float *B, float *C, int m, int n, int k);
__global__ void MatrixMulCUDA(const float *A, const float *B, float *C, int m, int n, int k, int ThreadBlockSize)
{
// 计算元素的行
const int row = blockIdx.x;
// 计算元素的列
const int col = blockIdx.y * ThreadBlockSize + threadIdx.x;
float temp = 0;
if (row < m && col < k)
{
for (int i = 0; i < n; ++i)
temp += A[row * n + i] * B[i * k + col];
C[row * k + col] = temp;
}
}
int main(int argc, char **argv)
{
if (argc != 5)
{
printf("Wrong Input!\n");
return 1;
}
int m = atoi(argv[1]);
int n = atoi(argv[2]);
int k = atoi(argv[3]);
int ThreadBlockSize = atoi(argv[4]);
float *A, *B, *C;
A = new float[m * n];
B = new float[n * k];
C = new float[m * k];
FillMatrix(A, m, n);
FillMatrix(B, n, k);
float *cuda_A, *cuda_B, *cuda_C;
// 使用cuda内置API计时
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaEventRecord(start, 0);
// 申请空间
cudaMalloc((void **)&cuda_A, sizeof(float) * m * n);
cudaMalloc((void **)&cuda_B, sizeof(float) * n * k);
cudaMalloc((void **)&cuda_C, sizeof(float) * m * k);
// 将A、B矩阵从CPU转移到GPU
cudaMemcpy(cuda_A, A, sizeof(float) * m * n, cudaMemcpyHostToDevice);
cudaMemcpy(cuda_B, B, sizeof(float) * n * k, cudaMemcpyHostToDevice);
// 定义的结构网格
dim3 grid(m, k / ThreadBlockSize);
// 矩阵乘法
MatrixMulCUDA<<<grid, ThreadBlockSize>>>(cuda_A, cuda_B, cuda_C, m, n, k, ThreadBlockSize);
// 将结果C矩阵从GPU转移回CPU
cudaMemcpy(C, cuda_C, sizeof(float) * m * k, cudaMemcpyDeviceToHost);
cudaFree(cuda_A);
cudaFree(cuda_B);
cudaFree(cuda_C);
// 计时
cudaEventRecord(stop, 0);
cudaEventSynchronize(stop);
float elapsedTime;
cudaEventElapsedTime(&elapsedTime, start, stop);
printf("Matrix Size is %d\nThreadBlockSize is %d\n", m,ThreadBlockSize);
printf("Calculation time is %.10f ms\n", elapsedTime);
// PrintMatrix(A, B, C, m, n, k);
delete[] A;
delete[] C;
delete[] B;
return 0;
}
void FillMatrix(float *matrix, int row, int col)
{
for (int i = 0; i < row; ++i)
for (int j = 0; j < col; ++j)
matrix[i * col + j] = random(0, 9);
}
void PrintMatrix(float *A, float *B, float *C, int m, int n, int k)
{
printf("Matrix A:\n");
for (int i = 0; i < m; ++i)
{
for (int j = 0; j < n; ++j)
printf("%f ", A[i * n + j]);
printf("\n");
}
printf("Matrix B:\n");
for (int i = 0; i < n; ++i)
{
for (int j = 0; j < k; ++j)
printf("%f ", B[i * k + j]);
printf("\n");
}
printf("Matrix C:\n");
for (int i = 0; i < m; ++i)
{
for (int j = 0; j < k; ++j)
printf("%f ", C[i * k + j]);
printf("\n");
}
} | code for sm_80
Function : _Z13MatrixMulCUDAPKfS0_Pfiiii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e280000002600 */
/*0020*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e280000002100 */
/*0030*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e620000002500 */
/*0040*/ IMAD R3, R3, c[0x0][0x184], R2 ; /* 0x0000610003037a24 */
/* 0x001fca00078e0202 */
/*0050*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x180], PT ; /* 0x0000600003007a0c */
/* 0x000fc80003f06270 */
/*0060*/ ISETP.GE.OR P0, PT, R0, c[0x0][0x178], P0 ; /* 0x00005e0000007a0c */
/* 0x002fda0000706670 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ MOV R4, c[0x0][0x17c] ; /* 0x00005f0000047a02 */
/* 0x000fe20000000f00 */
/*0090*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00a0*/ HFMA2.MMA R19, -RZ, RZ, 0, 0 ; /* 0x00000000ff137435 */
/* 0x000fe400000001ff */
/*00b0*/ ISETP.GE.AND P0, PT, R4, 0x1, PT ; /* 0x000000010400780c */
/* 0x000fda0003f06270 */
/*00c0*/ @!P0 BRA 0xc10 ; /* 0x00000b4000008947 */
/* 0x000fea0003800000 */
/*00d0*/ IADD3 R2, R4.reuse, -0x1, RZ ; /* 0xffffffff04027810 */
/* 0x040fe40007ffe0ff */
/*00e0*/ LOP3.LUT R4, R4, 0x3, RZ, 0xc0, !PT ; /* 0x0000000304047812 */
/* 0x000fe400078ec0ff */
/*00f0*/ ISETP.GE.U32.AND P0, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fe40003f06070 */
/*0100*/ MOV R19, RZ ; /* 0x000000ff00137202 */
/* 0x000fe40000000f00 */
/*0110*/ MOV R2, RZ ; /* 0x000000ff00027202 */
/* 0x000fd20000000f00 */
/*0120*/ @!P0 BRA 0xb00 ; /* 0x000009d000008947 */
/* 0x000fea0003800000 */
/*0130*/ IADD3 R6, -R4, c[0x0][0x17c], RZ ; /* 0x00005f0004067a10 */
/* 0x000fe20007ffe1ff */
/*0140*/ HFMA2.MMA R20, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff147435 */
/* 0x000fe200000001ff */
/*0150*/ IMAD R7, R0, c[0x0][0x17c], RZ ; /* 0x00005f0000077a24 */
/* 0x000fe200078e02ff */
/*0160*/ HFMA2.MMA R2, -RZ, RZ, 0, 0 ; /* 0x00000000ff027435 */
/* 0x000fe200000001ff */
/*0170*/ ISETP.GT.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe40003f04270 */
/*0180*/ MOV R19, RZ ; /* 0x000000ff00137202 */
/* 0x000fe40000000f00 */
/*0190*/ MOV R8, c[0x0][0x160] ; /* 0x0000580000087a02 */
/* 0x000fe40000000f00 */
/*01a0*/ MOV R5, c[0x0][0x164] ; /* 0x0000590000057a02 */
/* 0x000fe20000000f00 */
/*01b0*/ IMAD.WIDE R20, R3, R20, c[0x0][0x168] ; /* 0x00005a0003147625 */
/* 0x000fcc00078e0214 */
/*01c0*/ @!P0 BRA 0x960 ; /* 0x0000079000008947 */
/* 0x000fea0003800000 */
/*01d0*/ ISETP.GT.AND P1, PT, R6, 0xc, PT ; /* 0x0000000c0600780c */
/* 0x000fe40003f24270 */
/*01e0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*01f0*/ @!P1 BRA 0x6a0 ; /* 0x000004a000009947 */
/* 0x000fea0003800000 */
/*0200*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0210*/ MOV R9, R5 ; /* 0x0000000500097202 */
/* 0x000fe20000000f00 */
/*0220*/ LDG.E R18, [R20.64] ; /* 0x0000000414127981 */
/* 0x0000a8000c1e1900 */
/*0230*/ IMAD.WIDE R12, R7, 0x4, R8 ; /* 0x00000004070c7825 */
/* 0x000fe200078e0208 */
/*0240*/ MOV R9, c[0x0][0x180] ; /* 0x0000600000097a02 */
/* 0x000fc80000000f00 */
/*0250*/ LDG.E R28, [R12.64] ; /* 0x000000040c1c7981 */
/* 0x000ea2000c1e1900 */
/*0260*/ IMAD.WIDE R16, R9, 0x4, R20 ; /* 0x0000000409107825 */
/* 0x000fc600078e0214 */
/*0270*/ LDG.E R10, [R12.64+0x4] ; /* 0x000004040c0a7981 */
/* 0x000ee8000c1e1900 */
/*0280*/ LDG.E R11, [R16.64] ; /* 0x00000004100b7981 */
/* 0x0002e2000c1e1900 */
/*0290*/ IMAD.WIDE R22, R9, 0x4, R16 ; /* 0x0000000409167825 */
/* 0x000fc600078e0210 */
/*02a0*/ LDG.E R24, [R12.64+0x8] ; /* 0x000008040c187981 */
/* 0x000f28000c1e1900 */
/*02b0*/ LDG.E R25, [R22.64] ; /* 0x0000000416197981 */
/* 0x000b28000c1e1900 */
/*02c0*/ LDG.E R14, [R12.64+0xc] ; /* 0x00000c040c0e7981 */
/* 0x000f28000c1e1900 */
/*02d0*/ LDG.E R26, [R12.64+0x10] ; /* 0x000010040c1a7981 */
/* 0x000f22000c1e1900 */
/*02e0*/ IMAD.WIDE R22, R9, 0x4, R22 ; /* 0x0000000409167825 */
/* 0x020fca00078e0216 */
/*02f0*/ LDG.E R15, [R22.64] ; /* 0x00000004160f7981 */
/* 0x000b22000c1e1900 */
/*0300*/ IMAD.WIDE R20, R9, 0x4, R22 ; /* 0x0000000409147825 */
/* 0x001fca00078e0216 */
/*0310*/ LDG.E R27, [R20.64] ; /* 0x00000004141b7981 */
/* 0x000122000c1e1900 */
/*0320*/ IMAD.WIDE R16, R9, 0x4, R20 ; /* 0x0000000409107825 */
/* 0x002fc600078e0214 */
/*0330*/ LDG.E R21, [R12.64+0x1c] ; /* 0x00001c040c157981 */
/* 0x001f22000c1e1900 */
/*0340*/ FFMA R28, R18, R28, R19 ; /* 0x0000001c121c7223 */
/* 0x004fc60000000013 */
/*0350*/ LDG.E R18, [R12.64+0x14] ; /* 0x000014040c127981 */
/* 0x000ea8000c1e1900 */
/*0360*/ LDG.E R19, [R16.64] ; /* 0x0000000410137981 */
/* 0x0000a2000c1e1900 */
/*0370*/ FFMA R28, R11, R10, R28 ; /* 0x0000000a0b1c7223 */
/* 0x008fc6000000001c */
/*0380*/ LDG.E R10, [R12.64+0x18] ; /* 0x000018040c0a7981 */
/* 0x000ee2000c1e1900 */
/*0390*/ IMAD.WIDE R16, R9, 0x4, R16 ; /* 0x0000000409107825 */
/* 0x001fca00078e0210 */
/*03a0*/ LDG.E R11, [R16.64] ; /* 0x00000004100b7981 */
/* 0x0008e2000c1e1900 */
/*03b0*/ IMAD.WIDE R22, R9, 0x4, R16 ; /* 0x0000000409167825 */
/* 0x020fca00078e0210 */
/*03c0*/ LDG.E R20, [R22.64] ; /* 0x0000000416147981 */
/* 0x000162000c1e1900 */
/*03d0*/ FFMA R16, R25, R24, R28 ; /* 0x0000001819107223 */
/* 0x010fe4000000001c */
/*03e0*/ IMAD.WIDE R24, R9, 0x4, R22 ; /* 0x0000000409187825 */
/* 0x000fe200078e0216 */
/*03f0*/ LDG.E R28, [R12.64+0x20] ; /* 0x000020040c1c7981 */
/* 0x000f28000c1e1900 */
/*0400*/ LDG.E R29, [R24.64] ; /* 0x00000004181d7981 */
/* 0x000b22000c1e1900 */
/*0410*/ FFMA R16, R15, R14, R16 ; /* 0x0000000e0f107223 */
/* 0x000fe40000000010 */
/*0420*/ IMAD.WIDE R14, R9, 0x4, R24 ; /* 0x00000004090e7825 */
/* 0x000fe200078e0218 */
/*0430*/ LDG.E R23, [R12.64+0x24] ; /* 0x000024040c177981 */
/* 0x001f26000c1e1900 */
/*0440*/ FFMA R26, R27, R26, R16 ; /* 0x0000001a1b1a7223 */
/* 0x000fc40000000010 */
/*0450*/ IMAD.WIDE R16, R9, 0x4, R14 ; /* 0x0000000409107825 */
/* 0x000fe200078e020e */
/*0460*/ LDG.E R27, [R12.64+0x28] ; /* 0x000028040c1b7981 */
/* 0x000f28000c1e1900 */
/*0470*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000128000c1e1900 */
/*0480*/ LDG.E R22, [R16.64] ; /* 0x0000000410167981 */
/* 0x000328000c1e1900 */
/*0490*/ LDG.E R15, [R12.64+0x30] ; /* 0x000030040c0f7981 */
/* 0x001f22000c1e1900 */
/*04a0*/ FFMA R26, R19, R18, R26 ; /* 0x00000012131a7223 */
/* 0x004fc4000000001a */
/*04b0*/ IMAD.WIDE R18, R9, 0x4, R16 ; /* 0x0000000409127825 */
/* 0x000fc800078e0210 */
/*04c0*/ FFMA R26, R11, R10, R26 ; /* 0x0000000a0b1a7223 */
/* 0x008fe4000000001a */
/*04d0*/ IMAD.WIDE R10, R9.reuse, 0x4, R18 ; /* 0x00000004090a7825 */
/* 0x040fe400078e0212 */
/*04e0*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x0000a4000c1e1900 */
/*04f0*/ FFMA R24, R20, R21, R26 ; /* 0x0000001514187223 */
/* 0x020fe4000000001a */
/*0500*/ IMAD.WIDE R20, R9, 0x4, R10 ; /* 0x0000000409147825 */
/* 0x000fe200078e020a */
/*0510*/ LDG.E R26, [R12.64+0x2c] ; /* 0x00002c040c1a7981 */
/* 0x000ea8000c1e1900 */
/*0520*/ LDG.E R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x000762000c1e1900 */
/*0530*/ FFMA R28, R29, R28, R24 ; /* 0x0000001c1d1c7223 */
/* 0x010fc40000000018 */
/*0540*/ IMAD.WIDE R24, R9.reuse, 0x4, R20 ; /* 0x0000000409187825 */
/* 0x040fe400078e0214 */
/*0550*/ LDG.E R20, [R20.64] ; /* 0x0000000414147981 */
/* 0x000968000c1e1900 */
/*0560*/ LDG.E R11, [R12.64+0x34] ; /* 0x000034040c0b7981 */
/* 0x008ee2000c1e1900 */
/*0570*/ IMAD.WIDE R16, R9, 0x4, R24 ; /* 0x0000000409107825 */
/* 0x002fc600078e0218 */
/*0580*/ LDG.E R29, [R24.64] ; /* 0x00000004181d7981 */
/* 0x0002e8000c1e1900 */
/*0590*/ LDG.E R21, [R12.64+0x38] ; /* 0x000038040c157981 */
/* 0x010f28000c1e1900 */
/*05a0*/ LDG.E R19, [R16.64] ; /* 0x0000000410137981 */
/* 0x001f28000c1e1900 */
/*05b0*/ LDG.E R24, [R12.64+0x3c] ; /* 0x00003c040c187981 */
/* 0x002f22000c1e1900 */
/*05c0*/ FFMA R14, R14, R23, R28 ; /* 0x000000170e0e7223 */
/* 0x000fe2000000001c */
/*05d0*/ IADD3 R6, R6, -0x10, RZ ; /* 0xfffffff006067810 */
/* 0x000fc60007ffe0ff */
/*05e0*/ FFMA R27, R22, R27, R14 ; /* 0x0000001b161b7223 */
/* 0x000fe2000000000e */
/*05f0*/ ISETP.GT.AND P1, PT, R6, 0xc, PT ; /* 0x0000000c0600780c */
/* 0x000fe40003f24270 */
/*0600*/ IADD3 R8, P2, R8, 0x40, RZ ; /* 0x0000004008087810 */
/* 0x000fe40007f5e0ff */
/*0610*/ IADD3 R2, R2, 0x10, RZ ; /* 0x0000001002027810 */
/* 0x000fe40007ffe0ff */
/*0620*/ IADD3.X R5, RZ, R5, RZ, P2, !PT ; /* 0x00000005ff057210 */
/* 0x000fe200017fe4ff */
/*0630*/ FFMA R18, R18, R26, R27 ; /* 0x0000001a12127223 */
/* 0x004fc8000000001b */
/*0640*/ FFMA R10, R10, R15, R18 ; /* 0x0000000f0a0a7223 */
/* 0x020fc80000000012 */
/*0650*/ FFMA R10, R20, R11, R10 ; /* 0x0000000b140a7223 */
/* 0x008fc8000000000a */
/*0660*/ FFMA R10, R29, R21, R10 ; /* 0x000000151d0a7223 */
/* 0x010fe4000000000a */
/*0670*/ IMAD.WIDE R20, R9, 0x4, R16 ; /* 0x0000000409147825 */
/* 0x000fc800078e0210 */
/*0680*/ FFMA R19, R19, R24, R10 ; /* 0x0000001813137223 */
/* 0x000fe2000000000a */
/*0690*/ @P1 BRA 0x210 ; /* 0xfffffb7000001947 */
/* 0x000fea000383ffff */
/*06a0*/ ISETP.GT.AND P1, PT, R6, 0x4, PT ; /* 0x000000040600780c */
/* 0x000fda0003f24270 */
/*06b0*/ @!P1 BRA 0x940 ; /* 0x0000028000009947 */
/* 0x000fea0003800000 */
/*06c0*/ MOV R9, R5 ; /* 0x0000000500097202 */
/* 0x000fe20000000f00 */
/*06d0*/ LDG.E R18, [R20.64] ; /* 0x0000000414127981 */
/* 0x0000a8000c1e1900 */
/*06e0*/ IMAD.WIDE R10, R7, 0x4, R8 ; /* 0x00000004070a7825 */
/* 0x000fca00078e0208 */
/*06f0*/ LDG.E R24, [R10.64] ; /* 0x000000040a187981 */
/* 0x000ea2000c1e1900 */
/*0700*/ MOV R9, c[0x0][0x180] ; /* 0x0000600000097a02 */
/* 0x000fc60000000f00 */
/*0710*/ LDG.E R25, [R10.64+0x4] ; /* 0x000004040a197981 */
/* 0x000ee4000c1e1900 */
/*0720*/ IMAD.WIDE R22, R9.reuse, 0x4, R20 ; /* 0x0000000409167825 */
/* 0x040fe400078e0214 */
/*0730*/ LDG.E R27, [R10.64+0x8] ; /* 0x000008040a1b7981 */
/* 0x000f28000c1e1900 */
/*0740*/ IMAD.WIDE R12, R9.reuse, 0x4, R22 ; /* 0x00000004090c7825 */
/* 0x040fe200078e0216 */
/*0750*/ LDG.E R29, [R10.64+0xc] ; /* 0x00000c040a1d7981 */
/* 0x000f68000c1e1900 */
/*0760*/ LDG.E R22, [R22.64] ; /* 0x0000000416167981 */
/* 0x0002e2000c1e1900 */
/*0770*/ IMAD.WIDE R14, R9, 0x4, R12 ; /* 0x00000004090e7825 */
/* 0x000fc600078e020c */
/*0780*/ LDG.E R26, [R12.64] ; /* 0x000000040c1a7981 */
/* 0x000326000c1e1900 */
/*0790*/ IMAD.WIDE R16, R9.reuse, 0x4, R14 ; /* 0x0000000409107825 */
/* 0x040fe400078e020e */
/*07a0*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000368000c1e1900 */
/*07b0*/ IMAD.WIDE R20, R9, 0x4, R16 ; /* 0x0000000409147825 */
/* 0x001fe400078e0210 */
/*07c0*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x000168000c1e1900 */
/*07d0*/ LDG.E R15, [R10.64+0x14] ; /* 0x000014040a0f7981 */
/* 0x002f68000c1e1900 */
/*07e0*/ LDG.E R17, [R10.64+0x18] ; /* 0x000018040a117981 */
/* 0x001f62000c1e1900 */
/*07f0*/ FFMA R28, R18, R24, R19 ; /* 0x00000018121c7223 */
/* 0x004fc60000000013 */
/*0800*/ LDG.E R24, [R10.64+0x10] ; /* 0x000010040a187981 */
/* 0x000ea2000c1e1900 */
/*0810*/ IMAD.WIDE R18, R9, 0x4, R20 ; /* 0x0000000409127825 */
/* 0x000fc600078e0214 */
/*0820*/ LDG.E R20, [R20.64] ; /* 0x0000000414147981 */
/* 0x000ea6000c1e1900 */
/*0830*/ IMAD.WIDE R12, R9, 0x4, R18 ; /* 0x00000004090c7825 */
/* 0x000fe200078e0212 */
/*0840*/ LDG.E R23, [R18.64] ; /* 0x0000000412177981 */
/* 0x0000a8000c1e1900 */
/*0850*/ LDG.E R18, [R10.64+0x1c] ; /* 0x00001c040a127981 */
/* 0x001ea8000c1e1900 */
/*0860*/ LDG.E R19, [R12.64] ; /* 0x000000040c137981 */
/* 0x000ea2000c1e1900 */
/*0870*/ FFMA R22, R22, R25, R28 ; /* 0x0000001916167223 */
/* 0x008fc8000000001c */
/*0880*/ FFMA R22, R26, R27, R22 ; /* 0x0000001b1a167223 */
/* 0x010fc80000000016 */
/*0890*/ FFMA R29, R14, R29, R22 ; /* 0x0000001d0e1d7223 */
/* 0x020fe20000000016 */
/*08a0*/ IADD3 R8, P1, R8, 0x20, RZ ; /* 0x0000002008087810 */
/* 0x000fe40007f3e0ff */
/*08b0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*08c0*/ IADD3 R2, R2, 0x8, RZ ; /* 0x0000000802027810 */
/* 0x000fe40007ffe0ff */
/*08d0*/ IADD3 R6, R6, -0x8, RZ ; /* 0xfffffff806067810 */
/* 0x000fe40007ffe0ff */
/*08e0*/ IADD3.X R5, RZ, R5, RZ, P1, !PT ; /* 0x00000005ff057210 */
/* 0x000fe20000ffe4ff */
/*08f0*/ FFMA R16, R16, R24, R29 ; /* 0x0000001810107223 */
/* 0x004fc8000000001d */
/*0900*/ FFMA R16, R20, R15, R16 ; /* 0x0000000f14107223 */
/* 0x000fc80000000010 */
/*0910*/ FFMA R16, R23, R17, R16 ; /* 0x0000001117107223 */
/* 0x000fe40000000010 */
/*0920*/ IMAD.WIDE R20, R9, 0x4, R12 ; /* 0x0000000409147825 */
/* 0x000fc800078e020c */
/*0930*/ FFMA R19, R19, R18, R16 ; /* 0x0000001213137223 */
/* 0x000fe40000000010 */
/*0940*/ ISETP.NE.OR P0, PT, R6, RZ, P0 ; /* 0x000000ff0600720c */
/* 0x000fda0000705670 */
/*0950*/ @!P0 BRA 0xb00 ; /* 0x000001a000008947 */
/* 0x000fea0003800000 */
/*0960*/ MOV R9, c[0x0][0x180] ; /* 0x0000600000097a02 */
/* 0x000fe40000000f00 */
/*0970*/ MOV R10, R8 ; /* 0x00000008000a7202 */
/* 0x000fe40000000f00 */
/*0980*/ MOV R11, R5 ; /* 0x00000005000b7202 */
/* 0x000fe20000000f00 */
/*0990*/ IMAD.WIDE R12, R9, 0x4, R20 ; /* 0x00000004090c7825 */
/* 0x000fe400078e0214 */
/*09a0*/ LDG.E R20, [R20.64] ; /* 0x0000000414147981 */
/* 0x000ea4000c1e1900 */
/*09b0*/ IMAD.WIDE R10, R7, 0x4, R10 ; /* 0x00000004070a7825 */
/* 0x000fe400078e020a */
/*09c0*/ LDG.E R23, [R12.64] ; /* 0x000000040c177981 */
/* 0x000ee4000c1e1900 */
/*09d0*/ IMAD.WIDE R16, R9, 0x4, R12 ; /* 0x0000000409107825 */
/* 0x000fc400078e020c */
/*09e0*/ LDG.E R18, [R10.64] ; /* 0x000000040a127981 */
/* 0x000ea8000c1e1900 */
/*09f0*/ LDG.E R22, [R10.64+0x4] ; /* 0x000004040a167981 */
/* 0x000ee2000c1e1900 */
/*0a00*/ IMAD.WIDE R14, R9, 0x4, R16 ; /* 0x00000004090e7825 */
/* 0x000fc600078e0210 */
/*0a10*/ LDG.E R24, [R10.64+0x8] ; /* 0x000008040a187981 */
/* 0x000f28000c1e1900 */
/*0a20*/ LDG.E R25, [R16.64] ; /* 0x0000000410197981 */
/* 0x000f28000c1e1900 */
/*0a30*/ LDG.E R26, [R10.64+0xc] ; /* 0x00000c040a1a7981 */
/* 0x000f68000c1e1900 */
/*0a40*/ LDG.E R27, [R14.64] ; /* 0x000000040e1b7981 */
/* 0x000f62000c1e1900 */
/*0a50*/ IADD3 R6, R6, -0x4, RZ ; /* 0xfffffffc06067810 */
/* 0x000fc80007ffe0ff */
/*0a60*/ ISETP.NE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe40003f05270 */
/*0a70*/ IADD3 R8, P1, R8, 0x10, RZ ; /* 0x0000001008087810 */
/* 0x000fe40007f3e0ff */
/*0a80*/ IADD3 R2, R2, 0x4, RZ ; /* 0x0000000402027810 */
/* 0x000fe40007ffe0ff */
/*0a90*/ IADD3.X R5, RZ, R5, RZ, P1, !PT ; /* 0x00000005ff057210 */
/* 0x000fe20000ffe4ff */
/*0aa0*/ FFMA R18, R20, R18, R19 ; /* 0x0000001214127223 */
/* 0x004fc80000000013 */
/*0ab0*/ FFMA R18, R23, R22, R18 ; /* 0x0000001617127223 */
/* 0x008fe40000000012 */
/*0ac0*/ IMAD.WIDE R20, R9, 0x4, R14 ; /* 0x0000000409147825 */
/* 0x000fc800078e020e */
/*0ad0*/ FFMA R18, R25, R24, R18 ; /* 0x0000001819127223 */
/* 0x010fc80000000012 */
/*0ae0*/ FFMA R19, R27, R26, R18 ; /* 0x0000001a1b137223 */
/* 0x020fe20000000012 */
/*0af0*/ @P0 BRA 0x960 ; /* 0xfffffe6000000947 */
/* 0x000fea000383ffff */
/*0b00*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fda0003f05270 */
/*0b10*/ @!P0 BRA 0xc10 ; /* 0x000000f000008947 */
/* 0x000fea0003800000 */
/*0b20*/ HFMA2.MMA R9, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff097435 */
/* 0x000fe200000001ff */
/*0b30*/ IMAD R6, R0, c[0x0][0x17c], R2 ; /* 0x00005f0000067a24 */
/* 0x000fe400078e0202 */
/*0b40*/ IMAD R2, R2, c[0x0][0x180], R3 ; /* 0x0000600002027a24 */
/* 0x000fce00078e0203 */
/*0b50*/ IMAD.WIDE R6, R6, R9, c[0x0][0x160] ; /* 0x0000580006067625 */
/* 0x000fc800078e0209 */
/*0b60*/ IMAD.WIDE R8, R2, R9, c[0x0][0x168] ; /* 0x00005a0002087625 */
/* 0x000fca00078e0209 */
/*0b70*/ LDG.E R2, [R8.64] ; /* 0x0000000408027981 */
/* 0x0000a8000c1e1900 */
/*0b80*/ LDG.E R5, [R6.64] ; /* 0x0000000406057981 */
/* 0x0002a2000c1e1900 */
/*0b90*/ IADD3 R4, R4, -0x1, RZ ; /* 0xffffffff04047810 */
/* 0x000fe40007ffe0ff */
/*0ba0*/ MOV R11, c[0x0][0x180] ; /* 0x00006000000b7a02 */
/* 0x000fe40000000f00 */
/*0bb0*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fc60003f05270 */
/*0bc0*/ IMAD.WIDE R8, R11, 0x4, R8 ; /* 0x000000040b087825 */
/* 0x001fe200078e0208 */
/*0bd0*/ IADD3 R6, P1, R6, 0x4, RZ ; /* 0x0000000406067810 */
/* 0x002fc80007f3e0ff */
/*0be0*/ IADD3.X R7, RZ, R7, RZ, P1, !PT ; /* 0x00000007ff077210 */
/* 0x000fe20000ffe4ff */
/*0bf0*/ FFMA R19, R2, R5, R19 ; /* 0x0000000502137223 */
/* 0x004fc80000000013 */
/*0c00*/ @P0 BRA 0xb70 ; /* 0xffffff6000000947 */
/* 0x000fea000383ffff */
/*0c10*/ MOV R2, 0x4 ; /* 0x0000000400027802 */
/* 0x000fe20000000f00 */
/*0c20*/ IMAD R3, R0, c[0x0][0x180], R3 ; /* 0x0000600000037a24 */
/* 0x000fc800078e0203 */
/*0c30*/ IMAD.WIDE R2, R3, R2, c[0x0][0x170] ; /* 0x00005c0003027625 */
/* 0x000fca00078e0202 */
/*0c40*/ STG.E [R2.64], R19 ; /* 0x0000001302007986 */
/* 0x000fe2000c101904 */
/*0c50*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0c60*/ BRA 0xc60; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0c70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ca0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ce0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <cstdio>
#include <cstdlib>
#include <cuda_runtime.h>
#include <time.h>
#define random(a, b) (rand() % (b - a) + a)
void FillMatrix(float *matrix, int row, int col);
void PrintMatrix(float *A, float *B, float *C, int m, int n, int k);
__global__ void MatrixMulCUDA(const float *A, const float *B, float *C, int m, int n, int k, int ThreadBlockSize)
{
// 计算元素的行
const int row = blockIdx.x;
// 计算元素的列
const int col = blockIdx.y * ThreadBlockSize + threadIdx.x;
float temp = 0;
if (row < m && col < k)
{
for (int i = 0; i < n; ++i)
temp += A[row * n + i] * B[i * k + col];
C[row * k + col] = temp;
}
}
int main(int argc, char **argv)
{
if (argc != 5)
{
printf("Wrong Input!\n");
return 1;
}
int m = atoi(argv[1]);
int n = atoi(argv[2]);
int k = atoi(argv[3]);
int ThreadBlockSize = atoi(argv[4]);
float *A, *B, *C;
A = new float[m * n];
B = new float[n * k];
C = new float[m * k];
FillMatrix(A, m, n);
FillMatrix(B, n, k);
float *cuda_A, *cuda_B, *cuda_C;
// 使用cuda内置API计时
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaEventRecord(start, 0);
// 申请空间
cudaMalloc((void **)&cuda_A, sizeof(float) * m * n);
cudaMalloc((void **)&cuda_B, sizeof(float) * n * k);
cudaMalloc((void **)&cuda_C, sizeof(float) * m * k);
// 将A、B矩阵从CPU转移到GPU
cudaMemcpy(cuda_A, A, sizeof(float) * m * n, cudaMemcpyHostToDevice);
cudaMemcpy(cuda_B, B, sizeof(float) * n * k, cudaMemcpyHostToDevice);
// 定义的结构网格
dim3 grid(m, k / ThreadBlockSize);
// 矩阵乘法
MatrixMulCUDA<<<grid, ThreadBlockSize>>>(cuda_A, cuda_B, cuda_C, m, n, k, ThreadBlockSize);
// 将结果C矩阵从GPU转移回CPU
cudaMemcpy(C, cuda_C, sizeof(float) * m * k, cudaMemcpyDeviceToHost);
cudaFree(cuda_A);
cudaFree(cuda_B);
cudaFree(cuda_C);
// 计时
cudaEventRecord(stop, 0);
cudaEventSynchronize(stop);
float elapsedTime;
cudaEventElapsedTime(&elapsedTime, start, stop);
printf("Matrix Size is %d\nThreadBlockSize is %d\n", m,ThreadBlockSize);
printf("Calculation time is %.10f ms\n", elapsedTime);
// PrintMatrix(A, B, C, m, n, k);
delete[] A;
delete[] C;
delete[] B;
return 0;
}
void FillMatrix(float *matrix, int row, int col)
{
for (int i = 0; i < row; ++i)
for (int j = 0; j < col; ++j)
matrix[i * col + j] = random(0, 9);
}
void PrintMatrix(float *A, float *B, float *C, int m, int n, int k)
{
printf("Matrix A:\n");
for (int i = 0; i < m; ++i)
{
for (int j = 0; j < n; ++j)
printf("%f ", A[i * n + j]);
printf("\n");
}
printf("Matrix B:\n");
for (int i = 0; i < n; ++i)
{
for (int j = 0; j < k; ++j)
printf("%f ", B[i * k + j]);
printf("\n");
}
printf("Matrix C:\n");
for (int i = 0; i < m; ++i)
{
for (int j = 0; j < k; ++j)
printf("%f ", C[i * k + j]);
printf("\n");
}
} | .file "tmpxft_000a2d3f_00000000-6_MatrixMul_cuda.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z10FillMatrixPfii
.type _Z10FillMatrixPfii, @function
_Z10FillMatrixPfii:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $24, %rsp
.cfi_def_cfa_offset 80
movl %esi, 4(%rsp)
testl %esi, %esi
jle .L3
movq %rdi, %r15
movl %edx, %r14d
movl $0, %r13d
movl $0, %r12d
movslq %edx, %rax
movq %rax, 8(%rsp)
jmp .L5
.L7:
movslq %r13d, %rax
leaq (%r15,%rax,4), %rbx
movq 8(%rsp), %rsi
addq %rsi, %rax
leaq (%r15,%rax,4), %rbp
.L6:
call rand@PLT
movslq %eax, %rdx
imulq $954437177, %rdx, %rdx
sarq $33, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
leal (%rdx,%rdx,8), %edx
subl %edx, %eax
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, (%rbx)
addq $4, %rbx
cmpq %rbp, %rbx
jne .L6
.L8:
addl $1, %r12d
addl %r14d, %r13d
cmpl %r12d, 4(%rsp)
je .L3
.L5:
testl %r14d, %r14d
jg .L7
jmp .L8
.L3:
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _Z10FillMatrixPfii, .-_Z10FillMatrixPfii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Matrix A:\n"
.LC1:
.string "%f "
.LC2:
.string "\n"
.LC3:
.string "Matrix B:\n"
.LC4:
.string "Matrix C:\n"
.text
.globl _Z11PrintMatrixPfS_S_iii
.type _Z11PrintMatrixPfS_S_iii, @function
_Z11PrintMatrixPfS_S_iii:
.LFB2059:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $56, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, %r15d
movl %ecx, 40(%rsp)
movl %r8d, %ebx
movl %r8d, (%rsp)
movl %r9d, %r13d
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
testl %r15d, %r15d
jle .L12
movl $0, %r15d
movl $0, %r14d
movslq %ebx, %rcx
movq %rcx, 32(%rsp)
leaq .LC1(%rip), %r12
movl %r13d, 44(%rsp)
movl %ebx, %r13d
jmp .L13
.L16:
movslq %r15d, %rax
movq 8(%rsp), %rdx
leaq (%rdx,%rax,4), %rbx
movq 32(%rsp), %rcx
addq %rcx, %rax
leaq (%rdx,%rax,4), %rbp
.L14:
pxor %xmm0, %xmm0
cvtss2sd (%rbx), %xmm0
movq %r12, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %rbp, %rbx
jne .L14
.L17:
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %r14d
addl %r13d, %r15d
cmpl %r14d, 40(%rsp)
je .L15
.L13:
testl %r13d, %r13d
jg .L16
jmp .L17
.L15:
movl 44(%rsp), %r13d
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
cmpl $0, (%rsp)
jle .L18
.L29:
movl $0, %r15d
movl $0, %r14d
movslq %r13d, %rax
movq %rax, 8(%rsp)
leaq .LC1(%rip), %r12
jmp .L19
.L22:
movslq %r15d, %rax
movq 16(%rsp), %rcx
leaq (%rcx,%rax,4), %rbx
movq 8(%rsp), %rdx
addq %rdx, %rax
leaq (%rcx,%rax,4), %rbp
.L20:
pxor %xmm0, %xmm0
cvtss2sd (%rbx), %xmm0
movq %r12, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %rbp, %rbx
jne .L20
.L23:
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %r14d
addl %r13d, %r15d
cmpl %r14d, (%rsp)
jle .L21
.L19:
testl %r13d, %r13d
jg .L22
jmp .L23
.L21:
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
cmpl $0, 40(%rsp)
jle .L11
.L31:
movl $0, %r15d
movl $0, %r14d
movslq %r13d, %rax
movq %rax, (%rsp)
leaq .LC1(%rip), %r12
jmp .L25
.L27:
movslq %r15d, %rax
movq 24(%rsp), %rdx
leaq (%rdx,%rax,4), %rbx
movq (%rsp), %rcx
addq %rcx, %rax
leaq (%rdx,%rax,4), %rbp
.L26:
pxor %xmm0, %xmm0
cvtss2sd (%rbx), %xmm0
movq %r12, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %rbp, %rbx
jne .L26
.L28:
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %r14d
addl %r13d, %r15d
cmpl %r14d, 40(%rsp)
je .L11
.L25:
testl %r13d, %r13d
jg .L27
jmp .L28
.L12:
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
cmpl $0, (%rsp)
jg .L29
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L11:
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L18:
.cfi_restore_state
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L31
.cfi_endproc
.LFE2059:
.size _Z11PrintMatrixPfS_S_iii, .-_Z11PrintMatrixPfS_S_iii
.globl _Z43__device_stub__Z13MatrixMulCUDAPKfS0_PfiiiiPKfS0_Pfiiii
.type _Z43__device_stub__Z13MatrixMulCUDAPKfS0_PfiiiiPKfS0_Pfiiii, @function
_Z43__device_stub__Z13MatrixMulCUDAPKfS0_PfiiiiPKfS0_Pfiiii:
.LFB2084:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
leaq 192(%rsp), %rax
movq %rax, 160(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L41
.L37:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L42
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L41:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z13MatrixMulCUDAPKfS0_Pfiiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L37
.L42:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z43__device_stub__Z13MatrixMulCUDAPKfS0_PfiiiiPKfS0_Pfiiii, .-_Z43__device_stub__Z13MatrixMulCUDAPKfS0_PfiiiiPKfS0_Pfiiii
.globl _Z13MatrixMulCUDAPKfS0_Pfiiii
.type _Z13MatrixMulCUDAPKfS0_Pfiiii, @function
_Z13MatrixMulCUDAPKfS0_Pfiiii:
.LFB2085:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
call _Z43__device_stub__Z13MatrixMulCUDAPKfS0_PfiiiiPKfS0_Pfiiii
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z13MatrixMulCUDAPKfS0_Pfiiii, .-_Z13MatrixMulCUDAPKfS0_Pfiiii
.section .rodata.str1.1
.LC5:
.string "Wrong Input!\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC6:
.string "Matrix Size is %d\nThreadBlockSize is %d\n"
.section .rodata.str1.1
.LC7:
.string "Calculation time is %.10f ms\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $152, %rsp
.cfi_def_cfa_offset 208
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
cmpl $5, %edi
je .L46
leaq .LC5(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
movl $1, %eax
.L45:
movq 136(%rsp), %rdx
subq %fs:40, %rdx
jne .L63
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L46:
.cfi_restore_state
movq %rsi, %r14
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %rbp
movl %eax, 28(%rsp)
movq 16(%r14), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %r12
movq 24(%r14), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %r13
movl %eax, 36(%rsp)
movq 32(%r14), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, 40(%rsp)
movl %eax, 32(%rsp)
movl %ebp, %edi
imull %r12d, %edi
movslq %edi, %rdi
movabsq $2305843009213693950, %rax
cmpq %rdi, %rax
jb .L48
salq $2, %rdi
call _Znam@PLT
movq %rax, 8(%rsp)
movl %r12d, %edi
imull %r13d, %edi
movslq %edi, %rdi
movabsq $2305843009213693950, %rax
cmpq %rdi, %rax
jb .L64
salq $2, %rdi
call _Znam@PLT
movq %rax, 16(%rsp)
movl %ebp, %edi
imull %r13d, %edi
movslq %edi, %rdi
movabsq $2305843009213693950, %rax
cmpq %rdi, %rax
jb .L65
salq $2, %rdi
call _Znam@PLT
movq %rax, 56(%rsp)
movl %r12d, %edx
movl 28(%rsp), %esi
movq 8(%rsp), %rdi
call _Z10FillMatrixPfii
movl 36(%rsp), %edx
movl %r12d, %esi
movq 16(%rsp), %rdi
call _Z10FillMatrixPfii
leaq 96(%rsp), %rdi
call cudaEventCreate@PLT
leaq 104(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 96(%rsp), %rdi
call cudaEventRecord@PLT
movslq %ebp, %rbx
movslq %r12d, %r14
movq %rbx, %rax
imulq %r14, %rax
leaq 0(,%rax,4), %rcx
leaq 72(%rsp), %rdi
movq %rcx, 48(%rsp)
movq %rcx, %rsi
call cudaMalloc@PLT
movslq %r13d, %r15
imulq %r15, %r14
salq $2, %r14
leaq 80(%rsp), %rdi
movq %r14, %rsi
call cudaMalloc@PLT
imulq %r15, %rbx
salq $2, %rbx
leaq 88(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq 48(%rsp), %rdx
movq 8(%rsp), %rsi
movq 72(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %r14, %rdx
movq 16(%rsp), %rsi
movq 80(%rsp), %rdi
call cudaMemcpy@PLT
movl %ebp, 112(%rsp)
movl 36(%rsp), %eax
cltd
idivl 32(%rsp)
movl %eax, 116(%rsp)
movl 40(%rsp), %eax
movl %eax, 124(%rsp)
movl $1, 128(%rsp)
movl $1, 132(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 124(%rsp), %rdx
movl $1, %ecx
movq 112(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L66
.L55:
movl $2, %ecx
movq %rbx, %rdx
movq 88(%rsp), %rsi
movq 56(%rsp), %rbx
movq %rbx, %rdi
call cudaMemcpy@PLT
movq 72(%rsp), %rdi
call cudaFree@PLT
movq 80(%rsp), %rdi
call cudaFree@PLT
movq 88(%rsp), %rdi
call cudaFree@PLT
movl $0, %esi
movq 104(%rsp), %rdi
call cudaEventRecord@PLT
movq 104(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 124(%rsp), %rdi
movq 104(%rsp), %rdx
movq 96(%rsp), %rsi
call cudaEventElapsedTime@PLT
movl 32(%rsp), %ecx
movl 28(%rsp), %edx
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
pxor %xmm0, %xmm0
cvtss2sd 124(%rsp), %xmm0
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 8(%rsp), %rdi
call _ZdaPv@PLT
movq %rbx, %rdi
call _ZdaPv@PLT
movq 16(%rsp), %rdi
call _ZdaPv@PLT
movl $0, %eax
jmp .L45
.L48:
movq 136(%rsp), %rax
subq %fs:40, %rax
je .L51
call __stack_chk_fail@PLT
.L51:
call __cxa_throw_bad_array_new_length@PLT
.L64:
movq 136(%rsp), %rax
subq %fs:40, %rax
je .L54
call __stack_chk_fail@PLT
.L54:
call __cxa_throw_bad_array_new_length@PLT
.L65:
movq 136(%rsp), %rax
subq %fs:40, %rax
je .L57
call __stack_chk_fail@PLT
.L57:
call __cxa_throw_bad_array_new_length@PLT
.L66:
subq $8, %rsp
.cfi_def_cfa_offset 216
movl 48(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 224
movl %r13d, %r9d
movl %r12d, %r8d
movl 44(%rsp), %ecx
movq 104(%rsp), %rdx
movq 96(%rsp), %rsi
movq 88(%rsp), %rdi
call _Z43__device_stub__Z13MatrixMulCUDAPKfS0_PfiiiiPKfS0_Pfiiii
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L55
.L63:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC8:
.string "_Z13MatrixMulCUDAPKfS0_Pfiiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _Z13MatrixMulCUDAPKfS0_Pfiiii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <cstdio>
#include <cstdlib>
#include <cuda_runtime.h>
#include <time.h>
#define random(a, b) (rand() % (b - a) + a)
void FillMatrix(float *matrix, int row, int col);
void PrintMatrix(float *A, float *B, float *C, int m, int n, int k);
__global__ void MatrixMulCUDA(const float *A, const float *B, float *C, int m, int n, int k, int ThreadBlockSize)
{
// 计算元素的行
const int row = blockIdx.x;
// 计算元素的列
const int col = blockIdx.y * ThreadBlockSize + threadIdx.x;
float temp = 0;
if (row < m && col < k)
{
for (int i = 0; i < n; ++i)
temp += A[row * n + i] * B[i * k + col];
C[row * k + col] = temp;
}
}
int main(int argc, char **argv)
{
if (argc != 5)
{
printf("Wrong Input!\n");
return 1;
}
int m = atoi(argv[1]);
int n = atoi(argv[2]);
int k = atoi(argv[3]);
int ThreadBlockSize = atoi(argv[4]);
float *A, *B, *C;
A = new float[m * n];
B = new float[n * k];
C = new float[m * k];
FillMatrix(A, m, n);
FillMatrix(B, n, k);
float *cuda_A, *cuda_B, *cuda_C;
// 使用cuda内置API计时
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaEventRecord(start, 0);
// 申请空间
cudaMalloc((void **)&cuda_A, sizeof(float) * m * n);
cudaMalloc((void **)&cuda_B, sizeof(float) * n * k);
cudaMalloc((void **)&cuda_C, sizeof(float) * m * k);
// 将A、B矩阵从CPU转移到GPU
cudaMemcpy(cuda_A, A, sizeof(float) * m * n, cudaMemcpyHostToDevice);
cudaMemcpy(cuda_B, B, sizeof(float) * n * k, cudaMemcpyHostToDevice);
// 定义的结构网格
dim3 grid(m, k / ThreadBlockSize);
// 矩阵乘法
MatrixMulCUDA<<<grid, ThreadBlockSize>>>(cuda_A, cuda_B, cuda_C, m, n, k, ThreadBlockSize);
// 将结果C矩阵从GPU转移回CPU
cudaMemcpy(C, cuda_C, sizeof(float) * m * k, cudaMemcpyDeviceToHost);
cudaFree(cuda_A);
cudaFree(cuda_B);
cudaFree(cuda_C);
// 计时
cudaEventRecord(stop, 0);
cudaEventSynchronize(stop);
float elapsedTime;
cudaEventElapsedTime(&elapsedTime, start, stop);
printf("Matrix Size is %d\nThreadBlockSize is %d\n", m,ThreadBlockSize);
printf("Calculation time is %.10f ms\n", elapsedTime);
// PrintMatrix(A, B, C, m, n, k);
delete[] A;
delete[] C;
delete[] B;
return 0;
}
void FillMatrix(float *matrix, int row, int col)
{
for (int i = 0; i < row; ++i)
for (int j = 0; j < col; ++j)
matrix[i * col + j] = random(0, 9);
}
void PrintMatrix(float *A, float *B, float *C, int m, int n, int k)
{
printf("Matrix A:\n");
for (int i = 0; i < m; ++i)
{
for (int j = 0; j < n; ++j)
printf("%f ", A[i * n + j]);
printf("\n");
}
printf("Matrix B:\n");
for (int i = 0; i < n; ++i)
{
for (int j = 0; j < k; ++j)
printf("%f ", B[i * k + j]);
printf("\n");
}
printf("Matrix C:\n");
for (int i = 0; i < m; ++i)
{
for (int j = 0; j < k; ++j)
printf("%f ", C[i * k + j]);
printf("\n");
}
} | #include <cstdio>
#include <cstdlib>
#include <hip/hip_runtime.h>
#include <time.h>
#define random(a, b) (rand() % (b - a) + a)
void FillMatrix(float *matrix, int row, int col);
void PrintMatrix(float *A, float *B, float *C, int m, int n, int k);
__global__ void MatrixMulCUDA(const float *A, const float *B, float *C, int m, int n, int k, int ThreadBlockSize)
{
// 计算元素的行
const int row = blockIdx.x;
// 计算元素的列
const int col = blockIdx.y * ThreadBlockSize + threadIdx.x;
float temp = 0;
if (row < m && col < k)
{
for (int i = 0; i < n; ++i)
temp += A[row * n + i] * B[i * k + col];
C[row * k + col] = temp;
}
}
int main(int argc, char **argv)
{
if (argc != 5)
{
printf("Wrong Input!\n");
return 1;
}
int m = atoi(argv[1]);
int n = atoi(argv[2]);
int k = atoi(argv[3]);
int ThreadBlockSize = atoi(argv[4]);
float *A, *B, *C;
A = new float[m * n];
B = new float[n * k];
C = new float[m * k];
FillMatrix(A, m, n);
FillMatrix(B, n, k);
float *cuda_A, *cuda_B, *cuda_C;
// 使用cuda内置API计时
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
hipEventRecord(start, 0);
// 申请空间
hipMalloc((void **)&cuda_A, sizeof(float) * m * n);
hipMalloc((void **)&cuda_B, sizeof(float) * n * k);
hipMalloc((void **)&cuda_C, sizeof(float) * m * k);
// 将A、B矩阵从CPU转移到GPU
hipMemcpy(cuda_A, A, sizeof(float) * m * n, hipMemcpyHostToDevice);
hipMemcpy(cuda_B, B, sizeof(float) * n * k, hipMemcpyHostToDevice);
// 定义的结构网格
dim3 grid(m, k / ThreadBlockSize);
// 矩阵乘法
MatrixMulCUDA<<<grid, ThreadBlockSize>>>(cuda_A, cuda_B, cuda_C, m, n, k, ThreadBlockSize);
// 将结果C矩阵从GPU转移回CPU
hipMemcpy(C, cuda_C, sizeof(float) * m * k, hipMemcpyDeviceToHost);
hipFree(cuda_A);
hipFree(cuda_B);
hipFree(cuda_C);
// 计时
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
float elapsedTime;
hipEventElapsedTime(&elapsedTime, start, stop);
printf("Matrix Size is %d\nThreadBlockSize is %d\n", m,ThreadBlockSize);
printf("Calculation time is %.10f ms\n", elapsedTime);
// PrintMatrix(A, B, C, m, n, k);
delete[] A;
delete[] C;
delete[] B;
return 0;
}
void FillMatrix(float *matrix, int row, int col)
{
for (int i = 0; i < row; ++i)
for (int j = 0; j < col; ++j)
matrix[i * col + j] = random(0, 9);
}
void PrintMatrix(float *A, float *B, float *C, int m, int n, int k)
{
printf("Matrix A:\n");
for (int i = 0; i < m; ++i)
{
for (int j = 0; j < n; ++j)
printf("%f ", A[i * n + j]);
printf("\n");
}
printf("Matrix B:\n");
for (int i = 0; i < n; ++i)
{
for (int j = 0; j < k; ++j)
printf("%f ", B[i * k + j]);
printf("\n");
}
printf("Matrix C:\n");
for (int i = 0; i < m; ++i)
{
for (int j = 0; j < k; ++j)
printf("%f ", C[i * k + j]);
printf("\n");
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <cstdio>
#include <cstdlib>
#include <hip/hip_runtime.h>
#include <time.h>
#define random(a, b) (rand() % (b - a) + a)
void FillMatrix(float *matrix, int row, int col);
void PrintMatrix(float *A, float *B, float *C, int m, int n, int k);
__global__ void MatrixMulCUDA(const float *A, const float *B, float *C, int m, int n, int k, int ThreadBlockSize)
{
// 计算元素的行
const int row = blockIdx.x;
// 计算元素的列
const int col = blockIdx.y * ThreadBlockSize + threadIdx.x;
float temp = 0;
if (row < m && col < k)
{
for (int i = 0; i < n; ++i)
temp += A[row * n + i] * B[i * k + col];
C[row * k + col] = temp;
}
}
int main(int argc, char **argv)
{
if (argc != 5)
{
printf("Wrong Input!\n");
return 1;
}
int m = atoi(argv[1]);
int n = atoi(argv[2]);
int k = atoi(argv[3]);
int ThreadBlockSize = atoi(argv[4]);
float *A, *B, *C;
A = new float[m * n];
B = new float[n * k];
C = new float[m * k];
FillMatrix(A, m, n);
FillMatrix(B, n, k);
float *cuda_A, *cuda_B, *cuda_C;
// 使用cuda内置API计时
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
hipEventRecord(start, 0);
// 申请空间
hipMalloc((void **)&cuda_A, sizeof(float) * m * n);
hipMalloc((void **)&cuda_B, sizeof(float) * n * k);
hipMalloc((void **)&cuda_C, sizeof(float) * m * k);
// 将A、B矩阵从CPU转移到GPU
hipMemcpy(cuda_A, A, sizeof(float) * m * n, hipMemcpyHostToDevice);
hipMemcpy(cuda_B, B, sizeof(float) * n * k, hipMemcpyHostToDevice);
// 定义的结构网格
dim3 grid(m, k / ThreadBlockSize);
// 矩阵乘法
MatrixMulCUDA<<<grid, ThreadBlockSize>>>(cuda_A, cuda_B, cuda_C, m, n, k, ThreadBlockSize);
// 将结果C矩阵从GPU转移回CPU
hipMemcpy(C, cuda_C, sizeof(float) * m * k, hipMemcpyDeviceToHost);
hipFree(cuda_A);
hipFree(cuda_B);
hipFree(cuda_C);
// 计时
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
float elapsedTime;
hipEventElapsedTime(&elapsedTime, start, stop);
printf("Matrix Size is %d\nThreadBlockSize is %d\n", m,ThreadBlockSize);
printf("Calculation time is %.10f ms\n", elapsedTime);
// PrintMatrix(A, B, C, m, n, k);
delete[] A;
delete[] C;
delete[] B;
return 0;
}
void FillMatrix(float *matrix, int row, int col)
{
for (int i = 0; i < row; ++i)
for (int j = 0; j < col; ++j)
matrix[i * col + j] = random(0, 9);
}
void PrintMatrix(float *A, float *B, float *C, int m, int n, int k)
{
printf("Matrix A:\n");
for (int i = 0; i < m; ++i)
{
for (int j = 0; j < n; ++j)
printf("%f ", A[i * n + j]);
printf("\n");
}
printf("Matrix B:\n");
for (int i = 0; i < n; ++i)
{
for (int j = 0; j < k; ++j)
printf("%f ", B[i * k + j]);
printf("\n");
}
printf("Matrix C:\n");
for (int i = 0; i < m; ++i)
{
for (int j = 0; j < k; ++j)
printf("%f ", C[i * k + j]);
printf("\n");
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z13MatrixMulCUDAPKfS0_Pfiiii
.globl _Z13MatrixMulCUDAPKfS0_Pfiiii
.p2align 8
.type _Z13MatrixMulCUDAPKfS0_Pfiiii,@function
_Z13MatrixMulCUDAPKfS0_Pfiiii:
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x20
s_load_b32 s4, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[1:2], null, s15, s3, v[0:1]
s_cmp_lt_i32 s14, s4
s_cselect_b32 s3, -1, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_gt_i32_e32 vcc_lo, s2, v1
s_and_b32 s3, s3, vcc_lo
s_and_saveexec_b32 s4, s3
s_cbranch_execz .LBB0_6
s_load_b32 s3, s[0:1], 0x1c
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s3, 1
s_cbranch_scc1 .LBB0_4
s_load_b128 s[4:7], s[0:1], 0x0
s_mul_i32 s8, s14, s3
v_mov_b32_e32 v0, 0
s_ashr_i32 s9, s8, 31
v_mov_b32_e32 v2, v1
s_lshl_b64 s[8:9], s[8:9], 2
s_waitcnt lgkmcnt(0)
s_add_u32 s4, s4, s8
s_addc_u32 s5, s5, s9
.p2align 6
.LBB0_3:
v_ashrrev_i32_e32 v3, 31, v2
s_load_b32 s8, s[4:5], 0x0
s_add_i32 s3, s3, -1
s_add_u32 s4, s4, 4
s_addc_u32 s5, s5, 0
v_lshlrev_b64 v[3:4], 2, v[2:3]
v_add_nc_u32_e32 v2, s2, v2
s_cmp_eq_u32 s3, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v3, vcc_lo, s6, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s7, v4, vcc_lo
global_load_b32 v3, v[3:4], off
s_waitcnt vmcnt(0) lgkmcnt(0)
v_fmac_f32_e32 v0, s8, v3
s_cbranch_scc0 .LBB0_3
s_branch .LBB0_5
.LBB0_4:
v_mov_b32_e32 v0, 0
.LBB0_5:
s_load_b64 s[0:1], s[0:1], 0x10
v_mad_u64_u32 v[2:3], null, s14, s2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[1:2], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v1, vcc_lo, s0, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
global_store_b32 v[1:2], v0, off
.LBB0_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13MatrixMulCUDAPKfS0_Pfiiii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 40
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z13MatrixMulCUDAPKfS0_Pfiiii, .Lfunc_end0-_Z13MatrixMulCUDAPKfS0_Pfiiii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 36
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 40
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13MatrixMulCUDAPKfS0_Pfiiii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z13MatrixMulCUDAPKfS0_Pfiiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <cstdio>
#include <cstdlib>
#include <hip/hip_runtime.h>
#include <time.h>
#define random(a, b) (rand() % (b - a) + a)
void FillMatrix(float *matrix, int row, int col);
void PrintMatrix(float *A, float *B, float *C, int m, int n, int k);
__global__ void MatrixMulCUDA(const float *A, const float *B, float *C, int m, int n, int k, int ThreadBlockSize)
{
// 计算元素的行
const int row = blockIdx.x;
// 计算元素的列
const int col = blockIdx.y * ThreadBlockSize + threadIdx.x;
float temp = 0;
if (row < m && col < k)
{
for (int i = 0; i < n; ++i)
temp += A[row * n + i] * B[i * k + col];
C[row * k + col] = temp;
}
}
int main(int argc, char **argv)
{
if (argc != 5)
{
printf("Wrong Input!\n");
return 1;
}
int m = atoi(argv[1]);
int n = atoi(argv[2]);
int k = atoi(argv[3]);
int ThreadBlockSize = atoi(argv[4]);
float *A, *B, *C;
A = new float[m * n];
B = new float[n * k];
C = new float[m * k];
FillMatrix(A, m, n);
FillMatrix(B, n, k);
float *cuda_A, *cuda_B, *cuda_C;
// 使用cuda内置API计时
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
hipEventRecord(start, 0);
// 申请空间
hipMalloc((void **)&cuda_A, sizeof(float) * m * n);
hipMalloc((void **)&cuda_B, sizeof(float) * n * k);
hipMalloc((void **)&cuda_C, sizeof(float) * m * k);
// 将A、B矩阵从CPU转移到GPU
hipMemcpy(cuda_A, A, sizeof(float) * m * n, hipMemcpyHostToDevice);
hipMemcpy(cuda_B, B, sizeof(float) * n * k, hipMemcpyHostToDevice);
// 定义的结构网格
dim3 grid(m, k / ThreadBlockSize);
// 矩阵乘法
MatrixMulCUDA<<<grid, ThreadBlockSize>>>(cuda_A, cuda_B, cuda_C, m, n, k, ThreadBlockSize);
// 将结果C矩阵从GPU转移回CPU
hipMemcpy(C, cuda_C, sizeof(float) * m * k, hipMemcpyDeviceToHost);
hipFree(cuda_A);
hipFree(cuda_B);
hipFree(cuda_C);
// 计时
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
float elapsedTime;
hipEventElapsedTime(&elapsedTime, start, stop);
printf("Matrix Size is %d\nThreadBlockSize is %d\n", m,ThreadBlockSize);
printf("Calculation time is %.10f ms\n", elapsedTime);
// PrintMatrix(A, B, C, m, n, k);
delete[] A;
delete[] C;
delete[] B;
return 0;
}
void FillMatrix(float *matrix, int row, int col)
{
for (int i = 0; i < row; ++i)
for (int j = 0; j < col; ++j)
matrix[i * col + j] = random(0, 9);
}
void PrintMatrix(float *A, float *B, float *C, int m, int n, int k)
{
printf("Matrix A:\n");
for (int i = 0; i < m; ++i)
{
for (int j = 0; j < n; ++j)
printf("%f ", A[i * n + j]);
printf("\n");
}
printf("Matrix B:\n");
for (int i = 0; i < n; ++i)
{
for (int j = 0; j < k; ++j)
printf("%f ", B[i * k + j]);
printf("\n");
}
printf("Matrix C:\n");
for (int i = 0; i < m; ++i)
{
for (int j = 0; j < k; ++j)
printf("%f ", C[i * k + j]);
printf("\n");
}
} | .text
.file "MatrixMul_cuda.hip"
.globl _Z28__device_stub__MatrixMulCUDAPKfS0_Pfiiii # -- Begin function _Z28__device_stub__MatrixMulCUDAPKfS0_Pfiiii
.p2align 4, 0x90
.type _Z28__device_stub__MatrixMulCUDAPKfS0_Pfiiii,@function
_Z28__device_stub__MatrixMulCUDAPKfS0_Pfiiii: # @_Z28__device_stub__MatrixMulCUDAPKfS0_Pfiiii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 160(%rsp), %rax
movq %rax, 144(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z13MatrixMulCUDAPKfS0_Pfiiii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z28__device_stub__MatrixMulCUDAPKfS0_Pfiiii, .Lfunc_end0-_Z28__device_stub__MatrixMulCUDAPKfS0_Pfiiii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $248, %rsp
.cfi_def_cfa_offset 304
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
cmpl $5, %edi
jne .LBB1_1
# %bb.2:
movq 8(%rsi), %rdi
xorl %ebx, %ebx
movq %rsi, %r14
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r15
movq 16(%r14), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r13
movq 24(%r14), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r12
movq 32(%r14), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, 112(%rsp) # 8-byte Spill
movl %r13d, %eax
imull %r15d, %eax
cltq
leaq (,%rax,4), %rdi
testl %eax, %eax
movq $-1, %r14
cmovsq %r14, %rdi
callq _Znam
movq %rax, 80(%rsp) # 8-byte Spill
movl %r12d, %eax
imull %r13d, %eax
cltq
leaq (,%rax,4), %rdi
testl %eax, %eax
cmovsq %r14, %rdi
callq _Znam
movq %rax, 72(%rsp) # 8-byte Spill
movq %r12, 88(%rsp) # 8-byte Spill
movl %r12d, %eax
imull %r15d, %eax
cltq
leaq (,%rax,4), %rdi
testl %eax, %eax
cmovsq %r14, %rdi
callq _Znam
movq %rax, 104(%rsp) # 8-byte Spill
movq %r15, 8(%rsp) # 8-byte Spill
testl %r15d, %r15d
movq %r13, 16(%rsp) # 8-byte Spill
jle .LBB1_8
# %bb.3: # %.preheader.lr.ph.i
movl 8(%rsp), %r14d # 4-byte Reload
movl %r13d, %r15d
xorl %r12d, %r12d
jmp .LBB1_4
.p2align 4, 0x90
.LBB1_7: # %._crit_edge.i
# in Loop: Header=BB1_4 Depth=1
incq %r12
movq 16(%rsp), %r13 # 8-byte Reload
addl %r13d, %ebx
cmpq %r14, %r12
je .LBB1_8
.LBB1_4: # %.preheader.i
# =>This Loop Header: Depth=1
# Child Loop BB1_6 Depth 2
testl %r13d, %r13d
jle .LBB1_7
# %bb.5: # %.lr.ph.i
# in Loop: Header=BB1_4 Depth=1
movl %ebx, %eax
movq 80(%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax,4), %rbp
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB1_6: # Parent Loop BB1_4 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
cltq
imulq $954437177, %rax, %rcx # imm = 0x38E38E39
movq %rcx, %rdx
shrq $63, %rdx
sarq $33, %rcx
addl %edx, %ecx
leal (%rcx,%rcx,8), %ecx
subl %ecx, %eax
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, (%rbp,%r13,4)
incq %r13
cmpq %r13, %r15
jne .LBB1_6
jmp .LBB1_7
.LBB1_1:
movl $.Lstr, %edi
callq puts@PLT
movl $1, %eax
jmp .LBB1_17
.LBB1_8: # %_Z10FillMatrixPfii.exit
testl %r13d, %r13d
movq 88(%rsp), %r13 # 8-byte Reload
jle .LBB1_14
# %bb.9: # %.preheader.lr.ph.i50
movl 16(%rsp), %ebx # 4-byte Reload
movl %r13d, %r14d
xorl %r15d, %r15d
xorl %r12d, %r12d
jmp .LBB1_10
.p2align 4, 0x90
.LBB1_13: # %._crit_edge.i54
# in Loop: Header=BB1_10 Depth=1
incq %r12
movq 88(%rsp), %r13 # 8-byte Reload
addl %r13d, %r15d
cmpq %rbx, %r12
je .LBB1_14
.LBB1_10: # %.preheader.i52
# =>This Loop Header: Depth=1
# Child Loop BB1_12 Depth 2
testl %r13d, %r13d
jle .LBB1_13
# %bb.11: # %.lr.ph.i57
# in Loop: Header=BB1_10 Depth=1
movl %r15d, %eax
movq 72(%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax,4), %rbp
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB1_12: # Parent Loop BB1_10 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
cltq
imulq $954437177, %rax, %rcx # imm = 0x38E38E39
movq %rcx, %rdx
shrq $63, %rdx
sarq $33, %rcx
addl %edx, %ecx
leal (%rcx,%rcx,8), %ecx
subl %ecx, %eax
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, (%rbp,%r13,4)
incq %r13
cmpq %r13, %r14
jne .LBB1_12
jmp .LBB1_13
.LBB1_14: # %_Z10FillMatrixPfii.exit62
leaq 96(%rsp), %rdi
callq hipEventCreate
leaq 24(%rsp), %rdi
callq hipEventCreate
movq 96(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movslq 8(%rsp), %rbp # 4-byte Folded Reload
leaq (,%rbp,4), %r12
movslq 16(%rsp), %r14 # 4-byte Folded Reload
movq %r14, %r15
imulq %r12, %r15
leaq 48(%rsp), %rdi
movq %r15, %rsi
callq hipMalloc
movslq %r13d, %rbx
imulq %rbx, %r14
shlq $2, %r14
leaq 40(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
imulq %r12, %rbx
leaq 32(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
movq 48(%rsp), %rdi
movq 80(%rsp), %r12 # 8-byte Reload
movq %r12, %rsi
movq %r15, %rdx
movl $1, %ecx
callq hipMemcpy
movq 40(%rsp), %rdi
movq 72(%rsp), %r15 # 8-byte Reload
movq %r15, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
movl %r13d, %eax
cltd
movq 112(%rsp), %r14 # 8-byte Reload
idivl %r14d
# kill: def $eax killed $eax def $rax
movl %ebp, %edi
shlq $32, %rax
orq %rax, %rdi
movl %r14d, %eax
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rax, %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_16
# %bb.15:
movq 48(%rsp), %rax
movq 40(%rsp), %rcx
movq 32(%rsp), %rdx
movq %rax, 184(%rsp)
movq %rcx, 176(%rsp)
movq %rdx, 168(%rsp)
movq 8(%rsp), %rax # 8-byte Reload
movl %eax, 68(%rsp)
movq 16(%rsp), %rax # 8-byte Reload
movl %eax, 64(%rsp)
movl %r13d, 60(%rsp)
movl %r14d, 56(%rsp)
leaq 184(%rsp), %rax
movq %rax, 192(%rsp)
leaq 176(%rsp), %rax
movq %rax, 200(%rsp)
leaq 168(%rsp), %rax
movq %rax, 208(%rsp)
leaq 68(%rsp), %rax
movq %rax, 216(%rsp)
leaq 64(%rsp), %rax
movq %rax, 224(%rsp)
leaq 60(%rsp), %rax
movq %rax, 232(%rsp)
leaq 56(%rsp), %rax
movq %rax, 240(%rsp)
leaq 152(%rsp), %rdi
leaq 136(%rsp), %rsi
leaq 128(%rsp), %rdx
leaq 120(%rsp), %rcx
callq __hipPopCallConfiguration
movq 152(%rsp), %rsi
movl 160(%rsp), %edx
movq 136(%rsp), %rcx
movl 144(%rsp), %r8d
leaq 192(%rsp), %r9
movl $_Z13MatrixMulCUDAPKfS0_Pfiiii, %edi
pushq 120(%rsp)
.cfi_adjust_cfa_offset 8
pushq 136(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_16:
movq 32(%rsp), %rsi
movq 104(%rsp), %rbp # 8-byte Reload
movq %rbp, %rdi
movq %rbx, %rdx
movl $2, %ecx
callq hipMemcpy
movq 48(%rsp), %rdi
callq hipFree
movq 40(%rsp), %rdi
callq hipFree
movq 32(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 24(%rsp), %rdi
callq hipEventSynchronize
movq 96(%rsp), %rsi
movq 24(%rsp), %rdx
leaq 192(%rsp), %rdi
callq hipEventElapsedTime
movl $.L.str.1, %edi
movq 8(%rsp), %rsi # 8-byte Reload
# kill: def $esi killed $esi killed $rsi
movl %r14d, %edx
xorl %eax, %eax
callq printf
movss 192(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.2, %edi
movb $1, %al
callq printf
movq %r12, %rdi
callq _ZdaPv
movq %rbp, %rdi
callq _ZdaPv
movq %r15, %rdi
callq _ZdaPv
xorl %eax, %eax
.LBB1_17:
# kill: def $eax killed $eax killed $rax
addq $248, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.globl _Z10FillMatrixPfii # -- Begin function _Z10FillMatrixPfii
.p2align 4, 0x90
.type _Z10FillMatrixPfii,@function
_Z10FillMatrixPfii: # @_Z10FillMatrixPfii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $24, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rdi, 8(%rsp) # 8-byte Spill
testl %esi, %esi
jle .LBB2_6
# %bb.1: # %.preheader.lr.ph
movl %edx, %ebx
movl %esi, %eax
movq %rax, 16(%rsp) # 8-byte Spill
movl %edx, %r12d
xorl %r13d, %r13d
xorl %ebp, %ebp
jmp .LBB2_2
.p2align 4, 0x90
.LBB2_5: # %._crit_edge
# in Loop: Header=BB2_2 Depth=1
incq %rbp
addl %ebx, %r13d
cmpq 16(%rsp), %rbp # 8-byte Folded Reload
je .LBB2_6
.LBB2_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB2_4 Depth 2
testl %ebx, %ebx
jle .LBB2_5
# %bb.3: # %.lr.ph
# in Loop: Header=BB2_2 Depth=1
movl %r13d, %eax
movq 8(%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax,4), %r14
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB2_4: # Parent Loop BB2_2 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
cltq
imulq $954437177, %rax, %rcx # imm = 0x38E38E39
movq %rcx, %rdx
shrq $63, %rdx
sarq $33, %rcx
addl %edx, %ecx
leal (%rcx,%rcx,8), %ecx
subl %ecx, %eax
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, (%r14,%r15,4)
incq %r15
cmpq %r15, %r12
jne .LBB2_4
jmp .LBB2_5
.LBB2_6: # %._crit_edge13
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z10FillMatrixPfii, .Lfunc_end2-_Z10FillMatrixPfii
.cfi_endproc
# -- End function
.globl _Z11PrintMatrixPfS_S_iii # -- Begin function _Z11PrintMatrixPfS_S_iii
.p2align 4, 0x90
.type _Z11PrintMatrixPfS_S_iii,@function
_Z11PrintMatrixPfS_S_iii: # @_Z11PrintMatrixPfS_S_iii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $40, %rsp
.cfi_def_cfa_offset 96
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %r9d, (%rsp) # 4-byte Spill
movl %r8d, %r12d
movl %ecx, %ebx
movq %rdx, 32(%rsp) # 8-byte Spill
movq %rsi, 24(%rsp) # 8-byte Spill
movq %rdi, 16(%rsp) # 8-byte Spill
movl $.Lstr.1, %edi
callq puts@PLT
movl %ebx, %eax
movq %rax, 8(%rsp) # 8-byte Spill
movl %r12d, %r14d
movl %ebx, 4(%rsp) # 4-byte Spill
testl %ebx, %ebx
jle .LBB3_6
# %bb.1: # %.preheader42.lr.ph
xorl %r15d, %r15d
xorl %r13d, %r13d
jmp .LBB3_2
.p2align 4, 0x90
.LBB3_5: # %._crit_edge
# in Loop: Header=BB3_2 Depth=1
movl $10, %edi
callq putchar@PLT
incq %r13
addl %r12d, %r15d
cmpq 8(%rsp), %r13 # 8-byte Folded Reload
je .LBB3_6
.LBB3_2: # %.preheader42
# =>This Loop Header: Depth=1
# Child Loop BB3_4 Depth 2
testl %r12d, %r12d
jle .LBB3_5
# %bb.3: # %.lr.ph
# in Loop: Header=BB3_2 Depth=1
movl %r15d, %eax
movq 16(%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax,4), %rbp
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB3_4: # Parent Loop BB3_2 Depth=1
# => This Inner Loop Header: Depth=2
movss (%rbp,%rbx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.4, %edi
movb $1, %al
callq printf
incq %rbx
cmpq %rbx, %r14
jne .LBB3_4
jmp .LBB3_5
.LBB3_6: # %._crit_edge45
movl $.Lstr.2, %edi
callq puts@PLT
movl (%rsp), %ebp # 4-byte Reload
movl %ebp, %r13d
testl %r12d, %r12d
jle .LBB3_12
# %bb.7: # %.preheader41.lr.ph
xorl %r12d, %r12d
xorl %r15d, %r15d
jmp .LBB3_8
.p2align 4, 0x90
.LBB3_11: # %._crit_edge48
# in Loop: Header=BB3_8 Depth=1
movl $10, %edi
callq putchar@PLT
incq %r15
movl (%rsp), %ebp # 4-byte Reload
addl %ebp, %r12d
cmpq %r14, %r15
je .LBB3_12
.LBB3_8: # %.preheader41
# =>This Loop Header: Depth=1
# Child Loop BB3_10 Depth 2
testl %ebp, %ebp
jle .LBB3_11
# %bb.9: # %.lr.ph47
# in Loop: Header=BB3_8 Depth=1
movl %r12d, %eax
movq 24(%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax,4), %rbp
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB3_10: # Parent Loop BB3_8 Depth=1
# => This Inner Loop Header: Depth=2
movss (%rbp,%rbx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.4, %edi
movb $1, %al
callq printf
incq %rbx
cmpq %rbx, %r13
jne .LBB3_10
jmp .LBB3_11
.LBB3_12: # %._crit_edge50
movl $.Lstr.3, %edi
callq puts@PLT
cmpl $0, 4(%rsp) # 4-byte Folded Reload
jle .LBB3_18
# %bb.13: # %.preheader.lr.ph
xorl %r14d, %r14d
xorl %r15d, %r15d
jmp .LBB3_14
.p2align 4, 0x90
.LBB3_17: # %._crit_edge53
# in Loop: Header=BB3_14 Depth=1
movl $10, %edi
callq putchar@PLT
incq %r15
addl %ebp, %r14d
cmpq 8(%rsp), %r15 # 8-byte Folded Reload
je .LBB3_18
.LBB3_14: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB3_16 Depth 2
testl %ebp, %ebp
jle .LBB3_17
# %bb.15: # %.lr.ph52
# in Loop: Header=BB3_14 Depth=1
movl %r14d, %eax
movq 32(%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax,4), %r12
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB3_16: # Parent Loop BB3_14 Depth=1
# => This Inner Loop Header: Depth=2
movss (%r12,%rbx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.4, %edi
movb $1, %al
callq printf
incq %rbx
cmpq %rbx, %r13
jne .LBB3_16
jmp .LBB3_17
.LBB3_18: # %._crit_edge55
addq $40, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size _Z11PrintMatrixPfS_S_iii, .Lfunc_end3-_Z11PrintMatrixPfS_S_iii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13MatrixMulCUDAPKfS0_Pfiiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z13MatrixMulCUDAPKfS0_Pfiiii,@object # @_Z13MatrixMulCUDAPKfS0_Pfiiii
.section .rodata,"a",@progbits
.globl _Z13MatrixMulCUDAPKfS0_Pfiiii
.p2align 3, 0x0
_Z13MatrixMulCUDAPKfS0_Pfiiii:
.quad _Z28__device_stub__MatrixMulCUDAPKfS0_Pfiiii
.size _Z13MatrixMulCUDAPKfS0_Pfiiii, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "Matrix Size is %d\nThreadBlockSize is %d\n"
.size .L.str.1, 41
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Calculation time is %.10f ms\n"
.size .L.str.2, 30
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "%f "
.size .L.str.4, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z13MatrixMulCUDAPKfS0_Pfiiii"
.size .L__unnamed_1, 30
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Wrong Input!"
.size .Lstr, 13
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "Matrix A:"
.size .Lstr.1, 10
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "Matrix B:"
.size .Lstr.2, 10
.type .Lstr.3,@object # @str.3
.Lstr.3:
.asciz "Matrix C:"
.size .Lstr.3, 10
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__MatrixMulCUDAPKfS0_Pfiiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z13MatrixMulCUDAPKfS0_Pfiiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z13MatrixMulCUDAPKfS0_Pfiiii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e280000002600 */
/*0020*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e280000002100 */
/*0030*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e620000002500 */
/*0040*/ IMAD R3, R3, c[0x0][0x184], R2 ; /* 0x0000610003037a24 */
/* 0x001fca00078e0202 */
/*0050*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x180], PT ; /* 0x0000600003007a0c */
/* 0x000fc80003f06270 */
/*0060*/ ISETP.GE.OR P0, PT, R0, c[0x0][0x178], P0 ; /* 0x00005e0000007a0c */
/* 0x002fda0000706670 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ MOV R4, c[0x0][0x17c] ; /* 0x00005f0000047a02 */
/* 0x000fe20000000f00 */
/*0090*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00a0*/ HFMA2.MMA R19, -RZ, RZ, 0, 0 ; /* 0x00000000ff137435 */
/* 0x000fe400000001ff */
/*00b0*/ ISETP.GE.AND P0, PT, R4, 0x1, PT ; /* 0x000000010400780c */
/* 0x000fda0003f06270 */
/*00c0*/ @!P0 BRA 0xc10 ; /* 0x00000b4000008947 */
/* 0x000fea0003800000 */
/*00d0*/ IADD3 R2, R4.reuse, -0x1, RZ ; /* 0xffffffff04027810 */
/* 0x040fe40007ffe0ff */
/*00e0*/ LOP3.LUT R4, R4, 0x3, RZ, 0xc0, !PT ; /* 0x0000000304047812 */
/* 0x000fe400078ec0ff */
/*00f0*/ ISETP.GE.U32.AND P0, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fe40003f06070 */
/*0100*/ MOV R19, RZ ; /* 0x000000ff00137202 */
/* 0x000fe40000000f00 */
/*0110*/ MOV R2, RZ ; /* 0x000000ff00027202 */
/* 0x000fd20000000f00 */
/*0120*/ @!P0 BRA 0xb00 ; /* 0x000009d000008947 */
/* 0x000fea0003800000 */
/*0130*/ IADD3 R6, -R4, c[0x0][0x17c], RZ ; /* 0x00005f0004067a10 */
/* 0x000fe20007ffe1ff */
/*0140*/ HFMA2.MMA R20, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff147435 */
/* 0x000fe200000001ff */
/*0150*/ IMAD R7, R0, c[0x0][0x17c], RZ ; /* 0x00005f0000077a24 */
/* 0x000fe200078e02ff */
/*0160*/ HFMA2.MMA R2, -RZ, RZ, 0, 0 ; /* 0x00000000ff027435 */
/* 0x000fe200000001ff */
/*0170*/ ISETP.GT.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe40003f04270 */
/*0180*/ MOV R19, RZ ; /* 0x000000ff00137202 */
/* 0x000fe40000000f00 */
/*0190*/ MOV R8, c[0x0][0x160] ; /* 0x0000580000087a02 */
/* 0x000fe40000000f00 */
/*01a0*/ MOV R5, c[0x0][0x164] ; /* 0x0000590000057a02 */
/* 0x000fe20000000f00 */
/*01b0*/ IMAD.WIDE R20, R3, R20, c[0x0][0x168] ; /* 0x00005a0003147625 */
/* 0x000fcc00078e0214 */
/*01c0*/ @!P0 BRA 0x960 ; /* 0x0000079000008947 */
/* 0x000fea0003800000 */
/*01d0*/ ISETP.GT.AND P1, PT, R6, 0xc, PT ; /* 0x0000000c0600780c */
/* 0x000fe40003f24270 */
/*01e0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*01f0*/ @!P1 BRA 0x6a0 ; /* 0x000004a000009947 */
/* 0x000fea0003800000 */
/*0200*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0210*/ MOV R9, R5 ; /* 0x0000000500097202 */
/* 0x000fe20000000f00 */
/*0220*/ LDG.E R18, [R20.64] ; /* 0x0000000414127981 */
/* 0x0000a8000c1e1900 */
/*0230*/ IMAD.WIDE R12, R7, 0x4, R8 ; /* 0x00000004070c7825 */
/* 0x000fe200078e0208 */
/*0240*/ MOV R9, c[0x0][0x180] ; /* 0x0000600000097a02 */
/* 0x000fc80000000f00 */
/*0250*/ LDG.E R28, [R12.64] ; /* 0x000000040c1c7981 */
/* 0x000ea2000c1e1900 */
/*0260*/ IMAD.WIDE R16, R9, 0x4, R20 ; /* 0x0000000409107825 */
/* 0x000fc600078e0214 */
/*0270*/ LDG.E R10, [R12.64+0x4] ; /* 0x000004040c0a7981 */
/* 0x000ee8000c1e1900 */
/*0280*/ LDG.E R11, [R16.64] ; /* 0x00000004100b7981 */
/* 0x0002e2000c1e1900 */
/*0290*/ IMAD.WIDE R22, R9, 0x4, R16 ; /* 0x0000000409167825 */
/* 0x000fc600078e0210 */
/*02a0*/ LDG.E R24, [R12.64+0x8] ; /* 0x000008040c187981 */
/* 0x000f28000c1e1900 */
/*02b0*/ LDG.E R25, [R22.64] ; /* 0x0000000416197981 */
/* 0x000b28000c1e1900 */
/*02c0*/ LDG.E R14, [R12.64+0xc] ; /* 0x00000c040c0e7981 */
/* 0x000f28000c1e1900 */
/*02d0*/ LDG.E R26, [R12.64+0x10] ; /* 0x000010040c1a7981 */
/* 0x000f22000c1e1900 */
/*02e0*/ IMAD.WIDE R22, R9, 0x4, R22 ; /* 0x0000000409167825 */
/* 0x020fca00078e0216 */
/*02f0*/ LDG.E R15, [R22.64] ; /* 0x00000004160f7981 */
/* 0x000b22000c1e1900 */
/*0300*/ IMAD.WIDE R20, R9, 0x4, R22 ; /* 0x0000000409147825 */
/* 0x001fca00078e0216 */
/*0310*/ LDG.E R27, [R20.64] ; /* 0x00000004141b7981 */
/* 0x000122000c1e1900 */
/*0320*/ IMAD.WIDE R16, R9, 0x4, R20 ; /* 0x0000000409107825 */
/* 0x002fc600078e0214 */
/*0330*/ LDG.E R21, [R12.64+0x1c] ; /* 0x00001c040c157981 */
/* 0x001f22000c1e1900 */
/*0340*/ FFMA R28, R18, R28, R19 ; /* 0x0000001c121c7223 */
/* 0x004fc60000000013 */
/*0350*/ LDG.E R18, [R12.64+0x14] ; /* 0x000014040c127981 */
/* 0x000ea8000c1e1900 */
/*0360*/ LDG.E R19, [R16.64] ; /* 0x0000000410137981 */
/* 0x0000a2000c1e1900 */
/*0370*/ FFMA R28, R11, R10, R28 ; /* 0x0000000a0b1c7223 */
/* 0x008fc6000000001c */
/*0380*/ LDG.E R10, [R12.64+0x18] ; /* 0x000018040c0a7981 */
/* 0x000ee2000c1e1900 */
/*0390*/ IMAD.WIDE R16, R9, 0x4, R16 ; /* 0x0000000409107825 */
/* 0x001fca00078e0210 */
/*03a0*/ LDG.E R11, [R16.64] ; /* 0x00000004100b7981 */
/* 0x0008e2000c1e1900 */
/*03b0*/ IMAD.WIDE R22, R9, 0x4, R16 ; /* 0x0000000409167825 */
/* 0x020fca00078e0210 */
/*03c0*/ LDG.E R20, [R22.64] ; /* 0x0000000416147981 */
/* 0x000162000c1e1900 */
/*03d0*/ FFMA R16, R25, R24, R28 ; /* 0x0000001819107223 */
/* 0x010fe4000000001c */
/*03e0*/ IMAD.WIDE R24, R9, 0x4, R22 ; /* 0x0000000409187825 */
/* 0x000fe200078e0216 */
/*03f0*/ LDG.E R28, [R12.64+0x20] ; /* 0x000020040c1c7981 */
/* 0x000f28000c1e1900 */
/*0400*/ LDG.E R29, [R24.64] ; /* 0x00000004181d7981 */
/* 0x000b22000c1e1900 */
/*0410*/ FFMA R16, R15, R14, R16 ; /* 0x0000000e0f107223 */
/* 0x000fe40000000010 */
/*0420*/ IMAD.WIDE R14, R9, 0x4, R24 ; /* 0x00000004090e7825 */
/* 0x000fe200078e0218 */
/*0430*/ LDG.E R23, [R12.64+0x24] ; /* 0x000024040c177981 */
/* 0x001f26000c1e1900 */
/*0440*/ FFMA R26, R27, R26, R16 ; /* 0x0000001a1b1a7223 */
/* 0x000fc40000000010 */
/*0450*/ IMAD.WIDE R16, R9, 0x4, R14 ; /* 0x0000000409107825 */
/* 0x000fe200078e020e */
/*0460*/ LDG.E R27, [R12.64+0x28] ; /* 0x000028040c1b7981 */
/* 0x000f28000c1e1900 */
/*0470*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000128000c1e1900 */
/*0480*/ LDG.E R22, [R16.64] ; /* 0x0000000410167981 */
/* 0x000328000c1e1900 */
/*0490*/ LDG.E R15, [R12.64+0x30] ; /* 0x000030040c0f7981 */
/* 0x001f22000c1e1900 */
/*04a0*/ FFMA R26, R19, R18, R26 ; /* 0x00000012131a7223 */
/* 0x004fc4000000001a */
/*04b0*/ IMAD.WIDE R18, R9, 0x4, R16 ; /* 0x0000000409127825 */
/* 0x000fc800078e0210 */
/*04c0*/ FFMA R26, R11, R10, R26 ; /* 0x0000000a0b1a7223 */
/* 0x008fe4000000001a */
/*04d0*/ IMAD.WIDE R10, R9.reuse, 0x4, R18 ; /* 0x00000004090a7825 */
/* 0x040fe400078e0212 */
/*04e0*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x0000a4000c1e1900 */
/*04f0*/ FFMA R24, R20, R21, R26 ; /* 0x0000001514187223 */
/* 0x020fe4000000001a */
/*0500*/ IMAD.WIDE R20, R9, 0x4, R10 ; /* 0x0000000409147825 */
/* 0x000fe200078e020a */
/*0510*/ LDG.E R26, [R12.64+0x2c] ; /* 0x00002c040c1a7981 */
/* 0x000ea8000c1e1900 */
/*0520*/ LDG.E R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x000762000c1e1900 */
/*0530*/ FFMA R28, R29, R28, R24 ; /* 0x0000001c1d1c7223 */
/* 0x010fc40000000018 */
/*0540*/ IMAD.WIDE R24, R9.reuse, 0x4, R20 ; /* 0x0000000409187825 */
/* 0x040fe400078e0214 */
/*0550*/ LDG.E R20, [R20.64] ; /* 0x0000000414147981 */
/* 0x000968000c1e1900 */
/*0560*/ LDG.E R11, [R12.64+0x34] ; /* 0x000034040c0b7981 */
/* 0x008ee2000c1e1900 */
/*0570*/ IMAD.WIDE R16, R9, 0x4, R24 ; /* 0x0000000409107825 */
/* 0x002fc600078e0218 */
/*0580*/ LDG.E R29, [R24.64] ; /* 0x00000004181d7981 */
/* 0x0002e8000c1e1900 */
/*0590*/ LDG.E R21, [R12.64+0x38] ; /* 0x000038040c157981 */
/* 0x010f28000c1e1900 */
/*05a0*/ LDG.E R19, [R16.64] ; /* 0x0000000410137981 */
/* 0x001f28000c1e1900 */
/*05b0*/ LDG.E R24, [R12.64+0x3c] ; /* 0x00003c040c187981 */
/* 0x002f22000c1e1900 */
/*05c0*/ FFMA R14, R14, R23, R28 ; /* 0x000000170e0e7223 */
/* 0x000fe2000000001c */
/*05d0*/ IADD3 R6, R6, -0x10, RZ ; /* 0xfffffff006067810 */
/* 0x000fc60007ffe0ff */
/*05e0*/ FFMA R27, R22, R27, R14 ; /* 0x0000001b161b7223 */
/* 0x000fe2000000000e */
/*05f0*/ ISETP.GT.AND P1, PT, R6, 0xc, PT ; /* 0x0000000c0600780c */
/* 0x000fe40003f24270 */
/*0600*/ IADD3 R8, P2, R8, 0x40, RZ ; /* 0x0000004008087810 */
/* 0x000fe40007f5e0ff */
/*0610*/ IADD3 R2, R2, 0x10, RZ ; /* 0x0000001002027810 */
/* 0x000fe40007ffe0ff */
/*0620*/ IADD3.X R5, RZ, R5, RZ, P2, !PT ; /* 0x00000005ff057210 */
/* 0x000fe200017fe4ff */
/*0630*/ FFMA R18, R18, R26, R27 ; /* 0x0000001a12127223 */
/* 0x004fc8000000001b */
/*0640*/ FFMA R10, R10, R15, R18 ; /* 0x0000000f0a0a7223 */
/* 0x020fc80000000012 */
/*0650*/ FFMA R10, R20, R11, R10 ; /* 0x0000000b140a7223 */
/* 0x008fc8000000000a */
/*0660*/ FFMA R10, R29, R21, R10 ; /* 0x000000151d0a7223 */
/* 0x010fe4000000000a */
/*0670*/ IMAD.WIDE R20, R9, 0x4, R16 ; /* 0x0000000409147825 */
/* 0x000fc800078e0210 */
/*0680*/ FFMA R19, R19, R24, R10 ; /* 0x0000001813137223 */
/* 0x000fe2000000000a */
/*0690*/ @P1 BRA 0x210 ; /* 0xfffffb7000001947 */
/* 0x000fea000383ffff */
/*06a0*/ ISETP.GT.AND P1, PT, R6, 0x4, PT ; /* 0x000000040600780c */
/* 0x000fda0003f24270 */
/*06b0*/ @!P1 BRA 0x940 ; /* 0x0000028000009947 */
/* 0x000fea0003800000 */
/*06c0*/ MOV R9, R5 ; /* 0x0000000500097202 */
/* 0x000fe20000000f00 */
/*06d0*/ LDG.E R18, [R20.64] ; /* 0x0000000414127981 */
/* 0x0000a8000c1e1900 */
/*06e0*/ IMAD.WIDE R10, R7, 0x4, R8 ; /* 0x00000004070a7825 */
/* 0x000fca00078e0208 */
/*06f0*/ LDG.E R24, [R10.64] ; /* 0x000000040a187981 */
/* 0x000ea2000c1e1900 */
/*0700*/ MOV R9, c[0x0][0x180] ; /* 0x0000600000097a02 */
/* 0x000fc60000000f00 */
/*0710*/ LDG.E R25, [R10.64+0x4] ; /* 0x000004040a197981 */
/* 0x000ee4000c1e1900 */
/*0720*/ IMAD.WIDE R22, R9.reuse, 0x4, R20 ; /* 0x0000000409167825 */
/* 0x040fe400078e0214 */
/*0730*/ LDG.E R27, [R10.64+0x8] ; /* 0x000008040a1b7981 */
/* 0x000f28000c1e1900 */
/*0740*/ IMAD.WIDE R12, R9.reuse, 0x4, R22 ; /* 0x00000004090c7825 */
/* 0x040fe200078e0216 */
/*0750*/ LDG.E R29, [R10.64+0xc] ; /* 0x00000c040a1d7981 */
/* 0x000f68000c1e1900 */
/*0760*/ LDG.E R22, [R22.64] ; /* 0x0000000416167981 */
/* 0x0002e2000c1e1900 */
/*0770*/ IMAD.WIDE R14, R9, 0x4, R12 ; /* 0x00000004090e7825 */
/* 0x000fc600078e020c */
/*0780*/ LDG.E R26, [R12.64] ; /* 0x000000040c1a7981 */
/* 0x000326000c1e1900 */
/*0790*/ IMAD.WIDE R16, R9.reuse, 0x4, R14 ; /* 0x0000000409107825 */
/* 0x040fe400078e020e */
/*07a0*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000368000c1e1900 */
/*07b0*/ IMAD.WIDE R20, R9, 0x4, R16 ; /* 0x0000000409147825 */
/* 0x001fe400078e0210 */
/*07c0*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x000168000c1e1900 */
/*07d0*/ LDG.E R15, [R10.64+0x14] ; /* 0x000014040a0f7981 */
/* 0x002f68000c1e1900 */
/*07e0*/ LDG.E R17, [R10.64+0x18] ; /* 0x000018040a117981 */
/* 0x001f62000c1e1900 */
/*07f0*/ FFMA R28, R18, R24, R19 ; /* 0x00000018121c7223 */
/* 0x004fc60000000013 */
/*0800*/ LDG.E R24, [R10.64+0x10] ; /* 0x000010040a187981 */
/* 0x000ea2000c1e1900 */
/*0810*/ IMAD.WIDE R18, R9, 0x4, R20 ; /* 0x0000000409127825 */
/* 0x000fc600078e0214 */
/*0820*/ LDG.E R20, [R20.64] ; /* 0x0000000414147981 */
/* 0x000ea6000c1e1900 */
/*0830*/ IMAD.WIDE R12, R9, 0x4, R18 ; /* 0x00000004090c7825 */
/* 0x000fe200078e0212 */
/*0840*/ LDG.E R23, [R18.64] ; /* 0x0000000412177981 */
/* 0x0000a8000c1e1900 */
/*0850*/ LDG.E R18, [R10.64+0x1c] ; /* 0x00001c040a127981 */
/* 0x001ea8000c1e1900 */
/*0860*/ LDG.E R19, [R12.64] ; /* 0x000000040c137981 */
/* 0x000ea2000c1e1900 */
/*0870*/ FFMA R22, R22, R25, R28 ; /* 0x0000001916167223 */
/* 0x008fc8000000001c */
/*0880*/ FFMA R22, R26, R27, R22 ; /* 0x0000001b1a167223 */
/* 0x010fc80000000016 */
/*0890*/ FFMA R29, R14, R29, R22 ; /* 0x0000001d0e1d7223 */
/* 0x020fe20000000016 */
/*08a0*/ IADD3 R8, P1, R8, 0x20, RZ ; /* 0x0000002008087810 */
/* 0x000fe40007f3e0ff */
/*08b0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*08c0*/ IADD3 R2, R2, 0x8, RZ ; /* 0x0000000802027810 */
/* 0x000fe40007ffe0ff */
/*08d0*/ IADD3 R6, R6, -0x8, RZ ; /* 0xfffffff806067810 */
/* 0x000fe40007ffe0ff */
/*08e0*/ IADD3.X R5, RZ, R5, RZ, P1, !PT ; /* 0x00000005ff057210 */
/* 0x000fe20000ffe4ff */
/*08f0*/ FFMA R16, R16, R24, R29 ; /* 0x0000001810107223 */
/* 0x004fc8000000001d */
/*0900*/ FFMA R16, R20, R15, R16 ; /* 0x0000000f14107223 */
/* 0x000fc80000000010 */
/*0910*/ FFMA R16, R23, R17, R16 ; /* 0x0000001117107223 */
/* 0x000fe40000000010 */
/*0920*/ IMAD.WIDE R20, R9, 0x4, R12 ; /* 0x0000000409147825 */
/* 0x000fc800078e020c */
/*0930*/ FFMA R19, R19, R18, R16 ; /* 0x0000001213137223 */
/* 0x000fe40000000010 */
/*0940*/ ISETP.NE.OR P0, PT, R6, RZ, P0 ; /* 0x000000ff0600720c */
/* 0x000fda0000705670 */
/*0950*/ @!P0 BRA 0xb00 ; /* 0x000001a000008947 */
/* 0x000fea0003800000 */
/*0960*/ MOV R9, c[0x0][0x180] ; /* 0x0000600000097a02 */
/* 0x000fe40000000f00 */
/*0970*/ MOV R10, R8 ; /* 0x00000008000a7202 */
/* 0x000fe40000000f00 */
/*0980*/ MOV R11, R5 ; /* 0x00000005000b7202 */
/* 0x000fe20000000f00 */
/*0990*/ IMAD.WIDE R12, R9, 0x4, R20 ; /* 0x00000004090c7825 */
/* 0x000fe400078e0214 */
/*09a0*/ LDG.E R20, [R20.64] ; /* 0x0000000414147981 */
/* 0x000ea4000c1e1900 */
/*09b0*/ IMAD.WIDE R10, R7, 0x4, R10 ; /* 0x00000004070a7825 */
/* 0x000fe400078e020a */
/*09c0*/ LDG.E R23, [R12.64] ; /* 0x000000040c177981 */
/* 0x000ee4000c1e1900 */
/*09d0*/ IMAD.WIDE R16, R9, 0x4, R12 ; /* 0x0000000409107825 */
/* 0x000fc400078e020c */
/*09e0*/ LDG.E R18, [R10.64] ; /* 0x000000040a127981 */
/* 0x000ea8000c1e1900 */
/*09f0*/ LDG.E R22, [R10.64+0x4] ; /* 0x000004040a167981 */
/* 0x000ee2000c1e1900 */
/*0a00*/ IMAD.WIDE R14, R9, 0x4, R16 ; /* 0x00000004090e7825 */
/* 0x000fc600078e0210 */
/*0a10*/ LDG.E R24, [R10.64+0x8] ; /* 0x000008040a187981 */
/* 0x000f28000c1e1900 */
/*0a20*/ LDG.E R25, [R16.64] ; /* 0x0000000410197981 */
/* 0x000f28000c1e1900 */
/*0a30*/ LDG.E R26, [R10.64+0xc] ; /* 0x00000c040a1a7981 */
/* 0x000f68000c1e1900 */
/*0a40*/ LDG.E R27, [R14.64] ; /* 0x000000040e1b7981 */
/* 0x000f62000c1e1900 */
/*0a50*/ IADD3 R6, R6, -0x4, RZ ; /* 0xfffffffc06067810 */
/* 0x000fc80007ffe0ff */
/*0a60*/ ISETP.NE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe40003f05270 */
/*0a70*/ IADD3 R8, P1, R8, 0x10, RZ ; /* 0x0000001008087810 */
/* 0x000fe40007f3e0ff */
/*0a80*/ IADD3 R2, R2, 0x4, RZ ; /* 0x0000000402027810 */
/* 0x000fe40007ffe0ff */
/*0a90*/ IADD3.X R5, RZ, R5, RZ, P1, !PT ; /* 0x00000005ff057210 */
/* 0x000fe20000ffe4ff */
/*0aa0*/ FFMA R18, R20, R18, R19 ; /* 0x0000001214127223 */
/* 0x004fc80000000013 */
/*0ab0*/ FFMA R18, R23, R22, R18 ; /* 0x0000001617127223 */
/* 0x008fe40000000012 */
/*0ac0*/ IMAD.WIDE R20, R9, 0x4, R14 ; /* 0x0000000409147825 */
/* 0x000fc800078e020e */
/*0ad0*/ FFMA R18, R25, R24, R18 ; /* 0x0000001819127223 */
/* 0x010fc80000000012 */
/*0ae0*/ FFMA R19, R27, R26, R18 ; /* 0x0000001a1b137223 */
/* 0x020fe20000000012 */
/*0af0*/ @P0 BRA 0x960 ; /* 0xfffffe6000000947 */
/* 0x000fea000383ffff */
/*0b00*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fda0003f05270 */
/*0b10*/ @!P0 BRA 0xc10 ; /* 0x000000f000008947 */
/* 0x000fea0003800000 */
/*0b20*/ HFMA2.MMA R9, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff097435 */
/* 0x000fe200000001ff */
/*0b30*/ IMAD R6, R0, c[0x0][0x17c], R2 ; /* 0x00005f0000067a24 */
/* 0x000fe400078e0202 */
/*0b40*/ IMAD R2, R2, c[0x0][0x180], R3 ; /* 0x0000600002027a24 */
/* 0x000fce00078e0203 */
/*0b50*/ IMAD.WIDE R6, R6, R9, c[0x0][0x160] ; /* 0x0000580006067625 */
/* 0x000fc800078e0209 */
/*0b60*/ IMAD.WIDE R8, R2, R9, c[0x0][0x168] ; /* 0x00005a0002087625 */
/* 0x000fca00078e0209 */
/*0b70*/ LDG.E R2, [R8.64] ; /* 0x0000000408027981 */
/* 0x0000a8000c1e1900 */
/*0b80*/ LDG.E R5, [R6.64] ; /* 0x0000000406057981 */
/* 0x0002a2000c1e1900 */
/*0b90*/ IADD3 R4, R4, -0x1, RZ ; /* 0xffffffff04047810 */
/* 0x000fe40007ffe0ff */
/*0ba0*/ MOV R11, c[0x0][0x180] ; /* 0x00006000000b7a02 */
/* 0x000fe40000000f00 */
/*0bb0*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fc60003f05270 */
/*0bc0*/ IMAD.WIDE R8, R11, 0x4, R8 ; /* 0x000000040b087825 */
/* 0x001fe200078e0208 */
/*0bd0*/ IADD3 R6, P1, R6, 0x4, RZ ; /* 0x0000000406067810 */
/* 0x002fc80007f3e0ff */
/*0be0*/ IADD3.X R7, RZ, R7, RZ, P1, !PT ; /* 0x00000007ff077210 */
/* 0x000fe20000ffe4ff */
/*0bf0*/ FFMA R19, R2, R5, R19 ; /* 0x0000000502137223 */
/* 0x004fc80000000013 */
/*0c00*/ @P0 BRA 0xb70 ; /* 0xffffff6000000947 */
/* 0x000fea000383ffff */
/*0c10*/ MOV R2, 0x4 ; /* 0x0000000400027802 */
/* 0x000fe20000000f00 */
/*0c20*/ IMAD R3, R0, c[0x0][0x180], R3 ; /* 0x0000600000037a24 */
/* 0x000fc800078e0203 */
/*0c30*/ IMAD.WIDE R2, R3, R2, c[0x0][0x170] ; /* 0x00005c0003027625 */
/* 0x000fca00078e0202 */
/*0c40*/ STG.E [R2.64], R19 ; /* 0x0000001302007986 */
/* 0x000fe2000c101904 */
/*0c50*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0c60*/ BRA 0xc60; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0c70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ca0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ce0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z13MatrixMulCUDAPKfS0_Pfiiii
.globl _Z13MatrixMulCUDAPKfS0_Pfiiii
.p2align 8
.type _Z13MatrixMulCUDAPKfS0_Pfiiii,@function
_Z13MatrixMulCUDAPKfS0_Pfiiii:
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x20
s_load_b32 s4, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[1:2], null, s15, s3, v[0:1]
s_cmp_lt_i32 s14, s4
s_cselect_b32 s3, -1, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_gt_i32_e32 vcc_lo, s2, v1
s_and_b32 s3, s3, vcc_lo
s_and_saveexec_b32 s4, s3
s_cbranch_execz .LBB0_6
s_load_b32 s3, s[0:1], 0x1c
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s3, 1
s_cbranch_scc1 .LBB0_4
s_load_b128 s[4:7], s[0:1], 0x0
s_mul_i32 s8, s14, s3
v_mov_b32_e32 v0, 0
s_ashr_i32 s9, s8, 31
v_mov_b32_e32 v2, v1
s_lshl_b64 s[8:9], s[8:9], 2
s_waitcnt lgkmcnt(0)
s_add_u32 s4, s4, s8
s_addc_u32 s5, s5, s9
.p2align 6
.LBB0_3:
v_ashrrev_i32_e32 v3, 31, v2
s_load_b32 s8, s[4:5], 0x0
s_add_i32 s3, s3, -1
s_add_u32 s4, s4, 4
s_addc_u32 s5, s5, 0
v_lshlrev_b64 v[3:4], 2, v[2:3]
v_add_nc_u32_e32 v2, s2, v2
s_cmp_eq_u32 s3, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v3, vcc_lo, s6, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s7, v4, vcc_lo
global_load_b32 v3, v[3:4], off
s_waitcnt vmcnt(0) lgkmcnt(0)
v_fmac_f32_e32 v0, s8, v3
s_cbranch_scc0 .LBB0_3
s_branch .LBB0_5
.LBB0_4:
v_mov_b32_e32 v0, 0
.LBB0_5:
s_load_b64 s[0:1], s[0:1], 0x10
v_mad_u64_u32 v[2:3], null, s14, s2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[1:2], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v1, vcc_lo, s0, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
global_store_b32 v[1:2], v0, off
.LBB0_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13MatrixMulCUDAPKfS0_Pfiiii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 40
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z13MatrixMulCUDAPKfS0_Pfiiii, .Lfunc_end0-_Z13MatrixMulCUDAPKfS0_Pfiiii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 36
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 40
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13MatrixMulCUDAPKfS0_Pfiiii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z13MatrixMulCUDAPKfS0_Pfiiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000a2d3f_00000000-6_MatrixMul_cuda.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z10FillMatrixPfii
.type _Z10FillMatrixPfii, @function
_Z10FillMatrixPfii:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $24, %rsp
.cfi_def_cfa_offset 80
movl %esi, 4(%rsp)
testl %esi, %esi
jle .L3
movq %rdi, %r15
movl %edx, %r14d
movl $0, %r13d
movl $0, %r12d
movslq %edx, %rax
movq %rax, 8(%rsp)
jmp .L5
.L7:
movslq %r13d, %rax
leaq (%r15,%rax,4), %rbx
movq 8(%rsp), %rsi
addq %rsi, %rax
leaq (%r15,%rax,4), %rbp
.L6:
call rand@PLT
movslq %eax, %rdx
imulq $954437177, %rdx, %rdx
sarq $33, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
leal (%rdx,%rdx,8), %edx
subl %edx, %eax
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, (%rbx)
addq $4, %rbx
cmpq %rbp, %rbx
jne .L6
.L8:
addl $1, %r12d
addl %r14d, %r13d
cmpl %r12d, 4(%rsp)
je .L3
.L5:
testl %r14d, %r14d
jg .L7
jmp .L8
.L3:
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _Z10FillMatrixPfii, .-_Z10FillMatrixPfii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Matrix A:\n"
.LC1:
.string "%f "
.LC2:
.string "\n"
.LC3:
.string "Matrix B:\n"
.LC4:
.string "Matrix C:\n"
.text
.globl _Z11PrintMatrixPfS_S_iii
.type _Z11PrintMatrixPfS_S_iii, @function
_Z11PrintMatrixPfS_S_iii:
.LFB2059:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $56, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, %r15d
movl %ecx, 40(%rsp)
movl %r8d, %ebx
movl %r8d, (%rsp)
movl %r9d, %r13d
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
testl %r15d, %r15d
jle .L12
movl $0, %r15d
movl $0, %r14d
movslq %ebx, %rcx
movq %rcx, 32(%rsp)
leaq .LC1(%rip), %r12
movl %r13d, 44(%rsp)
movl %ebx, %r13d
jmp .L13
.L16:
movslq %r15d, %rax
movq 8(%rsp), %rdx
leaq (%rdx,%rax,4), %rbx
movq 32(%rsp), %rcx
addq %rcx, %rax
leaq (%rdx,%rax,4), %rbp
.L14:
pxor %xmm0, %xmm0
cvtss2sd (%rbx), %xmm0
movq %r12, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %rbp, %rbx
jne .L14
.L17:
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %r14d
addl %r13d, %r15d
cmpl %r14d, 40(%rsp)
je .L15
.L13:
testl %r13d, %r13d
jg .L16
jmp .L17
.L15:
movl 44(%rsp), %r13d
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
cmpl $0, (%rsp)
jle .L18
.L29:
movl $0, %r15d
movl $0, %r14d
movslq %r13d, %rax
movq %rax, 8(%rsp)
leaq .LC1(%rip), %r12
jmp .L19
.L22:
movslq %r15d, %rax
movq 16(%rsp), %rcx
leaq (%rcx,%rax,4), %rbx
movq 8(%rsp), %rdx
addq %rdx, %rax
leaq (%rcx,%rax,4), %rbp
.L20:
pxor %xmm0, %xmm0
cvtss2sd (%rbx), %xmm0
movq %r12, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %rbp, %rbx
jne .L20
.L23:
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %r14d
addl %r13d, %r15d
cmpl %r14d, (%rsp)
jle .L21
.L19:
testl %r13d, %r13d
jg .L22
jmp .L23
.L21:
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
cmpl $0, 40(%rsp)
jle .L11
.L31:
movl $0, %r15d
movl $0, %r14d
movslq %r13d, %rax
movq %rax, (%rsp)
leaq .LC1(%rip), %r12
jmp .L25
.L27:
movslq %r15d, %rax
movq 24(%rsp), %rdx
leaq (%rdx,%rax,4), %rbx
movq (%rsp), %rcx
addq %rcx, %rax
leaq (%rdx,%rax,4), %rbp
.L26:
pxor %xmm0, %xmm0
cvtss2sd (%rbx), %xmm0
movq %r12, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %rbp, %rbx
jne .L26
.L28:
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %r14d
addl %r13d, %r15d
cmpl %r14d, 40(%rsp)
je .L11
.L25:
testl %r13d, %r13d
jg .L27
jmp .L28
.L12:
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
cmpl $0, (%rsp)
jg .L29
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L11:
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L18:
.cfi_restore_state
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L31
.cfi_endproc
.LFE2059:
.size _Z11PrintMatrixPfS_S_iii, .-_Z11PrintMatrixPfS_S_iii
.globl _Z43__device_stub__Z13MatrixMulCUDAPKfS0_PfiiiiPKfS0_Pfiiii
.type _Z43__device_stub__Z13MatrixMulCUDAPKfS0_PfiiiiPKfS0_Pfiiii, @function
_Z43__device_stub__Z13MatrixMulCUDAPKfS0_PfiiiiPKfS0_Pfiiii:
.LFB2084:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
leaq 192(%rsp), %rax
movq %rax, 160(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L41
.L37:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L42
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L41:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z13MatrixMulCUDAPKfS0_Pfiiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L37
.L42:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z43__device_stub__Z13MatrixMulCUDAPKfS0_PfiiiiPKfS0_Pfiiii, .-_Z43__device_stub__Z13MatrixMulCUDAPKfS0_PfiiiiPKfS0_Pfiiii
.globl _Z13MatrixMulCUDAPKfS0_Pfiiii
.type _Z13MatrixMulCUDAPKfS0_Pfiiii, @function
_Z13MatrixMulCUDAPKfS0_Pfiiii:
.LFB2085:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
call _Z43__device_stub__Z13MatrixMulCUDAPKfS0_PfiiiiPKfS0_Pfiiii
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z13MatrixMulCUDAPKfS0_Pfiiii, .-_Z13MatrixMulCUDAPKfS0_Pfiiii
.section .rodata.str1.1
.LC5:
.string "Wrong Input!\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC6:
.string "Matrix Size is %d\nThreadBlockSize is %d\n"
.section .rodata.str1.1
.LC7:
.string "Calculation time is %.10f ms\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $152, %rsp
.cfi_def_cfa_offset 208
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
cmpl $5, %edi
je .L46
leaq .LC5(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
movl $1, %eax
.L45:
movq 136(%rsp), %rdx
subq %fs:40, %rdx
jne .L63
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L46:
.cfi_restore_state
movq %rsi, %r14
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %rbp
movl %eax, 28(%rsp)
movq 16(%r14), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %r12
movq 24(%r14), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %r13
movl %eax, 36(%rsp)
movq 32(%r14), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, 40(%rsp)
movl %eax, 32(%rsp)
movl %ebp, %edi
imull %r12d, %edi
movslq %edi, %rdi
movabsq $2305843009213693950, %rax
cmpq %rdi, %rax
jb .L48
salq $2, %rdi
call _Znam@PLT
movq %rax, 8(%rsp)
movl %r12d, %edi
imull %r13d, %edi
movslq %edi, %rdi
movabsq $2305843009213693950, %rax
cmpq %rdi, %rax
jb .L64
salq $2, %rdi
call _Znam@PLT
movq %rax, 16(%rsp)
movl %ebp, %edi
imull %r13d, %edi
movslq %edi, %rdi
movabsq $2305843009213693950, %rax
cmpq %rdi, %rax
jb .L65
salq $2, %rdi
call _Znam@PLT
movq %rax, 56(%rsp)
movl %r12d, %edx
movl 28(%rsp), %esi
movq 8(%rsp), %rdi
call _Z10FillMatrixPfii
movl 36(%rsp), %edx
movl %r12d, %esi
movq 16(%rsp), %rdi
call _Z10FillMatrixPfii
leaq 96(%rsp), %rdi
call cudaEventCreate@PLT
leaq 104(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 96(%rsp), %rdi
call cudaEventRecord@PLT
movslq %ebp, %rbx
movslq %r12d, %r14
movq %rbx, %rax
imulq %r14, %rax
leaq 0(,%rax,4), %rcx
leaq 72(%rsp), %rdi
movq %rcx, 48(%rsp)
movq %rcx, %rsi
call cudaMalloc@PLT
movslq %r13d, %r15
imulq %r15, %r14
salq $2, %r14
leaq 80(%rsp), %rdi
movq %r14, %rsi
call cudaMalloc@PLT
imulq %r15, %rbx
salq $2, %rbx
leaq 88(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq 48(%rsp), %rdx
movq 8(%rsp), %rsi
movq 72(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %r14, %rdx
movq 16(%rsp), %rsi
movq 80(%rsp), %rdi
call cudaMemcpy@PLT
movl %ebp, 112(%rsp)
movl 36(%rsp), %eax
cltd
idivl 32(%rsp)
movl %eax, 116(%rsp)
movl 40(%rsp), %eax
movl %eax, 124(%rsp)
movl $1, 128(%rsp)
movl $1, 132(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 124(%rsp), %rdx
movl $1, %ecx
movq 112(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L66
.L55:
movl $2, %ecx
movq %rbx, %rdx
movq 88(%rsp), %rsi
movq 56(%rsp), %rbx
movq %rbx, %rdi
call cudaMemcpy@PLT
movq 72(%rsp), %rdi
call cudaFree@PLT
movq 80(%rsp), %rdi
call cudaFree@PLT
movq 88(%rsp), %rdi
call cudaFree@PLT
movl $0, %esi
movq 104(%rsp), %rdi
call cudaEventRecord@PLT
movq 104(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 124(%rsp), %rdi
movq 104(%rsp), %rdx
movq 96(%rsp), %rsi
call cudaEventElapsedTime@PLT
movl 32(%rsp), %ecx
movl 28(%rsp), %edx
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
pxor %xmm0, %xmm0
cvtss2sd 124(%rsp), %xmm0
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 8(%rsp), %rdi
call _ZdaPv@PLT
movq %rbx, %rdi
call _ZdaPv@PLT
movq 16(%rsp), %rdi
call _ZdaPv@PLT
movl $0, %eax
jmp .L45
.L48:
movq 136(%rsp), %rax
subq %fs:40, %rax
je .L51
call __stack_chk_fail@PLT
.L51:
call __cxa_throw_bad_array_new_length@PLT
.L64:
movq 136(%rsp), %rax
subq %fs:40, %rax
je .L54
call __stack_chk_fail@PLT
.L54:
call __cxa_throw_bad_array_new_length@PLT
.L65:
movq 136(%rsp), %rax
subq %fs:40, %rax
je .L57
call __stack_chk_fail@PLT
.L57:
call __cxa_throw_bad_array_new_length@PLT
.L66:
subq $8, %rsp
.cfi_def_cfa_offset 216
movl 48(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 224
movl %r13d, %r9d
movl %r12d, %r8d
movl 44(%rsp), %ecx
movq 104(%rsp), %rdx
movq 96(%rsp), %rsi
movq 88(%rsp), %rdi
call _Z43__device_stub__Z13MatrixMulCUDAPKfS0_PfiiiiPKfS0_Pfiiii
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L55
.L63:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC8:
.string "_Z13MatrixMulCUDAPKfS0_Pfiiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _Z13MatrixMulCUDAPKfS0_Pfiiii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "MatrixMul_cuda.hip"
.globl _Z28__device_stub__MatrixMulCUDAPKfS0_Pfiiii # -- Begin function _Z28__device_stub__MatrixMulCUDAPKfS0_Pfiiii
.p2align 4, 0x90
.type _Z28__device_stub__MatrixMulCUDAPKfS0_Pfiiii,@function
_Z28__device_stub__MatrixMulCUDAPKfS0_Pfiiii: # @_Z28__device_stub__MatrixMulCUDAPKfS0_Pfiiii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 160(%rsp), %rax
movq %rax, 144(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z13MatrixMulCUDAPKfS0_Pfiiii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z28__device_stub__MatrixMulCUDAPKfS0_Pfiiii, .Lfunc_end0-_Z28__device_stub__MatrixMulCUDAPKfS0_Pfiiii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $248, %rsp
.cfi_def_cfa_offset 304
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
cmpl $5, %edi
jne .LBB1_1
# %bb.2:
movq 8(%rsi), %rdi
xorl %ebx, %ebx
movq %rsi, %r14
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r15
movq 16(%r14), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r13
movq 24(%r14), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r12
movq 32(%r14), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, 112(%rsp) # 8-byte Spill
movl %r13d, %eax
imull %r15d, %eax
cltq
leaq (,%rax,4), %rdi
testl %eax, %eax
movq $-1, %r14
cmovsq %r14, %rdi
callq _Znam
movq %rax, 80(%rsp) # 8-byte Spill
movl %r12d, %eax
imull %r13d, %eax
cltq
leaq (,%rax,4), %rdi
testl %eax, %eax
cmovsq %r14, %rdi
callq _Znam
movq %rax, 72(%rsp) # 8-byte Spill
movq %r12, 88(%rsp) # 8-byte Spill
movl %r12d, %eax
imull %r15d, %eax
cltq
leaq (,%rax,4), %rdi
testl %eax, %eax
cmovsq %r14, %rdi
callq _Znam
movq %rax, 104(%rsp) # 8-byte Spill
movq %r15, 8(%rsp) # 8-byte Spill
testl %r15d, %r15d
movq %r13, 16(%rsp) # 8-byte Spill
jle .LBB1_8
# %bb.3: # %.preheader.lr.ph.i
movl 8(%rsp), %r14d # 4-byte Reload
movl %r13d, %r15d
xorl %r12d, %r12d
jmp .LBB1_4
.p2align 4, 0x90
.LBB1_7: # %._crit_edge.i
# in Loop: Header=BB1_4 Depth=1
incq %r12
movq 16(%rsp), %r13 # 8-byte Reload
addl %r13d, %ebx
cmpq %r14, %r12
je .LBB1_8
.LBB1_4: # %.preheader.i
# =>This Loop Header: Depth=1
# Child Loop BB1_6 Depth 2
testl %r13d, %r13d
jle .LBB1_7
# %bb.5: # %.lr.ph.i
# in Loop: Header=BB1_4 Depth=1
movl %ebx, %eax
movq 80(%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax,4), %rbp
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB1_6: # Parent Loop BB1_4 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
cltq
imulq $954437177, %rax, %rcx # imm = 0x38E38E39
movq %rcx, %rdx
shrq $63, %rdx
sarq $33, %rcx
addl %edx, %ecx
leal (%rcx,%rcx,8), %ecx
subl %ecx, %eax
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, (%rbp,%r13,4)
incq %r13
cmpq %r13, %r15
jne .LBB1_6
jmp .LBB1_7
.LBB1_1:
movl $.Lstr, %edi
callq puts@PLT
movl $1, %eax
jmp .LBB1_17
.LBB1_8: # %_Z10FillMatrixPfii.exit
testl %r13d, %r13d
movq 88(%rsp), %r13 # 8-byte Reload
jle .LBB1_14
# %bb.9: # %.preheader.lr.ph.i50
movl 16(%rsp), %ebx # 4-byte Reload
movl %r13d, %r14d
xorl %r15d, %r15d
xorl %r12d, %r12d
jmp .LBB1_10
.p2align 4, 0x90
.LBB1_13: # %._crit_edge.i54
# in Loop: Header=BB1_10 Depth=1
incq %r12
movq 88(%rsp), %r13 # 8-byte Reload
addl %r13d, %r15d
cmpq %rbx, %r12
je .LBB1_14
.LBB1_10: # %.preheader.i52
# =>This Loop Header: Depth=1
# Child Loop BB1_12 Depth 2
testl %r13d, %r13d
jle .LBB1_13
# %bb.11: # %.lr.ph.i57
# in Loop: Header=BB1_10 Depth=1
movl %r15d, %eax
movq 72(%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax,4), %rbp
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB1_12: # Parent Loop BB1_10 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
cltq
imulq $954437177, %rax, %rcx # imm = 0x38E38E39
movq %rcx, %rdx
shrq $63, %rdx
sarq $33, %rcx
addl %edx, %ecx
leal (%rcx,%rcx,8), %ecx
subl %ecx, %eax
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, (%rbp,%r13,4)
incq %r13
cmpq %r13, %r14
jne .LBB1_12
jmp .LBB1_13
.LBB1_14: # %_Z10FillMatrixPfii.exit62
leaq 96(%rsp), %rdi
callq hipEventCreate
leaq 24(%rsp), %rdi
callq hipEventCreate
movq 96(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movslq 8(%rsp), %rbp # 4-byte Folded Reload
leaq (,%rbp,4), %r12
movslq 16(%rsp), %r14 # 4-byte Folded Reload
movq %r14, %r15
imulq %r12, %r15
leaq 48(%rsp), %rdi
movq %r15, %rsi
callq hipMalloc
movslq %r13d, %rbx
imulq %rbx, %r14
shlq $2, %r14
leaq 40(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
imulq %r12, %rbx
leaq 32(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
movq 48(%rsp), %rdi
movq 80(%rsp), %r12 # 8-byte Reload
movq %r12, %rsi
movq %r15, %rdx
movl $1, %ecx
callq hipMemcpy
movq 40(%rsp), %rdi
movq 72(%rsp), %r15 # 8-byte Reload
movq %r15, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
movl %r13d, %eax
cltd
movq 112(%rsp), %r14 # 8-byte Reload
idivl %r14d
# kill: def $eax killed $eax def $rax
movl %ebp, %edi
shlq $32, %rax
orq %rax, %rdi
movl %r14d, %eax
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rax, %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_16
# %bb.15:
movq 48(%rsp), %rax
movq 40(%rsp), %rcx
movq 32(%rsp), %rdx
movq %rax, 184(%rsp)
movq %rcx, 176(%rsp)
movq %rdx, 168(%rsp)
movq 8(%rsp), %rax # 8-byte Reload
movl %eax, 68(%rsp)
movq 16(%rsp), %rax # 8-byte Reload
movl %eax, 64(%rsp)
movl %r13d, 60(%rsp)
movl %r14d, 56(%rsp)
leaq 184(%rsp), %rax
movq %rax, 192(%rsp)
leaq 176(%rsp), %rax
movq %rax, 200(%rsp)
leaq 168(%rsp), %rax
movq %rax, 208(%rsp)
leaq 68(%rsp), %rax
movq %rax, 216(%rsp)
leaq 64(%rsp), %rax
movq %rax, 224(%rsp)
leaq 60(%rsp), %rax
movq %rax, 232(%rsp)
leaq 56(%rsp), %rax
movq %rax, 240(%rsp)
leaq 152(%rsp), %rdi
leaq 136(%rsp), %rsi
leaq 128(%rsp), %rdx
leaq 120(%rsp), %rcx
callq __hipPopCallConfiguration
movq 152(%rsp), %rsi
movl 160(%rsp), %edx
movq 136(%rsp), %rcx
movl 144(%rsp), %r8d
leaq 192(%rsp), %r9
movl $_Z13MatrixMulCUDAPKfS0_Pfiiii, %edi
pushq 120(%rsp)
.cfi_adjust_cfa_offset 8
pushq 136(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_16:
movq 32(%rsp), %rsi
movq 104(%rsp), %rbp # 8-byte Reload
movq %rbp, %rdi
movq %rbx, %rdx
movl $2, %ecx
callq hipMemcpy
movq 48(%rsp), %rdi
callq hipFree
movq 40(%rsp), %rdi
callq hipFree
movq 32(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 24(%rsp), %rdi
callq hipEventSynchronize
movq 96(%rsp), %rsi
movq 24(%rsp), %rdx
leaq 192(%rsp), %rdi
callq hipEventElapsedTime
movl $.L.str.1, %edi
movq 8(%rsp), %rsi # 8-byte Reload
# kill: def $esi killed $esi killed $rsi
movl %r14d, %edx
xorl %eax, %eax
callq printf
movss 192(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.2, %edi
movb $1, %al
callq printf
movq %r12, %rdi
callq _ZdaPv
movq %rbp, %rdi
callq _ZdaPv
movq %r15, %rdi
callq _ZdaPv
xorl %eax, %eax
.LBB1_17:
# kill: def $eax killed $eax killed $rax
addq $248, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.globl _Z10FillMatrixPfii # -- Begin function _Z10FillMatrixPfii
.p2align 4, 0x90
.type _Z10FillMatrixPfii,@function
_Z10FillMatrixPfii: # @_Z10FillMatrixPfii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $24, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rdi, 8(%rsp) # 8-byte Spill
testl %esi, %esi
jle .LBB2_6
# %bb.1: # %.preheader.lr.ph
movl %edx, %ebx
movl %esi, %eax
movq %rax, 16(%rsp) # 8-byte Spill
movl %edx, %r12d
xorl %r13d, %r13d
xorl %ebp, %ebp
jmp .LBB2_2
.p2align 4, 0x90
.LBB2_5: # %._crit_edge
# in Loop: Header=BB2_2 Depth=1
incq %rbp
addl %ebx, %r13d
cmpq 16(%rsp), %rbp # 8-byte Folded Reload
je .LBB2_6
.LBB2_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB2_4 Depth 2
testl %ebx, %ebx
jle .LBB2_5
# %bb.3: # %.lr.ph
# in Loop: Header=BB2_2 Depth=1
movl %r13d, %eax
movq 8(%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax,4), %r14
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB2_4: # Parent Loop BB2_2 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
cltq
imulq $954437177, %rax, %rcx # imm = 0x38E38E39
movq %rcx, %rdx
shrq $63, %rdx
sarq $33, %rcx
addl %edx, %ecx
leal (%rcx,%rcx,8), %ecx
subl %ecx, %eax
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, (%r14,%r15,4)
incq %r15
cmpq %r15, %r12
jne .LBB2_4
jmp .LBB2_5
.LBB2_6: # %._crit_edge13
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z10FillMatrixPfii, .Lfunc_end2-_Z10FillMatrixPfii
.cfi_endproc
# -- End function
.globl _Z11PrintMatrixPfS_S_iii # -- Begin function _Z11PrintMatrixPfS_S_iii
.p2align 4, 0x90
.type _Z11PrintMatrixPfS_S_iii,@function
_Z11PrintMatrixPfS_S_iii: # @_Z11PrintMatrixPfS_S_iii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $40, %rsp
.cfi_def_cfa_offset 96
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %r9d, (%rsp) # 4-byte Spill
movl %r8d, %r12d
movl %ecx, %ebx
movq %rdx, 32(%rsp) # 8-byte Spill
movq %rsi, 24(%rsp) # 8-byte Spill
movq %rdi, 16(%rsp) # 8-byte Spill
movl $.Lstr.1, %edi
callq puts@PLT
movl %ebx, %eax
movq %rax, 8(%rsp) # 8-byte Spill
movl %r12d, %r14d
movl %ebx, 4(%rsp) # 4-byte Spill
testl %ebx, %ebx
jle .LBB3_6
# %bb.1: # %.preheader42.lr.ph
xorl %r15d, %r15d
xorl %r13d, %r13d
jmp .LBB3_2
.p2align 4, 0x90
.LBB3_5: # %._crit_edge
# in Loop: Header=BB3_2 Depth=1
movl $10, %edi
callq putchar@PLT
incq %r13
addl %r12d, %r15d
cmpq 8(%rsp), %r13 # 8-byte Folded Reload
je .LBB3_6
.LBB3_2: # %.preheader42
# =>This Loop Header: Depth=1
# Child Loop BB3_4 Depth 2
testl %r12d, %r12d
jle .LBB3_5
# %bb.3: # %.lr.ph
# in Loop: Header=BB3_2 Depth=1
movl %r15d, %eax
movq 16(%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax,4), %rbp
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB3_4: # Parent Loop BB3_2 Depth=1
# => This Inner Loop Header: Depth=2
movss (%rbp,%rbx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.4, %edi
movb $1, %al
callq printf
incq %rbx
cmpq %rbx, %r14
jne .LBB3_4
jmp .LBB3_5
.LBB3_6: # %._crit_edge45
movl $.Lstr.2, %edi
callq puts@PLT
movl (%rsp), %ebp # 4-byte Reload
movl %ebp, %r13d
testl %r12d, %r12d
jle .LBB3_12
# %bb.7: # %.preheader41.lr.ph
xorl %r12d, %r12d
xorl %r15d, %r15d
jmp .LBB3_8
.p2align 4, 0x90
.LBB3_11: # %._crit_edge48
# in Loop: Header=BB3_8 Depth=1
movl $10, %edi
callq putchar@PLT
incq %r15
movl (%rsp), %ebp # 4-byte Reload
addl %ebp, %r12d
cmpq %r14, %r15
je .LBB3_12
.LBB3_8: # %.preheader41
# =>This Loop Header: Depth=1
# Child Loop BB3_10 Depth 2
testl %ebp, %ebp
jle .LBB3_11
# %bb.9: # %.lr.ph47
# in Loop: Header=BB3_8 Depth=1
movl %r12d, %eax
movq 24(%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax,4), %rbp
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB3_10: # Parent Loop BB3_8 Depth=1
# => This Inner Loop Header: Depth=2
movss (%rbp,%rbx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.4, %edi
movb $1, %al
callq printf
incq %rbx
cmpq %rbx, %r13
jne .LBB3_10
jmp .LBB3_11
.LBB3_12: # %._crit_edge50
movl $.Lstr.3, %edi
callq puts@PLT
cmpl $0, 4(%rsp) # 4-byte Folded Reload
jle .LBB3_18
# %bb.13: # %.preheader.lr.ph
xorl %r14d, %r14d
xorl %r15d, %r15d
jmp .LBB3_14
.p2align 4, 0x90
.LBB3_17: # %._crit_edge53
# in Loop: Header=BB3_14 Depth=1
movl $10, %edi
callq putchar@PLT
incq %r15
addl %ebp, %r14d
cmpq 8(%rsp), %r15 # 8-byte Folded Reload
je .LBB3_18
.LBB3_14: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB3_16 Depth 2
testl %ebp, %ebp
jle .LBB3_17
# %bb.15: # %.lr.ph52
# in Loop: Header=BB3_14 Depth=1
movl %r14d, %eax
movq 32(%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax,4), %r12
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB3_16: # Parent Loop BB3_14 Depth=1
# => This Inner Loop Header: Depth=2
movss (%r12,%rbx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.4, %edi
movb $1, %al
callq printf
incq %rbx
cmpq %rbx, %r13
jne .LBB3_16
jmp .LBB3_17
.LBB3_18: # %._crit_edge55
addq $40, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size _Z11PrintMatrixPfS_S_iii, .Lfunc_end3-_Z11PrintMatrixPfS_S_iii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13MatrixMulCUDAPKfS0_Pfiiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z13MatrixMulCUDAPKfS0_Pfiiii,@object # @_Z13MatrixMulCUDAPKfS0_Pfiiii
.section .rodata,"a",@progbits
.globl _Z13MatrixMulCUDAPKfS0_Pfiiii
.p2align 3, 0x0
_Z13MatrixMulCUDAPKfS0_Pfiiii:
.quad _Z28__device_stub__MatrixMulCUDAPKfS0_Pfiiii
.size _Z13MatrixMulCUDAPKfS0_Pfiiii, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "Matrix Size is %d\nThreadBlockSize is %d\n"
.size .L.str.1, 41
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Calculation time is %.10f ms\n"
.size .L.str.2, 30
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "%f "
.size .L.str.4, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z13MatrixMulCUDAPKfS0_Pfiiii"
.size .L__unnamed_1, 30
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Wrong Input!"
.size .Lstr, 13
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "Matrix A:"
.size .Lstr.1, 10
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "Matrix B:"
.size .Lstr.2, 10
.type .Lstr.3,@object # @str.3
.Lstr.3:
.asciz "Matrix C:"
.size .Lstr.3, 10
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__MatrixMulCUDAPKfS0_Pfiiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z13MatrixMulCUDAPKfS0_Pfiiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__device__ float tanh_(float x)
{
// e**2x - 1
// ---------
// e**2x + 1
float exp2x = exp(2.0*x);
return (exp2x - 1.0)/(exp2x + 1.0);
}
__global__ void LSTM1(float* layer1, float* lstm1, const float* gate1i, const float* gate1o, const int offset)
{
int i = blockDim.x*blockIdx.x + threadIdx.x; //256
float g_i = gate1i[256*offset + i];
float g_f = 1.0 - g_i;
float g_o = gate1o[256*offset + i];
float i_t = tanh_(layer1[256*offset + i]) * g_i;
float i_p = 0.0;
if (offset > 0)
i_p = g_f * lstm1[256*(offset-1) + i];
float sum = i_p + i_t;
lstm1[256*offset + i] = sum;
layer1[256*offset + i] = tanh_(sum) * g_o;
} | code for sm_80
Function : _Z5LSTM1PfS_PKfS1_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ IMAD.MOV.U32 R17, RZ, RZ, 0x4 ; /* 0x00000004ff117424 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fe400078e0203 */
/*0060*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x180] ; /* 0x00006000ff037624 */
/* 0x000fc800078e00ff */
/*0070*/ IMAD R0, R3, 0x100, R0 ; /* 0x0000010003007824 */
/* 0x000fc800078e0200 */
/*0080*/ IMAD.WIDE R14, R0, R17, c[0x0][0x160] ; /* 0x00005800000e7625 */
/* 0x000fca00078e0211 */
/*0090*/ LDG.E R20, [R14.64] ; /* 0x000000040e147981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ ISETP.GE.AND P0, PT, R3, 0x1, PT ; /* 0x000000010300780c */
/* 0x000fe20003f06270 */
/*00b0*/ IMAD.WIDE R10, R0.reuse, R17.reuse, c[0x0][0x170] ; /* 0x00005c00000a7625 */
/* 0x0c0fe200078e0211 */
/*00c0*/ SHF.R.S32.HI R3, RZ, 0x1f, R0 ; /* 0x0000001fff037819 */
/* 0x000fe40000011400 */
/*00d0*/ LEA R12, P1, R0.reuse, c[0x0][0x168], 0x2 ; /* 0x00005a00000c7a11 */
/* 0x040fe200078210ff */
/*00e0*/ IMAD.WIDE R16, R0.reuse, R17, c[0x0][0x178] ; /* 0x00005e0000107625 */
/* 0x040fe200078e0211 */
/*00f0*/ LDG.E R2, [R10.64] ; /* 0x000000040a027981 */
/* 0x000164000c1e1900 */
/*0100*/ LEA.HI.X R13, R0, c[0x0][0x16c], R3, 0x2, P1 ; /* 0x00005b00000d7a11 */
/* 0x000fe200008f1403 */
/*0110*/ IMAD.MOV.U32 R6, RZ, RZ, 0x652b82fe ; /* 0x652b82feff067424 */
/* 0x000fc400078e00ff */
/*0120*/ IMAD.MOV.U32 R7, RZ, RZ, 0x3ff71547 ; /* 0x3ff71547ff077424 */
/* 0x000fe200078e00ff */
/*0130*/ BSSY B0, 0x3a0 ; /* 0x0000026000007945 */
/* 0x000fe20003800000 */
/*0140*/ @P0 LDG.E R0, [R12.64+-0x400] ; /* 0xfffc00040c000981 */
/* 0x000368000c1e1900 */
/*0150*/ LDG.E R3, [R16.64] ; /* 0x0000000410037981 */
/* 0x000762000c1e1900 */
/*0160*/ F2F.F64.F32 R4, R20 ; /* 0x0000001400047310 */
/* 0x004ea40000201800 */
/*0170*/ DADD R4, R4, R4 ; /* 0x0000000004047229 */
/* 0x004e8c0000000004 */
/*0180*/ DFMA R6, R4, R6, 6.75539944105574400000e+15 ; /* 0x433800000406742b */
/* 0x004e8c0000000006 */
/*0190*/ DADD R8, R6, -6.75539944105574400000e+15 ; /* 0xc338000006087429 */
/* 0x004e8c0000000000 */
/*01a0*/ DFMA R18, R8, c[0x2][0x0], R4 ; /* 0x0080000008127a2b */
/* 0x004e8c0000000004 */
/*01b0*/ DFMA R8, R8, c[0x2][0x8], R18 ; /* 0x0080020008087a2b */
/* 0x0044240000000012 */
/*01c0*/ IMAD.MOV.U32 R18, RZ, RZ, 0x69ce2bdf ; /* 0x69ce2bdfff127424 */
/* 0x004fe400078e00ff */
/*01d0*/ IMAD.MOV.U32 R19, RZ, RZ, 0x3e5ade15 ; /* 0x3e5ade15ff137424 */
/* 0x000fcc00078e00ff */
/*01e0*/ DFMA R10, R8, R18, c[0x2][0x10] ; /* 0x00800400080a762b */
/* 0x001e0c0000000012 */
/*01f0*/ DFMA R10, R8, R10, c[0x2][0x18] ; /* 0x00800600080a762b */
/* 0x001e0c000000000a */
/*0200*/ DFMA R10, R8, R10, c[0x2][0x20] ; /* 0x00800800080a762b */
/* 0x001e0c000000000a */
/*0210*/ DFMA R10, R8, R10, c[0x2][0x28] ; /* 0x00800a00080a762b */
/* 0x001e0c000000000a */
/*0220*/ DFMA R10, R8, R10, c[0x2][0x30] ; /* 0x00800c00080a762b */
/* 0x001e0c000000000a */
/*0230*/ DFMA R10, R8, R10, c[0x2][0x38] ; /* 0x00800e00080a762b */
/* 0x001e0c000000000a */
/*0240*/ DFMA R10, R8, R10, c[0x2][0x40] ; /* 0x00801000080a762b */
/* 0x001e0c000000000a */
/*0250*/ DFMA R10, R8, R10, c[0x2][0x48] ; /* 0x00801200080a762b */
/* 0x001e0c000000000a */
/*0260*/ DFMA R10, R8, R10, c[0x2][0x50] ; /* 0x00801400080a762b */
/* 0x001e22000000000a */
/*0270*/ FSETP.GEU.AND P1, PT, |R5|, 4.1917929649353027344, PT ; /* 0x4086232b0500780b */
/* 0x000fca0003f2e200 */
/*0280*/ DFMA R10, R8, R10, 1 ; /* 0x3ff00000080a742b */
/* 0x001e0c000000000a */
/*0290*/ DFMA R10, R8, R10, 1 ; /* 0x3ff00000080a742b */
/* 0x001ed4000000000a */
/*02a0*/ IMAD R17, R6, 0x100000, R11 ; /* 0x0010000006117824 */
/* 0x008fe400078e020b */
/*02b0*/ IMAD.MOV.U32 R16, RZ, RZ, R10 ; /* 0x000000ffff107224 */
/* 0x000fe200078e000a */
/*02c0*/ @!P1 BRA 0x390 ; /* 0x000000c000009947 */
/* 0x000fea0003800000 */
/*02d0*/ FSETP.GEU.AND P2, PT, |R5|, 4.2275390625, PT ; /* 0x408748000500780b */
/* 0x002fe20003f4e200 */
/*02e0*/ DADD R8, R4, +INF ; /* 0x7ff0000004087429 */
/* 0x000fc80000000000 */
/*02f0*/ DSETP.GEU.AND P1, PT, R4, RZ, PT ; /* 0x000000ff0400722a */
/* 0x000e0c0003f2e000 */
/*0300*/ FSEL R16, R8, RZ, P1 ; /* 0x000000ff08107208 */
/* 0x001fe40000800000 */
/*0310*/ @!P2 LEA.HI R7, R6, R6, RZ, 0x1 ; /* 0x000000060607a211 */
/* 0x000fe400078f08ff */
/*0320*/ FSEL R17, R9, RZ, P1 ; /* 0x000000ff09117208 */
/* 0x000fe40000800000 */
/*0330*/ @!P2 SHF.R.S32.HI R7, RZ, 0x1, R7 ; /* 0x00000001ff07a819 */
/* 0x000fca0000011407 */
/*0340*/ @!P2 IMAD.IADD R4, R6, 0x1, -R7 ; /* 0x000000010604a824 */
/* 0x000fe400078e0a07 */
/*0350*/ @!P2 IMAD R11, R7, 0x100000, R11 ; /* 0x00100000070ba824 */
/* 0x000fc600078e020b */
/*0360*/ @!P2 LEA R5, R4, 0x3ff00000, 0x14 ; /* 0x3ff000000405a811 */
/* 0x000fe200078ea0ff */
/*0370*/ @!P2 IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff04a224 */
/* 0x000fcc00078e00ff */
/*0380*/ @!P2 DMUL R16, R10, R4 ; /* 0x000000040a10a228 */
/* 0x00004c0000000000 */
/*0390*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x002fea0003800000 */
/*03a0*/ F2F.F32.F64 R16, R16 ; /* 0x0000001000107310 */
/* 0x000e620000301000 */
/*03b0*/ IMAD.MOV.U32 R4, RZ, RZ, 0x1 ; /* 0x00000001ff047424 */
/* 0x001fe200078e00ff */
/*03c0*/ BSSY B0, 0x580 ; /* 0x000001b000007945 */
/* 0x000fec0003800000 */
/*03d0*/ F2F.F64.F32 R8, R16 ; /* 0x0000001000087310 */
/* 0x002e240000201800 */
/*03e0*/ DADD R6, R8, 1 ; /* 0x3ff0000008067429 */
/* 0x001e080000000000 */
/*03f0*/ DADD R8, R8, -1 ; /* 0xbff0000008087429 */
/* 0x000e640000000000 */
/*0400*/ MUFU.RCP64H R5, R7 ; /* 0x0000000700057308 */
/* 0x001e300000001800 */
/*0410*/ FSETP.GEU.AND P2, PT, |R9|, 6.5827683646048100446e-37, PT ; /* 0x036000000900780b */
/* 0x002fe20003f4e200 */
/*0420*/ DFMA R10, -R6, R4, 1 ; /* 0x3ff00000060a742b */
/* 0x001e0c0000000104 */
/*0430*/ DFMA R10, R10, R10, R10 ; /* 0x0000000a0a0a722b */
/* 0x001e0c000000000a */
/*0440*/ DFMA R10, R4, R10, R4 ; /* 0x0000000a040a722b */
/* 0x001e0c0000000004 */
/*0450*/ DFMA R4, -R6, R10, 1 ; /* 0x3ff000000604742b */
/* 0x001e0c000000010a */
/*0460*/ DFMA R4, R10, R4, R10 ; /* 0x000000040a04722b */
/* 0x001e0c000000000a */
/*0470*/ DMUL R10, R8, R4 ; /* 0x00000004080a7228 */
/* 0x001e0c0000000000 */
/*0480*/ DFMA R16, -R6, R10, R8 ; /* 0x0000000a0610722b */
/* 0x001e0c0000000108 */
/*0490*/ DFMA R16, R4, R16, R10 ; /* 0x000000100410722b */
/* 0x001064000000000a */
/*04a0*/ @P0 FADD R11, -R2, 1 ; /* 0x3f800000020b0421 */
/* 0x021fe40000000100 */
/*04b0*/ IMAD.MOV.U32 R5, RZ, RZ, RZ ; /* 0x000000ffff057224 */
/* 0x000fe400078e00ff */
/*04c0*/ @P0 FMUL R5, R11, R0 ; /* 0x000000000b050220 */
/* 0x000fc80000400000 */
/*04d0*/ FFMA R4, RZ, R7, R17 ; /* 0x00000007ff047223 */
/* 0x002fca0000000011 */
/*04e0*/ FSETP.GT.AND P1, PT, |R4|, 1.469367938527859385e-39, PT ; /* 0x001000000400780b */
/* 0x000fda0003f24200 */
/*04f0*/ @P1 BRA P2, 0x570 ; /* 0x0000007000001947 */
/* 0x000fea0001000000 */
/*0500*/ IMAD.MOV.U32 R21, RZ, RZ, R9 ; /* 0x000000ffff157224 */
/* 0x000fe200078e0009 */
/*0510*/ MOV R0, 0x550 ; /* 0x0000055000007802 */
/* 0x000fe20000000f00 */
/*0520*/ IMAD.MOV.U32 R20, RZ, RZ, R8 ; /* 0x000000ffff147224 */
/* 0x000fe400078e0008 */
/*0530*/ IMAD.MOV.U32 R9, RZ, RZ, R7 ; /* 0x000000ffff097224 */
/* 0x000fe400078e0007 */
/*0540*/ CALL.REL.NOINC 0x9e0 ; /* 0x0000049000007944 */
/* 0x000fea0003c00000 */
/*0550*/ IMAD.MOV.U32 R16, RZ, RZ, R8 ; /* 0x000000ffff107224 */
/* 0x000fe200078e0008 */
/*0560*/ MOV R17, R9 ; /* 0x0000000900117202 */
/* 0x000fe40000000f00 */
/*0570*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0580*/ F2F.F32.F64 R16, R16 ; /* 0x0000001000107310 */
/* 0x000e220000301000 */
/*0590*/ IMAD.MOV.U32 R8, RZ, RZ, 0x652b82fe ; /* 0x652b82feff087424 */
/* 0x000fe200078e00ff */
/*05a0*/ BSSY B0, 0x820 ; /* 0x0000027000007945 */
/* 0x000fe20003800000 */
/*05b0*/ IMAD.MOV.U32 R9, RZ, RZ, 0x3ff71547 ; /* 0x3ff71547ff097424 */
/* 0x000fe400078e00ff */
/*05c0*/ IMAD.MOV.U32 R20, RZ, RZ, 0x69ce2bdf ; /* 0x69ce2bdfff147424 */
/* 0x000fc400078e00ff */
/*05d0*/ IMAD.MOV.U32 R21, RZ, RZ, 0x3e5ade15 ; /* 0x3e5ade15ff157424 */
/* 0x000fe400078e00ff */
/*05e0*/ FFMA R5, R2, R16, R5 ; /* 0x0000001002057223 */
/* 0x001fc80000000005 */
/*05f0*/ F2F.F64.F32 R6, R5 ; /* 0x0000000500067310 */
/* 0x000e240000201800 */
/*0600*/ DADD R6, R6, R6 ; /* 0x0000000006067229 */
/* 0x001e0c0000000006 */
/*0610*/ DFMA R8, R6, R8, 6.75539944105574400000e+15 ; /* 0x433800000608742b */
/* 0x001e080000000008 */
/*0620*/ FSETP.GEU.AND P0, PT, |R7|, 4.1917929649353027344, PT ; /* 0x4086232b0700780b */
/* 0x000fe40003f0e200 */
/*0630*/ DADD R10, R8, -6.75539944105574400000e+15 ; /* 0xc3380000080a7429 */
/* 0x001e0c0000000000 */
/*0640*/ DFMA R18, R10, c[0x2][0x0], R6 ; /* 0x008000000a127a2b */
/* 0x001e0c0000000006 */
/*0650*/ DFMA R10, R10, c[0x2][0x8], R18 ; /* 0x008002000a0a7a2b */
/* 0x001e0c0000000012 */
/*0660*/ DFMA R18, R10, R20, c[0x2][0x10] ; /* 0x008004000a12762b */
/* 0x001e0c0000000014 */
/*0670*/ DFMA R18, R10, R18, c[0x2][0x18] ; /* 0x008006000a12762b */
/* 0x001e0c0000000012 */
/*0680*/ DFMA R18, R10, R18, c[0x2][0x20] ; /* 0x008008000a12762b */
/* 0x001e0c0000000012 */
/*0690*/ DFMA R18, R10, R18, c[0x2][0x28] ; /* 0x00800a000a12762b */
/* 0x001e0c0000000012 */
/*06a0*/ DFMA R18, R10, R18, c[0x2][0x30] ; /* 0x00800c000a12762b */
/* 0x001e0c0000000012 */
/*06b0*/ DFMA R18, R10, R18, c[0x2][0x38] ; /* 0x00800e000a12762b */
/* 0x001e0c0000000012 */
/*06c0*/ DFMA R18, R10, R18, c[0x2][0x40] ; /* 0x008010000a12762b */
/* 0x001e0c0000000012 */
/*06d0*/ DFMA R18, R10, R18, c[0x2][0x48] ; /* 0x008012000a12762b */
/* 0x001e0c0000000012 */
/*06e0*/ DFMA R18, R10, R18, c[0x2][0x50] ; /* 0x008014000a12762b */
/* 0x001e0c0000000012 */
/*06f0*/ DFMA R18, R10, R18, 1 ; /* 0x3ff000000a12742b */
/* 0x001e0c0000000012 */
/*0700*/ DFMA R18, R10, R18, 1 ; /* 0x3ff000000a12742b */
/* 0x001e140000000012 */
/*0710*/ IMAD R11, R8, 0x100000, R19 ; /* 0x00100000080b7824 */
/* 0x001fe400078e0213 */
/*0720*/ IMAD.MOV.U32 R10, RZ, RZ, R18 ; /* 0x000000ffff0a7224 */
/* 0x000fe200078e0012 */
/*0730*/ @!P0 BRA 0x810 ; /* 0x000000d000008947 */
/* 0x000fea0003800000 */
/*0740*/ FSETP.GEU.AND P1, PT, |R7|, 4.2275390625, PT ; /* 0x408748000700780b */
/* 0x000fe20003f2e200 */
/*0750*/ DADD R10, R6, +INF ; /* 0x7ff00000060a7429 */
/* 0x000fc80000000000 */
/*0760*/ DSETP.GEU.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600722a */
/* 0x000e0c0003f0e000 */
/*0770*/ FSEL R10, R10, RZ, P0 ; /* 0x000000ff0a0a7208 */
/* 0x001fe40000000000 */
/*0780*/ @!P1 LEA.HI R0, R8, R8, RZ, 0x1 ; /* 0x0000000808009211 */
/* 0x000fe200078f08ff */
/*0790*/ @!P1 IMAD.MOV.U32 R6, RZ, RZ, R18 ; /* 0x000000ffff069224 */
/* 0x000fe200078e0012 */
/*07a0*/ FSEL R11, R11, RZ, P0 ; /* 0x000000ff0b0b7208 */
/* 0x000fe40000000000 */
/*07b0*/ @!P1 SHF.R.S32.HI R7, RZ, 0x1, R0 ; /* 0x00000001ff079819 */
/* 0x000fca0000011400 */
/*07c0*/ @!P1 IMAD.IADD R8, R8, 0x1, -R7 ; /* 0x0000000108089824 */
/* 0x000fe400078e0a07 */
/*07d0*/ @!P1 IMAD R7, R7, 0x100000, R19 ; /* 0x0010000007079824 */
/* 0x000fc600078e0213 */
/*07e0*/ @!P1 LEA R9, R8, 0x3ff00000, 0x14 ; /* 0x3ff0000008099811 */
/* 0x000fe200078ea0ff */
/*07f0*/ @!P1 IMAD.MOV.U32 R8, RZ, RZ, RZ ; /* 0x000000ffff089224 */
/* 0x000fcc00078e00ff */
/*0800*/ @!P1 DMUL R10, R6, R8 ; /* 0x00000008060a9228 */
/* 0x00008c0000000000 */
/*0810*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0820*/ F2F.F32.F64 R10, R10 ; /* 0x0000000a000a7310 */
/* 0x004ea20000301000 */
/*0830*/ IMAD.MOV.U32 R16, RZ, RZ, 0x1 ; /* 0x00000001ff107424 */
/* 0x000fe200078e00ff */
/*0840*/ STG.E [R12.64], R5 ; /* 0x000000050c007986 */
/* 0x0007e2000c101904 */
/*0850*/ BSSY B0, 0x9a0 ; /* 0x0000014000007945 */
/* 0x000fea0003800000 */
/*0860*/ F2F.F64.F32 R8, R10 ; /* 0x0000000a00087310 */
/* 0x005e240000201800 */
/*0870*/ DADD R6, R8, 1 ; /* 0x3ff0000008067429 */
/* 0x001e080000000000 */
/*0880*/ DADD R20, R8, -1 ; /* 0xbff0000008147429 */
/* 0x000ea40000000000 */
/*0890*/ MUFU.RCP64H R17, R7 ; /* 0x0000000700117308 */
/* 0x001e300000001800 */
/*08a0*/ FSETP.GEU.AND P1, PT, |R21|, 6.5827683646048100446e-37, PT ; /* 0x036000001500780b */
/* 0x004fe20003f2e200 */
/*08b0*/ DFMA R18, -R6, R16, 1 ; /* 0x3ff000000612742b */
/* 0x001e0c0000000110 */
/*08c0*/ DFMA R18, R18, R18, R18 ; /* 0x000000121212722b */
/* 0x001e0c0000000012 */
/*08d0*/ DFMA R18, R16, R18, R16 ; /* 0x000000121012722b */
/* 0x001e0c0000000010 */
/*08e0*/ DFMA R16, -R6, R18, 1 ; /* 0x3ff000000610742b */
/* 0x001e0c0000000112 */
/*08f0*/ DFMA R16, R18, R16, R18 ; /* 0x000000101210722b */
/* 0x001e0c0000000012 */
/*0900*/ DMUL R8, R20, R16 ; /* 0x0000001014087228 */
/* 0x001e0c0000000000 */
/*0910*/ DFMA R10, -R6, R8, R20 ; /* 0x00000008060a722b */
/* 0x001e0c0000000114 */
/*0920*/ DFMA R8, R16, R10, R8 ; /* 0x0000000a1008722b */
/* 0x001e140000000008 */
/*0930*/ FFMA R0, RZ, R7, R9 ; /* 0x00000007ff007223 */
/* 0x001fca0000000009 */
/*0940*/ FSETP.GT.AND P0, PT, |R0|, 1.469367938527859385e-39, PT ; /* 0x001000000000780b */
/* 0x000fda0003f04200 */
/*0950*/ @P0 BRA P1, 0x990 ; /* 0x0000003000000947 */
/* 0x000fea0000800000 */
/*0960*/ IMAD.MOV.U32 R9, RZ, RZ, R7 ; /* 0x000000ffff097224 */
/* 0x008fe200078e0007 */
/*0970*/ MOV R0, 0x990 ; /* 0x0000099000007802 */
/* 0x000fe40000000f00 */
/*0980*/ CALL.REL.NOINC 0x9e0 ; /* 0x0000005000007944 */
/* 0x002fea0003c00000 */
/*0990*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x008fea0003800000 */
/*09a0*/ F2F.F32.F64 R8, R8 ; /* 0x0000000800087310 */
/* 0x000e240000301000 */
/*09b0*/ FMUL R3, R3, R8 ; /* 0x0000000803037220 */
/* 0x001fca0000400000 */
/*09c0*/ STG.E [R14.64], R3 ; /* 0x000000030e007986 */
/* 0x000fe2000c101904 */
/*09d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*09e0*/ FSETP.GEU.AND P0, PT, |R9|.reuse, 1.469367938527859385e-39, PT ; /* 0x001000000900780b */
/* 0x040fe20003f0e200 */
/*09f0*/ IMAD.MOV.U32 R7, RZ, RZ, R21 ; /* 0x000000ffff077224 */
/* 0x000fe200078e0015 */
/*0a00*/ LOP3.LUT R10, R9.reuse, 0x800fffff, RZ, 0xc0, !PT ; /* 0x800fffff090a7812 */
/* 0x040fe200078ec0ff */
/*0a10*/ IMAD.MOV.U32 R8, RZ, RZ, R6 ; /* 0x000000ffff087224 */
/* 0x000fe200078e0006 */
/*0a20*/ LOP3.LUT R23, R9, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff0000009177812 */
/* 0x000fe200078ec0ff */
/*0a30*/ IMAD.MOV.U32 R24, RZ, RZ, 0x1ca00000 ; /* 0x1ca00000ff187424 */
/* 0x000fe200078e00ff */
/*0a40*/ FSETP.GEU.AND P2, PT, |R7|.reuse, 1.469367938527859385e-39, PT ; /* 0x001000000700780b */
/* 0x040fe20003f4e200 */
/*0a50*/ IMAD.MOV.U32 R26, RZ, RZ, 0x1 ; /* 0x00000001ff1a7424 */
/* 0x000fe200078e00ff */
/*0a60*/ LOP3.LUT R11, R10, 0x3ff00000, RZ, 0xfc, !PT ; /* 0x3ff000000a0b7812 */
/* 0x000fe200078efcff */
/*0a70*/ BSSY B1, 0xfb0 ; /* 0x0000053000017945 */
/* 0x000fe20003800000 */
/*0a80*/ MOV R10, R6 ; /* 0x00000006000a7202 */
/* 0x000fe20000000f00 */
/*0a90*/ IMAD.MOV.U32 R6, RZ, RZ, R20 ; /* 0x000000ffff067224 */
/* 0x000fe200078e0014 */
/*0aa0*/ LOP3.LUT R4, R7, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff0000007047812 */
/* 0x000fe200078ec0ff */
/*0ab0*/ @!P0 DMUL R10, R8, 8.98846567431157953865e+307 ; /* 0x7fe00000080a8828 */
/* 0x000e040000000000 */
/*0ac0*/ IMAD.MOV.U32 R16, RZ, RZ, R6 ; /* 0x000000ffff107224 */
/* 0x000fe200078e0006 */
/*0ad0*/ ISETP.GE.U32.AND P1, PT, R4, R23, PT ; /* 0x000000170400720c */
/* 0x000fe20003f26070 */
/*0ae0*/ IMAD.MOV.U32 R25, RZ, RZ, R4 ; /* 0x000000ffff197224 */
/* 0x000fe400078e0004 */
/*0af0*/ MUFU.RCP64H R27, R11 ; /* 0x0000000b001b7308 */
/* 0x001e220000001800 */
/*0b00*/ @!P2 LOP3.LUT R17, R9, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff000000911a812 */
/* 0x000fe200078ec0ff */
/*0b10*/ @!P2 IMAD.MOV.U32 R20, RZ, RZ, RZ ; /* 0x000000ffff14a224 */
/* 0x000fc600078e00ff */
/*0b20*/ @!P2 ISETP.GE.U32.AND P3, PT, R4, R17, PT ; /* 0x000000110400a20c */
/* 0x000fe40003f66070 */
/*0b30*/ SEL R17, R24.reuse, 0x63400000, !P1 ; /* 0x6340000018117807 */
/* 0x040fe40004800000 */
/*0b40*/ @!P2 SEL R21, R24, 0x63400000, !P3 ; /* 0x634000001815a807 */
/* 0x000fe40005800000 */
/*0b50*/ LOP3.LUT R17, R17, 0x800fffff, R7.reuse, 0xf8, !PT ; /* 0x800fffff11117812 */
/* 0x100fe400078ef807 */
/*0b60*/ @!P2 LOP3.LUT R21, R21, 0x80000000, R7, 0xf8, !PT ; /* 0x800000001515a812 */
/* 0x000fe200078ef807 */
/*0b70*/ DFMA R18, R26, -R10, 1 ; /* 0x3ff000001a12742b */
/* 0x001e06000000080a */
/*0b80*/ @!P2 LOP3.LUT R21, R21, 0x100000, RZ, 0xfc, !PT ; /* 0x001000001515a812 */
/* 0x000fc600078efcff */
/*0b90*/ DFMA R18, R18, R18, R18 ; /* 0x000000121212722b */
/* 0x001e080000000012 */
/*0ba0*/ @!P2 DFMA R16, R16, 2, -R20 ; /* 0x400000001010a82b */
/* 0x000e480000000814 */
/*0bb0*/ DFMA R18, R26, R18, R26 ; /* 0x000000121a12722b */
/* 0x0010a4000000001a */
/*0bc0*/ IMAD.MOV.U32 R26, RZ, RZ, R23 ; /* 0x000000ffff1a7224 */
/* 0x001fe200078e0017 */
/*0bd0*/ @!P0 LOP3.LUT R26, R11, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff000000b1a8812 */
/* 0x000fc600078ec0ff */
/*0be0*/ @!P2 LOP3.LUT R25, R17, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff000001119a812 */
/* 0x002fe200078ec0ff */
/*0bf0*/ DFMA R20, R18, -R10, 1 ; /* 0x3ff000001214742b */
/* 0x004e22000000080a */
/*0c00*/ IADD3 R27, R26, -0x1, RZ ; /* 0xffffffff1a1b7810 */
/* 0x000fe40007ffe0ff */
/*0c10*/ IADD3 R22, R25, -0x1, RZ ; /* 0xffffffff19167810 */
/* 0x000fc60007ffe0ff */
/*0c20*/ DFMA R18, R18, R20, R18 ; /* 0x000000141212722b */
/* 0x001e220000000012 */
/*0c30*/ ISETP.GT.U32.AND P0, PT, R22, 0x7feffffe, PT ; /* 0x7feffffe1600780c */
/* 0x000fc80003f04070 */
/*0c40*/ ISETP.GT.U32.OR P0, PT, R27, 0x7feffffe, P0 ; /* 0x7feffffe1b00780c */
/* 0x000fe20000704470 */
/*0c50*/ DMUL R20, R18, R16 ; /* 0x0000001012147228 */
/* 0x001e0c0000000000 */
/*0c60*/ DFMA R22, R20, -R10, R16 ; /* 0x8000000a1416722b */
/* 0x001e0c0000000010 */
/*0c70*/ DFMA R22, R18, R22, R20 ; /* 0x000000161216722b */
/* 0x0010620000000014 */
/*0c80*/ @P0 BRA 0xe50 ; /* 0x000001c000000947 */
/* 0x000fea0003800000 */
/*0c90*/ LOP3.LUT R7, R9, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff0000009077812 */
/* 0x000fc800078ec0ff */
/*0ca0*/ ISETP.GE.U32.AND P0, PT, R4.reuse, R7, PT ; /* 0x000000070400720c */
/* 0x040fe20003f06070 */
/*0cb0*/ IMAD.IADD R6, R4, 0x1, -R7 ; /* 0x0000000104067824 */
/* 0x000fc600078e0a07 */
/*0cc0*/ SEL R7, R24, 0x63400000, !P0 ; /* 0x6340000018077807 */
/* 0x000fe40004000000 */
/*0cd0*/ IMNMX R6, R6, -0x46a00000, !PT ; /* 0xb960000006067817 */
/* 0x000fc80007800200 */
/*0ce0*/ IMNMX R4, R6, 0x46a00000, PT ; /* 0x46a0000006047817 */
/* 0x000fe20003800200 */
/*0cf0*/ IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff067224 */
/* 0x000fc800078e00ff */
/*0d00*/ IMAD.IADD R4, R4, 0x1, -R7 ; /* 0x0000000104047824 */
/* 0x000fca00078e0a07 */
/*0d10*/ IADD3 R7, R4, 0x7fe00000, RZ ; /* 0x7fe0000004077810 */
/* 0x000fcc0007ffe0ff */
/*0d20*/ DMUL R18, R22, R6 ; /* 0x0000000616127228 */
/* 0x003e140000000000 */
/*0d30*/ FSETP.GTU.AND P0, PT, |R19|, 1.469367938527859385e-39, PT ; /* 0x001000001300780b */
/* 0x001fda0003f0c200 */
/*0d40*/ @P0 BRA 0xfa0 ; /* 0x0000025000000947 */
/* 0x000fea0003800000 */
/*0d50*/ DFMA R10, R22, -R10, R16 ; /* 0x8000000a160a722b */
/* 0x000e220000000010 */
/*0d60*/ IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff067224 */
/* 0x000fd200078e00ff */
/*0d70*/ FSETP.NEU.AND P0, PT, R11.reuse, RZ, PT ; /* 0x000000ff0b00720b */
/* 0x041fe40003f0d000 */
/*0d80*/ LOP3.LUT R17, R11, 0x80000000, R9, 0x48, !PT ; /* 0x800000000b117812 */
/* 0x000fc800078e4809 */
/*0d90*/ LOP3.LUT R7, R17, R7, RZ, 0xfc, !PT ; /* 0x0000000711077212 */
/* 0x000fce00078efcff */
/*0da0*/ @!P0 BRA 0xfa0 ; /* 0x000001f000008947 */
/* 0x000fea0003800000 */
/*0db0*/ IMAD.MOV R9, RZ, RZ, -R4 ; /* 0x000000ffff097224 */
/* 0x000fe200078e0a04 */
/*0dc0*/ MOV R8, RZ ; /* 0x000000ff00087202 */
/* 0x000fe20000000f00 */
/*0dd0*/ DMUL.RP R6, R22, R6 ; /* 0x0000000616067228 */
/* 0x000e0a0000008000 */
/*0de0*/ DFMA R8, R18, -R8, R22 ; /* 0x800000081208722b */
/* 0x000e4a0000000016 */
/*0df0*/ LOP3.LUT R17, R7, R17, RZ, 0x3c, !PT ; /* 0x0000001107117212 */
/* 0x001fe400078e3cff */
/*0e00*/ IADD3 R8, -R4, -0x43300000, RZ ; /* 0xbcd0000004087810 */
/* 0x002fc80007ffe1ff */
/*0e10*/ FSETP.NEU.AND P0, PT, |R9|, R8, PT ; /* 0x000000080900720b */
/* 0x000fc80003f0d200 */
/*0e20*/ FSEL R18, R6, R18, !P0 ; /* 0x0000001206127208 */
/* 0x000fe40004000000 */
/*0e30*/ FSEL R19, R17, R19, !P0 ; /* 0x0000001311137208 */
/* 0x000fe20004000000 */
/*0e40*/ BRA 0xfa0 ; /* 0x0000015000007947 */
/* 0x000fea0003800000 */
/*0e50*/ DSETP.NAN.AND P0, PT, R6, R6, PT ; /* 0x000000060600722a */
/* 0x000e9c0003f08000 */
/*0e60*/ @P0 BRA 0xf80 ; /* 0x0000011000000947 */
/* 0x004fea0003800000 */
/*0e70*/ DSETP.NAN.AND P0, PT, R8, R8, PT ; /* 0x000000080800722a */
/* 0x000e9c0003f08000 */
/*0e80*/ @P0 BRA 0xf50 ; /* 0x000000c000000947 */
/* 0x004fea0003800000 */
/*0e90*/ ISETP.NE.AND P0, PT, R25, R26, PT ; /* 0x0000001a1900720c */
/* 0x000fe20003f05270 */
/*0ea0*/ IMAD.MOV.U32 R18, RZ, RZ, 0x0 ; /* 0x00000000ff127424 */
/* 0x001fe400078e00ff */
/*0eb0*/ IMAD.MOV.U32 R19, RZ, RZ, -0x80000 ; /* 0xfff80000ff137424 */
/* 0x000fd400078e00ff */
/*0ec0*/ @!P0 BRA 0xfa0 ; /* 0x000000d000008947 */
/* 0x000fea0003800000 */
/*0ed0*/ ISETP.NE.AND P0, PT, R25, 0x7ff00000, PT ; /* 0x7ff000001900780c */
/* 0x000fe40003f05270 */
/*0ee0*/ LOP3.LUT R19, R7, 0x80000000, R9, 0x48, !PT ; /* 0x8000000007137812 */
/* 0x000fe400078e4809 */
/*0ef0*/ ISETP.EQ.OR P0, PT, R26, RZ, !P0 ; /* 0x000000ff1a00720c */
/* 0x000fda0004702670 */
/*0f00*/ @P0 LOP3.LUT R4, R19, 0x7ff00000, RZ, 0xfc, !PT ; /* 0x7ff0000013040812 */
/* 0x000fe200078efcff */
/*0f10*/ @!P0 IMAD.MOV.U32 R18, RZ, RZ, RZ ; /* 0x000000ffff128224 */
/* 0x000fe400078e00ff */
/*0f20*/ @P0 IMAD.MOV.U32 R18, RZ, RZ, RZ ; /* 0x000000ffff120224 */
/* 0x000fe400078e00ff */
/*0f30*/ @P0 IMAD.MOV.U32 R19, RZ, RZ, R4 ; /* 0x000000ffff130224 */
/* 0x000fe200078e0004 */
/*0f40*/ BRA 0xfa0 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*0f50*/ LOP3.LUT R19, R9, 0x80000, RZ, 0xfc, !PT ; /* 0x0008000009137812 */
/* 0x001fe200078efcff */
/*0f60*/ IMAD.MOV.U32 R18, RZ, RZ, R8 ; /* 0x000000ffff127224 */
/* 0x000fe200078e0008 */
/*0f70*/ BRA 0xfa0 ; /* 0x0000002000007947 */
/* 0x000fea0003800000 */
/*0f80*/ LOP3.LUT R19, R7, 0x80000, RZ, 0xfc, !PT ; /* 0x0008000007137812 */
/* 0x001fe200078efcff */
/*0f90*/ IMAD.MOV.U32 R18, RZ, RZ, R6 ; /* 0x000000ffff127224 */
/* 0x000fe400078e0006 */
/*0fa0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0fb0*/ IMAD.MOV.U32 R6, RZ, RZ, R0 ; /* 0x000000ffff067224 */
/* 0x000fe400078e0000 */
/*0fc0*/ IMAD.MOV.U32 R7, RZ, RZ, 0x0 ; /* 0x00000000ff077424 */
/* 0x000fc400078e00ff */
/*0fd0*/ IMAD.MOV.U32 R8, RZ, RZ, R18 ; /* 0x000000ffff087224 */
/* 0x000fe400078e0012 */
/*0fe0*/ IMAD.MOV.U32 R9, RZ, RZ, R19 ; /* 0x000000ffff097224 */
/* 0x000fe200078e0013 */
/*0ff0*/ RET.REL.NODEC R6 0x0 ; /* 0xfffff00006007950 */
/* 0x000fec0003c3ffff */
/*1000*/ BRA 0x1000; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*1010*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1020*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*10a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*10b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*10c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*10d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*10e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*10f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__device__ float tanh_(float x)
{
// e**2x - 1
// ---------
// e**2x + 1
float exp2x = exp(2.0*x);
return (exp2x - 1.0)/(exp2x + 1.0);
}
__global__ void LSTM1(float* layer1, float* lstm1, const float* gate1i, const float* gate1o, const int offset)
{
int i = blockDim.x*blockIdx.x + threadIdx.x; //256
float g_i = gate1i[256*offset + i];
float g_f = 1.0 - g_i;
float g_o = gate1o[256*offset + i];
float i_t = tanh_(layer1[256*offset + i]) * g_i;
float i_p = 0.0;
if (offset > 0)
i_p = g_f * lstm1[256*(offset-1) + i];
float sum = i_p + i_t;
lstm1[256*offset + i] = sum;
layer1[256*offset + i] = tanh_(sum) * g_o;
} | .file "tmpxft_0011da24_00000000-6_LSTM1.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z5tanh_f
.type _Z5tanh_f, @function
_Z5tanh_f:
.LFB2027:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2027:
.size _Z5tanh_f, .-_Z5tanh_f
.globl _Z33__device_stub__Z5LSTM1PfS_PKfS1_iPfS_PKfS1_i
.type _Z33__device_stub__Z5LSTM1PfS_PKfS1_iPfS_PKfS1_i, @function
_Z33__device_stub__Z5LSTM1PfS_PKfS1_iPfS_PKfS1_i:
.LFB2052:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movl %r8d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 12(%rsp), %rax
movq %rax, 144(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L9
.L5:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L10
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 184
pushq 56(%rsp)
.cfi_def_cfa_offset 192
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z5LSTM1PfS_PKfS1_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L5
.L10:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2052:
.size _Z33__device_stub__Z5LSTM1PfS_PKfS1_iPfS_PKfS1_i, .-_Z33__device_stub__Z5LSTM1PfS_PKfS1_iPfS_PKfS1_i
.globl _Z5LSTM1PfS_PKfS1_i
.type _Z5LSTM1PfS_PKfS1_i, @function
_Z5LSTM1PfS_PKfS1_i:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z5LSTM1PfS_PKfS1_iPfS_PKfS1_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _Z5LSTM1PfS_PKfS1_i, .-_Z5LSTM1PfS_PKfS1_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z5LSTM1PfS_PKfS1_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z5LSTM1PfS_PKfS1_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__device__ float tanh_(float x)
{
// e**2x - 1
// ---------
// e**2x + 1
float exp2x = exp(2.0*x);
return (exp2x - 1.0)/(exp2x + 1.0);
}
__global__ void LSTM1(float* layer1, float* lstm1, const float* gate1i, const float* gate1o, const int offset)
{
int i = blockDim.x*blockIdx.x + threadIdx.x; //256
float g_i = gate1i[256*offset + i];
float g_f = 1.0 - g_i;
float g_o = gate1o[256*offset + i];
float i_t = tanh_(layer1[256*offset + i]) * g_i;
float i_p = 0.0;
if (offset > 0)
i_p = g_f * lstm1[256*(offset-1) + i];
float sum = i_p + i_t;
lstm1[256*offset + i] = sum;
layer1[256*offset + i] = tanh_(sum) * g_o;
} | #include <hip/hip_runtime.h>
#include "includes.h"
__device__ float tanh_(float x)
{
// e**2x - 1
// ---------
// e**2x + 1
float exp2x = exp(2.0*x);
return (exp2x - 1.0)/(exp2x + 1.0);
}
__global__ void LSTM1(float* layer1, float* lstm1, const float* gate1i, const float* gate1o, const int offset)
{
int i = blockDim.x*blockIdx.x + threadIdx.x; //256
float g_i = gate1i[256*offset + i];
float g_f = 1.0 - g_i;
float g_o = gate1o[256*offset + i];
float i_t = tanh_(layer1[256*offset + i]) * g_i;
float i_p = 0.0;
if (offset > 0)
i_p = g_f * lstm1[256*(offset-1) + i];
float sum = i_p + i_t;
lstm1[256*offset + i] = sum;
layer1[256*offset + i] = tanh_(sum) * g_o;
} |
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